IEEE MTT-V053-I02 (2005-02) [53, 2 ed.]

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FEBRUARY 2005

VOLUME 53

NUMBER 2

IETMAB

(ISSN 0018-9480)

MINI-SPECIAL ISSUE ON MICROWAVES, RADAR, AND WIRELESS COMMUNICATIONS (MIKON) Guest Editorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. W. Modelski

425

MINI-SPECIAL ISSUE PAPERS

Rigorous Analysis and Investigations of the Scan Antennas on a Ferroelectric Substrate. . . . . . . . Y. Yashchyshyn and J. W. Modelski Frequency Conversion of Optical Signals in p-i-n Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. A. Malyshev, B. A. Galwas, A. L. Chizh, J. Dawidczyk, and V. F. Andrievski Retrieval of Information About Turbulence in Rain by Using Doppler-Polarimetric Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F. J. Yanovsky, H. W. J. Russchenberg, and C. M. H. Unal

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MINI-SPECIAL ISSUE ON RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) Guest Editorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T. Quach

451

MINI-SPECIAL ISSUE PAPERS

A Low-Power Highly Digitized Receiver for 2.4-GHz-Band GFSK Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H. J. Bergveld, K. M. M. van Kaam, D. M. W. Leenaerts, K. J. P. Philips, A. W. P. Vaassen, and G. Wetkzer A 0.25-m CMOS OPLL Transmitter IC for GSM and DCS Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P.-U. Su Millimeter-Wave CMOS Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell An Image-Rejection Down-Converter for Low-IF Receivers . . . . . . . . . . . . . . . S. J. Fang, A. Bellaouar, S. T. Lee, and D. J. Allstot A 0.6-V 1.6-mW Transformer-Based 2.5-GHz Downconversion Mixer With +5.4-dB Gain and 02.8-dBm IIP3 in 0.13-m CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Hermann, M. Tiebout, and H. Klar Broad-Band MMICs Based on Modified Loss-Compensation Method Using 0.35-m SiGe BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .M.-D. Tsai, C.-S. Lin, C.-H. Lien, and H. Wang Scaling and Technological Limitations of 1=f Noise and Oscillator Phase Noise in SiGe HBTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G. Niu, J. Tang, Z. Feng, A. J. Joseph, and D. L. Harame Optimization of EDGE Terminal Power Amplifiers Using Memoryless Digital Predistortion . . . N. Ceylan, J.-E. Mueller, and R. Weigel A Simple Systematic Spiral Inductor Design With Perfected Q Improvement for CMOS RFIC Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.-Y. Lee, T.-S. Chen, J. D.-S. Deng, and C.-H. Kao

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(Contents Continued on Back Cover)

(Contents Continued from Front Cover) A High Average-Efficiency SiGe HBT Power Amplifier for WCDMA Handset Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .J. Deng, P. S. Gudem, L. E. Larson, and P. M. Asbeck Image-Rejection CMOS Low-Noise Amplifier Design Optimization Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T.-K. Nguyen, N.-J. Oh, C.-Y. Cha, Y.-H. Oh, G.-J. Ihm, and S.-G. Lee An Efficient Nonlinear Circuit Simulation Technique . . . . . . . . . . . . . . . . . . . . . . . . E. Dautbegovic´, M. Condon, and C. Brennan Design of Multistandard Adaptive Voltage-Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . A. Tasic´, W. A. Serdijn, and J. R. Long An Experimental Study of Carrier Heating on Channel Noise in Deep-Submicrometer NMOSFETs Via Body Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H. Wang, R. Zeng, and X. Li Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers . . . . . . . . . . . . . .V. Aparin and L. E. Larson Decreasing-Size Distributed ESD Protection Scheme for Broad-Band RF Circuits. . . . . . . . . . . . . . . . . . . M.-D. Ker and B.-J. Kuo Jitter Considerations in the Design of a 10-Gb/s Automatic Gain Control Amplifier. . . . . . . . . . . . D. Kucharski and K. T. Kornegay G-Band (140–220 GHz) and W -Band (75–110 GHz) InP DHBT Medium Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V. K. Paidi, Z. Griffith, Y. Wei, M. Dahlstrom, M. Urteaga, N. Parthasarathy, M. Seo, L. Samoska, A. Fung, and M. J. W. Rodwell A GSM/EGSM/DCS/PCS Direct Conversion Receiver With Integrated Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y.-J. Kim, Y.-S. Son, V. N. Parkhomenko, I.-C. Hwang, J.-K. Cho, K.-S. Nah, and B.-H. Park A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach . . . . . . .H. Hashemi, X. Guan, A. Komijani, and A. Hajimiri

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CONTRIBUTED PAPERS

Dielectric Constant, Loss Tangent, and Surface Resistance of PCB Materials at K -Band Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V. N. Egorov, V. L. Masalov, Y. A. Nefyodov, A. F. Shevchun, M. R. Trunin, V. E. Zhitomirsky, and M. McLean Novel T-Rail Electrodes for Substrate Removed Low-Voltage High-Speed GaAs/AlGaAs Electrooptic Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .J. Shin, C. Ozturk, S. R. Sakamoto, Y. J. Chiu, and N. Dagli New Approaches for Designing Microstrip Filters Utilizing Mixed Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E. Semouchkina, A. Baker, G. B. Semouchkin, M. Lanagan, and R. Mittra A Compact 2-D FDFD Method for Modeling Microstrip Structures With Nonuniform Grids and Perfectly Matched Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J.-N. Hwang Spectrum Emission Considerations for Baseband-Modeled CALLUM Architectures . . . R. Strandberg, P. Andreani, and L. Sundström An Efficient Method for Determining TE and TM Modes in Closed Waveguides Made up of N Cylindrical Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V. de la Rubia and J. Zapata An Active Differential Broad-Band Phase Splitter for Quadrature-Modulator Applications . . . . . . . E. Tiiliharju and K. A. I. Halonen Design of an RF Low-Noise Bandpass Filter Using Active Capacitance Circuit. . . . . Y.-H. Chun, J.-R. Lee, S.-W. Yun, and J.-K. Rhee EO Probe for Simultaneous Electric and Magnetic Near-Field Measurements Using LiNbO3 With Inverted Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E. Suzuki, S. Arakawa, H. Ota, K. I. Arai, R. Sato, and K. Nakamura Extremely High-Q Factor Dielectric Resonators for Millimeter-Wave Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. Krupka, M. E. Tobar, J. G. Hartnett, D. Cros, and J.-M. Le Floch Excitation of Coupled Slotline Mode in Finite-Ground CPW With Unequal Ground-Plane Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .G. E. Ponchak, J. Papapolymerou, and M. M. Tentzeris Estimation of Complex Permittivity of Arbitrary Shape and Size Dielectric Samples Using Cavity Measurement Technique at Microwave Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Santra and K. U. Limaye Comparison of the “Pad-Open-Short” and “Open-Short-Load” Deembedding Techniques for Accurate On-Wafer RF Characterization of High-Quality Passives. . . . . . . . . . . . . . . . . . . . . . . . . . . .L. F. Tiemeijer, R. J. Havens, A. B. M. Jansman, and Y. Bouttement Analysis and Characterization of PLL-Based Retrodirective Array . . . . . . . . . . . . . . . . . . . . V. Fusco, C. B. Soo, and N. Buchanan Power Level-Dependent Dual-Operating Mode LDMOS Power Amplifier for CDMA Wireless Base-Station Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y. Chung, J. Jeong, Y. Wang, D. Ahn, and T. Itoh Miniaturized Spurious Passband Suppression Microstrip Filter Using Meandered Parallel Coupled Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S.-M. Wang, C.-H. Chi, M.-Y. Hsieh, and C.-Y. Chang High-Power High-Efficiency SiGe Ku- and Ka-Band Balanced Frequency Doublers . . ..J.-J. Hung, T. M. Hancock, and G. M. Rebeiz Influence of Epitaxial Structure in the Noise Figure of AlGaN/GaN HEMTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Sanabria, H. Xu, T. Palacios, A. Chakraborty, S. Heikman, U. K. Mishra, and R. A. York Deembedding the Effect of a Local Ground Plane in Electromagnetic Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. C. Rautio Wide Tuning-Range Planar Filters Using Lumped-Distributed Coupled Resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B. E. Carey-Smith, P. A. Warr, M. A. Beach, and T. Nesimoglu An Adaptive Predistortion RF Power Amplifier With a Spectrum Monitor for Multicarrier WCDMA Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S.-Y. Lee, Y.-S. Lee, S.-H. Hong, H.-S. Choi, and Y.-H. Jeong Information for Authors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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IEEE MICROWAVE THEORY AND TECHNIQUES SOCIETY The Microwave Theory and Techniques Society is an organization, within the framework of the IEEE, of members with principal professional interests in the field of microwave theory and techniques. All members of the IEEE are eligible for membership in the Society and will receive this TRANSACTIONS upon payment of the annual Society membership fee of $14.00 plus an annual subscription fee of $24.00. For information on joining, write to the IEEE at the address below. Member copies of Transactions/Journals are for personal use only.

ADMINISTRATIVE COMMITTEE K. C. GUPTA, President M. P. DE LISO S. M. EL-GHAZALY M. HARRIS T. ITOH

K. VARIAN, Vice President D. HARVEY J. HAUSNER L. KATEHI

A. MORTAZAWI, Secretary T. LEE D. LOVELACE J. MODELSKI

S. KAWASAKI J. S. KENNEY N. KOLIAS

Honorary Life Members A. A. OLINER K. TOMIYASU T. S. SAAD L. YOUNG

L. E. DAVIS W. GWAREK W. HEINRICH W. HOEFER

M. HARRIS, Treasurer

V. J. NAIR B. PERLMAN D. RUTLEDGE Distinguished Lecturers T. ITOH B. KIM J. LASKAR J. C. RAUTIO

K. VARIAN R. WIEGEL S. WETENKAMP

W. SHIROMA R. SNYDER R. SORRENTINO D. RYTTING M. SHUR P. SIEGEL R. J. TREW

Past Presidents R. J. TREW (2004) F. SCHINDLER (2003) J. T. BARR IV (2002)

MTT-S Chapter Chairs Albuquerque: G. WOOD Atlanta: J. PAPAPOLYMEROU Austria: R. WEIGEL Baltimore: B. MCCARTHY Beijing: Y.-R. ZHONG Beijing, Nanjing: W.-X. ZHANG Belarus: A. GUSINSKY Benelux: D. V.-JANVIER Buenaventura: L. HAYS Buffalo: M. R. GILLETTE Bulgaria: F. FILIPOV Cedar Rapids/Central Iowa: D. JOHNSON Central New England/Boston: F. SULLIVAN Central & South Italy: R. TIBERIO Central No. Carolina: T. IVANOV Chicago: R. KOLLMAN Cleveland: G. PONCHAK Columbus: J.-F. LEE Croatia: J. BARTOLIC Czech/Slovakia: P. HAZDRA Dallas: P. WINSON Dayton: A. TERZOULI, JR. Denver: K. BOIS East Ukraine: A. KIRILENKO Eastern No. Carolina: D. PALMER Egypt: I. A. SALEM Finland: T. KARTTAAVI Florida West Coast: S. O’BRIEN

Foothill: C. ANTONIAK France: O. PICON Germany: W. HEINRICH Greece: I. XANTHAKIS Hong Kong: W. Y. TAM Houston: J. T. WILLIAMS Houston, College Station: K. MICHALSKI Hungary: T. BERCELI Huntsville: M. A. BARNES India/Calcutta: P. K. SAHA India Council: K. S. CHARI Israel: S. AUSTER Japan Council: H. JUI-PANG Kitchener-Waterloo: R. R. MANSOUR Long Island/New York: M. HANCZOR Los Angeles Council: T. LEE Malaysia: Z. AWANG Melbourne: R. BOTSFORD Milwaukee: S. G. JOSHI Mohawk Valley: P. RATAZZI Montreal: K. WU New Hampshire: T. PERKINS New Jersey Coast: G. N. S. PRASANNA New South Wales: G. TOWN North Italy: G. GHIONE North Jersey: K. DIXIT North Queensland: A. TSAKISSIRIS Northern Nevada: B. S. RAWAT Norway: M. OLAVSBRATEN Orange County: H. J. DE LOS SANTOS Oregon: T. RUTTAN Orlando: T. WU

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Associate Editors Editor-In-Chief BUMMAN KIM KENJI ITOH ZOYA POPOVIC MICHAEL STEER STEVEN MARSH WOLFGANG MENZEL North Carolina State Univ. Univ. of Ulm Pohang Univ. Sci. Technol. Univ. of Colorado at Boulder Mitsubishi Electric Corp. Midas Consulting Raleigh, NC Germany Korea USA Japan U.K. 27695-7911 USA email: [email protected] email: [email protected] email: [email protected] email: [email protected] email: [email protected] Phone: +1 919 515 5191 ANDREAS CANGELLARIS AMIR MORTAZAWI DYLAN F. WILLIAMS Fax: +1 919 513 1979 Univ. of Illinois, Urbana Champaign Univ. of Michigan at Ann Arbor NIST email: USA USA USA VITTORIO RIZZOLI [email protected] email: [email protected] email: [email protected] email: [email protected] ALESSANDRO CIDRONALI Univ. of Bologna YOSHIO NIKAWA PETER RUSSER ANTTI RÄISÄNEN Italy Univ. of Florence Helsinki Univ. of Technol. Technische Univ. Muenchen Kokushikan Univ. email: [email protected] Italy Finland Germany Japan email: [email protected] email: [email protected] email: [email protected] email: [email protected] R. VAHLDIECK, Editor, IEEE Microwave and Wireless Component Letters T. LEE, Web Master M. GUPTA, Editor, IEEE Microwave Magazine

IEEE Offficers W. CLEON ANDERSON, President MICHAEL R. LIGHTNER, President-Elect MOHAMED EL-HAWARY, Secretary JOSEPH V. LILLIE, Treasurer ARTHUR W. WINSTON, Past President MOSHE KAM, Vice President, Educational Activities

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Digital Object Identifier 10.1109/TMTT.2005.844586

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

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Guest Editorial

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HIS TRANSACTIONS’ Mini-Special Issue includes three papers from the 15th International Conference on Microwaves, Radar, and Wireless Communications (MIKON’04). MIKON’04 was held 17–19 May 2004, Warsaw, Poland, where 234 papers from 32 countries were presented. It is worth pointing out that the success of last year’s conference should be perceived in the light of MIKON’s 35-year-long history. It began in 1969 as a microwave solid-state technology conference (MECS) and, in 1983, it was transformed into and renamed as a microwave conference. Over the years, MIKON has been continuously modified and expanded. The first nine conferences were national assemblies of the Polish microwave community, organized every two or three years with only a limited number of invited foreign guests. In the early 1990s, the decision was made to transform our national microwave conference MIKON into an international event focused on Central and Eastern Europe and organized biannually. This decision followed from the initiative and encouragement by the Polish IEEE Microwave Theory and Techniques (MTT)/Antennas and Propagation (AP)/Aerospace and Electronic Systems (AES) Joint Chapter, yet required a lot of courage and willingness to face new challenges. MIKON took place in its new format for the first time in 1994. Since then, it has been held on a regular basis under the auspices of two parent institutions: the Polish Academy of Sciences, being the original one, and the new one—the IEEE. It has also enjoyed careful supervision and devoted efforts by the long-term organizer: the Telecommunications Research Institute (PIT). PIT celebrated its 70th anniversary in 2004 and is the leading research center in radar technology in Poland with the biggest grouping of microwave and radar specialists in Poland. Due to the fact that telecommunications and radar technology are the principal driving forces behind microwave research, the scope of MIKON was extended once again in 1998 and since then has been held as an international conference on microwaves, radar, and wireless communications. Out of the 234 papers presented at MIKON’04, 105 came from Poland and, what was highly appreciated, 129 from abroad. These figures are certainly indicative of the enhanced international dimension of MIKON. The majority of foreign papers were submitted from neighboring countries—Russia, Ukraine, Germany, Sweden and Lithuania, but also many came from other European countries, particularly France, Italy, and The Netherlands. From overseas, the largest number of papers came from Australia and the U.S. The MIKON’04 program comprised 36 sessions covering a wide range of topics: antenna design, modeling, and measurement; active and passive devices and components; microwave and optical integrated circuits; millimeter and sub-millimeter technology;

photonics, microwave–light-wave interaction; RF, VHF, and UHF technology; computer-aided design (CAD) techniques, modeling, and simulation; microwave measurements, industrial, environmental, and medical applications; microwave and optical communication systems; wireless and personal communications; radar technology; radar polarimetry and signatures; sensors, detectors, and vehicular radars, as well as electromagnetic compatibility. The majority of MIKON’04 papers follows the directions established by other leading conferences, therefore, the keywords common for today’s microwave research include: compact, planar, small, and low cost. It can be observed, however, that the trend toward a higher level of integration is mostly motivated by wireless communications and, though to a lesser degree, by radar. Growing interest was placed in antennas and associated analysis and design tools and techniques. MIKON’04 constituted the kernel of the Microwave and Radar Week 2004 in Poland (17–21 May), which was comprised of, besides MIKON, the following events: the 5th International Radar Symposium, the 17th International Conference on Electromagnetic Fields and Materials and the East–West Workshop on Advanced Techniques in Electromagnetics. A total number of 506 participants from 40 countries attended the whole week, of which 374 papers were presented. The Polish microwave and radar community felt privileged to have many distinguished guests among the conference participants. We took the chance of listening to welcome addresses given by Prof. Michal Kleiber, Minister of Scientific Research and Information Technology and the IEEE Microwave Theory and Techniques Society (IEEE MTT–S) 2004 President, Prof. Robert Trew. Furthermore, six distinguished members of the MIKON community were presented with special certificates of appreciation in recognition of their outstanding contributions to the technical program of the conferences over the years, as well as the promotion of MIKON among the world’s microwave and radar community. Last year’s conference hosted a strong representation of young authors. MIKON’04 continued the Young Scientist Contest addressed to young engineers and Ph.D. students. In whole, 83 papers of young authors were submitted for the competition. The five prizes were founded by the European Microwave Association, the IEEE MTT/AP/AES Joint Chapter of Poland Section, and the Polish Academy of Sciences. We are very pleased to observe that MIKON’04 was a very successful event and that the conference has already gained the status of a significant and well-known event in Central Europe.

Digital Object Identifier 10.1109/TMTT.2004.841415

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JÓZEF W. MODELSKI, Guest Editor Warsaw University of Technology Institute of Radioelectronics Warsaw, 00-665 Poland

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Józef W. Modelski (SM’90–F’01) was born in Kawnice, Poland, in 1949. He received the M.Sc., Ph.D., and D.Sc. (habilitation) degrees in electronics from the Warsaw University of Technology (WUT), Warsaw, Poland, in 1973, 1978 and 1987, respectively. In 1994, he became a Professor. Since 1973, he has been with the Institute of Radioelectronics, WUT, where he has been a Teaching/Research Assistant through a Tenured Professor (1991). From 1976 to 1977, he was a Fulbright grantee with the University of Texas at Austin, Cornell University, and the COMSAT Laboratories. In 1985, he visited Germany as a Deutcher Akademischer Austauschdienst (DAAD) grantee. From 1986 to 1988, he was a Senior Scientist with the Braunschweig Technical University, Braunschweig, Germany. Since 1996, he has been Director of the Institute of Radioelectronics, Warsaw University of Technology. He has authored or coauthored over 200 technical papers and four monographs. He holds nine patents. His research interests include microwave modulators and shifters with semiconductor and ferrite elements, dielectric resonators and their applications, integrating waveguide technology, methods, and equipment of material properties measurements, and recently, ferroelectric and smart antennas for communication systems. He acts as consultant to industry and Polish Government agencies. Dr. Modelski is an associate member of the National Academy of Sciences of Ukraine and a few committees of the Polish Academy of Sciences. Since 1996, he has been chair of the International Conference on Microwaves, Radar and Wireless Communications (MIKON), a member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) Technical Program Committees (TPCs) and the European Microwave Conference. He has been a member of the TPC and Steering Committees of numerous local conferences in Europe. Since 2000, he has been an IEEE MTT-S Administrative Committee member. From 2000 to 2001, he was chair of the Transactional Committee. From 2002 to 2003, he was chair of the Membership Services Committee. He is currently vice-chairman of the Technical Coordinating Committee. Since 2002, he has also served as IEEE Region 8 chair of the Chapter Coordination Committee.

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Rigorous Analysis and Investigations of the Scan Antennas on a Ferroelectric Substrate Yevhen Yashchyshyn, Member, IEEE, and Józef W. Modelski, Fellow, IEEE

Abstract—In this paper, the radiation characteristics of a new microstrip electrically controllable scan antenna are investigated theoretically and experimentally. Both longitudinal and transverse currents are taken into account. The substrate of this antenna consists of a ceramic–polymer composite with modified ferroelectric powder Ba0 65 Sr0 35 TiO3 and an appropriate polymer. The permittivity of the substrate can be varied by an applied electric control dc-bias field. It allows to change electrically phase constant of the propagation wave and, in turn, changes the main beam direction. It is shown that the main beam position changes over 30 when dc-bias field is applied up to 200 V. The comparison with experimental results has fully confirmed the usefulness of the scan-antenna concept and method of analysis. Presented results of the electrical scanned antenna investigation are promising for various fixed-frequency applications where frequency scanning is impossible. Index Terms—Antenna theory, antennas, ferroelectric materials, integral equations, leaky-wave antennas, moment methods.

I. INTRODUCTION

D

ESPITE THE enormous effort made to reduce the cost of scanning phased-array antennas, the desired progress has yet to be achieved. However, as recently demonstrated, a number of array configurations (without phase shifters) are a promising solution to inexpensive beam steering. There are four main configurations of beam steering, which are: 1) electronically scanned antennas; 2) optically controlled antennas; 3) ferrite-type dielectric antennas; and 4) antennas with ferroelectric dielectric. The first ones are utilized most frequently. A frequency scannable leaky-wave antenna integrated with a voltage-controlled oscillator, effectively achieving an electronically controlled beam, has been reported in [1]. However, for numerous applications, fixed-frequency operation would be preferable. In [2], the authors achieved electronic scanning by using p-i-n diodes to modulate the effective waveguide size. They have demonstrated fixed-frequency electronic beam steering and have reported a 10 change in beam angle as the diode bias was varied. A similar fixed-frequency beam-switching solution has been reported in [3]. The authors have used a different approach. They electronically vary the perturbation spacing. A rectangular dielectric rod was loaded with a grating of metal-strip perturbations, which had been loaded with p-i-n Manuscript received April 18, 2004; revised July 10, 2004. This work was supported in part by the Polish State Committee for Scientific Research under Contract 4T11B 073 22. The authors are with the Institute of Radioelectronics, Warsaw University of Technology, 00-665 Warsaw, Poland (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840779

diodes. The p-i-n diodes act as switches, controlling the effective grating spacing. The second configuration of beam steering is based on an optically controlled beam-steering antenna. In most of them, the signal (e.g., millimeter wave) propagates along a semiconductor waveguide or in a compound dielectric waveguide containing a photosensitive layer [4]. By a specially patterned illumination, a photoinduced plasma grating is excited on the surface of the waveguide. As in a leaky-wave antenna loaded with a metal grating, in an optically controlled antenna, the millimeter-wave signal propagating along the semiconductor waveguide interacts with the plasma grating and couples out in a specific direction that depends on the grating period. The main disadvantage of this design is that the photoinduced plasma grating also significantly attenuates the beam and prevents the millimeter-wave signal from effectively propagating along the waveguide. As a result, it becomes difficult to produce a radiating aperture of a reasonable size. In [5], the authors have presented a new photonically controlled antenna architecture free of the above-mentioned shortcoming. A ferrite-type dielectric waveguide antenna for phase scanning in the millimeter-wave region has been presented in [6]. Another solution has been described in [7]. In the second case, the scanning sector was 20 , a sidelobe level was approximately 12 dB, the range of control current was approximately 0.7 A, and power consumption was approximately 1 W. The major feature of antennas that use ferroelectric dielectric materials is the change of permittivity with an applied dc-bias voltage. The property of ferroelectric materials having a dielectric constant that can be modulated at high frequencies, under the effect of an electric-field bias operating perpendicular to the direction of propagation of the signal, is very attractive and can be used to develop a new family of devices operating in the microwave and millimeter-wave range. Ferroelectric materials are in many ways dual to ferromagnetic materials. However, they have a number of advantages over magnetically controlled ferrites. In ferroelectric, the driven energy required to change the property of the material goes primarily to the change in the stored electrostatic energy and is not dissipated in the ferroelectric material. As a consequence, less power is required to control the property of the material. Ferroelectrics also allow faster phase shifting compared to ferromagnetic materials, they have a smaller and lighter structure, and allow high power capability. Phased-array approaches using ferroelectric have been presented in [8]. Two possible configurations, i.e., one a traveling-wave type and another a lens-type antenna, have been discussed. However, there is one main disadvantage: very high dc bias (maximum is approximately 13.5 kV).

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Fig. 1.

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Basic geometry of the radiation structure and the scan principle.

The main reason why ferroelectric materials have not been used at microwave range is the large bias voltage required to change their dielectric constant and high losses of the materials. A new low-cost scan-antenna concept (without phase shifters) has been presented in [9]. The substrate of this microstrip antenna has been made using a ceramic–polymer composite with modified ferroelectric powder Ba Sr TiO and an appropriate polymer (grains of the powder were sprayed into polymer with the use of a specific method). The ceramic–polymer composite was designed to change permittivity in response to an applied electric control field for antenna utilization [10]. In this paper, full-wave analysis and theoretical and experimental investigations of the developed scan antenna on a ferroelectric substrate is presented with current distribution and radiation patterns. Theoretical and experimental results have been compared in order to estimate the accuracy and usefulness of the analysis and design methods. This paper is organized as follows. Section II describes the main concept of the scan antenna on a ferroelectric substrate. We also present the main characteristics of the ferroelectric ceramic–polymer composite, which constitutes a base for the substrate of the proposed scan antenna. In Section III, the theory and full-wave analysis are presented. Both longitudinal and transverse currents have been taken into account. The applied method is based on an extension of the Fourier integral method, which is used in conjunction with the method of moments. The special expansion functions are used for both longitudinal and transverse currents. The same functions are used in the Galerkin solution like weighting functions. Section IV presents the numerical analysis and results for the current distribution and radiation patterns. It includes comparisons of the theoretical and experimental results. We also present three-dimensional

(3-D) radiation patterns for showing the full field over the scan antenna and the direction where a surface wave exists. II. SCAN-ANTENNA CONCEPT The antenna, which was presented in [11], is a frequencyscanning one. Our concept is also based on the first higher order mode on a microstrip line, but the substrate is made using a ceramic–polymer composite with modified ferroelectric powder and an appropriate polymer. It allows to electrically change the phase constant of the propagation wave and, in turn, changes of the main beam direction. Fig. 1 shows the basic geometry of the radiation structure and the scan principle. The microstrip and , linewidth and the thickness of substrate are equal to respectively. As already mentioned, the substrate of the scan antenna had been made using ferroelectric ceramic–polymer composites. Those composites are a homogeneous mixture of the ceramic state and the organic polymer state. In this case, they constitute a continuous phase matrix, in which grains of the ceramic (ferroelectric) material have been discretely dispersed. Materials based on barium titanate modified with various types of additives or solid solution of barium and strontium tiTiO were the basic ferroelectric substances tanate Ba Sr used in the studies carried out. Barium titanate, as the basic ferroelectric ceramic material, is very rarely used in the pure form. Many of its parameters undergo favorable changes when small amounts of admixtures of various types of substances are introduced to it. These admixtures should form a solid solution with barium titanate or modify the inter-grain borders in the polycrystalline ceramic sinter. Pure barium titanate is characterized by the Curie temperature range of 120 C–127 C.

YASHCHYSHYN AND MODELSKI: RIGOROUS ANALYSIS AND INVESTIGATIONS OF SCAN ANTENNAS ON FERROELECTRIC SUBSTRATE

By changing the solid solution composition and introducing small amounts of additives it is, however, possible to decrease this temperature to 95 C. In the case of applying these types of materials for the construction of antennas and other devices operating in the microwave range, this would be of great advantage since their operation temperature is typically from 40 C to 60 C, i.e., in the range of their paraelectric properties. The synthesis conditions of this type of materials are other properties permitting the control of the properties of solid solutions based on barium titanate. By selection of temperature and the synthesis time, it is possible to control both the degree of conversion and the phase composition of the ceramic materials obtained. The different chemical compounds formed during the synthesis are characterized by various properties ) and, hence, even in this way, it is possible to obtain ( , materials for application in the microwave range. Temperature and sintering time of the dielectric materials synthesized in the solid phase reaction are consecutive parameters that can be controlled. The processing of the post-synthesis product permits to obtain a powder material of a defined shape, size, and size distribution of the grains. The continuous polymeric phase not only permits to form the geometry of samples. By changing the volumetric ratio of the ceramic powder to the polymer, it is possible to affect the permittivity and dielectric loss of the ceramic-powder–polymer composite. The selection or synthesis of such polymers, whose glass transition temperature would be lower than 40 C and would, at the same time, show good adhesion properties in relation to the ceramic powder grains, is also essential. Poly(vinyl alcohol) plasticized with glycerol or poly(ethylene glycol), thermoplastic poly(vinyl butyrate) in composition with phthalates, polystyrene, polymethacrylates, or poly(vinyl chloride) are among the most often applied polymeric materials. Composite layers obtained from the Ba Sr TiO synthesized in the solid-state reaction within 1150 C–1350 C temperature range during 0.5–5 h were used for the studies. This composite was doped with nickel, manganese, and iron oxides in an amount from 0.5% to 5% of weight in order to modify its electric parameters. The suitable grain size for application was obtained by grinding the sintered powder in the laboratory ball mill. The composite ceramic–polymeric layers were designed in such a way that the ferroelectric powder volume was from 75% to 97.5% of volume, whereas the polymer volume was from 100 to 500 m. Studies on the selection of the kind of polymer enabling to obtain a composite of appropriate parameters have also been carried out. Mechanical strength and appropriate flexibility permitting free operation of the composite layers obtained, as well as depositing these layers on a conducting metallic base, are the most essential properties that should characterize such a polymer. Polystyrene and poly(vinyl butyrate) were characterized as having the best properties among many other polymers studied. The main advantage of the developed composites over ceramic ferroelectric materials is that the first one is elastic and can have any dimensions (even 1 m 1 m) and has got a very low permittivity, but a high tunability (Fig. 2).

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Fig. 2. Ferroelectric ceramic–polymer composite material for the scan antenna.

Fig. 3. field.

Permittivity of some ceramic–polymer composites versus applied bias

The correspondences between the permittivity of some samples of ferroelectric ceramic–polymeric composites and applied bias voltage are reported in Fig. 3. It shows that some samples (e.g. T-6, T-7, T-8) have got a very small tunability and the other ones (T-10, T-13) are high or very high (T-18). The tunability, defined as a fractional change of the dielectric constant with applied dc-bias voltage tunability

(1)

depends on the kinds of polymer applied for the ceramic–polymer composite. Small tunability has been obtained in case of using polystyrene as the main polymeric material. In other cases (high tunability), poly(vinyl butyrate) (PVB) has been applied. The maximum tunability (for T-18) has been obtained at approximately 57%. III. THEORETICAL ANALYSIS The integral equation satisfied by the unknown natural-mode and on the line with an surface currents

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assumed propagation dependence of expressed as

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can be

(2) (7) (3) , , and are components of the where is the unknown Green’s function; complex axial propagation constant of the natural mode, and is the relative permittivity of the substrate, which can be changed by an applied electric control field. The permittivity of the ferroelectric substrate is anisotropic and can be described by the tensor. However, the thickness of the substrate (where is the wavelength) so we can suppose that only produces the main influence [12]. It has been confirmed in experimental investigations. The conventional method-of-moments procedure results in appropriate equations for open microstrip geometry [13], [14]. and transverse current The longitudinal densities on microstrip for the even and odd cases may be written as follows. 1) Even case:

where and are unknown complex constants and and are expansion functions. is Dirac’s delta, and are Chebyshev polynomials of the first kind. The expansion and weighting functions presented in this paper are better than pulse functions, which were used in [9]. Below it will be shown that the five functions are only needed for the solution, which is obtained faster and is more accurate in this case. The relation between the tangential components of the eleccurrent modes may be written in matrix tric field and the form (8) where the use of bold face denotes a matrix. The components of the matrix can be calculated using the formula for mutual impedance between different modes of both longitudinal and transversal currents (9)

(4)

are the tangential components of the electric where field on the surface of the microstrip line due to a current . The method of calculation of the tangential components is presented below. The solution of the problem has been determined by applying the boundary conditions. Since the tangential components of the electric fields at the surface of the conductor vanish, matrix form (8) becomes (10)

(5) 2) Odd case:

where is the square matrix of order and is a column matrix of the unknown complex constant. The characteristics equal to zero equation is found by setting the determinant of as follows: (11)

(6)

The eigenvectors and may be obtained by solving (8) for a particular , which, in turn, satisfies relation (11). Here, the tangential fields (and impedance functions) due to and transverse an open microstrip carrying longitudinal currents (Fig. 1) are determined. The problem is formulated in terms of fields TE and TM (relatively to the -direction) [15]. In our case, this combination constitutes a complete set describing all possible modes.

YASHCHYSHYN AND MODELSKI: RIGOROUS ANALYSIS AND INVESTIGATIONS OF SCAN ANTENNAS ON FERROELECTRIC SUBSTRATE

In general, the field intensities may be expressed in terms of (electric current) and (magnetic current) as

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is the current density distribution of original electric where or magnetic currents. Employing (16) in (14), we obtain the recomponent lationship for the

(12)

where

(17)

where

(13) is the absolute complex permittivity, is the absolute complex permeability, is the observation point, and is the source point. The longitudinal component of electric field can be expressed by

(18) Similarly to (17), the relationship for the be written as

component may

(14) (19)

The Green’s function may be presented in different forms. In the Cartesian’s coordinate system, it may be written as where

(20) (15) ; . A double sign at an where exponent takes into consideration different forms of the Green’s (upper sign) function in a source-free region: (lower sign). An analysis of (15) shows that and , we if the environment is lossless and when obtain a spectrum of traveling waves, which are propagating in , waves are suppressing in the the OZ-direction. If OZ-direction. Employing (15) in (13), we may obtain

, , , and The transverse components of the field in a source-free region may be given by longitudinal components as

(21)

Substituting (17), (19), and (20) in Maxwell’s equations, we may obtain the following relationship: (16) (22)

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Rewriting (22) in Descartes’ coordinate system, we can obtain another relationship for

(23)

(24) The full field is a sum of vectors (23) and (24). When substituting (6) and (7) into (17)–(20) (for the case , , ) and next into (23) and (24), and ) components of the electric field we obtain tangential ( , on the surface of the microstrip line. These components are substituted into (9) so, in our case, the impedance functions may be written as

Fig. 4. (a) Normalized phase constant and (b) leakage constant as a function of permittivity for h = 0:2 mm and w = 10:5 mm.

(25)

where

, , and

, is the Bessel’s

function (29) (30) where (26)

(27) (28)

is the reflection function for the TM/TE case. IV. NUMERICAL ANALYSIS AND RESULTS

The integrands of the spectral representation of mutual impedances (25–28) contain: 1) branch points and 2) simple pole singularities. There are three propagation regimes for higher order modes on open microstrip transmission lines, which are: 1) a bound regime; 2) a surface-wave regime; and 3) a radiation one. In [16], it is shown that both the poles and branch points migrate from quadrants II and IV, across the contour of integration, into quadrants III and I when changes. This necessitates a deformation in the contour of spectral integration around both the branch cuts and surface-wave poles.

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TABLE I COMPLEX FACTORS FOR " =" = 3:25

TABLE II COMPLEX FACTORS FOR " =" = 3:5

TABLE III COMPLEX FACTORS FOR " =" = 3:75

Fig. 4(a) and (b) shows calculated normalized phase constant and leakage constant, respectively, as a function of permittivity mm and mm [9]. It can be seen that, as for the permittivity is lowered (after onset of leakage), the value of the leakage constant increases and the beam moves up from the endfire. In the current structure, the complex propagation constant can be changed by changing the frequency or by changing the dielectric constant of the substrate, as in the case of the electrically controlled ferroelectric ceramic–polymer composite. In general, -plane) is given the direction of the radiated beam (in the by (31) where is the phase constant, is the angle of the beam maximum measured from the broadside direction, is the leakage constant. and are obtained by solving (8) for The eigenvectors particular . During the calculation of and , normalization of has been assumed. The value of other factors has been calculated in the course of the pseudosolution finding of matrix equation (8) in which the first factors) is moved to the right-hand side of the equacolumn ( tion. It is necessary to note that the error of the conventional solution, which is obtained by matrix inversion (one equation is rejected), is large. Tables I–III present examples of complex

Fig. 5. (a) Longitudinal and (b) transverse currents distribution of the first higher order mode for different values of permittivity.

: 3.25, 3.5, factors found for three values of permittivity and 3.75, respectively, and for GHz. From these tables, we can infer that the application of five modes is adequate for our case because the maximal value of (Table I) is up to 5%. Fig. 5 presents an example of current distributions of the first higher order modes for which frequency equals 7.75 GHz and ( mm, mm, can be changed from 3.0 to 4.0). It can be seen that transverse currents very strongly depend on substrate permittivity. The same current distributions have been obtained in [16]. Comparisons show that the forms of the current are similar, whereas the magnitudes are different due to different normalization. In this paper, we present the general expression for the 3-D radiation pattern. To take into consideration the vector character of fields, we can write (32)

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where

(33) (34)

(35) where is the tangential electric field in the antenna aperture. Functions can be calculated by transforming to spherical coordinates in (17), (23), and (24) with and . Wave impedance depends on the dimensions of an aperture, the angle of an incidence wave, and other factors. For example, if the phase of the field in an aperture (of which dimensions are larger than wavelength) has zero phase progression, then the wave impedance will be equal to . Finally, in the case of infinite grounded substrate , functions may be written as

(36)

H

Fig. 6. Normalized radiation patterns in the -plane for different values of substrate permittivity, simulated for the current shown in Fig. 5.

Fig. 7. Aperture of an electrical scan antenna on a ferroelectric substrate.

(37) where

H

Fig. 8. Theoretical radiation patterns in the -plane for different values of substrate permittivity and measured ones for different bias voltages.

is the length of the antenna.

Similar relations have been presented in [17] and [18] for rectangular elements. In Fig. 6, the normalized radiation patterns of the scan antenna described above are shown as a function of in the elevation plane for different values of substrate permittivity.

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Fig. 9. Topographic view of normalized radiating power in the far zone for different values of substrate permittivity. (a) " =" = 3:0. (b) " =" = 3:25. (c) " =" = 3:5. (d) " =" = 3:75.

They were simulated for current distribution shown in Fig. 5. In Fig. 6, the dependence of radiating patterns with respect to substrate permittivity, which changes only from 3.0 to 4.0, is depicted. It can be noticed that, for those values of permittivity, the beam moves from broadside toward the endfire direction. The necessary tunability of the required substrate permittivity is approximately 25% in this case. In order to verify the properties of radiation, the scan antenna has been fabricated (Fig. 7). A 100-mm-long microstrip of the width of 10.5 mm was placed on a 0.2-mm-thick ferroelectric ceramic-composite substrate with relative permittivity, which could be changed from 3.0 to 4.0. The antenna is fed by a microstrip line across a slot in the ground plane. This feeding network differs from the one presented in [9]. The feeding network was especially designed to prevent bias voltage leakage in the rest of the circuit, however, it is not shown in Fig. 7. Examples of theoretical and experimental radiation patterns of the described microstrip electrically controllable scan antenna are shown in Fig. 8. It presents calculated radiation pat-

terns in the -plane for three values of permittivity (taking into account ferroelectric ceramic–polymer composite loses and the load on the end of the antenna) and measured for three values of applied voltage (0, 100, and 200 V), respectively. It is easy to notice a very good agreement. In [19], the dependence of normalized maximum radiating power (calculated and measured) on substrate permittivity is shown. It can be seen that the maximum radiating power decreases rapidly near the broadside direction. Again, a good agreement between theoretical and experimental results can be observed. Particular attention was dedicated to the design of the matching circuit to minimize the variation of insertion losses between biased and unbiased conditions. This aim was successfully achieved with the observation that losses of the ferroelectric ceramic–polymer composite increase under bias condition. This property can be used by having a well-matched circuit dB, GHz) in the unbiased condition ( and a merely sufficient matching under biased condition dB, GHz). (

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Fig. 10. Topographic view of normalized power of TM surface wave for different values of substrate permittivity. (a) " =" (c) " =" = 3:5. (d) " =" = 3:75.

A topic worthy of further theoretical investigation for the leaky-wave scan antenna is the presence of the 3-D radiating pattern. To our knowledge, qualitative and quantitative information cannot be found in the literature for these kinds of structures. Fig. 9 shows a topographic view of normalized radiating (kapa1)– (kapa2) coordipower in the far zone (in nate system) for different values of substrate permittivity: [see Fig. 9(a)], [see Fig. 9(b)], [see Fig. 9(c)], [see Fig. 9(d)]. Fig. 10 shows the normalized power of the surface wave in the first TM mode

for an infinite grounded substrate. The function is estimated below. These results clearly show that, despite the

= 3:0. (b) " =" = 3:25.

fact that the main beam exists, there is also the power propagated by a TM surface wave. The direction of the propagation of this wave may be written as

(38) where is the angle of propagation of the surface wave mea; ); is the sured from the main direction ( surface-wave eigenvalue corresponding to the pole of the func. tion (29) obtained for The power propagated by the surface wave may be calculated from (17) because the residues of the pole (which correspond to the wavenumber of the surface-wave mode on an infinite structure) directly determine the amplitude of this mode. The commakes the largest contribution in ponent of the electric field the TM surface wave power [12].

YASHCHYSHYN AND MODELSKI: RIGOROUS ANALYSIS AND INVESTIGATIONS OF SCAN ANTENNAS ON FERROELECTRIC SUBSTRATE

Fig. 11. Calculated normalized power of the surface wave as a function of the substrate permittivity.

Transforming the component on the surface of the substrate to the polar coordinate and using the theorem of residues of the pole, we may write

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expand functional possibilities of the known frequency scan leaky-wave antennas. The substrate of the presented microstrip antenna has been made using a ceramic–polymer composite with modified ferroelectric powder Ba Sr TiO and an appropriate polymer (grains of the powder were sprayed into polymer with the use of a specific method). The ceramic–polymer composite was designed to change permittivity in response to an applied electric control field for antenna utilization. The main advantage of the developed composites over ceramic ferroelectric materials is that the first one is elastic and can have any dimensions (even 1 m ), it has also got a very low permittivity and a high tunability. It allows to electrically change the phase constant of the propagation wave and, in turn, changes the main beam direction. It has been shown that the beam angle changes over 30 when the dc-bias field is applied up to 200 V. The rigorous full-wave analysis of the developed scan antenna on a ferroelectric substrate has taken into account the current distributions of the first higher order modes, and radiation characteristics have been investigated. The expansion and weighting functions presented in this paper are better than earlier applied pulse functions because the five functions are only needed for the solution. The solution is more accurate and can be received faster. The comparison with experimental results has fully confirmed the usefulness of the scan-antenna concept and method of analysis. Presented results of the electrical scanned antenna investigation are promising, especially for fixed-frequency operation, where frequency scanning is impossible. ACKNOWLEDGMENT

(39) where and Fig. 11 shows normalized power

of the surface wave in the direction (38) as a function of the propagation constant , which, in turn, is a function of the substrate permittivity. This curve is very similar to the one depicted in [19, Fig. 4] because power of the surface wave is related to the total power over structure. The influence of dielectric material is observed even when is small, especially in the -plane. The direction of the surface-wave propagation and the power of surface wave depend of the longitudinal and transverse on propagation constant current densities on the microstrip line. This means that when the array of the scan antenna is considered on the large substrate, then mutual coupling between scan antennas is necessary to be taken into account. V. CONCLUSION In this paper, rigorous analysis and investigation of the new low-cost electrical scanned antenna on a ferroelectric substrate has been presented. The electrical scan property permits to

The authors would like to thank Prof. N. Szafran and Ms. E. Bobryk, both of the Chemical Department, Warsaw University of Technology, Warsaw, Poland, for the development of the ferroelectric ceramic–polymer composite. REFERENCES [1] R. Fralich and J. Litva, “Beam steerable active array antenna,” Electron. Lett., vol. 28, pp. 184–185, Jan. 1992. [2] R. E. Horn, H. Jacobs, E. Freibergs, and K. L. Klohn, “Electronic modulated beam-steerable silicon waveguide array antenna,” IEEE Trans. Microw. Theory Tech., vol. 28, no. 6, pp. 647–655, Jun. 1980. [3] L. Huang, J. C. Chiao, and M. P. De Lisio, “An electronically switchable leaky wave antenna,” IEEE Trans. Antennas Propag., vol. 48, no. 11, pp. 1769–1772, Nov. 2000. [4] C. H. Lee, P. S. Mark, and A. P. DeFonzo, “Optical control of millimeterwave propagation in dielectric waveguides,” IEEE J. Quantum Electron., vol. 16, no. 3, pp. 277–288, Mar. 1990. [5] V. A. Manasson, L. S. Sadovnik, V. A. Yepishin, and D. Marker, “An optically controlled MMW beam-steering antenna based on a novel architecture,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 8, pp. 1497–1500, Aug. 1997. [6] R. A. Stern and J. Borowick, “A millimeter-wave homogeneous ferrite phase scan antenna,” Microwave J., pp. 101–108, Apr. 1987. [7] A. S. Cherepanov and A. B. Gouskov, “Innovative integrated ferrite phased array technologies for EHF radar and communication applications,” in Proc. Int. IEEE Phased Array Systems and Technology Symp., Oct. 1996, pp. 74–77. [8] J. B. L. Rao, G. V. Trunk, and D. P. Patel, “Two low-cost phased arrays,” IEEE Aerosp. Electron. Syst. Mag., vol. 12, pp. 39–44, Jun. 1997. [9] J. Modelski and Y. Yashchyshyn, “A new microstrip electrically controllable scan antenna,” in Proc. 33rd Eur. Microwave Conf., vol. 1, Oct. 2003, pp. 931–934. [10] Y. Yashchyshyn, M. Szafran, J. Modelski, and E. Bobryk, “Investigation of the ferroelectric material behavior in microwave band” (in Polish), Electron. Telecommun. Quart., vol. nr. 49 z.2, pp. 245–254, 2003. [11] W. Menzel, “A new traveling-wave antenna in microstrip,” Electron. Commun., vol. 33, no. 4, pp. 137–140, Apr. 1979.

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[12] D. M. Pozar and D. H. Schaubert, Microstrip Antennas. The Analysis and Design of Microstrip Antennas And Arrays. Piscataway, NJ: IEEE Press, 1995. [13] T. Itoh and W. Menzel, “A full-wave analysis method for open microstrip structures,” IEEE Trans. Antennas Propag., vol. AP-29, no. 1, pp. 63–68, Jan. 1981. [14] J. M. Grimm and D. P. Nyquist, “Spectral analysis considerations relevant to radiation and leaky modes of open-boundary microstrip transmission line,” IEEE Trans. Microw. Theory Tech., vol. 41, no. 1, pp. 150–153, Jan. 1993. [15] L. B. Felsen and N. Marcuvitz, Radiation and Scattering of Waves. Englewood Cliffs, NJ: Prentice-Hall, 1973. [16] J. S. Bagby, C. H. Lee, D. P. Nyquist, and Y. Yuan, “Identification of propagation regimes on integrated microstrip transmission lines,” IEEE Trans. Microw. Theory Tech, vol. 41, no. 11, pp. 1887–1894, Nov. 1993. [17] P. Permutter, S. Shtrikman, and D. Treves, “Electric surface current model for the analysis of microstrip antennas with application to rectangular elements,” IEEE Trans. Antennas Propag., vol. AP-33, no. 3, pp. 301–311, Mar. 1985. [18] E. Levine, G. Malamud, S. Shtrikman, and D. Treves, “A study of microstrip array antennas with the feed network,” IEEE Trans. Antennas Propag., vol. 37, no. 4, pp. 426–434, Apr. 1989. [19] Y. Yashchyshyn and J. Modelski, “Rigorous analysis and investigations of the scan antenna on ferroelectric substrate,” in Proc. Int. Microwave Radars and Wireless Communications Conf., May 2004, pp. 391–394.

Yevhen Yashchyshyn (M’96) was born in Lviv, Ukraine, in 1957. He received the M.Sc. degree in radioelectronics engineering from the Lviv University of Technology, Lviv, Ukraine, in 1979, and the Ph.D. degree in microwave devices and antennas from the Moscow Institute of the Electronic Machine Building, Moscow, Russia, in 1986. In 1991 he became a Senior Scientist. From 1979 to 1999, he was with the Lviv Polytechnic National University, as an Engineer, Head of the Research Laboratory, and Associate Professor with the Telecommunication Department. Since 1999, he has been with the Institute of Radioelectronics (IR), Warsaw University of Technology (WUT), Warsaw, Poland, where he is currently an Associate Professor. Since 2002, he has been Head of the Antennas Laboratory, IR WUT. His research interests cover the areas of antenna theory and techniques, smart beamforming and design of communications, and radar antennas. He has authored or coauthored over 100 technical papers. He holds six patents.

Józef W. Modelski (SM’90–F’01) was born in Kawnice, Poland, in 1949. He received the M.Sc., Ph.D., and D.Sc. (habilitation) degrees in electronics from the Warsaw University of Technology (WUT), Warsaw, Poland, in 1973, 1978 and 1987, respectively. In 1994, he became a Professor. Since 1973, he has been with the Institute of Radioelectronics, WUT, where he has been a Teaching/Research Assistant through a Tenured Professor (1991). From 1976 to 1977, he was a Fulbright grantee with the University of Texas at Austin, Cornell University, and the COMSAT Laboratories. In 1985, he visited Germany as a Deutcher Akademischer Austauschdienst (DAAD) grantee. From 1986 to 1988, he was a Senior Scientist with the Braunschweig Technical University, Braunschweig, Germany. Since 1996, he has been Director of the Institute of Radioelectronics, Warsaw University of Technology. He has authored or coauthored over 200 technical papers and four monographs. He holds nine patents. His research interests include microwave modulators and shifters with semiconductor and ferrite elements, dielectric resonators and their applications, integrating waveguide technology, methods, and equipment of material properties measurements, and recently, ferroelectric and smart antennas for communication systems. He acts as consultant to industry and Polish Government agencies. Dr. Modelski is an associate member of the National Academy of Sciences of Ukraine and a few committees of the Polish Academy of Sciences. Since 1996, he has been chair of the International Conference on Microwaves, Radar and Wireless Communications (MIKON), a member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) Technical Program Committees (TPCs) and the European Microwave Conference. He has been a member of the TPC and Steering Committees of numerous local conferences in Europe. Since 2000, he has been an IEEE MTT-S Administrative Committee member. From 2000 to 2001, he was chair of the Transactional Committee. From 2002 to 2003, he was chair of the Membership Services Committee. He is currently vice-chairman of the Technical Coordinating Committee. Since 2002, he has also served as IEEE Region 8 chair of the Chapter Coordination Committee.

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Frequency Conversion of Optical Signals in p-i-n Photodiodes Sergei A. Malyshev, Member, IEEE, Bogdan A. Galwas, Member, IEEE, Alexander L. Chizh, Member, IEEE, Jaroslaw Dawidczyk, and Vatslav F. Andrievski, Member, IEEE

Abstract—A planar InGaAsP/InGaAs/InGaAsP p-i-n photodiode has been fabricated and used for frequency conversion of two optical signals. Nonlinear properties of the photodiode have been investigated. It is shown that photodiode responsivity ( ) dependence on bias voltage can be characterized by a parameter of the nonlinearity , which is equal to ( ) ( ) and the maximal conversion efficiency is achieved at the bias voltage where the parameter has the maximal value. Index Terms—Optoelectronic mixing, p-i-n photodiode.

I. INTRODUCTION

P

-I-N photodiodes are most widely used as photodetectors in broad-band receivers of analog optical fiber links. In a conventional design, the photodiode converts an optical signal into an electrical signal. The signal is then amplified and subjected to up or down conversion in an electrical way. With such a design, the photodiode is used in a linear mode. However, in general, the photodiode is a nonlinear device. In subcarrier multiplexed systems, when a large number of electrical carriers is led into a system, this nonlinearity causes frequency conversion between particular signals. This is an undesirable process. On the other hand, this nonlinearity can be turned to advantage. The process of recovery of the electrical signal can be simplified by using mixing phenomena, which occur between transmitted signals. This design solution offers cost-effective, simple, and potentially high-performance alternatives in radio-on-fiber systems. In this technique, the photodiode acts simultaneously as a detector and an up or down converter. It is worth noting that mixing of two optical signals in the photodiode has potential advantages over optical-microwave mixing [1]–[3] because there is no need to use a microwave local oscillator at the receiver part [4]. The main goal of this paper is to study the influence of such parameters of intensity-modulated optical signals as average optical power, modulation frequency, and optical modulation depth (OMD) on the frequency conversion process in the planar InGaAsP/InGaAs/InGaAsP p-i-n photodiode fabricated.

Manuscript received April 18, 2004; revised June 29, 2004. This work was supported by the Belarusian Republican Fund of Fundamental Researchers under Project F03MC-022. S. A. Malyshev, A. L. Chizh, and V. F. Andrievski are with the Laboratory of Semiconductor Optoelectronics, Institute of Electronics, National Academy of Sciences of Belarus, Minsk 220090, Belarus (e-mail: [email protected]). B. A. Galwas and J. Dawidczyk are with the Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, 00-665 Warsaw, Poland. Digital Object Identifier 10.1109/TMTT.2004.840774

Fig. 1. Measured reflection coefficients: (a) in the frequency range of 3 GHz for different bias voltages and zero optical power and 0.3 MHz (b) for different optical powers at 1.51-m wavelength and zero bias voltage. (a) points show frequencies with a 0.25-GHz step. (b) points show 0.0003, 0.125, 0.25, 0.5, 1.0, 1.5, 2.0, 2.5, and 3.0 GHz.

4

II. p-i-n PHOTODIODE PERFORMANCE To achieve an efficient optoelectronic mixing, a p-i-n photodiode should have a high responsivity under reverse-bias voltage and a sharp knee of the responsivity–voltage charac[5]. To obtain high conversion efficiency, a p-i-n teristic photodiode based on an InGaAsP/InGaAs/InGaAsP epitaxial heterostructure has been designed and fabricated. The photodiode had a front-illuminated p -region placed in a pigtailed fiber-optical module. The epitaxial structures of the photodiode undoped n consisted of an 1.0- m-thick 1.2 10 cm In Ga As P top layer, 3.0- m-thick 1.2 10 cm undoped n In Ga As absorption layer, 1.0- m-thick 3 10 cm Te doped n In Ga As P contact layer, and a 400- m-thick semi-insulating InP substrate. The p -region was formed by local diffusion of Zn into the wide-band gap n-InGaAsP top layer. P-n junction depth was made 0.8 m. The device photosensitive area was 35 m in diameter and the wavelength range was from 1.0 up to 1.65 m. The spectral sensitivity at 1.51 m was 1.0 A/W at reverse-bias voltage 5 V and 0.98 A/W at zero-bias voltage. The photodiode reflection coefficient in the frequency range of 0.3 MHz 3.0 GHz under different bias voltages and optical powers is shown in Fig. 1. Measurements have been carried out using an HP 8753C vector network analyzer. It is seen that, -parameters strongly depend on the under zero-bias voltage, optical power. The relative responsivity versus photodiode voltage under different frequencies is shown in Fig. 2(a). The photodiode response exhibits the highest nonlinearity near zero-bias

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Fig. 2. (a) Relative responsivity and (b) parameter of nonlinearity versus voltage at the p-i-n photodiode under optical power 0.5 mW at the 1.3-m wavelength and for different modulation frequencies 0.01, 0.5, and 1.5 GHz.

Fig. 3. (a) Relative responsivity and (b) parameter of nonlinearity versus voltage at the p-i-n photodiode for a modulation frequency of 2.0 GHz and different optical power values at the 1.51-m wavelength.

voltage. A decrease in the reverse-bias voltage results in the decreasing of the depletion region, and part of the generated photocarriers recombine in the neutral region and do not contribute to the photocurrent. This results in the lowering of the photodiode response at the small bias voltages. Nonlinearity of the photodiode response is convenient to evaluate by the use of the nonlinearity parameter , which is equal to the product , and is shown in Fig. 2(b). The steepest curve is obtained at low frequencies (below 0.1 GHz), and parameter takes a maximum value at the bias voltage 0.37 V. The increasing of the modulation frequency leads to a decrease in the maximum of the parameter and its shifting toward the reverse-bias voltages. Conversely, the nonlinearity of the characteristic for the reverse-bias voltages is increased. For the frequencies 0.5 2.0 GHz, parameter is maximum at the bias voltage of approximately 0.1 V. Fig. 3(a) shows a decrease in the photodiode responsivity under high optical power due to a photocurrent saturation effect. It should be noted that measurements of the relative responsivity have been made under various OMDs of the intensity-modulated optical signal, and it has been found that characteristic does not show any dependence on the the OMD. Thus, the responsivity of the p-i-n photodiode depends only on the average power of the intensity-modulated optical signal.

It is seen from Fig. 3(b) that an increase of the optical power causes lowering of the maximum of the nonlinearity parameter , shifting of its position toward the reverse-bias voltages, and characteristic in the increasing of the nonlinearity of the region of higher reverse-bias voltages. For the p-i-n photodiode under study, the characteristic does not depend on the optical power if its value is below 0.4 mW. This optical power can be called the saturation optical power in the nonlinear mode. It is worth noting that this value is considerably lower than the saturation optical power in the linear mode measured at a high reverse-bias voltage. In contrast to its behavior in the linear regime, in the nonlinear mode, the saturation optical power does not depend on the bias voltage or modulation frequency and is only determined by the p-i-n photodiode structure. III. OPTO-ELECTRONIC MIXING EXPERIMENTAL SETUP Fig. 4 shows the schematic diagram of the experimental setup used to investigate the process of frequency conversion of two intensity-modulated optical signals in a p-i-n photodiode. Two optical sources were used, i.e., an HP 83400A 1.3- m lightwave source and a 1.51- m Fabry–Perot laser. The output power of both optical sources was intensity modulated by and . The two electrical signals of different frequencies

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Fig. 4. Block diagram of the experimental setup.

Fig. 6. Conversion efficiency of the up-converted signal versus photodiode voltage in the case of the first small optical signal at the wavelength 1.3 m and with modulation frequency 2.0 GHz, power 0.1 mW, and OMD 70%, and the second large optical signal at the wavelength 1.51 m and with modulation frequency 0.2 GHz, OMD 99%, and different optical power values: 0.2, 0.3, 0.5, 1.0, 1.5 mW.

Fig. 5. Power of the detected and converted signals versus photodiode voltage in the case of small optical signals of equal power of 0.25 mW at the wavelength 1.51 and 1.3 m, and modulation frequencies 0.2 and 2.0 GHz, respectively.

modulated optical signals

and are both lead through optical fibers to an optical coupler and then to a p-i-n photodiode. Electrical signals from the photodiode (detected signals and mixing products) are lead to an Anritsu MS2661 spectrum analyzer and measured. Up- and down-converted signals were measured versus voltage across the p-i-n photodiode at the and the frequency , respectively. frequency The mechanism of mixing of two modulated optical signals in the p-i-n photodiode is mainly determined by the voltage dependence of the photodiode responsivity under the condition of nonzero load resistance [5]. Thus, the opto-electronic mixing proceeds in the following way. The p-i-n photodiode detects an optical signal and generates a photocurrent. Due to the photocurrent loading effect, the detected signal produces oscillations of the voltage at the photodiode, which result in oscillations of the photodiode responsivity . Thus, the second optical signal is detected by the p-i-n photodiode with modulated responsivity and, therefore, mixing products with sum and difference frequencies are generated. Hence, to obtain an efficient opto-electronic mixing of two modulated optical signals, it is necessary to have high photodiode responsivity and large voltage derivative of the responsivity . In other words, for the opto-electronic mixing to be efficient, the parameter of nonlinearity should be as high as possible, and maximum conversion efficiency is achieved at a bias voltage is at maximum. where the parameter

Fig. 7. Conversion efficiency of the up-converted signal versus photodiode voltage in the case of the first small optical signal at the wavelength 1.3 m and with modulation frequency 2.0 GHz, power 0.1 mW, and OMD 70%, and the second large optical signal at the wavelength 1.51 m and with modulation frequency 0.2 GHz, power 1.5 mW, and different OMD values: 3, 25, 50, 75, and 99%.

IV. RESULTS AND DISCUSSION To describe the efficiency of the frequency-conversion process, it is convenient to define the conversion efficiency as the ratio of the microwave power measured at the mixing frequency and the power measured at the signal frequency related to the smallest optical signal in the linear mode of the p-i-n photodiode [4], [5]. Fig. 5 shows the detected and converted signals versus voltage in the case of small optical signals of equal power 0.25 mW at the wavelength 1.51 and 1.3 m and modulation frequencies 0.2 and 2.0 GHz, respectively. Fig. 5 shows that, for high reverse-bias voltages, the photodiode responsivity is not affected by voltage (linear mode), and no mixing products are generated. The converted signals demonstrate the highest power at bias voltages 0.8 0.2 V.

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Fig. 8. Conversion efficiency of the: (a) down-converted signal and (b) up-converted signal versus photodiode voltage for the case of the first small optical signal at the wavelength 1.3 m with modulation frequency 1.5 GHz, power 0.1 mW, and OMD 70%, and the second large optical signal at the same wavelength 1.3 m with power 0.5 mW, OMD 95%, and different modulation frequency values: 0.01, 0.5, 1.0, 1.4, 1.45, and 1.475 GHz.

It should be remarked that the behavior of the characteristic is different for 0.2 and 2.0 GHz. Therefore, a maximum of the conversion efficiency is achieved at the bias voltage where reaches the product of nonlinearity parameters the maximum. Fig. 6 shows the up-conversion efficiency versus voltage at the p-i-n photodiode in the case where the optical signal at the 1.51- m wavelength has the OMD of 99% and the optical power 2, 3, 5, 10, and 15 times higher than the power of the optical signal at the 1.3- m wavelength. It can be seen that, as the optical power of the first signal is increased, the conversion efficiency rises irrespective of the bias voltage and the optimal bias voltage is shifted toward the reverse-bias voltages. It must be noted that the optimal bias point does not change with the optical power at 1.51 m increasing from 0.2 to 0.3 mW because these optical powers are smaller than the saturation optical power in the nonlinear mode of the p-i-n photodiode under consideration. Fig. 6 also demonstrates saturation of the conversion efficiency under a high optical power. It is explained by a decrease in the photodiode nonlinearity parameter at high optical powers. Thus, as power of the mixed optical signals is increased, two different regions appear. The first region can be referred to as linear mixing, and it is bounded by the saturation optical power in the nonlinear mode (curves 0.2 and 0.3 mW in Fig. 6). For this region, the conversion efficiency is increased at any bias proportionally with increasing optical power voltage. The second region corresponds to optical powers higher than the saturation optical power in the nonlinear regime, and it can be referred to as saturated mixing (curves 0.5, 1.0, and 1.5 mW in Fig. 6). In this region, the maximum conversion efficiency rises at a slower rate than the rate of increase of the , and the optimal bias voltage shifts toward optical power the reverse-bias voltages where the conversion efficiency builds up significantly. Fig. 7 shows the up-conversion efficiency as a function of the optical signal modulation depth for a 1.5-mW signal at 1.51- m wavelength and modulation frequency of 0.2 GHz. The second optical signal has 0.1-mW power, 1.3- m wavelength, and 2.0-GHz modulation frequency. One can see that a decrease of the OMD results in a decrease of the conversion efficiency,

which is caused by a fall in the detected signal power. It should be pointed out that conversion efficiency decreases by the same number of decibels as the detected signal power. This supports the view that opto-electronic mixing in the p-i-n photodiode occurs only due to the fact that responsivity depends on the bias voltage and nonzero load resistance. Fig. 8 shows the behavior of the down- and up-conversion efficiency for the modulation frequency of the first optical signal varying from very low frequencies to frequencies close to the modulation frequency of the second optical signal. It can be seen from Fig. 8(a) that the down-converted signal is suppressed as modulation frequencies of the mixed optical signals get closer to each other and, in contrast, there is no suppression of the up-converted signal, as shown in Fig. 8(b). When the modulation frequency of the first optical signal is low (0.01 GHz), as compared with the second optical signal (1.5 GHz), the curves of the down-and up-conversion efficiency versus bias voltage look the same, and the maximum conversion efficiency is 12.6 dB. As the modulation frequency of the first optical signal increases up to 0.5, 1.0 and 1.5 GHz, the maximum up-conversion efficiency falls down to 19, 20, and 20.5 dB, respectively, due to a decrease of the maximum value of the nonlinearity parameter . At the same time, the parameter of nonlinearity increases in the domain of high reverse-bias voltages. This leads to an increase in the up-conversion efficiency with increasing frequency in the region of high reverse-bias voltages. The down-conversion efficiency tends to diminish at any bias voltages. The suppression of the down-converted signal in the case where modulation frequencies of the mixed optical signals are close to each other is connected with the transit time delay between the oscillations of the optical signal power and voltage at the photodiode. To prevent suppression of the down-converted signal, the difference between the oscillation periods of the mixed optical signal amplitudes should be much larger than the transit time of the p-i-n photodiode

MALYSHEV et al.: FREQUENCY CONVERSION OF OPTICAL SIGNALS IN p-i-n PHOTODIODES

For the p-i-n photodiode fabricated, is approximately 100 GHz, the ps, and for the modulation frequency down-converted signal will not be suppressed if the difference of the mixed optical signals between modulation frequencies will be much larger than 0.225 GHz. This condition is satisfied GHz , where downfor the case shown in Fig. 5 and up-converted signals have the same microwave power. V. CONCLUSION The process of frequency conversion of two intensity- modulated optical signals in the p-i-n photodiode has been investigated. It is shown that the parameter of nonlinearity that is determines the conversion equal to the product efficiency of the opto-electronic mixing, and maximum conversion efficiency is achieved at the bias voltage where parameter takes the maximum value. Increasing the power or modulation frequency of the mixed optical signals decreases the maximum of the parameter of nonlinearity , shifts its position toward the reverse-bias voltages, and increases nonlinearity of the characteristics in the region of high reverse-bias voltages. The conversion efficiency of the opto-electronic mixing rises with increasing power and OMD of the mixed optical signals. It is found that the down-converted signal is suppressed when modulation frequencies of the mixed optical signals become close to each other. For the planar InGaAsP/InGaAs/InGaAsP p-i-n photodiode fabricated, maximum conversion efficiency of 12.6 dB has been obtained. REFERENCES [1] J. Piotrowski, B. Galwas, S. Malyshev, and V. Andrievski, “Investigation of InGaAs p-i-n photodiode for optical-microwave mixing process,” in Proc. 12th Int. Microwaves Radar Conf., vol. 1, May 1998, pp. 171–175. [2] J. Dawidczyk, B. Galwas, and S. Malyshev, “Investigation of optical-microwave frequency conversion processes for p-i-n photodiode,” in Proc. High Performance Electron Devices for Microwave and Optoelectronic Applications, Nov. 1999, pp. 103–107. [3] B. Galwas, J. Dawidczyk, A. Chizh, and S. Malyshev, “Modeling of responsivity of InP p-i-n photodiode for studying optoelectronic frequency conversion processes,” in Proc. Eur. Gallium Arsenide and Other Semiconductors Application Symp., Oct. 2000, pp. 157–160. [4] M. Tsuchiya and T. Hoshida, “Nonlinear photodetection scheme and its system applications to fiber-optic millimeter-wave wireless down-links,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 7, pp. 1342–1350, Jul. 1999. [5] S. Malyshev, B. Galwas, A. Chizh, J. Dawidczyk, and V. Andrievski, “Study of frequency conversion process of two optically transmitted signals to p-i-n photodiodes,” in Proc. 15th Int. Microwaves, Radar, Wireless Communications Conf., vol. 3, May 2004, pp. 878–881.

Sergei A. Malyshev (M’96) was born in Grossenhain, Germany, 1946. He received the Diploma degree in electronic engineering from the Belarusian State University of Informatics and Radio Electronics, Minks, Belarus, in 1970, and the Ph.D. degree in solid-state electronics from the Institute of Electronics, National Academy of Sciences of Belarus, Minks, Belarus, in 1979. In 1973, he joined the Institute of Electronics, National Academy of Sciences, where he currently heads the Laboratory of Semiconductor Optoelectronics. His current research involves microwave photonics, opto-electronic devices based on AIII–BV compounds and photodetectors for various applications. Dr. Malyshev is a Fellow of the Institute of Physics (IoP) and a member of the Belarusian Physical Society.

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Bogdan A. Galwas (M’92) was born in Tomaszow Mazowiecki, Poland, in 1938. He received the M.Sc., Ph.D., and Habilitated Doctor’s degrees in electronic engineering from the Warsaw University of Technology, Warsaw, Poland, in 1962, 1969, and 1976, respectively. In 1962, he joined the Faculty of Electronics, Warsaw University of Technology, as Lecturer. In 1986, he became a Full Professor. His current research interests are focused on microwave electronics and photonics. He has authored over 130 scientific papers and two books in these areas. His current main field of academic interest is connected with technology of education. He heads the Centre of Open and Distance Education (CODE). Prof. Galwas was a chairman of the International Management Committee of the International Travelling Summer Schools (1991). He is a member of the International Assocation of Continuing Engineering Education (IACEE) (since 1997) and the Societe Europeenne pour la Formation des Ingenieurs (SEFI) (since 1997).

Alexander L. Chizh (M’03) was born in Bryansk, Russia, 1977. He received the Diploma degree in physical electronics from the Belarusian State University, Minks, Belarus, in 1999. In 1999, he joined the Institute of Electronics, National Academy of Sciences, Minsk, Belarus, where he is currently a Researcher with the Laboratory of Semiconductor Optoelectronics. His current research involves microwave photonics, opto-electronic device simulation, and photodetectors for various microwave applications. Mr. Chizh is a member of the Belarusian Physical Society. He was the Recipient of the 2002 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Graduate Fellowship.

Jaroslaw Dawidczyk was born in Warsaw, Poland, in 1974. He received the M.Sc. degree (with first-class honors) in electronic engineering from the Warsaw University of Technology, Warsaw, Poland in 1998, and is currently working toward the Ph.D. degree at the Warsaw University of Technology.

Vatslav F. Andrievski (M’97) was born in the Vitebsk region, Belarus, 1960. He received the Diploma degree in opto-electronics from the St. Petersburg Electroengineering Institute, St. Petersburg, Russia, in 1983, and the Ph.D. degree in solid-state electronics from the Institute of Electronics, National Academy of Sciences of Belarus, Minks, Belarus, in 2002. In 1991, he joined the Institute of Electronics of National Academy of Sciences of Belarus, where he is currently a Senior Researcher with the Laboratory of Semiconductor Optoelectronics. His main research interest is the study of electrophysical properties of AIII–BV compounds and opto-electronic devices design and packaging.

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Retrieval of Information About Turbulence in Rain by Using Doppler-Polarimetric Radar Felix J. Yanovsky, Senior Member, IEEE, Herman W. J. Russchenberg, and Christine M. H. Unal

Abstract—This paper considers new possibilities of turbulence intensity retrieval by using Doppler and Doppler-polarimetric radar sounding. Peculiarities of microwave scattering on moving droplets of different size and shape underlie new methods that are introduced, discussed, and checked by using radar data. Index Terms—Atmosphere turbulence, Doppler-polarimetric radar, Doppler polarimetry, Doppler spectrum, drop velocity distribution, microwave radar, remote sensing of rain, spectral differential reflectivity.

I. INTRODUCTION

R

ADAR RETURNS from weather objects (clouds, precipitation, etc.) are usually considered as clutter. Clutter echoes are random and have noise-like characteristics because the individual clutter components (scatterers) give random phases and amplitudes. In many cases, the clutter signal level is much higher than the receiver noise level. Thus, the radar’s ability to detect targets embedded in high clutter background depends frequently on the signal-to-clutter ratio rather than the signal-to-noise ratio. At the same time, in many cases, weather formations are objects of radar detection, measurement, and recognition. Doppler radars are used to obtain necessary information for weather forecasts and aviation safety. One of the most important is information about the turbulence intensity in clouds and precipitation. This information is contained in the spectra of echo-signal. Echo-signal is formed during the interaction of returns from the scatterers, which are located in the radar resolution volume. These scatterers participate in several motions, and one of them is caused by turbulence. Sometimes it is possible to distinguish the turbulent component of the motion among other ones by using a special mode of sounding, particularly at horizontal sounding. However, the retrieval of information about the turbulence intensity is a complicated problem in the general case [1]. Some new possibilities of retrieving turbulence intensity in rain using Doppler radar with an arbitrarily directed antenna beam were considered in [2].

Manuscript received May 13, 2004. This work was supported by the Dutch Scientific Fund STW. F. J. Yanovsky is with the Institute of the Information and Diagnostic Systems, National Aviation University, Kiev 03058, Ukraine (e-mail: [email protected]). H. W. J. Russchenberg and C. M. H. Unal are with the Remote Sensing Sector, International Research Centre for Telecommunications and Radar, Delft 2600, The Netherlands (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840772

In this paper, Doppler methods are expanded by Dopplerpolarimetric consideration. Experimental results were obtained with the Transportable Atmospheric Radar (TARA), which is a full-polarization -band FM continuous wave (CW) Doppler radar system [3]. II. DROP VELOCITY DISTRIBUTION AND DOPPLER SPECTRUM Raindrops take part simultaneously in several motions caused by different reasons. This consideration takes into account only two main reasons, which are: 1) gravity and 2) turbulence. Both and turbulence drop fall drop radial velocity distribution were described in [4]. Taking into velocity distribution account that velocity of a raindrop is an algebraic sum of two , the combined distribution , velocities caused by both gravitational falling and turbulence influence, can be determined by the convolution (1) with as the maximal possible drop velocity caused by turbulence. The probability distribution of drop velocity caused by both reasons is (2)

and into (1) Substituting the expressions of and (2), the drop velocity distribution can be calculated at a different eddy dissipation rate , antenna elevation , parameters of gamma model of dropsize distribuand , and turbulence maximal scale . An example tion of calculation is shown in Fig. 1 in the Marshall–Palmer case for light ( cm s , dashed line) and heavy ( cm s , solid line) turbulence at two modes of sounding, and i.e., the antenna is pointed toward the zenith . The rest of the paramthe antenna elevation equals mm, m). The curves eters are constant ( at are located to the right-hand side of the curves at because the radial drop fall velocity is maximum when the antenna is pointed toward the zenith. The curves that correspond to heavy turbulence are significantly broader than the ones for light turbulence. The value of the broadening due to turbulence is more apparent at small elevation angles than at large elevation angles . More positive velocities (toward the radar) are seen at the sounding into the zenith,

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Fig. 1. Radial drop velocity probability distribution at different values of turbulence intensity " and antenna elevation  . Fig. 2. Spectral differential reflectivity at different turbulence intensity ".

and more negative (away from the radar) velocities can occur at heavy turbulence. is the radial drop velocity distribution Doppler spectrum caused by both gravity and turbulence weighted by radar cross , i.e., section (RCS)

[7], the In contrast to well-known differential reflectivity is a function of velocity. spectral differential reflectivity for polarization, where , Doppler spectrum ; , can be determined as

(3)

It can be measured by Doppler radar and used for the retrieval of important information on microstructure and dynamics of rain. In particular, Doppler spectrum width increases when turbulence intensity increases. No suppositions concerning particle shape were made when (3) was derived. Hence, polarization cannot be taken into account at such consideration.

(5) where is drop velocity distribution due to both gravity and , RCS can be calculated acturbulence. In case cording to

III. SPECTRAL DIFFERENTIAL REFLECTIVITY In recent years, a new Doppler-polarimetric technique was developed [5], [6], i.e., the spectral differential reflectivity . With this technique, polarization radar measurements are combined with Doppler measurements in such a way that, for a volume of radar scatterers, the specific polarization properties for targets with different velocities can be determined. The technique comprises the following two steps. Step 1) The Doppler-velocity spectrum of a signal coming from the radar target is calculated at different polarizations. Step 2) For each velocity class in the spectrum, the ratio of the signal power at two different polarizations is calculated. and vertically Usually, the ratio of horizontally polarized returns is measured as (4) denotes the estimate of the value in angle brackets; and are Doppler spectra at polarization indicated by indexes (the first index denotes polarization of a received signal component and the second one denotes polarization of a transmitted wave). where

(6) with as the radar wavelength, as the equivolumetric diamas eter of a sphere, as the relative permittivity, and the term that represents the shape of the particle (quantified with ); takes into account the orientation ( , ) of the particle and the radar elevation angle . The functions and were explained in [8]. The upper limit of inshould be chosen as if tegration in (5) , where is a spatial scale below which [4]. turbulence does not affect raindrops of a certain size Otherwise it should be calculated as an inverse function from at . This helps to take into account the inis the biggest raindrop diameter (usually ertia of drops. mm). Spectral differential reflectivity curves calculated by substiare tuting (5) into shown in Fig. 2 as functions of Doppler velocity at different turbulence intensity and invariably other parameters of the model, , mm, , and cm. particularly Raindrops can be different by size. Bigger droplets are more oblate, and they also fall faster than smaller ones. In general, will one can say that if scatterers become more oblate, increase as well.

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Fig. 2 shows this behavior clearly, especially at negligible cm s . The behavior changes in case of turbulence turbulence intensity increases: raindrops that would otherwise fall with a different velocity may get the same speed because of the turbulence-induced random mixing. This also implies that particles with different shapes are mixed now and may get the same fall velocity, thereby effec. At small fall velocities, tively changing goes up, and at large velocities, it goes down. The curve will flatten with the increased intensity of turbulence.

IV. DOPPLER APPROACHES TO RETRIEVE TURBULENCE INTENSITY Several possibilities exist to measure turbulence by Doppler radar. The first way is the retrieval of turbulence contribution from the Doppler spectrum width . At ground-based radar, remote sensing of rain with a rather narrow antenna beam at comparatively short (less than 10 km) distances, the main contributions are the variance of drop to the Doppler spectrum variance and turbulence . That is why the profall velocities posed simple algorithm provides the following key steps. as a paramStep 1) Estimate median drop diameter eter of dropsize distribution (for each resolution volume) by using radar measurements of, e.g., radar or/and differential reflectivity reflectivity [1], [7]. Step 2) Make some assumption about spread parameter of dropsize distribution , retrieve raindrop fall veusing the locity distribution developed models [4], [5]. (denoted ) as the Step 3) Calculate the variance of second central moment of . Step 4) Estimate the velocity variance due to turbulence , assuming , where is the estimated variance of the measured Doppler spectrum. Step 5) Calculate eddy dissipation rate as a function of (taking into account the scale of turbulence). In this case, we use information only about small-scale turbulence (less than radar resolution). However, assuming homogeneous isotropic turbulence, one can calculate from such data the rms of turbulent motion of air at any maximum spatial scale in the limits of the turbulence inertial interval. The second way is the retrieval of turbulence information changes. We can try from spatial mean Doppler velocity to detect turbulent zones from the same data by comparing in contiguous resolution volumes if the radar data are obtained with good resolution. The profiles of being calculated from nonaveraged Doppler spectra can probably indicate the places of spatial mean velocity changes since the behavior of differences and can indicate the intensity of turbulence between of the appropriate spatial scale. In this case, we get information about turbulence, the scale of which is more than radar spatial resolution since the minimum scale is defined by the distance between the resolution volumes

Fig. 3. Normalized drop fall velocity distribution at different: (a) (b) heights.

D

and

with mean Doppler velocity and . In fact, large gradient of indicates turbulence. The third way comprises the retrieval of turbulence information from temporal mean Doppler velocity changes. For this purpose, a large number of profiles of the same path is necessary. In this case, the scale of spatial averaging can be limited by radar resolution. Let us consider the retrieval of turbulence contribution from the Doppler spectrum width employing radar reflectivity . Such an estimation can use the drop fall velocity distribution, which is derived from gamma dropsize distribution. The varican be calculated more accurately taking into account ance the drop fall velocity dependence on height . We approximate , where is the drop fall it as velocity at sea level. Under these conditions, the normalized drop fall velocity distribution is shown in Fig. 3 at different (left-hand side) and heights (right-hand side). The median drop diameter is difficult to measure. However, a rough estimate can be easily achieved using radar measurements. We suppose that the common reflectivity

YANOVSKY et al.: RETRIEVAL OF INFORMATION ABOUT TURBULENCE IN RAIN BY USING DOPPLER-POLARIMETRIC RADAR

" and

Fig. 4. Procedure for extracting turbulence contribution  from measured Doppler spectrum width [W = (Doppler spectrum width) ].

Fig. 5. Slope

empirical relation between and rain rate is true: with and . The rain rate is

parameters like rain intensity and the eddy dissipation rate of turbulence (Fig. 2). This gives the possibility relating Doppler-polarimetric parameters with parameters of turbulence. curve (or its other paSpecifically, the slope of the rameters) contains information about turbulence. Fig. 5 shows an example of the relationship between turbulence eddy discalculated by using the sipation rate and the Slope modeled data [accordingly to (5) and (6)] with linear interpolation of the intermediate points. leads to the interesting The described behavior of option to remotely measure the intensity of turbulence with Doppler-polarimetric weather radar. However, the research based on experimental data should first be done to confirm the theory.

(7) where is the volume of the drop of diameter , is the steady drop fall velocity, and is the , dropsize distribution. In the Marshall–Palmer case . General formula (7) after the unit transformation and analytical integration using Atlas’ approxiis reduced to mation [1]

Modeled relationship between turbulence intensity given by .

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Z

VI. MEASUREMENTS

(8) where is a function of and . Equation (8) is valid for the integer only. Due to dependence on being rather weak, it can be simpli. fied by substitution of Numerical solving shows that, finally, simple empirical deand may be used. pendence between Now we have all necessary formulas to extract turbulence contribution from measured Doppler spectrum width. The methodology is clearly demonstrated in Fig. 4 as a calculation procedure, which uses measured reflectivity , height , and Doppler velocity variance . , In accordance with this procedure, having estimates of , and , we can calculate drop fall velocity distribution , of drop fall velocity, and then the contribution of variance to the measured variance of Doppler velocity turbulence as a difference . Finally, the estimate of the Doppler spectrum width caused by turbulence is . V. DOPPLER-POLARIMETRIC APPROACH TO RETRIEVE TURBULENCE INTENSITY The developed forward model calculates Doppler spectra curves at given input at different polarizations and

Here, both Doppler and Doppler-polarimetric approaches are checked by using data. The data of rain observation were acquired September 19, 2001 by the FM CW TARA radar system [3], Cabauw, The Netherlands. Basic specifications of TARA are: 1) carrier frequency 3.315 GHz; 2) frequency sweep can be changed from 2- to 50-MHz computer controlled (that corresponds to range resolution from 75 to 3 m); 3) dynamic range 90 dB; 4) receiver noise figure is equal 1 dB; and 5) antenna pa30 dB, first rameters: beamwidth 2.2 , cross polarization 25 dB. During the measurements of rain, the sidelobe level range resolution was set to 15 m and the Doppler velocity resolution was set to 1.8 cm/s. Radar data were processed using MATLAB. Fig. 6 shows 13 profiles of Doppler spectrum width components obtained at the of widespread rain. slant sounding In the upper panel of Fig. 6, the measured Doppler velocity (in meters/second) versus height (in mespectrum width ters) is presented, the middle panel of Fig. 6 shows the retrieved , and the lower panel contribution of the drop fall velocity of Fig. 6 demonstrates the result of the retrieval of turbulence in accordance with the algorithm given in contribution Fig. 4. The developed approach allows experimentally estimating to the Doppler spectrum width the turbulent contribution . This is an estimate of rms turbulent velocity inside the resolution volume, i.e., turbulent velocities of spatial scales less . than

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Fig. 6. Measured profiles of the Doppler spectrum width (DS width), drop fall velocity distribution width (DFVD width), and retrieved turbulent drop velocity distribution width (TDVD width).

Another estimation of turbulence was obtained from the time fluctuations of mean Doppler velocity . In this case, the resolution volume is considered as a point, and only turbulent eddies whose size is bigger than radar resolution affect the mean Doppler velocity. This means that the rms of the mean Doppler velocity is an estimate of turbulence of spatial scales more than m. The universal parameter of turbulence intensity is eddy dissipation rate . Theoretically, in the inertial sub-range of turbulence, the value should be constant. In that case, it can be unambiguously determined from the rms of turbulence velocity at the given spatial scale. Different approaches for retrieval can be applied. We used a simple formula as from value follows, which was given in [1]:

Fig. 7. Slope of Z (v) (upper panel) and Doppler spectrum width (lower panel) versus time and space. Note their negative correlation.



(9) is a dimensionless factor of the order of one in the where Kolmogorov–Obukhov law of isotropic turbulence (minus 5 3 law), is a range from radar to the resolution volume, and is a beamwidth. From (9), the value can be calculated using retrieved turbu. Equalence contribution to the Doppler spectrum width tion (9) does not contain a range resolution term , though, in the strict sense, it should affect. Evidently, (9) was obtained [1] for the operational Doppler weather radar system where nor. For a flexible radar system like TARA, when mally radar range resolution is very high m , the tangential and radial sizes of the resolution volume become equal only between the radar antenna and a target is when the distance m. Thus, (9) is valid for . For the cases when , a more complicated expression should be used. Doppler-polarimetric observable variables are shown in Fig. 7 as grayscale spectrograms in “height–time” coordinates. is bigger in upper heights, while Note that Slope values of are the smallest there. Evident layer structure of the space draws attention, especially the line at approximately . 800 m with increased turbulence and decreased Slope Generally, one can see that behavior of slope of curves is opposite to the behavior of .

Fig. 8. Comparison of different measures of turbulence.

The same conclusion can be done when considering the meafulfilled simultaneously with estisurements of Slope , rms mean Doppler mates of the eddy dissipation rate , . It is invelocity, or spatial gradient mean Doppler velocity teresting to note that behaviors of Doppler parameters that were and ; measured at different polarizations ( and ) are very similar, and it is questionable to expect that joint estimates of them can significantly increase the reliability of turbulence detection or measuring intensity of turbulence. At the same time, the new Doppler-polarimetric variable , and particularly parameter Slope , is very promising because it provides an independent estimate of turbulence-related variable. Comparison of different measures of turbulence is given in Fig. 8. The solid curve is the rms of mean Doppler velocity that is a measure of turbulence, the scales of which are more than . The dotted curve represents Doppler spectrum width . The dashed curve shows retrieved contribution of turbuas a component of measured . lence is a measure of turbulence the scales of which are Value less than . Both values and were measured at horizontal

YANOVSKY et al.: RETRIEVAL OF INFORMATION ABOUT TURBULENCE IN RAIN BY USING DOPPLER-POLARIMETRIC RADAR

Fig. 9. Vertical profiles of the spatial gradient of mean Doppler velocity (dashed line), rms of the time variations of mean Doppler velocity (solid line), and retrieved eddy dissipation rate of turbulence.

polarization, but vertically polarized waves lead to very similar results. are similar, and it is reThe behaviors of rms and markable because they represent the results of independent measures of turbulence (inside and outside radar resolution volume). The last two curves in Fig. 8, marked by dots and crosses, and retrieved eddy dissipation represent measured Slope rate correspondingly. The changes of the Doppler-polarimetric variable Slope on average are opposite to other characteristics, as was predicted theoretically (Fig. 5). The values of parameter that characterizes turbulence intensity and was retrieved by the algorithm, given in Fig. 4, were divided by ten in order to be plotted in a convenient scale. The values of indicate light turbulence in the measured rain, and turbulence is stronger in the surface layer. It has a maximum at approximately 800 m. , rms , Slope , , All considered parameters and were measured or calculated by using the time variations in each radar resolution volume. They can be referred to the first or third way of turbulence measuring (see above). The possibility to retrieve turbulence information from changes of spatial was indicated above as the second mean Doppler velocity way, and the results of corresponding measurements are shown in Fig. 9. The dashed line represents the absolute values of spatial calculated over all range bins in the rain gradient zone. rms (solid line) and (dotted line) lines are shown for comparison. One can see very nice correspondence between the measurements in the time and spatial domains. VII. CONCLUSION New techniques for turbulence information retrieval from the measurements of Doppler and Doppler-polarimetric radars have been developed. The developed procedure for the retrieval of turbulence component from the total Doppler spectrum width can be

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successfully used for measuring the intensity of turbulence in rain by Doppler radar. Further improvement of this method can be achieved by increasing the accuracy of median drop . This can be done by using polarimetric diameter estimate measurements additionally to Doppler, differential reflectivity instead of or together with reflectivity can particularly be used. However, a real Doppler-polarimetric approach is not a simple combination of Doppler and polarimetric parameters. New Doppler-polarimetric variables can be introduced providing new possibilities. One of them is spectral differential and its parameter Slope . reflectivity Theoretical investigation, modeling, and data processing have is correlated to turbulence in clearly demonstrated that rain. This leads to the interesting option to remotely measure the intensity of turbulence with Doppler-polarimetric radar. The fulfilled processing of real data by using different Doppler approaches and the new Doppler-polarimetric approach has demonstrated well-correlated results. Application of independent turbulence-related radar variables can improve the reliability and accuracy of radar measurements. Measurements of microstructure and dynamic parameters of weather objects by Doppler-polarimetric radar can be very useful to solve wave propagation problems for the tasks of microwave communications and the radar’s ability to detect targets embedded in a high-clutter background. ACKNOWLEDGMENT The main volume of data for this paper was processed during the Doppler-Polarimetric Radar Observations of Turbulence in Rain (09.2002–03.2003) project in the framework of long-term cooperation between the International Research Centre for Telecommunications and Radar (IRCTR), Delft, The Netherlands, the Technical University of Delft, Delft, The Netherlands, and the National Aviation University (NAU), Kiev, Ukraine. REFERENCES [1] R. J. Doviak and D. S. Zrnic, Doppler Radar and Weather Observations, 2nd ed. San Diego, CA: Academic, 1993. [2] F. J. Yanovsky, “Doppler radar: Retrieval of information about turbulence in rain,” in 15th Int. Microwaves, Radar and Wireless Communications Conf., Warsaw, Poland, May 2004, pp. 86–91. [3] S. H. Heijnen and L. P. Ligthart, “TARA: Development of a new Transportable Atmospheric Radar,” in 5th Int. Radar Systems Conf., Brest, France, May 1999, pp. 223–226. [4] F. J. Yanovsky, H. W. J. Russchenberg, and L. P. Ligthart, “Doppler-polarimetric models of microwave remote sensing of rain,” in 11th Microwave Technique Conf., Pardubice, Czech Republic, Sep. 2001, pp. 47–62. [5] C. M. H. Unal, D. N. Moisseev, F. J. Yanovsky, and H. W. J. Russchenberg, “Radar Doppler polarimetry applied to precipitation measurements: Introduction of the spectral differential reflectivity,” in 30th Int. American Meteorological Soc. Radar Meteorology Conf., Munich, Germany, Jul. 2001, pp. 316–318. [6] F. J. Yanovsky, “Phenomenological models of Doppler-polarimetric microwave remote sensing of clouds and precipitation,” in IEEE Int. Geoscience and Remote Sensing Symp., vol. 3, Toronto, ON, Canada, Jun. 2002, pp. 1905–1907. [7] V. N. Bringi and V. Chandrasekar, Polarimetric Doppler Weather Radar. Cambridge, U.K.: Cambridge Univ. Press, 2002. [8] D. A. De Wolf, H. W. J. Russchenberg, and L. P. Ligthart, “Effective permittivity of and scattering from wet snow and ice droplets at weather radar wavelengths,” IEEE Trans. Antennas Propag., vol. 38, no. 9, pp. 1317–1325, Sep. 1990.

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Felix J. Yanovsky (M’94–SM’96) received the Engineer (M.S.) and D.Sc. degrees from the National Aviation University (NAU), Kiev, Ukraine, in 1968 and 1992, respectively, and the Ph.D. and D.Sc. degrees from the Moscow State Technical University (MSTUCA), Moscow, Russia, in 1979 and 1993, respectively. He is currently a Full Professor with the Institute of the Information and Diagnostic Systems, NAU, and a Guest Top Scientist with the Delft University of Technology, Delft, The Netherlands. His research interests are radar and remote sensing, Doppler polarimetry, signal processing, math modeling, and multiparametric and adaptive methods. He introduced significantly to airborne weather radar theory and practice and was one of the initiators of air-traffic collision-avoidance system development in the Ukraine. He has authored or coauthored over 300 scientific papers and six books. He holds 38 patents. He appears in Who’s Who in the World. Dr. Yanovsky is a member of the General Assembly (GA) of the European Microwave Association. He served as a section organizer, chairman, and Technical Program Committee (TPC) member of numerous International Conferences. He was elected as an Academician of the Transport Academy of Ukraine, International Academy of Navigation and Traffic Control, St. Petersburg, Russia, and Electromagnetics Academy, Cambridge, MA. He was the recipient of the State Award of the Ukraine in the field of science and engineering in 1996.

Herman W. J. Russchenberg is Head of the Remote Sensing Sector, International Research Centre for Telecommunications and Radar, Delft, The Netherlands. He possesses extensive experience in remote sensing of clouds and precipitation with ground-based radar, lidar, and microwave radiometry, and is one of the initiators of this work in The Netherlands. He is experienced in theoretical, as well experimental research of the scattering process and the retrieval of geophysical parameters from radar and lidar measurements. He has performed several studies for the European Space Agency (ESA), dealing with radar observations of clouds and precipitation. He is the initiator of the Cabauw Experimental Site for Atmospheric Research.

Christine M. H. Unal received the D.E.A. degree in physics for remote sensing from the University of Paris, Paris, France, in 1987. In 1988, she joined the Delft University of Technology, Delft, The Netherlands, where she is currently a Research Scientist. She possesses experience with radar polarimetric calibration and radar Doppler polarimetry (quasi-simultaneous Doppler spectra of polarimetric measurements, their processing, and their interpretation). Since 2003, her research has focused on radar Doppler polarimetry applied to atmospheric targets.

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Guest Editorial

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HIS TRANSACTIONS contains the 2004 Mini-Special Issue on the 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. The symposium was held 6–8 June 2004, Fort Worth, TX. This Mini-Special Issue features papers expanded from those presented at the 2004 RFIC Symposium, covering the latest innovations and advancements in RFIC technology targeting wireless and communications applications. The symposium saw continued growth with a record number of manuscript submissions. Additionally, a record number of manuscripts were expanded and submitted for consideration to this TRANSACTIONS. As such, this Mini-Special Issue has been expanded from previous years to accommodate 20 manuscripts and necessitated moving the Mini-Special Issue from November 2004 to February 2005. These papers cover a broad range of topics and provide a sample flavor of those presented at the symposium. Within this Mini-Special Issue, for example, you will find advancements reported in developing highly integrated circuits (ICs) in support of cellular and wireless applications. Advancements are shown in a direct conversion receiver with an integrated synthesizer using 0.35- m BiCMOS technology, as well as in the area of a low-power highly digitized receiver at 2.4 GHz. Research is reported using

SiGe HBT device technology to improve the efficiency/linearity tradeoff for wide-band code-division multiple-access (WCDMA) handset power amplifiers. Another paper discusses the application of applying digital pre-distortion in an enhanced data for global system for mobile evolution (EDGE) environment. The remaining pages focus on other aspects of RFIC technology, including efforts related to optical system ICs, frequency synthesizers, mixers, voltage-controlled oscillators (VCOs), low-noise amplifiers (LNAs), device technology, and modeling and simulation. I hope you enjoy reading this TRANSACTIONS’ Mini-Special Issue. I also invite you to join us in June 2005 at Long Beach, CA, for the 2005 IEEE RFIC Symposium, which promises to showcase the latest RFIC advancements and innovations. I want to also take this opportunity to thank each author for submitting their papers to this Mini-Special Issue, without whose efforts this TRANSACTIONS would not be possible. In addition, I want to thank the reviewers who gave so freely of their time and expertise. Lastly, I would like to thank Joseph Staudinger (previous guest editor) and this TRANSACTIONS’ Editor-in-Chief, Prof. Michael B. Steer, for their valuable support and guidance in this effort. The reviewers for this TRANSACTIONS’s Mini-Special Issue are as follows.

Digital Object Identifier 10.1109/TMTT.2004.840782

List of Reviewers Kashif Ahmed Walid Ali-Ahmad Kirk Ashby Seiichi Banba Scott Barker Luciano Boglione Natalino Camilleri Sudipto Chakraborty Thomas Cho David Choi Yann Deval Stephen Dow Charles Dozier Frank Ellinger Werner Geppert Aditya Gupta

Andre Hanke Olin Hartin James Haslett Gamal Hegazi Rashaunda Henderson Darrell Hill Song Hong Albert Jerng Marion Kazimierczuk Sayfe Kiaei Woonyun Kim Kursad Kiziloglu Kevin Kobayashi Kevin Kornegay Bill Kuhn Mahesh Kumar

U. Langmann Jenshan Lin Louis Liu David Lovelace Shey-Shi Lu Kevin McCarthy Charles Meng Mel Miller Jyoti Mondal Mohamed Mostafa Vijay Nair Tadao Nakagawa David Ngo Dan Nobbe Jeffrey Ou Allen Podell

Bill Redman-White Francis Rotella Gary Sadowniczak Franco Sechi Phillip Smith Joseph Staudinger Noriharu Suematsu Bruce Thompson Iason Vassiliou Zhi-Gong Wang Alan Westwick Ke Wu Hong Zhong Xu

TINA QUACH, Guest Editor Freescale Semiconductor Inc. Tempe, AZ 85284 USA 0018-9480/$20.00 © 2005 IEEE

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Tina Quach (M’94) received the B.S.E.E. degree from the University of California at San Diego, La Jolla, in 1989, and the M.S.E.E. degree from Arizona State University, Tempe, in 1999. She is currently a Principal Staff Engineer with Freescale Semiconductor, Tempe, AZ. Her interests are primarily in the area of power-amplifier circuits and technology for mobile communications. Ms. Quach has held various positions within the IEEE RFIC Technical Program and Steering Committees since 2000.

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A Low-Power Highly Digitized Receiver for 2.4-GHz-Band GFSK Applications Henk Jan Bergveld, Kees M. M. van Kaam, Domine M. W. Leenaerts, Senior Member, IEEE, Kathleen J. P. Philips, Member, IEEE, Ad W. P. Vaassen, and Gunnar Wetkzer, Member, IEEE

Abstract—This paper describes the design and measurement results of a low-power highly digitized receiver for Gaussian frequency-shift keying modulated input signals at 2.4 GHz. The RF front-end has been based on a low-IF architecture and does not require any variable gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a analog-to-digital low-power high-resolution time-continuous converter (ADC). This leads to a linear receive chain without limiters. A fifth-order poly-phase loop filter is used in the complex ADC. The digital block performs filtering and demodulation. Channel filtering is combined with matched filtering and ADC. The high the suppression of noise resulting from the degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18- m CMOS process and measures 3.5 mm2 . The only external components are an antenna filter and a crystal. The power consumption is only 32 mW in the continuous mode, which is at least a factor of two lower than state-of-the-art CMOS receivers.

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Index Terms—CMOS integrated circuits (ICs), demodulation, digital signal processors, sigma–delta modulation, UHF receivers.

I. INTRODUCTION

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EVERAL standards for low-cost short-distance wireless systems are emerging, such as Bluetooth, IEEE802.11x, and Zigbee. In addition to low cost, low power is also important for the portable devices implementing these standards. Low cost is achieved by minimizing the number of external components for the transceiver integrated circuit (IC) and by using a standard baseline IC process technology. The size of the digital hardware, forming a considerable part of the transceiver IC, scales down for newer CMOS generations. Therefore, full integration in CMOS becomes interesting. Low power is influenced by the chosen architecture. Architectures using limiters are commonly considered for low power, but lack flexibility. As the available bandwidth is limited, new standards for higher data rates will require the use of nonconstant envelope modulation techniques. A highly digitized architecture offers flexibility at low power. Several transceivers realized in CMOS and aimed at Bluetooth/Gaussian frequency-shift keying (GFSK) applications

Manuscript received April 27, 2004. H. J. Bergveld, K. M. M. van Kaam, D. M. W. Leenaerts, K. J. P. Philips, and G. Wetzker are with Philips Research Laboratories, 5656AA Eindhoven, The Netherlands (e-mail: [email protected]). A. W. P. Vaassen was with Philips Research Laboratories, 5656AA Eindhoven, The Netherlands. He is now with Philips Semiconductors, 5656 AA Eindhoven, The Netherlands. Digital Object Identifier 10.1109/TMTT.2004.840756

have been reported in the literature [1]–[5]. Most referenced transceivers have been realized in 0.18- m CMOS, whereas the Bluetooth receiver revealed in [5] has been realized in 0.13- m CMOS. All cited references report power consumptions for the receiver part of over 60 mW. Most receiver architectures use a limiter, after which demodulation takes place based on zero-crossing detection [1], [3], [4]. Although suitable for GFSK applications, the disadvantage of such nonlinear receivers is that the concept is not applicable to nonconstant envelope modulation. The concept presented in [2] uses a linear receiver, where digitization of the IF signal is performed using a variable-gain amplifier (VGA), an eighth-order filter, and a 6-bit ADC. This enables digital demodulation, but this has not been included in the presented silicon. The receiver architecture presented in [5] is also linear and performs demodulation in the digital domain. Discrete-time analog signal processing is applied at the input involving RF sampling with an all-digital phase-locked loop (PLL) using a digitally controlled oscillator. A considerable amount of filtering and variable-gain control occurs in the signal path before the analog-to-digital converter (ADC). The Bluetooth specifications are met with a considerable margin, but the power consumption is still relatively high. The receiver architecture presented in this paper aims at a high level of integration, low power consumption, and a high degree of digitization [6]. Removing all analog filtering and VGA in the front-end significantly reduces the design complexity and power consumption of the RF part. Instead, channel filtering and demodulation take place in the digital domain with the advantages of flexibility with respect to changing standards and lower power consumption and chip area for newer CMOS generations. Moreover, the receiver chain is linear, which enables using the same architecture for future systems with nonconstant envelope modulation. The concept does place tough requirements on the design of the ADC. In order to verify our concept, an IC has been designed in 0.18- m CMOS for applications in the 2.4-GHz industrial–scientific–medical (ISM) band with GFSK-modulated input signals. Specifications have been derived from the Bluetooth standard. The architecture is described in Section II. Section III highlights important design issues of the analog front-end and Section IV describes the design of the digital filter and demodulator. Top-level design issues are described in Section V and measurement results are discussed in Section VI. Finally, conclusions are drawn in Section VII.

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Fig. 2. Schematic and basic BPF/impedance-matching network.

design

equations

for

the

Fig. 1. Simplified block diagram of the receiver.

II. RECEIVER ARCHITECTURE A. Block Diagram A simplified block diagram of the receiver is shown in Fig. 1. An external bandpass filter (BPF) selects the 2.4-GHz band and performs impedance matching. Two matched low-noise amplifiers (LNAs) are used in parallel to provide sufficient isolation between the in-phase (I) and quadrature (Q) channels after the mixers. The LNAs have been implemented as V–I converters. The RF output current is down-converted to a low IF of 500 kHz by passive mixers, driven directly by a quadrature voltage-controlled oscillator (VCO) in a PLL. A high-resolution complex ADC converts the quadrature IF currents into noise-shaped I and Q bit streams. The digital block performs channel and decimation filtering, as well as demodulation.

B. Derivation of the Main Specifications The noise figure (NF) of the analog front-end has been based on the 70-dBm sensitivity specification in 1-MHz bandwidth of the Bluetooth standard. The thermal noise power in 1-MHz or 114 dBm bandwidth at the receiver input equals MHz, assuming a perfect match between antenna with impedance and LNA input impedance. A signal-to-noise ratio (SNR) of 18 dB is needed at the demodulator input to properly demodulate an input signal with a bit error rate (BER) of 0.1%. Taking into account a 2-dB margin, the NF of the analog front-end must be less than 24 dB. When the noise of the RF front-end is made dominant, the design of the ADC becomes very difficult and vice versa. Therefore, equal noise contributions of the RF front-end and the ADC have been adopted as a best compromise with respect to design complexity of the RF front-end and ADC. This leads to an NF requirement for the RF front-end of 21 dB, which should be relatively easy to achieve. With a maximum input power of 20 dBm based on Bluetooth, the required dynamic range (DR) of the ADC becomes 73 dB. The linearity and interference specifications of the front-end have also been based on Bluetooth. This implies a specified third-order input-referred interception point (IIP3) of 21 dBm.

Fig. 3.

Circuit schematic of the LNA/mixer combination.

III. DESIGN OF THE ANALOG FRONT-END A. BPF/Impedance-Matching Network The schematic and basic design equations of the BPF/impedance-matching network are shown in Fig. 2. The filter comprises an LC tank tuned to the Bluetooth band from 2.4 to 2.5 GHz with capacitive tapping to achieve voltage multiplication and impedance matching. The filter has been designed such that the differential antenna impedance of , seen at the output of the filter , matches the 150 LNA input impedance of 1350 . For the current version of the IC, an external filter has been used with pF nH at 2.4 GHz. The approach has been chosen and to be able to integrate this filter, enabling tuning by adding switchable MOS capacitors to the circuit. However, this has not yet been implemented on the current version of the IC. B. LNA/Mixer Combination A circuit schematic of the LNA/mixer combination is shown in Fig. 3. The LNA is a simple differential pair providing voltage-to-current conversion. The ADC has been designed such that it can handle the entire DR. Therefore, the LNA just acts as a buffer and driver toward the mixer. The receive chain has been dimensioned such that for a maximum input signal of 20 dBm at the antenna, the differential output current of . This is achieved the LNA/mixer combination is 50 A with a transconductance for the LNA of 0.6 mA/V. When this full-scale (FS) input current is applied to the ADC, a digital output signal corresponding to digital FS minus 3 dB results, i.e., a bit stream of all ones. The LNA should also provide isolation between the I and Q paths. This can be obtained by using cascode techniques, leading to a reduced output voltage range. We have chosen to use two LNAs, leading to optimum isolation at the cost of higher power consumption. However, as the LNAs have been designed

BERGVELD et al.: LOW-POWER HIGHLY DIGITIZED RECEIVER FOR 2.4-GHz-BAND GFSK APPLICATIONS

Fig. 4. Block diagram of the quadrature VCO and circuit schematic of the oscillator core.

Fig. 5. Placing an additional zero (90 phase shift) in the couplings of the I and Q paths in Fig. 4. A similar technique is needed for VCO2.

to function at much lower power than the other front-end blocks, this becomes less of an issue. Passive mixers are used at a common-mode voltage of 0.8 V and a nonoverlapping clock scheme has been implemented in order to reduce distortion and noise. Therefore, the dc level of the VCO output that is directly driving the mixer has been set to 1.4 V, i.e., at least a threshold voltage above the common-mode voltage. C. VCO and PLL The VCO has been designed to provide a large output voltage swing of 1 differential to enable direct drive of the mixers. A quadrature VCO has been realized by cross-coupling two identical oscillator cores, as indicated in Fig. 4 [7]. The tank circuit in each core has been built up around two inductors of 2.2 nH each with a measured quality factor of 10 at 2.45 GHz and with a resonance frequency of 9 GHz. The tunable capacitance has been realized with two identical nMOS devices. VCO2 is connected to VCO1 in antiphase in Fig. 4, while VCO1 is connected to VCO2 in common phase. This implies a 180 phase shift from the VCO2 output to the VCO1 input, forcing a 90 phase shift in each core, where a 0 phase shift is preferable for optimum phase-noise performance. Therefore, an additional zero has been introduced in each coupling in the form of a common-source amplifier with a capacitor , introducing a 90 phase shift between gate voltage and drain current (see Fig. 5) [7]. This brings the oscillator-core phase shift back to the optimum value of zero. A similar coupling is used to connect VCO2 to VCO1. Analog tuning with the tunable capacitance results in 200 MHz or 8% tuning range. This is enough to cover the

455

Fig. 6. Use of two 32-MOS capacitor banks to enable digital tuning of the VCO center frequency to deal with process spread.

Bluetooth band, but not enough to cover process spread as well. Increasing the analog tuning range to cover process spread is not preferable since it leads to a higher VCO gain in the PLL loop and, hence, increased sensitivity to noise on the VCO tuning input. Therefore, digital tuning using a 32-MOS capacitor bank on each side of each core is used to cope with process spread. This is indicated in Fig. 6. The individual capacitors are turned ON or OFF by applying a control voltage of either zero or the supply voltage to the drain/source connections of the MOSFETs using a 5-bit digital-code word and a thermometer decoder block. The digital tuning is used to set the VCO to the proper center frequency at startup. The VCO has been included in a PLL using a multimodulus divider and a reference frequency of 500 kHz derived from a 64-MHz clock signal generated by an on-chip third-overtone crystal oscillator [7]. Analog tuning is applied in a synthesizer loop (PLL) to lock the VCO at various channel frequencies. Combined analog and digital tuning leads to a measured total tuning range of 400 MHz or 16%. The phase noise at 3 MHz offset has been measured at 120 dBc/Hz. For digital code word 15, i.e., halfway the digital tuning range, the Bluetooth band is completely covered by the analog tuning range of the PLL [7]. D. Continuous-Time

ADC

No analog filters or VGA are present in the architecture of Fig. 1. By consequence, the ADC needs to handle the entire signal DR and must be immune to interferer channels over the entire Bluetooth band. The signal bandwidth from 0 to 1 MHz can, in principle, be converted into the digital domain ADCs processing the I and using two identical low-pass Q channels separately. The transfer function of both ADCs is symmetrical with respect to dc in this case, leading to the same resolution as from 0 Hz to 1 MHz being available from 1 MHz to 0 Hz. Since this is not necessary, we have chosen ADC with quadrature inputs and to use a single complex outputs with a poly-phase loop filter [8]. The fifth-order poly-phase loop filter has been implemented in continuous time, which is advantageous for low power consumption and provides inherent antialiasing filtering. The five notches of this filter can only be placed in the band from 0 to

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Fig. 9.

Fig. 7. Simulated effect on the ADC output spectrum of limited image ADC. rejection due to mismatch between the quadrature parts of the

61

Fig. 8. Block diagram of the fifth-order complex continuous-time

61 ADC.

1 MHz. As the converted bandwidth is halved compared to two ADCs, the effective over-sampling is doubled and efreal ficient bandpass noise shaping around the IF frequency occurs. However, mismatch between the quadrature parts of the ADC will lead to leakage of quantization noise from negative frequencies to the wanted band and, hence, to degradation of the SNR. This is illustrated in Fig. 7, showing the effect of limited image rejection on the simulated output spectrum of a fifth-order ADC. Therefore, one filter notch has been placed at the edge of the image band from 1 MHz to 0 Hz; the remaining four notches being placed in the wanted signal band from 0 to 1 MHz [8]. A detailed discussion on interferer immunity of conADCs and further improvements thereof can tinuous-time be found in [9]. ADC is The block diagram of the complex fifth-order shown in Fig. 8 [8]. Feed-forward branches are used in the loop filter to ensure stability and to ensure graceful degradation in case large input signals are applied. A sampling frequency of 64 MHz is used, leading to a theoretical maximum SNR of 90 dB. The on-chip third-overtone crystal oscillator generates the 64-MHz clock signal. For sufficient linearity of the overall receiver chain, the input impedance of the ADC needs to be low compared to the output impedance of the RF front-end. As can be seen in Fig. 8, an

Block diagram of the digital filter and demodulator.

operational transconductance amplifier in integrating feedback configuration determines the input impedance of the ADC. This provides a virtual-ground summing node, which makes the ADC itself highly linear, preventing intermodulation of interferers from decreasing the resolution in the wanted channel. Moreover, it provides the desired low-ohmic termination of the RF front-end. The differential input impedance is below 400 over the entire Bluetooth band. This specification sets the current consumption of the input stage and dominates the overall consumption. As a consequence, instead of the input stage, the resistive DAC used in the feedback path of the ADC and the second integrator limit the SNR to 79 dB due to thermal noise. A further 3-dB reduction in SNR results from timing jitter present on white noise induced by the 7-ps the 64-MHz clock. This results in a fair distribution of power consumption between crystal oscillator and ADC. ADC inThe measured performance of the standalone cludes a DR of 76 dB and a third-order intermodulation (IM3) distortion below 82 dBc. Applying an FS input signal with a frequency near that of the 64-MHz clock signal causes a folding component in the signal band at 77 dB, which illustrates the antialiasing behavior of the ADC [8]. IV. DIGITAL FILTER AND DEMODULATOR A block diagram of the digital filter and demodulator is shown in Fig. 9. The I and Q output bit streams from the ADC are clocked in at 64 MHz. After filtering and decimation in the cascaded integrator-comb (CIC) filters, the clock frequency in the remainder of the block is 8 MHz. CIC filters have been introduced in [10]. These filters offer good performance and are relatively easy to implement in a short design time. The structure consists of integrator stages in series, followed by a decimation down-sampling of the signal by a factor of , followed by differentiation stages in series. The transfer function of this filter is given by (1) where and have been chosen in the design. These parameters have been chosen such that a reasonable over-sampling factor of eight of the signal is maintained, a high suppression of the aliasing frequency is achieved, and the deformation of the passband remains small. The rotating coordinate rotation digital computing (CORDIC) rotates the complex input signal composed of an I and Q data stream by a given angle , which is provided by the phase input signal [11]. Elementary rotations are combined,

BERGVELD et al.: LOW-POWER HIGHLY DIGITIZED RECEIVER FOR 2.4-GHz-BAND GFSK APPLICATIONS

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Fig. 11. Block schematic of the DFE.

Fig. 10.

Comparison of C (t) and g

t

( ) impulse responses.

each of them realizing a different elementary rotation angle, to realize different rotation angles . This leads to a simple implementation only based on additions and subtractions. The rotating CORDIC shifts the IF frequency of the output signals of the CIC filters from 500 kHz to 0 Hz. The complex GFSK baseband signal present at the output of the rotating CORDIC is represented by (2) where the instantaneous phase

is given by

(3) with denoting the frequency swing of the GFSK-modulated with the modulation index and the signal denoting the data bits (part of the symbol period time), set ) and expressing the impulse response of the combined impulse-shaping and Gaussian filter used to shape the data bits before modulation. It can be proven that this nonlinear representation of the complex GFSK-modulated baseband signal can be rewritten as a series expansion containing a finite number of time-limited amplitude-modulated pulses [12]. Moreover, the signal can be approximated with good accu. The result is racy using only the main impulse response a linear approximation of the complex GFSK-modulated signal given by (4) leads to optimum suppression Using a filter matched to of white noise [13]. Fig. 10 shows that the impulse response is very similar to a pure Gaussian impulse response . The impulse response is only weakly dependent on the modulation index . The advantage of using is that a matched filter defined by impulse response it leads to a simpler implementation since a Gaussian filter would have a somewhat longer impulse response.

The vectorizing CORDIC calculates the phase of the complex signal represented by a Cartesian vector. The CORDIC rotates the given vector in several steps until it meets the -axis. Elementary rotations are used in a similar way as for the rotating CORDIC. As the receive chain is linear, the vectorizing CORDIC can also be used to determine the amplitude of the signal as a future extension to deal with other modulation takes place at the techniques. Phase differentiation output of the vectorizing CORDIC to obtain the instantaneous frequency. The combination of the vectorizing CORDIC and phase differentiation forms a frequency modulation (FM) demodulator. A decision-feedback equalizer (DFE) yields an output bit stream that is eight times over-sampled compared to a 1-Mb/s symbol rate. The DFE is a nonlinear equalizer, which gives better performance in terms of the BER compared to a linear equalizer at only slightly increased complexity [13]. A block diagram of the DFE is shown in Fig. 11. Compared to a standard DFE with a three-tap feed-forward filter (FFF) and a 1-tap feed-back filter (FBF), an additional interference canceller has been added. This leads to a further improvement of the BER performance since only using a standard DFE with optimized coefficient settings for the FFF and FBF does not fully suppress precursive inter-symbol interference (ISI). The implemented three-tap FFF is a finite impulse response (FIR) filter. The input signal of the DFE is an instantaneous frequency. Since the output of the slicer drawn in the middle of Fig. 11 is either 1 or 1, it needs to be translated back into a frequency value. Therefore, the outcome of this slicer is multiplied by 10.18 kHz, the value of which has been obtained from simulations in order to optimize the BER performance of the demodulator. A slicer is also used at the DFE output to obtain the original data bits. Due to differences in crystal frequencies of transmitters and receivers in, for example, a Bluetooth system, a frequency offset will be present in the signal that has to be demodulated. This leads to a dc shift in the differentiator output. Therefore, a frequency-compensation loop including first-order filtering is used. The loop error signal is added to the default frequency shift of 256, i.e., the digital representation of the IF frequency of 500 kHz, and then fed to a numerically controlled oscillator (NCO). This leads to a shift to 0 Hz of the incoming signal by the rotating CORDIC, even in the presence of an offset frequency. The system has been designed to deal with frequency offsets up to 150 kHz.

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TABLE I MEASURED POWER CONSUMPTION OF RECEIVER BLOCKS

Fig. 12.

Die photograph of the receiver test IC.

V. DESIGN OF THE COMPLETE IC The receive chain has been realized in a six-metal-layer 0.18- m standard CMOS process on a 10- cm substrate. The die photograph in Fig. 12 shows a core area of 3.5 mm . The IC has been packaged in a 48-pin low-profile quad flat package (LQFP) plastic package and mounted on an FR-4 board. Apart from supply decoupling capacitances, the only external components needed are an antenna filter/impedance-matching network and a 64-MHz crystal. Several measures have been taken to deal with crosstalk between the digital and analog blocks. The complete analog front-end has been implemented differentially and many substrate contacts connected to a clean analog ground have been used. The pad ring has been cut at two places yielding an analog and a digital pad ring. Finally, a guard ring connected to the positive digital supply voltage has been laid out around the digital block to minimize any generated substrate noise. As an additional means to investigate crosstalk from the digital block to the analog block substrate contacts (“sensors”) have been placed at various locations on the IC and connected to dedicated pads. The same die will also be used in the future to experiment with wafer-scale packaging techniques [14]. An advantage of wafer-scale packaging is the small size of the package, i.e., roughly 3 mm 3 mm, as opposed to the size of the LQFP48 package of 7 mm 7 mm. Moreover, the possibility exists to etch a trench between analog and digital. Substrate “sensors” have been placed on either side of the future trench. This will enable determination of the additional suppression due to the trench of noise generated by the digital block as perceived on the analog side of the IC. VI. MEASUREMENT RESULTS The measured power consumptions of the various blocks in the receiver chain are listed in Table I. The supply voltage for the analog part is 1.8 V, whereas the digital supply voltage is 1.4 V. The total power consumption is 31.7 mW in continuous mode.

Fig. 13. Measured and simulated BER curves versus SNR at the demodulator input. Simulations have been based on an ideal front-end and AWGN channel.

This is at least a factor of two lower than for other reported CMOS receivers with identical functionality [1]–[5]. The measured and simulated behavior of the demodulator are compared in Fig. 13 by plotting the SNR at the demodulator input versus the achieved BER at the demodulator output based on a modulation index of 0.35. The number of samples used in the measurements is 10K. The simulations have been performed with an ideal receiver front-end model for the additive white Gaussian noise (AWGN) channel. The difference in SNR for % is roughly 3 dB, which can be found by extrapolating the measured line. This is caused by nonidealities in the real receiver chain compared to the simple ideal model, e.g., the effect of limited rolloff of the CIC filters that has not been considered in the ideal model used in the simulations. The behavior of the digital demodulator is illustrated in Fig. 14 for Bluetooth channels 0, 48, and 78. Similar behavior occurs for all channels as expected, leading to an extrapolated of 17 dB. Fig. 15 shows the SNR for which BER curve versus RF input power for channel 0. Measurements obtained for 10K and 300K samples have been combined to extend the BER curves to values below 0.001. The RF input power corresponding to an SNR of 17 dB at the output of the ADC and a BER of 0.001, i.e., the sensitivity level, is 71 dBm. The measured DR of the ADC was found to be 76 dB [8]. This leads to an NF of the RF front-end of 25 dB, which is higher than the designed value due to matching problems at the RF input. Modeling inaccuracies at the time of designing the RF input circuits have caused these problems. This will be addressed by

BERGVELD et al.: LOW-POWER HIGHLY DIGITIZED RECEIVER FOR 2.4-GHz-BAND GFSK APPLICATIONS

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Fig. 16. Measured ADC output spectrum for two-tone experiment with 30-dBm input power (channel 48).

0 Fig. 14. Measured BER curves versus SNR at the demodulator input for Bluetooth channels 0, 48, and 78.

Fig. 17. Measured linearity of the receiver chain based on extrapolation of fundamental (slope 1) and IM3 powers (slope 3) (channel 0).

Fig. 15. Measured BER curve versus RF input power using 10K and 300K samples (channel 0).

a redesign of the input circuits using proper models, including the design of an integrated and tunable version of the antenna filter. For the current realization, the maximum input power has been determined at 19 dBm. This leads to a signal range of the receiver chain of 52 dB across the entire band. The linearity of the receiver chain has been determined by offering two tones separated 100 kHz apart in the band of interest. The measured output spectrum of the ADC for a two-tone experiment in channel 48 is depicted in Fig. 16. The fundamental tones at 450 and 550 kHz and the IM3 products at 350 and 650 kHz can be clearly recognized. The RF input powers of dBm. An IIP3 the two tones have been installed at value of 10 dBm can be calculated from the spectrum using [15]. An alternative method to assess the IIP3 is by extrapolation [15]. The result is shown in Fig. 17 for channel 0, revealing an IIP3 value of 11 dBm and a 1-dB compression point of roughly 18 dBm. Additional linearity measurements have been performed according to the Bluetooth specification. A GFSK-modulated signal has been applied at 64 dBm in the wanted channel at

frequency . A static sine wave has been applied at a power level of 39 dBm and frequency , whereas a GFSK-modulated signal with random data has been applied at a power level of 39 dBm at frequency . The relations between these and MHz. frequencies are given by The BER has been determined in the wanted channel based on 300K bits yielding 0.003% in channel 0, 0.005% in channel 48, and 0.01% in channel 78. This means that the BER is indeed lower than 0.1% in all channels, as specified. This can be expected from the IIP3 value of 11 dBm, which is indeed better than the specified value of 21 dBm. The interference behavior has been measured according to the Bluetooth specification based on 10K data bits in the wanted channel and a GFSK-modulated interferer with random data. The results are listed in Table II for channels 0, 48, and 78. For the various interferers at various carrier-to-interferer (C/I) ratios, the BER values are smaller than 0.001, as specified. It should be noted that the co-channel and adjacent channel specifications do not depend on the implementation of the receiver chain. The mirror specifications are dependent on the used IF frequency. Since we use an IF frequency of 500 kHz, the MHz” specification coincides with the co-channel “mirror specification, but is a lot more stringent since a C/I ratio of

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TABLE II MEASURED INTERFERENCE BEHAVIOR

toward new wireless standards, and the scalability of the digital back-end. ACKNOWLEDGMENT

TABLE III PERFORMANCE SUMMARY OF THE RECEIVER CHAIN

The authors wish to acknowledge C. Dijkmans, M. Sousa, B. Theunissen, and C. Vaucher, all of Philips Research Laboratories, Eindhoven, The Netherlands, K. Moore and M. Thompson, both of the S3 Group, Silicon and Software Systems, Dublin, Ireland, and M. Vrouwe, Philips Semiconductors, Eindhoven, The Netherlands, for their support during the design phase of the test IC. The authors further acknowledge I. Bonne and G. Huisman, Philips Semiconductors, Nijmegen, The Netherlands, and D. Jeurissen, Philips Research Laboratories, Eindhoven, The Netherlands, for their support during the measurements. REFERENCES

20 dB should be used. It is allowed to adhere to the most relaxed specification in this case. Therefore, the “mirror+1 MHz” specification has not been listed in Table II. The “mirror-1 MHz” specification coincides with the “adjacent-2 MHz” specification. In principle, the “adjacent-2 MHz” is less relaxed than the “mirror-1 MHz” specification, but since both are easily met, they have both been listed in Table II. The “adjacent 3 MHz” and mirror specifications are met only with a small margin in applicable C/I ratio. The measured behavior and main characteristics of the receiver chain have been summarized in Table III. It can be concluded that all measured specifications comply with the Bluetooth standard. This means that apparently the crosstalk between the digital block and analog blocks is not a problem. This has been confirmed by measurements at the substrate “sensors” located inside the region labeled “Analog block” in Fig. 12 and available at dedicated pins. Switching on the digital block had no or hardly any effect on the noise level in the IF frequency band. Spurious tones at multiples of 8 MHz, i.e., the main clock frequency in the digital block, appear on the substrate inside the analog block with an attenuation of 20 dB or more compared to the substrate at the edge of the digital block. Future experiments have to reveal how much more attenuation can be achieved when a trench is etched between analog and digital [14]. VII. CONCLUSION A 32-mW highly digitized receiver for GFSK applications in the 2.4-GHz ISM band has been realized in 3.5 mm in 0.18- m CMOS. The power consumption is at least a factor of two lower than for state-of-the-art CMOS receivers. The only external components are an antenna filter and a crystal. The main advantages of the highly digitized architecture are the simplicity and low power of the RF front-end, the flexibility

[1] P. van Zeijl, J.-W. T. Eikenbroek, P.-P. Vervoort, S. Setty, J. Tangenberg, G. Shipton, E. Kooistra, I. C. Keestra, D. Belot, K. Visser, E. Bosma, and S. C. Blaakmeer, “A Bluetooth radio in 0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1679–1687, Dec. 2002. [2] H. Ishikuro, M. Hamada, K. Agawa, S. Kousai, H. Kobayashi, D. M. Nguyen, and F. Hatori, “A single-chip CMOS Bluetooth transceiver with 1.5 MHz IF and direct modulation transmitter,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., San Francisco, CA, Feb. 2003, pp. 94–95. [3] H. Komurasaki, T. Sano, T. Heima, K. Yamamoto, H. Wakada, I. Yasui, M. Ono, T. Miwa, H. Sato, T. Miki, and N. Kato, “A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 817–825, May 2003. [4] S. Byun, C.-H. Park, Y. Song, S. Wang, C. S. G. Conroy, and B. Kim, “A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1609–1618, Oct. 2003. [5] K. Muhammad, D. Leipold, B. Staszewski, Y.-C. Ho, C. M. Hung, K. Maggio, C. Fernando, T. Jung, J. Wallberg, J.-S. Koh, S. John, I. Deng, O. Moreira, R. Staszewski, R. Katz, and O. Friedman, “A discrete-time Bluetooth receiver in a 0–13 m digital CMOS process,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., San Francisco, CA, Feb. 2004, pp. 268–269. [6] H. J. Bergveld, K. M. M. van Kaam, D. M. W. Leenaerts, K. J. P. Philips, A. W. P. Vaassen, and G. Wetzker, “A low-power highly digitized receiver for 2.4-GHz-band GFSK applications,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., Fort Worth, TX, Jun. 2004, pp. 347–350. [7] D. M. W. Leenaerts, C. S. Vaucher, H. J. Bergveld, M. Thompson, and K. Moore, “A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1155–1162, Jul. 2003. ADC for Bluetooth re[8] K. Philips, “A 4.4 mW 76 dB complex ceivers,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., San Francisco, CA, Feb. 2003, pp. 64–65. [9] K. Philips, P. A. C. M. Nuijten, R. Roovers, A. H. M. van Roermund, F. Muòoz, M. Tejero, and A. Torralba, “A continuous-time ADC with increased immunity to interferers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2170–2178, Dec. 2004. [10] E. B. Hogenauer, “An economical class of digital filters for decimation and interpolation,” IEEE Trans. Acoust., Speech, Signal Process., vol. ASSP-29, no. 2, pp. 155–162, Apr. 1980. [11] J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput., vol. EC-8, no. 3, pp. 330–334, Sep. 1959. [12] P. E. Laurent, “Exact and approximate construction of digital phase modulations by superposition of amplitude modulated pulses (AMP),” IEEE Trans. Commun., vol. COM-34, no. 2, pp. 150–160, Feb. 1986. [13] J. G. Proakis, Digital Communications, 2nd ed. New York: McGrawHill, 1989. [14] C. van Veen, H. J. Bergveld, T. van den Ackerveken, G. Zilber, and D. Teomim, “Shellcase packaging: A novel approach of cross-talk suppression for system-on-chip,” presented at the Eur. Microelectronics Packaging Symp., Prague, Czech Republic, Jun. 16–18, 2004. [15] D. Leenaerts, J. van der Tang, and C. Vaucher, Circuit Design for RF Transceivers. Boston, MA: Kluwer, 2001.

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Henk Jan Bergveld was born in Enschede, The Netherlands, in 1970. He received the M.Sc. degree (cum laude) and Ph.D. degree (cum laude) in electrical engineering from the University of Twente, Enschede, The Netherlands, in 1994 and 2001, respectively. In 1994, he joined Philips Research Laboratories, Eindhoven, The Netherlands. He is currently a Senior Scientist with the Mixed-Signal Circuits and Systems Group, Philips Research Laboratories, where he focuses on the integration of RF transceivers in CMOS technology. His research interests were the design of battery management systems and the modeling of rechargeable batteries to improve these designs. The results of these research activities resulted in his doctoral degree and Battery Management Systems—Design by Modeling (Boston, MA: Kluwer, 2002).

Kees M. M. van Kaam was born in Steenbergen, The Netherlands, in 1977. He received the B.Eng. degree in electrical engineering from Breda Polytechnic, Breda, The Netherlands, in 1999, and the M.Sc. degree in electrical engineering from the Eindhoven University of Technology, Eindhoven, The Netherlands, in 2004. In 1999, he joined Philips Research Laboratories, Eindhoven, The Netherlands, where he is currently a Member of the Scientific Staff with the Digital Design and Test Group. His research interest was the test and design for the debugging of digital ICs. His current research interest is in silicon integration aspects of digital ICs.

Domine M. W. Leenaerts (M’94–SM’96) received the Ph.D. degree in electrical engineering from the Eindhoven University of Technology, Eindhoven, The Netherlands, in 1992. From 1992 to 1999, he was with the Eindhoven University of Technology, as an Associate Professor with the Micro-Electronic Circuit Design Group. In 1995, he was a Visiting Scholar with the Department of Electrical Engineering and Computer Science, University of California at Berkeley. In 1997, he was an Invited Professor with the Technical University of Lausanne (EPFL), Lausanne, Switzerland. Since 1999, he has been a Principal Scientist with Philips Research Laboratories, Eindhoven, The Netherlands, where he is involved in RF integrated transceiver design. He has authored or coauthored over 100 papers in scientific and technical journals and conference proceedings. He holds several patents. He has coauthored two books, including Circuit Design for RF Transceivers (Boston, MA: Kluwer, 2001). His research interests include nonlinear dynamic system theory, ADC/digital-to-analog converter (DAC) design, and RF and microwave techniques. Dr. Leenaerts is an IEEE Distinguished Lecturer and an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS.

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Kathleen J. P. Philips (M’03) received the M.Sc. degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1995, and is currently working toward the Ph.D. degree in the area of time-continuous sigma–delta A/D conversion at the Eindhoven University of Technology, Eindhoven, The Netherlands. She is currently with the Mixed-Signal Circuits and Systems group of the Philips Research Laboratories, Eindhoven, The Netherlands, where she is currently a Senior Scientist. Her research interests include A/D and D/A conversion for audio systems and radio receivers, IF circuits, and CMOS integrated receivers.

Ad W. P. Vaassen was born in Eindhoven, The Netherlands, in 1972. He received the M.Sc. degree in electrical engineering from the Eindhoven University of Technology, Eindhoven, The Netherlands, in 2003. In 1996, he joined Philips Research Laboratories, Eindhoven, The Netherlands, where he was a Member of the Research Staff with the Digital Very Large Scale Integration (VLSI) Group. He is currently a Senior Design Engineer with the Embedded Processor Department, Philips Semiconductors, Eindhoven, The Netherlands, where he focuses on design and implementation of high-performance reduced-instruction-set computer (RISC) processors. His research interests have included the design and implementation of VLSI circuits by the use of recursive and hierarchical design methodologies.

Gunnar Wetzker (M’94) was born in Hamburg, Germany, in 1968. He received the Dipl.-Ing. and Dr.-Ing. degrees from the University of Karlsruhe, Karlsruhe, Germany, in 1993 and 1998, respectively. Since 1999, he has been a Senior Scientist with Philips Research Laboratories, Eindhoven, The Netherlands. His research involves digital signal processing for wireless systems such as multiple input multiple output (MIMO), wireless local area networks (WLANs), and wireless personal area networks (WPANs). Dr. Wetzker is a member of the Verean Deutscher Elektrotechniker (VDE).

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A 0.25-m CMOS OPLL Transmitter IC for GSM and DCS Applications Peng-Un Su

Abstract—A single-chip CMOS global system for mobile communications/digital cellular system dual-band offset phase-locked loop (OPLL) transmitter is presented in this paper. This chip includes a quadrature modulator and an OPLL modulation loop. Except for the loop filter and high-power voltage-controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter. This transmitter integrated circuit is fabricated in a 0.25- m CMOS process. The current consumption without the TX VCO is approximately 23 mA under 2.7-V power supply for both bands. The measured rms and peak phase errors for Gaussian minimum shift-keying (GMSK) modulated signals are approximately 1 and 2.4 , respectively. The measurements show comparable performance to its BiCMOS counterparts. Index Terms—Carrier suppression, digital cellular system (DCS), global system for mobile communcations (GSM), harmonic rejection filter, offset phase-locked loop (OPLL), quadrature modulator, transmitter. Fig. 1. Dual-band OPLL transmitter IC of this study.

I. INTRODUCTION

A

LTHOUGH third-generation (3G) systems are taking off these years, the global system for mobile communications (GSM) is still the most commonly used cellular system today. The annual growth of GSM technology is 89% in the Americas from September 2002 to September 2003, and there were nearly one-billion GSM subscribers worldwide by the end of 2003. Although the GSM market share in Europe will decline due to the growth of 3G, it will still occupy 91.4% of the market in the year 2007. The worldwide GSM market is still huge in the near future. While most GSM RF transceivers have utilized a bipolar and or BiCMOS process and have benefited from its high ratio over the past several years [1]–[7], only a few GSM transceivers were implemented in CMOS in the 1990s [8]–[10], where few of them use the offset phase-locked loop (OPLL) architecture. However, it has come to an age that everything should be integrated together to form a system more compact in size and, thus, system-on-a-chip (SoC) has become an unavoidable trend. Although bipolar RF circuits and CMOS baseband circuits can be integrated together with BiCMOS process, the cost is still higher than using only CMOS. In order to make SoC possible and to lower the cost of the system, more and more GSM transceivers are implemented with the advanced deep-submicrometer CMOS process, e.g., 0.18 or 0.12 m, in recent years due to their higher and higher achievable Manuscript received April 20, 2004; revised August 17, 2004. The author is with the System-on-a-Chip Technology Center/Industrial Technology Research Institute, Hsin-Chu, Taiwan 310, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840757

[11]–[14]. In this study, even lower cost 0.25- m CMOS is chosen to show its comparable performance to its bipolar or BiCMOS counterpart. This paper is organized as follows. Sections II and III give the transmitter architecture and building blocks in detail, respectively. Die photograph and measurements are given in Section IV, and Section V concludes this paper. II. TRANSMITTER ARCHITECTURE This transmitter integrated circuit (IC) is composed of two major building blocks, i.e., a quadrature modulator and an OPLL, as shown in Fig. 1. The quadrature modulator first converts the baseband signal with the quadrature LO signals generated by dividing to IF the 182-MHz sinusoidal wave provided by the IF synthesizer, which is not shown in Fig. 1. The following harmonic rejection filter is designed to guarantee the spurs generated by the quadra, , and so on are greatly suppressed so ture modulator at that a clean modulated reference signal is provided to the OPLL. If these harmonics are not successfully filtered, the nonlinearity of the following stages would create intermodulation products that fall into the transmit channel [15]. In the OPLL, the limiter followed by the phase-frequency detector (PFD) is used to limit the modulated reference signal and feedback signal, which is a down-converted version of the output of the high-power voltage-controlled oscillator (TX VCO), to a fixed amplitude due to the digital-type PFD used in this study. The PFD compares these two limited signals and controls the charge pump to generate a voltage that is used to control the output frequency of the TX VCO. Exploiting the

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into account, and the result is derived degeneration resistor in Appendix A as follows:

(2)

Fig. 2. Dual-band quadrature modulator with input attenuation stages.

nature of the PLL and the frequency translation of the offset mixer in the feedback path, the modulated reference signal provided by the quadrature modulator can be reproduced at the output of the external TX VCO at RF. Besides, the purity of the output spectrum can also be achieved because the OPLL also behaves like a high- bandpass filter. III. BUILDING BLOCKS A. Quadrature Modulator Fig. 2 shows the circuit diagram of the quadrature modulator. baseband signal from a D/A converter is The single-ended 1 first attenuated by a resistive voltage divider and a degenerated differential pair that is followed by a PMOS source follower. The quadrature modulator itself is composed of two Gilbert cells with a degenerated transconductance stage. The input stages attenuate the input signal by a factor of four such that the signal single-ended. amplitude at the Gilbert cell input is 0.25 Except for output power and linearity, there are two other major parameters for a quadrature modulator, which are carrier suppression and sideband suppression. Since carrier leakage is caused by frequency translating the input referred dc offset of the baseband input port to RF, carrier supvoltage pression can be seen as the amplitude ratio of the ac baseband [11]. The input referred offset voltage input signal and of a simple MOS differential pair is given in [16] to be

(1)

where is the dc current of the current source. However, the input referred offset voltage that causes carrier leakage in a quadrature modulator is slightly different from that in (2). Since there are local oscillator (LO) switches in a quadrature modulator that make currents flow into loading resistors alternately, the loading resistance can be seen “averaged” so the mismatch of loading resistors would not contribute to any carrier leakage. As a consequence, carrier suppression is, in fact, the amplitude ratio between the baseband input signal , where and

(3)

which is obtained by substituting into (2). It is seen from (3) that bias current mismatch is amplified by . What (3) suggests is that it is not possible to enhance carrier suppression by simply enlarging the baseband input signal beshould also be enlarged to maintain the cause, in that case, same linearity and, hence, resulting in a larger input referred offset voltage. A more thorough optimization for carrier suppression should be done to determine the input baseband signal amplitude, overdrive voltage of the transconductance stage, bias current, and degeneration resistor. in Fig. 2 is chosen to be Transistor device size of size and ratio not only enhances 400/1. This large the matching characteristics of the differential pair, i.e., min, but also minimizes the overdrive voltage , imizing hence, improving the carrier suppression characteristic of the quadrature modulator. However, the linearity of this quadrature is too large, such that bias modulator is over designed, i.e., current mismatch contributes to carrier leakage more than it should. A more detailed description of quadrature modulators is provided in [11]. B. Harmonic Rejection Filter [17], [18]

where is the threshold voltage mismatch of the differential is the overdrive voltage of the transconductance stage, pair, is the loading resistor, and is the aspect ratio of the transconductance stage. However, with degeneration resistors typically used in a quadrature modulator, as shown in Fig. 2, due to the large input baseband signal from the D/A converter, this input referred dc offset voltage should be modified and take the

Shown in Fig. 3 is a Sallen–Key low-pass filter (SK LPF). The gain and output resistance of the amplifier in the filter is denoted as and , respectively. Equation (4), shown at the bottom of the following page, describes the transfer function of such filter. is the output resistance of the amplifier in Note again that Fig. 3, not the commonly used notation for the output resistance of a MOS transistor.

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Fig. 3. General model of an SK LPF where resistance of the amplifier, respectively.

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K and r

are the gain and output

The zeros introduced by are undesired because the frequency response of the filter at high frequency would be flattened. Techniques such as feedback can be used to push the zeros to a higher frequency [19]. Yet with proper design, these zeros can be used as transmission zeros to form narrow-band rejection at the desired frequencies. , we By assuming that the zeros are located at can write the numerator of (4) in the form of

Fig. 4. SK LPF for a harmonic rejection filter.

TABLE I DESIGN PARAMETERS OF THE HARMONIC REJECTION FILTER

(5) Equations (6) and (7) show the natural frequency and quality factor of the transfer function in (5) as follows: (6) (7)

By taking the derivatives of with respect to and letting it equal zero, it can be shown that, for , i.e., , there will be a minimum value, i.e., a notch, in the when magnitude response of (8)

, , , , and , (4) becomes (9). It is then obvious that we need four equations to solve for four filter parameters, i.e., , , and , and the product as follows: of and

From the above discussion, we know that as long as the zero , the filter will have locations are properly assigned, i.e., a frequency response with a notch, and the notch frequency can be designed by using (8). Fig. 4 shows the SK LPF circuit used in our filter design, where a source follower is used as the amplifier in Fig. 3. It is well known that the gain and output resistance of a source , respectively. By subfollower are approximately 1 and and into (4) and assuming that stituting

(9)

(4)

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Fig. 5. Simulated frequency responses of the harmonic rejection filter. (a) Frequency responses of the first and second stages of the filter in the GSM mode. (b) Frequency response of the harmonic rejection filter in the GSM mode. (c) Frequency responses of the first and second stages of the filter in the DCS mode. (d) Frequency response of the harmonic rejection filter in the DCS mode.

The first two equations come from solving and by using (5) and the numerator of (9) and substituting them into (7) and (8). The obtained equations are as follows: (10) (11) The other two equations come from the quality factor and the natural frequency of the denominator of (9). The obtained equations are as follows: (12) (13) With (10)–(13), we can evaluated the circuit parameters , , , and , by choosing: 1) , which is used to define

the depth of the notch; 2) , which is used to define the notch , which is the quality factor of the frequency of the filter; 3) filter; and 4) , which is the natural frequency of the filter. The evaluation procedure is shown in Appendix B. The harmonic rejection filter used in this study is a cascade of two SK LPFs with frequency notches that are described above. The circuit of each SK LPF is shown in Fig. 4. The frequency and for the first and second SK notches are located at LPFs, respectively. The chosen and evaluated filter parameters are listed in Table I. The and product in the digital cellular system (DCS) band is half of that in the GSM band, as shown in Table I, thus, dual-band application is achieved by simply switching the capacitor values. The simulated filter responses are shown in Fig. 5. This harmonic rejection filter provides approximately 10-dB gain for both bands. The gain of the filter may vary by a few decibels due to process variation, but this is not a problem in this OPLL architecture since the filter is followed by a large gain limiter prior to the digital PFD, and the gain variation can be compensated by the limiter.

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Fig. 7. Schematic of the dual-band charge pump, which is achieved by switching ON/OFF the second identical charge pump.

Fig. 6. Precharge-type phase frequency detector. (a) This PFD is composed of two identical flip-flops. (b) Circuit schematic of the PFD.

The current consumption of the filter is only 4.4 mA in simulation for both modes. An additional bidirectional buffer is inserted at the output of the filter, such that the performance of the modulator and OPLL can be measured separately. C. Limiter, PFD, Charge Pump, and Loop Filter The limiter is formed by cascading two differential pairs with a large gain to transform the filtered signals into square waves without distorting the phase information. The output signal amplitude is chosen to be 300 mV single ended as a compromise between noise immunity, speed, and signal coupling into the substrate. A precharge-type PFD, as shown in Fig. 6, is utilized in this study. It is composed of two identical flip-flops. For each flipflop, the activation of the output depends directly on the inputs. As a consequence, there are no gate delay problems that cause the charging and sinking to take place simultaneously, hence, the matching requirement of the charging and sinking current in the charge pump is not so stringent in this design [20]. The pump currents of the charge pump are 2 and 1 mA for the GSM and DCS modes, respectively. The pump currents are difin ferent in different modes because the TX VCO gain the DCS mode is approximately twice of that in the GSM mode. With this design, we can use the same third-order loop filter for both modes without changing the loop dynamics. Fig. 7 shows the schematic of the charge pump. Both PUMP1 and PUMP2 provide charging and sinking currents of 1 mA. The only difference is that PUMP2 is only activated in the GSM mode such that the pump current ratio of two in different modes can be achieved accurately despite any process variation.

Fig. 8. Driver for the TX VCO feedback signal. Single-to-differential conversion is achieved in this driver.

D. Driver and RF LO Buffer Since the feedback signal from the TX VCO is single ended, the function of the driver is not only to amplify that signal, but also to perform single-to-differential transformation. As shown in Fig. 8, this single-to-differential transformation is done by . Transistors form a cascoded current mirror to minimize the current mismatch due to channel length modulation. While the input signal that goes through common gate and has 0 phase change, the signal that goes amplifiers has a phase through cascoded common source amplifier change of 180 . As a result, the output is a differential signal version of the input [21]. A cross-coupled cascode amplifier is used for amplification because of its broader bandwidth and larger gain [5]. The RF LO buffer is modified from the driver by eliminating the single-to-differential transformation stage. E. Offset Mixer and Low-Pass Filter The offset mixer is used to down-convert the RF signal to IF without scaling its phase information, which would happen if frequency dividers, instead of a mixer, were used. The low-pass filter is used to filter out all the spurs generated by the offset mixer such that the signal at the TX VCO output can be faithfully reproduced at IF and provided to the PFD. The bandwidth requirement of this low-pass filter is broader than that of the harmonic rejection filter. Take the GSM mode for example. At the instance of powering ON the transmitter, the

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Fig. 9. Die photograph of the transmitter. The die size is 1.8 mm including ESD protected pads and testing buffers.

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2 1.4 mm

control voltage of the TX VCO must be 0 V, hence, the TX VCO oscillating frequency is at lowest channel of the GSM, say, 880 MHz. Assume that the transmit channel is assigned to be the highest channel of GSM, i.e., 915 MHz, the required LO frequency for the offset mixer would be 960.5 MHz. With this 960.5-MHz LO frequency and 880-MHz RF feedback signal from the TX VCO, the down-converted IF signal by offset mixer is at 80.5 MHz. As a consequence, the low-pass filter bandwidth must be wide enough for this 80.5 MHz to pass through or there would be no feedback signal to the PFD, and the OPLL would fail to lock. For the DCS band, the filter bandwidth must be wider than 166 MHz. For the reason stated above, the second stage, instead of the first stage, of the harmonic rejection filter , as shown in Fig. 4, is modified with a frequency notch at and reused here for the low-pass filter. The spurs are suppressed by at least 30 dB. IV. MEASUREMENT RESULTS This chip is fabricated in TSMC 1P5M 0.25- m CMOS technology. Fig. 9 shows the die photograph. Except for the charge pump output pad and TX VCO feedback input pad, all other pads are protected by electrostatic discharge (ESD) protection circuits. The die size is 1.8 mm 1.4 mm, and could be further minimized by eliminating all the testing buffers. This chip consumes 29.6 mA (6.6 mA out of 29.6 mA was consumed by the testing buffers that are irrelevant to the transmitter operation.) for both bands under 2.7-V power supply. Panasonic’s VCO (ENFVZ4G59) is used as the TX VCO in the test, and the current consumption of this VCO is approximately 34 mA. The loop bandwidth of the OPLL is designed to be 1.6 MHz as a compromise between noise and speed. The following measurements are the results of measuring several samples without any trimming or calibration. Although the performance of these samples does not differ from each other significantly, the author believes that yield optimization is still required for mass production. Fig. 10(a) and (b) shows the output signal spectrum with a wide frequency span before and after the harmonic rejection

Fig. 10. Wide frequency span output signal spectrum before and after the harmonic rejection filter in the DCS band. (a) Before the filter. (b) After the filter.

filter. It should be noted that signal testing buffers with large current consumptions are placed at the output of the quadrature modulator and the harmonic rejection filter so that their output signals can be observed without distortion. Due to the large-signal swing of the IF LO in the quadrature modulator, the output of the modulator would consists of unwanted harmonics , , and so on, assuming that the circuit is fully balat anced. As shown in Fig. 10(a), the largest harmonic is located and is 17 dB smaller than the wanted signal. Harmonics at and are also observed due to the mismatches that at make the circuits not fully balanced. After the harmonic rejection filter, as shown in Fig. 10(b), all the harmonics are heavily suppressed, and the result is the RF output spectrum that lies under the spectrum mask with margins, as shown in Fig. 11.

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Fig. 11. Single-sideband test and GMSK modulated output spectrum of the GSM/DCS dual-band transmitter. (a) Single-sideband test output spectrum in the GSM mode. (b) GMSK modulated output spectrum in the GSM mode. (c) Single-sideband test output spectrum in the DCS mode. (d) GMSK modulated output spectrum in the DCS mode.

Fig. 11(a) and (c) shows the single-sideband test of the transmitter in both the GSM and DCS bands. Carrier and sideband suppressions in both bands are approximately 39 and 56 dBc, respectively. Good carrier suppression is achieved by large devices, i.e., better matching, used in the transconductance stage and current sources of the quadrature modulator, and good sideband suppression is achieved by symmetric layouts and partially due to the low IF chosen for the system. The third-order harmonic distortion (HD3) suppression is 62 dBc in the DCS band, but it is only 46 dBc in the GSM band. The direct impact of this insufficient HD3 suppression is the degradation of the Gaussian minimum shift-keying (GMSK) modulated spectrum, as shown in Fig. 11(b) and 11(d), where

GMSK modulated spectrums are shown in the GSM and DCS bands, respectively. While the spectrum in the DCS band lies well beneath the spectrum mask with a 7-dB margin at 400-kHz offset, the spectrum in the GSM band has only a 3-dB margin. This grown-up spectrum due to the insufficient linearity can be explained by [10] and [15]. The GMSK modulated output spectrum in the GSM band with 20-MHz frequency span is shown in Fig. 12. The output spectrum lies well under the spectrum mask. There is a stringent specification for the GSM transmitter, i.e., the noise floor at 20-MHz offset from the carrier should be lower than 162 dBc/Hz. However, due to the dynamic range limitation and not sufficiently low noise floor of the spectrum analyzer,

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TABLE II SUMMARY OF SPECIFICATIONS AND MEASUREMENTS

Fig. 12.

GMSK output spectrum with a larger span in the GSM mode.

V. CONCLUSIONS In this paper, a GSM/DCS dual-band transmitter has been implemented in 0.25- m CMOS technology. Transmitter architecture and detailed circuits of each block have been described. A thorough analysis of carrier leakage due to device mismatches in a quadrature modulator and a detailed derivation of the harmonic rejection filter design have also been given. The current consumption and die size are only 64% and 84% of its 0.18- m counterpart [11], respectively. This improvement is mainly due to the novel design of the harmonic rejection filter. Small phase errors for GMSK modulated signal and good carrier and sideband suppressions are achieved by careful design and layout. All these measurements show that this chip is comparable to its high-performance BiCMOS counterparts. APPENDIX A

Fig. 13. Constellation, EVM, rms phase error, and peak phase error performance of the demodulated GMSK signal in the GSM band.

the best noise floor measured at 20-MHz offset from the carrier is 160 dBc/Hz, and that is when the spectrum analyzer suffers slightly from over loading. Fig. 13 shows the demodulated GMSK signal constellation, error vector magnitude (EVM) performance, rms phase error, and peak phase error in the GSM band. The measured rms and peak phase errors are 1 and 2.4 , respectively. The phase error performance is better in the DCS band due to its better HD3 suppression performance. The measured rms and peak phase errors in the DCS band are 0.7 and 1.7 , respectively. Table II summarizes the specifications and measured results of the GSM/DCS dual-band transmitter for one sample, and Table III compares the performance of this study with those OPLL transmitters previously published.

Fig. 14 shows a degenerated MOS differential pair. This differential pair suffers from process mismatches, e.g., resistor mismatch ( and ), current factor mismatch ( and , where is proportional to for NMOS), transistor threshold voltage mismatch ( and ), and current source mismatch ( and ). Note that the variance of the current factor and threshold voltage are inversely proportional so that the matching would be to the transistor area better if larger size transistors were used [22]. To make the formulation easier, we let , , , , , , and . The output dc offset voltage due to these mismatches can be evaluated as follows:

(14) where

and

.

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TABLE III PERFORMANCE SUMMARY OF PREVIOUS OPLL TRANSMITTERS AND THIS STUDY

Solving (16) for

, we have

(17)

We can now find the output offset voltage by substituting (17) into (14), and the result is shown in (18) as follows:

Fig. 14.

Degenerated MOS differential pair with device mismatches.

Our next step is to solve for . To solve for , we need to find out the voltage across the degeneration resistor by noting that the input offset voltage is (15) (18) Rearranging (15) for

, we have of Fig. 14 can then The input referred offset voltage in (18) and replacing be found by letting by , and the result is shown in (2). APPENDIX B To solve the circuit parameters , (10)–(13), first rewrite (10) to obtain

,

, and

in

(19) (16) Note that the assumption is used in (16). This is usually true when the input signal of the differential pair is large is large to improve the linearity. and degeneration resistor

Substituting (19) into (11) and rearrange it for have

, we

(20)

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Substituting (19), again, into (12) and rearrange it for , we have

(21) Now substitute (19)–(21) into (13). We can obtain a quadratic equation of , as follows:

(22) Equation (22) allows us to solve for once we have determined the frequency response characteristics, which are charof the filter. Circuit parameters acterized by , , , and and can then be solved by substituting into (20) and (21), respectively. After and are obtained, can be solved by solving (19). ACKNOWLEDGMENT The author would like to thank C.-M. Hsu, System-on-a-Chip Technology Center/Industrial Technology Research Institute, Hsin-Chu, Taiwan, R.O.C., for providing his valuable experience and his consistent help on this project. REFERENCES [1] S. Feng, B. Kolb, H. Herrmann, W. Veit, V. Thomas, S. Herzinger, F. Volpe, G. Lipperer, and J. Fenk, “A bipolar upconversion modulation loop transmitter for dual-band mobile communication,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., 1998, pp. 253–256. [2] J. L. Tham, M. A. Margarit, B. Pregardier, C. D. Hull, R. Magoon, and F. Carr, “A 2.7-V 900-MHz/1.9-GHz dual band transceiver IC for digital wireless communication,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 286–290, Mar. 1999. [3] T. Yamawaki, M. Kokubo, K. Irie, H. Matsui, K. Hori, T. Endou, H. Hagisawa, T. Furuya, Y. Shimizu, M. Katagishi, and J. R. Hildersley, “A 2.7-V GSM RF transceiver IC,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2089–2096, Dec. 1997. [4] G. Irvine, S. Herzinger, R. Schmidt, D. Kubetzko, and J. Frank, “An up-conversion loop transmitter IC for digital mobile telephones,” in IEEE Int. Solid-State Circuits Conf Tech. Dig., 1998, pp. 364–365. [5] T. D. Stetzler, I. G. Post, J. H. Havens, and M. Koyama, “A 2.7–4.5 V single chip GSM transceiver RF integrated circuit,” IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1421–1429, Dec. 1995. [6] M. A. Margarit and M. J. Deen, “A low power high spectral purity frequency translational loop for wireless application,” in Proc. IEEE Custom Integrated Circuits Conf., 2000, pp. 593–596. [7] G. K. Dehng, C. F. Kuo, S. T. Wang, M. H. Tsai, C. C. Ku, V. Yeh, L. W. Ke, C. M. Hsiao, C. Chiu, B. Tzeng, C. C. Tang, J. C. Bo, R. Juan, and H. Xue, “A single-chip RF transceiver for quad-band GSM/GPRS applications,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2004, pp. 427–430. [8] C. Marshell, F. Behbahani, W. Birth, A. Fotowat, T. Fuchs, R. Gaethke, E. Heimerl, S. Lee, P. Moore, S. Navid, and E. Saur, “A 2.7 V GSM transceiver IC’s with on-chip filtering,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 1995, pp. 148–149.

[9] T. Yamawaki, M. Kokubo, and H. Hagisawa, “A CMOS offset phase locked loop for a GSM transmitter,” Analog Integrated Circuits Signal Processing, vol. 25, pp. 253–259, 2000. [10] B. Razavi, “A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 573–579, May 1999. [11] J. M. Hsu, “A 0.18-m CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 603–613, Apr. 2003. [12] E. Gotz, H. Krobel, G. Marzinger, B. Memmler, C. Munker, B. Neurauter, D. Romer, J. Rubach, W. Schelmbauer, M. Scholz, M. Simon, U. Steinacker, and C. Stoger, “A quad-band low power single chip direct -modulation loop for GSM,” in conversion CMOS transceiver with Proc. Eur. Solid-State Circuits Conf., 2003, pp. 217–220. [13] T. Manku, M. Kahrizi, C. Snyder, Y. Ling, J. Khajehpour, J. Wei, K. Lee, V. Yavorskyy, Y. Lai, W. Kung, S. Devison, L. Wong, S. Dosanjh, K. Trainor, M. Tran, D. Marchesan, M. Schumacher, G. Weale, and S. Holditch, “A single chip direct conversion CMOS transceiver for quad-band GSM/GPRS/EDGE and WLAN with integrated VCO’s and fractional N synthesizer,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2004, pp. 423–426. [14] M. Simon, R. Weigel, B. Neurauter, and G. Marzinger, “A CMOS quadband transceiver for GSM-EDGE with dual mode transmitter architecture for low noise and high linearity,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2004, pp. 431–434. [15] A. Rofougaran, G. Chang, J. J. Rael, J. Chang, M. Rofougaran, P. J. Chang, M. Djafari, M. K. Ku, E. W. Roth, A. A. Abidi, and H. Samueli, “A single-chip 900-MHz spread-spectrum wireless transceiver in 1-m CMOS—Part I: Architecture and transmitter design,” IEEE J. SolidState Circuits, vol. 33, no. 4, pp. 515–534, Apr. 1998. [16] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001, ch. 4. [17] P. U. Su and J. M. Hsu, “A quadrature modulator with enhanced harmonic rejection filter,” in Proc. IEEE Asia–Pacific Conf., 2002, pp. 319–322. , “A dual-band enhanced harmonic rejection filter for modulators [18] in GSM and DCS transmitters,” in Proc. Eur. Solid-State Circuits Conf., 2003, pp. 663–666. [19] J. A. Weldon, R. S. Narayanaswami, J. C. Rudell, L. Lin, M. Otsuka, S. Dedieu, L. Tee, K. C. Tsai, C. W. Lee, and P. R. Gray, “A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 2003–2015, Dec. 2001. [20] J. T. Wu, H. D. Chang, and P. F. Chen, “A 2-V 100-MHz CMOS vector modulator,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 1997, pp. 80–81. [21] B. Gilbert, “The MICROMIXER: A highly linear variant of the Gilbert mixer using a bisymmetric class-AB input stage,” IEEE J. Solid-State Circuits, vol. 32, no. 9, pp. 1412–1423, Sep. 1997. [22] M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 10, pp. 1433–1440, Oct. 1989.

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Peng-Un Su was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. degree in electrical engineering and M.S. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1999 and 2001, respectively. From 2000 to 2001, he was with Siemens Telecommunication System Ltd., where he was involved with the design of the cdma2000 base transceiver station (BTS) RF/IF transceiver system. In 2001, he joined the SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, R.O.C. His research interests are in the area of wireless communication ICs. He is now currently involved with SiGe BiCMOS low-power transmitters for wide-band code division multiple access (WCDMA) and CMOS RF circuits.

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Millimeter-Wave CMOS Circuit Design Hisao Shigematsu, Member, IEEE, Tatsuya Hirose, Forrest Brewer, and Mark Rodwell, Fellow, IEEE

Abstract—We have developed a 27- and 40-GHz tuned amplifier and a 52.5-GHz voltage-controlled oscillator using 0.18- m CMOS. The line-reflect-line calibrations with a microstrip-line structure, consisting of metal1 and metal6, was quite effective to extract the accurate -parameters for the intrinsic transistor on an Si substrate and realized the precise design. Using this technique, we obtained a 17-dB gain and 14-dBm output power at 27 GHz for the tuned amplifier. We also obtained a 7-dB gain and a 10.4-dBm output power with a good input and output return loss at 40 GHz. Additionally, we obtained an oscillation frequency of 52.5 GHz with phase noise of 86 dBc/Hz at a 1-MHz offset. These results indicate that our proposed technique is suitable for CMOS millimeter-wave design. Index Terms—Millimeter wave, phase noise, tuned amplifier, voltage-controlled oscillator (VCO).

I. INTRODUCTION

T

HE RAPID growth of wireless communication using, for example, mobile phones and wireless local area networks (LANs), has created a great demand for Si-based RF integrated circuits (RFICs), operating at microwave and millimeter-wave bands. These applications require a low production cost, thus, CMOS is the most attractive solution and the best component. , an However, the CMOS maximum oscillation frequency important parameter for analog circuits, is no higher than those of other devices, such as SiGe HBT and III–V devices. Therefore, it has been difficult to realize analog circuits, especially tuned amplifiers, which operate at close to millimeter-wave frequencies. The III–V devices have accurate parameters around these frequencies because they are fabricated on semi-insulating substrates, and it is easy to eliminate the parasitic parameters. However, CMOS has to be fabricated on a conductive substrate, and its parameters are not applicable to this frequency range. Amplifiers based on III–V and SiGe technologies have been reported. However, there have been very few reports about CMOS amplifiers [1]. In this paper, we propose an accurate parameter-extraction technique with a line-reflect-line (LRL) calibration for CMOS technology, and report a 27- and 40-GHz tuned amplifier and a 52.5-GHz voltage-controlled oscillator (VCO). This parameter-extraction technique provides us with accurate -parameters of the intrinsic transistor and enables the precise design of the integrated circuits.

Manuscript received April 20, 2004; revised August 7, 2004. H. Shigematsu and T. Hirose are with the High-Speed Integrated Circuits Technology Division, Fujitsu Laboratories Ltd., Atsugi 243-0197, Japan. F. Brewer and M. Rodwell are with the University of California at Santa Barbara, Santa Barbara, CA 93106 USA. Digital Object Identifier 10.1109/TMTT.2004.840758

Fig. 1. Parameter-extraction pattern of the transistor.

II. CIRCUIT DESIGN A.

-Parameter Extraction

The extraction of accurate parameters for transistors and transmission lines is important for millimeter-wave circuit design. To achieve this, we used a microstrip-line (MSL) structure, which consists of a metal1 ground and a metal6 signal line [2]. This line structure eliminates the effect of the conductive substrate and provides us with accurate characteristic impedance, allowing us to avoid unwanted differences between the simulation and measured values. The MSL characteristics, obtained through electric–magnetic (EM) simulation, agreed well with the measured results, even though our metal1 had slots to relax the stress. This enabled us to design the matching circuits more precisely. We prepared the parameter-extraction pattern for the transistor, as shown in Fig. 1. This pattern consisted of an intrinsic transistor and outgoing electrode lines for the gate and drain, which uses metal6 with probe pads. We used LRL calibrations to extract the -parameters. This method needs two lines of different lengths and an open pattern. Therefore, we also prepared on-wafer patterns. With this technique, we were able to set the calibration reference planes to the edges of the outgoing lines and obtain the intrinsic -parameters. Yang et al. reported a measurement technique using line-reflect-reflect-match (LRRM) up to 110 GHz, but the reference plane is on the probe tips, as shown by the triangles in Fig. 1 [3]. Therefore, our extraction technique enables easier and more accurate measurement of the -parameters of the intrinsic transistors [4]. , maxFig. 2 shows the frequency dependence of the imum stable gain (MSG) and the maximum available gain (MAG). The profiles were very smooth, and the cutoff freand maximum oscillation frequency were 58 quency and 84 GHz. This indicates that we can obtain accurate -parameters with this technique, and design the circuits precisely. and from 0.25 to Fig. 3 shows measured and simulated 110 GHz on a Smith chart. The -parameters turned smoothly up to 110 GHz, and no unwanted resonance could be seen up to 110 GHz. We extracted the transistor parameter and created the model. The model is

0018-9480/$20.00 © 2005 IEEE

SHIGEMATSU et al.: MILLIMETER-WAVE CMOS CIRCUIT DESIGN

Fig. 2. j 110 GHz.

h

j

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Fig. 5.

MAG and MSG of the single and cascode transistors.

Fig. 6.

Schematic of the tuned amplifier.

, MSG, and MAG of the intrinsic transistor from 0.25 to

S

S

Fig. 3. Measured and simulated and from 0.25 to 110 GHz (dotted line: simulated data, solid line: measured data).

Fig. 4. Measured and simulated I–V (dotted lines: simulated data, solid lines: measured data).

in good agreement with the measured data shown in Fig. 3. Fig. 4 shows the measured and simulated I–V characteristics of the transistor with a gatewidth of 40 m. The off-breakdown voltage is over 3 V, where the body is tied to the source terminal. The model is also a good agreement with the measured data in dc characteristics. We used this model for the following designs. B. Tuned Amplifier Design At millimeter-wave regions, the loss of the transmission line increases so the transistor’s gain is very important for the CMOS amplifier design. A cascode configuration does not degrade the frequency-response at high-frequency regions due to the Miller effect. Therefore, it is superior to the single transistor configuration at high-frequency regions. Fig. 5 shows the MAG of the single and cascode transistors. The cascode configuration has a much larger stable gain than the single transistor configuration. We used the cascode configuration for the amplifier design. Fig. 6 shows a schematic of the tuned amplifier. It consists of three stages with a cascode configuration. Each drain bias was applied through a quarter-wavelength line. Each gate bias was applied through the high-impedance resistor. We used

Fig. 7. Source and drain voltage of

Q2 at 10-dBm input.

metal–insulator–metal (MIM) capacitors at the interstage. The design was based on gain matching, rather than power matching because of the insufficient gain of CMOS at millimeter-wave frequency range. We utilized a transmission line between and to stabilize each stage. The optimized 120- m lengths exist for the stabilization of the amplifier. The amplifier stability factor was above 50. Fig. 7 shows the simulated results for the source and drain at the saturated 10-dBm input at 40 GHz. The voltage of maximum drain–source voltage of is less than 1.7 V. Thereand operate under the breakdown fore, both transistors voltage. Next, we will mention the design for the transmission line. Fig. 8 shows the frequency dependence for the MSL and a coplanar-waveguide (CPW) line on an Si substrate. Fig. 9 shows their structures. For the MSL, metal1 was used for the ground planes and metal6 was used for the signal line. Metal1 shields the unwanted effects of the conductive substrate. The loss is

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Fig. 8.

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Frequency dependence for the MSL and CPW on an Si substrate.

Fig. 11.

Fig. 9. Line structures on an Si substrate. (a) MSL (b) CPW.

Fig. 10.

Simulated isolation between two parallel lines at 40 GHz.

0.25 dB/mm for the MSL, and 2.3 dB/mm for the CPW at 40 GHz. The MSL had a much better performance than the CPW. The EM simulation result for the MSL was in good agreement with the measured one, as shown in this figure. The MSL structure can provide a precise design, and we applied it to the layout design. When we use an MSL, we must consider the isolation between the adjacent lines because the coupling between the two adjacent lines changes the characteristic impedance. This degrades preciseness for the design, especially at millimeter-wave frequencies. Fig. 10 shows the simulated isolation between two parallel lines at 40 GHz. We obtained a 50-dB isolation at a distance of 50 m. This distance was sufficient to retain the characteristic impedance. Here, the length of the parallel line was 500 m. Even at a distance of 20 m, we obtained a 30-dB isolation at 40 GHz. This value was more than adequate for the layout. However, we used a 50- m separation to eliminate the unwanted effects of coupling completely this time. C. VCO Design Fig. 11 shows a schematic of the VCO. We chose a single-ended fundamental oscillator design to demonstrate the effectiveness of our technique. Recently, harmonics-type VCOs using CMOS technology have been reported to obtain a higher oscillation frequency [5]. This kind of VCO usually consists of two VCOs and combines each of the second harmonics of the output. The fundamental frequencies cancel each other out at the cross point. The highest oscillation frequency ever reported

Schematic of the VCO.

in a CMOS fundamental oscillator was 51 GHz without a special process, such as a high-resistivity substrate and buried and epi layers [6]. (This oscillator used 0.13- m technology.) We designed the VCO with 0.18- m CMOS technology to overcome this oscillation frequency. If we obtain a higher oscillation frequency in the fundamental frequency, the oscillation frequency in the harmonics VCO also increases because this is the basis of the harmonics VCO design. We used a combination and the parallel source of the extrinsic source resistance of stub to generate negative resistance around the target frequency. The tank inductor was made of an MSL to realize an accurate inductance. We used a multifinger CMOS diode for the varactors. To reduce the gate resistance, we used a multifinger transistor in the oscillator core. The gate resistance is a parameter that is very sensitive to the oscillation conditions. The resistor was located at the output port to realize impedance matching and isolation between the output and oscillator core. The drain bias was applied through the quarter-wavelength line at a fundamental frequency. Regarding the design procedure, we first determined the startup oscillation conditions with the extracted -parameters as follows. The negative resistance generated by the oscillator must exceed the resistive losses of the resonator. This means that the VCO must have a net negative resistance (1) Also, we set the oscillation frequency according to the equation (2) where (3) Fig. 12 shows the simulated results for the VCO startup frequency at point A, with -parameter analysis. In this method, the startup oscillation frequency is 53 GHz. After setting the startup oscillation frequency, we also performed a harmonic-balance simulation with a large-signal model to compensate for the difference between the startup oscillation frequency and the steady-state one. Fig. 13 shows the harmonic-balance simulation result of the VCO. The oscillation frequency of 52.7 GHz is slightly lower than that using -parameter analysis. An output of approximately 0.3 was obtained.

SHIGEMATSU et al.: MILLIMETER-WAVE CMOS CIRCUIT DESIGN

Fig. 12.

Fig. 13.

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Oscillation frequency simulations with S -parameters. Fig. 15.

Measured S -parameters of the 27-GHz tuned amplifier.

Fig. 16.

Measured P –P

Fig. 17.

40-GHz tuned amplifier.

Fig. 18.

Measured S -parameters of the 40-GHz tuned amplifier.

Harmonic-balance simulations with the extracted model.

characteristics at 27 GHz.

Fig. 14. 27-GHz tuned amplifier.

III. CIRCUIT MEASUREMENTS The circuits were fabricated using a 0.18- m mixed-signal process. In this process, metal6 was 2- m thick to reduce losses. The measured transistor’s cutoff frequency and the maximum oscillation frequency were 58 and 84 GHz, respectively. Fig. 14 shows a microphotograph of the 27-GHz tuned amplifier. The chip size was 1.2 1.7 mm and the power dissipation was 300 mW. We measured the -parameters using an HP8510XF network analyzer. Fig. 15 shows the frequency characteristics of the amplifier at a of 3 V. A small-signal gain of 17 dB was obtained at 27 GHz. This is the highest yet reported for a CMOS amplifier at 27 GHz. and were below 10 dB. The simulation agreed well with the measurements. We also measured the – characteristics at 27 GHz (Fig. 16). We used an HP1131 frequency synthesizer to generate the input signal, and the output signal was measured with an HP E4418B power meter. We obtained saturated power of 14 dBm at 27 GHz. As far as we know, this performance is the best ever reported for CMOS amplifiers. The simulation results with the large-signal model are also shown in this figure. This simulation agreed well with the measurements, as well as with

the small-signal characteristics. Our amplifier can be applied to short-range wireless communication. Fig. 17 shows a microphotograph of the 40-GHz tuned amplifier. The chip size was 1.2 1.7 mm and the power dissipation was 300 mW. The minimum separation between one line and the other line was 50 m to prevent coupling, as previously mentioned. Fig. 18 shows the frequency characteristics of the amplifier at of 3 V. A small-signal gain of 7 dB was obtained at 40 GHz. The impedance matching was done well for the input

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Fig. 19.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Measured P –P

characteristics at 40 GHz.

Fig. 20.

53-GHz VCO.

Fig. 21.

Measured oscillation frequency of the VCO.

TABLE I PERFORMANCE COMPARISON

and output, and and were below 15 dB. The simulation agreed well with the measurement, as well as with the 27-GHz tuned amplifier. This performance is comparable to the previous reported 90-nm silicon-on-insulator (SOI) CMOS amplifier [7]. This superior performance can be obtained without such advanced technology. We also measured the – characteristics at 40 GHz (Fig. 19). We obtained saturated power of 10.4 dBm at 40 GHz. As far as we know, this performance is the best yet reported for CMOS amplifiers. The simulation results with the large-signal model are also shown in this figure. The simulation agreed well with the measurements, as well as with the small-signal characteristics. These results indicate that our proposed technique is quite effective for the medium-power amplifier at millimeterwave frequencies. Our amplifier is applicable to short-range wireless communication. Table I summarizes the current CMOS amplifiers. Fig. 20 shows a microphotograph of the VCO. The chip size was 0.8 1.0 mm, and the power dissipation was 41 mW. Fig. 21 shows the measured oscillation spectrum of the VCO. This measurement was done with waveguided (WG) tubes. The oscillator output signal was down-converted by the HP4211A mixer module, and the spectrum was measured by the HP2411 spectrum analyzer. We obtained an oscillation frequency of 52.5 GHz and output power of 8 dBm (after removing the WG tube loss). This oscillation frequency is the highest ever reported for a fundamental VCO without a high-resistivity substrate, such as an SOI structure, or buried and epi layers. The measured oscillation frequency is nearly equal to the simulated one. These results indicate our proposed LRL

calibration design technique is promising for high-frequency designs. The control range was 100 MHz. In this study, we intended to use the loose coupling capacitor for the varactor to confirm the design accuracy and this causes the narrow control range. We can easily improve the frequency control range by changing the ratio of the coupling capacitor and varactor. IV. CONCLUSION We developed a CMOS tuned amplifier and VCO based on a 0.18- m process. The LRL calibration technique along with an MSL structure consisting of metal1 and metal6 enabled us to extract the accurate -parameters for the intrinsic transistor and realize the precise design. Using this method, we obtained a 17-dB gain and a 14-dBm output power with good input and output return loss at 27 GHz. We also obtained a 7-dB gain and a 10.4-dBm output power, with a good input and output return loss at 40 GHz. Additionally, we realized an oscillation frequency of 52.5 GHz, with phase noise of 86 dBc/Hz at 1-MHz offset for the VCO. These results indicate that our proposed technique is promising for millimeter-wave-circuit designs. ACKNOWLEDGMENT The authors would like to thank Dr. M. Urteaga, University of California at Santa Barbara, and Dr. Takigawa, Fujisu Laboratories Ltd., Japan, for their advice, encouragement, and support.

SHIGEMATSU et al.: MILLIMETER-WAVE CMOS CIRCUIT DESIGN

REFERENCES [1] B. Floyd, L. Shi, U. Taur, I. Lagnado, and K. K. O, “A 23.5-GHz SOI CMOS tuned amplifier,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 9, pp. 2193–2196, Sep. 2002. [2] H. Shigematsu, M. Sato, T. Hirose, F. Brewer, and M. Rodwell, “A 40 Gb/s CMOS distributed amplifier for fiber-optic communication systems,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 476–477. [3] M. Yang, P. Ho, Y. Wang, T. Yeh, and Y. Chia, “Broadband small-signal model and parameter extraction for deep sub-micron MOSFETS valid up to 110 GHz,” in RF Integrated Circuits Dig., Jun. 2003, pp. 369–372. [4] M. Urteaga, S. Krishnan, D. Scott, Y. Wei, M. Dahlstrom, S. Lee, and M. J. W. Rodwell, “Submicron InP-based HBT’s for ultra-high frequency amplifiers,” Int. J. High-Speed Electron. Syst., to be published. [5] R. Liu, H. Chang, and C. Wang, “A 63 GHz VCO using a standard 0.25 m CMOS process,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 446–447. [6] M. Tiebout, H. Wohlmuth, and W. Simburger, “A 1 V 51 GHz fullyintegrated VCO in 0.12 m CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2002, pp. 300–301. [7] F. Ellinger, “26–42 GHz SOI CMOS low noise amplifier,” IEEE J. SolidState Circuits, vol. 39, no. 3, pp. 522–528, Mar. 2004. [8] M. A. Masud, H. Zirath, M. Ferndahl, and H. Vickes, “90 nm CMOS MMIC amplifier,” in RF Integrated Circuits Dig., Jun. 2004, pp. 201–204.

Hisao Shigematsu (M’04) graduated from Osaka University, Osaka, Japan, in 1990. He is currently a Senior Researcher with the High-Speed Integrated Circuits Technology Division, Fujitsu Laboratories Ltd., Atsugi, Japan. In 1990, he joined Fujitsu Laboratories, Kanagawa, Japan, where he was engaged in research on development of high-speed compound semiconductor devices (high electron-mobility transistors (HEMTs), HBTs) and ICs. In 2003, he was a Visiting Researcher with the University of California at Santa Barbara, where he was involved with millimeter-wave CMOS circuits. His current research interest includes high-speed IC design for fiber-optic communication systems. Mr. Shigematsu is a member of the Japan Society of Applied Physics.

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Tatsuya Hirose received the B.E. degree from Tokyo Denki University, Tokyo, Japan, in 1987, the M.E. degree from Hokkaido University, Sapporo, Japan, in 1989, and the Ph.D. degree from Tohoku University, Sendai, Japan, in 2004. . He is currently a Senior Researcher with the High-Speed Integrated Circuits Technology Division, Fujitsu Laboratories Ltd., Atsugi, Japan. In 1989, he joined Fujitsu Laboratories, Kanagawa, Japan, where he was engaged in research on characterization and modeling for heterostructure devices and the development of MMICs based on their technologies. His current research interest includes microwave and millimeter-wave IC design for automotive radar systems, wireless communication systems, and fiber-optic communication systems. Dr. Hirose is a member of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan.

Forrest Brewer received the B.S. degree in physics (with honors) from the California Institute of Technology, Pasadena, and the M.S. and Ph.D. degrees in computer science from the University of Illinois at Urbana-Champaign. He is currently a Professor with the University of California at Santa Barbara. His research spans high-level very large scale integration (VLSI) system formal modeling to physical VLSI design for power, noise, and timing constraints. This research includes synthesis of production-based specifications (technology underlying the Synopsys Protocol Compiler 1 toolset), NDFA-based scheduling (symbolic scheduling), and related high-level synthesis procedures. His current research includes high-reliability finite-state machine synthesis for field-programmable gate array (FPGA) and deep-submicrometer CMOS, as well as cryogenic ultra-low-power CMOS sensors. Dr. Brewer has served on the Technical Advisory Boards of several silicon valley startups and is a member of the Association for Computing Machinery (ACM), the IEEE Antennas and Propagation Society (IEEE AP-S), Tau Beta Pi, and Phi Kappa Phi.

Mark Rodwell (M’89–SM’99–F’03) received the B.S. degree from the University of Tennessee at Knoxville, in 1980, and the M.S. and Ph.D. degrees from Stanford University, Stanford, CA, in 1982 and 1988, respectively. He is currently Professor and Director of the Compound Semiconductor Research Laboratories and the National Science Foundation (NSF) Nanofabrication Users Network (NNUN), University of California at Santa Barbara. From 1982 to 1984, he was with AT&T Bell Laboratories, Whippany, N.J. His research focuses on high-bandwidth InP bipolar transistors and multigigahertz bipolar circuit design. His recent research activities also include microwave power amplifiers, and monolithic analog and digital transistor circuits operating above 100 GHz. Dr. Rodwell was the recipient of a 1989 NSF Presidential Young Investigator Award. His work on GaAs Schottky-diode ICs for subpicosecond/millimeterwave instrumentation was awarded the 1997 IEEE Microwave Prize.

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An Image-Rejection Down-Converter for Low-IF Receivers Sher Jiun Fang, Member, IEEE, Abdellatif Bellaouar, Senior Member, IEEE, See Taur Lee, Member, IEEE, and David J. Allstot, Fellow, IEEE

Abstract—Implemented in 4.1 mm2 in 130-nm CMOS, a dual-conversion image-rejection down-converter applied to the wireless code-division multiple-access (WCDMA) standard draws 13 mA from a single 1.8-V power supply. Using an IF of 2.5 MHz, the WCDMA image-rejection band is widened from 0.58–4.42 MHz to 0.48–5.2 MHz—a bandwidth ratio of 10.8—to accommodate process, voltage, and temperature variations in high-volume production. Ten samples are measured and fully characterized: average image-rejection ratio (IRR) is 46.6 dBc, gain is 12 dB, and noise figure is 10.8 dB. Typical IRR is 44.8, 46.5, and 47.5 dBc at 20 C, 25 C, and 80 C, respectively. Index Terms—Image-rejection down-converter, low-IF receiver, mixer, polyphase filter, quadrature local-oscillator (LO) generator, quadrature mixer, wireless code-division multiple-access (WCDMA).

channel spacing (2.5 MHz), the required IRR equals the specified WCDMA adjacent channel rejection ratio, as confirmed using the adjacent channel selectivity (ACS) test. It measures the ability to receive a desired signal at the center frequency of an assigned channel in the presence of an undesired adjacent channel signal at a given frequency offset. The average energy per pn chip for the dedicated for ACS testing is set at physical channel 103 dBm 3.84 MHz ; hence, the allowable interference level is dBm where

is the processing gain chip rate user data bit rate Mc/s kb/s

I. INTRODUCTION

T

HE LOW-IF receiver architecture offers a level of integration comparable to that of the popular direct-conversion noise, and second-order receiver while avoiding its dc offset, nonlinearity problems [1]. Despite these drawbacks, however, most prior wireless code-divison multiple-access (WCDMA) receivers use the direct conversion approach [2], [3]. The low-IF technique has not been implemented in a WCDMA receiver because the required image-rejection ratio (IRR) is problematic over the WCDMA bandwidth (3.84 MHz) at low-IF frequencies. A low-IF WCDMA receiver front-end implemented in a standard 130-nm CMOS process is described in this paper. It enables integration with baseband digital circuits toward the realization of a single-chip radio. By positioning the low-IF down-converted signal band slightly above the flicker noise corner frequency, many problems that plague the direct conversion approach are avoided with the same high level of integration. Since the low-IF receiver architecture faces a severe image-rejection challenge, a careful choice of the IF frequency is critical. In fact, with the low-IF set to half the WCDMA

Manuscript received April 25, 2004; revised August 25, 2004. This work was supported in part by the National Science Foundation Grant CCR-0086032 and Grant CCR-0120255, by the Semiconductor Research Corporation under Grant 2000-HJ-771 and Grant 2001-HJ-926, and by Texas Instruments Incorporated. S. J. Fang and S. T. Lee were with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195-2500 USA. They are now with the Wireless Terminal Business Unit, Texas Instruments Incorporated, Dallas, TX 75243 USA. A. Bellaouar is with the Wireless Terminal Business Unit, Texas Instruments Incorporated, Dallas, TX 75243 USA. D. J. Allstot is with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195-2500 USA. Digital Object Identifier 10.1109/TMTT.2004.840759

dB and is set at 7.2 dB to obtain a minimum bit-error rate (BER) of 0.001 including margins for baseband imperfections is typically set at a high value in the ACS [16], [17]. test, e.g., 14 dB above the sensitivity level, and 6 dB of blocker noise margin is added to the acceptable interference level so that dBm

dB

dBm

The undesired modulated adjacent channel signal offset by 5 MHz from the center frequency of an assigned channel has a power of 52 dBm. The selectivity required to reduce it to an acceptable interference level is dB Adding an additional 1-dB margin brings the ACS to approximately 40 dB. Consequently, if a low-IF receiver architecture is adopted, the required IRR is at least 40 dB—a daunting specification using conventional image-rejection techniques. The ACS test is depicted in Fig. 1. Including margins for process, voltage, and temperature (PVT) variations, the image-reject (IR) band used in this paper is extended from its nominal 0.58–4.42 MHz to of 10.83. 0.48–5.2 MHz—a bandwidth ratio An image-rejection scheme employing a passive phasing technique consumes less current and introduces fewer noise sources than the active double-quadrature mixer method. The phasing method applied to an image-rejection down-converter

0018-9480/$20.00 © 2005 IEEE

FANG et al.: IMAGE-REJECTION DOWN-CONVERTER FOR LOW-IF RECEIVERS

Fig. 1. Adjacent channel selectivity test.

Fig. 2.

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Fig. 4. Typical WCDMA duplexer characteristics [6].

Phasing method for an image-rejection down-converter. Fig. 5.

Fig. 3.

Dual-conversion low-IF receiver architecture.

requires a wide-band 90 phase-difference network (Fig. 2); it exhibits an inherent phase error that depends on the network complexity and bandwidth ratio in the IR band [5]. Parasitic components associated with the large passive element values required for implementation of the low-frequency 90 phase-shift network also cause phase errors. Both effects have impeded the development of low-IF WCDMA receivers. The new dual-conversion low-IF receiver (Fig. 3) avoids the primary drawbacks of the direct-conversion approach and exceeds the WCDMA IRR specifications. In the proposed architecture, an off-chip duplexer filter provides isolation between transmit and receive bands. It is required because WCDMA employs frequency division duplexing (FDD) with simultaneous transmission and reception. An off-chip surface acoustic wave (SAW) filter that suppresses out-of-band blockers is also included because interference that arises from continuous operation of the high-power transmitter creates severe dynamic range and intermodulation distortion problems. In addition to filtering out blockers, the SAW filter also serves as the first IR

Image-rejection down-converter.

filter for image frequencies that appear after the first mixer. Low-side injection for the first mixer is chosen to take advantage of the sharper rolloff at lower frequencies of the duplexer filter that translates to greater image rejection. It is clear from Fig. 4 that the duplexer filter rejects by more than 48-dB signals that are situated 200 MHz lower than the receive band [6]. A dual-conversion IR subsystem (Fig. 5) down-converts the received signal to a low IF of 2.5 MHz and rejects image signals. System-level performance, hardware, and power advantages accrue from the single differential output to the baseband that provides additional amplification and channel selection. The proposed receiver is also attractive for global system for mobile communications (GSM) and enhanced data rates for GSM evolution (EDGE) standards wherein the conventional use of ac coupling capacitors to overcome dc offsets negatively impacts the achievable BER because of the relatively narrow channels (200 kHz). The viability of a low-IF receiver meeting stringent IRR specifications is demonstrated via an IR down-converter for WCDMA applications in a single-poly six-metal 1.8-V 130-nm CMOS process. As shown in Fig. 5, it uses a Gilbert mixer for the first down-conversion stage, a digitally corrected quadrature local oscillator (DCQLO) generator and a masking quadrature mixer (MQM) for accurate quadrature local oscillator (LO) mixing, and a five-stage passive polyphase filter (PPF) to implement the 90 phase-shift function. Note that, for a bandwidth

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Fig. 6. Four-phase RC polyphase filter.

Fig. 7.

Pole positions in the stopband of a five-stage polyphase filter.

ratio of , the theoretical IRR limit is 50.9 dBc using a five-stage PPF. Section II overviews a polyphase filter used as a wide-band 90 phase-difference network in an IR filter. Section III details circuit implementations, and Section IV summarizes the measurement results. II. SEQUENCE-ASYMMETRIC POLYPHASE FILTER A wide-band 90 phase-difference network (Fig. 6) is required in the image-rejection architecture; in this case, a polyphase filter is used. It is a sequence asymmetric filter that passes one sequence of signals, but rejects another [7]. Although it is commonly used as a complex filter for single-sideband modulation and image-rejection down-conversion, it is also useful as a quadrature generator, as described in this paper. A. Filter Characteristics An example of a negative sequence network is shown in Fig. 6; its inputs are driven by four-phase signals; i.e., its voltages and the currents are in four phases. To implement an image-rejection down-converter, the four outputs of a quadrature mixer are applied to the four inputs of a negative sequence polyphase filter; it passes the desired signal and rejects the unwanted image. B. Bandwidth Each stage in a polyphase filter contributes one-pole frequency around which the image is attenuated; i.e., it provides narrow-band rejection. Image rejection over a wide bandwidth is achieved by cascading several stages [5], [7]–[10], wherein the pole frequencies are placed at equal frequency ratios; i.e., , etc. Consequently, the frequencies are spaced equally on a logarithmic scale in the stopband ranging to , as shown in Fig. 7. A smaller pole frequency from ratio provides greater image rejection at the expense of more stages for a given bandwidth. General approximations of an equal ripple 90 phase-differand netence network are shown in Fig. 8 [8]. Phase error work complexity are related as (1)

Fig. 8. Equal ripple phase-difference approximation.

where network complexity; i.e., number of polyphase filter stages; complete elliptic integral of the first kind of modulus ; complete elliptic integral of the first kind of modulus ; modular angle. The bandwidth ratio is related to the modulus as (2) From (1), it is clear that phase error is reduced as more stages are used. Hence, several stages are typically required in a polyphase filter used as a quadrature generator. The theoretical IRR for a given error angle is (3) As the phase error decreases due to the use of more stages, the IRR increases. It also depends on the bandwidth ratio . For a wider bandwidth at a lower center frequency, more stages are required to achieve a specified IRR; theoretical IRR as a function of bandwidth ratio and network complexity is shown in Fig. 9. The graph can be used to determine the number of polyphase filter stages needed to meet a given IRR specification. It is good design practice to use a larger than required bandwidth to provide margins against PVT variations associated with on-chip passive components.

FANG et al.: IMAGE-REJECTION DOWN-CONVERTER FOR LOW-IF RECEIVERS

Fig. 9. IRR versus bandwidth ratio and network complexity.

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Fig. 11. IRR over 1 dB of amplitude error with 0.1 , 0.5 , 1 , and 2 fixed phase error.

D. Practical Achievable IRR

Fig. 10. IRR over 10 of phase error with 0.01-, 0.1-, 0.2-, and 0.5-dB fixed amplitude error.

C. Ideal IRR As described above, the 90 phase-difference network used in the phasing method for image rejection has an inherent phase error that depends on the complexity of the network and the required bandwidth ratio. These two factors should be considered in any comparison of the IRR performance of image-rejection down-converters. In fact, many publications claim high IRR without regard to the theoretical limit based on these critical parameters. Figs. 10 and 11 show achievable IRRs for different fixed amplitude and phase errors over practical ranges of phase and amplitude errors, respectively. Clearly, the higher the theoretical IRR, the more sensitive the performance to path mismatches in the polyphase filter. Path mismatch is an important factor in comparing the performance of integrated IR down-converters.

Fig. 9 shows ideal IRR values for an IR down-converter with perfect quadrature input signals and exact polyphase filter component values. In practice, however, several factors conspire to degrade IRR, including imperfect quadrature inputs from the quadrature mixer, and component value errors and parasitic components in the polyphase filter. 1) Phase and Amplitude Errors in the Input Quadrature Signals: Phase and amplitude errors in the input quadrature signals due to LO phase and amplitude mismatches degrade IRR. More specifically, phase errors reduce peak rejection and amplitude errors shift the peak attenuation frequency. Both effects reduce IRR at the pole frequency. The image-rejection down-converter introduced in this paper achieves precise quadrature LO signals, and the quadrature stage to avoid mixers share a single transconductance mismatches in the mixers. With careful layout of the LO switches, accurate quadrature signals are applied to the polyphase filter and do not degrade the achievable IRR. 2) Component Mismatches: Component mismatches in the polyphase filter shift the pole frequencies, which leads to imperfect cancellation and reduced IRR at the desired frequency. 3) Parasitics: Parasitic components play an important practical role in determining IRR performance. In this study, the low-IF center frequency of the polyphase filter results in large passive component values that consume large die area with large accompanying parasitics. The minimum spacing between metal lines (0.175 m) is smaller than the minimum thickness of the metal lines (0.305 m) for the 130-nm CMOS process. Hence, capacitive coupling between closely spaced parallel metal lines and their resistive losses reduce the achievable IRR. Metal widths greater than minimum and stacked metal layers are used to minimize these effects.

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Fig. 12.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Digitally corrected quadrature LO generator.

E. Polyphase Filter Loading For a given stage in a multistage polyphase filter, the load is either the input impedance of a subsequent polyphase filter stage or the impedance driven at the polyphase filter output, which is normally a capacitive load in CMOS. The lower the impedance, the more severe the loading effect that causes loss in the polyphase filter. It is fortuitous that IRR is independent of the load of the polyphase filter; it depends on the pole frequency, which is not a function of the load impedance. As described earlier, wide-band image rejection requires a multistage polyphase filter. Proper design choices of the resistances minimize losses due to cascaded loading; i.e., the resistor values are tapered in a gradually increasing fashion to reduce loading effects on the previous stages. However, there is an unavoidable tradeoff between gain and noise; the last polyphase filter stage experiences the most loss; thus, overall noise is dominated by it when referred back to the input [11]. Therefore, lower resistor values in later stages lead to lower noise, but higher loss.

III. CIRCUIT IMPLEMENTATIONS Phase and amplitude errors in the quadrature LO signals, amplitude errors in the quadrature mixer transconductors, load mismatches, and phase-shift errors in the polyphase filter degrade IRR. In this design, quadrature LO amplitude error is not a concern because rail-to-rail digital signals are used, accurate

quadrature phase delay is derived using higher clock frequencies [12], the quadrature LO signals are digitally corrected, and efficient mixing reduces mixer loss. A. LO Generator The LO quadrature signals are generated by the digitally corrected quadrature LO generator (Fig. 12) using logical operations to create an accurate phase delay. For example, if an , and another clock runs fourfold faster, LO operates at , then its period is exactly 90 of a cycle of . If , its rising edge is delayed a clock is run at twice 90 from its falling edge assuming a 50% duty cycle. To avoid is significant loss of conversion gain, a half-period of used to generate precise quadrature LO signals. Using accurately defined quadrature LO signals, the mixer effectively mixes the LO with narrower pulses 90 apart to generate the in-phase and quadrature IF signals. Thus, the mixer , where is the fractional conversion gain is duty cycle of the LO signal. However, quadrature mismatch , or of the uncorrected LO signals ILO2X ( ) may cause both phase and amplitude mismatches in the generated quadrature LO signals. To overcome this concern, a logical AND operation is performed on ILO2X and the centeraligned ( or ) to generate OLO2X ( , or ). Hence, overall accuracy is ensured regardless of the inaccurate quadrature phase relationships of the uncorrected ILO2X quadrature signals (Fig. 13).

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Fig. 13.

Fig. 14.

Center alignment of 2

2f

P

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signals to avoid quadrature errors.

Masking operation of the DCQLO outputs by the 8

2f

Fig. 15.

Conventional quadrature generator block diagram.

Fig. 16.

Digital quadrature generator block diagram.

signals.

However, if the signals do not have exact 50% duty cycles, quadrature phase and pulsewidth errors result in a mixer quadrature gain error. To overcome this problem, another clock of eight times the LO frequency is used. Exploiting the accurate and reproducible period of this clock, the edges of the generated quadrature signals are masked. Hence, the allowable duty cycle varies from 50% by 6.25% (one half period of )—a 43.75%–56.25% duty cycle is tolerated for the signals. Signals generated from a divide-by-four circuit (e.g., the signals) generally have a much smaller duty cycle range than 43.75%–56.25%. The masking operation is depicted in Fig. 14. In addition to correcting duty cycle errors in the signals, the masking operation also corrects for rise- or fall-time mismatches in the signals because the masking pulses are identical for both edges owing to the repeatability of the clock periods. Clock frequencies higher than can also be used to increase pulsewidth; i.e., the mixer achieves higher conversion gain at the price of correcting smaller duty cycle errors. Accurate LO signals and the mask signal are generated by digital gates. The masking operation is done in the mixer to prevent errors before the mixing operation.

TABLE I MEASURED DIGITAL QUADRATURE GENERATOR PHASE NOISE

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Fig. 17.

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Simplified schematic of the MQM.

B. Digital Quadrature Generator and signals are generated The using a circuit block that divides the incoming frequency by and ) at the two and generates quadrature signals ( output. The most common technique for generating quadrature signals is using two latches that are triggered with positive and negative edges of the input clock [13], as shown in Fig. 15. Since it is a divide-by-two circuit, the input clock frequency is twice the output frequency. For high-frequency operation, source-coupled logic (SCL) CMOS latches are used in the divide-by-two circuit. The disadvantages of the SCL latch are its high noise, high current consumption, and low-frequency limit at which the circuit can operate. Also, it does not have rail-to-rail output and, therefore, a source–follower or other buffer that consumes more power is required to drive the next stage. To reduce power consumption and noise, a digital quadrature generator is used [14], [15]. It uses two latches and, like the typical quadrature generator, is triggered by the positive and negative edges of the input clock. The difference between the common and digital quadrature generators is in the latches. The block diagram of the static clocked-CMOS C MOS quadrature generator is shown in Fig. 16. The differential latch is a input to the positive level-sensitive latch that passes the output when clock (CLK) is high. When CLK is low, the input data is sampled on the falling edge of CLK and is held stable at the output for the entire phase due to the back-to-back inverter connection. When two of these latches are connected in a master–slave structure, as shown in Fig. 16, with one acting as a positive latch and the other as a negative latch, and with

the negative output of the second latch fed back to the positive input of the first latch, it generates I and Q signals at half the frequency of the input clock. The performance of this circuit is technology and powersupply dependent. Simulations of the static clocked-CMOS quadrature generator are performed with a 2-GHz input frequency and a 1.5-V power supply. The current consumption at 2 GHz is 259 A. The phase noise at different offset frequencies from the carrier is tabulated in Table I. In addition to low phase noise, this quadrature generator also has no low-frequency limitations. C. MQM The MQM is shown in Fig. 17. It exhibits minimum amplitude errors because it is has only one stage and is switched by rail-to-rail LO signals. Using digitally corrected LO signals and a single transconductance stage, quadrature errors in the MQM outputs are also greatly reduced. Hence, IRR is determined primarily by PPF component mismatches and parasitics. This is not the case for the conventional quadrature mixer. The two stages used in it introduce amplitude errors, and the uncorrected LO signals are subject to quadrature phase errors. Moreover, in cases where the LO switches are implemented using bipolar technology, the LO signals do not swing from rail-to-rail and, therefore, accurate generation of equal amplitudes is difficult. centered at 2.5 MHz, the PPF requires With large capacitors with large parasitics, especially in a 130-nm CMOS process with no poly–poly or metal–insulator–metal (MIM) capacitors; small resistor values are used for low-noise generation.

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Fig. 18.

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Five-stage RC polyphase filter component values.

D. Polyphase Filter The polyphase filter with its output frequency centered at 2.5 MHz is placed at the output of the MQMs. From Fig. 9, an ideal four-stage polyphase filter with a bandwidth ratio of 10.8 achieves an IRR of only 39.5 dBc; therefore, a five-stage polyphase filter is required in this design; its ideal IRR is 50.9 dBc. With the wide bandwidth and low IF, the required component values are large, which results in greater parasitics that introduce greater phase error. This is a major obstacle for realizing the low-IF architecture in WCDMA. Careful layout planning is required to reduce the effects of the parasitics. In this design, the resistor values for the first four stages are set at 2 k and at 4 k for the last stage. The resistor values are set at relatively small values to minimize the contributions to noise. Fig. 18 gives the RC values used in the polyphase filter. 1) Layout Considerations: Layout of the polyphase filter is critical to ensure good matching between the four phases in the PPF; moreover, careful layout reduces parasitics that cause undesirable phase shift deviations. For good matching, larger physical area and close proximity of components is required. However, parasitics also increase with area, thus, an optimum solution is required. To reduce the photolithographic resolution error imposed mismatches, component sizes need to be large. Thus, four 8-k resistors are laid out in parallel to realize the 2-k resistor. The width of the resistors is chosen as 5 m. The width cannot be chosen arbitrarily large because the cutoff frequency affected by the parasitic capacitance to ground and the resistance from the resistors may disturb the phase shift of the filter and limit the achievable IRR. Dummy resistors are placed at the two ends of the resistor banks to prevent over-etching of the end resistors relative to the other resistors. The values of the capacitors are necessarily relatively large because the resistor values are kept low to minimize loss and noise generation. Depending on how the layout is done, interconnects to the capacitors may be very long and their parasitic resistances and capacitances may degrade the desired phase shift and achievable IRR. A high-density metal–metal capacitor is used in the polyphase filter, as shown in Fig. 19. This capacitor trades off its quality factor ( ) against density. The top plate connection has five layers of stacked metal connected using vias. However, the bottom plate connection has only metal 3 and metal 5 connected together. To recover some of the , metal 4 and metal 5 are stacked together through vias with 2- m width running around the capacitors in parallel with the internal bottom plate connection (Fig. 20). Note that the layout of the capacitor is conservative considering process variations and mismatches. Cross-coupling and inter-digitized techniques are used throughout the layout, and

Fig. 19.

High-density metal–metal capacitor.

Q

Fig. 20. Layout method to improve the quality factor ( ) of a metal–metal capacitor.

dummy capacitors are placed around each capacitor. Of course, the area of the polyphase filter is larger than that using a more liberal layout style. IV. MEASUREMENT RESULTS Input matching circuits and a balun were used on a test board to provide the required input return loss and single ended to differential conversion for the RF signals. To boost the mixer gain for noise measurements, an off-the-shelf low-noise low-distortion line receiver was included on the test board. This line receiver converts differential outputs to a single-ended output and drives the 50- test equipment. Another reference line receiver for deembedding the on-chip test chip buffer and the on-board line receiver gain and noise are also included on the test board. The noise measurement is done using the -factor measurement [18]. The average total noise figure (NF) including the test buffer and external amplifier for six chips is measured at 13.6 dB . The noise of corresponding to a total noise factor the test buffer is measured at 5.9 nV/ Hz, and it is subtracted

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Fig. 23. Chip microphotographs of the active circuits and the five-stage polyphase filter implemented in 130-nm CMOS.

Fig. 21. Measured IRR centered at 2.5 MHz over the margined WCDMA bandwidth for a typical sample. Worst case IRR is 47.1 dBc at room temperature.

images and signals from ten chips for a single tone swept over the extended WCDMA bandwidth; the average IRR is 46.6 dBc and the worst case IRR is 44.5 dBc at 1.1 MHz. A typical chip was measured over temperature; its IRR was 44.8, 46.5, and 47.5 dBc at 20 C, 25 C, and 80 C, respectively. The chip consumes 23.4 mW, its NF is 10.8 dB, and its in-band input-referred third-order intercept point (IIP3) is 7 dBm. Chip photographs are shown in Fig. 23, and the active circuits and PPF occupy 4.1 mm and the total area is 8.96 mm . V. CONCLUSION The first image-rejection down-converter for use in a low-IF WCDMA receiver is successfully integrated in 130-nm CMOS. The low-IF approach achieves the same high level of integration noise, as direct conversion while avoiding the dc offset, and second-order nonlinearity problems. The technique is also applicable to other standards such as GSM and EDGE, wherein it avoids the use of ac coupling capacitors that degrade the BER because of their narrow channels (200 kHz). REFERENCES

Fig. 22. Measured output power levels of the desired and image signals for ten samples at room temperature obtained sweeping a single tone across the extended WCDMA bandwidth.

from the measured NF to obtain the actual image-rejection down-converter noise factor [15] (4) The noise factor of the mixer (5) is found to be 10.8 dB. The IRR of the down-converter is measured using an input signal modulated with a WCDMA source, and taking the difference between the signal channel power and image channel power. The IRR of a typical sample is shown in Fig. 21; worst case IRR at room temperature is 47.1 dBc. Fig. 22 shows

[1] J. Crols and M. S. J. Steyaert, “Low-IF topologies for high-performance analog front ends of fully integrated receivers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 3, pp. 269–282, Mar. 1998. [2] D. Manstretta, R. Castello, F. Gatta, P. Rossi, and F. Svelto, “A 0.18 m CMOS direct-conversion receiver front-end for UMTS,” in IEEE Int. Solid-State Circuits Conf., 2002, p. 240, 241, 463. [3] R. Gharpurey, N. Yanduru, F. Dantoni, P. Litmanen, G. Sirna, T. Mayhugh, C. Lin, I. Deng, P. Fontaine, and L. Fang, “A direct-conversion receiver for the 3G WCDMA standard,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 556–560, Mar. 2003. [4] S. J. Fang, A. Bellaouar, S. T. Lee, and D. J. Allstot, “An image rejection down-converter for low-IF receivers in 130 nm CMOS,” in IEEE Radio Frequency Integrated Circuit Symp., 2004, pp. 57–60. [5] S. Bedrosian, “Normalized design of 90 phase-difference networks,” IRE Trans. Circuit Theory, vol. CT-7, no. 6, pp. 128–136, Jun. 1960. [6] CTS Wireless Compon., Bloomingdale, IL, KFF6669A Ceramic Duplex Filter Datasheet, 2001. [Online]. Available: http:// www.ctscorp.com/components/datasheets/KFF6669A.pdf. [7] M. J. Gingell, “Single-sideband modulation using sequence asymmetric polyphase networks,” Elect. Commun. Mag., vol. 48, pp. 21–25, 1973. [8] D. Weaver, “Design of RC wide-band 90-degree phase-difference network,” Proc. IRE, no. 4, pp. 671–676, Apr. 1954. [9] W. Saraga, “The design of wide-band phase splitting networks,” Proc. IRE, no. 7, pp. 754–770, Jul. 1950. [10] R. Macario and I. Mejalie, “The phasing method for sideband selection in broadcast receivers,” Eur. Broadcast Union (E.B.U.) Rev.–Tech. Part, no. 181, pp. 119–125, Jun. 1980.

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[11] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 873–887, Jun. 2001. [12] T. Hornak, K. L. Knudsen, A. Z. Grzegorek, K. A. Nishimura, and W. J. McFarland, “An image-rejecting mixer and vector filter with 55-dB image rejection over process, temperature, and transistor mismatch,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 23–33, Jan. 2001. [13] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: PrenticeHall, 1998. [14] S. Fang et al., “Digital CMOS quadrature LO generator,” U.S. patent application. [15] S. Fang, “CMOS frequency conversion techniques for wideband code division multiple access,” Ph.D. dissertation, Dept. Elect. Eng., Univ. Washington, Seattle, WA, 2003. [16] MS Receiver Sensitivity in UTRA FDD Mode, 3GPP Tech. Specification: TSGW4#1(99)012, 1999. [17] O. Jensen et al., “RF receiver requirements for 3G W-CDMA mobile equipment,” Microwave J., vol. 43, pp. 22–46, Feb. 2000. [18] “Fundamentals of RF and microwave noise figure measurements,” Hewlett-Packard, Palo Alto, CA, Applicat. Note 57-1, Jul. 1983.

See Taur Lee (M’96) received the B.Sc. degree from the University of Malaya, Malaya, Malaysia, in 1993, the M.Eng. degree from the Nanyang Technological University, Singapore, in 1996, and the Ph.D. degree from the University of Washington, Seattle, in 2003. From 1993 to 1994, he was with National Semiconductor, Penang, Malaysia. From 1994 to 1995, he was a Research Assistant with the Nanyang Technological University, Singapore. Since 1996, he has been with the Institute of Microelectronics, Singapore, where he develops analog/RFICs for accelerometers, infrared proximity sensors, and Bluetooth transceivers. In 2001, he was an Intern with Texas Instruments (TI) Incorporated, Dallas, TX, where he was involved with digital transmitters for GSM. In 2002, he joined the Wireless Terminal Business Unit, TI, where he is involved with RFICs for cellular transceivers.

Sher Jiun Fang (S’90–M’93) received the B.Sc. degree from the State University of New York at Buffalo, in 1991, the M.Eng. degree from the National University of Singapore, Singapore, in 1996, and the Ph.D. degree from the University of Washington, Seattle, in 2003. From 1991 to 1992, she was with TriTech Microelectronics, Singapore, as an Analog Integrated Circuit Designer. In 1992, she joined the Institute of Microelectronics, Singapore, where she developed mixed-signal integrated circuits, g -C filters, up-converters for the Japanese personal handyphone system and intermediate frequency integrated circuits (IFICs) for WCDMA. In 2001, she interned with Texas Instruments (TI) Incorporated, Dallas, where she developed an image-rejection down-converter for WCDMA. In 2002, she joined the Wireless Terminal Business Unit, TI, where she is involved with RF integrated circuits (RFICs) for cellular transceivers.

Abdellatif Bellaouar (SM’96) was born in Algiers, Algeria, on November 22, 1959. He received the Doctorate degree from the University of Paul-Sabatier, Toulouse, France, in 1995. For over five years, he was a Research Associate Professor with the Very Large Signal Integration (VLSI) Group, University of Waterloo, Waterloo, ON, Canada. Since 1996, he has been with the RF Group, Wireless Terminal Business Unit, Texas Instruments Incorporated, Dallas, TX, where he is involved with RFIC development for cellular applications. In 2001, he became a Distinguished Member of Technical Staff (DMTS) with Texas Instruments Incorporated. He has authored or coauthored over 30 papers. He holds over 30 patents. His current research includes software radio transceivers, frequency synthesizers, and multimode radios.

David J. Allstot (S’72–M’72–SM’83–F’92) received the B.S. degree from the University of Portland, Portland, OR, the M.S. degree from Oregon State University, Corvallis, and the Ph.D. degree from the University of California at Berkeley. He has authored or coauthored approximately 200 papers. He has advised approximately 75 M.S. and Ph.D. graduates. Dr. Allstot is a member of Eta Kappa Nu and Sigma Xi. His professional service includes associate editor (1990–1993) and editor (1993–1995) of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING, Technical Program Committee (1990–1993) IEEE Custom Integrated Circuits Conference, Education Award Committee (1990–1993) IEEE Circuits and Systems Society, Board of Governors (1992–1995) IEEE Circuits and Systems Society, Technical Program Committee (1994–1997) IEEE International Symposium on Low-Power Electronics and Design, Mac Van Valkenberg Award Committee (1994–1996), IEEE Circuits and Systems Society, Technical Program Committee (1994–2004), IEEE International Solid-State Circuits Conference, Special Sessions chair (1995) IEEE International Symposium on Circuits and Systems, Executive Committee member and short course chair (1996–2000) IEEE International Solid-State Circuits Conference, co-chair (1996–1998) IEEE Solid-State Circuits and Technology Committee, Distinguished Lecturer (2000–2001) IEEE Circuits and Systems Society, and co-general chair (2002) IEEE International Symposium on Circuits and Systems. He was the recipient of several outstanding teaching and advising awards, the 1978 IEEE W. R. G. Baker Prize Paper Award, the 1995 IEEE Circuits and Systems Society Darlington Best Paper Award, the 1998 IEEE International Solid-State Circuits Conference Beatrice Winner Award, the 1999 IEEE Circuits and Systems Society Golden Jubilee Medal, and the 2004 Technical Achievement Award presented by the IEEE Circuits and Systems Society.

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A 0.6-V 1.6-mW Transformer-Based 2.5-GHz Downconversion Mixer With +5.4-dB Gain and 2.8-dBm IIP3 in 0.13-m CMOS Carsten Hermann, Marc Tiebout, Member, IEEE, and Heinrich Klar, Member, IEEE

Abstract—On-chip transformers are best suited to lower the supply voltage in RF integrated circuits. A design method to achieve a high current gain with an on-chip transformer operating in resonance is presented. The proposed method will be proven analytically and has been applied to a downconversion mixer. Thereby part of the overall gain of the mixer has been shifted from the RF input stage to the transformer. Thus, the power consumption has been reduced and, in spite of the low supply voltage, moderate linearity has been achieved. Although the transformer has a bandpass behavior, a 3-dB bandwidth of 900 MHz at a center frequency of 2.5 GHz has been achieved. The downconversion mixer has been realized in 0.13- m CMOS. It consumes 1.6 mW from a 0.6-V supply. A gain of 5.4 dB, a third-order intercept point of 2.8 dBm, an input 1-dB compression point of 9.2 dBm, and a single-sideband noise figure of 14.8 dB have been achieved.

+

Index Terms—CMOS, low power, low voltage, mixer, RF, transformer.

I. INTRODUCTION

W

ITH SCALING of technology, the supply voltage of modern digital processes becomes lower and lower, thus, the number of transistors between the supply rails needs to be reduced. One method that allows a lower supply voltage in mixers is to employ an on-chip transformer to establish a current coupling between the RF input stage and commutating stage (see Fig. 1) so the stacked arrangement of transistors as existing in the conventional Gilbert mixer is avoided. This approach has been applied in [1]–[3], but a high transconductance of the RF input stage is required to overcome the conversion loss of the on-chip transformer, which leads to a high power consumption. In this study, the transformer is operating in resonance, and care has been taken of the differential output and input impedance of the RF input stage and the commutating stage, respectively, resulting in a high current gain of the on-chip transformer [4]. Therefore, the transconductance of the RF input stage has been lowered. In this way, either the current consumption of the RF input stage and, thus, the power dissipation, can be reduced, or the effective gate–source voltage of the transistors of the RF input stage can be increased in favor

Manuscript received April 21, 2004; revised August 6, 2004. This work was supported by Infineon Technologies AG. C. Hermann and H. Klar are with the Institute of Computer Engineering and Microelectronics, Technical University of Berlin, 10587 Berlin, Germany (e-mail: [email protected]; [email protected]). M. Tiebout is with Corporate Research, Infineon Technologies AG, 81730 Munich, Germany (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840762

Fig. 1. Single balanced mixer circuits. (a) Conventional mixer with stacked transistors. (b) The RF stage and the commutating stage are current coupled with an on-chip transformer to avoid the stacked arrangement of transistors for lowering the supply voltage. L and L are the inductance of the primary and secondary windings of the transformer, respectively.

of a higher linearity [5]. To a certain degree, both the power consumption and linearity can be improved at the same time, as described in [4]. In Section II, a design method to achieve a high current gain of an on-chip transformer is presented. The proposed method has been applied to a downconversion mixer, described in Section III. The improvement of linearity and the reduction of power consumption due to the current gain of the transformer will be pointed out in Section IV. Section V gives insight into the layout, especially that of the on-chip transformer. The measurement results are presented in Section VI. Conclusions are presented in Section VII. II. DESIGN METHOD FOR HIGH-CURRENT GAIN OF ON-CHIP TRANSFORMERS On-chip transformers are best suited to lower the supply voltage in mixers. With proper design, they can also have a high current gain. For this purpose, the resonant frequency of the transformer has to be tuned to the desired signal frequency and care has to be taken of the source and the load impedance. A. Equivalent-Circuit Model of the On-Chip Transformer Fig. 2 shows the lumped equivalent-circuit model of the on-chip transformer introduced in [6]. The inductance and ohmic losses of the primary and secondary winding are modand . and eled with describe the capacitance between the windings and substrate. The capacitance between the primary and secondary . Substrate losses are modeled with winding is given by and . Each inductance is mutual coupled with

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and , as well as and , describe the ohmic losses and inductances of the primary and secondary winding, respectively, with

(1) The mutual inductance

is given by (2)

All parasitic capacitances are considered by and . for the Additional tuning capacitors are presented by primary winding and by for the secondary winding. If and are assumed to be small, they can be and are as follows: neglected for simplification, and Fig. 2. Lumped equivalent-circuit model of an on-chip transformer. Each inductance is coupled mutually with every other inductance resulting in six coupling coefficients.

and

(3)

To be more accurate, equivalent parallel elements of , , , and can be calculated [7] for a center frequency . Afterwards, the resulting equivalent parallel resistances can be merged with the source and the load resistance , respectively. These resistance equivalences hold only over a narrow range of frequencies centered around . C. Resonant Tuning of the On-Chip Transformer

Fig. 3. Small-signal equivalent-circuit model of an on-chip transformer with tuning capacitors C and C .

every other inductance, resulting in six coupling coefficients . These coefficients and all other elements of the lumped equivalent-circuit model of the on-chip transformer can be extracted from the geometric dimensions of the transformer with the software described in [6]. The extracted elements of the on-chip transformer used in the proposed mixer are nH, pH, , , fF, fF, fF, , , , , , and . B. Small-Signal Equivalent-Circuit Model for the On-Chip Transformer With Source and Load If the transformer is balanced and differentially driven, the and (refer to Fig. 2) are at a constant potential center taps and can, therefore, be tied to the ac ground. The resulting circuit is symmetric and can be halved. Fig. 3 shows a transformer . driven from a current source with the output resistance is the load resistance seen by the transformer’s output.

Resonant operating at the desired frequency is achieved by and , which, together with the adjusting the capacitors transformer’s parasitic capacitances and and the transand , comprise a double resonant former’s inductances network [8] with the two resonant frequencies and

(4)

with (5) are two positive integers with where and Optimal design [8] is given for and whereas

odd.

(6)

is the coupling coefficient of the transformer and

The transfer function obtained by calculating

(7)

of the circuit in Fig. 3 can be

(8)

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with

A high source resistance and a low load resistance result in and a high current gain. Considering the ohmic losses of the windings, (15) overestimates the achievable current gain. and to be roughly proIf we assume the ohmic losses portional to the inductances of the winding, we can define the coefficient (16)

(9) resulting in the maximal achievable current gain signal frequency as follows:

at the (10)

Neglect of the ohmic losses and of the windings gives , as shown in (11) at the bottom of the transfer function this page. With (4), (6), and (11),

(12) is the turn ratio and is a constant to get a degree whereas and , as well as of freedom to independently specify and , we can compute an approximation (13) for the maximal achievable current gain at the signal frequency , which after some effort, results in

(14)

Since is expected to be small compared with reasonable , (14) reduces to

, with

(15)

H (s) =

which can be extracted from the geometric dimension of the transformer with the software described in [6] or with that in [9]. nH is realistic for the used Infineon A value down to and technology without making the parasitic capacitances too high and, accordingly, the self-resonant frequency of the transformer too low, compared with the desired signal frequency of 2.5 GHz for the proposed mixer. with As an example, we examine a 3 : 1 transformer , , nH, and nH at a signal GHz. From (6) and (12), we obtain frequency of , nH, fF, and pF. k and , (10) gives a current With , whereas (15) predicts a current gain gain of . For lower ohmic losses nH , a of higher signal frequency or higher inductances (15) are more accurate, while a higher turn ratio worsens the prediction of (15). However, what we obtain from (15) is that, with careful design of the transformer, a high current gain can be achieved. We return to this point in Section V when the layout of the proposed mixer is described. is equal to so that the maximal current In (6), gain in (15) is limited by the turn ratio of the transformer. With consideration of the ohmic losses, the gain is even lower. With , the maximal current gain can be higher than the turn ratio at the expense of a smaller bandwidth. The resulting coupling coefficient is different from (6). , , and can be found due to a simple numeric maximizing algorithm using (8)–(10), in which the ohmic losses of the for , windings are taken into account. In the example above ( nH, nH, GHz, k , ) and with fF, pF, and from (10), we obtain , and with nH, . This example shows that a high is we get not essential to achieve a high current gain, when operating the transformer in the resonant mode. Fig. 4 shows the current gain and over frequency for the case for nH using (8)–(10). The 3-dB bandwidth is 850 and 400 MHz, respectively. III. CIRCUIT DESCRIPTION The proposed downconversion mixer is depicted in Fig. 5. The RF input stage and commutating stage are coupled with an on-chip transformer. The center taps of the primary and

p

kR L L s L L C C R R (10 k )s + L L (C R + C R )(1 0 k )s +[(L C + L C )R R

+

L L (1 0 k )] s

+(

LR

+

L R )s + R R

(11)

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and shows the mixer during the positive phase of the LO. are off and, hence, they are omitted for simplification. Due to symmetry, only one-half of the circuit has to be considered. Fig. 7 shows the small-signal equivalent model of the half-circuit. The transconductances and differential output resistances are denoted with and , respectively. of the transistors A. RF Input Stage

Fig. 4.

Current gain over frequency for two different tuning methods. With , a high current gain can be achieved. With , the 3-dB bandwidth is higher.

L C >L C

L C =L C

and of the RF input stage transform the The transistors differential input voltage into a differential current. The biasing and (not shown in Fig. 5) is performed with a resisof tive voltage divider, which also terminates the input to enable reliable measurements in a 50- system, although deteriorating the noise figure. To improve the IIP3 and to save the voltage drop across the current source, the RF input stage consists of a grounded-source pair rather than a differential input pair with constant tail current [10], [11]. The common mode rejection is performed by the on-chip transformer and, in conjunction with and , the transformer isolates the the cascode transistors RF input stage from the commutating stage. B. Current Gain of the On-Chip Transformer As described in Section II, the current gain of the on-chip transformer depends on the source and load resistance seen by the transformer’s ports. A high source resistance and a low load resistance will increase the current gain. Therefore, the differential output resistance (17) of the RF input stage (see Fig. 7) has to be high. At several gigahertz and with short-channel low-voltage devices, this can be challenging even by the use of a cascode transistor. To make the differential input resistance

Fig. 5. Circuit of the proposed downconversion mixer. The RF input stage and commutating stage are current coupled with an on-chip transformer. The and to resonate at the signal frequency. transformer is tuned with

C

C

(18) of the commutating stage as low as possible, the transconduchas to be high. Therefore, either tance of have to be wide or a high drain current for would be necessary. Wide transistors would load the local oscillator (LO), and a high drain current would increase the power consumption and the voltage drop across the output resistors, thus, a tradeoff has to be made. However, with proper designed RF input and commutating stage, in the current domain, the transformer contributes to the overall gain, as shown in Section II, thus making and to imit possible to reduce the transconductance of prove their linearity [5] or their current consumption, as will be discussed in Section IV.

Fig. 6. Simplified circuit of the mixer during the positive phase of the LO high and low). For simplification, only one-half of the ( circuit is considered.

LO+ =

LO0 =

secondary windings are connected to the positive and negative supply voltages, respectively. Therefore, in the RF input stage, only two transistors and, accordingly, in the commutating stage, only one transistor and one resistor are between the supply rails, making the low supply voltage of 0.6 V possible. Fig. 6

C. Commutating Stage of the commutating stage are biased The transistors near threshold voltage. Therefore, their effective gate source voltage is reduced, their transconductance and their current efare increased, and the switching time and, thus, ficiency , are reduced [10]. A small LO power is the noise of possible [12], keeping in mind that the phase noise of the LO is proportional to the reciprocal of the LO power. For low flicker

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LO+ =

LO0 =

g

r

Fig. 7. Simplified small-signal equivalent model of the mixer during the positive phase of the LO ( high and low). and are the . is the positive input voltage at the radio frequency, is the positive output transconductances and differential output resistances of the transistors voltage at the intermediate frequency. is the on-chip transformer with coupling coefficient .

N v

X

noise, should be wide, but a great width would present a great capacitive load to the LO and, therefore, increase the power consumption. A good compromise has been found for a width of 100 m. IV. IMPROVEMENT OF LINEARITY AND POWER CONSUMPTION of the commutating stage Assuming the transistors acting as perfect switches, the main contribution of distortion is and of the RF input stage [13]. In from the transistors [14], the third-order intercept point (IIP3) of the mixer is given by (19) and, thus, in first approximation, proportional to the effective gate–source voltage , where is the drain curis the transconductance, and is a transistor constant. rent, and of Therefore, the transconductance of the transistors the RF input stage can be divided by the current gain of the on-chip transformer. Due to coreless coupling between the primary and secondary windings, there is no harmonic distortion induced by the transformer. If an inherent current gain of (simulated) of the 7 : 2 transformer is assumed, (19) results in an improvement of dB

(20)

for the IIP3, while the drain current is kept constant and the square law of the MOS transistor is assumed. Due to the low supply voltage of 0.6 V, only a small effective gate–source voltage is possible. The smaller the effective gate–source voltage is, the further the transistor is operating in moderate inversion, where the drain current has an exponential characteristic and exhibits greater third-order terms. Thus, an increase has a stronger positive impact on the IIP3. With the of proposed method, a greater IIP3 improvement than predicted in (20) can, therefore, be achieved. The transconductance and and can also be decreased at the same drain current of time, thus improving both linearity and power consumption. V. LAYOUT The chip was realized in an Infineon 0.13- m standard lowcost CMOS process with six metal layers. The die consumes an

k

v

area of 1 mm 1 mm. For the symmetrical 7 : 2 transformer, the upper two thick metal layers were used in parallel and were merged with via bars to lower the ohmic losses of the windings. The ohmic losses and parasitic capacitance of the windings are determined by their geometric dimensions. Wider windings reduce ohmic losses, but increase the parasitic capacitance to the substrate. Metal layers in parallel also reduce ohmic losses, but while connecting the lower layers to the coil, the capacitance roughly increase with the reciprocal of the distance from the lowest layer to the substrate. There has to be made a tradeoff between the increase of inductance and the reduction of ohmic losses to achieve a high current gain on the one hand, and to minimize the parasitic capacitances of the on-chip transformer to result in a sufficient high self-resonant frequency on the other hand. A greater radius and a higher number of turns can relax the problem. Whereas this is very important for the primary winding, the situation for the secondary winding is more relaxed. Since an in the vicinity of some picofarad additional capacitance needs to be connected in parallel to the secondary, this winding can be made wider while slightly reducing the additional capacitance. To achieve a high current gain of the on-chip transformer, a high turn ratio is necessary, requiring great primary and small secondary inductances, respectively. However, if the primary winding is too big, it leads to a high parasitic capacitance between the metal winding and substrate. To meet (7) and (12), this results in a small tuning capacitor. Due to the ohmic losses in the substrate, the parasitic capacitance of the primary winding has a low quality factor compared with the tuning capacitor. Therefore, the overall quality factor of the primary winding decreases with greater dimensions of the winding and the current gain begins to drop at a certain turn ratio. Furthermore, a big primary winding increases the area consumption of the on-chip transformer. Designing the on-chip transformer for a high turn ratio by making the secondary winding too small reduces the magnetic coupling between the primary and secondary windings and the current gain again begins to drop at a certain turn ratio. Turn ratio and size of the on-chip transformer, therefore, have to be chosen to enable a sufficiently high magnetic coupling between the primary and secondary windings on the one hand and, on the other hand, to keep the impact of the parasitic capacitance of the primary winding small enough to not affect the quality

HERMANN et al.: 0.6-V 1.6-mW TRANSFORMER-BASED 2.5-GHz DOWNCONVERSION MIXER

Fig. 8. Two-tone output spectrum with fundamentals at 10 and 11 MHz and third-order intermodulation products at 9 and 12 MHz. supply voltage: 0.6 V, gain: 5.4 dB, RF: 2.51 and 2.511 GHz, LO: 2.5 GHz 1 dBm.

+

493

Fig. 10. Conversion gain over frequency, supply voltage: 0.8 V, gain: 10.2 dB, LO: 1 dBm, IF: 10 MHz. The 3-dB bandwidth is 900 MHz.

+

0

0

+

1

+

Fig. 11. =f noise, supply voltage: 0.6 V, gain: 10.4 dB, LO: 2.5 GHz 1 dBm. The flicker noise corner frequency is approximately 85 kHz.

0

Fig. 9. IIP3 curves, supply voltage: 0.6 V, gain: 5.4 dB, RF: 2.51 and 2.511 GHz, LO: 2.5 GHz 1 dBm. The input referred IP3 is 2.8 dBm.

0

0

factor of the primary winding. An inner radius of 100 m and a turn ratio of 7 : 2 have been found to be optimal for the on-chip transformer of the proposed mixer. The outer radius is 164 m. VI. MEASUREMENT RESULTS with The input ports of the mixer are matched to 50 on-chip resistors and are biased externally. External 180 power splitters and combiners have been employed to convert the single-ended signals into differential signals and vice versa. All losses due to cables and power splitters/combiners, and all signal generators and measurement equipment, were calibrated before measurement. The output port of the mixer is buffered by the use of on- and off-chip operand matched to 50 ational-amplifier impedance transformers. The nonlinearity and noise of the impedance transformers adversely affect the measurement results. The chip has been measured at supply voltages of 0.6 and 0.8 V, and with gain adjusted to approximately 5, 10, and 15 dB (only for 0.8 V). The gain has been adjusted externally due to the bias potential of the RF input stage. The IIP3 has been measured by feeding RF signals at 2.51 and 2.511 GHz and an LO signal at 2.5 GHz into the mixer. Figs. 8 and 9 show

Fig. 12.

Die photograph of the downconversion mixer.

the output spectrum and IIP3 curves, respectively. The conversion gain over frequency is shown in Fig. 10. The 3-dB bandwidth ranges from 2.1 to 3.0 GHz measured at a constant IF at 10 MHz. The single-sideband (SSB) noise figure has been measured at 2.51-GHz RF input frequency and 2.5-GHz LO frequency using the Agilent E4448A spectrum analyzer and a low-noise pre-amplifier. The flicker noise corner frequency is approximately 85 kHz (Fig. 11) For measuring, the die (Fig. 12)

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with the formulas given in (4)–(7) and (12) or with a simple numeric maximizing algorithm. Maximal current gain will be achieved when the ohmic losses in the transformer windings and the load resistance seen by the transformer are minimal and when the source resistance of driving current source is high. It has been shown that both the IIP3 and power consumption of the mixer can be improved due to the current gain of the transformer. The use of on-chip transformers is also best suited to lower the supply voltage. REFERENCES

Fig. 13.

Die bonded to the PCB and mounted on a metal block.

TABLE I MEASUREMENT RESULTS

[1] L. A. MacEachern, E. Abou-Allam, L. Wang, and T. Manku, “Low voltage mixer biasing using monolithic integrated transformer de-coupling,” in Proc. IEEE Int. Circuits Systems Symp., vol. 2, May 30–Jun. 2, 1999, pp. 180–183. [2] J. R. Long and M. C. Maliepaard, “A 1 V 900 MHz image-reject downconverter in 0.5 m CMOS,” in Proc. IEEE Custom Integrated Circuits, May 16–19, 1999, pp. 665–668. [3] M. Tiebout and T. Liebermann, “A 1 V fully integrated CMOS transformer based mixer with 5.5 dB gain, 14.5 dB SSB noise figure and 0 dBm input IP3,” presented at the Eur. Solid-State Circuits Conf., Sep. 16–18, 2003. [4] C. Hermann, M. Tiebout, and H. Klar, “A 0.6 V 1.6 mW transformer based 2.5 GHz downconversion mixer with 5.4 dB gain and 2.8 dBm IIP3 in 0.13 m CMOS,” presented at the IEEE Radio Frequency Integrated Circuits Symp., Jun. 6–8, 2004. [5] A. A. Abidi, G. J. Pottie, and W. J. Kaiser, “Power-conscious design of wireless circuits and systems,” Proc. IEEE, vol. 88, no. 10, pp. 1528–1545, Oct. 2000. [6] D. Kehrer, W. Simbürger, H.-D. Wohlmuth, and A. L. Scholtz, “Modeling of monolithic lumped planar transformers up to 20 GHz,” in IEEE Custom Integrated Circuits Conf., May 6–9, 2001, pp. 401–404. [7] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998, pp. 91–93. [8] A. C. M. de Queiroz, “Generalized LC multiple resonant networks,” in IEEE Int. Circuits Systems Symp., vol. 3, May 26–29, 2002, pp. III519–III-522. [9] A. M. Niknejad, “Modeling of passive elements with ASITIC,” in IEEE Radio Frequency Integrated Circuits Symp., Jun. 2–4, 2002, pp. 303–306. [10] M. N. El-Gamal, K. H. Lee, and T. K. Tsang, “Very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications,” Proc. Inst. Elect. Eng., vol. 149, no. 56, pp. 355–362, Oct.–Dec. 2002. [11] S. Wu and B. Razavi, “A 900-MHz/1.8-GHz CMOS receiver for dualband applications,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2178–2185, Dec. 1998. [12] P. J. Sullivan, B. A. Xavier, and W. H. Ku, “Low voltage performance of a microwave CMOS Gilbert cell mixer,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1151–1155, Jul. 1997. [13] L. A. MacEachern and T. Manku, “A charge-injection method for Gilbert cell biasing,” in IEEE Canadian Electrical and Computer Engineering Conf., vol. 1, May 24–28, 1998, pp. 365–368. [14] Q. Huang, F. Piazza, P. Orsatti, and T. Ohguro, “The impact of scaling down to deep submicron on CMOS RF circuits,” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1023–1036, Jul. 1998.

+

has directly been bonded to the printed circuit board (PCB) and the PCB has been mounted on a metal block (Fig. 13). At 0.6-V supply voltage, a gain of 5.4 dB, an IIP3 of 2.8 dBm, an input referred 1-dB compression point of 9.2 dBm, and an SSB noise figure of 14.8 dB have been achieved. Depending on the adjusted gain of the mixer at a supply voltage of 0.8 V, a gain up to 15.0 dB, an IIP3 up to 4.3 dBm, a 1-dB compression point up to 6.5 dBm, and a noise figure as low as 8.8 dB is possible. Table I summarizes the measurement results. VII. CONCLUSION A design method to achieve a high current gain with an on-chip transformer has been presented and has been applied to a downconversion mixer. The on-chip transformer is operating in resonant mode and has been tuned with extra on-chip capacitors. Whether to achieve a wide bandwidth or to optimize for maximal current gain, the tuning capacitors can be estimated

0

Carsten Hermann received the Diploma degree in electrical engineering from the Technical University of Berlin, Berlin, Germany, in 1996, and is currently working toward the Ph.D. degree in electrical engineering at the Technical University of Berlin. He was a Software Engineer for Siemens, Bocholt, Germany, where he was involved with the development of software for corded phones. His current research interests include low-power low-voltage low-noise amplifiers and mixers.

HERMANN et al.: 0.6-V 1.6-mW TRANSFORMER-BASED 2.5-GHz DOWNCONVERSION MIXER

Marc Tiebout (M’90) was born in Asse, Belgium, in 1969. He received the M.S. degree in electrical and mechanical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1992. In 1992, he joined Corporate Research and Development, Microelectronics, Siemens AG, Munich, Germany, where he was involved with the design of analog integrated circuits (ICs) in CMOS and BiCMOS technologies. In 1997, he became involved with the design of RF devices and building blocks in submicrometer CMOS technologies. From 1999 to 2001, he was with Wireless Products, Infineon Technologies AG, Munich, Germany, where he was involved with RF CMOS circuits for wireless communications transceivers. He was the Workpackage Leader for the CMOS portion of the European Commission (EC)-funded LEMON project (single-chip universal mobile communication system (UMTS) transceiver). Since 2001, he has been with Corporate Research, Infineon Technologies AG, Munich, Germany. He has authored or coauthored numerous RF CMOS publications. He holds numerous patents. His research is focused on low-power high-frequency circuits and transceivers in deep-submicrometer CMOS.

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Heinrich Klar (M’97) received the Dipl.-Ing. and Dr.-Ing. degrees from the Technical University of Munich, Munich, Germany, in 1972 and 1976, respectively. In 1976, he joined the Research Laboratories, Siemens AG, Munich, Germany, where he was engaged in the research development of circuits for transmission and processing of analog and digital signals, as well as the design of standard MOS ICs. He currently a Professor with the Institute of Computer Engineering and Microelectronics, Technical University of Berlin, Berlin, Germany. His research interests are ICs for digital and analog signal processing, especially spiking neural networks, high-speed high-resolution analog/digital converters, and RF CMOS circuits.

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Broad-Band MMICs Based on Modified Loss-Compensation Method Using 0.35-m SiGe BiCMOS Technology Ming-Da Tsai, Student Member, IEEE, Chin-Shen Lin, Student Member, IEEE, Chun-Hsien Lien, Student Member, IEEE, and Huei Wang, Senior Member, IEEE

Abstract—Using the concept of loss compensation, novel broad-band monolithic microwave integrated circuits (MMICs), including an amplifier and an analog multiplier/mixer, with LC ladder matching networks in a commercial 0.35- m SiGe BiCMOS technology are demonstrated for the first time. An HBT two-stage cascade single-stage distributed amplifier (2-CSSDA) using the modified loss-compensation technique is presented. It demonstrates a small-signal gain of better than 15 dB from dc to 28 GHz (gain-bandwidth product = 157 GHz) with a low power consumption of 48 mW and a miniature chip size of 0.63 mm2 including testing pads. The gain-bandwidth product of the modified loss-compensated CSSDA is improved approximately 68% compared with the conventional attenuation-compensation technique. The wide-band amplifier achieves a high gain-bandwidth product with the lowest power consumption and smallest chip size. The broad-band mixer designed using a Gilbert cell with the modified loss-compensation technique achieves a measured power conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz, which is the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz, and the measured low-frequency noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. The mixer performance represents state-of-the-art result of the MMIC broad-band mixers using commercial silicon-based technologies. Index Terms—Attenuation compensation, distributed amplifier (DA), Gilbert cell, monolithic microwave integrated circuits (MMICs), mixer, SiGe BiCMOS.

I. INTRODUCTION

B

ROAD-BAND monolithic microwave integrated circuits (MMICs) are essential components for various wide-band applications. Most manufacturers of broad-band components have obtained wide bandwidths by using advanced technoloand . Also, the multiplication or mixing gies with high circuit is an important building block in signal-processing and communication systems. The broad-band analog multiplier is used for the modulation of high-speed data transmitted at microwave or millimeter-wave carrier frequencies [1], and a Manuscript received April 19, 2004; revised August 12, 2004. This work was supported in part by the National Science Council under Grant 93-2752-E-002002-PAE, Grant 93-2219-E-002-016, and Grant 93-2219-E-002-024. The authors are with the Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840766

key component in the broad-band correlator for the radio telescope system of array for microwave background anisotropy (AMiBA) [2]. In this paper, we demonstrate two broad-band circuits based on the attenuation-compensation concept [3], which is extended from the common collector–common emitter (CC–CE) configuration (or mentioned as the Darlington configuration [30]–[32]). We proposed to add a series inductor to the CC–CE configuration, called the modified loss-compensation technique, to improve the high-frequency performance. The proposed technique can achieve higher gain-bandwidth product than the conventional attenuation compensation technique [3]. The circuit performance using this technique also rivals those circuits fabricated in more advanced processes [1], [6], [8], [9]. One of the developed circuits is an HBT broad-band amplifier. We proposed and realized a miniature low-power HBT cascaded single-stage distributed amplifier (CSSDA) based on the modified loss-compensation technique for the first time. From our simulations, the broad-band amplifier using the modified loss-compensation technique can improve gain-bandwidth product by 68% compared with the conventional attenuation compensation technique presented in [3]. Another broad-band circuit is an analog multiplier/mixer [29]. Based on the advantage of the modified loss compensation, we have also demonstrated a wide-bandwidth 0.1–23-GHz SiGe BiCMOS analog multiplier/mixer using the Gilbert of the transconductance multiplier cell. Although the device used in the design is approximately 57 GHz, which is significantly lower than that of the GaAs, SiGe, and InP HBT device, our LC ladder matching networks and modified loss-compensation method resulted in high gain and wide bandwidth for this chip. This MMIC chip, even without RF and IF amplifiers can achieve the highest gain-bandwidth product of 204 GHz among the previous reported HBT-based analog active mixers. In Section II, the MMIC process will be described. The modified loss-compensation technique will be introduced in Section III. Section IV will present circuit design and simulation results. Finally, experimental data will be demonstrated in Section V. II. DEVICE CHARACTERISTICS AND MMIC PROCESS The MMICs reported in this paper are based on a 0.35- m three-poly three-metal (3P3M) SiGe BiCMOS process. Three

0018-9480/$20.00 © 2005 IEEE

TSAI et al.: BROAD-BAND MMICs BASED ON MODIFIED LOSS-COMPENSATION METHOD

Fig. 1. Small-signal equivalent- model including the substrate parasitics (R and C ).

PARAMETERS

TABLE I SMALL-SIGNAL EQUIVALENT- MODEL 13.9 m SINGLE-EMITTER HBTs

OF THE

0.3

2

497

(a)

OF THE

metal layers are available for inter-connection. Metal–insulator–metal (MIM) capacitors are provided with a unit capacitance of 1 fF m . The substrate conductivity is approximately 10 S/m. The HBT dc-current gain is approximately 160 at a current kA/cm . The common-emitter breakdown density of voltage of high-speed npn devices is 2.5 V. The 0.3 13.9 m single-emitter HBTs used in this design achieve an of 79 GHz and an of 57 GHz at a collector current of 4 mA of 1.5 V. The small-signal and collector–emitter voltage equivalent- model including the substrate parasitics ( and ) is shown in Fig. 1 and the parameters are shown in Table I. III. MODIFIED LOSS-COMPENSATION TECHNIQUE For broad-band applications, the most popular approach is to emulate the circuit as an artificial transmission line. The conventional distributed amplifier (DA) accommodates two artificial transmission lines (formed by LC ladders) in conjunction with active devices connected in parallel. Each stage can be considered as a T-section network amplifier connected in parallel. Even though the parasitic capacitance of the active device is absorbed into the LC ladder, the input intrinsic series parasitic resistance of the transistor would result in high signal loss in the artificial transmission line. Compared with DA designs using field-effect transistor (FET) devices, the gain-bandwidth product of the HBT DA is mainly limited due to the intrinsic base resistance . As can be observed in the HBT model described in Section II, the intrinsic base resistance of the HBT is approximately 30 , which is significantly higher than the input intrinsic series parasitic resistance of FETs. Moreover, the inductive elements in the standard monolithic low-resistivity silicon process for the LC ladder result in a lower quality ( ) factor and, thus, a higher power loss with

(b) Fig. 2. (a) Modified loss-compensation configuration constructed by a Darlington cell with series inductor (L ). (b) Simplified model of modified loss-compensation configuration.

increasing operation frequency compared with those in III–V, silicon-on-insulator (SOI), or SiGe-HBT processes. In addition, the termination resistance of the LC ladder for minimizing signal reflection also leads to signal loss. Therefore, an effective method to compensate the power loss and improve the highfrequency gain is desired. The dotted box in Fig. 2(a) presents the Darlington configuration, which is a common-collector stage followed by common-emitter stage , as mentioned in some of the recent literature [30]–[32], which is slightly different from the very early description of the Darlington pair [33]. The common-collector device can actively transforms the input capacitive looking of to negative impedance at the input, which results in positive reflection coefficient. Therefore, the Darlington configuration can compensate for part of the loss in the input transmission line. However, the positive reflection coefficient cannot compensate the entire signal loss. We then proposed to add an input series inductor in front of the conventional Darlington configuration, called the modified loss-compensation configuration, as shown in Fig. 2(b). The input impedance of the modified loss-compensation cell, considering intrinsic base resistance and base–emitter capacitance , can be derived from the simplified model in Fig. 2(b) as (1)

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Fig. 3. Input reflection coefficient (S ) of the modified loss-compensation configuration with increasing series inductance (L ).

Fig. 5. Forward transmission coefficient (S ) of the modified loss-compensation configuration with increasing series inductance (L ). TABLE II COMPARISON OF THE REPORTED HBT DA. ATTENUATION-COMPENSATION TECHNIQUE (ACT)

Fig. 4. Input reflection coefficient (S ) of the modified loss-compensation configuration on the Smith chart from 12 to 27 GHz with increasing series inductance (L ).

where

which is the input admittance of the Darlington pair without the series inductance . The input reflection coefficients in decibels are plotted in Fig. 3 by varying from 0 to 400 pH with mS, , fF, and fF, as listed in Table I. It is observed that rises with an increase in the input series inductance . The results are also plotted on the compressed Smith chart shown in Fig. 4. With the series inductance increasing, the location of the input impedance

on the Smith chart would move along a constant resistance (constant-r) circle. Since the negative resistance is obtained from the actively impedance transformation through device , the location of the input impedance on the Smith chart is out of the unity circle . The input series inductance makes the impedance move along a constant-r circle on the Smith chart, and transforms the reflection coefficient to an even higher value. The required negative-impedance condition can be derived from (1) by neglecting the base–collector capacitance as (2) According to (2), the condition to have negative impedance is , intrinsic base resisdetermined by the transconductance tances and , and parasitic base–emitter capacitances and . With proper device size and biasing condition, the highest frequency for loss compensation will be (3)

TSAI et al.: BROAD-BAND MMICs BASED ON MODIFIED LOSS-COMPENSATION METHOD

499

Fig. 6. Small-signal equivalent-circuit model of an HBT n-CSSDA.

Fig. 7. Circuit schematic of the proposed modified loss-compensated HBT two-stage cascaded single-stage distributed amplifier (2-CSSDA).

According to (3), there is a tradeoff between ' , ' , and . While reducing device size or collector current leads to reduce should be increased. However, it comes with ', the expense of increasing intrinsic base resistance ' and, thus, sacrificing the power gain. The significant improvement of forward transmission coefficient is shown in Fig. 5. By a proper selection of the input series inductance, the modified loss-compensation configuration could achieve higher gain and wider bandwidth. In Section IV, a wide-band amplifier and an analog multiplier/mixer will be described using the LC ladder matching with this modified loss-compensation technique. IV. CIRCUIT DESIGN A circuit topology to provide high gain with a minimum number of gain stages is attractive because it can save power consumption and chip area. A modified loss-compensated broad-band amplifier is described, and is then followed by a broad-band LC ladder matching analog multiplier/mixer using the same concept. A. Modified Loss-Compensated HBT CSSDA In the past, the conventional HBT DA based on the attenuation-compensation technique was presented [3]. An HBT DA

with feedback resistors in the attenuation compensation cell was also demonstrated in [4]. An HBT CSSDA was simulated and shown in [5] without measurement results. The highest frequency of an HBT DA using a very advanced SiGe HBT and of all better than technology, which provides 200 GHz, was shown in [6]. The reported HBT wide-band DAs to date with or without attenuation compensation were demonstrated with large chip size and high power consumption [3], [4], [6]–[9], as shown in Table II. Here, we present a miniature and low-power HBT CSSDA using the modified loss-compensation technique. The design methodology of a CSSDA using HBTs is similar to that using the FETs [26], [27]. The main differences in their performances are determined by the inherent characteristics of the FET devices. In general, an HBT device has the characteristics of high input parasitic resistance and, thus, leads to a poor DA performance compared with an FET DA. Due to the lossy input characteristics of the HBT device, the attenuations of the input and inter-stage transmission lines are major limiting factors of gain-bandwidth performance in an HBT CSSDA. The schematic of the simplified small-signal equivalent-circuit model of an HBT -stage cascaded single-stage distributed amplifier ( -CSSDA) is shown in Fig. 6, which is similar to an FET CSSDA [27], . If a signal voltage but includes intrinsic base resistance is applied to the HBT -CSSDA, the total current at wave

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the output of the amplifier considering the -stage voltage and base–emitter division of intrinsic base resistance is given by (4) capacitance (4) Therefore, the available gain for an HBT -CSSDA can be derived as (5)

where is the internal characteristic impedance, represents the base line characteristic impedance of the first stage, stands for the collector line characteristic impedance and of the last stage. It also shows that available gain is attenuation owing to the intrinsic base by a factor of resistance . Fig. 7 is the schematic of our HBT CSSDA using the modified loss-compensation technique. The modified loss-compensation , resistor , transistors cell consisting of the inductor , and is applied to compensate the input and interstage transmission lines. The inter-stage artificial transmission lines are formed by coupling the output of the first stage and the input of the second stage. Although the modified loss-compensation technique can be applied to the input of the gain cell, the output compensation is also important for the inter-stage and output artificial transmission lines in the design of a CSSDA. In this design, we use the cascode cell to increase the output shunt resistance presented to the inter-stage and output transmission lines and, thus, result in lower effective and attenuation. Furthermore, the common-base transistors of the cascode cell can reduce the Miller capacitance of and and increase the bandwidth. The base transistor and are fed biases of the common-base transistors through self-biasing resistors and accompanied with and . The input base voltage the bypass capacitors of the input is supplied through the matching resistor artificial transmission line and bypass capacitors, which prevent currents through the matching resistor. The base voltage of the second stage is directly fed into the inter-stage artificial transmission line to avoid blocking low-frequency signals. The and , as shown in Fig. 7, are 2 and supply voltage 2.5 V, and the currents are 3.5 and 15 mA, respectively, and consume a total dc power of 44.5 mW. In this design, the series inductors of modified loss-comand . The simulated small-signal pensation cells are power gain of the complete amplifier is shown in Fig. 8 with from 0 to various inductance values 400 pH. A significant improvement can be observed by a proper selection of series inductance. As the inductance is 0 pH, the design condition is identical to the conventional attenuation compensation technique described in [3]. For a flat small-signal gain over frequency, the optimal series inductance is 400 pH and the 3-dB bandwidth can be improved from 16 to 27 GHz. The results indicated a 68% improvement in the

Fig. 8. Small-signal gain (S ) of the modified loss-compensated 2-CSSDA =L ). with increasing series inductance L (= L

Fig. 9. Input return loss of the modified loss-compensated 2-CSSDA with increasing series inductance L (= L =L ).

Fig. 10. Chip micrograph of the modified loss-compensated HBT 2-CSSDA (size: 0.956 mm 0.657 mm).

2

gain-bandwidth product using the modified loss-compensation technique. The input and output return losses with various series inductance are illustrated in Figs. 8 and 9, which are better than 8 dB with various series inductance values. The chip microphotograph of the HBT CSSDA is shown in Fig. 10. The chip size is only 0.63 mm . The miniature chip size

TSAI et al.: BROAD-BAND MMICs BASED ON MODIFIED LOSS-COMPENSATION METHOD

Fig. 11.

501

Circuit schematic of the SiGe BiCMOS broad-band mixer/multiplier.

is achieved due to only two-stage design, which can perform high gain and wide bandwidth using the modified loss-compensation technique. B. Broad-Band Analog Multiplier and Mixer The circuit schematic of this broad-band multiplier/mixer is shown in Fig. 11. The circuit can be divided into the: 1) pre-distortion circuit; 2) dc-bias circuit; 3) output buffer; 4) Gilbert-cell core; 5) input LC ladder matching network; and 6) modified loss-compensation circuit. The Gilbert-cell configuration is selected for the double-balance mixer design, which offers high conversion gain and improved spur performance in a very compact size [10]. The RF signal enters a lower amplifier formed by the emitter coupled pair. The local-oscillator (LO) signal enters an upper cross-coupled quad of devices through the pre-distortion circuit. In order to improve the bandwidth, broad-band impedance matching is necessary to reduce the signal reflection. Broad-band impedance matching was achieved by an equivalent 50- resistor shunted with the high-input impedance of the input transistor in previously reported design [10], but the capacitive-looking impedance of the emitter couple pairs (ECPs) at the upper band edge will degrade the return loss. Moreover, the shunt resistor deteriorates the conversion gain at high frequency. The broad-band analog multiplier/mixer

using transmission-line matching networks achieved better conversion gain and input return loss simultaneously than the design with an equivalent shunted 50- resistor [15]. Similar to the distributed circuits, wide-band impedance matching can be achieved with the artificial transmission line formed by LC ladder filters. However, the losses of passive of the HBT also elements and the base parasitic resistance degrade the overall bandwidth and conversion gain, especially for the circuits using standard silicon MMIC technologies. In order to enhance the high-frequency performance, the modified loss-compensation method is also adopted to overcome these obstacles. The modified loss-compensation network, which consists of series inductance and Darlington configuration, and the LC ladder matching network are shown in Fig. 11. The LC ladder network provides broad-band impedance matching, which usually appears in the distributed designs. The matching network is loaded by the input equivalent capacitance of the modified loss-compensation network and terminated with its characteristic impedance at the end with spiral inductors to form the artificial transmission line. All the passive elements of capacitors and inductors are simulated by the full-wave simulation tool [28] to predict the high-frequency effects. The simulated mixer conversion gain with series inductance is shown in Fig. 12, and the 3-dB bandwidth is improved from 19 to 24 GHz, which indicates approximately 26% improvement.

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Fig. 14. Simulated and measured small-signal gain and input return loss of the modified loss-compensated HBT CSSDA. Fig. 12. Conversion gain of the broad-band mixer with different series inductance L .

Fig. 13. 1.5 mm

Chip micrograph of broad-band analog multiplier/mixer (size:

2 1 mm).

The bias current is supported by current mirror and and to the charge–injection method is realized by bias the lower emitter-coupled pair and relax the voltage . The supply voltages , , and are 5, 3.3, drop on and 3.1 V, and the total dc power is 145 mW. Fig. 13 shows the chip micrograph with a chip size of 1.5 1 mm .

V. EXPERIMENTAL RESULTS A. Modified Loss-Compensated HBT CSSDA The HBT CSSDA is measured through on-wafer testing. The simulated and measured small-signal power gains are depicted in Fig. 14. It is observed that the simulation reasonably agrees with measurement. The average measured gain is approximately 15 dB from dc to 28 GHz. As shown in Figs. 14 and 15, the measured output return loss is better than 7 dB, and the input return loss is better than 5 dB. The total dc power consumption of the proposed loss-compensated HBT CSSDA is only 48 mW, slightly higher than simulation. The measured results of this CSSDA represented high gain-bandwidth product of 157 GHz with lowest power consumption and smallest chip area.

Fig. 15. Simulated and measured output return loss of the modified loss-compensated HBT CSSDA.

B. Analog Multiplier and Mixer While measuring the multiplier characteristics, the input signals were fed from the IF pads and the output was extracted from the BF pad with wire bonding at the output pad. The output was then connected to a spectrum analyzer through dc-blocking capacitors. The output voltage was measured at output impedance and ports) swept from of 50 with two input signals (at 0.1 to 30 GHz, a fixed baseband frequency (BF) of 10 MHz, and the same IF input signal powers of 20 dBm. The sensitivity, which is the ratio of BF output voltage to total IF input power, was better than 3000 V/W with a bandwidth of 0.1–25 GHz, as plotted in Fig. 16. The mixer characteristics of the chip were measured using as the LO input port and as RF on-wafer probing on input ports (as shown in Fig. 13). The mixer characteristics were measured with the same setup as the multiplier measurement. The power conversion gain as a function of LO power with RF frequency of 10 GHz and IF frequency of 10 MHz shows that the conversion gain almost saturated approximately 0 dBm of LO power. The conversion gain versus the RF frequency is shown

TSAI et al.: BROAD-BAND MMICs BASED ON MODIFIED LOSS-COMPENSATION METHOD

COMPARISON

503

OF

TABLE III MONOLITHIC INTEGRATED MIXERS MMIC TECHNOLOGIES

IN

VARIOUS

Fig. 16. Measured conversion gain of mixer with IF frequency of 10 MHz, LO power is 0 dBm, and sensitivity of multiplier with input power of 20 dBm.

0

Fig. 17. Measured output low-frequency noise of the broad-band multiplier/mixer.

in Fig. 16 with both RF and LO ports swept in frequency up to 30 GHz, a fixed IF frequency of 10 MHz, and LO power of 1 dBm. The conversion gain is approximately 19 dB with a 3-dB bandwidth of 0.1–23 GHz. The bias conditions in the analog multiplier and the mixer testing are the same, and lead to the same power consumption of 145 mW, close to simulation. The low-frequency noise of this analog multiplier/mixer was also measured. A preamplifier with a gain of approximately 100 and a noise level of 1–2 nV/sqrt(Hz) was used in the test set. The chip was directly dc coupled to the low-noise differential amplifier. A spectrum analyzer, which can measure the low-frequency signal to 30 Hz, was used to investigate the noise performance. A battery was used as the dc power supply in the noise test setup for a clean environment. Fig. 17 presents the measured output low-frequency noise. The noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. VI. CONCLUSIONS Based on the proposed modified loss-compensation technique, two state-of-the-art broad-band MMICs have been demonstrated. The modified loss-compensated HBT 2-CSSDA

was first realized and demonstrated with a small-signal power gain of 15 dB from dc to 28 GHz, which indicates the high gain-bandwidth product of 157 GHz. The total power consumption is only 48 mW with a miniature chip size of 0.68 mm . The gain-bandwidth product of the modified loss-compensated 2-CSSDA is improved approximately 68% compared with the convention attenuation-compensation technique. It also demonstrates the lowest power consumption and smallest chip size, as shown in Table II. The active broad-band mixer sets the highest gain-bandwidth product for the reported monolithic integrated mixers by using the LC ladder matching networks to achieve broad-band impedance matching, and the modified loss-compensation method to improve the conversion gain and bandwidth. A mixer conversion gain of 19 dB is achieved with a wide bandwidth of 0.1–23 GHz, and the highest gain-bandwidth product of 204 GHz among the reported SiGe-, InP-, and GaAs-based HBT analog active mixers, as shown in Table III. Moreover, since these broad-band SiGe broad-band circuits were fabricated in a standard silicon technology, they can be easily integrated with other Si-based front-end and baseband circuits without any additional post-processing steps. ACKNOWLEDGMENT The chip was fabricated by the the Taiwan Semiconductor Manufacturing Company (TSMC) through the Chip Implementation Center (CIC), Taiwan, R.O.C. The authors would like to thank Dr. W. Wilson and P. Robert, both of the Australia Telescope National Facility, Sydney, Australia, for noise measurement, Dr. K.-Y. Lin, National Taiwan University (NTU), Taipei, Taiwan, R.O.C., and Dr. C.-T. Li, Academia Sinica Institute of Astronomy and Astrophysics (ASIAA), Taiwan, R.O.C., for the coordination of chip testing.

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REFERENCES [1] K. W. Kobayashi, R. M. Desrosiers, A. K. Oki, and D. C. Streit, “A DC–20-GHz InP HBT balanced analog multiplier for high-data-rate direct-digital modulation and fiber-optic receiver application,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 2, pp. 194–202, Feb. 2000. [2] C. T. Li, D. Kubo, C. C. Han, C. C. Chen, C. H. Lien, H. Wang, R. M. Wei, C. H. Yang, T. D. Chiueh, J. Peterson, M. Kesteven, and W. Wilson, “A wideband analog correlator system for AMiBA,” in Proc. SPIE Astronomical Telescopes and Instrumentation, Jun. 2004, pp. 455–463. [3] K. W. Kobayashi, R. Esfandiari, and A. K. Oki, “A novel HBT distributed amplifier design topology based on attenuation compensation techniques,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp. 2583–2589, Dec. 1994. [4] S. Mohammadi, J. W. Park, D. Pavlidis, J. L. Guyaux, and J. C. Garcia, “Design optimization and characterization of high-gain GaInP/GaAs HBT distributed amplifiers for high-bit-rate telecommunication,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 6, pp. 1038–1044, Jun. 2000. [5] K. L. Koon, Z. Hu, H. Aghvami, and A. A. Rezazadeh, “High gain and ultra wideband SiGe/BiCMOS cascaded single stage distributed amplifier for 4G RF front-end applications,” in Proc. IEEE Personal, Indoor, Mobile Radio Communication Symp., 2003, pp. 2180–2184. [6] O. Wohlgemuth, P. Paschke, and Y. Baeyens, “SiGe broadband amplifiers with up to 80 GHz bandwidth for optical applications at 43 Gbit/s and beyond,” in IEEE 33rd Eur. Microwave Conf. Dig., 2003, pp. 1087–1090. [7] K. W. Kobayashi, L. T. Tran, M. D. Lammert, A. K. Oki, and D. C. Streit, “Transimpedance bandwidth performance of an HBT loss-compensated coplanar waveguide distributed amplifier,” Electron. Lett., vol. 32, no. 24, pp. 2287–2288, Nov. 1996. [8] S. Kudszus, A. Shahani, S. Pavan, D. K. Shaeffer, and M. Tarsia, “A 46-GHz distributed transimpedance amplifier using SiGe Bipolar technology,” in IEEE MTT-S Int. Microwave Symp. Dig., 2003, pp. 1387–1390. [9] J. Aguirre and C. Plett, “A 0.1–50 GHz SiGe HBT distributed amplifier employing constant-k m-derived sections,” in IEEE MTT-S Int. Microwave Symp. Dig., 2003, pp. 923–926. [10] K. Osafune and Y. Yamauchi, “20-GHz 5-dB-gain analog multipliers with AlGaAs/GaAs HBTs,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 3, pp. 518–520, Mar. 1994. [11] K. L. Deng and H. Wang, “A 3–33 GHz PHEMT MMIC distributed drain mixer,” in IEEE RFIC Symp. Dig., 2002, pp. 151–154. [12] Y. Imai, S. Kimura, Y. Umeda, and T. Enoki, “DC to 38-GHz distributed analog multiplier using InP HEMT’s,” IEEE Microw. Guided Wave Lett., vol. 4, no. 12, pp. 399–401, Dec. 1994. [13] L. M. Burns, J. F. Jensen, W. E. Stanchina, R. A. Metzger, and Y. K. Allen, “DC-to-Ku-band MMIC InP HBT double-balanced active mixer,” in IEEE Int. Solid-State Circuits Conf. Dig., San Francisco, CA, 1991, pp. 124–125. [14] J. Glenn, M. Case, D. Harame, B. Meyerson, and R. Poisson, “12-GHz Gilbert mixers using a manufacturable Si/Si–Ge epitaxial-base bipolar technology,” in Proc. IEEE Bipolar/BiCMOS Circuits Technology Meeting, Minneapolis, MN, 1998, pp. 186–189. [15] H. Wang, “A 1-V multi-gigahertz RF mixer core in 0.5-m CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig., San Francisco, CA, 1998, pp. 370–371. [16] B. Tzeng, C. H. Lien, H. Wang, Y. C. Wang, P. C. Chao, and C. H. Chen, “A 1–17-GHz InGaP-GaAs HBT MMIC analog multiplier and mixer with broad-band input-matching networks,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 11, pp. 2564–2568, Nov. 2002. [17] I. Gresham and A. Jenkins, “A low-noise broadband SiGe mixer for 24-GHz ultra-wideband automotive applications,” in Proc. IEEE RAWCON, 2003, pp. 361–364. [18] A. Y. Umeda, C. T. Matsuno, A. K. Oki, G. S. Dow, K. W. Kobayashi, D. K. Umemoto, and M. E. Kim, “A monolithic GaAs HBT upconverter,” in IEEE Microwaves Millimeter-Wave Monolithic Circuits Symp. Dig., Dallas, TX, 1990, pp. 77–80. [19] C. C. Meng, S. S. Lu, M. H. Chiang, and H. C. Chen, “DC to 8 GHz 11 dB gain Gilbert micromixer using GaInP/GaAs HBT technology,” Electron. Lett., vol. 39, pp. 637–638, Apr. 2003. [20] S. Hackl, J. Bock, M. Wurzer, and A. L. Scholtz, “40 GHz monolithic integrated mixer in SiGe bipolar technology,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 2, Seattle, WA, 2002, pp. 1241–1244.

[21] P. Weger, G. Schultes, L. Treitinger, E. Bertagnolli, and K. Ehinger, “Gilbert multiplier as an active mixer with conversion gain bandwidth of up to 17 GHz,” Electron. Lett., vol. 27, no. 7, pp. 570–571, Mar. 1998. [22] K. W. Kobayashi, L. T. Tran, S. Bui, A. K. Oki, D. C. Streit, and M. Rosen, “InAlAs/InGaAs HBT X -band double-balanced upconverter,” IEEE J. Solid-State Circuits, vol. 29, no. 10, pp. 1238–1243, Oct. 1994. [23] J. Wholey, I. Kipnis, and C. Snapp, “Silicon bipolar double balanced active mixer MMIC’s for RF and microwave applications up to 6 GHz,” in IEEE Microwaves Millimeter-Wave Monolithic Circuits Symp. Dig., Long Beach, CA, 1989, pp. 133–137. [24] M. Wurzer, T. F. Meister, S. Hackl, H. Knapp, and L. Treitinger, “30 GHz active mixer in Si/SiGe bipolar technology,” in Proc. IEEE Asia–Pacific Microwave Conf., Dec. 2000, pp. 780–782. [25] S. Hackl, M. Wurzer, J. Bock, T. F. Meister, H. Knapp, K. Aufinger, L. Treitinger, and A. L. Scholtz, “Low-noise, low-power monolithically integrated active 20 GHz mixer in SiGe technology,” Electron. Lett., vol. 37, no. 1, pp. 36–37, Jan. 2001. [26] K. L. Deng, T. W. Huang, and H. Wang, “Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 11, pp. 2188–2196, Nov. 2003. [27] B. Y. Banyamin and M. Berwick, “Analysis of the performance of four-cascaded single-stage distributed amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2657–2663, Dec. 2000. [28] Sonnet User’s Manual, Sonnet Software, Liverpool, NY, 1998. [29] M.-D. Tsai, C.-S. Lin, C.-H. Wang, C.-H. Lien, and H. Wang, “A 0.1–23-GHz SiGe BiCMOS analog multiplier and mixer based on attenuation-compensation technique,” in IEEE RFIC Symp., Jun. 2004, pp. 417–420. [30] B. Aganval, Q. Lee, D. Mensa, R. Pullela, J. Guthrie, and M. J. W. Rodwell, “Broadband feedback amplifiers with AlInAs/GalnAs transferred substrate HBT,” Electron. Lett., vol. 34, pp. 1357–1358, Jun. 1998. [31] D. Mensa, Q. Lee, J. Guthrie, S. Jaganathan, and M. J. W. Rodwell, “Baseband amplifiers in transferred-substrate HBT technology,” in IEEE Gallium Arsenide Integrated Circuit Symp., Nov. 1998, pp. 33–36. [32] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001, pp. 202–205. [33] D. A. Hodges, “Darlington’s contributions to transistor circuit design,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 1, pp. 102–104, Jan. 1999.

Ming-Da Tsai (S’03) was born in Miaoli, Taiwan, R.O.C., on August 31, 1979. He received the B.S. degree in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2001, the M.S. degree from the Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. in 2003, and is currently working toward the Ph.D. degree at the Graduate Institute of Communication Engineering, National Taiwan University. His research interests are in the areas of RF and millimeter-wave integrated circuits in CMOS, SiGe BiCMOS, and compound semiconductor technologies.

Chin-Shen Lin (S’03) was born in Hsin-Chu, Taiwan, R.O.C., on February 7, 1979. He received the B.S. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, R.O.C., in 2001, and is currently working toward the Ph.D. degree at the Graduate Institute of Communication Engineering, National Taiwan University. His main research is monolithic microwave/millimeter-wave circuit design.

TSAI et al.: BROAD-BAND MMICs BASED ON MODIFIED LOSS-COMPENSATION METHOD

Chun-Hsien Lien (S’99) received the B.E. degree in communication engineering from the National Chao-Tung University, Hsin-Chu City, Taiwan, R.O.C., in 1997, and is currently working toward the Ph.D. degree at the National Taiwan University, Taipei, Taiwan, R.O.C. His main research interests are monolithic microwave/millimeter integrated circuits.

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Huei Wang (S’83–M’87–SM’95) was born in Tainan, Taiwan, R.O.C., on March 9, 1958. He received the B.S. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, R.O.C., in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, in 1984 and 1987, respectively. During his graduate study, he was engaged in research on theoretical and numerical analysis of electromagnetic (EM) radiation and scattering problems. He was also involved in the development of microwave remote detecting/sensing systems. In 1987, he joined the Electronic Systems and Technology Division, TRW Inc. He was a Member of the Technical Staff and Staff Engineer responsible for MMIC modeling of computer-aided design (CAD) tools, MMIC testing evaluation, and design. He then became the Senior Section Manager of the Millimeter Wave Sensor Product Section, RF Product Center, TRW Inc. In 1993, he visited the Institute of Electronics, National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C., and taught MMIC-related topics. In 1994, he returned to TRW Inc. In February 1998, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, as a Professor. Dr. Wang is a member of Phi Kappa Phi and Tau Beta Pi.

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Scaling and Technological Limitations of 1=f Noise and Oscillator Phase Noise in SiGe HBTs Guofu Niu, Senior Member, IEEE, Jin Tang, Student Member, IEEE, Zhiming Feng, Alvin J. Joseph, Member, IEEE, and David L. Harame, Fellow, IEEE

Abstract—This paper examines the impact of SiGe HBT scaling noise and phase noise of oscillators and frequency syntheon 1 sizers. The increase of transistor speed with scaling is shown to significantly increase the sensitivity of oscillation frequency to 1 noise and, thus, degrade close-in phase noise, but decrease the sensitivity of oscillation frequency to base current shot noise and base resistance thermal noises. The results show that corner offset frequency defined by the intersect of the 1 3 and 1 2 phase noise has little to do with the traditional 1 corner frequency. The relative importance of individual noise sources in determining phase noise is examined as a function of technology scaling, device sizing, and oscillation frequency. The collector current shot noise and base resistance noise are shown to set the fundamental limits of phase noise reduction. A methodology to identify the maximum tolerable factor is established and demonstrated for the HBTs used. 1 Index Terms—Corner frequency, cyclostationary noise, 1 noise, phase noise, SiGe HBT, upconversion.

I. INTRODUCTION

O

SCILLATOR phase noise is an important concern for an RF semiconductor technology. Physically speaking, osnoise, base resiscillator phase noise results from transistor tance thermal noise, the base and collector current shot noise, as well as any other thermal noise sources in the passives (e.g., inductors). All of the above noise sources, however, change with technology scaling. In SiGe RF technologies, vertical scaling often requires the use of narrow, but more heavily doped base profile, with a higher Ge mole fraction [1]. This translates into a lower thermal budget, which may inadvertently increase noise, as shown below. It is, therefore, necessary to examine the noise, as well as oscillator impact of technology scaling phase noise, which we address in this paper using experimental data from SiGe HBTs featuring 50- and 120-GHz peak . noise is desired to reduce phase Even though a lower noise in semiconductor manufacnoise, the reduction of turing is very challenging, as it is sensitive to defects, particularly in scaled technologies with low thermal cycles. From a manufacturing standpoint, it is highly desired to quantitatively noise level that can be tolerated for determine the highest a given system phase noise requirement. In this paper, we will Manuscript received April 20, 2004. This work was supported by the Semiconductor Research Corporation under Contract 2001-NJ-937 and by the National Science Foundation under Grant ECS 0112923 and Grant ECS 0119623. G. Niu, J. Tang, and Z. Feng are with the Alabama Microelectronics Science and Technology Center, Electrical and Computer Engineering Department, Auburn University, Auburn, AL 36849 USA (e-mail: [email protected]). A. J. Joseph and D. L. Harame are with IBM Microelectronics, Essex Junction, VT 05452 USA. Digital Object Identifier 10.1109/TMTT.2004.840768

develop a method of determining such “critical” or “threshold” noise level for a given bipolar technology, and demonstrate its utility for the SiGe HBTs used. noise figure-of-merit is the so-called An often used corner frequency, often defined by the intersect of the base curnoise and the base current shot noise. The utility of the rent corner frequency is that it indicates whether noise or base current shot noise dominates for a given frequency. Howcorner ever, due to the complexity of the upconversion, the frequency is not a meaningful figure-of-merit for phase noise, as we will show below. Instead, we will introduce the concept of corner offset frequency [2], defined by the intersect of the phase noise and the phase noise upconnoise upconverted from verted from other white noise sources. A detailed analysis of phase noise upconversion is made to facilitate understanding of noise measured at the dc the quantitative relations between biasing point and phase noise. noise, there is always thermal noise due to base Besides resistance and the base and collector current shot noise associated with the dc currents. To help identify the phase noise limitations of today’s technologies, we will separate the phase noise contributions from various physical noise sources. The bottle neck of phase noise can then be identified and improved. II. A.

Noise

NOISE

Factor

noise in an SiGe HBT is in its base current. The major The noise is a function of and emitter area [3] (1) where is a constant for a given technology, depending on the defect level. Vertical scaling of the SiGe HBT focuses on base and collector transit time reductions. Base transit time reduction can be achieved by using a narrow and more heavily doped base profile together with a lower thermal cycle for the bipolar processing and increasing the Ge ramp to create a higher accelerating electric field for minority carriers. A small amount of carbon can also be added in the base to limit boron diffusion so that the base doping profile can be kept in place after device fabrication. The physical changes of the emitter–base junction composition during scaling may inadvertently worsen (increase) the noise factor. Here, we compare a 50-GHz 0.5- m SiGe HBT [4] with a 120-GHz 0.18- m SiGe HBT [5] built in a BiCMOS process flow. Fig. 1(a) compares the measured

0018-9480/$20.00 © 2005 IEEE

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(a)

(b)

2A

Fig. 2. (a) Measured S versus I . Frequency is 10 Hz.

Fig. 1. Measured S spectra of 50- and 120-GHz HBTs. S normalized by A . (a) Comparison at I = 10 A. (b) Comparison at I 1:4 mA.

versus I . (b) Measured S

2A

is

=

noise

spectra at A. Similar emitter areas are chosen: 0.5 2.5 m and 0.2 6.4 m for the 50, is and 120-GHz technologies. Since . As expected, the 120-GHz SiGe HBT has a normalized by higher noise, which is attributed to the base width scaling. noise at the same biasing For oscillators, a comparison of is more relevant since the biasing sets the amplitude of oscillation. Fig. 1(b) compares the low-frequency noise spectra HBTs at mA. The of the 50- and 120-GHz peak noise difference is only 3 , in part due to the increase of with scaling, as for a given . at 10 Hz as a function of . Fig. 2(a) shows is proportional to in both HBTs. The noise factor, for a given , increases from 2.0 which measures 10 m to 8.6 10 m for the two HBTs. Fig. 2(b) shows at 10 Hz shown as a function of . The at the same is proportional to , and increases by 3 with scaling because of increase with scaling. B.

Noise Corner Frequency

noise corner frequency The is given by [6]

at which

(2)

Fig. 3. Measured f

versus J .

The increase of the noise factor with scaling tends to in. However, depending on device design, is often crease increased with scaling as well, which partially offsets the factor increase. Fig. 3 shows the measured a function of for the 50- and 120-GHz HBTs. The nature of bipolar tranto realize the sistor operation necessitates a higher operating high-speed potential offered by scaling. A larger range is thus used for the 120-GHz HBT. For a given , an increase of is observed. At mA m , the 120-GHz HBT of 1.6 MHz, which is relatively high compared shows a to a 50-GHz HBT at mA m . Such an increase of corner frequency, however, does not necessarily cause an increase of the overall oscillator phase noise or the ultimate frequency synthesizer noise due to different mechanisms of phase

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Fig. 4. Schematic of the single-ended Colpitts oscillator.

noise upconversion for the base current rent shot noise, as detailed below.

Fig. 5. Simulated output of the 5.5-GHz single-ended Colpitts oscillator.

noise and base cur-

III. OSCILLATOR PHASE NOISE A. Simulation Method Colpitts oscillators are designed and simulated using ADS and SpectreRF. Calibrated Vertical Bipolar Intercompany (VBIC) models that accurately reproduce measured dc and RF characteristics are used. The VBIC model is implemented in SpectreRF using Verilog-A to access the internal base and collector transport currents responsible for shot noises, which are not available in ADS/SpectreRF when the built-in VBIC model is used, but necessary for understanding the different upnoise and base conversion mechanisms of the base current current shot noise, as described below. We will use a 5.5-GHz oscillator shown in Fig. 4 for both HBTs for comparison, even though both HBTs are capable of much higher frequency oscillation. A common-base bias configuration provides gain from emitter to collector, which connects to the resonator. The capacitor divider ( and ) provides positive feedback from collector to emitter, and sets oscillation frequency together with the inductor . The two HBTs described in Section II are used here. V is chosen to avoid breakdown. The frequency-sensitivity phase noise analysis method is chosen since it is more appropriate for near carrier phase noise, which is the focus of this study. B. Phase Noise mA. The output Fig. 5 shows the simulated output swing increases noticeably with scaling because of increasing and . Fig. 6 shows simulated phase noise versus offset component due to noise upconversion frequency. A and a component due to white noise upconversion can be component increases clearly identified. With scaling, the by 11.4 dB, in part because of the increasing factor. The phase noise resulting from upconversion of white noises, however, improves (decreases) by 7.2 dB with HBT scaling. C. Corner Offset Frequency We now define the corner offset frequency using the and phase noises. is a direct intersect of the measure of the importance of the phase noise upconverted from

Fig. 6. Comparison of phase noise of oscillators designed using the two technologies.

noise with respect to the phase noise upconverted from the is 595.4 Hz and 40.8 kHz for the white noise sources. 50- and 120-GHz technologies, as can be seen from Fig. 6. Note itself does not contain any information on either the that or phase noise level. does not necessarily mean higher phase A higher for the 120-GHz HBT is nearly noise. In this case, the 70 higher than for the 50-GHz HBT. The overall effect of scaling on oscillator phase noise is a degradation at offsets below 10 kHz, but an improvement at higher offset frequencies. In a frequency synthesizer, if the loop bandwidth is much greater than 10 kHz, the overall synthesizer phase noise will corner frequency, improve with scaling, despite increased as the oscillator phase noise below 10 kHz is removed by loop feedback. is significantly lower than the Interestingly, corner frequency at the biasing current for both technoloHz, while gies. For the 50-GHz HBT, kHz. For the 120-GHz HBT, kHz, while MHz. This observation has significant noise evaluation of a implications on the methodology of process technology. One would have disqualified the 120-GHz corner frequency HBT for low phase noise oscillators if the was used as a figure-of-merit for phase noise (1.6 MHz at 2.5 mA m ). In Section IV, we investigate why the corner frequency is different from the corner offset frequency in SiGe HBT oscillators.

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Fig. 7. Simplified large-signal transistor model.

IV.

CORNER VERSUS PHASE NOISE CORNER FREQUENCIES

To investigate the relationship between corner frequency and the phase noise corner offset frequency, we consider the phase noise upconversion process implemented in ADS. For simplicity, we will first consider the upconversion of only the noise and the base current shot noise. In frebase current quency-sensitivity analysis, the method chosen here, the sensitivity of oscillation frequency to a noise current injection is calculated from the large-signal harmonic-balance solution. The sensitivity function can be viewed as the transfer function from physical noise source to phase noise. The noise source, however, is often cyclostationary by the very nature of oscillation, which versus . is responsible for the difference between In a small-signal noise measurement, the transistor is biased or . The small-signal noise and the shot at a fixed noise are simple functions of the base terminal current . For instance, the shot noise is white, and described by a power spec. In an oscillator, the situation is complicated tral density of as follows. has a large capacitive com• The terminal base current noise or ponent, which does not contribute to either shot noise. Instead, the internal base to emitter junction is responsible for noise generation. This is current illustrated in Fig. 7 using a simplified large-signal tranis different from sistor model. Similarly, the terminal the noise-generating collector to emitter transport current . and responsible for base and col• The internal lector current noise generation is periodically oscillating. Therefore, to understand the phase noise upconversion process, from the external . we first need to separate the internal At present, neither ADS, nor Cadence SpectreRF allows access when the built-in transistor VBIC model is of the internal used. A. Noise Generating Current Versus Terminal Current The internal and can be accessed by implementing the transistor model using an analog hardware description language, e.g., Verilog-A or Verilog-AMS. There are publicly available Verilog-A implementations of early VBIC models, however, when used in circuit simulation, these implementations give quite different results from the built-in VBIC model, for various reasons, including syntax differences between circuit simulators, as well as bugs in the codes. To ensure accuracy and achieve consistency with the built-in VBIC model, we

Fig. 8. Comparison of terminal I and internal I for the 50-GHz HBT. The internal V is shown on the right-hand-side y -axis.

implemented exactly the same model equations given in the user manual of ADS for the built-in VBIC model. For verification, extensive dc, ac, and noise simulations are performed using both the built-in VBIC model and our Verilog-A implementation. The results are identical within the error limits of the circuit simulator, confirming the validity of our Verilog-A implementation. , the noise Fig. 8 shows the waveforms of the terminal , and for an oscillator designed generating internal device. The difference between with the 50-GHz peak and is obvious even if the device peak is much higher than the oscillation frequency (5.5 GHz). Due to the nature of oscillation, the base–emitter junction is turned on and off periodically, as shown on the right-hand-side -axis of Fig. 8. A significant portion of the terminal base current is due to capacitive charging and discharging of the strongly nonlinear is only junction capacitances. The noise generating current noise a small portion of the terminal . Inside ADS, the is assumed to be the same associated with the oscillating as the noise measured under a base current equal to the dc . This is physically reasonable considering component of noise are large. Clearly, the dc that the time constants of is different from that of in oscillators. component of B. Phase Noise Upconversion The phase noise at a given offset frequency originates from the sensitivity of the oscillation frequency to sideband with being the harmonic index noises at to ). As the correlation time of the shot noise ( process is typically much smaller than oscillation period, these can be approximated by a unity noises at stationary noise source modulated by the instantaneous ( or ) [7] (3) where

is the modulation function

(4)

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with being the Fourier coefficient of being a unity stationary noise

at

, and

(5) where is a random phase angle and the auto-correlation funcis a delta function . After lengthy tion of at can be shown to manipulations, the noises of be correlated to each other. The cross-correlation spectral denand is related to sity of the noise currents at by [7] the harmonics of the shot noise generating current (6) is the order Fourier coefficient of the noise where generating current . The noise contribution to phase noise at an offset angular frequency is from the dc component of only [8]

Fig. 9.

i

and i

contributions to phase noise.

the dc-biasing current or the dc component of does not in, as dicate the value of the phase noise corner frequency observed in our simulation results. D. Impact of Scaling on Upconversion

(7) where indicates the zeroth-order harmonic current and is the dc component of . contribute to a For shot noise, all of the noises at phase noise at . As these noises are correlated, the total phase noise is given by [8] shot

(8)

where

is the number of harmonics in question, according to (6), and the superscript stands for taking the conjugate. The factor of “2” in (8) is due to the consideration of the single-sideband phase noise. C. Disconnection Between

and

Even though the phase noise is determined by the dc , the phase noise associated with the component of has little to do with the dc component of shot noise of in typical bipolar oscillators. For typical waveforms found in bipolar oscillators, shot is dominated by the noise sideinstead of the noise sidebands near dc. shot bands near is mainly determined by the noises at , , as well as . For all practhe corresponding frequency sensitivity tical purposes, one can safely neglect the upconversion of shot . For instance, noise associated with the dc component of for the 50-GHz HBT oscillator considered here, the total phase shot noise is 80 dB higher than that associated noise due to with the dc component alone. corner frequency is defined by the interRecall that the noise and the shot noise at a given dc bisect of the asing . For phase noise upconversion, however, only the noise upconversion is related to the dc component of (which in oscillators). is determined by differs from total and , while shot is mainly determined and . It is, therefore, not surprising that the by corner frequency defined using and at either

Fig. 9 shows the simulated phase noise contributions from the noise and base current shot noise for base current the two HBTs. With scaling, the contribution to phase noise increases by 11.4 dB, or 13.8 . Part of this increase noise available for upconversion. is due to the increase of , is 63.4 and 13.6 A for the The dc component of oscillators designed with the 50- and 120-GHz HBTs, respecis 54 and 10 A). The higher speed of tively (the dc biasing the scaled 120-GHz HBT leads to faster turn on and turn off of , as evidenced by the simulated waveforms (Fig. 10). The 120-GHz HBT turns on faster and stays on for only a porin the tion of the oscillation period. As discussed above, oscillator, instead of the dc biasing , determines the amount noise available for phase noise upconversion. In this of case, the noise increases from 6.47 10 to A Hz (at 10 Hz), a 1.87 increase. 1.21 10 phase noise, however, degrades by 11.4 dB The overall (Fig. 9) primarily because of a large increase of the sensitivity of noise with scaling. In contrast, the oscillation frequency to base current shot noise contribution to phase noise (indicated by ) decreases by 13.8 dB, or 24 with scaling. The first-order harmonic of , decreases from 67.2 to 20.5 A with scaling. The extra decrease of the phase noise from upconversion of base current shot noise is due to the decreased sensitivity of oscillation frequency to shot noise. , where the and The corner offset frequency phase noises intersect, is 5.9 kHz and 0.81 MHz (not shown in this figure) for the 50- and 120-GHz technologies. corner frequenThese numbers are much smaller than the cies at the biasing current (200 kHz and 1.4 MHz) noise because of different upconversion mechanisms of and shot noise, as discussed above. The overall corner offset frequency is even lower because of additional contributions from other white noise sources, e.g., the base resistance and collector current shot noises. Based on the above discussions, we conclude that the widely used corner frequency is not a good indicator of the relative importance of phase noise upconverted from noise for

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Fig. 10.

Comparison of internal I

NOISE AND OSCILLATOR PHASE NOISE IN SiGe HBTs

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for the 50- and 120-GHz HBT oscillators.

SiGe HBTs. As we have shown, the phase noise upconverted noise is important only for offset frequencies below from , which is, in general, much higher than at the biasing current. The speed increase with scaling leads to more efficient energy shuffling in oscillator, which helps reducing the noise available for upconversion with scaling. amount of noise, but Scaling increases the sensitivity of oscillation to decreases the sensitivity of oscillation to base current shot noise. V. TECHNOLOGICAL LIMITATIONS To understand the limiting factor of phase noise, we compare the phase noise contributions from individual noise sources in Fig. 11(a) and (b) for the 50- and 120-GHz HBTs. The major noise sources include: 1) base current noise ; 2) base current shot noise ; 3) collector current shot noise ; and 4) thermal noise due to intrinsic and extrinsic base resistance ( and ). In the 50-GHz HBT, the noise is the most dominant phase noise contributor, followed by and (comparable), and then . In the 120-GHz HBT, the noise is the most dominant phase noise , and contributor, followed by collector current shot noise then the intrinsic base resistance noise and (comparable). With scaling, noise becomes more dominant over noise. The and contributions may be further decreased by increasing the emitter length, provided that oscillation swing is not decreased. The lower limit is set by the and shot noise contributions ( and ). A. Intrinsic Versus Extrinsic Base Resistance Noise Fig. 12 compares the and contributions to phase noise. The intrinsic noise contribution dominates in the 50-GHz HBT, while the extrinsic noise contribution dominates in the 120-GHz HBT. The phase noise is proportional to the product of the amount of thermal noise and the sensitivity of oscillation frequency to a given thermal noise. With scaling to 120 GHz, decreases dramatically from 111 to 8.9 because of increased emitter length-to-width ratio, as well as decreased intrinsic base sheet resistance. The extrinsic , however, stays about the same (26 versus 24 ) despite increased length-to-width ratio. The normalized by emitter length increases from 65 to 153 m due to complexities of extrinsic base scaling [9].

Fig. 11. Individual phase noise contributions from major noise sources. (a) 50-GHz HBT. (b) 120-GHz HBT.

Fig. 12.

r

and r

contributions to phase noise.

The sensitivity of oscillation frequency to and noise is found to decrease by 30% with scaling as a result of transistor speed increase. For both HBTs, the sensitivity of oscillation frequency to noise is 50% of the sensitivity to noise, which indicates that, for the same amount of total base resistance, a process in which dominates is better in terms of phase noise reduction. This result suggests the importance of reducing extrinsic base resistance in scaled SiGe HBT technologies. New device structures with raised extrinsic base [10] are expected to alleviate this problem. B. Transistor Sizing In RF integrated-circuit (RFIC) design, transistor size is often optimized for better circuit performance, which can be

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Fig. 13.

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Fig. 15. Overall phase noise comparison for oscillators with different oscillation frequency. The 120-GHz HBT is used.

Phase noise for transistors with different emitter areas.

Fig. 14. Individual phase noise contributions as a function of frequency is 10 kHz.

N

. The offset

realized by varying the number of emitter fingers. Among the various noise sources, the base resistance noise and base current noise are inversely proportional to the number of emitter fingers (or total effective emitter length). For the same biasing current, increasing the size also reduces transistor speed, which may affect the sensitivity of oscillation frequency to noise, as described above. It is, thus, not obvious how sizing affects oscillator performance. Oscillation will eventually stop if the size is too big because of diminishing . Fig. 13 compares the overall phase noise spectra for 50-GHz HBTs of different emitter fingers. The biasing current is fixed at 3 mA. The oscillation frequency does not change much with transistor size. The far-off phase noise performance improves as the effective increases from 0.5 2.5 1 m to 0.5 2.5 5 m , and remains invariant with further increasing . The close-in phase noise performance increases slightly as increases from 0.5 2.5 1 m to 0.5 2.5 5 m , and decreases with further increasing . Fig. 14 shows the major phase noise contributions as a function of emitter finger number . The offset frequency is 10 kHz. Both the and thermal noise contributions decrease as increases from 1 to 13. This is likely due to the base resistance decrease. The relative importance of different noise contributions change as increases. For m , the noise is the most dominant far-off phase noise component. However, for m , the noise becomes the most dominant, which sets the ultimate limit to phase noise reduction.

Fig. 16. Individual phase noise contributions as a function of oscillation frequency. The 120-GHz HBT is used. The offset frequency is 1 MHz.

C. Oscillation Frequency Dependence Fig. 15 compares the phase noise spectra for four oscillators with different oscillation frequency (i.e., 5.5, 10, 20, and 30 GHz). The biasing current is 3 mA, and the output swing is approximately the same. The 5.5-GHz oscillator has the best phase noise performance at both small- and large-offset frequencies. The far-off phase noise degrades with increasing oscillation frequency. The close-in phase noise, which is dominated by base current noise contribution, first increases and then decreases with increasing oscillation frequency. All of the white noise contributions, however, increase monotonically with oscillation frequency (Fig. 16). VI. SYNTHESIZER PHASE NOISE AND THRESHOLD In frequency synthesizers, the voltage-controlled oscillator (VCO) phase noise within the loop bandwidth is suppressed by the loop feedback mechanism. The out-of-band phase noise of the VCO, however, directly translates into synthesizer out-of-band phase noise. From an application standpoint, if the loop bandwidth is sufficiently higher than the corner offset phase noise can be completely suppressed frequency, the by loop feedback. The out-of-band noise will then be the phase noise due to white noises. Using 10 as a criterion, the phase noise is only 1/10 of the phase noise at the that is 1/10 of loop bandwidth offset frequency, for an the loop bandwidth, as shown in Fig. 17.

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VII. CONCLUSIONS

Fig. 17. Illustration of the conversion process of the VCO and reference phase noise to frequency synthesizer phase noise and the definition of K .

We have examined the implications of SiGe HBT scaling on noise, and phase noise of oscillators and frequency synthenoise upconversion. A sizers, as well as the mechanisms of noise typically measured significant difference between the noise available for phase at the dc biasing current and the noise upconversion has been identified using Verilog-A based circuit modeling. The increase of transistor speed with scaling has been found to significantly increase the sensitivity of oscilnoise, but decrease the sensitivity of oslation frequency to cillation frequency to white noises. For a given process, the factor only needs to be below certain threshold, and any furfactor does not help reducing system ther reduction of the is shown to decrease with phase noise. The threshold scaling. This, together with the increase of the factor with noise an increasingly important technology scaling, makes concern with further scaling. The actual for both technologies , leading to are found to be close to or below their respective an overall improvement of synthesizer noise with scaling. The impact of transistor sizing and oscillation frequency variation on phase noise has then been examined. The extrinsic base resistance noise and the collector current shot noise are shown to set the fundamental limit of phase noise reduction. ACKNOWLEDGMENT The authors would like to thank J. Cressler, Georgia Institute of Technology, Atlanta and X. Ma and F. Dai, both of Auburn University, Auburn, AL, for their contributions. REFERENCES

Fig. 18. f versus K factor. K is determined for a loop bandwidth of 200 kHz. The actual K values are shown as 3.

For a given oscillator, decreases linearly with according to the analysis in Section IV. For a given process and equal to 1/10 loop bandwidth, a threshold that makes of the loop bandwidth can be defined. Once , the synthesizer phase noise no longer decreases with further decrease of . One can also view this threshold as the maximum tolerable . This is very attractive from a semiconductor technology development standpoint because the factor is sensitive to defect level, and very challenging to minimize. versus noise factor for both Fig. 18 shows technologies. Assuming a loop bandwidth of 200 kHz, is at which kHz such that the determined as the phase noise is only 10% of the noise at 200 kHz. For m , and the actual the 50-GHz HBT, m is well below . Thus, noise is not a concern for synthesizer phase noise since practically all of the phase noise is suppressed by loop feedback, and the in-band noise is limited by reference oscillator. For the 120-GHz HBT, m , which is slightly smaller than the acm . The combination of decreasing tual of 8.6 10 and increasing with scaling makes noise an increasingly important concern for phase noise of frequency synthesizers.

[1] G. Freeman, B. Jagannathan, S. Jeng, J. Rieh, A. D. Stricker, D. C. Ahlgren, and S. Subbanna, “Transistor design and application considerations for >200-GHz SiGe HBTs,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 645–655, Mar. 2003. [2] G. Niu, J. Tang, Z. Feng, A. Joseph, and D. L. Harame, “SiGe technology scaling implications on 1=f noise and oscillator phase noise,” RFIC, to be published. [3] J. D. Cressler and G. Niu, Silicon–Germanium Heterojunction Bipolar Transistors. Norwood, MA: Artech House, 2003. [4] D. C. Ahlgren, G. Freeman, S. Subbanna, R. Groves, D. Greenberg, J. Malinowski, D. Nguyen-Ngoc, S. J. Jeng, K. Stein, K. Schonenberg, D. Kiesling, B. Martin, S. Wu, D. Harame, and B. Meyerson, “A SiGe HBT BiCMOS technology for mixed signal RF applications,” in Proc. IEEE Bipolar/BiCMOS Circuits Technology, Sep. 1997, pp. 195–197. [5] A. Joseph, D. Coolbaugh, M. Zierak, R. Wuthrich, P. Geiss, Z. He, X. Liu, B. Orner, J. Johnson, G. Freeman, D. Ahlgren, B. Jagannathan, L. Lanzerotti, V. Ramachandran, J. Malinowski, H. Chen, J. Chu, P. Gray, R. Johnson, J. Dunn, S. Subbanna, K. Schonenberg, D. Harame, R. Groves, K. Watson, D. Jadus, M. Meghelli, and A. Rylyakov, “A 0.18 m 120/100 GHz (f =f ) HBT and ASIC-compatible CMOS using copper interconnect,” in Proc. IEEE Bipolar/BiCMOS Circuits Technology, Oct. 2001, pp. 143–146. [6] J. Tang, G. Niu, Z. Jin, J. D. Cressler, S. Zhang, A. J. Joseph, and D. L. Harame, “Low-frequency noise figures-of-merit in RF SiGe RF technology,” in RFIC Symp. Tech Dig., Seattle, WA, Jun. 2002, pp. 179–182. [7] C. Dragone, “Analysis of thermal and shot noise in pumped resistive diodes,” Bell Syst. Tech. J., pp. 1883–1902, Nov. 1968. [8] R. Poore, “Oscillator phase noise simulation using ADS, including flicker noise conversion,” presented at the IEEE MTT-S Int. Microwave Symp. Workshop, Jun. 2003. [9] G. Freeman, B. Jagannathan, S.-J. Jeng, J.-S. Rieh, A. D. Stricker, D. C. Ahlgren, and S. Subbanna, “Transistor design and application considerations for >200-GHz SiGe HBTs,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 645–655, Mar. 2003.

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[10] B. Jagannathan, M. Khater, F. Pagette, J.-S. Rieh, D. Angell, H. Chen, J. Florkey, F. Golan, D. R. Greenberg, R. Groves, S. J. Jeng, J. Johnson, E. Mengistu, K. T. Schonenberg, C. M. Schnabel, P. Smith, A. Stricker, D. Ahlgren, G. Freeman, K. Stein, and S. Subbanna, “Self-aligned site NPN and 207 GHz f in a manufacturable transistors with 285 GHz f technology,” IEEE Electron Device Lett., vol. 23, no. 5, pp. 258–260, May 2002.

Guofu Niu (M’97–SM’02) was born in Henan, China, in December 1971. He received the B.S. (with honors), M.S., and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1992, 1994, and 1997, respectively. From December 1995 to January 1997, he was a Research Assistant with the City University of Hong Kong, where he was involved with mixed-level device/circuit simulation and quantum effect programmable logic gates. From May 1997 to May 2000, he conducted post-doctoral research with Auburn University, Auburn, AL. In 2000, he joined the faculty of Auburn University, where he is currently a Professor of electrical and computer engineering. His research activities include SiGe devices and circuits, RF CMOS, noise, single-event effects, SiC devices, low-temperature electronics, and technology computer-aided design (TCAD). He has authored or coauthored over 70 journal papers and over 60 conference papers. He coauthored Silicon-Germanium Heterojunction Bipolar Transistors (Norwood, MA: Artech House, 2003). Dr. Niu has served on the Program Committee of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (2002–present), the IEEE Nuclear and Space Radiation Effects Conference (2002), the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (2004), the ECS SiGe Materials, Processing and Devices Symposium (2004), and the Asia–South-Pacific Design Automation Conference (1997). He has regularly served as a reviewer for numerous journals including the IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE ELECTRON DEVICE LETTERS, and the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He was the recipient of the 1993 and 1994 T. D. Lee Physics Award.

Jin Tang (S’02) was born in Sichuan, China, in November 1977. She received the B.S. degree from the Huazhong University of Science and Technology, Wuhan, Hubei, China, in 2000, the M.S. degree from Auburn University, Auburn, AL, in 2003, both in electrical engineering, and is currently working toward the Ph.D. degree at Auburn University. Her research focuses on low-frequency noise and phase noise in SiGe HBT RF technologies.

Zhiming Feng was born in Jilin, China, in April 1973. He received the B.S. degree in electrical engineering from Jilin University, Jilin, China, in 1995, and is currently working toward the M.S. degree in electrical and computer engineering at Auburn University, Auburn, AL. From 1997 to 2001, he was involved with RF engineering with Ericsson. His research interests include Verilog-A-based device modeling, and small-signal parameter extraction.

Alvin J. Joseph (S’92–M’97) received the B.E. degree in electrical engineering from Bangalore University, Bangalore, India, in 1989, and the M.S. and Ph.D. degrees from Auburn University, Auburn, AL, in 1992 and 1997, respectively, both in electrical engineering. His doctoral research involved the study of physics, optimization, and modeling of cryogenically operated SiGe HBTs. In 1997, he joined the SiGe Technology Development Group, IBM Microelectronics, Essex Junction, VT, where he has been involved in various aspects of installing several SiGe BiCMOS technologies into production. He is currently the Process Integration Team Leader for 0.18-m SiGe BiCMOS technology. He has authored or coauthored several technical journal papers and conference publications related to SiGe HBTs. Dr. Joseph was a member of the Device Physics Subcommittee for the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) from 1997 to 2001.

David L. Harame (S’77–M’83–SM’01–F’03) was born in Pocatello, ID, in 1948. He received the B.A. degree in zoology from the University of California at Berkeley, in 1971, the M.S. degree in zoology from Duke University, Durham, NC, in 1973, the M.S. degree in electrical engineering from San Jose State University, San Jose, CA, in 1976, and the M.S. degree in materials science and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, both in 1984. In 1984, he joined the Bipolar Technology Group, IBM T. J. Watson Research Center, Yorktown Heights, NY, where he was involved with the fabrication and modeling of silicon-based integrated circuits. His specific research interests at with the IBM T. J. Watson Research Center included silicon and SiGe-channel field-effect transistors (FETs), npn, and pnp SiGe-based bipolar transistors, complementary bipolar technology, and BiCMOS technology for digital and analog- and mixed-signal applications. In 1993, he joined the Semiconductor Research and Development Center (SRDC), Advanced Semiconductor Technology Center 9ASTC), IBM, Hopewell Junction, NY, where he was responsible for the development of SiGe BiCMOS technology. He managed SiGe BiCMOS technology development at the ASTC until 1997. In 1998, he joined the Manufacturing Organization, IBM, Essex Junction, VT, where he managed an SiGe technology group and installed the 0.5-m SiGe BiCMOS process in the manufacturing line. In 1999, he rejoined the SRDC, while remaining in Essex Junction, VT, and co-managed the qualification of a 0.25-m SiGe BiCMOS, as well as 0.18-m SiGe BiCMOS and two derivative SiGe BiCMOS technologies. In May 2000, he assumed management of the SiGe BiCMOS RF Analog Models and Design Kits area. He currently manages the RF/Analog and Mixed Signal Technology, Modeling, and Design Automation areas, SRDC. He is a Distinguished Engineer of the IBM Corporation. Dr. Harame is an Executive Committee member of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) and a member of the Compact Model Council.

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Optimization of EDGE Terminal Power Amplifiers Using Memoryless Digital Predistortion Nazim Ceylan, Jan-Erik Mueller, Member, IEEE, and Robert Weigel, Fellow, IEEE

Abstract—This paper describes a lookup-table (LUT)-based digital predistortion system usable for enhanced data for global system for mobile evolution (EDGE) handset transmitters. The system is memoryless and capable of improving average efficiency and performance in terms of the leakage power at offset frequencies and error vector magnitude. The obtainable efficiency at maximum linear output power is comparable, but at backoffs superior to commercial EDGE power amplifiers (PAs). Minimum system requirements on word length and LUT size have been investigated, which shows that a LUT having approximately 500 coefficients and a system word length of 13 bits are sufficient for EDGE. The proposed system is simple compared to basestation implementations comprising PA memory compensation and can be easily implemented in handsets in order to improve the overall system performance. The effects of antenna mismatch on system performance have been investigated. Index Terms—Linear circuits, memoryless systems, mobile communication, power amplifiers (PAs), telephone sets.

I. INTRODUCTION

I

N NEW-GENERATION mobile communication systems, power amplifier (PA) linearity is a key requirement. PA linearization methods are very attractive because they are capable of solving this problem. Sophisticated methods like adaptive digital predistortion (ADP) are used mostly in base-station PAs, but not in terminal PAs due to system complexity and cost. However, digital predistortion (DP) can also be useful in handsets if a complete system optimization can be achieved. In today’s mobile communication systems, the overall system performance is important. This means the individual integrated circuits (ICs ) must not necessarily have very high performance, but the systems composed of these ICs and embedded within an adequate architectural approach require good performance in terms of linearity and efficiency. This makes DP attractive because the PA can be designed for high efficiency and the linearity can be improved with DP. The combination of both gives design flexibility for achieving good linearity and efficiency at the same time. Global system for mobile (GSM) is one of the most widely used and reliable mobile communication systems. Enhanced data for global system for mobile evolution (EDGE) is a system

Manuscript received April 21, 2004; revised August 9, 2004. This work was supported in part by Infineon Technologies. The work of N. Ceylan was supported in part by the University of Erlangen–Nuremberg. N. Ceylan and J.-E. Mueller are with Secure Mobile Solutions, Infineon Technologies, 81677 Munich, Germany (e-mail: [email protected]; [email protected]). R. Weigel is with the Institute for Electronics Engineering, University of Erlangen–Nuremberg, 91058 Erlangen, Germany; (e-mail: weigel@ lte.e-technik.uni-erlangen.de) Digital Object Identifier 10.1109/TMTT.2004.840631

that is compatible to the GSM infrastructure and capable of transmitting high data rates up to 384 kb/s. This is possible by -shifted eight phase-shift keying (PSK) modulation. using Since this modulation creates a nonconstant carrier envelope, the signal must be amplified with a linear PA. It is known that the available linear output power of an amplifier can be increased with linearization. This means, at the same time, higher efficiency because, in solid-state PAs, the efficiency normally increases with increasing output power. In [1], the performance of a DP system in a GSM–EDGE base-station PA has been demonstrated. In handsets, the current trend is to implement simple predistortion systems with moderate improvement like analog predistortion with third- or fifth-order intermodulationdistortion compensation. However, in EDGE, the requirement for leakage power at the adjacent channel (at 200 kHz) is not critical compared with the first and second alternate channels (at 400 and 600 kHz) [1]. Therefore, a system capable of compensating high-order nonlinearities like DP is required. If the power consumption of digital signal processing in DP can be kept low compared to the efficiency improvement due to linearization, then DP can also be implemented in handsets. The topology of DP should also be simple for handset implementation. This paper investigates the performance of a simple memoryless lookup-table (LUT)-based DP system for EDGE handset implementation. Minimum system requirements in terms of the LUT size and the word length of the data and LUT coefficients have been calculated. The effects of antenna mismatch and required system changes in terminal transmitters for DP implementation are also discussed. To the authors’ knowledge, this paper investigates, for the first time, the quantization analysis for EDGE and the effects of antenna mismatch on the performance of terminal PAs with DP. II. THEORY OF MEMORYLESS DP The structure of DP depends on the transmitter path architecture. In today’s mobile communication systems, mainly an in-phase and quadrature (I&Q) presentation of baseband signals is used where a quadrature modulator upconverts baseband signals to IF or directly to RF. Fig. 1 shows an appropriate DP structure for direct conversion. It is a so-called gain-based predistorter [2]. Recent developments show that polar modulator gains in importance. A simple transmitter architecture with polar modulator and DP is shown in Fig. 2. In the following, those two architectures are compared with respect to their complexities. In the case of quadrature modulation (Fig. 1), the signal samples in the digital domain are multiplied one by one with LUT coefficients selected by input signal addressing.

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Fig. 1.

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Memoryless DP block diagram for direct quadrature modulation.

Fig. 2. Memoryless DP block diagram for polar modulation.

The coefficients stored in the LUT have been calculated using the measurement-based PA AM–AM and AM–PM distortion characteristics, which is going to be discussed in detail in Section III. The LUT coefficients are calculated in such a way that the combination of the predistorter and PA will have a linear response at the output [2]. Predistorted digital signals are converted to analog [digital-to-analog converter (DAC)], low-pass filtered, and sent to the quadrature modulator. We have assumed to have an ideal modulator between the predistorter and PA. However, the imperfections in the modulator can result in significant performance degradation in amplifier linearization circuits [3]. For measurements, a precision signal generator has been used as a modulator, which can be assumed to be ideal. The direct modulated predistorted signal is sent to the PA and then to the antenna. LUT address calculation can be done in different ways, including: 1) input amplitude; 2) power; or 3) optimum addressing. In [4], the difference between amplitude and power addressing is explained. Input power addressing is the easiest one and it requires squaring Q&I branches and adding them

up in the addressing block. The result is squared magnitude of the complex input signal, which corresponds to its power. Since the LUT coefficients are calculated for input signal values equispaced in power, there is a high coefficient density (low spacing between coefficients) near to saturation, which means good linearization for low backoff operation. However, if the PA also has nonlinearities in the high backoff region, as in classes B or AB, which is mostly the case for today’s mobile communications handsets for efficient operation, then the correction may not be sufficient in this region. On the other hand, for amplitude addressing a square-root calculation unit is required in addition to the operations in the power addressing method explained above. Square-root operation is a computationally intensive block [5]. Amplitude addressing gives, in general, better intermodulation distortion (IMD) suppression due to its uniform coefficient distribution equispaced in voltage in both high and low backoff. In optimum addressing, the coefficients are dense in the regions where PA nonlinearity is high, and less dense in low nonlinearity regions [6]. This means the coefficients are closely spaced in nonlinear regions in order to increase the performance. According to [6], the IMD performance in amplitude addressing is better than power addressing (approximately 10 dB), but the best IMD performance is obtained with optimum addressing, which is 1–4 dB better than amplitude addressing. However, optimum addressing is cumbersome and it depends on the amplifier, modulation, and backoff during the operation. Therefore, amplitude addressing seems to be a good overall compromise in terms of its performance, modulation format, and PA-type independency and simplicity. These issues are important especially for application in battery-operated small-size handsets. In the case of polar modulation (Fig. 2), the signal samples in the digital domain are modified one by one, as in the quadrature modulator case. A sigma–delta modulator (SDM) is used to modulate the phase, and this phase-modulated signal is multiplied with amplitude data using a mixer. The resultant signal is input to the PA and then sent to the antenna. Amplitude addressing would be especially advantageous if a polar modulator is used instead of a vector modulator. Since the amplitude data is already available in polar modulation architecture, there is no need to have an address calculation block required in the system shown in Fig. 1 with a quadrature modulator. The predistorter is also simpler and needs just a multiplier and an adder to perform DP. In contrast to that in the quadrature modulator case, we need a complex multiplier composed of four multipliers, one adder, and one subtractor. Our measurement setup is such that the measurement results are representative for quadrature, as well as polar modulator architectures. The reason is that the predistorted signals are generated under ideal conditions suppressing analog imperfections in front of the PA, which would be normally different for those two architectures. The proposed DP is a memoryless system, which means it assumes that the AM–AM and AM–PM distortion of the PA depend just on the instantaneous value of the input signal envelope. Memory effects in handset PAs are normally not strong compared to base-station PAs [7]. Therefore, memoryless DP topology is a reasonable decision in terms of its performance

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(a) Fig. 3.

Measurement setup to obtain gain and phase characteristics of a PA.

and simplicity compared to much more sophisticated DP systems applied in base stations using Volterra series in order to take the memory effects into account. Using DP in the system increases the design freedom of PAs in terms of efficiency and linearity compromise. The efficiency can be maximized in PA design and the resultant nonlinearities can be corrected later by using DP. (b)

III. PA CHARACTERIZATION Gain and phase characteristics of the PA must be obtained precisely in order to have a good linearization performance. The instantaneous power measurement technique has been used to obtain gain and phase characteristics because they are more precise compared to the characteristics obtained with network analyzer measurements [8]. Fig. 3 shows the measurement setup. A generated two-tone signal is applied to the PA input and to channel 1 of the 2-GHz digital oscilloscope. The PA output signal is applied to channel 2 of the oscilloscope. Thus, input and output waveforms have been stored simultaneously, and this data has been used to obtain PA gain and phase characteristics. The amplifier used is a GSM handset PA from RF Micro Devices, Greensboro, NC (Tripleband GSM/DCS/PCS PA module RF3110). A two-tone signal with 270-kHz (bandwidth (BW) of EDGE signals) tone spacing has been used as the input because the peak-to-average power ratio (PAR) of it (3 dB) is close to the PAR of the EDGE signal (3.2 dB) and it covers the complete input signal range from zero to peak value. Since AM–AM and AM–PM distortion is due to input power, but not due to the phase, we have used such a simple amplitude modulated signal. Compared to the setup in [8], a double-channel IF downconverter has not been used in the measurement setup because of the high sampling capability of the oscilloscope. This data has been down-converted, filtered, and processed inside the computer. Doing this gave us the possibility to eliminate all imperfections that can appear due to analog down-conversion and filtering. This makes our setup simpler and characterization more accurate compared to [8]. In the following, the nonlinear effects due to PA behavior are explained. The PA characteristics have been investigated at high output power levels intentionally in order to see the compression characteristics of the PA. Fig. 4(a) and (b) shows the PA input and output signal (phasor) amplitude and phase curves, respectively. The values seen on the -axis of Fig. 4(a) are scaled

(c) Fig. 4. (a) Input and output two-tone signal envelopes. (b) Input and output two-tone signal phases. (c) Type of change in output phasor diagram due to AM–AM and AM–PM nonlinearities.

for demonstration purposes. The compression at PA output is obvious from this time-domain signal, which is AM–AM distorted. From Fig. 4(b), AM–PM distortion is also obvious at high instantaneous powers. Fig. 4(c) demonstrates the phasor diagram of the ideal input two-tone signal and distorted output signal due to AM–AM and AM–PM nonlinearity of the PA. The gain characteristics of the PA is obtained by dividing the output signal amplitude by the input amplitude [see Fig. 4(a)] and the phase characteristics by subtracting the input phase from the output phase [see Fig. 4(b)] for each point. Fig. 5(a) and (b) show the power gain and output phase of the PA (RF3110) obtained in this way. A high-degree polynomial function has been fitted to those data revealing PA characteristics. There are small hysteresis loops visible in the gain and phase characteristics at high input power values, which is a measure of memory effects [8].

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Fig. 6.

DP measurement setup.

(a)

(b) Fig. 5. PA.

(a) Gain curve of the measured PA. (b) Phase curve of the measured

There may be some differences between PA characterizations with a two-tone and EDGE signals. There are mainly two reasons for possible mismatch, one is the difference between PARs and the other is the effect of PA memory. Since PARs of the two-tone and EDGE signals are close, it is assumed that the deviation due to the PAR is negligible. On the other hand, the EDGE signal is composed of a lot of spectral components in a specified BW and if there were strong memory effects, then the deviation between two-tone and EDGE signal characterizations would be significant. However, the memory effects are low in handset PAs [7] and we simply neglect them because we try to find a method giving good results with very low effort. Two-tone signal characterization shows that there are memory effects for a frequency spacing of 270 kHz, but they are very low. In today’s mobile communications systems, a reliable operation is essential. If DP is implemented in a system, then the LUT coefficients must match the PA well and the system must have a good performance under various conditions like changing temperature or supply voltage. There are mainly two DP architectures: open loop and closed loop with adaptation. In the open-loop case, one way is to calibrate each system by measuring its AM–AM and AM–PM characteristics, which is complicated. However, if the PA characteristics are reproducible having low deviations with process or assembly variations, there is a good chance that simple calibration procedures similar to those used today may be sufficient. On the other hand, the effects of temperature and supply voltage variations can be taken into account by implementing or using available sensors in the system because their effects are predictable. In closed-loop implementation, however, the effects of all these variations are corrected automatically, requiring no special calibration process during fabrication. The drawback is the requirement of an additional feedback path and signal processing, increasing the system cost, size, and power consumption.

Fig. 7. PA output spectrum with and without predistortion at 28.5-dBm output power.

IV. PERFORMANCE OF MEMORYLESS DP The DP measurement setup is shown in Fig. 6 with RF3110. The LUT coefficients have been calculated using measured gain and phase characteristics from Fig. 5(a) and (b). The input predistorted EDGE signal has been obtained by means of simulations for each measured output power level. Those data have been downloaded to an arbitrary waveform RF generator and used as input signal for the PA. The resultant output is analyzed by a vector signal analyzer. Fig. 7 shows the PA output spectrum with and without DP for 28.5-dBm output power. Without DP, the spectrum mask is not fulfilled, whereas with DP 3-dB margin is obtained showing the usefulness of the concept. A significant improvement in the adjacent channel leakage power (ACLP) ratio and error vector magnitude (EVM) have been observed using DP. ACLP at 400- and 600-kHz offset frequencies versus output power and EVM versus output power are shown in Fig. 8(a)–(c), respectively. ACLP at 200-kHz offset is not shown because it is not critical compared to 400 and 600 kHz. The specification limits [9] including a 3-dB spectrum mask margin for ACLP at offset frequencies are shown for comparison in Fig. 8(a) and (b). As can easily be seen from this figure, DP improves the output RF spectrum at 400 kHz significantly and at 600 kHz slightly. There is also improvement in EVM rms values [see Fig. 8(c)]. EVM rms should not exceed 9% according to specifications [9], which is fulfilled even without DP. By applying DP, the maximum output power increases from 25 to 28.5 dBm and PA efficiency increases from 15.2% to 23.4% while fulfilling the spectrum mask with a 3-dB margin with respect to leakage power at 400- and 600-kHz offsets. EVM rms has also been reduced from 3.4% to 2.6% at 28.5-dBm

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output power values above 25 dBm, where the PA by itself does not fulfill linearity requirements. DP can be switched off during lower output power transmission in order to save power. Thus, a significant improvement in PA performance can be achieved by DP implementation. The measurement and simulation results agree well at high output powers where DP is beneficial. For decreasing power levels, the agreement gets worse. At 400-kHz offset, maximum difference comes up to approximately 5 dB and at 600 kHz up to 10 dB. The reasons for deviations are supposed to be measurement and simulation errors and memory effects. However, there is still a significant improvement in system performance due to the benefit at high powers. V. QUANTIZATION ANALYSIS

(b)

(c) Fig. 8. (a) Measured ACLP at 400-kHz offset relative to the carrier with and without predistortion. (b) Measured ACLP at 600-kHz offset relative to the carrier with and without predistortion. (c) Measured EVM rms with and without predistortion.

output power. At maximum linear output power of 28.5 dBm, the power-added efficiency (PAE) of the used PA (RF3110) plus DP is 23% (estimated power consumption of DP is 50 mW), which is close to commercial PAs designed for EDGE. However, for lower output powers, the proposed system is significantly better because the quiescent current for the GSM PA has been measured to be 180 mA, whereas it is 480 mA for an EDGE PA (RF3145) from the same manufacturer. Since handsets in EDGE are not supposed to always transmit at maximum output power, the system efficiency depends not only on PA efficiency at the maximum output power, but also on efficiencies at lower output powers. Measured PAs are not state-of-the-art, but measurement results show that proposed system is advantageous, especially during operation with high backoff. This results from the fact that constant envelope PAs can be more easily designed for lower quiescent currents compared to dual-mode linear PAs where more design tradeoffs have to be taken into account. The efficiency can be further improved with a careful design of the PA. The PA used has been designed to give maximum efficiency at output power of 35 dBm for GSM, which is not optimum for EDGE. DP is not required for all output power values according to the measurement results in Fig. 8(a) and (b). It is required just for

In [4], a detailed quantization analysis for digital baseband predistortion is presented. The relation between adjacent channel interference (ACI) and the word length at different parts of the system has been calculated, and it has been stated that, with a careful design, the efficiency of the system can be highly improved. We are going to define the minimum requirements of a DP system in EDGE mobile stations in terms of LUT size and word length by means of simulations done in the Advanced Design System (ADS), Agilent Technologies, Palo Alto, CA. For this purpose, DP simulations have been done for six different LUTs having 2560, 1280, 640, 320, 160, and 80 coefficients, and their performances have been compared in Fig. 9(a) and (b). This figure shows the improvement in the leakage powers at 400- and 600-kHz offsets and spectrum mask limits including a 3-dB margin. The measurement results without DP are also shown in this same figure. Simulation results are shown just for these two frequencies because they are the most critical issues in terms of linearity in EDGE. The word length in DP has been selected to be 14 bits. As can be seen with decreasing LUT size, the offset powers at PA output can still be in the specified region and be improved compared to the output without linearization. However, there is a trend in leakage power to increase with respect to the carrier with a decreasing output power for small LUTs . For large LUTs, this effect is negligible and the leakage power ratio stays almost constant for small output powers. The reason for worse performance at low powers is the decrease in the number of LUT coefficients used to multiply with the input signal. Fig. 9(a) and (b) shows that the performances of LUTs having 640, 1280, and 2560 coefficients are very similar. This means a LUT having 640 coefficients can be used for a good DP performance in the case that a word length of 14 bits is used. The LUT size has been kept constant in the following simulations and the system word length has been changed in order to see its effect on DP performance. The LUT having 2560 coefficients has been used for simulations in order to see degradation just due to the word length, but not due to the LUT size. Fig. 10 shows the simulation results with word lengths of 11–14 bits at 1.8-MHz frequency offset. It is visible from Fig. 10 that the noise floor decreases approximately 6 dB for each additional bit, agreeing with relation between the signal-to-noise ratio and word length [4]. The word length is not critical for 200 and

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(a) Fig. 11.

(b) Fig. 9. (a) ACLP at 400-kHz offset with different LUT sizes. (b) ACLP at 600-kHz offset with different LUT sizes.

Measurement setup for antenna mismatch.

mask in EDGE. Using smaller word length depends on DP implementation in the system. Actually, today’s mobile communication applications are not as simple as shown in Fig. 1. There are some additional blocks in the digital domain like frequency, dc offset, and I&Q imbalance correction and interpolation units. The word lengths required in these operations are relatively high (12–13 bit) in order to avoid large rounding errors. Therefore, the word length of DP need to be correspondingly high for a proper operation with a complete system. There is a mismatch between ACLP measurements and simulations because simulation results in Fig. 9(a) and (b) show just the effects of LUT size due to ideally selected environmental conditions. LUT size of 500 coefficients has been selected since there is no significant improvement in the performance of DP by increasing the LUT size further. If a lower LUT size is used, then the linearization performance is expected to be worse, especially at lower output powers, which may be acceptable for some applications.

VI. ANTENNA MISMATCH

Fig. 10.

ACLP at 1.8-MHz offset with different word lengths.

400 kHz. However, its effect becomes obvious for higher frequency offsets. We assume that if the output power spectrum fulfills the spectrum mask at 1.8 MHz, then the power at lower frequency offsets should also be below the spectrum mask. The noise floor increases with reducing the word length and the simulations have shown that the power at frequencies higher than 1.8 MHz is almost equal to the power at 1.8 MHz if DP is used. Since the maximum allowed power is 71 dBc at frequency offsets greater than 6 MHz [9], we select a word-length value that results in a noise power less than 71 dB minus a margin of 3 dB. According to Fig. 10, a word length of 13 bits can be selected, which results in a noise power of approximately 78 dBc. Simulations show that a LUT having approximately 500 coefficients and a word length of 13 bits can fulfill the spectrum

Very favorable DP system performance has been shown under optimum PA output match conditions. In the following, the impact of antenna mismatch is investigated. Since mobile phones can be moved continuously and they can be put everywhere, the environment of an antenna can change and, therefore, the antenna impedance seen by the system can change continuously. This results in changes of voltage standing-wave ratio (VSWR) at the PA output. We have used the measurement setup shown in Fig. 11 in order to see the effects of antenna mismatch on the performance of DP. A network analyzer has been used in the setup in order to adjust the tuner for different VSWR values and phases of the load. Fig. 12(a) and (b) describes the influence of antenna mismatch for maximum output power (28.5 dBm) with and without DP for VSWR of three and phase angles of the load between 0 –360 . Fig. 12(a) shows the ACLP at 200, 400, and 600 kHz as function of load phase. The system performance under worst case conditions with DP is at 200 kHz superior ( 3 dB), at 400 kHz comparable, and at 600 kHz inferior ( 3 dB) to the performance without DP. Fig. 12(b) describes EVM rms as function of load

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VIII. CONCLUSION

(a)

DP linearization for EDGE handset PAs has been investigated. It has been shown that memoryless DP can significantly improve system linearity and efficiency. A nonlinear GSM PA has been linearized and tested for EDGE achieving a linear output power of 28.5 dBm with a system efficiency of 23%, which is close to commercial EDGE PAs . On the other hand, at backoffs, the efficiency of the proposed system can be much higher than the PAs designed for EDGE, which results in significant improvement in average system efficiency. The simulations with an EDGE signal show that a LUT having approximately 500 coefficients and system word length of 13 bits are sufficient in order to use DP fulfilling EDGE specifications. The effects of antenna mismatch on DP performance have been investigated. The performance degrades compared to matched load conditions, but was found to be comparable to the case without DP. REFERENCES

(b) Fig. 12. (a) Variation of ACLP at the output with and without predistortion as function of load phase (P out = 28:5 dBm and VSWR = 3) for different frequency offsets. (b) Variation of EVM rms at the output with and without predistortion as function of load phase (P out = 28:5 dBm and VSWR = 3) for different frequency offsets.

phase. The performance without DP under worst case conditions is 11.2%; however, with DP, only 9.7%. These results indicate that the load mismatch performances in both cases are approximately the same order. To take full advantage of the DP system also under mismatch conditions, additional measures are required such as using an isolator or using adaptive DP. VII. REQUIRED SYSTEM MODIFICATIONS There should be some modifications in a terminal transmitter to be able to implement DP [10]. First, the BW of the reconstruction filters after DACs must be increased in order to let the predistorted signals pass without degradation because predistorted signals have wider BWs. Second, increase the word length of DACs if required. Since PAR of the predistorted I&Q phase signals are higher (can be approximately 3 dB in voltage) than without a predistortion case, increasing the word length can be helpful to keep quantization noise low. However, if the noise is not a problem at high output powers where DP is used, then it can be left as it is. The third modification may be in the transmitter chain portion between reconstruction filters and PA, which can be composed of analog baseband amplification and the correction circuit, modulator, and preamplifier. This path should be linear enough, have no significant I&Q imbalance and, thus, be able to handle the predistorted signals without significant distortion, which have higher PAR.

[1] P. B. Kenington, M. Cope, R. M. Bennett, and J. Bishop, “A GSM-EDGE high power amplifier utilizing digital linearization,” in IEEE MTT-S Int. Microwave Symp. Dig., May 2001, pp. 1517–1520. [2] J. K. Cavers, “Amplifier linearization using a digital predistorter with fast adaptation and low memory requirements,” IEEE Trans. Veh. Technol., vol. 39, no. 4, pp. 374–382, Nov. 1990. [3] , “The effect of quadrature modulator and demodulator errors on adaptive digital predistorters for amplifier linearization,” IEEE Trans. Veh. Technol., vol. 46, no. 2, pp. 456–466, May 1997. [4] L. Sundström, M. Faulkner, and M. Johansson, “Quantization analysis and design of a digital predistortion linearizer for RF power amplifiers,” IEEE Trans. Veh. Technol., vol. 45, no. 4, pp. 707–719, Nov. 1996. [5] P. Andreani and L. Sundström, “Chip for wideband digital predistortion RF power amplifier linearization,” Electron. Lett., vol. 33, no. 11, pp. 925–926, May 1997. [6] J. K. Cavers, “Optimum table spacing in predistorting amplifier linearizers,” IEEE Trans. Veh. Technol., vol. 48, no. 5, pp. 1699–1705, Sep. 1999. [7] J. S. Kenney, W. Woo, L. Ding, R. Raich, H. Ku, and G. T. Zhou, “The impact of memory effects on predistortion linearization of RF power amplifiers,” in Proc. 8th Int. Microwave Optical Technology Symp., June 2001, pp. 189–193. [8] S. Boumaiza and F. M. Ghannouchi, “Realistic power-amplifiers characterization with application to baseband digital predistortion for 3G base stations,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 12, pp. 3016–3021, Dec. 2002. [9] Technical Specification Group GSM/EDGE Radio Access Network Radio: Transmission and Reception, ETSI Specification 3 GPP TS 45.005 V6.2.0, 2003. [10] N. Ceylan, J. E. Mueller, T. Pittorino, and R. Weigel, “Mobile phone power amplifier linearity and efficiency enhancement using digital predistortion,” in Proc. 33rd Eur. Microwave Conf., vol. 1, Oct. 2003, pp. 269–272.

Nazim Ceylan was born in Kurtalan, Turkey, in 1976. He received the B.Sc. degree in electrical engineering from the Middle East Technical University, Ankara, Turkey, in 1998, the M.Sc. degree from the University of Kassel, Kassel, Germany, in 2000, and is currently working toward the Ph.D. degree at the University of Erlangen–Nuremberg, Erlangen, Germany, in conjunction with Infineon Technologies, Munich, Germany. His current research interests include efficient power-amplification structures in transmitters for mobile communications, as well as terminal PA behavioral modeling and linearization with DP.

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Jan-Erik Mueller (M’86) received the Dipl.-Ing. and Dr.-Ing. degrees in electrical engineering from the Technical University of Munich, Munich, Germany, in 1973 and 1978, respectively. From 1975 to 1978, he was an Assistant Professor with the Institute of Electronics, Technical University of Munich, where he was engaged in research of high-sensitivity broad-band photodetectors. From 1978 to 1999, he was with the III–V Electronics Department, Siemens Corporate Technology, where he was involved in the development of GaAs MESFET, high electron-mobility transistor (HEMT), and HBT technologies and circuits for commercial applications including millimeter-wave and power applications. He is currently the Senior Principal for Si and III–V technologies with Infineon Technologies, Munich, Germany. Within their Wireless Innovation Group, he investigates new technology, and circuit and system concepts mainly for transmitter applications. He lectures on devices and circuits for mobile communications at the Technical University of Berlin, Berlin, Germany. He has authored or coauthored over 60 papers. He holds numerous patents. Dr. Mueller has served as a guest editor for the IEEE JOURNAL OF SOLIDSTATE CIRCUITS and has been a Distinguished Lecturer for the IEEE Electron Devices Society. Since 1994, he has served on the IEEE GaAs IC Symposium Technical Program Committee. He is a member of the IEEE Electron Device Society Compound Semiconductor IC Technical Committee, and is co-chair of the recently established the International Technology Roadmap for Semiconductors (ITRS) Wireless Working Group.

Robert Weigel (S’88–M’89–SM’95–F’02) was born in Ebermannstadt, Germany, in 1956. He received the Dr.-Ing. and Dr.-Ing.habil. degrees in electrical engineering and computer science from the Munich University of Technology, Munich, Germany, in 1989 and 1992, respectively. From 1982 to 1988, he was a Research Engineer, from 1988 to 1994, a Senior Research Engineer, and from 1994 to 1996, a Professor of RF circuits and systems with the Munich University of Technology. In Winter 1994–1995, he was a Guest Professor for SAW technology with the Vienna University of Technology, Vienna, Austria. Since 1996, he has been Director of the Institute for Communications and Information Engineering, University of Linz, Linz, Austria. In August 1999, he co-founded Danube Integrated Circuit Engineering (DICE), Linz, Austria, an Infineon Technologies Development Center, which is devoted to the design of mobile radio circuits and systems. In 2000, he became a Professor for RF engineering with Tongji University, Shanghai, China. In 2002, he became the Director of the Institute for Electronics Engineering, University of Erlangen–Nuremberg, Erlangen, Germany. He has been engaged in research and development on microwave theory and techniques, integrated optics, high-temperature superconductivity, surface-acoustic wave (SAW) technology, and digital and microwave communication systems. Within these fields, he has authored or coauthored over 400 papers and has presented over 200 international papers. He is a reviewer for European and Asian research projects and international journals. Dr. Weigel is a member of the Institute for Components and Systems of The Electromagnetics Academy, and a member of the German Informationstechnísche Gesellschaft (ITG) and the Austrian Engineering Society (ÖVE). Within the IEEE Microwave Theory and Techniques Society (IEEE MTT-S), he is a member of the Administrative Committee (AdCom), chair of the Austrian COM/MTT Joint Chapter, Region 8 coordinator, Distinguished Microwave Lecturer, and vice-chair of MTT-2 Microwave Acoustics. In 2002, he was the recipient of the German ITG award.

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A Simple Systematic Spiral Inductor Design With Perfected Q Improvement for CMOS RFIC Application Chih-Yuan Lee, Tung-Sheng Chen, Joseph Der-Son Deng, and Chin-Hsing Kao

Abstract—In this paper, a systematic design procedure based on key factor analysis of the curve has been proposed. In addition to inductor design, we also present a technique that combines optimized shielding poly, and proton implantation treatment is utilized to improve the inductor value. The shielding effect of poly-silicon and the semi-insulating characteristics of proton-bombarded substrate have added a 37% and 54% increment to the value of the inductors, respectively. The combination of the two means has created a multiplication of their individual contribution rather than addition. The dramatic improvement of the value resulted from the doping level and film thickness optimization of a poly shield layer combined with a proton implantation treatment. A phenomenal -value increment as high as 122% of 4-nH spiral inductors can be realized. This technique shall become a critical measure to put inductors on a silicon substrate with satisfactory performance for Si-based RF integrated-circuit applications. Index Terms—Poly shield, proton implant, grated circuit (RFIC), spiral inductor.

value, RF inte-

I. INTRODUCTION

T

HE RACE of on-chip spiral inductor design has been accelerated in recent years due to the strong push of a system-on-chip (SOC) notion for handheld portable communication applications. On-chip inductors generally enhance the reliability and efficiency of silicon-integrated RF circuits. They can offer circuit solutions with superior performance and contribute to high-level integration. However, there are some efforts required for the purpose of achieving satisfactory inductor performance such as sufficient quality ( ) factor and designated inductance value ( ) in the designing stage of silicon-based communication integrated circuits (ICs) [1]. Since inductors with sufficient values are indispensable in many RF circuits, it is essential to develop a practical way of constructing inductors by a CMOS process with reasonable values. In the past, SPICE and electromagnetic (EM) simulators have been applied to assist designing planar inductors and predicting their performance [2], [3]. However, it is usually not sufficient to rely on simulation alone. Due to the lossy nature of silicon substrate, the physical model of spiral inductors over the

silicon substrate has become the beacon of proper design [4]. The substrate effect that limits spiral inductor performance has been considered carefully in previous analysis such as Greenhouse’s work [5]. Even the substrate effect known as the optimized inductor design was still difficult. When a spiral inductor on silicon operates at high frequency, two substrate-related energy loss mechanisms take place. One is caused by the transient electric field radiating from the inductor metal strips and the other is induced by the quasi-TEM EM wave propagating from the inductor core. As the electric field penetrates into the silicon substrate, ohmic dissipation results. In addition, the time-varying magnetic field of the EM wave would induce an eddy current in the lossy substrate and lead to energy dissipation. As a result, the energy stored by the inductor is subtracted and value drops. Up to now, much effort, such as the micromachining process or silicon-on-insulator (SOI) structure, has been adopted in reducing substrate loss [6], [7]. However, most techniques involve a complicated process. In this paper, we propose a simple procedure of systematic design for an Si-based spiral inductor. In addition, a feasible technology that combines a grounded poly shield and proton implant to reduce substrate loss has been demonstrated for the sake of pursuing -value improvement. Although a poly shield has been utilized in the past [8], [9], most results are unsatisfactory due to the negligence of process conditions. In our experiment, careful optimization of poly doping concentration has been conducted. Moreover, a selected proton implant condition has been employed to maximize the inductor value. II.

-CURVE ANALYSIS

The design procedure begins with the consideration of the parallel equivalent-circuit model of a spiral inductor, as shown in Fig. 1. The series inductance , series resistance , series , oxide capacitance between feed-forward capacitance , the spiral inductor and Si substrate, Si substrate resistance are represented as follows [4]: and parasitic capacitance

Manuscript received April 21, 2004. This work was supported by the National Nano-Device Laboratory under Contract NDL-92S-C-079. C.-Y. Lee and C.-H. Kao are with the Department of Applied Physics, Chung-Cheng Institute of Technology, National Defense University, 335 Taiwan, R.O.C. (e-mail: [email protected]). T.-S. Chen and J. D.-S. Deng are with the Department of Electric Engineering and School of Defense Science, Chung-Cheng Institute of Technology, National Defense University, 335 Taiwan, R.O.C. Digital Object Identifier 10.1109/TMTT.2004.841216 0018-9480/$20.00 © 2005 IEEE

(1) (2) (3) (4) (5)

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Fig. 2. f

Q curve of a spiral inductor with the Q set by key factors S ; S ; and f .

value and corresponding

Fig. 1. Circuit model and corresponding element parameters determined by the device structure and process conditions.

where and are the metal width and total length of the inductor body. In (1), is the dc conductivity and is the skin depth of the Al metal. In (2), and are the number of turns and the thickness of the interlevel dielectric between and , respectively. In (3), the thickness between the spiral inductor and Si substrate is . In (4) and (5), and represent the capacitance and conductance of the Si substrate per unit area. According to the fundamental definition, one can derive the factor of the silicon-based spiral

Fig. 3. General trend of maximum Q factor with corresponding variations of element parameters.

(6) where (7) (8) Based on (6), the curve versus frequency can be decomposed and depicted by three critical factors, which are: 1) the ; 2) the high-frequency slope ; low-frequency slope , as shown in Fig. 2. The inand 3) the resonant frequency ductor characteristic can then be predicted as long as the key factors are determined. The general trend of element-parameter influence on is examined first in Fig. 3. Among all element parameters, the and have exhibited the most sigvariations of . Lower and tend to result nificant impact on in a greater value. A similar trend can be achieved with in. creased For a detailed study of a high- inductor design, the influence of crucial element parameters on key factors of the curve must be studied. The first element parameter considered is . The variation trend indicates that lower tends to result in a greater low-frequency slope and higher resonant frequency. However, inductance is basically not tunable for optimization due to the constraint placed by circuit designers.

Once is determined, the element parameters that play important roles in perfecting the key factors of the curve must be recognized. Based on circuit simulation results, as shown in Fig. 4, among the variations of all element parameters, reducing of the inductor wire is the only effective serial resistance way to increase the low-frequency slope of the curve. Therebecomes critical in setting the desired fore, optimizing value at the designated frequency by controlling . Possible include the metal thickness increment, measures to reduce geometry optimization, and the adoption of copper metallization. Still, further optimization of the high-frequency slope is required since they must co-act to reach the desired . might jeopardize the value even with high A low . The element parameter variations indicate that the high-frequency slope can be enlarged with an increased substrate resistance, oxide thickness, or reduced inductor serial resistance. predominates over and . Among the three options, One possible way to increase the effective substrate resistance is to insert a grounded shielding layer between the inductor and substrate [9]. Another way is to create a semi-insulating substrate by proton implantation [10]. A design procedure of high- inductors can be established as shown in the flowchart of Fig. 5. To begin with, the design specification of inductance, bandwidth, working frequency, and can then be demaximum quality factor must be given first. termined from the working point value and its corresponding

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Fig. 4. Influence of element-parameter variation on key factors of spiral inductors. Fig. 6. Micrograph and corresponding cross-sectional view of the test structure with a poly shielding layer.

the formation of n poly-silicon film, a 1- m-thick tetraethylorthosilicate Si(OC H ) (TEOS) was deposited by PECVD as an insulation layer on top of poly-silicon. To ground poly-silicon as desired, contact holes through the TEOS layer were opened and CoSi was formed before the 1- m-thick aluminum ) was sputtered and served as an underpass metal metal 1 ( of the spiral inductors. After , another TEOS (1 m) was deposited as inter-level dielectrics and via-holes were etched. , 1 m) was sputtered and patFinally, aluminum metal 2 ( terned as the main body of spiral inductors. Fig. 6 shows the top view and cross-sectional view of the test structure (metal width of 10 m and spacing of 4 m) used in this study. RF parameters were characterized before and after proton implant cm energy MeV) by a network ana(dosage lyzer (Hewlett-Packard 8510C) and the parasitic effects were eliminated through standard short-open-load-through (SOLT) calibration and a deembedding procedure. IV. RESULTS AND DISCUSSION

Fig. 5.

Flowchart of designing optimal spiral inductors.

frequency. Meanwhile, the appropriate value can be determined by an empirical equation summarized from Fig. 5. The resonant frequency plays an important role in total capacitance and from . Finally, and and one can extract of the model can be decided with . The desired and specifications established by the circuit designer are transformed into the three key factors of the curve and appropriate element parameters must then be fine tuned to reach the design goal. III. EXPERIMENTAL The test wafers began with wet oxidation (0.8 m) of silicon, followed by thin-film poly-silicon deposition. Phosphorus implantation with dosage ranging from 5 10 cm to 5 10 cm were then performed over separate test wafers. After

In order to raise by increasing effective , a practical process technique with an insertion of a grounded poly-shield layer and a proton implant treatment has been adopted to accomplish such a purpose. Although a poly shield has been utilized in the past, most results are unsatisfactory due to the negligence of process conditions. In this study, optimization of film thickness and doping concentration has been assessed carefully and significant improvement of the value has been obtained. EM simulation by IE3D indicates that the thinner the shielding-poly layer, the better inductor performance can be achieved, as shown in Fig. 7. However, current process controllability of poly film thickness has limited it to be no less than 0.05 m. The purpose of the grounded poly-silicon layer is to obstruct the transient electric field and EM wave from penetrating into the silicon substrate. However, the conductivity of the shielding layer must be determined carefully. If the shielding layer is highly conductive, as conventional gate poly is, a significant eddy current tends to be formed on the shield and the factor is actually degraded. If the shielding layer is highly insulating, on the other hand, it will be transparent to the electric field, as well

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Process window of poly-silicon thickness for

Q

improvement.

Fig. 9. Improvement of

Q curve with various proton implant conditions.

TABLE I EXTRACTED PARAMETER VALUES OF THE COMPONENTS IN THE EQUIVALENT-CIRCUIT MODEL

Fig. 8. Process window of poly-silicon doping concentration for refinement.

Q

as the EM wave, and plays no role in -factor improvement. Therefore, the goal is to set up a shielding layer that can reduce the electric field and EM wave penetration effectively without inducing a considerable eddy current on the shield itself. A process window of poly doping concentration between 10 –10 cm has been established from EM simulation and minimum implant dosage available in existing process technology, as shown in Fig. 8. The major influence of a grounded shielding layer is to obstruct the penetration of the transient electric field, as well as the quasi-TEM mode EM field. The interception of transient fields has caused increased effective , which, in turn, leads to -value improvement due to reduction of substrate loss. Notice that a poly-Si optimization is critical since a conductive layer tends to induce eddy current on it, while an insulating layer would become transparent to directly is to imall transient fields. Another way to raise plant the substrate with a proton, which creates deep-trapping levels in the forbidden gap to annihilate free carriers [10]. For maximum -value enhancement to be achieved, an optimized process condition of proton implantation is required, as shown in Fig. 9. By analyzing the equivalent-circuit model in Fig. 1 and measured data of test structures with various process conditions and treatment, the extracted model parameter values through the fine-tuned curve-fitting procedure of acquired data have been obtained and are listed in Table I. It is found that the influence of

the poly-silicon layer is reflected on a certain element value in the equivalent-circuit model. Specifically, the oxide capacitance is decreased by 30% and the equivalent substrate resistance is increased by 100% with a grounded poly-silicon layer compared to the one without poly-silicon. For proton implant by approximately three times is treatment, the increment of the result of proton-induced deep trapping levels that are capable of capturing free carriers and preventing them from conducting and the increase of imply current [10]. The decline of that the insertion of a grounded poly shield or the treatment of proton implantation has successfully reduced energy coupling and dissipation in the substrate. For the case where a grounded poly shield structure and proton implant treatment are both incorporated, the electric-field obstruction and eddy current reduction have been reinforced by the combined mechanisms. The grounded poly shield that impedes the electric field and EM wave has served as the first defense line and the increased substrate resistivity caused by proton implant has served as the second to avoid energy dissipation. The combination of a proton implant with a poly shield even reduces the substrate loss further. It is obvious to see that the most important parameter and -curve factor of the proposed and high-frequency techniques are substrate resistance , respectively. The technique utilized to increase slope and in this study is combining the grounded shielding

LEE et al.: SIMPLE SYSTEMATIC SPIRAL INDUCTOR DESIGN WITH PERFECTED

(a)

(b)

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Fig. 10. (a) -value improvement by various test structures and process conditions. (b) Inductance of various test structures and process conditions.

IMPROVEMENT

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and their combination are 37%, 54%, and 122%, respectively. The dramatic improvement of the value reveals that effective shielding on a semi-insulating substrate can multiply their individual contribution. Since the technique adopted in this study does not affect the original inductance design, as shown in Fig. 10(b), and no complicated process steps are involved, it is very attractive in CMOS technology. One concern that might be raised is the influence of proton implantation on poly-silicon film. If poly-silicon turns into an insulating layer after proton implant, the shielding effect would then vanish. Fortunately, experimental results indicate that the poly shielding effect is sustained even after the proton implant. The ineffectiveness of proton implantation on the conductivity of the poly shielding layer can be explained by the noncrystalline nature of poly-silicon that makes it difficult to create activated proton-induced trapping sites. It is, therefore, a practical tactic to promote the inductor value by incorporating a poly-silicon layer with a proton implant without jeopardizing the shielding effect. Further improvement can be expected if copper metallization is adopted. Simulation results indicate that extremely high increments of 188% and 356% can be achieved if 1- and 3- m-thick copper are utilized, respectively, as shown in Fig. 11. Since copper metallization has become more and more popular in CMOS technology recently, it can be expected that a high- inductor should be realized for SOC communication application in the near future. V. CONCLUSION A promising technique of designing and creating a highinductor has been demonstrated and proven to be very successful. The process optimization of poly-silicon with low dosage (10 cm ) has resulted in a maximum -factor increment of 37%. Further improvement is supplied when proton implant treatment is incorporated as well. The overall improvement (as high as 122%) has been achieved for the inductor with a poly shield and proton implant treatment. Since poly-silicon is fully compatible with the current CMOS process and proton implant can be focused on a passive element only, it is a feasible technique suitable for future RFIC design. ACKNOWLEDGMENT

Fig. 11. Frequency dependence of a different matallization technology.

Q factor for 3.5-turn inductors with

poly with the proton implant treatment. The result has lead to , as shown in Fig. 10(a). The major influence of a high grounded shielding layer is to obstruct the penetration of the transient electric field, as well as the quasi-TEM mode EM field. The interception of transient fields has caused increased , which, in turn, leads to -value improvement effective due to reduction of substrate loss. Another way to raise directly is to implant the substrate with a proton, which create deep-trapping levels to annihilate free carriers. The increments provided by a grounded poly shield, proton implant, of

The authors would like to thank Dr. G.-W. Huang and Dr. K.-M. Chen, both of the National Nano-Device Laboratory (NDL), Hsinchu, Taiwan, R.O.C., for their useful suggestions and assistance. The authors also thank T.-S. Duh, Institute of Nuclear Energy Research, Lungtan, Taoyuan, Taiwan, R.O.C., for proton implantation. REFERENCES [1] J. Craninckx and M. S. J. Steyaert, “A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 736–744, May 1997. [2] E. Ragonese, G. Girlando, and G. Palmisano, “A very accurate design of monolithic inductors in a 2D EM simulator,” in IEEE Electronics, Circuits, Systems Technique Dig., vol. 3, 2002, pp. 1199–1202. [3] J. R. Long and M. A. Copeland, “The modeling, characterization, and design of monolithic inductors for silicon RF IC’s,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 357–369, Mar. 1997.

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[4] C. P. Yue and S. S. Wong, “Physical modeling of spiral inductors on silicon,” IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 560–568, Mar. 2000. [5] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Trans. Parts, Hybrids, Packag., vol. PHP-10, no. 2, pp. 101–109, 1974. [6] J. B. Yoon, B. K. Kim, C. H. Han, E. Yoon, and C. K. Kim, “Surface micromachined solenoid on-Si and on-glass inductors for RF applications,” IEEE Electron Device Lett., vol. 20, no. 9, pp. 487–489, Sep. 1999. [7] C. M. Nam and Y. S. Kwon, “High-performance planar inductor on thick oxidized porous silicon (OPS) substrate,” IEEE Microwave Guided Wave Lett., vol. 7, no. 8, pp. 236–238, Aug. 1997. [8] T. Yoshitomi, Y. Sugawara, E. Morifuji, T. Ohguro, H. Kimijima, T. Morimoto, H. S. Momose, Y. Katsumata, and H. Iwai, “On-chip spiral inductors with diffused shields using channel-stop implant,” in Int. Electron Devices Meeting Tech. Dig., 1998, pp. 540–543. [9] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground shields for Si-based RF ICs,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743–752, May 1998. [10] C. P. Liao, T. H. Huang, C. Y. Lee, D. Tang, S. M. Lan, T. N. Yang, and L. F. Lin, “Method of creating local semi-insulating regions on silicon wafers for device isolation and realization of high- inductors,” IEEE Electron Device Lett., vol. 19, no. 12, pp. 461–462, Dec. 1998.

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Tung-Sheng Chen received the B.S. degree in physics from the Chung-Cheng Institute of Technology (CCIT), Taiwan, R.O.C., in 1986, the M.S. degree in electrical engineering from the Naval Postgraduate School, Monterey, CA, in 1990, and the Ph.D. degree in electrical engineering from the University of Texas at Austin, in 1998. While working toward the Ph.D. degree, he was also a Teaching Assistant with the University of Texas at Austin. In Summer 1997, he was an Intern with the Motorola Semiconductor Technology Laboratory. He is currently an Associate Professor with the Department of Electrical Engineering, CCIT, National Defense University (NDU), Tahsi, Taoyuan, Taiwan, R.O.C. His research interest include gigabyte digital random access memories (DRAMs), piezoresistive sensors, packaging-induced stressing effect on microelectronic devices, crosstalk related issues in RFIC, high- spiral inductors, and Flash memory development.

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Joseph Der-Son Deng was born in Taiwan, R.O.C., in 1965. He received the B.S. degree in applied physics from the Chung-Cheng Institute of Technology (CCIT), Taiwan, R.O.C., in 1988, the M.S. degree in electrical engineering from the Polytechnic University, New York, NY, in 1994, and is currently working toward the Ph.D. degree at the National Defensive University, CCIT. His doctoral research concerns the topic of high- Si-based spiral inductors. Since 1988, he has been with the Chung-Shang Institute of Science and Technology (CSIST), Lungtan, Taoyuan, Taiwan, R.O.C. His fields of research include quartz crystal resonators, monolithic crystal filters (MCFs), and microwave package and passive component design, as well as characterization.

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Chih-Yuan Lee received the B.S. degree in physics from the Chung-Cheng Institute of Technology (CCIT), Taiwan, R.O.C., in 1994, the M.S. degree in electrooptical engineering from National Sun-Yat-San University, Taiwan, R.O.C., in 1998, and the Ph.D. degree in physics from the Chung-Cheng Institute of Technology, National Defense University, Taiwan, R.O.C., in 2004. He is currently an Assistant Professor with the Department of Applied Physics, Chung-Cheng Institute of Technology, National Defense University. His research topics include RFIC-related devices, high- spiral inductors, and RFIC crosstalk issues.

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Chin-Hsing Kao received the B.S. degree in physics from the Chung-Cheng Institute of Technology, Taiwan, R.O.C., in 1980, and the Ph.D. degree in electrical engineering from the National Tsing-Hua University, Taiwan, R.O.C., in 1990. In 1990, he joined the Department of Applied Physics, Chung-Cheng Institute of Technology, where he is currently the Director of the College of Science. His research interests including MOS device analysis, CMOS low-temperature characteristics, radiation hardness of the CMOS devices, RFIC-related devices, RFIC crosstalk issues, and Flash memory development.

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A High Average-Efficiency SiGe HBT Power Amplifier for WCDMA Handset Applications Junxiong Deng, Student Member, IEEE, Prasad S. Gudem, Member, IEEE, Lawrence E. Larson, Fellow, IEEE, and Peter M. Asbeck, Fellow, IEEE

Abstract—The linearity of a silicon–germanium (SiGe) HBT power amplifier (PA) is analyzed with the help of a power-dependent coefficient Volterra technique. The effect of emitter inductance is included and the dominant sources of nonlinearity are identified. A dynamic current biasing technique is developed to improve the average power efficiency for wide-band code-division multiple-access (WCDMA) PAs. The average power efficiency is improved by more than a factor of two compared to a typical class-AB operation, while the power gain keeps roughly constant. The measured adjacent channel power ratio with 5- and 10-MHz offsets at 23.9-dBm average channel output power are 33 and 58.8 dBc, respectively, and satisfies the Third-Generation Partnership Project WCDMA specifications. The output power at the 1-dB compression point is 25.9 dBm. Index Terms—Average power efficiency, dynamic biasing, HBTs, intermodulation distortion, linearity, power amplifiers (PAs), Volterra series, wide-band code division multiple access (WCDMA).

I. INTRODUCTION N RECENT years, silicon–germanium (SiGe) has become a competitive candidate for the development of cellular handset power amplifiers (PAs) of third-generation (3G) wireless communication systems since SiGe exhibits good linearity, low-cost, and compatibility with BiCMOS technology [1]–[3], even though the SiGe HBT has a lower breakdown voltage and efficiency than its GaAs counterpart and is also affected by thermal runaway. The specifications of 3G wide-band code-division multiple-access (WCDMA) PAs are listed in Table I. To accommodate more users and maximize the usage of the spectrum in WCDMA systems, PAs have stringent limitations on linearity. PAs are also significant contributors to power consumption within mobile phones. Therefore, linearity and efficiency are the most critical parameters in the design of WCDMA handset PAs. The linearity of RF amplifiers is usually analyzed using Volterra series. Besides providing insights into the nonlinearity

I

Manuscript received April 23, 2004. This work was supported in part by the Center for Wireless Communications, University of California at San Diego and its member companies, and by the University at San Diego under a Discovery Grant. J. Deng, L. E. Larson, and P. M. Asbeck are with the Center for Wireless Communications, Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0407 USA. P. S. Gudem is with Qualcomm Inc., San Diego, CA 92121 USA. Digital Object Identifier 10.1109/TMTT.2004.840629

TABLE I 3GPP WCDMA PA SPECIFICATIONS [4]

mechanism, Volterra series can handle memory elements typical in the high-power amplifier [5]–[8]. To keep the analysis tractable while maintaining accuracy, Volterra series is often truncated to third order to analyze weakly nonlinear RF amplifiers operating in the class-A mode [6], [7]. On the other hand, high-efficiency code-division multiple-access (CDMA) PAs typically operate in the class-AB mode and exhibit strong nonlinearities. This renders the traditional Volterra analysis truncated to third-order inadequate and necessitates the inclusion of higher order terms, vastly increasing the complexity of the analysis. To keep the analysis tractable, and accurately predict the intermodulation distortion, we use a power-dependent coefficient Volterra technique [8]. Our analysis includes the effect of emitter bond-wire inductance, which is crucial to accurately predict the intermodulation distortion of PAs. With the help of the power-dependent coefficient Volterra technique, the dominant sources of nonlinearity in SiGe HBT PAs are highlighted. Average power efficiency (over the full range of output powers), instead of peak power-added efficiency (PAE), is the key factor determining the talk time and battery life for portable wireless applications [9]. Previous efforts using dynamic biasing techniques [10]–[12] achieved improved average power efficiency, but their power gains changed drastically when switched from the high-power region into the low-power region. This can create problems in the operation of the power control loop for a CDMA handset. Besides satisfying the specifications in Table I, our approach [13] substantially increases the average power efficiency, while keeping the power gain roughly constant. In Section II, the linearity of SiGe HBT PAs is analyzed using a power-dependent coefficient Volterra technique. In Section III, we describe our dynamic current biasing (DCB) technique used in improving the average power efficiency of the WCDMA PA.

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Fig. 1. Simplified schematic of a typical SiGe HBT PA.

Fig. 2.

Equivalent HBT nonlinear circuit for Volterra-series calculation.

In Section IV, measurement results are discussed. The conclusions are summarized in Section V. II. LINEARITY ANALYSIS OF SiGe HBT PAs A. Power-Dependent Coefficient Volterra Analysis A simplified schematic of a typical SiGe HBT PA is shown in Fig. 1, and its equivalent nonlinear circuit for Volterra series represents the source calculation is shown in Fig. 2, where impedance, including the effects of the input matching network, represents bias network, and base resistance of transistors, the load impedance, including the effects of the output matching network (OMN), output capacitance, and conductance of tranrepresents the emitter impedance, including the sistors, and bond-wire inductance and ballasting resistance. and are the main sources of nonIn our analysis, linearity, and the remaining elements are assumed linear. Our simulations show that this is an adequate model to predict the nonlinearities in our PA. Note that the nonlinear elements depend on both the quiescent bias point and RF signal power. Therefore, their values have to be determined under large-signal conditions. , the stored charge in the base can be expressed as For

Fig. 3. Simulated nonlinearity coefficients: (a) C and K K versus output power. I = 110 mA.

and (b) g

and

where and can be determined from the excursion of the base–emitter voltage together with the quiescent bias condition. The effects of capacitances and collector voltage variation are removed in calculating these coefficients. and The resulting nonlinearity coefficients are plotted in Fig. 3 for output power ranging from 0 to 26 dBm. As shown in Fig. 4, at even-order harmonic frequencies (including and ) is achieved through use of a quarter-wave stub. With this additional simplification, the nonlinear transfer function can be derived using the method of nonlinear currents described in [14] and [15] by combining (1) and and (2). With the assumption, the third-order intermodulation ratio can be expressed as

(1) The RF input signal determines the excursion range of the base–emitter voltage and this, together with the quiescent bias and . condition, determines the coefficients and base reThe effects of the base–collector capacitance sistance are removed in calculating these coefficients. Similarly, the nonlinear collector current can be expressed as (2)

(3) where and are the matching network voltage gains from the source to the base–emitter at frequencies and , respectively. Detailed derivations of the expresand are described in the sions for Appendix.

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Fig. 4. Schematic of circuit used for experimental verification of linearity analysis.

Fig. 5. IMR comparison between SPECTRE simulation, Volterra calculation, and measurement for the circuit of Fig. 4.

B. Experimental Verification of Analysis The single-stage PA shown in Fig. 4 was fabricated in a 0.25- m SiGe BiCMOS process.1 The main bipolar transistors in the PA are composed of 100 devices, each with an emitter area of 48 m 0.44 m. The devices were packaged in the Amkor micro-lead-frame (MLF) package. The chip was mounted on a Rogers20 printed circuit board (PCB). The quiescent bias current at the collector is 110 mA. obtained from experimental measureA comparison of ments with our Volterra expression in (3) shows good agreement throughout the entire range of output powers from 0 to 26 dBm between (Fig. 5). In addition, the excellent agreement of SPECTRE simulations and our Volterra expression validates the completeness of our model shown in Fig. 2 and the corresponding extraction methodology described in Section II-A. , but also Our analysis not only accurately predicts the provides insight into the individual contributions from the main nonlinear sources. Fig. 6 displays the calculated amplitude and in the following three cases. phase of Case 1) With the effect of the nonlinearity of only . 1IBM 6HP BiCMOS Process. [Online]. Available: 3.ibm.com/chips/techlib/techlib.nsf/products/BiCMOS_6HP

http://www-

Fig. 6. Individual contributions to amplitude and phase of output IMR . Note that the jump in the phase of output IMR comes from the fact that, at low input powers, the nonlinearity of i dominates the phase of output IMR , whereas at high input powers, the C nonlinearity dominates the phase of output IMR : (a) amplitude of IMR and (b) phase of IMR

Case 2) With the effect of the nonlinearity of only . and Case 3) With the effects of the nonlinearities of together. We observed that the nonlinearity of and nonlinearity of are quite large over the whole power range, but they are opposite in phase, resulting in the well-known intermodulation cancellation effect [16]. At low input powers, the nonlinearity of

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Fig. 7. IMR with different values of L

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;I

= 110 mA.

Fig. 9.

Simulated PAEs at 26-dBm output power with different values of L .

impedance )

, load impedance

, and bond-wire inductance

(4)

Fig. 8. Comparison of simulated and calculated power gains with different values of L .

dominates the magnitude and the phase of output . The nonlinearity dominates at high input powers so that the output is determined by the nonlinearity. The overall linearity of the SiGe HBT PA depends on the degree to which this cancellation is achieved [17]. Furthermore, the linearity is also limited due to considerations of power gain and efficiency. C. Effect of Emitter Bond-Wire Inductance The effect of bond wires connected to the emitter of the PA is critical in the design of the PA. Without considering its effect, the power gain and linearity cannot be accurately predicted. Therefore, it is necessary to include its effect in our linearity analysis. Expression (3) was compared to SPECTRE simulations for different values of the bond-wire inductance, as shown in Fig. 7. From this figure, we observed that the linearity of the PA is improved with the increase of the bond-wire inductance . Obviously, it may not be possible to pursue the best linearity by continuously increasing the value of due to the reductions in gain and PAE. The effect of on power gain is demonstrated in Fig. 8, where three different values of are compared. Calculation results are based on (4), which is the complete expression for power gain of the amplifier (including the effects of source

where the base resistance is included in , in which is the unity current gain radian frequency, is the total capacitance between the base and emitter, and is the base–collector capacitance. All circuit parameters used in (4) are extracted at the corresponding bias point from SPECTRE simulation. Note that the power gain is very sensitive to the effect of . The effect of on PAE is illustrated in Fig. 9, where PAEs at 26-dBm output power are compared with different values of . The effect of emitter inductance on PAE is not as significant as its effect on power gain, but we can still observe that, with an increase of , the power gain decreases and, thus, so does the PAE. This can be seen from the following definition of PAE [18]: (5) For WCDMA PAs, it is always desirable to have the power gain and PAE as high as possible, while satisfying the linearity requirement. For our PA, we found that 80 pH is the optimum value for bond-wire inductance , considering the tradeoff between gain, linearity, and efficiency. III. EFFICIENCY ENHANCEMENT TECHNIQUE A. Average Power Efficiency The average power efficiency is a measure of the ratio of the total energy transmitted to the total energy drawn from the battery [9], i.e., (6)

where is the output power, , and a certain output power

is the probability of is the PAE at .

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Fig. 10. Bipolar junction transistor (BJT) current versus voltage, demonstrating different dynamic biasing strategies (DCB/DVB). Fig. 12. Simulated HBT cutoff frequency versus collector current with differing device sizes (single device: 25 m ; m represents the number of devices in parallel).

Fig. 11. Output stage transistors with DCB. HBTs are biased “on” or “off” in response to output power requirements.

The average output power of a CDMA handset is well below the peak output power, where efficiency is a maximum, so it is very desirable to improve the PAEs of the amplifier at lower output powers. For class-A PAs, the average power efficiency (over representative CDMA conditions) is roughly 1.3% [19]. Therefore, improving average power efficiency is one of the key objectives for future PAs. B. DCB The typical approaches for reducing dc power consumption at lower output powers are reducing either dc-bias current through DCB or dc bias voltage (DVB) or both, as shown in Fig. 10. Power amplifiers with DCB have been proposed [10], [11], but their power gain changes by more than 8 dB with the change in dc-bias current. With the decrease of input power, the current swing at the output also becomes smaller and the total bias current can be reduced. However, the current density of each transistor drops, resulting in a reduction of power gain for the whole , the power gain of the PA can be simplified as PA. With (7) From (7), it is clear that, in order to maintain a constant power gain, we need to operate the transistor at a constant . Therefore, the transistor should operate at a constant current density. To lower the collector current and keep the power gain roughly constant, we utilize low-loss MOS switches at the bases of the transistors and dynamically bias the SiGe HBTs either fully “on” or fully “off” [20], as depicted in Fig. 11.

Fig. 13. Equivalent input circuit including NFET switches. For 100 parallel = 0:3 , C = 3:26 pF, R = 1 , and C = 204 pF. devices, R

The number of “on” transistors is adjusted in response to changes in the desired output power; the collector current density is increased slightly at the low-power region so as to keep the power gain constant. As shown in Fig. 12, the PA is operated in the low power at a slightly higher transition frequency . Operating the tranmode than in the higher power mode enables us to keep the gain relatively sistor at this higher constant by overcoming the effects of the extra parasitics in the low power mode. C. Design Considerations Ideally, for each output power, the dc-bias current could be adjusted to achieve maximum power efficiency. However, it is simpler to vary the current in discrete finite steps. Simulation results show that a single step variation in dc bias provides the best tradeoff of average power efficiency and circuit complexity. In our case, the high-power mode consisted of 100 parallel devices, and the low-power mode consisted of 20 devices. Each device consists of a bipolar transistor with an emitter area 48 m 0.44 m. The simplified equivalent input circuit is shown in Fig. 13. There are two sources of power loss due to the n-type field-effect Gain transistor (NFET) switches—resistance loss and capacitance loss Gain . The gain loss can be expressed as Gain

Gain

Gain

(8a) (8b)

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Fig. 16.

DCB SiGe HBT PA.

Fig. 14. Effects of gate finger on gain and 1-dB compression. Each finger is 15 m 0.25 m finger and the HBT is 48 m 0.44 m.

2

2

Fig. 15. PA schematic. An op-amp-based dc-bias circuit provides a low impedance at the baseband frequency.

Based on calculation using parameters extracted from simuis insigniflation (in Fig. 13), capacitance loss Gain . icant compared to resistance loss Gain The effects of the NFET switch size on both the power gain and 1-dB compression point of the PA were simulated. The results are shown in Fig. 14. Based on the simulation results that match the expression in (8b), an optimum MOS switch size of 3 finger 15 m 0.26 m was chosen. The corresponding gain loss at 1.95 GHz was 2.5 dB. The bias network consists of a helper and a low-impedance buffer, as shown in Fig. 15. This topology provides a CV biasing to the base of the PA and also terminates the sub-harmonic frequency at the input to improve the overall linearity [21]. In order to effectively terminate the sub-harmonic component, the buffer needs to satisfy certain bandwidth requirement. For WCDMA handset PAs, the channel bandwidth is 3.84 MHz, thus, the minimum bandwidth of the bias network has to be for larger than 3.84 MHz. Simulations show MHz. The even-order harmonics are terminated by using a quarter-wave stub connected to the base of transistors on the testing PCB board, which, for simplicity, is not shown in Fig. 15. IV. EXPERIMENTAL RESULTS AND DISCUSSIONS For WCDMA PAs, a two-stage topology is normally needed. In this study, we focus on the output stage, which is the key bottleneck in designing high-efficiency PAs. The first stage can be designed in a straightforward way. The single-stage PA with DCB for WCDMA handset applications was fabricated in the 0.25- m SiGe BiCMOS process used for the circuit of Fig. 4. The chip size, including the bias network, is 0.9 mm 1.2 mm. The die photograph is shown in

Fig. 17. Output power probability distribution P and measured dc current for different biasing techniques. The switch point from 100 devices to 20 devices = 18 dBm. V = 3 V. occurs at P

Fig. 18. Measured PAEs with CV with fixed area (CV) and DCB with varied area (DCB) PAs.

Fig. 16. The devices were tested in MLF (MLF12) packages. The OMN is implemented off-chip to achieve high for optimum PAE. Fig. 17 compares the measured dc currents for different biasing approaches for a single-stage WCDMA PA, superimposed on a typical probability distribution function for the output power [19]. These approaches include constant base voltage (CV) biasing with a fixed number of parallel transistors and DCB with a fixed base voltage. Using (6), average power efficiencies are calculated as 2.5% for CV biasing and 8.0% for DCB—a substantial improvement with the new approach. Fig. 18 shows measured PAEs with DCB and CV approaches. The peak PAE is not as high as other III–V WCDMA amplifiers reported [22], but the average power efficiency is improved. Table II is a summary of average power efficiencies for different reported dynamic biasing techniques, including this study.

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TABLE II AVERAGE POWER-EFFICIENCY COMPARISON OF REPORTED DYNAMIC BIASING TECHNIQUES

V. CONCLUSION

Fig. 19. Measured power gains with CV with constant area (CV), DCB with varied HBT area, and DCB with fixed HBT area PAs.

This paper has used a power-dependent coefficient Volterra technique to analyze the linearity of SiGe HBT PAs. The analyzed model has taken into account the effect of emitter bondbetween analysis, wire inductance. The comparison of simulation, and measurement data has validated this approach. The main sources of nonlinearity in SiGe HBT PAs have been highlighted. The authors have also developed a DCB technique to improve the average power efficiency for PAs. A prototype chip with a DCB for WCDMA applications has been fabricated and measured. The measured 1-dB compression point is 25.9 dBm, and the peak PAE is 31%. The average power efficiency has been improved from 2.5% to 8.0% by more than a factor of two using the DCB technique, while the power gain has been kept almost constant. The PA has also satisfied the ACPR specification for linearity. APPENDIX Here, we derive (3) in detail using the method of nonlinear currents described in [14] and [15]. The fundamental responses of the collector voltage and base–emitter voltage are found to be (9a) (9b)

Fig. 20.

Measured ACPRs of DCB SiGe HBT PA.

(10a) Fig. 19 compares the measured gain variation between a DCB with a varied HBT area, a DCB with a fixed HBT area, and CV with a fixed HBT area. The gain change for a DCB with a varied HBT area is less than 2 dB, and is much more constant than a DCB with a fixed HBT area [10], [11]. The linearity of the DCB amplifier is measured under adjacent channel power ratio (ACPR) testing with a WCDMA signal. The corresponding simulated ACPR curve is not compared here because the simulation of the ACPR in the Cadence design environment is very time consuming and the ACPR may [25], [26]. As shown in Fig. 20, be easily derived from the circuit satisfies the 3GPP class-3 WCDMA ACPR specification with 23.9-dBm channel output power.

(10b) where

(11) in which

and

are evaluated at the frequency

.

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Substituting the expressions of the nonlinear currents (13b) and (14b) into (15) yields the final intermodulation product

(16) Fig. 21. Equivalent circuit for the computation of the third-order !. intermodulation product 2!

0

The response of the base–emitter voltage at

The ratio of the third-order intermodulation product and the fundamental at the collector is then found to be

is given by

(12a) (12b) and are evaluated at the frequency . in which Since at even-order harmonic frequencies (including and ), there is no need to compute the second-order responses. Now we can calculate the third-order intermodulation product . The equivalent circuit for its computation is shown at in Fig. 21. From [15], we find

(13a) (13b)

(17) Since the OMN is a linear passive network, (17) is also valid for the ratio of the third-order intermodulation product and the fundamental at the output load. ACKNOWLEDGMENT The authors would like to acknowledge useful discussions with Dr. C. Wang, Dr. L. Sheng, Dr. M. Vaidyanathan, Dr. V. Leung, D. Kimball, H. Ng, and A. Yang, all of the University of California at San Diego, La Jolla. REFERENCES

(14a) (14b) By applying Kirchoff’s law in the circuit of Fig. 21, we find that

(15) in which and are evaluated at the frequency . and and Since evaluated at the frequency are approximately equal to and evaluated at the frequency , respectively. . Then

[1] J. Pusl, S. Sridharan, P. Antognetti, D. Helms, A. Nigam, J. Griffiths, K. Louie, and M. Doherty, “SiGe power amplifier IC’s with SWR protection for handset applications,” Microwave J., Jun. 2001. [Online]. Available: http://www.mwjournal.com. [2] P.-D. Tseng, L. Zhang, G.-B. Gao, and M. F. Chang, “A 3-V monolithic SiGe HBT power amplifier for dual-mode (CDMA/AMPS) cellular handset applications,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1338–1344, Sep. 2000. [3] J. B. Johnson, A. J. Joseph, D. Sheridan, and R. M. Malladi, “SiGe BiCMOS technologies for power amplifier applications,” in IEEE Gallium Arsenide Integrated Circuit Symp., 2003, pp. 179–182. [4] UE Radio Transmission and Reception, 3GPP Standard 25.101 (V5.3.0), 2002. [5] J. Vuolevi and T. Rahkonen, “Analysis of third-order intermodulation distortion in common-emitter BJT and HBT amplifiers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 12, pp. 994–1001, Dec. 2003. [6] R. A. Minasian, “Intermodulation distortion analysis of MESFET amplifiers using the Volterra series representation,” IEEE Trans. Microw. Theory Tech., vol. MTT-28, no. 1, pp. 1–8, Jan. 1980. [7] A. E. Parker and G. Qu, “Intermodulation nulling in HEMT common source amplifiers,” IEEE Microw. Wireless Compon. Lett., vol. 11, no. 3, pp. 109–111, Mar. 2001. [8] C. Wang, M. Vaidyanathan, and L. E. Larson, “A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers,” IEEE J. Solid-State Circuits, to be published. [9] J. F. Sevic, “Statistical characterization of RF power amplifier efficiency for CDMA wireless communication systems,” in Wireless Commun. Conf., 1997, pp. 110–113. [10] D. Dening, “Setting bias points for linear RF amplifiers,” Microwaves RF, Jun. 2002. [Online]. Available: http://www.mwrf.com.

DENG et al.: HIGH AVERAGE -EFFICIENCY SiGe HBT PA

[11] T. Fowler, K. Burger, N. S. Cheng, A. Samelis, E. Enobakhare, and S. Rohlfing, “Efficiency improvement techniques at low power levels for linear CDMA and WCDMA power amplifiers,” in IEEE Radio Frequency Integrated Circuits Symp., 2002, pp. 41–44. [12] G. Hanington, P. Chen, P. M. Asbeck, and L. E. Larson, “High-efficiency power amplifier using dynamic power-supply voltage for CDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 47, pp. 1471–1476, Aug. 1999. [13] J. Deng, P. Gudem, L. E. Larson, and P. M. Asbeck, “A high-efficiency SiGe BiCMOS WCDMA power amplifier with dynamic current biasing for improved average efficiency,” in IEEE Radio Frequency Integrated Circuits Symp., 2004, pp. 361–364. [14] S. A. Maas, Nonlinear Microwave Circuits. Norwood, MA: Artech House, 1988, pp. 190–207. [15] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Norwell, MA: Kluwer, 1998, pp. 137–156. [16] S. A. Maas, B. L. Nelson, and D. L. Tait, “Intermodulation in heterojunction bipolar transistors,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 3, pp. 442–448, Mar. 1992. [17] M. Vaidyanathan, M. Iwamoto, L. E. Larson, P. S. Gudem, and P. M. Asbeck, “A theory of high-frequency distortion in bipolar transistors,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 2, pp. 448–461, Feb. 2003. [18] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Norwood, MA, 1999, pp. 53–54. [19] P. Asbeck, private communication, Apr. 2003. [20] M. Rofougaran, A. Rofougaran, C. Olgaard, and A. A. Abidi, “A 900 MHz RF power amplifier with programmable output,” in VLSI Circuits Symp., 1994, pp. 193–194. [21] V. Aparin and C. Persico, “Effect of out-of-band terminations on intermodulation distortion in common-emitter circuits,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, 1999, pp. 977–980. [22] Y. Bito, T. Kato, and N. Iwata, “High efficiency power amplifier module with novel enhancement-mode heterojunction FET’s for wide-band CDMA handsets,” in Gallium Arsenide Integrated Circuit Symp., 2000, pp. 255–258. [23] J. Staudinger, B. Gilsdorf, D. Newman, G. Norris, G. Sadowniczak, R. Sherman, and T. Quach, “High efficiency CDMA RF power amplifier using dynamic envelope tracking technique,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 2, 2000, pp. 873–876. [24] B. Sahu and G. A. Rincon-Mora, “A high-efficiency linear RF power amplifier with a power-tracking dynamically adaptive buck-boost supply,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 1, pp. 112–120, Jan. 2004. [25] J. C. Pedro and N. Carvalho, “On the use of multi-tone techniques for assessing RF components’ intermodulation distortion,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 12, pp. 2393–2402, Dec. 1999. [26] N. B. de Carvalho and J. C. Pedro, “Compact formulas to relate ACPR and NPR to two-tone IMR and IP3,” Microwave J., Dec. 1999. [Online]. Available: http://www.mwjournal.com.

Junxiong Deng (S’02) received the B.S. degree in electrical engineering from Southeast University, Nanjing, China, in 1997, the M.S. degree in electrical engineering from the University of California at San Diego (UCSD), La Jolla, in 2002, and is currently working toward the Ph.D. degree at UCSD. His research concerns high-efficiency and highlinearity PAs for advanced wireless communication systems.

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Prasad S. Gudem (M’96) received the Ph.D. degree in electrical and computer engineering from the University of Waterloo, Waterloo, ON, Canada, in 1996. His doctoral research concerned the modeling and numerical simulation of amorphous silicon devices. After a brief time with Mitel Semiconductors, Kanata, ON, Canada, he joined Cadence Design Systems, San Diego, CA, where he was involved with semiconductor-device modeling for analog and RF applications. In August 2000, he joined the Watson Research Center, IBM, where he was involved with RF integrated-circuit design for WCDMA applications using IBM’s SiGe technology. He was also a Lecturer with the University of California at San Diego, La Jolla, where he taught a three-quarter course on communication circuit design. He recently joined Qualcomm Inc., San Diego, CA, where he continues to work on RF circuit design for wireless applications.

Lawrence E. Larson (S’82–M’86–SM’90–F’00) received the B.S. and M.Eng. degrees in electrical engineering from Cornell University, Ithaca, NY, in 1979 and 1980, respectively, and the Ph.D. degree in electrical engineering from the University of California at Los Angeles (UCLA), in 1986. From 1980 to 1996, he was with Hughes Research Laboratories, Malibu, CA, where he directed the development of high-frequency microelectronics in GaAs, InP, Si/SiGe, and microelectromechanical systems (MEMS) technologies. In 1996, he joined the faculty of the University of California at San Diego (UCSD), La Jolla, where he is currently the Inaugural Holder of the Communications Industry Chair. He is currently Director of the UCSD Center for Wireless Communications. During the 2000–2001 academic year, he was on leave with IBM Research, San Diego, CA, where he directed the development of RF integrated circuits (RFICs) for 3G applications. He has authored or coauthored over 200 papers. He holds 27 U.S. patents. Dr. Larson was the recipient of the 1995 Hughes Electronics Sector Patent Award for his research on RF MEMS technology. He was corecipient of the 1996 Lawrence A. Hyland Patent Award of Hughes Electronics for his research on low-noise millimeter-wave high electron-mobility transistors (HEMTs), and the 1999 IBM Microelectronics Excellence Award for his research in Si/SiGe HBT technology.

Peter M. Asbeck (M’75–SM’97–F’00) received the B.S. and Ph.D. degrees from the Massachusetts Institute of Technology (MIT), Cambridge, in 1969 and 1975, respectively. He is currently the Skyworks Chair Professor with the Department of Electrical and Computer Engineering, University of California at San Diego (UCSD), La Jolla. He was with the Sarnoff Research Center, Princeton, NJ, and the Philips Laboratory, Briarcliff Manor, NY, where he was involved in the areas of quantum electronics and GaAlAs/GaAs laser physics and applications. In 1978, he joined the Rockwell International Science Center, where he was involved in the development of high-speed devices and circuits using III–V compounds and heterojunctions. He pioneered the effort to develop HBTs based on GaAlAs/GaAs and InAlAs/InGaAs materials and has contributed widely in the areas of physics, fabrication, and applications of these devices. In 1991, he joined UCSD. He has authored or coauthored over 250 publications. His research interests are in development of high-speed HBTs and their circuit applications. Dr. Asbeck is a Distinguished Lecturer for the IEEE Electron Devices Society and the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He was the recipient of the 2003 IEEE David Sarnoff Award for his work on HBTs.

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Image-Rejection CMOS Low-Noise Amplifier Design Optimization Techniques Trung-Kien Nguyen, Student Member, IEEE, Nam-Jin Oh, Student Member, IEEE, Choong-Yul Cha, Yong-Hun Oh, Student Member, IEEE, Gook-Ju Ihm, and Sang-Gug Lee, Member, IEEE

Abstract—This paper reviews and analyzes two reported image-rejection (IR) low-noise amplifier (LNA) design techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18- m CMOS technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, lower than 1.5-dB noise figure, 5-dBm input-referred third-order intercept point and an IR of 26 dB. Index Terms—CMOS, image-rejection (IR) technique, low-noise amplifier (LNA), noise optimization, RF, wireless local area network (WLAN).

I. INTRODUCTION

G

ENERALLY, superheterodyne architecture is the most widely used for stage-of-the-art receivers in modern handsets since it is capable of providing high and stable performance in mobile communications [1]–[3]. In the superheterodyne receivers, proper filtering of image signals is mandatory, and this filtering is done by external passive components such as surface-acoustic wave (SAW) filters. These external filters are large and expensive, but unavoidable in superheterodyne architectures. Consequently, they are the major impediment to increase the level of integration of wireless radio since they cannot be easily implemented monolithically. To overcome the problems from those external filters, imagerejection (IR) mixers using phase cancellation are developed [4]–[8]. However, due to the gain and phase mismatches, IR ratios for 5-GHz-band receivers generally lie within the range

Manuscript received April 21, 2004. T.-K. Nguyen, N.-J. Oh, Y.-H. Oh, and S.-G. Lee are with the RF Microelectronics Laboratory, Information and Communications University, Daejeon 305-714, Korea. C.-Y. Cha was with Gaintech, Daejeon 305-343, Korea. He is now with the Samsung Advance Institute of Technology, Suwon 305-751, Korea. G.-J. Ihm was with the Information and Communications University, Daejeon 305-714, Korea. Digital Object Identifier 10.1109/TMTT.2004.840744

Fig. 1.

Typical superheterodyne receiver.

of 25–35 dB [3]. Therefore, an extra 50-dB IR should be provided to meet the specification of a superheterodyne receiver, which typically requires 80 dB of IR. To address this need, some of the recent research has focused on the development of monolithic IR using a notch filter [9]–[14]. In this technique, a notch located at the image frequency is used to reject image signals rather than bandpass filtering. By combining an on-chip IR filter with an integrated image reject mixer, 79 dB of on-chip IR could be obtained [14]. In this paper, two previously reported IR low-noise amplifier (LNA) design techniques are reviewed and analyzed. The analyses and discussions are based on the quality factor and the ability to control frequencies at both image and wanted signals. As a solution to overcome the limitations of two previously reported works, this paper proposes a new notch-filter topology—the third-order active notch filter. In other words, the proposed topology can not only control both the image signal and wanted signal, but can also obtain a high-quality factor regarding the low-quality factor of an on-chip inductor. In addition, this paper shows the guideline as to how to design an LNA that achieves power-constrained simultaneous noise and input matching, as well as satisfies the linearization condition. By combining a low-noise high-gain LNA designed by the proposed optimization technique with the proposed notch filter, an IR LNA, shown in Fig. 1, is implemented. The proposed IR LNA is optimized for superheterodyne applications having 5.25 GHz with IF frequency of 500 MHz. The measurement results show the power gain of 20.5 dB, lower than 1.5-dB noise figure (NF), and an IR of 26 dB. Measured two-tone test results show 5 and 8 dBm of the input-referred third-order intercept point (IIP3) in the cases of using and not using the notch filter, respectively. The circuits dissipate a dc current of 4 mA under a supply voltage of 3 V. Section II summarizes the reported analysis details of two reported IR design techniques

0018-9480/$20.00 © 2005 IEEE

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Fig. 3. (a) Schematic of the IR LNA with the third-order passive notch filter. (b) The filter’s equivalent circuit including the series resistance of the on-chip inductor only.

fore, the quality factor of the on-chip integrated inductor plays a minor role in the quality factor of the filter, which is given by

(2)

Fig. 2. (a) Schematic of the IR LNA with second-order active notch filter. (b) The filter’s small-signal equivalent circuit only.

where represents the total resistance. The frequency of resonance for the filter can be derived as (3)

along with the proposed filter topology. Sections III and IV describe the design and measurement details of the proposed IR LNA. Section IV concludes this study.

II. IR DESIGN TECHNIQUES A. Second-Order Active Notch-Filter Technique The on-chip IR LNA with the second-order active filter was first introduced in [9]. This active notch filter is based on a series resonator, whose resonant frequency is tuned to the image frequency. Fig. 2(a) shows the cascode LNA with the second-order active filter is attached, and Fig. 2(b) shows only the smallsignal equivalent circuit of the filter. is From Fig. 2(b), the impedance looking into the gate of given by

At this frequency, is minimum, with the value depending on the quality factor of the filter. However, this notch filer can work negatively to the wanted signal. That means, at the wanted frequency, the input impedance of the second-order active notch filter might be lower than the case without the filter. Therefore, it is possible that there is some amount of wanted signal that can be lost to the ground. Consequently, the power gain of the amplifier can be degraded, while the NF can be increased due to the signal loss to the ground. B. Third-Order Passive Notch-Filter Technique The cascode LNA with the third-order passive notch filter noted in Fig. 3(a) is introduced in [10] as the solution to control both the image and wanted signal. From Fig. 3(a), the input impedance of the filter is given by (4)

(1) where is the gate–source capacitor transconductance, is the series gate resistance of , and is the series resistance of on-chip inductor . Note that the negative term on the right-hand side of (1) rep) seen at the resents the negative resistance (proportional to . Thus, by adjusting , i.e., the bias gate of transistor current , sufficient negative resistance can be generated to and . This results in a dramatic increase in cancel out the quality factor of the filter to very high values [9]. There-

The image and wanted signals are located at (5) (6) The filter can provide low impedance at the image frequency and high impedance at the wanted frequency. This filter is designed not only to reject the image signal, but also to remove

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Fig. 4.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Filter characteristic for various

Q factor values of an on-chip inductor.

the effect of the parasitic capacitance in the signal path of cascode amplifier. Thus, by providing high and low impedance at the wanted and image signals, the filter archives IR and good noise performance at the same time. However, the major drawback of this filer comes from the quality of the on-chip inductor that affects the overall quality factor of the filter. In typical CMOS technology, the quality factor of the on-chip inductor is dominated by the series resistance. By neglecting all the parasitic components, except the series resistance of the on-chip inductor, the equivalent circuit of only the filter can now is the series be represented as shown in Fig. 3(b), where resistance of . Also assume that only the quality factor of the filter at the image frequency is of most interest at this moment; the quality factor of filter is given by

(7) As can be seen in (7), the quality factor of the filter is limited by the parasitic series resistance of . Since, in CMOS technology, the on-chip inductor tends to have high resistance, so does the quality factor of the filter. Fig. 4 shows the filter characteristic as a function of frequency with various values of the inductor’s quality. In this simulation, the on-chip inductor is modeled as introduced in [15]. From Fig. 4, it can be seen that the filter characteristics significantly depends on the quality factor of the on-chip inductor. Therefore, in order to design a filter with a high quality factor, an off-chip inductor is needed. However, using an off-chip inductor will violate the idea of an on-chip integrated IR filter.

Fig. 5. (a) Schematic of cascode IR LNA with the proposed third-order active notch filter. (b) The filter’s small-signal equivalent circuit only.

where

(9) and . Note that the negative term in the right-hand side of (9) rep) seen at the resents the negative resistance (proportional to . Like the first filter topology shown in gate of transistor by varying the bias current , sufFig. 2(a), by adjusting ficient negative resistance can be generated to cancel and . Therefore, the quality factor of this filter is almost unaffected by the quality factor of an on-chip inductor. Assuming that all the parasitic components are cancelled, the input impedance of the filter is now re-expressed as (10) where (11)

C. Proposed Third-Order Active Notch Filter To overcome the limitations of [9] and [10], in this paper, a third-order active notch filter is introduced, as shown in Fig. 5(a). As can be seen from the small-signal equivalent of the circuit shown in Fig. 5(b), the input impedance proposed active filter can be expressed as (8)

From (11), the image and wanted signals are located at (12) (13)

NGUYEN et al.: IR CMOS LNA DESIGN OPTIMIZATION TECHNIQUES

Fig. 6.

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Filter characteristic of the proposed notch filter.

At the image frequency, the impedance looking into the filter can be reduced to zero such that the entire image signal will be extracted from the original path, whereas at the wanted is maxfrequency, the input impedance of the proposed filter imized. Therefore, the loss of the wanted signal can be avoided. The ability of IR depends on the difference of impedance between the filter and the original LNA at the image frequency. The larger the difference is, the higher the IR can be obtained. To increase this difference, a feedback connection from the drain of the transistor to the input of the inductor has been added [9], as denoted by the dark line in Fig. 5(a). Now, the input impedance such that the will be decreased by the factor of impedance difference becomes less dependent on the negative term in (9). This means that with a relatively low filter implemented in the signal path of a typical cascode LNA it is possible to realize a very deep notch with a very high provided that the bandpass filter has a large impedance difference. Fig. 6 shows the filter characteristic as a function of frequency. This design is optimized for a 5.25-GHz wireless local area network (WLAN) and a local oscillator (LO) of 4.75 GHz for 500-MHz IF wireless receivers. Hence, the image signal is located at 4.25 GHz. As can be seen from Fig. 6, the impedance at 4.25 GHz is very low, while the impedance at the wanted signal has a peak value. However, the impedance at the image signal has a narrow valley; therefore, for the correct image cancellation, the zero must occur at the correct frequency. On the other hand, the peak is a wider valley and the exact location of the pole is less important. III. IR-LNA DESIGN In this design, the proposed IR LNA is implemented by applying a two-stage current reuse LNA [16] with the proposed third-order active notch filter shown in Fig. 5. A complete schematic of the IR LNA is shown in Fig. 7. The first stage is a common source inductive degeneration topology. In this is used together with and stage, an extra capacitor so as to obtain power-constrained simultaneous noise and input matching [17], [18]. The second stage uses a cascode and . configuration, which consists of the transistors is the ac-coupling capacitor and is the bypass capacitor. In

Fig. 7. Schematic of the proposed IR LNA.

Fig. 8. Small-signal equivalent circuit of the input stage of the IR LNA in Fig. 7 for noise analysis.

this design, an inter-stages inductor is included to resonate with an input capacitor of the second stage (approximately ) to improve the gain equal to the gate–source capacitor of network is used to and NF of the amplifier. A simple match the output of the LNA. A. Input Stage Noise Optimization Typically, the noise performance of an LNA is dominated to the input stage. Thereby, in order to simplify the analysis, in this study, only the input stage noise analysis is considered. From this assumption, the simplified small-signal input-stage’s equivalent circuit of the proposed LNA, shown in Fig. 7, is predicted as Fig. 8 for the noise analysis. In Fig. 8, the effects of the parasitic resistances of the gate, body, source, drain terminals, and on the noise and frequency the gate–drain capacitance of response are also assumed to be neglected. Readers may refer to [17] and [18] for further detail of noise analysis. However, in this study, in order to have an overall perspective understanding of the design methodology for the noise and linearity optimization technique, some of the noise parameter expressions called the noise factor, minimum NF,

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optimum noise impedance, and noise resistance are rewritten as (14)–(17), shown at the bottom of this page, where

From Fig. 8, the input impedance of the LNA is given by (18) The condition that allows the simultaneous noise and input matching is now (19) From (16) and (18), (19) can be satisfied when the following conditions are met:

As can be seen in (18), the source degeneration generates a real part at the input impedance. This is important because there is no real component in the input impedance without degeneration, while there is one in the optimum noise impedance. Therehelps to reduce the discrepancy between the real parts fore, of the optimum noise impedance and the LNA input impedance. is changed Furthermore, from (18), the imaginary part of by , and this is followed by nearly the same change in in (16), especially with advanced technology, as discussed in [18]. Therefore, (23) can be dropped, which means that, for a given value of , the imaginary value of the optimum noise impedance becomes approximately equal to that of the input impedance with opposite sign. Now, the design parameters that (or ), , and . Since satisfy (20)–(22) are there are three equations and four unknowns, (20)–(22) can be by fixing the value of one of solved for an arbitrary value of the design parameters, which is possibly the power dissipation . In other words, this LNA design optimization technique or allows designing simultaneous noise and input matching at any given amount of power dissipation. B. Linearity Analysis

(20)

In RF circuit design, the linearity is another important parameter that needs to be considered. Since the LNA is the first block in the typical receiver system, the linearity of the LNA is commonly estimated by the third-order intermodulation and (IM3) product. Two signals of adjacent channels will generate products IM3 such as and at the output of the nonlinear circuit. Normally, IM3 is calculated as the ratio of the IM3 and response magnitude of the fundamental frequency, which is given by [2]

(21) (24) (22)

(23)

and are the first- and third-order coefficient of where Volterra series. As mentioned above, the proposed IR LNA consists of two amplifier stages. According to [2], the linearity of the second

(14)

(15)

(16)

(17)

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Fig. 9.

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Circuit model for linearity analysis.

stage plays an important role and it cannot be neglected when the linearity is considered. Thereby, for the linearity analysis purpose, the equivalent small-signal circuit of the LNA in Fig. 7 can be predicted as Fig. 9, where the second stage is considered . Assume that, and modeled by the series transconductance and are neglected. In Fig. 9, in this case, the effects of and is added the output admittance seen at the drain of in the model with the purpose of identifying the output contribuat can be derived from tion. The magnitude of the Volterra-series analysis [18] as follows: (25) where (26) (27) (28)

(29) (30) (30) (31) Here, and are the second- and third-degree coefficients of the transistor nonlinear Taylor expansion. The coefficient is and the second-order interaction of the products . is the transconductance of the circuit. Substireversely depend on tuting (26) into (25), it shows that the term

compared to the resistive and capacitive degenimprove eration topology since such cancellation does not exist. As can be seen from (30) and (31), the effect of and coefficients in is inversely dependent on the bias , indicating that the linearity can be improved by increasing the gate–source voltage. However, increasing the gate–source voltage will inand values crease the power dissipation. With large value, (32) is increased such that linearity will and small be increased. For the same reason, with any increase in , preserving the simultaneous noise and input matching conditions is not used, the also improves the linearity. Note that if is. The higher , the higher the gate–source capacitance gate–source capacitance can be increased with an increase of the transistor size. However, at a given bias condition, increasing the transistor size results in the more current dissipation. Therefore, not only helps to archive matching conditions in both input impedance and noise at a given amount of power consumption, but also helps to improve the linearity. C. Input Stage Design Methodology Here, the overall consideration for the input stage of LNA design to obtain power-constrained simultaneous noise and input matching, as well as satisfy the linearization condition, is described. The qualitative description of the proposed design process would be as follows. , for example, the bias point • First, choose the dc bias . that provides minimum based on the power • Second, choose the transistor size . constraint , as well as • Third, choose the additional capacitance to satisfy (20), (22), and the degeneration inductance, conditions (as mentioned above, to improve the linearity of the LNA, the condition need to be satisfied). With the given , the condiis automatically satisfied. At this tion point, simultaneous noise and input matching is achieved. • As the final phase, if there exists any mismatch between and , as shown in Fig. 8, an impedance-matching circuit can be added. This design optimization technique suggest that, by using an , in principle, the LNA can be designed extra capacitor to achieve power-constrained simultaneous noise and input matching, as well as satisfy the linearization condition at a given amount of power consumption. However, the limitations and low effective cutoff frequency. High of this are high can be a serious limitation for the practical high-yield LNA design. D. Inter-Stage Series Resonant Technique

(32) As can be seen in (25), the linearity can be improved by using or with the indifferent ways such as the reduction of crease (30). From (27), with inductive degeneration, the term will cancel the “1” term and, as a result, is reduced. This indicates that the inductive degeneration topology helps to

Fig. 10(a) shows the small-signal equivalent circuit from the to that of of the LNA shown in Fig. 7. drain node of and represent parasitic impedance to In this figure, the ground through the silicon substrate and the load impedance and are the real part of the first stage, respectively. of the input impedance and equivalent input capacitance of the is much second stage seen from node , respectively. If

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Fig. 11. Fig. 10. Small-signal equivalent circuit of the IR LNA. (a) The small-signal equivalent circuit from node X to Y to evaluate the effect of the inter-stage series resonant technique and (b) to evaluate the effect of the quality factor of the inter-stage series on the performances of the IR LNA.

smaller than , then the series resonant network will provide low impedance at node . Under the series is approximately equal to , resonance, and assume that to that of can be given the current gain from the drain of by

Measured NF of a simple cascode LNA: with and without C .

where is the parasitic series resistance of . As can be seen can significantly depend on . The effect in (34) and (35), on the performances of the LNA can be summarized of as follows. First, the series resonant condition will provide low impedance at node such that the current gain from node to . Second, the voltage gain node does not depend on from the gate of to that of can be calculated based on the equivalent circuit shown in Fig. 10(b). From Fig. 10(b), the output current of the first stage can be given by (36) The voltage at the input of the second stage is (37)

(33) Therefore, the voltage gain where are, respectively, the currents of and and are the gate–source capacitor and transconductance of , respectively, represents the cutoff frequency of , and represents the operating frequency. Note that (33) is valid and the value of , as regardless of the size of transistor . In (33), with the given 0.18long as m CMOS technology, the proposed series resonant technique can provide a current gain of over ten. In addition, due to the small impedance presented at node , the proposed topology can avoid the signal loss through substrate. Besides, the low impedance at node also reduces voltage gain of the first stage is reduced. so that the Miller effect on In Fig. 10(a), the effect of the quality factor of the inter-stage series resonant network on the performances of the LNA is one of the important factors that needs to be considered. From can Fig. 10(a), the quality factor of the resonance network be calculated by (34) (35)

can be expressed as (38)

From (38), the voltage gain is independent of , thereby does not affect the voltage gain of the amplifier. Therefore, is implemented as on-chip. in this design, IV. MEASUREMENT RESULTS In this design, considering the power gain and linearity of circuit, the current dissipation is fixed to be 4 mA. To demonon the noise performance of the LNA, strate the effect of two simple cascode LNA versions are fabricated: one uses an extra capacitor, while the other does not. The measured NF results are shown in Fig. 11. As can be seen from Fig. 11, the one has a lower NF compared to that with without . with The improvement in the NF effect can be understood as the mismatch between and . To demonstrate the effect of the proposed notch filter on the performances of the LNA, two versions of the LNA are designed. Version 1 is an LNA without the proposed notch filter, and version 2 includes the proposed third-order notch filter. Fig. 12 shows the measurement results of the NF versus the

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Fig. 12. Measured NF of LNAs. Fig. 14.

Measured IIP3 of LNAs.

Fig. 15. Microphotograph of the LNAs. (a) Simple cascode without C , (b) with C , (c) current reused with the proposed filter, and (d) without the proposed filter. Fig. 13.

Measured power gain of LNAs.

frequency of the LNAs. As can be seen from Fig. 12, version 2 presents a high NF near the image frequency that can be understood as the signal loss through the notch filter. However, as the frequency approaches 5.25 GHz, the NF reduces below that of version 1. Fig. 13 shows the power gain of the two LNAs. From Fig. 13, by using the proposed filter, the IR LNA provides approximately 26 dB of overall IR. At 5.25 GHz, the power gain of the version 2 is higher than that for version 1. The improvements in NF and power gain at the operating frequency are 0.1 and 0.5 dB, respectively, which are explained and the parasitic capacitance as the resonant effect between at node [10]. From measured results, the values of of two LNAs, with and without a filter, are 18 dB 20 dB and 19 dB 20 dB, respectively. The measured IIP3 results of the LNAs are shown in Fig. 14. Two tones were applied with equal power levels at 5.25 and 5.255 GHz. The measured results indicate 5-dBm and 8-dBm IIP3 for the case of using and not using the notch filter. The effect of the linearity improvement is not clear at this point; however, this result is confirmed by measurement. The photographs of LNAs are shown in Fig. 15. The chip area of versions 1 and 2 are 0.4 and 0.5 mm, respectively. The measured performances of LNAs are summarized in Table I.

TABLE I SUMMARY OF THE MEASURED IR-LNA PERFORMANCES

V. CONCLUSION The rejection of image signals is the main problem in the superheterodyne architecture. To eliminate the use of an off-chip SAW filter, the on-chip IR techniques have been developed. Among them, the IR notch filter appears to be the proper solution for an on-chip integrated image receiver. This paper introduces the third-order active notch filter as the satisfactory factor. The proposed notch filter can control not only the wanted signal, but also the image one. It can also provide a high-value quality factor regardless of the quality factor of the on-chip inductor. In addition, the method to design an

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LNA satisfying the power-constrained simultaneous noise and input matching, as well as linearity optimization conditions is introduced. The IR LNA, implemented by integrating a high-gain LNA with the proposed third-order active notch filter, shows some improvement in the NF and power gain thanks to the resonant effect between the inductor used in the notch-filter topology and the parasitic capacitor at the signal path at the middle node of the cascode topology. In addition, this paper introduces the LNA design methodology, which obtains noise matching and power matching, as well as linearity optimization at a given amount of power consumption. Another advantage of using the proposed third-order notch filter is that the linearity of the LNA can be improved. Although this improvement is not clear to us at the moment, it has been confirmed by measured results. Measured results also show a power gain of 20.5 dB, an NF of lower than 1.5 dB, an IIP3 of 5 dBm, and an IR of 26 dB for the proposed IR LNA, which dissipates a dc current of 4 mA under a supply voltage of 3 V.

REFERENCES [1] B. Razavi, “Challenges in portable RF transceiver design,” IEEE Circuits Devices Mag., vol. 12, pp. 12–25, Dec. 1996. , RF Microelectronics: Prentice Hall, 1998. [2] [3] T. H. Lee, “5-GHz CMOS wireless LANs,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 268–280, Jan. 2002. [4] S. Wu et al., “A 900-MHz/1.8 GHz CMOS receiver for dual-band applications,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2178–2185, Dec. 1998. [5] S. Lee et al., “A 1 GHz image-rejection down-converter in 0.8 m CMOS technology,” IEEE Trans. Consum. Electron., vol. 44, no. 2, pp. 235–239, May 1998. [6] J. P. Maligeorgos et al., “A low-voltage 5.1–5.8 GHz image-rejection receiver with wide dynamic range,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1917–1926, Dec. 2000. [7] N. Kim et al., “An image rejection down conversion mixer architecture,” in TENCON 2000, pp. 287–289. [8] P. B. Khannur et al., “A 2.45 GHz fully differential CMOS image-reject mixer for Bluetooth applications,” in Radio Frequency Integrated Circuits Symp., 2002, pp. 415–418. [9] J. Macedo et al., “A 1.9 GHz silicon receiver with monolithic image reject filtering,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 378–386, Mar. 1996. [10] H. Samavati et al., “A 5-GHz CMOS wireless LNA receiver front-end,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765–772, May 2000. [11] Y. Chang et al., “An inductorless active notch filter for RF image rejection,” in 42nd Midwest Circuits Systems Symp., 2000, pp. 166–169. [12] C. Guo et al., “A monolithic 2-V 950-MHz CMOS bandpass amplifier with a notch filter for wireless receivers,” in IEEE Radio-Frequency Integrated Circuit Symp., 2001, pp. 79–82. [13] Y. Chang et al., “A monolithic RF image-reject filter,” in Southwest Mixed-Signal Design Symp., 2000, pp. 41–44. [14] C. Guo et al., “A full integrated 900 MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1084–1089, Aug. 2002. [15] S. S. Mohan et al., “Simple accurate expression for planar spiral inductances,” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1419–1424, Oct. 1999. [16] C. Y. Cha et al., “A 5.2 GHz LNA in 0.35 m CMOS utilizing interstage series resonance and optimizing the substrate resistance,” in Eur. Solid-Stage Circuit Int. Conf., Sep. 2002, pp. 339–342. [17] T.-K. Nguyen et al., “CMOS low noise amplifier design optimization techniques,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1433–1442, May 2004.

[18] T.-K. Nguyen et al., “A power-constrained simultaneous noise and input matching low noise amplifier design technique,” presented at the IEEE Circuits Systems Symp., Vancouver, BC, Canada, 2004. [19] E. Roa et al., “A methodology for CMOS low noise amplifier design,” in IEEE Integrated Circuit Systems Design Symp., 2003, pp. 14–19.

Trung-Kien Nguyen (S’04) was born in Hanoi, Vietnam, in 1977. He received the B.S. degree in radiophysics from the Hanoi National University, Hanoi, Vietnam, in 1999, the M.S. degree in electronics engineering from the Information and Communications University, Daejeon, Korea, in 2004, and is currently working toward the Ph.D. degree in RF microelectronics at the Information and Communications University. From 1999 to February 2001, he was with the Laboratory of Research and Development of Sensor, Institute of Material Science (IMS), Vietnamese Academy of Science and Technology (VAST). He is currently with the RF Microelectronics Laboratory, Information and Communications University.

Nam-Jin Oh (S’04) was born in Daejeon, Korea. He received the B.S. degree in physics from Hanyang University, Seoul, Korea, in 1992, the M.S. degree in electrical engineering from North Carolina State University, Raleigh, in 1999, and is currently working toward the Ph.D. degree in RF microelectronics at the Information and Communications University, Daejeon, Korea. From 1992 to 1997, he was with the LG Corporate Institute of Technology, Seoul, Korea. From 1999 to 2001, he was with Samsung Electronics, Suwon, Korea. He is currently with the RF Microelectronics Laboratory, Information and Communications University.

Choong-Yul Cha was born in Hapchun, Korea. He received the B.S. degree in electronics from Yeungnam University, Kyungpook, Korea, in 1995, and the M.S. and Ph.D. degrees in electronics engineering from the Information and Communication University, Daejeon, Korea, in 2002 and 2004, respectively. In 2003, he joined Gaintech, Daejeon, Korea, where he has been engaged in the development of fiver-optic transceiver integrated circuits for 155-Mb/s–10-Gb/s application and RF integrated circuits such as LNAs, mixers, and voltage-controlled oscillators (VCOs) for wireless communications. He is currently with the Samsung Advance Institute of Technology, Suwon, Korea.

Yong-Hun Oh (S’04) was born in Daejeon, Korea, in 1975. He received the B.Sc. degree in electrical engineering and computer science from Handong University, Pohang, Gyoung-buk, Korea, in 1999, the M.S. degree in electronics engineering from the Information and Communications University, Daejeon, Korea, in 2002, and is currently working toward the Ph.D. degree at the Information and Communications University.

NGUYEN et al.: IR CMOS LNA DESIGN OPTIMIZATION TECHNIQUES

Gook-Ju Ihm was born in Jeonnam, Korea, in 1974. He received the B.S. degree in electrical engineering from Hanyang University, Seoul, Korea, in 1998, and the M.S. degree in electronics engineering from the Information and Communications University, Daejeon, Korea, in 2004.

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Sang-Gug Lee (M’04) was born in Gyungnam, Korea, in 1958. He received the B.S. degree in electronic engineering from Gyungbook National University, Gyungbook, Korea, in 1981, and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida at Gainesville, in 1989 and 1992, respectively. In 1992, he joined Harris Semiconductor, Melbourne, Florida, where he was engaged in silicon-based RF integrated-circuit designs. From 1995 to 1998, he was an Assistant Professor with the School of Computer and Electrical Engineering Handong University, Pohang, Korea. Since 1998, he has been with the Information and Communications University, Daejeon, Korea, where he is currently an Associate Professor. His research interests include the silicon-technology-based (bipolar junction transistors (BJTs), BiCMOS, CMOS, and SiGe BiCMOS) RF integrated-circuit designs such as LNAs, mixers, oscillators, power amps, etc. He is also active in the high-speed integrated-circuit designs for optical communication such as transimpedance amplifiers (TIAs), driver amps, limiting amps, clock data recovery ICDR), mux/demux, etc.

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An Efficient Nonlinear Circuit Simulation Technique Emira Dautbegovic´, Student Member, IEEE, Marissa Condon, Member, IEEE, and Conor Brennan, Member, IEEE

Abstract—This paper proposes a novel method for the analysis and simulation of integrated circuits (ICs) with the potential to greatly shorten the IC design cycle. The circuits are assumed to be subjected to input signals that have widely separated rates of variation, e.g., in communication systems, an RF carrier modulated by a low-frequency information signal. The proposed technique involves two stages. Initially, a particular order result for the circuit response is obtained using a multiresolution collocation scheme involving cubic spline wavelet decomposition. A more accurate solution is then obtained by adding another layer to the wavelet series approximation. However, the novel technique presented here enables the reuse of results acquired in the first stage to obtain the second-stage result. Therefore, vast gains in efficiency are obtained. Furthermore, a nonlinear model-order reduction technique can readily be used in both stages making the calculations even more efficient. Results will highlight the efficacy of the proposed approach. Index Terms—Integrated-circuit (IC) design, model-order reduction, nonlinear circuit simulation, wavelet collocation scheme.

I. INTRODUCTION

I

N THE initial stage of a design cycle, the circuit designer is interested in the overall functional behavior of the designed circuit, i.e., will the integrity of desired logical states be preserved at the output? In order to ascertain this, the designer needs to perform numerous simulations before settling on a final design. Any change in the requirements for the circuit design will necessitate the simulation process to restart from the beginning. Furthermore, the complexity of today’s integrated circuits (ICs) is such that these simulations are computationally expensive both in terms of time and computer resources. The overall result is a prolonged design cycle that is economically unacceptable. Hence, there is a need for a simulation technique that enables the designer to obtain the circuit response with the desired accuracy and within a reasonable time frame. Ideally, the first phase of the design process should involve obtaining a rough initial result for the circuit response to verify the functionality of the design. In the second phase, when a higher degree of accuracy for fine tuning the designed IC is sought, the possibility of reusing results from the first phase would yield huge gains in the efficiency of a simulation, thereby leading to major savings in design time and ultimately reducing the cost of the designed IC. Harmonic balance [1]–[3] and time-domain integration [4] are the two most widely employed circuit simulation techniques

Manuscript received April 18, 2004; revised August 16, 2004. This work was supported by IBM under the Ph.D. Fellowship Program. The authors are with the School of Electronic Engineering, Dublin City University, Dublin 9, Ireland (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840627

in circuit simulators for the analysis of high-frequency nonlinear circuits. Harmonic balance is most effective for periodic or quasi-periodic steady-state analysis of mildly nonlinear circuits and, thus, is of limited use for the complex modulation formats encountered in today’s high-speed systems or for systems involving strong nonlinearities. Time-domain integration, on the other hand, is only practical for baseband systems. For the simulation of circuits with digitally modulated high-frequency carriers with long bit sequences, time-domain integration is excessively slow. As a result, there is a need for some form of a general-purpose technique that can simulate state-of-the-art systems that are subject to transient high-frequency signals or complex modulated RF carriers. Several envelope transient analysis approaches have recently been proposed, whereby a mixed-mode technique is implemented [5], [6]. The essence of these approaches is that the slowly varying envelope of a signal is treated by time-domain integration and that harmonic balance treats the high-frequency carrier. However, existing techniques have limitations, e.g., restrictions in the bandwidth of the excitation signal [5] and the limitations of harmonic balance with respect to strong nonlinearities. In [7], Roychowdhury proposes converting the differential-algebraic equations that describe the circuit to multitime partial differential equations and applying time-domain methods directly to solve the resultant systems. Pedro and Carvalho [8] also employ a multitime partial differential-equation approach, but uses a combination of harmonic balance and time-domain integration to solve the resultant system. The basic technique presented in this paper is a variation and improvement of the multitime partial differential-equation approach presented by Condon and Dautbegovic´ in [9]. A modification of the wavelet-based collocation approach proposed by Cai and Wang in [10] forms the core of the technique and, unlike Christoffersen and Steer [11], the cubic spline wavelet basis is employed to solve the multitime partial differential-equation representation of the system rather than the original ordinary differential-equation representation. However, the technique presented in [9] is greatly enhanced in this paper, yielding considerable gains in efficiency in two respects. Firstly, a nonlinear model reduction process similar to that in [12] is employed within the proposed envelope simulation technique to obtain very high standalone simulation efficiencies, as shown in [13]. This paper compares, for test systems, the result that is obtained with a full wavelet system, as is employed in [9], to the result that is obtained when the model reduction strategy is utilized. The accuracy will be seen to be excellent while significant gains in computational speed are achieved. A result is also given when a lower order wavelet scheme is employed. The results will confirm that, for comparable computation times, significant gains in accuracy may be achieved by employing the

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approach proposed in this paper as opposed to simply using a lower order full wavelet scheme. Secondly, in this paper, a further step toward a more accurate simulation technique with even greater efficiency within the overall design cycle has been proposed. The crucial step introduced in this paper involves utilizing the multiresolution nature of wavelet systems [14]. Rather than recalculating a complete set of new coefficients for a higher degree accuracy approximation, it utilizes the coefficients calculated from a previous simulation that involved a lower order approximation. Each time a new layer is added in the wavelet series approximation, only the coefficients for that layer need to be calculated. The process may be repeated by adding more layers until the required degree of accuracy is achieved. The excellent simulation results obtained for test circuits show the potential of the proposed technique as a modern design simulation tool. The remainder of this paper is organized as follows. Section II gives a short presentation of the multitime partial differentialequation approach. Sections III and IV describe the technique for obtaining the rough initial solution of the first stage. Section V further extends this contribution by presenting the mathematical basis for an approximation with a higher degree of accuracy incorporating results from an approximation with a lower degree of accuracy. Finally, the simulation results obtained for sample circuits using the proposed technique are presented in Section VI.

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Fig. 1.

Diode rectifier circuit.

has been suggested by the authors [9]. In Section III, a brief overview of the wavelet collocation scheme is given. III. WAVELET COLLOCATION SCHEME The technique involves approximating the unknown function with a wavelet series in the dimension where is scaled such that , i.e.,

II. MULTITIME PARTIAL DIFFERENTIAL-EQUATION APPROACH that is composed of a carrier moduConsider a signal lated by an envelope where the envelope signal is assumed to be uncorrelated with the carrier. The signal may be represented in two independent time variables as (1) relates to the low-frequency envelope and relates to the high-frequency carrier. Now consider a general nonlinear circuit described by (2) is the excitation vector, are the state variables, where and is a nonlinear function. The corresponding multitime partial differential-equation system can be written as shown in [7] as (3) This multitime partial differential equation can be solved using exclusively time-domain approaches as employed by Roychowdhury [7] or using a combination of time-domain integration for the envelope and harmonic balance for the carrier, as in [8]. However, for strongly nonlinear circuits, the use of harmonic balance for the inner loop can prove limited. Another approach for solving (3) using a pseudowavelet collocation method derived from that proposed by Cai and Wang [10]

(4) and are scaling and wavelet functions, respecwhere tively, and are spline functions introduced to approximate are the boundary nonhomogeneities, as described in [10]. unknown coefficients, which are a function of only. The total , where deternumber of unknown coefficients is mines the level of wavelet coefficients to be taken into account . From this point forward, when approximating shall be referred to as wavelets where it is understood that these , the wavelet functions , comprise the scaling functions and the nonhomogeneity functions . As proposed by Condon and Dautbegovic´ in [9], (3) is then to result in a semidiscollocated on collocation points in cretized equation system. The interpolation points are those as chosen in [10]. At this juncture, a nonlinear model reduction strategy is employed. The particular model reduction strategy chosen is based on that presented by Gunupudi and Nakhla in [12]. Thus, instead of solving an th-order system at each time step to obtain the unknown state variables and output quan, a reduced-order system of transformed coefficients is tity solved. Once the transformed coefficients are determined for the , entire time range of interest, the original coefficients, and, consequently, the value of the state variables and output may be obtained in one single post-processing quantity step. The solution process with the applied reduction scheme is described in detail in the Section IV.

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(a)

(b)

(c)

(d)

Fig. 2. (a) Result from ODE solver with a very short time step. (b) Result from a full wavelet scheme (J = 1; L = 80). (c) Result from a full wavelet scheme (J = 1; L = 80) with model-order reduction applied (q = 5). (d) Result with lower order full wavelet scheme (J = 0; L = 5).

IV. MODEL REDUCTION TECHNIQUE The expression in (4), if written for all collocation points in , may be expressed as follows at a specific point in time (5) where is a constant -dimensional square matrix whose columns comprise the values of the wavelet functions at the collocation points. The matrix is evaluated once at the outset of the algorithm. is an -dimensional column is an -divector of the unknown state variables and mensional column vector of the unknown wavelet coefficients at the collocation points in at a specific instant in . Substitution of (4) and (5) in (3) yields (6) is an -dimensional matrix whose columns are where formed from the derivatives of the wavelet functions in (4)

collocation points in . Again, evaluated at each of the is evaluated only once at the outset of the algorithm. and are column vectors comprising the values of and at the collocation points. is expanded in At this point, the vector of coefficients a Taylor series as follows: (7) where is the initial time and where the coefficients computed recursively as in [12]. A Krylov space is formed for as follows:

may be

(8) where is the order of the reduced system and is significantly less than . An orthogonal decomposition of results in (9)

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where . is the -dimensional identity matrix. is then employed to perform a congruent transformation of (5) as follows: (10) Thus, a new reduced equation system is formed as

or (11) and . where This new system, i.e., (11), of dimension may then be solved to determine over the entire time domain of interest. A trapezoidal-rule integration scheme is employed because of its superior stability qualities. Once the coefficients have been and, consequently, , may determined, be obtained in one single post-processing step. Thus, the above solution process is significantly more efficient than solving at each time step, as was done in [9]. directly for

(a)

V. FORMATION OF AN APPROXIMATION OF A HIGHER DEGREE OF ACCURACY Assume that a preliminary circuit response is obtained by applying the technique presented in Section IV. If a response with a higher degree of accuracy is now required, the wavelet series can be expanded approximating the unknown function for another layer, i.e., (b)

(12) where and the total number of unknown coefficients . At this point, two options are available. is now Firstly, the method proposed in Section IV can be implemented from scratch to obtain the circuit response. The size of the ordinary differential equations (ODEs) system to be solved to is increased from and, consequently, the computational requirements for obtaining the required solution are also increased. Alternatively, the following approach may be applied to obtain the circuit response with increased accuracy. First, write (12) as

Fig. 3. (a) Accuracy improved by adding an extra layer (J = 2) in wavelet series approximation. (b) Result from the proposed new higher order technique after adding an extra layer (J = 2) in wavelet series approximation.

(14) The first term in (14) depends solely on coefficients from previous layers. The values for these coefficients at the collocation points up to the layer are already known from previous calculations and any additional required values can be obtained using an interpolation technique [15]. The second term in (14) consists solely of coefficients from the added layer and, thus, they need to be calculated. Now, for presentation purposes, consider the following notation: (15) and (16)

(13) or, after setting proximating the unknown function

, the wavelet series apcan be written as

Thus, the wavelet series approximating the unknown function can be written as

(17)

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Fig. 4. MESFET amplifier.

The expression in (17), if written for the collocation points of the added layer in , may be expressed as follows at a specific point in time :

Substituting (20) in (19) yields the following equation:

(21) (18) This may be written for convenience as is an -dimensional column vector of the unknown where is an -dimensional wavelet coefficients of layer . column vector of the known wavelet coefficients at the collocation points in at a specific instant in , and its entries are either already known directly or may be obtained as interpolated is a constant -dimensional values for any time . matrix whose columns comprise the values of the wavelet at the collocation points of the extra functions is a constant -dimensional square matrix layer, while at the collocation points as its entries. All with constant matrices are evaluated only once at the outset of the is an -dimensional column vector of algorithm. the unknown state-variables on layer . Substitution of (17) and (18) in (3) yields (19) where is an dimensional matrix whose columns are formed from the derivatives of the wavelet functions evaluated collocation points in , and is an at each of the dimensional matrix. Again, and are evaluated only once and are column vectors at the outset of the algorithm. comprising the values of and at the collocation points of level . Bearing in mind the notation introduced in (15) and (16), may be expressed, using (6), as a function of (20)

(22) where

(23) and (24) system of ODEs where Equation (22) represents an the unknowns may be readily determined using a standard numerical technique for solving a system of ODEs [16]. A trapezoidal-rule integration scheme is recommended because of its stability qualities. The system in (22) is significantly smaller in dimension than that in (6) in that it involves unknowns rather unknowns when written for the same wavelet apthan . Therefore, the computational cost for proximation level obtaining the circuit response is significantly reduced. Furthermore, the structure of the equations in (6) and (22) is exactly the same. Therefore, the same model-order reduction technique, as presented in Section IV, may readily be applied to the system in (22). As a result, even more gains in computational efficiency may be achieved. VI. SAMPLE SYSTEMS The above technique has been employed for two nonlinear systems: a diode rectifier circuit and a MESFET amplifier. The nonlinear diode rectifier circuit is deliberately selected, as it is strongly nonlinear in nature. The ability to efficiently simulate

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the behavior of this circuit with good accuracy will provide a strong recommendation for employing the wavelet-based simulation technique presented here to simulate nonlinear circuits subjected to input signals that have widely separated rates of variation. The results for the MESFET amplifier response will further confirm the efficacy of the proposed method for structurally complex nonlinear circuits. A. Nonlinear Diode Rectifier Circuit The highly nonlinear diode rectifier circuit, as shown in Fig. 1, is excited with the following source:

(25) corresponds to the envelope period and correwhere sponds to the carrier period. Fig. 2(a) shows the output from an ordinary differential-equation solver with a very short time step in order to obtain a highly accurate version of the output voltage to act as a benchmark for the purposes of confirming the accuracy of the proposed new simulation technique. Fig. 2(b) presents the output from a full wavelet scheme with no model-order reduction applied, as was done in [9]. For the and , the size of the chosen wavelet parameters . An adaptive backward-Euler preODE system is dictor corrector approach is employed for obtaining the solution. Good agreement is achieved when compared to the “accurate” result [see Fig. 2(a)]. However, the size of an ODE system that is solved is considerable and requires significant computer resources. Fig. 2(c) shows the output when the model-order reduction technique proposed in Section IV is applied. For the same , the initial system of wavelet parameters unknown wavelet coefficients is reduced to before obtaining the solution for the reduced-order system (11). In terms of accuracy, the relative difference between the result from the full wavelet scheme and the results obtained having applied the model reduction technique is negligible. However, in terms of computational time, the result obtained with the model reduction technique is computed in only 7% of the time necessary for the full wavelet scheme. This excellent gain in computational efficiency is due to the fact that, instead of solving an ODE system with 163 unknowns, a system with only five unknowns is solved. Finally, Fig. 2(d) shows the result when a lower order full and in wavelet scheme is employed. In this case, th-order system of equations, which (4). This results in an has similar computational requirements to the reduced wavelet . As can be seen from Fig. 2(d), there is scheme with a significant loss in accuracy. This result clearly confirms that the approach presented in Section IV is significantly better than simply employing a full lower order wavelet scheme, especially when circumstances require high computational efficiency. To emphasize the gains in accuracy achieved by the addition of an extra layer in the wavelet approximation series, Fig. 3(a)

(a)

(b)

(c) Fig. 5. (a) Result from an ODE solver with a very short time step. (b) Result with full wavelet scheme (J = 1; L = 20) with model-order reduction (q = 20) applied. (c) Result with the proposed new higher order technique after adding an extra layer (J = 2) in wavelet series approximation.

shows an example with wavelet layers and . The collocation points range parameter was deliberately chosen to be very low so that gains in the accuracy due to adding an extra layer would be highlighted. The significant improvement in the accuracy of the circuit response, as evidenced from Fig. 3(a), confirms the rationale for employing extra layers.

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However, if the basic wavelet approach of Section IV for simulating a system is employed, the addition of extra layers increases the computational requirements greatly. However, with the novel technique proposed in Section V, this is no longer a barrier. Fig. 3(b) shows the results for the diode rectifier circuit with . The full line reprea new layer added sents result obtained using a full wavelet scheme with model reduction. The dashed line is the circuit response calculated at the same wavelet level, but reusing results calculated from the lower order simulation. As can be seen, these two responses are practically indistinguishable. However, it took only 14% of the computing time to obtain the higher degree of accuracy circuit response with the new method when compared to the time necessary to compute the circuit response by simply restarting the full wavelet simulation scheme . with

Furthermore, utilizing the multiresolution nature of wavelets, this paper has presented a further step toward a more accurate simulation technique with even greater efficiency within the overall design cycle. Rather than recalculating a complete set of new coefficients for higher order approximation of the unknown in the multitime partial differential-equation representation of the system, it utilizes the coefficients calculated from a previous simulation that involved a lower order approximation. Therefore, the technique can be very useful for the IC designer since it enables the desired circuit response degree of accuracy to be achieved in steps rather than restarting simulations each time a higher degree of accuracy is sought. The results from highly nonlinear sample circuits indicate the efficiency and accuracy of the proposed approach. As shown, the multilayer approach allows a controlled refinement and, for any practical usage, it would be helpful to derive the error measurement. This forms a basis of future work by the authors.

B. MESFET Amplifier Fig. 4 presents a practical RF MESFET amplifier circuit whose behavior is described by a tenth-order ODE system. The source input has the same structure as in (25), i.e., it has widely separated rates of variation. Fig. 5(a) shows the output from an ODE solver with a very short time step in order to obtain a highly accurate version of the output voltage to act as a benchmark. Fig. 5(b) presents the MESFET response with the full wavelet scheme employed. As can be seen, the general nature of the circuit response is obtained. However, the lowis not sufficient in this order wavelet approximation case to acquire the fine details of the output. Hence, there is a need to use a higher order wavelet approximation. Fig. 5(c) presents the output obtained with the proposed new higher degree accuracy technique after adding an extra layer in the wavelet series approximation. It can be seen that the accuracy of the output voltage is considerably improved. However, it took only 21% of the computational time to obtain the circuit response with the new technique involving the calculation of an extra layer coefficients compared to the computational time required when the simulation is restarted from the beginning. Therefore, the results presented here clearly confirm that, by employing the approach presented in Section V, the accuracy degree may be increased by adding an extra layer into the wavelet series approximation, but with considerably less computational costs than restarting a full wavelet scheme. This is possible since the coefficients calculated for a lower order approximation are reused to form the higher order approximation. VII. CONCLUSION A highly efficient wavelet-based simulation technique for high-frequency circuits has been presented. The multitime partial differential-equation system describing the circuit has been solved using a pseudowavelet collocation method. A nonlinear model-reduction process has been applied, leading to significant gains in efficiency, but without a complementary loss in accuracy.

ACKNOWLEDGMENT The authors wish to acknowledge the help of Prof. T. Brazil and the Microwave Engineering Research Group, University College Dublin, Dublin, Ireland. REFERENCES [1] K. S. Kundert and A. Sangiovanni-Vincentelli, “Simulation of nonlinear circuits in the frequency domain,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. CAD-5, no. 10, pp. 521–535, Oct. 1986. [2] D. Long, R. Melville, K. Ashby, and B. Horton, “Full-chip harmonic balance,” in Proc. IEEE Custom Integrated Circuits Conf., Santa Clara, CA, 1997, pp. 379–382. [3] M. Nakhla and J. Vlach, “A piecewise harmonic balance technique for determination of periodic response of nonlinear systems,” IEEE Trans. Circuits Syst., vol. CAS-23, no. 2, pp. 85–91, Feb. 1976. [4] L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” Univ. California at Berkeley, Berkeley, CA, Tech. Rep. ERLM520, 1975. [5] E. Ngoya and R. Larcheveque, “Envelope transient analysis: A new method for the transient and steady-state analysis of microwave communications circuits and systems,” in IEEE MTT-S Int. Microwave Symp. Dig., San Francisco, CA, 1996, pp. 17–21. [6] D. Sharrit, “New method of analysis of communication systems,” presented at the IEEE MTT-S Nonlinear Computer-Aided Design Workshop, Jun. 1996. [7] J. S. Roychowdhury, “Analyzing circuits with widely separated timescales using numerical PDE methods,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 5, pp. 578–594, May 2001. [8] J. C. Pedro and N. B. Carvalho, “Simulation of RF circuits driven by modulated signals without bandwidth constraints,” in IEEE MTT-S Int. Microwave Symp. Dig., Seattle, WA, 2002, pp. 2173–2176. [9] M. Condon and E. Dautbegovic, “A novel envelope simulation technique for high-frequency nonlinear circuits,” in Proc. 33rd Eur. Microwave Week, Munich, Germany, 2003, pp. 619–622. [10] W. Cai and J. Z. Wang, “Adaptive multi-resolution collocation methods for initial boundary value problems of nonlinear PDEs,” SIAM J. Numer. Anal., vol. 33, pp. 937–970, Jun. 1996. [11] C. E. Christoffersen and M. B. Steer, “State-variable-based transient circuit simulation using wavelets,” IEEE Microwave Wireless Compon. Lett., vol. 11, no. 4, pp. 161–163, Apr. 2001. [12] P. K. Gunupudi and M. S. Nakhla, “Model reduction of nonlinear circuits using Krylov-subspace techniques,” in Proc. Design Automation Conf., New Orleans, LA, 1999, pp. 13–16. [13] E. Dautbegovic, M. Condon, and C. Brennan, “An efficient nonlinear circuit simulation technique,” in IEEE RFIC Symp. Dig., Fort Worth, TX, 2004, pp. 623–626.

DAUTBEGOVIC´ et al.: EFFICIENT NONLINEAR CIRCUIT SIMULATION TECHNIQUE

[14] C. S. Burrus, R. A. Gopinath, and H. Guo, Introduction to Wavelets and Wavelet Transforms (A Primer). Englewood Cliffs, NJ: Prentice-Hall, 1998, pp. 10–19. [15] J. M. Maron and R. J. Lopez, Numerical Analysis: A Practical Approach, 3rd ed. Belmont, CA: Wadsworth, 1991, ch. 6. , Numerical Analysis: A Practical Approach, 3rd ed. Belmont, [16] CA: Wadsworth, 1991, ch. 8.

Emira Dautbegovic´ (S’99) received the B.Sc. degree in control and electronic engineering from the University of Sarajevo, Sarajevo, Bosnia Herzegovina, in 2000. She is currently a Ph.D. Researcher with the RF Modeling and Simulation Group, School of Electronic Engineering, Dublin City University, Dublin, Ireland. From 2000 to 2001, she was with Javno Preduzece Elektroprivreda Bosne i Hercegovine (JP EPBiH), the national electric power supplier in Bosnia Herzegovina. From 1999 to 2001, she was a Teaching Assistant with the Faculty of Electrical Engineering, University of Sarajevo. Her current research interests are in the area of simulation and modeling of high-speed linear and nonlinear circuits, development of computer-aided design (CAD) algorithms for high-frequency circuits and systems, simulation of interconnects, model-order reduction techniques, and the development of efficient numerical algorithms. Ms. Dautbegovic´ is member of the Institution of Engineers of Ireland (IEI), the Institution of Electrical Engineers (IEE), U.K., and the Association of Computing Machinery (ACM). She was co-founder and the vice-president of the IEEE Student Branch at the University of Sarajevo. She was a recipient of the 2002–2003 and 2003–2004 IBM Worldwide Fellowship Program. She was among the top 5% of students of the Faculty of Electrical Engineering, University of Sarajevo, for which she was the recipient of the Golden Medallion.

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Marissa Condon (M’98) received the B.E. degree (with honors) and Ph.D. degree from the National University of Ireland, Galway, Ireland, in 1995 and 1998, respectively. She then joined the National Grid of the Electricity Supply Board of Ireland for two years prior to joining the School of Electronic Engineering, Dublin City University, Dublin, Ireland. She is also joint leader of the RF Modeling and Simulation Group, Dublin City University. Her research interests are the analysis and simulation of high-frequency circuits, the development of algorithms for CAD packages, nonlinear model reduction, and the development of suitable macromodels for large-scale circuits and systems operating at high frequencies. Dr. Condon is a reviewer for the European Conference on Circuit Theory and Design (ECCTD). She served on the Steering Committee of the Universities Power Engineering Conference from 1999 to 2000.

Conor Brennan (M’02) was born in Dublin, Ireland, in 1972. He received the B.A. (Mod.) degree in mathematics and Ph.D. degree from the University of Dublin Trinity College, Dubline, Ireland, in 1994 and 1998, respectively. From 2000 to 2002, he was a Post-Doctoral Researcher with the Radio Propagation Group, Department of Electrical Engineering, University of Dublin Trinity College. In 2003, he joined the academic staff of the School of Electronic Engineering, Dublin City University (DCU), Dublin, Ireland, where he is joint leader of the RF Modeling and Simulation group. He is a member of the DCU-based Research Institute for Networks and Communications Engineering (RINCE). Dr. Brennan was the recipient of a Forbairt Post-Doctoral Fellowship on the topic of efficient integral-equation methods.

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Design of Multistandard Adaptive Voltage-Controlled Oscillators Aleksandar Tasic´, Wouter A. Serdijn, and John R. Long

Abstract—A multistandard/multiband adaptive voltage-controlled oscillator (VCO) satisfying the phase-noise requirements of both second- and third-generation wireless standards is described in this paper (1.8-GHz DCS1800, 2.1-GHz wide-band code division multiple access, and 2.4-GHz wireless local area network, Bluetooth, and digital enhanced cordless telecommunications standards). The design procedure for the VCO is based on an adaptive phase-noise model. A factor of 12 reduction in power consumption with a phase-noise tuning range of 20 dB is demonstrated by adapting the VCO bias to the desired application. The VCO achieves 123-, 110-, and 103-dBc/Hz phase noise at 1-MHz offset in a 2.1-GHz band at supply currents of 6, 1.2, and 0.5 mA, respectively. Index Terms—Adaptive circuits, loop gain, multistandard (MS)/multiband (MB) circuits, phase noise, phase-noise tuning, voltage-controlled oscillators (VCOs).

I. INTRODUCTION

T

HE DEMANDS for new telecom services requiring higher capacities and data rates have motivated the development of broad-band third-generation (3 G) wireless systems. The coexistence of second- and third-generation cellular systems requires multimode, multiband (MB), and multistandard (MS) mobile terminals. To prolong talk time, it is desirable to share and/or switch transceiver building blocks in these handsets, without degrading the performance compared to single-standard transceivers. It is possible to share circuits when different standards do not operate simultaneously. In these situations, considerable power can be saved by using circuits that are able to trade off power consumption for performance on the fly. However, MS frontends typically use duplicate circuit blocks or even entire radio front-ends for each standard. Although this approach is simpler to implement, it is neither optimal in cost, nor in power consumption [1]. For example, a voltage-controlled oscillator (VCO) that is designed to satisfy the most stringent specifications consumes more power than necessary when operating under more relaxed conditions [2]. Selection of the design parameters of an adaptive MS circuit is different from the design for a single standard. Therefore, an adaptive phase-noise model is introduced in this paper that accounts for a number of oscillator operating conditions and required specifications.

Referring to the adaptive phase-noise model, an adaptive second-generation (2 G)/3 G VCO that satisfies the phase-noise requirements of DCS1800, wide-band code division multiple access (WCDMA), wireless local area network (WLAN), Bluetooth, and digital enhanced cordless telecommunications (DECT) standards is described in this paper. Operating from a 3-V supply, a tuning range of 1.8–2.4 GHz is realized. The VCO phase noise at 1-MHz offset in a 2.1-GHz band is 123, 110, and 103 dBc/Hz for power consumption levels of 18, 3.6, and 1.5 mW, respectively. By adapting VCO power consumption to the desired operating scenario, the phase noise of the oscillator can be tuned over a 20-dB range with a factor of 12 reduction in power consumption. An adaptive VCO is described in Section II. After a thorough examination of the contribution of all noise sources to the phase noise of an oscillator, an adaptive phase-noise model is introduced in Section III. The design procedure of an adaptive VCO is outlined in Section IV, while measurement results and concluding comments are presented in Sections V and VI, respectively. II. ADAPTIVE VCO The quasi-tapped (QT) bipolar VCO [3], shown in Fig. 1, is used to implement the adaptive oscillator. It consists of a resonant LC tank and cross-coupled transconductor , where is the tank inductance, is the varactor capacitance, and and are the quasi-tapping capacitances. Feedback via tapped capacitors maximizes the voltage swing across the LC tank, while active devices and remain far from heavy saturation. Moreover, freedom to set the base bias voltage lower than the supply voltage allows for a large tank voltage, approaching the voltage swing of CMOS implementation. is degenerating inductor for the tail-current source (TCS). Degeneration of the current source is necessary to minimize the phase noise contributed by the bias circuit. The oscillation signal is delivered to the measurement equipment (50- input impedance) using an on-chip open-collector buffer and an external transformer balun (TR). Buffering the output from the bases rather than the LC tank allows the buffer to share the base bias voltage, thereby eliminating output coupling capacitors. Gain of the buffer is set by the emitter-degeneration resistance . The relationships between the parameters of the oscillator are summarized as

Manuscript received April 21, 2004. The authors are with the Electronics Research Laboratory/Delft Institute of Microelectronics and Submicrontechnology, Delft University of Technology, Delft 2628CD, The Netherlands (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840648 0018-9480/$20.00 © 2005 IEEE

(1)

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Fig. 2. QT-VCO noise sources (without degeneration).

Fig. 1.

frequency from the resonant frequency , and is the amplitude of the voltage swing across the LC tank. The noise sources of the QT VCO, with a TCS without degeneration, are shown in Fig. 2. These are the tank conductance , the base-resistance thermal noise , the colnoise lector and the base current shot noise, and the equivalent of the current source transistor input voltage noise

QT VCO with open-collector buffer.

(5) (2) (6) (7) (3) and stand for the inductor and the varactor Here, series loss resistances, for the effective tank conductance, is the quasi-tapping factor, is the small-signal conductance seen by the LC tank, is the transconductance of the bipolar transistors and is their base–emitter capacitance, is the small-signal loop gain of the oscillator, is the tail current, is the oscillation frequency, and is the thermal voltage. III. PHASE-NOISE MODEL OF AN ADAPTIVE OSCILLATOR Phase noise of an oscillator is defined as the ratio of the noise and the power in a 1-Hz bandwidth at a frequency carrier power

(4) and stand for the total voltage and current noise spectral densities at the output of the oscillator (LC tank), is the equivalent tank impedance at an offset

and stand for the collector and base currents, is the transconductance of the transistor , and is the Boltzmann’s constant. For the estimation of the phase noise of the QT VCO, the transfer of the indicated noise sources to the LC tank must be known. Considering the transconductor as a nonlinear voltage-to-current converter (limiter) allows for the inclusion of all the noise-generating mechanisms in the oscillator. Namely, phenomena such as switching of the transconductor noise and the noise of the tail current source, both resulting in the folding of noise, can be understood. A. Time-Varying Transfer Function The nonlinear voltage-to-current transfer function of the transconductor and its equivalent time-varying transconductance in the presence of a large driver signal are shown in Fig. 3 does not [4]. As long as the limiting of the oscillation occur, the transfer function of an accompanying small signal has a constant value . When limiting occurs, the small-signal (e.g., noise) transfer reduces to zero. If the large-signal oscil, the period of a small signal time-varying lation period is is . Considering the transfer from bases to the gain – , the small-signal gain collectors of the transconductor is .

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Fig. 3. V-to-I and time-varying transfer functions.

Before evaluating the contribution of the various noise sources to the phase noise of the oscillator, let us first estimate the duty cycle (Fig. 3) of the time-varying gain. If is the voltage swing of the oscillation signal across is the linear region the bases of the transconductor, and of the limiter, the duty cycle of the time-varying gain can be expressed as

Fig. 4. Base-resistance noise folding.

The contribution of the base-resistance noise at the output (LC tank) now becomes (14)

(8) With the aid of (2), the voltage swing across the tank (a product and the first Fourier coefficient of of the tank resistance the current ) equals

where and tance of the active devices with the aid of the equality

and

is the startup transconduc. This result is obtained

(15) (9) Assuming a 100-mV transconductor linear region and a large loop-gain value , the duty cycle without loss of generality can be written as (10)

that is derived from (2). C. Transconductor Shot Noise By splitting the current noise sources, the collector and base current shot noise transform to the resonator as given by the following: (16)

B. Base-Resistance Noise and (both contribuThe noise from the transistors tions) is switched on/off with the frequency of time-varying gain . As a consequence, noise folding occurs, i.e., noise from a number of frequencies is converted into the noise at one frequency. The harmonic components of the white base-resistance noise (multiples of ) and the components of the timevarying gain are shown in Fig. 4. at odd As a result of the noise folding, the base noise multiples of the oscillation frequency is converted to the LC tank at the resonance frequency, as given by the following: (11)

(12)

are the (complex) Fourier coefficients and is the period . With the aid of (2), the of the transfer function transferred noise density equals (13)

The noise sources of both transistors are active for a fraction of the period , whereas for the rest of the period, the noise sources of only one transistor are active. With the aid of (6), (10), and (16), the contribution of the transconductor shot noise becomes (17) The same result would be obtained if switching of the shot noise is considered. Namely, the transconductor shot noise, when both transistors are active, turns on and off with the rate (Fig. 2 with ). Referring to of the transfer function (12), this would lead to (17) as well. D. Tail-Current Noise (TCN) The harmonic components of the equivalent TCN (multiples of ) and the components of the ideal switcher are shown in Fig. 5. The noise of the biasing current source is modulated by the oscillator switching action. Therefore, the TCN around even multiples of the resonant frequency is folded back to the

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of the active part noise and the tank resistance noise as , and the contribution of the TCN as , we can define the phase-noise difference (PND) as the ratio of the corresponding noise contributions (24) as follows: (24) Referring to (24), the PND becomes (25)

Fig. 5. TCN folding.

resonator noise at the oscillation frequency as given by the following:

(18) Here,

is the output noise current density of the TCS and are the (complex) harmonic components of the squarewave ( 1 ideal switch). To account for the finite switching time, a factor is added, as the tail current noise does not conand are sitribute to the phase noise when transistors originates from the active multaneously active. The factor . transistors load impedance By combining (7) and (18), and using the well-known weights of the square-wave amplitude components

The PND compares the contributions of the TCN and all other and (VCO design data), then noise sources. If . In other words, the TCS for a loop gain, degrades the phase-noise performance of the VCO by 10.5 dB. F. Resonant-Inductive Degeneration (RID) has the largest Recognizing that the bias current noise at impact, RID [8] is employed to minimize the TCN contribution. The procedure relies on forming a resonance between the deand the base–emitter capacitance generating inductor of the TCS at twice the oscillation frequency. As the input impedance of an inductively degenerated transistor equals [9],

(26) the imaginary part is set to zero at satisfied as follows:

(19)

when condition (27) is

(27)

the transferred TCN density equals is the TCS transistor transit frequency, and is the real part of the impedance seen at the base of the current source transistor. Now, the transfer function of the TCS base-resistance noise (i.e., the equivalent transconductance of the RID current–source transistor) to the output current noise of the degenerated TCS at equals [9] Here,

(20) Finally, with the aid of (2), (15), and (20), the contribution of the TCN to the phase noise becomes (21)

(28) E. Oscillator Total Noise Considered to be uncorrelated, all noise sources, viz., the tank conductance noise, base resistance noise, transconductor shot noise, and TCN add to the equivalent output noise, as given by the following: (22) Now, the noise factor

The TCS collector-current shot noise is suppressed, while the base-current shot noise is completely transferred to the output the TCS transistor of the current source because at operates in a common base-like configuration. Combining these contributions, the total output noise density of the RID TCS becomes

of the oscillator is (29) (23)

From (23), it can be observed that the contribution of the TCS noise to the phase noise of the VCO (Fig. 1) is larger than all other contributions together [5]–[7]. Denoting the contribution

where and stand for the TCS base-resistance and base-current noise sources. Equation (29) implies that by apis reduced by plying RID, the contribution of the TCN at more than a factor of .

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Referring to the example of this section, i.e., and , the applied RID results in a factor of 40 TCN suppression (VCO design data). The calculated PND reduces to 1.1 dB after the degeneration, which is an improvement of 9.4 dB. The simulations predict an improvement of 7 dB and dB [see (24)] for this low loop-gain value. For larger loop-gain values (in the current design ) and, accordingly, larger ’s of the transistors, a factor of 100 bias-noise suppression is expected, making the noise contribution of the TCS almost negligible. Therefore, the noise factor of the VCO with RID of the bias TCS reduces to (30) G. Phase-Noise Tuning Model When the noise contributed by the bias circuit is negligible, the oscillator phase-noise performance depends on the components in the ac signal path, viz., transconductance cell and resonator. With the aid of (4), (9), (22), and (30), the adaptive phase-noise model becomes (31) This model is parameterized with respect to power consumption via loop gain . Unlike fixed hardware determined design parameters, the loop gain and voltage swing can be varied by , shown in Fig. 1. This allows adaptation changing current of the oscillator phase noise to different specifications. The phenomenon is named phase-noise tuning [10], while the figure-ofmerit describing the oscillator’s adaptivity to phase noise is the -times change in phase-noise tuning range (PNTR). For a power consumption, the PNTR is defined as (32) Once the minimum and maximum attainable loop gains are known, the ranges of the power-consumption and phase-noise adaptation can be determined. For example, if and (VCO design data), (32) predicts that 17.4 dB of the phase noise can be traded for a factor of ten savings in power consumption. IV. DESIGN FOR ADAPTIVITY Selection of the design parameters for an adaptive multistandard oscillator is different from the design for a single standard. The design of an adaptive MS/MB VCO (i.e., DCS1800/WCDMA/WLAN–Bluetooth–DECT) will be outlined here. The phase-noise requirements (decibels relative to a carrier/hertz at 1–MHz offset in receive modes) for five different standards are listed in Table I [11]–[15]. We will refer to the DCS1800 standard as a phase-noise demanding (PN-D) standard, to the WCDMA, WLAN, and Bluetooth standards as phase-noise moderate (PN-M) standards, and to the DECT standard as a phase-noise relaxed (PN-R) standard. Given the phase-noise requirements listed in Table I, the phase-noise range between demanding (PN-D) and moderate

TABLE I MS/MB VCO REQUIREMENTS

(PN-M) modes is GHz GHz dB. Taking into account the relaxed DECT mode (PN-R), the PNTR increases to dB. Therefore, a PNTR of 21 dB is targeted. Having the effects of the noise from the biasing TCS eliminating by RID (27), the minimum and maximum loop gain and tail current can be estimated from (32). Accordingly, the PNTR of 17.4 dB can be realized between the loop gain (safety startup) and . However, if is 1.5, the tuning range extends to dB. Once the maximum loop gain is known, the oscillator biasing is can be determined. The choice of the base bias potential a compromise between a large output voltage swing and satuand (Fig. 1). For the ration of transconductor devices maximum loop gain and lowest phase noise, a voltage swing of V is estimated from (9). Further, to avoid saturation of the transistors in the active part of the oscillator, should satisfy (33) This worst case condition is derived assuming the largest base and the lowest collector potential and, therefore, insures proper operation of the transistors in the active part at all times. V is the supply voltage, is the base–emitter voltage, and is the collector–emitter saturation voltage. For a capac, a base potential of V itive quasi-tapping ratio is finally obtained from (33). The calculations indicate that a factor of ten reduction in power consumption can be realized between the PN-D and PN-R modes of the adaptive VCO under consideration. A. VCO Circuit Parameters nH is chosen as a compromise between Tank inductor low power consumption and high quality factor in the 2.1-GHz band. The inductor is fabricated using 4- m-thick aluminum top metal in a 50-GHz SiGe technology. The three-turn inductor m, a metal width of has an outer diameter of m, and a metal spacing of m. The differentially shielded symmetric inductor uses a ladder metal filling scheme, as shown in Fig. 6 [16]. This improves the peak factor by 40%, but has only a minor effect on the inductor self-resonant frequency ( around 2.1 GHz). It also satisfies the aggressive metal fill restrictions in modern very large scale integration (VLSI) backend technologies without compromising RF performance. The quality factor of the varactor can also limit the overall tank factor in an integrated oscillator. The quality factor of from simthe collector–base varactor is estimated at ulation. The varactor consists of two base–collector diodes with 32 fingers, each 4- m wide and 20- m long.

´ et al.: DESIGN OF MS ADAPTIVE VCOs TASIC

Fig. 6. Shielded inductor layout (bottom view).

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Fig. 8. Packaged integrated circuit (IC) on a printed circuit board (PCB) in test fixture.

Fig. 9. Fig. 7.

f -tuning curve for a 3-V tuning voltage.

MS VCO photomicrograph.

For a quasi-tapping ratio of , the metal–insulator–metal capacitances fF and fF are is chosen. For effective suppression of the TCS noise, set to 3.4 nH using the resonant-tuning design method outlined in Section III. The degeneration inductor is realized in the 0.85- m-thick second metal layer, as for this inductor is not m, of concern. The inductor outer diameter is m, metal spacing is m, and it metal width has seven turns. Finally, the open-collector output buffer is designed with an - linearization resistor and a bias mA. current V. MEASUREMENT RESULTS The chip photomicrograph is shown in Fig. 7. It occupies an area of 700 970 m including the bondpads. Wire bonded in a 20-lead RF package, the chip is tested in a metal fixture with filtering on all bias and supply lines, as shown in Fig. 8. On the test board, three-stage low-pass LC filters designed remove low-frequency noise originating from the power supply and bias interconnections. Heavy filtering of the supply and bias lines is needed to remove spurs from the VCO output caused by pick-up from the supply and tuning lines. This unwanted interference

Fig. 10.

Phase noise at 1-MHz offset in the 2.1-GHz band.

modulates the VCO in both phase and frequency, making accurate phase-noise measurements impossible without the employed filtering on bias lines. For a 3-V supply, the frequency tuning range of 600 MHz (i.e., output from 1.8 to 2.4 GHz) is measured, as shown in Fig. 9. This frequency range covers all the bands of interest. Plots of the measured phase noise at 1-MHz offset in the 2.1-GHz mid-frequency band are shown in Fig. 10. Due to the

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The 2 G/3 G adaptive VCO, operating in DCS1800, WCDMA and WLAN–Bluetooth–DECT bands, satisfies the phase-noise requirements of these standards at 18-, 3.6-, and 1.5-mW power consumption, respectively.

TABLE II OSCILLATOR PERFORMANCE IN 2.1-GHz BAND

REFERENCES TABLE III POWER-CONSUMPTION AND TUNING-RANGE FIGURES-OF-MERIT

degeneration resistor in the output buffer, an output signal in order of 20 dBm (maximum) is measured in a 50- system. This results in a noise floor for the phase-noise measurement of 130 dBc/Hz, as shown in Fig. 10. The operating conditions accompanying the measurements shown in Fig. 10 are listed in Table II. As can be seen from Table II, by adapting the bias tail current from 0.5/0.9 mA to 6 mA, a PNTR of 20 dB/15 dB is achieved. This satisfies the requirements of five different wireless standards, as desired. Note that following the measured phase-noise slope in the range 100 kHz–1 MHz, a phase noise better than 133 dBc/Hz at a 3-MHz offset is expected, fulfilling the most stringent DCS1800 requirement (in a receive mode) at this offset as well. The power-consumption figure-of-merit and the tuning-range of the figure-of-merit oscillator under consideration are compared with other designs from the recent literature in Table III (modulus: decibels). The adaptive VCO shows a good compromise between phase-noise and frequency-tuning performance. Referring to Leeson’s phase-noise formula (34),

(34) FOM2 appears to be a useful VCO figure-of-merit. It accounts for the frequency dependency of the phase noise, as well as the power consumption and tuning range of the oscillator, the latter related to the LC tank factor.

VI. CONCLUSION By sharing functional blocks among different standards, adaptive MB/MS front-end circuits offer reduced complexity, power consumption, chip area, and overall cost. The adaptive phase-noise model establishes a relationship between the oscillator performance parameters (phase noise, loop gain, voltage swing, and power consumption). A concept of phase-noise tuning is used to design an adaptive oscillator.

[1] J. Ryynanen, K. Kivekas, J. Jussila, A. Parssinen, and K. Halonen, “A dual-band RF front-end for WCDMA and GSM applications,” in Proc. Custom Integrated Circuits Conf., May 2000, pp. 175–178. [2] D. Wang et al., “A fully integrated GSM/DCS/PCS Rx VCO with fast switching auto-band selection,” in Proc. Radio Wireless Conf., Aug. 2002, pp. 209–212. [3] A. Tasic´ , W. A. Serdijn, and J. R. Long, “Multi-standard/multi-band adaptive voltage-controlled oscillator,” in Proc. RF Integrated Circuits, Jun. 2004, pp. 135–138. [4] C. A. M. Boon, “Design of high-performance negative feedback oscillators,” Ph.D. dissertation, Delft Univ. Technol., Delft, The Netherlands, 1989. [5] J. J. Rael and A. Abidi, “Physical Processes of phase-noise in differential LC osillators,” in Proc. Custom Integrated Circuits Conf., May 2000, pp. 569–572. [6] E. Hegazi et al., “Filtering technique to lower oscillator phase-noise,” in Proc. Int. Solid-State Circuits Conf., Feb. 2001, pp. 364–365. [7] P. Andreani and H. Sjoland, “Tail current noise suppression in RF CMOS VCOs,” in IEEE J. Solid-State Circuits, vol. 37, Mar. 2002, pp. 342–348. [8] A. Tasic´ , W. A. Serdijn, and J. R. Long, “Resonant-inductive degeneration of voltage-controlled oscillator’s tail-current source,” in Proc. Int. Circuits Systems Symp., May 2003, pp. 673–676. [9] , “Matching of low-noise amplifiers at high frequencies,” in Proc. Int. Circuits Systems Symp., May 2003, pp. 321–324. [10] A. Tasic´ and W. A. Serdijn, “Concept of phase-noise tuning of bipolar VCOs,” in Proc. Int. Circuits Systems Symp., May 2002, pp. 161–164. [11] Digital Cellular Communication System, ETSI Standard, 1997. [12] UE Radio Transmission and Reception (FDD), 3GPP Standard, 2000. [Online]. Available: http://www3gpp.org.2000. [13] Wirelss Local Area Network, IEEE Standard 802.11b-1999, 1999. [14] Specifications of the Bluetooth System, ver. 1.1, 1999. [15] Digital European Cordless Telecommuncaitions, ETSI Standard, 1999. [16] T. S. D. Cheung et al., “Differentially-shielded monolithic inductors,” in Proc. Custom Integrated Circuits Conf., Sep. 2003, pp. 95–98. [17] J. O. Plouchart et al., “3 V SiGe differential VCO for 5 GHz and 17 GHz wireless applications,” in Proc. Eur. Solid-State Circuits Conf., 1998, pp. 332–335. [18] M. Soyuer et al., “An 11 GHz 3 V SiGe VCO with integrated resonators,” in Proc. Int. Solid-State Circuits Conf., Feb. 1997, pp. 1451–1454. [19] A. Mostafa et al., “A sub-1 V 4 GHz VCO and 10.5 GHz oscillator,” in Proc. Eur. Solid-State Circuits Conf., 2000, pp. 312–315. [20] H. Wang et al., “A 50 GHz VCO in 0.25 m CMOS,” in Proc. Int. Solid-State Circuis Conf., Feb. 2001, pp. 372–373.

Aleksandar Tasic´ received the M.Sc. (Ir. Engineer) degree in electrical engineering from the University of Nis, Nis, Serbia, in 1998, and is currently working toward the Ph.D. degree at the Delft University of Technology, Delft, The Netherlands. He was a Research Assistant with the University of Nis until 2000. He then joined the faculty of Electrotechnics, Mathematics and Informatics, Electronics Research Laboratory/Delft Institute of Microelectronics and Submicrontechnology (DIMES), Delft University of Technology. His research interest includes adaptive and MS RF front-end circuits for wireless communications with an emphasis on adaptive VCOs. His research also includes RF front-end system study, with a particular interest in the optimal distribution of specifications to RF front-end circuit blocks.

´ et al.: DESIGN OF MS ADAPTIVE VCOs TASIC

Wouter A. Serdijn was born in Zoetermeer (“Sweet Lake City”), The Netherlands, in 1966. He received the Ingenieurs (M.Sc.) and Ph.D. degrees from the Delft University of Technology, Delft, The Netherlands, in 1989 and 1994, respectively. Since 2002, he has been a Workpackage Leader on the freeband impulse project AIR-LINK, which is aimed at high-quality wireless short-distance communication employing ultra-wideband (UWB) radio. He co-edited and coauthored Research Perspectives on Dynamic Translinear and Log-Domain Circuits (Boston, MA: Kluwer, 2000), Low-Voltage Low-Power Analog Integrated Circuits (Boston, MA: Kluwer, 1995), and Dynamic Translinear and Log-Domain Circuits (Boston, MA: Kluwer, 1998). He has also authored or coauthored over 150 publications and presentations. He teaches analog electronics for electrical engineers, micropower analog IC techniques and electronic design techniques. His research interests include low-voltage, ultra-low-power, high-frequency, and dynamic-translinear analog ICs along with circuits for RF and UWB wireless communications, hearing instruments, and pacemakers. Dr. Serdijn has served as an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING, as tutorial session co-chair for the International Circuits and Systems Symposium (ISCAS’2003), as analog signal processing track co-chair, for ISCAS’2004, and as chair of the Analog Signal Processing Technical Chapter of the IEEE Circuits and Systems Society. He is currently an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS, as analog signal processing track co-chair for the International Conference on Electronic Circuits and Systems (ICECS’2004), as Technical Program Committee member for the 2004 International Workshop on Biomedical Circuits and Systems, and as analog signal processing track co-chair for ISCAS’2005.

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John R. Long received the B.Sc. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 1984, and the M.Eng. and Ph.D. degrees in electronics engineering from Carleton University, Ottawa, ON, Canada, in 1992 and 1996, respectively. For ten years he was with Bell-Northern Research, Ottawa (now Nortel Networks), where he was involved in the design of application-specific integrated circuits (ASICs) for gigabit/second fiber-optic transmission systems. For five years he was with the University of Toronto. In January 2002, he joined the faculty of the Delft University of Technology, Delft, The Netherlands, where he is currently Chair of the Electronics Research Laboratory. His current research interests include low-power transceiver circuitry for highly integrated radio applications and electronics design for high-speed data communications systems. Prof. Long currently serves on the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC), the European Solid-State Circuits Conference (ESSCIRC), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), and GAAS2004 European Microwave Symposium. He was an associate editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He was the recipient of the Natural Sciences and Engineering Research Council of Canada (NSERC) Doctoral Prize, the Douglas R. Colton and Governor General’s Medals for research excellence, and the ISSCC 2000 and IEEE BCTM 2003 Best the Paper Awards.

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An Experimental Study of Carrier Heating on Channel Noise in Deep-Submicrometer NMOSFETs Via Body Bias Hong Wang, Member, IEEE,, Rong Zeng, and Xiuping Li

Abstract—In this paper, RF noise in 0.18- m NMOSFETs concerning the contribution of carrier heating and hot carrier effect is characterized and analyzed in detail via a novel approach that modulates the channel carrier heating and number of hot carriers using body bias. We confirm qualitatively a negligible role of hot carrier effect on the channel noise in deep-submicrometer MOSFETs. For a device under reverse body bias ( ), even though the increase in hot carrier population is clearly characterized by dc measurements, the device high-frequency noise is found to be irrelevant to the increase in the channel hot carriers. Experimental results show that the high-frequency noise is , and can be qualitaslightly reduced with the increase in tively explained by secondary effects such as the suppression of nonequilibrium channel noise and substrate induced noise. The reduction of with the increase in may provide min and a possible methodology to finely adjust the device high-frequency noise performance for circuit design. Index Terms—Hot carriers, MOSFETs, semiconductor device noise.

I. INTRODUCTION

A

S THE downscaling of CMOS technology makes the CMOS transistors an important option for microwave and RF applications, the analysis and modeling of RF noise in deep-submicrometer MOSFETs have become critical issues, particularly for low-noise circuits. Significant efforts have been made in the characterization and modeling of device high-frequency noise behavior. Although it is now widely accepted that the channel thermal noise could play a dominant role in determining the overall RF noise behavior in submicrometer NMOSFETs, some controversy still remains about the physical mechanism in deep-submicrometer devices. For example, experimental observations have shown that, in short-channel devices, the measured drain current noise is much higher than the one predicted by the long-channel model. The most popular explanation and physical model for the excess channel thermal noise observed in submicrometer MOSFETs are based on the postulation of carrier heating and hot carriers [1], [2]. However, recent modeling results reported from different research groups [3], [4] do not support the above postulation. Scholten et al. [3] suggest that it is possible to predict the excess noise without Manuscript received April 21, 2004. H. Wang and R. Zeng are with the Microelectronic Centre, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). X. Li is with the School of Telecommunication Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, China. Digital Object Identifier 10.1109/TMTT.2004.840647

invoking carrier heating based on a surface-potential-based compact MOS mode with improved descriptions of carrier mobility and velocity saturation. Chen and Deen [4] demonstrated that the excess channel noise in deep-submicrometer MOSFETs could be modeled by considering the channel length modulation. Furthermore, simulation based on a nonstationary transport model [5] suggests that the source side of the channel is responsible for most of the excess noise. This obviously does not support the explanations related to carrier heating and velocity saturation where the drain side of the channel is associated with these phenomenon. Notice that all the aforementioned studies were based on complicated RF modeling, and some ambiguities could arise during the definition of device models and parameter extraction. This, in turn, influences the direct understanding of the various physical origins of RF noise in submicrometer devices. To date, direct information about the enhancement of channel noise by carrier heating remains lacking. On the other hand, recent studies on deep-submicrometer reveal that a reverse MOSFETs with reverse body bias increases the electric field of the drain–substrate junction, and induces secondary impact ionization by the enhanced heating of holes [6]–[8], and substantially increases the population of high-energy (hot) carriers. This was confirmed by Monte Carlo simulation [9] and light emission measurement [10]. The carrier heating in submicrometer NMOSFETs by reverse provides a possible means to directly verify the contribution of carrier heating to channel noise by modulating the number of high-energy electrons. The primary emphasis in this paper is to provide an experimental evaluation of the effect of carrier heating on channel noise in submicrometer NMOSFETs and answer the question as to whether carrier heating has a great impact on RF noise in deep-submicrometer MOSFETs. Furthermore, since the body (or substrate)-to-source bias has been demonstrated to provide an effective fine control of the device [11], circuit frequency and circuit performance such as [12], and low-frequency properties [13], a comprehensive analysis and understanding of the effect of body bias on the device microwave (or RF) noise behavior is important for the potential use of CMOS technology in high-frequency low-noise circuits. This paper discusses the experimental results of microwave noise in 0.18- m NMOSFETs subjected to reverse body bias and it is a significant expansion of [14]. In Section II, the detailed information on the device and experiments is given. The results for the dependence of device dc and high-frequency noise performance on body bias are provided in Section III.

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Fig. 1. Schematic representation of an NMOSFET under reverse body bias used in the experiments described in this study.

The possible physical origins of the experimental observations are discussed in Section IV. Finally, Section V summarizes the important results from those studied. II. EXPERIMENTAL The devices used for the tests were NMOSFETs fabricated using a commercial dual-gate oxide process with shallow trench isolation (STI). The gate oxide was 29- thick containing 1% nitrogen, grown via rapid thermal oxidation in an N O ambient, followed by the deposition of a 2000- -thick polysilicon gate and phosphorus pre-doping. The moderately doped source/drain extensions were then formed by low-energy arsenic implantation. After nitride spacer formation, a high-dose arsenic implantation was applied to form the N source/drain junctions and simultaneously doped the polysilicon gate. The test devices had a multiple gate layout with a drawn channel dimensions of m m. The data shown in this paper were measured from the devices with eight gate fingers. The devices used here are based on twin-well CMOS technology. Contacts to the p-Si well allow for adjustment of the body bias to vary the electric field between the channel and substrate. For a MOSFET with reverse , it is also called channel initiated secondary electron (CHISEL) injection. This is schematically depicted in Fig. 1. The CHISEL mode allows for variation of the electron energy distribution in the device with less impact on the oxide electric field (gate-to-source voltage) and other device parameters. In contrast, for the NMOSFETs under conventional bias , a higher is frequently used to increase the channel electric field and heat up the carrier. However, this may also cause a significant change in the oxide field, which, in turn, induces large variations in other device parameters. Device characterizations were carried out using a semiauto Cascade probe station. An HP4156B semiconductor parameter analyzer was used for dc measurements. Device -parameters were measured using an HP8510B network analyzer with frequency up to 50 GHz. Measurements of noise characteristics were conducted using an ATN NP5 noise and -parameter measurement systems in the frequency range of 2–14 GHz. All of the parasitic effects from probing pads and interconnections were deembedded following the approach proposed by Deen and Chen [15].

Fig. 2. Substrate (I ) and drain (I ) currents as functions of gate voltage V with different substrate voltages V as the parameter. The drain voltage V is 1.8 V.

III. EFFECT OF REVERSE BODY BIAS ON DC AND HIGH-FREQUENCY NOISE PERFORMANCE Monte Carlo simulation suggests that the electrons in shortchannel MOSFETs could be heated up by applying a negative bias to the substrate through an impact ionization feedback process [9]. It have been found that, under an increased vertical field, the additional hot electrons could be generated by the hot holes as they traverse the substrate from the point near the drain, inducing an increased hot carrier population in the device. This results in an improved programming efficient for high-speed low-power nonvolatile memories (NVMs). The carrier heating via reverse body bias can be easily probed by monitoring the change of substrate and gate currents [6]–[9] or spectroscopic photon emission measurements [10]. Since the experiment confirmed that by an increase in the reverse of an NMOSFET, the number of hot carries and their energy could be modulated, we will limit our characterization and analysis of high-frequency regime to directly assess the impact of noise in the reverse carrier heating on channel noise in NMOSFETs. A. Effect of Reverse Body Bias on DC and Microwave Characteristic and drain curFig. 2 shows the typical substrate current for different reverse values. Increasing rent versus from 0 to 1.8 V results in an approximately 30% increase of , suggesting an increase in the number of hot carrier population in the channel. The increase of threshold voltage with the increase is due to the body effect. Considering the increasingly of large , which lowers the for a given , an even larger , increase in hot carrier population, defined as the ratio of ratio versus could be expected. Fig. 3(a) plots the and to illustrate the enhancement of hot carrier population by increasing . The use of instead of alone is to exclude the body effect, which can also be similarly plotted with respect to , as illustrated in Fig. 3(b). In the later part of this paper, a similar approach will be used for plotting the noise data so that the body effect can be excluded. It can be seen from V, increasing from 0 to Fig. 3(a) that, at , suggesting 1.8 V results in a 48% increase in the ratio of

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0

Fig. 4. Saturation and linear transconductances (g ) as a function of V V with different body bias. Inset: Output conductance at zero drain source bias V with different body bias. Both g and (g ) (g ) as a function of V are insensitive to V .

0

0

Fig. 3. Plot substrate current I and ratio of I =I versus: (a) V V and (b) I to exclude the body effect. The increase in I and I =I suggests the carrier heat via negative body bias.

a drastic carrier heating in the channel. However, it is interesting to see that the impact of body bias on the other important paoutput conductance at rameters, such as transconductance , is trivial. Note that these paramzero drain source bias eters could also largely affect the device noise behavior. Fig. 4 of an NMOSFET meacompares the linear and saturation sure at different body bias, and only a negligible decrease in can be found. The slight reduction of with the increase could be explained by the increase in surface scattering in of the channel electrons since applying a negative body bias on the NMOSFET could make the channel electron move toward on the the region close to the surface. The dependence of body bias is illustrated in the inset of Fig. 4. The variation of with different body bias up to V is negligible. Furthermore, the effect of body bias on device microwave performance was also evaluated by comparing the cutoff frequency , which is shown in Fig. 5 and its inset. Again, a plot of versus drain current as a function of suggests a negligible influence of body bias on the device microwave performance. In general, the device dc and microwave characteristics such as and are insensitive to 3% negative body bias if the body effect is excluded. While in contrast, applying a nega-

Fig. 5. Cutoff frequency f versus drain current as a function body bias. The V was set to 1.8 V during the measurements. Inset: Plot the same curve in a log scale of I to illustrate the low I region.

tive body bias results in a drastic increase in the ratio of , i.e., carrier heating, as illustrated in Fig. 6. This confirms that may only have a minimal impact on oxide applying reverse field and, thus, device operation, except carrier heating. B. Effect of Reverse Body Bias on RF Noise at 2 GHz At high frequencies, channel thermal noise is the major noise source. Besides the channel thermal noise, induced gate noise, gate resistance noise, and substrate noise could also contribute to the overall noise. To emphasize the channel noise and simGHz, and plify our analysis, an intermediate frequency ( ) is chosen to minimize the influence of low-frenoise and induced gate noise, which quency noise such as is important at high frequency. The gate resistance noise, which

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Fig. 6. Comparison of the variations of I =I ; g ; g , and f with the increase in body bias. The increase in V b results in drastic increase in the ratio of I =I with negligible impact on the other parameters.

j j

is determined by the poly gate resistance, is hardly affected by body bias, and can be treated as a constant noise source for dif. Fig. 7(a) shows a typical set of minimal noise figure ferent at 2 GHz for different measured under different body biasing voltages. For low values of , the minimum noise . At certain , indecreases in value with the increase in causes the minimum noise to increase in value. crease in the This is due to the variation of for different . In the low regime, is increased with the increase in , while starts at which the minimum noise figure reaches its to saturate at causes a shift minima minima. Increase in reverse toward high . This, again, could be attributed to the shift of device turn-on due to body effect, which is confirmed by re-plotas a function of instead of itself, as ting not shown in Fig. 7(b). It is clear that an increase in reverse only causes the shift of minima, but also causes a slight decrease in value. Similar trends were observed for the noise figures when the measurements were switched to the 50- system. is dominated by device drain current thermal noise and much larger than , which ensures better noise deembedding accuracy and eliminates the possible errors induced by the is shown in noise measurements. The measurements of shows a 0.4-dB decrease when the Fig. 8. Measured body bias is changed from 0 to 1.2 V. on the The dependence of equivalent noise resistance body bias shown in Fig. 9 reveals a trend similar to those for is decreased from 148 to 131 when is noise figures. varied from 0 to 1.2 V. To a first order, if the contribution of and substrate noise is small [16], the noise parameters for the MOS devices can be written as [17], [18]

Fig. 7. Minimum noise figure NF versus gate bias: (a) V and (b) drain with the increase current I as function of body bias. A slight decrease in NF of V is measured.

j j

(1) (2) where and are parameters of the models is for channel noise and induced gate noise. Notice that

Fig. 8. Noise figure at 50- generator impedance NF as a function drain current I . Increase of V from 0 to 1.2 V results in 0.4-dB reduction of NF .

j j



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Fig. 9. Noise resistance R versus drain current I as a function body bias V .

Fig. 10. Magnitude and angle of the optimum coefficient versus drain current at 2 GHz as a function of body bias.

dominated by the channel (drain) noise current, while is related to the contributions from the channel (drain) noise current and gate-induced noise current (term under the square root). and The reduction of channel noise along could affect both and ). It is worth noting that the renoise figures ( duction of and would be beneficial to low-noise circuit design. Considering the well-known noise-figure equation pertaining to a linear noisy two-port,

may not play a dominant role in determining the excess channel noise in deep-submicrometer MOSFETs. Considering that is unaffected by , following the (2), the decrease in with the increase in (shown in Fig. 9) would suggest a slight reduction of the factor with carrier heating. This does not agree with the postulation of the increase of by hot carriers. Two possible models based on different physical mechanisms could be used to explain our experimental observation. One is the nonequilibrium noise theory proposed by Navid and Dutton [19]. It was proposed that, in deep-submicrometer MOSFETs, the channel noise should include not only the usual thermal noise component, but also a partially suppressed shot noise term associated with the limited number of inelastic scattering events in the channel. Simulation studies indicated that reducing the channel length or increasing the mean free path to reduce the number inelastic scattering events to the orders of ten could significantly enhance the contribution of this nonequilibrium noise. For an NMOSFET with gate length shorter than 0.7 m, the nonequilibrium noise could not be ignored. Applying the nonequilibrium noise theory to our experimental data, the reduction of the channel noise can be easily explained. As we increase to increase the body potential, more scattering events are expected due to the surface scattering mechanism. This causes a reduction of nonequilibrium noise components and, consequently, reduces the total channel noise. Mathematically, the drain noise can be expressed as

(3) where is the signal source admittance, smaller results in smaller . Furthermore, for a design with imperfect noise matching, i.e., is not exactly equal to ,a by applying a reverse could reduce the noise decrease in at a contributed by mismatching. The reflection coefficient , minimal noise figure, instead of the optimum admittance is often used in noise measurement as follows: (4) where the characteristic impedance . Fig. 10 shows the magnitude and angle of the optimum coefficient versus drain current at 2 GHz as a function of body bias. Both magnitude and angle of the optimum coefficient are insensitive to body bias. The weak dependence of magnitude and angle of the optimum coefficient to the body bias indicates that the variation of the device equivalent-circuit element values at different is small. IV. DISCUSSION If carrier heating plays an important role in determining channel thermal noise, applying a negative body bias to increase the hot carrier population would cause an increase in the and . However, the noise white noise -factor, thus, measurements given in Figs. 7 and 9 show otherwise. and are weakly dependent on and, in fact, slightly decrease with the increase in , indicating that carrier heating

(5) where

is the equilibrium noise term, and the coefficient is deliberately indicated in a generic form to indicate that the proportionality factor depends in a complex way on the gate, drain, and body biasing voltages. In our case, due to if more scattering events are induced by increasing surface scattering, the contribution from nonequilibrium noise could be suppressed or even vanished, which then reduces the drain noise. Note that, although a qualitative explanation can be given based on the aforementioned nonequilibrium noise model, a theoretical prediction and calculation of device noise including

WANG et al.: EXPERIMENTAL STUDY OF CARRIER HEATING ON CHANNEL NOISE IN DEEP-SUBMICROMETER NMOSFETs

Fig. 11. Bulk transconductance (g ) as a function of I for different V . Reduction of g from 4.7 to 2.9 mS when V is increased from 0 to 1.2 V.



j j

the nonequilibrium effect is difficult, unless the correlation between the coefficient and device bias can be determined. An alternative explanation can be proposed by considering the substrate noise. Although it is generally believed that substrate noise generated from the distributed substrate resistance could be considered as a second-order effect on the device overall noise [16], and the substrate resistance [20] and substrate induced noise [21] are not very sensitive to device bias conditions, ignoring the impact of the contribution from the substrate by (2) could still be oversimplified. For example, according to [22], the substrate noise will probably play a considerably important role when the gate resistance is reduced to a small value by the multiple-finger layout. The substrate noise can be qualitatively expressed as [23]

(6) where is a constant, is the space size between gate and bulk is the gatewidth, and is the bulk transconduccontact, tance, which depends on . Indeed, Fig. 11 shows a reduction from 4.7 to 2.9 mS with the increased from 0 to of 1.2 V. Due to the unknown constant , an accurate calculation of this substrate noise is difficult. However, by considering the substrate noise, following the method given in [22], a quantitais possible by modifying (2) with a factor tive estimation of as of with For the device biased in a strong inversion region, by

(7) is given

(8)

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shows a parabolic relation. The values R Fig. 12. Plotting R versus g and g were extracted from Figs. 9 and 11 at I = 7 mA for different V .

and are the gate and substrate resistances, where respectively. Substituting (7) into (8), the new expression for equivalent noise resistance becomes (9) and Therefore, if the parameters such as are independent to body bias, we would expect a parabolic bewith at different . Plotting versus in havior of Fig. 12 well follows this trend. Thus, the possibility of supprescan also qualitatively justify sion of substrate noise at high the reduction device noise. V. SUMMARY AND CONCLUSION In summary, this paper has investigated the impact of body bias on RF noise behavior in deep-submicrometer NMOSFETs to understand if carrier heating and hot carrier effect are the root causes of the excess channel thermal noise observed in short-channel MOSFETs. Using a novel approach that modulates the channel carrier heating and number of hot carriers through reverse body bias without causing significant changes of other device parameters, the postulation of enhancement of high-frequency noise in deep-submicrometer MOSFETs due to channel carrier heating is directly assessed. Even though the increase in hot carrier population in the 0.18- m NMOSFETs was confirmed by dc characteristics, the device by reverse high-frequency noise is found to be irrelevant to the increase in channel hot carriers in the explored bias conditions. Clear evidence was found, instead, that high-frequency noise , and can be qualiis slightly reduced with the increase in tatively explained by the secondary effects such as the suppression of nonequilibrium channel noise or substrate induced noise. Our experimental result does not support the postulation that invokes the enhancement of channel noise in deep-submicrometer NMOSFETs by the hot carrier effect. At least in the bias conditions for conventional operation, the contribution of carrier heating to high frequency is nevertheless too insignificant

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and could be masked by those second-order effects. This is consistent with some of the recent findings based on the extraction of RF noise models. and with We further notice that the reduction of outlined in this paper provides a possible the increase in methodology to finely adjust the device high-frequency noise performance. ACKNOWLEDGMENT The authors wish to thank Chartered Semiconductor Manufacturing, Singapore, for the supply of test devices. The authors gratefully acknowledge the critical reading of this paper’s manuscript by C. L. Tan, Temasek Laboratory, Nanyang Technological University, Singapore. REFERENCES [1] D. P. Triantis, A. N. Birbas, and D. Kondis, “Thermal noise modeling for short-channel MOSFETs,” IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1950–1955, Nov. 1996. [2] P. Klien, “An analytical thermal noise model of deep submicron MOSFETs,” IEEE Electron Device Lett., vol. 20, no. 8, pp. 399–401, Aug. 1999. [3] A. J. Scholten, H. J. Tromp, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, P. W. H. de Vreede, R. F. M. Roes, P. H. Woerlee, A. H. Montree, and D. B. M. Klaassen, “Accurate thermal noise model for deep-submicron CMOS,” in Int. Electron Devices Meeting Tech. Dig., Dec. 1999, pp. 155–158. [4] C.-H. Chen and M. J. Deen, “Channel noise modeling of deep submicron MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1484–1487, Aug. 2002. [5] J. S. Goo, C. H. Choi, F. Danneville, E. Morifuji, H. S. Momose, Z. Yu, H. Iwai, T. H. Lee, and R. W. Dutton, “An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2410–2419, Dec. 2000. [6] J. D. Bude, “Gate current by impact ionization feedback in sub-micron MOSFET technologies,” in Proc. Very Large Scale Integration Tech. Symp., 1995, pp. 101–102. [7] D. Esseni and L. Selmi, “A better understanding of substrate enhanced gate current in VLSI MOSFET’s and flash cells—Part I: Phenomenological aspects,” IEEE Trans. Electron Devices, vol. 46, no. 2, pp. 369–375, Feb. 1999. [8] L. Selmi and D. Esseni, “A better understanding of substrate enhanced gate current in VLSI MOSFET’s and flash cells—Part II: Physical analysis,” IEEE Trans. Electron Devices, vol. 46, no. 2, pp. 376–382, Feb. 1999. [9] J. D. Bude, M. R. Pinto, and R. K. Smith, “Monte Carlo simulation of the CHISEL flash memory cell,” IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1873–1881, Oct. 2000. [10] M. Pavesi, L. Selmi, M. Manfredi, E. Sangiorgi, M. Mastrapasqua, and J. D. Bude, “Evidence of substrate enhanced high-energy tails in the distribution function of deep submicron MOSFET’s by light emission measurements,” IEEE Electron Device Lett., vol. 20, no. 11, pp. 595–597, Nov. 1999. [11] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, “A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation,” in Int. Electron Devices Meeting Tech. Dig., 1994, pp. 809–812. [12] J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1396–1402, Nov. 2002. [13] M. J. Deen and O. Marinov, “Effect of forward and reverse substrate biasing on low-frequency noise in silicon PMOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 409–413, Mar. 2002.

[14] H. Wang and R. Zeng, “Experimental verification of the effect of carrier heating on channel noise in deep submicron NMOSFET’s by substrate bias,” in IEEE RF Integrated Circuits Symp., 2004, pp. ???–???. [15] M. J. Deen and C.-H. Chen, “The impact of noise parameter de-embedding on the high-frequency noise modeling of MOSFETs,” in Proc. Int. Microelectronic Test Structures Conf., 1999, pp. 34–39. [16] A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, A. T. A. Zegers-van Duijnhoven, and V. C. Venezia, “Noise modeling for RF CMOS circuit simulation,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 618–632, Mar. 2003. [17] C. Enz, “An MOS transistor model for RF IC design valid in all regions of operation,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 342–358, Jan. 2002. [18] C. Fiegna, “Analysis of gate shot noise in MOSFETs with ultrathin gate oxides,” IEEE Electron Device Lett., vol. 20, no. 2, pp. 108–110, Feb. 2003. [19] R. Navid and R. W. Dutton, “The physical phenomena responsible for excess noise in short-channel MOS devices,” in Int. Simulation of Semiconductor Processes and Devices Conf., 2002, pp. 75–78. [20] Y. Chen and M. Matloubian, “On the high-frequency characteristics of substrate resistance in RF MOSFETs,” IEEE Electron Device Lett., vol. 21, no. 12, pp. 604–606, Dec. 2000. [21] S. V. Kishore, G. Chang, G. Asmanis, C. Hu, and F. Stubbe, “Substrate-induced high-frequency noise in deep-sub-micron MOSFET’s for RF applications,” in IEEE Custom Integrated Circuits Conf., 1999, pp. 365–368. [22] C. Enz and Y. Chen, “MOSFET transistor modeling for RF IC design,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 186–201, Feb. 2000. [23] Y. Lin, M. Obrecht, and T. Manku, “RF noise characterization of MOS devices for LNA design using a physical-based quasi-3-D approach,” IEEE Trans. Circuits Syst.—II, Analog Digit. Signal Process., vol. 48, no. 10, pp. 972–984, Oct. 2001.

Hong Wang (S’99–M’01) received the B.Eng. degree from Zhejiang University, Hangzhou, China, in 1988, and the M.Eng. and Ph.D. degrees from the Nanyang Technological University (NTU), Singapore, in 1998 and 2001, respectively. From 1988 to 1994, he was with the Institute of Semiconductors, Chinese Academy of Sciences, where he developed InP-based opto-electronic integrated circuits (OEICs). From 1994 to 1995, he was a Royal Research Fellow with British Telecommunications Laboratories, Ipswich, U.K., where he was involved with the development of InP-based heterostructure field-effect transistors (HFETs) using E-beam lithography. Since 1996, he has been with the Microelectronics Centre, Nanyang Technological University, where he is currently an Assistant Professor. He has authored or coauthored over 100 technical papers related to his research. His current research interests are compound semiconductor and Si-based device physics, fabrication technology, and characterization.

Rong Zeng received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999, the M.S. degree in electrical and computer engineering from the National University of Singapore, Singapore, in 2002, and is currently working toward the Ph.D. degree at the Nanyang Technological University, Singapore. Since 2002, she has been a Research Associate with the Nanyang Technological University. Her research interests include characterization and modeling of high-frequency devices.

Xiuping Li, photograph and biography not available at time of publication.

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Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers Vladimir Aparin and Lawrence E. Larson, Fellow, IEEE

Abstract—Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum 3 in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum 3 at RF. It was used in a 0.25- m Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved 22-dBm 3 with 15.5-dB gain, 1.65-dB NF, and 9.3 [email protected] power consumption.

IIP

IIP

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Index Terms—Amplifier noise, intermodulation distortion, MOSFET amplifiers, nonlinearities, Volterra series.

I. INTRODUCTION

T

HE SINGLE-TONE desensitization requirement for code-division multiple-access (CDMA) phones demands a very high linearity of the low-noise amplifier (LNA) to reduce its cross-modulation distortion of a single-tone jammer in the presence of a transmitted signal leakage [1]. The high linearity should be achieved in combination with a low noise figure (NF), high gain, and low current consumption. The LNA linearity is usually specified as an input-referred third-order intercept . For example, a typical cellular CDMA LNA must point dBm, a nominal NF of 1.6 dB, and power gain have of 16 dB with the power consumption less than 30 mW. This design challenge requires the use of linearization techniques. As was shown in [2], the linearity of an Si bipolar junction transistor (BJT) or an SiGe HBT can be reliably improved using a simple technique based on low-frequency low-impedance base termination without degrading gain or NF. However, this technique is not effective for linearizing field-effect transistor (FET) amplifiers. In [3], feed-forward distortion cancellation was proof a CMOS LNA. This techposed to achieve a very high nique relies on accurate scaling between the input signals of the main and auxiliary gain stages and their transfer functions. The results demonstrated in [3] were measured using a coaxial assembly to split and attenuate the input signal for the main and auxiliary gain stages; thus, the feasibility of this approach for practical applications is questionable. An FET can also be linearized by biasing at a gate–source at which the third-order derivative of its dc voltage Manuscript received April 21, 2004; revised September 17, 2004. V. Aparin is with Qualcomm Inc., San Diego, CA 92121 USA (e-mail: [email protected]). L. E. Larson is with the Center for Wireless Communications, University of California at San Diego, La Jolla, CA 92093-0407 USA. Digital Object Identifier 10.1109/TMTT.2004.840635

peaks transfer characteristic is zero [4]–[7]. The resulting making this technique sensitive in a very narrow range of sensitivity to the bias, to bias variations. To reduce the the derivative superposition (DS) method was proposed in [8]. It uses two or more parallel FETs of different widths and gate biases to achieve a composite dc transfer characteristic with an range in which the third-order derivative is close extended to zero. However, the improvement in this method is only modest at RF (3 dB, as reported in [9]). Reducing the source degeneration inductance and drain load impedance at the second harmonic frequency of the composite input transistor allowed in the DS method by as much the authors of [10] to boost as 10 dB. However, a small degeneration inductance prevents a simultaneous noise-power input match leading to a higher NF. This NF increase comes in addition to an intrinsically higher NF of a composite FET in comparison with a single FET (higher by 0.6 dB, as reported in [10]). This NF increase due to replacing a single FET by a composite FET in the DS method is not predicted by simulations using BSIM3v3 models. performance of the convenHere, we explain the poor tional DS method at RF based on the Volterra-series analysis. We also explain the higher NF resulting from the use of this method. We propose a modified DS method to achieve a very at RF. Its principle of operation is explained based on high the Volterra-series analysis. A cellular CDMA 0.25- m CMOS LNA using this method is described. The measured data is presented to confirm the analytical results. II. DC THEORY OF DS METHOD Consider a common-source FET biased in saturation. Its small-signal output current can be expanded into the following power series in terms of the small-signal gate–source voltage around the bias point (1) is the small-signal transconductance and the higher where etc.) define the strengths of the correorder coefficients ( sponding nonlinearities. Among these coefficients, is particularly important because it controls the third-order intermodulaat low signal levels and, thus, determines tion distortion . The input tone amplitude at the intercept point is given by [16] (2) The power series coefficients generally depend on the dc and . However, gate–source and drain–source voltages

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Fig. 2. Small-signal nonlinear equivalent circuit of the composite FET in Fig. 1(a).

III. RF THEORY OF DS METHOD

Fig. 1. DS method. (a) Composite FET. (b) Third-order power series coefficients. (c) Theoretical A at dc and IIP at 880 MHz. Note that the bondwire inductance reduces the improvement in IIP at the optimum gate biases at high frequencies.

the dependence on for an FET in saturation can be neglected. The coefficients of (1) can then be found as

(3)

The dependence of on is such that changes from transitions from the weak and positive to negative when moderate inversion regions to the strong inversion (SI) region curvature of one FET [7]. If a positive with a certain with a similar, but mirror-image is aligned with a negative curvature of another FET by offsetting their gate biases, and the magnitudes are equalized through a relative FET scaling, the resulting composite will be close to zero and the theoretical will be significantly improved in a wide range of the gate biases, as shown in Fig. 1. At the optimum gate biases, FET operates in the weak inversion (WI) region near the peak in its positive and FET operates in the SI region near the dip improvement due to zero in its negative . The achieved composite happens only at very low frequencies at which the effect of circuit reactances is negligible.

Consider a small-signal nonlinear equivalent circuit shown in in Fig. 1(a). The signal Fig. 2 for a composite FET generator is modeled by a Thevenin equivalent circuit with an open-circuit voltage and a transformed output impedance . is the source degeneration inductance. Here, we made the following assumptions. . 1) The body effect is negligible i.e., . 2) All capacitances are zero, except for the composite is bias independent, i.e., linear. 3) The composite 4) The FET gate and source series resistances and the dc resistance of the degeneration inductor are zero. 5) The FET output conductance is infinite, i.e., there is no channel length modulation. nonlin6) The input signal is very weak such that the earities of the order higher than three are negligible. This assumption is typical for LNAs because they operate far below their 1-dB compression point. In this weakly nonlinear case with the neglected would be generated entirely by the component of the drain current if was zero. The source degeneration inductance cre. This feedback ates a feedback path for the drain current to is particularly strong for high-frequency spectral components of . For example, the second harmonics and generated are fed back across the gate and source adding to the by fundamental components of . These spectral components are then mixed in to produce the responses at and . Thus, the second-order nonlinearity of also con. tributes to is much smaller than and Assuming that such that and the signal generator is conjugately , we can derive matched to the FET input at [7]: the following expression for (4) where (5)

As can be seen from (4) and (5), making the composite zero does not result in an infinite as it does at low frequencies due to the second term in (5). This term represents the contri. As expected, bution of the second-order nonlinearity to this contribution depends on the degeneration inductance .

APARIN AND LARSON: MODIFIED DS METHOD FOR LINEARIZING FET LNAs

Fig. 1(c) shows calculated at 880 MHz using (4) and (5) for the composite FET in Fig. 1(a) with an input matching circuit consisting of a series capacitor and shunt inductor. As can be seen, the source degeneration inductance significantly suppeaking at where is presses the high-frequency close to zero. In fact, for realistic values of , which are limnH), the conventional ited by the downbond inductance ( DS method provides no improvement at all. Replacing a common-source configuration with a symmetrically driven differential pair does not eliminate the second-order because the second harmonic currents contribution to generated by the FET pair are in-phase and create a commonmode voltage at the common source if the impedance from this node to ground is not zero at the second harmonic frequency. As a result, the gate–source voltages of both FETs contain nonzero second harmonic responses, which are mixed with the differential fundamental responses by the second-order nonlinearities of responses in the drain the FETs producing the differential currents. According to (5), to minimize the second-order contribution of a common-source FET with a nonzero source-deto must be increased. However, generation inductance, then becomes sigthe feedback through the neglected nificant, which also leads to the second-order contribution to . To completely eliminate this contribution and achieve improvement in the DS method, the gate a significant and drain terminations of the composite FET at the second harmonic frequency must be optimized. Our analysis shows that one of these terminations must have a negative real part, which would result in potential instability of the amplifier. improvement The authors of [10] achieved a noticeable using the conventional DS method by simply minimizing the source degeneration inductance and the drain load impedance. However, with a very small , it is difficult to simultaneously achieve a good voltage standing-wave ratio (VSWR) and NF. The gain and NF of the LNA in [10] are only 10 and 2.85 dB, respectively, at 900 MHz.

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Fig. 3. Schematic of the DS method with major noise sources. The dc blocking capacitors and the bias resistors are neglected for simplicity.

where (8) where is the Boltzmann’s constant, is the absolute temand are the bias-dependent noise coefficients, perature, is the drain–source conductance at zero is the is the channel width, gate–oxide capacitance per unit area, is the channel length assumed to be the same for both and FETs. The subscript in the above notations denotes either or . The two noise currents are partially correlated, with a correlation coefficient defined as (9) For simplicity, we will neglect the short-channel effects here. According to van der Ziel [11] if is a saturated long-channel , and FET biased in SI, (10) where is the electron mobility and is the drain satura. The van der Ziel noise model can also be tion current of extended for an FET in WI. As shown in Appendix A, if is a saturated long-channel FET biased in WI, , and

IV. NOISE ISSUES IN DS METHOD The DS method in general uses two FETs one of which is biin Fig. 1(a)] and the other in the SI ased in the WI region [ region [ in Fig. 1(a)]. Intuitively, the overall NF of the composite FET should be dominated by the FET in SI since it draws 20–40 times more current than the FET in WI. This assumption is confirmed by simulations using BSIM3v3 models. However, it disagrees with our measured data. The most significant MOSFET noise sources at RF are the drain current noise and the induced gate noise. These noise sources for the composite FET in the DS method are shown in Fig. 3, where the dc blocking capacitors and the bias resistors are neglected for simplicity. As can be seen, the drain and induced gate noise currents of the two FETs appear in parallel. These noise currents are given by [11]

(11) where is the drain saturation current of and is the . Substituting (11) into (8) and the latter thermal voltage into (7), we can make an interesting observation. While draws a negligible drain current, its induced gate noise is inversely proportional to the drain current and, thus, can be quite , designificant. It adds to the induced gate noise current of grading the overall NF in the DS method. Simulations using BSIM3v3 models do not predict this NF degradation because they do not take into account the induced gate noise. To quantitatively estimate the NF degradation in the DS , we will reuse the result method due to the WI operation of for the minimum noise factor of a common-source amplifier without degeneration from [14], but we will rewrite it in a more general way as follows:

(6) (7)

(12)

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Fig. 5.

Modified DS method.

Fig. 6.

Simplified equivalent circuit of the composite FET in Fig. 5.

Fig. 4. Theoretical F of the circuit in Fig. 1(a) with L = 0 versus the gate bias of M . The gate bias of M is kept constant.

We will neglect the drain noise current of . We can then write that

due to the fact (13a) (13b) (13c)

The induced gate noise of increases the portion of the total induced gate noise current that is uncorrelated to . This uncorrelated portion is given by

(14) From the last equation, we get (15) Substituting (15) and (13) into (12), we get

(16) of the circuit in Fig. 1(a) with comThe plot of is shown in Fig. 4 puted using (16) versus the gate bias of is kept constant). As can be seen, (the gate bias of rapidly increases with falling below the threshold voltage (in this process, 0.58 V) due to the increasing contribution of the . It should be noted that (16) was deinduced gate noise of rived using the van der Ziel’s first-order approximation of the induced gate noise and, therefore, it may correctly show the trend versus gate bias, but it may not be accurate for preof [15]. dicting the absolute values of V. MODIFIED DS METHOD For the DS method to significantly boost at RF, it is not necessary to completely eliminate the second-order contribution . It is enough to make it the same magnitude and oppoto site phase with the third-order contribution. Instead of optimally scaling and rotating the second-order contribution by tuning the second harmonic terminations of the composite FET, here we propose a method shown in Fig. 5, which is similar to the conventional DS method, but uses two source-degeneration induc-

tors in series. The FET sources are connected to different nodes of the inductor chain to adjust the magnitude and phase of the is biased in WI with a composite third-order contribution. and is biased in SI with a negative . It can positive and to the overall rebe shown that the contributions of sponse are negligible. The purpose of connecting the source to the common node of the two inductors is to change the magcontribution to relative to the nitude and phase of its and contributions of . To explain how the composite FET in Fig. 5 achieves high at RF, we will analyze its simplified equivalent circuit shown in Fig. 6, where the signal generator is modeled by a Thevenin equivalent circuit with an open-circuit voltage and as before, and are a transformed output impedance and , respectively, the gate–source capacitances of and are the small-signal gate–source voltages of and , respectively, and and are the small-signal drain curand , respectively. Here, we used the same asrents of sumptions as those made for the equivalent circuit in Fig. 2. To simplify derivations further, we also neglected the linear and , i.e., assumed that and second-order responses of . The combined output current can be represented as the following truncated Volterra series in terms of the excitation voltage in the time domain:

(17) where is the Laplace transform of the th-order Volterra kernel, also often called the th-order nonlinear transfer function, is the Laplace variable, and the operator “ ” means that the magnitude and phase of each is to be changed by the magnitude spectral component of

APARIN AND LARSON: MODIFIED DS METHOD FOR LINEARIZING FET LNAs

and phase of component is

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where the frequency of the . For a two-tone excitation (18)

the input tone amplitude at the intercept point of the with the fundamental response at sponse at by [16]

reis given

(19) as the available power of the signal generator We will treat at the third-order intercept point. It is given by [17]

Fig. 7. Vector diagram for the IMD components. (a) Conventional DS method. (b) Modified DS method.

(20) To find the transfer functions of (17), we will use the harmonic input method [17]. This method is based on probing the circuit with a multitone excitation and solving the Kirchhoff’s law equations in the frequency domain at the sum of all input frequencies. The number of incommensurable frequencies in is equal to the order of the nonlinear transfer function to be found. The procedure starts with a single-tone excitation to determine the linear transfer function and is continued to higher order functions by adding one more input tone at each step. and for a narrow The derivations of tone separation, the conjugate input match at the fundamental frequency, and a low-impedance input termination at the second harmonic frequency are shown in Appendix B. Substituting (47a) and (65) into (20) and taking into account (66), we get (21) where

(22)

. The above expression does not show and dependence on the intermodulation frequency (i.e., versus ) because the contribution of the differencefrequency mixing terms to is negligible at small due to the absence of a dc source resistance in the analyzed circuit (see Fig. 6). Parameter shows how different nonlinearities of the circuit in Fig. 6 contribute to . The first two terms in (22) represent the contributions of the third-order nonlinearities of and , respectively, and the last term represents the contribu. The phase of the tion of the second-order nonlinearity of

Fig. 8. Theoretical IIP at 880 MHz of the circuit in Fig. 5 (W = 240 m, W = 460 m, L = 0:83 nH, L = 0:61 nH, V = 0:2 V).

composite third-order contribution of and is dependent on . If were zero, the imaginary part of the first term in (22) would be zero and the vector of the composite third-order contribution described by the first two terms could never be made collinear with the vector of the second-order contribution described by the last term since the latter has a nonzero imaginary part. Therefore, the distortion cancellation would not be possible, as in the case of the conventional DS method. Graphically, this is explained by the vector diagram in Fig. 7(a). portion The idea of the modified DS method is to use the of the total degeneration inductance to rotate the phase of the contribution to relative to that of the contribution such that their sum is out-of-phase with the second-order contribution. Graphically, this is explained by the vector diato be zero, both the real gram in Fig. 7(b). In order for and imaginary parts of must be zero. The equations and can be solved for and . Using the FET sizes and bias offset from Fig. 1(a) as an example, the solutions V are nH and nH. The at plot of at 880 MHz computed using (21) versus is shown in Fig. 8. As can be seen, with the total degeneration inimprovement is achieved ductance of 1.44 nH, a significant at optimum gate biases in comparison with the conventional DS method used at the same frequency [see Fig. 1(c)]. The fact that the proposed modified DS method does not require the degeneration inductance to be minimized as in [10] makes the simultaneous noise-power match possible.

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Fig. 10. Fig. 9.

Measured CMOS LNA two-tone transfer characteristics.

Simplified schematic diagram of LNA using modified DS method.

VI. LNA DESIGN AND MEASURED RESULTS The proposed modified DS method was used in the cellular-band CDMA LNA whose schematic is shown in Fig. 9. Instead of two degeneration inductors in series, the LNA uses a single tapped inductor to save the die area. The input FETs and are interdigitated for better mutual matching and to reduce their combined drain–bulk capacitance and, thus, . FET is the noise contribution of the cascode FET is biased in SI. Their gate bias biased in WI and FET and voltages are generated by the diode-connected FETs , respectively, whose drain currents and are independently programmable. We used the current-derived bias variations from part to part than because it results in less bias circuit was used a voltage-derived bias. A constantvariations over temperature. to minimize the gain and The ratios and were optimized using a commercial circuit simulator. Due for the highest and , the evaluated values of to the interdigitation of were limited to ratios of small integers, i.e., 1/1, 2/1, 3/2, etc. The evaluated values of were also limited to the ratios of integers whose sum was kept constant (equal to 40) to ensure a constant total dc current. At each optimization step, the total degeneration inductance was adjusted to keep the LNA gain constant. We found that the optimum ratios were and with of 2.7 nH including the the total degeneration inductance bondwire. The LNA was manufactured in a 0.25- m Si CMOS technology as part of a cellular-band CDMA zero-IF receiver and packaged in a 32-pin quad flat no-lead (QFN) package. Its measured power gain and NF are 15.5 and 1.65 dB, respectively, with the current consumption of 9.3 mA from 2.6 V excluding the bias circuit. The input and output return losses are lower than 11 dB. The LNA was tested with two tones at 880 and 880.5 MHz and was found to be insensitive to the tone separation. The measured output powers of the fundamental and responses as functions of the input power per tone are plotted in Fig. 10. In the single-tone desensitization scenario of an IS-98 mobile receiver, the combined power of the single-tone jammer and the transmitted signal leakage can be as high as 27 dBm. Therefore, it is important that the LNA exhibits a high linearity below this input power. As can be seen from Fig. 10, below

0

Fig. 11. Measured IIP at P = 30 dBm as a function of the combined dc is kept constant. current of the input FETs. The ratio I =I

of 25 dBm per tone, the curve rises with a dBm. At higher input power levels, slope 3 : 1 and is domithe slope is steeper than 3 : 1 indicating that nated by the fifth-order and higher odd-order nonlinearities. If the third-order nonlinearity was completely cancelled, the slope would be meaningless. In this 3 : 1 would not exist and case, the fifth-order or higher order intercept points could be used to estimate the distortion levels at particular input power for different values of the master levels. We also measured kept constant. Fig. 11 reference current with the ratio in a wide range of shows that the LNA maintains high the dc current through the composite FET. The achieved was found to be insensitive to the input and output harmonic terminations. on the LNA To investigate the effect of the gate bias of performance, we measured the LNA , gain, NF, and dc curwith kept constant. The results rent as functions of is are presented in Fig. 12. As can be seen, the peak in V. As predicted fairly broad and centered around by the theory, reducing increases the LNA NF due to the . The rate at which increasing induced gate noise current of is much lower than the NF increases with the dropping the theoretical one shown in Fig. 4 indicating the deficiency of the van der Ziel’s first-order approximation of the induced gate noise at subthreshold biases (see also [15]). We also manufactured an LNA with a single-input FET. It , and 1.4-dB NF with 9-mA achieved 16-dB gain, 2-dBm dc current. Thus, the proposed modified DS method boosted by approximately 20 dB, but degraded the NF by 0.25 dB in due to the induced gate noise of the FET biased in WI ( Fig. 9).

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reason why the composite FET in the DS method exhibits a higher NF than a single FET. Our analysis showed that the FET biased in the subthreshold region is responsible for this NF degradation due to its high induced gate noise, which is inversely proportional to the drain current. We found that the van der Ziel noise theory overestimates this NF degradation, which indicates the deficiency of its first-order approximation of the induced gate noise at subthreshold biases. APPENDIX A Fig. 12. Measured IIP , gain, NF, and combined dc current versus the gate 0:75 V). bias voltage of M . The gate bias of M is kept constant (V



TABLE I COMPARISON OF STATE-OF-THE-ART LINEAR FET LNAS

Here, we derive the drain and induced gate noise coefficients for a saturated long-channel MOSFET biased in WI ( in Fig. 3) following the approach outlined by van der Ziel in [11]. For simplicity, we omit the letter in the subscripts of notations here. To find the drain noise current, we will start with an expression for the drain current caused by the noise voltage across the channel section between and [11] as follows: (24) is the channel conductance per unit length at , where is the dc potential at . In the WI region, the drain and current mechanism is due to diffusion. According to [12], (25)

To compare the designed high-linearity CMOS LNA with other state-of-the-art FET LNAs, we will use the dynamic-range figure-of-merit (FOM) defined as [18] (23)

where is the channel conductance per unit length at the source and is the thermal voltage . terminal is given by The mean-square value of (26) where

where point

is the output referred third-order intercept Power Gain is the noise factor , and is the dc power consumption. Table I summarizes the performances of our and other state-of-the-art FET LNAs. As can be seen, our LNA using the modified DS method has the highest FOM. To our knowledge, this FOM is also the highest among LNAs using bipolar transistors.

(27) The total drain noise current can be found as follows:

(28) VII. CONCLUSION We have shown that the conventional DS method does not improvement at RF due to the provide a significant contribution of the second-order nonlinearity to . In general, the vector of this contribution is not collinear with the vector of the third-order contribution and, therefore, they cannot cancel each other. To give these contributions opposite phases, we proposed a modified DS method that uses two inductors in series (or a tapped inductor) for source degeneration of the of the designed composite FET. This method boosted CMOS LNA by 20 dB. This LNA has the highest dynamic range FOM among known FET LNAs. We also explained the

is the dc drain potential (the source is assumed where grounded). The last equation was first derived by Klaassen and Prins [13]. Substituting (25) into (28) and simplifying the result , we get for (29) We also know that (30)

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Substituting (25) into (30), we get

Taking into account (34), we can write (31)

For

, the above expression simplifies to (32)

Solving for

(41) A comparison of (41) with (7) yields To find the correlation coefficient between need the following cross-correlation:

. and

, we

(42)

in (32) and substituting it to (29), we get (33)

Substituting (39) and (24) into (42) and taking into account (27), we get

(34)

(43)

Using (31) and (32), we can also find

Finally, the correlation coefficient

and, thus, (35)

(44)

. A comparison of (35) with (6) yields In the first-order approximation, the gate current caused by is given by [11] the noise voltage APPENDIX B

(36) We know that [11] (37)

Here, the first- and third-order coefficients of the Volterra series (17) are derived using the harmonic input method. First, we will establish the relationship between the combined and . From output current and the gate–source voltages Fig. 6, (45a) (45b) (45c)

and, therefore, (38)

The gate–source voltages can be modeled by the following truncated Volterra series in terms of the excitation voltage :

Substituting (37), (38), and (25) into (36) and simplifying the , we get result for

(46a)

(39)

(46b) Substituting (46) into (45c) and comparing the resulting expression with (17), we can write

The total induced gate noise current is

(47a)

(40)

(47b)

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where the bar indicates the symmetrization (averaging) of the corresponding transfer function over all possible permutations of the Laplace variables, i.e.,

(45a), (45b), and (46a) and (46b) into (49a) and (49b), equating on both sides of (49a)–(49g) and the coefficients of , we get solving for

(47c)

(52)

and , we first need to find and . The Kirchhoff’s current law equations for each node of the circuit in Fig. 6 are

Therefore, to find

Similarly, using a three-tone excitation, we can derive

(48a) (48b) (48c) Solving these equations for and solutions into

and

and substituting the , we get

(53) at is For the input excitation given by (18), and . Assuming closely found by setting , we can simplify (53) and spaced frequencies, i.e., (47c) as follows:

(49a) (49b) where

(54) (49c) (55)

(49d) (49e) (49f)

Substituting (52) into (55), we get

(49g) Equation (49a)–(49c) is the starting point for derivations of the transfer functions of (46a) and (46b). The idea of the harmonic input method is that these equations must hold separately for the first-order (i.e., linear) terms, as well as the second- and third-order intermodulation products. To find the linear transfer and , we will excite the circuit with a functions . Substituting (45a), (45b), and (46a) and single tone on (46b) into (49a) and (49b), equating the coefficients of and , we both sides of (49a)–(49g), and solving for get (50a)

(56) where lows that to

. From the assumption that , it foland . Equation (56) then simplifies

(57) Substituting (57) and (50a) into (54), we get

(50b) where (51) To find the second-order transfer function excite the circuit with two tones

, we will . Substituting

(58)

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Substituting (58), (57), and (50a) into (47b), we get

where

(65b)

(59)

For needed:

derivations, the following quantity will also be

To simplify (59), we will consider the case of the conjugately matched input at the fundamental frequency, i.e., (66) (60) where

is the input impedance of the circuit given by

REFERENCES [1] W. Y. Ali-Ahmad, “RF system issues related to CDMA receiver specifications,” R. F. Des., pp. 22–32, Sep. 1999. [2] V. Aparin and L. E. Larson, “Linearization of monolithic LNA’s using low-frequency low-impedance input termination,” in Eur. Solid-State Circuits Conf., Sep. 2003, pp. 137–140. [3] Y. Ding and R. Harjani, “A 18 dBm IIP3 LNA in 0.35 m CMOS,” in IEEE Int. Solid-State Circuits Conf., 2001, pp. 162–163. [4] J. C. Pedro and J. Perez, “Design techniques for low in-band intermodulation distortion amplifiers,” Microwave J., pp. 94–104, May 1994. [5] G. Qu and A. E. Parker, “Analysis of intermodulation nulling in HEMT’s,” in Optoelectronics and Microelectronic Materials and Devices Conf., Dec. 1996, pp. 227–230. [6] B. Toole, C. Plett, and M. Cloutier, “RF circuit implications of moderate inversion enhanced linear region in MOSFETs,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 51, no. 2, pp. 319–328, Feb. 2004. [7] V. Aparin, G. Brown, and L. E. Larson, “Linearization of CMOS LNA’s via optimum gate biasing,” in IEEE Int. Circuits Systems Symp., vol. IV, May 2004, pp. 748–751. [8] D. R. Webster, D. G. Haigh, J. B. Scott, and A. E. Parker, “Derivative superposition—A linearization technique for ultra broadband systems,” IEE Wideband Circuits, Modeling, Technology Colloq., pp. 3/1–3/14, May 1996. [9] B. Kim, J.-S. Ko, and K. Lee, “A new linearization technique for MOSFET RF amplifier using multiple gated transistors,” IEEE Microw. Guided Wave Lett., vol. 10, no. 9, pp. 371–373, Sep. 2000. [10] T. W. Kim, B. Kim, and K. Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223–229, Jan. 2004. [11] A. van der Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986. [12] R. J. van Overstraeten, G. J. deClerck, and P. A. Muls, “Theory of the MOS transistor in weak inversion—New method to determine the number of surface states,” IEEE Trans. Electron Devices, vol. ED-22, p. 282, 1975. [13] F. M. Klaassen and J. Prins, “Thermal noise of MOS transistors,” Philips Res. Rep., vol. 22, pp. 505–514, 1967. [14] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge, U.K.: Cambridge Univ. Press, 1998, ch. 11. [15] K.-H. To, Y.-B. Park, T. Rainer, W. Brown, and M. W. Huang, “High frequency noise characteristics of RF MOSFET’s in subthreshold region,” in IEEE RF Integrated Circuits Symp. Dig., Jun. 2003, pp. 163–167. [16] T. T. Ha, Solid-State Microwave Amplifier Design. New York: Wiley, 1981, ch. 6. [17] D. D. Weiner and J. F. Spina, Sinusoidal Analysis and Modeling of Weakly Nonlinear Circuits. New York: Van Nostrand, 1980. [18] D. C. Ahlgren, N. King, G. Freeman, R. Groves, and S. Subbanna, “SiGe BiCMOS technology for RF device and design applications,” in Proc. IEEE Radio Wireless Conf., 1999, pp. 281–284. [19] S. Ock, K. Han, J.-R. Lee, and B. Kim, “A modified cascode type low noise amplifier using dual common source transistors,” in IEEE MTT-S Int. Microwave Symp. Dig., 2002, pp. 1423–1426. [20] Y.-S. Youn, J.-H. Chang, K.-J. Koh, Y.-J. Lee, and H.-K. Yu, “A 2 GHz 16 dBm IIP3 low noise amplifier in 0.25 m CMOS technology,” presented at the IEEE Int. Solid-State Circuits Conf., 2003, Paper 25.7.

+

(61) In this case, (62) We will further assume that (63a) (63b) (63c) (63d) where . The last two assumptions call for a relatively low impedance presented to the composite FET gate at the second harmonic frequency. They are not necessary for the proposed modified DS method to work and are only used here to simplify expressions for demonstration purposes. Using (63), we can write (64a)

(64b) (64c)

Substituting (62) and (64) into (59), we get (65a)

APARIN AND LARSON: MODIFIED DS METHOD FOR LINEARIZING FET LNAs

Vladimir Aparin received the Diploma of Engineer-Physicist degree (with honors) in electronics and automatics from the Moscow Institute of Electronic Engineering (MIEE), Moscow, Russia, in 1989, and is currently working toward the Ph.D. degree in electrical engineering at the University of California at San Diego, La Jolla. From 1987 to 1992, he was involved in the design and testing of high-speed analog and digital GaAs integrated circuits (ICs) in the device modeling and characterization at the MIEE. From 1992 to 1996, he was with the Hittite Microwave Corporation, where he designed GaAs and Si BiCMOS RF integrated circuits (RFICs) for communication systems. Since 1996, he has been with Qualcomm Inc., San Diego, CA, where he designs RFIC products for CDMA systems. He has authored or coauthored numerous technical papers. He holds nine patents.

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Lawrence E. Larson (S’82–M’86–SM’90–F’00) received the B.S. and M.Eng. degrees in electrical engineering from Cornell University, Ithaca, NY, in 1979 and 1980, respectively, and the Ph.D. degree in electrical engineering and MBA degree from the University of California at Los Angeles (UCLA), in 1986 and 1996, respectively. From 1980 to 1996, he was with Hughes Research Laboratories, Malibu, CA, where he directed the development of high-frequency microelectronics in GaAs, InP, and Si–SiGe and microelectromechanical system (MEMS) technologies. In 1996, he joined the faculty of the University of California at San Diego (UCSD), La Jolla, where he is currently the Inaugural Holder of the Communications Industry Chair. He is currently Director of the UCSD Center for Wireless Communications. During the 2000–2001 academic year, he was on leave with IBM Research, San Diego, CA, where he directed the development of RF integrated circuits (RFICs) for third-generation (3G) applications. He has authored or coauthored over 200 papers and has coauthored three books. He holds 27 U.S. patents. Dr. Larson was the recipient of the 1995 Hughes Electronics Sector Patent Award for his work on RF MEMS technology. He was corecipient of the 1996 Lawrence A. Hyland Patent Award of Hughes Electronics for his work on low-noise millimeter-wave high electron-mobility transistors (HEMTs), and the 1999 IBM Microelectronics Excellence Award for his work in Si–SiGe HBT technology.

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Decreasing-Size Distributed ESD Protection Scheme for Broad-Band RF Circuits Ming-Dou Ker, Senior Member, IEEE, and Bing-Jye Kuo, Student Member, IEEE

Abstract—The capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broad-band RF circuits due to impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the ESD performance. A new distributed ESD protection structure is proposed to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, called as decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme, which is beneficial to the ESD level. The new proposed DS-DESD protection scheme with a total capacitance of 200 fF from the ESD diodes has been successfully verified in a 0.25- m CMOS process to sustain a human-body-model ESD level of greater than 8 kV. Index Terms—Coplanar waveguide (CPW), distributed electrostatic discharge (DESD) protection, electrostatic discharge (ESD), resistive ladder, shallow-trench isolation (STI) diode.

I. INTRODUCTION

E

LECTROSTATIC DISCHARGE (ESD) is one of the most serious reliability issues to integrated circuit (IC) products. With the continuous scaling of process technology and rapid increase in circuit operating frequency, providing effective ESD protection to protect the ICs has become a challenge [1]. The main consideration on ESD protection design in wireless (RF) and high-speed (broad-band) applications is to achieve high ESD robustness, but not to affect the normal circuit performance. Therefore, the ESD protection devices in RF circuits are often designed with small device size to reduce its parasitic capacitance [2]–[4] and placed close to the I/O pins. However, with the continuous increase of circuit operation in broad-band frequencies, the traditional ESD protection design has met its limitation due to severe impedance mismatch caused by the parasitic capacitance of the ESD protection device. To improve the impedance match for broad-band RF circuits, a distributed ESD protection scheme, which employs line segments between ESD protection devices, had been reported [5]–[8], as shown in Fig. 1. Such a distributed ESD protection scheme has achieved either good ESD protection or good broad-band RF Manuscript received April 21, 2004; revised August 12, 2004. This work was supported by the National Science Council, Taiwan, R.O.C., under Contract NSC 93-2215-E-009-014. M.-D. Ker is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan 300, R.O.C. (e-mail: [email protected]). B.-J. Kuo is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan 300, R.O.C. and also with MediaTek Inc., Hsinchu, Taiwan 300, R.O.C. Digital Object Identifier 10.1109/TMTT.2004.840733

Fig. 1. Traditional distributed ESD protection design with equal-size diodes in four ESD stages [6]–[8].

performance, but not both [5]–[8]. In [5], the ESD protection devices of gate-grounded NMOS devices were designed with series -well resistors in the drains of NMOS, which was beneficial for uniform turn-on during ESD events to achieve a high ESD level. However, due to the large thermal noise contributed from the -well resistors, it could not be suitable in the RF low-noise amplifier (LNA). In [6]–[8], a four-stage distributed ESD protection design by using ESD devices (p diodes and n diodes) of equal size was reported to achieve a good impedance match over a broad-band frequency range, but the ESD performance of such a design was never verified in the silicon chip. In this paper, a new distributed ESD protection scheme with a decreasing-size ESD structure is proposed to achieve both excellent RF performance and ESD robustness. The new decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme has been verified in a 0.25- m CMOS process to sustain a human-body-model (HBM) ESD level of greater than 8 kV [9]. II. NEW DISTRIBUTED ESD PROTECTION SCHEME A. Concept of the New Distributed ESD Design To sustain the desired ESD robustness, the traditional ESD protection devices should be drawn with large enough device size and placed near the signal pins, as shown in Fig. 2. However, for broad-band RF performance, the protection devices are preferred to be divided into numerous small units with the same device size and separated by transmission lines (T lines), coplanar waveguides (CPWs), or inductors, as that shown in Fig. 1. The dilemma can be overcome by the new proposed ESD protection scheme, as that illustrated in Fig. 3. The proposed ESD protection structure allocates the ESD protection devices with decreasing size from the signal pin to the core circuit, which is called as the DS-DESD protection scheme.

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TABLE I FORM THE CHARACTERISTIC IMPEDANCES OF THE CPWG IN A 0.25-m CMOS PROCESS

PARAMETERS

TO

Fig. 2. Traditional ESD protection design with large ESD devices close to the signal pin to achieve a high ESD level.

Fig. 3. New proposed DS-DESD protection scheme for broad-band RF circuits.

+

+

Fig. 5. Layout top views of: (a) the n /p-well diode and (b) the p /n-well diode, realized in a 0.25-m CMOS process. One pair of these diodes contributes a parasitic capacitance of 25 fF.

with large spacings yield high characteristic impedances. In this study, narrow signal lines were preferred to make it obvious that the difference of the ESD protection levels between the traditional equal-size distributed electrostatic discharge (ES-DESD) protection scheme and the new proposed DS-DESD protection scheme. However, due to the narrower signal line, the series resistor of the CPWG increased, which is adverse in RF power transfer and the ESD current conduction. The CPWG with of 70 was finally chosen to compromise this conflict. C. Diode Design Fig. 4.

Structure of CPWG realized in a CMOS process.

B. CPW With Ground Shield (CPWG) In the distributed ESD protection design, the T lines have been often used to compensate the effect of the parasitic capacitances generated from the ESD protection devices. Here, the CPWG are used as T lines with the well-controlled characteristic impedance ( ) and the low substrate loss [10], [11]. The structure of the CPWG is shown in Fig. 4. The thick top-layer metal is used as the signal line of the CPWG, and metal 1 (the lowest metal layer) is employed as the ground shield. Due to the limitation of the given 0.25- m CMOS process, the thickness of the top-layer metal is only 1.5 m and the height between the top-layer metal and metal 1 is 5.71 m. The permittivity of the silicon dioxide is 4.1 and that of the substrate is approximately 11.7. The required spacing between the signal line and coplanar ground, as well as the width of the top-layer metal (signal line) to achieve various characteristic impedances, have been calculated and listed in Table I. Narrow widths of the signal line

The ESD protection devices in RF circuit should be chosen without contributing large resistances and capacitances for the noise and match concerns. factors are often used to evaluate the qualities of the ESD protection devices. The definition of a factor for a series RC network has been written as (1) As seen in (1), with the reduction of the series resistance and capacitance, the factor of the ESD protection device increases. The shallow-trench-isolation (STI) diodes have been often used as ESD protection elements due to their high- factors [12]. In this study, one pair of n /p-well and p /n-well STI diodes with layout dimension [(width (W)/length (L)] of 1.2 m/5.5 m contributes the parasitic capacitance of approximately 25 fF in the given 0.25- m CMOS process. The layout top views of these diodes are shown in Fig. 5. If four pairs of such diodes are connected in parallel, they will totally contribute a capacitance of 100 fF.

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Fig. 6. Turn-on efficient V DD -to-V SS ESD clamp circuit drawn with ESD protection NMOS Mnesd of large device size. TABLE II DEVICE SIZES USED IN THE V DD -TO-V SS ESD CLAMP CIRCUIT

D.

-to-

ESD Clamp Circuit

In RF ESD protection design, the power-rail ESD clamp circuit is valuable to help conducting ESD currents through the -toforward-biased paths [4]. The turn-on efficient ESD clamp circuit, beneficial for fast turn-on speed during ESD events, is shown in Fig. 6 [13], [14]. The RC time delay was chosen approximately 0.1 s to turn on the ESD NMOS ) during ESD events, and to keep it off under the normal ( power-on condition. R and C were realized by the -well resistor and MOS capacitor, respectively. The inverter can trigger to a high level to help the gate voltage of being uniformly turned on while facing the ESD pulse. Hence, the conductance of the PMOS in the inverter needs to be large quickly during the ESD event. enough to turn on the ) must be drawn The main ESD protection device ( carefully. First, the silicided diffusion is forbidden for ESD protection consideration. Second, the channel width must be drawn large enough to discharge ESD current. Third, the finger width and channel length have to be well selected according to the suggested ESD design rules in the given CMOS process. -toESD clamp circuit The device sizes used in this are listed in Table II. The simulated voltage waveforms on and the drain current of under the the gate of ESD-stress condition and the normal power-on condition are shown in Fig. 7(a) and (b), respectively. With suitable circuit -toESD clamp circuit is only triggered design, the on during the ESD-stress conditions. E. RF Performance Analysis With Smith Chart -parameter matrix has been widely used in the RF system to show the performance of the network. Starting with a standard 50- system, which is commonly found in RF systems, the equivalent RF circuit models of these two different ESD protection schemes are shown in Fig. 8(a) and (b). Fig. 8(a) shows the equivalent RF circuit model of the traditional ES-DESD protection scheme [6]–[8]. The equivalent RF circuit model of the new proposed DS-DESD protection scheme is shown in Fig. 8(b).

Fig. 7. Simulated voltage waveforms and the transient current of the V DD -to-V SS ESD clamp circuit under: (a) the ESD-stress condition and (b) the normal power-on condition.

Fig. 8. Equivalent RF circuit models of: (a) the traditional ES-DESD protection scheme and (b) the DS-DESD protection scheme. The total parasitic capacitance (200 fF) of the ESD protection devices (diodes) is modeled as Cesd to the ac ground.

A signal source with 50- impedance drives the input node of the ESD protection schemes, and a 50- output load is connected to the output node of ESD protection schemes. In each ESD protection scheme, the ESD protection diodes are modeled . It had been demonstrated that the CPWG as capacitances can provide excellent RF performance for operating frequency

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Fig. 9. Matching procedures of: (a) the traditional ES-DESD protection scheme and (b) the DS-DESD protection scheme, expressed on the Smith chart.

over 10 GHz [10], [11], so they are also used in the ESD protection schemes for broad-band RF circuits. STI diodes were employed as the ESD protection devices for their high- factors [12]. is assumed to be Initially, the total ESD capacitance 200 fF, a value sufficient to achieve the 2-kV HBM ESD protection level [3]. The characteristic impedance of the CPWG in this study. -parameter simulations is employed as 70 over the frequency range of 1 15 GHz are performed on these two ESD protection schemes by using the microwave circuit and the simulator ADS to find the reflection parameter . With the neglect on the loss in the transmission parameter is the result of . Thus, , related to the CPWG, impedance match, is the main consideration to compare these two ESD protection schemes shown in Fig. 8(a) and (b). The matching principles of the ES-DESD and DS-DESD ESD protection schemes are expressed in the Smith chart, as those shown in Fig. 9(a) and (b), respectively. The operating frequency is set to 10 GHz in Fig. 9. The centered point of the Smith chart is normalized to 50 . Each CPWG length has been optimized to reach the best match in each ESD protection scheme. The serial number labeled on each point indicates the matching procedure contributed by these components from the core circuit with a 50- output load to the input node of ESD protection scheme. of the ES-DESD ESD protection The matching locus on scheme is shown in Fig. 9(a), and that of the DS-DESD ESD protection scheme is shown in Fig. 9(b). These two ESD

Fig. 10. Simulation results on the RF performance of: (a) S 11– and (b) S 21-parameters between the ES-DESD and the DS-DESD protection schemes.

Fig. 11.

Resistive ladder of the traditional ES-DESD match.

protection schemes have good matching results back to the real line of the Smith chart. However, the final matching points are not the original center point in the Smith chart. The simulation - and -parameters results on the RF performance of between the ES-DESD and DS-DESD protection schemes are shown in Fig. 10(a) and (b), respectively. Comparing the curves -parameters in Fig. 10(a), the RF performances of of ES-DESD and DS-DESD ESD protection schemes have a little difference when the frequency increases up to 10 GHz. Hence, -parameters of these two ESD protection schemes in the Fig. 10(b) also have a little difference when the frequency increases up to 10 GHz. Due to the lack of detailed RF parameters in the given CMOS process, the loss in the

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Fig. 12. (a) ES-DESD protection scheme and (b) the DS-DESD protection scheme with the technology.

narrow signal line and the loss in the substrate are not included into the simulation here. Those nonideal effects will cause a different result on between the simulation and experimental measurement. However, according to the simulation results in Fig. 10, the DS-DESD protection scheme indeed achieves a comparable broad-band RF performance as that of the ES-DESD protection scheme over a wide frequency bandwidth. F. RF ESD Protection Design Considerations For an input pin, there are four modes of pin combinations during ESD stress, which are: 1) positive-to(PS mode); (NS mode); 3) positive-to(PD 2) negative-to(ND mode) ESD stresses mode); and 4) negative-to[15]. The ESD level of an input pin is defined as the lowest ESD level among the four modes of ESD stresses. Therefore, the on-chip ESD protection design should provide effective discharge paths for the four-mode ESD stresses. The turn-on ef-toESD clamp circuit, with the RC inverter ficient NMOS ESD protection circuit, is applied to ensure the ESD protection devices operating in the forward-biased condition under the four ESD-stress modes on the I/O pad [13], [14]. To compare and analyze the ESD performance, the resistive ladder model of the ES-DESD protection scheme is employed, as shown in Fig. 11. According to [5], the large values of the series resistance of CPWG ( ) and the resistance of ESD de) degraded ESD robustness when the ESD-generated vice (

V DD -to-V SS

ESD clamp circuit realized in 0.25-m CMOS

power across them. Therefore, in order to enhance ESD proand should be minimized. The new tection level, the proposed DS-DESD protection scheme by enlarging the size of ESD protection devices at the first ESD stage can reduce the of the first stage, where is usually the most possible location to be damaged. With a relatively large device size at the first ESD stage, it can discharge ESD current more quickly at the first ESD protection stage without along the CPWG of the next stages with the lengths of several hundreds micrometers. Thus, the proposed DS-DESD protection scheme will have better ESD robustness, as compared to that of ES-DESD protection scheme. III. CHIP IMPLEMENTATION To investigate both the RF performance and ESD robustness of the proposed DS-DESD scheme, the advanced process would be preferred. However, limited to the resource of advanced process, which is often quite expensive, the experimental test chip of this study has been designed and fabricated in a 0.25- m CMOS technology with five metal layers. The CPWG employed the top metal as the signal line and metal 1 as the grounded shield, hence, the thickness of the signal line and the height between the signal line and metal 1 were fixed. The ways to adjust the characteristic impedance ( ) of the CPWG are to change the width of the signal line and the spacing between the signal line and coplanar ground. Based on the fixed dielectric constant, the required length of the CPWG to compensate the

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TABLE III COMPONENT PARAMETERS OF ESD PROTECTION ELEMENTS USED IN THE ES-DESD AND DS-DESD PROTECTION SCHEMES

parasitic capacitance can be determined. The impedance of 70 with the signal-line width of 5.5 m and spacing of 7.4 m were chosen to make the resistive-ladder effect more obvious. The STI p- and n-diodes were chosen to shunt the ESD paths or . Each pair of p- and n-diodes with a dimento sion of 5.5 1.2 m contributes a parasitic capacitance of approximately 25 fF. The ES-DESD and DS-DESD protection -toESD clamp circuits have been circuits with the implemented and shown in Fig. 12(a) and (b), respectively, with a total parasitic capacitance of 200 fF from the ESD diodes. -toThese two ESD protection schemes without the ESD clamp circuits are also fabricated in the same testchip as a comparative reference. The component parameters of the ESD protection elements and the length of the CPWG used to realize these two ESD protection schemes in a 0.25- m CMOS process are listed in Table III. IV. EXPERIMENTAL RESULTS AND DISCUSSION A. Measured -Parameters The -parameters of these two ESD protection schemes have been measured on-wafer with two-port ground–signal–ground (G–S–G) probes from 1 to 15 GHz. The 20-GHz -parameter measurement system (HP85122A) is used to characterize the ( ) is 2.5 V circuit behavior. The voltage supply of (0 V), and the input dc bias is 1.0 V. The source and load resistances to the fabricated ESD protection circuits are kept at 50 . The parasitic effects from the input and output pads have been deembedded through the reference open pads to obtain the pure -parameters of the ESD protection circuits. - and -parameters versus frequency are The measured shown in Fig. 13(a) and (b), respectively. As seen in Fig. 13(a), -parameters between the ES-DESD and DS-DESD the ESD protection schemes are different from the simulated ones due to the large power loss along the signal lines and the lossy substrate in the 0.25- m CMOS process. Nevertheless, the -parameters of these two ESD protection schemes still display the same trend as that in the simulated ones. The of ES-DESD scheme is a little smaller than that of DS-DESD when the frequency up to 10 GHz. -parameters of the ES-DESD and DS-DESD protecThe tion circuits are the mixture of the power loss and transmission

Fig. 13. Measured results of RF performance on: (a) S 11- and (b) S 21-parameters of the fabricated ES-DESD and DS-DESD protection schemes.

along the ESD stages with CPWGs of different lengths. Due to the large loss from the narrow signal line and the lossy substrate in the given 0.25- m CMOS process, the performance of is almost reverse to the length of the signal line (CPWG). With a shorter total length of CPWG in the DS-DESD protection circuit, which is realized by top metal 5 in a 0.25- m CMOS of the DS-DESD protection scheme is technology, the better than that of the ES-DESD protection scheme, as shown in Fig. 13(b). This is due to the loss of longer CPWG in the ES-DESD scheme (the DS-DESD scheme has a shorter length of total CPWG). This situation can be further improved by employing wider signal lines and the advanced process to can approach reduce the power loss. When the measured under the condition employing ideal signal the simulated will be positively proportional to the lines, the measured matching condition. However, from the experimental results in this study, the new proposed DS-DESD protection scheme has indeed achieved a good broad-band RF performance as that of the traditional ES-DESD protection scheme. B. ESD Test Results The HBM ESD test results of these two ESD protection -toESD clamp schemes with or without the

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TABLE IV HBM ESD LEVELS OF THE ES-DESD AND DS-DESD ESD PROTECTION -TOESD CLAMP CIRCUITS SCHEMES WITH OR WITHOUT THE

V DD

V SS

circuits are summarized in Table IV at the failure criterion of 30% I–V curve shifting under 1- A current bias. The neg(ND) and positive-to(PS) mode ESD ative-tostresses are the two worse ESD conditions for the ESD stresses on the I/O pin with diodes as ESD protection devices [14]. in -toESD clamp circuit for both The ES-DESD and DS-DESD ESD protection schemes is realized m m in the test with device dimension of chip. The traditional ES-DESD protection scheme can sustain the HBM ESD level of 5.5 kV, but that of the DS-ESD protection scheme can be improved up to 8 kV with the help of the -toESD clamp circuit. Without the -toESD clamp circuit, both of these two ESD protection schemes have a very low ESD level. This has also verified the effectiveness of the active -toESD clamp circuit to improve ESD robustness of RF circuits, which are protected by the diodes with small device sizes to reduce the parasitic effect on RF signal. The typical failed I–V curve shifts on the ES-DESD protection circuit before and after HBM ESD stresses in the ND-mode and PS-mode ESD test are shown in Fig. 14(a) and (b), respectively. From the well-known experience of ESD failure analysis, the curve shifting in Fig. 14 can be judged from the junction leakage on the ESD protection diodes. In order to make sure the ESD protection results consistent with the principle of the resistive ladder model in Fig. 11, the failed circuits after ESD stresses have been de-processed to find the failure location. The EMMI (photon emission microscope) photographs on the ES-DESD protection circuit with a -toESD clamp circuit after 5.5-kV PS-mode ESD stress are shown in Fig. 15(a) (the whole view) and Fig. 15(b) (zoomed-in location on the damaged site). The EMMI photographs have confirmed that the ESD damage is located on the p-diode junction of the first ESD stage with a shining area after the PS-mode ESD stress. The evidence in Fig. 15 has proven that the concept of the resistive-ladder model is correct. The first ESD stage is the weakest location of ESD protection along the ES-DESD ESD protection scheme. Hence, the new proposed DS-DESD ESD protection scheme with the relatively enlarged first ESD stage (but keeping the same total capacitance of ESD diodes) can actually achieve a better ESD robustness than that of ES-DESD ESD protection scheme. To further reduce the loss of the RF signal along the longer CPWG in such ES-DESD and DS-DESD schemes, the CPWG with higher characteristic impedance will be a better selection to

Fig. 14. I–V curves of the input diodes before and after: (a) the (ND-mode) and (b) the positive-to(PS-mode) ESD negative-tostresses. These I–V curves are monitored with both and relatively grounded.

V DD

V SS V DD V SS

achieve better RF performance. The required spacing between the signal line and coplanar ground, as well as the width of the top-layer metal (signal line) to achieve various characteristic impedances have been calculated and listed in Table I. Narrow widths of the signal line with large spacings yield high characteristic impedances. However, the CPWG connected from the pad to ESD diodes drawn with a too-narrow linewidth could be burned out to open circuit by the large ESD transient current in the order of several amperes. A CPWG of 50 (or even with smaller impedance) has a wider linewidth for better ESD current discharging. However, the required line length of the CPWG with smaller characteristic impedance to do RF matching for ESD diodes will become much longer, which will, in turn, cause more power loss for the RF signal through the much longer CPWG. Optimization on the CPWG between the linewidth for ESD current discharging and the characteristic impedance for RF matching (or loss) in different CMOS processes will be a design tradeoff. Thus, in this study, with real chip implementation, the characteristic impedance ( ) of the CPWG is employed as 70 to meet both considerations of RF performance and the linewidth for ESD current discharging.

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[7] [8] [9] [10]

[11] [12] [13] [14]

[15]

Fig. 15. EMMI photographs to show the location of ESD damages in the ES-DESD protection circuit with the V DD -to-V SS ESD clamp circuit after the PS-mode stress. (a) The whole view of the ES-DESD circuit. (b) The zoomed-in view of the damaged location on the p-diode at the first ESD stage.

V. CONCLUSION A new DS-DESD protection circuit with excellent broad-band RF performance and great ESD level has been proposed and verified in a 0.25- m CMOS process. Compared to the traditional ES-DESD protection scheme, the new proposed DS-DESD protection scheme has presented a comparable good RF match and much better ESD robustness. With the help of an active -toESD clamp circuit, the device sizes of ESD protection diodes in the RF input pin can be further reduced to decrease the parasitic capacitance from ESD devices for achieving better RF circuit performance. This new broad-band ESD protection scheme is more useful for ESD design in broad-band RF ICs. REFERENCES [1] S. H. Voldman, “The state of the art of electrostatic discharge protection: Physics, technology, circuits, design, simulation, and scaling,” IEEE J. Solid-State Circuits, vol. 34, no. 9, pp. 1272–1282, Sep. 1999. [2] P. Leroux, J. Janssens, and M. Steyaert, “A 0.8-dB NF ESD-protected 9-mW CMOS LNA,” in IEEE Int. Solid State Circuits Conf. Tech. Dig., 2001, pp. 410–411. [3] C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Jude, and P. Mortini, “Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18-m CMOS process,” in Proc. EOS/ESD Symp., 2000, pp. 251–259. [4] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S. Kao, “ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness,” in IEEE Radio Frequency Integrated Circuit Symp. Dig., 2002, pp. 427–430. [5] B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, “Distributed ESD protection for high-speed integrated circuits,” IEEE Electron Device Lett., vol. 21, no. 8, pp. 390–392, Aug. 2000. [6] C. Ito, K. Banerjee, and R. W. Dutton, “Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs,” IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1444–1454, Aug. 2002.

, “Analysis and design of ESD protection circuits for high-frequency/RF applications,” in Proc. IEEE Int. Quality Electronic Design Symp., 2001, pp. 117–122. , “Analysis and optimization of distributed ESD protection circuits for high-speed mixed-signal and RF applications,” in Proc. EOS/ESD Symp., 2001, pp. 355–363. M.-D. Ker and B.-J. Kuo, “ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme,” in IEEE Radio Frequency Integrated Circuits Symp. Dig, 2004, pp. 383–386. B. Kleveland, C. H. Diaz, D. Vook, L. Madden, T. H. Lee, and S. S. Wong, “Exploiting CMOS reverse interconnect scaling in multi-gigahertz amplifier and oscillator design,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1480–1488, Oct. 2001. C. P. Wen, “Coplanar waveguide: A surface strip transmission line suitable for nonreciprocal gyromagnetic device applications,” IEEE Trans. Microw. Theory Tech., vol. MTT-17, pp. 1087–1090, Dec. 1969. R. M. D. A. Velghe, P. W. H. de Vreede, and P. H. Woerlee, “Diode network used as ESD protection in RF applications,” in Proc. EOS/ESD Symp., 2001, pp. 337–345. M.-D. Ker, “Whole-chip ESD protection design with efficient V DD -to-V SS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 173–183, Jan. 1999. M.-D. Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang, “ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1194–1199, Aug. 2000. M.-D. Ker, C.-Y. Wu, T. Cheng, and H.-H. Chang, “Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 4, no. 3, pp. 307–321, Sep. 1996.

Ming-Dou Ker (S’92–M’94–SM’97) received the B.S. degree in electronics engineering and the M.S. and Ph.D. degrees from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1986, 1988, and 1993, respectively. In 1994, he joined the Very Large Scale Integration (VLSI) Design Department, Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, R.O.C., as a Circuit Design Engineer. In 1998, he became a Department Manager with the VLSI Design Division, CCL/ITRI. In 2000, he became an Associate Professor with the Department of Electronics Engineering, National Chiao-Tung University. He has been invited to teach or help ESD protection design and latchup prevention by hundreds of design houses and semiconductor companies in Hsinchu, Taiwan, R.O.C., and in Silicon Valley, San Jose, CA. His research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed or mixed-voltage I/O interface circuits, especial sensor circuits, and semiconductors. In the field of reliability and quality design for CMOS ICs, he has authored or coauthored over 200 technical papers in international journals and conferences. He holds over 180 patents on reliability and quality design for ICs, which including 81 U.S. patents. His inventions on ESD protection design and latchup prevention method have been widely used in modern IC products. Dr. Ker has serviced as member of the Technical Program Committee and Session Chair of numerous international conferences. He was elected as the first President of the Taiwan ESD Association in 2001. He has also been the recipient of numerous research awards presented by ITRI, the National Science Council, and National Chiao-Tung University, and the Dragon Thesis Award presented by the Acer Foundation. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan, R.O.C., by the Junior Chamber International (JCI).

Bing-Jye Kuo (S’02) was born in Taiwan, R.O.C., in 1978. He received the B.S. degree in electronics engineering and M.S. degree from National ChiaoTung University (NCTU), Hsinchu, Taiwan, R.O.C., in 2000 and 2004, respectively. Since 2002, he has been with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, NCTU. In 2004, he joined MediaTek Inc., Hsinchu, R.O.C., as a Design Engineer responsible for on-chip RF ESD protection circuit design and transmitter circuit design. His current research interests are in the area of on-chip RF ESD protection circuit design and global system for mobile communications (GSM) transmitter circuit design.

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Jitter Considerations in the Design of a 10-Gb/s Automatic Gain Control Amplifier Daniel Kucharski, Student Member, IEEE, and Kevin T. Kornegay, Senior Member, IEEE

Abstract—The effects of noise on random jitter in multistage broad-band amplifiers are analyzed. Limiting amplifiers are compared to automatic gain control (AGC) amplifiers with different gain profiles. Results are presented for a 10-Gb/s AGC amplifier of 45 GHz. Active peaking implemented in an SiGe process with techniques were used to achieve a maximum gain of 48 dB with 7.8 GHz of bandwidth. The amplifier demonstrates low jitter and less than 0.5 dB of peak-to-peak output amplitude variation over a 50-dB input amplitude range. It consumes 30 mW of power from a 3.3-V supply. The amplifier core occupies 0.1 mm2 and requires no external components. Index Terms—BiCMOS integrated circuits, broad-band amplifiers, gain control, optical communication, optical receivers, timing jitter.

I. INTRODUCTION

D

ATA RATES in optical communication systems are limited by the speed of available opto-electronic devices such as lasers and photodetectors, as well as their electrical interfaces. This is particularly true for short-distance applications where dispersion and attenuation in optical fibers are secondary. Parallel data links can be used to increase data throughput and achieve very high aggregate data rates. However, to make such links economically feasible requires a high level of integration and area-efficient design, leading to high circuit density. Such circuits also benefit from low power consumption, which alleviates power distribution and heat-dissipation problems and simplifies array implementation. A signal path of an optical receiver begins with a photodetector, which produces a current that is proportional to the incident optical power. The photocurrent is subsequently amplified and converted to voltage by a transimpedance amplifier (TIA). However, a typical TIA is a single-stage circuit with limited gain and an output amplitude on the order of a few tens of millivolts, which can vary over a wide range due to variations in the transmitter’s output power, as well as optical losses. Clock and data recovery (CDR) requires consistent large-signal levels to minimize bit error rate (BER). Consequently, a postamplifier is required with a high gain, wide dynamic range, and constant output swing. These requirements can be satisfied with a limiting amplifier (LA) or an automatic gain control (AGC) amplifier. An LA is designed to saturate at the desired signal Manuscript received April 21, 2004; revised October 5, 2004. This work was supported in part by the Cornell Broadband Communications Research Laboratory, Cornell University, by MOSIS, and by IBM. The authors are with the Cornell Broadband Communications Research Laboratory, Cornell University, Ithaca, NY 14853 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840731

level, while an AGC amplifier maintains the signal level using a feedback loop to adjust gain. LAs are a popular choice for optical receivers due to their relative simplicity. However, a variable gain amplifier (VGA) with AGC offers certain advantages. First, it maintains gain stages in their linear region to achieve a linear phase response and low deterministic jitter. Second, the AGC reduces the gain when presented with a large input signal, which avoids excessive noise amplification during signal transitions and reduces random jitter compared to an LA with the same maximum gain. Low jitter is very important for CDR operation because nonreturn-to-zero (NRZ) data has no energy at the clock frequency, and the clock must be recovered from data transitions. The remainder of this paper is organized as follows. Noise and jitter relationships are derived in Section II, the amplifier architecture and circuit design are presented in Section III, and fabrication details and experimental results are presented in Sections IV and V, respectively. II. RANDOM JITTER IN AGC AMPLIFIERS Random jitter in broad-band amplifiers arises from the noise present during signal transitions. Total jitter in amplifiers is due to the combined effect of random and deterministic jitter. The following analysis focuses on random jitter, as deterministic jitter is caused by limited bandwidth or nonlinear phase response and can be minimized through careful circuit design. Also, for simplicity of calculations, it is assumed that the noise power is much smaller than the signal power, which is true under most conditions in practical wireline communication systems. A. Effect of Slew Rate Jitter is defined as the deviation from the ideal transition time , and it depends on the noise voltage amplitude and the signal slew rate in the vicinity of the decision threshold. This relationship can be expressed as (1) Noise in electronic circuits is typically modeled as a random Gaussian process with white power spectral density. When sampled at any given instant, the Gaussian random variable associated with the noise has a probability density function (PDF) of the form

0018-9480/$20.00 © 2005 IEEE

(2)

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Fig. 3. Multistage amplifier.

Fig. 1. Conceptual representation of the relationship between noise, transition time, and jitter.

Fig. 4.

Voltage-transfer characteristics of: (a) a VGA and (b) an LA.

where is the rms value of the noise , which can be obtained by integrating noise across the entire circuit bandwidth. Since a function of a random variable is itself a random variable [1], the PDF of random jitter can be calculated from (1) and (2) as follows:

If a random Gaussian process is sampled at different points, the resulting random variables will be uncorrelated and independent if the power spectrum of the process is flat over the pass, which is satisfied in most practical circuits [1], band of [3]. Consequently, the total noise power at the output of the mulis the sum of independent noise power tistage amplifier contributions of each stage

(3)

(5)

From (3), it becomes clear that the rms jitter is linearly proportional to the rms noise and inversely proportional to the slew rate near the decision threshold

where is the output noise contributed by the th stage. Note that the noise from earlier stages is amplified by the subsequent stages, and these early stages have a greater effect on the overall noise figure (NF) of the amplifier. The signal-to-noise ratio (SNR) at the output can be calculated as

Fig. 2. Representation of a single amplifier stage.

(4) It should be reiterated that the linear noise-to-jitter transfer function in (4) is only valid if the noise amplitude is small compared to the signal amplitude [2]. The relationship between noise, transition time, and jitter is illustrated in Fig. 1 to provide a more intuitive insight. As suggested by (4), fast transitions reduce the conversion of noise to jitter.

(6)

where is the maximum peak-to-peak output voltage swing. From the noise perspective, the worst situation occurs to when all stages must operate at maximum gain amplify a small input signal. The SNR in this case is given by

B. Amplifier Noise Model In a typical high-speed broad-band amplifier, multiple stages are required to achieve the desired signal gain. For the purpose of jitter analysis, a single-stage amplifier can be represented as shown in Fig. 2, where white Gaussian noise with rms value is added to the input signal . Their sum is then amof , which repplified by gain and passed through a filter resents the frequency response of the amplifier. If a Gaussian process is passed through a linear time-invariant system, the output will also be a Gaussian process, although it is no longer [3]. A white due to the bandwidth limitation imposed by multistage amplifier can be represented as a cascade of identical , as shown stages with equal amount of input referred noise in Fig. 3.

(7)

Limiting amplifiers always operate at their maximum gain during signal transitions so it would appear that, for large-input amplitudes, their SNR would be lower compared to AGC amplifiers, which can reduce gain in response to a larger input. However, thanks to signal saturation, which is an intrinsic property of LAs, the noise between transitions is effectively turned off in each stage, and does not propagate to the subsequent stages [2]. This phenomenon can be understood by visually comparing voltage-transfer characteristics for both types of amplifiers, as shown in Fig. 4. A VGA always operates in a

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linear fashion providing the same gain for all input voltages regardless of their position relative to the decision threshold. Consequently, the input noise will always be amplified, and it will contribute to the vertical eye closure. On the other hand, an LA has a relatively narrow maximum gain region centered at the decision threshold and a limiting region in which the output does not change in response to the input. If the limiting region is reached due to a large input signal, the logic levels will be largely unaffected by noise and only the noise present during signal transitions will be amplified and converted to jitter. For example, a small amplitude input noise centered at either of the two logic levels will appear at the output of the VGA [see Fig. 4(a)], but not at the output of the LA [see Fig. 4(b)]. To better understand this effect, the input noise can be projected on the voltage-transfer curve. In the LA case, the effective linear gain in the limiting region is zero. Thus, the only global consequence of noise in LAs is jitter accumulation. However, a single limiting stage can be used at the output of an AGC amplifier to provide clean logic levels, while contributing less jitter than an equivalent amplifier consisting entirely of limiting stages. Jitter advantages of AGC amplifiers are demonstrated in more detail in Section II-C.

Expressing (10) in terms of the input slew rate yields desired signal gain

and the total

(11) where and . It should be noted that the total gain cannot exceed the product of maximum gains in all stages, as given by (12), and it defines the smallest input as amplitude that can produce the desired output swing follows: (12) By combining (4) and (11), the rms jitter due to the th stage can be expressed at its output as (13) where . Substituting (13) into (8) and taking the square root yields the final result for the rms jitter at the output of an -stage amplifier

C. Jitter Formulation Since noise signals arising in individual amplifier stages are independent, their jitter contributions are also independent and can be added to obtain the total rms output jitter. It can be expressed in terms of slew rate and , which is the rms noise contribution of the th stage at its output

(8)

(14)

Equation (14) is valid for amplifiers whose slew rate is bandwidth limited, which implies constant transition times in all stages. The maximum slew rate of is possible only when the maximum signal swing is reached. If transitions of an amplifier are limited by a constant slew rate rather than its bandwidth, (14) can be simplified to

Further, assuming that the amplifier is bandwidth limited, the slew rate is a function of the peak-to-peak signal amplitude and the transition time , which is constant for all stages (9) For simplicity, ideal transitions are assumed, which is a reasonable approximation, because the maximum slew rate is observed in the immediate vicinity of the decision threshold, and jitter effects of small amplitude noise are more severe in this region. The and signal amplitude in the th stage depends on the input the product of gains in all stages from the first to the th. How, which ever, the amplitude of that signal cannot exceed is the maximum allowed swing. This is the consequence of the limiting behavior of an LA or the gain control imposed by an AGC. Based on these conditions, the slew rate at the output of the th stage can be calculated as

(10)

(15) , then clearly a slew-rate-limited amplifier will If have less output jitter than an equivalent bandwidth-limited amplifier. However, many practical broad-band amplifiers use lowvoltage differential signaling to achieve high data rates. Thus, they tend to be bandwidth limited, and their jitter is more accurately described by (14). Slew-rate limitation typically comes into play at larger voltage swings. D. Jitter-Performance Comparison Jitter performance of LAs and AGC amplifiers can be compared based on the result in (14). For the purpose of this comparison, a hypothetical 10-Gb/s four-stage amplifier was assumed with a total gain of 40 dB and bandwidth of 7 GHz 0.7 data rate . The transition time for an amplifier with this bandwidth is approximately 45 ps, and can be estimated either by assuming first-order low-pass (LP) characteristics with 3-dB cutoff at 7 GHz [4] or by calculating the maximum slew rate of a 7-GHz sinusoid. These specifications are representative of many commercially available 10-Gb/s optical postamplifiers.

KUCHARSKI AND KORNEGAY: JITTER CONSIDERATIONS IN DESIGN OF 10-Gb/s AGC AMPLIFIER

Fig. 5. Normalized rms output jitter comparison of four-stage amplifiers with maximum gain of 40 dB and the worst case output SNR of six (15.6 dB).

Normalized rms output jitter is plotted as a function in Fig. 5, where is the bit peof normalized input ps for 10-Gb/s data rate). Two different gain riod ( profiles were considered for the AGC. A uniform-gain AGC has identical gain in all stages, while a high SNR AGC maintains more gain in the initial stages by reducing the excess gain until reaches unity, followed by in the last stage stage, and so on, until , which also implies . This nonuniform gain profile can improve the that overall NF [5]. Its advantages are most significant for moderate input signals, as implied by (6). The input referred noise power of each stage ( ) was calculated from (7) assuming the worst case output SNR of six. This SNR value corresponds to a BER of 10 , which defines the lower limit of acceptable performance for many communication systems. It also satisfies the earlier assumption that the noise should be small compared to the signal. As expected, at low input levels, the amplifiers operate close to their maximum gain and exhibit comparable jitter performance. The difference becomes evident as the input increases. The high SNR AGC amplifier demonstrates the lowest output jitter, while the LA levels off at approximately 15 dB below the maximum input amplitude. This advantage of AGC amplifiers becomes particularly important in noisy environments. Based on the assumed amplifier parameters, the LA can produce up to 68% more output jitter. A difference of this magnitude can have an adverse effect on BER. Finally, AGC amplifiers were compared under bandwidth-limited and slew-rate-limited assumptions by plotting (14) and (15), as shown in Fig. 6. This suggests that the optimal low-jitter gain profile depends on the actual factors that limit the transition time; however, the SNR benefits of the nonuniform gain profile indicate that it is a better overall design choice. III. AMPLIFIER ARCHITECTURE AND DESIGN As detailed above, AGC amplifier architectures have the potential for lower output jitter than LAs. They can also allow a

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Fig. 6. Normalized rms output jitter comparison of a bandwidth-limited and slew-rate-limited AGC amplifiers. Both have four stages, maximum gain of 40 dB, and the worst case output SNR of six (15.6 dB).

Fig. 7. AGC amplifier architecture.

dynamic tradeoff between gain and bandwidth, which can improve transition times and further reduce jitter. A block diagram of the implemented 10-Gb/s postamplifier is shown in Fig. 7. The signal path is fully differential and consists of a low-noise input stage followed by three VGA stages independently controlled by an AGC circuit. Due to a high maximum gain of the amplifier, an offset cancellation loop is provided to compensate for device mismatches induced by process variations. A. Input Stage A schematic diagram of the input stage is shown in Fig. 8. To avoid loading of the TIA, the input is buffered with emitter driving a differential pair . The input stage was followers optimized for low-noise performance and has a constant gain of 15 dB. The offset cancellation circuit is an integral part of the input stage. It consists of a pair of first-order low-pass filters (LPFs) – , which extract dc components from the outputs of the last VGA. The difference is applied to an error amplifier , and the offset is subtracted from the signal path via logarithmic loads . The offset cancellation loop creates a low-frequency corner at 10 MHz. This is sufficiently low to have a negligible effect on inter-symbol interference (ISI) of 10-Gb/s 8B 10B coded data. Phase margin of 80 guarantees stability.

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Fig. 8. Input stage and offset cancellation circuit.

Fig. 9.

Fig. 10.

Calculated impedance of the active inductor.

Fig. 11.

VGA stage.

Circuit model for the active inductor.

Further, transistors function as active inductors in conjunction with their base–emitter capacitances and the error amplifier loads . The inductive peaking provides bandwidth extension and was tuned to obtain a flat frequency response. A simplified model of the active inductor is shown in Fig. 9. The impedance can be approximately calculated looking into the emitter of as

(16) where is the base–emitter resistance is the is the base–collector capacbase–emitter capacitance, and . Additionally, is the gate–drain capacitance itance of of n-type field-effect transistor (NFET) whose gate is also connected to , which is relatively large and can be assumed to provide an ac ground at the frequencies of interest for inductive peaking. Using device sizing information and the actual technology values for HBT small-signal parameters, (16) can increases with be plotted, as shown in Fig. 10, where frequency above 5 GHz, exhibiting inductive behavior , and and . rolls off above 30 GHz due to the effect of This parasitic capacitance limits performance of the active inductors compared to spiral inductors whose high-frequency operation is determined by self-resonance. In general, active inductors can be useful at frequencies up to approximately , and a high-quality factor is not necessary for peaking of broad-band amplifiers [6]. The drawbacks of active inductors include their noise and additional voltage headroom required to properly bias the devices. However, they can offer very substantial savings in chip area, as illustrated by the design

example in Fig. 8, where bandwidth extension is an added benefit of the offset cancellation circuit, and it carries no area in series with the active inductors inoverhead. Resistors crease gain, reduce input referred noise, and improve linearity . of the differential amplifier B. VGA A schematic diagram of the VGA stage is shown in Fig. 11. A low-headroom topology was chosen instead of a Gilbert multiplier cell to reduce transistor stacking and assure better lowwhose voltage performance. At its core is a differential pair implegain is controlled via variable emitter degeneration mented with a field-effect transistor (FET) device operated in the triode region. In addition to its low-headroom requirement, it also offers high-frequency operation, low noise, and low distortion [7]. Since the emitter degeneration is variable, one cannot achieve a consistent bandwidth extension with a capacitive by. Very small values of would render peaking inpass of effective at high gain settings. A similar argument can be made for the linearizing properties of emitter degeneration. Consequently, a separate local feedback is used to improve linearity and bandwidth. This is achieved with feedback elements with LP characteristics, which introduce a zero in the frequency response to cancel the effects of the dominant pole. The feedto improve back elements are buffered with emitter followers forward isolation and to provide a level shift that eliminates dc

KUCHARSKI AND KORNEGAY: JITTER CONSIDERATIONS IN DESIGN OF 10-Gb/s AGC AMPLIFIER

Fig. 12.

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VGA circuit model with local LP feedback.

current flow through . Each VGA stage has a gain range of , the maximum midband gain 0–11 dB. Assuming that can be approximately calculated as

Fig. 13.

Calculated frequency response of the VGA.

Fig. 14.

AGC circuit.

(17) is the resistive part of . As expected, this reduces where to when becomes very large. The effect of LP feedback can be illustrated by plotting the frequency response of the VGA. A simplified model, showed in Fig. 12, was used for this purpose, where emitter followers are represented as ideal unity seen looking gain buffers with a finite output resistance or , which is equal to into emitters of (18) The model includes the parasitic capacitances of in addi, and representing the tion to the feedback capacitance loading effect due to the next VGA stage. Based on this model, a single-stage transfer function can be calculated as (19), shown is the impedance of at the bottom of this page, where (20) and (21) where is the Miller capacitance of , which is defined , and and are small-signal as equivalent-circuit components of transistor . Maximum gain was assumed and, consequently, emitter degeneration was ignored. To demonstrate the bandwidth extendue to sion capabilities of the local LP feedback, (19) was plotted using design- and technology-specific parameter values with . As shown in Fig. 13, and without the feedback capacitor a 2-GHz bandwidth improvement is achieved. In the actual design, the last VGA stage has more bandwidth extension compared to the first two. This improves transition times at the output, and allows the amplifier to drive larger loads such

as a CDR or a 50- buffer. The bandwidth extension in the preceding stages is more conservative to preserve a linear phase response and low deterministic jitter. C. AGC A simplified schematic of the AGC circuit is shown in Fig. 14. It samples the output amplitude of the last VGA stage using a – , and then compares the result differential peak detector is to a reference value after the common-mode voltage from stabilize the sampled voltages during subtracted. Capacitors data transitions and are slowly discharged by currents . The resulting amplitude error feeds an LPF consisting of a transconwith an active load and a capacitor ductance amplifier . The amplitude reference is set using a resistor and a tail current source . The LPF parameters were chosen to track variations in optical power, which are slow compared to 10 Gb/s data. Error amplifiers – follow the LPF and drive separate gain control lines. This improves isolation and allows for different gain profiles for each VGA stage. As suggested by reduces the the analysis in Section II, selecting

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Fig. 15. Chip microphotograph.

Fig. 17.

Measured output amplitude and open eye amplitude at 10 Gb/s.

Fig. 18. 10-Gb/s single-ended output eye diagrams with: (a) 2.8 mV differential input and (b) 900 mV differential input. Same scale is used.

Fig. 16. Measured frequency response at the maximum gain.

jitter and improves the NF by retaining more gain in the initial amplifier stages [8]. The interaction between the offset cancellation loop and gain control loop was analyzed to assure stability. It was complicated, however, by the fact that the gain control loop contains a nonlinear rectifying peak detector. Its behavior was predicted using methods outlined in [9] and verified with numerical modeling and detailed circuit simulations. The AGC response to a large step in the input signal amplitude settles in less than 100 ns without ringing. IV. FABRICATION The AGC amplifier was fabricated in IBM’s 0.25- m SiGe of 45 GHz. The amplifier is designed BiCMOS process with as a self-contained core intended for integration with a TIA and a CDR circuit, and it occupies only 0.1 mm of space. It includes all loop filters and supply-independent bias circuits. It requires no external components for 10-Gb/s 8B 10B signals. If necessary, an external capacitor can be added in parallel with in Fig. 8 to shift the low-frequency the on-chip capacitors corner and support data coding schemes with a significant frequency content below 10 MHz. To facilitate independent testing, the core was implemented as a separate chip with the addition of a 100- differential input termination and a 50- differential output buffer. The chip is pad limited and measures 0.75 mm 1.00 mm, as shown in Fig. 15.

Fig. 19. Measured rms jitter for 10-Gb/s 2 (PRBS).

0 1 pseudorandom bit sequence

V. EXPERIMENTAL RESULTS The AGC amplifier consumes 30 mW from a nominal 3.3-V power supply and is fully functional at voltages as low as 2.7 V using less than 25 mW. The measured 3-dB bandwidth is 10 MHz–7.8 GHz, and the maximum broad-band gain is 48 dB, as shown in Fig. 16. The AGC maintains differential output amplitude across a wide range 600 mV of input signal levels, as illustrated in Fig. 17. Measurements demonstrate less than 0.5 dB of peak-to-peak output amplitude variation across a 50-dB input amplitude range corresponding to

KUCHARSKI AND KORNEGAY: JITTER CONSIDERATIONS IN DESIGN OF 10-Gb/s AGC AMPLIFIER

– mV differential. To provide insight into the noise margins of the amplifier, Fig. 17 also shows the amplitude 1 of the vertical eye opening at data rate of 10 Gb/s. A 2 pseudorandom binary sequence was used to generate output eye diagrams, as shown in Fig. 18, for input signals separated in amplitude by approximately 50 dB. These data points are indicated on the amplitude plot in Fig. 17 and correspond to the boundaries of the amplifier’s intended operating range. Output jitter as a function of input amplitude is presented in Fig. 19. The output waveforms were symmetrical with the worst case 20%–80% transition times of 48 ps and no observable duty cycle distortion. VI. CONCLUSION Random jitter relationships for multistage broad-band amplifiers were developed, and a nonuniform gain profile AGC amplifier was chosen due to its jitter and SNR advantages. The amplifier was designed and fabricated in a production SiGe BiCMOS technology. Experimental results demonstrate high gain, low jitter, and low ISI at 10 Gb/s. The output amplitude is tightly controlled across a wide input amplitude range. Active peaking techniques were used to achieve low-power dissipation with high bandwidth and a very compact core layout suitable for receiver array applications. ACKNOWLEDGMENT The authors wish to acknowledge D. Guckenberger, J.-H. C. Zhan, and J. Duster, all of the Cornell Broadband Communications Research Laboratory (CBCRL), Cornell University, Ithaca, NY, for sharing their technical insight, as well as MOSIS and IBM for fabricating the chip. REFERENCES [1] J. G. Proakis and M. Salehi, Communication Systems Engineering. Toronto, ON, Canada: Prentice-Hall, 1994. [2] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 790–804, Jun. 1999. [3] L. W. Couch, Digital and Analog Communication Systems, 6th ed. Toronto, ON, Canada: Prentice-Hall, 2001. [4] B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, 2003. [5] H. T. Friis, “Noise figures of radio receivers,” in Proc. Inst. Radio Eng., Jul. 1944, pp. 419–422. [6] E. Sackinger and W. C. Fischer, “A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1884–1888, Dec. 2000.

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[7] S. Otaka, G. Takemura, and H. Tanimoto, “A low-power low-noise accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1942–1948, Dec. 2000. [8] R. Reimann and H.-M. Rein, “A single-chip bipolar AGC amplifier with large dynamic range for optical-fiber receivers operating up to 3 Gbit/s,” IEEE J. Solid-State Circuits, vol. 24, no. 12, pp. 1744–1748, Dec. 1989. [9] D. M. Badger, “Stability of AGC circuits containing peak detectors,” IEEE Trans. Consum. Electron., vol. 38, no. 3, pp. 377–383, Aug. 1992.

Daniel Kucharski (S’00) received the B.S. degree in electrical engineering from the Rochester Institute of Technology, Rochester, NY, in 1998, the M.S. degree in electrical engineering from Cornell University, Ithaca, NY, in 2004, and is currently working toward the Ph.D. degree at Cornell University. In 1998, he joined IBM Microelectronics, where he was involved with application-specific integrated circuit (ASIC) library development. In 2000, he joined the Cornell Broadband Communications Research Laboratory (CBCRL), Cornell University. He spent the summers of 2001–2004 with the IBM T. J. Watson Research Center, where he was involved with parallel optical data links in SiGe and CMOS. His research interests focus on low-voltage and low-power circuit techniques for high-speed communication systems.

Kevin T. Kornegay (SM’96) received the B.E.E. degree from the Pratt Institute, Brooklyn, NY, in 1985, and the M.S. and Ph.D. degrees in electrical engineering and computer science from the University of California at Berkeley, in 1990 and 1992, respectively. From 1992 to 1994, he was a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. In 1998, he joined the faculty of the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, where he is currently an Associate Professor. He is also the Director of the Cornell Broadband Communications Research Laboratory (CBCRL), Cornell University. His research interests include mixed-signal integrated-circuit (IC) design, RF integrated circuit (RFIC) design, millimeter-wave integrated-circuit (MMWIC) design, and broad-band wireless and wireline data communication systems. Dr. Kornegay serves on the Technical Program Committees of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS), the Radio Frequency Integrated Circuits Symposium, and the International Symposium on Low Power Electronic Design. He is an editor for the IEEE ELECTRON DEVICE LETTERS. He is a Distinguished Lecturer of the IEEE Electron Devices Society and a member of the Eta Kappa Nu and Tau Beta Pi. He has also served as a member of the Defense Science Study Group. He has been the recipient of numerous awards, including the Black Engineer of the Year Award, the National Science Foundation (NSF) CAREER Award, the IBM Faculty Partnership Award, the National Semiconductor Faculty Development Award, the Cornell University Provost Award for Distinguished Scholarship, and the 2003 Device Research Conference (DRC) Best Student Paper Award.

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G-Band (140–220 GHz) and W -Band (75–110 GHz) InP DHBT Medium Power Amplifiers

Vamsi K. Paidi, Zach Griffith, Yun Wei, Mattias Dahlstrom, Miguel Urteaga, Navin Parthasarathy, Munkyo Seo, Lorene Samoska, Andy Fung, and Mark J. W. Rodwell, Fellow, IEEE

Abstract—We report common-base medium power amplifiers -band (75–110 GHz) designed for -band (140–220 GHz) and in InP mesa double HBT technology. The common-base topology is preferred over common-emitter and common-collector topologies due to its superior high-frequency maximum stable gain (MSG). Base feed inductance and collector emitter overlap capacitance, however, reduce the common-base MSG. A single-sided collector contact reduces ce and, hence, improves the MSG. A single-stage common-base tuned amplifier exhibited 7-dB small-signal gain at 176 GHz. This amplifier demonstrated 8.7-dBm output power with 5-dB associated power gain at 172 GHz. A two-stage common-base amplifier exhibited 8.1-dBm output power with 6.3-dB associated power gain at 176 GHz and demonstrated 9.1-dBm saturated output power. Another two-stage common-base amplifier exhibited 11.6-dBm output power with an associated power gain of 4.5 dB at 148 GHz. In the -band, different designs of single-stage common-base power amplifiers demonstrated saturated output power of 15.1 dBm at 84 GHz and 13.7 dBm at 93 GHz. Index Terms—InP heterojunction bipolar transistor, millimeterwave amplifier, monolithic microwave integrated circuit (MMIC) amplifiers.

I. INTRODUCTION

W

-BAND (75–110 GHz) and -band (140–220 GHz) amplifiers have applications in wide-band communication systems, atmospheric sensing, and automotive radar. The high mobility of InGaAs, high electron saturation velocity of InP, and submicrometer scaling result in wide-bandwidth transistors with high available gain in this frequency band. In a transferred substrate InP HBT process, 6.3-dB gain is reported at 175 GHz with a single-stage amplifier [1]. State-of-the-art results in InP high electron-mobility transistor (HEMT) technologies include a three-stage amplifier with 30-dB gain at 140 GHz [2], a three-stage amplifier with 12–15-dB gain from 160 to 190 GHz [3], and a three-stage power amplifier with 10-dB gain from 144 to 170 GHz [4].

Manuscript received April 21, 2004; revised July 24, 2004. This work was supported in part by the Office of Naval Research under Grant N00014-04-10071. A portion of this work was carried out at the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, under a contract with the National Aeronautics and Space Administration. V. K. Paidi, Z. Griffith, Y. Wei, M. Dahlstrom, N. Parthasarathy, M. Seo, and M. J. W. Rodwell are with the Electrical and Computer Engineering Department, University of California at Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: [email protected]). M. Urteaga is with the Rockwell Scientific Corporation, Thousand Oaks, CA 91360 USA. L. Samoska and A. Fung are with the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 91109 USA. Digital Object Identifier 10.1109/TMTT.2004.840662

Recent research in a scaled InP/InGaAs/InP mesa double HBT (DHBT) with a 30-nm carbon-doped InGaAs base with a graded base doping and 150 nm of total depleted collector thickness achieved wide-bandwidth transistors with 370 GHz and 459 GHz [5], [6]. In this paper, we describe how this technology is used to realize several power amplifiers in the 75–220-GHz frequency range. II. InP DHBT PROCESS The transistors in the circuit are formed from a molecular beam epitaxy (MBE) layer structure with a highly doped 35-nm InGaAs base and a 210-nm collector and are fabricated in a triple-mesa process with both active junctions defined by selective wet etch chemistry. The increased collector thickness over despite increases in [5] and [6] is intended to maintain high device critical dimensions, motivated by the desire for improved transistor yield. Polyimide passivates and planarises the devices. One level of deposited metal forms circuit interconnects and electrical contacts to transistors and resistors. SiN metal–insulator–metal (MIM) capacitors and coplanar-waveguide (CPW) transmission lines are employed to synthesize the tuning elements. Plated air bridges bridge the ground planes and suppress the CPW slot-line modes. III. AMPLIFIER DESIGN A. Models and Simulations The transistor SPICE model parameters used in the simulations are extracted from the measured two-port -parameters. The amplifiers are simulated using the Advanced Design System software of Agilent Technologies, Palo Alto, CA. A planar method-of-moments electromagnetic (EM) simulator (Momentum) modeled the CPW structures and the MIM capacitors. B. Transistor Characteristics The dc common-base characteristics of a twofinger 0.7 m 11 m InP common-base power DHBT is shown in Fig. 1. The common-base breakdown voltage is more than 7 V (Fig. 2). The feasible load line is, however, constrained by the device safe operating area (Fig. 1), as determined by both breakdown voltage and and thermal resistance. The devices have shown 240 GHz when biased at 3 mA/ m current density and 290 GHz (Fig. 3). The degradation in relative to [5] is 1.7 V

0018-9480/$20.00 © 2005 IEEE

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-BAND (140–220 GHz) AND

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Fig. 1. Common-base dc characteristics of a two-finger 0.7 common-base DHBT.

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m 2 11 m

Fig. 4. Comparison of MSG/MAG of common-base, common emitter, and common collector configuration of an InP DHBT. L and C are omitted.

Fig. 2. Common-base dc characteristics of a two-finger 0.7 common-base DHBT.

m 2 11 m

Fig. 3. Short-circuit current gain and Mason’s gain as a function of frequency of a single-finger 0.7 m 7 m common-emitter DHBT.

2

due to a wider base mesa intended to improve yield and due to relatively poor base ohmic contacts in this process run. C. Transistor Layout Parasitics The common-base topology is chosen as it has higher maximum stable gain (MSG) in this band when compared to the common-emitter and common-collector topologies (Fig. 4). At present, however, we ignore both base feed inductance and collector–emitter overlap capacitance . At 180 GHz, the common-base topology exhibits 10-dB MSG, while the common-emitter and common-collector topologies exhibit 4

and 3 dB, respectively. Since power amplifiers use large-signal load match, rather than a small-signal output match, the gain falls below the MSG. The above comparison between different configurations igand . While these parasitics reduce nores the effect of the common-base MSG, in the -band, the common-base topology still provides the highest gain when compared to the common-emitter and common-collector configurations. If not and could potentially cause modeled in the designs, instability. Base inductance is due to the long thin base contact metal stripes on either side of the emitter [see Fig. 5(a)]. Loop inductance depends upon the current return path; this is difficult is not readily to identify in the transistor geometry, hence, modeled with accuracy. This creates uncertainty in the stability analysis. -parameter extractions indicate approximately 3-pH base feed inductance per 12- m-long emitter finger having 0.8- m base contact width. The collector-to-emitter overlap also reduces MSG. is the capacitance capacitance between the emitter interconnect metal and the collector ohmic contact metal [see Fig. 5(a) and (b)]. These metals are separated by 400–500-nm polyimide. This thickness varies in variable. Degradation in MSG/maxour process, rendering imum available gain (MAG) of a common-base topology due to and of an InP DHBT with double-sided layout parasitics collector contacts is shown in Fig. 6. Potential instability in the and was observed small-signal characteristics due to in the first-generation amplifiers fabricated. In second-generation designs, the collector-to-emitter overlap capacitance was significantly reduced by employing single-sided collector contacts as opposed to double-sided collector contacts (Fig. 7). In , this also increases the collector resisaddition to reducing tance and, thus, further improves circuit stability. NiCr resistors provide additional resistive stabilization in some designs. D. Circuit Design Fig. 8 shows a single-stage amplifier circuit schematic. Shunt capacitors are either SiN MIM capacitors or CPW open-circuit stubs. Two-stage amplifiers (Fig. 9) are formed by cascading

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Fig. 6. Comparison of common-base MSG/MAG with and without layout parasitics. The InP DHBT has a double-sided collector contact.

(a)

Fig. 7. Comparison of MSG/MAG of common-base HBT with single-sided collector contact and double-sided collector contacts. The design values of the power-amplifier gains are also shown.

Fig. 8. Single-stage common-base amplifier.

IV. MEASUREMENTS A. Small-Signal Measurements

(b) Fig. 5. (a) Cross section and top view of an InP mesa DHBT with double-sided collector contacts. (b) Cross section and top view of an InP mesa DHBT with single-sided collector contacts.

two identical single-stage designs. The output of the first stage is large-signal matched to the second stage input, avoiding firststage premature power gain compression.

-band amplifiers are measured on wafer using an HP 8510C vector network analyzer (VNA) with Oleson Microwave Laboratories’ Millimeter Wave VNA extensions. The test-set extensions are connected to GGB Industries coplanar wafer probes via WR-5 waveguides. The amplifier measurements are calibrated using off-wafer thru-reflect line (TRL) calibration -band amplifier small-signal gains and return standards. losses were measured on-wafer using a -band Agilent 8510 network analyzer calibrated with an off-wafer calibration using TRL calibration standards.

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Fig. 11.

148–152-GHz power measurement setup.

Fig. 12.

75–110-GHz power measurement setup.

Fig. 9. Two-stage common-base amplifier.

Fig. 13. Die photograph of the single-stage common-base monolithic-microwave integrated-circuit (MMIC) amplifier centered at 176 GHz. This measures 0.36 mm 0.3 mm.

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Fig. 10.

170–180-GHz power measurement setup.

B. 172–180-GHz Power Measurements -band power measurements were performed at the Jet Propulsion Laboratory (JPL), California Institute of Technology, Pasadena. The 170–180-GHz power measurement -band power from a backward setup is shown in Fig. 10. wave oscillator (BWO) power source is amplified and is doubled in frequency using a Schottky diode frequency doubler. The frequency-doubler output drives the input of the device-under-test (DUT). The DUT output power is measured using a calorimeter. Since the input and output power are measured at separate times, the saturated power-gain measurements are subject to approximately 1-dB drift in gain. The saturated output power measurement is not subject to this drift, and we estimate the output power data is accurate to 0.5 dB. Data is corrected for measured probe attenuation.

Fig. 14.

Measured S -parameters of the 176-GHz single-stage amplifier.

amplified and tripled in frequency to 75–110 GHz. This signal is further amplified to drive the DUT input. The DUT output power is measured using a -band power sensor. V. RESULTS

C. 148–152-GHz Power Measurements

A. 176-GHz Single-Stage Amplifier

The 148–152-GHz measurement setup is shown in Fig. 11. A 150-GHz Gunn oscillator drives the DUT. A variable attenuator adjusts the input power.

A die photograph is shown in Fig. 13. The transistor has two separate 0.8 m 12 m fingers. The amplifier bandwidth is limited by the output tuning network. The transistor output is large-signal load-line matched for maximum saturated output power, as opposed to a small-signal match for maximum gain. This amplifier exhibited 7-dB small-signal gain at 176 GHz mA and V (Fig. 14). when biased at

D. 75–110-GHz Power Measurements The 75–110-GHz power measurement setup is shown in Fig. 12. The output of a dc–40-GHz frequency synthesizer is

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Fig. 17.

Die photograph of a 165-GHz amplifier.

Fig. 18.

S -parameters of a 165-GHz single-stage amplifier.

Fig. 15. Output power, power-added efficiency (PAE) versus input power of the 176-GHz single-stage amplifier at 172 GHz.

Fig. 16.

176-GHz amplifier saturated output power as a function of frequency.

This medium power amplifier is designed to obtain 16.5-dBm mA saturated output power at 180 GHz when biased at and V. The output power versus input power characteristic is shown in Fig. 15. The amplifier exhibited a saturated output power of 8.77 dBm with an associated power gain of 5 dB mA and V. at 172 GHz when biased at This medium power amplifier demonstrated 8-dBm saturated output power between 172–176 GHz (Fig. 16). The circuit exhibited 7.9-dB uncompressed gain under the above conditions at 172 GHz. Measured -parameter data exhibits potential instability in the 140–170-GHz range due to feedback parasitics and .

Fig. 19. Output power: PAE versus input power of the 165-GHz single-stage amplifier.

B. 165-GHz Single-Stage Amplifier A second single-stage common-base amplifier (Fig. 17) exhibited 6.5-dB small-signal gain at 165 GHz (Fig. 18) when mA and V. This amplifier’s smallbiased at signal gain is 3 dB between 152–180 GHz. The transistor has two separate 0.8 m 12 m fingers. This medium power amplifier exhibited 8.3 dBm saturated output power with 4.5-dB associated power gain at 172 GHz mA and V. (Fig. 19) when biased at C. 176-GHz Two-Stage Amplifier A die photograph is shown in Fig. 20. This amplifier is a cascaded version of two individual amplifiers designed for 50-

Fig. 20. Die photograph of a 176-GHz two-stage MMIC amplifier. This measures 1 mm 0.7 mm.

2

input resistance and 50- load. Each stage employs two separate 0.8 m 12 m HBT fingers. The small-signal measuremA ments are performed with the first stage biased at and V and the second stage biased at mA and V. Small-signal measurements indicate 7-dB gain at

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Fig. 24. Die photograph of a 150-GHz two-stage MMIC amplifier. Fig. 21.

Small-signal measurements of the 176-GHz two-stage amplifier.

Fig. 25.

Fig. 22.

Small-signal measurements of the 150-GHz two-stage amplifier.

Power measurements of the 176-GHz two-stage amplifier.

Fig. 26. Power measurements of the 150-GHz two-stage amplifier.

Fig. 23. Power measurements of the 176-GHz two-stage amplifier at 150.2 GHz.

176 GHz and 13-dB gain at 150 GHz. There is a potential instain 140–150-GHz range (Fig. 21). bility in This amplifier exhibited 8.1-dBm output power with 6.35-dB associated power gain at 176 GHz and demonstrated 9.1-dBm saturated output power (Fig. 22). These measurements are mA and performed with the first stage is biased at V and the second stage biased at mA and V. At 150.2 GHz, the medium power amplifier exhibited 10.3-dBm output power with 3.4-dB associated power mA and gain (Fig. 23). The first stage is then biased at V and the second stage is biased at mA V. Uncompressed gain at 150.2 GHz is 9.2 dB. and

Fig. 27.

Die photograph of a 84-GHz single-stage amplifier.

D. 150-GHz Two-Stage Amplifier A second two-stage amplifier (Fig. 24) exhibited 10-dB gain mA and at 150 GHz with the first stage is biased at V and the second stage biased at mA and

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Fig. 28.

Small-signal measurements of the 84-GHz amplifier.

Fig. 31.

Fig. 29.

Power measurements of a 84-GHz amplifier.

Fig. 32. Power measurements of the 92-GHz amplifier at 93 GHz.

Small-signal measurements of 92-GHz amplifier.

F. 92-GHz Single-Stage Amplifier A second common base amplifier (Fig. 30) exhibited 5-dB mA and small signal gain at 92 GHz when biased at V (Fig. 31). This amplifier demonstrated 13.7-dBm saturated output power at 93 GHz (Fig. 32) when biased at mA and V.

VI. CONCLUSION Fig. 30.

Die photograph of a 92-GHz amplifier.

V (Fig. 25). This two-stage amplifier demonstrated 11-dBm output power at 150.2 GHz with 4.2-dB associated power gain (Fig. 26). At 148 GHz, a 11.6-dBm saturated output power is obtained with an associated power gain of 4.5 dB. These power measurements are performed with the first stage mA and V, and the second stage biased at mA and V. biased at E. 84-GHz Single-Stage Amplifier A single-stage amplifier (Fig. 27) exhibited 5.6-dB smallmA and signal gain at 84 GHz (Fig. 28) when biased at V. The transistor has four separate 0.8 m 12 m fingers. This circuit demonstrated 15.1-dBm saturated output power at 84 GHz with 4-dB associated power gain (Fig. 29).

Common-base high-gain -band and -band medium power amplifiers in InP mesa DHBT technology have been presented. A single-stage common-base tuned amplifier with 7-dB small-signal gain at 176 GHz exhibited 8.7-dBm output power with 5-dB associated power gain at 172 GHz. The common base topology provides the largest MSG. This configuration and or the MSG will requires careful layout to minimize be reduced. Despite large-signal load-line matching, the design values of gain remain high at 180 GHz, and close to the MSG. Power levels, efficiency, and center frequency are below design values, an effect we attribute to modeling errors. Recent DHBTs [6], suggesting feasibility have been reported at 459 GHz of power amplifiers at 250 GHz. Increasing the number of HBT fingers should result in power amplifiers with output power over 100 mW. The results presented here have demonstrated the potential of InP DHBT technology for high-performance ultrahigh-frequency millimeter-wave circuit applications.

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-BAND (140–220 GHz) AND

-BAND (75–110 GHz) InP DHBT MEDIUM POWER AMPLIFIERS

REFERENCES [1] M. Urteaga et al., “G-band (140–220-GHz) InP-based HBT amplifiers,” IEEE J. Solid-State Circuits, vol. 38, no. 9, pp. 1451–1456, Sep. 2003. [2] C. Pobanz et al., “A high-gain monolithic D -band InP HEMT amplifier,” IEEE J. Solid-State Circuits, vol. 34, no. 9, pp. 1219–1224, Sep. 1999. [3] R. Lai et al., “InP HEMT amplifier development for G-band (140–220 GHz) applications,” in Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, Dec. 2000, pp. 175–177. [4] L. Samoska et al., “A 20 mW, 150 GHz InP HEMT MMIC power amplifier module,” IEEE Microwave Wireless Compon. Lett., vol. 14, no. 2, pp. 56–58, Feb. 2004. [5] Z. Griffith et al., “InGaAs/InP mesa DHBTs with simultaneously high f and f and low C =I ratio,” IEEE Trans. Electron Devices, vol. 25, no. 5, pp. 250–252, May 2004. [6] M. Dahlstrom et al., “InGaAs/InP DHBT’s with >370 GHz f and using a graded carbon-doped base,” presented at the IEEE Device f Research Conf., Salt Lake City, UT, Jun. 23–25, 2003.

Vamsi K. Paidi received the B.Tech. degree in electrical engineering from the Indian Institute of Technology (IIT), Madras, India, in 2000, and is currently working toward the Ph.D. degree at the University of California at Santa Barbara (UCSB). His research includes design and fabrication of high-frequency power amplifiers for wireless applications using GaN HEMTs and InP DHBTs.

Zach Griffith received the B.S. and M.S. degrees in electrical engineering from the University of California at Santa Barbara (UCSB), in 1999 and 2001, respectively, and is currently working toward the Ph.D. degree at UCSB. His primary research includes design and fabrication of InP high-speed digital integrated circuits.

Yun Wei received the B.S. degree from Fudan University, Shanghai, China, in 1991, the M.S. degree from the Oregon Graduate Institute of Technology, Portland, in 1998, and the Ph.D. degree from the University of California at Santa Barbara (UCSB), in 2002, all in electrical and computer engineering. From 1991 to 1997, he was a Researcher with the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China. His research concerned high-speed bi-CMOS circuits and devices. Since 1998, he has been with UCSB, where he is involved with ultrahigh-speed compound semiconductor power HBTs and MMICs.

Mattias Dahlstrom received the M.Sc. degree in engineering physics and Ph.D. degree in photonics from the Royal Institute of Technology (KTH), Stockholm, Sweden. He is currently with the University of California at Santa Barbara (UCSB), where he is involved with ultrahigh-speed InP HBTs. His main focus is on device design, process development, and high-frequency measurements.

Miguel Urteaga received the B.A.Sc. degree in engineering physics from Simon Frasier University, Vancouver, BC, Canada, in 1998, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of California at Santa Barbara (UCSB), in 2001 and 2003 respectively. He is currently with the Rockwell Scientific Corporation, Thousand Oaks, CA. His reaserch has included device design and fabrication of high-speed InP HBTs, as well as the design of ultrahigh-frequency integrated circuits.

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Navin Parthasarathy received the M.Sc. (honors) degree in physics and B.E. (honors) degree in electrical and electronic engineering from the Birla Institute of Technology and Science, Pilani, India, in 2000, and is currently working toward the Ph.D. degree at the University of California at Santa Barbara (UCSB). His research includes the design and fabrication of InP-based high-speed transistors and circuits.

Munkyo Seo received the B.S.E.E. and M.S.E.E. degrees in electronic engineering from Seoul National University, Seoul, Korea, in 1994 and 1996, respectively, and is currently working toward the Ph.D. degree at the University of California at Santa Barbara (UCSB). From 1997 to 2002, he was a Research Engineer with LG Electronics Inc., where he designed RF subsystems for wireless communication. His research interests includes microwave/mixed-signal circuit design and digital signal processing.

Lorene Samoska received the B.S. degree in engineering physics from the University of Illinois at Urbana-Champaign, in 1989, and the Ph.D. degree in materials engineering from the University of California at Santa Barbara (UCSB), in 1995. She was subsequently a Post-Doctoral Researcher with the Electrical and Computer Engineering Department, UCSB, where she was engaged in the design and fabrication of state-of-the-art microwave digital circuits based on InP HBTs. In 1998, she joined the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, where she is currently a Senior Engineer involved in the design and testing of 70–300-GHz HEMT and HBT MMIC power amplifiers for local-oscillator sources and transmitters in future space missions.

Andy Fung received the B.S.E.E., M.S.E.E., and Ph.D. degrees in electrical engineering from the University of Minnesota at Minneapolis-St. Paul, in 1993, 1995, and 1999, respectively. He is currently a Member of the Technical Staff with the Jet Propulsion Laboratory, California Institute of Technology, Pasadena. His research involves the development of high-speed InP HBTs and GaAs Schottky diodes.

Mark J. W. Rodwell (M’89–SM’99–F’03) received the B.S. degree from the University of Tennessee at Knoxville, in 1980, and the M.S. and Ph.D. degrees from Stanford University, Stanford, CA, in 1982 and 1988, respectively. He is currently Professor and Director of the Compound Semiconductor Research Laboratories and the National Science Foundation (NSF) Nanofabrication Users Network (NNUN), University of California at Santa Barbara. From 1982 to 1984, he was with AT&T Bell Laboratories, Whippany, N.J. His research focuses on high-bandwidth InP bipolar transistors and multigigahertz bipolar circuit design. His recent research activities also include microwave power amplifiers, and monolithic analog and digital transistor circuits operating above 100 GHz. Dr. Rodwell was the recipient of a 1989 NSF Presidential Young Investigator Award. His work on GaAs Schottky-diode ICs for subpicosecond/millimeterwave instrumentation was awarded the 1997 IEEE Microwave Prize.

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A GSM/EGSM/DCS/PCS Direct Conversion Receiver With Integrated Synthesizer Young-Jin Kim, Young-Suk Son, Victor N. Parkhomenko, In-Chul Hwang, Member, IEEE, Je-Kwang Cho, Kyung-Suc Nah, Member, IEEE, and Byeong-Ha Park, Member, IEEE

Abstract—A global system for mobile communications direct conversion receiver with an integrated synthesizer is implemented with a 0.35- m BiCMOS technology. Proposed second-order intercept point calibration method is analyzed and verified by measurements. The maximum IIP2 = 66 dBm is achieved by an 8-b resistive calibration code. The receiver draws 57/63 mA from a 2.7-V supply. Index Terms—Direct conversion receiver (DCR), global system for mobile communications (GSM), receiver, second-order intercept point (IP2) calibration.

I. INTRODUCTION

A

DIRECT conversion receiver (DCR) has been a popular architecture, in which the dc offset, local oscillator (LO) re-radiation, second-order intercept point (IP2) and so forth are important factors. In a heterodyne system, these are not important specifications because the carrier frequency at the antenna is different from the LO frequency and the second-order intermodulation distortion (IMD2) components by interferers are placed in the out-band range. Although there are many troublesome problems, the DCR has been tried to implement in order to minimize the external components. The dc offset in a DCR can be divided into static and dynamic dc offset. The static dc offset is generated by the LO self-mixing due to the fact that the LO signal resides in the same band as the RF signal. The dynamic dc offset problem is more serious if the self-mixing varies with time, which occurs when the LO leakage radiates out from the antenna and is subsequently reflected back to the antenna from nearby moving objects. If we pursue symmetry, balancing, and perfect differential design, the low dc offset by high isolation can be obtained naturally. An IMD2 component is also closely related with dc offset. However, the more noteworthy problem is that this makes in-band noise by interferers. For improving IP2 characteristics, one method is to reduce the second harmonic coefficient in a nonlinear block, which is especially the down-conversion mixer. If we make the positive and negative nodes of the mixer perfectly differential, the second harmonic components will be removed by the common-mode rejection of the following block. Manuscript received April 20, 2004; revised September 24, 2004. Y.-J. Kim, V. N. Parkhomenko, I.-C. Hwang, J.-K. Cho, K.-S. Nah, and B.-H. Park are with the Samsung Electronics Company Ltd., Kyungki-Do 449-711, Korea. Y.-S. Son is with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305701, Korea. Digital Object Identifier 10.1109/TMTT.2004.840737

Fig. 1. GSM receiver block diagram: LNA, PPF, HM, three-stage PGA, eight-pole LPF, three-stage DCOC, and fractional- (FN) synthesizer with integrated loop filter.

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Fig. 2.

HM schematic and LO conduction diagram.

In other words, we can say the performance of a DCR receiver depends on how we can make the DCR receiver symmetric. In Fig. 1, for improving the LO re-radiation and dc-offset characteristic, the harmonic mixer (HM) circuit in Fig. 2 is adopted. By adopting this HM, we use the LO frequency, which is different from the RF frequency. Only the second harmonic component of the LO signal contributes to the self-mixing by the radiated power, but this contribution is negligible. In Fig. 3, the low-noise amplifier (LNA) scheme is a well-known common source with a degeneration inductor. In Fig. 4, for improving symmetry, the IP2 calibration block, which is composed of digitally controlled resistances, is placed at the output of down-conversion mixers. The asymmetries at the output nodes of mixer come from many factors, but the asymmetries from all kinds of causes can be revised by only tuning the load resistance precisely. Thus, this phenomenon will be analyzed by a simple expansion and verified by a measurement [2], [4].

0018-9480/$20.00 © 2005 IEEE

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Using known identity we can easily get an expression for the gate function form

, in the

(3) Along with the fact that that

, it can be shown

Fig. 3. Differential LNA schematic with gain control for the GSM/EGSM and DCS/PCS mode ( = 9).

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(4) a duty cycle of the proper LO signal. where In duty cycles, the real circuit will be defined by input LO buffer distortion, voltage offsets of switching block transistors, LO amplitude mismatch, and LO phase mismatch. There is only one condition for duty-cycles variations of LO signals in the . Assume switching block, which is that these all effects can be expressed as only duty mismatch for simple estimation. In Fig. 2, the Taylor series of the LO signal of our HM can be expressed as

D D

Fig. 4. IP2 calibration block diagram (8 b): 3-b coarse calibration ( 7– 5), denotes the inversion 4-b fine calibration ( 4– 1), and 1-b sign ( 8), of and and are the output loads of the mixer in Fig. 2.

D

R

D D R

D D

II. IP2 ANALYSIS OF HM The adopted HM and LO conduction diagram are shown in Fig. 2. Since a half of RF frequency is used as LO frequency, ideally there is not any frequency component same as RF frequency. The switching diagram can be easily expressed because the current of the transconductance stage is passed two times within one cycle. The principle of mixer operation can be easily explained. First, the input voltage signal is converted into the current signal by the transconductance stage. The flow path of this current signal is controlled by the switching stage. This operation at the switching stage can be viewed as the sum of a multiplication of the current signal by a rectangular wave and a 90 phase-shifted rectangular wave. The analysis sequence of IP2 will be the following procedure. The nonlinearity characteristic of the input stage is expressed as

(5) where

. From (2), let us set the input amplitudes as and . The currents of the transconductance stage are given as

(1) The two-tone input signal is given as , and if this two-tone signal is substituted into (1), the equation can be shown as (2) where

.

(6)

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where

phase mismatch. Equation (6) is multiplied by (5), which is the equivalent expression of quadrature switching. After being filtered by a low-pass filter (LPF), the differential output voltage after switching can be given as

From (8), it is shown that the final IIP2 is determined by the , input amplitude , transconductance duty ratio , and output load mismatches. It is very difstage ficult to adjust the duty ratio, input amplitude, and transconductance mismatches because the operation frequencies of those are so high. However, the operation frequency at the output load is relatively low. Fortunately, the denominator at (8) is made to be zero by trimming only the load resistance mismatch. We can conclude that the only fine tunable resistance is needed in IP2 calibration [1]. This variable resistor can be implemented as an active or a passive circuit. Since the implementation by a passive component has some merits in terms of the noise figure (NF) and intermodulation characteristics, we implemented this variable resistor as a digitally controllable passive resistor in Fig. 4.

(7) III. IMPLEMENTATION

where A. Front-End Block

The input second-order intercept point (IIP2) of the harmonicbalanced mixer can be expressed as

(8) and the equation shown at the bottom of this page.

In Fig. 3, the LNA schematic is shown. It is designed by a differential cascaded common source with degeneration inductors, which are realized by bonding wire. For reducing chip area, the four LNAs for four modes are merged into global system for mobile communications (GSM) and extended global system for mobile communications (EGSM) LNAs and digital communications system (DCS) and personal communications system (PCS) LNAs. For covering both modes for each LNA, the quality factor of the inter-stage matching between the LNA and the following block should be decreased. Fortunately, the following block is the 400- poly-phase filter (PPF), which makes the quadrature signal at the signal path. By this resistive load, the quality factor of inter-stage matching circuit is decreased and wide-band matching can be achieved naturally. By changing the size of transistor, the gain of the LNA can be controlled by 20 dB. For removing the down-converted strong interferer, the 327-pF internal capacitor, which is implemented with stacked capacitors, between differential nodes at the output of mixer is connected. We can say that the effective third-order intercept point (IP3) of the following blocks can be increased by this one-pole LPF. Therefore, we can dismiss the IP3 of the baseband block. Since the IP3 of the LNA is designed as more than system IP3, the input stage of the mixer is the inevitable bottleneck in the receiver. For satisfying the system IP3, the target IP3 value of the mixer is directly decided by the gain of LNA. To increase the IP3 of the mixer, the passive resistance is used as degeneration impedance in order to reduce the chip area. However, the NF of the mixer will be increased by this resistive degeneration. Thus, we cannot use the excessively large resistance because of the system NF, and the excessively small resistance because of the system IP3.

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C. Synthesizer

Fig. 5.

Block diagram of the PGA.

The degeneration value is carefully decided in order to satisfy the IP3 and NF of the receiver simultaneously. In Fig. 1, the main signal is phase shifted by the passive PPF. This quadrature signal from the PPF is then just down-converted into the baseband by the HM. Each HM needs a differential quadrature LO, which is generated by the PPF. The IP2 calibration can be implemented by either the digital or analog method. Due to easy controllability, the IP2 calibration method with digital control is proposed in Fig. 4. – controls are used to set to the coarse calIn Fig. 4, ibration. are used to set to the fine calibration. is assigned to the sign bit. If 3-b coarse calibrations are connected to the plus node, the 4-b fine calibrations should be connected is toggled for making contrary conto minus node. If the nection, the 3-b coarse calibrations are connected to the minus node and the 4-b fine calibrations are connected to the plus node. is connected for equalAdditionally, the dummy resistance izing the resistances of two nodes at the zero code. The load mismatch between plus/minus nodes is less than 1.6%, which is calculated by the distance between the two resistances at the plus/minus nodes, geometry of each resistance in the layout, and process parameters. The calibration range of the IP2 calibration block is designed as 0.07%–7.6% because the load resistance is 1 k and the in Fig. 4 is 24 k .

B. Baseband Block The baseband chain consists of filters and programmable gain amplifiers (PGAs) to provide required selectivity and gain. The performance of filtering, amplifying, and canceling the dc offset at the mixer output makes an effect on the linearity and noise characteristics of the receiver full path. In this design, the low-noise baseband amplifier with lowpass filtering and canceling dc offset is located at the mixer output to overcome noise contribution from the next stages and to remove large blocker signals efficiently at the same time. For sufficient channel selectivity with reasonable group delay, an eighth-order filter is employed. The simple master–slave artuning for corner-frequency tuning is chitecture with 4-b used. A 20% process variation can be covered. As shown in Fig. 5, the PGA circuit has been partitioned into three sub-blocks according to their functions, which are: 1) the differential gain amplifier; 2) the common-mode feedback (CMFB); and 3) the dc-offset corrector (DCOC) blocks [8]. The – ladder network is used as degeneration impedance and decibel-linear gain control.

Voltage-Controlled Oscillator (VCO)

The frequency synthesizer for this design requires the integration of a wide-band VCO to cover the whole range of GSM/EGSM/DCS1800/PCS1900 bands and the property of agile channel switching for GPRS application. To meet these contending requirements at the same time, the frequency synthesizer was designed with a FN phase-locked loop (PLL) using a – modulator (SDM). The synthesizer consists of two functional loops of a PLL and a frequency-locked loop. An adaptive frequency calibration (AFC) block is needed to tune the VCO near target frequency prior to the start of the phase lock. The AFC block compensates for variation in lock time depending on the distance of the target frequency from a free-running frequency in the wide-band VCO [3]. The programmable counter determines the division ratio of the prescaler dynamically to serve as a multimodulus divider for the multibit SDM (3-bit fourth-order SDM). The designed 3-bit fourth-order SDM employs an interpolative architecture with multiple feedback paths and metal-connected multipliers to implement the feedback coefficients [7]. The modulator showed good idle-tone property without additional dithering logic and, thus, exhibited good fractional spur performance. The modulator provides lower out-of-band phase noise, fine frequency resolution of 3 Hz, and agile switching time. The integrated loop filter was designed with a third-order was passive network, as shown in Fig. 6(a). The value of too large to have been integrated on silicon thus far. For integrating the synthesizer fully, we adopted the capacitance multiplier method in the loop filter, which is a well-known method for reducing area [9]. The equivalent expression of capacitor multiplier in Fig. 6(b) can be derived as (9) As a result, the effective capacitance is amplified by within the band . The 2.78-nF equivalent capacitance is implemented. Fig. 7 shows the integrated wide-band VCO. To increase the loaded factor of the LC tank and improve phase noise performance, we used bond-wire inductor of the package parasitic as the inductor of the LC tank. When designing a wide-band VCO, oscillation amplitude varies with respect to operating frequency at a constant tail current because of the variation of the loaded factor of the LC tank. This phenomenon affects phase-noise performance, which usually means that phase noise becomes worse as frequency goes up. To prevent this, we designed digital control scheme to the tail current by sharing the 6-bit control word for capacitor bank [5]. IV. MEASUREMENT The maximum 66-dBm IP2 in Fig. 8 is achieved at optimum code. After calibration, only 30-dBm IIP2 is improved into 66 dBm. It is more important that there is an optimum code without a local maximum code. The fusing cells are also employed because chip-to-chip and lot-to-lot code variations

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Fig. 6. (a) Loop filter configuration. (b) Self-biased capacitance multiplier [6].

= LO32+3

Fig. 8. Measured IIP2: two-tone frequency MHz and kHz, two-tone power dBm, receiver gain setting MHz (a) GSM/EGSM mode. (b) DCS/PCS mode

3

Fig. 7.

+70

= 030

LO32+ = 90 dB.

Integrated wide-band VCO circuit.

are serious. There should be no LO frequency component in the same band as the RF signal. However, the harmonic components of the LO generator during DCS/PCS mode operation deteriorates radiation characteristics. The radiated power at the input of LNA is less than 120 dBm in the GSM/EGSM mode and 94.5 dBm in the DCS/PCS mode. In Fig. 9, the NF of the receiver is measured by the -factor measurement method according to baseband frequency. In Fig. 10, the relative noise level of the EGSM band at the baseband output is measured by a vector signal analyzer (VSA). The NF results are confirmed by both measurement methods. Both measurements showed roughly similar results, around 2.2 dB, which is compensated by typical 1.9-dB surface acoustic wave (SAW) loss. The gain control range of the receiver shows approximately 100 dB. The gain step is 2 dB with less than 1-dB gain step error,

Fig. 9. Full-path NF measurement (Y -factor measurement method): single-point measurement by spectrum analyzer, kHz.

RBW = 10

as shown in Fig. 11. The three-stage DCOC works well in the maximum gain setting.

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Fig. 13. Typical locking process including AFC and phase locking. Fig. 10. Noise power measurement by VSA (EGSM mode, full-path 82-dB gain setting): Noise(ON) = 18:19 dBm, Noise(OFF) = 29:24 dBm, measured NF = 14:77 10 log(10^(11:05=10) 1) 1:9 = 2:2 dB.

0

0

0 0

0

Fig. 11. Gain table measurement of receiver full path: gain step = 2 dB, gain error < 1 dB.

Fig. 12.

Fig. 14.

Phase noise plot of the synthesizer: operation frequency = 1:39 GHz.

Fig. 15.

Chip photograph: 3.4 mm

Full-path selectivity measurement.

Fig. 12 shows a filter frequency response. The filter pole location can be controlled by 4 b and the group delay is 200 nS within 200-kHz bandwidth. Fig. 13 shows a typical locking process within 150 s, which are divided into AFC lock and phase lock. The integration of the loop filter can cause the close-in phase noise to be raised due to additional noise from the active circuits of the loop filter. In our case, the in-band phase noise is observed to be increased by 3–4 dB compared with the case of the external loop filter.

2 3.4 mm.

Fig. 14 shows the phase-noise plot when the synthesizer is locked at 1.397 GHz. It indicates that the in-band phase noise

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TABLE I SUMMARY OF MEASURED RESULTS

[5] J.-K. Cho, H.-I. Lee, K.-S. Nah, and B.-H. Park, “A 2-GHz wide band low phase noise voltage-controlled oscillator with on chip LC tank,” presented at the IEEE Custom Integrated Circuits Conf., Sep. 21–24, 2003. [6] I.-C. Hwang, H.-I. Lee, K.-S. Lee, J.-K. Cho, K.-S. Nah, and B.-H. Park, “A - fractional- synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver,” in IEEE VLSI Circuits Symp., Jun. 17–19, 2004, pp. 42–45. [7] K.-S. Lee, J.-H. Lee, M.-J. Yoh, and B.-H. Park, “A fractional- frequency synthesizer with a 3-bit 4th order – modulator,” in Proc. Eur. Solid-State Circuits Conf., 2002, pp. 803–806. [8] K.-S. Nah, Y.-S. Son, and B.-H. Park, “A CMOS differential dB-linear programmable-gain amplifier with DC-offset correction for zero-IF transceivers,” presented at the System-on-a-Chip Design Conf., Nov. 5–6, 2003. [9] S. Solis-Bustos, J. Silva-Martinez, F. Maloberti, and E. SanchezSinencio, “A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 12, pp. 1391–1398, Dec. 2000.

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SD

is less than 80 dBc/Hz. The out-band phase noise is less than 120 dBc/Hz at 400-kHz offset and shows uniform phase-noise performance obtained by adaptively controlling the bias current at two frequency points. The reference spur of 70 dBc is observed at 13-MHz offset. A chip photograph with a 3.4 mm 3.4 mm area is shown in Fig. 15. The location of each block is expressed and the remaining block is the test block. All measurement results are summarized in Table I.

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Young-Jin Kim was born in Seoul, Korea, in 1972. He received the B.S. degree in electrical engineering from the Kyung-Pook National University, Taegu, Korea, in 1995, and the M.S. and Ph.D. degree in electrical engineering from the Korea Advanced Instituted of Science and Technology (KAIST), Daejeon, Korea, in 1997 and 2002, respectively. His doctoral dissertation focused on the transceiver architecture about image rejection and spurious rejection. In 2002, he joined the Samsung Electronics Company Ltd., Kyungki-Do, Korea, where he is currently a Senior Engineer involved in the design of code division multiple access (CDMA) and GSM/GPRS wireless mobile application. He is also involved in the design of LNAs and down-conversion mixers for multimode CDMA and GSM/GPRS direct conversion transceivers in CMOS/BiCMOS technology.

V. CONCLUSION The symmetric system architecture, which can solve numerous problems of the DCR, was embodied and the DCR receiver fully operating in GSM/E-GSM/DCS/PCS band was implemented. The IIP2 estimation equation in an HM architecture was derived. The mismatches come from numerous origins, but we have shown the all mismatches could be calibrated by simply adjusting the load resistance, one of many origins. This phenomenon was analyzed by simple expansion and verified by measurement. For reducing external components, the stacked capacitor for an LPF and a loop filter for a PLL were implemented, and the internal VCO used bond-wire inductors. The minimum bill of materials (BOM) was achieved. REFERENCES [1] K. Kivekas, A. Parssinen, and K. A. I. Halonen, “Characterization of IIP2 and DC offsets in transconductance mixers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 11, pp. 1028–1038, Nov. 2001. [2] K. Kivekas, A. Parssinen, J. Ryynanen, J. Jussila, and K. Halonen, “Calibration techniques of active BiCMOS mixers,” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 766–769, Jun. 2002. [3] H.-I. Lee et al., “A fractionalfrequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/EGSM/GPRS/WCDMA applications,” in IEEE 29th Eur. Solid-State Circuits Conf., Sep. 2003, pp. 97–100. [4] D. Manstretta, M. Brandolini, and F. Svelto, “Second-order intermodulation mechanisms in CMOS downconverter,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 394–406, Mar. 2003.

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Young-Suk Son was born in Taegu Korea, in 1971. He received the B.S. degree in electrical engineering from the Kyung-Pook National University, Taegu, Korea, in 1994, the M.S. degree in electrical and electronics engineering from the Pohang University of Science and Technology, Kyungbuk, Korea, in 1996, and is currently working toward the Ph.D. degree in electrical engineering at the Korea Advanced Instituted of Science and Technology (KAIST), Daejeon, Korea. From 1996 to 2001, he was with the LG Semiconductor Company Ltd., Cheong-Ju, Korea, where he was an Associate Engineer with the System Large Scale Integration (LSI) Division. Since 2002, he has been with the Samsung Electronics Company Ltd., Kyungki-Do, Korea, where he is currently a Senior Engineer. His current research interests include high-speed, low-noise, and low-power analog integrated-circuit design techniques for wireless applications.

Victor N. Parkhomenko was born in Gomel, Belarus, in 1954. He received the Diploma and Doctoral degrees in electronics from the Moscow Institute of Physics and Technology, Moscow, Russia, in 1977 and 1986, respectively. He is currently with the Samsung Electronics Company Ltd., Kyungki-Do, Korea. His interests include RF and mixed-signal integrated-circuit design for wireless communications.

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In-Chul Hwang (M’00) received the B.S, M.S, and Ph.D. degrees in electronics engineering from Korea University, Seoul, Korea, in 1993, 1995, and 2000, respectively. From 2000 to 2001, he was a Post-Doctoral Research Associate with the University of Illinois at Urbana-Champaign (UIUC), where he was involved with advanced VCO structures and delay-locked loop (DLL)-based clock generators. In November 2001, he joined Samsung Electronics, Kyungki-Do, Korea, where he is a Senior Engineer involved in the design of sigma–delta FN PLLs and frequency planning for wireless local area networks (WLANs), GSM, etc. He currently leads the 2.5-G transceiver project. His current research interests are integrated RF transceivers having multiple standard options with special emphasis on CMOS RF circuit design. He is listed in Marquis’ Who’s Who in the World (2005). Dr. Hwang was the recipient of the First Prize of the LG Semiconductor Corporation’s 1999 semiconductor design contest.

Je-Kwang Cho was born in Taegu, Korea, in 1975. He received the B.S. and M.S. degrees in electronics engineering from Korea University, Seoul, Korea, in 1998, 2000, respectively. In 2000, he joined the Samsung Electronics Company Ltd., Kyungki-Do, Korea, where he is currently an RF Circuit Design Engineer. From 2000 to 2001, he designed up-conversion mixer and IF auto gain controller (AGC) circuits for universal mobile telecommunications system (UMTS) applications. Since then, he has been involved in the design of on-chip VCOs, TX driver amplifiers, and regulators for CDMA/GSM/GPRS/EDGE transceivers. His current research interests include CMOS/BiCMOS RF and mixed-signal circuits design for wireless communications systems. Mr. Cho was the recipient of the Korea University Presidential Top Honor Prize in 1998.

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Kyung-Suc Nah (M’03) was born in Seoul, Korea, in 1967. He received the B.S. degree in electrical engineering from the University of Virginia, Charlottesville, in 1988, and the M.S. degree in computer and systems engineering and Ph.D. degree in electrical engineering form Rensselaer Polytechnic Institute, Troy, NY, in 1990 and 1994, respectively. In 1994, he joined the Samsung Electronics Company Ltd., Kyungki-Do, Korea, where he is currently a Senior Engineer. He has participated in the design of analog integrated circuits for RF transceivers for CDMA and GSM/GPRS wireless mobile phones. In 2003, he became a Principle Engineer.

Byeong-Ha Park (M’98) received the B.S. degree from Hanyang University, Seoul, Korea, in 1984, and the M.S. and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1995 and 1997, respectively. His doctoral dissertation focused on the design of CMOS FN frequency synthesizers. From 1983 to 1992, he was with the Samsung Electronics Company Ltd., Kyungki-Do, Korea, where he focused on analog integrated-circuit design and tuner integrated circuits for video equipment. From 1992 to 1997, he was with the Georgia Institute of Technology, where he was involved with an analog working group. From 1996 to 1997, he was with Rockwell Semiconductor Systems (currently Skyworks Systems), where he designed PLL-based frequency synthesizers and RF integrated circuits for wireless mobile phones such as GSM and CDMA. In 1997, he rejoined the Samsung Electronics Company Ltd. as a Vice President in charge of the development of RF/analog front-end integrated circuits for wireless communications applications such as CDMA, GSM, Bluetooth, and WLAN. His research interests include analog circuitry of all types ranging from low-frequency analog to high-speed RF communications systems. His current research is focused on RF/analog integrated-circuit design.

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A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach Hossein Hashemi, Member, IEEE, Xiang Guan, Student Member, IEEE, Abbas Komijani, Student Member, IEEE, and Ali Hajimiri, Member, IEEE

Abstract—A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB. Index Terms—BiCMOS integrated circuits, phase-locked loops, phased arrays, radio receivers, silicon, voltage-controlled oscillators (VCOs).

I. INTRODUCTION

P

HASED ARRAYS are capable of beam forming and electronic steering by adjusting the relative phases of the signal received or transmitted by each antenna. In the past, the high price of discrete microwave modules limited the achievable complexity level of such systems for consumer applications. A low-cost fully integrated silicon-based phased-array transceiver facilitates widespread commercial applications such as ultrahigh-speed wireless communications and vehicular radar. The Federal Communications Commission (FCC), has allocated 250 MHz of bandwidth around the 24-GHz frequency for unlicensed industrial, scientific, and medical (ISM) applications, in addition to field-disturbance sensors, as well as fixed and point-to-point wireless operation [1]. The FCC has also opened up a 7-GHz window between 22-29 GHz for ultrawideband vehicular radar systems [2]. Consequently, research on 24-GHz range wireless technologies has accelerated, demonstrating various building blocks and single path receivers at this frequency [4]–[7]. Compared to the 2.4- and 5-GHz frequencies that are commonly used for today’s short-range wireless data communications schemes, the 24-GHz carrier frequency has a smaller

associated wavelength that reduces the required size of the common resonant-based antennas and their spacing in a multiple antenna scheme. The smaller antenna size will, however, result in a reduced collected power at these higher frequencies. A recent study of an indoor wireless channel in an office environment at a variety of carrier frequencies [8] reveals that, at 24 GHz, the large absorbance of walls and ceilings results in more isolation between multiple floors and allows for increasing the frequency reuse and overall system capacity. It also shows that the 24-GHz carrier frequency can support a higher data rate due to lower delay spreads. The excess path loss at 24 GHz is more or less comparable to the 2.4- and 5.2-GHz bands due to the waveguide effect inside the building at higher frequencies. To demonstrate the feasibility of a phased-array system on silicon and explore its advantages, we have implemented the first fully integrated 24-GHz phased-array receiver in silicon [3]. After a brief description of narrow-band phased arrays in Section II, we will focus on various architectural choices for a fully integrated phased-array receiver in Section III. The receiver architecture of an eight-path phased-array receiver based on a local-oscillator (LO) phase-shifting scheme will be presented in Section IV. Multiple LO phase generation and distribution are covered in Section V, followed by receiver array measured results in Section VI. II. NARROW-BAND PHASED ARRAYS When a plane electromagnetic (EM) wave arrives at an with respect to the normal to antenna array at an angle array plane, the signal is received by each antenna at a different time due to the spatial path differences. In general, an angledependent time delay at the receiver can compensate the arrival delay and effectively focus the beam in a desired direction. In a one-dimensional array, the effective beam angle is related to , the spacing the delay difference of two adjacent elements of two adjacent antennas , and the speed of light via (1)

Manuscript received April 23, 2004; revised August 11, 2004. This work was supported in part by the National Science Foundation and by the Lee Center for Advanced Networking. H. Hashemi is with the Department of Electrical Engineering—Electrophysics, University of Southern California, Los Angeles, CA 91030 USA (e-mail: [email protected]). X. Guan, A. Komijani, and A. Hajimiri are with the Department of Electrical Engineering, California Institute of Technology, Pasadena, CA 91125 USA (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.841218

With ideal delay elements following each antenna, the beam forming works independently of the frequency and bandwidth of the signal. Unfortunately, there are practical challenges to implementation of such broad-band tunable delay elements in the RF signal path, e.g., signal attenuation, noise, and linearity degradation, as well as signal dispersion. Fortunately, in many practical applications, such as wireless communications, the

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Fig. 1. Output signal constellation of an eight-path narrow-band phased-array receiver.

bandwidth of interest is a small fraction of the center frequency and, hence, a uniform delay (linear phase) is only required over this narrow bandwidth. One way to implement the delay is to approximate the uniform delay with a constant phase shift inside the signal bandwidth. This makes the carrier phase at different paths coherent, but because of the constant phase shift and, hence, zero group delay, it does not synchronize the baseband modulation signals. As the ratio of signal bandwidth to carrier frequency increases, this baseband time incoherence affects the signal integrity and results in constellation spreading. This signal degradation is independent of the mechanism and/or the architecture used to produce the phase shift. The effect can be best seen through the following example. Fig. 1 shows the simulated constellation of the received signal (without noise) for an eight-path phased-array receiver at bit rates of 1 and 10 Gb/s at the worst case incident angle of 90 with respect to normal, using a quadrature phase-shift keying (QPSK) modulation scheme with a carrier frequency of 24 GHz. A square-root raised cosine filter with a rolloff factor of 0.5 is used at both the transmitter and receiver for pulse shaping. A of 0.5 corresponds to a spectrum efficiency of 1.33 bits/s/Hz. As the direction of the beam becomes more oblique, the delay between the paths increases and so does the error introduced by constant phase-shift approximation. The constellation spreading is a function of the signal’s angle of arrival, ratio of signal bandwidth to the carrier frequency, and the modulation pulse shape. The error vector magnitude (EVM) is a measure of constellation spreading and quantifies the difference between the measured and ideal modulated signals. In a typical receiver, the EVM is degraded due to noise, nonlinearity, and mismatches between in-phase (I) and quadrature-phase (Q) paths. The approximation of propagation delay with a constant phase shift is another factor contributing to a higher EVM in phased-array systems. The EVM of the received signal is calculated for different signal bandwidths and angles of incidence and the result is plotted in Fig. 2. As can be noted, for a carrier of 24 GHz, even for bit rates as high as 1 Gb/s and an incidence angle of 90 (worst case), the level of EVM is lower than 2 , and the signal integrity is maintained without the need for any additional equalization. This figure shows the narrow-band phase-shifting approach to be a viable solution for wireless communications at 24 GHz. Of course, there is a gradual degradation of the constellation integrity as the signal bandwidth continues to increase.

Fig. 2. EVM for two signal bandwidths of 750 MHz (1 Gb/s) and 7.5 GHz (10 Gb/s) in an eight-path narrow-band phased-array receiver at 24 GHz.

Fig. 3. Simplified scheme of phase shifting at RF in a homodyne receiver.

As mentioned earlier, phase shifting can be performed at different stages, giving rise to different phase-array architectures. These architectural variations will be discussed below. III. PHASED-ARRAY RADIO ARCHITECTURES A. Signal Path Phase Shifting The most common method of adjusting the signal time delay is by approximating it with a variable phase shift at the bandwidth of interest in each signal path, as shown in Fig. 3. The phase shifters should have a relatively low loss across the bandwidth of the received signal so that they do not attenuate the received signal and degrade the overall signal-to-noise ratio. A low-loss and broad-band variable phase shifter at high frequencies is a challenging building block to implement in an integrated setting and is a source of active research [10], [11]. By phase shifting and signal combining at RF, other radio blocks are shared among the paths resulting in reduced area and power consumption. Additionally, since the unwanted interference signals are cancelled after signal combining, the dynamic-range (both linearity and noise figure) requirements of the following blocks are more relaxed, allowing them to trade this with other system requirements such as power consumption. If amplitude control

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Fig. 4. Simplified scheme of digital-array implementation in a homodyne receiver.

is needed (e.g., for null placement), it can be achieved by variable-gain low-noise amplifiers (LNAs) before or after the phase shifters at RF. Phase shifting and signal combining can also be performed after down-converting the received signals to an IF. Due to the additional signal amplification at the RF stages, phase-shifter loss will have a less deteriorating effect on receiver sensitivity in case it is performed at the IF stage. However, some of the aforementioned advantages, including a lower dynamic-range requirement for the RF mixer, become less effective. Moreover, the value of passive components (e.g., inductors and capacitors) needed to provide a certain phase shift is inversely proportional to the carrier frequency. Since the values of integrated passive components are directly related to their physical size (i.e., area), passive phase shifters at IF consume a larger area compared to the ones at RF. B. Digital Arrays The delay and amplitude of the received signal can be adjusted at the baseband using a digital processor (Fig. 4). Digital-array architecture is very flexible and can be adapted for other multiple antenna systems used for spatial diversity such as multiple-input multiple-output (MIMO) schemes [13], [14]. Despite its potential versatility, baseband phased-array architecture uses a larger number of components compared to the previous two approaches, resulting in a larger area and more power consumption. At the same time, since the interference signals are not cancelled before baseband processing, all the circuit blocks, including the power-hungry analog-to-digital converters, need to have a large dynamic range to accommodate all the incoming signals without distortion. Above all, handling and processing a large amount of data through multiple parallel receivers can be challenging even for today’s advanced digital technology. For instance, imagine a digital array of eight receivers where each has a 6-bit analog-to-digital converter that samples the signal with a 10-MHz channel bandwidth at twice the Nyquist rate. These numbers are on the low end of the acceptable range for a typical wireless system. Nevertheless, the baseband data rate of the whole system can be calculated to be 1.92 GB/s. As

Fig. 5.

Simplified scheme of phase shifting at the LO in a homodyne receiver.

a comparison, the fastest rate for sending the data into a personal computer using today’s peripheral component interconbits MHz Gb/s. This nect (PCI) standard is rate is almost halved when notebook computers are used (e.g., the IEEE1394 Standard supports 400 Mb/s). Alternatively, a very powerful digital signal processing (DSP) core can be used to process this large influx of data, but it is going to be bulky, power-hungry, and expensive in today’s technology. In short, until faster and more power-efficient digital data processing becomes available at a lower price, digital implementations still seems to be a more expensive solution for multiple-antenna systems. C. LO Path Phase Shifting As an alternative approach, one can indirectly vary the phase of the received signal by adjusting the phase of the LO signal used to down-convert the signal to a lower frequency. This is due to the fact that the output phase of a multiplier (or mixer) is a linear combination of its input phases, i.e.,

(2) Fig. 5 shows a simplified phase-array receiver that uses LO phase shifting. Phase shifting at the LO port is advantageous in that the phase-shifter loss does not directly deteriorate the receiver sensitivity. Additionally, the nonlinearity and loss of active phase shifters such as phase-interpolating implementations (e.g., [12]) can be more easily tolerated in the LO path compared to the signal path. However, since the undesired interferences are only rejected after the combining step at the IF, the RF amplifiers and mixers need to have a higher dynamic range than the ones in the signal-path phase-shifting scheme. The signal amplitude can be controlled using RF or IF variable-gain amplifiers (VGAs). This architecture is particularly attractive for silicon-based integrated systems due to the large number of transistors available

HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER

Fig. 6.

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Block diagram of the fully integrated 24-GHz phased-array receiver.

and the possibility of accurate multiple phase generation and distribution, which will be discussed in great details below. IV. 24-GHz PHASED-ARRAY RECEIVER ARCHITECTURE The implemented phased-array receiver employs an LO phase-shifting architecture for several reasons. Phase shifting and signal processing at baseband (i.e., digital arrays) was eliminated due to the larger chip area, power consumption, and the high demand on the baseband digital interface, particularly for the high data rates of interest. Passive variable phase shifters at 24-GHz RF will have a relatively higher loss due to ohmic and silicon substrate loss in integrated passive components (especially inductors and varactors). This loss in the signal path deteriorates the receiver’s overall sensitivity and can be minimized by providing more gain at the LNA preceding them. More importantly, the phase-shifter’s loss usually changes significantly with its phase shift that necessitates the use of RF VGAs with fine resolution to compensate these variations. Additionally, phase-shifter nonlinearity will be directly in the signal path, making the receiver more sensitive to a strong blocker. In contrast, the signal loss in the LO phase-shifting networks can be easily compensated by high-gain amplifiers (e.g., limiters) without the need for any amplitude tuning. The reason for this is that many RF mixer implementations (e.g., Gilbert type) perform better when driven to switch with a large amplitude at the LO port making their conversion gain less sensitive to the LO amplitude. This approach also makes it possible to generate multiple phases of an LO signal by efficient methods other than using phase shifters.

The aforementioned considerations led to the design of a phased-array receiver that uses different phases at the LO path. The block-diagram schematics of the 24-GHz phased-array receiver consisting of eight paths is shown in Fig. 6. The receiver uses a two-step down-conversion architecture with an IF of 4.8 GHz for two main reasons. Firstly, compared to single down-conversion schemes such as homodyne, a heterodyne-type receiver achieves more selectivity and gain control at multiple stages. Secondly, with the mentioned frequency planning, both LO frequencies can be generated in one synthesizer loop with the use of a divide-by-four block, as shown in the upper right part of Fig. 6. A single oscillator core generates 16 discrete phases (i.e., 4-bit resolution) that are used to control the phase of each path. The effect of using discrete phase compensation is discussed in Section V. A set of eight phase selectors (i.e., analog phase multiplexer) provides the appropriate phase of the LO to the corresponding RF mixer for each path independently. In other words, the LO phase for each path can be chosen irrespective of the phase of the other paths. The phase-selection data is serially loaded to an on-chip shift register using a computer interface. The image frequency of the first down-conversion at 14.4 GHz is attenuated by the narrow-band transfer function of the front-end (i.e., antenna and LNA). Since communication schemes around the image-frequency band are mainly low power, and due to the directionality of the phased-array receiver, no additional image-rejection provisions are introduced. The final down-conversion to baseband or very low-IF is done by a pair of quadrature mixers. The divide-by-four block that is used to generate the second LO will naturally produce I and Q signals to drive these mixers.

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Each RF path consists of two stages of low-noise amplification and a down-conversion mixer. The design of the 24-GHz front-end and receiver signal path is discussed in [9]. In Section V, multiple phase generation and distribution of the 19-GHz LO are described in detail.

V. MULTIPLE PHASE GENERATION AND DISTRIBUTION A. Quantized Phase Effects An on-chip LO generates 16 discrete phases of the LO that can either be directly applied to the RF mixers or interpolated between to generate additional intermediate phases in order to compensate the narrow-band phase shift of the carrier frequency at each path. This discrete method can only compensate the carrier phase shift at a few incidence angles precisely. For all other angles, the signal constellation at each received path is rotated with an amount equal to the value of phase quantization error. Clearly, the phase quantization error depends on the desired phase shift for each path, itself a function of the angle of incidence. Since the constellation at each received path is rotated differently, the combined signals are not added coherently, causing interference between the I and Q channels. Fig. 7 plots the EVM as a function of the angle of incidence when discrete phase shifts are used at the receiver for 8 (3 bit), 16 (4 bit), and 32 (5 bit) equally spaced phases. The signal has a bandwidth of 7.5 GHz and all the other simulation parameters are identical to the ones described in Section II. Using a 4-bit phase-shifting scheme with phase steps of 22.5 creates a peak EVM at an incidence angle of 70 , which is 1.5 times larger than the peak EVM generated if an LO with a continuous phase shift was available. For continuously adjustable phase shift, the peak naturally happens at an incidence angle of 90 , which corresponds to largest time delay between antennas. As a comparison, if a 3-bit phase shifting scheme with 45 phase steps was used, this peak occurs at incidence angle of 60 with a peak EVM value, which is 1.8 times the peak EVM value for a 4-bit scheme. The ratio of these peaks depends on the bandwidth of signal, and tends to increase for lower signal bandwidths. In Fig. 8, we show that using discrete LO phases does not sacrifice the beam-forming accuracy significantly. In fact, in the worst case, the signal loss is less than 1 dB in this 4-bit phaseshifting scheme for a full spatial coverage. B. Multiple Phase Generation At least two distinct methods to create various phases of an LO signal can be envisioned. In the first approach, only one phase is generated in the oscillator core (two phases considering differential signals). Phase shifters, phase interpolators, or similar blocks follow the oscillator in order to generate multiple phases of its output signal in a continuous or discrete fashion [12], [15]. These blocks can be narrow-band around the LO frequency and their loss is usually not a major concern in the LO path. In the second scheme, multiple phases are generated inside the oscillator core. Usually, this method results in discrete phases with a minimum resolution of , where is an integer number.

Fig. 7. EVM for continuous-phase 5-bit (one-step interpolation), 4-bit (raw resolution), and 3-bit (hypothetical) phase-shifting resolutions.

Fig. 8.

Array pattern with 4-bit phase-shifting resolution.

In our design, a ring connection of eight fully differential CMOS amplifiers forms the 19.2-GHz voltage-controlled oscillator (VCO) capable of generating 16 phases (Fig. 9) [16]. By flipping one of the connections, the number of amplifying stages is cut into half in a fully differential structure (top left connection of Fig. 9). These phases are then applied to phase selectors that can also function as interpolators generating a finer phase resolution. If no inductors at the amplifier outputs were used (e.g., differential pair with resistive load or CMOS inverters), each amplifier should have operated at a speed very close to the maximum operating frequency of transistors in the process causing challenges for a reliable startup. To better observe this, imagine that each amplifier could be modeled as a single-pole system (3) Each amplifier could produce a phase shift equal to . In the case of a 22.5 phase shift for each amplifier at 19 GHz, the pole frequency should be at least at 46 GHz. Since the gain of each stage should be more than one to guarantee oscillation startup, the unity-gain frequency approaches the device cutoff of each amplifier

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Fig. 9. Schematic of the 16-phase 19.2-GHz CMOS ring VCO.

Fig. 11.

Fig. 10.

Schematic of the VCO buffer.

frequency. Unfortunately, this imposes unnecessary restrictions on the individual transistor’s speed and current consumption. However, inductors can generate the necessary phase shift for each amplifier in the following fashion. At the oscillation , the equivalent parallel load causes a phase frequency shift of (4) In the case of a 22.5 phase shift for each stage, we should have (5) is the load quality factor and is equal to . For at 19 GHz in this process, or . In other words, each amplifier is almost tuned at the oscillation frequency. Each of the designed amplifier stages draws less than 3.2 mA from a 2.5-V supply resulting in a total power consumption of 63 mW for the oscillator. The center frequency can be tuned by changing the control voltage of differential MOS varactors. In order to make the high-frequency oscillator insensitive to loading, all the eight differential outputs are buffered prior to connection to other circuit blocks (Fig. 10). Emitter followers and differential pairs draw approximately 1 and 1.9 mA from a 2.5-V supply, respectively. This results in approximately 9.8 mW of power consumption for each buffer. where

Schematic of the third-order PLL.

An on-chip third-order phased-locked loop (PLL) with a loop bandwidth of 7 MHz is designed to lock the 19.2-GHz LO signal to a 75-MHz external reference signal source (Fig. 11). The integrated synthesizer uses a standard tri-state frequency phase detector [22] and a multiswitch charge pump [17] to minimize the reference feed-through. All divide-by-two blocks use a master–slave architecture and an emitter coupled logic for high-speed operation (Fig. 12). In order not to disturb the symmetry of VCO output phases, none of them are connected to any external pads for measurements. Nevertheless, we can verify the standalone VCO performance by picking up the high-frequency signal via a loop antenna placed on top of the chip. The frequency of the VCO can be continuously varied from 18.8 GHz to 21 GHz (Fig. 13). The slope of this transfer characteristic is 2.1 GHz/V at 19.2 GHz and reaches a maximum of 2.67 GHz/V close to 19.6 GHz. The output spectrum and phase noise of the VCO at 18.70 GHz is shown in Fig. 14. The VCO achieves a phase noise of 103 dBc/Hz at 1-MHz offset from the carrier. The measurement at higher offset frequencies is limited by the thermal noise floor of the spectrum analyzer used to measure the phase noise. The output spectrum and phase noise of the locked VCO are shown in Fig. 15. As can be seen, the phase noise stays constant within the loop bandwidth as the frequency changes. Our synthesizer phase-noise measurements have been limited by the phase noise of a synthesized sweeper that was used as the 75-MHz input reference signal. Better phase noise is expected if a crystal type reference is used. C. Systematic Phase Distribution It is essential that the 16 generated phases of the VCO are fed to each of the eight phase selectors in Fig. 6 with equal

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Fig. 12.

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Schematic of the high-speed divide-by-two blocks.

is the per-unit-length coupling capacitance to the adwhere jacent line. In general, the traveling wave can be considered as a linear combination of even- and odd-mode transmissions. Let and denote the characteristic impedances of and , respectively. The magnitude and phase of and are related to phase difference by

(8)

(9) Fig. 13.

VCO frequency versus control voltage.

amplitudes and delays. A symmetric binary tree structure, as shown in Fig. 16(a), is used to distribute LO phases. Each path consists of 16 metal lines running in parallel, similar to Fig. 16(b). Due to the strong EM coupling between the closely spaced metal lines, the symmetry not only depends on the path length, but also on the phase arrangement within the bus due to EM coupling between the lines. Several mechanisms, such as multimode excitation, coupling between nonadjacent lines, and boundary discontinuity of a finite array can cause phase and amplitude mismatches in the tree structures of Fig. 16(a) and (b). To understand the multimode excitation, consider two idenand running in parallel tical lossless transmission lines and , respectively. and driven by two signal sources If (even-mode excitation), the characteristic impedance of each line is given by

and form a complex conjugate pair, It can be seen that or 180 . which are equal only for EM crosstalk between nonadjacent lines can also cause phase and amplitude errors [19]. EM simulations are performed on an array of 16 on-chip transmission lines, as shown in Fig. 16(b). In our design, each line is 4- m thick, 5- m wide, and 200- m long with a 5- m edge-to-edge spacing. These lines are 12 m above the silicon substrate. Fig. 17 shows the extracted mutual inductance and coupling capacitance normalized to the inductance and capacitance , respectively. It illustrates that although the capacitive coupling is negligible between nonadjacent lines, the magnetic coupling is significant and the mutual inductance decreases very slowly with the distance. Fig. 16(b) shows three different phase arrangements in a transmission-line bus carrying multiple phases. If the array has an infinite number of lines, arrangement 1 provides the best symmetry, and the characteristic impedance can be calculated to be

(6) where , , and are per-unit-length capacitance to ground, inductance, and mutual inductance, respectively. On the other (odd-mode excitation), the characteristic hand, for a impedance of each line is given by (7)

(10)

and are the mutual inductance and coupling where capacitance between two lines with phase difference of .

HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER

Fig. 14.

VCO output spectrum and phase noise at 18.7 GHz.

Fig. 15.

Output spectrum and phase noise of the locked VCO.

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Fig. 17. Simulated coupling capacitor and inductor of the phase distribution line array of Fig. 16.

Fig. 16. array.

(a) LO phase distribution tree structure. (b) Phased transmission-line

However, in a finite array, the discontinuity at the edge and the inductive crosstalk between nonadjacent lines can produce significant mismatch at the outputs of arrangement 1. According to Ampere’s law, placing differential phase pairs as shown in arrangements 2 and 3 can minimize magnetic coupling. If is small (in this study, ), arrangement 3 has better phase- and amplitude-matching characteristics than the other two. This is because, in arrangement 3, the adjacent lines of two different pairs are closer in phase so that the capacitive

Fig. 18. Output voltage of the phase distribution line versus the source impedance value.

coupling between them is minimized. For a small , the characteristic impedance of the transmission lines in arrangement 3 can be approximated by the odd-mode impedance given by (7).

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Fig. 19. Comparison of different phase distribution configurations of Fig. 16(b). (a) Amplitude matching. (b) Phase matching.

Fig. 20.

Phase-selection circuitry.

To compare these three proposed phase arrangements, EM simulations were performed. Each of the three arrays is driven by 16 evenly spaced phases of a 19.2-GHz sinusoid. at both input and The transmission lines see a resistance output ports. Fig. 18 illustrates the voltage at the output . It verifies that port of the central wire as a function of using resistance values estimated by (10) and (7) results for arrangements 1 and 3, respectively. in maximum Fig. 19(a) and (b) shows the magnitudes and phases of the voltages at the 16 output ports for three arrangements. It can be seen that arrangement 3 exhibits less mismatch and, hence, is adopted in our 24-GHz phased-array receiver. The LO phase distribution lines transform the input impedance of the phase-selection circuitry to a new impedance at the LO buffer output node of Fig. 9. This transformed impedance should be made equal to the complex conjugate of the output impedance of the LO buffer to achieve the maximum power transfer and, hence, the largest LO amplitude at the input of phase-selection circuitry. Under a conjugate matched condition and neglecting the loss in distribution lines, the theoretical maximum achievable differential signal swing at the input of each phase-selection circuitry is (11)

Fig. 21.

Die microphotograph.

where and are the tail current and output resistance is the of the differential-pair buffer in Fig. 9, respectively; input resistance of each phase selector and is the number of phase selectors that are connected to a single LO buffer. In our implementation, the maximum swing based on (11) is approximately 140 mV. Due to the inaccuracies in prediction and

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Fig. 22.

High-frequency measurement setup.

Fig. 23.

Array measurement setup.

modeling of LO distribution lines in addition to their loss at 19 GHz, we expect the amplitude to be smaller in practice. However, the phase-selection circuitry discussed below is designed to maintain the required LO amplitude across RF mixers. D. Phase Selector/Interpolator As previously mentioned, each receiver path has independent access to all 16 phases of the LO. In order to minimize the complexity of the phase-selection circuitry, the appropriate phase of the LO for each path is selected in two steps. Initially, an array of eight differential pairs with switchable current sources and a shared tuned load are used to select one of the eight output pairs of oscillator (Fig. 20). A dummy array with complementary switching signals is used to maintain a constant load and prevent relative changes in phases while switching. In the basic mode of operation, at any given time, one of the LO phases is fed to the output of the main analog multiplexer, while other phases are fed to the output of the unused multiplexer. In the next step, another pair of cross-coupled differential pairs selects the sign bit, resulting in complete access to all LO 16 phases. The above-mentioned cascaded configuration reduces the necessary number of phase selectors (i.e., differential pairs in our case) from 2 to 2 2 for each path. The cross-coupled differential

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pairs at the output of each stage partially cancel the loss associated with the inductors and transistors’ outputs and, hence, increase the LO amplitude driving RF mixers. Phase interpolation can be achieved by turning on more than one tail transistor at any given time, forcing the output to be the vector sum of all the turned-on phases. A first-order interpolation can be achieved by turning two adjacent paths on simultaneously, doubling the phase resolution. VI. RECEIVER MEASUREMENT RESULTS The phased-array receiver is implemented in an IBM of 120 GHz 7HP SiGe BICMOS process with an HBT and 0.18- m CMOS transistor [20]. The die micrograph of the chip is shown in Fig. 21. The chip occupies an area of 3.3 mm 3.5 mm. For all measurements, the silicon chip has been mounted on a gold-plated brass substrate to provide a good grounding. A high-frequency Duroid board surrounds the chip and is used to connect the input, bias, and control signal lines using wire bonds (Fig. 22). Special attention has been paid to minimize the length of wire bonds at RF input and ground lines. All signal and bias lines are fed with standard subminiature A (SMA) connectors attached to the brass membrane.

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Fig. 24.

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Measured array patterns with two operating paths. TABLE I SUMMARY OF THE MEASURED PERFORMANCE

Fig. 25.

Measured array pattern with four operating paths.

Ideally, all the input paths have to be connected to on-board antennas [4] and the reception pattern of the array has to be measured. However, in order to separate the effect of the antenna array from the receiver, phase shifters in the input path are used to emulate the phase difference of signals at each path. Array measurements have been performed with a signal being fed to only four of the receiver paths. The setup used for array measurements is shown in Fig. 23. Receiver pattern measurements at eight different angles with only two operating paths are shown in Fig. 24. The difference between the peak and the null is 10–20 dB in all cases. This value is mostly limited by the mismatch in different paths and can be significantly improved with a gain control block in each receiver path for future implementations. In any event, using all

eight paths is expected to significantly improve this number, as well as make the beamwidth narrower. Theoretical receiver patterns and the measurements at three different angles are shown in Fig. 25 for a four-channel setup. Table I summarizes the measurement results. VII. CONCLUSION Moore’s 1965 seminal paper [21] ends with the following prediction: “It is difficult to predict at the present time just how extensive the invasion of the microwave area by integrated electronics will be . The successful realization of such items such

HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER

as phased-array antennas, for example, using a multiplicity of integrated microwave power sources, could completely revolutionize radar.” In this paper, almost 40 years later, we have demonstrated the first silicon-based fully integrated phased-array receiver at microwave frequencies for use in ultrahigh-speed wireless communication and radar applications.

ACKNOWLEDGMENT The authors would like to thank A. Natarajan, R. Aparicio, D. Lu, M. Morgan, and Prof. D. Rutledge, all of the California Institute of Technology, Pasadena, for valuable technical discussions. The authors acknowledge N. Wadefalk, and A. Shen, both of the California Institute of Technology, both of whom assisted in printed circuit board and microwave package preparation. The original version of the software for programming the phased-array receiver was provided by R. Chunara, California Institute of Technology.

REFERENCES [1] “Code of federal regulations, title 47–telecommunication, chapter I,” Federal Commun. Commission, pt. 15—Radio Frequency Devices, secs. 15.245 and 15.249, 2004. [2] “Code of federal regulations, title 47–telecommunication, chapter I,” Federal Commun. Commission, pt. 15—Radio Frequency Devices, secs. 15.515 and 15.521, 2004. [3] H. Hashemi, X. Guan, and A. Hajimiri, “A fully integrated 24 GHz 8-path phased-array receiver in silicon,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 390–391. [4] D. Lu, D. Rutledge, M. Kovacevic, and J. Hacker, “A 24 GHz patch array with a power amplifier/low-noise amplifier MMIC,” Int. J. Infrared Millim. Waves, vol. 23, pp. 693–704, May 2002. [5] X. Guan and A. Hajimiri, “A 24 GHz CMOS front-end,” in Eur. SolidState Circuits Conf. Tech. Dig., Sept. 2002, pp. 155–158. [6] E. Sonmez, A. Trasser, K. Schad, R. Abele, and H. Schumacher, “A single chip 24 GHz receiver front-end using a commercially available SiGe HBT foundry process,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Jun. 2002, pp. 159–162. [7] I. Gresham, A. Jenkins, R. Egri, C. Eswarappa, F. Kolak, R. Wohlert, J. Bennett, and J. Lanteri, “Ultra wide band 24 GHz automotive radar front-end,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2003, pp. 369–372. [8] D. Lu and D. Rutledge, “Investigation of indoor radio channel from 2.4 GHz to 24 GHz,” in IEEE AP-S Int. Symp. Dig., Jun. 2003, pp. 134–137. [9] X. Guan, H. Hashemi, and A. Hajimiri, “A fully integrated 24-GHz 8-path phased-array receiver in silicon,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2311–2320, Dec. 2004. [10] D. Parker and D. Zimmermann, “Phased-arrays—Part II: Implementations, applications, and future trends,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp. 688–698, Mar. 2002. [11] H. Zarei and D. Allstot, “A low-loss phase shifter in 180 nm CMOS for multiple-antenna receivers,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 392–393. [12] M. Chua and K. Martin, “1 GHz programmable analog phase shifter for adaptive antennas,” in Proc. IEEE Custom Integrated Circuits Conf., May 1998, pp. 11–14. [13] T. Rappaport, Wireless Communications: Principles and Practice. Upper Saddle River, NJ: Prentice-Hall, 1996. [14] T. Alamouti, “A simple transmit diversity technique for wireless communications,” IEEE J. Sel. Area Commun., vol. 16, no. 8, pp. 1451–1458, Oct. 1998. [15] T. Yamaji, D. Kurose, O. Watanabe, S. Obayashi, and T. Itakura, “A four-input beam-forming downconverter for adaptive antennas,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1619–1625, Oct. 2003.

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[16] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase-frequency detector,” IEEE J. SolidState Circuits, vol. 38, no. 1, pp. 13–21, Jan. 2003. [17] J. Cranincks and M. Steyaert, Wireless CMOS Frequency Synthesizer Design. Norwell, MA: Kluwer, 1998. [18] D. Ham, “Statistical electronics—Noise processes in integrated communication systems,” Ph.D. dissertation, Dept. Elect. Eng., California Inst. Technol., Pasadena, CA, 2002. [19] C.-K. Cheng et al., Interconnect Analysis and Synthesis. New York: Wiley, 2000. [20] A. Joseph et al., “A 0.18 m BiCMOS technology featuring 120/100 GHz (ft=f ) HBT and ASIC-compatible CMOS using copper interconnect,” in Proc. IEEE Bipolar/BiCMOS Circuits Technology Meeting, 2001, pp. 143–146. [21] G. E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, pp. 114–117, Apr. 1965. [22] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: PrenticeHall, 1998.

Hossein Hashemi (M’99) received the B.S. and M.S. degrees in electronics engineering from the Sharif University of Technology, Tehran, Iran, in 1997 and 1999, respectively, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 2001 and 2003, respectively. In 2003, he joined the Department of Electrical Engineering—Electrophysics, University of Southern California, as an Assistant Professor, where the core of his research constitutes the study of integrated communication circuits and systems. Dr. Hashemi is an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING. He was the recipient of the 2000 Outstanding Accomplishment Award presented by the von Brimer Foundation, the 2001 Outstanding Student Designer Award presented by Analog Devices, and a 2002 Intel Fellowship.

Xiang Guan (S’98) received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, in 1996, the M.Eng. degree in electrical engineering from the National University of Singapore, Singapore, in 2000, and is currently working toward the Ph.D. degree at the California Institute of Technology, Pasadena. From 1996 to 1997, he was a Research Assistant with the Integrated Circuits Group, Instituto Superior Tecnico, Lisbon, Portugal, where he was involved in the development of a data acquisition chip for electrocardiogram remote monitoring devices. During the summer of 2003, he was a Co-Op Researcher with the IBM T. J. Watson Research Center, Yorktown Heights, NY. Mr. Guan was the recipient of the 2002 Analog Devices Outstanding Student Designer Award.

Abbas Komijani (S’98) received the B.S. and M.S. degrees in electronics engineering from the Sharif University of Technology, Tehran, Iran, in 1995 and 1997, respectively, and is currently working toward the Ph.D. degree at the California Institute of Technology, Pasadena. His research interests include high-frequency power amplifiers, wireless transceivers, and phasedarray architectures.

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Ali Hajimiri (S’95–M’99) received the B.S. degree in electronics engineering from the Sharif University of Technology, Tehran, Iran, in 1994, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1996 and 1998, respectively. From 1993 to 1994, he was a Design Engineer with Philips Semiconductors, where he was involved with a BiCMOS chipset for global system for mobile communications (GSM) and cellular units. In 1995, he was with Sun Microsystems, where he was involved with the UltraSPARC microprocessor’s cache RAM design methodology. During the summer of 1997, he was with Lucent Technologies (Bell Laboratories), Murray Hill, NJ, where he investigated low phase-noise integrated oscillators. In 1998, he joined the Faculty of the California Institute of Technology, Pasadena, where he is currently an Associate Professor of electrical engineering and the Director of Microelectronics and Noise Laboratories. He is a cofounder of Axiom Microdevices Inc. He coauthored The Design of Low Noise Oscillators (Boston, MA: Kluwer, 1999). He holds several U.S. and European patents. His research interests are high-speed and RF integrated circuits. He was a Guest Editorial Board member of Transactions of the Institute of Electronics, Information and Communication Engineers of Japan (IEICE). Dr. Hajimiri is an associate editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is a member of the Technical Program Committee of the International Solid-State Circuits Conference (ISSCC). He has also served as an associate editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Part II: ANALOG AND DIGITAL SIGNAL PROCESSING. He is a member of the Technical Program Committees of the International Conference on Computer-Aided Design (ICCAD). He was a guest editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He is listed on the Top 100 Innovators (TR100) List. He was the recipient of the Gold Medal of the National Physics Competition and of the Bronze Medal of the 21st International Physics Olympiad, Groningen, The Netherlands. He was a corecipient of the ISSCC 1998 Jack Kilby Outstanding Paper Award and a three-time recipient of the IBM Faculty Partnership Award, as well as the National Science Foundation (NSF) CAREER Award.

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Dielectric Constant, Loss Tangent, and Surface Resistance of PCB Materials at -Band Frequencies

K

Victor N. Egorov, Vladimir L. Masalov, Yuri A. Nefyodov, Artem F. Shevchun, Mikhail R. Trunin, Victor E. Zhitomirsky, and Mick McLean

Abstract—This paper develops the theoretical approach and describes the design of a practical test rig for measuring the microwave parameters of unclad and laminated dielectric substrates. The test rig is based on a sapphire whispering-gallery resonator and allows the measurement of the following parameters: dielecof the dielectric substrate in the range from 2 to tric constant of the dielectric substrate in the range 10, loss tangent from 10 4 to 10 2 , and microwave losses of copper coating of the substrate in the range from 0.03 to 0.3 . Measurements of numerous commonly used microwave printed-circuit-board materials were performed at frequencies between 30–40 GHz and over a temperature range of 50 C to 70 C.

()

(tan )



+

Index Terms—Anisotropy, complex permittivity, dielectric resonator (DR), resonance spectrum, surface resistance, whispering-gallery (WG) modes.

I. INTRODUCTION

E

SSENTIAL parameters needed for the efficient design of integrated microwave circuits are dielectric properties ( and ), the degree of passive intermodulation, and the microwave copper resistance of the printed-circuit-board (PCB) substrate on which the active elements are mounted. As components are increasingly miniaturized and frequencies increased, the need for accurate dielectric measurements of low-loss substrate materials increases. The properties of these materials should be known over a wide temperature range. Resonant measurement methods represent the most accurate way of obtaining the dielectric constant and loss tangent with unclad thin materials [1], [2]. The high value of the unloaded of the resonator enables measurements of the quality factor smallest losses in the test materials. Methods based on bulk resonators have been developed in numerous laboratories and the results widely published [1]–[5]. The cylindrical cavity Manuscript received January 5, 2004; revised February 16, 2004. This work was supported by the National Measurement System Directorate of the U.K. Department of Trade and Industry. The work of Y. A. Nefyodov was supported by the Russian Science Support Foundation. V. N. Egorov and V. L. Masalov are with the East-Siberian Research Institute of Physico-Technical and Radioengineering Measurements, Irkutsk 664056, Russia (e-mail: [email protected]; [email protected]). Y. A. Nefyodov, A. F. Shevchun, and M. R. Trunin are with the Institute of Solid-State Physics, Russian Academy of Sciences, Chernogolovka, Moscow 142432, Russia (e-mail: [email protected]; [email protected]; [email protected]). V. E. Zhitomirsky and M. McLean are with Scientific Generics, Cambridge GB2 5GG, U.K. (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.841219

has been used to measure both the in-plane dielectric parameters for thin dielectric samples and surface resistance [6]–[8]. Howof bulk resonators does not ever, at room temperature, the exceed 10 in the millimeter-wavelength band. The open hemispherical resonator [3], [4], [9] is a very sensitive instrument for in-plane dielectric measurements of very low loss and flat specimens with diameters much greater than the wavelength. There are two problems with this approach: nonflatness of real samples and large resonator sizes, which limit the application of this technique for measurements in a wide temperature range. Microstrip-based tests [10] do not allow the dielectric and ohmic losses to be measured separately. The nonreproducibility of the rig connection impedance limits the accuracy of this method. A dielectric split resonator [11] made from thercylindrical mostable high-permittivity ceramic has been successfully used for in-plane dielectric film measurements at frequencies below 10 GHz, but it was found unsuitable for measurements at higher frequencies due to increased loss tangent in ceramic materials . and, hence, decrease of In all the above-mentioned methods, the interface surface of the specimen is placed along the microwave -field. At the same time, most PCBs operate with the electric field primarily normal to the plane of the sheet. An incident electromagnetic field should, therefore, have an electric-field component orthogonal to the sample surface. The sapphire disk “whispering at approximately 40 000 gallery” (WG) resonator [12] has at room temperature in the range of 40 GHz (wavelength of approximately 8 mm) and a typical diameter approximately 1.5 . There are two WG-mode types: quasi- (or ) and ) with a high value for a large azimuth quasi- (or . They can be used for dielectric substrate mode index measurements with orthogonal and tangential microwave -fields, respectively. A significant and universal problem with making dielectric measurements with an orthogonal field is the so-called “residual air-gap,” which exists due to the microroughness at the contact between the flat resonator and specimen surfaces. As a result, an effective “residual air gap” should be taken into consideration in the electrodynamic model of the measured structure. The goal of this paper is to evaluate both theoretically and experimentally the uncertainties of the sapphire disk WG dielectric-resonator (DR) technique for measurements of out-of-plane dielectric properties of thin materials using up to five different modes. Acceptable accuracy of measurement resonance

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Fig. 1.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

(a) DR 1 above a metallic plane with dielectric layer 3 inserted in between, the residual air gap 2 is also shown. (b) Dielectric layer in the split DR.

was provided for both extremely thin substrates with a thickness down to 30 m, as well as for very thick substrates with a thickness exceeding 1 mm. This is possible because the DR achieves a substantial filling factor value even with very thin substrates. A high- factor of the DR also helps to accurately measure very small changes to the resonance frequency. An accuracy of 1% for permittivity measurements of thin dielectric materials and a resolution of the order of 10 for their loss tangent has been shown at 40 GHz. Our test method also allows the measurement of the effective microwave surface resistance of laminated metal at the interface between the laminated material and dielectric.

is represented in the form of linear combination of standing - and -waves, which forms a hybrid standing or wave along the -axis. Transverse (on , coordinates) field distribution in gap 2, the dielectric layer 3 and top space 4 is assumed the same as in disk 1. The longitudinal wavenumand of the - and -waves, respectively, are the bers same and are equal to the longitudinal wavenumber of the hy. The boundary conditions brid wave in disk 1: , for inside and outside field within the limits components at define the equation of a circular “dielectric post resonator” with single axis anisotropy [13]

II. ELECTRODYNAMICS A. Measurement Structure Basic Below we describe the resonance mode structure of a dielectric cylinder [see Fig. 1(a)] with diameter and height , which is separated from a metallic plane by a dielectric layer of height and a gap of height . If the component of the electric is an even function of , then the field in the -direction (metallic surface) behaves as a so-called “electric plane wall” for which the following boundary conditions are satisfied: . The electrodynamic structure of the modes in such a case is equivalent to the modes of the split DR with a dielectric layer of double height in the slot [see Fig. 1(b)]. The relative permittivity of a DR is characterized by a tensor

(1)

where , , , and are the Bessel and Hankel functions of the order and their derivaand are the inside and outside transverse tives, , , and wavenumbers, respectively, . For , this equation is reduced into the equation of an isotropic “dielectric post resonator” [14], [15]. For

which determines its electric properties, and by a scalar for are related to the the magnetic properties. Symbols and components of in the direction along the optical (geometrical) axis and in the plane perpendicular to this axis, respectively. We for the isotropic dielectric layer, and , for the use , ambient isotropic space, which includes both the top space 4 and gap 2. We analyze the electromagnetic resonance modes by the method of approximate separation of variables with one-mode approximation of the fields at all fractional volumes of the resonator [9]. In this approach, an electromagnetic field at frequency inside the resonator within the boundaries

modes with odd longitudinal index , the boundary conditions at , , , and result in the characteristic equation

[13]

(2)

EGOROV et al.: DIELECTRIC CONSTANT, LOSS TANGENT, AND SURFACE RESISTANCE OF PCB MATERIALS AT

where , dinal wavenumbers in regions

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, and are the longitu(Fig. 1)

Fig. 2. Schemes for measurements of: (a) ", tan  , (b) R (d) q , R .

The set of (1) and (2) defines the values , , and , which depend on the relative dielectric sample per. Equation (1) does not explicitly depend mittivity on and for determination of , one should solve (1) and (2) and at the measured resonant in series with the values of frequencies. The electrodynamic model described by (1) and (2) does not take into account an influence of the part of the dielectric sample , , i.e., outside the resonator. If this sample at volume is taken properly into account, the resonant frequencies will decrease and, hence, (1) and (2) (which do not take this into account) will overestimate values for . The dielectric sample volume outside the resonator is exposed to only a small part of the total electromagnetic energy. This enables one to correct the value of the dielectric constant by the perturbation method

, (c) Q

, and

and resonance modes. The frequency dispersion of low-loss dielectric samples in such a narrow frequency range is usually negligible in comparison with the uncertainty of the real measurements. The problem of the unknown residual air gap makes an additional contribution to inaccuracy, which slightly reduces the measured value . Uncertainty of the measurements depends on the frequency and is reduced with the increase of the azimuth index of the resonant mode. directly absorbed by the The electromagnetic power sample [dielectric layer 3 in Fig. 1(b)] and electromagnetic stored in the sample layer are connected by the energy , where is the dielectric loss relationship angle of a measured sample. In the ordinary approximation of the additive contribution of different losses, the power is connected with the total power loss and the unloaded of the resonator by the following equation: quality factor

(3) and , where are the total resonator energy and electric field energy outcan be found by numerical side the resonator disks. Factor differentiation of (1) and (2) with respect to the ambient media is of the order of 0.01–0.02. permittivity [16]. B. Dielectric Permittivity and Loss-Tangent Measurements of Nonmetallic Substrates For measurements of the dielectric permittivity and loss tangent of the substrate, the foil is removed from both sides of the microwave PCB sample. The sample (substrate) is clamped between the plates of the split DR [see Figs. 1(b) and 2(a)]. In the experiment, the values of the resonant frequencies of modes are determined. The basic data for calculating the dielectric permittivity of the sample using (1) and (2) are: 1) resonant of modes with known azimuth index ; frequency 2) dimensions and of the DR; 3) sapphire dielectric per, ; and 4) the thickness of the sample. The mittivities value of a residual air-gap is determined by the roughness of the surfaces of both the measured sample and the faces of the resonator and cannot be measured directly. One can estimate this value from the condition that the measured value should not be dependent on the frequency of the measurements in a narrow frequency interval, which is defined by the frequen, , cies of neighboring (by azimuth index)

(4) is a dielectric loss power in the resonator dielecwhere is a partial quality factor of these disks, tric disks only, is the radiant loss, and is the radiant quality factor of the resonator. It is easy to satisfy the condition by choosing dimensions of the DR. In this case, from (4), we get (5) is a filling factor of the resonator. The where can be obtained from the value of the stored envalue of ergy by integrating the field components over the corresponding volumes of the resonator

(6) where is the energy of the electric or magnetic field stored in the -volume of the resonator. Another way to calcuis by numerical differentiation of the function late

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obtained from (1) and (2) at measured resonant frequencies of the resonator with a sample inside [16] (7) The quantity in (5) is the unloaded quality factor of the resonator with a hypothetical sample, which has the dielectric . The permittivity of the real sample, but has no loss is close to the unloaded of the split resonator value without a sample and can be found from the equation (8) where , , and . Here, and are the energy stored in the longitudinal and transverse components of electric field in the sapand are phire disks with a sample between them; the components of the loss tangent tensor of sapphire in the direction of optic axis and in the plane perpendicular to this axis, respectively. and are Similarly to (6) and (7), the coefficients calculated via integration of longitudinal and transverse components of vector or by numerical differentiation of the resonant frequency dependences

Fig. 3. Measurement cell diagram.

From (10)–(12), we get the surface resistance of the laminated dielectric sample

(9) (13) C. Surface-Resistance Measurements Under Dielectric To measure the surface resistance of the metallic foil on its interface with the dielectric material, disk 1 is pressed against unclad surface of the sample [see Figs. 1(a) and 2(d)]. In order , we will use values of the filling factor for to determine the laminated sample and the unloaded quality factor of of an unclad sample measured in the resonator, as well as accordance with the procedure described in Section II-B. Similarly to (4) and taking into account (5), the unloaded quality of the resonator pressed onto the dielectric sample factor with a copper laminated layer is defined as (10) where is the total loss power, factor due to ohmic loss in the metallic foil, and loss power, which is equal to

is a partial is an ohmic

(11) where is the tangential component of the microwave magnetic field on the surface of the metal; is the surface area at the interface between the metallic foil and the dielectric layer. Total stored in the resonator can be found by integrating energy the magnetic-field energy in partial resonator volumes

(12)

. Neglecting the where contribution of the longitudinal component of the magnetic field is calculated in [17]. in (12), a geometric factor III. EXPERIMENT A. Measurement Cell A simplified schematic of the measurement cell is shown in Fig. 3. A sample is placed between polished sapphire disks with diameter of 12.51 mm and a height of 2.54 mm, which are arranged inside a thick-wall aluminum shield with an inner diameter of 25 mm. The diameter of the shield was chosen to exclude any influence of the metal wall on either the resonant frequencies or the quality factors of the sapphire disks. The aluminum shield is placed inside a thermal isolation chamber. The lower sapphire disk is attached to the post guide and clamped to the sample through the spring with the pressure of approximately three bars. We took special care to prepare “nearly ideal” DRs. Sapphire disks were cut from the same piece of a carefully oriented sapphire single crystal of very high chemical purity. The dimensions of both disks were identical to an accuracy of within 1 m. The -axis of both the disks was perpendicular to their faces. The faces of each disk were parallel with the accuracy better than 1 m across the disks diameter. Surface roughness reduced to 2 nm after polishing. The deviation from flatness of each surface was less than 0.5 m across each disk’s diameter. As a result, the problem of the “residual air-gap” was significantly reduced even when the two disks were brought into contact without a “soft” dielectric film between them. Moreover, because these two disks

EGOROV et al.: DIELECTRIC CONSTANT, LOSS TANGENT, AND SURFACE RESISTANCE OF PCB MATERIALS AT

in close mechanical contact constitute a near-perfect monolithic crystal, no measurable splitting of the resonance curves has been detected. To simplify the process of changing dielectric samples, the post guide is designed to be axially moveable and have no radial free play. The aluminum shield with sapphire disks and sample can be moved toward and away from the microwave microstrip line by a stepper motor (not shown) in order to tune the coupling of the transmission line with the DR. The latter was included into the line as a directional coupler. Coupling change had not resulted in the resonance frequency shift. Semirigid coaxial cables connect the microstrip to standard 2.9-mm connectors outside the cell thermal isolation. The measuring cell is placed in a stainless-steel vacuum cryostat with a temperature control system. For low-temperature measurements, liquid nitrogen is evaporated from the cryostat and its vapor flows around the resonator and the aluminum shield. Rhode&Schwarz SMR-40 and Gigatronics-8541C were used as the generator and power meter, respectively. B. Experimental Procedure and Results The procedure for taking measurements of dielectric constant, loss tangent, and surface resistance of one-side laminated dielectric samples is described below. First, the resonant spectrum (resonator output microwave power versus frequency ) of the upper DR is measured. For this measurement, the lower resonator is moved away by a maximum distance of 3 mm from the upper resonator and does not influence the measured quantities. Thereupon we determine the resonant frequencies , loaded quality factors , and coupling coefficients of modes of the upper resonator in the range GHz. At room temperature C, the unloaded quality factors of the modes with are equal to 35 790, 40 850, 45 360, 44 970, 37 080, respectively. The maximum quality factor corresponds to the mode. The further increase of azimuth index results in a drop in due to the increase of the sapphire loss tangent. The measured values of resonant frequencies and quality factors for modes of the single resonator at different temperatures within the range C are saved into computer memory as calibration constants. We proceed with similar measurements with both sapphire disks pressed together and determine the values of resonant fremodes of this doubled quencies and quality factors for resonator at the same temperatures C. The results obtained are also stored into the computer memory for further calculations of the dielectric constant, loss tangent, and surface resistance of laminated dielectric samples. The measured frequencies of the double resonator are significantly lower than corresponding frequencies of the single one. The difference decreases when the azimuth number increases. For example, it is equal to 4406 MHz for and 3637 MHz for . This approximately corresponds to the theoretical calculations for the double resonator. Results of theoretical calculations using (1) and (2) are shown in Table I along with the measured resonant frequencies. In these calculations, we used sapphire permittivities of

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TABLE I RESONANT FREQUENCIES OF HE

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MODES

and [18]. The discrepancy between the calculated and measured frequency values does not exceed 1.3% for the single resonator and 0.5% for the doubled resonator. Dielectric sheet samples used for measurements of the dielectric constant and loss tangent have planar dimensions 25 50 mm , thickness up to 1 mm, and a one-side copper-laminated square surface of 25 25 mm . The sample is held with force between the upper and lower resonators [see Fig. 2(a)] providing the sapphire disks are in the center of the square 25 25 mm surface. When the sample is clamped inside the split DR, the are shifted down compared measured resonant frequencies to the frequencies of the single resonator. The problem of identification of the mode arises. Fortunately, however, modes are the highest, and secfirst the coupling of the ondly, the frequency difference between the nearest and modes is almost independent for . If the mode identification was correct, the results of calculations for all the modes give very close values for both the permittivity and loss tangent. The mean values of and are calculated using results obtained for all modes. The results are weighted according to the uncertainty of the resonance curve fitting. Examples of such results obtained for a set of samples at room temperature are shown in Table II. Below mean values, the coefficients and are shown. These values are introduced as correction coefficients describing the influence of the absolute uncertainty (in micrometers) in measurements of the thickness of the sample. The error for permittivity can then be found by the formula . Similarly, the error in the loss tangent value is given by . The test rig allows measurements at different temperatures. Such measurements are made in a similar fashion to those at room temperature. The only difference is that preliminary calibration of the resonance frequencies and quality factors of the single and double resonator are performed in the range of temperatures. The temperature is stabilized at exactly the same values for measurements with and without the sample, which helps to compensate almost completely for the temperature dependence of sapphire dielectric properties. An example of and temperature dependences obtained by this scheme for two samples (NY9220 0.01 in and Tly5a0200) is presented in Figs. 4 and 5, respectively. The method of surface resistance measurements of the laminated dielectric samples is illustrated in Fig. 2(b)–(d). Two approaches are possible here, which are: (I) direct measurements and (II) measurements using a calibrated reference copper foil. Let us consider them separately.

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TABLE II SAMPLES PARAMETERS AT ROOM TEMPERATURE

Fig. 4. Temperature dependences of permittivity in NY9220 and Tly5a0200 (Taconic).

2 0.01 in (Nelco)

(I) The direct method of the surface resistance measurements is based on the calculation of using (13). In this case, the sample is placed into the resonator as shown in Fig. 2(d), and

Fig. 5. Temperature dependences of loss tangent in NY9220 and Tly5a0200 (Taconic).

2 0.01 in (Nelco)

the quality factor of the upper resonator with laminated dielectric sample is measured. Using the previously determined quality factor of the resonator without a sample and the sample loss tangent (obtained by measuring the nonclad

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of this sandFig. 2(c)]. The quality factors wich structure are measured for different resonance modes. The values at resonant frequencies are found by the following formula: (15)

Fig. 6. Evolution of resonance curves of the HE mode in the sample RO3003 0.0 (Rogers) for direct measurement of surface resistance.

2

part of the sample as described above), the value of tained as follows:

is ob(14)

where filling factor is calculated for the laminated sample. Factor has appeared before as a denominator in the righthand side of (13). It characterizes an ohmic loss in the metal lamination at the interface with dielectric material. The geometric factor is calculated elsewhere [17]. Fig. 6 illustrates the frequency shifts and quality-factor variations for measurements of at the mode. The accuracy of the direct surface resistance measurements strongly depends on the thickness and the dielectric losses in the substrate. To obtain reliable results by this method, ohmic losses in the laminated metal must be comparable to dielectric losses. In case of copper foil, the applicability criteria for direct measurements can be written as , where the thickness of the substrate is expressed in m. In Table II, the data of the fourth, fifth, seventh, eighth, and ninth samples were obtained by direct measurements. (II) The second method to measure the surface resistance of laminated dielectric samples involves a few extra steps, which are shown in Fig. 2(b)–(d). Step 1) The smooth copper metal foil is chosen as a reference. The surface resistance of the foil (if unknown) is determined by measuring the quality factor of the upper resonator pressed against this foil [seeFig. 2(b)]. Using measurements at the resonance frequencies of several modes, the surface resistance can be calculated as , where . The expression for follows from (13) for the resonator located on a metallic plane without dielectric layer , but with an effective air-gap . In turn, an effective air gap can be found from (1) and (2), and the condition of equality of double resonator frequency to the frequency of the upper resonator on the metal surface (see [17]). Step 2) The reference foil is placed underneath the uncoated region of the dielectric sample, and they are held together between the disks of the split resonator [see

In contrast to determined during the first in (15) determine the step, the quality factors losses in the reference foil, taking into account the electromagnetic-field distribution in the structure of Fig. 2(c). Step 3) The same distribution of the field occurs in the geometry shown in Fig. 2(d). The quality factor related to the ohmic loss at the interface between the metal foil and the dielectric material is determined in accordance with (14). The surface resistance of the metal foil at the resonant frequencies of the modes is found as , where the value of the reference foil measured at the first step is linearly approximated to the appropriate frequency of the third measurement step. The advantage of method (II) in comparison with the direct method (I) is that the surface resistance does not depend on the calculation of the geometric factor in (13) and, hence, the accuracy of method (II) is higher, especially for thicker samples. IV. CONCLUSION In this paper, we have presented a novel technique for the measurement of the dielectric constant and loss tangent of dielectric substrates with reasonable accuracy for substrate thickness ranging from 10 to 1000 m. For the first time, a resonance technique with the electric field of electromagnetic radiation orthogonal to the surface of the substrate has been demonstrated. The high sensitivity for thin samples is made possible by the high unloaded quality factor of the “WG” resonator and substantial filling factor value. There is no fundamental restriction on the maximum thickness of substrate, while its dielectric permittivity is lower than the one of sapphire. When the dielectric thickness increases, the measurement structure shown in Fig. 1 gradually turns to a single DR on the dielectric half-space. Experimental results do not show any influence of the “residual air-gap” problem, which is explained by the optical-quality sapphire polishing, elasticity, and/or flatness of most of the samples, as well as by pressure applied between the sapphire disks and substrate. The method also provides measurements of the surface resistance of metal films. The presence of copper film in the resonator reduces the quality factor by an order of magnitude. The accuracy of surface resistance measurements at the interface between a metallic film and a dielectric layer is strongly influenced by the substrate thickness, dielectric constant, and loss tangent. and , the 15%–20% accuIn the case of was shown experimentally for dielectric substrate racy of mm. Such materials are widely used thickness at 30–40 GHz.

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ACKNOWLEDGMENT The authors are grateful to S. V. Ryzhkov, V. N. Kurlov, and G. E. Tsydynzhapov, all of the Institute of Solid-State Physics, Russian Academy of Sciences (ISSP RAS), Moscow, Russia, for technical help. The authors would like to thank Rhode&Schwartz, Munich, Germany, for providing the long-term loan of a microwave signal generator. The authors would also like to express their gratitude to the numerous companies that provided samples for their validation measurements. This list includes, but is not limited to Rogers, Chandler, AZ, Labtech, Presteigne, U.K., Spemco, Portsmouth, U.K., Isola, Cumbernauld, U.K., Sheldahl, Nelco, Lannemezan, France, Bookham Technology, Caswell, U.K., and Celestica, Telford, U.K. REFERENCES [1] J. Baker-Jarvis, B. Riddle, and M. D. Janezic, “Dielectric and magnetic properties of printed wiring boards and other substrate materials ,” NIST, Boulder, CO, Tech. Note 1512, 1999. [2] J. Baker-Jarvis, M. D. Janezic, B. Riddle, C. L. Holloway, N. G. Paulter, and J. E. Blendell, “Dielectric and conductor-loss characterization and measurements of electronic packaging materials,” NIST, Boulder, CO, NIST Tech. Note 1520, 2001. [3] A. L. Cullen and P. K. Yu, “The accurate measurement of permittivity by means of an open resonator,” in Proc. Roy. Soc., vol. 325, London, U.K., 1971, pp. 493–509. [4] R. J. Cook and R. J. Jones, “Comparison of cavity and open resonator measurements of permittivity and loss angle at 35 GHz,” IEEE Trans. Instrum. Meas., vol. IM-23, no. 4, pp. 438–442, Dec. 1974. [5] M. N. Afsar and K. J. Button, “Millimeter-wave dielectric measurement of materials,” Proc. IEEE, vol. 73, no. 1, pp. 131–153, Jan. 1985. [6] H. E. Bussey, “Standards and measurements of microwave surface impedance, skin depth, conductivity and ,” IEEE Trans. Instrum. Meas., vol. IM-9, no. 3, pp. 171–175, Sep. 1960. [7] A. Hernandes, E. Martin, and J. M. Zamarro, “Resonant cavities for measuring the surface resistance of metals at band frequencies,” J. Phys. E., Sci. Instrum., vol. 19, pp. 222–225, 1986. [8] G. Kent, “Nondestructive permittivity measurement of substrates,” IEEE Trans. Instrum. Meas., vol. 45, no. 1, pp. 102–106, Feb. 1996. [9] L. A. Vainshtein, Open Resonators and Open Waveguides (in Russian). Moscow, Russia: Sov. Radio., 1966. [10] IPC-TM-650 Test Methods Manual, Inst. Interconnecting and Packaging Electron. Circuits, Northbrook, IL, 1997. [11] T. Nishikawa, K. Wakino, H. Tanaka, and Y. Ishikawa, “Precise measurement method for complex permittivity of microwave dielectric substrate,” in Precise Electromagnetic Measurements Conf. Dig., Tsukba, Japan, 1988, pp. 155–156. [12] V. F. Vzjatyshev et al., A Possibility of Superhigh Quality Resonator Creation (in Russian). Moscow, Russia: Trudy Moskovskogo Energeticheskogo Instituta, 1978, vol. 360, pp. 51–57. [13] V. N. Egorov and I. N. Mal’tseva, “Azimuthal modes in anisotropic dielectric resonator” (in Russian), Electronnaja Technika. Serija 1, Electronica SVCH, no. 2, pp. 36–39, 1984. [14] B. W. Hakki and P. D. Coleman, “A dielectric resonator method of inductive capacities in the millimeter range,” IRE Trans. Microw. Theory Tech., vol. MTT-9, no. 4, pp. 402–410, Jul. 1960. [15] W. E. Courtney, “Analysis and evaluation of a method of measuring the complex permittivity and complex permeability of microwave insulators,” IEEE Trans. Microw. Theory Tech., vol. MTT-19, no. 8, pp. 476–485, Aug. 1970. [16] V. F. Vzjatyshev and V. S. Dobromyslov, The Mutual Correlation of Characteristics in Multilayer Waveguides and Resonators (in Russian). Moscow, Russia: Trudy Moskovskogo Energeticheskogo Instituta, 1979, vol. 397, pp. 5–7. [17] V. N. Egorov, V. L. Masalov, Y. A. Nefyodov, A. F. Shevchun, M. R. Trunin, V. Zhitomirsky, and M. McLean, “Measuring dielectric properties and surface resistance of microwave PCB’s in the -band,”, [Online]. Available: http://xxx.lanl.gov/ftp/cond-mat/papers/0312/0 312 151.pdf, 2003. [18] V. N. Egorov and A. S. Volovikov, “Measuring the dielectric permittivity of sapphire at temperatures 93–343 K,” Radiophys. Quantum Electron., vol. 44, no. 11, pp. 885–891, 2001.

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Victor N. Egorov was born in Irkutsk, Russia, in 1950. He received the M.Sc. degree in physics and electronics from Irkutsk State University, Irkutsk, Russia, in 1972, and the Ph.D. degree in microwave theory and technique from the Moscow Power Engineering Institute, Moscow, Russia, in 1985. Since 1975, he has been with the East-Siberian Research Institute of Physico-Technical and Radioengineering Measurements (VS NIIFTRI), Irkutsk, Russia, where he is currently a Deputy Director. His research interests are mainly concerned with low-noise microwave generators, high- resonators, and microwave parameters measurements.

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Vladimir L. Masalov was born in Arkhangel’sk, Russia, in 1941. He received the M.Sc. degree in physics and electronics from the Novosibirsk Electrotechnical Institute, Novosibirsk, Russia, in 1967. Since 1976, he has been with the East-Siberian Research Institute of Physico-Technical and Radioengineering Measurements (VS NIIFTRI), Irkutsk, Russia, where he is currently a Senior Researcher. His research interests are mainly concerned with low-noise microwave generators and superconducting resonators and DRs.

Yuri A. Nefyodov was born in Chernogolovka, Russia, in 1977. He received the B.Sc. and M.Sc. degrees in physics and mathematics and Ph.D. degree in condensed matter physics from the Moscow Institute of Physics and Technology (MIPT), Dolgoprudny, Russia, in 1998, 2000, and 2003, respectively. Since 1997, he has been with the Institute of Solid State Physics, Russian Academy of Sciences (ISSP), Chernogolovka, Moscow, Russia, where he is currently a Researcher. His current research interests are mainly concerned with electrodynamics of anisotropic medium, especially with high- superconductors.

Tc

Artem F. Shevchun was born in Leipzig, Germany, in 1979. He received the B.Sc. and M.Sc. degrees in physics and mathematics from the Moscow Institute of Physics and Technology (MIPT), Dolgoprudny, Russia, in 2000 and 2002, respectively. Since 2000, he has been with the Institute of Solid-State Physics (ISSP), Chernogolovka, Moscow, Russia, where he is currently a Junior Researcher. His current research interests are mainly concerned with microwave electrodynamics of superconductors.

Mikhail R. Trunin was born in Moscow, Russia, in 1958. He received the M.Sc. degree in theoretical physics from Gorky State University, Nizhnii Novgorod, Russia, and the Ph.D. and D.Sc. (habilitation) degrees in condensed matter physics from the Institute of Solid-State Physics (ISSP), Chernogolovka, Moscow, Russia, in 1985 and 1999, respectively. Since 1980, he has been with the ISSP, where he is a Head of the Laboratory of Electron Kinetics. Since 2000, he has been a Professor with the Moscow Institute of Physics and Technology (MIPT), Dolgoprudny, Russia. His current research interests are concerned with low-temperature physics, superconductivity, and high-frequency electrodynamics of solids.

EGOROV et al.: DIELECTRIC CONSTANT, LOSS TANGENT, AND SURFACE RESISTANCE OF PCB MATERIALS AT

Victor E. Zhitomirsky was born in Kharkov, Ukraine, in 1967. He received the B.Sc. and M.Sc. degrees in physics and mathematics and the Ph.D. degree in condensed matter physics from the Moscow Institute of Physics and Technology (MIPT), Dolgoprudny, Russia, in 1987, 1989 and 1993, respectively. He was a Researcher with the Institute of SolidState Physics (ISSP). He has held post-doctoral positions with the Max-Planck Institute für Festkörperforschung, Stuttgart, Germany and Oxford University, Oxford, U.K. Since 2001, he has been with the Science and Technology Group, Scientific Generics (SG), Cambridge, U.K., an integrated business and technology consultancy, where he is currently a Senior Consultant. His current research interests are concerned with microwave techniques and disruptive technologies in the area of semiconductors and opto-electronics.

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Mick McLean was born in London, U.K., in 1948. He received the B.Sc degree in logic with physics and M.Phil in computer simulation modeling from the University of Sussex, Sussex, U.K., in 1970 and 1979, respectively. Since joining the Science and Technology Group, Scientific Generics (SG), Cambridge, U.K., a business and technology consultancy group, in 1989, he has managed over 300 assignments involving technology management for private- and public-sector clients. He is also Director and General Manager of Technical Investment Services Ltd.—the specialist “due diligence” company within the Generics Group launched in January 2001.

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Novel T-Rail Electrodes for Substrate Removed Low-Voltage High-Speed GaAs/AlGaAs Electrooptic Modulators JaeHyuk Shin, C. Ozturk, S. R. Sakamoto, Y. J. Chiu, and Nadir Dagli, Senior Member, IEEE

Abstract—A novel traveling-wave electrode utilizing capacitively loaded T-rail elements was developed for low-voltage high-speed substrate-removed GaAs/AlGaAs electrooptic modulators. Electrodes with varying dimensions were fabricated and characterized. Electrode phase velocity, characteristic impedance, loss coefficient, and capacitive loading were extracted from the measured -parameters up to 40 GHz. Electrode was also simulated using a finite-element solver. The measured and calculated electrode capacitance values were found to be in excellent agreement, showing that the electrode can be precisely designed. Approaches were outlined to provide a group velocity-matched very high-speed modulator electrode suitable for a low drive-voltage substrateremoved GaAs/AlGaAs electrooptic modulator. Index Terms—Electrooptic modulators, GaAs modulators, optical modulators, microwave transmission lines.

I. INTRODUCTION

H

IGH-SPEED intensity modulated fiber-optic transmission systems require low-voltage high-bandwidth external modulators, preferably with adjustable chirp. Currently, LiNbO modulators have the most mature technology and are commercially available [1]. However, there is still need to reduce the drive voltage and improve the frequency response of existing modulators. Modulators in other material systems, such as compound semiconductors and polymers, are actively being researched for this purpose. Compound semiconductor modulators have well-known advantages such as the possibility of integration with sources. They also have other properties that help toward building a superior modulator. Compound semiconductors have very small index dispersion between microwave and optical frequencies. Therefore, in traveling-wave designs, velocity matching requires slowing the microwave signal. This is the opposite of what is required in traveling-wave LiNbO modulators. Velocity slowing can be achieved by using Manuscript received January 5, 2003; revised April 13, 2004. J. Shin and N. Dagli are with the Electrical Engineering Department, University of California at Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: [email protected]; [email protected]). C. Ozturk was with the Electrical Engineering Department, University of California at Santa Barbara, Santa Barbara, CA 93106 USA. He is now with Sabanci University, 34956 Istanbul, Turkey (e-mail: [email protected]) S. R. Sakamoto was with the Electrical Engineering Department, University of California at Santa Barbara, Santa Barbara, CA 93106 USA. He is now with the Lockheed-Martin Management and Data Systems, San Jose, CA USA (e-mail: [email protected]) Y. J. Chiu was with the Electrical Engineering Department, University of California at Santa Barbara, Santa Barbara, CA 93106 USA. He is now with the National Sun Yat-Sen University, Kaohsiung 804, Taiwan, R.O.C. Digital Object Identifier 10.1109/TMTT.2004.840735

capacitively loaded slow-wave electrodes. Such designs allow high electric fields overlapping very well with the optical mode. This possibility combined with the refractive index value higher than LiNbO results in a low drive voltage, even in bulk GaAs. Another significant advantage is due to epitaxial growth and advanced processing. For example, using substrate removal techniques, one can process both sides of an epitaxial layer. This enables the fabrication of an ideal push–pull modulator. Taking advantage of these properties, we recently demonstrated a novel substrate-removed (SURE) GaAs/AlGaAs electrooptic modulator [2]. Even with a very conservative design, this of 8.7 V cm, which is similar device had a drive voltage to LiNbO modulators. However, the electrode design was not suitable for high-speed operation. Here, we provide the results of the first experimental study of a wide-bandwidth slow-wave electrode that is suitable for high-speed SURE modulators. In Section II, general design guidelines for traveling-wave electrooptic modulators are given. Next, our electrode design that satisfies all these requirements is introduced. This is followed by the description of the fabrication of this electrode and experimental results. Finally, conclusions of this work are presented. II. TRAVELING-WAVE ELECTROOPTIC MODULATOR DESIGN GUIDELINES For successful utilization of optical modulators in system applications, there is a long list of requirements. This list definitely includes wide bandwidth, low drive voltage, low insertion loss, low wavelength and temperature sensitivity, and low cost. Some of these requirements, such as the drive voltage and bandwidth, are coupled and, usually, compromises are necessary. A well-established approach to very wide electrical bandwidth modulators with low drive voltage is the so-called traveling-wave design. In such a design, the electrode is designed as a transmission line. Therefore, electrode capacitance is distributed and does not create an RC limit on the modulator speed. The small-signal modulation response of a traveling-wave modulator whose electrode is terminated by its characteristic impedance is given as [3]

0018-9480/$20.00 © 2005 IEEE

SHIN et al.: NOVEL T-RAIL ELECTRODES FOR SUBSTRATE REMOVED LOW-VOLTAGE HIGH-SPEED GaAs/AlGaAs ELECTROOPTIC MODULATORS

where

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expressed using the well-known transmission-line equations as (1)

and are the loss coefficient and length of the electrode, respectively. is the electrical frequency and is the speed and are the microwave and optical of light in vacuum. indices and are related to the microwave and optical velocities through well-known expressions. To maximize the bandwidth, microwave and optical velocities should be matched. Our earlier work identified these velocities as the optical group and microwave phase velocity [4], [5]. Based on (1), if there is no velocity mismatch, 3-dB bandwidth will be at the frequency where the total electrode loss becomes 6.34 dB. Therefore, a low-loss and velocity-matched electrode is essential for the realization of a very wide-bandwidth traveling-wave modulator. of a Mach–Zehnder electrooptic interThe drive voltage ferometric modulator with push–pull electrodes (in which applied voltage increases the index a certain amount in one arm and decreases exactly the same amount in the other arm of the interferometer) is given as (2) is the mode effecwhere is the wavelength of operation, is the electrooptic coefficient, is the electrode tive index, gap, and is the overlap between the optical mode and the appropriate component of the applied electric field. For compound -oriented substrate, the approsemiconductors grown on a direction or perpriate electric-field component is in the pendicular to the substrate. This electric field modulates the TE polarized optical mode due to bulk electrooptic effect. There is no modulation for the TM polarized optical mode. Based on this discussion, the following requirements should be satisfied to take full advantage of the traveling-wave idea. 1) Propagation loss of the optical guide should be low so that a long modulator can be realized. This helps to significantly reduce the drive voltage, as seen in (2). 2) Electrode phase velocity should be matched to optical group velocity. The electrodes should not have dispersion; in other words, the electrode group and phase velocities should be the same. This eliminates the velocity mismatch and the electrode can be made very long. In III–V semiconductors, velocity matching requires slowing the microwave velocity. Optical group velocity , which is the target electrode is known for a given material system. phase velocity For example, GaAs/AlGaAs material system at 1.55 m has a group index around 3.5, which corresponds to cm/ns

(3)

Furthermore, if the desired electrode characteristic impedance is , the capacitance per unit length and of the electrode can be inductance per unit length

as

(4) As an example, assume a 50- electrode with 8.57-cm/ns phase velocity. The required and values are then pF/cm and

nH/cm

(5)

3) Electrode microwave loss coefficient should be low so that a long modulator can be realized. As described earlier, total electrode loss should be lower than 6.34 dB at the desired 3-dB bandwidth point. 4) For efficient modulation, a good overlap between the optical mode and vertical component of the microwave electric field is needed. In other words, in (2) should be as close to one as possible. 5) Push–pull drive should be possible to reduce the drive voltage a factor of two. This also makes chirp zero. 6) Electrode gap should be as small as possible to generate as large an electric field as possible for a given voltage. However, this should be achieved without making electrode capacitance and loss, as well as optical loss, excessively large. should be increased as 7) The electrooptic coefficient much as possible without increasing optical loss. Conditions 1) and 3) are hard to realize when doped layers are present. One can reduce the optical and microwave loss drastically using unintentionally doped self-depleting GaAs/AlGaAs layers, as we demonstrated earlier [6], [8]. Using undoped layers makes condition 4) difficult to realize unless the growth substrate is removed. By removing the growth substrate, independent electrodes can be placed directly on the top and bottom of an optical waveguide. This makes it possible to apply -oriented electric field overlapping very well with the opa tical mode. Conditions 5) and 6) are also difficult to realize in an optimum way if the high dielectric constant growth substrate is present. If the substrate is removed, the electrodes at the top and bottom of the optical waveguide can be independently biased. This allows applying the same voltage magnitude with opposite polarity across the arms of an interferometer, and the direction of the electric field between the arms can easily be reversed. Hence, true push–pull operation can be realized. If the substrate were present, changing the electric-field direction between the arms would require a biasing scheme, which doubles the voltage required [14]. Furthermore, the electrode gap becomes the same as the epilayer thickness, hence, it can easily be reduced significantly. Therefore, for a given voltage, the vertical component of

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Fig. 3. Electrical equivalent circuit of the electrode.

Fig. 1. Top longitudinal schematic of the electrode and details of its top and cross-sectional profiles.

a ground–signal–ground (G–S–G) coplanar waveguide periodically loaded by tiny capacitors. The unloaded line is formed on a polymer layer, which is on a transfer substrate. In this case, the polymer and transfer substrate are benzocylcobutene (BCB) and semi-insulating (SI) GaAs, respectively. The tiny capacitors that periodically load the unloaded line are formed in between the “T-rails” placed on the top and bottom of each single-mode semiconductor waveguide, as shown in Fig. 1. The two waveguides form the arms of a Mach–Zehnder-type modulator. These waveguides are formed on an epilayer removed from its growth substrate. Such SURE waveguides with very low optical propagation loss were realized earlier, as both stand alone waveguides [6] or as parts of SURE modulators [2]. The topside and backside T-rails are connected to the signal and ground electrodes of the unloaded line using narrow stems, respectively. In this design, epilayer thickness is the same as the electrode gap. Hence, very accurately controlled narrow electrode gaps are possible. The periodical loading of the unloaded line with these tiny capacitors form a slow-wave transmission line [7]. The equivalent circuit of the resulting electrode is shown in Fig. 3. and are the inductance, capacitance, resistance, and conducis tance per unit length of the unloaded transmission line. the capacitance per unit length due to capacitive loading on one is due to the resistance of the arm of the modulator, and stems. One can express as (6)

Fig. 2. Cross-sectional profile of the optical waveguide with top and bottom rails.

the electrical field is maximized. Condition 7) can be realized by using quantum wells of appropriate composition. In this study, we present an electrode design to satisfy all these requirements, except for condition 7), and yield modulators with superior characteristics. However, the given electrode can also be used with an appropriate material design satisfying condition 7). III. DEVICE DESCRIPTION Figs. 1 and 2 show the details of the top and cross-sectional views of the microwave electrode, respectively. The electrode is

where is the width of the topside rail, is the overall thickness of the epilayer, is the length of the rails, is the period of the loading, is the length of the electrode, is the number is the fill factor. is a scaling factor that of periods, and accounts for the fringing fields as well as the geometrical details of the epilayer between the rails. We previously used such capacitively loaded slow-wave electrodes in the design and fabrication of traveling-wave electrooptic modulators [8], [9]. Our previous results indicate that periodic loading is mainly capacitive and the inductance per unit length of the loaded line is almost identical to that of the unloaded line. We can then express the characteristic and the phase velocity of the loaded line as impedance

and (7) is typically 50 . should be chosen The target value of as the optical group velocity of the semiconductor optical waveis known, one can choose a suitable guide. If the value of and values. unloaded line geometry with the required

SHIN et al.: NOVEL T-RAIL ELECTRODES FOR SUBSTRATE REMOVED LOW-VOLTAGE HIGH-SPEED GaAs/AlGaAs ELECTROOPTIC MODULATORS

The first step in the design is to choose the appropriate as low as possible, should be kept as epilayer. To keep small as possible, as seen in (2). This requires tight vertical confinement, which is achieved by maximizing the index step between the core and upper and lower claddings of the optical waveguide. In a GaAs/AlGaAs material system, this can be achieved by choosing the core as GaAs and the Al content of the claddings as high as possible. This choice also helps to since high Al-content AlGaAs layers have a lower reduce dielectric constant. In our design, the upper and lower claddings are chosen as Al Ga As. The core and cladding thicknesses are then chosen such that optical mode is entirely confined in the semiconductor layers and the overlap of the optical mode with the metal electrodes is minimized. This is essential to minimize the optical propagation loss. This condition is achieved by choosing the core layer as thick as possible to increase the confinement. The upper limit is the cutoff thickness of the second-order TE slab mode. The cladding thickness is then increased until the overlap of the optical mode with the metal layers is minimized. The criterion for the minimum overlap value is found considering the optical propagation loss due to metal electrodes. This loss is calculated using the complex refractive index of the metal and a perturbation analysis. An excess optical propagation loss of 0.1 dB/cm was used as the criteria. The resulting epitaxial design is shown Fig. 2. It has a 0.44- m-thick GaAs core layer surrounded by 0.75- m-thick Al Ga As upper and lower claddings. The next step is to choose the width of the rib waveguide. This value was chosen as 4 m, mainly due to lithographic considerations. Once the width is determined, the etch depth of the rib for single-mode operation can be calculated. The first cut calculation was done using the effective dielectric-constant method, which gives a conservative estimate. The value found this way was verified using beam propagation method analysis. The result was a rib etch of 0.4 m. Once the epi thickness and waveguide width were determined, the T-rail capacitance was estimated using (6) with and different T-rail widths. For a given T-rail width, this value defines the upper limit since the effect of rib etching and the lower dielectric constant of upper and lower claddings are not taken into account. Once this value was estimated, capacitance and inductance per unit length of the unloaded line were calculated using (7). The values were then converted into line dimensions using wellknown transmission-line design equations [10]. This exercise resulted in different line dimensions. Using these calculations, we determined a parameter space to experimentally determine the optimum electrode geometry. We used two different topside rail widths of m and m. The bottom rails widths corresponding to these top rail widths were chosen as 2 and 4 m, respectively. The period of loading was chosen as 100 m. Since a slow-wave transmission line also works as a filter, we need to make the Bragg frequency as high as possible so as not to have a dispersive electrode. This choice makes the Bragg frequency in the several hundred gigahertz range [11], hence, there are no dispersive effects in the range of frequencies investigated in this study. We kept the fill factor at 0.9 to keep the drive voltage as low as possible. The width of the signal line was chosen as 40 m. A wider center conductor results in a lower microwave loss, but increases the unloaded line

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capacitance. Furthermore, a wider center conductor requires further separation between the arms of the interferometer. This results in longer Y-branches to keep the optical loss minimum, which makes the device longer. 40 m was estimated to be a reasonable compromise. The main electrode gap was chosen as 80 m mainly to reduce the unloaded line capacitance as much as possible. IV. DEVICE FABRICATION Fabrication steps are shown in Fig. 4. Fabrication starts with the molecular beam epitaxy (MBE) growth of the designed epilayer. This epilayer is unintentionally doped and is self depleting due to Fermi level pinning at the surfaces. This results in very low conductivity and the entire epilayer behaves as a dielectric with slight loss for alternating fields of frequency in excess of 10 Hz [2]. Next, the 4- m-wide waveguides were fabricated using reactive ion etching (RIE) of the semiconductor in a BCl /SiCl gas mixture. The resultant profile at the end of this step is shown in Fig. 4(a). The etch mask used was hard-baked photoresist and the etch depth was 0.4 m. This was followed by topside electrode fabrication. The process was done in two steps. First, T-rails with short stems were fabricated using liftoff, as shown in Fig. 4(b). The metal used in this step was 200 Ti/5000 Au evaporated by e-beam, which formed Schottky contacts. The epilayer was then etched in the field regions slightly into the AlAs etch stop layer, as shown in Fig. 4(c), using a mixture of H PO : H O : H O 1 : 14 : 200. This step removed the epilayer, except for the areas where optical guiding is needed. The wet etch also gave sloped sidewalls, which ensured that the connecting partial electrodes would not break when going over the mesa etch. The next step was to form the partial electrodes, which connect the front T-rails to the back electrodes. These partial electrodes were formed using liftoff. In order to obtain good liftoff, a thick deep UV photoresist known as SF-11 was used to planarize the uneven surface. Regular photoresist was spun on the 2.5- m-thick SF-11 layer and was patterned using regular photolithography. The patterned photoresist was used as a mask to expose SF-11 under a deep UV light source. After developing SF-11, 200Ti/15 000- Au was deposited by e-beam. An overnight bath in the SF stripper lifted off the patterns, as shown in Fig. 4(d). The epilayer was then transferred to another GaAs substrate using a BCB layer as glue. This was followed by spray etching the growth substrate. The details of this process were outlined in [2] and [6]. With the removal of the growth substrate, processing of the backside epilayer was possible. Using standard lithography, the backside T-rails and electrodes were patterned using liftoff. The electrode was 200- Ti/5000- Au evaporated by e-beam, which formed Schottky contacts. Separate microwave calibration standards were also fabricated. A 6- m-thick BCB layer was spun and cured on a piece of SI GaAs substrate and 200Ti/5000- Au calibration standards were patterned using the standard liftoff technique. V. EXPERIMENTAL RESULTS Microwave measurements were made using the HP8510 vector network analyzer. Using a thru-reflect-line (TRL) microwave calibration scheme, the input/output probe pads

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Fig. 5. Measured s-parameters for the electrode with r = 3 m and w = 4 m. The reference impedance level for the measurements was 94 .

Fig. 6. Phase velocity v different rail dimensions.

Fig. 4. Processing steps used in the fabrication. (a) Waveguide etch. (b) Deposition of the top rails. (c) Removal of the epitaxial layer where not needed. (d) Deposition of the partial electrode. (e) Gluing of the device onto a transfer substrate. (f) Substrate removal. (g) Deposition of the bottom rails and the rest of the electrode.

were calibrated out. A typical plot for the ters is shown in Fig. 5.

- and

-parame-

calculated directly using the s-parameters for two

One technique to determine the line parameters is to convert -parameters and then the measured -parameters into -parameters to calculate the microwave phase use these velocity , microwave loss , and the loaded line character[12]. The loaded line capacitance and inistic impedance and . We will refer to this ductance can be found from as the direct extraction technique. The results obtained this way are shown in Fig. 6. was found to be 6.0 0.4 cm/ns and 7.2 0.6 cm/ns for m, m) and T-rail width combinations of ( m, m), respectively. However, a reliable ( could not be extracted by this procedure. is very value of sensitive to reflection -parameters and , which are rela- and -parameters tively weak. Even a small change in the due to resonances originating from small reflections shifts the around the true value considerably. However, we measured can obtain the crucial parameters as follows. The unloaded line and unloaded line capacitance was calculated inductance nH/cm and pF/cm for electrodes to be sitting on 9.2- m-thick BCB on SI GaAs using a previously developed program [13]. It was also previously found that the inductance is almost exactly the same for loaded and unloaded structures [8]. Thus, assuming that the loaded line inductance is the same as the unloaded line inductance, one can determine the

SHIN et al.: NOVEL T-RAIL ELECTRODES FOR SUBSTRATE REMOVED LOW-VOLTAGE HIGH-SPEED GaAs/AlGaAs ELECTROOPTIC MODULATORS

TABLE I SUMMARY OF RESULTS OBTAINED USING DIRECT EXTRACTION TECHNIQUE

additional capacitance per arm as

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THE

due to the T-rails using (7)

(8) is found, the impedance of the loaded line can Once be calculated using (7). Table I shows the results obtained this way for different T-rail dimensions. and A different approach was also used to determine . One can convert the -parameters to -parameters -parameters are reusing the well-known expressions. lated to the complex propagation constant and characteristic through impedance

Fig. 7. Experimental and fitted value of jAj as a function of frequency obtained using the curve-fitting technique.

(9)

(10) Furthermore,

can be written as

with and

(11)

Equations (9)–(11) were fitted to the experimental data using and as fitting parameters. Once the fitting parameters are found, the line parameters can be calculated using (4) and (11). We refer to this as the curve-fitting technique. Fig. 7 using this shows the directly extracted and the curve-fitted technique. The fit is quite good up to 30 GHz. The frequency variation of the line parameters obtained this way is shown in Fig. 8 and the results are summarized in Table II. As expected, narrower rails have smaller loading capacitance. This results in less velocity slowing and higher characteristic impedance. The microwave loss is mainly due to the conductor loss of the unloaded line. The additional resistance due to stems increases the loss slightly. In this case, the loss coefficient is high since the electrode metal is only 0.5- m thick. This loss can be reduced significantly by increasing the metal thickness. The resonances in the -parameters proved to be detrimental in obtaining a better fit, as well as directly extracting . They

Fig. 8. Frequency variation of phase velocity v , characteristic impedance Z , microwave loss coefficient , and phase constant obtained using the curve-fitting technique. v and values directly extracted from the measured s-parameters are also shown. In this case, r = 3 m and w = 4 m. TABLE II SUMMARY OF THE RESULTS OBTAINED USING THE CURVE-FITTING TECHNIQUE

arise due to reflections in the electrode. Calibration should help to reduce the effect of reflections up to the reference planes. The resonances due to reflections at the reference planes are spaced

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approximately 3 and 3.5 GHz depending on T-rail dimensions. However, additional resonances were also observed. These additional resonances are thought to originate from the GaAs epilayer underneath the electrode. The electrode turns 45 away at both ends to minimize the overlap of the probe pads with optical waveguides at the input and output. The electrode in the bent section is on top of the BCB. However, there is a small region between the probe pads and main electrode where the electrode crosses over the semiconductor epilayer, as shown in Fig. 1. This creates a big dielectric constant step and, thus, reflections, which is thought to be the source of additional resonances appearing in the -parameters. Since calibration standards did not include the epilayers, it was not possible to calibrate out these reflections. They can be calibrated out using a calibration standard with epilayers buried in the BCB. Alternatively, one can reduce these reflections by tapering the epilayer in such a way that the microwave field gradually “feels” the epilayer, hence, reducing sharp reflections. The modeling was also used to calculate the measured parameters. As described earlier, unintentionally doped semiconductor epilayer behaves as a slightly lossy dielectric at frequencies over a few hertz. Schottky electrodes can then be modeled as regular electrodes on dielectric material. Hence, we can carry out a quasi-static analysis by numerically solving the Laplace’s equation for the given geometry. In the solutions, a commercially available software package was used.1 This package allows an adaptive finite-element solution, which allowed us to model the entire electrode accurately. Fig. 9 shows the overall mesh and the mesh in between the T-rails. As seen in this figure, a submicrometer mesh was possible over the optical waveguide, where the electric field is the highest. The resulting electrostatic potential distribution on the optical waveguide is shown in Fig. 10. Once the potential was found, the total charge on the electrode and line capacitance was calculated. Subtracting the unloaded line capacitance from the total electrode capacitance, dividing by 2, and multiplying by was obtained. The calcu0.9 to account for the fill factor, lated values were listed along with the experimental values in Table I. The agreement between the experimental values deduced using two different techniques and the calculated value are excellent. These results show that we can design the appropriate electrode very accurately. It is obvious that the additional capacitance due to the T-rails is too high, which lowered the values of and below and 8.57 cm/ns. There are three their target values of 50 approaches to reduce this value. One is to reduce the length of the T-rails. However, this comes at the expense of reduced effective electrode length, which means the drive voltage will be higher. The second approach is to reduce the unloaded line capacitance. This can be done using a low dielectric-constant substrate such as quartz and/or increasing the low dielectric-constant polymer bonding layer thickness. However, since the rail capacitance is almost the same as the desired capacitance per unit length value, shown in (5), this approach only helps to improve 1MATLAB Partial Differential Equations Toolbox, The Mathworks, Natick, MA.

Fig. 9. Adaptive mesh used in the simulations: (a) over the entire electrode and (b) over the optical waveguide.

Fig. 10.

Electrostatic potential over the optical waveguide.

values somewhat. The third approach could be to and reduce by reducing the width of the rails. This is clearly demonstrated in Tables I and II. However, to maintain a good overlap with the optical mode, the width of the optical waveguide should also be reduced. This requires a more strongly confined waveguide, which can be fabricated using substrate removal techniques. Using a combination of these three approaches, an optimum design could be possible. However, even with the current design, one can still match the velocity at the expense of electrode impedance. This requires reducing the inductance of the unloaded line. This may not be a bad compromise provided that the electrode can be terminated with a matched termination. For example, using pF/cm as determined in this experiment [see (4) and (7)] and assuming that the velocity of the unloaded coplanar line is

SHIN et al.: NOVEL T-RAIL ELECTRODES FOR SUBSTRATE REMOVED LOW-VOLTAGE HIGH-SPEED GaAs/AlGaAs ELECTROOPTIC MODULATORS

given as , we can calculate and values under the velocity matching condition. This, in turn, value. In this calculation, if we allows us to calculate the assume , i.e., without polymer bonding layer, we obtain . If we use this velocity-matched 18- electrode with a matched termination, there will not be a standing wave on the line. Even if this electrode is driven by a 50- source, 76% of the available power from the source will be transferred to the electrode. This is the worst case estimate, and using the techniques outlined above, a more favorable situation can be obtained. In this electrode study, there was not a full modulator since of input and output Y-branches were missing. However, the a full modulator can be estimated using (2) for the waveguide and design shown in Fig. 2. Using m/V, m at 1.5 m, one obtains a of 3.7 V cm.

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[8] S. R. Sakamoto, R. Spickermann, and N. Dagli, “Narrow gap coplanar slow wave electrode for travelling wave electro-optic modulators,” Electron. Lett., vol. 31, no. 14, pp. 1183–1185, Jul. 1995. [9] R. Spickermann, S. R. Sakamoto, M. G. Peters, and N. Dagli, “GaAs/AlGaAs travelling wave electrooptic modulators with an electrical bandwidth 40 GHz,” Electron. Lett., vol. 32, no. 12, pp. 1095–1096, Jun. 1996. [10] K. Gupta, R. Garg, I. Bahl, and P. Bhartia, Microstrip Lines and Slotlines. Norwood, MA: Artech House, 1996. [11] R. Spickermann and N. Dagli, “Experimental analysis of millimeter wave coplanar waveguide slow wave structures on GaAs,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 10, pp. 1918–1924, Oct. 1994. [12] K. Kiziloglu, N. Dagli, G. L. Matthaei, and S. I. Long, “Experimental analysis of transmission line parameters in high-speed GaAs digital circuit interconnects,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 8, pp. 1361–1367, Aug. 1991. [13] G. L. Matthaei, G. Chinn, C. Plott, and N. Dagli, “A simplified means for computation of interconnect distributed capacitances and inductances,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 11, no. 4, pp. 513–524, Apr. 1992. [14] R. G. Walker, “High speed III–V semiconductor intensity modulators,” IEEE J. Quantum Electron., vol. 27, no. 3, pp. 654–667, Mar. 1991.

>

VI. CONCLUSION In this paper, a novel capacitively loaded T-rail electrode for low-voltage high-speed SURE GaAs/AlGaAs electrooptic modulators has been designed, fabricated, and characterized up to 40 GHz. The electrode design satisfies all the requirements of a traveling-wave electrode suitable for a low-voltage and high-speed electrooptic modulator. Measured values of electrode impedance, loss coefficient, phase velocity, and capacitive loading were provided for different line dimensions using two different data extraction techniques. The capacitive loading was found to be higher than desired, which resulted in lower than desired characteristic impedance and phase velocity. However, the measured capacitance values are in excellent agreement with the results of simulations, showing that this type of a modulator can be precisely designed. Different approaches were outlined to reduce the capacitive loading. The results along with the ability to accurately simulate make this electrode suitable for low-voltage high-speed GaAs/AlGaAs electrooptic modulators. REFERENCES [1] N. Dagli, “Wide bandwidth lasers and modulators for RF photonics,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 7, pp. 1151–1171, Jul. 1999. [2] S. R. Sakamoto, A. Jackson, and N. Dagli, “Substrate removed GaAs/AlGaAs electrooptic modulators,” IEEE Photon. Technol. Lett., vol. 11, no. 10, pp. 1244–1246, Oct. 1999. [3] K. Kubota, J. Noda, and O. Mikami, “Traveling wave optical modulator using a directional coupler LiNbO waveguide,” IEEE J. Quantum Electron., vol. QE-16, no. 7, pp. 754–760, Jul. 1980. [4] R. Spickermann, S. R. Sakamoto, and N. Dagli, “In traveling wave modulators which velocity to match,” in Proc. 9th Annu. IEEE/LEOS’96 Meeting, Boston, MA, Nov. 18–21, 1996, Paper WM3, pp. 97–98. [5] R. Spickermann, S. R. Sakamoto, and N. Dagli, “GaAs/AlGaAs traveling wave electrooptic modulators,” in Proc. SPIE Optoelectronic Integrated Circuits Conf., vol. 3006, San Jose, CA, Feb. 8–14, 1997, Paper 33, pp. 272–279. [6] S. R. Sakamoto, C. Ozturk, Y. T. Byun, J. Ko, and N. Dagli, “Low loss substrate-removed (SURE) optical waveguides in GaAs/AlGaAs epitaxial layers embedded in organic polymers,” IEEE Photon. Technol. Lett., vol. 10, no. 7, pp. 985–987, Jul. 1998. [7] R. E. Collin, Foundations for Microwave Engineering. New York: McGraw-Hill, 1966.

JaeHyuk Shin was born on February 4, 1975, in Seoul, Korea. He received the B.S. degree in inorganic materials engineering from Seoul National University, Seoul, Korea, in 1999, and is currently working toward the M.S./Ph.D. degree in materials from the University of California at Santa Barbara. His graduate studies focus on the development of high-bandwidth low-drive voltage modulators for fiber-optic communications.

C. Ozturk, photograph and biography not available at time of publication.

S. R. Sakamoto, photograph and biography not available at time of publication.

Y. J. Chiu, photograph and biography not available at time of publication.

Nadir Dagli (M’79–SM’04) was born in Ankara, Turkey. He received the B.S. and M.S. degrees in electrical engineering from the Middle East Technical University, Ankara, Turkey, in 1976 and 1979, respectively, and Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, in 1986. Upon graduation, he joined the Electrical and Computer Engineering Department, University of California at Santa Barbara, where he is currently a Professor. He has authored or coauthored over 100 refereed journal and conference publications. His current interests are design, fabrication, and modeling of guided-wave components for optical integrated circuits, ultrafast electrooptic modulators, wavelength division multiplexing (WDM) components, and photonic nanostructures. Dr. Dagli is currently editor for IEEE PHOTONICS TECHNOLOGY LETTERS and is an elected member of the IEEE Lasers and Electro-Optics Society (LEOS) Board of Governors.

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New Approaches for Designing Microstrip Filters Utilizing Mixed Dielectrics Elena Semouchkina, Member, IEEE, Amanda Baker, George B. Semouchkin, Michael Lanagan, Member, IEEE, and Raj Mittra, Life Fellow, IEEE

Abstract—A strategy is developed for designing capacitively loaded microstrip filters on low-temperature co-fired ceramic (LTCC) substrates with inclusions or superstrate layers of higher permittivity dielectrics. Finite-difference time-domain simulations of the field distribution at resonant frequencies are used to determine the optimal locations and size of capacitive loads. It is demonstrated that strategic capacitive load placement enables altering the center and attenuation pole frequencies, the shape and width of the passband, and input impedance of the filter by modification of selected resonant modes. Capacitive loading with higher permittivity dielectrics is shown to be very efficient in decreasing dimensions of microstrip filters with low-permittivity substrates. The designs of novel compact resonators and filters have been developed and the prototypes fabricated by using LTCC technology. The results of prototype measurements agree with the simulation results, which validates the proposed approach. Index Terms—Electromagnetic fields, finite-difference timedomain (FDTD) methods, microstrip filters, resonance.

I. INTRODUCTION

R

ECENTLY there has been a growing interest in the application of microstrip bandpass filters in the next-generation wireless and mobile communication systems. These filters have a low profile and can provide space, weight, and cost savings. In addition, microstrip filters with elliptical function response are notable due to narrow-band and low-insertion loss. Canonical elliptical filters built with open-loop square rings have been described by Hong and Lancaster [1]. These filters are relatively large in size, and one way of size reduction is introduction of capacitive loading or stepped impedance in their design. Capacitive loads of different types were often introduced in monopole and patch antennas to reduce their dimensions [2], [3]. Stepped impedance has been frequently used in resonators, including microstrip ones [4]. Hong and Lancaster [5] used the stepped-impedance approach in the design of an open-loop filter, in which the microstrip width gradually increased toward the slot, which resulted in reduced size and wider upper stopband of the filter. Size reduction and Manuscript received January 8, 2004; revised March 17, 2004. This work was supported by the National Science Foundation under Award DMI-0339535 and as part of the Center for Dielectric Studies under Grant 0120812. E. Semouchkina, A. Baker, G. B. Semouchkin, and M. Lanagan are with the Materials Research Institute, The Pennsylvania State University, University Park, PA 16802 USA (e-mail: [email protected]). R. Mittra is with the Electromagnetic Communication Laboratory, The Pennsylvania State University, University Park, PA 16802 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840741

improvement of the characteristics of an open-loop filter was also reported by Banciu et al. [6], who added symmetrically located patches and open stubs in the filter design. However, the efficiency of stepped impedance is limited by the maximum possible size of microstrip or patch sections that are added to the filter design. Another option for device miniaturization is using higher permittivity (higher ) dielectric substrates, however, it meets serious problems, such as impedance mismatch and increased mutual coupling between the components. At this point, an approach that would combine location of the main circuitry of the device on a low- substrate with utilizing higher materials for local capacitive loading promises to present an efficient way for device miniaturization and parameter optimization. Low-temperature co-fired ceramic (LTCC) technology, which is efficient for fabrication of compact multilayer microwave components and packages [7], provides the means to co-process diverse ceramics in multilayer and planar architecture. Today, several types of ceramic materials, such as columbites , low-loss glass ceramics ( in the 17–85 range) [8] and Bi-pyrochlore ( between 40–150) [9], [10] are ready for integration in the modules based on commercial LTCC tapes with the in the range from 4.1 to 10, either by embedding into the cavities in the substrate or by thin or thick-film technologies. These achievements in materials offer a possibility to use hybrid dielectric substrates in microwave devices; however, such applications have not yet been developed. It is also worth noting that capacitive loading, especially in complex designs, could change and even degrade device parameters if it is not based on accurate electromagnetic-field analysis. In [11], we used finite-difference time-domain (FDTD) simulations for optimal placement stepped-impedance sections in microstrip filters. In this paper, we develop a strategy for designing microstrip filters and resonators on LTCC substrates with local capacitive loads utilizing inclusions or superstrate layers of higher permittivity dielectrics. We apply the FDTD simulations of the field distribution at resonant frequencies to determine the optimal location and size of high-permittivity capacitive loads. This enables us to efficiently modify selected resonant modes and to monitor passband and stopband characteristics, as well as input impedance of the filter. We also develop the designs of microstrip filters utilizing mixed dielectrics, describe the prototypes fabricated using LTCC technology, and compare the results of prototype measurements with the simulation results.

0018-9480/$20.00 © 2005 IEEE

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Fig. 1. Schematics of open-loop square ring resonators: (a) without capacitive loading, (b) with loading near the ring slot, (c) with loading in the middle of the front rib, and (d) with loading at the side ribs.

II. CONCEPT DESCRIPTION A. Field Analysis and Resonant-Mode Modification Here, the simulation results for capacitive loads, which are placed at different locations in an open-loop microstrip resonator, are presented. The center and attenuation pole frequencies, passband width, and input impedance are altered using dielectrics of different permittivity in the loads. Fig. 1(a)–(d) shows the geometries of a single-section microstrip open-loop square ring resonators: (a) without highloading so that the structure is composed of only the matrix dielectric with and (b)–(d) with capacitive loads using high and ) placed at three different permittivity dielectrics ( locations: (b) near the slot, (c) in the middle of the front rib, and (d) at the side ribs. The substrate has a thickness of 0.66 mm and dielectric constant of 9; the width of microstrips is 1 mm. The loads are either stepped-impedance sections of a patch type placed on top of uniform substrate or metal patches placed inside the low- substrate above the inclusions of higher [see Fig. 1(b) and (c)]. For the case depicted in Fig. 1(b), dielectric inclusions consist of two parts with different values, sections placed closer to the slot than with the higher sections. The resonator shown in Fig. 1(d) the lower has patch sections separated from the side ribs by a 0.8-mm gap, and connected with them by 0.4-mm-wide microstrips. An output microstrip line was added to the rings in order to model the coupling with the next section and to calculate the spectrum. In the FDTD simulations, perfectly matched layer boundary conditions were used at all boundaries of the computational domain, except for the bottom boundary, which was a perfectly conducting ground plane. A Gaussian-shaped electric-field pulse modulated by a sine wave was applied between the microstrip and ground plane to excite the structure. The fast Fourier transformation was used to convert the time-domain simulation results into the frequency-domain data that allowed visualization of field standing waves at the resonant frequencies [11]. spectrum of the unloaded resonator [see The simulated Fig. 1(a)] is presented in Fig. 2, which also shows the standingwave patterns of the normal electric-field component at the fremode and resoquencies corresponding to the nant modes, respectively. It is also seen in Fig. 2 that the first atspectrum at 1 GHz corresponds to the tenuation pole in the resonance in the right shoulder of the square ring between the input feedline and gap, while the second pole at 3 GHz is associated with the resonance in the same shoulder.

Fig. 2. S spectrum of open-loop square ring resonator depicted in Fig. 1(a), and standing-wave patterns corresponding to the peaks and attenuation poles of the spectrum.

In order to decrease the resonant frequency of a particular mode of the microstrip resonator, capacitive loads are placed in a position of amplitude maximum of electric field for this mode. Conversely, the capacitive load placed at the node of the electric field standing wave of a resonant mode does not affect the resonant frequency of this mode. Thus, resonant frequencies and transmission zeros can be independently manipulated by selectively loading high- dielectrics within a low- matrix structure. For the loading of the type shown in Fig. 1(b), the resonant frequencies of all the modes depicted in Fig. 2 decrease, which spectrum to lower frequency results in shifting of the entire (Fig. 3). This effect strongly increases with an increase of the dielectric constant of the load. When the load is located in the middle of the front rib [see and modes in a similar way, but Fig. 1(c)], it affects the and modes. Quite opposite, the loads does not alter the placed at the locations of standing-wave antinodes for the mode at the side ribs of the filter [see Fig. 1(d)] strongly affect this mode and the mode responsible for the second attenuaand tion pole, while producing negligible effect on the modes (compare field patterns in Fig. 2), which provides with peak and the second attenuation pole a strong shift of the spectrum (Fig. 4). These results illustrate modificain the tion of the bandwidths of the passband and stopbands, as well as their shapes, by affecting only selected modes of the spectrum through using proper load location. Fig. 5 demonstrates changes in input impedance of the resonator due to the loading: input impedance increases for the

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Fig. 3. S spectra for resonators: (Data1) without loading and (Data2–Data5) with capacitive load located near the slot [see Fig. 1(b)], (Data2) loading by metal patches with matrix dielectric ( ), (Data3) loading by patches above inclusions with = = 21, (Data4) loading by patches above inclusions = 45 and = 21, and (Data5) loading by patches above inclusions with with = 90 and = 21.

K

K K

K K

K

K

Fig. 5. Input impedance spectra for resonators with capacitive load located: (a) near the slot [see Fig. 1(b)], area of each patch 15 mm , (Data1–Data5) correspond to the same loading as in Fig. 3, and (b) in the middle of the front rib [see Fig. 1(c)] with a patch area of 12 mm , (Data1) unloaded filters, (Data2) = 9), (Data3) filter loaded with capacitor patch with matrix dielectric ( capacitor patch with = 21, (Data4) capacitor patch with = 45, and = 90. (Data5) capacitor patch with

K

K

K

K

B. Design of Microstrip Filters Utilizing Mixed Dielectrics

S

spectra for resonators: (Data1) without loading and (Data2–Data5) Fig. 4. with capacitive load located at the side ribs [see Fig. 1(d)], (Data2) loading by metal patches, (Data3) loading by patches above inclusions with = 21, and (Data4) loading by patches above inclusions with = 30.

K

K

loading shown in Fig. 1(b) [see Fig. 5(a)], while its behavior is opposite [see Fig. 5(b)] for the loading shown in Fig. 1(c). It points at the possibility to match impedance by varying the location and permittivity of the loads. It is worth noting that capacitive loads connected precisely to the points where the resonant mode has electric field maxima [see Fig. 1(d)] were found to be more efficient in modifying the resonant frequency of the mode and the input impedance, than adding stepped impedance sections at the area of high electric fields [see Fig. 1(b) and (c)].

The process of reducing filter size and optimizing its characteristics by using combinations of different loads is demonstrated here. This process requires multiple load adjustments since each load could change input impedance, introduce new spurious modes, and modify existing resonant modes of the filter. The steps in optimizing loading of the initial open-loop square-ring resonator [see Fig. 1(a)] to provide narrow passband at 2.45 GHz are illustrated below. mode of the As seen from Fig. 2, the passband of the initial resonator is not accompanied by a lower frequency attenuation pole, while the broad passband between 1.5–2.5 GHz, and modes, has the opportuwhich results from the nity for two attenuation poles. Fig. 6(a) depicts the schematics of the resonator with the substrate permittivity of 9, in which the size and the permittivity of the loads placed at the front

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Fig. 6. (a), (c), (e) Geometries (dimensions are given in numbers of cells, the size of one cell is 0.2 mm) and (b), (d), (f) corresponding S (dotted curves) and S (solid curves) spectra of filters with substrate of K = 9 and loaded by combinations of dielectric inclusions of different size, placed at different locations and with different K : ( a, b) K = 21; 30 and 65; ( c, d) K = 21; 30 and 65, and ( e, f) K = 21; 45 and 90.

and back ribs were adjusted to provide the center frequency of 2.45 GHz and to match input impedance, while the loads at the

side ribs were used to shift the mode closer to the mode [see Fig. 6(b)]. The size of this resonator [see Fig. 6(a)]

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Fig. 7. (a), (c), (e) Geometries and (b), (d), (f) S (dotted curves) and S (solid curves) spectra of filters with substrates of K = 7:8 and thickness of 660 m loaded by: (a), (b) dielectric plug with K = 100 and (c)–(f) superstrate with K = 100 and thickness of 55 m, (a)–(d) correspond to one-ring filters and (e) and (f) correspond to a two-ring filter with optimized coupling gap between the rings.

is (10 10) mm, in comparison with (20 20) mm of the unloaded resonator [see Fig. 1(a)]. However, the filter depicted in Fig. 6(a) has narrow stopbands [see Fig. 6(b)]. The design de-

picted in Fig. 6(c) provided an increase of the lower stopband width [see Fig. 6(d)] due to load adjustment and introduction of an additional slot in the ring. For the design shown in Fig. 6(e),

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Fig. 8. (a) Top and (b) cross-sectional views on the prototype with superstrate layer. Simulated (solid curves) and experimentally measured (dotted curves) (c) S and (d) S spectra of the prototype with the superstrate of = 49.

K

further adjustment of loads was performed and more slots were introduced in order to increase the upper stopband width [see Fig. 6(f)]. These examples show how a combination of highloads could provide desired shape of the passband and reduced dimensions of the filter. Combining loads of different permittivity potentially offers numerous degrees of freedom in shaping the passband, however, it is technologically difficult to reproduce. The design presented in Fig. 7(a) demonstrates that efficient passband shaping and size reduction of the filter could be achieved even when only one type of high- dielectric is used for loading. In this design, is inserted in the substrate of one plug of inside the microstrip loop. Metal patches and parts of the connecting strips are located at the surface of the plug to provide local loading. The simulated -parameter spectra of this filter show no spurious modes up to frequencies three times higher than the central one, and the passband of 3.6% [see Fig. 7(b)], while its area is decreased down to (5.4 5.4) mm . III. PROTOTYPE REALIZATION For practical realization of filters utilizing hybrid dielectrics, we investigated two fabrication opportunities. One was using high- superstrate layers over low- substrates and another one embedding high- plugs into low- substrates. Our primary goal was to prove the new concepts of microstrip filter fabrication and to implement the prototypes by simplest technological means. We intended to design and fabricate miniature

microstrip filters for 2.45-GHz center frequency with possibly narrow-band and low insertion loss in the passband. The results of the design modeling, prototype fabrication, and measurements are presented in Sections III-A and B. A. Capacitive Loading by Using High-

Superstrate

In the design depicted in Fig. 7(c), a square-shaped superstrate layer with the area slightly less than the area inside the ring is placed on top of the substrate. Metal patches located at the top and bottom of the superstrate serve as the electrodes of the loads, and the bottom electrodes are connected to the ground through vias in the substrate. The substrate thickness is 660 m, and its permittivity is 7.8. The superstrate is 55- m thick and has a permittivity of 100. The size and locations of the electrodes of the loads are adjusted to provide the central frequency of the filter equal to 2.45 GHz [see Fig. 7(d)] and to decrease its characteristic dimension down to 3.75 mm. To improve further the passband characteristics, two open-loop resonators with a 3.75-mm side were combined [see Fig. 7(e)], and the coupling gap between them, as well as the size and positions of load electrodes, have been further optimized to provide a low return-loss level and symmetric slopes of the spectrum [see Fig. 7(f)]. The latter design was reproduced with the substrate made of three layers of DuPont 951 LTCC tape . To make a via-connection between the bottom electrodes of the loads and the ground, the tapes were punched with a 150- m punch and then the holes were filled with silver via fill. The ground plane was printed on the backside of the lower layer with filled vias

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Fig. 10. (a) Contour plot and (b) three-dimensional distribution of the normal electric-field component in the plane below the substrate surface and parallel to it of the resonator depicted in Fig. 9(c) at a frequency of 2.45 GHz.

Fig. 9. Geometries of filters with substrates of K = 7:8 and high-K plugs of K = 74 immersed in the holes punched in the substrate.

using commercial silver ink. Bottom electrodes of the loads and microstrip pattern were printed on the top layer using commercial silver ink. The superstrate was then printed on this electroded tape using Bismuth Pyroclore ink, and the top electrodes of the loads were printed on top of the superstrate using silver ink. The bottom layer with a ground plane and filled vias, the middle layer with filled vias, and the top layer with an electroded superstrate were stacked, collated, and laminated. Filters were then singulated and fired to 875 C peak for a 30-min dwell time. Top and cross-sectional views of the prototype are shown in Fig. 8(a) and (b). We expected that the material of the printed superstrate would have a dielectric constant of 100, however, we obtained a smaller value, apparently due to the interaction between the superstrate material and the conducting ink. As the result, the observed resonance frequency was higher and the transmission in the passband lower [see Fig. 8(c) and (d)] than we expected. The simulated -parameter spectra of the filter with the same design, but with a superstrate of , were found to agree better with the experimental spectra [see Fig. 8(c)–(d)], and the same value for the permittivity was obtained from the independent measurements on fabricated capacitors. Research on the selection of well-matched conducting ink to provide stable superstrate layers with higher permittivity is now being conducted. B. Capacitive Loading by Embedded High-

Plugs

Another fabrication opportunity that we investigated was embedding plugs made of preliminary prepared high- ceramic tape into a low- substrate. The three layers of DuPont 951 LTCC tape with dielectric permittivity of 7.8 and a thickness of 250 m each were chosen as the substrate material, and the 250- m-thick bismuth zinc tantalate (BZT) LTCC tape with and (at 2.45 GHz) [9], [10] as the material for plugs to be inserted in the top substrate layer. Fig. 9 illustrates the development of the design, which has been reproduced in a prototype.

Fig. 9(a) shows the design of a one-section open-loop resonator utilizing four round high- pugs of 1.06-mm diameter. In order to provide resonant frequency of 2.45 GHz and to match input impedance in this design, the optimal values of loading capacitors are achieved through the adjustment of the diameters of the electrodes on the top and bottom of each plug separately. To simplify the processes of plug insertion and metallization, in the “back-to-back” design depicted in Fig. 9(b), one half-ring is flipped over, and four equal plugs with completely metallized top and bottom surfaces are used. This design also provides stronger magnetic coupling between the half-rings turned “back-to-back,” which is different from the design in Fig. 9(a), in which the half-rings are coupled primarily via the electric field in the coupling gaps. The equal size of loading capacitors [see Fig. 9(b)], however, did not provide sufficient degrees of freedom in optimizing resonator characteristics. Therefore, in the final design shown in Fig. 9(c), for which the prototype has been fabricated, we additionally adjusted the shapes of the microstrips and the locations of the feedlines. Fig. 10 shows the distribution of the electric field normal component in the plane located below the substrate surface and parallel to it at the resonant frequency of 2.45 GHz, which points at the half-wavelength resonance in the two half-rings at this frequency. The presented design consists of two resonators and is a two-pole (second order) filter with asymmetric characteristics. Asymmetric insertion-loss responses with one attenuation zero are often observed for multipole filters with one way for signal propagation, when none of the resonators are bypassed or cross-coupled (see, e.g., [12]). A second attenuation zero in such a filter could be added by introduction of cross-coupling in the filter design. The prototype fabrication began with preparation vias by punching holes with the diameter of 150- m in the two bottom substrate layers and filling them with silver via fill ink The top layer was then punched using a 1.25-mm-diameter punch. The three substrate layers were laminated in a platen press to form a “tray” for subsequent plug insertion, and PEOX was used to promote layer adhesion. BZT tape was printed on both the bottom and top sides with silver ink and then punched using a 1.25-mm punch. The resulting metallized BZT plugs were then carefully pressed into each of the slots formed in the LTCC tray. The filled tray was laminated and the microstrip pattern was then printed using silver ink. Resonators were singulated and fired to peak temperature of 850 C for 30 min holding time. Air-dried silver (Premetek 1228) was painted on the backs of the samples to form the ground plane.

SEMOUCHKINA et al.: NEW APPROACHES FOR DESIGNING MICROSTRIP FILTERS UTILIZING MIXED DIELECTRICS

Fig. 11. (a) Top and (b) cross-sectional views on the prototype with highand (d) spectra of the prototype. (dotted curves) (c)

S

S

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K plugs in the low-K substrate; simulated (solid curves) and experimentally measured

Fig. 11 presents the top and cross-sectional views of the fabricated prototype. Inclusion of a high-permittivity dielectric, as well as the via connecting the bottom electrode of the plug with the ground, are clearly seen. Fig. 11(c)–(d) compares the simulated and measured -parameter spectra of the prototype. The achieved return-loss level in the passband agrees with the predicted value ( 22 dB), which indicates that the input impedance of the prototype is matched. The measured value of the center frequency is 2.50 GHz, which, in comparison with the simulated value of 2.45 GHz, corresponds to an error of 2%. The simulations were performed without accounting for both conductor and dielectric loss, and the measured bandwidth at the 3-dB level is 0.21 GHz (8.4%) versus the simulated value of 0.16 GHz (6.5%). The measured insertion-loss level of 2.23 dB demonstrates that losses introduced by high- plug insertion are small. It is worth noting that the main circuitry of the device is still located at the low- substrate that decreases the influence of possible losses connected to high- materials. The dimensions of the fabricated prototype are (4.1 5.6) mm and there are no principal limitations to decrease them further. The agreement between the simulation and measurement results proves the validity of the proposed approach for designing microstrip filters utilizing hybrid dielectrics. It is worth noting at this point that, in a real production environment, the tolerances on the material properties and the manufacturing process could require tuning of the narrow filter band, which depends on the

capacitance of the inserted high- loads. Taking into account that upper electrodes of the loads are located at the surface, this capacitance could be tuned by using fine laser trimming of the top electrodes. Metal removal with 50- m accuracy will allow for resonant frequency shift by approximately 30 MHz at each trimming step. IV. CONCLUSION We have demonstrated the potential of high-permittivity dielectric materials for capacitive loading of microstrip resonators and filters. Capacitive loads are introduced in the device design based on the analysis of simulated field distribution at resonant frequencies. The use of hybrid dielectrics helps to substantially decrease filter dimensions and to control passband and stopband characteristics, as well as input impedance. The designs of miniature microstrip resonators and filters with high- dielectric loading have been developed, and the prototypes have been fabricated by using the LTCC technology. The results of prototype measurements were found to agree with the simulation results. REFERENCES [1] J. S. Hong and M. J. Lancaster, “Canonical microstrip filter using square open-loop resonator,” Electron. Lett., vol. 31, no. 23, pp. 2020–2022, Nov. 1995.

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[2] D. Lacey, G. Drossos, Z. Wu, L. E. Davis, T. W. Button, and P. Smith, “Miniaturized HTS microstrip patch antenna with enhanced capacitive loading,” IEE Superconducting Microwave Circuits Colloq. Dig., vol. 4, pp. 1–6, Apr. 1996. [3] C. Delaveaud, P. Leveque, and B. Jecko, “Small-sized low-profile antenna to replace monopole antennas,” Electron. Lett., vol. 34, no. 8, pp. 716–717, Apr. 1998. [4] M. Sagava, M. Makimoto, and S. Yamashita, “Geometrical structures and fundamental characteristics of microwave stepped-impedance resonators,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 7, pp. 1078–1085, Jul. 1997. [5] J. S. Hong and M. J. Lancaster, “Theory and experiment of novel microstrip slow-wave open-loop resonator filters,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 12, pp. 2358–2365, Dec. 1997. [6] M. G. Banciu, R. Ramer, and A. Ioachim, “Microstrip filters using new compact resonators,” Electron. Lett., vol. 38, no. 5, pp. 228–229, Feb. 2002. [7] S. Nishigaki, S. Yano, J. Fukuta, and T. Fuwa, “A new multilayered low temperature fireable ceramic substrate,” in Proc. Int. Society for Hybrid Microelectronics Symp., Oct. 1985, pp. 225–234. [8] G. Kniajer, K. Dechant, and P. Apte, “Low loss, low temperature cofired ceramics with higher dielectric constants for multichip modules (MCM),” in Proc. IEEE Int. Multichip Modules Conf., May 1997, pp. 121–127. [9] S. Kamba, V. Porokhonsky, A. Pashkin, V. Bovtin, J. Petzelt, J. Nino, S. Trolier–McKinstry, C. Randall, and M. Lanagan, “Broad-band dielectric spectroscopy of Bi pyrochlores in the range 100 Hz–100 THz,” in Proc. COST525 Meeting, Oct. 2001, pp. 49–53. [10] H.-J. Youn, C. Randall, A. Chen, T. Shrout, and M. Lanagan, “Dielectric relaxation and microwave dielectric properties of Bi O –ZnO–Ta O ceramics,” J. Mater. Res., vol. 17, no. 6, pp. 1502–1506, Jun. 2002. [11] E. Semouchkina, G. Semouchkin, M. Lanagan, and R. Mittra, “Field-simulation-based-strategy for designing microstrip filters,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, Jun. 2003, pp. 1897–1900. [12] S. Amari, G. Tadeson, J. Cihlar, and U. Rosenberg, “New parallel =2-microstrip line filters with transmission zeros at finite frequencies,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, Jun. 2003, pp. 543–547. Elena Semouchkina (M’04) received the M.S. degree in electrical engineering and Candidate of Science degree in physics and mathematics from Tomsk State University, Tomsk, Russia, in 1978 and 1986, respectively, and the Ph.D. degree in materials from The Pennsylvania State University, University Park, in 2001. She was a Scientist with Russian academic centers such as the Siberian Physics–Technical Institute, St. Petersburg State Technical University, and Ioffe Physics–Technical Institute, where she was involved with the investigation of metal–oxide–semiconductor devices and the development of infrared photodetectors. Since 1997, she has been with the Materials Research Institute, The Pennsylvania State University, initially as a Graduate Research Assistant, then as a Post-Doctoral Scholar and, since 2004, as a Research Associate. She has authored or coauthored approximately 50 publications in scientific journals. Her current research interests are focused on computational analysis of electromagnetic processes in microwave materials, metamaterials, and devices. Dr. Semouchkina was a recipient of the Xerox 2001 Research Award at The Pennsylvania State University for the best Ph.D. thesis and the National Science Foundation 2004 Advance Fellows Award.

Amanda Baker attended Tyler School of Art, Temple University, Philadelphia, PA, and The Pennsylvania State University, University Park. Prior to joining the Materials Research Institute, Pennsylvania State University, in 1998, she was with Johnson Matthey, TRW, and Optimax. While with The Pennsylvania State University, she has conducted dielectric materials development, processing, and cofiring. She currently manages the Thick Film Laboratory within the Keck Smart Materials Integration Laboratory. Her primary functions include design, materials selection, and construction of prototype devices using LTCC materials.

George B. Semouchkin received the M.S. degree in electrical engineering, Ph.D. degree in materials, and Doctor of Science degree in physics and mathematics from the Leningrad Polytechnic Institute (now SaintPetersburg State Technical University), Saint-Petersburg, Russia, in 1962, 1970, and 1990, respectively. Prior to joining The Pennsylvania State University, University Park, in 1999, he was with the Saint-Petersburg State Technical University, as a Professor, a Leading Scientist, a Head of the Laboratory, and earlier as a Senior Scientist, where he studied ionic crystals, ceramic materials, inorganic dielectrics, and developed microelectronic devices. He is currently a Visiting Professor of materials with the Materials Research Institute, The Pennsylvania State University. He has authored over 130 technical publications. His current research interests include designing LTCC-based microwave devices and all-dielectric metamaterials.

Michael Lanagan (M’99) received the B.S. degree in ceramic engineering from the University of Illinois at Urbana-Champaign, in 1982, and the Ph.D. degree in ceramic science and engineering from The Pennsylvania State University, University Park, in 1987. He is currently Professor of materials science and engineering, Associate Director of the Materials Research Institute, and Associate Director of the Center for Dielectric Studies with The Pennsylvania State University. Prior to joining The Pennsylvania State University, he was a Staff Scientist for 12 years with the Argonne National Laboratory, where he studied materials for superconductors, molten carbonate fuel cells, and high-energy density capacitors. He has authored over 150 technical publications. He holds eight patents. His current research interests include the development of new dielectric materials for highenergy density capacitors and microwave metamaterials. Dr. Lanagan is a member of The American Ceramic Society and The International Microelectronics and Packaging Societies. He was an invited participant to the National Academy of Engineering’s “Frontiers of Engineering,” which recognizes promising young scientists in all areas of research.

Raj Mittra (S’54–M’57–SM’69–F’71–LF’96) is currently a Professor with the Electrical Engineering Department, The Pennsylvania State University, University Park. He is also the Director of the Electromagnetic Communication Laboratory, which is affiliated with the Communication and Space Sciences Laboratory of the Electrical Engineering Department, The Pennsylvania State University. Prior to joining The Pennsylvania State University, he was a Professor of electrical and computer engineering with the University of Illinois at Urbana-Champaign. He is the President of RM Associates, a consulting organization that provides services to industrial and governmental organizations both in the U.S. and abroad. He has authored or coauthored over 600 technical papers and over 30 books or book chapters on various topics related to electromagnetics, antennas, microwaves, and electronic packaging. He holds three patents on communication antennas. He has advised over 80 Ph.D. students, approximately an equal number of M.S. students, and has mentored approximately 50 post-doctoral research associates and visiting scholars at the Electromagnetic Compatibility (EMC) Laboratories at the University of Illinois at Urbana-Champaign and Pennsylvania State University. Dr. Mittra is Past-President of the IEEE Antennas and Propagation Society (IEEE AP-S) and he has served as the editor of the IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION. He was the recipient of the 1965 Guggenheim Fellowship Award, the 1984 IEEE Centennial Medal, the 2000 IEEE Millennium Medal, and the 2002 IEEE AP-S Distinguished Achievement Award.

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A Compact 2-D FDFD Method for Modeling Microstrip Structures With Nonuniform Grids and Perfectly Matched Layer Jiunn-Nan Hwang

Abstract—Full-wave analysis of the microstrip structures is performed by using the compact two-dimensional (2-D) finite-difference frequency-domain (FDFD) method with nonuniform grids and perfectly matched layer (PML). The use of nonuniform grids can significantly reduce the computational matrix size. Less memory and CPU time are required as comparing with the original compact 2-D FDFD method. For the analysis of the microstrip structures with an absorbing boundary condition, the compact 2-D FDFD method with PML is presented. The performances of different PML thickness are studied. Numerical examples are presented to demonstrate the accuracy and efficiency of this method. Index Terms—Compact two-dimensional (2-D) finite difference frequency domain (FDFD), nonuniform grids, perfectly matched layer (PML).

I. INTRODUCTION

A

CCURATELY modeling the dispersion characteristics of a microstrip is important at the design stage. This procedure can be fulfilled by full-wave modeling approach. Among the available full-wave techniques, the finite-difference timedomain (FDTD) method has been widely used as an accurate way to predict the electromagnetic behavior of many guidedwave structures. To solve propagation problems, some research has introduced the dispersive boundary condition or high order boundary condition [1]–[3]. In these approaches, the phase of electric-field components at different locations are compared and the propagation constant can be extracted with knowledge of wave propagation between these locations. Another study [4] was performed by extracting equivalent-circuit components of a microstrip to determine the propagation constant and characteristic impedance. However, these approaches are limited to extract single-mode parameters due to the Fourier transform limit. The studies described in [5], [6] employed new methods with high-resolution signal-processing techniques and have the advantage of extracting multimode parameters. Unfortunately, when the dispersion parameters are very close to each other or extracting data at very low frequency, this method requires long simulation time. The finite-difference frequency-domain (FDFD) method can also be used to calculate the dispersion parameters [7],

[8]. In the existing FDFD method, the eigenfrequency can be extracted with a given propagation constant. Recently, a new compact two-dimensional (2-D) FDFD method [9], [10] was introduced to determine the propagation constant of guided-wave structures. Unlike the existing FDFD methods, the propagation constant can be extracted with a given frequency. This method can be used to accurately extract propagation constants of dominant and higher order modes. However, when studying guided-wave structures with fine geometry features, the computational matrix will be increased if uniform grids are used. Another problem is the boundary condition in [9] is a perfect electric conductor (PEC). The compact 2-D FDFD method with an absorbing boundary condition has not yet been proposed. In this paper, we propose a novel compact 2-D FDFD method with nonuniform grids and a perfectly matched layer to determine the propagation constant. In this approach, the simulation domain can be reduced significantly with nonuniform grids [11], [12]. We will demonstrate the advantage of this method by computing the dispersion characteristics of electrically large microstrip structures. The propagation problem in open space can be solved by introducing the perfectly matched layer (PML) concept [13], [14]. The PML equation for the compact 2-D FDFD method, which yields an eigenequation, is presented. We will compare the absorbing efficiency and computer burden of different PML thicknesses. The performances of the simulation results are evaluated. II. COMPACT 2-D FDFD METHOD The compact 2-D FDFD method can find the propagation constant with a given frequency . In this method, only four transverse fields are involved in the final equation. The compact 2-D FDFD equations are given by [9]

Manuscript received February 3, 2004; revised May 6, 2004 and June 29, 2004. The author is with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840569 0018-9480/$20.00 © 2005 IEEE

(1)

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(2)

Fig. 1. grids.

(3)

Spatial arrangement of the field components with 2-D nonuniform

Fig. 1 shows the spatial layout of the field components with 2-D nonuniform grids. When Yee’s grid is reduced to a compact 2-D grid, we can obtain

(6)

(4)

(7)

where and are the grid space in the - and - directions. Equation (1)–(4) can be concluded as an eigenproblem as

where is set as the average of the grid size in the two regions, . i.e., into (6), we can obtain After substituting

(5) , , and is a where sparse matrix and its matrix coefficients are listed in (1)–(4). To save the memory resource, the computational matrix can be decreased by using coarse grids in simulation. However, the grid size will influence the accuracy of numerical results. In the FDTD method [15], the grid size should be smaller than in the material medium, where is the wavelength of the highest frequency in the simulated frequency spectrum. In Section II, we will propose a new scheme to reduce the computational matrix while the numerical accuracy can still be maintained. III. COMPACT 2-D FDFD WITH NONUNIFORM GRIDS In the compact 2-D FDFD method, the computational domain depends on the size of the modeled structure. To simulate guided-wave structures with fine geometry features, fine grids are often used to accurately model the local field phenomena. This results in global refinement of the mesh density if uniform grids are used. Such a high level of refinement will increase the computational matrix size. To reduce the computational matrix size, the compact 2-D FDFD method with nonuniform grids is presented.

(8) Other field components can also be derived with similar procedures. When using the nonuniform grids, the grid space and in (1)–(4) are replaced by fine or coarse grid space depending on the electromagnetic fields’ positions. IV. COMPACT 2-D FDFD METHOD WITH PML IMPLEMENTATION The PML equations for the compact 2-D FDFD method are presented here. The original unsplit form of the PML equations in the frequency domain are given by [14]

(9)

HWANG: COMPACT 2-D FDFD METHOD FOR MODELING MICROSTRIP STRUCTURES

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By normalizing the field components with a square root of the and free-space wave impedance such that , we can obtain (10) (21) (11)

(22) (12)

(13)

(23) (14) where and denote electric and magnetic conductivity, respectively. The waves in the - direction do not need to be absorbed, i.e., . After some algebraic manipulations, (9)–(14) become the following forms:

(24)

(25) (15)

(16)

(17) (26) and are substituted into (21) and (22) and (24) and (25), respectively, the PML equations for the compact 2-D FDFD method can be obtained as (27)–(30) as follows: (18)

(19)

(20)

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(27)

(30) The directional electric conductivity in the PML is defined as (31) (32) is where is either or , is the thickness of the PML, and the maximum electric conductivity at the outer side of the PML. When studying the surface of conductors, it can be done by into (21)–(26) and inserting the boundary condition systematically modifying (27)–(30) accordingly. For example, in (22) and (27) will become

(28)

(33) V. NUMERICAL EXPERIMENTS

(29)

Numerical examples are used to verify the proposed method. In the first example, a dual-plane triple microstrip line on an anisotropic substrate, shown in Fig. 2, is studied. The modeled structure reported in [6] consists of 40 24 uniform grids, and is 3968 3968 . The the corresponding sparse matrix size computational domain can be reduced with nonuniform grids. The configuration of the modeled structure with nonuniform grids is shown in Fig. 3. The fine grid is chosen as 0.25 mm , , , and are chosen as and the coarse grids 0.4, 0.46, 0.4, and 0.48 mm, respectively. As shown in Fig. 4, the simulation results of the normalized effective dielectric constant are compared with those in [16]. Good agreement can be

HWANG: COMPACT 2-D FDFD METHOD FOR MODELING MICROSTRIP STRUCTURES

Fig. 2. Cross section of dual-plane triple microstrip lines. a = 10:0 mm, b = b = 1:0 mm, b = 4:0 mm, " = 9:4, " = 11:6, " = 9:4, W = W = W = 1:0 mm, and S = 2:0 mm.

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Fig. 5. Cross section of parallel coupled microstrip lines with finite strip thickness. " = 12:5. W = W = S = h = 0:6 mm, h = 10 mm, and S = S = 6 mm.

Fig. 3. Cross section of dual-plane triple microstrip lines with nonuniform grids. Fig. 6. Modeled effective dielectric constant for a coupled microstrip lines.

Fig. 7. Cross section of the computation domain for a microstrip line. W =

0:5 mm, h = 1:5 mm, and " = 9:4.

Fig. 4. Simulation results of the normalized propagation constants for dual-plane triple microstrip lines.

observed. The computational matrix size has been reduced to be 2134 2134 with nonuniform grids. The second analyzed structure is a coupled microstrip lines with finite strip thickness , as shown in Fig. 5. We use fine grids to model the strip thickness and coarse grids in other regions. The simulation results are shown in Fig. 6 and are compared with those in [17]. Good agreement is also reached. To verify the proposed PML equations for the compact 2-D FDFD method, a microstrip line with an absorbing boundary

condition is studied. As shown in Fig. 7, the PML is implemented on the sidewalls of the microstrip structure. To reduce the computational matrix, the thinner PML can be used and the absorbing efficiency must still be maintained. It has been found in [18] that the theoretical reflection coefficient and power need to be properly chosen to achieve small reflecshould tion. The thicker the PML, the smaller the chosen , the optimum range of be. After deciding upon the value of can be predicted. In this study, the PML thickness of five, six, eight, and ten cells are studied. The are chosen to be 10 , , and 10 , respectively. The of the five-cell-thick 10 , PML is chosen to be 2.0. When the PML thickness is larger than six cells, is chosen between 2.5–2.7. We increase the distance

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TABLE I MODELED RESULTS WITH DIFFERENT PML THICKNESS AND ITS CORRESPONDING MATRIX SIZE

cells. Both the computational matrix size are 2754 2754 . Fig. 9 shows the simulated effective dielectric constant. From the simulation results, it can be found that the dispersion parameters of the PEC boundary condition are smaller than those in [19]. Accurate results can be obtained by implementing a PML boundary condition. Fig. 8. Cross section of an asymmetric three-line microstrip lines with PML implementation. h = 0:635 mm, W = 0:3 mm, S = 0:2 mm, W = 0:6 mm, S = 0:4 mm, W = 1:2 mm, and " = 9:8.

VI. CONCLUSION In this paper, the compact 2-D FDFD method with nonuniform grids and a PML have been presented. When studying electrically large transmission-line systems, the use of nonuniform grids can significantly reduce the computational domain. The eigenform PML equations for the compact 2-D FDFD method are proposed to study the microstrip structure in open space. From simulation results, it is found that the performance of the six-cell PML can achieve accurate results with properly choosing PML reflection parameters. Numerical examples have been presented to demonstrate the efficiency and accuracy of this method. REFERENCES

Fig. 9. line.

Modeled effective dielectric constant for an asymmetric microstrip

between the microstrip line and PEC boundary as reference data to verify the PML absorbing efficiency. The distance is ten times the width of the microstrip line. The sparse matrix size of reference data is 1814 1814 . The simulated normalized propagais shown in Table I. Since the PML equations tion constant for the compact 2-D FDFD method are complex, the simulation results are also complex. The real part is the normalized propagation constant and the imaginary part is the loss due to the PML. The imaginary part will be decreased with an increase in the PML thickness. Comparing the simulation results of different PML thickness with the reference data, it is found that the performance of the six-cell PML can already achieve accurate results and sparse matrix size can also be significantly reduced. The second analyzed structure is an asymmetric three-line coupled microstrip lines, as shown in Fig. 8. The modeled structure with the PML boundary condition and PEC boundary condition are both studied. The thickness of the PML is six

[1] X. Zhang and K. K. Mei, “Time-domain finite difference approach to the calculation of the frequency-dependent characteristics of microstrip discontinuities,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 12, pp. 1775–1787, Dec. 1988. [2] X. Zhang, J. Fang, K. K. Mei, and Y. Liu, “Calculation of the dispersive characteristics of microstrips by the time-domain finite difference method,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 4, pp. 263–267, Apr. 1988. [3] Z. Bi, K. Wu, C. Wu, and J. Litva, “A dispersive boundary condition for microstrip component analysis using FD-TD method,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 4, pp. 774–777, Apr. 1992. [4] L. L. Liu, M. Mah, and J. Cook, “An equivalent circuit approach for microstrip component analysis using the FDTD method,” IEEE Microw. Guided Wave Lett., vol. 8, no. 10, pp. 330–332, Oct. 1998. [5] Y. X. Wang and H. Ling, “Multimode parameter extraction for multiconductor transmission lines via single-pass FDTD and signal-processing,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 1, pp. 89–96, Jan. 1998. [6] F. Liu, J. Schutt-Aine, and J. Chen, “Full-wave analysis and modeling of multiconductor transmission lines via 2-D FDTD and signal-processing techniques,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 2, pp. 570–577, Feb. 2002. [7] H. Y. D. Yang, “Finite difference analysis of 2-D photonic crystals,” IEEE Trans. Microw. Theory Tech., vol. 44, no. 12, pp. 2688–2695, Dec. 1996. [8] C. L. D. S. S. Sobrinho and A. J. Giarola, “Analysis of an infinite array of rectangular anisotropic dielectric waveguides using finite-difference method,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 5, pp. 1021–1025, May 1992. [9] Y.-J. Zhao, K.-L. Wu, and K. M. Cheng, “A compact 2-D full-wave finite-difference frequency-domain method for general guided wave structures,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 7, pp. 1844–1848, July 2002.

HWANG: COMPACT 2-D FDFD METHOD FOR MODELING MICROSTRIP STRUCTURES

[10] M.-L. Liu and Z. Chen, “A direct computation of propagation constant using compact 2-D full-wave eigen based finite-difference frequencydomain technique,” in Proc. Int. Computational Electromagnetics Applications Conf., Beijing, China, Nov. 1999, pp. 78–81. [11] P. Monk and E. Suli, “A convergence analysis of Yee’s scheme on nonuniform grids,” SIAM J. Numer. Anal., vol. 31, pp. 393–412, 1994. [12] P. Monk, “Error estimates for Yee’s method on nonuniform grids,” IEEE Trans. Magn., vol. 30, no. 9, pp. 3200–3203, Sep. 1994. [13] J. P. Berenger, “A perfectly matched layer for the absorbing of electromagnetic waves,” J. Comput. Phys., vol. 114, pp. 185–200, Oct. 1994. [14] R. Mittra and U. Peekl, “A new look at the perfectly matched layer (PML) concept for reflectionless absorbing of electromagnetic waves,” IEEE Microw. Guided Wave Lett., vol. 1. 5, no. 5, pp. 330–332, Mar. 1995. [15] A. Talflove, Computational Electrodynamics: The Finite-Difference Time-Domain Method. Norwood, MA: Artech House, 1995. [16] M. S. Alam, M. Koshiba, K. Hirayama, and Y. Hayashi, “Hybrid-mode analysis of multilayered and multiconductor transmission lines,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 2, pp. 205–211, Feb. 1997. [17] J.-T. Kuo and T. Itoh, “Hybrid-mode computation of propagation and attenuation characteristics of parallel coupled microstrips with finite metallization thickness,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 2, pp. 274–280, Feb. 1997.

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[18] Z. Wu and J. Fang, “Numerical implementation and performance of perfectly matched layer boundary condition for waveguide structures,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 12, pp. 2676–2683, Dec. 1995. [19] V. K. Tripathi and H. Lee, “Spectral domain computation of the apparent characteristic impedances and multiport parameters of multiple coupled microstrip lines,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 1, pp. 215–221, Jan. 1989.

Jiunn-Nan Hwang was born on June 23, 1978, in MiaoLi, Taiwan, R.O.C. He received the B.S.E.E. and M.S.E.E. degrees from the National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C., in 2000 and 2002, respectively, and is currently working toward the Ph.D. degree in communication engineering at the National Chiao Tung University, Hsinchu, R.O.C. His research interests include the electromagnetic modeling for electromagnetic compatibility (EMC)/electromagnetic interference (EMI) problem and applications for metamaterials.

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Spectrum Emission Considerations for Baseband-Modeled CALLUM Architectures Roland Strandberg, Student Member, IEEE, Pietro Andreani, Member, IEEE, and Lars Sundström, Member, IEEE

Abstract—Linear transmitters based on combined analog locked loop universal modulator (CALLUM) architectures are attractive, as they promise both high efficiency and high linearity. To date, it has not been possible to analyze a CALLUM transmitter as a linear feedback network due to the nonlinear nature of the control equations governing it. The main purpose of this paper has been the derivation of a linearized model for the control equations, which enables the use of linear network theory in the study of CALLUM. In particular, it can be used to analyze the stability and maximize the bandwidth of the system. Simulation examples are presented on how three different CALLUM architectures behave for enhanced data rates for global system for mobile communications evolution and wide-band code-division multiple-access signals. In addition, we have considered the effects of loop time delay, which is the ultimate limiting factor for all feedback-based linear transmitter architectures, particularly for large bandwidths. Finally, it is shown how frequency compensation of the feedback loop improves insensitivity to the loop time delay. Index Terms—Baseband modeling, combined analog locked loop universal modulator (CALLUM), linear power-amplifier (PA) architecture, loop gain, time delay.

I. INTRODUCTION

T

HE NEED of utilizing the available frequency spectrum as efficiently as possible has resulted in wireless communication standards abandoning the traditional constant-amplitude modulation schemes [such as Gaussian minimum shift keying (GMSK) in global system for mobile communications (GSM)], adopting instead nonconstant envelope modulations, as in the enhanced data rates for global system for mobile communications evolution (EDGE) standard. Common to all nonconstant envelope modulation schemes is that the information is not only impressed on the phase, but also on the amplitude of the carrier. This imposes stringent demands on the linearity of the power amplifier (PA) used in the radio transmitter, and makes the design of linear PAs highly nontrivial, especially when a major challenge in wireless applications is to realize low-power circuits. In fact, it is well known that linearity and efficiency trade with each other.

Manuscript received January 28, 2004; revised March 31, 2004. This work was supported by the Competence Center for Circuit Design, Lund University and VINNOVA, which is a Swedish agency for innovation systems. R. Strandberg is with the Department of Electroscience, Lund University, SE-221 00 Lund, Sweden (e-mail: [email protected]). P. Andreani is with the Center for Physical Electronics, Ørsted 1 DTU, Technical University of Denmark, DK-2800 Lyngby, Denmark (e-mail: [email protected]). L. Sundström is with Ericsson Mobile Platforms AB, SE-221 83 Lund, Sweden (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840568

Highly efficient linear power amplification can be achieved by linearizing a nonlinear, but very efficient PA. Established linearization techniques are feedback (either polar or Cartesian [1], [2]), feed-forward [3], and predistortion [4]. Alternatively, an intrinsically linear transmitter architecture can be adopted. The combined analog locked loop universal modulator (CALLUM), the subject of this paper, is one such linear architecture, having a theoretical efficiency of 100% for all output levels [5]. CALLUM is an expansion of the linear amplification using nonlinear components (LINC, first described in [6]) since it is based on a LINC core placed in a feedback loop. LINC and CALLUM are based on a kind of divide-and-conquer approach, which first transforms an amplitude- and phase-modulated signal into two constant-envelope phase-modulated signals, and then recombines them after they have been power amplified. Since a constant-envelope signal can be processed by a grossly nonlinear PA without information loss [7], the two constant-envelope signals can now be amplified by highly efficient, but highly nonlinear class-C PAs, or even by switching PAs (such as class-E PAs, having a 100% theoretical efficiency [8]). Although linear and efficient power amplification is particularly attractive for battery-powered wireless handsets, it could be fruitfully employed in base stations as well in order to decrease the overall power dissipation. The diminished cooling requirements would result in cheaper and more compact base stations. However, despite the promises offered by the different techniques just described, it should be admitted that major breakthroughs in the art of linear and efficient RF PA design have remained elusive to date. Numerous variations around the basic CALLUM architecture, usually referred to as CALLUM1, have appeared in the open literature. Chan and Bateman [5] reviewed no less than six: CALLUM1, CALLUM2, CALLUM3, CALLUM4, vectorlocked loop (VLL), and higher order. The various CALLUM implementations were investigated in terms of stability in the in-phase and quadrature ( ) plane and speed estimations performed by step response analysis, which were supplemented with measurements on physical implementation using discrete building blocks. Several CALLUM designs were simulated in [9], where their RF output spectra for a terrestrial trunked radio (TETRA)-like baseband modulation were presented, together with actual measurements for CALLUM2. This study was an important contribution to the understanding of the properties of the different CALLUM versions, and the goal of this paper is to further investigate these properties, mainly through the study of the feedback loop present in all CALLUM designs. We will confine our analysis to those implementations that are both continuous (i.e., with loop coefficients independent of

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the input signal value) and based on Cartesian feedback, as opposed to polar feedback. This second condition is important in guaranteeing matched time delays in the two paths of the feedback signal, which is crucial for achieving high linearity. As a consequence, we will focus on CALLUM1 and CALLUM2, together with an intermediate approach [9], here referred to as CALLUM1 with linearized denominator (CALLUM1lin). The remainder of this paper is organized as follows. The CALLUM architecture is presented at block level in Section II, and an equivalent baseband model used for the loop-gain calculations is presented in Section III. The loop-gain equations are plane, and are shown to contain graphically visualized in the important information for the subsequent stability analysis. In Section IV, spectral emissions for three different versions of CALLUM are compared when operating on an EDGE and on a wide-band code-division multiple-access (W-CDMA) signal, respectively. Finally, the effect of time delay in the feedback loop is presented in Section V, together with suitable frequency compensation techniques improving the stability properties of the system.

Fig. 1.

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Generic CALLUM transmitter architecture.

equation for is repeated here in (1) for convenience since it is the basis for two more CALLUM versions to be presented ]: in the following [an analogous equation describes

II. SYSTEM DESCRIPTION We have seen that, in a CALLUM architecture the input signal, which is assumed to be both amplitude and phase modulated, is divided into two constant-envelope phase-modulated signals, which are recombined after amplification. The feedback signal is advantageously taken as close to the antenna as possible (constrained by stability issues, see Section V) in order to minimize the number of error sources that cannot be corrected by the feedback loop. It is well known that the nonlinearities included in the loop are reduced by the action of negative feedback, which is a very powerful and robust remedy against distortion regardless of what causes it (e.g., mismatch between ideally identical branches, nonlinear transfers, etc.). The degree of distortion suppression is proportional to the magnitude of the signal gain in the loop. A major drawback of this approach, on the other hand, is that any feedback system has an increased complexity and, in general, is prone to instability. The stability properties are fundamental and will be studied in detail in Section V. The generic CALLUM architecture is shown in Fig. 1 at the functional block level. The signal component generator (SCG) is the heart of the architecture, and the algorithm implemented in the SCG will differ depending on the kind of CALLUM realized (or, equivalently, depending on the chosen set of control equations). In this paper, only continuous versions of CALLUM suitable for implementation based on a Cartesian representation are considered. Cartesian representation promises good signal matching properties between the and path in the feedback, especially in terms of delay [10]. Starting from the input signals and the feedback signals, the SCG generates the control voltages and for two voltage-controlled oscillators (VCOs) (i.e., and ). The SCG operates on signals either at baseband or at an intermediate frequency. A derivation of the control equations for the original version of CALLUM, here to be referred to as CALLUM1, was presented in [10]. The control

(1)

(2)

(3) Index in (1) denotes the control equation for the CALLUM1 version of the CALLUM design, while subscripts and refer to the input and output signals, respectively; is the gain factor of the VCO [in rad/(Vs)], is the asymptotic closed-loop transfer from input to output [11], and are gain factors, and is the magnitude of the complex should be chosen such that the maximum input vector. input signal amplitude generates the maximum output signal

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for best power efficiency. The value for is given by . It should now be noted that the square-root term in (1) poses severe challenges for the actual circuit implementation, and avoiding it might be advantageous from an overall point-of-view. A straightforward simplification can be obtained by replacing the square root with its Taylor series expansion, truncated at the first order [9]. This results in CALLUM1 with a linearized denominator (to be referred to as CALLUM1lin), whose control equation is given by (2). It is possible to make a very significant further simplification of (2) in order to improve designability even more. Since a division is a costly operation, denominator terms in the control equation for CALLUM1lin can be disregarded altogether; the resulting CALLUM version is known as CALLUM2 [5], [12], [13], with a control equation given by (3). Of course, possibly severely degraded signal performances are expected in CALLUM2.

Fig. 2. Vector addition of the constant envelope signals to reconstruct an amplified replica of the input signal.

A. Baseband Modeling of CALLUM System The dramatic reduction in simulation time is the major drive behind the realization of a baseband model for CALLUM. In a baseband simulation, the carrier frequency is not present and, as a result, simulations based on a baseband model are far more efficient in terms of computational workload than simulations performed on the system with RF signals. The carrier frequency can be removed because its only effect is to rotate the coordinate system (the complete diagram) without affecting the information contained at baseband. In all CALLUM architectures, both an up- and a down-conversion in frequency are performed, which are bypassed in the baseband model. It is, of course, crucial that the baseband model is able to capture all relevant features and possible problems of the original RF system. Since the carrier frequency is 0 Hz in a baseband simulation, and a reference phase is lacking, the signal representation has to be made in the complex domain. A normal circuit simulator based on time-domain analysis (e.g., spectreRF in Cadence) cannot handle complex signals directly, which calls for a workaround. The definition of the baseband output signal and its relation to the constant-envelope vectors and is shown in Fig. 2 and is given by (4) (5) (6) denotes the real (imaginary) part of the where output signal . It is now easy to identify the output and baseband components as (7) (8) The baseband circuit of Fig. 3 results directly from the above models the gain (or attenuation) equations, while the factor in the frequency down-conversion. The phase between and is rad to accommodate the complex implementation. To guarantee this relative phase shift between the VCOs,

Fig. 3. Baseband model for a generic CALLUM system with real-valued signal paths.

they are described as mathematical functions in the analog hardware description language (AHDL).1 To repeat, the baseband representation is of great importance since it makes possible the simulation of complete bursts of transmitted data in a reasonable amount of time. This, in turn, enables the assessment of the qualifying features for the different CALLUM versions. III. LOOP-GAIN CALCULATIONS BASED ON LINEARIZED EQUATIONS As is clear from (1)–(3), CALLUM is governed by a set of nonlinear control equations, from which basic features like loop gain, bandwidth, and stability are difficult to obtain. For these reasons, these equations will be linearized around a static bias point. Since the three CALLUM versions differ only in the control equations, the generic structure of the linearized baseband CALLUM model, displayed in Fig. 4, is the same in all cases. As with phase-locked loops (PLLs), the relevant input and output signals are phases, while inside the loop, different phase-tovoltage and voltage-to-phase conversions take place. The model in Fig. 4 is roughly equivalent to half of the circuit in Fig. 3 in that the cross-coupling between the and part of the baseband equivalent has been neglected. This rather drastic simplification can be justified as follows: since the goal is to have a linear signal transfer, the required amount of loop gain is subcomponent of the signal propastantial and, therefore, the part of the system will be significantly gating through the 1AHDL

is handled by numerous circuit simulators (in our case, spectre).

STRANDBERG et al.: SPECTRUM EMISSION CONSIDERATIONS FOR BASEBAND-MODELED CALLUM ARCHITECTURES

Fig. 4.

Reduced baseband model used for loop-gain calculations.

Fig. 5.

attenuated.2 This simplified model is only used for loop-gain calculations. Closed-loop simulations are, of course, performed on the complete model of Fig. 3. Throughout the remainder of this paper, the following notation is adopted, which hopefully will make the linearization as the total signal, procedure easy to follow: we define as its bias component, and as its small-signal variation (i.e., ). We begin the linearization procedure by noting goes to that the error signal for a constant input signal zero as time goes to infinity due to the presence of an integrator in the loop (it is well known from PLL theory that an oscillator behaves as an ideal integrator in the baseband PLL model [14]). At steady state, the output signal will be equal to the input signal , . scaled by the asymptotic gain Now, in order to perform a loop-gain analysis, all variations for the input signals are set to zero, whereas their bias components are fed to the system. The nonlinear system is linearized around this quiescent point, and the loop is opened at a suitable node (for instance, at the output of the signal adder) for open-loop calculations. From the outputs of the VCOs to the output of the CALLUM architecture a phase-to-amplitude conversion takes place, indiin Fig. 4. The trigonometric function performed cated by by the PA and the combiner is a projection of the output signal from the PAs onto the -axis, as shown in Fig. 5. The in-phase output signal is given by

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Projection of the output signal on the I -axis.

where if and if Fig. 4, we can write the loop gain as

. From the model in

(13) where

is the SCG transfer relative to signal .

A. Linearization of the Control Signals In the expression for the loop gain (13), the transfers for the and ) have not yet been derived. The SCG ( transfer is found by linearizing the control (1)–(3), respectively. Note that direct linearization of these equations in, which is not part of the SCG clude the effect of in order transfer. Therefore, the result should be divided by to include the effect of the gain in the feedback path only once in the loop-gain expression (13). As indicated in Fig. 4, only a small variation in the output signal is considered. Thus, the linearized transfers of the SCG are calculated in presence of the , , , , following signal: . These transfers for the three CALLUM derivatives are given by (14)

(9) is the transfer of the PA (here, considered as a where is the amplitude of the VCO signal. The constant), and , which debaseband input signal level is determined by pends on the feedback gain, PA gain, and VCO gain . The transfer function for the VCO is given by , where is the complex angular frequency as usual. Straightforward linearization of (9) yields the output signal as (10) where

,

, and

and

(15) (16) Here, is the amplitude of the input signal taken in the operating point (17) The SCG transfer for only differs from minus sign in front of the term.

by having a

are given by B. Loop-Gain Characteristics (11) (12)

2The I (Q) component is seen as a disturbance by the Q(I ) part of the system and, as such, is largely suppressed by it.

All information to express the loop gain for any of the CALLUM versions is now available. The loop gain is found by inserting the transfers of the SCG in the generic expression for the loop gain (13). The fairly complicated loop-gain expression prevents a direct interpretation; hence, the absolute value of diagram, which gives a very the loop gain is plotted in the

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Fig. 6. Loop gain is shown for a CALLUM1 system implementation. The loop gain refers to the in-phase component variation plotted at a fix frequency. The loop gain is set to zero outside the valid input range.

quick indication of the expected performance of the chosen implementation. Fig. 6 shows the magnitude of the loop gain for CALLUM1 for the in-phase component, plotted at a fix frequency. The maximum value of the loop gain is set to 100 to enable an easy comparison between the CALLUM versions. Due to the loop-gain normalization, the chosen frequency is arbitrary. The loop gain for CALLUM1 is constant over the in the plane, which whole valid input range is not obvious from the loop-gain expression. This is unique for the original CALLUM1 control law, as it has a continuous amplitude normalization in the loop-gain expression. For the quadrature-phase component variation, the loop gain will show the same pattern, rotated by 90 . Since the same information is contained in the and plots, in the following, we will not make this distinction. For CALLUM1lin, the first-order approximation is used in the SCG control equation, which changes the loop gain compared to CALLUM1. It can be shown that the first-order Taylor series expansion is , when similar results as for CALLUM1 accurate for are expected. The three-dimensional (3-D) loop-gain plot for CALLUM1lin is shown in Fig. 7, where the loop gain clearly drops for large values of . A more accurate approximation (i.e., a higher order Taylor expansion) would reduce the drop in loop gain at the expense of a much increased circuit complexity. Both CALLUM1 and CALLUM1lin have high-implementation costs due to the relatively complicated mathematical operations (square root and/or division) that have to be performed. The strive for reduced complexity resulted in CALLUM2, where the price to be paid is small loop gain (or lack thereof) at low-signal levels, and a strongly varying loop gain within , as shown in the amplitude interval of interest Fig. 8. The valid input range is limited at the lower end by the bandwidth of the closed-loop system [10], and at the upper end by signal-handling capability (i.e., by the onset of clipping). The information available in the 3-D contour plots of the loop gain allows the investigation of feedback stability and the related design of frequency compensation. A prediction where the loop

Fig. 7. Loop gain for CALLUM1 with linearized denominator.

Fig. 8. Loop-gain 3-D plot for CALLUM2. The region with low loop gain for a low envelope signal is one of the main drawbacks for CALLUM2 compared to CALLUM1.

gain has its largest value in the plane will serve as the point selected for compensation purposes since this is the worst case scenario in feedback systems. Clearly, in all CALLUM versions, . Thus, fremaximum loop gain is achieved when quency compensation must be performed in presence of maximum envelope for the input signal.

IV. COMPARISONS BETWEEN BASEBAND-SIMULATED SPECTRAL PERFORMANCES The three CALLUM versions under test, i.e., CALLUM1, CALLUM1lin, and CALLUM2, have been modeled in a circuit simulator (spectre/spectreRF) at baseband. The schematic views were built at the block level using AHDL as the description language. From the resulting simulations, the relative ranking of the different implementations, in terms of the amount of loop gain needed to correctly process a signal with a given modulation, and of the maximum acceptable loop delay, is presented in Sections IV-AB.

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A. CALLUM and Spectrum Emission Mask for EDGE The first issue investigated is how the implementation of the SCG affects the performance of the system when operating on an EDGE-modulated signal. The loop-gain plots in the plane (Figs. 6–8) provide the information to adjust the peak magnitude of the loop gain for each CALLUM version to a constant value. This allows easy comparison of the spectral properties for each implementation. The simulated spectra are based on a random data sequence containing 33 ksymbols, -shifted eight phase-shift keying (PSK) modulation using a and filtering according to the EDGE standard. The maximum peak amplitude of the input signal was chosen to be 98% of in order to avoid the problem of its valid input range having a zero at the denominator of the control equations in, for example, CALLUM1. The simulated spectrum is processed through a 30-kHz filter bandwidth and normalized to the power in 30 kHz of the carrier. The technical specifications covering GSM/EDGE radio transmission can be found in TS 05.05 at the third–generation partnership project (3GPP), and the European Telecommunications Standards Institute (ETSI).3 The EDGE spectrum emission mask for mobile stations in the GSM900 band is plotted in Fig. 9, together with the spectrum of transmitted signal for each CALLUM version. The input signal serves as a reference, from which it is possible to detect any spectrum degradation. The magnitude of the loop gain was adjusted in such a way that CALLUM2 barely passed the spectrum emission mask. The gap to CALLUM1 and CALLUM1lin is significant, and it can be concluded that dropping the denominator term in the control equations for CALLUM2 has severe effects on the spectral properties. The low loop-gain region for (Fig. 8) has low and medium signal amplitudes relative to a really strong impact on the performance of CALLUM2. The spectral performances of CALLUM1 and CALLUM1lin, on the other hand, are much better as a result of a more leveled loop plane for these CALLUM version. It can be gain in the noted that CALLUM1lin approximates the original CALLUM1 very closely and, for the tested modulation, they perform equally well. B. CALLUM and Spectrum Emission Mask for W-CDMA In Section IV-A, the peak loop gain was adjusted such that CALLUM2 just passed the spectrum emission mask test for EDGE. The same simulation setting, apart from a loop-gain scaling, was also used on a W-CDMA signal. Since the chip rate of a W-CDMA signal is 3.84 Mchips/s, compared to only 270.833 ksymb/s for EDGE, a bandwidth normalization was done. This normalization removes the effect of the larger bandwidth of the W-CDMA signal, and was accomplished by increasing the loop gain by 14 times, which results in a 14 larger loop bandwidth for this first-order system transfer. Fig. 10 shows the simulated output spectra for the CALLUM versions together with the spectrum of the input signal. The output power spectra obtained from the simulator were filtered before they were compared to the mask according to Standard TS 25.101, in which the details are found. The out-of-channel 3[Online]. Available: http://www.3gpp.org and http://www.etsi.org for complete standard specifications.

Fig. 9. Spectrum emission mask for mobile handset equipment for EDGE transmit spectrum is shown together with the input and output signals from different implementations of CALLUM.

Fig. 10. Spectrum emission mask for user equipment (UE) for the W-CDMA transmit spectrum is shown together with the reference and outputs for different implementations of CALLUM. Only the part of the spectrum covered by the spectrum emission mask requirement is plotted.

emission is specified relative the root raised cosine (RRC) filtered mean power of the modulated carrier. Close to the carrier (2.5–3.5 MHz) a 30-kHz measurement bandwidth is used, while at higher offsets (3.5–12.5 MHz), the bandwidth becomes 1 MHz. Again, CALLUM2 barely passes the spectrum emission mask test. A second test was to calculate the adjacent channel leakage power ratio (ACLR) for CALLUM2. The ACLR is the ratio of the RRC filtered mean power centered on the assigned channel frequency to the RRC filtered mean power centered on an adjacent channel frequency. In the closest neighbor channel, the space to the spectrum emission mask is fairly large, and the ACLR is more than 10 dB better than the specification demands. In the second neighbor channel, however, located 10 MHz relative to the carrier, the spectrum almost touches the mask and the ACLR is calculated at 43.7 dB, which is more or less at the 43 dB . lower limit of the specification

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It can be suspected from the shape of the spectrum of CALLUM2, due to its white-like character, that some sort of narrow spikes are superimposed on the signal in the time domain. In fact, it has been found from transient simulations that CALLUM2 loses lock now and then, always in conjunction with small amplitudes of the input signal. Turning again to Fig. 8, it is clear that the loop gain is low for small-to-medium signal amplitudes, and it is well known that the bandwidth of a system having only a single loop pole is proportional to the loop gain. Thus, the loop bandwidth decreases for small-signal amplitudes, with the result that the loop cannot follow the signal in some (rare) cases. After the loop is unlocked, the process of lock acquisition starts almost immediately. Lock acquisition is a nonlinear and fast process (compared to the modulated signal), which produces glitch-like disturbances in the output signal and, hence, the white-noise-like floor in Fig. 10. This unfavorable behavior of CALLUM2 makes it very unsuitable for operations on a W-CDMA signal. In principle, it is true that it is always possible to increase the loop gain to get improved performance; however, the unavoidable presence of parasitic phenomena such as time delays and high-frequency poles sets strong limitations to this brute-force approach, as it increases the risk of instability, due to the large loop bandwidth. Hence, it is the limited bandwidth of the CALLUM2 system that makes its application on a W-CDMA signal difficult. Further, the modulation used in W-CDMA, the so-called hybrid phase-shift keying (HPSK), also known as orthogonal-complex quadrature phase-shift keying (OCQPSK), allows zero crossings, and in any CALLUM architecture, zero crossings give rise to a spectrally very wide signal within the loop. We can conclude that building a linear transmitter for W-CDMA based on CALLUM2 is a real challenge in terms of the bandwidth needed. The performance for both CALLUM1 and its linearized sibling is strikingly good, as it tracks the reference perfectly. Actually, it would be possible to degrade the spectral performance and gain in design robustness. In Section V-A, robustness will be investigated in terms of the maximum acceptable loop delay and, in Section V-B, a bandwidth reduction technique will be applied to further enhance insensitivity to time delay. V. ACCOUNTING FOR TIME DELAY IN THE LOOP A pure time delay is often used to compensate for a complexity reduction in the model of a given system. In this way, a high-order system can be represented by a low-order model, plus an appropriate time delay. A time delay always reduces the stability of a system, and limits its achievable response time. In the CALLUM architecture, this delay originates from the fact that the PA output is filtered by resonant circuits (introducing a delay roughly proportional to their quality factor), and that the signal has to travel a physical distance both on-chip and on the printed circuit board. The effects of time delay on a CALLUM system are investigated here by isolating them from other sources; therefore, we will assume that the only pole present in the loop is the one due to the integrating action of the VCO. The introduction of the

Fig. 11.

Model used for loop-gain calculations including delay.

delay in the model used for loop-gain calculations is shown in Fig. 11. The loop-gain results found in Section III-B can handle , this time delay simply by multiplying (13) with the term and will not be repeated here. Noting that the phase shift asso, the maximum loop bandwidth ciated to the time delay is is given by (18) where is the phase margin of the feedback signal, and the integrator accounts for a 90 phase shift. Equation (18) can be interpreted in two ways: either the maximum loop bandwidth can be determined, once phase margin and delay are known or, for a given standard (e.g., EDGE, W-CDMA, TETRA), the maximum allowed time delay can be determined for the desired phase margin. This second interpretation, however, is unfortunately much less straightforward than might be thought since the loop must be able to handle bandwidths much larger than the bandwidth of the original input signal. This is an undesired consequence of the nonlinear conversion of an amplitude- and phase-modulated signal into two constant-amplitude signals. A. Acceptable Loop Delay in CALLUM Since the time delay in the loop is expected to be the limiting factor for the loop bandwidth in most real-life implementations, next we will examine its impact on CALLUM performances. The maximum acceptable time delay has been simulated for each CALLUM version and for the two standards already targeted—EDGE and W-CDMA. To create the necessary conditions for the simulations, the magnitude of the loop gain was adjusted for each CALLUM version to a level resulting in a close fit of the spectral emission, compared to the mask for the standard under test.4 Thereafter, a time delay was added, and the largest acceptable time delay for which the spectrum emission requirements were still fulfilled was noted in Table I. For small time delays, the spectral emission is not noticeably degraded, but as the delay increases, the far-out power spectrum starts increasing (similar observations were reported in [15]). Further increments in time delay prevent the circuit from acquiring lock altogether.

4It should be noted that, in these simulations, the loop gain varied between different CALLUM versions, while it was the same for all CALLUM versions in the simulations of Section IV.

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TABLE I MAXIMUM ACCEPTABLE LOOP DELAY TO FULFILL THE SPECTRUM EMISSION MASK

Fig. 12.

The large difference between the maximum allowable time delay for CALLUM1lin and CALLUM2, respectively, is due to the fact that some 50 lower peak loop gain is needed in CALLUM1lin, and an equally reduced loop bandwidth, when processing an EDGE signal. The maximum loop gain is the same for CALLUM1 and CALLUM1lin, but surprisingly, CALLUM1 was found to have a harder time acquiring lock. The smaller acceptable time delay for W-CDMA, compared to EDGE, is primarily due to the larger bandwidth of the W-CDMA signal, as discussed in Section IV-B. It can be noted that a time delay as small as 0.1 ns was enough to prevent CALLUM2 to acquire lock with a W-CDMA signal. B. Loop Bandwidth Reduction From (18), it can be concluded that the acceptable time delay can be increased if the loop bandwidth is reduced. Bandwidth reduction can be achieved in a brute-force approach by decreasing the loop gain, but this will deteriorate the spectral performances in an unacceptable way. A much better solution is to reduce the bandwidth while keeping the low-frequency loop gain unaffected. One such type of frequency compensation, often used in PLL design, is known as lag–lead compensation. It consists of the introduction of a pole-zero pair in the loop transfer function, which is easy to implement with a simple RC network [16] (see Fig. 12). As a rule of thumb, the zero is placed at approximately one-tenth of the loop bandwidth to be achieved; in this way, a robust stability is ensured. A second parameter is the distance between the zero and the pole in the lag-lead filter, here denoted . The loop bandwidth is reduced by as to a first-order approximation, and an approximately times larger delay can be accepted, compared to the uncompensated case. It is, therefore, clear that the factor should be maximized , the lag–lead network can be based on (in the limit of an integrator), while making sure that the zero keeps the right distance from the bandwidth edge. The inevitable drawback of introducing frequency compensation is that undesired spectral emissions will increase since the loop gain is reduced at higher frequencies and more energy in the adjacent channels will appear as a consequence. To compensate for this reduction in resolution for the high-frequency contents in the signal, the loop gain has to be increased, counteracting to some extent the loop bandwidth reduction of the lag–lead compensation. A few simulation iterations are usually sufficient to obtain the optimal values for pole, zero, and loop gain. The improvements in time-delay insensitivity yielded by the lag–lead compensation are discussed in Section V-C. C. Acceptable Loop Delay in CALLUM After Compensation We have seen that the goal of frequency compensation is to allow a larger time delay in the loop. Table II shows the max-

Passive implementation of lag–lead loop filter.

TABLE II ACCEPTABLE LOOP DELAY AFTER COMPENSATION STILL FULFILLING THE SPECTRUM EMISSION MASK

imum acceptable time delay for modulated signals still meeting the specifications on spectral emissions once frequency compensation has been applied. Clearly, the improvements on the uncompensated cases (see, again, Table I) are significant for EDGE. As an example, the settings for the CALLUM2 compensations were: 1) the lag–lead zero was placed at 8 Mrad/s; 2) was ten; and 3) the loop gain was increased by a factor of three, compared to the uncompensated case. These values are readily implementable in a real-life integrated design. In the case of a first-order system, an upper limit for the maximum acceptable time delay after compensation can be easily derived from (18) as (19) As an example, in the case of CALLUM2, (19) estimates to 3.3 ns, while the simulated value is 3.4 ns. In the case of CALLUM1lin, however, (19) would overestimate by 80%. Although too optimistic in general, (19) shows the (qualitative) relation linking , the loop gains before and after compensation, and the acceptable time delays before and after compensation. To succeed with the compensation strategy, there must be room for deterioration of the spectral emissions; if these are already very close to the spectral mask, no significant improvements can be made. Thus, the reason why large improvements were achievable for CALLUM1 and CALLUM1lin (and to a lesser extent, for CALLUM2) operating on EDGE was the relatively large distance between mask and actual spectral emissions for large offset frequencies; overly good spectral performances at large offset frequencies were, in this case, traded for higher insensitivity to time delay (as an example, compensation for CALLUM1 is shown in Fig. 13). For any of the three CALLUM versions operating on W-CDMA, on the contrary, even a small additional time delay was enough to deteriorate the signal spectrum at frequencies where it was positioned very close to the signal mask, thereby failing to comply with it. It remains to be noted that CALLUM1lin performed very well in terms of maximum acceptable time delay for a certain standard. Of course, the implementation cost for the SCG in CALLUM1lin is higher than that for CALLUM2, but

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versions both before and after frequency compensation. The applied compensation was shown to be truly efficient on each of the CALLUM versions working on an EDGE signal, while the high data rate and the modulation nature for W-CDMA demand that either CALLUM1 or CALLUM1lin be employed. In particular, CALLUM1lin appears to be the most attractive general-purpose CALLUM design, offering a very robust transmitter for a simplified CALLUM implementation. REFERENCES

Fig. 13. EDGE spectrum for CALLUM1 before and after lag–lead compensation. T = 10 ns, n = 15 Mrad/s, E = 8, and loop gain doubled compared to the uncompensated case.

0

significantly lower than for CALLUM1, without any obvious performance drawbacks. VI. CONCLUSIONS This paper has investigated the behavior of three different versions of the CALLUM transmitter architecture, which have been referred to as CALLUM1, CALLUM1lin, and CALLUM2. To perform accurate and time-efficient simulations on a large number of transmitted symbols (a prerequisite to calculate the spectrum of the modulated output signal), a baseband model for the generic CALLUM implementation was used. Further, the (nonlinear) baseband model was linearized around a bias point in order to enable the study of feedback stability through a small-signal analysis. The loop-gain equations for the three CALLUM versions were explicitly derived and plotted over the plane; these data contain the relevant information needed for stability analysis and subsequent frequency compensation. The three CALLUM versions were compared in terms of spectral emission performance for an equal peak magnitude of the loop gain and for operation on two different standards, i.e., EDGE and W-CDMA, representative for signals modulated both in-phase and in-amplitude. As the loop bandwidth is strongly coupled to both the loop gain and time delay in the loop, the peak loop gain was held constant to simplify comparison between the different CALLUM versions. Simulations showed a large performance difference in favor of CALLUM1 and CALLUM1lin compared to CALLUM2, whose strong point is, however, the significantly reduced design complexity. The EDGE standard can be handled by all three implementations, but the larger signal bandwidth of W-CDMA prevents the use of CALLUM2, when realistic time delays in the feedback loop are accounted for. Loop time delay is, in fact, a key parameter in the design of the CALLUM feedback network since, in all practical implementations, it is this delay that limits the achievable loop bandwidth. The maximum time delay compatible with spectral emission requirements was simulated for the three CALLUM

[1] M. Briffa, M. Faulkner, and J. Macleod, “RF amplifier linearization using Cartesian feedback,” in 1st Int. Mobile and Personal Communications Systems Workshop, Adelaide, Australia, Nov. 1992, pp. 343–348. [2] M. Johansson and T. Mattsson, “Transmitter linearization using Cartesian feedback for linear TDMA modulation,” in Proc. 41st IEEE Vehicular Technology Conf., May 1991, pp. 439–444. [3] P. Kenington, R. Wilkinson, and J. Marvill, “The design of highly linear broadband power amplifiers,” in IEE Solid-State Power Amplifiers Colloq., Dec. 1991, pp. 5/1–5/4. [4] E. Westesson and L. Sundström, “A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers,” in IEEE Int. Circuits and Systems Symp., vol. 1, 1999, pp. 206–209. [5] K. Chan and A. Bateman, “Linear modulators based on RF synthesis: Realization and analysis,” IEEE Trans. Circuits Syst., vol. 42, no. 6, pp. 321–333, Jun. 1995. [6] D. Cox, “Linear amplification with nonlinear components,” IEEE Trans. Commun., vol. COM-22, no. 12, pp. 1942–1945, Dec. 1974. [7] F. J. Casadevall and A. Valdovinos, “Performance analysis of QAM modulations applied to the LINC transmitter,” IEEE Trans. Veh. Technol., vol. 42, no. 11, pp. 399–406, Nov. 1993. [8] F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic´ , N. Pothecary, J. F. Sevic, and N. O. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp. 814–826, Mar. 2002. [9] D. J. Jennings, A. Bateman, and J. P. McGeehan, “Adjacent channel power and error-vector magnitude performance of reduced complexity CALLUM systems,” in Proc. IEE Communications, vol. 146, Oct. 1999, pp. 297–302. [10] R. Strandberg, P. Andreani, and L. Sundström, “Bandwidth considerations for a CALLUM transmitter architecture,” in IEEE Int. Circuits and Systems Symp., vol. 4, 2002, pp. 25–28. [11] E. H. Nordholt, Design of High-Performance Negative-Feedback Amplifiers. Delft, The Netherlands: Delft Univ. Press, 1993. [12] D. J. Jennings and J. P. McGeehan, “A high-efficiency RF transmitter using VCO-derived synthesis: CALLUM,” IEEE Trans. Microw. Theory Techniques, vol. 47, no. 6, pp. 715–721, Jun. 1999. [13] , “A high-efficiency RF transmitter using VCO-derived synthesis: CALLUM,” in Proc. Radio and Wireless Conf., 1998, pp. 137–140. [14] W. C. Lindsey and C. M. Chie, Phase-Locked Loops. New York: IEEE Press, 1986. [15] M. A. Briffa and M. Faulkner, “Stability analysis of Cartesian feedback linearization for amplifiers with small nonlinearities,” in IEE Proc. Communications, vol. 143, 1996, pp. 212–218. [16] R. E. Best, Phase-Locked Loops, 2nd ed. New York: McGraw-Hill, 1993.

Roland Strandberg (S’98) was born in Kristianstad, Sweden, in 1974. He received the M.Sc. degree in electrical engineering and Ph.D. degree in applied electronics from Lund University, Lund, Sweden, in 1998 and 2004, respectively. In 1998, he joined the Mixed-Signal Group, Department of Applied Electronics (now the Department of Electroscience), Lund University, where he was involved with low-noise digital circuits. From investigation of substrate-coupled noise the research moved to switched dc–dc on-chip power converters. Since 2000, he has been involved with linear power amplification, specifically the CALLUM architecture. His research interests include structured electronic design, analog amplifiers, PLLs, and applied control theory, as well as large-signal circuits with emphasis on PAs and linear transmitter architectures.

STRANDBERG et al.: SPECTRUM EMISSION CONSIDERATIONS FOR BASEBAND-MODELED CALLUM ARCHITECTURES

Pietro Andreani (S’98–A’99–M’01) received the M.S.E.E. degree from the University of Pisa, Pisa, Italy, in 1988, and the Ph.D. degree from Lund University, Lund, Sweden, in 1999. In 1990, he joined the Department of Applied Electronics, Lund University, where he contributed to the development of software tools for digital application-specific integrated-circuit (ASIC) design. During 1994, he was a CMOS Integrated Circuit Designer with the Department of Applied Electronics, University of Pisa, after which time he rejoined the Department of Applied Electronics, Lund University, as an Associate Professor, where he was responsible for the analog integrated-circuit course package from 1995 to 2001. He is currently a Professor with the Center for Physical Electronics, Ørsted 1 DTU, Technical University of Denmark, Kgs. Lyngby, Denmark, where he is mainly involved with analog/RF CMOS integrated-circuit design.

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Lars Sundström (S’91–M’95) received the M.Sc. degree in electronic engineering and Ph.D. degree from Lund University, Lund, Sweden, in 1988 and 1995, respectively. From 1995 to 2000, he was an Associate Professor with the Competence Centre for Circuit Design (CCCD), Department of Applied Electronics (now the Department of Electroscience), Lund University. In 2000, he joined Ericsson Mobile Communications AB (now Ericsson Mobile Platforms AB), Lund, Sweden. He continues his research activities with Lund University as an Adjunct Professor. His research interests include analog RF ASIC design and transceiver architectures.

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An Efficient Method for Determining TE and TM Modes in Closed Waveguides Made up of N Cylindrical Conductors Valentín de la Rubia and Juan Zapata, Member, IEEE

Abstract—In this paper, an efficient method for calculating TE and TM modes in closed waveguides made up of cylindrical perfect electric multiconductors and homogeneous isotropic media is presented. An ad hoc analytical formulation of the problem is carried out, and special emphasis is placed on its resolution. As a result, the determination of the cutoff wavenumbers is achieved using a robust and efficient algorithm. An adaptive approximation scheme is also proposed to ensure an acceptable precision and an efficient computation without missing any mode. Finally, several comparisons demonstrate the accuracy of the proposed method. Index Terms—Algorithms, Bessel series/transforms, circular waveguides, coaxial waveguides, Helmholtz equations, multiconductor transmission lines, poles and zeros, search methods.

I. INTRODUCTION

M

ODAL spectrum analysis in closed waveguides made up of cylindrical perfect electric conductors (PECs) and homogeneous isotropic media is of special interest in the design of several microwave devices such as quarter-wave transformers, directional couplers, hybrid power dividers, filters, and feeds in patch antennas backed by circular cavities, among others. The cases in which up to two conductors are considered have been widely discussed in the literature, and different techniques have been proposed. The canonical problems of a circular waveguide and a coaxial line are solved analytically [1]. Series expansion fulfilling boundary conditions on one of the conductors and imposing them point-wise on the other is addressed in [2]. Series expansion and field matching of the boundary conditions is carried out in [3]. A special analytical shape perturbation method is proposed in [4], where the perturbation comes from the eccentricity of the inner conductor taking the modal spectrum of the coaxial line as its pattern. Another perturbation technique has been considered in [5] for waveguides with an eccentric inner conductor not close to the outer conductor and a small ratio of the radii in which the circular waveguide is the pattern. This approach is especially suitable for the analysis of cylindrical cavities excited by a thin probe. Conformal transformation can convert the homogeneous eccentric annular waveguide into an equivalent

nonhomogeneous problem on a geometrically simpler domain, i.e., the Helmholtz equation in the complicated original geometry is replaced by an equivalent equation, which presents a weight function, in a canonical region. Under this scheme, [6] determines upper and lower bounds for the cutoff wavenumbers by means of the Rayleigh–Ritz and intermediate problem methods, respectively. Using the same conformal mapping, [7] proposes an approach with the finite-difference method. Reference [8] considers a conformal transformation in which the nonhomogeneity of the weight function in the equivalent Helmholtz equation is negligible. Trigonometric series in the simpler geometry achieved by conformal mapping is suggested in [9]. On the contrary, when more than two conductors are considered, an ad hoc approach of the problem has not been effectuated, necessitating an analysis by means of numerical methods for arbitrary cross-sectional waveguides. In this study, we use a series expansion approach in which a good convergence is achieved because the formulation carried out is specific for the types of structures considered. The mathematical foundations of this analysis are compiled in [10]. Moreover, the series expansion has been applied successfully to very generic problems [11]–[13]. In this paper, we concentrate on the numerical considerations of the mathematical problem and develop a robust and efficient algorithm, taking into account the peculiarities of our problem, which deals with the determination of the zeros in an analytic function. Additionally, an adaptive series expansion is proposed since a reasonable convergence is easily achieved. In this sense, a criterion to truncate the series expansion adaptively providing an acceptable precision and an efficient computation without missing any mode is proposed. Finally, numerical comparisons show the robustness, accuracy, and efficiency of the proposed method. II. FORMULATION Applying the Fourier transform to the Maxwell equations, one can find that the fields in the transform domain , except for TEM modes, are completely determined by their longitudinal components, which take the form (1)

Manuscript received January 14, 2004; revised May 25, 2004. This work was supported by the Comisión Interministerial de Ciencia y Tecnología, Spain, under Contract TIC2001-2739. The authors are with the Departamento de Electromagnetismo y Teoría de Circuitos, Universidad Politécnica de Madrid, 28040 Madrid, Spain (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840567

being the propagation constant and . The function is to satisfy the two-dimensional (2-D) scalar Helmholtz equation in the domain , specified in Fig. 1, as follows:

0018-9480/$20.00 © 2005 IEEE

(2)

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and

(6b)

Fig. 1. Definition of the problem: Cross section and geometrical aspects of the structures under analysis.

, is given in the where the function , as shown in Fig. 1. indicates Appendix and in relation to , giving rise to the polar the position of and . The shorthand notation coordinates denotes that can be directly substituted by or . In order to impose the boundary conditions (3), we can write exclusively in each of the coordinate systems , the field with the help of (6). This leads us to the infinite homogeneous system of linear algebraic equations

where

. Depending on whether TE modes or TM modes are to be found, homogeneous Neumann boundary conditions or homogeneous Dirichlet boundary conditions have to be imposed, respectively, on the of , i.e., boundary for TE modes

(3a)

for TM modes

(3b)

All the solutions of the Helmholtz equation (2) can be expressed as a series expansion, thus,

(7a) for TE modes, and

(4) where is the number of conductors involved in the structure under analysis, and represent the first- and the second-kind Bessel functions of order , respectively, and , are the expansion coefficients. is expressed in the coordinate system associated to each conductor, i.e., , , in Fig. 1, giving rise to the quantities and , which denote polar coordinates. Note that we start numbering from the outer conductor. Finally, the function has been defined for convenience as follows: (5) By means of the additional theorems for Bessel functions [14], it can be shown that

(6a)

(7b) for TM modes, where , are the radii of each conductor. The matrix associated to these infinite equation systems constitutes the dispersion matrix of the medium for the kind of mode considered. III. NUMERICAL ASPECTS In order to obtain field solutions apart from the trivial one, the determinant of the dispersion matrix of the medium has to vanish, which gives rise to the characteristic equation of the medium . Solutions of this equation allow us to find out the cutoff wavenumbers of the modes . Unfortunately, there is no analytical approach for the infinite determinantal

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equation so a numerical solution has to be accomplished by truncating the order of the dispersion matrix to a finite number. A. Truncation of the Dispersion Matrix and in (7) between Varying the integer numbers and , i.e., , yields the desired truncation of the system of equations and, consequently, the associated dispersion matrix. The accomplished truncation has the implication that these calculated fields are an approximation of the exact solutions. More specifically, the solutions are expressed as

(8) and the suitable boundary conditions are only approximately denote an approximposed. Hence, , , and , imation of the exact solution. In this sense, the characteristic toggles to . equation of the medium This truncation might be seen as a projection of the infinite dimension solution space of the boundary value problem on a increases, finite dimension subspace. Consequently, when the error in the approximation decreases and a larger number of the physical problem solutions may be determined, i.e., physical solutions that were orthogonal to a lower dimension subspace. However, there are particular cases in which this determined solution is the exact one, i.e., when the considered subspace itself constitutes a solution of the boundary value problem, as, for instance, is the case for a circular waveguide and a coaxial line, perfectly enclosed in the geometries being studied. B. Zero Finding Characteristic equation resolution is equivalent to the deter. Theoretical conmination of the zeros in the function siderations assure us that the solutions of this equation fulfill . This has the implication that all the zeros in belong to and if is a zero in that function so is , but both represent the same mode. we can 1) Preliminary Considerations: The function so we have to feel conwork with is an approximation of fident that our approximation is good enough to determine the modes we are looking for. This can be addressed by choosing a in (8); nevertheless, an alternative will conservative enough be presented in Section IV-B. Taking into account the form of the elements that constitute the truncated dispersion matrix, several properties of the funccan be obtained. tion 1) Nullifying it gives rise to a transcendental equation with an infinite number of solutions as a result of the oscillating nature of the implicated Bessel functions. . 2) Its definition domain is 3) It is analytic in its definition domain , except for the . negative real axis, i.e., in . 4) It is a real-valued function in in , which is derived from the 5) Schwarz reflection principle [15].

Regarding our purposes, we have to deal with determining in the the positive real zeros in the real-valued function positive real axis. Among all the different approaches to the problem, we highlight two families: iterative methods and contour integral methods. The former are extremely appropriate when the approximated values of the zeros are known, but have numerous disadvantages when neither these values, nor the number of zeros that exist in a given region are known. The latter are based on the residue theorem and try to overcome the deficiencies of the iterative methods determining the number of zeros in a given region, as well as their values with certain accuracy. A discussion on this issue can be found in [16]. As a result of the problem we are trying to solve, it is essential to guarantee that no mode be missed, i.e., to calculate all the zeros in the function in a positive real axis interval, including their multiplicity in order to be able to detect a degeneration of the modes. It is advantageous to know a priori the number of zeros in a given region. For this purpose, let be a closed counterclockwise contour. There are two ways to determine the enclosed by the number of zeros in an analytic function contour . One is via the contour integral (9) and the other, derived from it, by means of the number of times that the function circles the origin on the curve . This way, only the phase of the function is needed, whereas in the previous one, not only is the value of the function required, but also the value of its derivative. Since our function is the determinant of a matrix, the order of which may become rather high, the values that the function can take on might vary between numbers whose modulus are either extremely large or excessively small, making their representation difficult on a computer even in double precision. Hence, we discard all the zero-finding methods based on the values that the function takes. On the contrary, the phase of the function can be easily achieved by adding the phase of the main diagonal elements in the matrix of the LU decomposition through which the determinant of the matrix is obtained and, thus, all our effort is developed in this direction. vanishes The function whenever its real and imaginary part vanish simultaneously. and Therefore, if we define the curves , the zeros in the function are located at the intersection of the curves. It can be shown that if the function is analytic, these two curves intersect at approximately radians, being the multiplicity of the zero [17]. in our The positive real axis is a curve problem so the phase of the function in a line parallel to the positive real axis as close to it as we want only shows a meaningful variation in the neighborhood of a zero. The magnitude of this variation is related to multiplicity of the zero, and its rate of change, to the proximity of the line to the real axis. On the contrary, this behavior might not occur if the line is not close enough to the real axis. Fig. 2(a) and (b) details all of this, including the fact that the phase of the function cannot be calculated straightforwardly on a computer, but it

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Fig. 2. Function defined by the characteristic equation for TM modes in a coaxial line with outer and inner radii 1 and 0.5, respectively, with the simple zero in 6.246 and double zeros in 6.393 and 6.814 ( ). (a) Phase behavior along segments parallel to the real axis (artificial search intervals). (b) Behavior of the associated principal value of the phase. (c) Actual search interval, artificial search interval, and contour 0. (d) Number of times that the function circles the origin on the contour 0 highlighting the contribution from 0 and 0 . Note that there is a symmetry of the function phase on these two curves with respect to S .

is the principal value of the phase, i.e., , which can be . computed directly, obtaining quantities in the interval Consequently, these facts can be used to locate the positive real zeros in the function. Given an actual search interval, i.e., a positive real axis interval, sampling in an artificial search interval made up of the upper line interval parallel to the actual search interval [see , we can Fig. 2(c)] from left to right, i.e., conclude the following:

(10c)

(10d) where

(10a)

(10b)

, is a decision threshold to adjust and , denoting that there is either an , respeceven or odd number of zeros in the real interval tively. Therefore, sampling in the artificial search interval has the advantage of making it possible to detect an even number of zeros in the actual search interval, i.e., zeros that would remain dislocated by observing the phase of the function in the positive real axis.

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TABLE I CUTOFF WAVENUMBER CONVERGENCE IN THE GEOMETRY OF FIG. 4(c)

Therefore, we are able to determine all the zeros including along the their multiplicity in the real-valued function positive real axis with the required precision only by means of its phase using the properties of analytic function in the complex plane. 2) Algorithm: We propose the following robust and efficient zero-finding method. Given a positive real axis interval, i.e., actual search interval, and its associated artificial search interval, the algorithm is basically as follows. Step 1) Determining the number of zeros in the actual search interval. For this purpose, the only part of the real axis that has to be enclosed by the contour is the actual search interval [see Fig. 2(c)]. Step 2) Sampling the artificial search interval uniformly at a number of sample points proportional to the number of zeros previously detected, and applying (10), assuming the minimum number of possible zeros, i.e., 1 or 2, to locate the zeros, if necessary conveniently accompanied by the action explained in Step 1). Thus, we get reliable subintervals for the location of the zeros. Step 3) Whenever the achieved precision is not the required one, repeating Step 2) in the reliable subintervals for each zero until the precision is higher than the required limit. Step 1) deserves consideration for the sake of efficiency. This computation, i.e., the number of times that the function circles the origin on the contour , is carried out using the procedure detailed in [18], which proposes a variable step-size sampling scheme based on a certain order prediction of the function phase. Furthermore, this computation can be reduced by half , because by choosing contours such as . Let us be more specific. Let fulfill that reand be the two contours in which the quirement, and let , , real axis divides the contour , therefore, and are mirror images in respect to the real axis. Both i.e., curves are shown in Fig. 2(c). As stated earlier, so the number of times that the function circles the origin on the is the same as contour . Fig. 2(d) shows this fact contour and the existing phase symmetry on these two curves. This is the reason why we only have to evaluate the phase of the function on either or .

Fig. 3. Alternative contour mode.

0

for searching the lowest cutoff wavenumber

Our experience leads us to using ellipses with foci in the actual search interval as contour , as well as a parabolic phase prediction. Nevertheless, when the lowest cutoff wavenumber mode, i.e., a TE mode, is found, we have to start searching from 0 , and then the use of ellipses results in a large number of failures in the prediction of the phase as we approach the singularity that exists in the origin. These failures come about because the rate of variation of the phase is higher and higher as we approach the singularity, whose order may be rather high, on this contour. In this situation, we propose , , as shown in and are the halves Fig. 3, as alternative contour, where of circles centred at the origin and radii and , respectively, and are segments in the positive and negaand tive imaginary axes, respectively. This new contour, conserving the mirror image symmetry in respect of the real axis, is espeas cially advantageous because the phase of the function on is practically linear as a result of the singularity centred at the origin and, thus, a linear predictor perfectly matches with the phase. This prediction can also be extended to is an approximation of the function , good results. the zeros of which are real and symmetric from the origin. then remains constant along the positive The phase of imaginary axis, as well as along the negative imaginary one.

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Fig. 6. Adaptive scheme: value M used to determine each of the first 100 TE and TM modes in the geometry of Fig. 4(b). TABLE II COMPARISON BETWEEN THE CUTOFF WAVENUMBERS IN THE STRUCTURE OF FIG. 4(b) CALCULATED WITH AN ADAPTIVE AND CONSERVATIVE M

Fig. 4. (a) Eccentric annular line. (b) Shielded bifilar line. (c) Shielded three-wire line. (d) Shielded four-wire line.

Fig. 5. Cutoff wavenumbers relative error in modes for 0:2 u, and D = 0:5 u in the structure of Fig. 4(c).

R

= 1 u,

R

=

(SVD) algorithm of a matrix, which allows us to determine an orthonormal basis of the best approximation of the kernel of the singular matrix, in the least square sense.

Therefore, it is not necessary to carry out any calculation on and . C. Determination of the Expansion Coefficients Once the zeros in the determinant of the truncated dispersion matrix have been located and its multiplicity established, we can calculate the unknowns within the homogeneous system, which constitute the expansion coefficients of the fields. In this case, we determine a basis of the kernel of the truncated dispersion matrix. Nevertheless, the unavoidable numerical approach that has to be made cannot establish the exact vanishing of the determinant, but only the proximity to a zero in it. Thus, we try to find the best approximation of the kernel of the singular matrix. This task is carried out by means of the singular value decomposition

IV. NUMERICAL RESULTS A. Convergence The accuracy obtained by the proposed formulation depends on the considered structure, on the calculated mode, and, directly, on the number of functions used in the representation of the field as series expansion, i.e., on the value in (8). Indeed, the convergence is addressed in different ways. Table I shows the convergence of the cutoff wavenumber for the first ten TE and TM modes of the geometry of Fig. 4(c) for , , and , where denotes the unit of length. It can be seen that the calculated cutoff wavenumbers converge monotonically to the right solution as increases, but at a rate that depends on the mode. Likewise, the cells marked by a bar

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TABLE III COMPARISON BETWEEN THE CUTOFF WAVENUMBERS FOR TE AND TM MODES IN THE STRUCTURE OF FIG. 4(a)

TABLE IV COMPARISON BETWEEN THE CUTOFF WAVENUMBERS FOR TE AND TM MODES IN THE STRUCTURE OF FIG. 4(b)

TABLE V COMPARISON BETWEEN THE CUTOFF WAVENUMBERS FOR TE AND TM MODES IN THE STRUCTURE OF FIG. 4(c)

- in Table I mean that the considered mode cannot be represented with this number of functions, i.e., this zero in the determinant of the truncated dispersion matrix does not exist and, therefore, it suggests that it is necessary to increase the value of for representing that mode. Section IV-B deals with this in greater depth.

TABLE VI COMPARISON BETWEEN THE CUTOFF WAVENUMBERS FOR TE AND TM MODES IN THE STRUCTURE OF FIG. 4(d)

B.

Adaptive Selection Method

A crucial question for the efficiency of the analysis is the value of which suffices to achieve a certain precision in the results and guarantees that there is no mode missed. Unfortunately, no recipe exists for such a purpose generally. Moreover, not all precisions can be achieved efficiently. Let us define (11)

as the cutoff wavenumber relative error of a mode, where denotes that is calculated with a value in (8). Fig. 5 shows the behavior of the cutoff wavenumber relative error in a logarithmic scale for some modes represented in Table I, where it can be seen that, from a value , the improvement in approximation is rather low. Within that convergence zone, the key is

to choose the lowest that states that, in the analyzed interval, no mode is undetermined. Thus, we propose a method to adapt the value of to the order of the mode assuming that lower order modes might be represented with a lower number of functions than higher order modes. This adaptive scheme is possible as a result of a norm to proceed: variation in the number of modes in the analyzed interval. The algorithm for obtaining the number of zeros in the function in a given interval on the real axis is optimized,

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Fig. 7. Longitudinal field component. (a) Eccentric annular line. (b) Shielded bifilar line. (c) Shielded three-wire line. (d) Shielded four-wire line.

thus applying it twice for functions of , i.e., and such as be established.

with different values , different actions can

• If the number of zeros in the interval remains the same, then it is assumed that is still a good choice. • On the other hand, when the number of zeros is increased, obviously is considered a more suitable choice. Finally, in order to ensure a good convergence in all the results, the values of the zeros are determined with an greater than that suggested in this process. This procedure is accomplished interval by interval in such a way that the chosen value for propagates from this interval to the following one. The fundamentals for which only two evaluations of possible are required in an interval are: 1) a conservative initial value to begin this method in the positive real axis; 2) an appropriate difference between the values and ; and 3) a suitable interval size. Likewise, all these are closely related to efficiency considerations. The behavior of versus the cutoff wavenumber of the first 100 TE and TM modes of the structure of Fig. 4(b) for , , and is shown in Fig. 6, whereas Table II compares the cutoff wavenumbers of the first 20 TE and TM modes calculated with an adaptive and conservative . C. Comparisons Here, we aim to show the accuracy of the proposed analysis by comparing the results obtained with a 2-D finite-element

method (FEM) using second-order curved triangular isoparametric nodal elements and previously published data where possible, indicating, at the same time, the computational time used in the calculations on a Pentium IV 2.8-GHz PC. The cutoff wavenumbers of both of the first ten TE and the , TM modes in the structure of Fig. 4(a) for , and calculated by the proposed method are compared, in Table III, with those determined by a 2-D FEM and those published in [3], accompanied by Kuttler’s bounds [6]. In this eccentric annular line, we are able to compute the first 100 TE and TM modes in approximately 3.5 s. Table IV contains the cutoff wavenumbers of the first ten TE and TM modes in the structure of Fig. 4(b) for , , and . The time used to determine the cutoff wavenumber of the first 100 TE and TM modes in this shielded bifilar line is 5.6 s. The comparison between the last ten cutoff wavenumbers of the first 100 TE and TM modes in the structure of Fig. 4(c) for , , and is shown in Table V. It takes 13.3 s to determine the first 100 TE and TM modes. Regarding the geometry of Fig. 4(d), Table VI presents the cutoff wavenumbers of the first ten TE and TM modes for , , and . The first 100 TE and TM modes are computed in approximately 28.2 s. On the one hand, it can be seen that good agreement is achieved in all the comparisons. On the other hand, it has to be recognized that the computational effort depends on the numbers of conductors involved in the geometry since the size of the truncated dispersion matrix is a function of it.

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Finally, in Fig. 7, we detail the longitudinal field component of the modes highlighted in Tables III–VI. V. CONCLUSIONS An efficient method for determining TE and TM modes in cylindrical PECs and hoclosed waveguides made up of mogeneous isotropic media has been presented. The analytical approach constitutes an ad hoc formulation of the problem. The numerical considerations have been analyzed in detail, a robust and efficient algorithm has been proposed in order to work out the approximate characteristic equation, and a method to select the number of functions required to ensure an acceptable precision without missing any mode adaptively has also been established. Comparisons with a 2-D FEM and data available in literature, where possible, have been developed to demonstrate the correctness of the presented analysis. APPENDIX Definition of the function follows:

,

is as

[6] J. R. Kuttler, “A new method for calculating TE and TM cutoff frequencies of uniform waveguides with lunar or eccentric annular cross section,” IEEE Trans. Microw. Theory Tech., vol. MTT-32, no. 4, pp. 348–354, Apr. 1984. [7] B. N. Das and S. B. Chakrabarty, “Evaluation of cut-off frequencies of higher order modes in eccentric coaxial line,” Proc. Inst. Elect. Eng., pt. H, vol. 142, no. 4, pp. 350–356, Aug. 1995. [8] B. N. Das and O. J. Vargheese, “Analysis of dominant and higher order modes for transmission lines using parallel cylinders,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 4, pp. 681–683, Apr. 1994. [9] E. Abaka and W. Baier, “TE and TM modes in transmission lines with circular outer conductor and eccentric circular inner conductor,” Electron. Lett., vol. 5, pp. 251–252, 1969. [10] R. H. T. Bates, “Analytic constraints on electromagnetic field computations,” IEEE Trans. Microw. Theory Tech., vol. MTT-23, no. 8, pp. 605–623, Aug. 1975. [11] A. A. Kishk, R. P. Parrikar, and A. Z. Elsherbeni, “Electromagnetic scattering from an eccentric multilayered circular cylinder,” IEEE Trans. Antennas Propag., vol. 40, no. 3, pp. 295–303, Mar. 1992. [12] I. O. Vardiambasis, J. L. Tsalamengas, and K. Kostogiannis, “Propagation of EM waves in composite bianisotropic cylindrical structures,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 761–766, Mar. 2003. [13] J.-T. Kuo, “Vector finite Hankel transform analysis of shielded single and coupled microstrip ring structures,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 11, pp. 2161–2164, Nov. 1999. [14] G. N. Watson, A Treatise on the Theory of Bessel Functions, 2nd ed, ser. Cambridge Math. Library. Cambridge, U.K.: Cambridge Univ. Press, 1996, ch. 11, sec. 11.3. [15] P. M. Morse and H. Feshbach, Methods of Theoretical Physics. New York: McGraw-Hill, 1953, ch. 4, sec. 4.3. [16] L. M. Delves and J. N. Lyness, “A numerical method for locating the zeros of an analytic function,” Math. Comput., vol. 21, pp. 543–560, 1967. [17] R. W. Hamming, Numerical Methods for Scientists and Engineers, 2nd ed. New York: Dover, 1986, ch. 5, sec. 5.4. [18] J. Arroyo and J. Zapata, “Subspace iteration search method for generalized eigenvalue problems with sparse complex unsymmetric matrices in finite-element analysis of waveguides,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 8, pp. 1115–1123, Aug. 1998.

(A.1)

Valentín de la Rubia was born in Ciudad Real, Spain, in 1980. He received the Ingeniero de Telecomunicación degree from the Universidad Politécnica de Madrid, Madrid, Spain, in 2003, and is currently working toward the Ph.D. degree at the Departamento de Electromagnetismo y Teoría de Circuitos, Universidad Politécnica de Madrid. His research interests include numerical methods for microwave passive circuits and antennas design.

[1] S. A. Schelkunoff, Electromagnetic Waves. New York: Van Nostrand, 1945, ch. 10, sec. 10.6 and 10.7. [2] H. Y. Yee and N. F. Audeh, “Cutoff frequencies of eccentric waveguides,” IEEE Trans. Microw. Theory Tech., vol. MTT-14, no. 10, pp. 487–493, Oct. 1966. [3] L. Zhang, J. Zhang, and W. Wang, “Correct determination of TE and TM cutoff wavenumbers in transmission lines with circular outer conductors and eccentric circular inner conductors,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 8, pp. 1416–1420, Aug. 1991. [4] J. A. Roumeliotis, A. B. M. S. Hossain, and J. G. Fikioris, “Cutoff wave numbers of eccentric circular and concentric circular-elliptic metallic waveguides,” Radio Sci., vol. 15, pp. 923–937, Sep. 1980. [5] M. Davidovitz and Y. T. Lo, “Cutoff wavenumbers and modes for annular cross section waveguide with eccentric inner conductor of small radius,” IEEE Trans. Microw. Theory Tech., vol. 35, no. 5, pp. 510–515, May 1987.

Juan Zapata (M’93) received the Ing. Telecomunicación and Ph.D. degrees from the Universidad Politécnica de Madrid, Madrid, Spain, in 1970 and 1974, respectively. Since 1970, he has been with the Departamento de Electromagnetismo y Teoría de Circuitos, Universidad Politécnica de Madrid, initially as an Assistant Professor, then an Associate Professor (1975), and then a Professor (1983). He has been engaged in research on microwave active circuits and interactions of electromagnetic fields with biological tissues. His current research interest include computer-aided design for microwave passive circuits and antennas and numerical methods in electromagnetism, especially the FEM. Prof. Zapata is a member of the Editorial Board of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.

where

is the Kronecker delta. REFERENCES

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679

An Active Differential Broad-Band Phase Splitter for Quadrature-Modulator Applications Esa Tiiliharju, Member, IEEE, and Kari A. I. Halonen, Member, IEEE

Abstract—Area-efficient single-ended-to-differential phasesplitter (balun) integration is difficult for frequencies below 6 GHz. Few broad-band solutions are available, and those given in the literature often introduce quite high amplitude and/or phase errors to differential signaling. In this paper, a cascade of differential pairs is shown always to outperform any single-stage solution, and the measurement data for a two-amplifier prototype are supplied to support the theory. The prototype circuit was realized on 0.8- m SiGe as a 2.5-V RF integrated circuit measuring 1.2 1.2 mm2 including pads. The measured gain error is better than 1 dB up to 4.6 GHz, while phase difference is between 179.7 –180.9 in 0.6–4.1 GHz. The application of the realized phase splitter in a broad-band quadrature modulator is discussed. Index Terms—Phase splitter, quadrature modulator, SiGe.

I. INTRODUCTION

I

NTEGRATING a broad-band single-ended-to-differential phase splitter (balun) on silicon is problematic for frequencies below 6 GHz since: 1) waveguide or other distributed-element-based solutions consume too much area; 2) lumped-element baluns are narrow-band/area consuming; and 3) compact transistor-based solutions are generally not very good. Since 0.8–6 GHz is used in contemporary wireless standards like wireless local-area networks (WLANs), universal mobile telecommunications systems (UMTSs), etc., there is a demand for an accurate integrated balun solution. One important phase-splitter application example is driving an in-phase/quadrature (I/Q) modulator with a differential signal at microwave frequencies. In such an application, signals need to be very accurately balanced for proper circuit operation. To accomplish this for broad-band high-performance circuits, such as the 0.8–2.7-GHz quadrature modulator in [1], off-chip transformers could be used. This is not a desirable solution, however, since it introduces extra complexity and cost to the system. Active phase splitters that have been reported include singletransistor, common-gate–common-source (CGCS), or differential-pair implementations. Usually, single-transistor phase splitters [2] have too much phase error as a result of circuit parasitics, a situation that [3] seeks to correct with a pair of cross-connected correcting transistors. From [3], it is noted that the cross-connected transistor approach is not a promising solution for two reasons, which are: 1) seven integrated capacitors (excluding output buffering) are

Manuscript received January 19, 2004; revised July 12, 2004. This work was supported by Finland’s National Technology Agency TEKES and by Micro Analog Systems Oy, Espoo, Finland. The authors are with the Electronic Circuit Design Laboratory, Helsinki University of Technology, 02150 Espoo, Finland. Digital Object Identifier 10.1109/TMTT.2004.840566

needed to make it work—and, thus, there is a great deal of parasitic capacitance involved and 2) for better balance, each transistor should have equal gain from the gate to the source/drain terminals: this limits the topology to use in low-gain applications. The combination of these two points does not imply a promising broad-band performance for this topology. In contrast, the modified CGCS topology in [4] is much more dB (gain error) and – promising: (phase difference) values are reported in 0.5–4 GHz. A problem with this topology is the reported 5-dB loss, despite the 0.3- m technology used. Thus, as any differential pair offers the possibility of implementing gain in the signal path, it should be the chosen starting point for a lower microwave-range phase-splitter implementation. One such implementation is the emitter–follower-driven differential pair in [5] with a reported performance of: dB and – in 0.5–5 GHz. In [6], an asymmetrical feedback LCR network consisting of an inductor, a capacitor, and resistors is suggested as a means for improving differential-pair phase-splitting performance with dB and . However, the asymmetrical LCR-feedback topology makes achieving good performance an intensive design task as performance hinges on voltage-dependent parasitics etc. To improve even-order signal rejection, differential pairs can be cascaded: [7] uses a single-transistor balun to drive a cascade of two differential pairs to achieve a good phase-splitter perfordB and in 0.2–5 GHz. For mance at this performance, a 1- m epitaxial GaAs MESFET technology with air bridges and metal–insulator–metal (MIM) capacitors was used. The purpose of this paper is to analyze and quantify the improvement in differential signaling that is achievable through cascading. A further goal is to evaluate the practical usability of such a cascaded differential-pair phase splitter through statistical and other methods. To assist in this evaluation, measured results will be shown in support of the theory: a nominal dB up to 4.6 GHz and in 0.6–4.1-GHz performance will be compared to data at different biasing points. Application as an integrated local-oscillator (LO) balun in a broad-band direct-conversion quadrature modulator [8] will be discussed and compared to a single differential-pair LO balun. This paper is organized as follows. In Section II, a single differential pair is shown to have an inherent asymmetry in balun applications; in Section III, it is shown that the use of two or more cascaded differential pairs for phase splitting produces a fundamental improvement in accuracy. Section IV discusses the implementation of the proposed phase splitter as a 0.8- m SiGe

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Fig. 1. (a) Differential pair used as a phase splitter and (b) its small-signal model.

RF integrated circuit (RFIC). In Section V, measurement results are shown to support the theory, and Section VI discusses application in a direct-conversion quadrature modulator. Finally, Section VII presents conclusions. II. DIFFERENTIAL PAIR PHASE SPLITTING Fig. 1(a) depicts a bipolar differential pair connected as a phase splitter. This particular amplifier was realized in 0.8- m SiGe with GHz. Its simulated performance includes 13 dB of low-frequency voltage gain, 40-GHz 0 dB-bandwidth, and 7.1-mA current drawn from a 2.5-V supply. These results were obtained using an ideal (voltage) signal source with infinitely small source impedance and inductively peaked resistive loading. and ) as state variables the Using nodal voltages ( amplifier in Fig. 1(a) can be presented in matrix form as (1) From (1), it can be seen that perfect single-ended-to-differential conversion (outputs ) is possible if . To define the coefficients and , linear operation is assumed; the resulting small-signal model is seen in Fig. 1(b). To further simplify analysis, the use of an ideal signal source, as in [9], is assumed. Thus, the summing of currents and the analysis of the resulting equations yields definitions for and as (2) (3) Dividing (2) by (3) makes possible the definition of of as

in terms

Fig. 2. Simulated differential-pair gain and phase errors versus frequency.

equation. Thus, any differential pair is intrinsically asymmetric as a balun. Although the intrinsic asymmetry predicted by (4) is very small near dc, it gets rapidly worse with increasing frequency. This is caused by parasitic capacitance in parallel with the current source resistance , which transforms it to a frequencydependent complex impedance . To improve differential-pair common-mode rejection (CMR) cascoding of current source transistors, or an inductively compensated current source (as in [10]) could be used. Alas, cascoding of current–source transistors is not an option since it is not compatible with the specified 2.5-V supply, and the specified broad-band operation precludes use of integrated coils, as these will resonate with ubiquitous parasitics to produce a narrow-band response. The asymmetry of the differential-pair balun is also evident in the simulated gain-phase error plot shown in Fig. 2, where balun operation is near perfect at dc, but rapidly gives worse results at higher frequencies. Targeting WLAN/UMTS applications, the simulated gain and phase errors at 2.4 GHz are 0.6 dB and 3.1 , respectively. Maximum gain error peaks at 1.5 dB, 0.6 . while phase error varies between 11.5 III. CASCADED PHASE SPLITTING A block diagram presentation of a single-stage differentialpair phase splitter is given in Fig. 3(a). This block diagram is a symbolic presentation for a differential-pair phase splitter. Thus, comparison of Figs. 1(a) to 3(a) justifies equating signals and ) with their state variable ( and ) counterparts, respectively. The block diagram presentation is used to model a cascade similar differential pairs, which are connected as a of 0 180 phase splitter. This model is shown in Fig. 3(b). It can be described with a chain matrix equation as

(4)

Since both

and , a small error quantity is defined to represent the fractional part of the

where

for all

(5)

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681

Fig. 3. Differential-pair block diagrams connected as: (a) one-stage and (b) cascaded phase splitters.

Now, recalling definition (4), performing the necessary algebraic manipulations makes possible the presentation of factors and as a function of for all positive integer values as

(6) To complete this set of definitions, a generalized form for the factors and for -cascaded blocks can be written as

where

is an

-degree polynomial for all

(7)

Dividing by , as defined in (7), makes possible the definition of in terms of and a small error factor as (8) Comparison of the error terms and in (4) and (8) can be used in estimating the effect cascading has on phase-splitter accuracy. Assuming that accuracy is increased by cascading leads to the following inequality: (9)

Fig. 4. Simulated gain and phase errors of the cascaded phase splitter versus frequency.

in (7) and the definition of Combining the definition of as a small positive error factor constitutes proof for (9). Thus, cascading decreases phase-splitting errors of differential-pair baluns. To quantify the available improvement in cascaded (8) are phase-splitting is set to 0.4 and the values of 1.4000 1.0571 1.0093 1.0015 1.0003 . calculated: Thus, a 40% mismatch is reduced to 5.7% after the addition of one stage. The improved phase-splitter operation of the cascaded differential-pair phase splitter is also evident as simulated gain-phase error data in Fig. 4 is compared to the corresponding data for the single stage in Fig. 2. Near-perfect phase splitting is predicted by the data simulated for a cascade of two differential pairs. Targeting WLAN/UMTS applications simulated gain and phase errors at 2.4 GHz are 0 dB and 0.3 , respectively. 0.1 dB, while Maximum gain error varies between 0.1 0 . Comparison of phase error varies between 2.4 values at 2.4 GHz shows a definitive improvement as gain and phase errors are reduced by 0.6 dB and 2.8 , respectively. IV. IMPLEMENTED SiGe CASCADED DIFFERENTIAL-PAIR PHASE SPLITTER For the RFIC prototype realization of Fig. 3(b), a cascade differential pairs was realized. Since broadof two band operation extends to several gigahertz, three design issues arise, which are: 1) parasitic capacitances should be taken care of for higher bandwidths; 2) the effect of process variation on phase-splitting accuracy should be determined; and 3) the inputmatching circuitry to 50 has to introduce a minimum amount of error in the circuit’s phase-splitter function. A. Implementation of the Cascade The implemented phase splitter is shown in Fig. 5 with emitter areas (length in m, minimum width of 0.8 m used) and branch currents annotated to this figure. The RFIC has been

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TABLE I SIMULATED MONTE CARLO VARIATIONS AT 2.4 GHz FOR 500 RUNS

Fig. 5. Cascaded differential-pair phase-splitter circuit with matching circuit details shown.

realized in the Austria Mikro Systeme (AMS) 0.8- m SiGe GHz. process with The process supports high-density poly-to-poly capacitors and integrated coils, and it has a high-ohmic resistor module. In fact, the integrated feedback resistors (marked as “RB”) for biasing amplifier input transistor pairs were realized using high-ohmic resistors. At 8.7 k , they do not interfere with the phase-splitting function of the circuit. The differential pairs were buffered with emitter followers in order to let each stage perform its balun function without interference, and to maximize bandwidth. This was especially important for the quadrature-modulator application [8], where a lossy multistage polyphase filter was used for phasing the LO signal at 90 (quadrature) offsets. The resulting amplifier blocks are marked as Amp1 and Amp2, where the Amp1 input stage is a buffered realization of the differential pair in Section II. were implemented as Both differential pairs small-signal amplifiers without resistive linearization since simulations predicted that best broad-band balun operation will be attained in this way. Beneficially this produces high gain, which coincides with the design goal of lowering the required LO drive level to the quadrature modulator. As another bandwidth-increasing measure, the resistive loads “R” of the first amplifier Amp1 were inductively gain peaked [11] for approximately double bandwidth of the circuit. Integrated 2.5-nH planar coils were used for the purpose since no high- values are needed. A downside of the cascaded differential-pair phase-splitter approach is increased current consumption, but it should be noted that: 1) improved phase-splitter operation is inherent to cascading, and no current increase of a single differential pair will correct this; 2) there is no output buffering (and corresponding parasitics) in the comparison differential pairs; and 3) at higher frequencies, gain has to be divided between stages in numerous applications. B. Process Variations To assess cascaded differential-pair phase-splitter performance tolerance of process variations, statistical simulations and standard deviation of were performed. Mean and at 2.4 GHz were tabulated in Table I after 500 Monte Carlo runs. Similar data were tabulated for the differential pair for comparative purposes.

The importance of Monte Carlo simulations in assessing realistically attainable circuit performance (and yield) is based on the fact that different circuit elements share layers in modern processes. Thus, imitating process variations by perturbing a single element value is admittedly fast, but perhaps too inaccurate. Two types of Monte Carlo simulations were performed: LOT and DEV. In LOT simulations, each element of the same type (e.g., all npn transistors) is modeled with the same Monte Carlo solution, while in DEV, each element has an individual Monte Carlo result. Thus, LOT simulations imitate die-to-die variation, while DEV is good for modeling element-to-element variation. The DEV results in Table I were obtained using the foundryprovided LOT parameters by dividing each variation by 20. This 5% relation was chosen to reflect the fact that the matching between elements in an integrated circuit is very good. Both the DEV and LOT results in Table I closely correspond values, which complies with the to tabulated nominal known robustness of the differential pair. However, recorded values for the differential pair at (1.0 , 0.2 , 1,1 ) suggest a much higher variance in performance when compared to the corresponding values for the cascaded differential-pair phase splitter (0.1 , 0.1 , 0.2 ). C. Matching to 50- With Integrated Passives The matching of the cascaded differential-pair phase400 fF) to 50 was splitter’s input (npn base at 700 realized with the circuit block marked as Matching in Fig. 5. An integrated passive matching circuit was chosen for two reasons, which are: 1) to save power and 2) to improve the values. circuits large signal behavior for increased Another demand on a matching circuit is that it should not disturb phase-splitter operation. To accommodate both matching and unspoiled phase-splitter operation, large on-chip capacitors (50/25 pF) connected to an inductively peaked resistive pole were designed. Simulations with layout extracted parasitics suggest good matching, with input return loss values below 10 dB in 0.4–6.3 GHz. A comparison of simulated gain and phase errors shows that the realized matching circuit has a negligible effect on phase-splitter performance, and suppression of even-order harmonics is good. A 3-dBm signal power backoff from dBm imthe tabulated compression point of proves suppression of the third harmonic (3RD) to 37 dBc

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TABLE II SIMULATED VALUES FOR THE CASCADED DIFFERENTIAL-PAIR PHASE SPLITTER AT 2.4 GHz

Fig. 7. Comparison of measured s

Fig. 6. Micrograph of the 0.8 m 1.2

2 1.2 mm

and s

to simulated data.

SiGe RFIC.

( 31 dBc). Simulated performance data at 2.4 GHz in typical mean conditions are summarized in Table II. As ambient temperature was swept from 55 C to 110 C, values held at tabulated values, while corthe resulting responding gain of the circuit varied from 10 dB at 55 C to 4 dB at 110 C. This confirms the expected robustness of the differential-pair phase-splitting action, while use of on-chip current-driven bias block facilitates simple addition of proportional to absolute temperature (PTAT) biasing for constant gain values. V. MEASUREMENT RESULTS A micrograph of the realized 0.8- m SiGe RFIC is shown in Fig. 6. The chip measures 1.2 1.2 mm including the pad arrangements to accommodate ground–signal–ground (GSG)type wafer probing. Pad and circuit block labeling corresponds to schematics in Fig. 5, while all unmarked pads have been connected to circuit ground at RFIC circumference. To facilitate calibration to RFIC, a ground–signal– ground–signal–ground (GSGSG)-type probe with two signal (S) lines was used: the two outputs were each calibrated using calibration standards realized on a 50- impedance standard substrate (ISS) block. During calibrations, cable for the unused output was terminated with a broad-band 50- load, while the other cable was connected to the vector network analyzer

Fig. 8. Comparison of measured

1A and  to simulated data.

(VNA). Switching between the cable terminations (VNA, 50 ) allowed for the GSGSG probe to be kept fixed on the RFIC. To ensure validity of the corresponding calibration sets, the two output cables were kept fixed for most of their length. The resulting two sets of measured gain and phase values were subtracted in order to define the amplitude and phase error of the differential output. A narrow 4% smoothing window was applied to the measured data in order to filter out random noise without introducing a significant systematic error into the results. and are shown in The measured scattering parameters Fig. 7 in comparison to the simulated data. The simulated values were obtained using a layout extracted netlist with a parasitics description. The difference between the measured and simuvalues at higher frequencies reflects inductor model lated inaccuracy. data under nominal conditions are disThe measured played in Fig. 8, where gain error is better than 1 dB up to 4.6 GHz, and phase difference is 179.7 –180.9 in 0.6–4.1 GHz. Thus, good phase-splitter performance was achieved for nearly a decade of variation in input frequency.

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Fig. 9.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Measured: (a) gain errors and (b) phase differences during supply voltage V

sweeps.

Fig. 10. Measured: (a) gain errors and (b) phase differences as circuit is biased to draw supply currents I

The results in Figs. 7 and 8 were measured with the RFIC drawing 22.8 mA from a 2.5-V supply. This 57-mW biasing point was chosen to produce maximum quadrature-modulator power output [8] with a reasonably clean spectra. Application of a modern smaller minimum linewidth technology should significantly reduce both the power and current dissipation of the circuit. To test sensitivity of the realized balun circuit to different operating conditions, its point of operation was tuned as follows: the supply voltage was swept from 2 to 3.6 V in 0.4-V steps with nominal bias and the current bias was tuned to control current dissipation of the circuit between 15.2–26.2 mA in 3.7-mA steps from the nominal 2.5-V supply. The results from these measurements are plotted in Figs. 9(a)–10(b) as follows. plots at an offset • Only data measured using 2-V and from an otherwise tightly knotted group in both

: 15; . . . ; 26 mA.

results in Fig. 9(a)and (b). This is an expected result for the 2.5–5.5-V technology used. • Phase difference peaks above 182 for the –mA current dissipation; gain error performance remains practically unaffected (to within 0.25 dB) for each biasing point. These results at different biasing points demonstrate the genuine robustness of the cascaded differential-pair phase-splitter balun approach, while the use of inductor gain peaking and a passive broad-band matching circuit aided the achievement of a near-decade phase-splitter performance with regular SiGe technology. The proposed circuit compares well with performance values reported for state-of-the-art solutions [6], [7] despite the fact that it is measured with output buffering intended for driving a difficult RC load in a quadrature-modulator application.

TIILIHARJU AND HALONEN: ACTIVE DIFFERENTIAL BROAD-BAND PHASE SPLITTER

TABLE III QUADRATURE-MODULATOR CHARACTERISTICS SIMULATED WITH DIFFERENT LO BUFFERS

VI. APPLICATION TO A BROAD-BAND QUADRATURE MODULATOR The proposed balun circuit was originally developed as an integrated single-input LO buffer for the direct-conversion quadrature modulator in [8]; this approach avoids the use of two parallel cascaded differential pairs and tuning circuitry, as in [12]. There were two design objectives for the proposed balun, which were that: 1) it should drive the quadrature modulator with a nearly perfectly balanced LO signal for better spectral purity of mixing products and 2) it should have high gain so that the quadrature modulator could be driven with a low-power LO source; this contributes to achieving a low LO-leakage level at the quadrature-modulator output. To test whether the design goals were met, the quadrature modulator in [8] was characterized with three different LO buffers: the proposed phase-splitter circuit was compared against an ideal transformer and a single-stage differential pair (diffpair). The tabulated results in Table III indicate that better spectral purity with a lower LO power can be achieved using the proposed balun instead of a single differential pair. Image-rejection ratio (IRR) and 3RD suppression are dominated by quadrature-generation accuracy and mixer distortion, but suppression of even-order spurious products depends on differential signal balance. The tabulated carrier (CRR) and second harmonic (2ND) rejection ratios show a definitive improvement for the proposed balun circuit. 2ND rejection even surpasses the 100-dB limit set for the use of in Table III. The obvious disadvantages of cascading are higher noise and power dissipation, but its 12-dBm lower LO power requirement could compensate for these disadvantages in frequency synthesizer design. VII. CONCLUSION In this paper, theoretical analysis has been applied to show that a cascade of two or more differential pairs is fundamentally more accurate as a phase splitter than a single standalone differential pair. Theoretically, a 40% mismatch in a single differential-pair phase splitter is converted to much smaller values

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of 5.7% or 0.9% by a cascade of two or three similar stages, respectively. The measured amplitude error is better than 1 dB up to 4.6 GHz, while phase difference stays between 179.7 –180.9 in 0.6–4.1 GHz. This phase-splitter performance for a variation of nearly a decade in input frequency has been achieved without tuning. Biasing point sweeps produce near-nominal performance so the circuit has good tolerance of variation in biasing point and parasitics. This claim for robust operation is backed by statistical simulations, which, in fact, predict improved tolerance of process variations for the proposed phase splitter. Application of the phase splitter to a direct-conversion quadrature-modulator produces lower transmitted spurious signal levels at the cost of higher noise and power dissipation. However, as this performance has been achieved with lower LO power, it is possible to utilize this in frequency synthesizer design. On the basis of theoretical and experimental data, it is felt that this level of broad-band phase-splitter performance with an integrated circuit at lower microwave frequencies is virtually impossible with any other technique. ACKNOWLEDGMENT The authors acknowledge K. Stadius, Electronic Circuit Design Laboratory, Helsinki University of Technology, Espoo, Finland, for his help on wafer probing measurements. REFERENCES [1] B. Sam and P. Halford, “High-performance quadrature modulators for broadband wireless communication,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., 2001, pp. 17–20. [2] H. Koizumi, S. Nagata, K. Tateoka, K. Kanazawa, and D. Ueda, “A GaAs single balanced mixer MMIC with built-in active balun for personal communication systems,” in IEEE Microwave Millimeter-Wave Monolithic Circuits Symp. Dig., 1995, pp. 77–80. [3] M. Goldfarb, J. Cole, and A. Platzker, “A novel MMIC biphase modulator with variable gain using enhancement-mode FET’s suitable for 3 V wireless applications,” in IEEE Microwave Millimeter-Wave Monolithic Circuits Symp. Dig., vol. I, 1994, pp. 99–102. [4] M. Kawashima, T. Nakagawa, and K. Araki, “A novel broadband active balun,” in 33rd Eur. Microwave Conf., Munich, Germany, 2003, pp. 495–498. [5] K. W. Kobayashi, “A novel HBT active transformer balanced Schottky diode mixer,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 2, 1996, pp. 947–950. [6] H. Ma, S. J. Fang, L. Fujiang, and H. Nakamura, “Novel active differential phase splitters in RFIC for wireless applications,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2597–2603, Dec. 1998. [7] S. K. Altes, T.-H. Chen, and L. J. Ragonese, “Monolithic RC all-pass networks with constant-phase-difference outputs,” IEEE Trans. Microw. Theory Tech., vol. MTT-34, no. 12, pp. 1533–1537, Dec. 1986. [8] E. Tiiliharju and K. Halonen, “A 0.75–3.6 GHz SiGe direct-conversion quadrature-modulator,” in Proc. 29th Eur. Solid-State Circuits Conf., Estoril, Portugal, Sep. 2003, pp. 565–568. [9] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed. New York: Wiley, 1993. [10] J. Lin, C. Zelley, O. Boric-Lubecke, P. Gould, and R. Yan, “A silicon MMIC active balun/buffer amplifier with high linearity and low residual phase noise,” in IEEE MTT-S Int. Microwave Symp. Dig., 2000, pp. 1289–1292. [11] R. G. Meyer, W. D. Mack, and J. E. M. Hageraats, “A 2.5-GHz BiCMOS transceiver for wireless LAN’s,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2097–2104, Dec. 1997. [12] A. Bóveda, F. Ortigoso, and J. I. Alonso, “A 0.7–3 GHz GaAs QPSK/QAM direct modulator,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1340–1349, Dec. 1993.

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Esa Tiiliharju (S’94–M’04) was born in Rovaniemi, Finland, in 1966. He received the M.Sc. degree in information technology and Lic.Tech. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 1998, in 1995 and 1998, respectively, and is currently working toward the Ph.D. degree in electronic circuit design at the Helsinki University of Technology. From 1996 to July 1997 he was an Assistant with the Helsinki University of Technology, and since 1997, he has been a Research Assistant with the Electronic Circuit Design Laboratory, Helsinki University of Technology. He has authored or coauthored several internationally refereed conference and journal publications on analog integrated circuits. His research interests include the design of integrated low-power circuits for portable telecommunication applications. He has designed and measured several integrated circuits for this application area.

Kari A. I. Halonen (M’02) was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT), Espoo, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1987. From 1982 to 1984, he was an Assistant with HUT and a Research Assistant with the Technical Research Center of Finland. From 1984 to 1987, he was a Research Assistant with the Electronics, Systems, Automation, and Technology (ESAT) Laboratory, Katholieke Universiteit Leuven, under a temporary grant from the Academy of Finland. Since 1988, he has been with the Electronic Circuit Design Laboratory, HUT, as a Senior Assistant (1988–1990) and as the Director of the Integrated Circuit Design Unit of the Microelectronics Center (1990–1993). During the 1992–1993 academic year, he was on a leave of absence, acting as a Research and Development Manager with Fincitec Inc., Kemi, Finland. From 1993 to 1996, he was an Associate Professor and, since 1997, he has been a Full Professor with the Faculty of Electrical Engineering and Telecommunications, HUT. In 1998, he became the Head of the Electronic Circuit Design Laboratory. He has authored or coauthored over 150 international and national conference and journal publications on analog integrated circuits. He holds several patents on analog integrated circuits. His research interests are CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. Dr. Halonen was an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS (1997–1999). He has been a guest editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He was the Technical Program Committee Chairman for the European Solid-State Circuits Conference in 2000. He was the recipient of the Beatrice Winner Award presented at the 2002 IEEE International Solid-State Circuits Conference.

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Design of an RF Low-Noise Bandpass Filter Using Active Capacitance Circuit Young-Hoon Chun, Member, IEEE, Jae-Ryong Lee, Member, IEEE, Sang-Won Yun, Member, IEEE, and Jin-Koo Rhee, Member, IEEE

Abstract—In this paper, a novel RF active bandpass filter (BPF) is proposed and its noise performance is optimized by noise analysis. In the proposed design, a resonator consists of an active capacitance circuit together with a conventional inductor. The active capacitor is made of a field-effect transistor that exhibits negative resistance as well as capacitance. It can, therefore, compensate the loss of an inductor. Whereas the conventional active filters using negative resistance circuits usually have a high noise figure, the proposed active filter shows good noise property achieved by adopting a novel active capacitance circuit, which is proven by noise analysis and the experimental result. The measured second-order active BPF shows bandwidth of 95 MHz, 0.1-dB insertion loss, 0.3-dB ripple, and a noise figure of 2.4 dB at the 1.9-GHz band, which agrees well with the simulated results. Index Terms—Active filters, bandpass filters (BPFs), capacitance, filter noise, negative resistance circuits, noise.

I. INTRODUCTION

M

ONOLITHIC microwave integrated circuit (MMIC)/RF integrated circuit (RFIC) technology becomes popular as GaAs- and Si-based processes mature today. Even though there has been much effort to integrate into a single chip with the whole system, one of the major difficulties to accomplish a fully integrated RF front-end is the integrated RF bandpass filters (BPFs). When we shrink the volume of an integrated RF filter, it shows poor performances. It still requires more progress for commercial usage, whereas there have been several attempts to overcome this problem, such as active resonators, since the 1960s [1]–[9] and RF microelectromechanical systems (MEMS) filter designs [10]–[14]. On the other hand, the design of passive filters has been extensively studied over the last 50 years. The major interest in the design of miniaturized narrow BPFs is the low insertion loss, which requires resonators with a high-quality ( ) factor. It is well known that the smaller resonator, the smaller their values. Therefore, increasing with a smaller resonator size is the key for the integrated BPF design. During the past ten years, numerous researchers have published active filter design Manuscript received February 16, 2004; revised July 17, 2004. This work was supported by the Korea Science and Engineering Foundation under the Engineering Research Center program through the Millimeter-Wave Innovation Technology Research Center, Dongguk University. Y.-H. Chun and J.-K. Rhee are with the Millimeter-Wave Innovation Technology Research Center, Dongguk University, Seoul 100-715, Korea (e-mail: [email protected]; [email protected]). J.-R. Lee is with the Samsung Electronics Company, Kyounggi-Do 442-742, Korea (e-mail: [email protected]). S.-W. Yun is with the Department of Electronic Engineering, Sogang University, Seoul 121-768, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840565

methods based on active resonators [1]–[9], active couplings [15]–[17], or other schemes [18]–[22]. For active BPFs to provide useful alternatives of their passive counterparts in many applications such as receivers, their corresponding noise figures should be comparable with those of the competing passive filters. Some of active BPFs, unfortunately, did not show good noise figures, and the other types are not applicable to the narrow BPF design. Also, it could be possible to face a problem that a negative resistance circuit becomes unstable because of an insufficient forecast for the negative resistance value as the frequency varies. Reference [4] shows the feasibility for an active filter using a negative resistance circuit to have a good noise performance. In this paper, we especially analyze in detail the new type of active resonator based on an active capacitance circuit. We also present its design method based on the conventional microwave passive BPF design using immittance inverter theory. We wish to discuss the frequency-response characteristic of equivalence resistance for the circuit, which has a series feedback circuit of a common-source structure, as depicted in Fig. 1(a). Through the simulated and measured results, it is shown that the proposed RF active filter can be applicable to the narrow BPF design, which also possesses low-noise characteristics. II. NEGATIVE-RESISTANCE THEORY Most of the negative resistance topologies are composed of common-source or common-gate series feedback structures. These feedback structures are usually used for oscillator design, and the noise performance of overall circuits is degraded by a series feedback structure. The proposed topology is common-source and an R–L–C series feedback structure. Fig. 1(a) shows the structure and equivalent circuit of this topology. It is different from the conventional types in the oscillator design methods. It does not use a common-gate series feedback structure or any additional drain- or source-to-gate parallel feedback paths, which may decline the noise performance. Therefore, the noise performance can be improved by the proposed topology. The active capacitor made of a field-effect transistor (FET) exhibits a negative resistance property, as well as capacitive property. This topology is simple in structure and could be conveniently applied to the narrow-band filter design. Fig. 1(b) represents the equivalent circuit of Fig. 1(a). In Fig. 1(b), the input admittance can be written as follows:

0018-9480/$20.00 © 2005 IEEE

(1)

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TABLE I PARAMETERS OF AN FET AND A SERIES FEEDBACK CIRCUIT FOR INSTANCE

In the real part of (2), we can find the frequency range in which the circuit has negative resistance, as shown in (4)–(6) at the bottom of this page, where

The frequency that shows the maximum negative resistance is able to be expressed as follows: Fig. 1. (a) Proposed active capacitance circuit and (b) its simple equivalent circuit.

where the parameters are

(7) , the negative resistance is achieved as in the simple If relationship of (8) as follows: and

These relationships can be summarized as follows in (2) as concerns all series feedback circuit elements:

(2) where (3)

(8)

For the graphical illustration, a sample FET and a series feedback circuit are invoked. We performed calculations using these parameters, which are shown in Table I, and their results are shown in Figs. 2 and 3. Fig. 2 shows the frequency ranges in which the active capacitance circuit has negative resistance characteristic as the feedvaries from 0 to 100 . In this figure, we back resistance can find that the frequency range gets narrower and the frequency with maximum negative resistance gets lower as

(4) (5)

(6)

CHUN et al.: DESIGN OF RF LOW-NOISE BANDPASS FILTER USING ACTIVE CAPACITANCE CIRCUIT

Fig. 2. Frequency ranges in which the active capacitance circuit has a negative resistance characteristic as the feedback resistance (R ) varies.

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Fig. 4. Active resonator circuit, which consists of the proposed active capacitor (FET and Z ), external capacitors (C and C ), and a conventional inductor with loss (R ).

Fig. 5. Simplified schematic diagram of an active capacitor, which is composed of an FET and indictor (L ), and its equivalent circuit.

Fig. 3. Frequency responses as the feedback resistance (R ) varies.

becomes larger. The frequency responses proportional to are shown in Fig. 3. From these, we can draw the following conclusions. to . 1) Negative resistance can be obtained from makes the frequency range with negative 2) The larger resistances shrink and negative resistance decrease. is dominated by : becomes higher when be3) comes smaller. is dominated by : becomes lower when be4) comes larger. and effect on the maximum value of negative resis5) tance: the maximum value of negative resistance becomes or become larger. higher as We find that negative resistance can be obtained when the is inductive and the series network, drain feedback network and , is capacitive. Also, the frequency which consists of range with a negative resistance property is dominated by and , as considered in the above relationships. This means that the equivalent reactance value of an active capacitance cirand , and should be inductive cuit is determined by within the frequency range with a negative resistance property.

After evaluating the equivalent reactance value, we can deterto adjust the overall equivalent mine the adequate value of resistance level, as shown in Figs. 2 and 3. At first, we assumed in order to evaluate an equivalent circuit where that is an effective inductance value of within this frequency range. Fig. 4 shows an active resonator using the proposed active and can adcapacitance circuit. The external capacitors just the values of effective capacitance and negative resistance of an active capacitance circuit when we change their capaci, tances. A negative resistance can be obtained when and an active capacitance circuit can be simplified as depicted in Fig. 5, which coincides with the result of (2) as the following relationships: (9) (10) and . where The proposed topology can make negative resistance by the feedback and gate-to-drain capacitor . The negative , is also frequency dependent. Connecting shunt resistance with a proposed negative resistance circuit makes inductor it resonate at a certain frequency. An active resonator circuit

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Fig. 6. Equivalent circuit of a resonator employing the proposed active capacitance circuit of which equivalent impedance is represented as C and R .

Fig. 7.

Active two-pole BPF with lossy inductors.

Fig. 8.

Noise models of the lossy inductor and the active capacitance circuit.

can be more simplified like an L–C tank circuit with resistance , as described in Fig. 6. and [23], When we get (11)

where

(12) : the quality factor of an inductor (13) The resonance frequency is (14) In order to make a lossless and stable resonator, we would equal to as follows: choose the value of (15) , and If one of the unknown the design parameters ( ) is decided, the other parameters can be calculated using the above equations using the condition of (14) and (15).

Fig. 9. Noise analysis: two-pole BPF circuit model.

(17) III. NOISE ANALYSIS In order to analyze a low-noise two-pole active BPF in Fig. 7, active resonators are replaced by equivalent circuits, which consist of parallel L–C and short-circuit noise sources, as depicted in Fig. 8. Subsequently, the final equivalent circuit for the noise analysis of a two-pole BPF is formed as shown in Fig. 9. In the same way as in Section II, we can calculate the shortas the following equations: circuit noise current (16)

(18) is the 50- noise figure of the MESFET. where The total noise figure of the active BPF can be calculated by the method in [7]. The calculated result is shown in (19) as follows:

CHUN et al.: DESIGN OF RF LOW-NOISE BANDPASS FILTER USING ACTIVE CAPACITANCE CIRCUIT

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where

(19)

and are the low-pass filter prototype parameters. is reformulated as the folBy substituting (12) into (19), lowing equation:

(20) Furthermore, when we apply the condition of (14) and (15), we can estimate the noise figure of the BPF at the center frequency as follows: (21) The above expression reveals that it is not the capacitances and feedback inductance , but the passive proof an intotype parameters, the fractional bandwidth, the ductor, and the unmatched noise figure of the FET to dominate the overall performance of the proposed filter circuit under this condition. Negative resistance characteristics are obtained from the common-source capacitive feedback, which is commonly used for oscillator design in the most previously reported topologies. They could easily affected by the drain (or collector) noise current of the MESFET [or bipolar junction transistor (BJT)] because the source is generally involved with capacitive feedback, as far as the noise characteristics are concerned. The noise figure of active filters using such topologies is inevitably large. Therefore, it is necessary that the drain noise current source is minimized in the negative resistance circuits. The proposed circuit is based on the common-drain inductive and capacitive series feedback and equivalently provides the capacitance and negative resistance. Through the noise analysis, we can conclude that this topology has an inherently low-noise property when the loss induced from an inductor is exactly compensated by the negative resistance of the active capacitor. IV. DESIGN OF THE BPF It is possible to design a low-noise active microwave filter through the above analysis. The basic filter design procedure follows Cohn’s for the design of direct-coupled resonator filters [24]. We have adopted the shunt resonator capacitively coupled configuration. This configuration was also considered when it was analyzed above. The value of inductors was determined by the availability of commercial chip inductors. At first, we considered the simple active capacitance circuit,

Fig. 10.

Block diagram for the designed two-pole active BPF.

as shown Fig. 1, for convenience. Using the small-signal equivalent-circuit parameters of an FET, we can calculate the equivalent admittance of an active capacitance, as shown in (1) and (2). For convenience, we have determined the initial values and under the condition of series feedback parameters of . These values can be calculated using (4) and (8) when the frequency range at which an active capacitance circuit should have negative resistance is defined. For the stability and low-noise property, we should adjust the value of . Increasing makes an active capacitor have low negative resistance and shrink the frequency range with negative resistance, as shown in Figs. 2 and 3. We decided the initial values of and with the consideration of this characteristics. After we designed a series feedback network, we should tune and . Even though the resonance frequency by adding it influences the negative-resistance value, its variation is limited. We can substitute a passive resonator with a novel active resonator through the above procedure.

V. EXPERIMENTAL RESULTS As an example, we designed and tested a new type of RF active BPF. First, we designed a passive BPF using J-inverters from a low-pass prototype filter. From the passive filer, we substituted capacitors in resonators with active capacitance circuits, which were discussed above. Fig. 10 shows the schematic of a second-order active BPF using an active capacitance circuit. It has a center frequency of 1.9 GHz and a bandwidth of 95 MHz. The resonance circuit is composed of an active capacitance circuit and a shunt inductor of which value was decided by the convenience of obtaining. At this example, we have an inductance of 1.8 nH. The active capacitance circuit is composed

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TABLE II FEEDBACK CIRCUIT PARAMETERS FOR A COMPARISON

of an Agilent GaAs FET, ATF-34143, and commercially available lumped elements. The bias condition for the GaAs FET is V and mA. Under this bias condition, it has low noise property and a stable operation can be obtained. The quality factor ( ) of an inductor can be enhanced by the negative resistance circuit, which can compensate the losses of the resonator. Using its equivalent-circuit model, we can perform simulations to estimate the equivalent admittance. In order to show the design procedure, which was discussed in Section IV, we have designed two-pole active filters. By the method of Secand under tion IV, we at first chose the feedback elements . In this example, the frequency range the condition of with negative resistance is limited from 1.5 to 2.5 GHz. We can and using (8). If pF, determine the values for pF and nH. They the initial value can be is not should be adjusted when we consider the situation that 0 and the parasitic from microstrip lines used for the soldering and interconnections. The growing forces to have lower reduce , as discussed in Section III. value because larger Also, we should use larger capacitance for and lower inducwhen we insert microstrip lines. Also, adding tance for and could adjust the capacitance of an active capacitor for an active resonator to have its resonance frequency of 1.9 GHz. We can optimize the feedback parameters and external capacitors using commercial simulators. In order to get equal insertion loss in the passband and good stability, we designed series feedback circuits so that an active resonator takes adequate negative resistance values and an overall stability factor ( ) of an active filter is large enough. For the purpose of demonstrating the dependency between and the flatness at the passband, and the stability of an active BPF, two types of active resonator, which have the same topology with different values of series feedback circuits, are chosen. The detailed circuit parameters are noted in Table II. The simulated result using Agilent’s Advanced Design System (ADS) 20001 of an active resonator circuit shows that it resonates at 1.9 GHz and has a negative resistance around 1.9 GHz. The real parts of input admittances for the active resonators are depicted in Fig. 11. Two active filters with these characteristic have been designed and their performances were simulated as shown in Fig. 12. These responses have similar behaviors over the frequency, except around the passband. The flatness at the passband could be poor and an active BPF might be unstable when an active resonator has a large negative resistance at any frequency range, as shown in Fig. 11. In Case I, we found that the flatness in the passband was 0.8 dB, and 1ADS,

Agilent Technol. Inc., Palo Alto, CA 2000.

Fig. 11. II).

Real parts of input admittance for the active resonators (Cases I and

Fig. 12. BPFs.

Comparison of simulation results around the passband for active

the return loss become bigger than 0 dB around the higher stopband, as shown in Fig. 12, which might lead to an unstable operation when it connects with other unmatched devices. A stability problem might be critical for the existence of a feedback circuitry. If the circuit is not absolutely stable over the entire frequency range, oscillation would cause a problem. The oscillation may cause gain degradation, increasing noise, and so on. In order to keep the circuit absolutely stable, we observed the stability factor ( factor). We can say a circuit is stable, in general, if the factor is larger than unity. We added a series resistor at the drain feedback circuit in order to enhance the stability, as well as the flatness at the passband. As shown in the simulated result of Fig. 13, the circuit would be unstable if the negative resistance of the FET exceeds the inductor loss. As the drain resistance , which reduces the negative resistance, goes to a higher value, the stability factor becomes more than unity, whereas the active filter has more loss. We have taken 20 of for a stable operation and low insertion loss. In this case, the noise figure was also considered, and it was durable for usage.

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Fig. 15. Comparison between the simulated and measured frequency responses (S ; S ). Fig. 13. Simulated result—stability factors with the variable with 5- steps).

Fig. 14.

R

. (10–25



Implemented two-pole active BPF.

The final design parameters are

Fig. 16.

Noise figure of the active BPF.

TABLE III COMPARATIVE DATA OF THE SIMULATED AND MEASURED PERFORMANCES

nH pF pF pF nH pF pF These values can vary with the layout of an active BPF and the characteristics of a substrate. The fabricated RF active filter is shown in Fig. 14. Fig. 15 also shows the simulated and measured frequency response with almost zero insertion loss at the center frequency of 1.9 GHz. Its 3-dB bandwidth is approximately 95 MHz. Fig. 16 shows the simulated and measured noise figure of the fabricated active BPF. The measured noise figure is approximately 2.4 dB at the center frequency. Table III shows the comparison data of the

measured and simulated active BPF performances. Finally, in Table IV, a comparison of other reported data of RF active filters and a reference passive filter data is given. The passive filter uses the same kind of elements—chip inductors and capacitors. As shown in Table IV, the proposed active filter has additive noise less than 0.2 dB. It shows that the quality factor of the passive resonator is most critical to decide the noise performance of this

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TABLE IV NOISE PERFORMANCES OF THE VARIOUS MICROWAVE ACTIVE FILTERS

type of active filter, and its noise figure is approximately equal to the insertion loss of the passive filter. VI. CONCLUSION We have presented a low-noise active BPF using a new type of active capacitor. The active capacitor could be made of an active device such as a BJT and high electron-mobility transistor (HEMT), and its equivalent circuit was derived. From theoretical analysis, we have found that the active capacitor provides a negative resistance to compensate for the loss introduced by inductor when used as a resonator. At the same time, it was also shown that low-noise performance could be obtained by adopting this topology and the theoretical analyses were discussed in detail. Compared with conventional design methods of the active filters, the proposed scheme is better in several areas such as less complexity, realizability of a narrow bandwidth, and better noise performance. We have verified the low-noise property of the proposed filter by analyzing and measuring it. REFERENCES [1] D. K. Adams and R. Y. C. Ho, “Active filters for UHF and microwave frequencies,” IEEE Trans. Microw. Theory Tech., vol. MTT-17, no. 9, pp. 662–670, Sep. 1969. [2] R. V. Snyder, Jr. and D. L. Bozarth, “Analysis and design of a microwave transistor active filter,” IEEE Trans. Microw. Theory Tech., vol. MTT-18, no. 1, pp. 2–9, Jan. 1970. [3] D. K. Adams and R. Y. C. Ho, “Filtering, frequency multiplexing, and other microwave applications with inverted-common-collector transistor circuits,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, 1969, pp. 14–20. [4] J.-R. Lee, Y.-H. Chun, and S.-W. Yun, “A novel bandpass filter using active capacitance,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, 2003, pp. 1747–1750. [5] C. Y. Chang and T. Itoh, “Microwave active filters based on coupled negative resistance method,” IEEE Trans. Microw. Theory Tech., vol. 38, no. 9, pp. 1879–1884, Sep. 1990. [6] S. R. Chandler, I. C. Hunter, and J. G. Gardiner, “Active varactor tunable bandpass filter,” IEEE Microw. Guided Wave Lett., vol. 3, no. 3, pp. 70–71, Mar. 1993. [7] K.-K. M. Cheng and H.-Y. Chan, “Noise performance of resistance compensated microwave bandpass filters—Theory and experiments,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 5, pp. 924–927, May 2001. [8] I. C. Hunter, S. R. Chandler, D. Young, and A. Kennerley, “Miniature microwave filters for communication systems,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 9, pp. 1751–1757, Sep. 1995. [9] L. Billonnet, B. Jarry, S. E. Sussman-Fort, E. Rius, G. Tann’e, C. Person, and S. Toutain, “Recent advances in microwave active filter design—Part 2: Tunable structures and frequency control techniques,” in Int. J. RF Microwave Computer-Aided Design, 2002, vol. 12, pp. 177–189. [10] C. T.-C. Nguyen, “Frequency-selective MEMS for miniaturized lowpower communication devices,” IEEE Trans. Microw. Theory Tech., vol. 8, pp. 1486–1503, Aug. 1999.

[11] L. P. B. Katehi, G. M. Rebeiz, and C. T.-C. Nguyen, “MEMS and Si-micromachined components for low-power, high-frequency communications systems,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, 1998, pp. 331–333. [12] H.-T. Kim, J.-H. Park, Y.-K. Kim, and Y. Kwon, “Millimeter-wave micromachined tunable filters,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, 1999, pp. 1235–1238. [13] K. M. Strohm, F. J. Schmuckle, O. Yaglioglu, J. F. Luy, and W. Heinrich, “3-D silicon micromachined RF resonator,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, 2003, pp. 1801–1804. [14] R. Aigner, J. Ella, H.-J. Timme, L. Elbrecht, W. Nessler, and S. Marksteiner, “Advancement of MEMS into RF-filter applications,” in Int. Electron Devices Meeting Dig., Dec. 2002, pp. 897–900. [15] W. Schwab and W. Menzel, “A low-noise active bandpass filter,” IEEE Microw. Guided Wave Lett., vol. 3, no. 1, pp. 1–2, Jan. 1993. [16] F. Sabouri-S, “A GaAs MMIC active filter with low noise and high gain,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, 1998, pp. 1177–1180. [17] Y.-H. Chun, S.-W. Yun, and J.-K. Rhee, “Active impedance inverter: Analysis and its application to the bandpass filter design,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, 2002, pp. 1911–1914. [18] C. Rauscher, “Microwave active filters based on transversal and recursive principles,” IEEE Trans. Microw. Theory Tech., vol. MTT-33, no. 12, pp. 1350–1360, Dec. 1985. [19] M. J. Schindler and Y. Tajima, “A novel MMIC active filter with lumped and transversal elements,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 12, pp. 2148–2153, Dec. 1989. [20] K. V. Chiang, K. W. Tam, W. W. Choi, and R. P. Martins, “Noise performance of CMOS transversal bandpass filters,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, 2002, pp. 871–874. [21] S. E. Sussman-Fort, L. Billonnet, and B. Jarry, “Microwave, biquadratic, active-RC filter development,” in Int. J. Microwave Millimeter-Wave Computer-Aided Eng., 1998, pp. 102–115. [22] H. Ezzedine, L. Billonnet, B. Jarry, and P. Guillon, “Optimization of noise performance for various topologies of planar microwave active filters using noise wave techniques,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2484–2492, Dec. 1998. [23] J. Everad, Fundamentals of RF Circuit Design with Low Noise Oscillators. New York: Wiley, 2001. [24] S. B. Cohn, “Direct-coupled-resonator filters,” Proc. IRE, vol. 45, no. 2, pp. 187–196, Feb. 1957.

Young-Hoon Chun (M’00) received the M.S. and Ph.D. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1995 and 2000, respectively. He then joined the research staff of the Millimeter-Wave Innovation Technology (MINT) Research Center, Dongguk University, Seoul, Korea, where he is currently a Research Professor. Since June 2004, he has been a Visiting Scholar with Heriot-Watt University, Edinburgh, U.K., for a one-year period. His research area includes microwave active filters, RF MEMS, passive and active millimeter-wave devices, and multifunctional integrated devices for RF front-ends.

CHUN et al.: DESIGN OF RF LOW-NOISE BANDPASS FILTER USING ACTIVE CAPACITANCE CIRCUIT

Jae-Ryong Lee (M’02) received the B.S. degree in physics, and the M.S. and Ph.D. degrees in electronic engineering from Sogang University, Seoul, Korea in 1991, 1996, and 2002, respectively. From 1996 to 1998, he was with the Samsung Electro-Mechanics Company, Kyounggi-Do, Korea. Since 2002, he has been with the Samsung Electronics Company, Kyounggi-Do, Korea. His principal research is RF circuit design and handy phone design of second generation (2G) and third generation (3G).

Sang-Won Yun (M’84) received the B.S. and M.S. degrees in electronic engineering from the Seoul National University, Seoul, Korea, in 1977 and 1979, respectively, and the Ph.D. degree from the University of Texas at Austin, in 1984. Since 1984, he has been a Professor with the Department of Electronic Engineering, Sogang University, Seoul, Korea. From January 1988 to December 1988, he was a Visiting Professor with the University of Texas at Austin. His research interests include microwave and millimeter-wave devices and circuits. Dr. Yun is currently a vice president of the Korea Electromagnetic Engineering Society (KEES). He is also a chairman of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Korea Chapter.

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Jin Koo Rhee (M’80) was born in Kimpo, Korea, on February 1, 1946. He received the B.S. degrees in electronics engineering from Hankuk Aviation University, Seoul, Korea, in 1969, and the M.S. and Ph.D. degrees in electrical engineering from Oregon State University, Corvallis, in 1979 and 1982, respectively. From 1982 to 1985, he was Senior Engineer with Cray Research Incorporated. In 1985, he was a Engineer with the Microwave Semiconductor Corporation. Since 1985, he has been with the Department of Electronic Engineering, Dongguk University, Seoul, Korea, where he is currently a Professor. From 1990 to 1991, he was with the University of Michigan as a Visiting Research Scientist. He is currently the Director of the Millimeter-Wave Innovation Technology Research Center, Dongguk University. His research interests include microwave and millimeterwave devices and circuits. Dr. Rhee has been president-elect of the Institute of Electronics Engineering of Korea (IEEK) since 2004.

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EO Probe for Simultaneous Electric and Magnetic Near-Field Measurements Using LiNbO3 With Inverted Domain Eiji Suzuki, Satoru Arakawa, Hiroyasu Ota, Member, IEEE, Ken Ichi Arai, Member, IEEE, Risaburo Sato, Life Member, IEEE, and Kiyoshi Nakamura, Member, IEEE

Abstract—This paper presents a new type of optical probe for simultaneous measurements of electric and magnetic near fields with high accuracy up to the gigahertz range. Its probe head consists of a loop antenna element that is doubly loaded with LiNbO3 electrooptic crystals. Using optical technology, it can work as a conventional double-loaded loop probe without metallic cables and electrical hybrid junction. We examined probe characteristics for electromagnetic field detection up to 20 GHz. We confirmed that the probe can measure electric and magnetic fields simultaneously with a high accuracy in the gigahertz range. Index Terms—Electromagnetic near field, electrooptic (EO) crystal, loop antenna, Pockels effect, probe.

I. INTRODUCTION

T

A few reports have addressed optical magnetic-field probes consisting of loop antenna elements and optical modulators [13], [14]. However, loop probes also encounter difficulties caused by metallic loop elements. The elements pick up electric fields, which induce undesired signals in magnetic-field detection. Double-loaded loop probes have been developed to suppress this influence electrically [15]–[19]. Electrical hybrid junctions of such probes suppress that influence and provide selective measurements of electric and magnetic fields (Appendix A), but their operation is frequency dependent and need metallic cables. To overcome the obstacles described above, we developed a new type of optical probe for simultaneous measurement of electric and magnetic near fields. The probe consists of a loop antenna element doubly loaded with LiNbO EO crystals [20]. One of the LiNbO has two domains where -axes (optical axes) in each domain are directly oppose each other. The crystal shows a higher frequency response than that of magnetooptical crystals. Using optical technology, the probe can work as a conventional double-loaded loop probe without metallic cables and electrical hybrid junctions. The optical hybrid operation of the probe provides simultaneous measurements of electric and magnetic fields and solves problems inherent in conventional double-loaded loop probes. The probe, using no metallic cables or balun, allows measurement of electromagnetic fields with little invasive impact to the surroundings. Furthermore, the detected signal can be transmitted with no disturbance from noise that is picked up by metallic cables. These features state that the probe is suitable for simultaneous measurements of electric and magnetic near fields with high accuracy in the gigahertz range.

HIS PAPER describes a new type of optical probe for simultaneous measurements of electric and magnetic near fields in the gigahertz range. Measurements of electromagnetic fields near a radiation source are important from the standpoint of electromagnetic compatibility for electronic equipment. However, the electromagnetic near fields show a complicated structure, whereas far . fields are simply characterized by wave impedance Therefore, near-field analysis requires simultaneous measurements of electric and magnetic fields. Loop and dipole antenna sensors are fundamental tools for magnetic- and electric-field detection, respectively [1]. Nevertheless, these probes encounter difficulties caused by the metallic cables used for signal transmission. Such cables pick up surrounding electric fields, and thereby disturb probe outputs and electromagnetic fields to be measured [2]. Electric-field sensors with optical signal transmission have been developed to overcome the difficulties concomitant with metallic cable use. Bulk electrooptic (EO) modulators [3]–[9] or optical waveguide modulators [10]–[12] are used as transducers with dipole antenna elements.

A. Probe Head and System Configuration

Manuscript received February 24, 2004; revised May 10, 2004. E. Suzuki, S. Arakawa, H. Ota, and R. Sato are with the Sendai Electromagnetic Compatibility Research Center, National Institute of Information and Communications Technology, Sendai 989-3204, Japan (e-mail: [email protected]; [email protected]; [email protected]). K. I. Arai is with the Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan. K. Nakamura is with the Graduate School of Engineering, Tohoku University, Sendai 980-8577, Japan. Digital Object Identifier 10.1109/TMTT.2004.840575

Fig. 1 shows the probe head of the EO electric- and magnetic-field probe. It comprises a metallic loop element and two LiNbO EO crystals. Fig. 2 shows their dimensions. LiNbO is a ferroelectric uniaxial crystal that polarizes along the -axis (optical axis) of its crystal lattice. One of the LiNbO has two domains where -axes in each domain are directly oppose each other [21]. Heat treatment raises domain boundary to the median plane of the crystal. The probe head, with no metallic cables or balun, provides a means to measure electromagnetic fields with little invasive

II. EO ELECTRIC- AND MAGNETIC-FIELD PROBE

0018-9480/$20.00 © 2005 IEEE

SUZUKI et al.: EO PROBE FOR SIMULTANEOUS ELECTRIC AND MAGNETIC NEAR-FIELD MEASUREMENTS

Fig. 4. Induced voltages and the arrangements of

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+c-directions.

B. Principle of Optical Hybrid Operation Fig. 1. Probe head.

Fig. 2.

We describe our optical hybrid operation for simultaneous measurements of magnetic and electric fields: it consists of optical separation of magnetic- and electric-field signals. The operation is based on optical intensity modulation using the Pockels effect (Appendix B). The case we consider is that of a magnetic penetrating perpendicularly to the loop element where field a uniform electric field is present on the loop plane (Fig. 4). is cancelled at the LiNbO because of Voltage induced by structural symmetry of the probe. Thereby, induces . First, we explain optical modulation of the beam for magnetic induced by field detection ( -beam) in Fig. 4. Voltages are applied along the plus direction of the -axis at both LiNbO . caused by is given From (10), the total phase difference as

Probe dimensions.

(1) induced by is applied along the On the other hand, voltage plus direction of the -axis at the right LiNbO while is applied along the minus direction of the -axis at the left LiNbO . caused by is canThereby, the total phase difference celled as follows: (2)

Fig. 3. Probe system.

impact to the surrounding fields that is to be measured. Furthermore, the detected signals can be transmitted without any disturbance resulting from noise picked up by metallic cables. Fig. 3 shows the probe system. Two continuous-wave laser beams guided through optical fibers pass through optical circulators and collimator lenses. The beams enter the LiNbO with a single domain and LiNbO with an inverted domain in the probe head. The beams are reflected at one side of the latter LiNbO , then pass through the circulators, waveplates, and polarizers to photoreceivers. Spectrum analyzers process the resultant electrical signals.

That is, only gives modulation to the -beam passing through the probe head. The other beam ( -beam) provides electric-field detection because the same-direction arrangement of -axes for the -beam yields a phase difference for while it cancels that like (1) and (2). for Through the process explained above, the probe head optically provides hybrid operation of a conventional double-loaded loop probe and simultaneous measurements of magnetic and electric fields. It requires no metallic cables or electrical hybrid junction. After the beam leaves the head, it is modulated to an appropriate intensity by the optical intensity modulation. III. EXPERIMENTAL RESULTS A. Calibration Using TEM Cell We evaluated antenna factors (AFs) using a TEM cell (ETC-50; Elena Electronics Company Ltd., Tokyo, Japan) up

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TABLE I AF AND MINIMUM DETECTABLE FIELD STRENGTH

Fig. 6. Frequency responses above the MSL.

Fig. 5.

Experimental setting and electromagnetic field above the MSL.

to 3 GHz. AFs for magnetic field defined as

and electric field

are Fig. 7. Linearity of magnetic-field response.

(3) and (4) Magnetic- and electric-field strength dB

A m

and dB

are given by V

(5)

The loop element was set either parallel or orthogonal to the line. Under the parallel setting (0 ), the loop element received the maximum amount of magnetic flux. Under the orthogonal setting (90 ), the loop element received the minimum amount of magnetic flux. Distance between the MSL and the bottom of the loop element was 0.5 mm. C. Frequency Response

and dB

V m

dB

V

(6)

The TEM cell was powered at 20 dBm at 1 and 3 GHz. The probe received a magnetic field of 107.5 dB A/m and an electric field of 159.0 dB V/m. We set the resolution bandwidth of the spectrum analyzer to 30 Hz throughout the experiments. The noise floor of our probe system was 120 dm, as determined by the spectrum analyzer. Table I shows AFs and minimum detectable field strength (noise equivalent field strength) for the magnetic and electric fields at 1 and 3 GHz. B. Experimental Conditions Using a Microstrip Line (MSL) Fig. 5 shows the experimental setup using an MSL as an electromagnetic-field source. The MSL had a 1.0-mm-wide line with a 100 245 mm periphery; it was matched to 50 .

We examined probe frequency responses. The MSL was powered at 10 dBm over the frequency range of 0.1–20 GHz. The probe head was set above the center of the line under the 0 setting. Fig. 6 shows experimental results. The plots and show responses to the magnetic and electric fields, respectively. The resonance at 15.2 GHz is mainly caused by the self-inductance of the loop and capacitance with LiNbO . D. Linearity We examined the probe linear responses. The input power to the MSL ranges from 20 to 18 dBm. The probe head was set above the center of the line under the 0 setting. Figs. 7 and 8 show experimental results of linear responses to magnetic and electric fields, respectively. Linear responses under the condition were observed. Different outputs at every frequency reflect the frequency characteristics shown in Fig. 6.

SUZUKI et al.: EO PROBE FOR SIMULTANEOUS ELECTRIC AND MAGNETIC NEAR-FIELD MEASUREMENTS

Fig. 8. Linearity of electric-field response.

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Fig. 11. Conventional double-loaded loop probe. (a) External field and load currents. (b) Probe construction.

hand, the 0 and 90 results of Fig. 10 demonstrate that the probe can measure the electric-field distribution near the MSL. IV. CONCLUSION

Fig. 9.

Horizontal component of magnetic field above the MSL at 3 GHz.

We have demonstrated that our EO probe can detect electric and magnetic fields simultaneously near the MSL up to the gigahertz range. Using optical technology, it can work as a conventional double-loaded loop probe without metallic cables and electrical hybrid junction. The probe shows linear responses to power input to the MSL from 20 to 18 dBm up to 10 GHz. The minimum detectable field strengths are 87.6 dB A/m for magnetic field and 125.8 dB V/m for the electric field at 3 GHz. Those facts state that the probe is suitable for simultaneous measurements of electric and magnetic fields with high accuracy in the gigahertz range. APPENDIX A We explain electrical hybrid operation of a conventional double-loaded loop probe for the case shown in Fig. 11. The case we consider is that of a magnetic field penetrating perpendicularly to the loop element where a uniform electric field is present on the loop plane. and induce electric curand , respectively. A voltage induced by is canrents celled at the loads because of structural symmetry of the probe. induces . Resultant total currents at the left and Thereby, right loads and are given as (7)

Fig. 10.

Vertical component of electric field above the MSL at 3 GHz.

and

E. Electromagnetic-Field Distribution Above the MSL We measured magnetic- and electric-field distribution above the MSL powered at 10 dBm at 3 GHz by scanning the probe horizontally at a right angle to the line under 0 and 90 settings. Figs. 9 and 10 show experimental results. The horizontal axes show the probe head position from the line. The vertical axes show magnetic- and electric-field strength evaluated with the AFs. The 0 results of Fig. 9 demonstrate that the probe can measure the magnetic-field distribution near the MSL. In contrast, 90 outputs are not desirable for magnetic-field probes because the outputs are mainly induced by the electric field. On the other

(8) Therefore, the signal for

can be obtained by (9)

Fig. 11 shows the actual probe construction. Signals obtained at the two loads are transmitted through metallic cables to the according to (9). electrical hybrid junction that provides Hence, precision of magnetic-field detection is reliant upon the hybrid junction performance. Structural symmetry of the probe . is also essential to cancel the voltage induced by

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The photoreceiver changes the optical intensity to the corresponding intensity of electrical signal. The signal voltage is given as (13) where ( A/W) and are the conversion efficiency and output impedance of the photoreceiver, respectively.

REFERENCES

Fig. 12.

Optical intensity modulation.

APPENDIX B Probe operation is based on optical intensity modulation using the Pockels effect [22] (Fig. 12). A laser beam passes through an LiNbO , waveplates, and a polarizer for the modulation. -cut surfaces to apply an Electrodes are formed on the for induced voltage along the -axis. The refractive index the -polarized beam is 2.2; , for the -polarized beam, is 2.3. LiNbO shows the Pockels effect (the linear EO effect) that changes the refractive indices in proportion to an applied voltage. When a linearly polarized beam enters the LiNbO at a polarization angle of 45 to the -axis, the different refractive indices , the phase difference of the - and of the - and -axes cause - polarized beam. When a voltage is applied to the LiNbO along the -axis, is given as (10) is a constant of the natural birefringence independent where is given as of and half-wave voltage (11) ( m/V) and ( m/V) where are the EO constants of LiNbO . and are the LiNbO thickness along the -axis and length along the beam propagation, m). respectively. The laser beam wavelength is ( produces an elliptically polarized beam. The waveplates to obtain the highest sensitivity. Subsequently, compensate the polarizer set at 45 to the -axis produces a linearly polarmodulated by ized beam. Its resultant optical intensity is given as (12) where is the optical insertion loss from a laser source ( mW) is the laser source to a photoreceiver and power.

[1] M. Kanda, “Standard probes for electromagnetic field measurements,” IEEE Trans. Antennas Propag., vol. 41, no. 10, pp. 1349–1364, Oct. 1993. [2] S. Arakawa, E. Suzuki, H. Ota, K. I. Arai, and R. Sato, “Invasiveness of optical magnetic filed probes with a loop antenna element,” in Proc. EMC’04, Sendai, Japan, 2004, pp. 149–152. [3] H. Bassen and R. Peterson, “Complete measurement of electromagnetic fields with electro-optical crystals,” in USNC/URSI Annu. Biological Effects Electromagnetic Waves Meeting, vol. 77, 1975, pp. 310–323. [4] J. Wyss and S. Sheeran, “A practical optical modulator and link for antennas,” J. Lightw. Technol., vol. LT-3, no. 2, pp. 316–321, Apr. 1985. [5] K. D. Masterson and L. D. Driver, “Broadband, isotropic, photonic electric-field meter for measurements from 10 kHz to above 1 GHz,” in Proc. SPIE High Bandwidth Analog Applications of Photonics II, vol. 987, 1988, pp. 107–118. [6] K. D. Masterson, L. D. Driver, and M. Kanda, “Photonic probes for the measurement of electromagnetic fields over broad bandwidths,” in IEEE Nat. Electromagnetic Compatibility Symp., Denver, CO, 1989, pp. 1–6. [7] N. Kuwabara, S. Kuramoto, M. Sata, and M. Tokuda, “A wide band antenna using electro-optical crystals,” IEICE , Tokyo, Japan, Tech. Rep. EMCJ 88–90, 1989. [8] M. Kanda and K. D. Masterson, “Optically sensed EM-field probes for pulsed fields,” Proc. IEEE, vol. 80, no. 1, pp. 209–215, Jan. 1992. [9] R. Kobayashi, K. Tajima, N. Kuwabara, and M. Tokuda, “Theoretical analysis of the sensitivity on electric field sensor using LiNbO optical modulator,” in Trans. Inst. Electron. Inf. Commun. Eng., vol. J79-B-II, Nov. 1996, pp. 734–743. [10] K. Nishikawa and S. Furuichi, “Optical electric field sensor for EMC,” in Sensor Symp. Tech. Dig., 1995, pp. 105–108. [11] Y. Tokano, H. Kobayashi, T. Miyakawa, and Y. Houjyo, “A gigahertzrange micro optical electric field sensor,” in Proc. Electromagnetic Compatibility, Zurich, Switzerland, 2001, pp. 127–130. [12] K. Tajima, R. Kobayashi, N. Kuwabara, and M. Tokuda, “Development of optical isotropic E -field sensor operating more than 10 GHz Mach–Zehnder interferometers,” IEICE Trans. Electron, vol. E85-C, no. 4, pp. 961–968, Apr. 2002. [13] T. Miyakawa, K. Nishikawa, K. I. Arai, and R. Sato, “An optical waveguide sensor with a loop antenna element,” in EMC Eur. Int. Electromagnetic Compatibility Symp., 2002, pp. 635–638. [14] E. Suzuki, T. Miyakawa, H. Ota, K. I. Arai, and R. Sato, “Characteristics of an optical magnetic probe consisting of a loop antenna element and a bulk electro-optic crystal,” in Proc. Electromagnetic Compatibility, Zurich, Switzerland, 2003, pp. 61–64. [15] H. Whiteside and R. W. P. King, “The loop antenna as a probe,” IEEE Trans. Antennas Propag., vol. AP-12, no. 5, pp. 291–297, May 1964. [16] J. Dyson, “Measurement of near fields of antennas and scatterers,” IEEE Trans. Antennas Propag., vol. AP-21, no. 4, pp. 446–459, Jul. 1973. [17] M. Kanda, “An electromagnetic near-field sensor for simultaneous electric- and magnetic-field measurements,” IEEE Trans. Electromagn. Compat., vol. EMC-26, no. 3, pp. 102–110, Aug. 1984. [18] L. D. Driver and M. Kanda, “An optically linked electric and magnetic field sensor for Poynting vector measurements in the near fields of radiating sources,” IEEE Trans. Electromagn. Compat., vol. 30, no. 4, pp. 495–503, Nov. 1988. [19] F. Gassmann and M. Mailand, “A 9 channel photonic isotropic electric and magnetic field sensor with subnanosecond rise time,” in Proc. Electromagnetic Compatibility, Zurich, Switzerland, 1997, pp. 217–221. [20] E. Suzuki, T. Miyakawa, H. Ota, K. I. Arai, and R. Sato, “Optical magnetic field sensing with a loop antenna element doubly-loaded with electro-optic crystals,” in Proc. IEEE Electromagnetic Compatibility Symp., 2003, pp. 442–447.

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[21] K. Nakamura, H. Ando, and H. Shimizu, “Ferroelectric domain inversion caused in LiNbO plates by heat treatment,” Appl. Phys. Lett, vol. 50, no. 20, pp. 1413–1414, May 1987. [22] M. Bass, Ed., Handbook of Optics. New York: McGraw-Hill, 1994, ch. 13.

Eiji Suzuki was born in Yokohama, Japan, in 1971. He received the B.S. degree in physics from Rikkyo University, Tokyo, Japan, in 1994, and the M.S. degree in physics from Waseda University, Tokyo, Japan, in 1996. From 1997 to 2001, he was a Design Engineer of electronic devices with the TDK Corporation. Since 2001, he has been with the Sendai Electromagnetic Compatibility (EMC) Research Center, National Institute of Information and Communications Technology, Sendai, Japan, where he is currently involved with electromagnetic-field sensors. His main interest is the application of optical technology to electromagnetic-field measurements. Mr. Suzuki is a member of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan, and the Magnetic Society of Japan.

Satoru Arakawa was born in Fukushima Prefecture, Japan, in 1973. He received the B.E. and M.E. degrees from Niigata University, Niigata, Japan, in 1996, and 1998, respectively. From 1998 to 2001, he was a Development Engineer of electronic measuring instruments with the Anritsu Corporation, Kanagawa, Japan. Since 2001, he has been with the Sendai Electromagnetic Compatibility (EMC) Research Center, National Institute of Information and Communications Technology, Sendai, Japan, where he is currently involved with electromagnetic-field sensors. His main interest is the application of optical technology to electromagnetic-field measurements. Mr. Arakawa is a member of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan, and the Magnetic Society of Japan.

Hiroyasu Ota (M’03) was born in Aomori, Japan, in 1951. He received the B.E. and M.E. degrees from Tohoku University, Sendai Japan, in 1975 and 1977, respectively. He then joined the Sony Corporation, where he was engaged in switched-mode power supplies design. From 1996 to 2000, he was a Senior Researcher with Electromagnetic Compatibility (EMC) Research Laboratories Company Ltd., Sendai, Japan. Since 2000, he has been a Chief Research Engineer with the Sendai EMC Research Center, National Institute of Information and Communications Technology, Sendai, Japan. His research interests focus on the design of electromagnetic-wave absorbers and EMC measurement.

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Ken Ichi Arai (M’85) was born in Nagano, Japan, in 1943. He received the B.E., M.E., and D.E. degrees from Tohoku University, Sendai, Japan, in 1966, 1968, and 1971, respectively. From 1971 to 1975, he was an Assistant Professor with the Research Institute of Electrical Communication, Tohoku University. From 1975 to 1986, he was an Associate Professor, and since 1986, he has been a Professor with the Research Institute of Electrical Communication, Tohoku University. His current interests include magnetic materials, micromagnetic devices, and EMC. Dr. Arai is currently the president of the Magnetic Society of Japan.

Risaburo Sato (SM’62–F’77–LM’92) was born in Miyagi, Japan, in 1921. He received the B.E. and Ph.D. degrees from Tohoku University, Sendai, Japan, in 1944 and 1952, respectively. From 1949 to 1961, he was an Associate Professor with Tohoku University. In 1961, he became a Professor with the Department of Electrical Communication, Tohoku University. From 1973 to 1984, he was a Professor with the Department of Information Science, Tohoku University. He is currently an Emeritus Professor of Tohoku University and Tohoku Gakuin University. From 1969 to 1970, he was an International Research Fellow with the Stanford Research Institute, Menlo Park, CA. His research activities include studies of multiconductor transmission systems, distributed transmission circuits, antennas, and electromagnetic compatibility (EMC). He has authored or coauthored numerous technical papers and books in these fields. Dr. Sato is a chair of the IEEE EMC Society Sendai Chapter and a member of the IEEE EMC Society Standard Developing Committee. He was the recipient of a 1981 Certificate of Appreciation of the IEEE EMC Society, the 1982 Microwave Prize of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S), the 1984 IEEE Centennial Medal, and the 1987 Laurence G. Cumming Awards and 2002 Richard R. Stoddard Award presented by the IEEE EMC Society.

Kiyoshi Nakamura (M’77) was born in Nagano Prefecture, Japan, on April 22, 1942. He received the B.S., M.S., and Ph.D. degrees in electrical communication engineering from Tohoku University, Sendai, Japan, in 1966, 1968, and 1975, respectively. From 1968 to 1976 he was a Research Associate with the Department of Electrical Communications, Tohoku University, and in 1976, he became an Associate Professor. He is currently a Professor with the Graduate School of Engineering, Tohoku University. He has authored over 140 technical papers. He holds ten patents. His research covers a wide range of interests in ferroelectric and piezoelectric materials, and their applications to ultrasonic transducers, surface acoustic-wave (SAW) devices, and bulk acoustic-wave thin-film devices. In 1977, he discovered the SH-type surface acoustic wave on the 36 – LiTaO cut, which is now extensively used for SAW devices in cellular phones. He also discovered domain inversion phenomena induced by heat treatment of LiNbO or proton-exchanged LiTaO . Professor Nakamura has served as the Japan Chapter chair of the IEEE Ultrasonics, Ferroelectrics, and Frequency (UFFC) Society (1999–2000) and as the president of the Engineering Sciences Society of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan (2000). He currently serves as an Administrative Committee (AdCom) member of the IEEE UFFC Society. He is a Fellow of the IEICE, Japan. He was the recipient of the 1979 Best Paper Award presented by the IEICE, Japan.

Y X

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Extremely High-Q Factor Dielectric Resonators for Millimeter-Wave Applications Jerzy Krupka, Senior Member, IEEE, Michael E. Tobar, Senior Member, IEEE, John G. Hartnett, Dominique Cros, and Jean-Michel Le Floch

Abstract—It has been proven, based on a rigorous electromagnetic analysis, that spherical TE10 -mode Bragg-reflection resonators exhibit many times higher factors than corresponding cylindrical TE01 -mode dielectric resonators, dielectric whispering-gallery-mode resonators, or empty spherical TE10 -mode cavities. Rigorous equations have been derived that allow optimally designed -factor and “quarter-wavelength” reflector-multilayered-spherical Bragg-reflection resonators. Experiments have been performed on three-layer spherical resonators made of single-crystal YAG and single-crystal quartz. The unloaded factor for the TE012 mode in these resonators was 1.04 105 at 26.26 GHz for YAG and 6.4 104 at 27.63 GHz for quartz. Index Terms—Bragg scattering, dielectric materials, dielectric resonators, millimeter-wave technology. Fig. 1. Schematic diagram of a dielectric resonator(s) partially shielded by metal enclosure.

I. INTRODUCTION

D

IELECTRIC resonators are one of the most frequently used microwave devices. The most important paramfactor; and eters are: 1) permittivity; 2) dimensions; 3) 4) temperature coefficient of the resonance frequency. Dielectric resonators are usually made of different kinds of ceramics. In the recently accessed Web page “List of microwave dielectric resonator materials and their properties,” there are over 400 different ceramic compounds listed. Unfortunately for the vast majority of those materials and also for single crystals [1], the dielectric loss tangent decreases with frequency (manufacturers GHz product as a constant value) specify so, at millimeter-wave frequencies, available factors are not very large and sometimes not sufficient for more advanced applications. Exceptions to this rule are some low-loss plastics like PTFE, polyethylene, polyprophylene, and single-crystal quartz for which losses are almost constant with frequency. Let us consider in detail the theoretical -factor limits of a dielectric resonator. The unloaded factor of a dielectric resonator schematically depicted in Fig. 1, for any mode of operation, is determined either by the dielectric and radiation losses, in an open structure (without any shield), or by the dielectric and conductor losses for a completely shielded resonator. For Manuscript received March 6, 2004. This work was supported in part by the Australian Research Council. J. Krupka is with the Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, 00-662 Warsaw, Poland. M. E. Tobar and J. G. Hartnett are with the School of Physics, University of Western Australia, Perth 6009 W.A., Australia. D. Cros and J.-M. Le Floch are with the Institute in Optical and Microwave Communications, U.R.A. Centre National de la Recherche Scientifique 356, Faculte des Sciences, Universite de Limoges, 87060 Limoges, France. Digital Object Identifier 10.1109/TMTT.2004.840572

the general structure shown in Fig. 1, the unloaded factor can be expressed by well-known formulas (1)–(3) as follows:

(1) is the unloaded factor of the whole resonant where structure, is the surface resistance of the metal enclosure, is the geometric factor of the metal enclosure, and is the electric energy filling factor of a specific dielectric region. and electric energy filling factors are Geometric factor defined as follows:

(2)

(3)

where is the volume of the th dielectric region, is the volume of the whole resonant structure, is the spatial dependent permittivity inside the whole resonant structure, is the permittivity of the th dielectric region. The and contributions of each of these three loss components (dielectric losses, conductor losses, radiation losses) to the overall factor depend on the parameters of the structure (the dimensions, electromagnetic properties of the dielectrics, and metal) and the mode of operation. The most frequently used cylindrical

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Fig. 2. Cylindrical dielectric resonator in metal enclosure.

Fig. 4. (a) Q factor versus size of metal enclosure d=h = 2:0; D =d = L =h; " = 4:44; R = 47:4 m (silver at 25 GHz). (b) Electric energy filling factor.

Fig. 3. Geometric factor versus size of metal enclosure for D =d (a) d=h = 2:0. (b) d=h = 2:0. d=h = 1:0.

= L =h.

dielectric resonators operate on the mode. They have to be enclosed in a metal shield to avoid tremendous radiation -mode resonator losses (the factor due to radiation for a situated in a free space is approximately 50 if its permittivity is

equal to 38[2]). For shielded -mode dielectric resonators, conductor losses depend on the distance from the dielectric to the metal walls. To minimize metal wall losses, one has to situate the resonator away from all metal walls and optimize the size of the metal enclosure. Let us consider the resonant structure shown in Fig. 2. It has already been shown in earlier papers, e.g., [3] and [4], that for a given permittivity and dimensions of a dielectric resonator, an optimum size of the metal enclosure exists for which the wall losses are minimized. Fig. 3 shows the results of computations of the geometric factor -mode dielectric resonators for a few commercially for the available low-loss dielectric materials. The dielectric properties of these materials are listed in Appendix I (see the table therein). The computations have been performed employing a rigorous Rayleigh–Ritz technique [3]. From the results shown in Fig. 3, one can conclude that the higher the permittivity of the

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COMPUTED

Q FACTOR OF TE

TABLE I -MODE DIELECTRIC RESONATORS IN OPTIMUM SIZED SILVER ENCLOSURES

dielectric material, the larger the geometric factor. Thus, from this point-of-view, high-permittivity material is preferable. On factor also depends on dielectric the other hand, the total losses. Fig. 4(a) shows the results of computations of the total unloaded factor versus the size of metal enclosure for material having the same permittivity as a single-crystal quartz, but with different dielectric losses. It is seen that, for large , -factor values converge to the metal enclosures -factor value for an empty cavity. It is easy to explain because the electric energy filling factors in such cases converge to zero and the dielectric losses become negligible. For enclosures factor is always the equal to the size of the dielectric, the smallest because the geometric factor converges to its minimum value, which is equal to the geometric factor for an empty cavity divided by the square root of permittivity. The dielectric losses also approach a maximum at that point because the electric energy filling factor is equal to unity. If the dielectric , then the whole resonant material exhibits low loss structure would have a factor larger than that for an empty factor would also exhibit a local maximum at cavity, The a certain optimum size of metal enclosure. For a single-crystal quartz sample having dielectric losses and , the optimum size of metal enclosure is with , as shown in Fig. 4(a). In Table I, we show the results of computations of the total factor of shielded -mode dielectric resonators with optimum-sized metal enclosures (the size at which the total factor approaches a maximum) evaluated at different frequencies for the materials listed in Appendix I (see the table therein). To further minimize the conductor losses, one can utilize the so-called whispering-gallery modes (WGMs) that are higher order hybrid modes that can be excited in cylindrical or spherical dielectric specimens [5]–[8]. By proper choice of the elevation-angle-mode index for open WGM dielectric resonators, the radiation losses can be made negligible. For shielded WGM dielectric resonators, the geometric factor can be made arbitrarily large by proper choice of the mode index and dimensions of metal enclosure. It has been already proven for spherical and cylindrical WGM resonators [5], [6]. For well-designed WGM resonators, factor predominantly depends on the dielectric the overall losses, even if extremely small. In fact, WGM resonators have been constructed and measured that exhibit factor larger then 10 at 4.2 K and 10 GHz [4]. Since the electric energy filling factor for a WGM resonator is very close to unity, its overall factor can thus be estimated as the inverse of the dielectric loss tangent.

Fig. 5. Schematic diagram of multilayered spherical dielectric resonator.

II. BRAGG-REFLECTION DIELECTRIC RESONATORS As has been shown in Section I for the commonly used mode and for WGM dielectric resonators, it is impossible to obtain a factor above the dielectric property limit. However, if a complex multidielectric structure is built, where a substantial part of the electric energy is stored in the air, it is , the possible to obtain resonators with factors larger than dielectric factor, and larger than the factor of an empty metal cavity operating in the same mode. Such resonators employ a so-called Bragg-reflection effect, which is known in resonators operating at optical frequencies, but it has also been utilized in air-confined resonators operating at microwave frequencies [9]–[11] (see also [12]–[15] for dielectric-confined Bragg-reflection resonators). One of the simplest structures of Bragg-reflection air-confined resonators is a spherical multilayered resonator [16] schematically depicted in Fig. 5. For this structure, exact expressions for electromagnetic fields exist. They can be found in several textbooks and papers [17], [18] on electromagnetism. Such expressions, usually given for less complicated structures, can be extended for a multilayered structure, shown in Fig. 5, for an arbitrary number of dielectric layers. modes of this As an example, let us consider the structure only. In the th dielectric layer, the two orthogonal components of the electric and magnetic fields can be written as follows:

(4)

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(5) and and are where Bessel functions of the first and second kinds of the order of is the elevation angle mode index, and is the azimuthal because angle mode index. For the first dielectric layer, Bessel functions of the second kind are infinite at . is made Let us assume that the last surface of a perfect electric conductor. The requirements that, at , both tangential components of the every surface, electric and magnetic fields must be continuous and, that , the tangential component of the electric field at must vanish together, which leads to the following system of linear equations with respect to the unknown coeffiand for modes: cients

(6)

Fig. 6. Three-layer spherical Bragg-reflection resonator.

(10) The resulting system of linear equation can be expressed as follows: (11) and as the equation shown at the bottom of this page. For a and the matrix has the three-layer resonator, following structure:

(12)

(7) For

to

,

For larger , the matrix becomes sparse and banded with nonzero elements on five central diagonals only. The system of linear equations (11) has nonzero solutions vanishes. Hence, when the determinant of the matrix the resonance frequencies for all modes can be found as the solutions of a nonlinear equation as follows: (13)

(8)

(9)

The resonance frequencies do not depend on the azimuthal mode index and they are -fold degenerated with . The elevation angle mode index is explicitly given and the radial mode index denotes the number of subsequent roots of (14). When a resonance frequency is found, then the associated eigenvector can be determined (it cannot be uniquely determined, thus, we have ). When the eigenvector assumed, for simplicity, that is known, all the electromagnetic-field components can be mode. For modes, one evaluated for a specific can determine the geometric factors and the electric energy filling factors either directly from their definitions (2) and (3) or alternatively from incremental frequency rules [19], [20].

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TABLE II

COMPUTED RESONANCE FREQUENCIES AND

Q FACTORS OF TE

-MODE RESONATORS OPERATING AT 25 GHz

For the electric energy filling factors, incremental frequency rules are as follows: (14) with

while the geometric factor can be evaluated as (15) Knowing the electric energy filling factors and the geometric factors for materials, one can evaluate the unloaded factor of the resonator from (16) (16)

III. EXAMPLES OF COMPUTATIONS FOR SPHERICAL BRAGG RESONATORS Consider the mode of a three-layer dielectric resonator, as shown in Fig. 6. For the mode in such a resonator, it is possible to obtain the Bragg-reflection effect factor higher than for an [16] that achieves a resonator empty spherical cavity and much higher then the inverse of the dielectric loss tangent of the dielectric medium. This can be accomplished when the radius is equal to a half-wavelength and the subsequent layers are a “quarter-wavelength” thick. A rigorous design procedure of a “quarter-wavelength” spherical Bragg resonators is presented in Appendix II. The results mode factors and related of computations of the coefficients for three-layered Bragg resonators designed as “quarter-wavelength Bragg reflectors” are shown in Table II. In the theory presented here, we have assumed that dielectric spheres are made of isotropic materials. This theory also remains valid for spheres made of an uniaxially anisotropic material if they have been oriented such that their anisotropy axes are parallel to the -axis of the spherical coordinate system. In such a case, the electric field of modes is, in theory, perpendicular to the anisotropy axis and then the uniaxial anisotropy is not “visible” to the electric field.

Fig. 7. Electric field distribution for: (a) an empty spherical TE mode resonator and (b) an optimized spherical TE -mode dielectric resonator containing a hollow sphere of YAG " = " = 10:6.

To satisfy such requirements in practice, excitation probes or loops have to be situated in the equatorial plane of a spherical resonator, while the crystal anisotropy axis is situated perpendicular to this plane. The electric-field distribution for -mode resonator made of YAG is shown in a Bragg

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Fig. 8.

FACTOR DIELECTRIC RESONATORS FOR MILLIMETER-WAVE APPLICATIONS

Q factor of spherical Bragg-reflection dielectric resonators versus frequency. (a) TE

Fig. 7. For comparison, the electric field for an empty spher-mode resonator is presented. It is clearly visible in ical the electric-field plots that the amount of the electromagnetic in the Bragg resonator is much energy in region 3 smaller than for the empty cavity. As a consequence of such a field distribution, the geometric factor for the Bragg resonator is a few times larger than for the corresponding empty cavity, and this is shown in Table II. It may be noticed in Table II that the geometric factor value increases with increasing values of the real permittivity of the Bragg reflector. The real permittivity increases down the column from No. 1–5. Bragg resonators designed with “quarter-wavelength” layers exhibit high- factors, which are close, but not exactly the same as the maximum available -factor value. Optimization of three-layer Bragg resonators can be performed with respect to variables and , which factor. We allows one to obtain the maximum possible performed such an optimization, and the results for the YAG resonator are shown in Table II, row 4. One can observe that the optimum factor is only 1% higher than the factor of the “quarter-wavelength” layered resonator. The thickness of the dielectric layer of the optimized resonator is approximately 2% smaller than the “quarter-wavelength” and, as a consequence, its electric energy filling factor in region 2 and, hence, the dielectric losses, are approximately 5% smaller then for the “quarter-wavelength” layered resonator. On the other hand, the geometric factor of the optimized resonator is reduced and the conductor losses are higher but only approximately 2% compared to its “quarter-wavelength” layered counterpart. To increase further the geometric factors for Bragg resonators made of a low-permittivity material, one can implement an additional “quarter-wavelength” dielectric reflector situated at the position of metal enclosure and extend the size of metal enclosure for another “quarter-wavelength” outside of the dielectric. When a larger number of Bragg reflectors is mode with implemented, the resonator operates on a . The results of computations of the factor versus -mode frequency for spherical three- and five-layered Bragg resonators are presented in Fig. 8. The electric-field

mode (three layers). (b) TE

707

mode (five layers).

distributions for five-layered resonators are shown in Fig. 9. One can notice that implementation of a larger number hollow dielectric spheres is especially advantageous if they are made of a low-permittivity material. The drawback of such a solution is that the number of unwanted modes in the vicinity of the mode of interest increases with increasing the radial mode number. For five-layered Bragg resonators made of medium permitfactor predominantly depends on the tivity material, the product of dielectric loss tangent and the sum of the electric energy filling factors in dielectric reflectors. Further improvement factor of five-layered Bragg resonators is possible of the by increasing the radius of the first region. An appropriate must be equal to a multiple of “half radius of this region of wavelengths.” An example of the electric-field distribution and the results of the -factor computations of a five-layered -mode Bragg resonator are shown in Fig. 10. One can see that the factor of such a resonator operating at 25 GHz is approximately 60% larger than the factor of the five-layered -mode Bragg resonator. Its factor due to conductor losses is approximately 3.9 million (at 25 GHz). One mode can anticipate that by employing a higher order with a sufficiently large radial mode index in a five-layered Bragg resonator made of YAG, it will be possible to achieve factors of the order of 3 million at 25 GHz. For a sufficiently can be large radial mode index , asymptotic values of approximated by (17) [as is seen in Fig. 11(a)] (17) IV. TEMPERATURE STABILITY OF SPHERICAL BRAGG-REFLECTION RESONATORS In practice, it is important to construct temperature-stable resonators [12]–[14]. The temperature coefficient of the resonance frequency for the three-layered resonator, shown in Fig. 8, depends on the temperature coefficient of permittivity and the thermal expansion coefficients of the metal and dielectric and , respectively. An appropriate relationship can be derived as follows. Assume that the resonance frequency depends on

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Fig. 10. Electric-field distribution for a spherical five-layered TE -mode Bragg resonator containing two hollow spheres of single-crystal YAG, p + p = 0:063; G = 1:85 10 ; Q = 4:85 10 (at 25 GHz).

2

2

where

Fig. 9. Electric-field distribution for spherical TE -mode dielectric resonators containing: (a) two hollow spheres of single-crystal quartz " = " = 4:44; G = 22350 ; pe2 + pe4 = 0:1436 and (b) two hollow spheres of single-crystal YAG, G = 117 960 ; p + p = 0:098 77.

the four variables . Taking derivative of frequency with respect to temperature, one obtains

(18) After some algebra, one obtains (19)

The computed values of temperature coefficients of the resonance frequency are shown in Table III. Computations have been performed for the resonant structures having the parameters shown in Appendix I (and the table therein) and Table II. One can notice that, for Bragg-reflection resonators made of high-permittivity material, the thermal expansion of the dielectric has the dominant influence on , while for those made of low-permittivity material, the influence of the thermal expansion of metal and the temperature also become important. It is worth coefficient of permittivity noting that the thermal stability of spherical Bragg-reflection resonators is better than that of an empty metal cavity made of copper. To obtain a thermally stable Bragg-reflection resonant , one has to use a dielectric with a structure with negative temperature coefficient of permittivity. One can easily assess that, for dielectric material having the same permittivity as YAG, thermal coefficient of permittivity should be equal C. For temperature-stable ceramics, to used for dielectric resonators, manufacturers usually define , which includes both the thermal expansion the parameter

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Fig. 12. Disassembled spherical Bragg-reflection resonator with hollow single-crystal quartz sphere.

Assuming that, for typical ceramic materials, is in the range of 6 12 10 C, one can evaluate that, for a temperature-stable Bragg-reflection resonator made of ceramics with permittivity equal to 10.6, the temperature should be in the coefficient of the resonance frequency range 72 122 10 C. For a material having a C, should be permittivity of 24 and 161 10 C. Commercially available microwave ceramics have temperature coefficients of the resonance frequency at least four times smaller. Since for Bragg-type resonators the relationship between the temperature coefficient of the resonance frequency, the coefficients of thermal expansion, and the temperature coefficient of permittivity depend on all the , which parameters of the resonant structure, evaluation of is necessary to ensure thermal stability, must be performed individually for each specific case.

Fig. 11. (a) Geometric factors for five-layered TE spherical resonator versus radial mode number. Dotted lines show asymptotic -factor values given by (17). (b) Electric energy filling factor in two Bragg reflectors ( + ) for five-layered TE spherical resonator versus radial mode number.

G

p

p

TABLE III TEMPERATURE COEFFICIENTS OF THE RESONANCE FREQUENCY FOR QUARTER-WAVELENGTH REFLECTOR SPHERICAL TE -MODE RESONATORS

and temperature coefficient of permittivity in the following manner: (20) Expression (20) is valid for the mode and WGM dielectric resonators in free space or in sufficiently large metal enclosures with no additional elements. In such a case, the thermal expansion of the metal shield can be neglected and .

V. EXPERIMENTS Based on theory presented in Sections II and III and Appendix I, spherical Bragg-reflection resonators made of single-crystal quartz and YAG have been constructed, and a photograph is shown in Fig. 12. The dielectric spheres were mounted inside a silver-plated brass enclosure using Teflon supports. For the single-crystal quartz resonator, its anisotropy axis was perpendicular to the equatorial plane of the cavity cross section. Results of the experiments on the resonators are shown in Fig. 13 and are summarized in Table IV. In our computations, for single-crystal quartz and we assumed for YAG to fit measured -factor values of modes whose factors strongly depend on dielectric losses (electric energy filling factors for these modes are larger than 0.5). The measured resonance frequencies and temperature coefficients of the resonance frequency were very close to their theoretical values. The relatively small discrepancies between factors probably have a few oritheoretical and measured gins. Firstly, small displacements of the dielectric spheres with respect to the center of the cavity may exist, causing -factor degradation. Secondly, losses in real single crystals versus frequency do not exactly follow simplified models that were assumed in theoretical computations. In addition to that, there are small extra dielectric losses in Teflon supports.

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Fig. 13.

Q factors of three-layered spherical resonators versus frequency. Dots: theoretical values. Triangles: results of experiments. TABLE IV

MEASURED TE

-MODE RESONANT FREQUENCIES AND UNLOADED

Q FACTORS FOR BRAGG-REFLECTION RESONATORS AND EMPTY CAVITY (

r3

= 12:02)

TABLE V MEASURED DIELECTRIC PROPERTIES OF A FEW LOW-LOSS DIELECTRIC MATERIALS

VI. CONCLUSION Spherical three-layered -mode Bragg-reflection resfactor than onators have one order of magnitude higher the traditional -mode dielectric resonators and a few -mode times larger factor than a corresponding empty spherical cavity. This can be achieved by concentrating the electromagnetic energy inside a hollow dielectric sphere. -mode Bragg dielecHigher order spherical five-layered tric resonators are expected to achieve factors over 1 million at millimeter-wave frequencies. The practical implementation of such structures as extremely high- and temperature-stable resonators requires solutions of the following two technological problems. • The procurement of hollow dielectric hemispheres having wall thickness of the order 1 mm (for 25 GHz) or below.

• The manufacturing of low-loss dielectrics with temperin the ature coefficients of the resonance frequency range from 85 ppm/ C to 150 ppm/ C for thermally stable Bragg resonators. Such a requirement on the coefficient of the resonance frequency for the dielectric material is important only if the modulus of the temperature coeffineeds to be smaller cient of the resonance frequency than 10 ppm/ C. Using currently available low-loss dielectric materials, one can construct high- -factor Braggreflection resonators with temperature coefficients of the resonance frequency in the range from 18 ppm/ C to 9 ppm/ C. APPENDIX I Table V presents the measured dielectric properties of a few low-loss dielectric materials.

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APPENDIX II DESIGN OF MULTILATERAL QUARTER-WAVELENGTH SPHERICAL BRAGG RESONATORS spherical Bragg-reflecHigh- -factor multilayered tion resonators can be designed as an assembly of “quarterwavelength” dielectric layers separated by “quarter-wavelength” air layers. In addition, the radius of the first layer should be equal to the th multiple of a “half wavelength” corresponding to the resonance frequency. Taking into account the formulas for the electric-field distribution (4)–(5), a design procedure is as follows. from Step 1) For a given resonance frequency, evaluate the boundary condition This yields the following straightforward expression for : (21) where

is the th root of the equation

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[4] J. Krupka, K. Derzakowski, A. Abramowicz, M. E. Tobar, and R. G. Geyer, “Whispering gallery modes for complex permittivity measurements of ultra-low loss dielectric materials,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 6, pp. 752–759, Jun. 1999. [5] J. Krupka, “Precise measurements of the complex permittivity of dielectric materials at microwave frequencies,” Mater. Chem. Phys., vol. 79, no. 2–3, 10, pp. 195–198, Apr. 2003. , “Precise measurements of the complex permittivity of bulk [6] and tape dielectric materials at microwave frequencies,” presented at the Asia–Pacific Microwave Conf. Workshop (Special Section for Microwave Materials, 106 Slides), Dec. 3–6, 2001 [CD ROM]. [7] M. E. Tobar and A. G. Mann, “Resonant frequencies of higher order modes in cylindrical anisotropic dielectric resonators,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 12, pp. 2077–2083, Dec. 1991. [8] M. E. Tobar, J. D. Anstie, and J. G. Hartnett, “High- whispering modes in empty spherical cavity resonators,” IEEE Trans. Ultrason. Ferroelectr. Freq. Control, vol. 50, no. 11, pp. 1407–1412, Nov. 2003. [9] C. J. Maggiore, A. M. Clogston, G. Spalek, W. C. Sailor, and F. M. Mueller, “Low loss microwave cavity using layered-dielectric materials,” Appl. Phys. Lett., vol. 64, pp. 1451–1453, 1994. [10] C. A. Flory and R. C. Taber, “High performance distributed Bragg reflector microwave resonator,” IEEE Trans. Ultrason., Ferroelectr., Freq. Control, vol. 44, no. 5, pp. 486–495, Mar. 1997. [11] C. A. Flory and H. L. Ko, “Microwave oscillators incorporating high performance distributed Bragg reflector resonators,” IEEE Trans. Ultrason. Ferroelectr. Freq. Control, vol. 45, no. 3, pp. 824–829, May 1998. [12] M. E. Tobar, D. Cros, P. Blondy, and E. N. Ivanov, “Compact highTE sapphire-rutile microwave Bragg resonator,” IEEE Trans. Ultrason. Ferroelectr. Freq. Control, vol. 48, no. 3, pp. 821–829, May 2001. [13] J. G. Hartnett, M. E. Tobar, D. Cros, J. Krupka, and P. Guillon, “High mode res-factor Bragg-reflection sapphire-loaded-cavity TE onators,” IEEE Trans. Ultrason. Ferroelectr. Freq. Control, vol. 49, no. 12, pp. 1628–1634, Dec. 2002. [14] M. E. Tobar, C. R. Locke, E. N. Ivanov, J. G. Hartnett, O. Piquet, and D. Cros, “High- factor frequency-temperature compensated sapphire Bragg distributed resonator,” Electron. Lett., vol. 39, no. 9, pp. 293–295, 2003. [15] O. Piquet, A. Laporte, D. Cros, S. Verdeyme, and M. E. Tobar, “Highsapphire resonator with distributed Bragg reflectors,” Electron. Lett., vol. 39, no. 25, pp. 1791–1792, 2003. [16] M. E. Tobar, J.-M. Le Floch, D. Cros, J. Krupka, J. D. Anstie, and J. G. Hartnett, “Spherical Bragg reflector resonators,” IEEE Trans. Ultrason. Ferroelectr. Freq. Control, vol. 59, no. 9, pp. 1054–1059, Sep. 2003. [17] M. Gastine, L. Courtois, and J. L. Dormann, “Electromagnetic resonances of free dielectric spheres,” IEEE Trans. Microw. Theory Tech., vol. MTT-15, no. 12, pp. 694–700, Dec. 1967. [18] A. Julien and P. Guillon, “Electromagnetic analysis of spherical dielectric shielded resonators,” IEEE Trans. Microw. Theory Tech., vol. MTT-34, no. 6, pp. 723–729, Jun. 1986. [19] D. Kajfez, “Incremental frequency rule for computing the factor of dielectric resonator,” IEEE Trans. Microw. Theory a shielded TE Tech., vol. MTT-32, no. 8, pp. 941–943, Aug. 1984. [20] Y. Kobayashi, Y. Aoki, and Y. Kabe, “Influence of conductor shields on the -factors of a TE dielectric resonator,” in IEEE MTT-S Int. Microwave Symp. Dig., 1985, pp. 281–284.

Q

Q

Step 2) Assuming , solve the system of linear equations (22) with respect to unknown coefficients and (22) and then solve nonlinear equation (23) with respect to (23) Step 3) Solve the system of linear equations (24) with reand spect to unknown coefficients (24) and then solve nonlinear equation (25) with respect to

Q

Q

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(25) For a larger number of layers, Steps 2) and 3) should be repeated for subsequent pairs of layers to evaland and radii . uate coefficients REFERENCES [1] J. Krupka, K. Derzakowski, M. E. Tobar, J. Hartnett, and R. G. Geyer, “Complex permittivity of some ultralow loss dielectric crystals at cryogenic temperatures,” Meas. Sci. Technol., vol. 10, pp. 387–392, Oct. 1999. [2] D. Kajfez and P. Guillon, Dielectric Resonators. Norwood, MA: Artech House, 1986, ch. 6, p. 285. [3] J. Krupka, K. Derzakowski, B. Riddle, and J. Baker-Jarvis, “A dielectric resonator for measurements of complex permittivity of low loss dielectric materials as a function of temperature,” Meas. Sci. Technol., vol. 9, pp. 1751–1756, Oct. 1998.

Jerzy Krupka (M’00–SM’01) was born in Cracow, Poland, in 1949. He received the M.Sc. (with honors), Ph.D., and habilitation degrees from the Warsaw University of Technology, Warsaw, Poland, in 1973, 1977, and 1989, respectively. Since 1973, he has been with the Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, where he is currently a Professor. His research deals mainly with measurements of the electric and magnetic properties of materials at microwave frequencies and he is an international expert in this field. He was a leader and took part in several research projects on these subject in the U.S., U.K., Australia, Germany, and France. He has authored or coauthored over 100 papers appearing in international journals, encyclopedias, and conference proceedings. Dr. Krupka has been an Editorial Board member for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. since 1994. He was the recipient of the 1999 Best Paper Award in Measurements Science and Technology (U.K.).

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Michael E. Tobar (S’87–A’90–M’96–SM’01) was born in Maffra, Australia, on January 3, 1964. He received the B.Sc. degree in theoretical physics and mathematics and the B.E. (with honors) degree in electrical and computer systems engineering from Monash University, Melbourne, Australia, in 1985 and 1988, respectively, and the Ph.D. degree from the University of Western Australia (UWA), Perth, Australia, in 1992. His dissertation concerned gravitational wave detection and low-noise sapphire oscillators. From 1992 to 1993, he was a Research Associate with the UWA. From 1994 to 1996, he was an Australian Post-Doctoral Research Fellow with the UWA and, during 1997, he was a Senior Research Associate. From 1997 to 1998, he was a Research Fellow of the Japan Society for the Promotion of Science with the University of Tokyo, Tokyo, Japan. During 1998, he was a Visiting Professor with the Institut de Recherche en Communications Optiques et Microondes (CNRS), University of Limoges, Limoges, France. From 1999 to 2000, he was a Research Director of the CNRS for 11 months. He is currently an Associate Professor with the School of Physics, UWA. His research interests encompasses the broad discipline of frequency metrology, precision measurements, and precision tests of the fundamental of physics. He also leads Australian involvement in the Atomic Clock Ensemble in Space (ACES) mission. Dr. Tobar was the recipient of the 1999 Best Paper Award presented by the Institute of Physics Measurement Science and Technology, the 1999 European Frequency and Time Forum Young Scientist Award, the 1997 Australian Telecommunications and Electronics Research Board (ATERB) Medal, the 1996 URSI Young Scientist Award, and the 1994 Japan Microwave Prize. He was also the recipient of an Australian Professorial Fellowship presented by the Australian Research Council to focus on his research interests.

John G. Hartnett was born in Manjimup, Western Australia, on March 24, 1952. He received the B.Sc. (with honors) and Ph.D. (with distinction) degrees from the University of Western Australia (UWA), Perth, Australia, in 1973 and 2001, respectively. He is currently an Australian Research Council (ARC) Post-Doctoral Research Fellow with the Frequency Standards and Metrology Research Group, UWA. His current research interests include ultra-low-noise radar, ultra-high-stability microwave clocks based on pure sapphire resonators, tests of fundamental theories of physics such as special and general relativity, and measurement of drift in fundamental constants and their cosmological implications.

Dominique Cros received the Ph.D. degree in electrical engineering from the University of Limoges, Limoges, France in 1990. In 1990, he became an Assistant Professor with the Faculty of Science, University of Limoges. Since 1999, he has been Professor with the Faculty of Science, University of Limoges. He currently conducts research with the Research Institute in Optical and Microwave Communications (IRCOM), University of Limoges. His current research interests are planar and dielectric resonators for filters and oscillator applications at microwave frequencies, electromagnetic tools to design microwave systems, and application of new materials in millimeter-wave devices.

Jean-Michel Le Floch is in his first year as a double Ph.D. student in RF and optical telecommunications at the University of Limoges, Limoges, France, and the University of Western Australia (UWA), Perth, Australia. His current doctoral thesis concerns the design of high dielectric resonators.

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Excitation of Coupled Slotline Mode in Finite-Ground CPW With Unequal Ground-Plane Widths George E. Ponchak, Senior Member, IEEE, John Papapolymerou, Senior Member, IEEE, and Manos M. Tentzeris, Senior Member, IEEE

Abstract—The coupling between the desired coplanar-waveguide (CPW) mode and the unwanted coupled slotline mode is presented for finite-ground CPWs with unequal ground-plane widths. Measurements, quasi-static conformal mapping, and finite-difference time-domain analysis are performed to determine the dependence of the slotline-mode excitation on the physical dimensions of the finite-ground coplanar line and on the frequency range of operation. It is shown that the ratio of the slotline mode to the CPW mode can be as high as 10 dB. Air-bridges are shown to reduce the slotline mode by 15 dB immediately after the air-bridge, but the slotline mode fully reestablishes itself within 2000 m of the air-bridge. Furthermore, these results are independent of frequency. Index Terms—Coplanar waveguide (CPW), coupling, transmission lines.

I. INTRODUCTION

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INITE-GROUND coplanar waveguide (CPW) is often used in low-cost monolithic microwave integrated circuits (MMICs) because of its numerous advantages over microstrip and conventional CPW with large ground planes. It is uniplanar, which facilitates easy connection of series and shunt elements without via-holes, supports a low-loss quasi-TEM mode over a wide frequency band and, since the ground planes are electrically and physically narrow, typically less than wide where is the guided wavelength, they reduce the circuit size and the influence of higher order modes [1]. Finite-ground CPWs have been used for a multitude of circuits, some of which are lumped elements [2], [3], Wilkinson power dividers [4]–[7], and phase shifters [8], [9] without any reported problems. Finite-ground CPWs were developed and are typically modeled as symmetric transmission lines with slot widths and ground planes of equal values. However, in practice, especially in Wilkinson power dividers, rat-race dividers, switched-line phase shifters, and meander lines, this symmetry is often sacrificed to ease circuit layout. For example, in a Wilkinson power divider, the ground planes between the two sections are often combined, which places a virtual open circuit through the centerline of the circuit and truncates current lines on the ground planes, while the outer ground planes are finite [4]–[7]. In 90 hybrid couplers, there is a virtual short Manuscript received March 1, 2004. G. E. Ponchak is with the Electron Device Technology Branch, National Aeronautics and Space Administration Glenn Research Center, Cleveland, OH 44135 USA. J. Papapolymerou and M. M. Tentzeris are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA. Digital Object Identifier 10.1109/TMTT.2004.840571

circuit through one axis of symmetry that alters the current on the ground planes. Switched-line phase shifters incorporating finite-ground CPW transmission lines also employ asymmetric ground planes because the area between the transmission lines’ paths is often a continuous ground plane, while the ground plane on the outside of the path is finite. It is well known that the coupled slotline mode is excited in CPW circuits if there is a discontinuity or an asymmetry in the transmission line. For example, placing a shunt stub on one side of the CPW line excites the coupled slotline mode [10]. Right-angle bends and T-junctions are examples of other asymmetric CPW discontinuities that excite the coupled slotline mode [11]. It is for this reason that air-bridges are used to equalize the voltage on the two ground planes of CPW lines at the discontinuity and along the CPW line [10]. The asymmetry of the finite-ground planes in CPW lines in practical circuit layouts is also expected to excite the coupled slotline mode, and air-bridges are used in these circuits in the same manner as they are in CPW circuits to reduce this parasitic mode. The difference is that the asymmetry in CPW circuits is often localized at the point of the discontinuity and the air-bridges are placed at the point of the discontinuity, but the asymmetry in asymmetric finite-ground CPW lines is continuous. Therefore, finite-ground CPW lines with uneven groundplane widths may cause higher loss and noise than in the asymmetry at localized points in CPW circuits. In this paper, the effect of this asymmetry is presented for the first time with an emphasis on the excitation of the unwanted slotline mode by the CPW mode. Quasi-static analysis, finite-difference time-domain (FDTD) analysis, and experimental measurements are used to determine the coupling between the CPW mode and the slotline mode. These same methods are also used to determine the effect of air-bridges on the control of the parasitic mode. II. CHARACTERIZATION METHODS The asymmetric finite-ground CPW line is shown schematically in Fig. 1. CPW-type transmission lines are comprised of three separate conductors, and they will support two independent quasi-TEM modes. For symmetric CPWs, these modes are typically called the CPW or even mode and the coupled slotline or odd mode. Either of these two modes can propagate along the transmission line independently if they are excited, and they are coupled to each other at discontinuities. For asymmetric finite-ground CPW transmission lines, the two independent modes are a CPW-like mode and slotline-like mode. (Note:

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A. FDTD

Fig. 1. Schematic of finite-ground CPW with unequal ground-plane widths.

asymmetric CPW transmission lines cannot support two symmetric modes such as the even and odd modes. Instead, the two modes that are supported are typically called the and the modes, which are equivalent to the even and odd modes of symmetric transmission lines.) For the problem considered here, a symmetric finite-ground CPW transmission line supporting the CPW and the coupled slotline mode provides the excitation potentials for the asymmetric finite-ground CPW line in the same way that it would in a Wilkinson power divider or other circuit. Likewise, at the far end of the asymmetric finite-ground CPW line, a symmetric finite-ground CPW transmission line is expected to be placed. Thus, we keep the CPW-like mode and coupled slotline-like mode nomenclature throughout the paper and do not refer to the and modes. Determining or measuring the slotline- and CPW-like modes is difficult and involves measuring the current on each ground plane and then separating it into even and odd modes. A full two-mode analysis of the problem would consider the case when the coupled slotline mode is the excitation signal and the CPW signal is measured, and the case when the CPW mode is the excitation signal and the slotline mode is measured. In other words, a 4 4 scattering matrix would be determined. However, it is very rare that the coupled slotline mode is purposely excited on a CPW line and, in fact, air-bridges are usually used to suppress the slotline mode. Therefore, excitation by the coupled slotline mode is not being considered here, but measurements do show that the results are symmetric if that case is of interest. Thus, for each characterization method in this paper, the CPW mode is excited at the left-hand-side port, as shown in Fig. 1, and the coupled slotline mode is measured at the right-hand side. The circuits are fabricated for the measurements and simulations on silicon wafers with a resistivity of 2500 cm and a thickness of 400 m. The transmission lines are 1.5 m of electron-beam-deposited Au, which corresponds to three skin depths at approximately 25 GHz, over a 0.02- m-thick Ti adhesion layer, but the theoretical simulations assume lossless metals. The air-bridges are 3- m high and 50- m wide and are constructed of 2.5 m of plated Au. Two asymmetric finite-ground CPW geometries are characterized; the first is and of 15, 10, and 45 m, respectively, and the second is and of 50, 28, and 150 m, respectively. The parameter for each case is 0.43 and 0.47, respectively, which yields a characteristic impedance of 50 . The ground width is varied to yield a range of values for from 0.2 to 2.0.

To understand the physics behind the moding of the asymmetric finite-ground CPW lines, cross-sectional field plots are generated with the ATHENA FDTD simulator as two-and-one-half-dimensional (2.5-D) and three-dimensional (3-D) [12], [13]. The first step involves two 2.5-D simulations for even and odd excitation to derive the - and -field distributions for even (“quasi-CPW-like”) and odd excitation (“quasi-slotline-like”) mode in a plane perpendicular to the propagation direction. Various values of propagation constant (from 100 to 1000) are utilized to verify the quasi-TEM nature of both modes and also justify the almost frequency-invariant effective permittivity from 10 to 60 GHz. The 2.5-D simulations are critical for the accurate simulation of the full 3-D cases since they model the nonsymmetric current and voltage distributions due to the unequal ground-plane widths and also allow for the mode decomposition. The full 3-D geometry is excited with even excitation and the -field distribution is recorded at different distances from the air-bridges. Using the 2.5-D derived mode patterns for the -fields, the relative amplitudes of the two modes are identified for various ratios of ground sizes by performing numerical sampling of the 3-D field values with the respective 2.5 mode distributions along the cross sections of interest. It has to be noted that the 2.5-D mode pattern amplitudes have been normalized in such a way that they express the same total transferred power by division with over the value of the numerical surface integral of the transverse cross section. For each asymmetric finite-ground CPW line, the left- and right-hand-side metal ground planes are connected with 50- m air-bridges that are spaced every 2500 m, and the no air-bridge results are analyzed at 2500 m from an air-bridge. B. Conformal Mapping While FDTD analysis can yield a very accurate frequencydependent solution, it is time consuming and computationally extensive. Quasi-static solutions employing conformal mapping are widely used to determine the characteristic impedance of CPW and finite-ground CPW lines [14]. Here, conformal mapping is employed to determine the ratio of the slotline-like mode to the CPW-like mode from a calculation of the capacitance between each ground plane and center conductor. Fig. 2 illustrates the asymmetric finite-ground CPW line and its transformation into an equivalent structure. The structure shown in Fig. 2(b) is equivalent to the structure in [15, Fig. 2]. Therefore, the same analysis can be performed to determine the capacitance between line segment and the portion of the segment above it and the capacitance between line segment and the portion of the line segment above it, which are capacitances and , respectively. Due to the quasi-static equivalence between Fig. 2(a) and (b), and are the capacitances between ground planes of width and and the center conductor, respectively. The broken line from point to the line segment is a perfect magnetic wall that is an estimation of the exact location of the nonlinear magnetic wall. The ratio of the slotline-like mode to the CPW-like mode is found from .

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Fig. 4. Ratio of slotline mode to CPW mode measured and determined by FDTD analysis of an asymmetric line with S = 15 m, W = 10 m, B 1 = 45 m, and B 2=B 1 = 0:2. Fig. 2. (a) Asymmetric finite-ground CPW and its transformation into the W -plane (b). In (b), the broken lines are perfect magnetic walls.

Fig. 5. Ratio of slotline mode to CPW mode as a function of k and B 2=B 1 determined by conformal mapping. Fig. 3. Ratio of slotline mode to CPW mode at the end of an asymmetric finite ground coplanar line with S = 15 m, W = 10 m, and B 1 = 45 m.

C. Measurement Procedure Measuring circuits with noninsertable probe pads (ground–signal–ground (GSG) on the left-hand side and ground–signal (GS) on the right-hand side) is a difficult task. Various methods were tried, including a two-tier deembedding process, but the most consistent results are obtained by performing a thru-reflect-line (TRL) calibration with symmetric GSG probes at both ends of the line using standards fabricated on-wafer and substituting a GS probe for the right-hand-side GSG probe. For the measurements, the asymmetric transmission line is transitioned to symmetric probe pads by a 150- m-long linear taper to facilitate the symmetric GSG probes. During the measurements, a quartz wafer was placed between the silicon wafer and the metal wafer chuck. Due to these difficulties and the fact that GS probes are not accurate when unbalanced currents are present at the probe tips, the measurements shall be considered approximate. III. RESULTS First, to demonstrate the accuracy of the two theoretical methods, Fig. 3 shows the ratio of the slotline-like mode to the CPW-like mode at the end of a 12 000- m-long asymmetric finite-ground CPW line with no air-bridges, or the test port far from the air-bridges, and a center conductor width of 15 m. It

is seen that there is excellent agreement, which indicates that either method may be used. Both the FDTD analysis and measured results indicate that the characteristics shown in Fig. 3 are independent of the frequency from 1 to 50 GHz, which is shown in Fig. 4. Fig. 4 shows only one case ( m, , and ) of measured and FDTD analysis, but it is representative of the other cases. This demonstrates that the excitation of the slotline-like mode is due to quasi-static effects, which further confirms the appropriateness of using the conformal mapping. Fig. 5 shows the ratio of the slotline-like mode to CPW-like mode determined by conformal mapping as a function of the ratio of the ground planes. It is seen that the slotline-like mode is large, i.e., 10 dB, when is small and theoretically decreases to zero when . Although the slotline-like mode increases for large ratios of , it does not reach values above 25 dB. Furthermore, the slotline-like mode is stronger for smaller values of , which corresponds to higher characteristic impedance values. The slotline-like mode excitation is inversely dependent on the ground-plane width , as shown in Fig. 6, and decreases approximately by 6 dB as in increased from to . Larger ground sizes decrease the effect of the asymmetry because the majority of current in the ground planes is within to of the slots. Fig. 7 shows the measured ratio of the slotline-like mode to the CPW-like mode for asymmetric finite-ground CPW lines without air-bridges and a length of 13 000 m. It is seen that

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Fig. 6. Ratio of slotline mode to CPW mode as a function of ground-plane width B 1 for k = 0:5.

Fig. 8. Ratio of slotline mode to CPW mode as a function of distance from an air-bridge determined by FDTD. (a) Drawing of the circuit analyzed.

Fig. 7. Measured ratio of slotline mode to CPW mode on asymmetric finite-ground coplanar lines without air-bridges. (B 1 = 3S ).

the measured results qualitatively and quantitatively agree with the theoretical results in Fig. 3, except for the absence of a null at and m. For all of the measurements taken, the GS probe characteristics have less scatter and error for the narrower transmission lines than the wider lines. Thus, the lack of the null at is believed due to a higher noise floor for the - m measurements. The maximum slotline-like mode magnitude is 18 dB for Characterization of asymmetric finite-ground CPW lines of different lengths further shows that the ratio of the slotline-like mode to the CPW-like mode is independent of line length. The typical method of eliminating the parasitic slotline mode is to place air-bridges between the two ground planes periodically along CPW lines. An FDTD analysis of asymmetric finite-ground CPW lines with air-bridges spaced every 2500 m was performed. The ratio of the slotline-like mode to the CPWlike mode as a function of the distance from an air-bridge is shown in Fig. 8. It is seen that the ratio is small immediately after the air-bridge, but that the slotline-like mode grows linearly for 2000 m, after which the slotline-like mode magnitude saturates to the value without air-bridges. This characteristic is also found to be independent of frequency over the range of 1–50 GHz. Note that 2000 m is approximately at 15 GHz and, for lower frequencies, air-bridges must be placed at very small electrical lengths to suppress this mode. A set of asymmetric finiteground CPW lines was fabricated with air-bridges placed every 1000 m and the last air-bridge between 1000–4000 m from

the right-hand-side port. The maximum measured decrease in the slotline-like mode is 5 dB, which occurs when the air-bridge is 1000 m from the measurement port. At the air-bridge, it is expected that the slotline-like mode is eliminated, but as shown in Fig. 8, the mode still exists. Since the numerical noise floor of the FDTD analysis is lower than 50 dB, the slotline-like mode measured at the air-bridge is probably due to higher order evanescent modes in the near field of the air-bridge discontinuity and to the fact that the actual modes supported on the asymmetric finite-ground CPW are and modes that are not strictly equivalent to the CPW and slotline modes. IV. CONCLUSIONS The layout of circuits with CPW lines with unequal finite-ground-plane widths is demonstrated to cause a significant slotline-like mode to be excited. It is shown that the use of air-bridges does not eliminate the slotline mode, but it reduces the mode within short distances of the air-bridge. Lastly, these results are independent of frequency. Thus, air-bridges must be placed at short distances in asymmetric finite-ground CPW lines, even for low-frequency circuits. REFERENCES [1] G. E. Ponchak, L. P. B. Katehi, and E. M. Tentzeris, “Finite ground coplanar (FGC) waveguide: Its characteristics and advantages for use in RF and wireless communication circuits,” in 3rd Int. Wireless Communications Conf. Dig., Nov. 1–3, 1998, pp. 75–83. [2] G. E. Ponchak and L. P. B. Katehi, “Characteristics of finite ground coplanar waveguide lumped elements,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 8–13, 1997, pp. 1003–1006. [3] L. Zhu and K. Wu, “Characterization of finite-ground CPW reactive series-connected elements for innovative design of uniplanar M(H)MICs,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 2, pp. 549–557, Feb. 2002.

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[4] M. C. Scardelletti, G. E. Ponchak, and T. M. Weller, “Miniaturized Wilkinson power dividers utilizing capacitive loading,” IEEE Microw. Wireless Compon. Lett., vol. 12, no. 1, pp. 6–8, Jan. 2002. , “Corrections to ‘Miniaturized Wilkinson power dividers utilizing [5] capacitive loading’,” IEEE Microw. Wireless Compon. Lett., vol. 12, no. 4, p. 145, Apr. 2002. [6] T. M. Weller, R. M. Henderson, K. J. Herrick, S. V. Robertson, R. T. Kilm, and L. P. B. Katehi, “Three-dimensional high-frequency distribution networks—Part I: Optimization of CPW discontinuities,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 10, pp. 1635–1642, Oct. 2000. [7] R. M. Henderson, K. J. Herrick, T. M. Weller, S. V. Robertson, R. T. Kilm, and L. P. B. Katehi, “Three-dimensional high-frequency distribution networks—Part II: Packaging and integration,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 10, pp. 1643–1651, Oct. 2000. -band, [8] M. C. Scardelletti, G. E. Ponchak, and N. C. Varaljay, “ MEMS switched line phase shifters implemented in finite ground coplanar waveguide,” in 32nd Eur. Microwave Conf. Dig., Sep. 23–27, 2002, pp. 797–800. [9] D. Pilz, K. M. Strohm, and J. F. Luy, “SIMMWIC–MEMS 180 switched line phase shifter,” in IEEE Silicon Monolithic Integrated Circuits in RF Systems Topical Meeting Dig., Apr. 26–28, 2000, pp. 113–115. [10] N. I. Dib, M. Gupta, G. E. Ponchak, and L. P. B. Katehi, “Characterization of asymmetric coplanar waveguide discontinuities,” IEEE Trans. Microw. Theory Tech., vol. 41, no. 9, pp. 1549–1558, Sep. 1993. [11] R. N. Simons and G. E. Ponchak, “Modeling of some coplanar waveguide discontinuities,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 12, pp. 1796–1803, Dec. 1988. [12] A. Taflove, Computational Electrodynamics. Dedham, MA: Artech House, 1995. [13] L. Roselli, E. Tentzeris, and L. P. B. Katehi, “Nonlinear circuit characterization using a multiresolution time domain technique,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 7–9, 1998, pp. 1387–1390. [14] R. N. Simons, Coplanar Waveguide Circuits, Components, and Systems. New York: Wiley, 2001. [15] K.-K. M. Cheng, “Analysis and synthesis of coplanar coupled lines on substrates of finite thickness,” IEEE Trans. Microw. Theory Tech., vol. 44, no. 4, pp. 636–639, Apr. 1996.

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George E. Ponchak (S’82–M’83–SM’97) received the B.E.E. degree from Cleveland State University, Cleveland, OH, in 1983, the M.S.E.E. degree from Case Western Reserve University, Cleveland, OH, in 1987, and the Ph.D. degree in electrical engineering from The University of Michigan at Ann Arbor, in 1997. In 1983, he joined the staff of the Communication Technology Division, National Aeronautics and Space Administration (NASA) Glenn Research Center, Cleveland, OH, where he is currently a Senior Research Engineer. From 1997 to 1998 and 2000 to 2001, he was a Visiting Lecturer with Case Western Reserve University. He has authored and coauthored over 90 papers in refereed journals and symposia proceedings. His research interests include the development and characterization of microwave and millimeter-wave printed transmission lines and passive circuits, multilayer interconnects, uniplanar circuits, microwave microelectromechanical (MEMS) components, and microwave packaging. He is responsible for the development of GaAs, InP, and SiGe MMICs for space applications. Dr. Ponchak is a senior member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) and a member of the International Microelectronics and Packaging Society (IMAPS). He was the recipient of the Best Paper of the ISHM’97 30th International Symposium on Microelectronics Award. He was editor of a Special Issue on Si MMICs of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He founded the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems and served as its chair in 1998 and 2001 and its digest editor in 2000 and 2003. In addition, he has chaired many IEEE MTT-S International Microwave Symposium workshops and special sessions. He is a member of the IEEE MTT-S International Microwave Symposium (IMS) Technical Program Committee (TPC) on Transmission Line Elements and serves as its chair. He is a member of the IEEE MTT-S Administrative Committee (AdCom) Membership Services Committee.

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John Papapolymerou (S’90–M’99–SM’04) received the B.S.E.E. degree from the National Technical University of Athens, Athens, Greece, in 1993, and the M.S.E.E. and Ph.D. degrees from The University of Michigan at Ann Arbor, in 1994 and 1999, respectively. From 1999 to 2001, he was a faculty member with the Department of Electrical and Computer Engineering, University of Arizona, Tucson. During the summers of 2000 and 2003, he was a Visiting Professor with The University of Limoges, Limoges, France. In August 2001, he joined the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, where he is currently an Assistant Professor. He has authored or coauthored over 70 publications in peer-reviewed journals and conferences. His research interests include the implementation of micromachining techniques and MEMS devices in microwave, millimeter-wave, and terahertz circuits, and the development of both passive and active planar circuits on Si and GaAs for high-frequency applications. Dr. Papapolymerou was the recipient of the 2002 National Science Foundation (NSF) CAREER Award, the Best Paper Award presented at the 3rd IEEE International Conference on Microwave and Millimeter-Wave Technology (ICMMT2002), Beijing, China (August 17–19, 2002), and the 1997 Outstanding Graduate Student Instructional Assistant Award presented by the American Society for Engineering Education (ASEE), The University of Michigan Chapter.

Manos M. Tentzeris (SM’03) received the Diploma degree in electrical and computer engineering from the National Technical University of Athens, Athens, Greece, in 1992, and the M.S. and Ph.D. degrees in electrical engineering and computer science from The University of Michigan at Ann Arbor, in 1993 and 1998, respectively. He is currently an Associate Professor with School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta. During the summer of 2002, he was a Visiting Professor with the Technical University of Munich, Munich, Germany. He has authored or coauthored over 120 papers in refereed journals and conference proceedings and six book chapters. He has helped develop academic programs in highly integrated packaging for RF and wireless applications, microwave MEMs, SOP-integrated antennas and adaptive numerical electromagnetics (FDTD, multiresolution algorithms). He is the Georgia Tech National Science Foundation (NSF)-Packaging Research Center Associate Director for RF Research and the RF Alliance Leader. He is also the Leader of the Novel Integration Techniques Sub-Thrust of the Broadband Hardware Access Thrust of the Georgia Electronic Design Center (GEDC) of the State of Georgia. Dr. Tentzeris is member of the Technical Chamber of Greece. He was the 1999 Technical Program co-chair of the 54th ARFTG Conference, Atlanta, GA. He is the vice-chair of the RF Technical Committee (TC16) of the IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society. He was the recipient of the 2003 IEEE CPMT Outstanding Young Engineer Award, the 2002 International Conference on Microwave and Millimeter-Wave Technology Best Paper Award (Beijing, China), the 2002 Georgia Tech-Electrical and Computer Engineering (ECE) Outstanding Junior Faculty Award, the 2001 ACES Conference Best Paper Award, the 2000 NSF CAREER Award, and the 1997 Best Paper Award, International Hybrid Microelectronics and Packaging Society.

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Estimation of Complex Permittivity of Arbitrary Shape and Size Dielectric Samples Using Cavity Measurement Technique at Microwave Frequencies Mrityunjay Santra and K. U. Limaye

Abstract—In this paper, a simple cavity measurement technique is presented to estimate the complex permittivity of arbitrary shape and size dielectric samples. Measured shift in resonant frequency and change in quality factor due to the dielectric sample loading in the cavity is compared with simulated values obtained using the finite-element method software High Frequency Structure Simulator and matched using the Newton–Raphson method to estimate the complex permittivity of a arbitrary shape and size dielectric sample. Complex permittivity of Teflon (PTFE) and an MgO–SiC composite is estimated in the -band using this method for four different samples of varying size and shapes. The result for Teflon shows a good agreement with the previously published data, and for the MgO–SiC composite, the estimated real and imaginary parts of permittivity for four different shape and size samples are within 10%, proving the usefulness of the method. This method is particularly suitable for estimation of complex permittivity of high-loss materials. Index Terms—Complex permittivity measurement, finiteelement method (FEM).

I. INTRODUCTION

D

IELECTRIC materials are widely used in various microwave and millimeter-wave components. An exact knowledge of complex permittivity of these dielectric materials at microwave frequencies is of the utmost importance to accurately design microwave passive and active devices. Several methods of complex permittivity measurement of dielectrics such as: 1) the free-space technique and 2) the coaxial/waveguide measurement technique and cavity perturbation technique, etc., and their advantages and limitations have been discussed [1]–[3]. As reported, most of these methods, however, require the samples to be of specific shape and size only. There are situations where it may not be possible to have samples in specifically required dimensions. Several attempts were made earlier using different techniques to measure complex permittivity of samples of arbitrary shape and size. The technique reported, by Deshpande et al. [1] measures complex permittivity of arbitrary shape and size samples using waveguide measurement. The method presented by Coccioli et al. [4] can only estimate the real Manuscript received March 8, 2004. This work was supported by the Defence Research Development Organisation, Ministry of Defence, Government of India. M. Santra is with the Microwave Tube Research and Development Centre, Defence Research Development Organisation, Bangalore-560013, India (e-mail: [email protected]). K. U. Limaye is with the Electronics Radar Development Establishment, Defence Research Development Organisation, Bangalore-560093, India. Digital Object Identifier 10.1109/TMTT.2004.840570

Fig. 1.

Resonant cavity with a dielectric sample.

part of complex permittivity. The method of Rueggerberg [5] requires more than one sample of different materials with (the real part of the complex relative permittivity) close values to estimate the loss tangent. Thakur and Holmes [3] compare computed and estimated values of the -parameter at all measured frequencies around the resonance peak using a restricted Monte Carlo simulation to estimate complex permittivity. The method presented here is a general one and can estimate complex permittivity of samples of arbitrary shape and size using a cavity measurement technique. In this method, the frequency of resonance and the quality factor ( factor) of a rectangular cavity are measured using a scalar network analyzer, both for the unloaded cavity and for the cavity loaded with a dielectric sample. The same cavity structure is simulated and analyzed to obtain the resonant frequency and factor using the finite-element method (FEM) software High Frequency Structure Simulator (HFSS)1 with and without the dielectric sample inside the cavity. The shift in resonant frequency and change in the factor obtained from both measurement and simulation are then matched using the Newton–Raphson method to estimate the complex permittivity of the sample. II. REVIEW OF THE SMALL PERTURBATION THEORY The theory of perturbation of cavity resonators has been given by numerous authors [2], [6]. A dielectric sample of volume (nonmagnetic, i.e., ) is placed in a resonant cavity having volume (see Fig. 1) in which is the electric-field inis the electric field in the unperturbed terior of the object and 1Hewlett-Packard Company, Santa Rosa, CA, HFSS, release 5.3, Nov. 1998.

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SANTRA AND LIMAYE: ESTIMATION OF COMPLEX PERMITTIVITY OF ARBITRARY SHAPE AND SIZE DIELECTRIC SAMPLES

cavity. Frequency of resonance and the factor both change when the cavity is loaded with a dielectric material. The change in resonant angular frequency may be expressed as [2] (1) where is the complex relative permittivity of the dielectric sample. With the assumption of small perturbation, the change in resand change in the factor due to the onant frequency dielectric material may be expressed as [2] (2) is the shift in the real component of the where factor of the resonant frequency dielectric material [7] with and being the real parts of the resonant frequencies and and being the quality factors of the cavity in the absence and presence of the dielectric sample, respectively. is the shape factor, which depends upon the shape, orientation, size, and permittivity of the dielectric material and (3) The shape factor for some samples of specific shape and size like a rectangular bar, rod, or sphere have been theoretically estimated in a small perturbation condition and have been presented in [2] and [8] and, for such cases, the estimation of and is easily done from measured and using the following relations [2]: (4)

both ends short circuited with metal plates. Each metal plate has a hole at the center of a 10-mm diameter for coupling (see Fig. 1). One waveguide to coaxial (type ) adapter and one small waveguide section is attached at each end. The coaxial ends of both the adapters are, in turn, connected to ports 1 and 2 of a scalar network analyzer for transmission measurement. The cavity without any lossy material shows a number of resonances corresponding to different modes. In this case, three resonance frequencies are observed in the usable frequency range of the WR-284 waveguide, which are at 2.853, 3.2066, and , , and modes, respectively. 3.5918 GHz for When the cavity is loaded with the lossy dielectric material, its resonant frequency and factor change for all three frequencies, i.e., for all three modes. The dielectric sample is placed at distance ( guided wavelength for an approximately waveguide mode) from one end of the cavity. This position gives maximum sensitivity in measurement as the electric field at this position is maximum. The same cavity measurement setup is then simulated using the FEM software HFSS to obtain resonance frequencies and factors for both cases, i.e., for the unloaded cavity and cavity loaded with the dielectric sample. In the simulation, orientation, position, shape, and size of the sample is kept identical to the measurement. This gives the simulated values and . As the complex permittivity of the sample of and is made and is unknown, an educated guess of and are computed. These computed values are then matched with the measured values using the Newton–Raphson method following an iterative procedure, as will be discussed in Section IV. and are the computed values (computed from simIf ulation), and and are the measured values of change in resonant frequency and change in the factor for the dielectric material, then the error in estimation of these two parameter may be written as (6) (7)

(5) However, for samples of arbitrary shape and size, it is not possible to estimate the value of theoretically and, hence, esis not possible from the meatimation of values of and and . In the case of samples with specific sured values of shape and sizes (like a rectangular bar, rod, sphere, etc.), where or or the volume is large, the theory of small perturbation also does not hold well. This deviation from small perturbation theory has been elaborately discussed by Carter [9] and Meng et al. [6] for the cases of samples in a circular cylindrical cavity, which is also applicable in the case of samples in a rectangular cavity and, hence, considerable error may result in an estimation of and using (4) and (5) for these cases. This error also can be corrected using this method and treating these samples as arbitrary shape and size samples. III. ESTIMATION OF COMPLEX PERMITTIVITY OF ARBITRARY SHAPE AND SIZE SAMPLES To estimate and of arbitrary shape and size dielectric samples, an -band cavity measurement setup has made out of a WR284 waveguide section of length equal to 305 mm and with

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If

and are incremented by small values to , then the functions and written in Taylor’s series as

and may be

(8)

(9) where are the higher order terms in the and Taylor’s series, and may be neglected. If the increments are such that and are simultaneously zero, then we can write the following matrix equation: (10)

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The matrix elements in the coefficient matrix are calculated using the FEM software HFSS. The above equation is solved for and , which gives the new modified value of and (11) (12) and are again obtained from simulation with new values using the FEM software HFSS, and the previous of and until required procedures are repeated to obtain new and convergence is obtained, i.e., and become less than or equal to a pre-selected small values. This procedure converges faster to the true value of the complex permittivity if the first choice of both and are close to the true value of the complex permittivity.

Fig. 2. Comparison of estimated " for Teflon samples of different shape and size using the current method with published data [1].

IV. RESULTS To demonstrate the validity of the method presented here, complex permittivity is estimated for the following five PTFE material (Teflon) samples of different shape and size made from a single block of material, as shown in the first set of samples at the bottom of this page. is known and is equal to For Sample 1, the shape factor 1 and, hence, complex permittivity for this sample is estimated using (4) and (5) of the small perturbation theory. For the other four samples, shape factor is not known, though they are of regular shapes. For example, if the length of cylindrical samples 2 and 3 would have been equal to 34 mm (equal to dimension of the waveguide, as shown in Fig. 1) then is known and equal is to 1 (as it is for Sample 1) [2], [8]. As the shape factor not known for these samples, it is not possible to estimate the complex permittivity using (4) and (5) and, hence, it is estimated using the current method and compared with the published data, as well as with the results obtained using the small perturbation theory, and as shown in Figs. 2 and 3. Estimated values of (presented in Fig. 2) shows very good agreement with the published data [1], but in the case of losstangent estimation (shown in Fig. 3), error is quite high. This is

Sample No:

Sample No:

Fig. 3. Comparison of estimated loss tangent (tan  ) for Teflon samples of different shape and size using the current method with published data [1].

because the change in the factor for these samples made of low-loss material like Teflon is too small to accurately measure. Dielectric properties are also estimated for samples made from high dielectric-constant high loss materials like the MgO–SiC composite. Four samples are made from a single block of this composite and dielectric properties are estimated, as shown in the second set of samples at the bottom of this page. For Sample 1, and are estimated from the small perturbation theory (Sample 1,a), as well as using the method presented here (Sample 1,b), as shown in Figs. 4 and 5. For samples 2–4, shape factors are not known; hence, the result estimated using only the current method is presented here. Estimated values of and for all these samples are very close to each other (within

Shape Cylindrical Diameter Cylindrical Diameter Cylindrical Diameter Rectangular mm Rectangular mm

Size mm length mm length mm length mm mm

mm mm mm mm mm

Shape Cylindrical Diameter Cylindrical Diameter Rectangular mm Rectangular mm

Size mm length mm length mm mm

mm mm mm mm

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VI. CONCLUSION

Fig. 4. Variation of estimated " with frequency in the S -band for various shape and size MgO–SiC samples.

A simple cavity measurement technique in conjunction with the FEM software HFSS has been presented to estimate complex permittivity of arbitrary shape and size dielectric samples. Simulated and measured values of shift in resonant frequency and change in the factor have been matched using the Newton–Raphson method for this estimation. Complex permittivity of various shape and size Teflon samples are estimated using this method and have shown good agreement with the published data. Complex permittivity has also been estimated for samples made from high dielectric-constant high loss tangent materials. The time taken for each simulation run of a cavity loaded with a dielectric sample was approximately 1 h on a Sun workstation. Though results presented here are for three discrete frequencies in the -band, it is possible to predict and using this method for other frequencies in the band using different lengths of the cavity. For prediction in other frequency bands, the cavity should be made using waveguide used in those bands. ACKNOWLEDGMENT

Fig. 5. Variation of estimated loss tangent (tan  ) for various shapes and sizes MgO–SiC samples.

The authors are thankful to Dr. L. Kumar, Microwave Tube Research and Development Centre (MTRDC), Defence Research Development Organisation (DRDO), Bangalore, India, for a critical review of this paper’s manuscript and many valuable suggestions for improving this study. REFERENCES

Fig. 6.

Convergence checking of estimation algorithm.

10%) irrespective of the shape and size of the samples, i.e., irrespective of the shape factor . It is worth noting here that, in the case of Sample 1, use of the small perturbation theory directly ) yields an erroneous result. How(assuming shape factor ever, a corrected result for Sample 1 using this method shows good agreement with the estimated values for other samples. V. CONVERGENCE CRITERIA Convergence of the algorithm for estimating complex permittivity of an arbitrary shape and size sample is checked for a typical sample of the MgO–SiC composite with cylindrical geometry of 5.0-mm diameter and 20.0-mm length at are taken as 3.5918 GHz. Initial assumed values of and 30.0 and 12.0, respectively. The convergence criterion is set as and . After seven iterations, a convergence criterion is met, as shown in Fig. 6, and the converged values , , which matches with the values are estimated earlier for this sample.

[1] M. D. Desphande, C. J. Reddy, P. I. Tiemsin, and R. Cravey, “A new approach to estimate complex permittivity of dielectric materials at microwave frequencies using waveguide measurements,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 3, pp. 359–365, Mar. 1997. [2] A. W. Kraszewski and S. O. Nelson, “Observation on resonant cavity perturbation by dielectric objects,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 1, pp. 151–155, Jan. 1992. [3] K. P. Thakur and W. S. Holmes, “An inverse technique to evaluate permittivity of materials in a cavity,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 6, pp. 1129–1132, Jun. 2001. [4] R. Coccioli, G. Pelosi, and S. Selleri, “Characterization of dielectric materials with the finite-element method,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 7, pp. 1106–1111, Jul. 1999. [5] W. Rueggeberg, “Determination of complex permittivity of arbitrarily dimensioned dielectric modules at microwave frequencies,” IEEE Trans. Microw. Theory Tech., vol. MTT-19, no. 6, pp. 517–521, Jun. 1971. [6] B. Meng, J. Booske, and R. Cooper, “Extended cavity perturbation technique to determine the complex permittivity of dielectric materials,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 11, pp. 2633–2636, Nov. 1995. [7] D. M. Pozar, Microwave Engineering. New York: Wiley, 1998, ch. 6. [8] H. Altschuler, Handbook of Microwave Measurements, M. Shukher and J. Fox, Eds. Brooklyn, NY: Polytechnic Press, 1963, vol. 2, pp. 530–536. [9] R. G. Carter, “Accuracy of microwave cavity perturbation measurements,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 5, pp. 918–923, May 2001. [10] A. Prakash, J. K. Vaid, and A. Mansingh, “Measurement of dielectric parameters at microwave frequencies by cavity perturbation technique,” IEEE Trans. Microw. Theory Tech., no. 1, pp. 791–795, Jan. 1979. [11] B. Birnbaum and J. Franeau, “Measurement of microwave dielectric constants and loss of solids and liquids by a cavity perturbation method,” J. Appl. Phys., vol. 20, pp. 817–818, 1949. [12] W. Main, S. Tantawi, and J. Hamilton, “Measurements of the dielectric constant of lossy ceramics,” Int. J. Electron., vol. 720, pp. 499–512, Mar. 1992.

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Mrityunjay Santra was born in Kasigori (West Bengal), India, on January 18, 1966. He received the B.Tech. degree in radio physics and electronics from the University of Calcutta, Calcutta, India, in 1990, and the M.Tech. degree in microwave engineering from the Indian Institute of Technology, Kharagpur, India, in 1999. He is currently with the Microwave Tube Research and Development Centre (MTRDC), Defence Research Development Organisation (DRDO), Bangalore, India. His current field of interest is design and development of microwave tubes.

K. U. Limaye was born in Harihar (Karnataka), India, on August 17, 1946. He received the B.E. degree in electronics from the Indian Institute of Science, Bangalore, India, in 1968, and the M.Tech. degree in microwave engineering from the Indian Institute of Technology, Kharagpur, India, in 1976. He is currently with the Electronics Radar Development Establishment (LRDE), Defence Research Development Organisation (DRDO), Bangalore, India. His research encompasses microwave engineering, antennas, radar systems and microwave tubes.

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Comparison of the “Pad-Open-Short” and “Open-Short-Load” Deembedding Techniques for Accurate On-Wafer RF Characterization of High-Quality Passives Luuk F. Tiemeijer, Ramon J. Havens, André B. M. Jansman, and Yann Bouttement

Abstract—The impedance errors remaining after applying the industry standard “open-short,” a “pad-open-short,” and a “open-short-load” deembedding scheme on a 0.43-nH 20-GHz high- single-loop inductor test structure are investigated using real -parameter data taken up to 50 GHz. Since the latter two deembedding schemes both correct for all parasitic elements of the test structures, they are, at least in principle, error free. The accuracy of the “open-short-load” deembedding scheme, however, critically depends on how well the reactive part of the load resistance is accounted for. This issue makes the more simple “pad-open-short” deembedding scheme an attractive choice because the required split between external and internal capacitances is easy to make, either based on process and layout information or from measurements done on a “pad” dummy structure. Index Terms—Calibration, deembedding, integrated circuits, on-chip inductors, on-wafer microwave measurements. Fig. 1. Illustration of the general four-port description of the parasitics to be deembedded. The DUT is measured at ports 1 and 2, whereas the intrinsic device (INT) is connected to ports 3 and 4.

I. INTRODUCTION

W

ITH THE increasing operating frequencies of many wireless communication standards, the demands on the accuracy of on-wafer -parameter measurements become increasingly stringent. Since there are only limited possibilities to reduce wafer probing parasitics by down scaling of the on-wafer test structures, highly accurate deembedding schemes become a necessity. The most basic deembedding method is the simple “open” deembedding scheme, which was first introduced in 1987 [1]. In this technique, the pad capacitance is measured on an “open” test structure, and used to correct the measurement taken on the device-under-test (DUT). To include interconnect resistance and inductance, the “open-short” deembedding method was introduced in 1991 [2]. This method is now regarded as the industry standard and requires two dummy test structures. However, this approach and alternatives [3], [4], employing a few more dummy structures, assume a specific lumped-element circuit approximation, which reduces deembedding accuracy at high frequencies [5].

Manuscript received March 11, 2004. This work was supported by Philips Semiconductors. L. F. Tiemeijer, R. J. Havens, and A. B. M. Jansman are with Philips Research Laboratories, 5656 AA Eindhoven, The Netherlands (e-mail: Luuk.Tiemeijer@ philips.com). Y. Bouttement is with Philips Semiconductors Caen, 14079 Caen, France. Digital Object Identifier 10.1109/TMTT.2004.840621

In this paper, we compare the benefits of two deembedding strategies employing one additional dummy test structure. The first one is a “pad-open-short” strategy, which is a three-step version of the four-step approach introduced in [6]. The second one is an “open-short-load” strategy, which is a simplified and rationalized version of the approaches proposed in [7] and [8]. We will first show that both approaches consider all relevant parasitics in a general manner and, thus, are, at least in theory, well suited to provide better accuracy at high frequencies. II. FOUR-PORT PARASITIC DEEMBEDDING THEORY To generalize the deembedding problem and avoid potential errors by simplifications, a four-port system calibration methodology was introduced in [8]. In this methodology, the I–V relationships between the extrinsic and intrinsic ports (Fig. 1) are expressed in a 4 4 -matrix according to

(1)

The notation can be significantly simplified by defining and to represent the extrinsic voltage and current vectors, and

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and to represent the intrinsic voltage and current vectors. This reduces the above equation to

and represent the values of the resistances in and where these structures. With these dummy structures, the matrix can be found solving

(2) where are four 2 2 matrices. Using these, the and measured exdesired intrinsic device -parameters can be related as [8] trinsic -parameters (3) In [8], a procedure requiring five dummy structures is further given to find all 16 variables of the four 2 2 matrices. The industry standard “open-short” deembedding method uses only , two of these dummy structures, an “open” where . Applying this, one obtains and a “short” where (4) and (5) In the “open-short” method, the deembedded device parameters are calculated by

(11) and (12) and , but we can There are two possible solutions for select the correct ones by requiring the matrix to be continuous over frequency and equal to unity at low frequency. Since many practical on-wafer test structures are drawn with identical left and right ports, the reciprocal four-port parasitic deembedding scheme is still too general. When the left and right ports are identical, the number of independent parameters in the symmetrical 4 4 parasitics matrix reduces from 10 to 6. As a result of this, the number of independent parameters in the matrix reand , duces from 4 to 2 since we will have and we can omit the second resistive load dummy structure because it does not provide any new information. Alternatively, a symmetric “load” dummy structure with two resistive elements where (13)

(6)

can be used. With this “load” dummy structure, the can be found solving

matrix

Substituting (3)–(5) in (6), it is seen that the result of this method can be related to the intrinsic device -parameters as

(14)

(7) The four-port deembedding procedure outlined in [8] is far too general. One can safely assume the 4 4 parasitics matrix to be symmetrical, thus reflecting the reciprocal nature of the interconnect connecting the intrinsic device with the test-structure pads. For reciprocal interconnect, we have and . This allows us to simplify the above relation into

Compared to (11), finding the elements of is now a bit more can still be solved and complicated, but the system we can again select the correct roots by requiring the matrix to be continuous over frequency and equal to unity at low frequency. When it is known beforehand that the intrinsic device to be characterized is also symmetrical, the matrix multiplications commute, and the correction required on the “open-short” result simplifies to

(8)

(15)

where . For the usual on-wafer test structures, at low frequency, the dominant parasitics are the interconnect resistances. At these frequencies, standard “open-short” deembedding is correct and the matrix equals the unitary matrix. Once we know the four elements of the matrix , we are able to derive the intrinsic device -parameters at any frequency from the result obtained after the standard “open-short” deembedding. To find these four elements, we need two additional “left” and “right” resistive dummy structures where

were we do not need to resolve the matrix anymore. To summarize, the above refinements of the four-port parasitic theory shows that we can deembed any reciprocal parasitic four-port structure surrounding our intrinsic device by first characterizing four dummy test structures. In many practical cases, however, when both ports are drawn identical, a simplified four-port deembedding scheme can be applied. This scheme requires only three dummies, which are: 1) an “open”; 2) a “short”; and 3) either a “left,” “right,” or “load” test structure.

(9) and (10)

III. THREE-STEP PARASITIC DEEMBEDDING THEORY In the three-step deembedding approach [5], the equivalentcircuit model of Fig. 2 with nine unknown impedances is assumed for the parasitics. Using this model, the desired intrinsic

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since it incorporates nine unknown impedances, whereas the four-port scheme assumes ten unknown impedance. When we and, thus, , it is straightforward to assume show that the four 2 2 matrices of the four-port deembedding theory and the three 2 2 matrices of the three-step deembedding theory are related by

Fig. 2. Illustration of the parasitics assumed in the three-step deembedding approach. No a priori assumptions are made on the nature of these nine impedances.

device -parameters and the measured extrinsic are related as rameters

-pa(16)

where (17) (18)

(25) (26) (27) This allows us to conclude that when both ports are drawn identical, the four-port and three-step deembedding approaches are equivalent and equally accurate. Even when this is not the case, the differences will be small because asymmetric device connections will mainly affect , asymmetric probe placement will , and and are expected to be small mainly affect anyway. It could, therefore, be seen as a matter of preference whether an “open-short-load” or a “pad-open-short” procedure is used. In practice, however, the nonideality of the dummy structures and their impact on the final result needs to be considered in order to make the correct choice between these two alternatives. This will be the topic of the remainder of this paper.

(19) IV. DUMMY NONIDEALITIES For the open and short dummies, where , respectively, one obtains

and (20) (21)

is known, one can find the other It is easily seen that once and using the information protwo unknown matrices vided by the open and short dummy structures. A straightforward solution here is to add a “pad” dummy structure, which only contains the probe pads and is especially designed to dithrough rectly measure (22) and An alternative approach is to derive the ratio between from the probe pad and interconnect line dimensions and the process parameters and then use the low-frequency approximation (23) . After that, we can recover the to get a good estimate for using intrinsic device -parameters (24) We can use the same approach to correct noise-figure data taken on active DUTs by subtracting the noise correlation matrices of and from that of the DUT using the techniques described in [9]. For the general four-port deembedding scheme, this is less obvious. The three-step deembedding approach is almost as general as the reciprocal four-port deembedding scheme

In commercially available RF-probe calibration substrates, laser trimming is used to bring the resistors of the 50- load standards within a fraction of a percent of their target value, whereas the geometry is chosen such that the reactive parts coming from the inductance and self-capacitance cancel each other over a wide range of frequencies. This is clearly not feasible for the polysilicon resistors in an on-wafer “load” dummy structure. However, we may safely assume the and matrices to equal unity at low frequency, and base the final correction on the actual resistance values. “Open-short” deembedding cannot provide the reactive part of the intrinsic load impedances since it is not seen at low frequencies, whereas at high frequencies, the and matrices no longer equal the unitary matrix. The typical parasitic capacitance to the substrate of these polysilicon resistors, which can be as high as 30 fF [10] and may have a strong frequency dependence due to the substrate resistance, has to be accurately characterized and accounted for in order for the “open-short-load” deembedding scheme to produce accurate results. It is possible to minimize the parasitic capacitance of the resistors by down-scaling. However, due to design rule limitations and process uncertainties it will be difficult to know the reactive part of the intrinsic load impedances better than within a few femtofarads. At several tens of gigahertz, this may translate into significant phase errors of the eigenvalues of the and matrices, which, in turn, will adversely affect measured quality factors [11] and power gains. For the commercially available RF-probe calibration standards, “open” residual capacitance and “short” inductance are well known and accounted for in the calibration procedure. In the standard “open-short” deembedding approach, these dummy imperfections are usually neglected and absorbed in the intrinsic device. However, care

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Fig. 3. On-wafer test structure for a 0.43-nH 20-GHz high-Q single-loop inductor. The probe-pad pitch is 125 m. The inductor outer diameter and track widths are 200 and 10 m, respectively. The positions of the external ports 1 and 2 and internal ports 3 and 4 are indicated.

has to be taken that the intrinsic device is not over-corrected due to a (lossy) intrinsic open fringe capacitance or a resistance found in the short dummy, which is not present in the DUT. For a “pad” dummy structure, nonidealities seem to be less of an issue because its main purpose is to get an estimate for the ratio and . between V. MEASUREMENTS AND VERIFICATION The deembedding errors at high frequency of the standard “open-short” deembedding procedure can be seen when advanced high-speed bipolar transistors or MOSFET devices are characterized, but are most pronounced for high-quality passives [5] such as on-wafer inductors. We will, therefore, compare the “open-short-load” and “pad-open-short” deembedding procedures for the 0.43-nH 20-GHz high- single-loop inductor shown in Fig. 3. Due to its small size, this is an extremely difficult device to characterize because its intrinsic impedance is overwhelmed by the test-structure parasitics, and the parasitic crosstalk between the two ports is not negligible. This inductor originates from a set of inductor structures for which results were reported in [12], was realized in a BiCMOS process featuring a 3- m-thick top metal layer with a sheet resistivity of 10 m , and employs a ground shield made of polysilicon bars to prevent substrate loss. “Open,” “short,” and “load” dummy structures were realized in the usual way by removing the inductor, its polysilicon shield and the center tap connection. The signal pads were realized in the two top metal layers and are shielded from the substrate by a buried n layer with a sheet resistivity of 25 . The interconnect is realized in the top metal only and is shielded from the substrate by the first metal layer with a sheet resistivity of 60 m . The load resistances at the end of the interconnect lines were realized in n-type polysilicon, measure 1.9 6.6 m with heads, and 0.6 6.6 m without heads, and have a nominal resistance of 30 . After line-reflect-reflect-match (LRRM) calibration with automated load inductance extraction [13] for all structures, -parameters have been measured up to 50 GHz with a port power level of 10 dBm. To ensure identical probe placement for the DUT and the dummies, a semiautomatic test bench is used. Results for the three dummy structures are shown in Fig. 4. The characteristic impedance of the on-wafer microstrip

Fig. 4. S -parameters measured up to 50 GHz on the “open,” “short,” and “load” dummy structures. The characteristic impedance of the interconnect lines is 23 , the load resistances are 36 . The parasitic crosstalk between the two ports is acceptable, but certainly not negligible. TABLE I COMPARISON OF TEST-STRUCTURE PARASITICS CALCULATED FROM PROCESS DATA AND EXTRACTED FROM MEASURED S -PARAMETERS. THE AGREEMENT IS WITHIN THE NORMAL PROCESS VARIATIONS

lines connecting to the inductor appears to be approximately 23 . From process parameters, the pad and interconnect parasitics depicted in Table I are found, which agree well with the values extracted from -parameter data measured on the open dummy structure. In this extraction, the ratio between pad and interconnect capacitances is assumed to be the same as for the calculated capacitances. Applying “open-short” deembedding on the -parameter data measured on the “load” dummy structure, the load resistance value was found to be somewhat higher (Table I) than predicted. A considerable difference was found for the parasitic parallel capacitance of the load resistance using a standard layout extraction tool (1.1 fF) and a two-dimensional (2-D) electrostatic field solver (2.5 fF, Table I). The latter was taken as the “correct” value. Since a was “pad” structure was not available in the experiment, synthesized using the extracted parameters listed in Table I and contains the full extracted pad capacitance with its series resistance and half the extracted interconnect line capacitances. In comparing results, we restrict ourselves to the differential impedance (28) and differential (29)

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Q

Fig. 5. Inductance of the 0.43-nH single-loop inductor versus frequency. Only “open-short-load” and “pad-open-short” deembedding procedures reproduce the expected increase in inductance beyond 20 GHz when the inductor is approaching its resonance frequency.

Fig. 7. Differential factor of the 0.43-nH single-loop inductor versus frequency as obtained with “open-short-load” deembedding. The dashed lines represent a sensitivity analysis where the estimated load capacitance has been modified by and 1 fF.

Fig. 6. Resistance of the 0.43-nH single-loop inductor versus frequency. Both “open-short” and “open-short-load” deembedding produce unphysical artefacts beyond 20 GHz. “Pad-open-short” deembedding produces better results (solid line). When the 2.5-fF parallel capacitance of the load resistances is accounted for (“open-short-load C”) , similar results are obtained.

20 GHz when the inductor is approaching its resonance frequency. For the ac resistance, both “open-short” and standard “open-short-load” deembedding procedures yield unphysical artefacts beyond 20 GHz. In fact, due to the skin effect, a monotonic increase with frequency would be more in line with expectations. Here, the improvement in deembedding accuracy obtained from the standard “open-short-load” methodology over the “open-short” result is marginal. The “pad-open-short” deembedding however, produces fairly realistic results, as shown by the solid line in Fig. 6. Only when the 2.5-fF parallel capacitance of the load resistances is accounted for are similar results obtained for the “open-short-load” deembedding technique. The intrinsic load parasitic inductance has not been calculated. Including this inductance will improve the agreement between the two deembedding approaches because it partly compensates the load parasitic capacitance. Using lumped-element equivalent-circuit modeling, the dip in the series resistance observed around 30 GHz could be attributed to a fringe capacitance of the “open” dummy coupling to the lossy substrate, which is not seen in the actual inductor structure. Since the amount of energy dissipated at the end of the open dummy interconnect lines is difficult to quantify, for clarity, it was chosen not to correct for this effect.

+

Figs. 5 and 6 show the inductance and ac resisof the 0.43-nH single-loop inductor versus tance frequency. Two types of “open-short-load” deembedding are compared. In the standard version, the actual polysilicon resistance values found with “open-short” deembedding are used while the reactances are set to zero. In the improved version, the parallel capacitance of 2.5 fF calculated with the 2-D electrostatic field solver is also accounted for. It can be seen that only “open-short-load” and “pad-open-short” deembedding procedures recover the expected increase in inductance beyond

+

0

VI. SENSITIVITY ANALYSIS As shown in Section V, it is essential to accurately account for the reactive parts of the load resistances to apply the “open-short-load” deembedding scheme successfully. To obtain quantitative figures for this, a sensitivity analysis was conducted. Fig. 7 shows the factor of the 0.43-nH single-loop inductor versus frequency obtained after “open-short-load” deembedding. To see the impact of the parasitic load capacand 1 fF. itance, its estimated value has been varied by As a result of this, the peak factor is seen to vary from 40

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pacitance on the factor is small. Although the peak factor is seen to vary significantly, at 20 GHz, the variation is only from 28.4 to 27.8 and 30.5, which is per femtofarad deviation 25 times less than for the previous case. Finally, Fig. 9 gives a comparison of the factor measured on inductor versions with and without polysilicon ground shields and with and without a grounded center tap. Although grounding the center tap significantly changes the raw -parameters measured on the inductor structure, the factor derived from the differential impedance is not affected. The factor predicted by our scalable inductor compact model reported in [12] is included for reference. The overall agreement is fairly good. The remaining differences are caused by nonidealities of the “open” and “short” dummy structures. For inductors with larger inductance values and lower factor values, these minor artefacts were not seen [12]. VII. SUMMARY AND CONCLUSIONS

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Fig. 8. Differential factor of the 0.43-nH single-loop inductor versus frequency as obtained with “pad-open-short” deembedding. The dashed lines represent a sensitivity analysis where the pad-to-ground and interconnect-to-ground capacitances were enhanced/decreased by and 10 fF.

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Fig. 9. Differential factors measured on five different versions with and without a shield and with and without a grounded center tap of the 0.43-nH single-loop inductor versus frequency as obtained with “pad-open-short” deembedding.

to 30 and 60. At 20 GHz, the variation is from 24 to 21 and 27. This is quite large given the fact that, in practice, it will already be extremely difficult to know the reactive part of the load resistance within this 1 fF. Fig. 8 shows the factor of the 0.43-nH single-loop inductor versus frequency obtained after the “pad-open-short” deembedding. To see the impact of the pad capacitance, its estimated value has been varied by and 10 fF. To comply with (23), the estimated pad series resistance and interconnect capacitance values had to be varied by a similar amount in the opposite direction. Due to this compensation effect, the impact of this significant modification of the pad ca-

In this paper, we have investigated the practical benefits of adding a load dummy structure to the industry standard “open” and “short” dummy structures. We have found that the benefits of including this dummy structure are marginal unless the reactive part of its impedance is accurately accounted for. This cannot be done without any prior process knowledge and is susceptible to errors. We fear that this is also the case for the more general five-dummy scheme proposed in [8]. Almost identical results were obtained using a three-step “pad-open-short” approach, basically a simplified version of our earlier work [5], which requires only two dummy structures since the fraction of the total open dummy capacitance also seen in the pad dummy structure can easily be estimated with only modest process knowledge. A sensitivity analysis shows that the impact of errors in the estimated pad capacitance in the “pad-open-short” approach is 25 times less than the impact of errors in the estimated parasitic capacitance of the load resistance in the “open-short-load” approach. This makes the “pad-open-short” deembedding scheme an attractive alternative because the required split between external and internal capacitance generally is fairly simple to make either based on process and layout information or from measurements done on a “pad” dummy structure. Applying both deembedding approaches on the same dataset provides a powerful tool to check their validity, and that of the deembedded data. ACKNOWLEDGMENT The authors wish to acknowledge Philips Semiconductors, Hopewell Junction, NY, for providing the silicon. REFERENCES [1] P. J. van Wijnen, H. R. Claessen, and E. A. Wolsheimer, “A new straightforward calibration and correction procedure for “on-wafer” high frequency -parameter measurements (45 MHz–18 GHz),” in Proc. IEEE Bipolar/BiCMOS Circuits Technology Meeting, Sep. 1987, pp. 70–73. [2] M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, “An improved de-embedding technique for on-wafer high frequency characterization,” in Proc. IEEE Bipolar/BiCMOS Circuits Technology Meeting, Sep. 1991, pp. 188–191. [3] H. Cho and D. Burk, “A three step method for the de-embedding of high frequency -parameter measurements,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1371–1375, Jun. 1991.

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[4] E. P. Vandamme, D. M. M.-P. Schreurs, and C. van Dinther, “Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 737–742, Apr. 2001. [5] L. F. Tiemeijer and R. J. Havens, “A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high speed transistors,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 822–829, Mar. 2003. [6] T. E. Kolding, “A four-step method for de-embedding gigahertz on-wafer CMOS measurements,” IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 734–740, Apr. 2000. [7] N. L. Wang, W. J. Ho, and J. A. Higgins, “New de-embedding method for millimeter-wave bipolar transistor -parameter measurement,” Electron. Lett., vol. 27, no. 18, pp. 1611–1612, 1991. [8] Q. Liang, J. D. Cressler, G. Niu, Y. Lu, G. Freeman, D. C. Ahlgren, R. M. Malladi, K. Newton, and D. L. Harame, “A simple four-port parasitic deembedding methodology for high-frequency scattering parameter and noise characterization of SiGe HBTs,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 11, pp. 2165–2174, Nov. 2003. [9] H. Hillbrand and P. H. Russer, “An efficient method for computer aided noise analysis of linear amplifier networks,” IEEE Trans. Circuits Syst., vol. 23, no. CAS-4, pp. 235–238, Apr. 1976. [10] R. Gillon, W. Tatinian, and B. Landat, “Application of TRM self-calibration on standard silicon substrates,” in IEEE Int. Microelectronic Test Structures Conf., Apr. 2003, pp. 109–112. [11] R. J. Havens, L. F. Tiemeijer, and L. Gambus, “Impact of probe configuration and calibration techniques on quality factor determination of GHz level on-wafer inductors,” in IEEE Int. Microelectronic Test Structures Conf., Apr. 2002, pp. 19–24. [12] L. F. Tiemeijer, R. J. Havens, R. de Kort, Y. Bouttement, P. Deixler, and M. Ryczek, “Predictive spiral inductor compact model for frequency and time domain,” in IEEE Int. Electron. Devices Meeting Tech. Dig., Dec. 2003, pp. 875–878. [13] F. Purroy and L. Pradell, “New theoretical analysis of the LRRM calibration technique for vector network analyzers,” IEEE Trans. Instrum. Meas., vol. 50, no. 5, pp. 1307–1314, Oct. 2001.

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Ramon J. Havens was born in Nijmegen, The Netherlands, in 1972. He received the Bachelor’s degree from Eindhoven Polytechnic, Eindhoven, The Netherlands, in 1995. He then joined Philips Research Laboratories, Eindhoven, The Netherlands. His current field of research concerns on-wafer RF characterization of the various active and passive devices found in advanced integrated-circuit processes.

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Luuk F. Tiemeijer was born in Son en Breugel, The Netherlands, in 1961. He received the M.S. degree in experimental physics from the State University of Utrecht, Utrecht, The Netherlands, in 1986, and the Ph.D. degree in electronics from the Technical University of Delft, Delft, The Netherlands, in 1992. In 1986, he joined Philips Research Laboratories, Eindhoven, The Netherlands, where he has conducted research on InGaAsP semiconductor lasers and optical amplifiers. Since 1996, he has been involved in the RF characterization and modeling of advanced integrated-circuit processes.

André B. M. Jansman was born in Raalte, The Netherlands, in 1971. He received the M.S. degree in applied physics and Ph.D. degree from the University of Twente, Twente, The Netherlands, in 1995 and 1999, respectively. His doctoral research concerned high-temperature superconducting thin-film devices. In 2000, he joined Philips Research Laboratories, Eindhoven, The Netherlands, where he is involved with thin-film technologies for the realization of high- RF passives. He specializes in characterization and simulation and design of RF and microwave

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components.

Yann Bouttement was born in Berlin, Germany, in 1976. He received the Engineer’s degree from the École Polytechnique Universitaire de Lille (EUDIL), Lille, France, in 2000. In 2001, he joined Philips Semiconductor Caen, Caen, France, where he is currently involved with the characterization and modeling of RF integrated-circuit (RFIC) processes.

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Analysis and Characterization of PLL-Based Retrodirective Array Vincent Fusco, Fellow, IEEE, Chee Binn Soo, and Neil Buchanan, Member, IEEE

Abstract—In this paper, we present a new phase-locked loop (PLL) architecture that is capable of providing phase conjugation as required for retrodirective array action. An analysis is performed on the architecture, which shows that the presence of nonlinear mixing products gives rise to an additional and substantially larger rms noise-induced phase-error component than is suggested by analysis based on ideal mixer properties. In addition, the analysis allows us to quantify the effect that a Doppler shifted signal has on phase-conjugation error. For the purpose of demonstration, we have constructed and characterized a six-element array operating using commercially available components at 1 GHz. Near-perfect retrodirective action is presented over a 360 azimuth sweep, with 16-dB array gain. Due to the inherent isolation between input and output signals, and programmable retransmit frequency, the PLL approach introduced in this paper offers considerable practical advantage when used within retrodirective antenna arrays, as compared to the classical mixer-based approach where mixer losses and RF-to-IF frequency isolation are major issues. Index Terms—Phase jitter, phase-locked loop (PLL), retrodirective array.

I. INTRODUCTION

P

HASE conjugation is a known technique for producing retrodirective arrays [1]. Recently, there has been considerable research into these structures for short-range communications up to 66 GHz [2]–[5]. The classical approach to achieve the phase conjugation necessary for these antennas is to use a mixer arrangement [1], [2]. Here, the received signal is mixed with a local oscillator, running at twice, or, approximately twice the RF frequency, such that a lower sideband at, or approximately at, the RF frequency has its phase conjugated. Consequently each of the wavefronts comprising the retransmitted signal have their individual phases conjugated. Therefore, the retransmitted signal returns along the same path along which it was incident. The mixer approach has several disadvantages, including high conversion loss, unwanted mixing products, low retransmitted power, and the inability to correct any phase errors caused by component/fabrication variations. In order for retrodirective action to occur, each receiving antenna element in a retrodirective array is connected to a phase-conjugating unit before it is delivered to the transmitting array.

Manuscript received March 18, 2004. This work was supported by TDK Electronics Ireland and by the U.K. Engineering and Physical Research Council under Grant GR/R54996/01 and Grant GR/R15139/01. The authors are with the High Frequency Electronics Laboratories, School of Electrical and Electronic Engineering, Queens University Belfast, Belfast BT9 5AH, Ireland (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840620

Fig. 1. PCLL.

Previously, phase-locked loops (PLLs) have been used in antenna systems as phase shifters [6] or as oscillation stabilization devices [7] (neither application required that signal phase be conjugated). In this paper, a novel PLL system, referred to here as the phase-conjugating locked loop (PCLL) is introduced in order to accomplish the phase-conjugation function in a manner that is superior, in terms of conversion efficiency, RF-to-IF isolation, than the best passive mixing arrangements previously reported [8]. In addition, the PCLL approach can support a programmable frequency offset between received and retransmitted signals; this feature is necessary for full duplex retrodirective communication [9]. The use of the PCLL approach suggested in this paper should make the implementation of high-performance retrodirective (self-tracking) antenna arrays in applications such as automatic beam steering for vehicular telemetry [10] RF identification [11], communication with unstablized microsatellites [12] more practically accessible. II. THEORY OF OPERATION The PCLL is depicted in Fig. 1 (here, the RF input signal and the voltage-controlled oscillator (VCO) signal are combined by using an up-converting mixer in order to preserve the correct phase relationship required to phase conjugate the VCO signal). This arrangement allows an arbitrary incoming signal to have its phase conjugated and retransmitted at a different frequency . This phasing methodology has the benefit of producing a phase-conjugated signal , which is isolated from the incoming RF signal and whose frequency can be selected under loop divider control to provide a retransmitted signal, which is suitable for full duplex communication. A bandpass filter with 1.99-GHz center frequency, 3.34-dB insertion loss, and 10-dB cutoff frequencies of 1.854 and 2.077 GHz was inserted after the up-converting mixer in order to remove as many of the unwanted mixing products as possible since these may adversely affect subsequent phase detector operation.

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In Appendix I, with reference to Fig. 1, we derive the VCO in terms of RF input phase-conjugated output equation including the presence of noise and the efsignal phase fects of nonlinear up-conversion mixer products

where is the damping ratio of the PLL system and is the natural frequency of the PLL system. If we compare the denom, the parameters and inator of (2) with can be determined as

(1)

(4)

Equation (1), whose parameters are defined in Appendix I, gives the time-domain phase response for the PCLL architecture shown in Fig. 1. For the purpose of simulation, the parameters required for (1) were obtained experimentally and are listed in Appendix IV. Consider in (1) if the system were noiseless, , and if , then and perfect phase conjugation would occur.

(5) By enforcing the condition normally associated with a PLL that must be greater than the lock range the pull-out range , the following relationship can be established for the PLL under consideration here with the physical parameters given in Appendix IV:

III. PCLL STEP RESPONSE By obtaining the step response of the PCLL, we can ascertain information about its response time to digitally modulated phase , as it is defining the encoded signals. Assuming that reference phase for the other phases, then the transfer function for Fig. 1 is derived in the normal manner using the signal flow analysis procedure in [13], and with as an and obtain the arbitrary constant, we can write step response of the system, as shown in (2) at the bottom of this , we get page. By applying a Laplace transform pair [13] to

(3)

For our practical PCLL with gain set to unity, we can determine the minimum permissible value for the main divider ratio

hence, must be greater than 134. The reason for examining the limit of main divider ratio is due to the programmable characteristic inherent in the PLL chip, a UMA 1021M low-voltage frequency synthesizer [14], of 50. which has a minimum value for for the PCLL can be apThe approximate locking time proximated after [13] as

where s

(6)

First, we find the limit for required in order for the system to function properly, i.e., to avoid imaginary values for (7) from which the limit of the gain The pull-out range and the lock range for a secondorder PLL system, i.e., the same order as in (2), are after [13]

can be calculated as (8)

Thus, from (6), for all permissible main divider settings (9950–1592), the locking time is 39 s. This means that with the present practical settings (Appendix IV), the PCLL could

(2)

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conjugate incoming signals that have up to approximately 25-kHz variation superimposed. Following the procedure in [13], the loop gain for the PCLL is written as

TABLE I NOISE-INDUCED PHASE-CONJUGATION ERROR

(9) With the loop configured for maximum allowable gain, the gain margin for all divider ratios is infinite and its phase margin is 90 . IV. EFFECT OF DOPPLER SHIFT Consider now the situation where a signaling target is moving relative to the retrodirective array with a sinusoidal displacement inducing a Doppler shift

Consequently, using (1) with additional noise terms removed for simplicity,

(10) From which the phase-conjugation error associated with the Doppler shifted signal can be found. For example, if we wish the maximum phase-conjugation error to be restricted to 1 and 5 , respectively, and we permit the input phase variation to range from 180 to 180 , then with the current PCLL components (Appendix IV), the highest Doppler frequencies the PCLL would react to are 155 and 755 Hz, respectively. At frequencies above these, the PCLL is too slow to be sensitive to phase-modulation variation. In practice, the low-pass loop filter cutoff response, assumed in the above analysis to be constant, will act to allow Doppler or deliberately encoded carrier phase information to be stripped from the VCO error signal at the point of entry to the loop filter. For the practical PCLL considered here, the cutoff frequency was 5 Hz, and we successfully removed binary phase-shift keying (BPSK) encoded signal bit rates of up to 500 kb/s without affecting the much slower varying angle of arrival phase-conjugation performance of the loop. V. PCLL NOISE ANALYSIS We now compute the rms value associated with each noise integral using the equations derived in Appendices II and III. Table I illustrates the noise-induced phase-conjugation error as with set equal to unity. a function of main divider ratio From these results, it can be seen that the term is adding most of the additional rms phase-noise error to the conjugated signal. When the gain of the loop is increased to its maximum reduces permissible value, then for each value of to 0.4 , while remains of the order of 10 . When

Fig. 2.

PCLL retrodirective antenna array. (a) Physical layout. (b) Photograph.

mapped through the ideal beam-steering equation for , spacing the values in Table I give rise to maximum 2 beam offset. Consequently, they are low enough to be of little concern in terms of overall beam point accuracy. VI. PCLL RETRODIRECTIVE ANTENNA ARRAY The practical PCLL-based retrodirective antenna array uses a linear arrangement of commercial cellular mobile wireless

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Fig. 3. PCLL retrodirective array test setup. (a) PLL circuit configuration. (b) Array measurement setup.

monopole antennas; these, as well as commercial PLL components, were selected for the proof of concept demonstrator in order to facilitate module repeatability. For this reason, the prototype presented here operates at approximately 1 GHz. The physical layout for the array is shown in Fig. 2; the upper set of antennas are used for reception, while the lower set are used for signal retransmission. Each PCLL circuit was housed in a screened enclosure to significantly reduce cross-coupling effects. In addition, the retransmit path was fitted with an amplifier block having 10-dB gain and 30-dB reverse isolation. This amount of reverse isolation was necessary in order to prevent adjacent PCLL VCOs from frequency pulling each other upon signal retransmission. The cellular monopole antennas,1 produce a return loss of 10.9 dB at 1 GHz, and a coupling, for 120 mm element spacing, between adjacent elements of 15 dB. The ripple on each antenna is approximately 2 dB when measured in isolation over the ground plane specified in Fig. 2. A Philips UMA1021 1Panorama Antennas, Frogmore, London, U.K., model number: AFCQB cellular whip antenna. [Online]. Available: http://www.panorama.co.uk

PLL chip was used as the primary building block in the study reported here [14], the VCO was a Mini-Circuits POS-1025, and the up-converting mixer was an HP 81008 Gilbert cell mixer. The frequency of the output retransmit signal is selected by the main divider ratio. The actual PCLL configuration is shown as Fig. 3. Also shown in Fig. 3 is the monostatic radar cross section (RCS) measurement setup used to quantify the operation of the retrodirective PCLL array. Due to equipment limitations in our laboratory, we are unable to measure the bi-static RCS response. To verify the operation of each of the PCLL phase-conjugating modules, all six PLL modules were tested by varying the 1.05-GHz input signal phase using an adjustable delay line and measuring the PCLL output phase at the VCO output by means of a Tektronix TDS784D high-frequency oscilloscope. The results presented in Fig. 4 show that phase conjugation is occurring with a worst case phase-conjugation error of 15 . The PCLL was tested in a six-element retrodirective array (four is the minimum needed for useful retrodirective beam formation) [15]. Referring to the antenna layout of Fig. 1(a), the

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unaffected. Theoretical prediction of the retrodirective far-field response is based on the active element pattern approach [16]. These predictions agree well with the measured response (see Fig. 5). VII. CONCLUSION

Fig. 4.

PCLL module measured phase responses for six circuits.

Analysis has been successfully carried out on a novel phase-conjugating PLL-based circuit architecture and experimental characterization of a practical six-element retrodirective antenna array has been performed. The results of the analysis show that the PCLL can accommodate signals that have been Doppler shifted, and that nonlinear mixing gives rise to rms phase-noise error of the order of several degrees—a value low enough to be of little concern in terms of overall beam point accuracy. The PCLL when used in the six-element retrodirective array results in full 360 azimuth scan with 16-dB array gain achieved at both transmit and receive. The PCLL arrangement suggested in this paper would permit a commercially viable way to construct low-cost automatic full-duplex self-tracking transponders. The versatility offered by the strategies outlined in this paper should find considerable potential for deployment in a wide range of mobile wireless personal communications devices where reduction of effective isotropic radiated power (EIRP) and multipath effects are important. Other applications include asset tracking, radar transponder, satellite, and highaltitude platform stabilization. APPENDIX I PCLL LOOP EQUATIONS

Fig. 5. Normalized monostatic retrodirective array response.

upper set of monopoles was used for 940-MHz transmission, while the lower set was used for 1.05-GHz reception. Initially, the array far-field pattern was aligned to boresight. This was done as follows: the VCO for each element was powered ON in turn, while the others were powered OFF, and the retransmitted phases tuned to be equal via a dc offset [see Fig. 3(a)] applied to the VCO. This procedure was followed in order to remove the effects resulting from nonidentical phases from component/fabrication variations. All VCOs were then powered ON and the monostatic radar cross-sectional retrodirective pattern measured. The normalized monostatic radiation pattern, which represents the locus of the peak response of the six-element array, is shown in Fig. 5. This shows a variation of less than 3 dB across most of the array’s azimuthal 360 coverage. The ripple that is present is, at worst, 1 dB higher than the pattern ripple we measured for an isolated individual element. It should be remembered that while providing near omnidirectional retrodirective coverage, the measured gain of the array, upon receive and retransmit, was 16 dB with respect to a single monopole. In view of these responses, it is thought that, on average, the phase-conjugation errors produced by each PCLL module are self-compensating across the array so that final beam formation is largely

Using Fig. 1 as a reference and following the analytical approach in [18], let the received voltage at the th antenna element be expressed as (1.1) is the amplitude of the received signal at the th anwhere tenna, is the angular frequency of the transmitted signal, is the relative phase angle of the received signal, is the is the noise phase noise received by the th antenna, and angle. The signal output of the VCO is (1.2) is the amplitude of VCO output voltage, is a conwhere is the phase of the VCO. stant angular frequency, and The up-converting mixer is a nonlinear component, which causes intermodulation frequencies of the input signals to be generated, and is represented by the power series (1.3) is the incoming signal voltage across the th up-conwhere verting mixer. and produce the excitation signal, which The inputs is then applied to the mixer transfer function [see (1.3)]. After

FUSCO et al.: ANALYSIS AND CHARACTERIZATION OF PLL-BASED RETRODIRECTIVE ARRAY

mixing, the up-converted (doubled) products are fed to the bandpass filter. These are then divided by the main divider whose diand , respectively, thus vision ratio and gain are

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is the angular frequency of the reference oscillator signal. At in Fig. 1 is lock at the output of the phase detector, gain (1.6) Thus,

(1.4) where

(1.7) Following the process of phase detection, signal will be filtered by the low-pass loop filter leaving only dc components; and coefficients with thus, after reinserting the , where is the low-pass filter gain, assumed here to be constant. as We write

and are shown without explicit time dependence included. is If the signal from the stable reference stable oscillator gain, is divided by a second divider with division ratio then (1.5) where is the amplitude of the reference oscillator signal, is the relative phase angle of the reference oscillator signal, and

(1.8) where

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To a first-order approximation, the input noise is narrowband having passed through the bandpass filter shown in Fig. 1. and It is also not correlated to so, for the parts of (1.8) associated with noise, we replace and with their rms value

From this result, we define the phase-noise error components to be (1.14)

As a result, (1.8) becomes

(1.15)

We can also write (1.9) The criterion for VCO behavior in the th PLL assembly is such that its output frequency is proportional to the error voltage. will be Therefore, using (1.9), the VCO output frequency

where

(1.10) Hence, is the frequency in the absence of the error signal and where is the slope of the frequency versus the error-voltage graph for the VCO. , and asWhen lock is about to be acquired, suming small static phase error, then , and thus we can reduce (1.10) to a linear differential equation

Whereupon

(1.16) (1.11) and . If we assume , since it is defined as the reference phase for all of the and , then we other phases, and let can rewrite (1.11) as where

APPENDIX II PCLL NOISE ANALYSIS PCLL noise analysis commences with an examination of [17], [18] of the noise signal the autocorrelation function received by the th antenna, namely,

(1.12) should decay to zero at the steady-state locked condiSince . Subsequently, tion, its form is assumed to be (1.2) can be written as

with , as defined in Appendix I. The power spectral density for this signal is (2.1)

(1.13) Now the thermal noise , the main source of noise entering the system with noise equivalent bandwidth , and effective is noise temperature

Thus,

(2.2) and if the PLL loop of this system is categorized as a secondorder loop, then its bandwidth can be estimated after as [13]

where

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FUSCO et al.: ANALYSIS AND CHARACTERIZATION OF PLL-BASED RETRODIRECTIVE ARRAY

can be found from (4) and (5) respectively. We now need to compute . To do this, first examine the average noise signal power

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TABLE II PCLL EXPERIMENTAL PARAMETERS

(2.3) goes to and at , 99.74% As of the average noise power is accounted for. Thus, . Hence, (2.4)

where . The rms phase-noise equations components (2.4) and (2.5) are now restated as follows: (2.5)

(2.6) Thus, since represents the phase noise generated by the PCLL Here, is the result of higher direct (ideal) multiplier action, while order intermodulation mixing terms falling into the passband of the bandpass filter. Equation (2.6) is expanded to give then at steady-state noise, (3.1) becomes (3.2)

(2.7)

With the aid of (3.2), , and the rms expression of the noise components in (3.2) become [17] of

APPENDIX III RMS NOISE QUANTITIES

(3.3)

The rms of the noise signal can be written as of

(3.4)

APPENDIX IV PCLL EXPERIMENTAL PARAMETERS

but

Table II presents PCLL experimental parameters. APPENDIX V PERMISSIBLE PCLL DIVIDER RATIOS

(3.1)

Table III depicts the possible ratios that could be implemented so that the condition in (6) is adhered to and when 940 GHz is the receive frequency with 1.05 GHz as the retransmit frequency.

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TABLE III PERMISSIBLE PCLL DIVIDER RATIOS

ACKNOWLEDGMENT The work described in this paper is currently undergoing patent protection British Patent Application no. 0 322 538.0, PLL Phase Conjugation, 26 September 2003. REFERENCES [1] C. Y. Pon, “Retrodirective array using the heterodyne technique,” IEEE Trans. Antennas Propag., vol. AP-12, no. 11, pp. 176–180, Nov. 1964. [2] S. L. Karode and V. F. Fusco, “Frequency offset retrodirective antenna array,” Electron. Lett., pp. 1350–1351, Jul. 1997. [3] L. D. DiDomenico and G. M. Rebeiz, “Digital communications using self-phased arrays,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, Jun. 2000, pp. 1705–1708. [4] R. Y. Miyamoto, Y. Qian, and T. Itoh, “An active integrated retrodirective transponder for remote information retrieval,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, Jun. 2000, pp. 1431–1434. [5] N. B. Buchanan, T. Brabetz, and V. F. Fusco, “A 62/66 GHz frequency offset retrodirective array,” in IEEE MTT-S Int. Microwave Symp. Dig., Seattle, WA, Jun. 2–7, 2002, pp. 315–319. [6] N. B. Buchanan and V. F. Fusco, “Triple mode PLL antenna design,” in IEEE MTT-S Int. Microwave Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 1691–1694. [7] J. W. Andrews and P. S. Hall, “Oscillator stability and phase noise reduction in phase locked active microstrip patch,” Electron. Lett., vol. 34, no. 9, pp. 201–206, Apr. 1998. [8] T. Brabetz, V. F. Fusco, and S. Karode, “Balanced subharmonic mixers for retrodirective array applications,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 3, pp. 465–469, Mar. 2001. [9] S. Karode and V. F. Fusco, “Self tracking duplex communication link using planar retrodirective antennas,” IEEE Trans. Antennas Propag., vol. 47, no. 6, pp. 993–1000, Jun. 1999. [10] V. F. Fusco, “Retrodirective arrays used for ACC vehicular augmentation,” in IEE Antennas for Automotive Radar Colloq. Dig., 2000/02, London, U.K., Mar. 2000, pp. 6/1–6/5. [11] R. Y. Miyamoto, G. S. Shiroma, B. T. Murakami, and W. A. Shiroma, “A high directivity transponder using self-steered arrays,” in IEEE MTT-S Int. Microwave Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 1683–1686. [12] C. T. Rodenbeck, M. Li, and K. Chang, “A phased array architecture for retrodirective microwave power transmission from space solar power satellite,” in IEEE MTT-S Int. Microwave Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 1679–1682. [13] E. Best, Phase Locked Loop: Designs, Simulations and Application, 3rd ed. New York: McGraw-Hill, 1965.

[14] “Low voltage frequency synthesizer,” Philips, Eindhoven, The Netherlands, Applicat. Note UMA1021M, AN96083, Aug. 1996. [15] B. Y. Toh, V. F. Fusco, and N. Buchanan, “Assessment of performance limitations of non-retrodirective arrays,” IEEE Trans. Antennas Propag., vol. 50, no. 10, pp. 1425–1432, Oct. 2002. [16] B. Y. Toh, V. F. Fusco, and N. B. Buchanan, “Retrodirective array tracking prediction using active element characterization,” Electron. Lett., vol. 37, no. 12, pp. 727–728, Jun. 2001. [17] P. Panther, Modulation, Noise and Spectral Analysis. New York: McGraw-Hill, 1965. [18] R. N. Goose, “Electronically adaptive antenna systems,” IEEE Trans. Antennas Propag., vol. AP-12, no. 2, pp. 161–169, Mar. 1964.

Vincent Fusco (S’82–M’82–SM’96–F’04) received the B.S. degree in electrical and electronic engineering (with first-class honors), Ph.D. degree in microwave electronics, and D.Sc. degree in advanced front end architectures with enhanced functionality from the Queens University of Belfast (QUB), Belfast, Ireland, in 1979, 1982, and 2000, respectively. In 1995, he was appointed to a personal chair in High Frequency Electronic Engineering with the QUB. He is Head of the High Frequency Laboratories, QUB, and is Director of the International Centre for Research for System on Chip and Advanced Microwireless Integration. He has authored or coauthored 300 scientific papers in major journals and in referred international conferences. He has contributed invited chapters to several books in the field of active antenna design and EM field computation. He holds several patents. His research interests include nonlinear microwave circuit design, and active and passive antenna techniques. The main focus for his research is in the area of wireless communications. Prof. Fusco is a Fellow of the Institute of Electrical Engineers (IEE), U.K. since 1996. He was the recipient of the 1986 British Telecommunications Fellowship and the 1997 Northern Ireland (NI) Engineering Federation Trophy for outstanding industrially relevant research.

Chee Binn Soo received the B.Eng. degree (with first-class honors) from the Queens University of Belfast, Belfast, Ireland, in 2002, and is currently working toward the Ph.D. degree at Queens University of Belfast. He is currently a member of the High Frequency Electronics Group, Queens University of Belfast. His research interest concerns PLL-based active antenna arrays.

Neil Buchanan (M’00) received the B.Eng. degree (with honors) and Ph.D. degree from the Queens University of Belfast, Belfast, Ireland, in 1993 and 2000, respectively. His doctoral dissertation was entitled “Phase-Locked Millimeter-Wave HEMT Oscillators.” He is currently a Senior Engineer with the High Frequency Electronics Group, Queens University of Belfast. His research interests include millimeter-wave monolithic-microwave integrated-circuit (MMIC) design, millimeter-wave oscillators, and self-steered antenna arrays.

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Power Level-Dependent Dual-Operating Mode LDMOS Power Amplifier for CDMA Wireless Base-Station Applications Younkyu Chung, Member, IEEE, Jinseong Jeong, Yuanxun Wang, Member, IEEE, Dal Ahn, Senior Member, IEEE, and Tatsuo Itoh, Fellow, IEEE

Abstract—The design and analysis of a dual-operating mode laterally diffused metal–oxide semiconductor (LDMOS) power amplifier for code-division multiple-access wireless communication base-station applications is presented in this paper. The amplifier structure consists of four parallelly located single-stage LDMOS amplifier array, the dual-mode input power divider, and output power combiner. In this dual-mode operation, the number of operating power amplifier (either one or four amplifiers) is controlled depending on the required power level. This results in significant improvement in efficiency performance of the amplifier by minimizing unnecessary dc power consumption. In addition to the enhancement of efficiency, the amplifier design approach also provides better overall linearity performance. The proposed dual-operating mode design technique was successfully demonstrated by designing, implementing, and testing an LDMOS power amplifier with Motorola MRF 21030 in this study. Index Terms—Adjacent channel leakage power ratio (ACLR), characteristic impedance, code division multiple access (CDMA), coupled-line coupler, laterally diffused metal–oxide semiconductor (LDMOS), power-added efficiency (PAE), power amplifier.

I. INTRODUCTION

T

HE THIRD-GENERATION (3G) mobile communications systems require high-capacity networks that can handle bandwidth-intensive applications such as video, data, and image transmissions. Spread-spectrum modulation formats such as wide-band code division multiple access (W-CDMA) have become the leading 3G wireless standards [1]. This is essentially because the code division multiple access (CDMA)/W-CDMA modulation scheme enables multiple users to simultaneously access a shared communication channel by means of spreading the information signal from the users with a unique spreading waveform assigned to each user [1]–[3]. Since the CDMA/W-CDMA signal has a high peak-to-average ratio, however, CDMA/W-CDMA-type power amplifiers have to operate with a large amount of backoff from the output power compression point of the amplifier to avoid distortion of the

Manuscript received March 17, 2004; revised June 1, 2004. This work was supported by UC MICRO under Contract 02-029. Y. Chung was with the Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA 90095 USA. He is now with the Center for the Physics of Information, California Institute of Technology, Pasadena, CA 90095 USA (e-mail: [email protected]). J. Jeong, Y. Wang, and T. Itoh are with the Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA 90095 USA. D. Ahn is with the Division of Information Technology Engineering, Soonchunhyang University, Choongnam 336-745, Korea. Digital Object Identifier 10.1109/TMTT.2004.841220

signal waveform by clipping the peak of the signal. This results in lowering the efficiency of amplifier in CDMA-type signal applications. In such an application with variable output power, which is required by the CDMA/W-CDMA system, enhancing the efficiency of the power amplifier is one of the main system performance issues. Highly efficient power amplifiers in base stations not only provide better circuit performance, but also allow less cooling requirement and better thermal management. Several efficiency enhancing techniques, which are not limited to the base-station applications, were invented in the early era and have been widely used: the Doherty amplifier and the envelope elimination and restoration (EER) technique, often called the Kahn technique [4]–[6]. In addition to utilization of these design techniques, the dual-path and other design approaches have been proposed for high-efficiency amplifiers [7], [8]. In [7], a dual-path power amplifier scheme was investigated to minimize dc power consumption. Two different size GaAs high electron-mobility transistors (HEMTs) were integrated with path-control switches. Depending upon the input power level, a desirable HEMT in terms of a size was selected by the path-control switches. Recent research done at the University of California at Los Angeles (UCLA) reported a new power-combining technique [8]. Under the condition that the output power was dynamically changing, the number of operating amplifiers was determined. The combiner satisfied all output matching conditions at different operating states. Silicon laterally diffused metal–oxide semiconductor (LDMOS) has often been used for modern wireless communication base-station RF power amplifiers. This is because of the simplicity, mature device technology, and excellent RF performance such as high gain, good linearity, and high output power of the LDMOS transistor [9], [10]. In this paper, a new design approach for a highly efficient high power-amplifier system for CDMA base-station applications is introduced and investigated. This amplifier scheme is accomplished by developing and employing the dual-mode input power-dividing and power-combining schemes. The proposed schemes deliver source power and combine the output power from an array of amplifiers with the number of amplifiers in use being selected depending upon the required power level. The technical challenge for such a system is to realize the input power divider and output power combiner with the impedance matched at two different operating modes in order to avoid extra distortion introduced by gain and phase changes. The details on the proposed input power-dividing and power-combining

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Fig. 2. Alternative switching scheme using a coupled line coupler.

Fig. 1. Circuit diagram of the proposed dual-operating mode LDMOS power amplifier.

schemes are presented in Section II. The circuit design and fabrication of the LDMOS power amplifier is described in Section III and is followed by experimental results. II. CIRCUIT OVERVIEW Fig. 1 shows the circuit diagram of the proposed dual-operating mode LDMOS power amplifier. It consists of a proposed dual-mode input power divider, four LDMOS power amplifier arrays, a dual-mode output power combiner, and a digital circuit portion. The digital circuitry, which is composed of an envelope detector incorporated with a diode and comparator, generates digital signals to control the operating states of the input power and the bias voltage of the LDMOS power amplidivider . is applied to the switches in the dual-mode fiers power divider, while the gate voltages of the LDMOS amplifiers to provide the dual-mode operation. are controlled by In this dual-mode operation, the circuit has two different or four operating states, either one operating amplifier operating amplifiers , depending upon the required is consignal level. When the input signal level is low, ducting, while all others are not activated. In this operating mode, denoted as a low-input power mode, all of the input through the proposed power is exclusively delivered to the dual-mode input power divider. Likewise, the output power is led to the final output load through from the single the dual-mode combiner. On the other hand, for the required higher signal level, the divider and combiner structures are switched to their higher operating modes. In this high-input power mode, all four parallel amplifiers are active. Input power is evenly divided into four branches and the power from the through is combined and delivered amplifiers from to the output load. In this dual-mode operation, which controls the number of operating amplifiers with respect to the required power level, the overall efficiency as well as the linearity of the amplifier configuration can be improved at the same time.

in Section I, the path-control switch selected a proper HEMT device in [7]. Series switches were used to choose the activated branches at the input side in [8]. In spite of their good performance, however, the method to use control switches placed on the RF signal line generally makes the circuit complicated due to the necessary dc bias circuitry for the switches, and it also has some effect on the RF signal. In addition, the position of the switch in the circuit is sensitive not only to the performance of the input-dividing circuit part, but also the overall performance of the amplifier. This is because the finite isolation performance between the input and output terminals of a switch causes a loading effect from the circuit connected to the output of the switch. In other words, the input impedance of the switch is not constant, regardless of the operating condition of the next circuit stage to the switch. To solve these problems, an alternative switching scheme is demonstrated in this study by utilizing a coupled-line coupler with mode-control switches [11]. The switching scheme is illustrated in Fig. 2. A switch is connected to the coupling terminal of the coupler, while the isolation terminal remains an OPEN circuit. The RF signal propagates through the input and thru terminals. Note that and the coupler is designed to have the desired even-mode odd-mode characteristic impedances. The operating condition of the circuit is determined by the mode-control switch connected to the coupling terminal. When the switch is OFF, both the coupling and the isolation terminals become OPEN circuits. The coupler in this operating condition operates as an ordinary transmission line [12]–[14]. is The characteristic impedance of the transmission line given by (1) On the other hand, when the coupling terminal becomes ON, the coupler is not acting as a conventional transmission line. In Fig. 3, the equivalent circuit of the coupler in this operating condition is illustrated [12]–[14]. It is composed of one section of transmission line and another short-circuited stub. The characteristic impedances of both transmission lines and are expressed as follows [12]–[14]:

A. Dual-Mode Input Power Divider Series switches on the RF signal path have been simply utilized to select proper branches in circuit configurations providing different operating states [7], [8]. As briefly described

(2) (3)

CHUNG et al.: POWER LEVEL-DEPENDENT DUAL-OPERATING MODE LDMOS POWER AMPLIFIER

Fig. 3. Equivalent circuit of the switching scheme (control switch: ON).

Fig. 4.

Schematic of the dual-mode input power divider.

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or the isolation terminal, while the corresponding isolation or coupling terminal of each coupler remains OPEN. The same operating principle of the switching scheme can be used to describe the operation of this divider. When the coupler behaves as an ordinary transmission line, the characteristic , 70.7 from the given impedance of the line becomes even- and odd-mode characteristic impedance. In this mode, the source power is evenly divided into four branches, which implies that this divider acts as a 6-dB equal input power divider. The Wilkinson power-divider-like configuration satisfies all input matching conditions. On the other hand, when mode to are turned ON, while still recontrol switches from mains OPEN, the input impedances at reference points “A” and “B” in Fig. 4 become OPEN because of the operating principle of the couplers described before. It makes all input exclusively direct into port 1. In this operating mode, the divider ideally works as a 0-dB loss signal path. The matching condition is satisfied transmission line and by an ordinary quarter-wavelength another line formed by the coupler with . The power divider was implemented on the 0.787-mm-thick RT/Duroid with a dielectric constant of 2.33. The photograph of the fabricated divider is shown in Fig. 9 as an input part of the assembled dual-operating mode LDMOS power amplifier. From the measured return- and insertion-loss characteristics of the dividing circuit, the input power is equally divided into each branch with 6-dB power division when four branches are conducting. The input matching was also well accomplished over the designed frequency range. However, a 1.6-dB insertion loss was measured when one branch was conducting. This is due to the finite ON resistance, approximately 4–5 , of the mode-control switches. From Agilent’s ADS simulation, the insertion loss can be significantly improved as the ON state resistance of the switch approaches 1–2 . B. Dual-Mode Output Power Combiner

Note that the electrical length of the both transmission lines in Fig. 3 is a quarter-wave length at a target frequency of 2.12 GHz for designing the dual-mode input power divider and amplifier. As shown in the Fig. 3, the input impedance at the input port becomes low (SHORT) since it is 180 away from the short-circuited stub at the 2.12-GHz frequency. Meantime, the output impedance at the thru port becomes a high impedance point (OPEN). By making the coupling terminal in Fig. 3 connected to the ground (GND), the realization of the SHORT at the input and the OPEN at the thru port can easily be accomplished, regardless of the next stage of this alternative switch. As a result, the switching scheme has two different operating states, as described above, depending upon the condition of the mode-control switch connected to the coupling terminal. The coupler used in this study was fabricated using the lowtemperature cofired ceramic (LTCC) technology in practice and and of the coupler are 120.2 and 20.6 , respectively. Fig. 4 shows the schematic of the proposed dual-mode input power divider using the switching scheme with the coupler and transmission lines [11]. Four control switches and two quarter-wavelength transmission lines are used in this divider. As shown, mode-control to are connected to either the coupling switches from

When a field-effect transistor (FET) is biased to the deep pinchoff region, its output impedance is nearly reactive with a small fraction of resistive value [15], [16]. The essential idea of the dual-mode combiner is realized by using this fact in such a way that there is a large impedance difference when the FET is biased to a class-AB or deep pinchoff region. Fig. 5 shows the proposed dual-mode output power combiner with four power amplifiers. Similar to the described dual-mode input power divider in Section II-A, this output power combiner also has two different operating modes. In Fig. 5, the operating principle in the low-input power mode is conducting, while the other FETs are biis illustrated. ased to their pinchoff region. As explained above, the output impedance of the FET becomes nearly reactive when the FET is biased to its pinchoff. By means of adding a proper length offset line at the output of the FET, the impedance point can easily transferred to a high-impedance value at the output of the each amplifier. Reference points “C” and “D” become highis able to deliver the output impedance points. As a result, power to the output 50- load with minimum influence from the loading of the other three amplifiers. Two quarter-wavelength transmission lines on the top branch satisfy the output matching condition.

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Fig. 6. Fabricated single-stage LDMOS power amplifier.

Fig. 5. Schematic of the dual-mode output power combiner (low-input power mode).

On the other hand, all amplifiers from to are turned on in the high-input power mode. Four amplifiers evenly deliver the output power to the final load through the proposed power combiner. Notice that there are additional 50- quarterwavelength transmission lines at the input sides of the third and fourth branches. These lines are added in order to equate the phase for all working branches since there are more transmission-line components in the first and second branches. Overall, the Wilkinson power-combiner-like configuration meets the requirements for the output matching condition. The proposed output combiner designed at the center frequency of 2.12 GHz was fabricated on a substrate with the same parameters as the input divider. Note that the measurement of this combiner clearly showed that the all input signals are led to the output port when the combining scheme was in the low-input power mode. III. DESIGN AND EXPERIMENTAL RESULTS OF DUAL-OPERATING MODE LDMOS POWER AMPLIFIER A. Reference Single-Stage LDMOS Power Amplifier For testing the dual-mode operation of the LDMOS power amplifier structure, a single-stage LDMOS power amplifier was first designed. The Motorola MRF 21030 LDMOS and its thermal model1 in Agilent’s Advanced Design System (ADS) were used for the circuit design. The harmonic balance and -parameter simulators were utilized for the detailed simulation. The bias condition of the LDMOS amplifier was set to class-AB operation for the normal operation of the biased was equal to 28 V and the transistor. The drain voltage was 3.75 V. However, when the device was gate voltage not activated, was set to 0 V, while keeping the same bias voltage for the drain electrode. This bias condition provides a large difference of output impedance compared to the normal operation case for the dual-mode operation. The target frequency of the amplifier was 2.12 GHz, which is in the CDMA-type commercial wireless communication frequency range. For the single-stage amplifier, the optimum input and output impedances provided by the Motorola model were 1[Online].

Available: http://www.motorola.com

Fig. 7. Measured small-signal performance of the single-stage LDMOS power amplifier.

used instead of extracting these values using the device nonlinear model and the load–pull measurement setup. The source impedance was evaluated at the input gate side by looking into the source to ground, while the load impedance was measured from the drain to the load side. The designed circuit was built on a 0.787-mm-thick RT/Duroid substrate with a dielectric constant of 2.33. For better thermal dissipation, the fabricated circuit was mounted on a brass block, as shown in Fig. 6. V and V The bias voltages were set to for testing the small-signal performance of the biased LDMOS power amplifier under normal operation. Fig. 7 shows the measured input and output return losses and small-signal gain of the amplifier using the Agilent 8510C network analyzer. The measured results were compared with the ADS simulation results. At the designed 2.12-GHz 13.1-dB gain, 15.8-dB input return loss and 5-dB output return loss were obtained. For large-signal measurements, a driver amplifier in conjunction with an RF synthesizer was used for sufficient input power. The isolators at the input and output sides were inserted to protect the amplifier. The same bias voltages were applied for the large-signal performance of the circuit. The measured output power and power-added efficiency (PAE) is shown in Fig. 8 as a function of the input power. A saturated output power of 44.5 dBm and a maximum PAE of 47.1% were measured. B. Dual-Mode LDMOS Power Amplifier For testing the dual-mode LDMOS power-amplifier structure, four single-stage amplifiers, which are the same as the single-stage amplifier described in Section III-A, were fabricated. All individual circuit components including the input power divider, output power combiner, and amplifiers were

CHUNG et al.: POWER LEVEL-DEPENDENT DUAL-OPERATING MODE LDMOS POWER AMPLIFIER

Fig. 8. Measured large-signal performance of the single-stage LDMOS power amplifier.

Fig. 9.

Assembled dual-operating mode LDMOS power amplifier.

assembled together. The photograph of the assembled amplifier is shown in the Fig. 9. Notice that the input power detecting circuitry with the envelope detector is not included in Fig. 9. All measurements were accomplished at two different operating modes. One case is that the input signal passes through , as shown in Fig. 9. In the other the top branch amplifier to are activated. For case, all of the amplifiers from both cases, the drain bias voltage was set to 28 V. However, was set to 0 and 3.8 V for the low- and high-input power operations, respectively, to provide different output impedances, as described in Section II. Fig. 10 shows the measured large-signal performance with respect to the input power in the low-input power-mode case. A saturated output power of 43.4 dBm and 20.2% maximum PAE were obtained at the designed frequency of 2.12 GHz. Relative to the saturated output power of the reference singlestage amplifier, the output power is reduced by approximately 1 dB. The degradation of output power is caused by the loading . effect from the other three nonactivated amplifiers In spite of minimizing the loading effect in the circuit design step, the output impedances of the amplifiers, which are biased to the pinchoff operating region, are not ideally open in practice. Therefore, the finite output impedance causes some change to the designed output matching circuit. In addition to the decrease of output power due to the loading effect, the signal loss of 1.6 dB at the input power divider causes significant degradation of maximum PAE by approximately 27% compared to the

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Fig. 10.

Measured large-signal performance in the low-input power mode.

Fig. 11.

Measured frequency characteristics in the low-input power mode.

reference single-stage amplifier. This also results in lowering the measured small-signal gain relative to the reference amplifier performance. Frequency characteristics of the amplifier in the low-input power operating mode were measured from the 2.08- to 2.14-GHz frequency range. The measured maximum PAE and saturated output power over the frequency range are shown in Fig. 11. Since multiple quarter-wave length transmission lines are utilized in both the input power divider and output power combiner, as shown in Fig. 9, these parts cause relatively narrow frequency bandwidth characteristic. In the high-input power mode when all of the amplifiers are turned ON, a 50.2-dBm saturated output power and a 39.1% maximum PAE were measured. The detailed measured large-signal performance versus input power is shown in Fig. 12. By turning on all amplifiers, the saturated output power level reaches 50.2 dBm, which is approximately 6 dB more than that of the reference single-stage amplifier. It implies that the output powers from each individual amplifier are well combined, as expected. The measured frequency characteristics of the amplifier in the high-input power mode are also shown in Fig. 13. The measurement was accomplished over the frequency range from 2.07 to 2.14 GHz. The maximum PAE of approximately 39% and more than 49-dBm saturated output power over the frequency range were achieved.

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Fig. 12.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Measured large-signal performance in the high-input power mode. Fig. 15. Measured CDMA-signal ACLR in two operating modes.

Fig. 13.

Measured frequency characteristics in the high-input power mode.

Fig. 14.

Measured output power, gain, and PAE in mode-changing operation.

Fig. 14 shows the measured output power, gain, and PAE characteristics in the mode-changing operation for the fabricated LDMOS power-amplifier structure. The measured PAE results were compared with the one and four operating amplifier cases. In this mode-changing operation, the critical input power level to switch the operating mode was set to the input 1-dB compression point of the reference LDMOS power amplifier. At the low-input power level, the amplifier operates in the low power mode so that it follows one operating amplifier case. When the input power level reaches the critical value, the operating mode is switched to the high power mode. The input

power is divided into four branches equally in the desired way, as described in Sections I and II. As shown in Fig. 14, it is clear that the dual-mode operation improves overall efficiency of the amplifier in the low-input power level by eliminating unnecessary dc power consumption. At around 40-dBm output power, maximally approximately 8% higher PAE relative to that of the four operating amplifiers was achieved. This results in a 1.7 PAE ratio and approximately 40 W less dc power consumption at the same power level. By switching the operating condition before the PAE drops rapidly, the power amplifier can also maintain a high PAE up to more than 50-dBm output power. The enhancement may be increased even more dramatically by minimizing the signal loss of the implemented dual-mode input power divider in the low-input power operating mode. Since the limitation on adjacent channel interface is more stringent, in addition to the efficiency of an amplifier, the linearity of the amplifier also has to be carefully taken into account. Typically, the linearity would become a more important design issue for single-channel or multichannel base-station transmitters in ground or satellite communication systems. For testing the linearity performance of the built LDMOS power amplifier, an IS-95 forward-link CDMA signal using the Agilent E4433B and a spectrum analyzer to display the output signal were used. The information signal was modulated by a 2.12-GHz RF carrier frequency signal. The adjacent channel leakage power ratio (ACLR), which is defined as the ratio of the power at the adjacent channel to the in-channel power, was mea885-kHz offset frequencies. The ACLR was first sured at and four operating amplifier measured at one – modes, separately. The measured ACLRs at lower and upper adjacent channels for the two individual modes are shown in Fig. 15. From the measured ACLR values in Fig. 15, as the input power exceeds 25 dBm, it is clearly seen that the leakage power level relative to the in-channel power becomes higher than 30 dBc. This results in significant degradation of the linearity performance of the amplifier in the low-input power mode. Like the efficiency measurement of the power amplifier in the mode-changing operation, shown in Fig. 12, the amplifier configuration can provide an improved overall ACLR performance by switching operating mode. For instance, the critical input

CHUNG et al.: POWER LEVEL-DEPENDENT DUAL-OPERATING MODE LDMOS POWER AMPLIFIER

power level of 23 dBm for mode switching keeps the ACLR value below 35 dBc up to 34-dBm input power value. IV. CONCLUSION In this paper, a dual-operating mode design technique has been proposed and investigated for a high-efficiency amplifier. The dual-mode LDMOS power amplifier for CDMA basestation application has been successfully demonstrated. The basic operation has been realized by employing the dualmode input power divider and output power combiner. The FET device characteristic has also been taken into account to implement the design concept and LDMOS amplifier. An alternative switching scheme using a coupled-line coupler with a control switch has been introduced and utilized in the dual-mode input power divider. In the output power-combining scheme, the loading effect has been minimized by making use of the output impedance difference when the transistor was biased to a class-AB and deep pinchoff region. The number of operating transistors was properly chosen depending upon the input power level. This results in minimizing unnecessary dc power consumption and improving efficiency of the amplifier. From the dual-mode operation of the fabricated LDMOS power amplifier, a peak PAE of 20.2% and the saturated output power of 43.4 dBm with linear gain of 10 dB have been achieved from the low-input power operation. On the other hand, for the high-input power mode, a peak PAE of 39.1% and the saturated output power of 50.2 dBm with linear gain of 12 dB have been measured. By switching the operating mode, an 8% maximum improvement in PAE relative to that of the amplifier with four activated transistors has been achieved. The enhanced 8% PAE required approximately 40 W less dc power consumption. In addition to the enhancement in efficiency, the demonstrated amplifier scheme also provides an overall improvement in linearity performance. This study demonstrates that the proposed power-amplifier scheme can be successfully used to enhance efficiency and linearity by controlling the number of amplifiers in operation. ACKNOWLEDGMENT The authors would like to thank Dr. A. Khanifar and F. Cortes, both of PowerWave Technologies, Santa Ana, CA, for the support of high-power measurement setup. REFERENCES [1] A. Springer, L. Maurer, and R. Weigel, “RF system concepts for highly integrated RFICs for W-CDMA mobile radio terminals,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 254–267, Jan. 2002. [2] S. C. Yang, CDMA RF System Engineering. Boston, MA: Artech House, 1998. [3] J. Sevic, “Statistical characterization of RF power amplifier efficiency for IS-95 CDMA digital wireless communication systems,” in IEEE Wireless Communications Conf. Dig., 1997, pp. 110–113. [4] W. H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol. 24, no. Sep., pp. 1163–1182, 1936. [5] C. F. Campbell, “A fully integrated -band Doherty amplifier MMIC,” IEEE Microw. Guided Wave Lett., vol. 9, no. Mar., pp. 114–116, 1999. [6] L. R. Kahn, “Single sideband transmission by envelope elimination and restoration,” Proc. IRE, vol. 40, no. Jul., pp. 803–806, 1952.

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[7] M. Kim, J. B. Hacker, R. E. Mihailovich, and J. F. DeNatalein, “A monolithic MEMS switched dual-path power amplifier,” IEEE Microw. Wireless Compon. Lett., vol. 11, no. 7, pp. 285–286, Jul. 2001. [8] C. Y. Hang, Y. Wang, and T. Itoh, “A new amplifier power combing scheme with optimum efficiency under variable outputs,” in IEEE MTT-S Int. Microwave Symp. Dig., 2002, pp. 913–916. [9] A. Wood, W. Brakensiek, C. Dragon, and W. Bruger, “120 watt, 2 GHz Si LDMOS RF power transistor for PCS base station applications,” in IEEE MTT-S Int. Microwave Symp. Dig., 1998, pp. 707–710. [10] C. Dragon, W. Brakensiek, D. Burdeaux, W. Bruger, G. Funk, M. Hurst, and D. Rice, “200 W push–pull and 110 W single-ended high performance RF-LDMOS transistor for WCDMA base station applications,” in IEEE MTT-S Int. Microwave Symp. Dig., 2003, pp. 69–72. [11] Y. Chung, D. Ahn, E. Y. Wang, and T. Itoh, “A new input power dividing scheme for dual-state amplifiers,” presented at the IEEE Power Amplifiers for Wireless Communications Topical Workshop, 2003. [12] G. L. Matthaei, L. Young, and E. M. T. Jones, Microwave Filters, Impedance-Matching Networks, and Coupling Structures. Dedham, MA: Artech House, 1980. [13] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998. [14] Y. Chung, R. Song, K. Kim, D. Ahn, and T. Itoh, “Power routing scheme with dual operating modes: Two-way Wilkinson divider and one-way signal path,” Electron. Lett., vol. 40, no. 2, pp. 129–130, 2004. [15] S. Yanagawa, H. Ishihara, and M. Ohtomo, “Analytical method for determining equivalent circuit parameters of GaAs FET’s,” IEEE Trans. Microw. Theory Tech., vol. 44, no. Oct., pp. 1637–1641, 1996. [16] P. Perugupalli, M. Trivedi, K. Shenai, and S. K. Leong, “Modeling and characterization of an 80-V silicon LDMOSFET for emerging RFIC applications,” IEEE Trans. Electron Devices, vol. 45, no. Jul., pp. 1468–1478, 1998.

Younkyu Chung (S’00–M’04) received the B.S. degree in electronics from Kyungpook National University, Taegu, Korea, in 1998, the M.S. degree in electrical engineering from Seoul National University (SNU), Seoul, Korea, in 2000, and the Ph.D. degree in electrical engineering from the University of California at Los Angeles (UCLA), in 2004. From January 1998 to February 2000, he was with the Inter-University Semiconductor Research Center (ISRC), SNU, where he was involved with the development of GaAs pseudomorphic high electron-mobility transistor (pHEMTs) and monolithic microwave integrated circuits (MMICs). From September 2000 to February 2004, he was a Graduate Student Researcher involved with microwave amplifiers, RF front-ends, and frequency multipliers at UCLA. Since March 2004, he has been with the Center for the Physics of Information, California Institute of Technology, Pasadena, where he is a Post-Doctoral Fellow involved with millimeter-wave amplifiers. He has authored and coauthored 30 technical papers. His current research focus is on the design of microwave/millimeter-wave amplifiers, power-combining techniques, advanced RF front-end modules, and frequency multipliers. Dr. Chung is a member of IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He was the recipient of the General Electric Foundation Fellowship (1997–1998). He was also the recipient of the 2002 IEEE MTT-S Graduate Student Fellowship and the 2004 California Institute of Technology Post-Doctoral Research Fellowship.

Jinseong Jeong was born in Seoul, Korea, in 1974. He received the B.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1996, the M.S. degree in electrical engineering from the University of California at Los Angeles (UCLA), in 2002, and is currently working toward the Ph.D. degree at UCLA. From 1996 to 1999, he was with Seodu InChip Inc., Seoul, Korea, where he developed several CDMA modem chips for IMT-2000 and wireless local loops (WLLs). Prior to joining UCLA, he was with Nokia Mobile Phones, Seoul, Korea, where he developed personal communications system (PCS) phone modules. His research interests include high-efficiency and high linear RF power-amplifier design for wireless communications and the fusion of signal-processing and circuit techniques in microwave system design.

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Yuanxun Wang (S’96–M’99) received the B.S. degree in electrical engineering from the University of Science and Technology of China (USTC), Hefei, China, in 1993, and the M.S. and Ph.D. degrees in electrical engineering from the University of Texas at Austin, in 1996 and 1999, respectively. From 1993 to 1995, he was a Graduate Researcher with USTC, where he was involved with numerical methods and millimeter-wave radar-based instruments. From 1995 to 1999, he was with the Department of Electrical and Computer Engineering, University of Texas at Austin, where he was a Graduate Research Assistant involved with radar scattering modeling and SAR imaging. From 1999 to 2002, he was a Research Engineer and Lecturer with the Department of Electrical Engineering, University of California at Los Angeles (UCLA). In November 2002, he became an Assistant Professor with the Electrical Engineering Department, UCLA. He has authored and coauthored over 60 refereed journal and conference papers. He has been involved with novel experimental architectures and hardware implementations for high-performance antenna array and microwave amplifier systems with applications in wireless communication and radar sensors. Part of his research also involves numerical modeling techniques for microwave circuits. His research interests feature the fusion of signal-processing and circuit techniques into microwave system design. Dr. Wang is a member of the International Society for Optical Engineers (SPIE).

Dal Ahn (M’95–SM’04) was born in Kimje, Korea, on October 15, 1961. He received the B.S., M.S., and Ph.D. degrees from the Sogang University, Seoul, Korea, in 1984, 1986, and 1990, respectively, all in electronics. From 1990 to 1992, he was with the Mobile Communications Division, Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea. Since 1992, he has been with the School of Electrical and Electronic Engineering, Soonchunhyang University, Choongnam, Korea, where he is currently a Professor. He is currently Chief of the RF and Microwave Component Research Center (RAMREC), Soonchunhyang University. He is currently a Visiting Scholar with the University of California at Los Angeles (UCLA). He is also a technical consultant for Tel Wave Inc., Suwon, Korea, and MRW Technologies, Paju, Korea. His current research interests include the design and application of passive and active components at radio and microwave frequencies, circuit modeling using commercial electromagnetic analysis programs, and DGS application for RF and microwave components.

Tatsuo Itoh (S’69–M’69–SM’74–F’82) received the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, in 1969. From September 1966 to April 1976, he was with the Electrical Engineering Department, University of Illinois at Urbana-Champaign. From April 1976 to August 1977, he was a Senior Research Engineer with the Radio Physics Laboratory, SRI International, Menlo Park, CA. From August 1977 to June 1978, he was an Associate Professor with the University of Kentucky, Lexington. In July 1978, he joined the faculty at The University of Texas at Austin, where he became a Professor of Electrical Engineering in 1981 and Director of the Electrical Engineering Research Laboratory in 1984. During the summer of 1979, he was a Guest Researcher with AEG-Telefunken, Ulm, Germany. In September 1983, he was selected to hold the Hayden Head Centennial Professorship of Engineering at The University of Texas at Austin. In September 1984, he was appointed Associate Chairman for Research and Planning of the Electrical and Computer Engineering Department, The University of Texas at Austin. In January 1991, he joined the University of California at Los Angeles (UCLA) as Professor of Electrical Engineering and Holder of the TRW Endowed Chair in Microwave and Millimeter Wave Electronics. He was an Honorary Visiting Professor with the Nanjing Institute of Technology, Nanjing, China, and at the Japan Defense Academy. In April 1994, he was appointed an Adjunct Research Officer with the Communications Research Laboratory, Ministry of Post and Telecommunication, Japan. He currently holds a Visiting Professorship with The University of Leeds, Leeds, U.K. He has authored or coauthored 350 journal publications, 650 refereed conference presentations, and has written 30 books/book chapters in the area of microwaves, millimeter waves, antennas, and numerical electromagnetics. He has generated 64 Ph.D. students. Dr. Itoh is a member of the Institute of Electronics and Communication Engineers of Japan, and Commissions B and D of USNC/URSI. He served as the editor of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES (1983–1985). He serves on the Administrative Committee of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He was vice president of the IEEE MTT-S in 1989 and president in 1990. He was the editor-in-chief of IEEE MICROWAVE AND GUIDED WAVE LETTERS (1991–1994). He was elected an Honorary Life Member of the IEEE MTT-S in 1994. He was elected a member of the National Academy of Engineering in 2003. He was the chairman of the USNC/URSI Commission D (1988–1990) and chairman of Commission D of the International URSI (1993–1996). He is chair of the Long Range Planning Committee of the URSI. He serves on advisory boards and committees for numerous organizations. He has been the recipient of numerous awards including the 1998 Shida Award presented by the Japanese Ministry of Post and Telecommunications, the 1998 Japan Microwave Prize, the 2000 IEEE Third Millennium Medal, and the 2000 IEEE MTT-S Distinguished Educator Award.

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Miniaturized Spurious Passband Suppression Microstrip Filter Using Meandered Parallel Coupled Lines Shih-Ming Wang, Chun-Hsiang Chi, Ming-Yu Hsieh, and Chi-Yang Chang, Member, IEEE

Abstract—A novel meandered parallel coupled-line structure is proposed to suppress the first spurious passband of a microstrip bandpass filter. The meandered parallel coupled line can equalize the modal transmission phases at any interested frequency such as first spurious passband frequency due to its dispersive response. Several filters are designed and fabricated on a substrate with a dielectric constant of 10.2 and a thickness of 50 mil (1.27 mm) to demonstrate the validity of the proposed method. The example filters are chosen to be of large fractional bandwidth and with a relatively high dielectric-constant substrate where, in these cases, the first spurious passband near twice of the passband frequency (2 ) seriously degrades the conventional parallel coupled filter’s upper stopband performance. The upper stopband performance of the proposed filters drastically improves that the measured first spurious passband are suppressed to better than 50 dB for all example filters. Besides, a meandered coupled line not only suppresses the filter’s first passband, but also largely shrinks its length. The characteristics of the proposed structure and the design procedures of the filter are described in detail. Index Terms—Microstrip, microwave filter, parallel coupled line, spurious passband.

I. INTRODUCTION

T

HE MICROSTRIP parallel coupled filter first proposed by Cohn in 1958 [1] has been widely used in many microwave and wireless communication systems. This type of filter is popular due to its planar structure, insensitivity to fabrication tolerance, wide realizable bandwidth (from a few percent to more than 60%) [2]–[4], and simple synthesis procedures [5]. However, there are several disadvantages of the conventional microstrip parallel coupled filter. One of the disadvantages is that the first spurious passband of this type of filter appears at twice . Therefore, the rejecof the basic passband frequency tion of the upper stopband is worse than that of the lower stopband. Sometimes, the upper stopband rejection may be as bad as 10 dB, especially in case of wide bandwidth filters. Another disadvantage is the whole length of the filter is too long,

Manuscript received March 15, 2004. This work was supported in part by the National Science Council, R.O.C., under Grant NSC 92-2213-E-009-080. S.-M. Wang, C.-H. Chi, and C.-Y. Chang are with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]; [email protected]; [email protected]). M.-Y. Hsieh was with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. He is now with the Chung-Shan Institute of Science and Technology, Lung-Tang 325, Taiwan, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840619

especially when the order of a filter becomes high. Both disadvantages greatly limit the application of this type of filter. The reason for the first spurious passband is that the evenmode phase velocity is always slower than that of the odd mode because of the inhomogeneous medium of microstrip structure. cause the first spuThe unequal modal phase velocities at rious passband. There are two basic methods to equalize the modal transmission phase: providing different lengths for the even and odd mode, or equalizing the modal phase velocities. In [6] and [7], an over-coupled resonator is proposed to extend the electrical length of the odd mode to compensate the difference in the phase velocities. The structure in [8] and [9] uses capacitors to slow down the odd-mode phase velocity. The substrate suspension structures in [10] are substantially designed to speed up the even-mode phase velocity, and make the modal phase velocities equal. The wiggly coupled microstrip filter in [11] is also effective in improving the rejection characteristics . These published filters have some drawof the filter at backs. Firstly, all these filters in [6]–[11] are too long due to their straight structure, especially when the order of the filter becomes high. The filters in [8] and [9] need extra circuit components that cause higher material and assembly cost. The filter in [10] needs to suspend the substrate, and a costly package is required. The filters in [6], [7], [10], and [11] are with complex design procedures. An alternative method to eliminate spurious passband is to use a self-filtering resonator [12] where the resonator is formed by a high–low impedance low-pass filter. This kind of resonator is complex to layout as a parallel coupled filter. Moreover, due to the limitation of the high–low impedance ratio of the resonator, the spurious passband suppression is usually limited, unless a three-dimensional structure is used. Another method to improve a parallel coupled filter’s upper stopband performance is to move the first spurious passband [13], [14]. Usually, using the step impedance away from resonator can shift the first higher order resonant frequency of a resonator. However, the step impedance method is to move, not to suppress, the first spurious band. If we want to move the , a large impedance stepping ratio first spurious passband to of the resonator is required and the layout of the filter becomes difficult. In this paper, the motivation of the proposed filter is from [15] in that the even-mode phase velocity can be speeded up for a meandered parallel coupled line. As a parallel coupled filter meandered properly, not only can the filter’s first spurious passbe suppressed, but also its size can be drastically band near reduced. It is also unprecedented that a parallel coupled filter

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Fig. 1. TEM parallel coupled bandpass section. (a) Schematic representation. (b) Equivalent circuit.

can simultaneously suppress the spurious passband and greatly reduce its size. Furthermore, the proposed structure needs no additional circuit components or fabrication process such as capacitors or via-holes, thus, low fabrication cost can be kept. The proposed filter is developed by meandering each parallel coupled section of the conventional parallel coupled filter. The new parallel coupled section can be modeled as a meandered parallel coupled line and a commercial circuit simulator can analyze it. In this paper, the behaviors of the meandered parallel coupled line are explained particularly. Systematic design procedures of the proposed filter are described in detail. Several meandered parallel coupled microstrip filters are fabricated with various specifications, and the measured results match well with simulation. This paper is organized as follows. Section II explores the modal transmission phase equalization for a meandered parallel coupled microstrip line. Section III describes the design procedures of the proposed filter. Section IV presents the simulated and measured results of several fabricated filters. Section V discusses the transmission zeros in the upper stopband, and Section VI draws a conclusion. II. EQUALIZING MODAL TRANSMISSION PHASES USING MEANDERED PARALLEL COUPLED LINE The schematic of a parallel coupled bandpass section is shown in Fig. 1(a), and its equivalent circuit proposed by and are the Matthaei [2] is shown in Fig. 1(b), where even- and odd-mode characteristic impedances. The coupled electrical length , even-mode transmission phase , and odd-mode transmission phase are given by (1) (2)

Fig. 2. Schiffman section. (a) Schematic representation. (b) Dispersive phase responses.

mode phase velocities. Here, the equivalent circuit in Fig. 1(b) is based on the TEM mode, and and are both equal to for all frequencies. From Fig. 1(b), at , because , the series open stub will be open circuited at its input end. The transmission line between the two series open stubs is now at its half-wavelength resonant frequency where the first spurious passband locates. Since the two series open stubs are open circuited at their ends, no energy can be coupled to the half-wave resonator and a stopband will be formed. Therefore, the ultimate target of spurious passband suppression, described in Secat . Unfortunately, tion I, is to achieve in a microstrip structure, because the even-mode phase velocity of a microstrip coupled line is always slower than that of the odd-mode, is always larger than for all frequencies. Therefore, the spurious passband of a conventional microstrip parallel occurs. coupled filter at To understand the phase-equalizing scheme of the proposed structure, the behaviors of a Schiffman section must be studied. The Schiffman section, as shown in Fig. 2(a), is a two-port network, which is formed by connecting one side of a parallel coupled line [16]. If the interconnecting line has zero transmission phase, the relation between transmission phase and coupled electrical length of the two-port network is determined by

(3) where is the operating frequency, is the physical length of the parallel coupled line, and and are the even- and odd-

(4)

WANG et al.: MINIATURIZED SPURIOUS PASSBAND SUPPRESSION MICROSTRIP FILTER

Fig. 3. (a) Conventional parallel coupled line. (b) Proposed meandered parallel coupled line.

From (4), the dispersive phase responses can be shown in Fig. 2(b). Fig. 2(b) clearly indicates that, as two lines couple to each other, the transmission phase is reduced and, equiv. The alently, the phase velocity is speeded up for have the largest accelerating ratio. frequencies around However, the meandered parallel coupled line is a four-port rather than a two-port circuit. As discussed in [15], when the meandered coupled line is excited with an even mode, it can be equivalent to a single-line Schiffman section because the evenmode modal current distribution is similar to that of a single line. Therefore, the even-mode phase velocity is accelerated . To distinguish when even-mode transmission phase it from the conventional Schiffman section, we call it a coupled-Schiffman section. Fig. 3(a) shows a conventional parallel coupled-line section. Fig. 3(b) depicts the proposed meandered parallel coupled-line section, which is the basic building block of our parallel coupled-line filter. The coupled line in Fig. 3(b) is the variation of Fig. 3(a). All circuit dimensions of the meandered parallel coupled line are shown in Fig. 3(b), where is the linewidth, is the line spacing, is the coupled-Schiffman section length, is the interconnecting coupled-line length, which is also called the meandered distance, and is the tail coupled-line length. The meandered parallel coupled-line section, shown in Fig. 3(b), has the advantage of reducing the circuit size and equalizing the modal transmission phases. The effects of equalizing the modal transmission phases are originated from the coupled-Schiffman section. As discussed previously, the coupled-Schiffman section speeds up the even-mode phase velocity. In addition, because the odd-mode current distribution cannot be approximated to that of the Schiffman section, the odd-mode phase velocity is not obviously increased as the even mode. By electromagnetic (EM) simulation, the odd-mode phase velocity is found to increase very slightly. In an attempt to easily explain, here we neglect the tiny variation of the odd-mode transmission phase caused by meandering. The main mechanism of the proposed structure is to speed up

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Fig. 4. Modal transmission phases of a conventional parallel coupled line and a coupled-Schiffman section with different coupled line lengths. For l = L=2, :  , 4:  without Schiffman effect,  :  with Schiffman effect. For l < L=2, : , :  without Schiffman effect,  :  with Schiffman effect.

the even-mode phase velocity and to achieve the target of at . Since odd-mode transmission phase is not affected by meandering, the total length of the proposed meandered parallel coupled line is equal to that of the conventional coupled line and the total length is chosen to be at . and of a conventional coupled line are shown as the hollow-triangle dashed line and the hollow-square line in is smaller than , and their difference Fig. 4, respectively. is increased proportional to frequency. Now, if the coupled-line corners and interconnecting and tail coupled line are omitted, the even-mode phase velocity of a coupled-Schiffman section is decelerated at as the hollow-circle curve with length shown in Fig. 4. This is because the phase velocity accelerating region of a Schiffman section should be located in the region of and the most effective accelerating region is close be located to 90 . Therefore, in order to make the desired in the accelerating region, the length of the coupled-Schiffman . The even-mode phase velocity section must be shorter than of a shortened coupled-Schiffman secaccelerating effect at tion is shown as the solid-circle line in Fig. 4. The target of at can be achieved after adding a interconnecting coupled line, three coupled-line corners, and a tail coupled line. With the same and , there are multiple solutions of coupled-Schiffman section length , interconnecting coupled-line at length , and tail coupled-line length for . The hollow-circle and solid-circle curves in Fig. 5 are the even-mode transmission phases of two different meandered parat is achieved. allel coupled lines where The reason can be briefly explained that, as is shortened, the coupled Shiffman section length increases and the accelerating magnitude at decreases. Therefore, the meandered distance must be shortened to compensate the reduction of accelerating magnitude. Since and are tunable, the layout of a proposed meandered parallel coupled-line filter can be flexibly changed to obtain a desired filter’s width-to-length ratio.

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Fig. 5. Even-mode 4 and odd-mode transmission phases of a conventional parallel coupled line, and two different solutions  and  of meandered parallel coupled lines with equal modal transmission phases at 2f .

III. FILTER DESIGN Design procedures of the proposed filter will now be discussed. Here, as an example, take the filter’s passband frequency to be 1 GHz. Therefore, spurious passband at 2 GHz needs to be and thicksuppressed. The substrate is chosen with mil (1.27 mm). The main reason for choosing this ness relative high is to challenge the relatively large deviation between and . This will increase the difficulties in suppres. sion of the spurious passband at As shown in Fig. 3(b), the proposed meandered parallel coupled line comprises an interconnecting coupled line, a tail coupled line, a coupled-Schiffman section, and three coupled-line corners. A circuit simulator such as Agilent ADS or AWR Microwave Office can be used to analyze the behaviors of the meandered parallel coupled line. The models used in the circuit simulation are described as following. The interconnecting and tail coupled lines use the standard microstrip coupled-line model in the circuit simulator. The coupled-line corners and coupled-Schiffman section are modeled in most of circuit simulators based on a lookup table of EM results. Using a circuit simulator can quickly get desired design parameters. Shown in Fig. 6 are the design plots of the meandered parallel coupled line obtained by the above-described circuit models. As discussed in Section II, the tail coupled line length can be changed. Therefore, by properly choosing , one can obtain a good length-to-width ratio of the filter. For a certain value, two design plots such as those of Fig. 6(a) and (b) is needed to design the proposed filter. Since the dimensional and electrical variables of a meandered parallel coupled line are too many, a set of two plots to express them is required. The physical dimenat (this sions have some constrains to meet means that the physical dimensions cannot be freely chosen). To generate the design plots shown Fig. 6(a), tail coupled-line length can be chosen first. As long as is fixed, the meander

Fig. 6. Design plots of the meandered parallel coupled line with b = 60 mil. (a) The corresponding meandered distance d and coupled-Schiffman section length l. (b) The even- and odd-mode characteristic impedances versus w=h and s=h of a meandered parallel coupled line.

distance and coupled-Schiffman section length can be obtained corresponding to various and where the condition of at is matched. Now all of the physical dimensions in Fig. 3(b) are fixed. We should know that, for and , even- and odd-mode characteristic impedances of the meandered parallel coupled line are different from that of the and versus conventional coupled line. Fig. 6(b) shows and of a meandered parallel coupled line. The particular design curves in Fig. 6 are based on equal to a 1/80 wave, i.e., approximately 60 mil (1.524 mm)]. It should length [ be pointed out that because the accelerating magnitude around is larger than , as shown in Fig. 5, the frequency spacing and is smaller than one . It implies between that if the filter’s passband frequency is at , the frequency for at which the spurious passband located will be a little . bit lower than After completing the design plots for a chosen , we can use the design plots to design the proposed filter. First, for a given

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TABLE I FILTER DESIGN PARAMETERS

filter’s passband parameters, sets of even- and odd-mode characteristic impedances of each coupled-line section are obtained and based on a TEM assumption. Using Fig. 6(b), with obtained in step 1, we then have the corresponding and . Finally, as long as and are known, the corresponding and can be obtained in Fig. 6(a). By cascading each meandered parallel coupled-line section, a proposed filter is finished. According to the previous discussion, the filter is designed with and is free of spurious passband at . The passband at above-described design procedures based on a circuit simulator such as Agilent ADS or AWR Microwave Office can rapidly get the physical layout of the proposed filter. Final fine-tuning based on an EM simulator such as Sonnet is required to precisely eliminate the first spurious passband and to maintain the main passband performance. These design procedures can largely save the designing time compared to the method of purely using the EM simulator. IV. SIMULATION AND MEASURED RESPONSES Three bandpass filters with a Chebyshev response of 0.1-dB passband ripple are fabricated to demonstrate the proposed first spurious passband-free performance. The designed center frequency is 1 GHz. The circuits are fabricated on a Rogers RT/6010 substrate. The substrate has a relative dielectric constant of 10.2, a thickness of 50 mil, and a copper cladding of 0.5 oz. Although the design procedures have been described in Section III, we still need to provide the following further explanation. Since the fractional bandwidth (FBW) of the filters is too large, design equations in [1] are not adequate. More accurate design procedures based on an ideal TEM coupled line can and be used [2]. Following these design steps, a series of are obtained. We can then determine if has a preferable filter’s width-to-length ratio. After is chosen, we can draw the and design plots of Fig. 6(a) and (b). Using the obtained values, the corresponding and can then be obtained in Fig. 6(b). By using the known and with the design plot [see Fig. 6(a)], the corresponding and is, therefore, determined. The dimensions of each meandered parallel coupled-line section can be obtained separately by the above-described procedures . We can then have the circuit simulator do the initial verification for the obtained dimensions of the proposed filter. Finally, we use a EM simulator such as Sonnet to finalize the design. Here, it must be remembered that when a circuit simulator is used, it is assumed that each meandered coupled-line section is independent of each other. The practical interaction, however, indeed exists. Since the equality of and is very sensitive to external interference, slightly tuning of and to compensate

Fig. 7. Simulated and measured responses of filter A and the measured insertion loss of a conventional filter with the same specification is compared.

Fig. 8. Simulated and measured responses of filter B.

for interaction effects is needed in the EM simulation. Empirically, a 10% increase in and a 5% increase in are needed. Since the even- and odd-mode characteristic impedances are insensitive to the external interference, the and value can be maintained. The parameters including the specifications and detailed dimensions of each meander parallel coupled-line section of

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Fig. 10.

Layout of filter A.

Fig. 11.

Circuit size comparison between filter A and conventional filter.

Simulated and measured responses of filter C.

the filters are listed in Table I. The simulated and measured responses are depicted in Figs. 7–9, and their are all 60 mil. Two filters with order 3 and one filter with order 5 are designed. The FBW of filter A and C (orders 3 and 5, respectively) is 50%, and that of B (order 3) is 30%. Since the lower edge of the first spurious passband is closer to the upper edge of the main passband as the filter’s FBW becomes wider, the performance of the upper stopband may degrade seriously to worse than 30 dB. Therefore, a wide bandwidth filter is chosen to show the impressive improvement of the upper stopband performance. Fig. 7 shows the simulated and measured results of filter A. A conventional filter with the same specifications is also shown in Fig. 7 to compare the improvement of the upper stopband performance. In Fig. 7, the upper stopband rejection is improved from 30 dB to below 50 dB and the spurious passband suppression at 2 GHz is improved form 10 dB to below 60 dB. Comparing the proposed filter to the conventional one, an excellent improvement is achieved. In Fig. 8, filter B’s upper stopband is improved to 50 dB and the spurious passband can be suppressed to approximately 55 dB. In Fig. 9, filter C’s upper stopband is improved to approximately 70 dB and the spurious passband can be suppressed to approximately 70 dB. The layout of filter A is shown in Fig. 10. Fig. 11 depicts the circuit size comparison between filter A and a conventional filter with same filter parameters. It is obvious that the circuit size is drastically reduced. V. DISCUSSION If we look at the simulated insertion loss of all three filters in Figs. 7–9, some transmission zeros appear in the upper stopband. These transmission zeros are possibly due to the parasitic magnetic cross-coupling between nonadjacent resonators. The parasitic magnetic coupling is because at the bottom of the filter every meandered coupled-line section has the strongest RF current, and the strongest current-carrying line segments are very close to the next meandered coupled-line sections. In the mean

time, magnetic coupling cannot be blocked by other lines. These upper stopband transmission zeros cause the filters to display a steeper upper stopband skirt than that of a lower stopband. In addition, we can observe the insertion loss at the upper end of the passband is a little bit larger than that of the lower end. The reason is because the resonator’s quality factor is finite in practical fabrication and the transmissions zeros in the upper stopband cause sharp rolloff at the high side skirt. The transmission zeros are not apparent in the measured curves due to their finite resonator value and sensitivity of the measurement equipment (the sensitivity of our equipment is approximately 70 dB). All the measured results have a good agreement with the simulated results in both the passband and stopband. Summarizing the above three examples, we may conservatively conclude that the proposed meandered parallel coupled filter improves the by upper stopband rejection and the spurious passband at at least 20 and 40 dB, respectively. VI. CONCLUSION The proposed novel meandered parallel coupled-line structure has successfully suppressed the spurious passband at and reduced the circuit size of the filter. No additional materials, components, or fabricated process are required. The idea for spurious passband suppression is based on the fact that evenmode phase velocity can be speeded up by a coupled-Schiffman section. By proper adjustment of the physical dimensions of the meandered parallel coupled-line section, an equal even- and can be achieved. For a deodd-mode transmission phase at sired length-to-width ratio of the filter, a proper tail coupled-line length value can be chosen first. Furthermore, the structure can be analyzed quickly with good accuracy by a commercial circuit simulator. The design plots corresponding to a chosen value can be easily obtained. The filter design procedures based

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on this proposed structure have been described in detail. Good agreement of simulated and measured results has been achieved. Finally, the proposed filters have shown over 50-dB spurious and a deeper upper stopband rejecpassband suppression at tion than those of the conventional one.

REFERENCES [1] S. B. Cohn, “Parallel-coupled transmission-line-resonator filters,” IRE Trans. Microw. Theory Tech., vol. MTT-6, no. 4, pp. 223–231, Apr. 1958. [2] G. L. Matthaei, “Design of wide-band (and narrow-band) bandpass microwave filters on the insertion loss basis,” IRE Trans. Microw. Theory Tech., vol. MTT-8, no. 11, pp. 580–593, Nov. 1960. [3] C.-Y. Chang and T. Itoh, “A modified parallel-coupled filter structure that improves the upper stopband rejection and response symmetry,” IEEE Trans. Microw. Theory Tech., vol. 39, no. 2, pp. 310–314, Feb. 1991. [4] A. Riddle, “High performance parallel coupled microstrip filters,” in IEEE MTT-S Int. Microwave Symp. Dig., 1988, pp. 427–430. [5] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998, pp. 474–485. [6] J.-T. Kuo, S.-P. Chen, and M. Jiang, “Parallel-coupled microstrip filters with over-coupled end stages for suppression of spurious responses,” IEEE Microw. Wireless Compon. Lett., vol. 13, no. 10, pp. 440–442, Oct. 2003. [7] B. Easter and K. A. Merza, “Parallel-coupled-line filters of invented-microstrip and suspended-substrate MIC’s,” in 11th Eur. Microwave Conf. Dig., 1981, pp. 164–167. [8] S. L. March, “Phase velocity compensation in parallel-coupled microstrip,” in IEEE MTT-S Int. Microwave Symp. Dig., 1982, pp. 410–412. [9] I. J. Bahl, “Capacitively compensated high performance parallel coupled microstrip filters,” in IEEE MTT-S Int. Microwave Symp. Dig., 1989, pp. 679–682. [10] J.-T. Kuo, M. Jiang, and H.-J. Chang, “Design of parallel-coupled microstrip filters with suppression of spurious resonances using substrate suspension,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 1, pp. 83–89, Jan. 2004. [11] T. Lopetegi, M. A. G. Laso, J. Hernandez, M. Bacaicoa, D. Benito, M. J. Garde, M. Sorolla, and M. Guglielmi, “New microstrip ‘wiggly-line’ filters with spurious passband suppression,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1593–1598, Sep. 2001. [12] C. Quendo, J. Coupez, C. Person, E. Rius, M. Roy, and S. Toutain, “Bandpass filters with self-filtering resonators: A solution to control spurious resonances,” in IEEE MTT-S Int. Microwave Symp. Dig., 1999, pp. 1135–1138. [13] M. Makimoto and S. Yamashita, “Bandpass filters using parallel coupled stripline stepped impedance resonators,” IEEE Trans. Microw. Theory Tech., vol. MTT-28, no. 12, pp. 1413–1417, Dec. 1980. [14] C. Wang and K. Chang, “Microstrip multiplexer with four channels for broadband system applications,” Int. J. RF Microwave Computer-Aided Eng., pp. 48–54, Nov. 2001. [15] S.-M. Wang, C.-H. Chen, and C.-Y. Chang, “A study of meandered microstrip coupler with high directivity,” in IEEE MTT-S Int. Microwave Symp. Dig., 2003, pp. 63–66. [16] B. M. Schiffman, “A new class of broadband microwave 90 phase shifter,” IRE Trans. Microw. Theory Tech., vol. MTT-6, no. 4, pp. 232–237, Apr. 1958.

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Shih-Ming Wang was born in Tainan, Taiwan, R.O.C., on February 15, 1978. He received the B.S. and M.S. degrees in electrical engineering from the National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C., in 1999 and 2001, respectively, and is currently working toward the Ph.D. degree in communication engineering at the National Chiao-Tung University. His research interests include the analysis and design of microwave and millimeter-wave circuits.

Chun-Hsiang Chi received the B.S. degree in electronic engineering from the National Sun Yet-Sen University, Kaohsiung, Taiwan, R.O.C., in 2002, and is currently working toward the M.S. degree in communication engineering at the National Chiao-Tung University. His research interests including low-temperature co-fired ceramic (LTCC) RF passive components and LTCC modules design for wireless local area network (LAN) applications.

Ming-Yu Hsieh was born in Taiwan, R.O.C., on July 2, 1978. He received the B.S. and M.S. degrees in communication engineering from the National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 2001 and 2003, respectively. In 2003, he joined the Chung-Shan Institute of Science and Technology (CSIST), Lung-Tang, Taiwan, R.O.C., as an RF Engineer. His research interests include microwave broad-band filter design and oscillator design.

Chi-Yang Chang (S’88–M’95) was born in Taipei, Taiwan, R.O.C., on December 20, 1954. He received the B.S. degree in physics and M.S. degree in electrical engineering from the National Taiwan University, Taiwan, R.O.C., in 1977 and 1982, respectively, and the Ph.D. degree in electrical engineering from The University of Texas at Austin, in 1990. From 1979 to 1980, he was a Teaching Assistant with the Department of Physics, National Taiwan University. From 1982 to 1988, he was an Assistant Researcher with the Chung-Shan Institute of Science and Technology (CSIST), where he was in charge of development of microwave integrated circuits (MICs), microwave subsystems, and millimeter-wave waveguide E -plane circuits. From 1990 to 1995, he returned to CSIST as an Associate Researcher, where he was in charge of development of uniplanar circuits, ultra-broad-band circuits, and millimeter-wave planar circuits. In 1995, he jointed the faculty of the Department of Communication, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., as an Associate Professor and, in 2002, became a Professor. His research interests include microwave and millimeter-wave passive and active circuit design, planar miniaturized filter design, and monolithic-microwave integrated-circuit (MMIC) design.

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High-Power High-Efficiency SiGe - and -Band Balanced Frequency Doublers

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Juo-Jung Hung, Member, IEEE, Timothy M. Hancock, Member, IEEE, and Gabriel M. Rebeiz, Fellow, IEEE

Abstract—High-efficiency monolithic SiGe balanced frequency doublers have been developed for - and -band applications. A novel miniature second harmonic reflector is presented, and the impact of the parasitic inductor from emitter to ground is also explored to optimize the conversion efficiency of the doubler. The -band design presents an output power of 5–6 dBm from 15.4–18 GHz for an input power of 1.5 dBm. DC power consumption is 28 mW and the corresponding power-added efficiency -band design demonstrates an output (PAE) is 9.2%. The power of 10.5 dBm at 36 GHz for an input power of 6 dBm while consuming 114 mW of dc power, which results in a PAE of 6.4%. It also shows high spectral purity operation with the fundamental suppression of 35 dB. To our knowledge, these are the best results for active doublers using any technology. Index Terms—Balanced frequency doubler, high efficiency, high power, high spectral purity, monolithic microwave integrated circuit (MMIC), SiGe. Fig. 1. Schematic of the

I. INTRODUCTION

Ka-band balanced frequency doubler.

T

HE FREQUENCY doubler is an important component in microwave and millimeter-wave communication systems. As the design frequency increases, the implementation of low phase-noise oscillators becomes difficult. One solution is to use a doubler circuit preceded by a lower frequency high spectral purity voltage-controlled oscillator (VCO). In addition, if the oscillator/doubler is used in a phased-locked loop (PLL), the performance specifications of the frequency divider can be relaxed because it needs to work at only half of the output frequency. Frequency doublers have been implemented using field-effect transistor (FET) devices such as GaAs high electron-mobility transistors (HEMTs) [1], pseudomorphic high electron-mobility transistors (pHEMTs) [2], InP HEMTs [3] or silicon-on-insulator (SOI) CMOS [4], while some designs are realized using HBT devices like InGaP [5] or SiGe [6]. The research presented in [1]–[5] all takes the same approach of using the nonlinearities of a transistor biased to operate in a class-B configuration. This generates an output current rich in Manuscript received March 31, 2004; revised June 2, 2004. J.-J. Hung is with the Electrical Engineering and Computer Science/Radiation Laboratory, The University of Michigan at Ann Arbor, Ann Arbor, MI 481092122 USA (e-mail: [email protected]). G. M. Rebeiz was with the Electrical Engineering and Computer Science/Radiation Laboratory, The University of Michigan at Ann Arbor, Ann Arbor, MI 48109-2122 USA. He is now with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0407 USA (e-mail: [email protected]). T. M. Hancock was with the Electrical Engineering and Computer Science/Radiation Laboratory, The University of Michigan at Ann Arbor, Ann Arbor, MI 48109-2122 USA. He is now with the Analog Device Technology Group, Massachusetts Institute of Technology Lincoln Laboratory, Lexington, MA 02420-9108 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840615

Fig. 2.

Collector current modeled as a train of rectified cosine pulses.

harmonic content. The research in [4] is an unbalanced design that uses only a matching network at the second harmonic and has an output power of 3 dBm and a low fundamental suppression of 11 dB. In [1]–[3], the fundamental suppression is improved despite the unbalanced design with the use of an output resonant stub. A class-E unbalanced doubler was also presented in [7] with high conversion efficiency, but it was not a monolithic-microwave integrated-circuit (MMIC)/RF integrated-circuit (RFIC) design. In a balanced design, higher output power can be obtained because of the additional swing that differential operation allows. However, differential operation requires a 3-dB increase in the input drive level and the dc power. The balanced topology also has the advantage of achieving broad-band fundamental suppression without the use of a resonator structure at the output [8] and it is easily integrated with a differential oscillator. An example of balanced operation is [6], where linear multiplication is used to achieve doubling by connecting the local oscillator (LO) and RF ports of a Gilbert cell together. Although the doubler is balanced and achieves good fundamental suppression, the output power and efficiency are low because it is operated in a class-A configuration. The research in [5] is also a balanced

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Fig. 3. Simplified schematic of the doubling stage with: (a) lossless 50- delay line, (b) parasitic inductor L connected between the emitters and ground, and (c) parasitic inductor L connected between the emitters and ground with the reflectors connected to the emitters rather than ground.

design, but operates in a class-B configuration and good fundamental suppression is achieved due to the balanced topology. The performance of a doubler can be further improved by using a second harmonic reflector at the input of the transistors. This increases the conversion gain at the expense of a decrease in bandwidth and increase in circuit area [9]. For this reason, input reflectors are often not used in monolithic designs. However, with accurate electromagnetic design to account for parasitic coupling paths, miniaturized input reflectors can be used to improve the performance of a monolithic doubler without a significant increase in area. Depending on the topology used, there are tradeoffs between area, bandwidth, efficiency, and output power. Although the active doublers referenced above all achieve conversion gain, their power-added efficiencies (PAEs) are generally quite low. This - and -band depaper presents miniaturized balanced signs with high spectral purity using a commercial SiGe bipolar process (Atmel Corporation, San Jose, CA, SiGe2-RF).1 The doublers are designed for high efficiency while maintaining good performance comparable to monolithic III–V designs. SiGe HBT devices are more nonlinear than HEMT devices and result in excellent conversion gain and low-cost designs.

III.

-BAND FREQUENCY DOUBLER

A. Circuit Design The design of the -band doubler is more challenging than the -band design since the operating frequency becomes half of the unity-gain frequency of the transistor. The schematic of the doubler is shown in Fig. 1, in which and are operating as the doubling stage. A cascode stage is added not only to amplify the signal from the doubling stage, but also reduce the Miller effect of and , which results in a higher gainbandwidth product of the transistor. The doubling stage is biased V , while the cascode stage is closed to class B operating in the class-A region V. is designed to be 4 V in order to keep the of the transistors less than 2.5 V. The size of the transistors and can be determined by considering the relationship between the output power and dc power consumption. The harmonic component of collector current is a function of conduction angle, which can be controlled by the input driving power and base bias point. If the collector current is modeled as a train of rectified cosine pulses (Fig. 2), using a Fourier series expansion, it can be represented as [8] (1)

II. DEVICE CHARACTERISTICS Atmel Corporation’s SiGe2-RF is a 0.8- m lithography double-poly hetero-bipolar technology and the minimum 1.4 m (layout size) for vertical npn emitter size is 0.8 HBTs. There are two types of transistors available on the cm substrate. One is called the nonselectively im1000planted collector (non-SIC), which has a lower unity current of 50 GHz and a higher collector–emitter gain frequency breakdown voltage of 4 V, while the other, called an of 80 GHz and of 2.5 V. The transistor SIC, has an GHz is used in both - and -band designs. with This process also offers three metallization layers and resistors to 1.5 k . The nitride camade of poly-silicon from 4 pacitor with the bottom plate made of poly-silicon is available, but a nitride metal–insulator–metal (MIM) capacitor was not released until recently. Therefore, the high-quality nitride MIM capacitor is not used in our designs. 1Atmel SiGe HBT Foundry. [Online]. Available: http://www.atmel.com/ products/SiGeBipolar/

where

is the th harmonic current component (2) odd

(3)

even

(4)

is the maximum current, is the length of the pulse, and and is the period of the fundamental frequency. To maximize the second harmonic current , the conduction duty cycle of each transistor , which makes . Assuming the output matching network has 3 dB of loss and the voltage swing at the collector of is 2 V, in order to generate a 10-dBm output, the second harmonic current needs to be 40 mA and the dc current would be 30 mA (15 mA for each and ). Since the unit gain frequency is a direct function of the collector

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Fig. 4. Simulated conversion gain of Ka-band frequency doubler versus  at the second harmonic frequency.

current density and 0.7–1.5 mA m results in the highest in the Atmel SiGe2-RF process, the optimum size for and will be 10 20 m . These rough calculations are used as a starting point for the computer-aided design (CAD) simulation, and the transistor with 30 m 0.5 m emitter is finally used in the design. Parasitic feedback at the second harmonic is important to the doubler performance because the position of the reflector determines the phase of the reflected signal, which interferes either constructively or destructively with the desired output signal [10], [11]. Fig. 3(a) shows a simplified schematic of the doubling stage in which a lossless 50- transmission line with electrical length at the second harmonic is added to simulate the phase interference effect. Fig. 4 shows the results of sweeping the from 0 to 180 and changing the matching networks correspondingly for maximum gain. The results indicate that when , the parasitic feedback through generates a high loss compared to the optimum value ( or ). In order to maintain the compact size with high conversion gain, the distance between the bases of the doubling stage and reflectors needs to be kept as small as possible and is chosen to be 10 . from In addition to the effect of , the parasitic inductor the emitter to the ground plane also plays a prominent role in the doubler design. Fig. 3(b) shows the simplified schematic with the inductor connected between the emitters and reflectors. By sweeping the value of , the simulated maximum available conversion gain is plotted as denoted by the dashed line in Fig. 5. The gain drops abruptly and is very sensitive to the value of . This phenomenon is due to the degeneration effect of the inductor at the second harmonic frequency. At the fundamental frequency, since the input signals are differential, the emitters of and become a virtual ground, and this removes the effect of . At the second harmonic frequency, the bases of and are grounded through the reflector. When the emitter current flows through , a will be generated, and it causes the collector current to decrease through negative feedback. This problem can be solved by the topology shown in Fig. 3(c). In this case, the emitters are connected to

Fig. 5. Simulated conversion gain of Ka-band frequency doubler versus parasitic inductor L .

TABLE I VALUES OF THE LUMPED COMPONENTS FOR THE REFLECTOR MATCHING NETWORKS IN THE Ka-BAND DOUBLER

Fig. 6. Microphotograph of the Ka-band frequency doubler (0.7 without pads).

AND

2 0.5 mm

the reflector first and then to the output ground that introduces a parasitic . The base and emitter junctions are always shorted at the second harmonic through the reflectors and cannot be generated as increases. The corresponding simulation is shown as the solid line in Fig. 5. The small variation in the conversion gain is because the output impedances of and change slightly with . In order to show how much improvement is due to the cascode stage and reflector, simulations were performed without using them. The results indicate that the cascode topology and

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Fig. 7. Test setup for on-wafer measurement for the -band doubler. The spectrum analyzer is calibrated to a power meter and is accurate to within 0.5 dB.

6

a correctly designed reflector results in an increase of 3.8 and 1.8 dB of the conversion gain, respectively, and a total increase of 7.4 dB using both of them. This shows that these two design issues are essential to high-efficiency doubler performance. The reflector and matching networks are implemented using lumped components. The nitride capacitor (1.1 fF m ) has a bottom plate made of lossy poly-silicon (4 ), which is detrimental to the performance of the -band doubler. Therefore, an oxide capacitor (0.05 fF m ) between metal-1 and metal-2 is used for higher conversion efficiency, although it occupies a larger area. The lumped inductors are also implemented by stacking metal-2 and metal-3 together for higher . The novel reflector architecture presented in Section IV-A can save much area in the -band design, but it does not help much at this frequency since the required inductor value is already small and, therefore, two standard , reflector circuits are used. The harmonic-balance simulation is performed using Agilent’s Advanced Design System (ADS)2 and Sonnet3 is used for passive components modeling. Simulation indicates that the of the differential inductor is 21 at 19 GHz and that of the single-ended inductor is 18 at 38 GHz. The of the oxide capacitor is 40 and 25 at the fundamental and second harmonic frequencies, respectively, as opposed to 20 and 8 for the nitride capacitors. The values of the lumped elements are summarized in Table I.

Fig. 8. Measured PAE and output power in terms of input power and input bias for the -band frequency doubler.

Ka

Fig. 9. Measured and simulated conversion gain of the an input frequency of 16–20 GHz.

Ka-band doubler for

B. Measured Results The microphotograph of the circuit is shown in Fig. 6. Notice that the reflectors are connected to the emitters first, then through the parasitic inductance of the ground to the probe pads. This inductor is minimized by using a thick and wide metal strip, and has a value of approximately 85 pH, as indicated by simulation. The area without pads is 700 500 m . The test setup is shown in Fig. 7. A 180 hybrid is used to transfer the single-ended input signal from the synthesized sweeper (HP 83624A) to a differential output in order to feed in the differential picoprobe from GGB Industries, Naples, FL. , and are connected to the chip using The dc bias of , 2ADS

2003A, Agilent Technol. Inc., Palo Alto, CA, 1983–2003. ver. 9.52, Sonnet Software Inc., Syracuse, NY, 1986–2003.

3Sonnet,

Fig. 10. Measured and simulated output power of the input frequency of 16–20 GHz.

Ka-band doubler for an

a MCW-14 multicontact wedge, and the output signal is measured using a spectrum analyzer (HP 8564E). A back-to-back

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Fig. 11. Measured and simulated output power of the input power of 1–8 dBm.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Ka-band doubler for an

Ku

Fig. 13. (a) Schematic of the -band balanced frequency doubler. (b) Run of the reflector shown at the fundamental and second harmonic frequencies. TABLE II VALUES OF THE LUMPED COMPONENTS FOR THE REFLECTOR MATCHING NETWORKS IN THE -BAND DOUBLER

Ku

Fig. 12. Measured and simulated conversion gain of the an input bias of 0.4 –0.8 V.

AND

Ka-band doubler for

cable–coupler–differential probe and cable–probe are measured on a network analyzer at the first harmonic and second harmonic frequency bands, respectively, in order to determine the loss of the input and output off-wafer networks and correct the power values measured on the spectrum analyzer. The same design was measured on two different chips by sweeping the input frequency from 16 to 20 GHz in 200-MHz steps, the input power from 1 to 8 dBm in 0.25-dBm steps from 0.4 to 0.8 V in 0.05-V steps. The and the input bias measured results are shown in Figs. 8–12. Fig. 8 indicates that an input bias of 0.65 V and input power of 6 dBm results in and dBm with the lowest input a power. This is the optimum operating region of this design and Figs. 8–12 are plotted at this operating condition. Fig. 9 presents the frequency response of the circuit. The doubler has 4.5 dB of gain and a 3-dB bandwidth of 2.3 GHz, which is 13% of the center frequency of 18 GHz. Fig. 10 shows the fundamental rejection performance, and it is better than 35 dB for an input frequency of 17–18.8 GHz. The 180 hybrid from Krytar is used in the measurement and specified to have a phase imbalance of 12 from 6 to 26.5 GHz. The simulation is done with 6 of phase imbalance in order to fit the measured rejection performance in Fig. 10. Fig. 11 shows the output power and dc power consumption verses input power. When the input

power is 6 dBm, an output power of 10.5 dBm is obtained with 114-mW dc power consumption. This results in a PAE of 6.4%. Fig. 12 shows the conversion gain versus base dc voltage, and V results in the optimum perforit indicates that dB . The discrepancy between mance conversion gain the measured and simulation results could be the inaccuracy of the transistor model in the cutoff region. IV.

-BAND FREQUENCY DOUBLER

A. Circuit Design -band doubler is shown in The simplified schematic of the Fig. 13 [12]. The differential input signals are fed into the base and , which are biased near the class-B reof transistors gion in order to generate the second harmonic components efcomponents through ficiently. Due to the feedback of the the base–collector capacitor, a resonator is needed at the base and to reflect the second harmonic signals of transistors back into the doubler circuit for higher conversion gain. In this design, a space-saving reflector is achieved using one inductor and two capacitors . At the fundamental frequency,

HUNG et al.: HIGH-POWER HIGH-EFFICIENCY SiGe

Fig. 14. Microphotograph of the without pads).

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Ku-band frequency doubler (0.720.35 mm Fig. 16. Measured and simulated output power of the input frequency of 6–11 GHz.

Fig. 15. Measured PAE and output power in terms of input power and input -band frequency doubler. bias for the

Ku

the two input signals are out-of-phase, and the reflector presents , which are treated as part of the input two shunt capacitors matching network. At the second harmonic frequency, the components are in-phase, and the reflector is equivalent to two series resonators. Each resonator consists of and and presents a short circuit to increase the conversion efficiency. In a conventional design, two inductors are required and the mutual coupling between them needs to be taken into account. In this compact configuration, only one inductor with half of the inductance value is used and is implemented using a short meandered line, which has a of 7 at 18 GHz. and base bias voltage are The design supply voltage 2 and 0.65 V, respectively. The harmonic-balance simulator in Agilent’s ADS is used for the load–pull simulation in order to find the optimum input and output impedances for maximum conversion gain at the fundamental and second harmonic frequencies, respectively. Lumped L and C components are used to implement the input and output matching networks, as shown in Fig. 13. The lumped inductors are fabricated using metal-3 and the capacitors are implemented as poly/nitride/metal-1 capacitors. All the passive components are simulated in Sonnet, and

Fig. 17. Measured and simulated output power of the input power of 2–3 dBm.

0

Ku-band doubler for an

Ku-band doubler for an

the simulations indicate that the of the differential inductor is 16 at 9 GHz (input port) and that of the single-ended inductor is 10 at 18 GHz (output port). The values of the lumped elements for the reflector and matching networks are summarized in Table II. B. Measured Results The microphotograph of the circuit is shown in Fig. 14. Although the design is not optimized for area, the size is already quite small occupying only 700 350 m . The same design was measured on three different chips by sweeping the input frequency from 6 to 11 GHz in 200-MHz steps, the input power from 2 to 3 dBm in 0.25-dBm steps, and the input bias from 0.4 to 0.8 V in 0.05-V steps. The measured results are shown in Figs. 15–17. Fig. 15 shows the PAE and output power of sample 1 in terms of input power and input bias. This figure shows the optimum operating region are achieved concurrently where the maximum PAE and with the minimum input power. It shows that an input bias of and 0.65 V with input power of 1.5 dBm results in dBm. Figs. 16 and 17 are plotted at this operating condition.

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TABLE III FREQUENCY DOUBLER PERFORMANCES

the SiGe designs have the highest PAE compared to other monolithic doublers, including III–V designs. They also have a wide 3-dB bandwidth, 25-dB fundamental suppression due to the balanced design, and occupy a very small area. VI. CONCLUSION

Fig. 18. Comparison of different frequency doublers in terms of output power (dBm) and PAE (%).

Fig. 16 presents the frequency response of the circuit when the input power is 1.5 dBm. The doubler has 4.5-dB gain and a 3-dB bandwidth of 2.3 GHz, which is 27% of the center frequency of 8.4 GHz. The fundamental rejection performance is greater than 25 dB for an input frequency from 7.6 to 9.6 GHz. Compared to the simulation using the Gummel–Poon model for the transistors, the measured gain is 1.5 dB lower than expected, and the center frequency shifts down approximately 1 GHz. The reason could be modeling inaccuracies in the passive components in the matching and reflector networks. The discrepancy could also come from the inaccuracy of the large-signal model, which is not well known for the 80-GHz transistor. Since the transistors are biased in the class-B region, the dc power consumption is proportional to output power (Fig. 17). When the input power is 1.5 dBm, an output power of 6 dBm is obtained with only 28-mW dc power consumption, and is equivalent to a PAE of 9.2%. The measured results for all three samples are very close and indicate that this SiGe process is quite reliable and consistent. V. SUMMARY Table III and Fig. 18 summarize the performances of our SiGe doublers and other doubler designs. To the authors’ knowledge,

- and -band Monolithic SiGe frequency doublers for applications have been presented. The balanced topology is used for higher output power, broad-band fundamental suppression, and ease of integration with a differential oscillator. The conversion gain was improved through the design of a novel miniature second harmonic reflector at the transistor’s input -band doubler. In addition, the degeneration effect for the of the parasitic inductor is minimized by the careful layout in -band design. The results have demonstrated that SiGe the technology has comparable performance and better efficiency than III–V monolithic designs. ACKNOWLEDGMENT The authors thank Dr. J. P. Lanteri, M/A COM, Lowell, MA, for supporting this program through generous access to the ATMEL mask sets, and Dr. I. Gresham, M/A COM, for technical discussions. REFERENCES [1] C. Fager, L. Landén, and H. Zirath, “High output power, broadband 28–56 GHz MMIC frequency doubler,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2000, pp. 1589–1591. [2] T. Masuda, L. Landén, and H. Zirath, “Low power single-ended active frequency doubler for a 60 GHz-band application,” in Proc. GaAs, Sep. 2002 [CD-ROM]. [3] L. Tran, M. Delaney, R. Isobe, D. Jang, and J. Brown, “Frequency translation MMIC’s using InP HEMT technology,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 1996, pp. 261–264. [4] F. Ellinger and H. Jackel, “Ultracompact SOI CMOS frequency doubler for low power applications at 26.5–28.5 GHz,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 2, pp. 53–55, Feb. 2004. [5] D.-W. Kang, D.-H. Baek, S.-H. Jeon, J.-W. Park, and S. Hong, “A miniaturized -band balanced frequency doubler using InGaP HBT technology,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2003, pp. 107–110. [6] S. Hackl and J. Bock, “42 GHz active frequency doubler in SiGe bipolar technology,” in Proc. 3rd Int. Microwave and Millimeter Wave Technology Conf., 2002, pp. 54–57.

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-BAND BALANCED FREQUENCY DOUBLERS

[7] M. D. Weiss and Z. Popovic´ , “An X=K -band class-E high-efficiency frequency doubler,” in Proc. 31st Eur. Microwave Conf., Sep. 2001, pp. 225–228. [8] S. A. Maas, Nonlinear Microwave and RF Circuits. Norwood, MA: Artech House, 2003. [9] D. G. Thomas and G. R. Branner, “Single-ended HEMT multiplier design using reflector networks,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 5, pp. 990–993, May 2001. [10] C. Rauscher, “High-frequency doubler operation of GaAs field-effect transistors,” IEEE Trans. Microw. Theory Tech., vol. MTT-31, no. 6, pp. 462–473, Jun. 1983. [11] Y. Iyama, A. Iida, T. Takagi, and S. Urasaki, “Second-harmonic reflector type high-gain FET frequency doubler operating in K -band,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 1989, pp. 1291–1294. [12] J.-J. Hung, T. M. Hancock, and G. M. Rebeiz, “A high-efficiency miniaturized SiGe Ku-band balanced frequency doubler,” in IEEE RFIC Symp. Dig., Jun. 2004, pp. 219–222.

Juo-Jung Hung (S’03–M’05) received the B.S. and M.S. degrees from the National Taiwan University, Taipei, Taiwan, R.O.C., in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from The University of Michigan at Ann Arbor, in 2004, all in electrical engineering. He will soon join the Intel Corporation, Hillsboro, OR, as a Senior Circuit Design Engineer. His research interests CMOS/SiGe RFIC and RF microelectromechanical systems (MEMS) for microwave and millimeter-wave applications.

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Timothy M. Hancock (S’96–M’05) received the B.S. degree in electrical engineering from the Rose-Hulman Institute of Technology, Terre Haute, IN, and the M.S. and Ph.D. degrees in electrical engineering from The University of Michigan at Ann Arbor, where he was involved with the development of SiGe integrated microwave components. During the summers of 2000 and 2001, he was involved with a fully integrated global positioning system (GPS) solution and power control circuitry for handset power amplifier applications. In 2004, he was with M/A-COM, where he was involved with the design of SiGe components for an automotive radar solution at 24 GHz. He is currently a Technical Staff Member with the Analog Device Technology Group, Massachusetts Institute of Technology (MIT) Lincoln Laboratory, Lexington, where he is involved with the development of integrated microwave circuits and systems.

Gabriel M. Rebeiz (S’86–M’88–SM’93–F’97) received the Ph.D. degree in electrical engineering from the California Institute of Technology, Pasadena. He is a Full Professor of electrical engineering and computer science (EECS) with the University of California at San Diego, La Jolla. He authored RF MEMS: Theory, Design and Technology (New York: Wiley, 2003). His research interests include applying microelectromechanical systems (MEMS) for the development of novel RF and microwave components and subsystems. He is also interested in SiGe RF integrated-circuit (RFIC) design, and in the development of planar antennas and millimeter-wave front-end electronics for communication systems, automotive collision-avoidance sensors, and phased arrays. Prof. Rebeiz was the recipient of the 1991 National Science Foundation (NSF) Presidential Young Investigator Award and the 1993 International Scientific Radio Union (URSI) International Isaac Koga Gold Medal Award. He was selected by his students as the 1997–1998 Eta Kappa Nu EECS Professor of the Year. In October 1998, he was the recipient of the Amoco Foundation Teaching Award, presented annually to one faculty member of The University of Michigan at Ann Arbor for excellence in undergraduate teaching. He was the corecipient of the IEEE 2000 Microwave Prize. In 2003, he was the recipient of the Outstanding Young Engineer Award of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He is a Distinguished Lecturer for the IEEE MTT-S.

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Influence of Epitaxial Structure in the Noise Figure of AlGaN/GaN HEMTs Christopher Sanabria, Student Member, IEEE, Hongtao Xu, Student Member, IEEE, Tomás Palacios, Student Member, IEEE, Arpan Chakraborty, Sten Heikman, Umesh K. Mishra, Fellow, IEEE, and Robert A. York, Senior Member, IEEE

Abstract—The effect of noise figure of different AlGaN/GaN high electron-mobility transistor (HEMT) epitaxy structures is reported. The addition of a thin AlN layer between the barrier and channel gives better performance at biasings other than the best for minimum noise figure. However, varying Al composition in the HEMT barrier does not change the noise performance, contrary to a 2003 study by Lu et al. The measurements are checked with both the Pospieszalski and van der Ziel (Pucel) models. The models are used on six different samples, helping to reinforce the measurements and showing the strengths and weaknesses of each.

TABLE I COMPARISON OF MINIMUM NOISE FIGURES FOR THE STATE-OF-THE-ART IN VARIOUS MATERIAL STRUCTURES FOR HEMTs. DEVICE GATE LENGTH, MINIMUM NOISE FIGURE, FREQUENCY OF MEASUREMENT, COMMENTS ABOUT THE DATA, AND REFERENCE ARE LISTED, RESPECTIVELY. ALL MEASUREMENTS ARE AT ROOM TEMPERATURE

Index Terms—AlGaN, GaN, high electron-mobility transistor (HEMT), noise figure, Pospieszalski, Pucel, van der Ziel.

I. INTRODUCTION

A

LMOST ANY communication system will have to address signal amplification and noise. In such a system, a gain stage is designed to maximize gain while minimizing the amount of noise it adds. This makes figures-of-merits, such as noise figure, important when choosing a device and a material to integrate the device upon. In developing an integrated solution, there are many material systems to work in. Silicon, GaAs, and InP are more common choices. GaN is presenting itself as a new and attractive option. The biggest benefit is for power amplification. GaN high electronmobility transistors (HEMTs) have breakdown voltages in excess of 100 V. This eliminates the need for protection circuitry, such as in a front-end receiver, making a GaN-based design -band, GaN is curless complex and lower noise [2]. In the rently the only solid-state contender for high-power applications, again, because of its large breakdown voltage. GaN also has respectable electron mobility ( ) and a high peak electron velocity, thus, it is useful at high frequencies. Since these values translate into a good unity current gain ( ) and maximum frequency of oscillation ( ), it also performs well for noise. Table I presents a comparison of noise figures and their measurement frequencies for HEMTs in several solid-state technologies including GaN, GaAs, Si, and InP. The best noise performers are In-related materials. The other technologies perform similarly, including GaN. Manuscript received April 18, 2004; revised July 28, 2004. This work was supported in part by the Office of Naval Research under Contract N00014-010764. The authors are with the Electrical and Computer Engineering Department, University of California at Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840578

Having minimum noise figures less than 1 dB throughout the -band [3] and much higher power densities [4] means AlGaN/GaN HEMTs show promise for low-noise microwave applications. While GaAs-based HEMTs might show marginally better noise figures (1/10 or 2/10 of a decibel), GaN material growth and processing are not mature, and improvements in performance are expected. Only in the last few years have papers been published on microwave noise in GaN HEMTs. The first to do measurements for were Ping et al. in January 2000. The resulting 0.25- m gate-length devices was 0.77 dB at 5 GHz and 1.06 dB at 10 GHz [5], and is comparable to other later results, as shown in Table I. They also claimed comparable noise figures

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TABLE II DATA FROM HALL MEASUREMENTS (SHEET CHARGE CONCENTRATION, AND MOBILITY), S -PARAMETER MEASUREMENTS (BEST f AND f FOR THE DEVICE), AND TRANSMISSION-LINE MATRIX (TLM) MEASUREMENTS (SHEET AND CONTACT RESISTANCES)

Fig. 1. Cross section of the material structure for: (a) samples with varying aluminum mole fraction, (b) sample with AlN interlayer, and (c) SiC substrate sample.

to GaAs HEMTs and metal–semiconductor field-effect transistors. Moon et al. showed that, at a very low-biasing, such as 1 V, noise figures were similar to low-biased GaAs devices [2]. In 2003, Lu et al. varied the aluminum mole fraction of the AlGaN barrier to see if it changed the noise figure, finding that higher Al percentage gave a better noise figure [1]. A few other papers have presented standard noise measurements, most already summarized in Table I [1], [2], [5]–[17]. Here, we will study changes in the HEMT epitaxy to see how it affects the noise performance. Four samples with identical structure, except for varying aluminum mole fraction in the AlGaN barrier, are compared. Unlike an earlier aluminum composition study [1], all samples showed the same against frequency and current. We then present, for the first time, the effect of a very thin aluminum nitride (AlN) layer between the AlGaN and GaN on noise performance. The addition of the AlN layer increases the channel mobility and the two-dimensional electron gas (2-DEG) density as shown by as Shen et al. [18]. It causes a favorable difference in the well. Finally, we verify these results with two transistor noise models, Pospieszalski and van der Ziel (sometimes seen in the Pucel model formulation in the literature). The models are applied to six samples and simulated in Agilent’s Advanced Design System (ADS) software. Using so many samples allows for comparison with the measurements to see how well each model performs. II. DEVICE STRUCTURE AND DEVICE PROCESSING The device structures were grown by metal–organic chemical vapor deposition (MOCVD) on both -plane sapphire and -plane 4H-SiC substrates. The epitaxial structures of the samples appear in Fig. 1. Four of them, represented in Fig. 1(a), consisted of a GaN nucleation layer followed by a semi-insulating Fe-doped GaN buffer layer, and capped by a 29-nm N layer. Four different Al compositions (15%, 25%, Al Ga 27%, and 35%) were constructed with this template. In another sample, shown in Fig. 1(b), a 0.6-nm AlN layer was included between the 29-nm Al Ga N layer and GaN channel. The epitaxial structure of the sample grown on SiC substrate, shown in Fig. 1(c), consisted of an AlN nucleation layer followed by a semi-insulating Fe-doped GaN buffer layer and was capped by a 29-nm Al Ga N layer. The electron mobility and sheet charge concentration from Hall measurements for the samples are in Table II. All samples were identically processed. Source and drain ohmic contacts were created with Ti/Al/Ni/Au electron beam evaporation

Fig. 2. Schematic of the source–pull noise-figure measurement system for noise or S -parameter measurements.

and rapid thermal annealed at 870 C for 30 s. Contact resistance for each sample is also presented in Table II. Device isolation was achieved by reactive ion etching (RIE) in Cl . Stepper photolithography Ni/Au/Ni gates were electron beam evaporated with a nominal gate length of 0.7 m. SiN passivation was achieved with plasma-enhanced chemical vapor deposition. All devices in this paper have a gatewidth of 2 75 m, a gate–source spacing of 0.7 m, and a gate–drain spacing of 2 m. The pads are a coplanar waveguide (CPW) layout. III. PROCEDURE All measurements were performed on-wafer with Cascade-Microtech ACP40 ground–signal–ground CPW probes. -parameters were measured with an HP 8722D vector network analyzer (VNA) at several different device biases. From this, and were collected. The biasing the frequencies for was such as to find independently the best possible and for each device, which are presented in Table II. Noise measurements were performed with a source–pull noise-figure system. A schematic is presented in Fig. 2. Noise was measured with an HP 8970S noise-figure meter with an Agilent 346B noise source. The varying input impedance is generated by a Maury Microwave MT982A02 mechanical motorized tuner. The load tuner was set to 50 . A Maury Microwave MT998C RF switch changes between noise and -parameter measurements. An HP 8722D measures -parameters. The bias was set automatically by an HP 6625A

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System dc power supply. All components were controlled by a general-purpose interface bus (GPIB) by a proprietary Maury Microwave software program. The system was checked with an in-house fabricated CPW attenuator on GaN. Error in noise figure is 0.1 dB. IV. MEASUREMENTS AND ANALYSIS have the largest influence It is well known that and on noise figure [19]. It is, therefore, imperative when comparing and devices from different samples that they have similar . From each sample, two typical devices with similar and were used for all measurements. In the graphs that follow, only the first device from each sample is plotted for clarity. The second device from each sample was measured as a check on validity and only reinforces the data presented. was found for each device. The dc bias for lowest This also helps give a fair comparison among the different declose to pinchoff, vices. The noise bias was found by setting for the best . With set to this new then varying was swept in a coarse 5-mA sweep and value as a constant, then a 1-mA fine sweep to find the bias. It is worth noting that are not the same. the optimal bias for noise, i.e., , and of 4–5 V The best bias for noise was found to typically be and an approximately 10–20 mA. For and , the op7 V and a betimal bias for all devices was typically . The against the tween 20–30 mA, being higher for drain–source voltage is relatively flat [7], thus, plots of it are not included.

Fig. 3. Noise parameters of four devices from similar samples with varying aluminum mole fraction, each biased for lowest noise (as in Table IV). (a) Minimum noise figure. (b) Optimum source impedance (magnitude and phase). (c) Noise resistance (normalized by 50 ). (d) Associated gain.

A. Varying Aluminum Composition Study Measurements of the four samples structured as shown in Fig. 1(a) are plotted in Fig. 3(a)–(d). Here, we see the four noise in (a), : the complex parameters and the gain: the optimum source reflection coefficient (magnitude and phase) in (b), : the normalized (to 50 ) noise resistance in (c), and : the associated gain in (d), respectively. All are plotted against frequency for the 15%, 25%, 27%, and 35% aluminum mole fraction devices. Connecting lines are not a model and are added only as a visual aid to distinguish the data series. Each device as biased for lowest noise performance. increases from approximately 1 to 2.3 dB over the The 4–12-GHz measurements for the devices. This linear trend is common for noise measurements versus frequency. The magnitude of the source reflection coefficient drops from just over 0.8 at 4 GHz to 0.6 at 12 GHz, while the phase of the reflection coefficient increases almost linearly from approximately 18 to 55 over the same range. The overlap of the measurements is very good. The normalized noise resistance fluctuates in the range from approximately 0.7 to 0.9. It is relatively flat, which is an indicator of stability and accuracy in the noise measurements. The associated gains drop off from 15 to 8 dB with increasing frequency at a near 20-dB/decade slope. Differences in associated gain between the devices in Fig. 3(d) are as large as 1.5 dB. While the gain can affect the noise performance, as seen later in (1), the noise figures are still very close in value for all four devices.

Fig. 4. Noise figure versus I of four devices with varying aluminum mole fraction. Measurements made at 5 GHz with V of each device as found in Table IV.

In Fig. 4, we see the same four devices with their plotted against the drain–source current. Each device is plotted up to its maximum current. The measurement frequency is 5 GHz and the drain–source biasings are 4, 4, 4, and 5 V for the 15%, 25%, 27%, and 35% devices, respectively. The overlap

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) versus I of devices with and without an Fig. 6. Noise figure (f and f aluminum–nitride layer. Measurements made at 5 GHz with V that gave the lowest noise measurements.

Fig. 5. Noise parameters of similar devices with and without an AlN layer, each biased for lowest noise (see Table IV). (a) Minimum noise figure. (b) Optimum source impedance. (c) Noise resistance. (d) Associated gain.

of the four devices’ measurements is excellent. Figs. 3 and 4 present a convincing argument that Al composition does not , unlike what was found in [1]. Changing the Al effect the composition will slightly change the barrier height in the band . diagram, the total charge, and the maximum current As shown by modeling in Section V, these changes do not significantly change the small-signal parameters or the noise parameters. Presented in Section IV-B is a parameter that does change the noise figure.

frequency is never more than 0.15 dB, and can be judged a good match. Observing Fig. 6, a difference in noise figure against current as the curis evident. In this plot, the AlN layer is lower in rent increases. Both devices are approximately the same until the current is greater than 20 mA when the device without the AlN layer increases its faster with increasing current. ultiAt 135 mA, this difference is greater than 0.8 dB. mately determines the power gain for the device, which factors directly into the noise-figure definition as

(1)

were is the noise figure, is the signal coming in or going out of the device, is the noise coming in or going out of the device, is the gain, and is the noise added by the device. The gain is defined as (2)

B. With and Without AlN Layer Figs. 5 and 6 show a comparison of noise parameter measurements for a device with and without a very thin AlN layer between the channel and AlGaN barrier. In Fig. 5, we again see , optimum source reflection coefficient (magnitude and phase), noise resistance, and associated gain against frequency. is plotted against drain–source current with In Fig. 6, the 4 V and the device without the AlN layer device biased at 5 V. The measurement frequency is again 5 GHz. the layer at For each bias used for the noise data points, and were measured and also appear in Fig. 6. Many of the same trends are seen here as in the previous plots, with similar values and shapes. The difference is that the device with the AlN layer has slightly less gain, a smaller noise resistance, and smaller optimum source reflection-coefficient phase over the entire 4–12-GHz frequency range than the deagainst vice without an AlN thin layer. The difference in

and the noise out as (3) A larger gain for a given amount of device noise means a lower noise figure. In Fig. 6, we see that the device with the AlN layer and at all currents above 20 mA. maintains a higher is the bias for Note that the intersection of the two devices’ each device’s best noise performance and is where their is the same. The AlN provides better confinement of the 2DEG , as seen in at higher currents. This causes a better and Fig. 6, and, thus, better noise performance. V. MODELING To confirm the results, and to test the accuracy of two noise models, the devices were modeled with the van der Ziel and

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TABLE III EXTRACTED INTRINSIC AND EXTRINSIC SMALL-SIGNAL PARAMETERS WITH EACH DEVICE BIASED AS IN TABLE IV

Pospieszalski methods. Noise modeling of transistors usually follows the two-port formulation of Rothe and Dahlke [20]. The Pospieszalski and van der Ziel models are based on this formula, tion. These models use four measured noise parameters [ , and complex (magnitude and phase)] at one frequency and the -parameters of a device to predict the noise at other frequencies and different source reflection coefficients. -parameters were taken at the best biases for noise performance for each device. Using extrinsic and intrinsic small-signal parameter extraction techniques, as found in [19], [21], [22], the small-signal circuit parameters were determined in ADS and an equivalent circuit constructed for each device. These parameters are listed in Table III with the bias for each device found in Table IV. The top half of the table is the intrinsic parameters and the bottom half is the extrinsic parameters. Smith chart plots of the -parameters from this modeling are verified against measured data in Fig. 7. This comparison for the 35% aluminum mole fraction sample of modeled and measured -parameters was typical and shows excellent agreement. Another popular model is the Fukui model, but it is not considered here because it is based on finding a fitting parameter from measurements and has been shown to not work well above 26 GHz. The reason for this is that the model does not take into account the feedback capacitance and higher order frequency terms [23]. In the van der Ziel model, there is an equivalent noise source at the gate and the drain , as shown in Fig. 8(a). These sources, correlated with the complex variable , generate all the noise that would be found in the intrinsic device. van der Ziel’s formulation was extended by Pucel and Haus. The Pucel formulation would represent van der Ziel’s in terms of three parameters, and [24]. The extrinsic parameter parasitics still generate thermal noise that increase the noise figure [25]. Hillbrand and Russer created a method of extracting the noise

TABLE IV MEASURED NOISE PARAMETERS, VALUES FROM POSPIESZALSKI AND VAN DER ZIEL MODELS FOR ALL SAMPLES. ALL DEVICES HAVE A NOMINAL GATE LENGTH OF 0.7 m AND GATEWIDTH OF 150 m. ALL DATA IS AT A FREQUENCY OF 5 GHz

correlation matrices from noise and -parameter measurements to the noise parameters [26]. This analysis was recently put into a convenient form by Lee et al., which is easy to enter into a computer program [27], [28]. Pospieszalski’s model gives two parameters from the mea, a gate noise temperature, and sured noise parameters: , a drain noise temperature. To predict the noise figure in a small-signal model for a transistor, only the channel and drain–source resistances generate noise at these elevated temperatures, as shown in Fig. 8(b). These two sources of noise are uncorrelated. The equations to find these two parameters are found in [29]. The initial parameters of Pospieszalski and van der Ziel models must be found from measurements at one frequency, allowing prediction at other frequencies. Currently there does not exist an accurate model to go directly from the -parameters to the model parameters. Both models have been implemented in ADS, which calculates the models’ noise parameters from the noise measurements and small-signal parameters, and then simulates for noise. The results are presented in Table IV, which is divided into three sections. The top section lists measurements, at 5 GHz, of the noise with the biasing conditions. Notice the parameters, and agreement of the noise parameters for all samples. This supports the claim that all the different samples are capable of having the . In the middle section of Table IV are listed same best the two noise temperatures found from the Pospieszalski model

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Fig. 8. Small-signal model including noise modeling for: (a) van der Ziel method; the intrinsic model is noiseless while the extrinsic parasitics still generate noise and (b) Pospieszalski method; only the channel and drain–source resistances generate noise. Fig. 7. Measured (circles) and modeled (line) S -parameters showing verification of small-signal modeling. Shown is the 35% aluminum device without an AlN layer biased at V 5 V and I 11 mA. Frequency range is from 500 MHz to 25 GHz.

along with the noise parameters the model predicts when simulated in ADS. The bottom section of Table IV includes the gate and drain noise currents, the complex correlation coefficient for the van der Ziel model, and the noise parameters the model predicted when simulated in ADS. The comparisons made in the following discussion at 5 GHz apply for the models over the entire 4–12-GHz measurement range. The Pospieszalski model gave a drain temperature value that averaged 3700 K and a gate temperature of 493 K. The listed noise figures are within 0.12 dB of the measured values, a good agreement, as the expected error in the measurements was 0.1 dB. The modeled reflection coefficient is also in very good agreement with typically a 0.03 error from the measured value. The modeled noise resistance for the samples is off 0.1. The optimum source reflection coefficient phase is off by a few degrees. The van der Ziel model also did well in predicting the meausually being approximately 0.1 dB too high. The sured modeled phase was excellent, usually being less than 1 from measurements. The modeled reflection coefficient magnitude also corresponds well to the data being only 0.04 in excess. The modeled noise resistance, though, was not correct, as it was from 0.2 to 0.5 over the measured value. Typical drain current noise was 5 10 A Hz and gate current noise of 7 10 A Hz.

Comparing both, one sees that both work well at predicting and optimum source reflection-coefficient magnitude. the Pospieszalski’s model has trouble predicting the phase of the reflection coefficient, while the van der Ziel model has difficulties with the noise resistance. It is worth mentioning that a correlation of a magnitude of 0.8 was predicted here at 5 GHz, as well as in the paper Lee et al. [28]. An assumption of the Pospieszalski model is that the noise sources are uncorrelated. We see this is not always the case. For frequencies well above 10 GHz, and small gate-length devices (0.25 m or less), the correlation might well be close to 1. If the correlation is not 1, though, the Pospieszalski model may give predictions that are not true to the physics of the device. It should also be pointed out that the Pospieszalski model has described in it a limitation given by the inequality (4) being the unnormalized noise resistance and with being the real part of the optimum source impedance. This condition was not met in the modeling above, despite the accuracy of the results. VI. CONCLUSION It has been shown that, against frequency and current, the for AlGaN/GaN HEMTs does not change with aluminum composition in the barrier. This leaves a free variable when designing a device for noise. Other measurements showed, for the

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first time, that at higher currents, a device with a thin AlN layer will have slightly lower noise than does a device without the layer. However, a device with a thin AlN layer can have the same noise as a device without the layer if both devices are biased for best noise performance. This is useful if a design goal for an -band low-noise amplifier (LNA) was to have slightly more power, yet still maintain the same specification on noise figure. These two studies, and the performance seen from In channel devices, as seen in Table I, might suggest that it is the channel material that determines the noise performance. Finally, the Pospieszalski and van der Ziel models were applied to six different devices showing the strengths and limitations of each.

ACKNOWLEDGMENT The authors would like to thank the Office of Naval Research for their continued support of GaN projects at the University of California at Santa Barbara (UCSB). The authors would also like to thank R. Wallace, Maury Microwave, Ontario, CA, for numerous debugging conversations of our source–pull noise figure system.

REFERENCES [1] W. Lu, V. Kumar, R. Schwindt, E. Piner, and I. Adesida, “DC, RF, and microwave noise performance of AlGaN/GaN HEMTs on aluminum concentration,” IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 2499–2503, Apr. 2003. [2] J. S. Moon, M. Micovic, A. Kurdoghlian, P. Janke, P. Hashimoto, W.-S. Wong, L. McCray, and C. Nguyen, “Microwave noise performance of AlGaN–GaN HEMTs with small DC power dissipation,” IEEE Electron Device Lett., vol. 23, no. 11, pp. 637–639, Nov. 2002. [3] W. Lu, V. Kumar, R. Schwindt, E. Piner, and I. Adesida, “DC, RF, and microwave noise performance of AlGaN/GaN HEMTs on sapphire substrates,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 11, pp. 2499–2503, Nov. 2002. [4] A. Chini, D. Buttari, R. Coffie, S. Heikman, S. Keller, and U. K. Mishra, “12 W/mm power density AlGaN/GaN HEMTs on sapphire substrate,” IEEE Electron. Lett., vol. 40, no. 1, pp. 73–74, Jan. 2004. [5] A. T. Ping, E. Piner, J. Redwing, M. A. Khan, and I. Adesida, “Microwave noise performance of AlGaN/GaN HEMTs,” Electron. Lett., vol. 36, pp. 175–176, Jan. 2000. [6] N. X. Nguyen, M. Micovic, W.-S. Wong, P. Hashimoto, P. Janke, D. Harvey, and C. Nguyen, “Robust low microwave noise GaN MODFETs with 0.6 dB noise figure at 10 GHz,” IEEE Electron. Lett., vol. 36, no. 3, pp. 469–471, Mar. 2000. [7] J.-W. Lee, V. Kumar, R. Schwindt, A. Kuliev, R. Birkhahn, D. Gotthold, and S. Guo, “Microwave noise performances of AlGaN/GaN HEMT’s on semi-insulating 6H-SiC substrates,” Electron. Lett., vol. 40, pp. 80–81, Jan. 2004. [8] S. S. H. Hsu and D. Pavlidis, “Low noise AlGaN/GaN MODFET’s with high breakdown and power characteristics,” in 23rd Annu. Gallium Arsenide Integrated Circuit Symp. Tech. Dig., Oct. 2001, pp. 229–232. [9] J. Mateos, D. Pardo, T. González, P. Tadyszak, F. Danneville, and A. Cappy, “Influence of Al mole fraction on the noise performance of GaAs/Al Ga As HEMT’s,” IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 2081–2083, Sep. 1998. [10] H. Kawasaki, T. Shino, M. Kawano, and K. Kamei, “Super low noise AlGaAs/GaAs HEMT with one tenth micron gate,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 13–15, 1989, pp. 423–426. [11] J.-H. Lee, H.-S. Yoon, C.-S. Park, and P. Hyung-Moo, “Ultra low noise characteristics of AlGaAs/InGaAs/GaAs pseudomorphic HEMT’s with wide head T-shaped gate,” IEEE Electron Device Lett., vol. 16, no. 6, pp. 271–273, Jun. 1995.

[12] C. S. Whelan, P. F. Marsh, W. E. Hoke, R. A. McTaggart, C. P. McCarroll, and T. E. Kazior, “GaAs metamorphic HEMT (MHEMT): An attractive alternative to InP HEMT’s for high performance low noise and power applications,” in Proc. Indium Phosphide and Related Materials Conf., May 14–18, 2000, pp. 337–340. [13] H. Rohdin, A. Nagy, V. Robbins, C. Su, C. Madden, A. Wakita, J. Raggio, and J. Seeger, “Low-noise high-speed Ga In As/Al In As 0.1-m MODFETS and high-gain/bandwidth three-stage amplifier fabricated on GaAs substrate,” presented at the 7th Int. Indium Phosphide and Related Materials Conf., May 1995. [14] M.-Y. Kao, K. H. G. Duh, P. Ho, and P.-C. Chao, “An extremely lownoise InP-based HEMT with silicon nitride passivation,” in Int. Electron Devices Meeting Tech. Dig., Dec. 11–14, 1994, pp. 907–910. [15] Y. Ando, A. Cappy, K. Marubashi, K. Onda, H. Miyamoto, and M. Kuzuhara, “Noise parameter modeling for InP-based pseudomorphic HEMTs,” IEEE Trans. Electron Devices, vol. 44, pp. 1367–1374, Sep. 1997. [16] H. C. Duran, B.-U. H. Klepser, and W. Bachtold, “Low-noise properties of dry gate recess etched InP HEMT’s,” IEEE Electron Device Lett., vol. 17, no. 10, pp. 482–484, Oct. 1996. [17] F. Aniel, M. Enciso-Aguilar, L. Giguerre, P. Crozat, R. Adde, T. Mack, U. Seiler, T. Hackbarth, H. Herzog, U. Konig, and B. Raynor, “High performance 100 nm T-gate strained Si/Si Ge n-MODFET,” presented at the Elsevier Solid-State Electronics Conf., Feb. 2003. [18] L. Shen, S. Heikman, B. Moran, R. Coffie, N.-Q. Zhang, D. Buttair, P. Smorchkova, S. Keller, S. P. DenBaars, and U. K. Mishra, “AlGaN/AlN/GaN high-power microwave HEMT,” IEEE Electron Device Lett., vol. 22, no. 10, pp. 457–459, Oct. 2001. [19] P. H. Ladbrooke, MMIC Design: GaAs FET’s and HEMTs. Boston, MA: Artech House, 1989. [20] H. Rothe and W. Dahlke, “Theory of noisy fourpoles,” in Proc. IRE, vol. 44, Jun. 1956, pp. 811–818. [21] M. Berroth and R. Bosch, “Broad-band determination of the FET smallsignal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 38, no. 7, pp. 891–895, Jul. 1990. [22] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new method for determining the FET small-signal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 7, pp. 1151–1159, Jul. 1988. [23] H. Morkoç and L. Lianghong, “GaN-based modulation-doped FET’s and heterojunction bipolar transistors,” in Nitride Semiconductors: Handbook on Materials and Devices, P. Ruterana, M. Albrecht, and J. Neugebauer, Eds. Berlin, Germany: Wiley-VCH, 2003, pp. 608–613. [24] R. A. Pucel, H. A. Haus, and H. Statz, “Signal and noise properties of gallium arsenide microwave field-effect transistors,” Adv. Electron. Electron Phys., vol. 38, pp. 195–265, 1975. [25] A. Van Der Ziel, “Gate noise in field effect transistors at moderately high frequencies,” Proc. IEEE, vol. 51, no. 3, pp. 461–467, Mar. 1963. [26] H. Hillbrand and P. Russer, “An efficient method for computer-aided noise analysis of linear amplifier networks,” IEEE Trans. Circuits Syst., vol. CAS-23, no. 4, pp. 235–238, Apr. 1976. [27] S. Lee, V. Tilak, K. J. Webb, and L. Eastman, “Intrinsic noise characteristics of AlGaN/GaN HEMTs,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, Jun. 2002, pp. 1415–1418. [28] S. Lee, K. J. Webb, V. Tilak, and L. Eastman, “Intrinsic noise equivalent-circuit parameters for AlGaN/GaN HEMTs,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 5, pp. 1567–1577, May 2003. [29] M. W. Pospiezalski, “Modeling of noise parameters of MESFET’s and MODFET’s and their frequency and temperature dependence,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 9, pp. 1340–1350, Sep. 1989.

Christopher Sanabria (S’98) was born in Pasadena, TX, in 1979. He received the B.S. degree in electrical engineering from the University of Notre Dame, Notre Dame, IN, in 2001, the M.S. degree from the University of California at Santa Barbara (UCSB), in 2002, and is currently working toward the Ph.D. degree at UCSB. He has served internships with Delphi-Delco Electronics during the summers of 1998 and 1999, Texas Instruments Incorporated during the summer of 2000, and Agilent Laboratories, Agilent Technologies during the summer of 2003. His research interests include modeling and measurements of GaN HEMTs and analog circuits for noise and power applications.

SANABRIA et al.: INFLUENCE OF EPITAXIAL STRUCTURE IN NOISE FIGURE OF AlGaN/GaN HEMTs

Hongtao Xu (S’03) received the B.S. degree in electronic engineering from Fudan University, Shanghai, China, in 1997, the M.S. degree in electrical engineering from the University of California at Santa Barbara (UCSB), in 2001, and is currently working toward the Ph.D. degree at UCSB. His research interests include design and fabrication of power amplifiers, LNAs, and oscillators in GaN-based HEMT technology.

Tomás Palacios (S’99) received the Telecommunication Engineering degree from the Polytechnic University of Madrid, Madrid, Spain, in 2001, and is currently working toward the Ph.D. degree in electrical engineering at the University of California at Santa Barbara (UCSB). Since 1998, he has been involved with GaN-based devices, initially with the Institute for Systems based on Optoelectronics and Microtechnology (ISOM), in Madrid, Spain, and since 2002, with UCSB. During the summer of 2000, he was a Visiting Scholar with the Microelectronic Group, European Organization for Nuclear Research (CERN). His current research interest focuses on the search of novel GaN-based transistors for millimeter-wave applications. He has authored or coauthored over 45 papers concerning semiconductor devices in international journals and conferences.

Arpan Chakraborty was born in Calcutta, India, in 1977. He received the B.Sc. degree in physics from the University of Calcutta, Calcutta, India, in 1999, the M.S. degree in physical sciences from the Indian Institute of Science, Bangalore, India, in 2002, and is currently working toward the Ph.D. degree in electrical and computer engineering at the University of California at Santa Barbara (UCSB). His research interests includes MOCVD growth and characterization of group-III nitrides for electronic and opto-electronic applications.

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Sten Heikman received the Civilingenjör degree in applied physics and electrical engineering from Linköping University, Linköping, Sweden, in 1998, the M.S. degree in electrical and computer engineering from the University of Massachusetts at Amherst, in 1998, and the Ph.D. degree in electrical and computer engineering from the University of California at Santa Barbara (UCSB), in 2002. He is currently with the Department of Electrical and Computer Engineering, UCSB, where he conducts research on various aspects of group-III nitride semiconductors, including field-effect transistor (FET) structures and epitaxial growth techniques.

Umesh K. Mishra (S’80–M’83–SM’90–F’95) received the B.Tech. from the Indian Institute of Technology (IIT) Kanpur, India, in 1979, the M.S. degree from Lehigh University, Bethlehem, PA in 1980, and the Ph.D. degree from Cornell University, Ithaca, NY, in 1984, all in electrical engineering. He has been with various laboratory and academic institutions, including Hughes Research Laboratories, Malibu, CA, The University of Michigan at Ann Arbor, and General Electric, Syracuse, NY, where he has made major contributions to the development of AlInAs–GaInAs HEMTs and HBTs. He is currently a Professor and the Department Chair at the Department of Electrical and Computer Engineering, University of California at Santa Barbara (UCSB). He has authored or coauthored over 450 papers in technical journals and conferences. He holds nine patents. His current research interests are in oxide-based III–V electronics and III–V nitride electronics and opto-electronics. Dr. Mishra was a corecipient of the Hyland Patent Award presented by Hughes Aircraft and the Young Scientist Award presented at the International Symposium on GaAs and Related Compounds.

Robert A. York (S’85–M’89–SM’99) received the B.S. degree in electrical engineering from the University of New Hampshire, Durham, in 1987, and the M.S. and Ph.D. degrees in electrical engineering from Cornell University, Ithaca, NY, in 1989 and 1991, respectively. He is currently a Professor of electrical and computer engineering with the University of California at Santa Barbara (UCSB), where his group is currently involved with the design and fabrication of novel microwave and millimeter-wave circuits, high-power microwave and millimeter-wave amplifiers using spatial combining and wide-bandgap semiconductor devices, and application of ferroelectric materials to microwave and millimeter-wave circuits and systems. Dr. York was the recipient of the 1993 Army Research Office Young Investigator Award and the 1996 Office of Naval Research Young Investigator Award.

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Deembedding the Effect of a Local Ground Plane in Electromagnetic Analysis James C. Rautio, Fellow, IEEE

Abstract—In electromagnetic analysis of complex planar circuits, it may be necessary to use internal ports, e.g., in locations where surface mount devices might later be attached. These internal ports require a local ground plane for ground reference when access to the global ground reference is unavailable. Even if perfectly conducting, use of such a ground plane still introduces excess phase in the local ground currents. This paper describes how to remove the effect of a lossy or lossless local ground, even including multiple closely spaced ports. Index Terms—Calibration, deembedding, electromagnetic analysis, imperfect ground, low-temperature co-fired ceramic (LTCC), planar circuit, surface mount device (SMD), surface mount technology (SMT).

I. INTRODUCTION

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OST high-frequency and microwave circuit analysis makes use of ports and nodes. A port is two terminals, one terminal arbitrarily designated as the “signal,” the other arbitrarily assigned to be the “ground.” The port voltage is the difference in voltage between the two terminals. There is no inherent requirement that any one ground terminal be at the same potential as any other ground terminal. The concept of a node is used in nodal analysis. The voltage of each node in a circuit is referenced to a single common global ground. Nodal analysis is commonly used to analyze interconnected systems of -port devices. This is possible when all port ground terminals are connected to the same global ground. Thus, the port voltage is identical to the node voltage in nodal analysis. This allows -port devices to be freely incorporated into a nodal analysis of the complete system. It is upon this principle that modern high-frequency and microwave circuit analysis is based. However, due to the increased complexity of microwave circuitry, access to, or even the existence of a global ground cannot be assured. For example, surface mount devices (SMDs) [also known as surface mount technology (SMT)] are in common use on multilayer planar circuits including low-temperature co-fired ceramic (LTCC). With 12 or more layers, the top surface of an LTCC circuit is a considerable distance from any ground plane that might exist at the bottom. The SMD components mounted on the top surface do not have (and do not require) access to the global circuit ground.

Manuscript received April 14, 2004; revised June 20, 2004. The author is with Sonnet Software Inc., North Syracuse, NY 13212 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.840576

Fig. 1. SMDs.

Advanced LTCC circuit with topside internal ports for numerous

Fig. 1 shows an example LTCC circuit. The light top-side metal represents attachment pads for numerous SMD components. Several of the SMD local grounds and local ports are indicated. The complex interconnections beneath the local grounds do not allow access to the global ground. The result of electromagnetic analysis is an -port device (usually scattering, or -parameters as a function of frequency). As in the LTCC example above, the SMD themselves are typically not included in the electromagnetic analysis. Rather, internal ports are located at the SMD pin locations so that modeled or measured data for the SMD can be connected into the LTCC circuit later using nodal analysis. The problem is that these internal ports have no access to global ground, but nodal analysis requires all nodes to be referenced to global ground. A partial solution is to provide the SMD internal ports with a local ground and then to prohibit any later nodal analysis connections between any nodes referencing different grounds, global or local. Connections may be made between nodes referencing the same local ground, and between any nodes referencing global ground, but not between local and global ground referenced nodes. In fact, assigning one ground to be local and another to be global is itself arbitrary. In reality, all grounds are local. Even a perfectly conducting ground introduces delay in the ground return current. This delay, and loss if present, modifies the -port -parameters. If one has access only to the -port current and voltage information, there is no way to differentiate between the effect of the ground and signal current paths.

0018-9480/$20.00 © 2005 IEEE

RAUTIO: DEEMBEDDING THE EFFECT OF LOCAL GROUND PLANE IN ELECTROMAGNETIC ANALYSIS

Fig. 2. Local ground deembedding standard for two local ports includes transmission lines connecting the local ports to the box sidewalls. The box sidewall ports are then deembedded and their reference planes shifted to their mating local ports. A negative number on an internal port indicates positive current flows to the left.

From the viewpoint of the -port data, either the arbitrarily assigned ground or signal path can be considered lossless and delay free, with all the -parameters determined by the other path, and exactly the same -parameters result. The reality that the ground current experiences delay, and may have loss, is not of concern for nodal analysis, as long as the voltage difference between different ground terminals is of no consequence, as in a cascade of lossy transmission lines. When measuring an SMD, the effect of the actual ground current delay and loss is included in the SMD -port data. When using a local ground in electromagnetic analysis, the effect of the local ground current is also included. Since the SMD measurement already includes the effect of the actual ground, we must identify and remove the additional effect of the local electromagnetic analysis ground if we are to achieve an accurate analysis. In addition to the effect of the local ground, there are also fringing fields surrounding each SMD port and fringing field coupling between each port. Since the SMD measurement already includes the actual port discontinuities, the complete coupled -port discontinuity present in the electromagnetic analysis must be removed. Finally, there is coupling between the local electromagnetic analysis ground and the global ground. Since the actual SMD-to-global ground coupling is already included in the SMD measurement, the electromagnetic local-to-global ground coupling must be removed as well. Exactly characterizing and removing the entire effect of the local ground is the topic of this paper. We refer to this deembedding algorithm as general local ground (GLG) deembedding. II. LOCAL GROUND CALIBRATION STANDARD The electromagnetic analysis used in this study [1], [2] makes use of a “double delay” [3] deembedding algorithm for sidewall ports (ports 3 and 4 in Figs. 2 and 3). The double delay is the first application of modern microwave measurement calibration techniques [4] to electromagnetic analysis. The double-delay algorithm is closely related [5], [6] to the short-open-calibration (SOC) deembedding algorithm [7], [8]. This type of deembedding uses a perfect ground (real or virtual) for establishing a perfect (to within the numerical precision used) ground reference for sidewall ports. The deembedding additionally (and optionally) transfers the perfect ground reference to the interior

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Fig. 3. Equivalent circuit of the two-port local ground deembedding calibration standard shows the local ports 1 and 2 polarized so that positive . Ports 3 and 4 are sidewall (external) current flows out of the local ground ports and are polarized so positive current flows out of the sidewall (global) ground.

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of the box along a uniform port connecting transmission line by shifting the reference plane. Establishing this perfect ground reference at the local ports of the GLG calibration standard (ports 1 and 2 in Fig. 2) is critical in achieving full accuracy for the complete GLG deembedding. For this first tier deembedding, only algorithms such as SOC and double delay, which use a perfect ground reference, are recommended. The circuit for the local ground calibration standard (Fig. 2 and 3) shows the deembedded sidewall ports (3 and 4) shifted up to the local ports (1 and 2). There is zero impedance between the signal terminal of each sidewall port and its mating local ground port. The sidewall port ground terminal is connected to global ground. The local port ground terminal is connected to the local ground. Notice that the local ports (1 and 2) cannot be treated as single nodes. If this circuit is to be analyzed with nodal analysis, six nodes are required. Unfortunately, the full six-node information is not available. The electromagnetic analysis provides information only about the difference in voltage between the two terminals of a local port; we do not know the voltage between each terminal and global ground. The direction of positive current for the local ports in circuit , as inditheory (Fig. 3) is away from the local ground cated. In contrast, the direction of positive current in an electromagnetic analysis depends on the physical direction. In Fig. 2, the electromagnetic analysis has positive current flowing to the right. In Fig. 3, port 2 has positive current also flowing to the right, so there is no problem. However, port 1 (in Fig. 3) must have positive current flowing to the left. To change the direction of positive current for port 1 in the electromagnetic analysis to match circuit theory, we just change the sign of the port to 1. This makes the positive current direction for both the circuit of Fig. 3 and the electromagnetic analysis of Fig. 2 the same. If this is not done, then transmission -parameters are shifted in phase by 180 . For this electromagnetic analysis, as displayed in Fig. 2, all ports on the left and top sides of a local ground must have their sign changed. The -parameters of any -port are determined by placing a voltage source on one port, short-circuiting all other ports, and evaluating the resulting current. This can be done even when some of the ground terminals are not connected to global

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Fig. 4. For direct deembedding, the cascading parameters of the embedded DUT are multiplied by the deembedding adapter cascading parameters, thus deembedding the embedded DUT.

ground. For the circuit of Fig. 3, the -parameters are shown in (1) at the bottom of this page. The -parameters for more than two local ports are straightforward with some of the terms in (1) becoming sums. The schematic and (1) are for real conductances to simplify presentation. In general, all terms are complex. We use the symbol to indicate lumped elements and to indicate matrix elements. With knowledge that the signal path for this circuit is lossless and delay free (i.e., the signal terminals of ports 1 and 3 are shorted together, and ports 2 and 4 as well), we conclude that all the -port data is due to the local ground. We can consider to be the local ground, to be the and to be the port-to-port self-fringing fields of each port, to be the local port ground terminal fringing field coupling, to and local ground body to global ground coupling, and be the port signal terminal coupling to global ground. Linear combinations of the -parameters of (1) uniquely determine all of the elements in Fig. 3. Thus, the local ground is characterized. III. DIRECT LOCAL GROUND DEEMBEDDING Once the discontinuity to be deembedded is characterized, it can usually be removed by converting to cascading (e.g., ) parameters and inverting. This yields the “deembedding adapter.” The deembedding adapter cascading matrix is multiplied by the cascading matrix of the device-under-test (DUT). In this case, the circuit to be deembedded, as in Fig. 4. Cascading matrices must be square and have an even number of ports. In the illustrated case, for one local port, the deembedding adapter has two ports and, thus, a 2 2 cascading matrix. However, the DUT can have any number of ports, one or more. In addition, the DUT may have an odd number of ports. Thus, it might appear that we cannot use cascading matrices to connect the deembedding adapter to the embedded DUT. We might be tempted to calculate the deembedding adapter and then somehow apply nodal analysis to connect it to the DUT. This is impossible because, as mentioned above, nodal analysis assumes the voltage of each node is referenced to global ground. We do not have this information for the local ports.

Fig. 5. Both the embedded DUT and deembedding adapter have supplemental ports added to allow any number of DUT ports. The DUT supplemental ports are effectively open circuited when S -parameters are calculated.

Thus, we return to cascading matrices. If we modify both the embedded DUT and the deembedding adapter, we can form two square matrices with an even and equal number of ports. This is done by adding supplemental ports to both the embedded DUT and the deembedding adapter as needed (Fig. 5). Ports are added to the DUT by using nodal analysis to connect a resistor (any nonzero value, 1 shown) from an existing port to the added supplemental port. A 50- resistor is then added from the supplemental port to ground. After deembedding and conversion to -parameters, the 50- resistor combines with the 50- resistor terminating the supplemental port in the -parameter definition. This leaves the supplemental port open so that it has no effect on the other -parameters. When the number of external ports is less than the number of local ports, then supplemental DUT ports must be connected to one or more local ports. Supplemental ports so created by nodal analysis are also local ports, and no special nodal analysis consideration is needed. The deembedding adapter is supplemented by adding through connections until the required number of ports is realized. After the matrices are multiplied, all DUT supplemental ports are ignored, and the effect of the local ground is removed from the DUT. It would seem the deembedding algorithm is complete, except for one final problem. If the local ground is floating, and of Fig. 3 become small (typically at low frequency), then the cascading parameters become poorly conditioned. A simple solution for this problem is to require some kind of physical attachment from local ground to global ground. The attachment can be minimal, high resistance and reactance, as long as it from going to zero. keeps The fact that a nonsingular solution exists is seen by noticing that the -parameters corresponding to the inverted cascading parameters are those of (1) with a sign change. With this change,

(1)

RAUTIO: DEEMBEDDING THE EFFECT OF LOCAL GROUND PLANE IN ELECTROMAGNETIC ANALYSIS

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where are incident wave amplitudes and are reflected wave amplitudes. For more than two ports, and become vectors become matrices. Conversion from -parameters is and

(3)

Fig. 6. By connecting both the embedded DUT and the deembedding adapter in a double-port configuration, the overall cascading matrices become well conditioned even when the local ground and global ground are completely isolated.

all the positive conductances of Fig. 3 become negative. When the circuit of Fig. 3 is cascaded with a mirror image of itself, with all the conductors negative, it is seen that the local ground is not reduced to a perfect short circuit. Rather, the local ground becomes an open circuit and is completely removed from the circuit. The perfect zero-delay zero-loss signal path of the deembedding adapter takes its place. At least graphically, we see that does not cause any fundamental problem. A solution zero must exist that does not involve singularities. IV. DOUBLE-PORT DEEMBEDDING To avoid poorly conditioned cascading matrices, we connect the embedded DUT and the deembedding adapter in a double port configuration (see Fig. 6). Each port of the original -port is connected to two ports, one on either side. In Fig. 6, each of the six labeled ports are drawn as single ports. In general, each illustrated port repre– ports is equal to sents multiple ports. The number of the number of local ports. The number of – ports is also ports equal to the number of local ports. The number of – is the number of external DUT ports (i.e., all DUT ports, except local ports). The total number of ports is twice the number of DUT ports plus twice the number of local ports. After cascading, all ports, and are terminated in open circuits. Ports and except then represent the deembedded DUT. If cascading parameters are used, conversion to -parameters is usually realized by converting first to - or -parameters. However, a common test is to deembed the calibration standard. In this case, there are open circuits between local ports. This results in undefined -parameters. There are also short circuits between the sidewall and deembedded local ports. This results in undefined -parameters. In order to successfully deembed the standard, the -parameters can first be converted from current/voltage to incident/reflected waves, and then to -parameters. - or -parameters cannot be intermediate results. Rather than convert to wave variables after cascading, we work with wave variables throughout. The wave-variable equivalent of the cascading matrix is -parameters [9] as follows: (2)

ports by first This conversion is more easily realized for columns with the left columns. swapping the right Then perform a partial matrix inversion, solving only the last rows. Gaussian elimination routines are easily modified to do a partial solve. Such routines usually have an integer array that keeps track of which rows have been solved. To solve the rows only, initialize that array to indicate that the first last rows have already been solved. To convert from - back to -parameters, reverse the steps. Do a partial solve on the last rows, and then swap columns. Alternatively,

(4)

In order to insert the deembedding adapter into the doubleport connection of Fig. 6, we must first determine the -parameters of the deembedding adapter. Normally, one would convert the -parameters of the calibration standard to cascading parameters, invert the cascading parameter matrix, then convert back to -parameters. However, we cannot use cascading pa) for this task due to the probrameters (neither , nor of Fig. 3 becomes small. lems with poor conditioning when Prior to deembedding, the -parameters of the calibration standard still exist. Thus, we convert to -parameters and then change the sign of each -parameter. We then convert back to -parameters. This process converts the -parameters of the calibration standard into the -parameters of the deembedding adapter without using cascading parameters. The -parameters for the deembedding adapter inserted into the double-port connection on the right-hand side of Fig. 6 are

(5) As in Fig. 6, each of the indicated ports may actually represent multiple ports, making each matrix element above into matrices themselves. are the -parameters of the deembedding adapter with an additional 50- resistor connected from each port to ground [see Fig. 7(a)]. This provides all the -parameters in (5), except . the terms like . This term is determined by a source One such term is generating a wave exiting port with all ports teron port minated in 50 . The deembedding adapter places a shunt adthrough line, as shown in Fig. 7(b). mittance across the –

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Fig. 7. Adding shunt 50- resistors to each port of the deembedding adapter: (a) allows calculation of most of the double-port S -parameters. The remaining S -parameters require consideration of the S -parameters of (b).

Given the shunt admittance (which, in general, is a matrix) , of the circuit of Fig. 7(b) as follows: we are interested in (6)

Fig. 8. Deembedded DUT compares well with a reference 3.0-mm-long line. The comparison with the embedded DUT shows the effect of deembedding the local ground.

The shunt admittance is the input admittance of the two-port of Fig. 7(a) with the extra 50- resistor on the input removed as follows: (7) Substitution of (7) into (6) yields the desired -parameter terms cause the double-port connected for (5). These deembedding adapter cascading matrix to be well conditioned even when the deembedding adapter cascading matrix itself is not. In a similar manner, the DUT is inserted into a double-port connection, as shown in the left-hand side of Fig. 6. The only difference is that the external port related -parameters are in the third and sixth rows and columns. The second and fifth row/columns are filled with zero and unit matrices. Once the double-port DUT and deembedding adapter -parameters are complete, they are both converted to -parameters by (2) and multiplied in either order. The result is then converted and back to -parameters by (4). Finally, all ports, except , are terminated in open circuits. If we order and partition and ports are together the resulting matrix so that all the , we have the deemin the last row/columns in the matrix bedded DUT as (8) where is one component of the partitioned double-port matrix, and is the desired deembedded DUT. V. VALIDATION As mentioned above, an easy initial test is to deembed the calibration standard. The double-port deembedding yields a zero-loss zero-delay (to within numerical precision) multiport through in all cases tried. The next test is to use as a DUT the calibration standard modified by setting the sidewall port reference planes to zero length. With this modification, the DUT now includes the transmission lines connecting the sidewall ports to the local ports. This allows us to deembed a DUT different from the calibration standard, providing a more rigorous validation.

Fig. 9. In spite of using a lossless local ground in one case and a 10-k

per square local ground in another case, deembedding the local ground yields S -parameters that are identical to within the noise floor of the underlying electromagnetic analysis.

For this type of validation, we use the calibration standard of Fig. 2. The transmission line is 0.5-mm wide, the port 1 connecting line (left side) is 1.75-mm long, the port 2 connecting line is 1.25-mm long, and the local ground (near the center) is 1.0-mm long. The substrate has a relative dielectric constant of 10.0 and is 0.25-mm thick. There are 25 mm of air above the substrate. The box is 4.0 2.0 mm and is divided into 64 cells along its length and 32 cells across its width. The circuit is lossless. The DUT is the same as the calibration standard, except the reference planes are set to zero length. After deembedding, the local ports are shorted together using nodal analysis. The results (Fig. 8) are compared to an electromagnetic analysis of a similar line with the local ground removed; the line is 3.0-mm long. There is some difference at the high end of the frequency range; this is due to the difference in box length in the DUT and the reference circuit. To show the effect of deembedding, the embedded DUT with local ports shorted together is also shown. To provide an exact test of validity, we analyze this same DUT for two different local grounds. The first local ground is as above and is lossless. The second has only the local ground resistivity changed from 0 to 10 k per square. While this is a radically different local ground, it should give the same answer after deembedding. Fig. 9 shows the magnitude

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of the vector difference between the resulting -parameters and difference averaged). ( In spite of the extreme difference in local grounds, the difference in -parameters shows the noise floor of the deembedding procedure to be about the same as that of the underlying electromagnetic analysis, in this case, approximately 160 dB. If the test of Fig. 8 is repeated using the embedded 10-k local ground DUT (no GLG deembedding), an open circuit results. VI. FAILURE MECHANISMS The double-port GLG deembedding fails if the first tier deembedding, removing the local-to-sidewall port connecting lines, fails. The well-understood failure mechanisms of the first tier deembedding occur when the port connecting lines allow more than one propagating mode, and when the reference plane is so short that the fringing fields from the ports at each end interact. Good microwave design avoids the first failure mode. Keeping reference planes and port connecting line lengths longer than one or two substrate thicknesses or line widths (whichever is shorter) is usually sufficient to avoid the second failure mode. In addition, the first tier deembedding fails when box resonances are excited. The double-port GLG deembedding can tolerate very high resistance ground planes, but does fail if the ground resistance is too high. This is typically not a consideration unless the local ground is several electrically noncontacting areas. In this case, a low-frequency failure is seen as the coupling between the disjoint areas becomes small. As mentioned above, GLG deembedding requires an essentially perfect short circuit in the calibration standard between the sidewall and local ports. To test the degree of sensitivity, we intentionally set the sidewall port reference planes back 0.0625 mm from the local ports (1/8th of a linewidth, one cell length) and repeated the deembedding using this “bad” calibration standard. The validation test of Fig. 8 was repeated. The general shape of the curve is the same; however, the entire response is stretched up in frequency. For example, the zero at 18.5 GHz moves up over 5% to 19.5 GHz. The GLG deembedding fails if the local ground current due to coupling with the DUT (not accounted for in the calibration standard) becomes large compared to the other local ground currents. This is not a problem for typical fringing field coupling; however, if the DUT is electrically connected to the local ground in a manner not included in the calibration standard, then the deembedding can fail. This is because the DUT has significantly changed the local ground making the calibration standard inappropriate for the DUT. The deembedded DUT local ports are typically referenced to global ground. However, if the local ground currents induced by coupling from the DUT (not present in the calibration standard) become stronger than the local-to-global ground coupling ( in Fig. 3), then the DUT local ground is no longer attached to global ground. Even so, it still behaves as a perfect floating ground. If it is desired to have the local ground referenced to global ground, then one can supplement with an additional physical connection to the global ground. This would be required only if it is desired to make nodal analysis connections

Fig. 10. Poorly conditioned cascading matrix used in the direct GLG deembedding sometimes results in noisy data, unlike the double-port GLG approach. Note the very low frequency.

between the local ports and any external ports, which is a rare situation. As mentioned above, the direct GLG deembedding can fail when analyzing a floating ground. This is due to the poorly conditioned cascading matrix. We have not explored this problem in detail; however, we do know that the problem increases in magnitude when there are a large number of ports. It is also most prominent at low frequencies. The most peculiar aspect of the problem is that it can be clearly present in some -parameters, but not at all in others, all in the same analysis. We have found no pattern or explanation for this. To illustrate the problem, we modify the DUT used in the above validation tests by adding six through lines, each 0.125-mm wide, separated by 0.0625 mm, three on each side. The resulting 16-port DUT is deembedded by both the double-port GLG and the direct GLG. All the double port data and approximately 80% of the direct deembedded data are good. The rest of the direct data are noisy at low frequency. The direct data are either noisy or smooth, and there does not seem to be any kind of transition between the two states. In Fig. 10, the same -parameter is shown in both cases, one calculated using the double-port GLG and the other using direct deembedding. They both use the same DUT and calibration standard data. Note the low-frequency range. Fig. 10 shows . A similar plot of shows good data, further suggesting the noise is a numerical artifact of the poorly conditioned cascading matrix. It is possible that a carefully designed matrix solve and matrix multiply could reduce or eliminate the noise, especially if it is specialized to symmetric matrices. However, the preferred solution is to avoid the problem completely by using the double-port approach to GLG deembedding. VII. CONCLUSION A GLG deembedding procedure that provides complete characterization of a local ground and the removal of its effect from electromagnetic analysis data has been presented. This technique is useful when combining electromagnetic and nodal analysis for the analysis of SMDs on multilayer planar circuits.

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ACKNOWLEDGMENT The author extends special thanks to J. Merrill for suggesting the form of the calibration standard and for his patient requests over many years for a solution to this problem.

[8] V. I. Okhmatovski, J. Morsey, and A. C. Cangellaris, “On deembedding of port discontinuities in full-wave CAD models of multiport circuits,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 12, pp. 2355–2365, Dec. 2003. [9] D. M. Kerns and R. W. Beatty, Basic Theory of Waveguide Junctions and Introductory Microwave Network Analysis. New York: Pergamon, 1967.

REFERENCES [1] J. C. Rautio, “A time-harmonic electromagnetic analysis of shielded microstrip circuits,” Ph.D. dissertation, Elect. Eng., Dept., Syracuse Univ., Syracuse, NY, 1986. [2] J. C. Rautio and R. F. Harrington, “An electromagnetic time-harmonic analysis of shielded microstrip circuits,” IEEE Trans. Microw. Theory Tech., vol. MTT-35, no. 8, pp. 726–730, Aug. 1987. [3] J. C. Rautio, “A de-embedding algorithm for electromagnetics,” Int. J. Microwave Millim.-Wave Computer-Aided Eng., vol. 1, no. 3, pp. 282–287, Jul. 1991. [4] R. R. Pantoja, M. J. Howes, J. R. Richardson, and R. D. Pollard, “Improved calibration and measurement of the scattering parameters of microwave integrated circuits,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 11, pp. 1675–1680, Nov. 1989. [5] J. C. Rautio, V. I. Okhmatovski, J. Morsey, and A. C. Cangellaris, “Comments on ‘On deembedding of port discontinuities in full-wave CAD models of multiport circuits’,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 10, pp. 2448–2449, Oct. 2004. [6] V. I. Okhmatovski, J. D. Morsey, and A. C. Cangellaris, “Authors’ reply,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 10, pp. 2449–2450, Oct. 2004. [7] L. Zhu and K. Wu, “Unified equivalent circuit model of planar discontinuities suitable for field theory-based CAD and optimization of M(H)MICs,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 9, pp. 1589–1602, Sep. 1999.

James C. Rautio (S’77–M’78–SM’91–F’00) received the B.S.E.E. degree from Cornell University, Ithaca, NY, in 1978, the M.S. degree in systems engineering from the University of Pennsylvania, Philadelphia, in 1982, and the Ph.D. degree in electrical engineering from Syracuse University, Syracuse, NY, in 1986. From 1978 to 1986, he was with General Electric, initially with the Valley Forge Space Division, then with the Syracuse Electronics Laboratory. During this time, he developed microwave design and measurement software and designed microwave circuits on alumina and on GaAs. From 1986 to 1988, he was a Visiting Professor with Syracuse University and Cornell University. In 1988, he joined Sonnet Software, Liverpool, NY, full time, a company he had founded in 1983. In 1995, Sonnet Software was listed on the Inc. 500 list of the fastest growing privately held U.S. companies, the first microwave software company ever to be so listed. Today, Sonnet Software is the leading vendor of three-dimensional planar high-frequency electromagnetic analysis software. Dr. Rautio was the recipient of the 2001 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Microwave Application Award.

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Wide Tuning-Range Planar Filters Using Lumped-Distributed Coupled Resonators Bruce E. Carey-Smith, Paul A. Warr, Mark A. Beach, Associate Member, IEEE, and Tayfun Nesimoglu

Abstract—This paper describes a discretely tunable filter topology based on lumped-distributed coupled transmission lines, particularly suitable for microelectromechanical systems switching devices. This topology is capable of simultaneous wide-band center frequency and bandwidth tuning, limited only by the electrical size of the transmission lines and the placement density of the switching devices. Low fractional bandwidths can be achieved without the need for large coupled-line spacings due to the antiphase relationship of the lumped capacitive and distributed electromagnetic coupling coefficients. The positions of the additional poles of attenuation due to the lumped capacitive coupling can be selected either above or below band leading to the choice of a narrow bandwidth design having good high-side performance or a design with compromised upper stopband performance, but with no bandwidth tuning limitations. The interaction between a pair of lumped-distributed coupled transmission lines is analyzed and the resulting model is used to develop a filter synthesis procedure. The synthesis procedure and filter performance are validated through theoretical and experimental comparisons using a filter with low-side attenuation poles. Index Terms—Discrete tuned, filter synthesis, lumped-distributed coupled transmission lines, microelectromechanical systems (MEMS), microwave bandpass filters, tunable filters.

I. INTRODUCTION

I

NVESTIGATION into the implementation of software reconfigurable radio has highlighted the importance of flexible receiver front-end filtering [1]. In order to take advantage of a diverse range of wireless channels and standards, a wide range of frequencies and bandwidths should be selectable. A single reconfigurable filter capable of operating over the complete range is likely to offer significant savings in terms of size and system complexity. The continuing maturation of RF microelectromechanical systems (RF MEMS) has led to the possibility of wide-range tunable filters with low current consumption, low distortion, and potentially low cost. These devices have been used as alternative tuning elements in filters traditionally tuned using varactor and p-i-n diodes, but they have also prompted the design of new tunable filter topologies. The use of RF MEMS as the tuning elements in lumped-element filters has been demonstrated [2]–[5]. Due to the lack of high- MEMS-tunable inductors, the majority of these designs use lumped air-core inductors, the tuning being done using Manuscript received April 23, 2004; revised July 30, 2004. This work was supported in part by the European Union under the Information Society Technologies Project IST-2001-34091. The authors are with the Centre for Communications Research, University of Bristol, Bristol BS8 1UB, U.K. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.841221

Fig. 1. Lumped-distributed quarter-wave coupled resonators. From [10].

MEMS capacitors. Octave center frequency and 6 : 1 bandwidth tuning ranges have been reported [5]. RF MEMS have also been used to tune distributed filters. The center frequency of this class of filter can be altered by direct physical transmission-line length adjustment [6] or by the indirect capacitive loading of the resonant transmission-line elements [7], [8]. Bandwidth tuning is less common in planar filters due to the difficulties of adjusting the inter-resonator coupling. Tunable lumped-element coupling tends to alter the characteristics of the resonators, obligating the additional control of their resonant frequency [9]. Center frequency and bandwidth tuning by independent control of attenuation poles has been successfully demonstrated, however, the frequency dependence of the quarter-wavelength impedance inverters placed a severe limitation on the center-frequency tuning range of the design [8]. This paper investigates a wide center-frequency and bandwidth tuning range filter utilizing lumped-distributed coupled transmission-line resonators. The coupled resonator structures employed are particularly suitable for use with RF MEMS contact and capacitive switches. They allow wide range tuning of both the resonant frequency and coupling coefficient, limited only by the electrical size of transmission lines and the placement density of the RF MEMS devices. Futhermore, the use of multiple distributed tuning elements results in a flexible strucremains independent of ture where the resonator unloaded the tuning mechanism [10]. In order to achieve this, a modified combline topology is adopted, consisting of pairs of grounded quarter-wavelength coupled resonators whose input and output terminals are at the same end. The structure becomes tunable by incorporating switchable coupling capacitors and switchable ground connections along the length of the resonator lines (Fig. 1). The advantages of this topology are threefold: firstly, only a single grounding switch is in-circuit regardless of the selected length, therefore, the impact of resistive switch losses remains constant. Secondly, it retains a on the resonator constant overlap region and coupling factor regardless of the coupled-line length. Finally, because the electromagnetic (EM)

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coupling between the transmission lines is antiphase to the lumped capacitive coupling, very low coupling coefficients can be obtained regardless of coupled-line spacing. Using mathematical models developed in Section II, the coupling coefficient and transmission characteristics of the structure can be analyzed. The lumped-distributed capacitive coupling introduces an additional attenuation pole and it is shown that the antiphase relationship between the modes of coupling allows this pole to be placed either above or below the primary passband. A filter synthesis technique based on these models is introduced in Section III. Using this technique, the initial filter parameters can be derived from standard filter prototype values. The tuning performance of the filter is presented visually and discussed in Section IV. The theoretical filter performance and synthesis procedure are then verified through the design and measured results of a third-order lumped-distributed coupled-line filter realized in coplanar waveguide. II. LUMPED-DISTRIBUTED COUPLED LINES A pair of lumped-distributed coupled lines is shown in Fig. 1 having a per-unit-length coupling capacitance

Fig. 2. Lumped equivalent circuit of coupled transmission lines.

and are the self-capacitance and inductance of one where of the lines and and are the mutual capacitance and inductance between the coupled lines. Equations (3) and (4) can be rearranged to find the value of the equivalent lumped-circuit elements

(1) (5) and a coupled region length (2) (6) A. Mathematical Circuit Model A mathematical model of the lumped-distributed coupled-line section can be derived in several ways. A model that describes the true periodic nature of the lumped-distributed structure can be derived by using a combination of periodic and evenand odd-mode circuit analyses. However, it is also possible to model the circuit as purely distributed, leading to greatly simplified equations. A lumped-distributed structure exhibits its first stopband when its guided wavelength approaches the periodic spacing of the lumped components. At well below this stopband, the structure can be accurately approximated as purely distributed. This is the approach taken here. A pair of coupled lines can be described in terms of their even) and phase and odd-mode characteristic admittances ( , ). In the quasi-static case, these even- and velocities ( , odd-mode parameters can be represented in terms of equivalent lumped per-unit-length inductances and capacitances, as shown in Fig. 2 [11]. The relationships are

Additional inter-line coupling capacitance will have no and, as a consequence, effect on the parameters , , and the even-mode parameters and will remain unchanged. However, the odd-mode parameters will be affected and, by and can be exmaking use of (3)–(6) the new values pressed in terms of the original odd-mode parameters and the . The result additional per-unit-length coupling capacitance is (7) and (8) The admittance parameters of a symmetrical two-port network are related to the even- and odd-mode input admittances by the following two expressions: and

(9)

(3)

Since the one-port even- and odd-mode input admittances of the lumped-distributed coupled-line model both have the form

(4)

(10)

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end-shorted coupled lines terminated in a source and load admitcan be found from (11) and (12) as tance (14)

Fig. 3. Coupling coefficient of lumped-distributed coupled lines indicating that the capacitive coupling is in antiphase to the EM coupling.

where are the even- or odd-mode coupled-line phase lengths, the two-port admittance parameters can be written as

(11) and (12) where

Poles of attenuation occur when the denominator of (14) is equal to zero. This condition is satisfied when . For purely distributed same-end-grounded coupled lines in a nonhomogenous medium, the condition for a pole of attenuation is met only at dc. Complete transmission corresponds to zeros in the numerator, which occur when either or equal . This indicates that the primary passband is centered between the even- and odd-mode quarter-wavelength frequencies, its width being dependent on the ratio of to and . Further passbands occur at all odd harmonic frequencies. introduces an additional attenThe lumped capacitance uation pole. At low values of capacitance, where the coupling is still primarily magnetic, the pole appears above the primary passband. As the capacitance is increased, the pole frequency reduces until the pole and zero frequencies coincide and the primary passband disappears. The value of capacitance at which this occurs can be found by substituting (5) and (6) into (13) . This value corresponds to the point of graand setting dient change in Fig. 3 and is given by

is the angular velocity and is the coupled-line length.

B. Coupling Coefficient Analysis Using the formulation developed in [12], the coupling coefficient of the lumped-distributed coupled-line structure can be found from its simulated frequency response. Typical results are shown in Fig. 3 where the coupling coefficient for a pair of coupled microstrip lines is plotted against the total lumped capacitance for various values of coupled-line spacing . The change in gradient of the coupling coefficient, from negative to positive, is indicative that, for this coupled-line configuration, the distributed EM coupling is primarily magnetic in nature and is in antiphase to the direct capacitive coupling. The result is that, at low values of lumped coupling capacitance, the coupling coefficient is actually reduced, allowing the coupling coefficient and, therefore, the filter bandwidth, to be controlled down to a very low value without the need for large coupled-line spacings. The electric and magnetic coupling coefficients are the ratio of coupled-to-stored electric and magnetic energy. In the quasistatic case, they can be derived from the capacitance and inductance elements of the lumped equivalent circuit. Summing the two yields the total mixed coupling, which, for this configuration, takes the form (13)

C. Transmission Characteristics Using two-port circuit analysis, the ratio of input-to-output voltage or voltage attenuation function for a pair of same-

(15) When the lumped capacitance is larger than this value, the pole appears below the primary passband. Accordingly, two regions of variable coupling coefficient can be defined above and below . Using adjustable lumped capacitance in the lower region results in a bandwidth tunable filter with better high-side rejection. However, the maximum achievable bandwidth in this case occurs when the lumped capacitance is set to zero and will be dictated by the EM coupling that can be achieved. The maximum amount of EM coupling that can be obtained from a pair of same-end-grounded coupled lines is limited by the degree to which the structure supports unequal odd- and even-mode wave velocities. In practice, this will limit the use of the high-side pole variant to narrow-band filters. However, using adjustable coupling capacitance in the second ), although giving compromised upper stopregion (above band performance, does lead to a design where the maximum bandwidth is limited only by the capacitance value. III. SYNTHESIS A technique for deriving filter design equations is described in [13]. It is based on Cohn’s direct-coupled filter synthesis technique [14]; however, rather than relying on the derivation of expressions for the inverter and resonator slope parameters, it simply compares the admittance and phase of sections of the filter to be designed with those of a generic inverter-coupled filter, forcing the two to correspond at specific points in the filter passband. The interior sections of the filters are described and compared in terms of their image parameters, while the end sections are compared by defining an admittance seen looking

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directly from the two-port -parameter expressions derived in Section II by using the following relations: (19) (20) The admittance the -parameter

of the end sections can be obtained by using -network equivalent circuit (21)

A. Conditions of Correspondence for Interior Sections

Fig. 4. (a) Generic inverter-coupled filter circuit and (b) lumped-distributed coupled-resonator filter circuit divided into symmetrical sections.

through them toward the source. This method is useful for filter circuits where the inverter and resonator functions cannot be mapped directly to those of the generic inverter coupled filter. The circuit divisions of the generic inverter-coupled filter are shown in Fig. 4(a), where the sections are indicated by labels – . The circuit is a modified form of the standard filter prototype circuit, which uses only one kind of reactive element to . The admittance along with admittance inverters inverters are assumed to be ideal and frequency independent. and phase for the inteThe image admittance ) are rior sections of the modified prototype circuit ( – given by

When relating the lumped-distributed coupled resonator filter to the modified prototype, the use of the parameter correspondences from [13] leads to an error in the center frequency and bandwidth of the resultant filter. This error is caused by the asymmetric passband response of the lumped-distributed coupled-line circuit and is proportional to the value of capacitive coupling. The correspondence can be improved through the use of a frequency-mapping function derived by equating the image phase of the two circuits (17) and (20) as follows:

(22)

where is the new scaled frequency variable. The interior sec– of the modified prototype are then related to tions the interior sections – of the coupled-line circuit by forcing the following correspondences: (23) (24) (25)

(16) (17) under the condition that the capacitors , where is an is the terminating conarbitrary admittance scaling factor, ductance, and are the low-pass filter prototype element is the angular frequency of the low-pass protovalues, and rad. The admittance type filter having a cutoff frequency , needed to relate the end sections of the filters, is defined by looking at the source through the end section of the modified , prototype circuit, as shown in Fig. 4(a). Given that it is easily seen that

(18) The division of the lumped-distributed coupled-resonator filter into symmetrical sections is shown in Fig. 4(b). Each of the sections consists of a single pair of coupled resonators. The image admittance and phase can be found

is the value of the scaled frequency variable from where (22) corresponding to , and and are the lower and upper band edge frequencies related to the band center freand fractional bandwidth by quency and

(26)

The effect of these correspondences is to force the correct phase conditions at the band edges of the coupled-line section, while at the same time, ensuring that the image admittance is the correct value at the electrical band center (where ). Solving the three resulting equations simultaneously for given , , , , , and yields a solution values of , in terms of the coupled-line length , coupling capacitance , and the admittance scaling factor for each interior section. The admittance scaling factor must be held constant throughout the filter. When the number of interior sections exceeds two, this no longer occurs coincidentally, and the interior sections must be solved in an iterative manner; firstly,

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Fig. 5 also illustrates the improvement in upper stopband attenuation using the high-side attenuation pole. IV. TUNING ANALYSIS

Fig. 5. Response of an ideal fifth-order synthesized lumped-distributed coupled-resonator filter (solid line) compared to the prototype filter response (broken line). Additional poles of attenuation: (a) above and (b) below the passband.

to find the required value of to give reasonable admittance levels and, secondly, for the coupled-line parameter values for each of the interior sections. B. Conditions of Correspondence for End Sections The end sections and of the modified prototype are related to their corresponding coupled-line end sections – by forcing the following correspondences: (27) (28) is the electrical band center derived from the intewhere rior sections. The first correspondence ensures that the electrical band center for the end sections aligns with that of the interior sections, while the second correspondence forces the correct admittance transformation level into and out of the filter. As with the interior sections, the two resulting equations can be solved simultaneously using numerical methods and a solution found in terms of the coupled-line length and coupling capacitance for given values of , , , , , , , and . Once the design values for the individual sections have been found, the complete filter can be constructed by connecting the near-side resonators of adjacent sections to form a series of halfwavelength resonators coupled to each other along half their length. The filter differs from a quarter-wave combline topology in this respect, but the difference is necessary in order to accommodate the grounded MEMS switches. Unfortunately, the resulting structure supports passbands at all harmonic frequencies. This can be observed in Fig. 5, where the responses of an ideal fifth-order lumped-distributed coupled resonator filter are plotted with the poles of attenuation placed above and below the passband, respectively.

Using the equations developed in Section III, a filter can be designed from a number of lumped-distributed coupled-line sections. Solving these equations results in specific values of coupling capacitance and line length for a given filter center frequency and fractional bandwidth. Once these initial design values have been selected, the filter is tuned by the discrete switching of ground connections and coupling capacitors. Since the tuning is not continuous, only certain values of center frequency and bandwidth can be obtained. Furthermore, the relationships between coupling capacitance, resonator length, fractional bandwidth, and center frequency are not linear. From (3) and (4), it is clear that the coupling capacitance acts to reactively load the transmission lines, altering their odd-mode characteristic impedance and phase velocity. As the coupling capacitance is tuned, the effective phase velocity and, consequently, the resonant frequency of the transmission lines is altered. However, this change in phase velocity is not consistent throughout the filter. To achieve the impedance transformation required in practical transmission-line filters, the coupling capacitors of the filter end sections must be significantly larger than those of the interior sections. Changing the bandwidth involves scaling the inter-resonator coupling throughout the filter and the disproportionate size of the end section coupling capacitors means that their scaling has a greater effect on the phase velocity. This leads to a misalignment of end and interior section resonant frequencies, ultimately distorting the filter shape. Continuously variable resonator lengths could compensate for this by incremental adjustment; however, this is not possible in the discrete design. The result is that a good filter shape is only available at certain tuning points. In order to gain an appreciation of this effect, it is helpful to plot the points where good filter shape can be achieved on the two-dimensional tuning surface of the lumped-distributed coupled resonator filter; fractional bandwidth versus center frequency. To do so, a measure of a particular tuning point’s deviation from the desired filter characteristics is required. One way of expressing this deviation is to determine the line length and coupling capacitance of each filter section required for a particular fractional bandwidth and center frequency. The deviations of each of these length and capacitance values from the available discrete values can then be combined to give an overall error value. Plotting this error value on a contour plot versus center frequency and bandwidth gives a visual representation of the tuning performance of a particular filter. As an example, the error contour plot for the experimental filter to be introduced in Section V is shown in Fig. 6. The experimental filter has four lumped-distributed coupled-line sections and eight length and capacitance parameters. Due to the filter symmetry, only four of these are needed to find the overall error. This error value will vary between zero, for a perfect filter shape, and two, for maximum error. In the latter case, every length and capacitance parameter is exactly midway between discrete tuning points.

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TABLE I PRESELECTED COUPLED-LINE DIMENSIONS

TABLE II UNIT LENGTH AND COUPLING CAPACITANCE FOR EXPERIMENTAL FILTER

Fig. 6. Contour plot of filter shape error on the two-dimensional tuning space; fractional bandwidth and center frequency. Points circled on the plot are discussed in Section V.

The plot shows a series of good tuning points at the initial design fractional bandwidth (which, in this case, is equal to 0.15), uniformly spaced at frequencies corresponding to the discrete length tuning points. This occurs because, in this design, all of the filter sections have the same number of tunable length segments, resulting in the synchronous tuning of their electrical lengths. For different values of fractional bandwidth, the relationship becomes more complex. As alluded to earlier, this is caused by the changes in per-unit-length coupling capacitance. The result is that the points on the tuning surface, which yield good filter performance, follow nonequispaced lines, which diverge as the center frequency increases. The tuning surface plot provides a useful aid in visualizing these relationships and in selecting the appropriate tuning points for desired filter characteristics. V. EXPERIMENTAL RESULTS To verify the theoretical analysis of Section IV and to test the lumped-distributed coupled-line filter’s tuning capabilities, a third-order filter with 16 tunable segments was designed and fabricated based on a Butterworth prototype. A coplanarwaveguide medium was used, as it allows well-defined and easily adjustable ground connections for the resonators. The intention was to provide electronically controlled center-frequency and bandwidth tuning through the use of MEMS switches and MEMS bi-stable capacitors; however, for prototyping purposes, the transmission-line lengths and lumped coupling capacitance were adjusted manually through the use of removable printed links to ground, and surface-mount 0603-size capacitors. The filter was designed to operate in the region above (refer to Section II-C) having a maximum fractional bandwidth of 15% withallcouplingcapacitorsincircuit.Thedesigncenter-frequency tuning range of the filter was from 350 MHz (16 segments) to

Fig. 7. Diagram of experimental lumped-distributed coupled-line line filter.

1.4 GHz (four segments). A low-loss microwave laminate was mm, , ). Various critical used ( dimensionsofthecoupledlinesofthefilterwerepreselectedbased ontheparametersofthislaminate,andaregiveninTableI. A full-wave EM simulation was used to extract the even- and odd-mode characteristic impedances and phase velocities of a pair of coplanar-waveguide coupled lines with these critical dimensions and a lower ground plane. These are also listed in Table I. Using these coupled-line parameters and the appropriate prototype filter element values, the unit length and coupling capacitance for both the interior and end sections were derived using the technique described in Section III. The resulting values are given in Table II. A lumped-distributed coupled-line filter prototype was fabricated using standard lithography techniques. A drawing of the resultant filter layout is shown in Fig. 7; for clarity, the switchable coupling capacitors and ground connections are not shown. The filter measures approximately 44 240 mm. A hybrid model for the lumped-distributed coupled-line filter was built up from analytical and full-wave EM simulations using Agilent Technologies ADS. To reduce the simulation time and allow for the inclusion of multiple lumped components, EM simulations were only carried out on smaller circuit segments and the resulting data was integrated into an analytical simulation in the form of -parameter blocks. The periodic nature of the lumped-distributed coupled-line circuit meant it was well-suited to this hybrid approach. This EM and analytical hybrid model was used to simulate the response of

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TABLE III DETAILS OF A NUMBER OF BANDWIDTH TUNING POINTS

Fig. 8. Measured (solid line) and simulated (broken line) response for lumped-distributed coupled-line filter at the initial design frequency and bandwidth.

a constant unloaded position. Fig. 9. Simulated (broken line) and measured (solid line) results for five of the 16 possible tuning states of the experimental lumped-distributed coupled-line filter. The indexing terms, a–e refer to Fig. 6. Data from [10].

the experimental filter. This is presented in Fig. 8 along with the measured results of the filter at the initial design frequency and bandwidth. For medium bandwidths and low filter order the upper stopband rejection is poor, however, the simulated response shows reasonable correlation with the measured results. The increase in frequency of the low-side attenuation pole has been shown to be caused by cross-coupling between nonadjacent resonators. A. Center-Frequency Tuning Although many different center-frequency tuning states are possible, the largest number having constant fractional bandwidth occur at the design value of 0.15, as discussed in Section IV. These tuning states can be obtained by switching all the coupling capacitors in circuit and discretely varying the length of all the coupled-line sections synchronously. A selection (indexed as – in Fig. 6) of the 16 possible tuning states are shown in Fig. 9 along with the corresponding simulated responses. The filter gives almost constant fractional bandwidth across the complete tuning range, except for a slight reduction at low values of coupled-line length (from 14% to 11.5%). The variation in insertion loss across the tuning range is also minimal. This reflects

of the resonators regardless of tuning

B. Bandwidth Tuning To test the bandwidth tuning capabilities of the filter, two groups of sample points were chosen, which had similar center frequencies, but a range of bandwidth values. The two groups are indexed in Fig. 6 clustered around 800 and 400 MHz. The details of these points are given in Table III. Each of the points corresponds to a local minimum in the error function. The center frequency and fractional bandwidth for each of the points were obtained from Fig. 6 and are based on empirical relationships extrapolated from a selection of values calculated using the synthesis process. The four central columns of the table are the numbers of coupling capacitors and length segments required to achieve each fractional bandwidth and center frequency. In most cases, these numbers have been rounded from a noninteger number, indicating that a perfect filter shape cannot be obtained. The corresponding error value reflects the extent of this rounding in each case. Each of these points was measured using the experimental filter and the actual center frequencies and bandwidths are listed in the final columns of Table III. Since the mathematically derived values of center frequency and bandwidth are approximate, there is some variation in their correlation with the measured values. The measured results of the different tuning states are shown in Figs. 10–12. For clarity, the measured results for the 430-MHz cluster have been grouped around common center frequencies and split over two plots.

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Fig. 10. Measured insertion loss of experimental lumped-distributed coupled-line filter for six bandwidth tuning points detailed in Table III.

3.8 : 1 tuning range. A disadvantage is that the tuning ranges are not uniform; at lower frequencies, there is a greater choice of both center frequency and bandwidth. However, it may be possible to provide more consistent tuning resolution through the use of reconfigurable resonators, which can be switched either in parallel or series [15]. An essential aspect of tunable filter design is the effect of the tuning mechanism on the filter insertion loss. Simulations using realistic values for the contact resistance (0.5 ) and (50) of the RF MEMS contact and capacitive switches show that the unloaded of the resonators varies from a nominal value of 28 by only 21% across both frequency and bandwidth tuning ranges. This indicates that the filter structure is relatively independent of the number of tuning elements employed.

VI. CONCLUSION

Fig. 11. Measured insertion loss of experimental lumped-distributed coupled-line filter for five of the ten bandwidth tuning points detailed in Table III.

The lumped-distributed coupled-line filter topology described in this paper was developed to provide a filter structure, which could be tuned in both bandwidth and center frequency over a wide range. The shunt and parallel connections of the multiple distributed switching elements means that the losses remain constant regardless of the number of switching elements employed. The number and range of the tuning steps is thus only limited by the number of switching elements, not by losses in the filter structure itself. The antiphase relationship between the EM and capacitive coupling coefficients of lumped-distributed coupled lines allows for very low fractional bandwidths without the need for widely spaced lines. A filter synthesis procedure has been developed based on network models of the coupled lines, allowing the parameters of the filter to be derived from standard filter prototype values. This procedure and the performance of the lumped-distributed coupled-line filter have been verified through experimental results. Further study will involve reducing the filter to a standard combline structure through the intelligent implementation of the filter and switching elements. This will lead to greatly improved harmonic performance and a twofold reduction in electrical size. The use of lower coupling capacitance values to improve the upper stopband rejection, as described in this paper, will result in a high-performance discretely tunable planar filter, reconfigurable in both center frequency and bandwidth.

ACKNOWLEDGMENT Fig. 12. Measured insertion loss of experimental lumped-distributed coupled-line filter for five of the ten bandwidth tuning points detailed in Table III.

C. Discussion The results shown here demonstrate that both wide range center-frequency and bandwidth tuning are possible using the lumped-distributed coupled-line topology. The experimental filter could be tuned in discrete steps over two octaves of center frequency, i.e., 350 MHz–1.4 GHz, with little degradation in the response. In addition, a number of different bandwidth settings could be selected, ranging from 3.8% to 14.5%; a

Author B. E. Carey-Smith is grateful to C. J. Carpenter, University of Bristol, Bristol, U.K., for valuable discussions in the course of this study. The authors would like to acknowledge the contributions of their colleagues from Siemens AG, France Télécom—Research and Development, Centre Suisse d’Electronique et de Microtechnique S.A., King’s College London, Motorola SA, Panasonic European Laboratories GmbH, Regulierungsbehörde für Telekommunikation und Post, Telefonica Investigacion Y Desarrollo S.A. Unipersonal, Toshiba Research Europe Ltd., TTI Norte S.L., University of Southampton, University of Portsmouth, Siemens ICN S.p.A., 3G.com Technologies Ltd., and Motorola Ltd.

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REFERENCES [1] J. R. Macleod, M. A. Beach, P. A. Warr, and T. Nesimoglu, “A software defined radio receiver test-bed,” in Proc. 54th Vehicular Technol. Conf., vol. 3, 2001, pp. 1565–1569. [2] R. D. Streeter, C. A. Hall, R. Wood, and R. Mahadevan, “VHF highpower tunable RF bandpass filter using microelectromechanical (MEM) microrelays,” Int. J. RF Microwave Computer-Aided Eng., vol. 11, pp. 261–275, Sep. 2001. [3] J. Brank, J. Yao, M. Eberly, A. Malczewski, K. Varian, and C. Goldsmith, “RF MEMS-based tunable filters,” Int. J. RF Microwave Computer-Aided Eng., vol. 11, pp. 276–284, Sep. 2001. [4] R. L. Borwick, III, P. A. Stupar, J. F. DeNatale, R. Anderson, and R. Erlandson, “Variable MEMS capacitors implemented into RF filter systems,” IEEE Trans. Microw. Theory Tech., vol. 51, pp. 315–319, Jan. 2003. [5] R. M. Young et al., “Low-loss bandpass RF filter using MEMS capacitance switches to achieve a one-octave tuning range and independently variable bandwidth,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2003, pp. 1781–1784. [6] J. R. Macleod, T. Nesimoglu, M. A. Beach, and P. A. Warr, “Miniature distributed filters for software re-configurable radio applications,” in Proc. Information Society Technologies Mobile Wireless Telecommunications Summit 2002, Jun. 2002, pp. 159–163. [7] Y. Liu, A. Borgioli, A. S. Nagra, and R. A. York, “Distributed MEMS transmission lines for tunable filter applications,” Int. J. RF Microwave Computer-Aided Eng., vol. 9, pp. 254–260, Jul. 1999. [8] E. Fourn et al., “Bandwidth and central frequency control on tunable bandpass filter by using MEMS cantilevers,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2003, pp. 523–526. [9] C. Rauscher, “Reconfigurable bandpass filter with a three-to-one switchable passband width,” IEEE Trans. Microw. Theory Tech., vol. 51, pp. 573–577, Feb. 2003. [10] B. Carey-Smith, P. A. Warr, M. A. Beach, and T. Nesimoglu, “Tunable lumped-distributed capacitively coupled transmission-line filter,” Electron. Lett., vol. 40, pp. 434–436, Apr. 2004. [11] R. Mongia, I. J. Bahl, and P. Bhartia, RF and Microwave Coupled-Line Circuits. Norwood, MA: Artech House, 1999, pp. 150–151. [12] J.-S. Hong and M. J. Lancaster, “Couplings of microstrip square openloop resonators for cross-coupled planar microwave filters,” IEEE Trans. Microw. Theory Tech., vol. 44, pp. 2099–2109, Nov. 1996. [13] G. L. Matthaei, L. Young, and E. M. Jones, Microwave Filters, Impedance-Matching Networks and Coupling Structures. Norwood, MA: Artech House, 1980, pp. 636–638. [14] S. B. Cohn, “Direct-coupled-resonator filters,” in Proc. IRE, vol. 45, Feb. 1957, pp. 187–196. [15] B. Carey-Smith, P. A. Warr, M. A. Beach, and T. Nesimoglu, “A MEMSready wide tuning range planar resonator with application to microwave flexible filters,” in Proc. Asia–Pacific Microwave Conf., Nov. 2003, pp. 1581–1584.

Bruce E. Carey-Smith received the B.E. degree in electrical and electronic engineering from the University of Canterbury, Christchurch, New Zealand, in 1995, and is currently working toward the Ph.D. degree in electrical engineering at the University of Bristol, Bristol, U.K. From 1995 to 2002, he was with Tait Electronics Ltd., Christchurch, New Zealand, where he was involved in the design of RF circuits and systems for mobile radio applications. He subsequently joined the University of Bristol, as a Research Associate with the Centre for Communications Research, where his current research interests are in the area of tunable microwave circuits for software reconfigurable radio.

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Paul A. Warr received the B.Eng. degree in electronics and communications from The University of Bath, Bath, U.K., in 1994, and the M.Sc. degree in communications systems and signal processing and Ph.D. degree for his work on octave-band linear receiver amplifiers from The University of Bristol, Bristol, U.K., in 1996 and 2001, respectively. He was with the Marconi Company, where he was involved with secure high-redundancy cross-platform communications. He is currently a Lecturer of radio frequency engineering with the University of Bristol, where his research concerns the front-end aspects of software (reconfigurable) radio and diversity-exploiting communication systems, responsive linear amplifiers, flexible filters, and linear frequency translation. His research has been supported by the U.K. Department of Trade and Industry (DTI)/Engineering and Physical Sciences Research Council (EPSRC) alongside Commission of the European Communities (CEC) Advanced Communications Technologies and Services (ACTS) and Information Society Technologies (IST) programs and industrial collaborators. Dr. Warr is a member of the Executive Committee of the Institution of Electrical Engineers (IEE), U.K., Professional Network on Communication Networks and Services.

Mark A. Beach (A’90) received the Ph.D. degree from the University of Bristol, Bristol, U.K., in 1989. In 1989, he joined the University of Bristol, as a member of academic staff. He is currently a Professor of radio systems engineering with the University of Bristol. He has made contributions to the European collaborative projects, TSUNAMI, SATURN, ROMANTIK, TRUST, and more recently, SCOUT. His current interests are focused on multiple-input–multiple-output (MIMO) channel characterization and the design and optimization of space-time coded wireless architectures for third-generation (3G) and fourth-generation (4G) wireless networks. His research interests include smart antenna technology for wireless, as well as analog RF circuitry for software definable radio (SDR). Prof. Beach is a member of the Institution of Electrical Engineers (IEE), U.K., Professional Network on Antennas and Propagation. He is an editor for the IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS.

Tayfun Nesimoglu received the B.Sc. degree in electrical and electronic engineering from the Eastern Mediterranean University, Gazimaˇgusa, Mersin, Turkey, in 1996, the M.Sc. degree in mobile, personal and satellite communications from the University of Westminster, Westminster, U.K., in 1997, and the Ph.D. degree in electrical engineering from the University of Bristol, Bristol, U.K., in 2002. His doctoral research concerned novel amplifier linearization techniques for broad-band mobile communication systems and software radio. Since 2001, he has been a Research Associate with the University of Bristol, where he is involved in a number of European Union (EU) collaborative and industrial projects. His research interests include RF hardware, amplifier, mixer design and linearization, broad-band transmitter/receiver front-end architectures, and software radio enabling technologies. He has presented these research topics at international conferences. He has authored or coauthored numerous technical papers and has also reviewed several papers for IEEE conferences and journals.

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An Adaptive Predistortion RF Power Amplifier With a Spectrum Monitor for Multicarrier WCDMA Applications Seung-Yup Lee, Yong-Sub Lee, Seung-Ho Hong, Hyun-Sik Choi, and Yoon-Ha Jeong, Senior Member, IEEE

Abstract—This paper presents an adaptive predistortion RF power amplifier for repeater systems with a spectrum monitor. For adaptive control of cancellation, we implement a spectrum monitor that improves the adjacent channel leakage ratio (ACLR) characteristics of the power amplifier by analyzing the output spectrums of RF power amplifiers directly and simultaneously. For experimental validation, we also implement a class-AB RF power amplifier that adopts a predistortion linearizer with the spectrum monitor and measure the characteristics for the wide-band code division multiple access (WCDMA) band. With an optimum gate bias voltage of the power amplifier, ACLRs of 22 and 20.5 dB are improved for the cases of one- and four-carrier WCDMA applications, respectively. The predistortion power amplifier with the spectrum monitor delivers a out of 37.5 dBm with an ACLR of 45 dBc for four-carrier WCDMA applications. Furthermore, excellent ACLR characteristics are consistently maintained with the minimization algorithm by adaptively controlling the vector modulator in the predistorter under various environments that include varying input power levels, temperatures, and operating frequencies. Index Terms—Adaptive, adjacent channel leakage ratio (ACLR), linearity, power amplifier, predistorter (PD), spectrum, wide-band code division multiple access (WCDMA).

I. INTRODUCTION

D

IVERSE techniques for linearity improvement of RF power amplifiers have been investigated and developed endlessly in modern wireless communication systems such as global system for mobile (GSM), IS-95 series, CDMA2000, wide-band code division multiple access (WCDMA), etc. [1]. Among the linearization techniques, feedforward approaches provide high linearity, but result in complex and expensive solutions and, thus, are mostly used in base-station systems [2]–[4]. Feedback methods have fatal problems of instability and bandwidth limitations [5]–[7]. Development of digital predistortion (DPD) techniques is being actively pursued due to their high intermodulation distortion (IMD) suppression, but is complicated and typically implemented at the baseband level. Therefore, these techniques are not suitable for repeater systems, such as feedforward systems [8]–[11]. In contrast, analog predistortion techniques have the advantages of simple Manuscript received April 24, 2004; revised June 14, 2004. This work was supported in part by the Korean Ministry of Education and Human Resources Development under the BK21 Program. The authors are with the Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyungbuk 790-784, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2004.841222

structure, low cost, and proper linearization [12]–[15]. Compared with DPD techniques, they are suited to repeater systems because they can amplify RF signals directly between handsets and base stations with the above-mentioned advantages. However, conventional predistortion power amplifiers also have problems such as memory effects and variations in linearity depending on the environment. Therefore, adaptive control methods are in great demand for improving the performance of predistortion RF power amplifiers. In this paper, for adaptive control, we propose a spectrum monitor (we refer to the semispectrum analyzer implemented as the spectrum monitor to distinguish it from general spectrum analyzers) that is applied to an analog predistortion RF power amplifier. It directly analyzes the spectrum components of output power from RF power amplifiers. Its structure is not much different from those of general spectrum analyzers and can be adopted by other linearization applications. In the implemented adaptive predistorter (PD), the spectrum monitor impresses the proper control voltages of an attenuator and a phase shifter in the PD while analyzing the output spectrums. Down-link WCDMA signals are focused rather than continuous waves (CWs) or two-tone signals. For experimental validation, we linearize a 2.11 2.17-GHz-band class-AB RF power amplifier with 30-W peak envelope power (PEP). Adjacent channel leakage ratios (ACLRs) of 59.5 dBc (improved value of 22 dB) and 52.14 dBc (improved value of 20.5 dB) are obtained for one- and four-carrier WCDMA applications, respectively. As an ACLR of 45 dBc is put as a reference of the linearity in WCDMA applications, the predistortion of 37.5 dBm for four-carrier power amplifier delivers a WCDMA applications. Furthermore, excellent cancellation of nonlinearity is maintained with the spectrum monitor under all environments formed by varying input power levels, temperatures, and WCDMA channels. II. OPERATION OF PREDISTORTION POWER AMPLIFIER WITH SPECTRUM MONITOR We propose a predistortion RF power amplifier based on a spectrum monitor. Fig. 1 shows the block diagram of the proposed system. In conventional analog predistortion techniques that do not use a spectrum monitor, the spurious signal out of the main power amplifiers are cancelled with distorted signals in the PD by controlling two parameters of a variable attenuator and variable phase shifter (a vector modulator). However, the magnitude and phase of the vector modulator in the PD is

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LEE et al.: ADAPTIVE PREDISTORTION RF POWER AMPLIFIER WITH SPECTRUM MONITOR FOR MULTICARRIER WCDMA APPLICATIONS

Fig. 1. Block diagram of the proposed adaptive predistortion RF power amplifier.

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Fig. 3. Frequencies and shapes of RF, IF, and LO signals.

Fig. 2. Block diagram of the spectrum monitor.

fixed so the performance of the power amplifier is limited in the presence of environmental changes. In the proposed adaptive predistortion technique, the spectrum monitor analyzes the output spectrum components and maximizes the linearity of the predistortion power amplifier by controlling the vector modulator adaptively in the PD whenever the environment is changed. This method is similar to what engineers do to control the vector modulator while measuring the spectrums of output power on spectrum analyzers. The spectrum monitor is composed of a phase-locked loop (PLL), mixer, power detection unit, and microcontroller, as shown in Fig. 2. Its operation resembles that of a general spectrum analyzer. Stable local oscillation (LO) signals are generated in the PLL, and the RF signals are down-converted to IF signals by the LO signal in the mixer. The shape of down-converted IF signals is the same as that of RF signals, but only the frequency band is changed now, as shown in Fig. 3. The IF signals become a CW signal after passing through narrow bandpass filters (BPFs). A specific frequency component can be determined by detecting the CW signal in a logarithmic detector. If the frequency of the LO signal is swept gradually by the PLL, that of the IF signals is also swept. The magnitudes of the IF signals through the narrow windows of BPFs are detected gradually; thus, finally, the spectrums of the RF signals can be determined with the information of the frequency of the PLL ( -axis) and the magnitudes of the detected CW signals ( -axis). Fig. 4 shows the flowchart of the microcontroller in the spectrum monitor, which is optimized for WCDMA applications. The microcontroller detects changes in spectrum components

Fig. 4. Flowchart for maximizing ACLR characteristics.

continuously and minimizes spurious power with a minimization algorithm [16]. In WCDMA applications, it is not necessary for all spectrum components with a 70-MHz bandwidth to be detected to improve linearity. To improve the speed of minimization, 12 WCDMA channels are detected first and then spurious power (especially 5-MHz-offset components) of the activated channels are detected. The LO frequency is swept to search activated and deactivated channels frequently during minimization. It is the 5-MHz-offset frequency components that are necessary for ACLR improvement, and this frequency is swept easily by the PLL. In the adaptive analog predistortion technique, there are two control parameters in the attenuator and phase shifter. The power detection and control of the vector modulator are achieved continuously by the microcontroller. Denoting the spurious power density that is detected first with the first conas , and the trol voltage of the attenuator spurious power density that is detected second after applying as the changed control voltage of the attenuator , the minimization process for the ACLR is as follows: (1)

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FOUR CASES

OF IN THE

Fig. 5.

A. Implementation of the Spectrum Monitor

TABLE I APPLIED CONTROL VOLTAGES USED MINIMIZATION ALGORITHM

Concept of minimization algorithm.

(2) is the new control voltage to be applied to where the attenuator. The two directions of the new control voltage of the attenuator around possible four cases are arranged in Table I. has a negative value As shown in (1) and (2), if (Cases 2 and 3 in Table I), moves in a positive direction. Fig. 5 describes the concept of the minimization algorithm and especially shows Case 3. Conversely, if has a positive value (Cases 1 and 4), moves in a negative direction. The minimum value of the spurious power is obtained while this process is repeated continuously in the algorithm, and this value is continuously maintained. The control of the phase shifter operates in the same way as that of the attenuator. The simultaneous control of the attenuator and the phase shifter is difficult because it is not known which parameter contributes the improvement of the ACLR characteristics in a particular situation and, thus, these two components are controlled in an alternating manner.

III. EXPERIMENTAL RESULTS OF PREDISTORTION POWER AMPLIFIER WITH SPECTRUM MONITOR Here, we present the implementation and experimental results of the spectrum monitor and the adaptive predistortion RF power amplifier. The spectrum monitor analyzes the output spectrums directly. It automatically improves the linearity and maintains the maximum ACLR characteristics of the predistortion power amplifier.

Fig. 6 shows the entire block diagram of the implemented adaptive predistortion RF power amplifier with the spectrum monitor. In the spectrum monitor, the frequency range of the PLL is chosen as 1.75 1.81 GHz because that of the down-link WCDMA applications is 2.11 2.17 GHz and the center frequency of the BPFs is 360 MHz. The frequency of the PLL is initialized and swept by a microcontroller, i.e., Microchip’s PIC16F877. The RF input signals to a mixer should be small enough to escape the mixer’s nonlinear region. A power detection module consists of a low-pass filter (LPF), gain amplifiers, BPFs, logarithmic detector, and rectifier. The down-converted IF signals are filtered out by the LPF ahead to eliminate higher order harmonics. To obtain accurate specific frequency components, BPFs with narrow bandwidth are required. The bandwidth of the surface acoustic wave (SAW) filters used in the spectrum monitor is 200 kHz. The performances of one- and two-stage BPFs are compared in Fig. 7. The two-stage filter has excellent bandpass capability, and is suitable for separating and analyzing specific frequency components. The magnitudes of the separated frequency components are detected in the logarithmic detector and measured in a 10-bit analog-to-digital converter (ADC) in the microcontroller. The rectifier with Schottky diode is placed between the logarithm detector and the microcontroller to prevent detected voltages from rippling. The BPFs and the rectifier in the spectrum monitor are similar to the resolution bandwidth (RBW) and video bandwidth (VBW) in spectrum analyzers, respectively. The gain amplifiers should be placed in a few places in advance to prevent an increase of noise levels. Fig. 8 shows the low-cost and small-sized spectrum monitor that is implemented. The spectrum monitor operates at a supply voltage of 5 V and consumes 180 mA of current, excluding a liquid crystal display (LCD). It has an input port for RF signals, an output connector for the LCD to read the detected values, and two output ports to control the predistortion linearizer. A 3-dBm down-link WCDMA signal (Agilent’s E4433B) is measured by the spectrum monitor and a spectrum analyzer, and the spectrums are almost the same, as shown in Fig. 9. The sequence of the minimization algorithm in the spectrum monitor is detection, calculation of the new voltage, and control of the vector modulator. The loop time of the sequence in the implemented spectrum monitor is approximately 80 ms. The control of the attenuator and phase shifter is performed ten times in the microcontroller in an alternating manner. B. Experimental Results of Adaptive Predistortion Power Amplifier The spectrum monitor with the minimization algorithm is adopted into a predistortion RF power amplifier. The algorithm always maintains the minimum spurious power level by adjusting the vector modulator in the PD regardless of the environments (i.e., given various input power levels, temperatures, and WCDMA channels). A driver amplifier has a gain of 30 dB and a 1-dB compression point of 36 dBm. The power amplifier is designed and implemented using MRF21030 LDof 28 V. MOSFET from Motorola with 30-W PEP at a

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Fig. 6. Overall block diagram of an adaptive predistortion power amplifier with the spectrum monitor.

Fig. 9. Comparison of the spectrums of the implemented spectrum monitor of 3 dBm. and a spectrum analyzer at a P Fig. 7.

Characteristics of the BPFs.

Fig. 10. Changes of ACLR with the gate-bias voltage in the power amplifier. Fig. 8. Implemented spectrum monitor.

In the predistortion systems, the ACLR characteristics changes with not only the magnitudes and phases of the predistorted signals, but also the gate-bias voltage of the main power amplifier, as shown in Fig. 10. The best cancellation of nonlinearity

in the predistortion power amplifier occurs at a of 3.62 V mA), which the gate-bias voltage (quiescent current, is fixed. Under this condition, the power amplifier has a of 43.2 dBm and a gain of 11.5 dB. For the proper comparison of the ACLR characteristics, we also measured the power

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Fig. 12. ACLR characteristics of the adaptive predistortion power amplifier as a function of temperature for one-carrier WCDMA signals.

Fig. 11. ACLR characteristics for a one-carrier WCDMA signal. (a) Measured of 34.9 dBm. (b) Comparison of the ACLR spectrum densities at a P characteristics of the power amplifier with and without a PD.

amplifier without the PD at a of 3.7 V mA , which provides a moderate ACLR performance according to the datasheets. For reference, Agilent’s E4438C is used in the measurement of one- and four-carrier WCDMA applications. Fig. 11(a) shows the power spectrum densities measured under various conditions at an average output power ( ) of 34.9 dBm for a one-channel WCDMA application. The ACLR of the power amplifier with the PD reaches 59.5 dBc at a of 3.62 V. The ACLRs of 13.3 and 22 dB are improved and compared with the ACLR of the power amplifier without of 3.7 V and 3.62 V, respectively. The ACLR the PD at characteristics of the predistortion power amplifier with the spectrum monitor and the other conditions above are compared in Fig. 11(b), while input power levels are swept. In the case when the conventional PD is optimized for high output power, there is a problem in that the ACLR characteristics become worse than that of the power amplifier without the PD (@ V) at low-output power levels because the optimum magnitude and phase are varied along the levels of the output power. Therefore, adaptive control of the linearizer

is necessary. The implemented spectrum monitor searches and maintains excellent ACLR characteristics. From the viewpoint of power-added efficiency (PAE), since the gate bias voltage becomes small (3.62 V), the PAE is also improved as much as of 1.9% compared with that of the power amplifier at a 3.7 V. Furthermore, an increase in temperature causes an increase in the current of LDMOSFETs, and it eventually changes the optimum cancellation points of third-order intermodulation (IM3) power. The adaptive predistortion power amplifier with the spectrum monitor is excellent with an even variation in temperature, as shown in Fig. 12. The conventional predistortion power amplifier at a fixed control voltage in the vector modulator cannot follow the optimum cancellation of the spurious power; however, the adaptive power amplifier, which adopts the minimization algorithm, shows an improvement up to 9.2 dB at 80 C. There is another problem with conventional fixed PDs. As shown in Fig. 13, the optimum magnitudes and phases of IM3L and IM3H are also changed according to the center frequencies of the activated channels when a two-tone signal is applied because the output power levels are varied and the magnitudes and phases of the intermodulation terms vary with different frequencies. This results in negative effects on ACLR characteristics for WCDMA applications, as shown in Fig. 14, i.e., when the control voltages of the attenuator and the phase shifter are fixed in the PD for a specific channel, the ACLR characteristic can become worse in the other channels. However, the adaptive RF power amplifier with the spectrum monitor maintains maximum ACLR characteristics. Compared with the ACLR of the conventional PD that is fixed at a center channel, that of the adaptive predistortion power amplifier is improved up to 6.8 dB at the outside channels. It shows excellent performance at different input power levels, temperatures, and even WCDMA channels with the aid of the spectrum monitor. To reduce the memory effects of an LDMOSFET, a 3-mm-wide dc feed line is designed [17]. A four-carrier

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Fig. 13. Measured magnitudes and phases of IM3 power with changes in frequencies.

Fig. 14. ACLR characteristics of the adaptive predistortion power amplifier with changes in the channels.

Fig. 15. ACLR characteristics for four-carrier WCDMA signal. (a) Measured of 34.3 dBm. (b) Comparison of the ACLR spectrum densities at P characteristics of the power amplifier with and without a PD.

WCDMA signal is created by one signal generator. The maxof 34.3 dBm, imum ACLR of 52.14 dBc is obtained at a as shown in Fig. 15. The ACLR upper and ACLR lower values are measured in symmetric states. The improved ACLR (5-MHz offset) values are 11.7 and 20.5 dB under the conditions of of 3.7 and 3.62 V, respectively. The predistortion power of amplifier with the spectrum monitor can deliver a 37.5 dBm with an ACLR of 45 dBc for four-carrier WCDMA applications, whereas the power amplifier without the PD at a of 3.7 V delivers a of only 26 dBm. Excellent ACLR characteristics are maintained, due to the spectrum monitor. An ACLR of 13.7 dB is improved and compared with the power amplifier with a conventional PD at a of 26 dBm. As shown in Fig. 16, the spectrum monitor minimizes the variation of ACLR characteristics under temperature changes and improves it by up to 9.2 dB at 70 C. In the case of four-carrier applications, the predistortion power amplifier also shows excellent ACLR characteristics at a of 3.62 V, and this performance is maintained by the spectrum monitor under various environmental conditions.

Fig. 16. ACLR characteristics of the adaptive predistortion power amplifier as a function of temperature for four-carrier WCDMA signals.

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IV. CONCLUSION For the adaptive control of the predistortion RF power amplifier, we have proposed and implemented a low-cost spectrum monitor that can analyze the output spectrums directly. We have also implemented a predistortion RF power amplifier for repeaters in the WCDMA band of 2.11 2.17 GHz with a 30-W PEP LDMOSFET. The ACLR characteristics of the power amplifier with the PD changes with the gate-bias voltage of the power amplifier, and the optimum gate bias voltage is determined. For one-carrier WCDMA applications, the ACLR of 34.9 dBm, and is improved by reaches 59.5 dBc at a up to 22 dB by the spectrum monitor. From the viewpoint of input power levels, the problem of the linearity of the predistortion power amplifier becoming worse while the input power levels are decreased is solved with ACLR improvements of up to 15.4 dB. The variations of the ACLR with temperature in the fixed PD are also solved up to 8.3 dB. Another problem that can occur with changes of WCDMA channels is solved up to 6.8 dB with the spectrum monitor for one-carrier WCDMA applications. Even for four-carrier WCDMA applications, an ACLR of 52.14 dBc is obtained at a of 34.3 dBm by improving an ACLR of 20.5 dB. The power amplifier with the spectrum monof 37.5 dBm with an ACLR of 45 dBc. itor delivers a Excellent performance is maintained by the spectrum monitor under various temperatures. The output signals of the power amplifiers need to be analyzed in real time in order to solve the problems faced by conventional predistortion RF power amplifiers. Thus, the use of the spectrum monitor is proposed. The characteristics of the adaptive predistortion RF power amplifier with the spectrum monitor are excellent under various conditions such as varying input power levels, temperatures, and operating frequencies.

[8] S. P. Stapleton, “Amplifier linearization using adaptive digital predistortion,” Appl. Microwave Wireless, vol. 13, pp. 72–77, Feb. 2001. [9] S. Boumaiza and F. M. Ghannouchi, “Realistic power-amplifiers characterization with application to baseband digital predistortion for 3G base stations,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 12, pp. 3016–3021, Dec. 2002. [10] K. J. Muhonen, M. Kavehrad, and R. Krishnamoorthy, “Adaptive baseband predistortion techniques for amplifier linearization,” in 33rd Signals, Systems, and Computers Asilomar Conf. Rec., vol. 2, Oct. 1999, pp. 888–892. [11] S. Kusunoki, K. Yanamoto, and T. Iida, “Power-amplifier module with digital adaptive predistortion for cellular phones,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 12, pp. 2979–2986, Dec. 2002. [12] J. Yi, Y. Yang, M. Park, W. Kang, and B. Kim, “Analog predistortion linearizer for high-power RF amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2709–2713, Dec. 2000. [13] T. Nojima and T. Konno, “Cuber predistortion linearizer for relay equipment in 800 MHz band land mobile telephone system,” IEEE Trans. Veh. Technol., vol. VT-34, no. 11, pp. 169–177, Nov. 1985. [14] B. Aleiner, “The concept of predistortion,” Microwave J., vol. 46, no. 10, pp. 82–102, Oct. 2003. [15] K. Morris and P. Kenington, “Power amplifier linearization using predistortion techniques,” in RF Microwave Components Communications Systems Dig., Apr. 1997. [16] W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C. Cambridge, U.K.: Cambridge Univ. Press, 1988. [17] A. Rabany, L. Nguyen, and D. Rice, “Memory effect reduction for LDMOS bias circuits,” Microwave J., vol. 46, no. 2, pp. 124–130, Feb. 2003.

Seung-Yup Lee was born in Daegu, Korea, in 1973. He received the B.S. degree in electronics and electrical engineering from Kyungpook National University, Daegu, Korea, in 2000, the M.S. degree in electronics and electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2002, and is currently working toward the Ph.D. degree at POSTECH. His current research interests include various RF power-amplifier design and linearization systems.

ACKNOWLEDGMENT The authors would like to thank Prof. S. Lee, the Pohang University of Science and Technology (POSTECH), Pohang, Korea, for his assistance.

REFERENCES [1] J. Cha, J. Yi, J. Kim, and B. Kim, “Optimum design of a predistortion RF power amplifier for multi-carrier WCDMA applications,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 2, pp. 655–663, Feb. 2004. [2] Y. Y. Woo, Y. Yang, J. Yi, J. Nam, J. Cha, and B. Kim, “An adaptive feedforward amplifier for WCDMA base stations using imperfect signal cancellation,” Microwave J., vol. 46, no. 4, pp. 22–44, Apr. 2003. , “Feedforward amplifier for WCDMA base stations with a new [3] adaptive control method,” in IEEE MTT-S Int Microwave Symp. Dig., vol. 2, Jun. 2002, pp. 769–772. [4] J. W. Huh, I. S. Chang, and C. D. Kim, “Spectrum monitored adaptive feedforward linearization,” Microwave J., vol. 44, no. 9, pp. 160–167, Sep. 2001. [5] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House, 1999. [6] P. Kenington, High-Linearity RF Amplifier Design. Norwood, MA: Artech House, 2000. [7] Y. Kim, Y. Yang, S. H. Kang, and B. Kim, “Linearization of 1.8 GHz amplifier using feedback predistortion loop,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 1998, pp. 1675–1678.

Yong-Sub Lee was born in Namhea, Korea, in 1976. He received the B.S. degree in electronics and electrical engineering from Kwangwoon University, Seoul, Korea, in 2003, and is currently working toward the M.S. degree at the Pohang University of Science and Technology (POSTECH), Pohang, Korea. His current research interests include linear power amplifiers.

Seung-Ho Hong was born in Seoul, Korea, in 1979. He received the B.S. degree in electronics and electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2003, and is currently working toward the M.S. degree at POSTECH. His main research interests include CMOS devices and RF measurement.

LEE et al.: ADAPTIVE PREDISTORTION RF POWER AMPLIFIER WITH SPECTRUM MONITOR FOR MULTICARRIER WCDMA APPLICATIONS

Hyun-Sik Choi was born in Cheonan, Korea, in 1980. He received the B.S. degree in electronics and electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2003, and is currently working toward the M.S. degree at POSTECH. His main research is related to CMOS devices.

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Yoon-Ha Jeong (S’82–M’86–SM’96) received the Ph.D. degree in electronics engineering from the University of Tokyo, Tokyo, Japan, in 1987. From 1976 and 1981, he was an Assistant Professor of electrical engineering with the Kyungnam College of Technology, Pusan, Korea. From 1982 to 1987, he was a Research Assistant with the Department of Electronics Engineering, University of Tokyo, where he pioneered in situ vapor phase deposition and the development of photo-chemical vapor deposition (CVD) technology for InP metal–insulator–semiconductor field-effect transistors (MISFETs). In 1987, he joined the Pohang University of Science and Technology (POSTECH), Pohang, Korea, where he is a Professor with the Department of Electric and Electronics Engineering and a Director of the National Nano Devices Center for Industry, where he is involved with nano-CMOS devices and circuits for RF applications. His research interests include microwave and millimeter-wave device fabrication, RF circuit design, single electron transistors, and nano-CMOS devices. Dr. Jeong is a senior member of the IEEE Electron Devices Society. He is a member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S), the Japan Society of Applied Physics, and the Institute of Electronics Engineers of Korea. He was the recipient of the 1984 Graduate Excellent Award presented by the Rotary International Foundations, a 1985–1987 Research Fellowship presented by the Japanese Government, and a 1990 Research Fellowship presented by the Korean Government.

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Digital Object Identifier 10.1109/TMTT.2005.844588

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W. Jang R. Jansen J. Jargon B. Jarry P. Jarry A. Jelenski W. Jemison S.-K. Jeng M. Jensen E. Jerby G. Jerinic T. Jerse P. Jia D. Jiao J.-M. Jin J. Johansson R. Johnk W. Joines K. Jokela S. Jones U. Jordan L. Josefsson K. Joshin J. Joubert R. Kagiwada T. Kaho M. Kahrs D. Kajfez S. Kalenitchenko B. Kalinikos H. Kamitsuna R. Kamuoa M. Kanda S.-H. Kang P. Kangaslahtii B. Kapilevich K. Karkkainen M. Kärkkäinen A. Karpov R. Karumudi A. Kashif T. Kashiwa L. Katehi A. Katz R. Kaul S. Kawakami S. Kawasaki M. Kazimierczuk R. Keam S. Kee S. Kenney A. Kerr O. Kesler L. Kettunen M.-A. Khan J. Kiang O. Kilic H. Kim I. Kim J.-P. Kim W. Kim C. King R. King A. Kirilenko V. Kisel A. Kishk T. Kitamura T. Kitazawa M.-J. Kitlinski K. Kiziloglu R. Knerr R. Knöchel L. Knockaert K. Kobayashi Y. Kobayashi G. Kobidze P. Koert T. Kolding N. Kolias B. Kolner B. Kolundzija J. Komiak A. Komiyama G. Kompa B. Kopp B. Kormanyos K. Kornegay M. Koshiba T. Kosmanis J. Kot A. Kraszewski T. Krems J. Kretzschmar K. Krishnamurthy C. Krowne V. Krozer J. Krupka W. Kruppa H. Kubo C. Kudsia S. Kudszus E. Kuester Y. Kuga W. Kuhn T. Kuki M. Kumar J. Kuno J.-T. Kuo P.-W. Kuo H. Kurebayashi T. Kuri F. KurokI L. Kushner N. Kuster M. Kuzuhara Y.-W. Kwon I. Lager R. Lai J. Lamb P. Lampariello M. Lanagan M. Lancaster U. Langmann G. Lapin T. Larsen J. Larson L. Larson J. Laskar M. Laso A. Lauer J.-J. Laurin G. Lazzi F. Le Pennec J.-F. Lee J.-J. Lee J.-S. Lee K. Lee S.-G. Lee T. Lee K. Leong T.-E. Leong Y.-C. Leong R. Leoni M. Lerouge K.-W. Leung Y. Leviatan R. Levy L.-W. Li Y.-M. Li

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