Hardware Support of Parallel Asynchronous Processes

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HELSINKI UNIVERSITY OF TECHNOLOGY DIGITAL S YSTEMS LABORATORY Series A: Research Reports No. 2; September 1987

ISSN 0783-5396 ISBN 951-754-259-3

Hardware Support of Parallel Asynchronous Processes* VICTOR

I.

(?>

_.

e

/

VARSHAVSKY

Pr0fessor, Doctor of Engineering Computer Science Department

V.I.

Ulyanov ( Lenin

Prof. Popov Str. 5

)

Electrical Engineering Institute

197022 Leningrad

USSR

Abstract: These lecture notes have been prepared by Prof. V .I. Varshavsky in co­ operation with Dr. V.B. Marakhovsky, Dr. V:A. Peschansky, and Dr. L.Ya. Rosen­ blum of the same institute. The lectures were given by Prof. Varsh.vsky at the Helsinki University of Technology between December 5, 1982 and February 5, 1983. Keywords: Asynchronous processes, self-timed circuits, self-synchronizing cir­ cuits, aperiodic circuits, Muller-diagrams, Petri Nets.

•Translated rom Russian by Dr. Tech. Goran Pulkkis (Helsinki University of Technology) and M. Sc. Jorma Ylonen (Valmet Automation Projects).

Printing: TKK monistamo, 1987 Helsinki University of Technology Digital Systems Laboratory Otaniemi, Otakaari 5 A SF-02150 ESPOO, FINLAND

Phone:

90 460 144 +358-0

Telex: 123 889 hutel sf

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PREFACE

These papers are to be a collection of lecture notes presented by myself in 1982/83 at Helsinki University of Technology. Due to various resons the publication of the text hs been delayed and it is quite natural that the reader may sk: "Perhaps all that stuf is incredibly out of date?". To be rank I have also set such a question to myself. n

fact, during lst four years my research team (rom Computing Science Depart­ ment of Leningrad Ulyanov (Lenin) Electrical Engineering Institute) hs advanced a great deal in the theory and practice of self-timing. First, the new book ("Automata control of synchronous processes in computers and discrete systems", in Russian, Moscow, N auka, 1986) was published which covered by luck just only a part of these notes. Second, we obtained a number of new circuit design solutions or standard self­ timed modules comprising a library of basic circuit cells which are substantially diferent rom those described in the book s well s in this text. In particular, it hs been shown that the do.uble-rail self-timed CMOS implementation does not at all require that the number of transistors involved in it is twice those involved in a single-rail synchronous design version, thereby refuting the common prejudice against self-timed designs. Third, the pass from the gate level onto the transistor level in the synthesis proce­ dures has clearly shown the feasibility of the correct implementation of distributive circuits which are insensitive to wire and transistor switching delays, i.e. to those which are linked not only to the outputs of gates but also to the inputs of these. On the other hand, the analysis of the current literature shows that the problems which are under consideration in the lecture notes remain topical and have been so far unknown to the English-reading audience. I

would like to draw the reader's attention to the fact that the whole study reviewed in these lectures aims at the major goal of the synthesis of computing and control circuits. A number of methodological problems are of major concern here. First of all it is worth noting that the synthesis of delay-independent and self-timed circuits is far more tricky than that of conventional clocked circuits. This fact, however, should not confuse us since the "dimensional explosion" is by and large an item relating all kinds of circuits. Any concrete devices found in practice have a modular structure. This modularity is an inevitable consequence of the modularity of their source design speciication. We are unable to deine such a speciication if it is going to have an

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exponential complexity. Thus, since we have obtained the design description of our device using a high level language and this description is of a limited complexity then it is hopeful that the implementation of the device will have a complexity which is commensurable with that of the initial specification. This seems to reer to a theorem which I heard in the

60,s rom Proessor A.S.

Kronrod.

M2 with corresponding instruction sets i and I2 while S(P, I) is . store e.p.city which must be allocated or the program of tsk P using instruction set l. Then or any P, /i, 12, Let us have two mchines M1 and

S(P, i) - S(P, 12) where

T(I1, I2)

=

T(li, I2),

is a constant which is invariant to the tsk

the instruction sets of both machines Mi and The proof is quite trivial:

T(Ii, 12)

P and

depends only on

M2.

is a store capacity which must be allocated or

the interpreter of the instruction set

I2

by instructions from /i.

This theorem which can surely be regarded s a joke is meanwhile a source of valu­ able ideas of how to transer from the high level specification of systems behaviour to the systems description with a circuitry notation. I would be most pleased if the reader would bear this concept in mind. It will be thoroughly accounted in a new book which we are working on. The content of my lectures is bsed on the results obtained rom the cooperative research with my colleagues L . Ya. Rosenblum, V.B. Marakhovsky, B.S. Tsirlin, M.A. Kishinevsky, A.R. Taubin who s well s A . V . Yakovlev actively participated in the preparation of the lectures text. Sharing in full degree the authorship with them I also have to take the responsibility or any possible errors. I would like to thank Proessor Leo Ojala for his support during my visits to Helsinki University of Technology in

1982/83 and 1986/87.

I also thank him and Dr. Goran

Pulkkis for their organizational assistance in prepairing and publishing this text. Helsinki, December V . Varshavsky

1986

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Contents

1

1

INTRODUCTION

2

ASYNCHRONOUS PROCESSES AND TEIR INTERPRETA-

11

TION 2.1

2.2

3

Asynchronous Processes

11

2.1.1

Deinitions

2.1.2

Some subclsses

15

2.1.3

Reposition .

. .

19

2.1.4

Structurization

21

2.1.5

An asynchronous process s . met.model

23

11

. . .

Petri Nets . . . . . . . . .

24

2.2.l

Model description

24

2.2.2

Some classes

27

2.2.3

Interpretation .

27

2.3

Signal Graphs .

2.4

The Muller Model

32

2.5

Parallel Asynchronous Block Diagrams .

36

2.6

Asynchronous Automata. . . .. .

39

SELF-SYNCHRONIZING CODES

42

. .

30

3.1

Preliminary Deinitions

.

42

3.2

Codes with Straight Transitions .

45

3.3

Two-phased Codes

47

3.4

Double-rail Code

49

. . .

.

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4

3.5 Code with Identiiers . . .

50

3.6 Optimally Balanced Code

53

3.7 On the Redundancy of Codes

55

3.8 Coding "by changes" {One-phse Code)

57

SYNTHESIS OF SPEED NDEPENDENT CiCUITS

59

4.1

Introduction . . . . . . . . . . . . . . . . . .

59

4.2 Synthesis of Circuits from Muller Diagrams

66

4.3 Synthesis of Circuits using Petri Nets . . . .

85

4.4 Implementation of Parallel Asynchronous Block Diagrams

94

4.5 Synthesis of Circuits Deined by Finite Automata, and the Problem of Matching with the Environment . . . . . . . . . . . . . . . . . . . 106 5

ANALYSIS OF ASYNCHRONOUS CIRCUITS

114

5.1 A Model of an Asynchronous Logical Circuit

115

5.2 Reachability Analysis . . . . . . . . . . . . .

117

5.3 Reduction of the Reachability Problem to the Problem of Reachabil. . . . . . . . . . . . ity through Neighbourhood .

120

5.4 Semimodular Circuits . . . .

126

5.5 The Set of Operational States .

133

5.6 A Circuit Model with Non-zero Delays of Interconnection Wires .

142

5.7 Analysis of the Sensitivity to Wire Delays

147

5.8 Circuits Insensitive to Wire Delays . . . .

150

5.9 Reduction of the Complexity of the Solutions to Analysis Problems . 152 5.10 Asynchronous Circuit Analysis by Petri Nets . . . . . . . . . . . . . 160

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6

ANOMALOUS BEHAVIOUR OF LOGICAL CIRCUITS D TE ARBITRATION PROBLEM

166

6.1 Arbitration Circuits

169

6.2 Oscillatory Anomaly

171

6.3 Metastability Anomaly .

174

6.4 Design of Correctly Operating Arbiters .

178

6.5 1

"Limited" Arbiters and Safe Inertial Delays

181

DIAGNOSTIC PROPERTIES OF APERIODIC CIRCUITS AND SELF-REPAIR

189

7.1 Structural Peculiarities of Aperiodic Circuits and lndicatability Prop. . . . . . . . . . . 190 erties . . . . . . . . . . . . . . . . . . . . . . 7.2 Total Self-checking in Aperiodic Circuits .

204

7 3 Fault Detection of Autonomous Circuits

209

7.4 Self-repair Organization .

219

.

8

.

. .

Coments on the Bibliography

226

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INTRODUCTION

�fodern control systems include a very important subclass of systems - control leYices with a discrete state set or the coordination of process flow. This does not, ::owever, exclude the presence of continuous (analogue) variables. For instance, dis­ ?lacement of the tool of a metal-cutting machine is characterized by the coordinates of the cutting edge of the tool, by the changing speeds of these coordinates, by the components of the orces on the tool, etc. However, such variables as turn-on and :un-of of the eeding engine, the state of the reduction gear, the presence of infor­ :ation about the future mode of operation deine the system's discrete states. A equence of these realizes the discrete control of the machining process. A number of such examples can be ound in various fields: control of the starting and stopping o! a power plant, control of motions and displacements of robot crabs, control of data transer (realization of communication protocols) in inormation and control systems, computer network, to mention a few. Following essential characteristics of such control systems are given below: a) matching - the processes (and their component subprocesses) should have explicit phases, during which the process state changes (phase transition) are executed. The control systems should in any phase get inormation about the end of the phase, which in turn initiates the next phse transitions; b) parallelism - the possibility of simultaneous phase transitions in many sub­ processes; c) asynchrony - the absence of time bounds on phse transitions, which depend on many uncontrolled factors. We will use the term "transition" or briefness when the phase transitions are dis­ cussed below. Parallelism and asynchrony are natural characteristics of practically all technical systems. They are present both in control systems and in controlled objects . Vari­ ations in transition times in elements and blocks of control systems and communi­ cations channels are caused both by a spread of values of technological parameters and by changes in the physical operating conditions - temperature, pressure etc. Asynchrony requires the invariance of system operation with respect to transition time variations - except when the transition time is essential or the control pro­ css inormation. Matching is a less clear characteristic, which follows from the requirement of functional determinism of the system. This is necessary for realizing the wanted operation of the controlled object and represents cause-consequence ties of interaction between the object and the control system. The fact that the control system is a matched parallel asynchronous system with functional characteristics

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defined by the interaction of the system with the controlled object and the envi­ ronment, enables us to consider the pair "controlled object - control system" s a unit. Since we examine a system with a inite set of states, it is natural to use a inite automaton as a model of such a system. However, the diiculty of using the clssical model of inite automaton lies in the fact that this model ignores the concept of physical time. Thus, every time, when the problem of the technical realization of a finite automaton is encountered, there arises the necessity for essential changes in the initial model: a technical device representing a inite automaton will be a dynamic system with all the characteristics of such a system. B a rule, modern technology tries to solve the diiculties resulting rom these problems by means of external synchronization systems. There are two types of synchronization systems. If transition times in elements and blocks are limited and their upper bounds are known, then the influence of physical time is eliminated by a recognition of the system's state after the completion of all transitions. A new cycle of phse changes is initiated only after the transitions in the state recognition system have stopped. There are techniques, however, which do not disturb the common principle of synchronization. Such synchronization is promising because it can be esily implemented physically. On the other hand, if there re variations in transition times, then the device operation gets essentially slower in such an approach. f the transition time exceeds a given upper limit, then incorrect operation of the whole system may follow. The latter efect, i.e. the parametric fault, is one of the most common sources of ailure. It is well known to computer engineers; in the case of malfunction they irst try to eliminate it by lowering the frequency of the clock generator. In cases where the transition times in some blocks considerably exceed the transi­ tion times in other blocks of the system, or when the time variations .re so great that it is not efective to use the first type of synchronization, then the recogni­ tion of a new state is realized using periodical probing of synchronous signals by clock signals. A typical example of such . synchronization is the interrupt han­ dling system. One could imagine that incresing the frequency of probing (clock ) signals and the speed of logic elements would lead to s exact synchronization s wanted. However, these expectations were strongly ruined after the arbitration efect ws detected and analyzed. Now the impossibility to implement absolutely reliable arbiters, synchronizers and inertial delays without the use of analogous cir­ cuits (or instance, comparators) can be considered an established fact. The greater the probing frequency grows, the more probable is the occurrence of arbitration sit­ uations. Moreover, with growing speeds of logic elements there is an increase in the relative duration of metastable states of circuits provided with memory. Thus, in spite of the wide use of synchronous systems in modern technology, there are apparent diiculties to increse the speed of such systems. They get even worse with the use of submicron technology, in which the bsic signal propagation delays

-3! ly e.used by wires.

The variations of delay in wires may by hundreds of

� exced the delays in transistor junctions.

The opinion of many leading re­

�-.ies s that the use of the principle of external synchronization in the next

�ations of very large scale .nd high speed integrated circuits is very problem­ _

n submicronic integrated circuits the dimensions of transistor junctions are

�g some thousands of atom radiuses, the zones of interaction are getting

rable with the wave length of interaction signals. In connection with this you : k about equichronic zones, i.e. about zones, the components of which are

n:ing

"n

the same time", and about problems of matching (synchronizing)

� .:ctioning of objects situated in various equichronic zones of the chip, though

. !�ulation of such problems today may be considered as speculation. By the

w of the complexity of systems the problems occurring at the microlevel are

d o at the system level, or instance, in synchronizing multimicroprocessor

�-

:.g no account the fact that the term synchronization means a set of per­

:y .ned technical solutions, it is rational to avoid it and rather speak about �g the time behaviour of complex systems or about controlling parallel syn­ ."s processes. Here we shall be interested in diferent levels of abstraction in

�ptions - beginning rom transistors and wires to very complex devices - or

h the model of functioning can be regarded s a process with a discrete set of

. It should be very interesting to have a possibility to consider a system at ._ Tes of abstraction rom a uniied methodological position.

ri of all, what we mean by the term "time" hs to be defined more exactly. The

)'clopedia of physics deines this concept in the ollowing way: "Time is a set of

os expressing the coordination of states (phenomena), their sequence and du­ �n·. From this deinition follows that there is no other way to express the time :: through the relationships between observed events. External synchronization

• a ss of setting relationships between events in a systems through a sequence

i enns external to the system - changes of state of external "clocks" . Events

ni place in an external clock do not in principle have any cause-consequence

mctions with the events in the system and with the interaction with the system s.onment: "After this doesn't mean because of this". This methodological fact •

eTidently the source of diiculties which occur in the design of external synchr­

uion systems. From another point on view, the state changes of systems taking

en

real physical time give rise to a set of relationships describing the coor­

&tion of events in the system and in the environment interacting with it. This wt of relationship appears to be the system time for the given specific system and

mronment. Time slicing using events occurring in the system and in the environ­ �t rather than

in an external clock leads us to the concept of self-synchronization

elf-timing). The attractiveness of this concept essentially depends on the possibil­

' t0 use it in technical applications, particularly in the design of matched parallel

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asynchronous systems. We are going to throw some light on these questions. As mentioned above, a matched parallel asynchronous system is a set of interacting elements (blocks, subprocesses) . An event in such a system is a transition - a change of the system state. For solving the tsks that lie ahead of us we irst need a representation method giving us a possibility to describe such systems at various levels of abstraction (and which maintains the invariance of the description in external physical time) .nd a set of relationships between events deining the system time. Eforts of formalizing the system of relationships or the deinition of time were made by Aristotle, but the irst rigorous system was evidently proposed by J.N. Findley in 1941 in the article "Time: an overview of some mysteries". However, almost 20 years elapsed beore there appeared works formalizing the relationships between event in systems. In 1959 D.E. Muller and W.S. Bartky proposed a model called transition di agrams or Muller diagrams or the description of synchronous circuits (Muller circuits) . n 1962 C.A. Petri proposed a model (now called Petri nets) giving a possibility to describe lows of discrete events independently of the duration of these events. Both of the mentioned models hs advantages and limitations. However, because of resons not clear enough Petri nets is an example of a rather fshionable and rapidly developing are. of knowledge, but the language of Muller diagrams is far less popular than it deserves. When irst examining the operation of a system we can neglect the exact description of cause-sequence relationships between events and only maintain the occurrence possibility of such relationships. At this stage it is natural to propose a certain metam . odel with the possibility of various modelling and semantic interpretations. Such a model, in which the relationships between the stages of the system relect only the logical conditions of their ordering, is called an asynchronous process. The realiz.tion of various logical conditions s here deined both s internal semantics of the system and s environmental factors external to the system. Taking into account external factors is, irstly, not needed and secondly, impos­ sible. However, it is essential that we can consider also the environment s an asynchronous process. Another system interacting with a given system can be considered s a component of the environment. The language of synchronous pr­ cesses allows already at this level of abstraction the solution of principal problems of process and system composition. By the matching of processes there occurs the necessity to implement an additional matching process, which can be considered s a formal model of the interaction protocol between the system and the environment. The irst step connected with the registration of the semantics of system processes is reduced to the interpretation of an synchronous process by a language of a lower level of abstraction. Petri nets, Muller diagrams, parallel asynchronous graph

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, nd inite automata are used here as such languages. A structurization of � 5 of the initial processes is performed for implementing the interpretation :: o for olving tasks of matching and composition. It consists of an explicit �tation of events leading to the state changes of the asynchronous process.

...

- ��ate goal is the construction of . composition of ( controlled) subprocesses :: & ontrol system. First we ignore the control system itself and consider only the ��ation of transitions in subprocesses. In structurized subprocesses two types l .�:s can be pointed out: dat. variables characterizing (informational, ener­ � &terial) inputs and internal states of the subprocesses, and phase (control) .s starting and ending new transitions. 'r !rity we shall consider binary phse variables. They will be used for struc­ ::g the states of an asynchronous process at the description level of the control � �foreover, we shall assume that a transition initiated by an input phse .. ��e exactly repeats the value of the input phse variable. From this ollows : e subproceses can be represented s a delay in relation to the phse vari­ e. he lue of which is undeined and exposed to uncontrolled changes. The only :�ion s that the delay is inite. f the functioning of subprocesses meets the in­ d rstriction, then a system description constructed in that way relects the ) cordination of phses of subprocesses independently of the execution times � ee subprocesses. Hence, such a description contains suicient information for l system design but leaves the question about techniques unsolven. a

ng rom control process deinition languages to control system descriptions ct of all should deal with the problem of coding the phse variables of sub­ c as and the states of the system s a whole. Codes meeting the demands ry for organizing the control will be studied in Chapter 3 and are called �chronizing codes. Since binary coding of variables is introduced, we shall der s control system elements functional elements, the input-output function­ g f which s expressed by Boolean functions or inite-automaton equations. We l. ay that a circuit made from functional elements models the control system by l..Jsynchronous subprocesses given in one of the above mentioned languages, 1!

�

a) b) c

ie

description is homomorphic to the initial transition diagram of the circuits in the sense that the order of variables common to the initial and expanded transition diagrams coincide, o

each phse signal corresponds exactly one output of the functional element of the circuits.

) the operation of the circuit does not depend on the element delay values of its elements.

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6

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Thus, if a circuit models a control system, then - because of the independence of t. delay values of functional elements modelling phse variables - delays of arbitr�J

values can be connected n series with these elements. Hence, the modelling circuia provides the required phse coordination of concurrently unctioning subproce, i.e. the required operation of a system, which is independent of the delay values m its elements. It is thus

.

homomorphic expansion of the initial description of systm

operation. Our interest now turns to the theory of speed independent circuits (Muller circuis The classical theory of such circuits - ounded by Muller and Bartky - actully left unsolved the questions about the possibilities of synthesis of elements of a limited basis and questions about the interaction between such a system and te

aperiodic automat�

environment. These restrictions were overcome in the theory of which is an essential extension of the theory of Muller circuits.

The Muller diagrams were introduced for circuit analysis concerning the functionM

independence of the element delays. On the other hand, describing circuits tb&

satisfy the requirements of semimodularity can be derived using Muller diagr.. However, this procedure doesn't solve the synthesis problem, because it may lead o the necessity of using elements, or which - when using existing technologies - t.

initial preconditions of Muller theory are not fulilled (for instance, it appears to e impossible to reduce the delay of an element to its output). For some elements then

just may not exist a race-free technical realization. However, s will be shown, fr any Muller diagram with k variables there exists

.

semimodular expanded Mulr

diagram or which the initial diagram is a projection of the expanded diagram a the set of initial variables. Moreover, the expanded diagram may be realized f AND-OR-NOT elements. Such an approach opens up the possibility of implementing an arbitrary Mulr diagram by a circuit which models it in an AND-OR-NOT bsis. Because of d­ ality consideration this result applies also to the bsis OR-AND-NOT. We notie that we are speaking about an unrestricted bsis. The technological requiremena restrict the possibilities of using this method.

Thus there arises the question l

minimal circuit bses. Such bases are: for distributive Muller diagrams - 2-in& NAND elements

(or

dually 2-input NOR), and for arbitrary

emimodular

Mulls

diagrams - 2-input NAND + 2-input NOR. The proofs of functional completenm are constructive in the sense that they supply useful synthesis methods.

The language of safe persistent Petri nets also allows a direct transormation e modeling circuits which are independent of element delays.

For these purp8

there are standard circuits, n which any place of a Petri net is modelled by one i

only one fli-Hop, and every event (transition) by one and only one wire. A marks of the net is modelled by the states of the mentioned Hip-lop, and the occurrenm

of a transition by the sequence 1-1 or -10 in the corresponding wire. A circ&

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..s redundant elements and wires. However (what is important for our pur­ s .

s homomorphic to the initial Petri net. The circuit basis for constructing

it

1: cis consists of AND-OR-NOT or OR-AND-NOT and the minimal basis

5 of 2-input NANO or 2-input NOR (s also in the case of realization from ::._ti·e Muller diagrams). This means that the language of semimodular Muller

� s more powerful than that of sae persistent Petri nets. In any case, we � � �ceed

n finding a description method for nondistributive and semimodular

.e &grams by the language of safe and persistent Petri nets.

� .:::age of synchronous graph-schemes describes concurrent functioning of ss represented by operators. In fact, or the design of a speed indepen­

:: :l.t modelling a parallel synchronous graph-scheme it is enough to imple­ : & el of circuits modelling ragments of a parallel synchronous graph-scheme.

L�. J. Dennis proposed the ollowing set of fragments: bifurcator, ssembly,

-:e i r, conditional transition and operator. This is, however, insuicient for r -�-al system implementation methods. It is necessary to use a special block

� the isolation of phse signals of the subprocess representing the repeated �- Such a block is called a

multiple entry automaton.

i='·x J of a set of standard blocks is considered for two phse disciplines in &

: S)·stem.

� �e

In the irst one the control system hs two functional phases.

fst phse the initiation of subprocesses is realized. In the second phse

� e termination of the irst phse) the subprocesses (and the blocks, realizing �n to the initial states. In the second discipline both phse transitions

c e

bpr sses are realized in every functional phse of a control device. In

� e the blocks have diferent circuit complexity, and the choice of discipline

.

evey

time on the concrete requirements of the control system.

ll t S, specially when the process essentially depends on external informa­

�

cordination of subprocesses appears to be specified by the language of

:uos automata. The code of states is defined by the set of phse signals - �e change conditions by signals from the environment. In this case the _ '&circuit may be considered by the environment s a subprocess having an

- �signal (sometimes - a few phase signals), which initiates the change a � .&

:nl state of the circuit, and having an output phase signal (signals),

os the environment about the termination of transient processes and

e ssibility of changing the data and the phse signals in the input of

�t. A circuit, which does not depend on the delays, is called an aperiodic :.n.

It s possible to construct a corresponding aperiodic automaton for any

� :vmaton. Two methods can be used:

a

a ndrd procedure for synthesis of an automaton with a memory using �:p-los or T-flip-flops and methods or indicating the termination events

l t.sient processes;

-8b) a procedure for dcribing n aeiic automaton s a composition of Muller circuits, implementing transition diagrams or fixed values of the input vari­

ables; here the interaction �ith the environment is provided by breaking some wires and closing them through the environment. The organization of the interaction with the environment is very similar to the interconnection of semimodular circuits using the Muller theorem. In some cases the nature of interaction is such that there arises the need or arbitra­ tion, for which the methods to handle them cause essential delays in the functioning of devices. Thus, for instance, any preliminary ordering of procedures or usage of a common resource by many subprocesses either does not exclude arbitration or may cause a long halt at a process, if one of the subprocesses does not need the required real source.

The presence of arbitration situations is connected with a

violation of persistence of Petri nets and of the semimodularity of Muller diagrams and causes an anomalous functioning of corresponding circuits.

Research on the

arbitration phenomenon regarding the dynamic characteristics of circuit design ele­ ments shows that using logical elements it is impossible to implement an absolutely safe arbitration circuit ree rom metastable or oscillating anomaly. On the other hand, the transition of the diference between the voltages on its poles beyond a threshold value is the condition for the transition of a flip-lop out of an anomalous state, which gives the possibility to display the termination of anomaly by analogue comparators. In this cse, time independent circuits may be implemented for the control of processes, which include arbitration situations. Hence, the clss of situa­ tions and processes modelled by control circuits can be essentially expanded. Here, however, .rises the quite essential problem of recovery rom such situations. The problem of analysis is connected not only with the tsk of recovery rom arbitration situations. The fact is that the above mentioned synthesis methods provide means to design delay independent circuits, if the initial descriptions don't include arbi­

tration situations. M many universal methods, they are, however, excellent or all

cases, but they may turn out to be highly redundant in every concrete cse. This is conirmed by the century-old experience of the evolution of technology. However, the circuits designed in that way require a verification of their time independence and of their functional correspondence to the initial specification. Though the com­ mon indications of delay independence of circuits were published already by Muller, their direct verification using transition diagrams is very diicult: the complexity of this task grows exponentially with the number of elements in circuit. Analysis methods, which in acceptable time (using computers) allows us to verify circuits including up to hundreds of elements are considered here. Speed independent circuits have one very useful property. A constant fault of an elements s equivalent to the appearance of an infinitely long delay in it. This means

that f an element should switch ccording to the functional logic of a circuit, then in

the cse of a constant fault the further operation of the circuit terminates. This fact

-9nt

fron two points of view. First, time independent circuits are sae in

�t

or many control systems. Secondly, it is possible to prove rigorously

--I oStant faults in the sense that the operation of the circuit terminates, which w

:icircuits are completely self-testable relative to constant faults of elements. � ene of constant, or so called stuck-at, fault may be covered by temporal

;

:ne of the circuits - we can always define a critical time, during which

n ould occur an activation of the given signal in the circuit. The absence of

. i ctivation during the critical time interval tells about the presence of a fault �

cit. This allows us to localize the fault to some standard building block

� scial tests and using only a simple internal control circuit. The possibility

;

�Te

n electrical signal from a local ault allows the organization of circuit

!--r. It is especially attractive or circuits with a high level of homogeneity � · for instance, a memory, where one reserve cell and one numeric (binary

)

ay e used s a reserve space for the whole memory. For compensating faults

a c 1thmetic-logic unit it is enough to have one spare block for each fault. As an

-.. -_ · .i••e example is presented a counter circuit, which compensates one fault at

ee of one spare bit block. However, the above mentioned does not concern

�bility of a fault during the switching time of an element, because such a

•

:&y rsult in an arbitration situation or switch the system to a state, which is

. :lded in the functioning conditions of the system. Problems associated with

�

�s require additional research.

�-.� ·os ormulated here and described rather completely have a wider application �.n the design of control systems. The .periodic automata themselves can w �reted s synchronous processes s ws already mentioned above. This fact � wide possibilities of modular synthesis for self-timed computer and control

--.!of high complexity, where both standard units of computer technology and

>mputer systems can be used s blocks. In this case one can speak about a

l"hy .

:·:y

of modular descriptions.

important clss of devices, or which the stated methods and approaches

� o be efective, are the interf aces. The class of interfaces is wide - rom

r .urlce between equichronic zones in VLSI circuits and the interfaces between

:;- a interfaces between modules, interf aces between computers and interfaces � himicroprocessor systems. 1 =

Typical for such systems is:

"ll communication channels with uncontrolled delays, .

� delays

)

in bundled parallel wires,

3)

2)

1)

the necessity to

skews

( "distortions"

interaction between devices to be in­

�ed, whose response time is unpredictable.

n addition, rom the viewpoint

. J-repair techniques the interfaces are interesting because of the homogeneity d � communication channels and the receiver-transmitter devices. Examples of

ynchronizing interfaces, which are independent of delays in communication

nes and in the elements of a control system, are good illustrations of the efec­

- css of the proposed approaches. It should be mentioned that self-synchronizing

- 10interfs rquie u

�i o he

ormation by the i'.

channels the

a w

w

transmitter about reception of the in·

f -ey long delays in the communication

ed f e sm i n dd compared to synchronous systems. annctjve features of self.synchronizing

In this e, n order o ae te c l e

circuits, it maks ee o ot hyid syncronous self.synchronizing system in order to support high

ed.

s

on, however,

deviates rom the main

topic. An essential reserve or incresing system perfomance of interfaces and some data processing systems is process pipelining.

The orgnization of an synchronous

pipeline is most efective. The design of synchronous pipeline structures inevitably requires design of matched parallel synchronous systems and control circuits with speed independent characteristics. The corresponding modelling circuits also illus­ trate the application of obtained results.

- 112

��CHRONOUS PROCESSES AND THEIR 1"­ TRPRETATION

n

s.

.g

n

ll

lS

ly th

IS-

S:

le designers of discrete computer, informational and control systems .:: .ith a number of models, which allow to describe the dynamics of the ll. . thse systems with regard to the possible parallelism (concurrency) a synchrony of interaction of their subsystems. Any one of these models 11• r spects of system operation. That is why they have a restricted appli­ � -:. �heless, the presence of common characteristics of such models allows :ee a methodologically convenient metamodel, which may support some �¥A- odels. The mechanisms of such n outcome is defined by interpreti:g w ncepts of the metamodel. �

�el will here be used a formalization, which is called an "asynchrono.!

l. l

nchronous Processes

LL.l

itions

=n 2.1 ·

T

t a

tonempty set of situationB;

relation deined on the set P(S) of subsets of Bituations, which assignA i?me subset of situations a E P(S) another subset of situations 3 E P(S),

u •

z

t =

·

An asynchronous process P is a quadruple (S, F, I, .), in whid:

3;

u s ut : • •'r

of initiators I E P ( S ) such that any i E I, iFa is fulilled

. / i iFa !.

< •

:

.',r any i E I there is no a, a� I Buch that aFi;

:1 • E� =

�

x":!

and a� I, then from aF3 follows that J .I;

=

of resultants . 0

c

P { S), such that any r E

.

implies a E

for some asynchronous process then such a process

.

s

if r Fa. called au­

- 12 -

Conunents to

D e i it io

n

n

,, The words "situation" and "process must be understood in the general sense. "Situation (from lat. siius position) is a combi­ nation of conditions and circumstances, which create conditions, position" . ( GSE, 2. edition, vol. 39, p. 182). The concretization of the term "situation" depends on the interpretation of the concept of an asynchronous process and will be given below. It should be pointed out that an synchronous process can be in one and only one situation at any observation moment. "Process (lat. processus - move­ ment forward, from procedo I move forward) is . . . sequential changes of some object or phenomenon, in which is expressed certain obj ective regularities . . . ; a set of consequential actions directed to the achievement of a certain result . . . " (GSE, 2. edition, vol. 35, p. 177) . In our case a process describes the dynamics of the change of situations. The term "process" is specified by the adjective "syn­ chronous" . This specifications shows that the category of time is not ormally used in the definition: if aF 3, then the transition time from the subset of situations to the subset of situations 3 is not specified. It may be arbitrary, but finite. 2.1

-

-

The introduced relation F is a sequence relation and may be understood as a "logical necessity" . In other words: the notation aF3 means that a is a set of reasons and 3 is a set of possible consequences. The relation F, which is defined on the set of subsets of situations, emphsizes the nondeterminism of an asynchronous process. The latter reflects, in particular, also the "approximativity" of the speciication of an asynchronous process. This is caused by the absence of exact knowledge about the fact, in which of the situations of the set a the process is and to which of the situations of the set 3 it should move. The initiators, which activate a process, constitute a subset of situations. The purpose of the initiators is worked out on the bsis of the process semantics. The restrictions set on the choice of initiators introduced in Definition 2.1 only indicates that an initiator cannot be only a consequence of some subset of situations; it must al ways be a reson. Resultants are subsets of final situations. Their choice is also made on the basis of the process semantics. The restriction in Deinition 2.1 means that a resultant cannot be only a reson; it must always be a consequence of some reason. By the definition or resultants we essentially emphasized that if some situations rom R is announced as a resultant, then any other situation "following it" is also a resultant. Example 2 . 1

Let an asynchronous process be given in the following way: S { si, s2 , s3, s 4 , s5} , {s4, s2 } F { s3, s4, s s}, { s i , s2 , s3 , s4} F {ss} , { si, s2}, I = {i 1 } 1 i1 R = {r1}, r1 {s5} =

=

=

In

this example the relation F is speciied on the set of subsets of situations in

- 13 • .! .ce with Deinition 2.1.

,r

c

Since the process at the observation moments is

the situations, there arises a question about the relations between the �;s 1·. e . about specifying more exactly the relation F. The concretization of •.

1ption of the process may be reached, if the relation M deined on

S

)

{si is n o t the reason of Si · siMsc and SjMSt may ->.sly be satisied. In this sense the relation M maintains some forms of

·�isition from Sj t o Sp

.

x

The record Sj.,M sp is then interpreted as the "logical impossibility "

;, s k .

-�

S

'he record Sj Msc is interpreted as "logical possibility" of the transition

' · �;t ·minism of an asynchronous process. If for some Sj there exists only one

� J t s; Ms c , then the "logical possibility" also means the "logical necessity" ..-{tion from s; to B k .

speciied by the relation M, then it is natural to specify the sets of

·

-

: and resultants • •.n

R

s subsets of the set

.Vf may be presented by a directed graph. Its vertices correspond to

Aa arc connects s; with sc if s; M sc.

•

The situations s1 and Sm , or

- .•.f �l nd sm.Ms1 are not connected by arcs.

...;�� •

S (J c S , R c S ) .

?.1

(continued)

Fig. 2. 1 . demonstrates two possible concretizations of

� -3� o u s process in Example 2.1 .

. : , ·s

Fig. 2.1,a corresponds to the relation

1 -\11 s4 , s1M1s5, ssM1s5, s4M1s5 and Fig. 2.1,b to the relation M2 :

i l-f:ss , s2M2s4, s2M2s5 , s3M2ss, s4Mzs5 .

•

n

.'.f describes the process more exactly than F. In particular, if

• : � �. •he:: for some p ir s; , sc a s.

E a U 3,

for which s;Msc may be satisied:

F

is

E 8

..! is transitive but not relexive, because in aFa ws not assumed n � l (though this is not essential) . As a matter of fact, neither is M ";us, or Fig. 2.1,a s1M1 s 5 , but s5iM1 s1 . We note that s;Msc does

·

• . mean that the process immediately reaches sc from the situation s ; .

;ce ,

s;Msc, s;Msz , s1Msc. Then the relation M for the given process

e represented as in Fig. 2.2,a. The study of the semantics of the

, -�o w that the process reaches the situation sc from the situation s,

-

· le situations si, though s; is the reson or both sc and s1. That is

.., : be some interest to further specify a process given on a ixed set

:- •

l'sing the above mentioned restriction or the fragment in Fig. 2.2,a, - deined s follows: s; F si, s1 F sc . The graph or this relation is the

(b)

(a) Fig.

2.1

(b)

(a) Fi g .

2.2

Fig. 2 . 3

- 15 � 2 .b

c

But if s3 may immediately be followed by Bk , then the graph of coincides with the graph of the relation M ( Fig. 2.2,a) .

?

.. _ _. _ _

•he

relation M is nothing else than a degree of the relation F. The 1eans that there are n - 1 intermediate situations Ba, sb, . . . , Sw, for , • � F t• . . . , swF Sk are satisied, i.e. there is a path of the length n - 1 · .e a:cs rom Si to Sk.

a·

c

I _ a.e

another deinition of an asynchronous process, which allows us to . ss on the necessary level of concreteness. This definition will be on. if Deinition 2.1 is not specifically mentioned.

·

2. 2

A n synchronous process {AP} P is quadruple ( S , F, I, R), where:

situation sequence, deined on the set S

x

S (F

C

e: o/ initiators {I C S}, i.e . such situations for which skFs1 implies : • s Fsk, i E I and sk E l;

•

•

,

:

.

. : of resultants (R

... c .

..

c

S }, i. e . of such situations for which s E R if rFs

o

Deinition 2.1, other letters should in fact be used here or the relation F, the initiators I and the resultants R in order to avoid

Som e subclasses

�

sequence (possibly ininite) of situations s(l)s(2) . . . s(i)s(i + 1). s(i) c.ement in the i:th place of the sequence. e

e

a

.� s.�uation sequences

can be ormed or an AP, in which or any i s(i)Fs(i+l) and in which no sequence is a part of another one. All such sequences acceptable. Every acceptable situation sequence describes a possible path -ogram situation changes ( a trajectory of an AP) and corresponds to the ..>· .on· of the AP. •

•

d

e=

from the above that it is always possible to build the relation M corre­ to the relation F. Indeed, if for situations s;, Sj there exists a trajectory , to s3, then siMs;.

-

nz

.

_ given an AP, or which:

- 16 -

1) or any i E I there exists a r E R, such that iMr; 2) for any r E . there eists an i E I , such that iMr; 3) there is no situation s i R , such that (iMs) and (s•Mr) or any i E 1 and r E .R; 4) there exists no situations Si and s;, such that (si . R), (s; . R), (siMs;), and (s;Msi)· Deinition 2 . 3

efective.

A n asynchronous process satisying t.e characteristics is 1-� called

Thus, all trajectories in an efective process lead from initiators to resultants (char­ acteristics 1, 3, 4) and each trajectory leading to a resultant starts rom one of the initiators (characteristic 2). An efective AP may be undetermined; i.e. it is possible that the process can reach diferent resultants rom some initiator.

Consider the AP P = ( S , F, 1, .) , S = {si, . . . , s6}, for which the relation F is given in Fig. 2.9. If for this A P 1 = {s1, s"}, . = {ss}, then the AP is not efective because the characteristic 1} is not satisied. If I = { s1} , R. {s2, s3, s5 , s6} , then the characteristic £) is not satisied. If I = {s1, s4 , }, R = { s2, s3, ss}, then the characteristic S} is not satisied. We remark that if I = {s1 , s4}, R = { ss , ss, s6}, then the restriction of Deinition 2.£ is not satisied. s3Fs2 is indeed satisied, but 83 E R and s2 . .R .

Example 2.2

=

The following deinition gives an efective AP:

For some subsets of the situation set S a relation E can be defined:

1) for Si , Sj E s SjEs;, f SiMs; and s;Msi; 2) or any s E S sEs (in contrst to Deinition 2.1). The condition 1) provides the symmetry and transitivity of the relation E (The transitivity of E ollows rom the transitivity of M), and the condition 2) provides the reflexivity of E. Hence, E is an equivalence relation. The relation E allows us to construct a factor-set of the set S , i.e. a partition T ::: { S1, . . . , Sp) of the set S into equivalence clsses. For equivalence clsse we define the relation F of immediate predecessor-successor relationship between clsses. All

the acceptable sequences of equivalence clsses deined by the relation F are inite (in contrst to the acceptable sequences for F deined of the set S x S , which

- 17 &f be

infinite) . Initial and inal elements may be found in the acceptable sequence l ses . We shall call such clsses initial and closing equivalence clsses.

n

the basis of the introduced concepts we can ormulate the ollowing statements.

1 . f some , 3. 4.

situation s is an initiator and s E S(j), where S(j) is an equivalence clss in the j:th place of some acceptable sequence, then all situations of the clsses S (l), . . . , S(j) in this sequence are initiators . f some situation s is a resultant and s E S(j), then all situations of the classes S(j), S(j + 1), . . . , S(q), where S(q) is the closing clss, are resultants.

Any initial class consists for an efective AP only on initiators and any closing clss only of resultants. Any equivalence clss of situations, which does not belong to the resultants, consists of one situation or an efective AP.

If in an efective asynchronous process every acceptable sequence f classes leads from an initial class to one and only one closing class, then such a «ess is called a controllable process.

inition 2.4

mce a restriction on the degree of nondeterminism in introduced in a controllable P: to every initiator corresponds only one closing class, i.e. any trajectory rom e given initiator leads to this closing clss.

mple 2.3 Consider an AP with a situation set S = {s1, . . . , s10} and a relation F

fiuen in Fig. tq,a. Fig. £.4,b shows the relation F for the equivalence classes of ntuation set of this AP.

e

fI

=

{ s11 s2, 83, 8( } , R = {87, sa, 891 s10}, then it is easy to see that this process is

cntrolla ble. If the relation F is eztended with the pair s2Fs., then the given AP �omes non-controllable (but stays efective). We introduce a concept, which turns out to be useful when considering fragments f 0me AP.

If the situations s, and sc of some asynchronous process are inter­ cnnected by the relation s, Msc (siF" sc), then a fragment of the process connecting l trajectories leading from Si to sc are called the transition s; - sc.

inition 2.5

h.rther on the following AP clss will also be used.

et

in an AP:

1) s i I ollows from iFs for any i E I and s E S ;

a

2) s . R ollows from sFr or any s E S and r E R .

other words, it is impossible to reach another initiator (resultant) from an initia­ r ( resultant) , i.e. every trajectory includes exactly on initiator and one resultant.

- 18 -

(b)

(a) fig.

2.4

ig. 2 . 5

- 19 ition 2.6

A n asynchronous process satisfying these characteristics is called

e. u

ample of a simple AP is shown in Fig. 2.1, and of a nonsimple one in Fig. 2.4.

�Y. it is useful to introduce the concept of the protocol of a simple AP. ition 2. 7

We shall call the relation Q ;; I ironous process.

x

. the protocol of a simple

� Otcol of a simple AP can be considered s a simple synchronous process, i or every pair (i, r) E Q , i E I , r E . , iQr takes place (an immediate :1:;1ence of the resultant after the initiator) . That is why the set of situations � protocol of a simple AP consists of only initiators and resultants: S = 1 U . . �g the transformation of a simple AP to its protocol the set of trajectories, � �� rom i to r through intermediate situations, are replaced by one arc for 11 r (i, r). A protocol is a convenient orm of "input-output" description of • llronous process. J

Reposition

:h&nism of the transition rom resultants to initiators ws not speciied ._ _ . :e framework of Deinitions 2.1. . . 2.4. The description of such a mech­ . s, however, necessary for achieving the efect of renewing an A P and its ,. 3 ctivizations. Such a mechanism will be specified by the reposition of an :os process. a ' n 2.8 The

reposition of an asynchronous process P = (S', F', I', R.1) such that

S Hou process '

S'

c -

1

u

. u S d ' I'

c -

R ' R'

c -

=

( S , F, 1 , .) is an

1'

.. " ieines the trajectories of the transitions from the elements of 1 ' �

. to of R.' � 1 possibly through a number of additional situations in S d : S � I S = 0 . If S' = J u R. u Sd, I' = R, .' = 1, then the reposition is p ete. If F' = 0, then no reposition exists. In the remaining cases the s u clled partial.

U

1

t

�t s g P.

�

'i

the situations rom S d do not belong to the description of the corre­

� � of n AP J -

=

S

P hs

-

S ",

and its complete reposition orms an autonomous process. If a a complete reposition, then for the corresponding AP pa {S a , pa) , F4 = F U F'. =

- 20 From Deinition

2.8 ollows that

the reposition is always an efective process.

For formulating the concept of a pipeline process it is also necessary to introduce the clss of repositions dened on simple AP's.

Deinition

2.9

A

trivial

reposition of a simple asynchronous process P = ( S , F, 1, R)

with a protocol Q is a simple asynchronous process P' = (S', F', I', R'}

with a protocol Q', such that S' = 1 u R , !' = R , R'

=

!,

Q' = 1' x R'

and i' F' r' is satisied for any pair (i', r') E Q'. A non-trivial reposition of a simple asynchronous process P is a simple asynchronous process P'' = (S", F", 1", R"} such that S" = J" u R, I" c S \ R , R" = 1 , Q" = I" x R" and i"F"r" is sati.sied for any pair (i", r") E Q" . As is seen from this definition, a trivial reposition difers from a nontrivial one in such a way that only the resultants of the process P may be used s reposition initiators.

However, a nontrivial reposition may have some initiators, which are

situations diferent from the resultants of the process

P.

The resultants ollow

immediately after the initiators in both types of repositions. The union of an initial simple AP and its reposition (P' or P'') leads to an au­

tonomous process a ::: (Sa, 1)

sa = S

and

Fa},

Fa = S x S

such that

in the cse of a trivial reposition P',

2) sa � s (some additional situations s arise, which are not included in p P"), Fa C S a x Sa, Fa � F in the cse of a nontrivial reposition P" .

and

Deinition 2.10 In a simple autonomous process pa = (Sa, Fa}, which is formed by the union of the initial process P and its nontrivial reposition P", we separate the subset of situations S C S a coinciding with the situations S of the initial proces• and within them the initiators I and the resultants .; 1, R E S . If in any possibl order of initiators 1 the order of resultants R satisies the protocol of a simple asynchronous process Q c I x R (see Deinition 2. 7), then we shall call the proces P a pipeline process.

- 21 �1 �

die number of process situation changes rom an initiator i E I . is defined by the value n of the degree of the relation F. .. .,. n the number of situation changes from the initiator i E I to the •L ,. E :• s defined by the value m of the degree of the relation F . It is � � o evaluate the efectiveness of an asynchronous pipeline process as the ' = " m. It s obvious that 1) the minimal value of the coeicient K equals .evd by a trivial reposition, in which the process is not a pipeline -., = ?j the maimal value of K equals n and is reached when m = 1 . a

::�l r E

' !

&

nontrivial reposition is realized in such a way that m = 1, then it to calculate n; the coeicient K will be maximal independently of

,y , ,a

!on of the concept of a pipeline AP allows us to study the pipeline :iormation processing, which is bsed on the idea of a repeated AP Z. :: ·hich the AP has not yet reached a resultant. To illustrate the Ia - iple we shall use the ollowing analogy. Let us imagine an inclined ., •• ·� �s rolling balls in it. When the irst ball hs started, then another - � � --= on the higher end of the chute, then a third one etc. A ball can reach : ! one or fall behind but it cannot overrun the preceding one: having i: � :: rceding one the ball cannot roll further fster than the preceding ball. lwf i

•

1o t

A

l pieline

processes will be given below.

uctrization

m

iption of processes and for their deinition it is often necessary to ituations. The structurization may be done in various ways depending - s to be solved. M

�

: R -ays s the partitioning of situations into components

(events) ; to every ssign some predicate t , which gets the value 1, if the value oning logical conditions is true and the value zero in the opposite . tnation s represented in such . structurization by a binary vector with -nn qual to the number of semantically defined components. The number s - e vector corresponds to the number of true predicates. •••1 . • n :

we n

•

ze that attempts to use AP:s in applications should be based on a ::!erpretation and structurization of situations. Consider the following

:rr

ime 2.: There is a horizontal band transporter {Fig. �

-

2. 5) carrying parts of heavy and li"ght. The transporter is started by a starter. In the zone

- 22 A of the transporter there s a weighing-machine. The indicator of this machine switches on in case of heavy part and s unsensitive to a light one. Light parts art transported without machining to the end of the transporter, where they fall to a hopper. When a heaJy part appears in the zone A the transporter stops and a hand of a manipulator, which is in the initial position, grips the part. Then the drive of the manipulator moves the heavy part to the zone B and at the same time the transporter band is turned on. In the zone B, after a signal from the corresponding indicator, the grip lets the heavy part fall and the drive of the manipulator is actuated in the direction of the initial state. Then a new heavy part is found and the process i's repeated.

In this case it is possible to separate 11 components (from the point of view of the process control organization some of them may be redundant), to which correspond the following values of predicates:

P1 P2 P3 Pi Ps P6 r Ps Pg

= 1 - the transporter is started, = 1 - the transporter band starts moving = 1 signal "a heaJy object is in the zone A "1 = 1 the transporter band has stopped, = 1 the manipulator's hand is in the initial position, = 1 - the manipulator 's hand has gripped a heavy object, = 1 - actuating the hand's drive in the direction of the zone B, = 1 signal "the manipulator 's hand is in the zone B", = 1 the grip of a heavy object is turned down, = ia 1 a heavy object s in the zone B, Pu = 1 - actuating the hand's drive to the initial position. -

-

-

-

-

-

In the given case the situations are represent by a binary vector (Pi, P2 , . . . , P11}. For deinition of an AP only 9 of the 2 11 situations make sense. They are enumer­ ated below (components, which are not mentioned, are equal to O}. s1 s2

83 8& 85 86 87 8g 89 It is natural to choose I

=

P1 = P3 = Ps = 1, P2 = P3 = P6 = 1 , Pi = Ps = 1, p6 = 1, r = 1, Ps = P2 1, Pg = P2 = 1, P10 = P2 = Pu = 1, Ps = P10 = P6 = 1. =

{ 8 1 , 82, 83} and R

=

{ ss, sg} as sets of initiators an

- 23 rupectiuely. The sequence of situations is of the kind s1, s2, . . . , sg. A

w••

-:n of the example is given in the Section

!.!.9.

W . the structurization of situations presupposes the separation of input �

: cnmponents or only of one of them.

-

� mponents a situation • i

•

n the separation of both input

Si can be presented by an ordered triple

where x; is the value (symbol) of the component, x;

- e (symbol) of the output component,

._ l a omponent, which is neither an input nor an output component,

z1

5 ..


b). �

e denote by o - (b) ( O + (b)) a vector set adjacent to the vector b such that c < b � >

b)

if

c E o - (b) (c

i d the cardinality

E

O + (b)). It is obvious that the cardinality of o - (b) of 0 + (b) equals n - k, where n is the dimension of the

i nd k is the number of uninverted variables in it.

equals vector

ition 3.4 A vector comparable with all vectors from some set is called a er.

_\ !pacer is usually a vector

i ( e)

including only zeroes

inition 3.5 A function f(z1, .

. . , Zn ) is called

(ones ) .

-

1.

44

-

isotonous {antitonous) on a variable z; ,

I) � f(z;

=

if f( z;

1)

=

O)};

2. isotonous (antitonousJ,

j � n;

9. monotonous,

>

/ ( z;

=

0) f ( z;

if it is isotonous (antitonous) on all variables

z; , 1

=

�

if it is either isotonous or antitonous on every variable;

b, if it is isotonous (antitonous) on all variables included in the transition variation term ( a, b) .

4. isotonous (antitonousJ on a transition a -

e

At the same time it should be pointed out that if a function on a variable z; , it can be represented in the form

f(z 1 , . . . , zn ) where

f (z;

=


x. This means that instead of x vectors with the weight u - p s code vectors we can use a greater number x• of vectors with the weight u - p+ 1 . Since instead of x vectors with the weight u - p s code vectors we can use x• vectors with the weight u - p + 1 and instead of them x0 > x• vectors with the weight u - p + 2 etc. Thus it is obvious that a maximal number of code vectors can Taking into account that

be achieved if their weight is

then o r allowed values

[m/2].

Let us use s code vectors : vectors with the weight

]m/2[+p, 0 � p �]n/2[.

v + p adjacent vectors with the weight v + p + 1. x vectors with the weight v + p have :(v + p) connections with vectors with the weight v - p + 1. On the other hand, y vectors with the weight v + p - l. have y( u - p + 1) connections with vectors with the weight v + p. Thus, x vectors with the weight v + p .re connected with not less than x• vectors with the weight v + p - 1 and x* is defined from the relation Every one of these vectors hs

from which

Since

v

�

u we

J+p u - p+ l

x" = x -have x* > x for allowed values of p.

- 55 -

It follows from the last inequality that the number of code vectors will be maximal, if they all have the weight

Jm/2[.

Because or an even

[m/2] = m/2, then or this cse the minima.I vector is = m/2.

m ]m/2[=

a balanced coding with

k

For an odd

m,

unbalanced coding takes place also in the cse, when vectors

with the weights u and v are used jointly. However, it ollows from the calcu­

lation of the number of connections between vectors that instead of x vectors

with the weight v, then a balanced coding is at least not worse than the cse of unbalanced coding by vectors with the weights u and v . The theorem is proved.

Theorem 3.4 A balanced code {including OBC) is a self-synchronizing code if ev­

ery transition is regular. The correctness of the theorem ollows rom the uncomparability of any couple of working vectors of a balanced code.

3. 7

On the Redundancy of Codes

We shall compare redndancies of a double-rail code (PC), a Cl and an OBC

or

a

case, when the inormation interchange system s arranged to transmit any

positional binary code of length

n.

For this we consider self-synchronizing codes of

lengths t (for PC), q (for Cl) and r (for OBC). It is known that the redundancy of a code system is expressed by the equation

where No is the number of vectors used in the coding system and N is the number of possible vectors. For PC

t = 2n,

Values of t and From

Rpc

for

2

�

n

� 1 6 are given in columns

2

and

3

in Table

3.6.

(6) follows that the length r, when an OBC is used, for a fixed n should satisfy

the inequality

or

2n - n =0 5 -2-n,

(r-1)/2 < zn < cr/2 cr- 1 r r < log 2 cr /2 (r - l) /2 < n log cr-1 2

(7)

- 56 n

t

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

2

Rpc

3

4

6 8 10 12 14 16 18 20 22 24 26 28 30 32

0,5

cr

q

4

4

5 7 8 9 10 12 13 14 15 16 17 18 19 21

5 0,500 0,400 0,429 0,375 0,333 0,300 0,333 0,308 0,286 0,267 0,250 0,235 0,222 0,211 0,238

r 6 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19

o

Be

7 0,50 0,40 0,333 0,286 0,250 0,300 0,273 0,250 0,231 0,214 0,200 0,188 0,176 0,167 0,158

Table 3.6 For 2 S n S 16 values of r, satisfying the inequality (7), are given in column 6 Table 3.6.

n

It is obvious that or OBC o

nc = l -

log2 2" log2 2"

r

n

= -

(8)

r

The corresponding values of o Bc are given in column 7 in Table 3.6. In calculations or the great values of n we can use the Stirling ormula r! ; r"+o,5 e-r, rom which ct�1 )'2 � 2r ;J2 x (r - 1), c;12 = 2r+I 1�

=

(9)

From (8) taking into account (7) we get log2 V21r(r - 1) --� -< -

r

-

o

BC


n I

- 66Even if functions of elements are not self-dependent the situation when the availar circuit bsis does not include corresponding elements can be encountered in solving the synthesis problem. Then it is necessary to represent such an element by a corresponding subcircuit of bsic elements. This leads to a circuit, which contais more elements than the initial circuit and subsequently to another Muller diagram In order to obtain a correct solution of the synthesis problem, it is necessary ths the initial diagram is a projection of the new diagram on a set of variables of te initial diagram and that the derived circuit models the initial one. Thus, we shl understand the synthesis problem s a search or a semimodular modelling circuit constructed rom bsic elements. This method of solving the synthesis problem s used in all circuit speciication languages considered below. 4.2

Synthesis of Circuits from Muller Diagrams

synthesis procedure is essentially connected with the chosen bsis. The mt widely used bases are those containing elements NAND, NOR and AND-OR-NOT In these bses we shall search a synthesis procedure, ignoring in the beginning the fact that circuit elements have restrictions on the number on inputs (fan-in) and on the maximal load (fan-out) . The

We suppose that a circuit s deined by a seminodular Muller diagram, and that we can construct the function p;(Z) in accordance with the ormula ( 16) . If every function p;(Z) includes each variable Zi either straightly or with inversion, then the problem is already solved or the basis AND-OR-NOT. Thus, to the Muller diagram Fig. 4.1,a corresponds to the equations in ( 15 ) and the equation system

( 17) Z4, Z1Z2 V Z1Z3 V Z2Z3

Z3 Z4

corresponds to one of the modelling circuits with the diagram in Fig. 4.5. The satisfaction of the condition that the variable should be included only straightly or with inversion, is generally a rather rare situation. For instance, the equation system

(18) Z3 z4

Z1Z2 , z1z2

- 67 -

101*1f1 1 0*0 0 1 1

*1

Z1Z2Z3Z4 .

1 1

...

0 1

O*O 1�0*1* t

1

1

1

1

. ..·0·

•

11 *

---

1

0 O*O

1 u

_•1

0

J

/

1 U*1 *O 0

1*

11 t1•u � tc t 1 1 i� � O*O �

/ � ·�· 1*1 t �1 r �� 1*1 Q•Jl1 1 ,•u

t

1 0 1 *0

1 O*

�

1*1 1 U 1

0 1 1

�

* 11 t 1 1t 0*0 1 t1 1

0 1

1

O 0 1 0 0

0

1

0

Fig.

4. 6

l�

-

l

•J

G. .)

J •

B. J Fig.

4.1

U*0*1 0

U*

1 1*1

(b)

O

710t

---

�

(a)

O 1

o•u

--�

- 68 corresponds to the diagram in Fig. 4.6,a.

Although the functions Pi, are monotonous on z 1 and z2, these variables are still included in these functions both with and without inversion. This phenomenon cannot be remedied by inverting the function. The modelling circuit is in this ce constructed simply by introducing two additional inverters:

Z

i5,

z3aV zsz.zs,

1

Z2

Z3

ZtZ61

Z4

Z5

Z 1 Z 2, =

Z6

(19)

Z6 V z 1z4,

Z2

The diagram in Fig. 4.6,a is a projection of the diagram in Fig. 4.6,b on the variable set {z 1, z 2 , z3, z4}. The possibilities or such a simple transormation to a modelling circuit are, however, rather restricted. Even or such a simple diagram s the diagram in Fig. 4.3,a we have:

(20)

and the construction of the modelling circuit essentially requires the use of a more complicated procedure. Since here we are not interested in skillful tricky methods but rather in a standard synthesis procedure, we should search or universal approaches. It is necessary o notice that only skillful methods sometimes lead to excellent solutions. However, where can you ind or every circuit . T.A. Edison or a Robert Wood? We pay attention to the ollowing fact. Let the function p; (Z) be self-dependent. Then or a semimodular (autonomous) Muller diagram p;(Z) is either isotonic on Zj, I.e.

Zj

or if p;(Z) is antitonic

=

on

p;(Z )

=

d;(Z\z;) v zn;( Z\z;)

z;. Then only

(21)

- 69 -

(22) may take place. Suppose the opposite, i.e. that

Zj = P;(Z) The graph of changes of values Fig. 4.7. Values of

=

z;

z;aj(Z\zi) V z;Ji(Z\z;) in dependence on values

(23)

a;

From Fig. 4.7 follows that when a; = 1 and 3;

z;

should either change cyclically (this means that

=

and

z;

J;

z;.

is given in

O, then

z;

=

does not depend

on other variables and on the other hand, the function of the rest of the circuit does not depend on

z;)

or there are violations of the semimodularity of the circuit.

Therefore, besides the case (22), for the speed independence of the circuit it is

necessary and suicient that 3; �

B;(Z\z;)

a;, i.e. =

a;(Z\z;) V 1;(Z\z;)

It is necessary to have elements representing a variable

its inversion

(24)

z;, since our purpose is to study possibilities or constructing modelling z; and elements representing

circuits on AND-OR-NOT elements. In the simplest case the variable z; can be

realized by an inverter but, as it was said above, this does not always guarantee

(z;, z1)

semimodularity. If the variable

z;

changes its value, then the transitions of the pair

may be represented by the our diferent diagrams given in Fig. 4.8, a-d to

which corresponds the circuits given in Fig. 4.9,a-d. In the last igure

a;(Z\z;) , 6;(Z\z;) 1;(Z\z;) {z, z1)

(25)

(z, z;)

The upper index in P; means the corresponding transition (10 or 0-1). The no­ tation

is used or a par.phased variable with transit (0,0) and

with

transit (1,1). The functioning of the circuit in Fig. 4.9,d is described by the equations

z;

z; V .1.10 'j , �

Zj V /JJ1

(26)

- 70 -

'

Z· -J Z· J

1 0

Z· -] Z· J

1 0

•

l

0 1

1 1

0 1

0 1

1 1

0 1

a]

Z· -J z. J

0

1 1

-) Z·

1 0

0 0

Z· J

1

I

Fi;.

z.J

z. J

Z· J

-01

( b}

'j

1

]

0

z·J

(cl

(a)

(b}

0

4. 8

&

(a)

] a]

0 0

-10 p. J

(c)

(d)

zJ·

'

z·J

- 71 Let

the equation system z; = a;(Z\z;) Y zn;(Z\z;), j 1, . . . , n, in which every variable z; is realized by a Hip-lop of the type (26) with the triggering functions (25), correspond to some semimodular transition diagram. Then we can assert that the diagram of the new circuit is semimodular, and that its projection on the set of variables is the initial diagram. Omitting the proof of this act, we consider the idea of such a proof. We notice that the lip-flop (z;, z;) hs a transit state (0,0). 0 Let the unction PJ contain the conjunction K = z�;1 . . . z;�" and let the condition for the start of a transition process having form (1,0) - (0,0) - (1,0) be K = 1. This condition may occur only after the termination of transition processes in the lip-lops ( zil, zil), ... , (Ziki ;:) of the circuit. The resul t of the state chnge of the Hi-lop (z;, z;) is also received by the rest of the circuit only after the termination of the transition process in it. This fact allows us to prove strictly that if the initial diagram is semimodular then the diagram of the modelling circuit is also semimodular. n immediate substitution of z; into the expression or z; rom (26) gives =

z;

z; Y JJl Y J}o z;JJO y JJlJJO z;(:; Y 1;) V a;(a; V 1;) :;

V z;f;,

which proves that the initial diagram is a projection of the diagram of the modelling circuit on the variable set Z. It can be concluded rom the considerations of duality that the modelling circuit can be built using lip-lops (z;, !;) with transit states (1,1):

z;

z;

z ·;Ol ' J

=

z;;lO

The introduced method or constructing circuits will be called a per/ect

(27)

realization.

It is not diicult to see that lip-lop with functions (26) and (27) are implemented by AND-OR-NOT elements. However, the complexity of these elements is not restricted. We notice that special measures are taken for excluding logical races in such an implementation. Consider an example. Let a circuit be deined by the diagram given in Fig. 4.10, to which corresponds the equation system

- 72 z2 Z3 Z4

=

-

z3z• Y z3z4 v z2(z1zs V z1 zs), Z2Z4 Y Z3Z2, Z2Z3 V Z4Z2.

The equation system of the modelling circuit hs the form

Z1 z2 zs Z4 i1 z2 zs z.

=

=

z1 v z2z• v z2zs v zsz•, z2 V Z1Z3Z4 V z1 zsz4, Z3 V Z2Z41 z4 v i2is, z1 y Z2Z4 v z2zs v Z3Z4, Z2 v Z3Z4 v Z3Z4, Z3 V Z2Z41 Z4 V Z2Z3

for this cse. We pay attention to the implementation of z1 and z1 . Minimal fors for 1�1 and ll0 are Jl0 = z2z4 V z2zs and >�1 = z2z4 V z2zs. However, in the transition 1*O*11 - a* 11*1 the lip-flop {z2, z2) will switch through the transit stae z2 = z2 = O, in which the excitation of the elements z1 is removed, i.e. this element may e.use races. A similar situation occurs in the element z1 in the transition 0*0*00 - 0* 100. A standard method bsed on the change of the minimal form by a reduced orm can here be used in order to exclude races. When flip-flop switch through the transit state (1,1), then the mentioned collisions do not occur. The minimal orm can be used when circuits are implemented using elements of the type OR-AND-NOT. The minimal form is then suicient for the transit (0,0}, but the transit (1,1) requires the use of a reduced orm. A perect implementation allows us to construct in the basis AND-OR-NOT . circuit modelling any semimodular diagram in such a way that the number of variables will increse no more than twice. As any universal approach, a perfect implementation, which is good enough or all cases, often increse the circuit complexity. Besids that, the possibilities of such an approach are restricted by the real characteristics of circuit bses. For the basis NAND, the bsis NOR and the bsis AND-OR­ NOT ranks of conjunctions and disjunctions are restricted (usually they do not exceed eight). Furthermore, elements have a limited fan-out. Principally, (8-AND)­ (8-0R)-NOT elements allows us to construct most circuits met in practice. For more complex circuits, it is quite diicult even to use the Muller diagram, which is the indispensable instrument. Anyway, not all elements have even such functional

- 73 -

"ig.

4.10

---, z 3

, -�----- - - - - -- - -,

I I

I

I I I

K2

I I

&

I I K3 I I

&

_

z,

Fig. i. 11

I I

J

- 74 possibilities. Furthermore, it is necessary to take into account the accepted ths on the character of delays in elements and conducting wires. We explain this ida by an example.

The operation of the circuit in Fig. 4.11 is described by the equation system (15) . f the subcircuit encircled in this igure by a dashed line is considered s an entity, tbs everything is correct. However, if a full diagram is drawn, in which the variabls K1, K2 and Ks .re taken into account, then the picture will change substantially.

Fig. 4.12 a fragment of a diagram is presented, rom which, first of all, the possible trajectories or incorrect operation can be seen. Moreover, it is obvios that, if after a transition 1-0 of the element K3 the elements Ki and K2 swith faster than anyone of the elements z2 or z3, then there will be no violation of the operation. In

However, the reader can be convinced of the fact that the circuit in Fig. 4.13 models the diagram in Fig. 4.1,a,b independently of the delays in its elements. What was said justifies the search for a minimal circuit bsis for . clss of speed independent circuits and or corresponding synthesis methods, which have not only been applied but are also of theoretical interest. Our next problem will thus consist of the examination of possibilities to synthetize circuits from restricted bses.

n the beginning we treated the problem of reducing the number of conjunctions n functions defining a perfect realization.

Take the diagram given n Fig. 4.14,a. The equation system Z3Z4 v Z2Z3 v z1z2, Z3Z4 V Z1i4 V Z1 Z2Z31 z2i4 V z2zs V z1z2z4, i3Z4 V z1 z4 V z2zs

z1 Z2 zs z4

corresponds to it, and the following triggering functions of the flip-flops perect implementation:

p�o Jio J�o Jlo

p�l p�l

Z2Z3Z4, Z1 Z2Z4 v Z1Z3Z4, z2z4 v z1z2, z1i2z3, =

Z3Z4 V z2zs V z2Z4, z1Z3 V z3Z4,

m

the

(28)

.

,.,

1

I \

} �;

,

1*1*1*1*0

+

� 1 1 0

1

1

1

1*1*1*0 0

0*1 1

1

fig.

I I\ 4.12

1

0 0 O*O*

I I\

1

I� *

1 0 1*0*0 O*

,

...J

1*1 1*0*

:;'�L r I\ ( ,•,;,

1 1*1*0 1*0

0

---

/+�

1

0*1

+

�0 /

1 1

01 ' 111*

�

�

1

1*1 O*

0•1

1*0

u 1

0 0*0*1

z�z223k1 k.k3

I

� 11

- 76-

Fig.

4.13

- 77 -

We pay attention to the fact that the variables z2 and zs change their values in the diagram 4 times during a cycle. For this reson their triggering functions should contain no more than two terms. At the same time the variable z1 changes its value two times during a cycle, and J� 1 contains three terms. The presence of a redundant term z2z4 is explained by the necessity to keep the excitation of the variable z1 in the chain of transition o•o•oo - 0*10*0 - 0•110• - 0*111. We shall say that the corresponding term executes an intercept of the conjunctions (or simply an intercept) . The phenomenon of intercept is esily eliminated by introducing an additional variable s it is done in the diagram in Fig. 4.14,b. Then p�o Z3i4, 181 = z2z3z4, z1 = o, /�1 ::: zo, pf0 = zo and it is necessary to maintain zs = 0 in the state 1*0100 until the switching of the variable zo is inished, i.e. !R1 = zoz2Z4 V .z2z4. All other functions have their representations from (28). In a similar way ll intercepts can be removed. After the elimination of all intercepts rom a Muller diagram of every variable whose value changes exactly twice during a cycle, a perect implementation corresponds to a li-lop with triggering functions consisting of exactly one term (further on we shall call such functions monoterma�. =

Consider a method or constructing a circuit of lip-lops with monotermal triggering functions when the Muller diagram contains variables, which change their values more th.n twice during a cycle. At irst we construct a semicumulative diagram from the given Muller diagram. For instance, or the diagram in Fig. 4.14,b we get the diagram given in Fig. 4.15. We introduce new Boolean variables for the designation of multiple-variables in the semicumulative diagram: 7

Z· 1 _

{

1 0

(29)

Zj = 7

z·1 .. r u'

where 7 is an integer representing the value of a multiple-valued variable. Then the values of variables z; of the semicumulative diagram are represented by a set of values of the binary variables zj in the orm of a unitary code (containing one 1). It follows from this that a variable z; may be realized by a circuit for the controlled shift of one ( token shifter) . The control functions or such a shift have the following form for the considered example

101 0 - zO3> wOl - z3> O 2 IOI z00 z2>1 3 1014 - zl1zl3> _

-

_

_

11001 - z32• 11110 - zlO> 1011 - z0O 112 2 - z1lz4,l 11223 - z3,2 11320 - z1o - zo4 112 O 11330 123 3 - z2• 3 - z2>2 11140 - z33 _

_

_

_

_

_

_

- 78 -

'T� i/i 1

O*O 0

0*1 O*O

t�t t�

1 1

1 1

O*O

1 O*

1 1 *1 1

l

1 0 1 *1

t

1 O*O 1

t

1 *1 0 1

'

0 1*0 1

t

0 0 0*1

t

Ot

0*1 1 1

0 D*l*O --,-. *O 1 C "

0 1

+ ---. •

+ --- + t �t �� O*O 0

1•

1 *O

0 0*1 1

0 1 1

0 0•1

1 O*

0 1 1*1 1

t

•

0 1 0 1*1

O 1 O*O

t

0*1 1

�

1

u 1

1 1*1 0 1

� t

1 0 0 0*1

t

t

1 0 0 1 1*

--- 1 0 0 1*0

(a)

0 0*1 u .

0 1 1 O*O

1 0 1*O 1

O O 1

L0

0*1 1 O*

1*l 0*0 0

(b)

1

v•

�

- 79-

t

..-�1 *0 O * O 0

�

0 0*0*0 0

1*0 1 0 0

0 1 0•0 0

0 0*1 O*U

·� t

0 1

• .-- t

t �t +� t 1 0 *O

0 1 1 1 O*

0

1 1*1

0 1

1

t

2 1 *1

0 1 2*2

'

0*1 3 2

t

1'3 2 1

t

,

0 3*2 1

0 0 2'1

t

t

0 0 3 1. 0 0 J*O Fig. 4.15

fie. 4. 16

0 0 * 1 0*0

0 0*1

1

1

- 80-

These

control functions are monotermal only if the semicumulative diagram is Circuits for a controlled shift of one may be constructed on the bsis o. the basic cell shown in Fig. 4.16. Its function for interaction with its neighbours . described by the following diagram (arcs directed down are omitted): tributivc.

1*

Zj-1 Xj xi 1

0

z; 1

1

0

1

O*

1

1

0

1"

1

1

1

Xj+l

O*

0

1

1

1

1

0

1

1*

1

1

0

1

0

1*

1

o·

1

0

0

1

1

1*

0

0

1

1

0

O*

0

1

1

0

1

O*

_

{

r

request to the j:th cell . rom the (J - l):th

esponse of the (j- l):th cell about the receipt of _ the request signal by the j:th cell removal of the request __ signal from the (j- 1 ) :th cell _ request to the (j + 1) :th cell from the l:st one esponse of.he j:th cell about the receipt of the request signal by the (j + l):th cell

l

r

arguments in favour of using such a particular construction, we introduce a circuit, which models the variable zr This circuit (we shall call it a shift celD contains two lip-lops of the type shown in Fig. 4.16, n element im­ plementing the conjunction p;-l,c, n element with the output zJ , and an element with the output Yj,k· The token shifter constructed of such cells is closed to a loop. Here the loop is formed not only by the lip-lops of the shifter, but also by n even number of Yi,k elements. It is not diicult to see that the loop of Yi.c elements is a bistable circuit. Its switching rom one state to another is executed every time the token (active level) activates next cell of the shifter. It is easy to arrange that the binary variable z; of the initial Muller diagram is modelled by any variable Yj,k with an even index k. Omitting

in

Fig.

4.17

A shifter

cell operates in the following way. Let the vlue 1 be in the second iip­ flop of the (j - 1) :th cell. Then both lip-lops of the j:th cell are in the state 0 k and z;-1 = Yi,k-1 = 1, zj = 0. Then, after the conjunction ;; -l, has become equal to 1, the switching of the irst lip-lop of the j-th cell will occur. Then the switching of the output of the element Yi c from 0 to 1 will occur. This causes a ,

- 81 -

-r

z,

k-1�l

�:·'·� .

.

.

-

----

Fig.

11, 17

• •

&

•

Z 12 rz

Fi;.

L. 18

z 1zZz3z4

. -----. � 0 O*O*O ..

1 1

0*1 O*� ._0.*0*1 0 0*0/'0*1 ��1 0*1 ---�+ 1 � 1 0

1 1 O*

+

1*1 1

t

) 1*1

0 0'1 *1 0 0 f0 1 * I

Fig.

4. 19

0

- 82 transition process of state changes in the loop of Yi,k elements. After this process has terminated, Yi,k-I = 0 sets the second lip-flop of the (j- 1)-th cell to the state 0, after which z;-1 = 0. n the j-th cell a transmission of the value 1 from the irst lip-flop to the second one is executed. Then the first flip-lop is set to the state 0, and the output of the element z1 becomes 1, which indicates that the value 1 is in the j-th cell of the shifter. Next the (j + 1)-th cell will be active, etc. Thus, if the triggering functions allow a monotermal representation, then it is suf­ icient to use NAND elements (or due to duality NOR elements) or the implemen­ tation of the modelling circuit. Now it is natural to treat the problems of the minimal number of inputs to NAND (NOR) elements. It is seen rom Fig. 4.17 that all elements, except the element . . . .i.k-l c , have no more than two mputs. implementmg the term 'j '

This element may, however, be implemented by 2-input NANO elements and in­ verters as shown in Fig. 4.18. Here, for guaranteeing speed independent circuit operation, the problem of the permissible sequence of variables to be included in the term should be solved. Indeed, when zJ -1 = 1, then the variable zl should either hold the value 1 or, f it equals 0 , then it should immediately change its value by executing the transition 0 - 1. Similar requirements .re put on the variable z[i , when z;-1 zf = 1 , etc. It can be rigorously proved that if triggering unctions allow a monotermal representation, then such an ordering exists. The proof is bsed on the fact that during the transition -1 of the variable zJ -1, there should exist in the term ;:-1•1 at least one variable, which is not equal to 1 . In the opposite case, the condition or the transition is already satisied. Because of monotermality, the transition 0 1 of this variable is a single one. Any of the variables satisfying this requirement may be chosen to be the first one. After this, since z;-1 z[l = 1, the condition for transition either is satisfied or there exists in the term p:-l,c a variable , which is not equal to 1 , etc. •

-

Thus, we showed that if the triggering function allows a monotermal representation, then the modelling diagram corresponding to this representation can be represented by a circuit of 2-input NAND elements. Next we consider the problem of the minimal load (an-out) capacity of elements. It can be seen rom Fig. 4.17 that all elements except z� have the load which equal to 2. The problem can be solved trivially by including in the circuit zj a sequence of inverters, the number of which is two times the number of connected inputs. At the same time, the maximal load of one element is reduced to two. Now we should define clss of circuits, to which the nonotermal triggering functions correspond. It was mentioned above that the multitermality of these functions may be caused by the necessity of an intercept and by multiple transitions of variables

- 83 -

during a cycle. However, there exists one more reason for multitermality. This is illustrated by the diagram in Fig. 4.19 corresponding to the equation system

Zz Z4 V Z3Z4, z1 V i,h Z2 V Z4, Z1Z2Z3 V Z(Z3.

Z1 z2 Z3 Zt

Essential in this example is the .et that

P�1

=

z2 z4 V ziz•

constructing the modelling diagram corresponding t o

of the triggering function are unknown.

a

and that the methods for

monotermal representation

Cumulative diagrams constructed from such Muller diagrams orm a semimodular but a non-distributive lattice. The circuits corresponding to them will in brief be called non-distributive. We have not progressed in nding an implementation method for non-distributive circuits using NAND elements, nor have we succeeded in proving that such a method does not exist. However, evidently it does not. On the other hand, it can be proved that the combined use of 2-input NAND and NOR elements allows us to implement also non-distributive circuits. Because of the bulkiness of the proof of this act, we don't introduce it here. We limit ourselves to a simple example. Let be given an equation system corresponding to a non-distributive circuit:

z1 z2

Z4,

z3 Z4

z1 V z2, z1z2zs V Z3Z4

.z.,

The implementation of the corresponding modelling circuit is given in Fig. 4.20. In order to simplify the example we have neglected the fan-out restrictions here. However, already for the equation system

z1 z2 Z3 Z4 Z5

=

z5, z5, Z5 Z1 V Z2 V Z3, Z1Z2Z3Z4 V Z4Z5

- 84 -

Fig.

4.20

- 85 -

the use of a structure analogous to the one given in Fig. 4.20 requires the use of 3-input NOR elements. If only 2-input

NOR

elements are available, then one can

use, for instance, three circuits of the type in Fig. 4.20.

This will transorm the

equation system in the ollowing way: z1

i5,

z2

i5,

Xt

z1

V z2, z1z2x1 V x1x2,

x2

is,

Z3 Z4

X1 V Z3,

X3

Z3Z4X 1

x2 V xs,

X4 Z5

V X3Z4,

=

X2X3X4

V X4Z5.

Though it does not deine any common synthesis method for non-distributive cir­ cuits, this example still demonstrates existing diiculties and some ways to overcome them.

4.3

Synthesis of Circuits using Petri Nets

( Section 2.4) the iring of a transition was consid­ (the meaning of indivisibility is the same as or the

n the deinition of a Petri net

)

ered an indivisible operation

semaphores of E. Dijkstra . In other words, when a transition ires then a token is removed rom the input places of this transition, and strictly simultaneously tokens

are put into output places. n the implementing circuit this requirement can't be

strictly satisied. Thus, for the simplest fragment corresponding to the persistent safe Petri net shown in Fig. 4.21,a, the presence of a token in the input place of a transition enables this transition. After its iring in a real modelling circuit, the transit situation shown n Fig. 4.21,b is irst established after a iring. The token

rom the input place can be removed only after a token hs appeared in the output place. As a result of this, the situation shown in Fig. 4.21,c will arise.

Consider the Petri net fragment shown in Fig. 4.22 and containing two transitions Zj-1, z; and two places Xj, X;+1· In this fragment we will use the following inter­

(

)

pretation of transition of transitions and places. Let every place and transition be

assigned to the change of value of some signal variable of the modelling circuit in the following way:

l. the appearance of transition I

-

a

token in the place x; or Xj+l is associated with the

0 of the signals x; or Xj+i

- 86 -

(b)

--� Fig.

z

j-1

J J

X ·

Fi3.

J- _1_

1*

:

D*

· ·

1

J

.: .

1*

0

0

0

o•

4.21

.J

z .

I

. .

(c)

1

J

z .

1*

0

0

O*

xj + l

� I

1)

2)

4)

5/

6)

0

0

7)

O*

Fig.

xj

H

li .22

3)

1*

)

4 .23

the t.nsi tion

z

j

·

l

fi ri .: of transition

appearance

of a token

z.i J.S

the transition

(t"ansit) token

removal

.,i-l l1

plac"

en.bled

firing of transition

aprearance o: a

enabled

15

toke:

J

z . ln

place

from place x. J

J

x .

J +l

x .

- 87-

2 . the re moval of a token rom the place x; o r X;+l is assoc ia ted with the tran­ s ition 0 - 1 of the s ign al x; or Xj+ii 3. the trans ition z;-1 or z; is enabled if z;-1 = 1• or z; = 1*, respec tively ; 4. the firing o f the poss ib le transition s z;-i o r z; co nsis ts o f the transition 1 - 0 of th e signal z;-1 o r z3. In such a case , tak ing into account the appearance o f the transit s ituation shown in Fig. 4.2 1,b , the ope ration o f the ragment in F ig. 4 .2 2 can be descr ibed by the Muller d iagra m in F ig. 4.23. Cons idering one of the po ss ible de in itions, the equation sys tem x;

z;

V z;-1

(3 0)

is der ived . Now we return to the circu it in F ig. 4 .16, or w hich the correspond ing e qua tion syste m is of the form x· 1

f; z·1

-

x;z;-i.

t;x;+i,

XjZj-1

(3 1)

It is e asy to see that the circuit described by e quations (3 1) models the circui t correspond in g to the equa tions (30). A ttemp ts to use o the r poss ible interp re tations o f trans itions and p laces in the rag­ ment in F ig. 4.22 lead to a less econo mical real iza tion compared to the circuits in Fig. 4.16. Takin g into account the realization in F ig. 4 .16 we can construc t implementations o f typ ical fra gment o f persis tent and sae Pe tri ne ts as is s hown in F ig. 4 .24. The realized parts o f the ragmen ts themselves a re deno ted by dashed boxes in the col umn "F ragment". In case the number of input o r outp ut trans itions of the ragmen ts in Fig. 4.2 4 is gr eater tha n two, the correspond ing generalization is tr iv ial . Thus , when the re a re k inpu t events, then or the ragmen ts 1 and 2 it is re qu ired to use 2- inp ut-AND­ k-ou tpu t-NOR e lements and (k + 1)-input NAND eleme nts in the left arm o f the lip-flop, respectively. When there are k ou tpu t transitions, then for the fragmen ts 3 and 4 it i s requ ired to use 2- input-AND-k-in put-NOR ele ments in the right arm of the fl ip -lop. The elemen t z; requ ires k + 1 inputs in the general case .

- 88 Implementation

Frtgment r

r 1.1 z,-ql , L _ .. __

I

.1-l,\ ·----1 z,'

____

z,-1.?L

I

J

;- --;1D

..t1·

3

z-,� ·: ·� L

____

j

1.1

v .� j • 1.]

.

,

x1.1.1

_ :; _ • 1.l _ _ � _

l •I

r,

:

lz,-l.lL �- � {J.�

_

lI l

- 89 -

Csing the given interpretation it is easy to understand that an arbitrary persis­ :ent and safe Petri net is constructed s a parallel-serial composition of circuits :mplementing the described fragments. The described approach requires in the general case the use of an unrestricted basis of circuit elements. However, because we are interested in the minimal basis of circuits elements, we consider an implementation of Petri net fragments on 2-input \AND elements, for which we refer to Fig. 4.25. We

pay attention to the fact that the method for constructing modelling circuits given in Fig. 4.25 stipulates speciic interpretations of the order of enabling and iring transitions in the corresponding fragments. Thus, after the appearance of tokens in the places x;,i. x;,2, x; ,s of the fragment in Fig. 4.25,a, a token is irst removed from x;,1, then from Xj,2, after which a token appears in the place Xj+i · Finally, the token is removed rom x;,s. In the ragment in Fig. 4.25,c, a token irst appears in the place Zj, l i then in the place x;,2 , after which the token is removed from the place x;- 1 · It is easy to see that the fragment 3(4) in Fig. 4.24 is implemented in the basis 2input NANO by a sequential connection of circuits corresponding to the ragments in Fig. 4.25,b and c (a and c). We notice that such a Petri net interpretation, in which the requirement of indi­ visibility is ignored, is apparently legal only for the class of persistent safe Petri nets.

The fan-out of the elements in the circuit in Fig. 4.25 equals two for ll elements except for x;, 1 in the circuit in Fig. 4.25,c. For reducing the fan-out of this elements to two, one must include two sequentially connected inverters to the circuit denoted by an asterisk. When modelling persistent safe Petri nets, there certain diiculties may arise, which are illustrated by the following example. In Fig. 4.26,a is shown a modelled Petri net. In Fig. 4.26,b is shown a standard implementation on elements of the type shown in Fig. 4.16. In the latter a deadlock state is given, rom which the circuit can't get out. To avoid this phenomenon it is necessary to introduce fictive (dummy) transitions and places in the Petri nets to be implemented in order to prevent cycles of length two containing such "traps" . Circuits modelling Petri nets are in some sense dual to the Petri nets themselves, in which circles and dashes are "interchangeable" with each other. That is why the methods of interpreting transitions and places in nets can be very diferent. This gives a possibility to improve implementations. Thus, by a sequential connection of implementations of the ragments 3 and 1 in Fig. 4.24 one can after considerable

- 90 Fra,.ent

Implementation

{oJ

,;, . 1

0

z. _ ..__

x,.u

lei

Z1·' 11- I

Xi + x,

(d)

Fi g . !1 . 2 5

ZJ,2

1,

1

- 91 -

( �- )

fi : .

(b)

4 . 26


model is an inverter, can be realized by a circuit with a double-rail input - ::\ { see Fig. 4.45 ) . Inormation is also stored in the flip-lop in a double-rail a

cit

_

-� Ji, Yi v

-

• e

)

·

;: ¥;. An

a two-channel double-rail implementation for realizing the transition func­ example of the construction of . circuit implementation the function

a _n

in Fig. 4.46 for 2-input elements. The implementation is combined with :•er level gates of the memory cell. The output values of the elements when ;; = : are shown in the igure. When a new value of the variable z; is produced r � = 0, then only one element output signal changes its value in every stage - � circuit. Thus the value of the output of the circuit changes only after all .�ition processes in the circuit have terminated. This takes place during the 1ons 0 - 1 and 1 - 0 of the signal ai. Thus, the realization is invariant to the _ ! of its elements. I ��r

�

that an increase of the functional possibilities of the elements will decrese ;:h and the complexity of the circuit.

- 110 -

b· J

z ,

Pig.

j

J .45

- 111 -

_ 0

- 112 Because the automaton consists of two memory elements, i.e. of the auxiliary � and the basic M2; , the protocol of the interaction between the automaton n: environment can be deined, or instance, by the Petri net in Fig. 4.47. It hs 9 proposed that the structure of the environment also pressumes the existence :ia two-level memory. The Petri net in Fig. 4.47,a describes the interaction sho.= a Fig. 4.44,a and the net in Fig. 4.47,b describes the interaction shown in Fig. 4.H •

The interaction protocols may be implemented as is shown in Section 4.3. As a conclusion of this section we point out that there are also some other synthm methods. However, the description of these methods would essentially overload a text without giving any principally new knowledge.

- 1 13 -

M 2·

I

J

M2E

O I

(a)

(b)

- 114 5

ANALYSIS OF ASYNCHRONOUS CIRCUITS

The complexity of the control of synchronous processes leads to a necessity �

develop methods to analyse them. Here some issues in the functional analysis .:

asynchronous circuits will be presented. These are hardware implementations oft;�

control of asynchronous processes. However, the methods presented in this chapte:

may easily be utilized also for the analysis of synchronous parallel processes o:. other levels of computer systems.

The dynamic behaviour of a digital circuit consists of ordering of events durin! active periods of elements of the circuit. The element switching times may esse!.­ tially difer from each other, s they depend on the physical characteristics of th

elements, and change with time. n the general cse, an arbitrary number of circui;

elements may be simultaneously active. Thus, the behaviour of a digital circuit e::

be described by asynchronous switching processes.

(

)

All advantages of aperiodic selfsynchronizing circuits are mostly due to their speee independent behaviour; such a circuit works correctly independently of the valus of the switching delays of its elements. Proving the characteristics provided by suc. circuit is a topic of the analysis of this clss of circuits. Thus, the analysis essential!�­ difers from the traditional analysis of synchronous and asynchronous circuits. Design of automata implemented by logical circuits is a common technique in the analysis of such circuits. However, often the analysis of synchronous logical circuits is limited to less common tasks: to detect the existence or the absence of some kinfil of races or hazards in the circuit. It is considered that a circuit without any critic: races should operate correctly. A formal model of an asynchronous logical circuic plays an essential role in such an analysis.

Transition processes in a circuit w:

normally inish within some ixed time interval, which is determined by assuming the delay of any circuit element to be less than some given value. If this conditio: is abandoned and the circuit is required to operate correctly for any finite elemem delays, the traditional analysis methods appear to be ineicient. It is well-known that speed independent circuits are semimodular, distributive, anc

sequential circuits, which operate correctly or arbitrary inite element delays. We

consider that all classes of circuits presented in the following are free from critica:

(

)

races. The following analysis is capable to prove under the most general ssumption.

about the element delays analysis of aperiodic circuits , that a circuit belongs to a

certain clss of circuits. Such a direction of the analysis is justiied, irstly, because

any "correctly operating" circuit must - independently of its semantics - satisfy some limitations, and secondly, a classiication problem is often a necessary stage in the process of structural synthesis, because it might be useful to apply some special synthesis method for each class of circuits.

- 115

�

::?er formal model of an synchronous logical circuit or such analysis is the -:::: proposed by D. Muller (see Chapter 2.4). This model of an synchronous ._circuit is bsed upon the following ssumptions concerning the physical im­ .-•-:;tat ion: the elements of a circuit have inertial delays with finite but arbitrary � element delays and propagation delays up to branching points are consid­ : i be element's output delays, but propagation delays beyond the branching - ! are considered to be very small in comparison to the delays of the elements :3 those branching points are connected s inputs. _

.

::ing to such ssumptions, a circuit element can be considered s a sequential :ion of a delayless logical element i and a inertial delay Di with an arbitrary =te) value (Fig. 5.1).

� -

_.

._

::ea of the assumptions made about the delays is such that if the output of i.ement is connected to the inputs of two other elements, then the behaviour - .!! rignals in these three points (one output point and two input points) is iden­ c ny moment of time. These ssumptions do not put too great limitations on �erality of the models. If there arises the necessity to study transmission de1 :::en special delay elements (replicators) can be introduced into the considered _: A wide clss of electronic circuits in practice satisfy such hypotheses . l

A Model of an Asynchronous Logical Circuit

!: C

is a pair {Z , F) , where Z = {zi, . . . , zi , . . . , z,.J is the set of binary F is a system of boolean equations of the type t = fi(Z),

:.5 in the circuit and _

=

. , n.

�

words, a circuit is an interconnection of logical elements (they correspond nriables of the circuit) . Each input to a logical element is connected to - ::� only one element output. There are no pairs of interconnected element �-. The boolean equations describe the behaviour of the logical elements. We �at for this conception of "circuit" and "Muller model"' (Deinition 2.25) the :.g terms are equivalent: a state of the circuit, excited and stable variables - -.sponding to Definition 2.26. �

I

"• of excitations not acceptable in circuit s, which behave invariantly of

-�.!tively clear that the transition rom an excited state to a stable one through the ��:ions of element delay values, depends on the "speed" of an element z• . �e::nent may either "succeed" in switching or may be ('late" and then the ��n disappears. It is apparent that the behaviour of an element depends on _e of its delay under such circumstances. =er.ting mode of an element depends on the state change behaviour of the

- 1 16 -

Z_ 1

I

-

-

l

-

: .I _

_ _

: I

Zn I L -

-

-

fi

-

- -

zi

-

-

I

-

---·

-

- i

D,

I

!

I I

zi

I

- - _J

�'i ; . 5 . 1

1 *0 * 1 *

1- o � �� � _ ._� _ o

· -

1 •� 0 · 0 0 - 1 0 < 0

1

1 0 * -- 1 * i

� 0* 1 *0*� 'ig '

5 .2

1�i 1*1

- 117 :.iied circuit. Along with the conceptions "immediately follows" , "immediately hable" , and "immediately precedes" (Section 2.4) we will use the following one: .:� : state 3 ollows the state : (: -+ J) , if 3i ::: i or every variable Zi which is .>le in the state a. The relation "-+" s relexive, which means that : - a. f .:e : states : and 3 are related to each ot.hers by a -+ 3 and if they difer from h others through only one variable Zi ( a and J are neighbours on Zi) , then J :mediately follows after a through neighbourhood (: � 3 or : + 3).

A::aching . successor relation to each pair of states in a circuit makes it possible to :istruct a transition diagram of the circuit. n Fig. 5.2 is presented a simple circuit ::d its transition diagram. The transition diagram is not deterministic. However, :::obabilities are not ssigned to transitions in the theory of speed independent �cuits. Thus, objects of investigation are circuits, which have a desirable behaviour .=r any posible transitions.

The operation of a circuit consists of transitions from some state to some successor state by changing values of excited variables. States followed by no other states (all ,·ariables are stable in such a state) will be called dead states (or deadlocks).

The state 3 is reachable rom state : ( a > P), if there s a transitive chain of relations "-" between this state pair. (The state 3 is reachable rom the state : , f there is . path rom : to 3 in the transition diagram) . Analogously is defined reachability through neighbourhood: : ! J. The concept of reachability is generalized for the set of states in a circuit. Let A be some set of states of a circuit. The state set 8 of the circuit is immediately preceding the set A , if for each 3 E 8 is found a E A such that 3 - :, and if or an arbitrary a E A is ound 3 such that 3 - a then 3 E 8 . The immediate successor of the state set A of the circuit is deined analogously. 5.2

Reachability Analysis

There are two kinds of reachability; forward and backward reachability. Forward reachability means that for a given state set A of a circuit a new set of all such states 3 or which an :: E A is found satisfying : > J is defined. Backward reachability problem consists in the searching of all states 3 for which there is :: E A and 3 > ::. It is possible to suggest an iterative algorithm for the reachability analysis. At every step of this algorithm we determine the immediate successors (forward reachability) or immediate predecessors (backward reachability) of a state set, which has been formed during the preceeding iteration step. At the first iteration step the immedi­ ate successors or predecessors of the initial set of states is deined. The reachability

- 118 analysis process stops, when no new state would be ound at the next iteration step. Thus, the reachability analysis consists of repeating the search for immediate predecessors or successors of a given set of circuit states. A reachability analysiB problem can in principle be immediately solved by use of a transition diagram. Being a tool or describing the operation of real circuits a transition diagram, however, requires too much space to be efective for this purpose. For this reson there is a need or development of analysis methods utilizing more compact circuit representations - the Muller model. Let us assign the Boolean functions pA (Z) to the state set I of a circuit, which means that A = {!l P A (a) = 1}. Let us introduce two operators, Pc and Qc , which or an arbitrary set of circuit states define the immediate predecessors 8 and the immediate successors ) . Thus Pc (PA(Z)) = ps (Z) and Qc( P A (Z)) = pp (Z). For the particular cse - "neighbourhood" - the corresponding operators will be denoted by Pc1 and Q!, respectively. Let the circuit state set A be assigned with the Boolean functions P A (Z) in a normal orm, which means ormuls in the bsis AND, OR and NOT. In this form only variables can be negated. Pc is obtained fro m pA(Z) by substituting for each appearance of Zi (z.} (i = 1 , . . . , n). Statement 5.1

z,

V

i(Z) (z, V f;(Z))

Proof. The proof is limited to motivate the idea of the statement. The state set or which the value of the variable ; is "1" (; = 1) is denoted by I' � A . What conditions must be satisfied by z in states belonging to the immediate predecessors of A'? It is obvious that one of two conditions must be satisfied: either Zi = 1, i.e. the value of Zi doesn't change in the transition to a state in A', or f, (Z) = 1, i.e. if z, = 0 then the variable z. is excited and a change of the value of z, takes place in the transition to a state in A'. The cse ; = 0 is analogously handled. Let P A(Z) be given in an arbitrary form. The following corollaries of Statement 5.1 can be derived: Corollary 5.1

Pc1 (pA(Z))

= PA (Z )

Corollary 5.2

Pc1 (pA( Z)) n

=

P A (Z ) V

V

V

V

lSiSn

1 $iS n

PA (zi, . . . , Zi- 1 , h(Z), Z.+ 1 , . . . , Zn)

PA (zb . . . , i - 1 , t, Zi+li . . . , zn) (zs i fi (Z) )

the latter ormula, Zi B f; (Z) are the excitation condiLions of the variable s , PA ( zi, . . . , i- r , z;, i + i , . . . , zn ) gives the set of states difering rom states in I

- 1 19 ::- by the value of the variable z,, and oA {z1, . . . , Zi-lZi, Zt+1, . . . , zn)(z1 ll t(Z)) those states of this set or which the variable Zi is excited and, consequently, �:iwhich states in A are immediately reachable through neighbourhood. ps

�= Boolean functions in any sum-of-products normal orm be assigned to the circuit set A .

ee

. �·

The operator Qc is obtained from oA(Z) by substituting tV z;s (Z) � t (Z)) for each appearance of , (z,}. Hereby the following rules are applied transforming the formula with the marked variable z� :

utement 5.2 .

•

f.

if ; is an elementary product term in the sum-of-products normal form, and does not contain t and z: {1 � i ; n) simultaneously, then z� is changed to

i;

otherwise, the following rules are applied: ·

-

Zi, Zi z; V Zi z_,t. z�t z; · ii

z: Zi Z-iI V Zi z,I

o, 1,

•

, Zi

;Vt

z

z� v z;

z, , ,

ii.

Poof. Let the state 3 be immediately reachable from some : E A and let 3 difer �m : through the values of the variables z, 1 , , z;: . The state : gives one of :e terms of the unction pA ( Z) : zf 1 z�" . Performing the substitution and the ..sformation pointed out by the conditions of the statements will give as result 1 >ecially the term z,�1;1 z,�;1. zt� •n included in the state 3. On the other I. z,�'1+ .+1 _i; _i;. i;t+i a;. 1 1s inc lu ded in some state 3 , then 10r ld , l'f t he term z,. r all 1 . . . z,. k z,. :+ 1 . . . z,. ., ( l S e S k) a,, . f10 ( a) . Thus a + 3 or some a E A . • • •

•

•

•

•

•

•

•

•

•

n

·

·

·

n

A

simple solution method or forward reachability through neighbourhood cannot derived from Statement 5.2. Such methods can be derived with the aid of a circuit ::ansormation. A transormation of a circuit C is a circuit c• corresponding to the system of the Boolean equations Zi = Jt(Z) = i (z,, . . . , Zi - t , Zi, Zi +i , . . . , zn) , i = : . . . . , n. e

: the circuit C a � 3 then and only then when 3 � We point out that (C * ) * = C .

With the aid of the Corollaries 5.1 and be derived:

:n

5.2

a

in its transormation C* .

of statements the following corollaries

- 120 Corollary 5.3

Q�(pA(Z)) PA(Z) v v PA(z1, . . . , Zi- } , r(z), Z1+ 1 1 . . . , Zn)· =

l �i�n

Corollary 5.4

Q b (pA(Z)) PA (Z) V V PA(zi , . . . , ;, . . . , Zn) (zi B Jt(Z)) . =

5.3

1$i�n

Reduction o f the Reachability Problem to t h e Problem of Reachability through Neighbourhood

It is useul to replace . gener.I rech.bility problem with the special cse concerning reachability through neighbourhood 1 because of the computational simplicity of the operators P: and Qb. The conditions under which solutions of the general and the special cases coincide are first considered. We say that the state a is conlicting in terms of the variable Zi , if we can ind a state 3 ollowing : ( : + 3) is such that :i = 3i = i (3) - /i (:) (this means that the variable Zi is excited in the state : and stable in the state 3) . If 3 is such that : + 3 then : is !-conlicting (fact mentioned corresponds to Definition 2.21). For examp le , in the transition diagram in Fig. 5.3 , the state

It should be pointed out that a conflicting state may or may not be 1-confiicting. 1 1 1 is conflicting but not !-conflicting and the states 0 1 1 and 101 are only 1-confiicting. If all successors of a state : are non-conlicting, then the state set reachable from : is identical to the state set reachable from a through neighbourhood.

Theorem 5.1

Proof. Let for some 3 be : > 3 but not a . 3. The shortest possible sequence a0 > :1 > . . . > ak ---. :k+ l , where :0 = : and :k+l = 3, is changed by replacing . . 1 1 1 1 1 . 1 the pairs a' + :1· + 1 by sequences like :1 + 3 + + 3r + :•+ wherever this is possible. As a result, the maximal neighbourhood sequence 3°3 1 pmpm+l , where 3° = : and 3m+l = 3 , is received. Assume that some 3' is found or which pi . pi+ l is false. Let there be a I E (P , p + i ) which is a neighbour of p+l . Then 31 + I but I + 3i+l is false, because the constructed sequence would not be a •

•

•

•

1

The description of reachability algorithms is a little simpliied by

case to a special cse

(reachability

a

.

•

transition from the general

through neighbourhood). The evaluation of the computational

complexity of reachability algorithms, the general reachability problem, and the special cases is

outside the scope of this work .

We still point out that in many cases algorithms for solving

problems of reachability through neighbourhood are more eicient th.n algorithms for solving general reachability problems.

- 121 -

Fig.

0

5.3

;·:·\

1 *1

I

\ � 0

0

f

1 *0

1*

O*O*O

, /: I 1

Fi,.

+ 1

5-�

0

I

1

>' °

- 122 -

maximal neighbourhood sequence as conditions of the theorem.

{

� 31+ 1 . This is in contradiction with

...

In the transition diagram in Fig. 5.4 the state OOO is conflicting. Therefore, t.� state set reachable rom the state 111 doesn't coincide with the state set reachab:e from OOO through neighbourhood. The state 110 doesn't belong to the latter set. If all predecessors of the state a are non-conlicting, then the set of predecessors of a coincides with the set of predecessors of a through neighbourhood. Corolly 5.5

The problem of forward reachability can be reduced to the problem of forward reachability through neighbourhood with the aid of the following circuit transfor­ mation. The shift of the circuit G with respect to the state set A will be a circuit G defind by the system of Boolean equations: Zi = J,A (Z) = Zi ( fp (Z ) v Qb(PA (Z) . IP(Z))) v Zi (l(Z) v Qb(pA (Z) ' f{ (Z))) ,

where IP = i (zi = 0) and fl = J, ( zi = 1) are received by splitting the right sids of the Boolean equation system F representing the circuit G by /1 ( Z) = i i ( Zi = o) v zd1 (z1 = 1 ) , 1 ; i ; n (Shannon's formula). The idea of the described transformation is that all initial circuit states, which are !­ conflicting and belong to the set A , are free rom 1-conflicts in the new circuit. This happens through the spreading of variable excitations to states ollowing initially excited states. This "opens access" through neighbourhood to states, which earlier were not reachable through neighbourhood in the initial circuit. The basic properties of circuits created by the described transormation are ormu­ lated in the following theorem. Theorem 5 . 2

For the shift cA of the circuit C following statements hold:

1. if ti . i(a) then

.,

. f/ (a);

2. all states in the set A are not 1-conlicting in the circuit oA;

9. if . (9) . J/, then there exists a state

a E A, for which a + 3 takes place in the initial circuit G, and which is 1-conticting with respect to the variable Zi (this means that the transformation cA contains new variable excitations in comparison to the initial circuit C because of only point 2 of this theorem).

- 123 ?roof. Point 1 is proved by immediate substitution. Let a E A be I-conflicting with respect to variable j , which means that there exists a J or which a � J and l; = 3i = i (J) = i(a). It is ssumed that :i = 0. Then the state : belongs to :he set deined by the Boolean unctions �A (Z)t(z, = 0) and 3 to the set deined 1 . The case ; = 1 is ly Qh(PA( Z)i(z: = 0)) . Because of this, 3: : ' (3) analogically handled, which completes the proof of point 2. Point 3 holds, because tie unctions t(Z) and fiA are non-equivalent only in states :, or which f3-states n a 1-conOict exist such that J .. : is also true. =

ll excitations

present n the initial circuit are thus preserved in the circuit cA , and excitations new compared to the initial circuit C depend only on point 2 of the described theorem. From Theorem 5.2 immediately ollows that if in the circuit C, B is the set of 1-conflicting states of the set A (B � A), then cA = c8 .

Let 8 be the set of states of tke circuit C that are reachable from states of the set A . Then the state set of the shift 08 of the circuit C reachable through neighbourhood with respect to the state set A coincides with the set B . Theorem 5.3

A lemma is formulated for the proof of Theorem 5.3.

For each state a which is 1-conlicting with respect to j there exists state 3 which is 1-coniicting with respect to the variable j , such that a - 3 and a . 3.

Lema 5.1 a

Proof of Lemma 5.1. Let : be conflicting with respect to variable z; and { a1 , . . . , an be the set of all states for which a - .i and ri = o4 = t(ai) = a(:). Let in this cse ci difer rom a through the values of k; variables. K = min1 $j$e k; is the conflict range of the state : with respect to the variable Zi. The correctness of the lemma is evident or K = 1. Let the lemma be ssumed to be correct for K = m. The cse K = m + 1 is considered, which means that for some j, a difers from ai through the values of m + 1 variables. Let the state I be a neighbour of . . . 1 :' , which means that 1 E (:, :'). Then a - f and I - a', because otherwise the conflict range of the state a would be less than m + 1 . Consequently, the state 1 is 1-conlicting with respect to the variable Zi and satisies the irst condition of the lemma. Also the second condition is satisied: a ..1 as in the opposite case there exists a state 8 E (a, 1) for which a - 8 and :i = 8, = t(E) : a(:) , and then the conlict range of the state a with respect to the variable z1 is less than m + 1 . Proof of Theorem 5.3. Let :1 E A and .N E B . It will be shown that a1 . .N in the circuit cB . If : 1 > a2 > . . . aN is a maximal neighbourhood sequence in the circuit C and if for some ai .i :.aH1 is false in the circuit C , then the state a/ is

- 124 1-confiicting because of Theorem 5.1 and Lemma 5.1. According to Theorem 5.2, the state ti is not 1-confiicting in the circuit C8 , and this means that ti � ai +I in the circuit C8 . Let a 1 E A and a1 � aN in the circuit cB . It will be shown that tN E B . f a1a2 . . . aN is a state sequence or which aK \ aK+ I , 1 � K � N, and if the state ai, 1 � j S N, is the last state or which i � ai +l does not occur in the circuit C, then because of Theorem 5.2 the state f E B , which is 1-conflicting with respect to variable Ze, is ound in the circuit C, and for this state f t i in the circuit C. Since the state ai+ l difers from the state 7 through the values of the variables Ze and Zm , and both these variables of the circuit C are excited in the state 7, I + ai +l is consequently true. Thus t;+ l E B and since ai+l � aN in the circuit C then also aN E 8 . The last theorem shows that it is in principle possible to reduce problems of or­ ward reachability to the problem of orward reachability through neighbourhood. However, these problems will be solved stepwise, s the state set, to which it is nec­ essary to bring the initial circuit, is a priori unknown (this set is a goal or orward reachability problems) . n

the first step the state set ) is defined which in the initial circuit C is reachable through neighbourhood rom states of a given set A . Then the shift cP of the circuit c is constructed and the state set e is deined by the reachability through neighbourhood rom the given set in the circuit cD . If e = ) ' then ) is the desired state set. Otherwise the procedure is repeated with c0 s an original circuit. Example 5.1

system

The circuit in Fig. 5. 5 is given for the variable set {a, b, c} by the a b c

(b v e)a v be (a v e) b v ac (a V b) c V ab

of Boolean equations. The corresponding transition diagram is presented in Fig. 5. 6. Let the initial state set be given by the Boolean function abc. The following Boolean functions are deined in the iterative solution process of the backward reachability problem (reachability through neighbourhood is given in parentheses):

P(abc) P(ab) P(ab V abc) P(ab v ab)

=

ab, (P1(abc) ab v abc, (P1(ab) ab v ab, ab v ab.

For the forward reachability problem are deined

Q(abc)

=

c,

=

ab), ab),

- 125 -

c

F.l g .

5.5

100 0 1 C*0�1 1 0*+1*�� 0 0 1*1 /

0 1 0 --Fi g .

/

1

1

0

1

).6

a

c b

Fig.

1

/

lo* o * o

O*O

�

0*1 0

'

5.7

- 1

__ _ _ _ _

1

/·

0

1

/

1

01

o* - 1 *1 *1 - o

Fi,. 5 . 8

1

\

o

'']

- 126 Q (c) Q(cv ab)

c v ab, 1.

The solution process of the forward reachability through neighbourhood st� second step: Q1 (abc) Q 1 (ac v be)

:

.c v be, ac v be.

The non-equivalence of this last result with the result from solving the gener... ward reachability problem is explained by the existence of the 1-confticting sta:! in the deined state set. The shit of the initial circuit with respect to the st�! given by the Boolean function icV ib {Fig. 5. 1) is described by the equation ! a b c

c V ab c v ab (a Y b)c V ab

and by the transition diagram in Fig. 5.8. Continuing the solution process forward reachability through neighbourhood gives for this circuit Q 1 (ac v be) Q1(c) Q1(cv ab) Q 1 ( c v a v b)

c.1

c, c V ab , c V a V b, cV a v b .

The fact that this result is not identical with the solution of the general fo reachability problem can be explained by the presence of another 1-conticting � - 111 . The shift of the circuit to the state set given by the Boolean function c {Fig. 5.9} is described by the system of Boolean equations a c

b = c (a V b) c V ab.

Its transition diagram is given in Fig. 5.10. For this circuit Q 1 (cv av b) gives the solution to the general forward reachability problem. 5 .4

=

1, u:t

Semimodular Circuits

It should be pointed out that the name of this speed independent circuit clss well as those of other circuit classes) is connected with its algebraic properties.

I

•

- 127 -

a

Fif..

Fig.

o·o·o

I

\

· 1 0 0·

0·10

/\ I

10·1

110

\ I 1 1 1•

(al

·

5 .9

5 . 10

o·o·o

I \

· 1o o

o· 1 0

\ I 110 . 111

I bi Fig.

(c) 5. 11

- 128 -

It is ll known that speed independent circuits can operate correctly for arbitrary finite element delays. However, so far no synthesis methods are known for speed independent circuits, which are not semimodular. Thereore, in practice, semimod­ ular circuits are used, and analyzing the correct operation of a circuit for arbitrary finite element delay values means checking the semimodularity of the circuit. we

A circuit is semimodular with respect to . state a, if each state 3 reachable from the state a in this circuit is non-conflicting with respect to all variables (see Dei­ nitions 2.2.2 and 2.2.4). The analysis of the circuit membership in the semimodular clss must apparently include a search or conlicting states. The ollowing theorem points out the possi­ bility to simplify such an analysis. circuit is semimodular with respect to the state reachable from the state a is not a 1-conlicting state.

Theorem 5.4 A

:

, if each stat�

The proof immediately follows rom Lemma 5.1. If a circuit is semimodular with respect to the state a, then the set of states reachable in this circuit from the state a coincides with the set of states reachable from the state : through neighbourhood.

Theorem 5 . 5

The proof immediately follows from Theorem 5.1. As already hs been stated, some excited variables can be stable due to: change of the value of the variable, 2. the change of values of other variables, which this irst mentioned variable depends upon. 1.

n

a semimodular circuit only the first way to remove the excitation rom a variable is possible. A consequence of this is that the removal of one or several variable exci­ tations cannot "disturb" the removal of other variable excitations in a semimodular circuit. If states reachable rom the state a in . circuit are conflicting (with respect to variable Zi ) , then the circuit is not semimodular relative to the state (not semimodular for the variable ;). :

In a circuit 0 the sets of states conlicting and 1-conlicting with respect to the variable Zi are given by the Boolean functions

Statement 5.3

and respectively.

- I 29 -le validity of these formuls ollows rom the fact that they give the intersection etween the state set Zii(Z) and Zii (Z), or which the variable Zi is excited, .::d the state set Pc (zdi(Z)) and Pc (ii(Z)) after which ollow states with a �:able variable i without a value change of Zi (the latter state set is given by ?i(zdi (Z)) and Pb (zih(Z)), if the mentioned successor states are deined through :eighbourhood) . i

order to ind the state set relative to which . circuit is not semimodular, the et of stats which are conlicting (I-conflicting) with respect to all variables is irst :eined, and then the backward reachability problem is solved for this set. For this i:irpose it is suicient to solve the backward reachability through neighbourhood ccording to Theorem 5.I (Corollary 5.5). 'he speed independence properties are "global" in the sense that it is forbidden to enter a circuit state or which these properties are broken (this somehow explains diiculties to develop synthesis methods or the general case of speed independent circuits). On the other hand, the semimodularity properties can be called "local" . n particular, the localization of non-semimodularity

in conflicting states constitutes eicient check of the semimodularity of circuits. Analogously, distributive and sequential circuits s well s some other subclsses of speed independent circuits have "local" properties. n

Distributive circuits constitute a subclss of semimodular circuits. Additionally, or these circuits there are convenient synthesis methods bsed on the so called transition charts, which cannot be used or arbitrary semimodular circuits.

The state a is detonant with respect to . variable zi, if a is ollowed by a state pair, 3 and 1 ( a - 3, a - 1), or which :i = 3i = Ii = t( a) and /i (') = i(I) . ai (i.e. that the variable Zi is stable in the state : and excited in the states 3 and 1) , and, additionally, neither 3 - I nor I - 3 takes place. U 1 and 1 are such that a � 3 and a � I , then a is I-detonant.

The state OOO in the transition diagram in Fig. 5.Il.a,b is not detonant. However, the state OOO in the diagram in Fig. 5.11 .c is detonant with respect to the third variable but not conlicting.

It should be pointed out that the relationship between detonant and 1-detonant states is analogous to the relationship between conlicting and I-conlicting states (see Lemma 5.1). A circuit is distributive with respect to a state a, if each state 3 reachable rom the state a is neither conicting nor detonant with respect to all variables (this . corresponds to Definition 2.24).

- 1 30 -

circuit is distributive with respect to the state a if no 1-conlicting or 1-detonant state is reachable from the state a in this circuit.

Theorem 5.6 A

Theorem 5.6 is an obvious analogue to Theorem 5.4.

The unambiguousness of the local prehistory is a property of distributive circuits in the sense that each excitation of any variable can be caused in only one way by changing the values of all variables belonging to only one minimal collection of variables. The sets of detonant and 1-detonant states with respect to able j are given by the Boolean functions

Statement 5.4

(zi i h (Z))

v

a

vari­

Pc ((zi i h (Z))z,)Pc((zi i h (Z ))z1)

and

respectively. The validity of these two formuls follows rom the fact that they give an intersection of the state set Zi i /i (Z), or which the variable Zi is stable, and the state se! Pc(( zi $ /1(Z))z;) and Pc((Zi i i (Z))z;), from which two different states with the variable Zi excited are immediately reachable (the latter state set is given by P6{(i l /, (Z))z;) and Pb {(zi l fi(Z))zi), if the mentioned reachable states are deined through neighbourhood) . Sequential circuits constitute a subclss of distributive circuits. The state a is called bifurcant, if it hs more than one variable excited. A circuit s sequential with respect to a state a, if each state 3 reachable from : in that circuit is not bifurcant. Statement 5.5

function

The set of bif.rcant states of a circuit C is given by the Boolean

V

l, i,j,n,ifj

(i i f, ( Z)) (z; i /; (Z)).

The search for states, with respect to which a circuit is non-distributive ( non­ sequential ) , is performed analogously to the search for states, with respect to which a circuit is not semimodular. Parallel-sequential circuits, which are a further extension of sequential circuits ­ also a subclass of distributive circuits. The typical properties of states in circuits

- 131 -

belonging to this circuit class will be given in order to introduce the deinition of this circuit clss. The main successor of the state a is a state P following a (a 3) and difering rom a through the values of ll variables excited in the state a. +

A state : will be called a hammock state, if the variables excited in each of its .mmediatesuccessors - except perhaps the main successor - are the same variables (,B; = f; (8)) that were excited in the state a and have the same values that they had in the state a (ai 3; fi (a)) . =

=

A circuit is parallel-sequential with respect to a state a, if each state 8 reachable :rom the state a in that circuit is not conlicting with respect to all variables and s also a hammock state. Each variable in circuits of this clss is excited only after the stabilization of all previously excited variables through their value changes. Statement 5.6

The set of non-hammock states in a circuit C is gwen by the

Boolean function

V

1$i ,j$n

Example 5 . 2

( z; $ /; (Z))(z; $ ; (Z))Pc ( (; $ fi (Z))(z; $ /; (Z ))) .

The circuit in Fig. 5.12 is given by the system a

b

c

c a b

of Boolean equations and by the transition diagram in Fig. 5.19. This circuit is sequential with respect to all its states except to the states OOO and 111. The circuit s not semimodular with respect to the latter Jtates. The circuit in Fig. 5.Lt given by the system a

b

b a

c

c

of Boolean equations and by the transition diagram in Fig. 5.15 is distributive with respect to all its states. This circuit is however not parallel-sequential. The circuit in Fig. 5.9 is parallel-sequential with respect to all its states.

.

.

complete analysis consists of splitting the state set of circuit into two subsets: forbidden and allowed states. To the orbidden subset may - depending on what

- 132

Fi g .

....

) . 12

Fig. 5 . 1 3

Fig.

) . 14

Fi g .

5 . 15

- 133 -

classiied property is investigated - belong states with respect to which a circuit is non-semimodular, non-distributive, etc. Thus a complete analysis makes it possible to investigate the behaviour of a circuit for all sets of its states.

Example 5.3 A

complete analysis of the semimodularity of the circuit in Fig. deined by the system a

c

b c d e

ab V c (a V b) b cd v e(c v d)

5. 1 6

e

of Boolean equations gives the following results. states, which are given by the function

The circuit has twelve conlict

bde v bde v ace( b v d) v ace(b v d).

The

circuit is non-semimodular with respect to fourteen states given by the function e(ac v bd) v e(bdv ac) .

The circuit is semimodular with respect to the remaining eighteen states given by �he function ce(b v d) v ce(b v ) V ae(dv be) v a(de v bed) . h

should be pointed out that although the result of a complete analysis gives ex­ :ended information about the behaviour of a circuit, it is not always necessary and convenient. 5 .5

The Set of Operational States

:: some initial state is given for a circuit, then all circuit states reachable from the :.:tial one will be called operational states. The cardinality of the set of operational s:ates is often considerably smaller than 2" ( the cardinality of the set of all circuit !:ates) , where n is the number of circuit variables. The analysis can be simplified :y taking this point in consideration. Such a simplification is, for the first, b�ed on �:raction of the typical properties of the set of operational states, and, secondly, =n utilization of analysis methods taking these properties in consideration.

- 1 34

·-

c e

b --- �l J L

d

5 . 16

Fig.

-- O * O * O

1

0*1

1

1

,

o.1

--. ·1 ·1 _ 1

1

--�

1

1

,,/ . -

O*

�

� 0

0

1 *0

0

0

1

0

0

1

0

/

�--

� 1 1

1

--.. 0

0 *0*0

1

0

0

--

�

,,. /

1

O*

../ 1

0

0

�

1*1*1 0

0

;;·:

0

..0 0 1 *

.... . ._, 1 1 �0*1

� 1*1

0

0

5 . 17

1

O

0

0*1

0

1

�1

1

0*1

1

0

1

l* 1 1 ..._

1 *0

1 *0

./· 1

1

1 *

·-... 0 0

o

1 *0

Fig.

1

�

O

/

1 *0

1*1*1

0 - ---

. --0 *1

o

;----

0

0*0

0*1� 0 O*

..._

1

-�

..... . .. _ .

1

--­ -- 0 * 0

1

0

./--� 1*1*1 1 1 1

1*1*1

----

1 *0

0

·---·-

· --- 1

0 -- ---

0

�

/ �' 1*1

0

0

� � 0*1 O*O*O 0 0 � -1 1 O *O*O 0 0 0 0

�; �

1 *0

1

_ __ _

1

o

o

0 -

I

_ _

1 • 0 -��

- 135 -

A set of all circuit states such that or any state pair (:, 3) belonging to this set takes place : > 3 and 3 > a, will be called an equivalence clss. An equivalence class is called ictitious, if some variable i hs one and the same value and is excited in all circuit states n this clss. An equivalence clss is called closed, if an immediate successor of the clss coincides with this same clss (this means that if a state : belongs to the class and : > 3, then also 3 belongs to the class) . A

trivial example of a closed clss is constituted by the dead circuit states, i.e. the states in which all variables are stable.

A circuit is speed independent with respect to a state a, if the set of states reachable from a contains one non-ictitious equivalence clss. From this ollows that the set of speed independent operational states (this means states reachable from some initial state) contains exactly one closed equivalence class, and, in particular, this set can contain no more than one dead state. It should be pointed out that all considered clsses of asynchronous logical circuits are subclasses of speed independent circuits. Let there be a circuit C with the initial state a. Then the set of operational states for this circuit can be deined using iterative solution methods of the orward reachability problem. n this context, the purpose is served by checking - in each step solving the orward reachability problem - the membership of the circuit in some of the classes which are speed independent. The process to construct the set of operational states stops when no new states can be generated at the next step. At a irst glance it seems to be necessary to store all earlier revealed states in order to reveal new states. According to this, checking the stopping condition of the process, which in principle must be done in each iteration step, is the most labour-consuming thing to do in this iteration. The procedure can be simpliied, if the search at each iteration step for all immediate successors of the hitherto ound set of operational states is abandoned, and the search is limited to only deining states, which belong to these immediate successors, and which still haven't been included in this initial set. Thus; only operational states, which were revealed during preceding iteration steps, are interesting. The expenses of the special eforts to provide reflexivity to the reachability relation between sets derived during each iteration step are unnecessary. This fact makes it possible to simplify the construction of the set of operational states. For this purpose the formulas

Rb (pf(Z)) =

V

1;i;n

PA (Zi ,

·

·

·

, Zi-1, Zi, Zi+l,

·

·

· ,

Zn) .�i i /i(i, . . . 1 t, . . . 1 Zn )) ·

- 136 and 1 Rc(�11(Z))

=

I

v

Si Sn

-

�11(zi, . . . , Zi-1. /1(z1 , . . . , z;, . . . , Zn); Z;+ i, -

.

•

.

, Zn)

can be utilized to define states following the states in the set A through neigh.::­ hood.

A state sequence a1:2 . . . a1 (a' t a1+1) is called complete, if it is finite and ::a with a dead state or is ininite and doesn't contain any ininite subsequence % which there is some variable having one and the same value and being excitee % all states in this subsequence.2 Some comments on the concept of a complete sequence will be given. Sequen!I can apparently be presented by transition diagrams s inite ( if they don't contJ cycles) or s infinite ( if they contain cycles ) . Only such finite sequences, which u not be continued, are complete. This means that such sequences end in a sta�.. state. Among the innite sequences are complete those in which a circuit . " circle" for an arbitrary period of time . According to the hypothesis about i:Jt element delay, these properties are not possessed by loops in which some varia_ keeps its value and is excited in all states of the loop, because the value of : excited variable must change sooner or later. rom what hs been said it is cler that such sequences are complete, which in an exhausting way characterizes te order of possible state changes of a circuit. The subset of operational states of a circuit C, which are reachable from the ini�... state a after K steps through neighbourhood, is called the K:th layer LK of t� full set of operational states. The zeroth layer is Lo = {a} . From what hs been said ollows that the set of layers is ordered . A layer will st. repeating itself because of the inite number of circuit states starting rom o� step m in the construction process of the set of operational states. A layer of the set of operational states fully coincides with one of those which earlie­ have been called multiple ones. Let Vm be a multiple layer of the set of operational states of a circui! which means that Vm = Vi: for m > k. Then the set of operational states is

Theorem 5 . 1

3

=

v

D;iS m-1

i.

The validity of the theorem becomes obvious after having compared the deinitio� of the K :th layer and the set of operational states. �This definition coincides with the definition of an allowed sequence or a complete path.

- 137 -

From Theorem 5. 7 immediately follows that if some stabilization occurs in the :.rcuit analysis process - some m:th layer turns out to be a multiple one, which :::eans that the set V received in the m:th analysis step ully coincides with the state set Vk selected in the k:th analysis step (m > k) then all operational circuit s!ates after the initial state have been scanned. A repeated appearance of some layer � thus a stop signal to the construction process of the set of operational states. m

-

Generally speaking, not every layer obtained in the analysis process can repeat ::self. Some operational states are encountered only once in the operational process of a circuit. It s evident that such a state can 't enter any multiple layer. Each layer consisting of such states is complete in the sense that in a set B no layer covering :he whole set is found. ll multiple layers are complete too.

From Theorem 5. 7 ollows, according to what hs been said, that each state J in any complete sequence starting from the initial state a of a circuit 0 belongs to some complete layer Vr of the set of operational states. It is necessary to choose a "candidate to the position" of a multiple layer in such a :ayer-organized analysis (such a layer will be called a check layer) . Unortunately, w formal characteristics can be ofered or the selection of a check layer. It is evident that the operational state counts in diferent layers may be diferent. For instance the layer with the highest state count can be used s a check layer. f the set of operational states is an equivalence clss, then such a largest possible !ayer is obviously complete and multiple. f the set of operational states contains some initial fragment, i.e. this set contains some states which are not re-entered during the circuit operation time, but states belonging to the inite equivalence clss are reachable from these earlier mentioned states, then the broadest layer can - generally speaking - belong to the initial ragment, and, consequently cannot oe multiple. In this cse, the analysis of the set of operational states with the aid of layers may "lst forever" . n most real circuits initial ragments are however not wo broad, because these fragments have a lower degree of parallelism than cyclic fragments of the set of operational states have. It should be observed that an analogical layer organization of the analysis can be suggested also when "parallel" (not through neighbourhood) solution algorithms of reachability problems are used. Two adjacent layers may however then intersect. Such an event is impossible when solution methods bsed on direct reachability in semimodular circuits are used. A layer consisting of one state has a minimal breadth. Such a layer would be convenient to use as a check layer. Let us consider the conditions under which this S possible.

Let B be the state set reachable rom states of a set A in

.

circuit 0 (A

C

B).

- 138 a

sequences starting from states in 8 contain The state

A

will be called a nodal one or the set

a.

in this circuit, if ll c•

Let a circuit C be semimodular with respect to states in a &�; the state a is a nodal state for the set A, then exactly one variable is excited s state 3 reachable from states in the set A in this circuit in such a way that 3 = 1 and 3 --+ a .

Theorem 5.8

.•

On the other hand, if one non-ictitious equivalence class B is reachable from .. in the set A and the state a E A is such that exactly one variable is excited in .. in B , for which 3 � : and 3 - a, and which are reachable from states in A� A, then a is a nodal state for the set A . For the proof of Theorem

5.8

also ormulated and proved.

some concepts are introduced, and two lemmM L ,

A state sequence :1a2 a'c a1:2 . . . , :' + :'+1 , ac -+ : 1 , will be called a icti:i:. cycle for the variable set Z', if each variable Zi E Z' has one and the same -�e •

.

.

and is excited in all states of the sequence. Such a sequence will be called a st :a

Z',

cycle or the variable set

if each variable i

E Z'

is stable and hs conseque:�.

one and the same value in all states of the sequence.

1

To each fictitious cycle for the variable set

2\Z'I

-

a state

i

conjugate cycles, difering from

Z'

in a semimodular circuit correspot

in which to any state

ai

ai

of the ictitious cycle correspon!

only by values of variables in

Z 1•

If there is a nodal state 3 for the state set A in a circuit C and lt circuit is semimodular with respect to 3, then 3 can't be included in any ictitio, cycle.

Lema 5.2

Proof.

l.

A

Z" � Z'

conjugate cycle difering from the ictitious cycle for

variables in

2.

through values o!

is

a) ictitious for each variable in

b)

Z'

Z' \ Z " ,

ictitious or constant or each variable in

Z".

It will b e shown that if A is a ictitious cycle, then for each state

a complete sequence not containing :. Let

aE A

exists

A is ictitious. I a conjugate cycle B difering from A through the values Z' is constant for all variables in Z', then B is the sought-or complete sequence. If B is ictitious for Z"' � Z', then a conjugate cycle D difering rom A through values of variables in Z' \ Z"' will be examined. D is a stucked cycle for Z'\ Z"' and ictitious for Z"' because of the semimodularity which

of all variables in

Z'

be the maximal variable set for

- 139 of the circuit. Let B = 31 32 . 3e 31 . . . and D = 6182 . . . ok§I Then, for 2 ckcl 0: 1 e e eseI 3 I 3 + doesn't contain 3 1 +1 any ac E A, the sequence 8 8 . . a and is complete. .

.

.

.

_

.

•

.

t

Let a J and a . I in a circuit which is semimodular with respect a. Moreover, the sequence leading from a to I contains a state pair a1 ,a2, for

ea 5.3 :]

.

.

hich a1

t a2.

Then 3 .

I·

?-oof. Let :1 ,a2 be the irst state pair satisfying the condition of the lemma in the equence leading rom a to I· Then, because of the semimodularity, there exists equence leading from 3 to a1, such that each state in it - except a1 - difers :�om the corresponding state n the sequence leading from : to a1 only through the Lue of z1 . Consequently, 3 . a 1 . /. ?:oaf of Theorem 5.8. l.

Let J be a bifurcant state. It will be shown that t is not a nodal state. Because of the biurcant characteristics of 3 a state a' . t will be found for which 3 t .1 • Because of the semimodularity of the circuit such a state 1 will be ound for which : � I and a' � 1 If 1 is the only immediate successor of a or if 3 is the only immediate predecessor of :, then there exists a sequence leading from I to 3 and not containing a, since all indicated states belong to one equivalence clss. In the opposite case, even or only one direct immediate successor .0 of : takes place a0 . 3. Then also the sequence leading rom .0 to 3 doesn't contain the state a. Because of the semimodularity of the circuit there exists a state 1° for which I . 1° and .0 t 1° . Since the variable ; is excited in the states 3,:,1° and has one and the same value in all these states, then Zi must change its value in the sequence leading from .0 to 3, as 3 � a . a0 . 3 cannot be a a ictitious cycle (Lemma 5.2). Hence (Lemma 5.3) takes place 1 ° :} 3, and moreover, if the sequence leading rom a0 to 3 doesn't contain the state :, then the sequence leading rom 1° to 3 doesn't contain a. Consequently, there exists a cyclic sequence (3 � t1 � I . 3) , which dosn't pss through a and which is either complete or ictitious (and then the ictitious and cyclic sequence passing through : is 3 � a � I . 3). This and other things are in contradiction with the statement ". is a nodal state" . The opposite is proved indirectly. Let L = 1°1 1 . . / e l o be a complete se­ quence not containing a but the "nearest" to the state :. By induction on the "distance" between L and a, which is the length of the smallest possible sequence leading rom the state Ii E L to the state a, it isn't diicult to show that there exists a bifurcant state 3 or which 3 .; a . ·

2.

.

- 140 -

Theorem 5.8 can be illustrated in the following way. For a number of real circ� the output of one of the elements ( indicator) is changed s the last one and � output is excited only after ll other circuit elements have switched. The state . which this element will be excited will also be nodal. Nodal states are or instance the states OOO, 110, 1 1 1 , 001 in the circuit in Fig. (the transition diagram is n Fig. 5.10).

5.

The following theorem establishes a correspondence between the concepts of a noeL and a layer with a minimal breadth.

state

If some layer LK in a circuit, which is semimodu.lar with respect !: the initial state, contains a nodal state3, then this layer doesn't contain any mo� states. Theorem 5.9

On the other hand, i/ a multiple layer LK contains one state, then this state nodal.

u

Proof. It is ssumed that the layer LK contains two states one of which is nod: Then, considering that e.eh state, which is directly reachable from the initi al sta� and directly ollowed by a nodal state, is a non-bifurcant state (Theorem 5.8), i� isn't diicult to show by induction that each layer Le, 0 � e � K 1 contains more than one state. This is in contradiction with the condition I L0 J = 1 of the theorem -

The validity of the second part of the theorem will be obvious, if it is taken intn account that the whole closed equivalence clss of states :e.chable from the initia! state is contained "between" Lm and LK. The process of constructing the set of operational states in a circuit can according to Theorem 5.9 be considered to be terminated after the occurrence of one and the same nodal state or the second time.

A nodal state is - unortunately - not always ound in every circuit, which is semi­ modular with respect to the initial state (see or example Fig. 5.17) . Nodal states are usually not ound for pipeline circuits. Some subclsses of semimodular circuits are, however, the only clsses or which operational state sets with nodal states difer from each other. This is - for example - the cse for parallel-sequential circuits.

The circuit in Fig. 5. 9 is - as already has been said - parallel­ sequential with respect to the state OOO. Let this state be the initial state. The functions given by layers of the operational set have the form Example 5.4

Lo

=

abc,

3 This means that this state is nodal for the set

{,} = L0, where a is the initial st.te of a circuit.

- 14 1 -

L1 L2 Ls L4 Ls Ls

-

-

a(bc v be), abc, abc a(bcv be), abc ,

abc

-�e operational set is described by the Junction

V

Li =

0 9 55 'he states OOO, 011, : odal in this circuit.

111, 100

1.

given by the functions Lo, L2, Ls, Ls respectively are

ome nodal state properties of speed independent circuits are mentioned in following :.eorems. dosed

If the state a is nodal for the state set A, then a belongs to some if the set A doesn't form a ic titious class, then A = 3 .

class 8 . Moreove r,

Theorem 5.10

If there exists in a circuit G a state a, which s nodal for the state set A, then the circuit C is speed independent relative to all states in A . Theorem 5.11

Theorem 5.12

If a circuit C is parallel-sequential with respect to the state a, then there exists a nodal state for {a} .

There exist, however, circuits, which aren't parallel-sequential, but still possess an operational set with nodal states. The circuit in Fig. 5.16 isn't parallel-sequential for instance with respect to the state 00000 . The operational state set for this state, which has been chosen to be the initial state, however contains four nodal states: 00000, 11110,

Example 5.5

11111, 00001 .

Example 5.6

(Illustrating the "interaction" between analysis and synthesis in the design of aperiodical circuits.) Consider a well-known shit register consisting of an interconnection of three so called "David cells" {RS-tip-lop with a gate}. This circuit is - like a circuit with a great number of cdls - capable of correct operation for ini"tial states in which only one variable is excited. Now a question arises about the operational capability of such circuits for initial states with two simultaneously excited variables. This question concerns the possibility to use such circuits in a pipeline mode. An analysis

- 142 -

of the operational state set shows that a register containing / David cells hiu is this case no operational capability: the register quickly enters a dead state, whi: . is not allowed for autonomous circuits. On the other hand, an analogous circ..: consisting of 6 David cells, has no dead states. The operational state set of c�' latter circuit however contains conlict states. Th's latter circuit is consequen..1 non-semimodular. n Fig. 5.18 is presented the inal variant of the pipeline an e J of a register of the described type. The implementation of this variant required '· ! introduction of additional gate inputs and corresponding wires. __

Each complete sequence starting from the initial state isn't investigated in t� described analysis methods. On the other hand, sequential steps speeding up �� circuit analysis process are immediately taken along all paths of the correspond!� transition diagram.

5.6

A Circuit Model with Non-zero Delays of Interconnection Wires

Earlier issues of the analysis of logical circuits have been considered for assumpt.io� that the delay of interconnecting wires are negligently small s compared to �-� element delays. This hypothesis is not valid for circuits, in which the operati.� speed of the elements is so great that the size of element delays approaches the :�t of the delays in the wires. This is the cse, or instance, for circuits bsed on t�� I2L-technology or on the Josephson efect.

Moreover, there exists a wide clss of interface devices, which are connected to ot h� devices by comparatively long communication lines with delays considerably excee6ing the element delays. The problem of skew delays is a characteristic phenomena= or such devices. The delays of the wires have or a greater circuit integration leYe. . more and more noticeable inluence on the circuit behaviour, s these delays .. � comparable and even greater than the delays of logical elements. What hs b. said stipulates a necessity to analyze how the operation of synchronous circui! depends upon the delays of the wires. In some cses it is necessary to analyze circuits, in which the internal communicatio= is ssociated with considerable delays. Then special elements - repeaters - can ! introduced ( on the modelling level) instead of wires with considerable delays, :. the hypotheses of the circuit modeling principles must not be revised. What h� been said makes it possible to utilize earlier described methods in order to chU whether circuits with considerable delays in some wires operate correctly. Th investigation of the circuit presented in Fig. 5 . 1 9 is an example of such analys5 An analysis of the operational state set shows that the circuit is semimodular, o: instance with respect to the initial state 0 1 1 1 100, if the size of the wire delays isn·�

- 143 -

'ig.

5 . 18

-- ---

�----

- 144 -

essential. Taking the communication delays in consideration leads to the :... results. Delays, which do not disturb the correct circuit operation, are she� unshaded rectangles in Fig. 5.19. Communication associated with consi!e;r delays in the places shon by the shaded rectangles in Fig. 5 . 19 leads to violatio:: l the semimodularity of the circuit. Other communication in the circuit is analogous.y considered (with the aid of the marked rectangles) . Therefore, it is not required to analyze the circuit for correct operation by inserting delays into this communication. a

Attaching delays to all (or to most) internal communication of a circuit sharply adds complexity to the analysis tsks and makes it diicult to solve them. Thereore, there is an interest in the investigation about the objective laws according to which wire delays influence the behaviour of . circuit. There is also an interest to use the results of such investigations, in the development of methods, which don't require the introduction of additional vri.bles in a circuit. A wire is - using the earlier introduced ormal model of an synchronous logical circuit - deined as a pair of natural numbers (i, j) , such that /; ( Z) essentially depends on the variable z; . A wire (i,j) is an input to z; and n output rom Zi . Accordingly, Zi is the input variable and z; the output variable of the wire (i,j).

Let C = {(ii,j1), . . . , (im , im)} some wire set of a circuit C. The sets of input and output variables of wires in C are marked by I(C) and O(C) . f z; E O(C), then the set of input variables of all wires in C , or which z; is n output variable, is denoted by I(j, C). The influence of the wires on the behaviour of a circuit can be taken into consider­ ation by introducing additional variables in a ormal model. The circuit et = (zl, pl) or which 1.

2. 3.

zc

= Z U c• where '' = {ei, . . . , em} C (Zl) = z· e 'L = Je; < k< m' 'e ' 1 -

and

,• n Z

=

0,

if z;" E O(C) then ,1 = ff1 (Z l) = h. (z;" e), where zio E I(ii1 , !) (i.e. that eeh variable z;1 E I(i, C) is replaced by a new variable ek) , and if Zi . � O(C), then Zi" = /;� ( zl ) = fio (Z) =

will be called the extension of a circuit C for the wire set

C.

The introduced concept corresponds to the following ssumption: there is a delay in a wire after the last branching point with the exception of the cse when some element output is connected to some input of the same element. Then the delay is inserted before the branching point. This means that in practice the wire is considered to be without branches in miscellaneous inputs of one element.

- 145 -

f i g . 5 . 10 ,

ig.

5 . 20

- 146 -

The state of the circuit c c is a vector · of values of the variables Z C . This vc: of course consists of the vector a of values of the variables Z and of the vector a· of values of the variables . * . The projection of the state a = a 1 . . . an of a circuit C = ( Z , F ) on the variable : Z' = {zi " . . . , Zi1 J � Z is a vector al Z' = ai1 a;k of the values of all variab:� in Z', when the circuit is n the state a. •

•

•

Let a1 a2 . . . ak be a state sequence of a circuit, where a � a1+1 and a - ci+1 . � projection of this sequence on the variable set Z ' � Z is a sequence of projectiou of states in this set derived rom a11Z', a2 IZ', . . . , aklZ' through removal of e:: member, which coincides with the preceding one. The circuits C1 = (Zi, Fi) and C2 = {Z2, F2) will be called equivalent for the variable set Z � Z1 n Z2 with respect to the state pair (a,3) , if the sets of diferen: projections of complete sequences on Z starting rom the state a or the circuit C, and rom the state 3 for the circuit C2 are identical. ·

Equivalence of the circuits Ci , C2 for the variable set Z will be marked by C1 �i -

For an arbitrary state a of a circuit C such states of the ssociated extension e. will be marked by & and :, for which &IZ = a! Z = a, &k = a;" ' :; = a;"' 1 � k � m . A circuit C is insensitive to the wire set l with respect to the state a, if C 'c. with respect to (a, :) .

All circuits, which aren't semimodular, are sensitive to the wires. This is explained by the fact that absence of semimodularity indicates circuit operation dependency on element delays. A circuit C, which is semimodular with respect to the state a, is strictly insensitive to the wire set C relative to this state, if the associated extension cC is semimodular with respect to the state & for the variable set Z . A circuit C, which is strictly insensitive to the wire set C with respect to the state a, is also insensitive to C with respect to a .

It should be pointed out that the extension c c may be non-semimodular for strictly sensitive circuits - even if these circuits are insensitive.

However, if a circuit C is insensitive to the set of wires C which are inputs to z; (0 ( C) = { z;}) with respect to the state a, and if the variable z; is self-independent, i.e. f;(Z) is independent of z;, then this circuit is strictly insensitive to C with respect to a.

A circuit, which is sensitive to the wire set C with respect to some state a, is evidently also sensitive to f U {j, i} with respect to the state a, where (j, i) is an arbitrary wire.

- 147 -

.

Analysis of the Sensitivity to Wire Delays

If a circuit C is sensitive to the wire set C with respect to the state n Jure exists a variable z; E O(C), such that the circuit C is sensitive to the � M: _i, for which O(Ci) = {z;} and I(C i ) = I(j, C) .

m 5.13

the extension et of the circuit C all complete sequences of the circuit to the set of projections of complete sequences on Z . Consequently, • .-;on of the equivalence is possible only because of the generation of new �. which in tn s a result of new excited variables in Z . Let J be a state uit e. ' such that some variable Zj E 0( e)' which is stable in the state BI z , -Cuit 0, is excited in 3. Moreover, there exists a state sequence leading from : l which 3 is the irst state satisfying the described condition. f a1 t a2, _ ; E Z, occurs in this sequence, then - s a result of the selection conditions a:d with the state 3 - a1jZ r a2J Z occurs in the circuit C. This means - :. (Z U I(j, C)) t a21 (Z U I(j, C)) occurs in the circuit ctJ . If a1 h :2 , ,& E I(j, C), occurs, then a1j(Z U J(j, C)) h :2j (Z U I(j, C)) occurs in the _ : c:J. f tc . I(j, t), then a1 j (Z u I(j, !)) = a2)(Z u I(j, C)). From the _ i Z U l(j, .)) in the circuit ctJ the state 31(Z U I(j, C)) is thus reachable, • _.-� the variable z;, which is stable in the state JIZ of the circuit C, is excited. .=:sequently sensible to the wire set CJ. -

n

·

:. g

•

•

. ;e lst theorem follows that i

�!= �

�

there is no necessity to examine all possible wire circuit in the analysis of the sensitivity of the circuit to wire delays. It is to consider only wire sets having the same output variable.

a

�.cept of the Boolean derivative function a t ( Z ) /az, for a variable Zj will be �r analysis purposes: ai(Z ) a z;

=

i(z; = o) e h (z;

=

1)

=

h (Z ) e i( z1 , - . . , ; , . . . , zn)· _

- � said that the variable z; is active or ; in the state a � opposite cse z; is said t o be passive for z; in :. ,_

:,

if a h ( !) I a Zj

=

1.

:· �

Z be some variable set of a circuit. A state, which is opposite to the � i on Z', will be marked by :(Z') . A function derived rom f(Z) by inverting �ables in Z ' is accordingly marked by f(Z (Z') ) . In particular, f(Z (zi ) ) = The function S i(Z)/SZ' = f; (Z) $ /; (Z(Z')) is :• . . , z;-1 , : , ;+1 , . . . , zn)· � the sensitivity function of /t(Z ) on the variable set Z'. J of a circuit C will be called critical for if Zj is stable in the state 3 and S /; (P)/ S Z'

� :ate

: ;

:,

the variable =

1.

Zj to the set The state 3 is called

- I48 strictly critical or z; to the set Z', if 3 is critical for z; to the set Z', or ! .. excited in J, S /; (3)/SZ' = O, and there exists a variable zc, which is active ::c . in the state 3\Z') . Moreover, if zc . Z', then zc is excited and pssive or z, :.. state 3. The ollowing theorem gives necessary and suicient conditions for sensitivity strict sensitivity of a circuit to the wiring.

lC

circuit C is sensitive (strictly sensitive) to the wire set . . respect to the state a, if it has a state 3, which is critical (strictly critical) for !cr variable to the set I(C'), ,' � l, and, moreover, the state 3 is reachable from k state & in the extension c £ ' .

Theorem 5.14 A

Proof. The case of strict sensitivity will be considered. It is suicient to take :: account only such .C, or which O(C) = {z;} (Theorem 5.13). 1.

Let or some C' � , 3 be reachable from & the circui. e.' , in which 8 J strictly critical to I(l'). If J is critical to I(C'), then the variable z; is stab'.� in the state 3 of the circuit 0, and, s /; (3) . f; (3(I( C')) ) , then z; is excite ' in the state 3 of the circuit e . . Hence the extension e .' is non-equivale.: to the circuit C (on Z ) with respect to (:,&). The circuit C is sensitive o C' and thus also to . . Consequently, C is strictly sensitive to . with respec� to :. If 3 is noncritical to I(C'), then 3 h f' occurs in the circuit e . ' , n which z; is excited in 3 and stable in J' s zc is active or the variable z; in the state 3(I{l')) . The state p of the circuit cV is thus I-conlicting with respect to the variable z;' and hence the circuit e .' is non-semimodular with respect to the state & on the variable z;. The circuit C is strictly sensitive to f/ and thus also to l.

2. The converse. Let l' ;; . be the minimal wire set to which a circuit C is ' strictly sensitive. This means that the extension c c is non-semimodular with respect to &. The state sequence leading from & to 3, where 3' (8'\ Z = 3) is the irst I-conlicting state with respect to z; in this state sequence, will be considered. 31 = 3 s .C' is minimal. It will be shown that 3 is strictly critical for z; to the I(C') state. The variable z; is excited in the state 3(I(C')) of the circuit C (otherwise 3 would not be conlicting). Consequently, 3 is critical to I( C') , if z; is stable in the state 3 of the circuit 0. Let now Zj be excited in the state 1. Then S /;(1) /SI( .') = 0 because z; is excited in the state 3 of the extension c£ ' . Since 3 is I-conlicting with respect to z3 , then 3 +s occurs ' in the extension c C , where 31 = S; and If (8) . If' (8). If z = ei. E .C') * , then the variable Zi. E I(C') is active for z; in the state J(I( .')} . If, however, z = zc E Z , then zc is active or z; in 3(/(.')} (otherwise Zf would be excited in the state 8 of the extension oC'), is excited in 3, and is passive or Zj in 3 (otherwise the state 3 would be conlicting). The state 3 is in that case

- 149 in the other cse strictly critical for z; to I(L1). The proof for the �-�civity case is contained in the just described proof. :: o

be the set of wires from the output variable z; {O (C) = {z; }). 1�nsitivity {strict sensitivity) of the circuit C to the wire set £ with respect • �;1e a it is necessary and suicient to find in the circuit C a critical state ; :o the set I( C'), C' � C, such that

� 5.15 Let .. •

-

.&�·e exists a state sequence leading from !! I(C') change1 and

a

to 3 in which all variables in the

variable z; changes in this sequence1 i. e. if a � f h o . 3 occurs, - �I Sf;(l)/SZ' O, where Z' £ l(.') contains all such (and only such) : iri.bles in I( C'), which don't change in the sequence leading from the state :o the state 3.

- :

Ae

=

�:

in the circuit C be found a state sequence u leading directly rom a critical (strictly critical) st.te 3, which satisies the conditions of the orem. Then a sequence v leading rom & to 3 is found in the extension ::.: and the projection of this sequence on Z is no less than u. Actually, if : c h ci+I occurs in u, then jP k SP+l occurs in the extension e.'. Moreover, : , E !(£') and Zi doesn't change any more till the end of the sequence u, ' :;? oP+l f oP+2, where ei E (£'t is such that ei = Jt(ze ) = i· This is =ct for the cse i = z; because of condition 2) of the theorem and or the e i . z; s a consequence of the fact that the projection of the part of the �:ence u from . to oP coincides with the part of the sequence from : to ak . .. t3e

converse. Among all states, which are critical (strictly critical) to some !, and reachable from the state a in the circuit C, the closest ,::e to a will be chosen of such states for which & . J is in the extension � = (such a state exists because of Theorem 5.14). f the state 3 difers rom � :hrough all variables in (C')*, i.e. each e E (£')* changes in the sequence �g rom & to 3, then each variable in I(!') must change in this sequence. :ndition 1) is thus fulfilled. Let the variable Zj change in the sequence ' � � B, i.e. this sequence s & � ,.' J o . . �- The set of variables Zj , such �: If (Z .') = z, for ei E (£')* and the variable ei is excited in the state ,.• -llch means that Yi . 1;), will be marked by Z'. Since all variables in (£')* Le excited in the state 3, then Z' contains all variables in the set !(£') , which � not change in the sequence leading rom o l ' to 3. Moreover, for the case :: strict sensitivity a sequence & � 1.' 4 ul' J ol' � J, is found where � = difers rom 1!' through the values of those variables ei, which change .:. the sequence 5C! . 3. The variable z; is excited in J C ' , as otherwise not

- -:e �:

1(£1), ,' �

- 150 J but , e' J Z would be closest state, which is strictly critical to t. The e: Z' contains for this sequence on those variables in I(l'), which don't change in the sequence cl' > J. As If (!) = f; (l (Z � ) and as the projection c: & . IC ! ; cC ' . J to Z looks like a . I h 8 . 3, then /;(I) = f;("f ( Z , and the condition 2) is satisfied. Circuit analysis methods on sensitivity (strict sensitivity) to an arbitrary wire e: , can be suggested on the bsis of the Theorems 5.14 and 5.15. At the irst stage states which are critical (strictly critical) to , are treated. At the second stage the backward reachability problem is solved either for the extension e. of the circuit C (corresponding to Theorem 5.14) or for the circuit G itself. Here we verify the fulfilment of the conditions of Theorem 5.15. The ollowing statements give treatment methods of critical (strictly critical) states in a circuit C. Let , be the wire Bet from the output variahle z; (O(,) = {z;}). The set of states, which are critical for z; to I(l) is given by the function

Statement 5.7

S i (Z ) (z; i f;(Z)). SJ(, ) ·

Statement 5 . 8

_

The set of states, which are strictly critical for z; to I(C)

{ z;}) is given by the function

f Z1

f Jc-· i w 1· (Z)) y S/ SI1,lcv t.El( C) 8/;(Z(/(L))) lk(Z)( Vt.El(tj)\I (C) z. 8t, •

(O (C)

=

8/;(Z(I(.))) y 8t. (

Zk

)

fk Z ) ) ) ,

where I(z;) is the Bet of variables on which the function f;(Z) essentially depends.

It should be pointed out that states, which are strictly critical for z; to I(C), may also be revealed, if states I-conflicting with respect to Zj are ound in the extension cc and then the projection of these states on the variable set Z is taken. 5.8

Circuits Insensitive t o Wire Delays

Here the interdependency between the sensitivity of the circuit to wire delays and the characteristics of the boolean functions, which can be derived rom the circuit will be established. :i+ 1) is stationary on the variable i , if The state sequence a1 a2 a" (ai . . . s (ci) . af and /i(t1) a� = :i = . . •

.

=

.

•

t

=

=

There are four possible variants of stationarity on the variable zi :

- 151 ·

=

- ·

= =

:·

=

,', (ze) 0 and ... (ae) 1 represent stationarity on a stable variable, : . a(:e) 1 and l . i( .e) 0 represent stationarity on an excited variable. =

=

=

=

1 in the first cse, f/ (!e) = 1 in the second case, f° (ae) = 1 in and l (a) = l in the fourth case, where l : e � k, and as earlier . = 0), fl = i (Zi = 1). The functions P, ff, fP, l are called the :; ·-:ctions of the variable Zi for stationary sequences of the corresponding -over, J' , l are triggering functions and P, !l are blocking functions �.>!e i ·

; t�)

-: .e,

=

r:a:ionary sequence on the variable i the corresponding deining unction _:e "1" . This means that there is at lest one term of sum-of-products � function which has the value " 1" , but diferent terms of the sum-of­ l:� :=:m of the defining function may have the value "1" in diferent states of 2 ;:y sequence. In the state sequence a 1 a . . . ak, which is stationary on the � ; occurs an intercept of terms, if all terms of the reduced sum-of-products · ..= deining function of the given sequence having the value "1" in the state � �he value "O" in the state ak. Such an intercept is called an intercept for -.:�e s on the set Z' of variables, which change in the given sequence, if for :.. :: : 1 among the terms containing z; in the reduced sum-of-products form .t�-ing function is ound a term Ti, for which T1(!k) = l and no term for •

·

·

-: :t? )

=

1.

in which an intercept of terms for the variable Z& on the state set Z' ;.:.rn this circuit is strictly sensitive to the wire set l relative to the state a,

'!l 5.16 If from the state a in a circuit the irst state of a sequence is _ "" , ., �!

;

:)

.et

=

{zi}, l(l)

=

Z'.

a 1 a2 . . . am b e a stationary sequence o n

z;,

in which the intercept � .n Z' occurs s specified in the theorem. Moreover, such an intercept • xeur in any shorter sequence a1 . . . .e, e < m. This means that there is � - of the reduced sum-of-products form of the deining function such that = . . . = T(am-l) = 1 and T(am) = 0. In the extension e., where the wire : i:!s5es the conditions of the theorem, a state &1 . . . am is constructed, which � from a1 . . . am in the following way: if .i .1 :'+ 1, then a' .} a" is added . quence being constructed, and, if Zj E Z', and Zj changes in the sequence a-n, then a" J a"' is added, where e; E ! and ei = fe� (z . ) = Zj . It is een that the projection of the constructed sequence coincides with a1 . . . a"i != om) f fi (am), as all those deining function terms being equal to "I" in - ":e am are equal to "0" in am. This means, however' that if the variable Zj :e in the state am of a circuit C , then it is excited in the state am of the

- 152 extension e., and, the other way round, if Zi is excited in

am, then Zi is stable:.

'c. with respect to (a,&) isn't true, and, in the second� a. C is consequently strictly ser� to , with respect to a. am. n the first case C

e.

isn't semimodul ar on Zi with respect to

Corolary 5.6

If from the state a in a circuit the irst state in a sequence is rea­ able, in which an intercept for i on z; occurs, and, moreover, z; belongs to all te::L being equal to «1" in the foal state ak of the sequence, then this circuit is stri4 sensitive to the wire j, i) with respect to a.

The functioning of some asynchronous logical circuits doesn't depend on the is

delay values. To the number of circuits belongs, or instance, the trivial subclss.

semimodular circuits, in which there is no branching of wires. Besides, if a c::.

C is semimodular with respect to the state

a

(i,j). Generally

j(Z) essent� C is strictly insensitive to the ".

and the function

depends on only one variable Zi, then the circuit

speaking, this s also correct for circuits, in which each excite:

function of the variable z; essentially depends on only one variable, or inst.

z;

z;i V z;zk. n this cse the circuit is strictly insensitive to the wires

(k, j). =

(i,j) ,

Still, this class of asynchronous logical circuits is also comparatively nr.

particularly it doesn't even cover the clss of sequential circuits.

Exmple

5. 7 The circuit presented in Fig. 5.eo and consisting of a pair of . .lip-lops is sequential with respect to any state except states, in which hoth bras of any lip-lop are reset to ao". This circuit is insensitive to the set of all � interconnecting the lip-lops with each others. At the same time, it is sensr to the wires in the backward communication of the lip-lops. The structun this circuit is characteristic for lip-lop circuits of the «master-slave" type and :o reported analysis results are valid for all such circuits.

The parallel-sequential circuit in Fig. 5.9 has 5 wires: (a, c), b, c), (c, a), (c,! (c, c). The circuit is strictly insensitive to all these wires except the last one. : structure of this circuit is typical for parallel-sequential interconnection of ser.­ ular circuits. This also makes it possible to generalize the results of the analy_

5.9

Reduction of the Complexity of the Solutions to Analy� Problems

The element functions

fi(Z) of a circuit do not in many important practical c£

essentially depend on all circuit variables, and in particular, these functions are _

independent. n this there is a possibility to reduce the complexity of the solutiosf

analysis problems by reducing the size of these tsks. The complexity of solutioS -

reachability analysis problems grows exponentially with a growing number of :;

variables. In the worst cse, the number of iterations in solutions to reacha;!

- 153 �s s well s the costs to execute each iteration step depend exponentially on ..e circuit size. Therefore, or a circuit with a great number of variables it is more �:oitable to transorm the solving of one large analysis problem into the solving of e-eral smaller problems. A method or such a transormation will be considered . : he following . ... �eduction of the circuit C = (Z, F) on a self-independent variable :arked by Cz; = (Z \ {;}, FzJ , where Fz; is the system z;

=

Zi

will be

f; ( zi, ..., z,_., i(Z), Zs+i, . .. , zn ) , j = 1 , ... , i - 1, i + 1, ... , n,

::, - 1 Boolean equations. following theorem establishes a relation between the states with respect to -.ich the circuits C and Cz; are semimodular. -:e

heorem 5.17 Let a circuit C

= (Z, F) be semimodular with respect to the state E {O, 1} and i = 1 , . .. , n. Then the circuit Cz; is �.,imodular with respect to the state az; = a1 ...:i-1ai+l . . . an.

�

=

a1

.. . :i . . . :n1 where

a,

?:oof. The correctness of the given theorem immediately follows from an accepted ::>thesis about circuit element delays. The behaviour of a semimodular circuit �.esn't depend on the sizes of the delays of the elements constituting the circuit, :.i the circuit Oz; is equivalent to a circuit C having a zero delay in the element xample 5.8 Jn Fig. 5.21,a is shown

.!•connected inverters z1, :-1able z2 is shown.

1

z2, Z3.

circuit consisting of three sequentially in­ In Fig. 5.21,b the reduction of this circuit on the a

observe that if the circuit C is non-semimodulr with respect to the state a, the reduction on the variable z; can be semimodular with respect to the state t,. This is seen in the example for the states o = o•o•o• and :z; = O*O (the circuit = Fig. 5.21). The reduction of the circuit on a variable thus doesn't represent ,y equivalent circuit transormation or states relative to which the circuit is non­ e:nimodular. Xext,

..en

Each state of the circuit Cz; covers two states of the circuit C because of the smaller �e of Cz;. The following corollary of Theorem 5.17 is valid, since a circuit reduction �esn't create new conflict states. Corollay 5. 7 Let p and Pz; be characteristic functions of the state sets, with �spect to which C and Cz, respectively are non-semimodular. Then p(:) 2 p(:zJ � valid for any state !.

- 1 54 -

�

1

,

F : pl 11 z1

.

3

2

I t l)

o•o ----10•

( b) Pi;.

5.21

c

z, !

2

l)

=

=

=

l) z,

22

- 155 :-he successive reduction procedure of the circuit

.� �

Z

1. Let

2.

C = (Z) F}

on the variable set

will be considered.

c0 :=C) .M0 := M, k := 0.

From the set

.M k

any self-independent variable Zi is chosen. If no such vari­

able is found) then the procedure hs terminated. Otherwise the procedure

3. 1 Mk + := .M k \ {z1}, c k +t := C!, k := k + 1

continues rom step

3.

Let

•

and g o to step

2.

k, isn't necessarily equal to the .M contains only self-independent variables,

:: should be observed that the number ofreductions, rdinality of the set

.M.

Even if the set

�:ill a part of them may in the reduction process be self-dependent for some circuit c�, where e=

1, ... , k

and

k

< n.

Furthermore, a situation is possible such that

wme variable z,, which is self-dependent in the circuit ce, can be self-independent i the circuit

ce+l, where = o, . . ' k- 1 e

.

and

k

< n.

CM. = (ZM, FM), where ZM and FM are deined with the aid of the .iccessive reduction procedure CM= Ck , ZM = (Z \ M) U .M k , FM. = F k , will be :ailed the reduction of a circuit C = (Z,F) on the variable set .M � Z. The circuit

5.22 a counter flip-flop in a circuit : = { z1,zz,z3,z4,z1,z6)z1} is shown.

:i Fig.

\Ye have already seen that if a circuit �!ate

r,

C

reduction example on the variable set

is non-semimodular with respect to the

then its reduction on the variable Zi may be semimodular with respect to

Oz;· In F ig.

5.23

a circuit and its reduction on the variable set

�iven. The initial circuit �he circuit

C2

.Hates. In Fig.

C

Z = {z1,z2,z3}

is

is non-semimodular with respect to all its states, but

is - the other way round - semimodular with respect to all its

5.24

the reduction of the same circuit on the same variable set is

?resented, but the variables were chosen in . diferent way during the reduction

process. It is seen that the result of the reduction on the variable set depwends on

:he order of selecting variables from this set. The circuit in Fig.

5.24

:be initial circuit - non-semimodular with respect to all its states.

is also

-

s

The use of circuit reduction on variables makes it possible to decrease the solution complexity of problems in the complete analysis. The characteristic functions for the sets of conflict states and states with respect to which . circuit is non-semimodular

are indicated by J and P respectively.

5.17

Then

-

s a result of the corollary to

the chararteristic function Pz; of the state set with respect to which the circuit C z; is non-semimodular, deines a part of - or even all - the

Theorem

-

states, with respect to which the circuit

C

is non-semimodular. The function Pz;

is, however, more easily computed due to the smaller size of the circuit Oz;. The already computed unction Pz; can then be used or the computation of the function p in the transition rom the circuit

Oz; to the circuit

C.

For this it is necessary

- 156 --

z1=z2vz6

z 2==lv�7 z

3==1 v=6

2 =z vz? 4 2 z5=z3vz4

z6= �3v=5v �J 7.7=z vz5vz i 6 :

-- _J I //\, - - t_ I

r

L_

z2=z2z§vz1 .

..

j

z2:z2z vz7 6 zJ=z2vz.7

=:.. v z �

�

Z4=�2v

0

=7 zs= ::vz.

z5=z2z6vzh

z/=z .VZ.VZ., _: _) _, 0

.7=:. v.5v.6

z2=:2.6Vl( . z6=:2.6vz)v z7 6 z6=z.2z7vz5vz

c ·'··'

=

c :.

" � ')

Fig.

5.22

- 157 -

l

,,2

·_.

5

23

=... .

�· i g'

i-

,,,.., "

{ -

�l

.

zi = z �

)

--

J Fig.

5.24

j

--

0'

1 *

----

- 158 to solve the backward reachability problem starting - not from states deine w the function ;, but - rom states defined by the function J V Pz;· In the � context a reduction of the number of iterations in solving the backward reacha::s problem or the circuit C is achieved. A still greater decrese of the solution complexity of complete analysis ts! • achieved by using circuit reduction on a variable set. Let ce, e = O, . . . , k, k < , be an ordered group of circuits with diminishing sizes. The analysis procedure �

1. Let

e :=

k, pe+l

:=

0.

2. pe is computed for the circuit ce by solving the backward reachability prob!� or states defined by the function pe V pe+1. 3. e := e - 1 is computed. f e < O, then the procedure has terminated p = po. Otherwise the procedure continues from step 2.

�

The necessity to do computations with functions, which essentially depends on circuit variables, remains in this procedure.

L

Conditions making it possible to get rid of this drawback are defined. An element t of an arbitrary circuit is selected (Fig. 5.25). The circuit state from which conlicting states with respect to Zi are unreachable, is named (,.

et

is split up into the our subsets ;0, ;1, .0, and .1 according to the ollowin� definition. Let a= a1 ti an be some state in I,. Then

I,

•

.

.

• • •

a E i0, if � = 0 a E i1, if ai = 1 a E �0, if a,= 0 a E �1 , if i = 1

and and and and

/;(Z) = 1, /;(Z) = 1, /,(Z) = O, /1(Z) = 0.

The variable Zi is excited n states belonging to the sets ;0, .1 and stable in states belonging to the sets ; 1, �o. Besides, states in the set ;0 (; 1) .re not reachable from states in the set ; 0 ( .1) because of the deinition of Ii. The intersection n1s•sn I, evidently defines the state set with respect to which a circuit is semimodular. The subcircuit A of the circuit in Fig. 5.25 can in some case be reduced on some variable set, when Hi is computed. The sequential interconnection of two semimodular circuits A and B presented in Fig. 5.26,. is fundamental or a bsic sequential interconnection circuit. From the theorem about the interconnection of semimodular circuits ollows that the circuit in Fig. 5.26,a can be transormed into the two circuits in Fig. 5.26,b. This is in no way relected in the behaviour of the circuits A and B.

- 159 -

Fig.

5.25

'-0J'

_L

lJ I

1 1

B

'A

(a)

lJ ,_6�DJ

, -_--

I _�A

�I

{b)

?ig.

5.26

I A

ZA

-1

J

r

(a)

(b) Fig.

5

-

·---

27

z

-BJ'� I

1

P,

- 160Consequently, when the set �i is deined, where i corresponds to Zi and Zi � to the circuit A ( B) , then the initial circuit can be reduced on the variable e• .:· circuit B (A). In Fig. 5.27 a parallel interconnection of two semimodular c-11 A and B, for which the same conclusion is valid, is shown. However, the question about the conditions, which in the general cse sho.:: . deined in order to permit a reduction of the subcircuit A in circuits of the � shown in Fig. 5.25 during the search of the set H,, remains open. It seems that one of such conditions is the possibility to make an equivalent r� formation of an initial circuit either into a circuit, which is a basic sequenti: r parallel interconnection of semimodular circuits, or into a circuit, which is a c.­ bined interconnection of these simple bsic circuits.

5.10

Asynchronous Circuit Analysis by Petri Nets

Analysis methods based on direct use of the Muller model of circuits have be: worked out in earlier sections of the present chapter. The use of such a "loc:· representation for the description of circuit operation has made it possible to obta.:. eicient analysis algorithms. However, the direct utilization of Muller model (if . transition diagram isn't constructed) represents circuit operation dynamics in : indirect way. One of the most widely used formal instruments for parallel system research is the Petri net formalism, which has been examined in Section 2.2. Petri nets clearly relect the dynamics of circuit operation and give a local knowledge of the dynam­ ics. This means that Petri nets s well as Muller models establish local relations between system components, and, the global system behaviour is seen through local interactions between these components. this section a new Petri net clss will be introduced, which is adequate to Muller model. This class is especially meant or circuit analysis. It relects clearly the dynamics of circuit operation and is free from some shortcomings ssociated with Petri net classes examined in Section 2.2. n

The idea to represent a circuit element by a subnet is the bsis of the proposed approach. f

P' is a subset of the conditions in a net N (P'

P) and T* a subset of the Up;EP' O(p,), I(i*) Ut;ET" I (t,), ;;

events in N then I(P') = Up;EP' I(p,), O(P') = = and O(T*) = Ut;ET" O(t,). For each wire we deine a subset of conditions with a cardinality equal to the number of wire states. Such a representation makes it

- 161possible to extend the universality of the model s well s to reduce the model complexity because of the compact circuit element representation. A

subnet N' of the Petri net N

=

(P, T, Mo, H, F) is a quintuple

N' = (P', T',M�,H',F'), such that P' is an arbitrary subset of P, T' = I(P')uO(P'), F': P' x T'--+ {O, 1}, H': T' x P'-+ {O, I}, and Mo : P'-+ {O, 1, ...}. The subnet N m - (Pm , Tm ' Mm 0 ' Hm , Fm) of the net N ' where m = {p·} . ) T" {t;}, Mft = Mo(pi), Hm = H(pi, t;), and Fm = F(t;,Pi), will be called a minimal loop. Moreover, Hm = Fm = 1. �

A minimal loop in a net N will be represented by a bidirectional arc between the place Pi and the transition t;.

It should be noted that in a minimal loop the event t; cannot occur for M(pi) and, on the other hand, the occurrence of t; will not change M(pi )· For n arbitrary subnet N' we denote: C(P') and V(P') = O(P') \ C(P') output events.

=

=

0,

I(P') n O(P') are internal events

a Petri net a condition corresponds to a circuit variable Zi and events correspond the switching transitions of elements. n event s corresponding to the element :ransition 0 + 1 is an input event for the condition ; (and also or the corresponding state Zi = 1) and an output event or the condition Zi (and for the corresponding state Zi = 0). An event r corresponding to the element transition 1 + 0 is an input event for the condition Zi and an output event for the condition Zi. n

w

The output behaviour of an element can thus be modelled by a subnet of the type shown in Fig. 5.28. This subnet is called the characteristic cycle of an element. The characteristic function of an element can be presented in the Shannon orm Zi = l V Szi. The transition 0-+ 1 corresponds to S = 1 and the transition 1-+ 0 to R = l . The Petri net arcs reflecting the links of the inputs of an element with outputs of other elements must enter minimal loops, since the switching in an element transmits no direct influence to the external element inputs. s

A conjunctive decomposition of

Sand R will be utilized. Then the modelling circuit of the Petri net must have auxiliary conditions corresponding to the disjunctive terms of functions. Such conditions will for the function S be input conditions or r-type events and exit conditions for s-type events. For the function R it is the other way round. A net modelling the operation of any switching circuit can be constructed analogously to the construction of the characteristic cycle of an

·-------

-

- 162 -

Fig. ).22

1

&

1

(al

(b) Fig. 5.29

- 163 element since element inputs are either outputs from other elements or external circuit inputs, and each element input can be represented by a subnet of a Petri net. In Fig. 5.29,a n example of a switching circuit is given, which is modelled by the Petri net in Fig. 5.29,b. The initial marking corresponds to the initial circuit state. It is easily seen that . one-to-one correspondence exists between the net and the circuit (or rather the Muller model of the circuit) . The described net can be classified s a special Petri net class. Such nets are provided with structural peculiarities (each event is included in some characteristic element cycle and hereby all conditions, which are incidental to this event and not included in the characteristic cycle of the element, will form a minimal loop with the event). These nets will be called Circuit Petri nets (CPN). Circuit Petri nets corresponding to conjunctive representations of characteristic functions and elements will be called Conjunctive Circuit Petri nets (CCPN}. Such a net contains 2n events or a circuit of n elements. Two subsets can be distinguished in the set P : •

•

P1 is the subset of characteristic conditions included in some of the character­ istic element cycles, I Pd = 2n, and

P2 is the subset of conditions corresponding to disjunctive terms of character­ istic element functions, IP2/ � :i=t t, where t is the number of terms in the unctions S and R of the element z,.

By utilizing a disjunctive decomposition of the functions S and R we can construct disjunctive Circuit Petri nets. The properties of these nets .re analogous to those of conjunctive circuits of Petri nets. Here we will restrict ourselves to examine properties of Conjunctive Circuit Petri nets. Each marking of a Circuit Petri net corresponds to some state of the modelled circuit. The set RN of all markings reachable rom Mo is thereore bounded; IRN I < zn, where n is the number of variables in the circuit.

Let there be a Conjunctive Circuit Petri net in wMch Pr E P, ti E O(pr)1 lj E V'(Pr), V'(Pr) � V(pr) and M(pr } is some marking for which the integer e = M(pr) exists. Then Mis a conlicting marking, if all events in V'(Pr) and the event ti are possible and IV'(Pr)I � e except this. Theorem 5,18

The proof of the theorem directly follows from the definition of conflicting markings and the set V (P). The idea of Theorem 5.18 is the following. A marking M is conflicting, if after the occurrence of some events (T ) enabled in Mthere is "not *

- 164 enough" tokens in the marking M' (M .; M') or the condition Pr to implemen� events possible for M'. If there are "enough" tokens, then M is not conflicting. Theorem 5.19 Let a marking M of a Circuit Petri net N correspond to t.e state a

of a circuit C. The circuit is semimodular with respect to the state a, if no marcin� M' reachable from M in N is conlicting. This property immediately follows rom a comparison of the deinitions of persis­ tence in Petri nets and semimodularity of circuits. An algorithm for searching a cover or the set of all conflicting markings in a Circuit Petri net is bsed on Theorem 5.18, rom which originates the existence of an algorithm for searching a cover for the subset of circuit states, with respect to which the circuit is non-semimodular. The first part of this algorithm consists of a search for conlicting net markings and the second part of a search for markings, from which conflicting markings .re reachable. Analogously it can be shown that all analysis algorithms examined in preceding sections of this chapter can be reformulated with reference to the analysis of Circuit Petri nets (CPN). This, however, also follows from the one-to-one correspondence between CPN and the Muller model. It should be noted that circuit analysis with the aid of Circuit Petri nets thus reductibly comes to solving the well-known reachability problem of Petri nets (con­ sidering the facts concerning their boundedness). This analysis method, however, favourably difers rom the well-known analysis methods, which utilize a local prop­ erty (conflict in a marking) or the determination of the set of conflicting circuit states and also a Petri net circuit description with considerably less complexity. Circuit Petri nets have some here not introduced interesting properties, which, in particular, make it possible to analyse deadlock and liveness properties in circuits. Liveness means the ability of all circuit elements to switch an unlimited number of times for cyclic circuit operation. The use of a popular parallel process model such as Petri net or circuit analysis not only clearly illustrates synchronocity and parallelism in the switching of circuit elements, but gives rise to application of the algorithms examined in the present chapter or the analysis of the correctness of synchronous parallel programs and processes. It is sometimes convenient to combine the proposed analysis methods with the indicatability verification methods, which are exposed in chapter 7. The topics treated in this chapter turn out to be ormal spects of the analysis of synchronous logical circuits. The results ormulated in ssertions 5.1-5.8 are fundamental or the design of circuit analysis algorithms. Such algorithms have

-165een implemented by the authors in LISP or BESM-6 computers and in P-1 or computers.

S

- 1666

ANOMALOUS BEHAVIOUR OF LOGICAL Cll­ CUITS AND THE ARBITRATION PROBLE�t

The evolution of the architecture of computer and control systems s we: � increase in their functional speed have brought about the necessity to solve p.concerning timing agreement ssociated with iteration between system := and problems concerning common resource sharing. The first referencs :: diiculties, which arise in solving the above mentioned problems, were no: :�"= the middle of the sixties. These diiculties can be illustrated by processs . asynchronous device, whose input receives an asynchronous signal ( Fig. 6.1 7r device consists of a D-lip-flop T, whose straight and inverted outputs are Q ': Q respectively, and an .�D-element, whose output is connected to the input ; the flip-lop T. The input gate of the device receives an external asynchronous sequence X �= � sequence C of internal synchronization impulses. At the output of this gate =�� may appear short impulses (Fig. 6.1,b) . The energy of such impulses may suic:r .= start a transition process in the flip-flop of the device but may not suice to ch.! the state of the flip-lop. n arbitration phenomenon arises inside the lip-lop 11 a result of this. The flip-flop may enter a state of unstable balance (metst�: state) , in which the output values coincide on a level representing neither a log:.. 0 nor a logical 1. Devices, which asynchronously agree on signal sequences enter.::! the inputs, are called synchronizers, and the described behaviour of these dev?::� is called anomalous. Later, it was discovered that anomalous behaviour also is characteristic of arbite� which are devices granting a common resource to exactly one of the processes ski..! or this resource. An arbitration problem arices independently of the nature oft::� processes and the common resource. Even if the arbiters are programmed, ::� problem still comes down in the very end to the construction of a hardware arbiter which functions correctly. A generally accepted structure of the signals to and fro:: a k-input arbiter (Fig. 6.2 ) consists of •

• • •

the request signal ai, . .., ak to the arbiter for the common resource R fro: the processes Pl, ... , Pk, the acknowledge signal bi, , be from the arbiter to requests from pi, . . . , p:, the request signal ao for the resource from the arbiter, the acknowledge signal bo rom the resource to the arbiter. . . •

There are four well-known types of anomaly in the behaviour of circuits, which implement arbitration and synchronization: •

the already mentioned metastability anomaly ( Fig. 6.3,a ) ,

- 167 -

:=tJ-tfJ - : (a)

I c

I

I !

I

\

x c

a 0

-I �--u---.----­ - - - - - -/ --�" - ..

(b)

Fig.

6.1

-

-

-

-

- 168 -

a,

.

.

.

b

1

AK

QK b

Oo b

o

K ') fiv. ., -' . ...

[a)

(b I

b,

b? ( c)

�----(d)

Fig.

6.3

- 169 •

• •

oscillatory anomaly ( Fig. 6.3,b) , which is a phase-locked oscillatory change of the signals in both output. The signal values coincide at each moment of time in this change. unstable transition process (Fig. 6.3,c) ,

dragging in one of the edges during a transition process (Fig. 6.3,d ) .

.\ .:iomalous behaviour may arise in the handling of a short impulse to one of the ::puts of an arbiter or a synchronizer, especially when the amplitude of such an ..?pulse only slightly exceeds the operation threshold of an element. Anomalous �baviour may also arise in cases, when requests or a common resource arrive rom =$erent processes in a time shorter than the execution time of transition processes i an arbiter. The possibility that anomalies of the two last types arise, depends : i the device structure and their avoidance is not very complicated. On the other :and, anomalies of the two irst types have a fundamental character, and searching :ie ways to .void them encounters the greatest of diiculties.

=xperiments show that the behaviour of arbiters and synchronizers implemented .-ith binary logical elements is an essential source of faults in computer and control systems. Theoretical foundations of anomalous behaviour and methods to design :orrectly functioning arbiters will be presented below. Such a presentation is of current interest, as there is . great number of incorrectly implemented arbiters and synchronizers in the design practice of today. 6.1

Arbitration Circuits

Beore the formal deinition of arbitration circuits we introduce a number of auxil­ iary deinitions, which supplement the deinitions of the preceding chapters . ..n asynchronous logical circuit C is a triple (Z, Zo, F), where Z = {z1, ... , z0} is the set of binary variables, Zo c Z is the set of input variables, F is a system of Boolean equations of the type Zi = /;(z1, . . . , Zn ) , and z; E Z \ Zo.

A vector I consisting of the values of the variables in Z' c Z is called a circuit substate. A substate with the dimension e corresponds to a subcube consisting of 2n-e states. A subst.te f will be called stable (with respect to ixed value of input variables ) , if the variables z; E Z1 (zi E Z1 n (Z \ Zo)) are stable in all states corresponding to it. s the behaviour of arbiters will be investigated for ixed values of input request signal, then it is suicient to consider the cases where the input variables .re stable in all the states.

The set of all states reachable from the state a is markel by R( a) and the set of all states immediately reachable from a is marked by T(:). It should be remembered

- 17 0 -

that a state set D = { a1, ... , an} is called a closed class, if R( :i ) = ). The set of closed clsses reachable from a is marked by E(a).

:i E

)

for each

The projection of the state set B = { :1, ..., am} on Z' (8 I Z') is defined, and equally are defined the state projections :1 I Z', if a1 I Z' = . . . = am I Z'. 8 I Z' is undeined in the opposite cse. For brevity, only variables in Z', which have value 1 in a projection state (a set of projection states) , will be written out. The states themselves will be given not by binary vectors but by product terms corresponding to them. For instance, if Z' = {z1, z2}, then z1z2z3Z4 I Z' = z2 and z1z2z3z4 I Z' = o. The circuit C1 covers the circuit C2 of the same dimension, if each arc, which is found in the transition diagram (TD) of C2, is also ound in the TD of C1. It should be pointed out that the utilized model of an synchronous logical circuit is based on the same principles, on which also the hypotheses in Chapter 5 about its physical realization are based.

= (Z, Z0, A, 8, F) 1 where I = { a1,. .. , ae} C Z0 is the set of input request variables and B = { b1, ... , b:} C Z is the set of output acknowledgement variables is called an arbitration circuit of the range k (Ae circuit), if it satisies the conditions

Deinition 6.1 A circuit Ae

1.

acknowledgement set condition: if the state a is such that a I I = ail . ..�e, e . k, then a) for any closed class D E

E{o),

DI B = bh holds, where i S

b) any complete directed path from a leads to

a

closed class;

2. acknowledgement reset condition: if the state a is such that a I E(a) I b, = O; 9.

/

.

e, and

� =

0 then

acknowledgements stability condition: if the state a is such that a I ai = � and a I B =bi, then Y(a) I 8 = k

It should be pointed out that here Ae-circuits are not required to be free rom races with respect to the acknowledgement variables. This means that no restrictions are put on acknowledgement variables during the transition. It is also considered that a straightforward signal coding can be used and still no generality is lost. Moreover, since the interaction with processes is the source of anomalous behaviour of arbiters, only arbiter substructures, which are "responsible" or this interaction, are here interesting. Property 6.1 Any Ae-circuit (k

>

l) is also an At-1-circuit.

- 171 Property 6.2 Any Ak-circuit (k > 1) can be constructed using Ak-1 and �ircuits. -ie proof of case

k

2

=

is trivial.

Fig.

6.4

Az ­

presents a construction for the case

c > 2, for which it s easily shown that if Ak-1 and A2 satisfy the conditions

1-3 of

)einition 6.1, then also Ak satisies them. According to these characteristics it is :�ear that a necessary and suicient condition for the design of any A:-circuit is a ::esign of an A2-circuit.

6.2

Oscillatory Anomaly

Still some auxiliary concepts will be introduced, which make it possible to inves­ :igate the dependence of the internal eedback communications of elements on the momalous behaviour of arbitration circuits . .. variable Zi is

selfdependent, if

fs(zi, ..

.

, Zi

=

O, . . . , Z n

Otherwise it is non-selfdependent.

) - i(z,, . . . , Zi

=

1, . . ., Zn) ·

A circuit C is non-selfdependent, if each its

,-ariable is non-selfdependent. Otherwise C is selfdependent.

\ circuit variable t is (non)antitone-selfdependent, if it is selfdependent and t is

\non)antitonous with respect to z,. An asynchronous logical circuit 0 is antitone­

selfdependent, if all its selfdependent variables are antitone-selfdependent. Other­ wise C is non-antitone-selfdependent .

Property 6.3 A circuit 0 is non-selfdependent with respect to the variable z,J if for any pair of states : and cl 1 which are neighbours on Zi 1 either : E 1( :') or a' E 1(a) is true but never both together.

Property 6.4 A circuit is antitone-selfdependent with respect to the variable Zi, if for any pair of states : and ci, which are neighbours on Zi, a E 1(:') or ci E J(:) is true and both conditions are together true for one such pair. Deinition 6.2 It will be said that a circuit C has an oscillatory anomaly on the variable set Z', if there exists a state cycle :1a2 ...apa1a2 ... (ai E '(i-1), 1 S i $ p 1, a1 E t(ap)) such that for some :ia3, 1 S i, j $ p, the relation :i I Z' . :j I Z' is true. -

Theorem 6.1 No Ak-circuit belongs to the class of non-selfdependent or antitone­ selfdependent circuits.

- 172 -

r· I 01

• • •

- -- - - - - -

,·- -J -b_

----

I I

Q H�- -�

j

AK-1

�

,

-

-

1 --1-

n

• • •

,

�-1 b

;

•.

--- _1

OK--,--- �------· I L

-

- - ----,

--

-

- -· •• •

_

__

__

I �w

-- -- - -- - - - - - - - - - - J fig.

6.4

r--r I

IiI

f I

L_L _!

I

� --f

(a)

V L

'i g

6-5

/

I L

__

__

f

- 17 3 �:of. It is suicient to prove the theorem for A2-circuits because of Proper­ 6. 1 and 6.2, and because of the fact that a construction based on Property 6.2 ::serves non-selfdependency and antitone-selfdependency. Let A = {a1,a2} and Two cases are possible. - = { b1, b2}.

..s

For each state o such that a I A = a1, a2, Di l 8 = D; I B is true for arbitrary Di, D; E E(a). Let D; I 8 = b1 or clarity. Two states o = a1a2b1b23 and ci = a1a2b1b23, which are neighbours on b2, will be examined. Here 3 is the vector of values of other circuit variables. According to the Properties 6.3 and 6.4 either a E 1(0') or a' E 1(:) must be true. The first condition is, however, in contradiction with the stability condition of the acknowledgement in an Ak-circuit and the second one contradicts the initial assumption that Di \ B = b1 or the stability condition of the acknowledgement. Case I is thus contradictory. 2. There exists a state :, a I A = a1a2, such that there are two closed clsses D1,D2 E E (:) , for which D1 \ 8 = D2 I B. Let D1 \ B =bi and D2 I 8 =b2 for clarity. Let two state sets R1 and R2 be examined, or which Ri I A = R2 I A = a1a2, R1 1 8 = bi, and R2 I 8 = b2. Evidently D1 C Ri, D2 c R2, and R1 i R2= 0. R1 and R2 are also closed state sets (when a1 and a2 are fixed to 1) because of the stability condition of the acknowledgement. Let the our states :1 = a1a2b1b23, :2 = aia2hb23, a3 = aia2btb23, and :4 = a1a2b1b23 be examined. Evidently oi, a4 . R1, R2 and do not belong to any closed class in E(a1), either. :1 is a neighbour of :2 and a3, 04 of :2 and :3, and a1, a4t1(:2),1(03). Consequently, :2, :3E1(a1),1(:4) according to Properties 6.3 and 6.4. Then a1 E 1(a4), 04 E 1(a1), however. This is in contradiction with the acknowledgement set condition b ) . The theorem is proved. Corollay 6.1 Any non-selfdependent or antitone-selfdependent circuit, which cov­ !•s an A:·Circuit, has an oscillatory anomaly with respect to an acknowledgement l.

:uriable.

Corollary 6.1 follows immediately from case 2 in the proof of Theorem 6.1. In fact i104 is independently of 3 an oscillatory anomaly with respect to acknowledgement -ariable. a semiconductor gate is considered to be an element, then no element can be selfdependent. Nevertheless, the set of the gates situated on one chip having one _nverter-amplifier output signal can be considered s one element, whose delay is �educed to an output inverter. Such a model adequately describes the behaviour )f discrete elements and integrated microcircuits used in practice. Connecting the output of such an element to an input gives a circuit, which can be considered as antitone-selfdependent with a suicient degree of precision. It is, however, necessary to get a positive amplification coeicient in the loop in order to implement non­ antitone-selfdependent circuits. This can be achieved in two ways: f

-174 1.

there are no inverters in the loop, or

2. there is an even number of inverting cascades in the loop. In the irst case it is impossible to get any signal amplification in the loop. n the second case it is n incorrect supposition what the delay to the element is reduced to it output. n the analysis of the behaviour of such an element it s necessary to consider each inverting cascade as a separate element, and the element will consequently not be selfdependent. Thus, an arbiter can not be designed using binary logical circuitry s any such design will have an oscillatory anomaly with respect to the acknowledge variables.

Metastability Anomaly

6.3

A ternary function (T-function) is a mapping rom the n-old Cartesian product of the set of ternal elements {O, 0, 1} into this itself. The class of Boolean-ternary functions (BT) is deined s ternary functions, which preserve the set {O, l}. This means that a BT-function for any combination of O's and I's will have the value 0 of 1 but never 0. Examples of elementary ternary unctions are following: 1. O, 0, 1 are constants.

2. x Vy= max(x, y) is a generalized disjunction, 3.

x

4. x 5

·

=

a

·

y

=

1

x =

{

min(x, y) is

- x

a

generalized conjunction,

is a generalized negation (1

-

0 = 0)

l if X = a · · of a, where a = 0 , 0, 1. · · function = a is th e ch aractenst1c 0 if x

All introduced functions are BT-functions except the constant 0. corresponds to a triple (ZT, ZJ', FT), where zT = { z1, . . . ' Zn} is the set of ternary circuit variables, Zl c zT is the set of ternary input variables to the circuit, and FT is a system Zi = Fi(z1, . . . , Zn) , Zi E zT \ ZJ, of ternary equations, where Fi is T-function.

Deinition 6.3 A ternary circuit {TO}

cT

All earlier introduced concepts for asynchronous circuits can be generalized for a TC. A variable Zi E zT is metastable in a state a, if a I Zi = Fi( a) = 0. A substate 1 corresponding to values of variables in Z' c Z will be called metastable, if for all states given by 1, only variable ZiE Z' is metstable and the other variables in Z' are unexcited. The concept of a ternary transition diagram can be introduced for a TC in a similar manner as this hs been done or binary circuits.

- 175 �t the behaviour of a circuit element (variable) Zi be given by the Boolean equation ;

\

= fi( zi, . . . , zo), where the function ft is presented in the

AND-OR-NOT bsis.

i(zi, . . . , zn)

BT-function derived from the initial Boolean function

through a

;eneralization of the conjunction, disjunction and negation operations and through �

exchange of binary variables with ternary ones will be called the

. the function, which also will be denoted by

:

t(z1, . . . , zn)·

generalization

In order to derive

;eneralizations of Boolean functions presented in some other basis it is necessary > express each operation in this basis using ormulas in the AND-OR-NOT basis

id

the generalize operations and variables.

-�e behaviour of an element ; =

F; (z1, . . . , z0)

i(z,, . . . , Zn)

-. _ , VH, V0 � ) ',

.

•

"1"

t

will be given by the ternary equation

in a TC describing circuit operation during a transition process.

:-ie values of the T-functions �-nctions

(variable)

F;

depend on the values of the generalized element

as well s upon the signal states representing

0

and

1.

Let

indicate element threshold voltage values in switching rom the logical

and

0

levels respectively.

(

analysis of the input-output characteristics Fig.

6.5)

of logical elements shows

�at the ollowing dependency variations of the slope characteristics and the hys­ :eresis width are possible:

1. V0

VL $ Vn 2. VL ::;V0 $ VH 3. VL $ VH $ V0 4 . V0 $ Vn $ VL 5. VH $ V0 $ VL 6. Vn $ VL $ V0 and 7. the level V0 is not ixed ( "loats" ) , and in some instants V0 may satisfy diferent $

inequalities.

7ie cses correspond to four diferent T-function types, which are defined by the �rnary ormulas

(3 4)

FH(Z)

=

zp ;(Z) v 01:(z) v 0z; ,

zf t (z1 , . . . , zn) V 0/°(Z) V 0zf

zfJ, (Z) v zf If (Z) v 0/P(Z) v 0zf zf i(Z) = z;1 !f (Z) V 0/l{Z) V 0zf

(3 4)

- 176 It should be pointed out that if z; = f,(Z) = 0, then F, (z1, . . . , z1) = C . • ! � not excited in the state 0. This is due to the fact that the level 0 correpon� .:: ampliication coeicient of a logical element having the value 1 .

A TC given by the equations ; = F;, (z1, . . . , zn) , j E {1, 2 , 3, 4}, where in E­ the function type j) may ffer rom diferent variables Zi, hs following e. ties. If a variable Zi would be stable in a circuit state a then it is also stab!e .:. corresponding TC-state. A variable Zi, which is excited in the state a of the ... circuit, remains excited also in the corresponding TC-state. However, F1(a = in this context, as the switching of an element from 0 to 1 or rom 1 to 0 :: through 0 . If a variable Zi is non-selfdependent in the initial circuit, then . � gets excited with the value 0 after the start of a switching process, which co:� till Zi becomes 0 or 1. Finally, if ft (a) = 0 , then Zi may be excited or stable de>r� ing on the value of z; in this state and on the interrelations of the levels VL ,\·::� • This is defined by the type of the function Fi. The above given ternary functions Fli, F2i1F3,,F4; will be called normal exten.;w of the Boolean function i (Z) of the type 1 - 4, respectively.

Property 6.5 Let ;(Z) be a Boolean function and Fi(Z) its normal extensiv" ff

any type. Then

1 . if /i (:) = 0 and ci I zi f 1, then F;(:') � 0, where the ternary vector derived from a by changing some binary values to 0; £. S.

if t(a) = 1 and :' \ z; f 01 then F, (a') � 0;

{

a'

if f; (:) = 01 ft (3 ) = 1 and a I fi f 3 I z;, then F, (a I 3) = 0, where a I J a; ' if a; = 3; . . ( � . h dtgtt . h the i:t i) = a ternary vector whic aI J 0, if a; f 3;

f

u

·

Proof. Points 1. and 2. are proved by induction on the depth of the ormula give= for ; and point 3. ollows immediately from points 1 . and 2. Deinition 6.4 A TC cT is called a ternary representation of a circuit C, if \ZT\

=

\ ZL \ZJ'I = \ Zo\1 and each T-junction F; is a normal extension (of arbitrary type1 of the corresponding Boolean function ; . Deinition 6.5 A TC cT has a metastable anomaly on the variable set Z', .r

for some binary vector of the input variables there exists

a metastable (sub)statt which is reachable from some binary a, and if only one variable Zi E Z' s metastable.

7,

Theorem 6.2 Let C be a non-selfdependent or an antitone-selfdependent circuit

covering some Ak-circuit and satisfying the acknowledgement stabilit. condition (in Deinition 6.1). Then its ternary representation C has a metastable anomaly on the set of acknowledgement variables.

- 177 ?-oa.

It is suicient to prove the theorem or an A2-circuit.

the state a2 = a1a2b1b28 and :3 = a1a2b1b23 of the circuit C be examined, :ere J is an arbitrary vector of other circuit variable values.

_et

the acknowledgement stability condition is fulfilled, then /u (:2) = /b2 (:3) ::d /bi ( a3) = 62 ( :2 ) = 0 independently of the values in 3. s

=

1

ecause of Property 6.5,3.,

::dependently of the type of the extension and independently of the values of the iable in 3. The substate a1 = a2 = 1 , b1 = b2 = 0 is consequently metastable. It ..ould be shown that this substate is reachable rom binary states. This, however, .:mediately follows rom the proof of Theorem 6.1. .e. the states a1 = a1a2b1h8 and a4 = a1a2b1b23 be examined. The variables b1 i::d b2 are excited in :1 and a2. The substate a1a2btbt is consequently reachable .om a1 and a4 in the ternary representation. The theorem is proved. �-om this theorem it follows that any arbiter design bsed on binary logical circuitry s a metastable anomaly with respect to the acknowledgement variables. �ow we derive a property which gives us a method for the search of metastable sub)states. The excitation function for the variable

-iere

is defined by

i

Fi(Z) is the T-unction or the variable Zi in a TC. It is evident that

•

Zi

•

z;

•

z;

is metastable in the state a, if p:(a) = 0 and a I is stable in

:,

is excited in

if p;(:) = 0 and

:,

if p( :) = 1

:

I

Zi =

0 and

Zi

=

0,

Property 6.6 Let er be a TC and f be a (sub}state (corresponding to the values ;/ the variables n Z1 C Z) .

;'hen f is metastable, if Vz·FZ' . - Pi(i) .'unction for Zi in the (sub}state f·

=

O, where Pif) is the value of the excitement

Example 6.1 A very simple non-set/dependent implementation of a two-input ar­ hter (with inverted requests) can be given by the asynchronous logical circuit bi =

- 178 -

•(•a1 V b2), b2

= •(•a2 V v2). Its transition diagram fragment for a1 = a2 = 1 e a ; represent the existence of the oscillatory anomaly a1a2b1 b2 - a1a2b2b2 with respec: to the acknowledgement variables.

An analysis of the binary representation of this circuit shows that the state a1 = 1, b1 = b2 = 0 is metastable with respect to the acknowledgement variablu a2 and is reachable from the binary states a1a2b1b2 and a1a2b1b 2 independently of tht extension. =

6.4

Design of Correctly Operating Arbiters

For the design of correctly operating arbiters only elements, the behaviour of which cannot adequately be expressed with the aid of binary logic but can be described by BT-functions, should be utilized. There are two possible types of correctly operating arbiters: "limited" and "unlim­ ited" . Arbiters of the irst type have a limited acknowledgement time on process independently of the interarrival times of requests to arbiter inputs (these interar­ rival times may be arbitrarily short ) . More exactly, if at some moment of time one or several requests arrive to the inputs of a ready arbiter, then an acknowledge­ ment to one request will emerge from an arbiter output after a finite time limitd by some (linear) function of its own element delay values. A possible approach to the design of a limited arbiter is based on the exclusion of anomalies through the use of elements, which in initial modes do not behave like binary logical elements. Oscillatory anomalies can, however, not be excluded with this method, s they are independent of the character of the transition process. The exclusion of metastable anomalies is possible through the use of a rectangular hysteresis element (RHE). the function of which can be described by the BT-function f(Z) = x1 v x0z 1, where x is the input and z is the output variable of such an element. In Fig. 6.6,a an input cascade arbiter circuit with a RHE is presented. By means of methods describec in the preceding section we can prove that the metstable anomalies are absent in this circuit. The rise of oscillatory anomalies· is, however, possible in this circuit. Moreover there is a probability for the occurrence of a metastable state, s the design of an ideal RHE is impossible. An analysis of the transition characteristics of the circuit in Fig. 6.6,a using a Schmidt trigger instead of the RHE reveals the existence of a metstable state. Arbiters of the second type have an undefined time for the acknowledgement of si­ multaneous or nearly simultaneous requests. This means that the acknowledgement

- 179 -

-

a,

(a J

G

( b l

-

01

b'1

c -

Oz

b2

L

-

(c l Fig.

6.6

s

I

I

_ _,

&

B

�1

b2

- 180 -

time is not deined by element delay values in such an arbiter. The essence of the approach to the construction of an "unlimited" arbiter is •

•

locking the arbiter output signal during the time, when the circuit occupies anomalous state, and allowing these signals to change only after the circuit hs left .n anomalous mode.

The correctness of such arbiters is explained by objective physical statistical laws· circuits leave an anomalous state after a possibly long but inite time period with an upper limit. The locking can be carried out with the aid of inserted delays (see Fig. 6.6,b) .

It is, however, necessary to choose the value of these delays D tens or even hundreds of times longer than the value of a transition process in a circuit in order to secure a suiciently small probability of anomalous behaviour "leakage" to the acknowl­ edgement outputs bi and b2. This consequently makes the arbiter operation slowe: by a corresponding factor. It should also be pointed out that for the sake of correc! arbiter operation it is necessary to use G-fliplops (Muller C-elements) rather than AND-elements or the circuit outputs. Another locking method is bsed on the use of a threshold comparator, which is utilized as a termination indicator of anomalous arbiter behaviour. Such an indication is possible, because the arbiter output signals change in phase during an oscillatory anomaly (see Fig. 6.3,b) and, as also during a metastable anomaly. then these signals coincide with a defined accuracy at each moment of time. The comparator threshold value must be suiciently large in order to guarantee that a divergence of arbiter output signals exceeding the threshold value indicates a terminated withdrawal from an anomalous state. An input cscade circuit or sud: arbitration is presented in Fig. 6.6,c. It should be pointed out that a transition process is or such a solution - unlike the preceding solution - prolonged only under conditions of anomalous behaviour in the input liplop of the arbiter. The comparator 0 and the threshold elemen: are for clarity shown separately in Fig. 6.6,c. They can, however, be implemente s one single element. The solution shown in Fig. 6.6,c has a drawback in the see that the variable modelling the comparator behaviour is non-semimodular. Thi! means that short impulses may appear at the comparator output in case of reL (non-ideal) inertial comparator delay. These impulses may reach the circuit out­ puts b1 and b2. These impulses must necessarily be iltered in order to obtain & correct solution. A consequence of the described drawback is that a circuit is no: self-checking with respect to stuck-at-0 fault at the comparator output. The com­ parator stops executing locking functions if such a fault takes place, and anomalo! behaviour of the output signal bi, b2 will occur.

- 181 circuit, which can be transformed rom the circuit in Fig. 6.6,b by exchanging .e output gates with G-fliplops and connecting the output b1 (b2) to the input of .:e element b� (bD is, however, ree from the described drawback . \

.:biters with arbitrary input disciplines and multichannel arbiters can be derived :: the base of the described fundamental circuits.

6.5

"Limited" Arbiters and Safe Inertial Delays

::ere the complexity of a correct solution to the "limited" arbiter design problem J considered. It will also be discussed s to how this problem is related to the �:oblem of implementation of safe delays. :: is convenient to divide delay elements, in which the output signal is shifted �ative to the input signal, into pure (perfect) and inertial delays. A pure delay �erforms a time shift on an arbitrary input signal without any change in the form :: the signal. This means that the input signal f (t) is transformed to the output __ial f(t - D), where D s the delay value. A pure delay cannot be accurately �>roduced physically since each physical device cannot react on an input, which ! under its sensitivity threshold. The behaviour of a pure delay is approximately .odelled by a transmission line. -ie behaviour of an ideal inertial delay is illustrated in Fig. 6. 7. Signals with a :.ration less than D at the input Y are "not pssed" to the output y (they are -:tered) , but a signal with a duration exceeding D will appear at the output with a ..'le shift of the value D. n approximately ideal inertial delay can be implemented _sing RC-filters and a majority element M(see Fig. 6.8 ) .

:0r any, however small, € > 0 a signal with a duration D - f should be iltered and signal with a duration D + € should be passed to the output in an ideal inertial -:elay independently of the duration of the next signal, which also may be arbitrary :iall. However, such a model has no corresponding accurate physical realization :Cause of the described nature of a sensitivity threshold. In other words, every .::ertial delay has some "ambiguity zone" [D - £, D + £] . It is impossible to predict, :ow such a delay reacts on a signal with a duration within the limits of this zone. .

.:. Fig. 6.9 the well-known Friedman circuit is presented, which models the be­ :aviour of an ideal inertial delay with the aid of a pure delay D and a majority '.ement M with a zero delay. Input pulses ( 1-0-1, if y = 1 , and 0-1-0, if y = 0) -ith a duration less than D are iltered under the condition that the period between �1ccessive impulses is not less than D. The inluence of the input signal change dis­ ::pline has influence on the behaviour of an inertial delay. This is explained by the

- 182 -

L .1�

y

y

'

-Dj

I

�·:

,.

6.7

y

0

: :- 6.8

y

- d- D

y

- 183 -

(

-..:ia of physical elements. Some preparation time relaxation time

)

is necessary

.use of this inertia for a circuit just before another short pulse can be filtered .

=at hs been said makes it necessary to introduce another inertial delay model,

•:h will have almost ideal characteristics and take into account the existence of

. ambiguity zone and input disciplines.

�::owing parameters of inertial delays are introduced .

-:put

discipline.

Let a sequence of alternating binary signals with high and low

logical levels be brought to the input of an inertial delay.

It can be inter­

preted as a sequence of alternating positive and negative pulses

Ttr;-rtr3- . . . or r; r{ T; T; . . . , where Tt and Ti-

( Fig. 6.7) like

are d urations of positive and

negative respectively. n input discipline or inertial delays puts restrictions on the allowed interrelations of the durations of successive pulses. The input discipline thus puts the limitation "if circuit in Fig.

6.9.

Filtration thresholds.

Ti < D

D"

on the example

D� and D_ are called filtration T+ < D, and negative pulses of

The positive real numbers

thresholds, if positive pulses of duration duration

then THI >

T- < D_ are not

pssed to the delay output.

f not only a binary signal

Ti+l (Ti�l)

but also a signal

rf+ l

with some inter­

mediate amplitude may arrive to the delay input after the pulse

!

it is natural to consider that this signal is filtered if T +l

T/ (Ti- ) , then

< D,, ( rf+ l < D, ) .

No limitations are, however, needed in the handling of longer pulses with an

intermediate amplitude.

Dj, Df are called pssing thres­ + holds, if a positive pulse of duration r > Dj and a negative pulse of duration T- > DM .re passed to the delay output without distortion or with an allowed

Passing thresholds.

The positive real numbers

time distortion. A maximal possible relative

(e)

or absolute

(.)

distortion

allowed for the time behaviour of a signal may be given for the evaluation of

Ti transormed rl r, J < r; .

the time distortion. Thus, if an input pulse at a delay output, then The intervals

[D_, Dj]

I r:

-

and

T;

J < . or I

[D;, DM]

-

into the pulse

rl

£ •

are called ambiguity zones of positive

and negative pulses respectively.

Delay durations.

The delay duration

n+

and

n-

are the periods during which

the shift of an allowed positive and negative signal, respectively, occurs. Evi­

n+

D.

D,,, as a delay cannot "decide" whether to pass a pulse to the output until r+ � D_ or : D_ is defined in real-time. Consequently, a delay output change cannot start earlier than D, (or nJ

dently

�

and

n-

�

,-

after the corresponding input change.

It should be pointed out that the parameters

D_, D_, Dj, Df, n+, n-

the general case be functions of both time and the input sequences.

may in

- 184 Inertial delays have thus three types of time zones: and

passing zones.

iltration zones, ambiguity w :1

f a pulse sequence corresponding to some input discipline �­

pears at the input of an inertial delay, then pulses in a filtration zone are not p.. : to the output, but pulses in the pssing zone are transferred to the delay out;_­ with maintained durations (within a required accuracy.)

Deinition 6.6 An inertial delay will be called safe, if each pulse entering the d�:.1 input corresponding to some input discipline and having a duration within the lim, of an ambiguity zone (D, � r � Dc or D, � r � DM} is either iltered or pau�' to the delay output but without distortion (within a given accuracy). A

strongly distorted signal may arise at the output of an unsafe delay during r:�

generation of a pulse n the ambiguity zone at the input of the delay. Particular'.:

a short parasitic pulse may appear, which - s already has been said - may le:

to a fault and to an anomaly in the circuit behaviour. Let a circuit shown in Fig.

6.10 consisting of two similar cscades,

each of the::

consisting of a delay and an arbiter, be examined. The second request input anc the irst acknowledgement output of each arbiter are inverted. Only the first c­

knowledgement output is used in the circuit . For simplicity, it will be required tha: the delays and the arbiters are identical in both cscades.

D be a pure delay and A2 be an ideal non-inertial arbiter. Then it is clear tha: the circuit in Fig. 6.10 implements an ideal inertial delay, which ilters short pulss

Let

with a duration less than

D under the condition that the interval between successive

short pulses is longer than

D.

Pulses with a duration longer than

the output without distortion and with the delay short positive pulses pulses

( r+ < D)

2D.

D

are passed to

It should be pointed out that

are iltered by the irst cscade and short negative

( T- < D) by the second cscade.

Pulses, the duration of which is exactly

D,

may in a nondeterministic way be either iltered or pssed to the output with the delay

2D.

The introduced construction implements an inertial delay (but with other param­ eters) also in the case, when a safe inertial delay with the iltration thresholds

D_

=

D,

=

0 is used as the delay D and a

"limited" arbiter is used s A2 .

S.H. Unger and B.I. Strom have also shown that a "limited" arbiter can be designed by means of ideal inertial delays. design.

This fact is valid also a for safe inertial delay

The problems of limited arbiter design and safe inertial delay design are

thus equivalent in the sense that if one of these problems is solved, then also the other one can be solved.4 4The problem of "limited" synchonizer design - this is a synchronizer with an upper limit on the time of transition processes - also equivalent with the problems of "limited" arbiter design an. safe inertial delay design.

- 185 -

,-

-

I

81b1: : t

D

1 *

A,I

'

- 1

)

1

I�

L _�

I

I

L ---

1

r- - - - - -

I

� _ a ,_

I I I

,

1

rI

I

- - - - -

_

1

0

J

1

__

1

0

_ _

_

1

I

_

1

_

0

_

_

1

_

J

1 *

0

[ 1 1 · 1 * 1 0 ---- 1 0 0 * 1 * 0 - - - 1 0 * 0 * 0 0 * --- 1 0 * 0 � 0 1 --- 1 1 1 : · 1 *

(b) ; ig. 6. 1 1

.

I

- 186 Diiculties arising in connection with attempts to design considered in the concluding section.

a

"limited"

rbi::

The idea to design arbiters with a limited acknowledge time can be concluc. the following. It is necessary to indicate anomalous input cascade behaviour the use of special methods like in Fig. 6.6,c. In doing so, it is not suicie:� lock arbiter outputs during the whole time of the anomaly. It is also necs.�. to influence actively all arbiter inputs (locking on one of the requests ) in ore� � achieve a faster possible recovery rom the anomalous state. The circuit in Fig. 6.11,a is examined. It difers rom the circuit in Fig. 6 � only through the existence of an additional AND-OR-NOT element locking a request a2 and through the existence of two unsafe inertial delays at the arb�e outputs. Moreover, the request a2 is given to the arbiter in inverted orm (tho�p this inversion may be formed also inside the arbiter) . The transition diagrac i the introduced circuit contains two regions; the region of normal operation and � acknowledge variable race region. The latter in turn consists of an area of a st.: and a dynamic hazard5 or the variables bL b�, the duration of which is limited � the switching time of some circuit elements, and, of an area of a dynamical haz.: with an unlimited duration for the variable b�. The latter condition is explain� by the unpredictable duration of anomalous behaviour in the flip-lop (bi, b2). It ! possible that the flip-lop (bi, b2) leaves an anomalous state at the same mome:� of time as an indication of anomalous behaviour occurs, and the operation of tct second request starts under the influence of a eed back signal. The comparato: may catch this situation, and the second request will be revived. The flip-flop (b: b2) may enter another anomalous behaviour cycle and so on. A transition diagra:: fragment corresponding to the described operation is presented in Fig. 6.11,b (tht variable values are spatially arranged in states s the elements also are arranged n Fig. 6.11,a) . •

It is seen from this diagram that the existence of a feedback signal from the anomaly indicator output makes possible an inner "submotion" of the anomalous behaviour in the flip-flop (bi, b2) . The circuit can s a result of this enter a mode of oscillation with an undefined duration even for fixed inputs. A hazard with a limited duration can be fil tered, because an arbiter operates in "request-acknowledgement" mode. The existence of an unlimited hazard for b� however makes the circuit in Fig. 6.11,a incorrect. .

Anomalous diiculties also arise with another arbiter composition method, in which input registers for request storage and self-synchronization is used ( Fig. 6.12,a) . f two requests arrive to the inputs ai , a2 within a small time interval, then it is 5 A statical hazard is here considered to be the possible apper.nce of single pulse, . dynamic

hazard several successive pulses, at the element outputs

in the region of normal operation.

b�, b;.

The variables

b�, b;

are haz ard-free

- 187 �ible that the second one (let it be ai ) arrives to the input at the moment, when � arbiter inputs are being locked (cut of; c = 0) under the inluence of the irst ! (let it be a2 ) . The flip-lop (bL bi) may then enter an anomalous state under the :.:ence of a possible short negative pulse at the input. f a comparator indication x n anomalous state occurs at the moment, when the lip-lop moves from an cmalous state to the state ( 1 , 0), then a subcircuit ( Fig. 6. 12,b) may enter n .:lating mode ( Fig. 6.12,c) because of the feedback rom the comparator output. ' cynamical hazard with an unlimited duration may s a consequence arise at the r=!ter output b2. ::el arguments proving the impossibility of pushing a circuit out of an anomalous �:e have been presented. These practical arguments are conirmed by theoretical �Its. It can therefore be considered that the arbiter construction approach pre­ ::ed in Section 6.4 is the only possible approach to the design of arbiters with a ::rect operation independent of element delay values.

- 188 -

c

(a)

{bi

(c)

r:.g. 6 . 1 2

- 189 r

DIAGN O S TI C PROPERTIES OF APERIODIC CIR­ CUITS AND SELF-REPAIR

:. early stages of the development of the theory of aperiodic circuits it looked s .; :teir advantages over traditional circuits consisted of speed gains by means of - _-e 'ational organization of real element delays s well s of stabilization of circuit --Stabilities. By now has become clear that the most remarkable merits of aperiodic ::uits are their self-diagnostic properties. As a matter of fact, the possibility ·: Sx up the termination moments of transition processes simultaneously brings ·: solution diagnostic problems, i.e. detection of a set of circuit faults. Since an -eriodic circuit operates correctly for any inite elements delays, a circuit will never ��eh the state, in which the termination signal of a current transition process is .::ivated, if the delay of some involved element grows to ininity. The element delay rov.;th to infinity can in turn be interpreted s a defect in the element concerned. 1_ model of such a defect is a stuck-at-0 or -1 fault. This means that such a fault is :?:ected as a ixed "constant O" or "constant 1 " signal at the element output. :::cuits, in which faults belonging to some clsses are revealed in the operation ;-ocess, are called self-checking in technical diagnostics. The idea of self-checking s bsed on . partition of input and output signal sets (or states s will be seen -.:er) of circuits into classes. For such a partition correct and faulty circuits belong i diferent output signal state clsses (or states) as a response on one and the same :ss of input signal states. eif-checking circuits are usually provided with such structures (also self-checking), •nich can recognize what class an output set belongs to. Any fault of the given ::•pe in a circuit provided with such a built-in circuit check (or with some tester .:: a diferent way) is revealed at the circuit outputs. The following output coding ::ethod is generally accepted for circuits with built-in tester (outputs are usually :oubled for such circuits): normally the output signal 01 or 10 are ormed, but, .! faults belonging to a given class arise, then the signal 00 or 1 1 are formed. A 3Jawback of this coding is the rise of critical states for transitions 01 + 10 (10 + .1). During these transitions the sets 00 and 11 appear for a short time at outputs >f correctly operating circuits as faulty evidence about faults. This drawback can :.ardly be fully overcome in a traditional approach. The theory of self-checking circuits is well developed only for the clss of syn­ :honous circuits. The use of the term "totally self-checking" is, however, not fully Ccurate, since the faults of the synchronization mechanism can not be detected. Essential diiculties connected with the necessity to provide not only self-checking capabilities but also an absence of critical hazards or races in a circuit arise in the synthesis of asynchronous, totally self-checking circuits. Attempts to solve these

- 190 tasks separately result n cumbersome circuits. Aperiodic circuits, which are free rom a synchronization mechanism and e: · races, are - s will b e shown late - also totally self-checking.

Studying SL

-

tural properties of aperiodic circuits is thus important not only or itself anc c

circuit analysis but also from the point of view of solving the problem of funct:; a diagnostics.

7.1

Structural Peculiarities of Aperio dic Circuits and lndicat­ bility Properties

It is ssumed in designing aperiodic circuits that the environment communica::c with a circuit also is aperiodic.

A circuit together with its environment co�

tutes an autonomous circuit . It can consequently be designed and analyzed ��

corresponding methods.

(for example, consists of many devic!

Though many devices in practice can be isolated in system decomposition and t.­ real external environment is very complex

it is still not rational to examine such an external environment together with e�

device and it is not always convenient to use this method for the analys is o: a

device.

The eiciency of the methods worked out in Chapter 5 for analysing semimodularit! of aperiodic circuits is degraded, if devices with a large number of input terminu are the subject of the analysis. Typical representants of such devices are circui�

(

which are implemented with the aid of a structural canonical ) model of an aperioch: automation. In such unclosed

(or unautonomous)

devices the input terminals, t.

combinatorical part, the memory elements, and the output terminals can obvio�! be distinguished.

It is quite evident that the necessary conditions for correct operation of an uncloee aperiodic device also corresponds to the aperiodic behaviour of the external enn­ ronment. This condition is provided with a requirement to have only allowed inpm

)

transitions. This is a requirement to implement input vector change protocols

(­

quences , for which the completion moment of each next transmitted input vecto­ can be determined in a simple way responding to Deinition

3. 7).

(input vectors form self-synchronized codes cor­

It is such a mode of environment operation that !

needed "rom the point of view" of the device.

It is well-known that the necessity of a correct input vector change protocol is

a

property not only of aperiodic but also of synchronous circuits. The latter case s

(vector following each other must asynchronous circuits) . Just for aperiodic circuits

connected with the avoidance of critical hazards usually be direct neighbours in

- 1 91 :�s necessity is, however, recognized - not s a certain engineering trick but ,

a necessity of homogenity of the environment and the device; s their adequacy

.or each other. :he requirement to have only allowed input and output vector transitions for a 5ystem described by characteristic circuit functions will guarantee the absence of .:nctional hazards in these vectors, and is - as a matter of fact - a generalization

(

:: the functional hazard concept more correctly reeness from functional hazards

)

:::r the case of systems defined by characteristic functions of multiple output circuits.

2ircuits must, moreover, be free rom logical races. This requirement is connected

�th the accepted hypothesis about the character of the element and the delays of �e interconnection wires, and, also with the character of the characteristic element ::ictions as well as with the types of the transitions at element inputs. It is esy o

{

make sure that in a circuit, in which each element has an isotonous antitonous

)

iaracteristic function or the allowed input vector transitions, no logical races can J::Se, if a transition takes place at the inputs of each element. :ne basic goal of the structured approach to the analysis of aperiodic circuits con­ :sts of checking whether signals .bout the termination of transition processes are .:med for all circuit elements. The indicator output is in this context one of the

_:cuit outputs

(it may define

)

an output vector clss . It is natural to try to ind

:onditions, for which the termination of an allowed circuit output transition after t

allowed input transition will guarantee that the transition process has termi­

.ated in all circuit elements. f a circuit is divided into parts, then the fulfilment

:: such conditions or all circuit parts must indicate that the transition process has

:erminated in all circuit elements. :\

structural approach to aperiodic circuits is - according to what has been said

- the most natural approach in the synthesis of such circuits. Precisely such an pproach has actually been used in most earlier aperiodic circuit implementations. 7he concept of indicatability hs a central role in the formal evaluation of structural :.aracteristics in aperiodic circuits. This concept is an abstract expression inherent :: the processing mechanism of signals about the termination of transition processes .:. aperiodic circuits. The indicatability concept is first formulated or combinatorial -.:cuits. �ext a system of Boolean functions

S,. = S,. (x1, . .

.

) 1�

, Xt ,

r

� s will be considered,

hich is implementei by a redundant combinatorial circuit en with the inputs

i:

:·

X=

, xn}, n � t, m, the outputs Y = {yi, , Ym} , m : s, and the system = f; (x 1, . . , Xm ) , 1 � j � m, of characteristic functions (SCF), or more shortly F (x) .

:i,

.

..

. . .

.

=

�.:eh a circuit description, which is common or synchronous implementations, 1s

- 192 obviously insuicient for asynchronous

(and aperiodic circuits) .

From this :­

first of all, that the clss of allowed input transitions should be bounded. The encoding of a vector in the sets

X

and

Y

is carried out in such a way t.

A, B = Z(A) and K, L = Z(A), respectively, can be distin.-• in each of them. Moreover, AU B C X and LUK C Y , where X and Y are the � all binary vectors at circuit inputs and outputs, respectively. Also Z(A) ..� z and Z(K) = U A(k), where a E A and k E K. k

subvector classes

=

Deinition 7.1 An allowed transition a - b1 where a E A and b E B,

to be present at the inputs of a combinatorial circuit. Another allowed tran k - l of the circuit outputs, where k E K and l E L, is initiated by this tran­ If F(t) = l for any t E [a, b], then it will be said that the inputs X in the n� are indicated to the outputs Y at the transition a - b (or, more shortly, th: . circuit indicates the transition a - b). It will said that the inputs X in a circui: .. indicated to the output Y (the circuit is indicatableJ , when the circuit inputs X _ indicated to the outputs Y for all allowed transitions. The idea of the "circuit indicatability" concept is that an output vector in L � appear as a result of a transition process in a circuit only after a vector in

B hs �

peared at the circuit input. The deinition of indicatability makes possible a

oa

approach to problems concerning self-checking circuits, but obviously provids s

relation between these characteristics and the SCF deining the circuit. A si:� special case of indicatability will irst be examined in order to make investigatia about this notion.

Deinition 7 .2 Let there be an allowed transition

a - b at the inputs of a cirt such that a E o - (b), c(a, b) = xi, 1 :;; l :;; n (or a E o + (b), c ( a, b ) = x1}, and � a transition k - l for which the variation term e(k, l) contains Yr or ir, 1 :;; r � � be induced to the circuit outputs. It will be considered that Yr in this case translata x1 . This fact will be written by Yr = T(x1/a - b) .

The idea of the "translatability" concept is that a change of the value of some inp. signal in a circuit necessarily leads to the change of the value of some output sign:

Deinition 7.3 If for any allowed direct transition ai - b (either ai E o - (b

c(ai , b) = Xi or ai E O+ (b), c(ai, b) = Xi , 1 :;; i :;; n, for all allowed a1 - b) u found a variable Yr, 1 S r S m, for which Yr = T(xi/a• - b), then it will be sau that the circuit inputs X are translated to the outputs Y from the vector b in one step. This will be written as Y = Ts(X/b) . Some lemms and statements must be proved, when the characteristics of indicata­ bility are studied.

Lema 7 .1 A necessary condition for circuit indicatability is that all functions in

the SCF of the circuit are monotonous for allowed transitions.

- 193 ?:oof. :

-b

Assume the contrary. This implies the existence of an allowed tr.nsition

associated with a function

i (X) E F(X)

in the variation term

€(a, b),

such

:3at this function is not monotonous with respect to a variable x; . The relations

/i (Xj = 1) . f;(x; = 0) are thus valid because of of i(X) will - s a consequence of this - change more :tan once during the transition a - b. The transition k - l is thus not allowed Deinition 3.1) and satisfies neither Deinition 3.6 concerning an allowed transition �or Deinition 7.1 conceng indicatability. .... (xi = 1) l f; ( xi = 0) )efinition 3.5. The value

and

:he scope of the ollowing considerations will be limited to coding systems provided

(

-ith spacers see Chapter i

3).

The protocol of input and output vector changes used

(

this context is called tw-phased with a spacer a transition from a spacer to an

)

=?er.ting vector is an operating phse and an opposite transition is an idle phse .

Jn order to make transition s - b b - s) allowed, when b E B is a ::a-phased protocol with the spacers s, the class B = Z(s) must consist of vectors, ...ich are pairwise incomparable.

Leuna 7.2

be can be used after a spacer s for a i, where i is the zero spacer. Then the ::ansitions i - bk and i - be must be comparable: i < bk and i < be. Now, suppose :hat bk and be are comparable. Let b" < be for clarity. Then i < b" < be holds. This means that b" E [i, be], which is in contradiction with point 4 of Definition 3.6. n analogous resoning is correct or cases including the opposite transition b - i, $ = e, and for the general case s = i, e. ?roof. Any vector rom B, or instance

bk

or

:.·o-phse protocol with this spacer. Let s =

n the following the analysis of indicatability conditions is presented in order to ind :.e necessary and suicient conditions for translatability in combinatorial circuits.

A circuit output Yr , 1 � T � m translates an input x; , 1 � j � n, b is a direct transition and the varilble value vector given by the transition constant term w ( a, b) is a root of the equation.

Assertion 7.1

if a

-

7 .2 be satisied: for example, the variation Yr for g(a, b) = Xe. This means that there exists a variable Yr such that Yr(a) ) -(b) = 1 for ae - be. Thus ae = be, where a and b are values of e e �he variable Xe . Hence Yr(Xe = 0) i Yr(X = 1). From the deinition of the Boolean e derivative ollows that this equality is correct, if the record X given by the term '(a, b) is a root of the equation 8fr (X)/8xe = 1. Proof. Let the conditions of Definition

:erm

€(k, l)

contains

Assertion 7 . 2 directly ollows from this ssertion and from Deinition 7.3.

The inputs X in a circuit are translated to the outputs Y in one step from the vector b, if for any allowed direct transition a; - b the vector of variable Assertion 7.2

- 194 values given by the term w(a' , b) is a root of the corresponding i:th equation :.� type B ff' (X) 1 , = '=l ax,

v

where n is the number of inputs, m is the number of outputs, k is the cardinality of the vector b, 1 $ i $ k, if ai E o -(b) and t:(ai, b) = x;, 1 $ i $ n - k if ai E o+(b) and e(ai , b) = x;.

f ll functions fr(x) are isotonous with respect to the variable X , then equation i assumes the orm m

;= 0) fr(x; = /'(xV·

'=l

1) =

l.

This simplifies the utilization of Assertions 7.1 and 7.2. The corresponding ex.. sion is easily constructed for the cse, in which fr(X) is antitonous with resp. • the variable x;.

Exmple

7.1 Let the SCF for a circuit be Yl = fi(X) = x1 x2 , Y2 = 2(X = x1 V x2 {Fig. 7.1). The set o - (b1) consists of the vectors a1 = 01 and a2 = 10 .'• the vector b1 = 1 1 . The set o + (b1) is empty = 0). The set o +(b2) consists of ir vectors a1 and a2 for b2 = 00. The set o - (b2) is empty ( = 0). The derivatna of the function fi(X) and f 2 (X) with respect to x 1 equal a fi(X)/ B x 1 = x2 � a h.(X)/ ax 1 = X2 , respectively. The derivatives with respect to X2 are analogof computed. YI = Ts(X/b1) is true, if transitions from o - (b1) to b1 are allowed, � Y2 = Ts(X/b2), if O +(b2 ) = {a1, a2} . ·

The following theorem makes it possible to consider translatability as a special m of indicatability. Theorem 7 .1 A two-phase protocol of changing input vectors with a spacer a • supposed to be used in a combinatorial circuit. Let all transitions be direct (for b E B either e(s, b) = x; or e(s, b) = x;). Then the fulillment of the following thrt conditions is necessary and suicient for a circuit to be indicatable:

1. all vectors in the SCF of the circuit are monotonous for allowed transitiou 2.

all vectors in a class L are pairwise incomparable,

S.

x;.

for any allowed transition an output Yr, 1

$

T

$

m

is found, translating x;

Proof. It is suicient to examine the cse, or which all functions in the circuit .re isotonous or allowed transitions and e(s, b) = x;.

SCF

�

of

a

- 195 -

-

,- - - - -

I

I o -··r

- - -

&

I

I I I -

I

I I I

I I I I I I

--1 !

I

- -1

0

0 --I ._ -

-

--

Fig. 7 . 1

I

_I

Y2

- 196 a) Necessity. The necessity of condition dition

2.

1.

follows rom Lemma

7.1.

The necessity of co..­

ollows rom the fact that the output vector

k

=

F(s)

plays t.�

role of a spacer in a tw�phse output protocol and from Lemma 7.2. .� necessity of condition 3. ollows from Definition 7.1: F(s) = F(b) or any .­ lowed transition s

)

b

Yr

=

T(x;/ s - b)

Suiciency.

- b (b - s). Consequently, there exists at e:(s, b) = :; (:(s, b) = x;).

least one vari'�

when

The input protocol is allowed because of the conditions of the theorem. T�

l is fulfilled since t = 0. The vectors s and b are neighbm:.! and there are vectors n the subcube ( s, b). The output transitions are allowC because of similar considerations. f Yr = T( :; / s - b) is ound for any allow: transition s - b (s) , then k f l (F(s) . F(b) ) . The correctness of the transiti. k - l ollows rom the isotonocity of the functions. If remains to show th: H E Y \ (K U £) for any h E [k, l]. From the isotonocity of the functio� ollows that k < h < 16, and h i L because of the incomparability of ::} vector pair in L. All conditions of Definition 7.1 are thus satisfied.

requirement

F(t)

=

A generalization of Theorem

7.1

to the cse of arbitrary allowed transitions lead :

the following theorem.

Theorem 7.2 A two-phase protocol of alternating input vectors with a spacer 1 is assumed to be utilized in a combinatorial circuit. Then the fulilment of tAt following four conditions is necessary and suicient for a circuit to indicate lt allowed transitions b - s and s - b at the inputs: 1. all functions of the SCF of the circuit are monotonous for allowed transition! !.

all vectors i·n the class B are incomparable in pairs,

S.

all vectors in the class L are incomparable in pairs,

4. the inputs X are translated to the circuit outputs vectors b and s, respectively.

Y

in one step from tht

Proof. a

)

Necessity. The necessity of condition

1.

follows from Lemma 7 . 1 . Conditions 2. and 3 7.1 from Lemma 7.2. The necessity

-

follow - s in the proof of Theorem of condition all

Y

t =

4.

follows Definition

being neighbours to

Ts(x/b)

b

7.1: f(t) f l

for all

t(s, b), t � b, s. Thus F(t) - F(b).

are included, which means that

according to Definition

7.3.

6 lt should be pointed out that al allowed transitions in a two-phse protocol with a space­

occur between comparable vectors.

- 197 b) Suiciency. The input protocols are allowed because of the conditions of the theorem.

F(t ) . l is fulilled, since for any vector t E [s, bj a neigh­ bour vector d of b is found such that d E (t, b) = F(b) according to Defini­ tion 7.3. F(t ) . F(b) and F(t ) . l s F(t) :; F(d) :; F(d) ( the functions are isotonous) . The output transitions are proved to be allowed in the same way as in Theorem 7.1. All conditions of Definition 7.1 are thus satisied. The requirement

It should be noted that the indicatability of the transitions a the indicatability of the transition From Definition

b

-

a.

b do not guarantee

7.1 immediately ollows that a sequential composition of indicatable

circuits is also indicatable.

A combinatorial circuit (a circuit without eedback loops) can be split into layers in

the following way. The input variables constitute the O:th layer. The elements, the

(

) (k � i) , i) is not

inputs of which are connected to at lest one output of an elements in the i - l :th layer and not connected to any output of any element in the k:th layer constitute the i:th layer. H an output signal from the i:th layer connected to any

l :th layer (j

< I :; i),

(1

:; j $

then this signal belongs to both the input

and the output vector of signals at the i:th layer. Then the set of outputs rom the i:th layer and the set of inputs to the

(i + l ) :th layer coincide.

f the split into layers is made in a combinatorial circuit using the .hove method, then from Deinition

7 .1

follows that the inputs are indicated to the outputs in

any combinatorial circuit consisting of elements with monotonous characteristic

(

)

functions such functions of many commonly used elements are monotonous , if the conditions in Theorem

7.2 are satisied for all circuit layers.

From what has be said follows that . method for an.lyzing the operating capability of unclosed aperiodic circuits can be bsed on the conclusions of this theorem.

Example 7 .2 Let a combinatorial circuit of an aperiodic interface receiver he ex­

amined. This circuit carries out a transformation of the code "code-out-of-6" {OBC) into a 4- bit positional binary code. The code "S-out-o/-6" consists of mutually in­ comparable vectors {SSC}. this code can be used to set up a two-phase protocol of allowed input transitions with a spacer. Two additional outputs are used in order to ensure allowed transitions at the output of the transformations circuits. The trans­ formation table of the code is shown in Table 1.1. Various input vectors in this table may correspond to the same output vector, as the input code bits P1 and p2 are brought without transformation to the 4-bit positional code. The functions y3 , ia, )4, /4 are given by {Fig. 7.2.}

Ya

P1P3 V P2P5 V p3p5 ,

- 198 -

decimal Y3 Os Y• Y• equivalent 0 0 0 0 i-spacer 0 1 0 1 0 1 0 0 1 2 0 1 1 0 1 1 0 1 0 3 0 1 0 1 8 1 0 0 1 10 0 1 1 0 9 1 0 1 0 11 0 1 0 1 4 1 0 0 1 6 0 1 1 0 5 1 0 1 0 7 0 1 0 1 12 1 0 0 1 14 0 1 1 0 13 1 0 1 0 15

P1 P2 PS P• p5 P6 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0

Table 7.1

Y3 Y• Y•

P1Ps V P2Pi V PiP6, P1P4 V P2Ps V p3p4, P1Ps V P2 V PsP6,

when the forbidden bit patterns in the deinition have been taken into account. clearly seen that the conditions 1.-3. of Theorem 7 .2 are satisied or allo... input transitions of the circuit. The derivatives re computed in order to chd condition 4: It is

8y3/8p3 8ys/8p4 8 Ys/8p5 8ys/8p6 8Js/Bp3 8;3/8p4 8;3/ ops 8Js /8p5 ay./ops

=

P1P2 V P1Ps V P2Ps,

O·

'

P1P2 V P2Ps V P1Ps,

O·,

0,

=

P1P2 V P1P6 V P2ts; 0, P152 V P1P• V fhp4; fhP2 V PtP4 Y P2i•,

- 199 -

-

&

-&

1

--

II

I I

�

I

u 0

v

[&--

I

1

--- &

T

-

&

H--- -D Y3

- �,� &

I I I I I

�

I

� · --

I II

I I I I I

I

I I I

I

---� - y. 1, U

I

I

I I I I I I I

L

__--,

&

I I I

I

-&

_

_

_

Fig.

_

7.2

_

I

l

_

I I

-1 ___

_

I I J

.

y.

- 200 av. /ap5

O·'

8y4/8p4

PIP2 v PIPS v P2P3,

ay. /ap6

-

8J4/aps

O·' O·'

8;4/8p4 8 f4 /8p5

o;

=

8 f4 /BP6

PIP2 V PtP6 V P2P6; PIP2 V i1Ps V P2P6.

Disjunctions of the derivatives .re then formed in order to check the translatab· conditions:

P1P2 v PIP6 v P2is Y P1P2 v PIPS v P2Psi P1P2 v P2P3 v P1P3 v P1P2 v PIP6 v P2P5 ; P1P2 v PIP4

6 B y·

V

v P2P4

v P1P2 v P1P5 v PlPS

8y· � and V � are analogously defined.

i=l Pt

s

i=I P2

A transition rom a spacer to the vector b2

=

1 11000 is examined. Then

{011000, 101000, 110000} , 1, 1, Pt V P2

1

The examination of the transition thus shows that all conditions of Theorem 7.! are satisfied and that the transition is indicated by the circuit. The translatability

- 201 conditions for other transitions can be checked in thesame way in order to be sure that all allowed transitions are indicated by the circuit ( the circuit is indicatable) . A

fundamental indicator design method is shown below.

Example 7.3 The inputs X of a combinatorial circuit consisting of an AND­ element {OR-element} with an isotonous characteristic function Yl ::: x1 · x2 · . . . - Xn ( Y2 = X 1 V x2 V . . . V xn) are indicated to the outputs Y at the transition i - e (e - i), but the reverse transition e - i {i - e} is not indicated. However, in a cir­ cuit consisting of a pair of AND- and OR-elements {Fig. 7.S, a so called "parallel compression circuit") inputs are indicated to outputs at allowed transition protocols of the type e - i' - e - e · · ·. Actually, ByifBxi ::: x1 · x2 · · · · · Xi-1 · Xi+l · · • • • Xn and Xn. Thus Y1 = Ts (x/e) and Y2 = Ts (x/i) . 8y2/Bx1 = x1 • x2 · · · · · i\ -1 X1+1 All conditions of Theorem 7.2 are satisied, since the classes B and L consists of the single vector e {i). •

•

·

·

• •

\foltiple input AND- and OR-elements ( NAND- and NOR-elements) in a parallel compression circuit can be replaced by multilayer circuits consisting of all types of elements with a smaller number of inputs. This replacement naturally also includes circuits consisting of two-input elements. Indicators and especially parallel compression circuits makes it possible to obtain a single completion signal in a circuit. These circuits are built-in test checkers rom the viewpoint of technical diagnostics. The allowed transition concept is preserved for aperiodic automata implemented using canonical structural models ( this concerns extended aperiodic circuits con­ taining memory elements) . Such a preservation is in harmony with Deinition 3.5 ( in this deinition the concept of an allowed transition is introduced that is not re­ lated to any characteristics of a the type of circuit of the vectors, which may follow each other) and this concept belongs to the allowed transition protocols.

The diference between a combinatorial circuit and a automaton designed to corre­ spond to a canonical structural model is - from "the structural point of view" that one of the layers in such an automaton is composed of memory elements. These memory elements are elements described by the automata equations Y = F(X, Z) . When the operation of such elements is studied, then it is necessary to take tran­ sitions between automaton states into consideration (s - q, s E S, q E Q). The indicatability for Moore automata ( a Mealy automaton can be obtained as a com­ position of a Moore automaton and a combinatorial circuit; a special definition of the indicatability for a Mealy automaton is not introduced ) is - corresponding to what hs been said - defined by the following. Deinition 1.4 Let there be an acceptable transition a b (a E A, b E B} at the inputs of a circuit descri'bed by a model of a Moore automaton. Let this transition -

, �I - 202 -

(

1

Xn

--

r

:

Y1

Fi g . 7 . 3

x

I,

1

&

&

-� &

Fi g.

7.L

0

y2

- 203 initiate an acceptable transition s - q (s E S, q E Q) between automaton states (i. e. between vectors which are coded as states}. If F(t, r) . q for any t E [a, b} and r E [s, q] , then it will be said that the circuit indicates the transition a b. For the case, when the circuit indicates all acceptable transitions, the circuit is considered to be indicatable. -

Deinition 7.4 fully corresponds to Definition

7. I.

One can thus esily be convinced

of the fact that theorems and assertions analogous to those proved in this chapter

for combinatorial circuits are valid for the considered automata types with the diference that automata equations or sequential circuits must be treated instead of characteristic functions for combinatorial circuits.

rom what has been said follows that any circuit, in which a combinatorial part and a

memory can be distinguished in an obvious way, can be designed and analyzed

by structural methods

(in

particular - as will be seen further on - diagnostic

)

characteristics of circuits can be checked by structural methods . In this context, an analysis of the operation capability includes • •

the division of the combinatorial part and, possibly, the memory into layers, on each layer, the definition of allowed input and output transitions, which arise in the process of circuit operation, and

•

the checking of the transmission conditions.

Analysis with structural methods can be combined with circuit semimodularity

checks. In some cases it turns out to be efective to analyze the combinatorial part

with structural methods but to analyze memory elements by checking their semi­

(

modularity after the corresponding connection of output to inputs see Chapter

5). (

The well-known-non-formal deinition of an aperiodic automaton is recalled here it

)

is in the orm of a subclass of automata with a two-phased input protocol .

Deinition 7 .5 An automaton is called matched in the case, when the cycle for the environment is formed by the automaton and the cycle for the automaton is formed by the environment. An aperiodic automaton is a matched automaton, for which a transition process caused by the change of an input state class is executed with a corresponding change of an output state class independently of the values of the delays in elements of which the automaton is constructed. Assertion 7.3 A circuit is aperiodic if it is indicatable. Proof. The assertion can be prooundly motivated but not strictly proved because

of the non-formality of the definition.

- 24 a) Necessity. Assume the contrary.

(SSC )

protocols

The generally used input and output vector chang!

in aperiodic circuits are allowed. Therefore, the ssumptio.

that the circuit is not indicatable is reduced to the statement that a vecto�

tE

[a, b]

and state r E

[s, q]

(

are ound or which / t, r)

)

=

q.

However, the�

the class change of output vectors (states in the circuit will continue till sor element is switched.

The automaton thus moves rom a state belonging �

some clss to a state belonging to some other class till the transition proce will terminate at the input or in some element of the circuit. b ) Suiciency

Assume the contrary. Let the circuit be indicatable and ssume that som class of automaton states hs changed s long s some clss of input state changed or till the transition process in some of the circuit elements bu terminated.

Then a vector

t . B is still present at the circuit inputs bu�

the automaton has already entered the state with Definition

7 .2

7.4 about indicatability.

qE

Q . This is in contradictio.

Total Self-checking in Aperiodic Circuits

Unsuccessful attempts to design totally self-checking synchronous circuits are a­ parently explained by the fact that the specific eatures of such circuit require •

revision of the well-known deinitions of fault-tolerance, self-testing and totL self-checking, and

•

more detailed an examination of issues concerning variable encoding and per­ missible vector transition disciplines

(these

questions are - s already hu

been said - most closely connected to the appearance of unctional hazar! s well s with the demand or absence of logical races in synchronous ci'­

cuits) .

There must thus exist a fundamental connection between the concepts indicatabil­ ity and total self-checking. Total self-checking in synchronous circuits is evidentl­ possible only or a deined input vector transition discipline. The two-phase disci­ pline is practically the only discipline, which does not put strong restrictions on th� organization of the environment. The concept "allowed transition"

(Deinition 3.6) and the earlier notation are kept

The absence of aults in a circuit will be denoted by subscript µ.

operating circuit implements the unction system fµ(X) iests itself in such

Fp(X) - F(X).

a

=

F(X).

A correctly

A fault p man­

way that the combinatorial circuit implements the function

- 205 Deinition 7.6 An asynchronous combinatorial circuit (with a two-phased disci­ pline) is called totally self-checking for faults of the class P, if the following condi­ tions are satisied for all p E P: a} either

(36)

or is

(37)

satisied for any allowed transition a - b;

b) either

(38)

(39)

OT

is satisied for any allowed transition b - a.

{The conditions a) and b} constitute the essence of the condition concerning "fault-tolerance") c) there exists at least one allowed transition a - b or b-a for which condition (97) or {99} is satisied ("sel-testing").

fault may be revealed - not immediately at the moment of its occurrence but - only at the next phse of circuit operation ( two-phse discipline) . This must, however, not be considered s a notation of the ideology of total self-checking, since the moment or period of circuit operation is derived from the full operational cycle, which included both phses of the two-phase discipline. A

�ow a theorem will be ormulated, which combines the structural property of indi­ catability of fault-ree combinatorial circuits with the diagnostic properties - total self-checking - of such circuits. Theorem 7.3 An indicatable combinatorial circuit is totally sel-checking for single and multiple stuck-at-0 or -1 faults in circuit elements. If there are no branching at circuit inputs or if faults appear before branching, then stuck-at faults at circuit inputs will also be revealed.

Proof. Let there be a fault in some element of a indicatable circuit. Let the fault be stuck-at-0.

a) If the aulty element does not have to switch during an acceptable transition a - b, then the condition (36) of Deinition 7.6 will be satisied. If this element has to switch rom 0 to 1, then either Fp(b)

=

Fµ(a) , or Fp(b)

=

Fµ(t) where

- 206 t E

[a, b] ,

or

Fp(b)

=

h, where h E

L according to Deition

satisied.

7.1.

[k, l]. F(t) . L, F(a)

Thus the condition

(37)

. L and � E

of Definition 7 E

b) If the faulty element is essential, then there is at lest one allowed transitio. x

a - b or b- a, where this element must switch (it will be without of� of generality ssumed that this transition is of the type a- b or the considlC fault). Then an allowed transition a - b is ound, or which Fp (b) = Fµ(a r F(b) = F4(t) or Fp (b) = h, h E (k , l] . the type

Consequently, Fp (b) . L and point a) of Deinition

7.6 is fulilled, which means t.;

the circuit is totally self-checking. An analogous reasoning can be carried out x

case of a stuck-at-1 fault and multiple faults.

The deinition of totally self-checking sequential circuits is a generalization of .

corresponding definition for combinatorial circuits. This deinition will be or.

lated only for a Moore automaton. 3 earlier, a Mealy automaton will be considec

to be a composition of a Moore automaton and a combinatorial circuit. It should .

pointed out that an inter-state transition

c

- d in

an automaton cannot termin�

in cse of a fault p E P, since together with the final vector vector 6 E

[c, ]

will show up, and during the transition

F4(b, d) will change to the record Fp(a, 1) in the cse of a fault .

show up. Thus, the record

F4(a, c)

to the record

d of this transition o:r d - c a vector I E (c, dj -_ Fp(b,

8) and the r!

Deinition 7. 7 A n asynchronous Moore automaton (with a two-phase discipli&! will be called totally self-checking for faults in the class P, if the following conditiou are satisied for all p E P: a} either

Fp(b, 6) = F4 (b , d) ,

(C

or (41 is satisied for any allowed transition of the type a - b; b} either (42 or

(43)

is satisied for any allowed transition of the type (The conditions a) and "!ault-tolerance ".)

b)

b

-

a.

constitute the essence of the condition concerning

�

207 -

c) there exists at least one allowed transition (of the type a b or b the condition 11) or 19) is satisied (self-testing). -

-

a

} for which

Attention should be paid to the act that a ault in an automaton can - s also in a combinatorial circuit - be revealed not immediately, "at the moment of occurence" , but only during the next phse of the tw-phse discipline. A theorem can be formulated or synchronous automata in analogy with Theo­ rem

7.3.

Theorem 7.4 Indicatable automata are totally sel-checking for single and multiple stuck element faults. From Theorem

7.4

immediately follows that aperiodic automata are totally self­

checking sequential circuits, since Assertion

7 .3 is satisied for combinatorial s well

s for sequential circuits. The fault detection mechanism is necessarily connected with the ability to encode input and output variables with self-synchronizing codes (Chapter

3).

A time in­

�erval, during which a circuit must complete a transition can be evaluated rom the operational speed. Then the absence of an output vector belonging to the clss (or a transition of the type a

b

-

b)

D

of to the class C (for a transition of the type

a) at the end of this time period can be interpreted s the existence of faults in

-

the circuit. The Theorems

7 .3

and

7.4

have principal importance: a bridge is built between

problems of technical diagnostics and the theory of aperiodic automata.

n immediate result of the fact is the possibility to use methods for analysis and

synthesis of aperiodic circuits in the design and checking of totally self-checking circuits. The results of the theory of aperiodic automat. make it possible to solve some problems of the theory of totally self-checking circuits. Earlier hs already been stated that the faults of the synchronization system can­ not be found in synchronous self-checking circuits. Thereore, only going over to synchronous7 (aperiodic) totally self-checking circuits actually makes it possible to obtain total sef-checking with respect to stuck element defects.

Usually a cir­

cuit with checking capabilities is designed without paying attention to diagnostic demands, and then various "mechanisms" are artificially added, which provide the circuit with an ability to test by means of a partition of the circuit input and output 7It should be pointed out that synchronous circuits - as is known - constitute a special case of synchronous circuits. For example, the presence and the absence of the synchronization impulse can

be considered as two circuit operation phases.

- 208 vectors into clsses. Then a tester, which recognizes the class a vector is a m::. of, is "attached" to the circuit. The ability to test is provided immediately !r� the design of an aperiodic circuit. This makes it possible to simplify essenti:: a

synthesis methods or totally self-checking circuits themselves as well s for t �...

which recognize the clss membership of vectors. It should be pointed out tha: R parallel compression circuit

( Fig. 7.3)

is like an "abstract model" of n arbi..-..�

tester for two-rail coding. The circuit is totally self-testing for single and mU:·­ stuck element faults. Two examples are given s a conclusion to this section.

Example

7.4 A solution to the tester design problem concerning the balanced :* of S" is presented. This problem is actually "insoluble" in an ordinary totally 1� checking circuit. Such a tester circuit is shown in Fig. 7.4. This circuit complelf corresponds to Deinition 7.6. Hereby A = {i}, B = {001, 100, 010}, K = {i}, a L = { 10} . The circuit implements the system «1

X1 V Xz V X3

11

/2

X1X2

v

X1Xg

v

x2x3,

and transforms the code "1 of S" into the code «1 of 2".

Example

7.5 Let it be necessary to implement the automaton equation

in the form of a totally self-checking asynchronous circuit. After encoding the in: vectors and the states of the automaton with self-synchronizing codes, the system Y

y

yx2 V : 1 X1X2 V Y Xt

is obtained. An aperiodic implementation of this equation system is presented in Fig. 7.5. Tt circuit is implemented with the aid of an aperiodic D-iip-iop using a canonic. structure of the aperiodic automaton. Input variables in this context are: xi, r: and a . The class of operational input tJectors is characterized by the conditios a = 1, which for output vectors corresponds X1 f x1 and Xz f x. The class of idle tJectors is deined by the condition a = 0. One can - by using methods examined is the present chapter - easily be convinced of the fact that the combinatorial circa: and the tip-top are i"ndicatable. Layers {Y, G}, {G , M}, (M, y) can in this conte: be distinguished in the memory. The symbols within parenthesis are, respectivelr input and output vectors of a layer.

- 209 -

-

l

I

...

'

O

0

I

v

::

c:

J

0

-

, :> -

0

I

I

I

v

e)

l

-

-

�

'

�- --

-

----

J

-- -

-

-- --

�

I�

I

I

--

-- --

•6

�

- x

�--

�

N

x

(

::

) �

x

"

I l

�

:1ex

) N

x

--

--

-

--

•-

--

-

- 2 10 The operation of this circuit i·s examined for the case of a stuck-at fault in a ii;-.z element. Let a fault M = 0 appear in the element M. Then the value of the o ..: � signals from the elements M, y, G and G cannot change either, which mean! � M = y = G = G = 1 . The signals Y = Y = 0, M = O, M = 1, y = y ::: b = 0 will appear at the element outputs of the combinatorial circuit for a tran-.:· from an operational vector to the spacer i (a = 0 when this happens). Tht .1� is thus in this phase i·n no way visible and the output vector {automaton stag! • in no way diferent from the vector which in this case would be obtained in a !�,._ free circuit. The requirement of fault-tolerance is consequently fulilled. Then, ..� having applied an operational vector to the circuit inputs, the condition Y - l' : be satisied, for example Y = 1, Y = 0 (a = 1), and the element M must s : from 0 to 1 . However, the signals G = G = 1, M = 1, M = 0, Y = 1, y ::: : will appear at the outputs of the circuits layers because of the fault in this elem�. This means that the idle vector at the output y will never change to an operatiosa vector. Moreover, b = 0 and will not switch from 0 to 1. _

To sum up, if a delay � with a value many times longer than the sum of the vlI of the delays in the elements of the circuit is connected in parallel with the cin� (it should be pointed out that this in no way will inluence the operational s�� of the circuit, since this delay "works" only in case of a fault in the circuit)1 At the appearance of a signal from this delay earlier than from the signal b make! : possi"ble to conclude that there is a stuck element fault in the circuit. If the sign: r will appear earlier than the signal from the output of the delay �, the excitation ..� the delay will be disregarded. This delay will therefore not inluence the functioni•f of a fault-free circuit. Fault localization is possible, or example, within the accuracy of a lip-flop bit. a register bit or a bit in some other storage element. Self-repair is carried out ' switching in a reserve module instead of a aulty one. Section 7.4 is dedicated = automatic organization of self-repair. 1.3

Fault Detection of Autonomous Circuits

The definitions in Section 7.2 of the concept "totally self-checking synchronou, combinatorial circuits and automata" can be extended to the circuit ssignmen. cse with the aid of the Muller model of circuits examined in Chapters 2 and 5 (equation system, transition diagram) . f

a transition process in an unautonomous unclosed circuit terminates in some deadlock state of the transition diagram, then the fault-free autonomous circuit will not enter deadlocks. A

stuck element fault is described in the Muller model as a reeze in the initial

- 211 equation system (in a fault-ree circuit) or the variable corresponding to the faulty element . Such a freeze only describes the inal result of the appearance of a stuck­ at fault in an element. However, since .n autonomous circuit "operates eternally" , the question concerning a circuit transition rom a fault-free state to . aulty state should not be left without attention. Two stable (1 and 0) and two excited (1 * and O*) element states are treated in the Muller model. An element may - s a result of a stuck-at fault - be n the states 1 or O, which become so to say "deinitely stable" . The transitions 1 -+ 1 , 1* -+ 1 , O* -+ 1 , 0 -+ 0, O* -+ 0, 1* 0, 0 + 1, 1 0 (or models of the "collapsing" process of an element) are accordingly possible. The irst six transitions do not lead to a change of the circuit state (or lead to a state change, which will appear also in a fault-free circuit) . A constant fault of this type will be e.Bed conservative. The two lst transitions lead to new interstate communication in the transition diagram. This means that such transitions change the behaviour of the circuit. This type of a stuck-at fault will be called mutational. Mutational faults are especially diicult to debug, since such faults "distort" . transition diagram in an arbitrary way. They may even take circuit beyond the limits of the set of operational states. +

+

Example 7.6 The circuit in Fig. 5.!1,a and especially its complete transition dia­

gram presented in the same igure be examined. The system of characteristic func­ tions (Fig. 5.£1,a} is transformed to Z1

0

Z2

Z1

Zs

=

Z2,

and the transition diagram is changed to the diagram shown in Fig. 7.6 for the fault Z1 = 0. Th"s fault is in no way relected in the operation of the elements z2 and zs, but the existence of a fault in the circuit can be detected through the termination of switching in the circuit, since the state 010 is a deadlock state. This does not often occur directly; for example the transition 1 * l * 1 - 010 requires 6 switching operations. If the circuit is in the states 110 or 100 at the moment of appearance of the fault 0, then the fault is mutational. If the circuit is in one of the other circuit states, then the fault is conservative.

z =

A natural manifestation of faults thus presents itself by the existence of deadlock states in transition diagrams of aulty circuits. Hereby can any essential conservative faults be revealed suiciently simply. The discovery of mutation aults is obviously not always possible and requires transition diagrams of ault-ree circuits to be provided with some special characteristics.

The ollowing notation is adopted:

- 212

Fig.

�

7.6

'� ! � L�! ,� - o * v * o --- 0 * 1

o•-0*1 * 1 -0*0

Fi g .

7.7

1 *

_I

- 213 -

.? a) r

( such

the set of operational states of the circuit including the state a

will also be called an

operational cycle

a union of inite (including deadlock

through the state

a set

a);

) sets of operational states of a fault-ree

circuit. The set of operational states - also including deadlocks - of a faulty

(

circuit will not coincide with these sets the latter states will appear during

p) ;

the transformation of the transition diagram of a fault-ree circuit by means of reezing the variables corresponding to a fault

R

the union of the set of infinite circuit operational cycles given, including all states, which belong to at lest one of these cycles. Each cycle is an infinite

(meaning cyclic here)

:he subscripts M and

state sequence .

p will -

earlier - mark s corresponding notations for

s

..ult-free and faulty circuit, respectively.

.(3)

E

R,

the relation

nd the relation

R( a)

R( a) . R(3) R(3), if they

=

For a pair of operational cycles

R( a) ,

will be used, if these cycles do not coincide coincide.

An autonomous circuit with operational cycles in R is called totally l!lf-checking for faults of the class P, if the following conditions are satisied for all

Deinition 7 .8 _, E

P:

a} for any operational cycle R(a) E R either (44) or

Rp(a) E T (and Rp(a) . R}

(45)

is satisied (the condition of fault-tolerance); b) there exists at least one operational cycle, for which the condition {45} satisied {self-testing).

is

The idea of the condition of ault-tolerance is that either operational cycles of :ault-free and aulty circuits coincide, or an operational cycle of a faulty circuit does not coincide with any infinite operational cycle of the correspondin g fault-free

(

)

circuit and is simultaneously finite contains a deadlock . The self-testing condition requires that a faulty circuit must enter a deadlock state.

(

It has been ound out that semimodular circuits see Chapters self-checking for all fault classes.

2 and 5)

It is quite obvious that if a part of the states in an operational cycle a

fictitious equivalence class

(a ictitious

sequence of a circuit - see Section

5.5),

are totally

R(a)

orms

equivalence class is not a complete state

1 is excited and = 1 will not - corresponding to

in which the variable Zs =

still not switching, then the circuit with the fault

z8

- 214 -

Definition 7.8 be totally self-checking (it should be pointed out that the indica:� fault is conservative for states in the ictitious equivalence class) . Indeed, for :. fault the states in a fictitious equivalence clss change to each other infinitely, :.: the circuit will not enter any deadlock state. It is clear that the fault will no: :. detected in this cse, and operating cycles in fault-ree and faulty circuits do :' coincide. It is, however, possible to become convinced of the fact that the prse::r of ictitious equivalence clsses in a transition diagram is caused by the existe::r of elements with inputs isolated from outputs of other elements (such are elen:e.! closed into themselves s well s generators of the logical values "O" or "1" ) . -

Example 7 .7 The circuit described b y the system

contains one "1 "-generator and its transition diagram {Fig. 7. 7) has a ictitiOM equivalence class. The fault z1 = 0 cannot be detected in this circuit, as is e.. �1 seen.

Examination of autonomous circuits with such isolated elements is not expedie::� since such a circuit can be simplified just because of them. Therefore, only circuia. which do not posses any ictitious equivalence clss will be examined further on . this chapter. Deinition 7 .9 A constant fault p will be called

a) external to the set RJ if the circuit) which hitherto has been in one of the sta�� of an operational cycle included in F, after the appearance of p turns out :; be in a state 8p such that 8p . R and 8p � r; b} mobile for the set R with the operational cycles R(a), R(3) E R1 if a stll!t Im E R(a) is found where [p E R(8) . This means that p(a) = RM (o p(a) = RM (1) , an d RM ( a ) = RM (3) .

Faults of both indicated types are obviously mutational, and it is also obvious th: every mutational fault is not necessarily either external or mobile. An external a.: difers from a mobile fault by the fact that it takes a circuit out of the region, whe� the behaviour of the circuit hs been investigated. A circuit may therefore ente� an ininite state cyde or an external fault. An external fault is thus dangerous o: the reason that it may actually turn out to be mobile. Example 7 .8 The behaviour of a circuit is described by the transition diagram is

Fig. 7. 8 (four states are omitted in the diagram) since the circuit behaviour is no:

- 215 -

{

tssential in these states). The transition diagram in Fig. the equation system Zl = Z1i2 V Z2Z2

:c

z2 z3 Z4

= =

{

=

7.8 especially corresponds

z2 z1z2 v z4 z2 V z1zs V Z1Z3

This equation system is for z2 = 1 and z2 = 0 reduced to

:nd

{

respectively. For z1 = z2 = 0,

s

z1 z2 Z3 Z4

Z1 z2 Z3 Z4

{

is

1

=

Z1 V Z4

1

=

Zt z2 Z3 Z4

Z1 V Z3 0 Z4 z1z3 v z1zs

0 0 Z4 i3

obtained.

Both constant faults of the element z2 are mobile for the set of operational cycles R {R(lOOO) U R(llll)J. For z2 = 1 the circuit will leave the operational cycle R(lOOO) and enter a state in the operational cycle R(l lll). The circuit will thus not enter any deadlock state. For z2 = 0 the operational cycle change occurs the other way roundj from states in R(llll) into a state in R(lOOO) . The fault z1 = z2 = 0 turns out to be external for the indicated operational cycles, since the circuit will leave the set R but will still not enter any deadlock state when the fault appears. The condition

p (a)

E r

or an external fault. For p (a) . R will be satisfied.

will obviously not be satisied

mobile faults neither this condition nor the condition

External and mobile faults in autonomous circuits will thus as a rule not be detected.

Theorem 7.5 An autonomous circuit with the ininite operational cycles R(a),

R(3) , . . . , R(w) E R without ictitious equivalence classes and semimodular with re­ spect to the states a , 3, . . . , w is totally self-checking for single and multiple constant element fa-ulis which are neither external to nor mobile for R.

- 216 -

L1

a•o

-- t � I ·o • o �

r

_

,

0

1- 1 * 1

0 ---1

0 -0 * 1

0*0-1

1

1

1

-o

0

1

f

0 * 0 �1 o

0-1

1 *1

o_ _

_

_ _ _

0*-1

0

1*1 - 0*1

1

1-o

O*O

1 *

0

0

1 -1

1

0*1

0

1

1 * 1 --

1 • 1 -- o * o

O * - o*o

1

1 * 1 -1

Fig.

1--1 * 1

� I --� ! � I o

o*- 1

1

o

i

1

7.8

1 *1 -0*1

Fi g .

0

1 -1

1

1.9

J 1 *

Fi g . 7 . 10

1

0* 1

o

o

1 * -

--.

·1 *

�

- 217 Proof. If the set example in

R(:)

R

contains some operational cycles, then in some of them - for

- may be found elements, which are not live

)

they do not switch during the given operational cycle .

(this

means that

Conservative aults in these elements will thus in no way show themselves dur­ ing the operational cycle

R(:) .

The condition

(44)

is thus satisied. Mutational

faults, which are neither mobile or external, in elements, which are not live, lead to deadlock states. The condition

(45)

is thus satisfied. If an element is live, then a

non-external and non-mobile ault in it leads, in particular, to a situation, in which the element output signal is rozen. Since the circuit is semimodular and the set of operational states of the circuit does not contain any ictitious equivalence classes,

a state I is found in this set, such that only the faulty element is excited.

element cannot switch because of the fault and condition

( 45)

This

is thence satisfied.

) of 7.8 (self-testing) is satisfied, since there must be no circuit element, which is not live for any one of the operational cycles of the circuit (such an element would be useless and should be removed rom the circuit ) . The fault-tolerance conditions are thus satisied in all cases. Also condition b Deinition

Example 7.9 A circuit, whose behaviour is described by the transition diagram in Fig. 7. 9, will be examined. The circuit speciically corresponds to the equation system Z1

i2 V Z3 V Z4

Z3

Z1Z2 V Z3Z4

Z2

Z4

Z2Z4 V Z3Z4

=

(46)

z2z4 v z2z3

The operating cycles of the circuit are R(lOOO) and R(llll). The state 1111 will be a deadlock state for the fault z1 ::: 1 . Self-testing thus occurs. The fault z1 = 0 also revealed in the operational cycle R{1111}; the state 0101 turns out to be a deadlock state. The fault z 1 = z2 = 0 is external to the set R = (R(lOOO) U R(l l l l)). However, with the assignment of still operating cycle - R(OOOO) the fault becomes non-external and non-mobile. The fault can then be detected, since hereby the circuit (46) turns out to be in a deadlock state. -

It !s necessary to note that the semimodularity of a fault-free circuit with respect to

R is essentially used in the proof of Theorem 7 .5. If a circuit does not possess these characteristics ( even if the circuit would not speed-independent) ,

states in the set

then constant non-external and non-mobile faults in the circuit may also remain undetected.

Example 7.10 A fault in one of the inverters in the already operating speed-in-

- 218 dependent circuit

will not lead to a deadlock state and a circuit "stop ". For example, the fault z1 = : wW be relected by the equation system

and by the the transition diagram in Fig. 7.10. It is obvious that the indicated f.: will not be detected although it is neither external nor mobile for the initial circ. Investigations on diagnostic properties of autonomous circuits are especially r portant, since so called modelling

(or

hsis) circuits, which are represented by &

modular structure model of a complex device, are autonomous. The diagnosis d

such devices is not possible without solving the problem of forming signals fro::

(

)

device autonomous faults by using signals rom module faults. The analysis of diagnostic properties of autonomous circuits can � generally speak­ ing

�

be carried out in two directions. The irst direction is to check a circuit fc:

(

)

given faults in the class of stuck-at type faults and given operational cycles. Sm±

an analysis can be carried out with the same methods s the usual analysis a:

the operational state set n a circuit

( Section 5.5)

and is comparatively simple. h

should be pointed out that the analysis of semimodularity must usually preced!

the analysis of diagnostic properties of a circuit corresponding to the conditions o! Theorem

7 .5.

The purpose of the analysis is in this irst approach to check, whether

the circuit will reach a deadlock state, when the given faults appear.

(

The second approach in a complete circuit analysis Section

5.4) includes the search

for all infinite operational cycles, with respect to the states of which the circuit is semimodular, and the definition of all finite

(including

)

deadlock

operational

cycles of the circuit. Then using the obtained information, it is possible to predict all possible external and mobile circuit aults.

These fault types are especially

dangerous, since semimodul.r circuits are not totally self-checking or such faults. The discovery of frozen variables leading to such faults makes it possible to make arrangements for the most "vulnerable" circuit points which, for example, ought to be "strengthened" by technological methods. The computational complexity of the required algorithms is quite high in such an approach to the analysis of diagnostic properties of autonomous circuits. No essentially better methods have hitherto been developed than the construction of a complete transition diagram for a circuit and sorting out ll possible combinations of mutational element faults in the circuit.

- 219 Even more complex and less investigated is the analysis of the possibilities to detect defects leading to a circuit topology change, or example a wire short circuit or a :>reak after a branching point (a break before a branching point is reduced to a stuck-at type element fault ) and also a short circuit from the output to the input of an element. The most probable ones of such defects can be investigated using :he methods described in Chapter 5 in a similar way it is proposed to be done for stuck-at faults. For some faults corresponding to above indicated defects can hereby �utonomous circuits in some cses turn out to be totally self-checking. The question about regular synthesis methods of autonomous circuits, which are or arbitrary constant element faults, remains open, since semimodular circuits are not completely self-checking for all constant element faults.

:ompletely self-checking

7.4

Self-repair Organization

The self-repair process in some device is ssociated with the sequential execution of a three steps fault diagnosis that is: determination of faults' presence in the device )peration; fault localization, i.e. discovery of the place in which a fault has occurred or example with the accuracy of a cell in a regular structure ) ; and repair, which is :ontained in the switching leading to the exchange of the faulty cell with a reserve :ell. Self-repair thus leads to the restoration of the ability of a device structure to operate. order to restore the process, which a device ws executing till the moment of :he appearance of a fault, it is necessary after the termination of self-repair to set :he device into the initial state ( or into the latest control state) and to restart the irocess. n

will be considered that the irst one of the three mentioned steps - functional diagnostics - can be implemented with the means described n the present chapter. A result of the diagnostics is the production of ault signal d = 1.

It

Two methods of self-repair organization can be proposed. In the irst method a faulty cell will be replaced by . reserve cell in cse of fault appearance. One and the same reserve cell can hereby replace any one of the basic cells, in which a fault ay appear. The given method will thereore be called self-repair based on a general reserve. Fig. 7.11 (block diagram ) shows the organization of self-repair based on a general reserve. Every i:th cell of device is connected to the preceding (i - l ) :th cell and to the succeeding (i + 1) :th cell. 8 This diagram consists of a functional part Pi, a fault 8The block diagram can easily be generalized to arbitrary intercommunication between cells.

- 220 -

Di and a communicator Ki , which can connect inputs of t� >i with the functional reserve block >n+I instead of >;+i, if a fa�: has been localized to the (i- 1 ) :th cell, or instead of >;+ 1 , if a fault hs been localiz: to the (i + l ) :th cell. The outputs of the detectors Di- l and Di+1 control � switching operations of Ki . The repair also includes the connections of the rertr

localization detector functional part

cell inputs with the outputs of all cells, which have been connected to the inpc:t of the aulty cell. This function is carried out at the input of the reserve cell � the commutator

Kp according to fault localization signals of detectors D1 , . . . , D.

It should be noted that a correct self-repair organization will be obtained, since ­

(

)

faults in the i:th cell in the unctional part s well s in the switching part cn � successfully repaired "by force" by the other cells.

The circuit given in Fig.

7.12

is a bsic bit of a self-repairing counter. The curc:i�

(

contains a functional part - a counter flip-Hop the elements localization detector consisting of the

�

and a fault lip-Hop

(Ti , ',) .

Ui , i1, q, , .1 , Pi, Pi )

-

a

modulo 2 summing subcircuit with the outp��

The input wire commutator of the counter bit a

combined with the functional part and is directly implemented by the elements " and s ·

Every bit of the binary counter contains one input wire: the carry

i- l

rom the preceding bit. The commutator must implement one switching functior_

a, = ti-lPi-1 V T1-1J1•

Consequently, t

Piuias - Pii;T1-1Pi-1 v p1uiTi-1P1,

i

u, asp, u,p,T;-1Pi-1 v utiiTi-1P1•

and

The additional

(reserve)

� -, .. � - � � � � � �

�� �

bit circuit consists of a counter lip-lop and an input

cou tator implementing one switching function, where

po

is the counter input.

If there is no fault in the counter, then state

(0, 1 ) .

Hereby

bit is blocked,

a; = Pi-1

a1 = 0.

.

•

.

V

TnPn-1

1 and each fault flip-lop is in the stable

s in an ordinary counter. The input of the reserve

Let a ault appear in the i:th bit.

d

d=

a1 = T1po V T2Pl V

Then the diagnostic system will operate and

0 will be set. After this the localization detector will operate d= 0(T;, T;) = ( 1 , 0) will be set for the fault Hi-lop. The switching function of the additional bit should be a1 = Pi-1 and the switching function of the (i + l ) :th bit. the input of which hs been connected to the i:th bit, is a; = p9 • =

and

-

- 221 -

,I , i

! ,

•

I

I I !

I

I

i

I

I

'

..

·� '

I

l

e"

- .. I

l

I ·�

"

��

.. + c

'

__JJ

rr r � � ..,

o

_

__,

. ..

e

c

e

- 222 -

-

>

1

·'J .;

1

_

:: ... ..

J

�

�

_

� I

��

I

-

� I

..

- 223 A repair process •

is thus carried out and results in the replacement of the i:th bsic in the counter circuit by the reserve bit with the output Pg·

A.er a fault elimination, it may be necessary to reset the flip-flop (Ti, Ti) with the llitialization signal HY = 0.

• should be noted that if the i:th counter bit is faulty, then ; = 0 corresponds to = Pi = 1 and ai = 1 corresponds o Pi . Pi · The initial state of the additional it is ag = 0 and Pg . Pi. f the connection of the additional bit into the counter ccurs for ai = O, then this bit will not switch and ;+1 = 1. The phses of the dditional bit will consequently agree with the phses of the bsic counter bits, when the reserve is connected to the counter. The transition process interrupted y a fault will then terminate the indicator swtiching and the f.ult signal d = 1 -ill be reset, which will indicate the termination of self-repair. The process may be incorrect from the point of view of the inormation, since the inormation written into the additional bit might not coincide with the information which should be present in the i:th bit. Therefore, it is necessary to repeat the counting after the ermin.tion of the self-repair.

i

The method introduced makes self-repair possible for any single conservative fault. Single conservative faults in localization detectors will in no way afect circuit oper­ ation, since these loclization detectors start operating only after the appearence of a fault in the circuit (in the functional or switching parts of the circuit) . No local­ ization detector faults can, thereore, be self-repaired with the introduced methods. On the other hand, a fault setting (Ti, T;) to the state (1,0) despite the absence of a fault in the bit leads to the connection of the additional bit in parallel with the current normal processes in the counter. This may cause an erroneous unindicatable situation. In other words, single mutational faults in localization detectors lead to circuit operations errors. This drawback can be eliminated by implementing the switching function ai = dli-1 V d(Ti-lPi-1 V T;-1pg) - No faults in the localization detector (multiple, con­ servative and mutational) will for such a switching function implementation disturb the correct operation of the functional part of a self-repairable counter, if of course no faults are in the switching and functional parts of the counter cells. The advantage of the self-repair method based on a general reserve is the uni­ versality, as the method can be applied for arbitrary cell intercommunication in one-dimensional s well as in multidimensional structures. Another method is bsed on the utilization of sliding redundancy. In case of a defect the faulty cell is "shunted" by logical means, i.e. the cell is simply "extracted" from the structure. This method is convenient to use only in case of regular and moreover

- 224 one-dimensional structures. The advantage of this method is the total similr:] 6 all cells, both basic cells and reserve cells, s cells in a general reserve at the 9 time have more complex commutators than bsic cells have. A block diagram of the organization of self-repair bsed on sliding redund�� shown in Fig. 7.13 for the cse of a linear one-dimensional structure. The in9 of each i:th cell are normally connected only with the outputs of the (i 1 cell. After the localization of a detect that has occurred in the (i 1) :th cell. M commutator K; will connect the outputs of the ( i- 2) :th cell to the inputs of the s � cell. The commutator Ki implements an ad hoe example function ; = '1- i.-l T1 -1>1-2, and the circuit of a self-repairable counter with sliding redundancy ffn from the circuit in Fig. 7.12 only in that the signal >1 -2 (instead of p1) becoms • input to the i:th cell. -

-

- 225 -

u

- 226 8

Comments on the Biblio graphy

Chapter

2

The concept of an synchronous process is proposed in

(

[2.3].

The ormalisms cl:

)

12.: :

to this rather learning towards theoretical programming topics are given in and

[2.18]. [2.5]

The equivalence clss concept is in fact adopted in

5.).

(more in detail in chapc [2.19

The model later called Petri nets was irst proposed by C.A. Petri

This model became a subject of proound and wide-spread investigations and t!

as a matter of fact become an independent research direction. A detailed surve. of the basic results in the theory of Petri nets is given in

[2.18].

A merit of tb

survey, which contains a vst bibliography, is the possibility to get acquainted wi•= the topic on an informal level. A considerable amount of Petri net research w�

done in USA within the ramework of the MAC-project in Massachusetts Institut� of Technology, where this research ws connected to system development and ­ automata theory, and in Bonn

(FRG ) , where this research developed in a directio.

of creating a more general and abstract Petri Net theory. The Petri net researc: in Bonn is described in more detail in

[2.19].

Later on a considerable geographic.

spread of this research hs occurred outside the limits of the mentioned centres. A survey of French research on Petri nets and closely related topics is given in Petri net research in the Soviet Union is reported in Research of marked graphs is reported in

[2.9].

[2.s:.

[2.3,2.4,2.6,2.7].

The signal graph concept introduced

in this report difers rom the interpretation accepted in back to the switching table proposed by M.A. G.vrilov

[2. 10] but goes conceptually [2.2].

The formalism here called the Muller model is the work of D. Muller and his fellow The formalism is also reviewed in

[2.5] .

The presec.ted notion of parallel synchronous low-charts is given in

[2.5] .

researchers

[2. 12,2 . 13,2.14,2.15,2.16].

This

ormalism is . modiication of the famous language of low-charts in order to be able to adequately describe synchronous processes.

Chapter

S

The possibility to use codes with equal weights

(balanced

of circuits with unbounded delays ws irst shown in

[3.11].

)

codes

in the design

The authors of this

report did not - unfortunately - ind out that double-rail codes are simplest subclass of codes with equal weights and can be esily implemented. A double-rail representation was irst investigated in

[3.10]

and used in

[3.1]

but also in

[6.8]

where

the corresponding codes are called autosynchronous. Similar coding systems have

- 227 �een used in the research on technical diagnostics (see Chapter 7 for details) . Codes >-ith indentifiers are also called Berger codes [3.8]. The result of Theorem 3.3 or more precisely the fact that the maximal number incomparable vector pairs contains optimal codes with equal weights, ws first obtained in [3.4]; the proof is based on the research reported in [3.12]. The authors attention was drawn to this by J .L. Sagalovich. �r

The direct transition encoding utilizes a modification of the racey method [3.13] , described also in [3.2]. The material in chapter 3 has been published in [3.3,3.5,3.6,3.7]. Chapter 4 The idea to implement Petri Net ragments with standard modules (according to events ) is expressed in [4.8] and [4.10]. A group of French researchers working in the Aero-Space Research Centre in Toulouse proposed a set of hardware modules and a technique providing Petri Net implementation by a network such modules [4.5], � 4 .7] and [4.12]. It should, however, be pointed out that the authors of these reports did not try to provide the obtained implementations with a membership in a class of �emimodular circuits. Immediate use of their results thus happens to be impossible . \evertheless, the design of one of these modules, the so called David elemen [4.5], ns been modiied and an asynchronous distributor [3.2,4.1] has been proposed as a result of this modiication. Another ( hypothetical) module set ( a circuit imple­ mentation of these modules can apparently be obtained, if the same interpretation, which has been used for the implementation of conditional Petri nets, would be applied ) has been considered in [4.6] . Approaches to the implementation of parallel synchronous flow-charts and pipeline processes have been proposed in [3.2] and thereafter developed in [2.21]. The multiple operation block construction (repeated initiation) which has been improved rom that of [3.2] is given in [4.2]. The present functional completeness concept difers rom the generally known cor­ responding concept, although there is no contr.diction. The results of this section have been published in [3.2,4.3,4.4] and are bsed on the speed independent circuit classiication described in [2.5]. A set of universal speed independent modules (with memory ) has been proposed in [4.9], where also a question hs been raised concerning the possibility to cut down the number of modules and, more generally, to decrease the number of inputs and outputs. Another (suiciently cumbersome) implementation method is proposed

- 228 in

[4. 1 1] ,

but this method does not guarantee the semimodularity of the synthesized

circuits with respect to variables, which are not encountered in the initial diagram.

Chapter 5 The analysis of the operation of synchronous parallel systems bsed on earlier ex­

(rather oriented towards theoretical programming problems, how­

amined models

)

ever is the research topic in many reports. Among these can be mentioned papers on the analysis by Petri nets

[2.4,5.7,5.8], and

by labelled transition systems

(models relating closely to an synchronous process [2. l]).

tion can be obtained from surveys and

[2.8,5.3,2.19]

[2.11)

More complete inorma­

and thematic report collections

[5.9]

[5. 11] .

Various circuit analysis topics diferent rom those contained m Chapter

treated in

[5.lj

and

5

are

[5.2] .

Research on analysis of speed independent circuits conducted by D . Muller is re­ ported in

[5.4]

and

[5.5].

Solution methods or forward and backward state reachability problems are inves­ tigated in

[4.9]

[5.l].

gives an approach t o the design o f circuits, the operation o f which is indepen­

dent of wire delays. This approach is based on the use of a set of universal modules. Circuits consisting of such modules do not depend on the operation speed of the modules and are insensitive to intermodular wire delays. The shortcoming of this approach is the bulkiness of the obtained circuit solutions and, most of all, that the operation of the modules depend on the delays in constituent elements and on intramodule wire delays. The growing inluence of wire delays with a higher circuit integration level is exam­ ined in

[5.10].

Topics related to the analysis of switching circuits with the aid of a special sort of Petri nets are investigated in

[5.6].

Chapter 6 The first remarks on the diiculties ssociated with solving arbitration and syn­ chronization problems were apparently made in

1966

in

[6.3]

and

[6.10].

A large

quantity of later research ws dedicated to the collection of experimental data about the "anomaly" in the behaviour of various devices

[6.5,6.7,6.13] .

Statistical treat­

ment of the obtained data carried out by some researchers shows that anomalous behaviour of arbiters and synchronizers is an essential source of faults in computing systems

[6.12).

Recommendations concerning the architecture of computing sys-

- 229 ems aiming at a lower probability of faults because of anomalous behaviour are also presented in [6.12]. Arbiter and synchronizer designs are proposed in [6.9], [6.14] and [6.16]. The circuit Fig. 6 .6,a is proposed in [6.16]. An attempt to design a bounded arbiter based on :he circuit solution in Fig. 6.12,a is mde in [6.14]. The results in Section 6.1-6.4 correspond to [6.1]. The concept of a safe inertial delay is closely related to the concept of an ideal inertial delay [6.15]. Circuits with inertial delays re proposed m [6.8] . The circuit in Fig. 6.10 is proposed in [6.15]. n [6.2] and [6.15] is established a relation of the problem of designing ideal arbiters and synchronizers with a limited answer time to the problem of designing an ideal inertial delay. In [6.11] is shown .or a wide clss of dynamic systems that a short enough input pulse can be chosen :bat results in system entering a anomalous state. This result is a strong argument n favour of the impossibility to implement . limited synchroniser, n ideal arbiter and a safe inertial delay.

:n

Chapter

7

n informal definition of an .periodic automaton and of some structural models for such an automaton hs been proposed in [3.2,7.2,7.4,7.5]. A definition of a matched automaton has been proposed in [2.5] and specified in more detail in [7 .9].

The indicatability concept and an approach to the synchronous circuit indicata­ bility analysis are given in [7. 7] . The concept of a Boolean unction derivative is :.ised in {7.19]. The methods for indicating completion of transition processes in a circuit are bsed on an invention [7.1] and on n idea of D. Muller [2.5] . Hazard-free aperiodic circuits are treated in [3.2,7.6] and [7.12] . The concept of totally self-checking circuits is proposed in [7.14]. Many research works, among which [7.13] and [7.20] are usually especially mentioned, give syn­ :hesis methods for circuits having such properties. They give bsic deinitions and >roperties of totally self-checking circuits.

The design methodology for self-checking devices with memory ( automata) is far :ss developed that that of combinatorial circuits. Basic structural peculiarities of such automata were irst investigated in [7 .20] . A formal definition of totally self­ :hecking automata bsed on the results in [7.20] hs been given in [7.16] and more >recisely in [7 .15]. The most complete exposition of topics related to self-checking n (synchronous) circuits is found in [7.8] and [7. 11] . Attempts to synthesize asynchronous circuits belonging to this class have been made :n [7.10] and [7.15] . However, the separate solution to the problem of struggle with

- 230 hazards and diagnostics hs predetermined the bulkiness of the proposed solutions. The diagnostic properties of aperiodic (semimodular) circuits have been emphasized in

[2.5,3.2,7.17]

and

[7.18].

The fault detection method is bsed on a technical

solution which is protected by an invention certiicate

[7.3].

References

[2.ll

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