Handbook of Integrated Circuit Industry [1st ed. 2024] 9819928354, 9789819928354

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Yangyuan Wang Min-Hwa Chi Jesse Jen-Chung Lou Chun-Zhang Chen Editors

Handbook of Integrated Circuit Industry

Handbook of Integrated Circuit Industry

Yangyuan Wang • Min-Hwa Chi • Jesse Jen-Chung Lou • Chun-Zhang Chen Editors

Handbook of Integrated Circuit Industry With 1014 Figures and 203 Tables

Editors Yangyuan Wang Institute of Microelectronics Peking University Beijing, China Jesse Jen-Chung Lou School of Software and Microelectronics Peking University Beijing, China

Min-Hwa Chi GTA Semiconductor Co., Ltd. Shanghai, China Chun-Zhang Chen Peng Cheng Laboratory Shenzhen, Guangdong, China

ISBN 978-981-99-2835-4 ISBN 978-981-99-2836-1 (eBook) https://doi.org/10.1007/978-981-99-2836-1 Jointly published with Publishing House of Electronics Industry. The print edition is not for sale in China (Mainland). Customers from China (Mainland) please order the print book from: Publishing House of Electronics Industry. Jointly published with Publishing House of Electronics Industry, Beijing, China. © Publishing House of Electronics Industry 2024 This work is subject to copyright. All rights are reserved by the Publishers, whether the whole or part of the material is concerned, specifically the rights of reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publishers, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publishers nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publishers remain neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore Paper in this product is recyclable.

Preface

(The preface of “The Handbook of Integrated Circuit Industry” used here, is a translation of that from its 2018 sisterbook in Chinese.) Penning Past and Present: A History of The Handbook of Integrated Circuit Industry Yangyuan Wang

Writing and compiling The Handbook of Integrated Circuit Industry has been of special significance for me and my colleagues. After graduating from universities, we have all been engaged in the field of integrated circuit and have established a lifelong bond with it. Like members of one big family, we share the same aspiration, which is to work innovatively and use the newest technologies in the integrated circuit as a cornerstone to pave the way for the great rejuvenation of the Chinese nation. “He who pursues truth today gains most from classical wisdom.”

“He who pursues truth today gains most from classical wisdom,” thus pronounced Wang Fu, a thinker of the Eastern Han Dynasty (AD 25–220), in an essay called “In Praise of Learning” in his work Thus Speaks a Hermit. This reveals how important the role of classics is in learning, inheriting, and innovating in education and career development. The purpose of compiling The Handbook of Integrated Circuit Industry (or The Handbook) is thus to make it a “classic” that not only meets the demand but also promotes the innovation in the field of integrated circuit. It all started from the beginning of 1992, when a group of young people, all from the Division of Basic Products, Ministry of Mechanical and Electronic Industry, proposed to compile a book of this kind. Among them were Minzheng Zheng, Xiaotian Xu, Xian Chen, and Yongwen Wang from the Departments of Integrated Circuit and of Science and Technology. Driven by the needs of the IC industry and the implementation of its major projects at that time, their initiative won the immediate and enthusiastic support of the Division and the Ministry. A panel of more than 100 young and middle-aged scientists, technicians, engineers, and project managers were accordingly organized top-down, and I was made Editor-in-Chief. A year’s collaboration eventually led to the publication of the Handbook in April 1993 by the Electronic Industry Publishing House. Qili Hu, then Minister of Mechanical v

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and Electronic Industry, calligraphed the title of the Handbook, and Peiyan Zeng, then Vice-Director of the National Planning Commission, prefaced it. It was favorably received by the profession, in the field of science and technology, and among the educational circles. More than 20 years had passed, and it was still in demand though it had long been out of print. As is stated in the “Editor’s Note” in the Handbook, “This book serves as an handbook of integrated circuits, covering not only the technologies and economy related to these technologies, but also the management and construction of the industry. It can be used as a handbook by administrators at various levels of the industry as well as by front-line corporate executives, engineers and technicians for their regular reference, with an aim to facilitate their decision-making in line with professional rationale. It can also be used as a teaching guide for educators so that students they cultivate can fully grasp the traits and rules of the industry besides learning knowledge of the field. In the mean time, the Handbook also serves as a convenient reference for scientists and technicians exploring information while engaging themselves in research.” This was our original aspiration. Time goes on and 25 years have passed. The form, size, and level of science and technology and of the IC industry have undergone constant change and have made tremendous progress. For example, the 1993 edition was able to project the scale of the industry only as far as the year 2000, envisioning a level of technology reaching 0.12 μm/300 mm silicon integrated circuits, but this was surpassed as early as the beginning of 2000. Some projections of device development have become true, while others have not, as certain new configurations of the IC devices, especially multi-gate and all-around gate, failed to be recognized back then. Nowadays, these new devices with high performance and low power consumption have been industrialized and become a core competitive force in large-scale production. This makes it urgent to compile a new edition of the Handbook to meet the needs of the development of the modern IC industry. The initial aspiration has remained unchanged, but we must continue to move on. How time flies! The young talents of the team who nurtured the birth of the 1993 edition have reached their 70s. Yet, despite their age, they are still staunch proponents of the new edition and they played a central role in its remaking. And I, an octogenarian, inspired by these old colleagues, also joined in. However, with the deepening of reform and the transformation of government functions, it is all but impossible to accomplish this new edition in the same top-down manner as it was with the 1993 edition. Therefore I proposed to the National Advisory Committee on the Development of the Integrated Circuit Industry (or National Advisory Committee) and the Ministry of Industry and Information Technology (or MIIT) on August 31, 2015, to compile A Series of Books on the Integrated Circuit (or The Series). An upgraded version of The Handbook of Integrated Circuit Industry would be the first volume of the Series. The proposal found favor with both the Committee and the Ministry. With the needs of industrial development, the active participation of the colleagues, and the enthusiastic support of the leadership, it was time for us to “set sail for the high seas.” On February 26, 2016, I chaired a meeting in preparation for the Editorial Committee of the Series and the Handbook in Southern University of

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Science and Technology in the city of Shenzhen. We brought forth an overall plan for the compilation of the Series and the Handbook and proposed a list of nearly 100 scientists as the first panel members, on the basis of the group members who had participated in the discussion on the strategic planning of the academic and industrial development of microelectronics. This new Handbook was to be divided into 10 chapters. Experts and authorities in the related fields were invited to act as chief and deputy chief editors for each chapter. Recommendation was made that an executive editor be further appointed for each chapter to assist the chief and deputy chief editors. The whole Handbook was designed to cover about 1000 entries, with an average length of about 1000 words for each entry. Together with all the graphs and tables, the Handbook would be a tome of 1.2 million to 1.5 million words. We also laid down that the headword of each entry was to be provided in simplified and traditional Chinese as well as in English. Though the body of the entry was to be in simplified Chinese only, this did not mean that there would be no room for future expansion. The idea was to provide standard and uniform terminology for the various realms of the IC industry so as to facilitate future academic exchange both home and abroad. On April 6, 2016, the Preparatory Committee of the Series and the Handbook issued a “Letter of Inquiry” to more than 100 experts in the IC field in China. Most experts responded with enthusiasm and showed support for the work. They agreed to serve on the Editorial Committee and recommended more experts to join in. Consequently, on April 26, 2016, MIIT’s Division of Electronic Information announced, on behalf of the Secretariat of the National Advisory Committee, a call for conference to members of the Editorial Committee. The conference took place on May 7 in Beijing, chaired by Deputy Director Hongbing Peng and others of the Division of Electronic Information. They announced the official establishment of the Editorial Committee, and I was to serve as Editor-in-Chief. On behalf of the Secretariat of the National Advisory Committee, letters of appointment to members of the Editorial Committee attending the meeting were presented. After offering an overall appraisal of China’s IC industry, attention was called to the country’s “pressing need for talent cultivation, which made it an opportune moment to initiate the compiling of the Series and the Handbook.” Also called for was a strong sense of honor and responsibility among all the editorial members for the compilation, urging them “to keep pace with the time and stay in close touch with the industry” and to bring forth an Handbook “with full coverage and scientific accuracy.” At the inaugural assembly of the Editorial Committee, I quoted Gorky to illustrate the importance of our compilation: “Books are the ladder of human progress.” I also believe books are, as that well-known ancient Chinese poem says, “just rain that knows the season and comes with the spring. It steals on the breeze into the night, and moistens all things softly without sound.” Books are the potential and powerful drive behind industrial development, talent growth, and cultivation of personal integrity. They are also an essential part of the cultural construction of the IC industry. Regarding some of the important questions in the compilation, I made the following points:

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1. Writing is serious work. Knowledge must be created on the basis of learning and inheritance, so as to promote the progress of humanity and the development of science, technology, and the IC industry. Learning, inheritance, and innovation entail an arduous course of hard work in their own right, allowing no expediency or opportunism. “Topless is the mount of learning, but we scale it by the path of diligence; boundless is the sea of knowledge, but we sail it by the boat of assiduity.” 2. Respect others’ intellectual property as we respect our own. No plagiarism or “suspected plagiarism” is allowed anywhere in our work. We must be aware that the slightest academic misconduct at a single point or in a single entry will ruin the whole book and the whole Series, as well as spoil the achievements and reputations of all those who contribute to the compilation. This therefore will be a most important focus in our future review of the drafts. Any quote must be specified of its source, and we will later seek permission collectively from the proprietors of the copyrights concerned. Indication of the sources is required even in the case of snippets of remarks from the Internet, which should be documented in the reference section after the entry. 3. Humans are the messenger of knowledge, but human life is too short and limited to be able to make more than a splash in the long river of history. Even though colleagues here today can at best lead the research on integrated circuits for a couple of decades, our words, the works we produce, will last longer. They will have a much longer life and will exert more enduring influence than we do. No matter how fast science and technology develops and how rapidly the industry upgrades its various aspects, the philosophical inquiry and exploratory spirit embodied in our scientific writing will have a far more lasting impact on future generations to come than knowledge itself. “Much of what happened in the past and present is to be found in writings.” All our contributors will find themselves holding a heavy pen and bearing a historical responsibility. After the establishment of the Editorial Committee, the writing of all the chapters of the Handbook began. Plans for individual publication of the Series as monographs were also under way. Up to December 31, 2016, the preliminary drafts of all the chapters had been completed, with the number of entries reaching 1126, totaling about 1.8 million words by 276 contributors. In order to ensure the quality of the writing, we finalized a list of chief, deputy chief, and executive editors for all the chapters and supplemented new editors in answer to the actual progress of the project. After a self-review by the editors of each chapter, we organized the first draft review meeting in Shenzhen from February 19 to 24, 2017, with the support of the Shenzhen Industrial Base for Integrated Circuit Design and Shenzhen Guowei Electronics Co., Ltd. Prof. Yongwen Wang, Deputy Chief Editor and SecretaryGeneral of the Editorial Committee, addressed the meeting on behalf of the Editorial Committee on the progress of and problems existing in the writing. The results of the first review sounded an alarm to us, with duplicate checking greatly exceeding the standard, aberrations in the writing widely evident, and plagiarisms or “suspected plagiarisms” spotted in many places. Some contributors

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even copied and pasted materials directly from the Internet bearing the original logos into the entry they wrote. This is an act we firmly oppose and strictly prohibit! This is absolutely intolerable! In view of this, I demanded with gravity that the attendees of the meeting ask themselves the following questions: In writing the entries, did we work innovatively on the basis of our own learning and inheritance? Do the entries have independent intellectual property rights? Have we offered new knowledge to the reading public? Have we honestly documented and cited the research work of others and included them in the reference? I reiterated at this meeting that we should always keep the bottom line of academic integrity. Writing is the same as living our life and building our career; absence of integrity will get us nowhere. For this reason, in the minutes of the meeting, we demanded that every editor, contributor, and reviewer abide by honesty as the fundamental principle. At the same time, we offered counsels to inexperienced young scholars on the proper way to write entries, i.e., how to write independently and innovatively through learning, digestion, and absorption and how to quote others’ work and expositions from the Internet correctly. This they could do by properly noting the quoted words, phrases, sentences, and paragraphs and listing the sources in the reference. This process, in essence, is a process of educating and training young scholars in the discipline of writing. For drafts which failed the duplicate checking, the Committee requested that they be re-examined by their respective chapter editors. Stimulated by this, the Committee also decided to examine the Handbook entry by entry and chapter by chapter for the second review. The 3 months between the first and second reviews was the first critical stage for the writing and improvement of the Handbook, in which all the contributors and organizers reprocessed the preliminary draft in the spirit of “originality first, quality first.” When the second review came, the total number of contributors and reviewers involved surpassed 500. It was simply hard work to unify the ideas and standards of them all. Nevertheless, we repeatedly stressed that this Handbook was to be a stupendous undertaking by more than 500 experts who, through their collaboration, aimed to yield a serious academic product that should be able to stand the test of time and professional challenges from all over the world. It would not allow any relaxation or academic irregularity. Each contributor and reviewer should be responsible for themselves, for all the other contributors, reviewers and editors, as well as for the future of the IC industry. We must adhere to the bottom line of honesty and reliability. From May 7 to 31, 2017, with the support of Semiconductor Manufacturing International Corporation (SMIC) and Huada Semiconductor Co., Ltd., the second review and duplicate checking of the Handbook were successively carried out in SMIC, Shanghai, and Wanshou Hotel, Beijing. It was a painstaking yet touching enterprise which manifested the strength of China’s scientific core force. Loyal and dedicated to the country’s IC industry, they were the hope for the thriving of our cause.

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On these two meetings, editors, contributors, and reviewers worked with conscientiousness and responsibility. Obvious inaccuracies and discrepancies in the first draft were corrected, and the quality of the second draft was greatly improved. The second review turned out to be a process of entry-by-entry duplicate checking and examination of more than 1000 items. It was like gold panning in which one “sweeps and sifts the sand until gold peeps through the blown dust.” Entries like “mixed mud and sand” had to be sifted and filtered repeatedly until the good “gold extracts” appeared. It was worth it though, because that was why we launched the enterprise in the first place. A lot of touching things happened during the second review. First of all was that the chief and deputy chief editors of each chapter took serious note of the revision. They attended the two-day review meeting in person and listened to various opinions. After returning from the meeting, they organized their editors, writers, and reviewers to make improvements and give timely feedbacks. Yuan Pu, Executive Editor of Chap. 8, came all the way from the United States to Shanghai to participate in the review and did not return to the Silicon Valley until after the review was over. Weiping Liu, editor and reviewer of Chap. 5, came to the review in no time upon notification of revising the entries he was in charge of. He took the drafts back and worked on them overnight until two o’clock in the morning. They passed the next day’s review smoothly. Here I would also like to express my special thanks to the four Deputy Chief Editors of the Handbook, Yongwen Wang, Xian Chen, Min-Hua Chi, and Jesse Jen-Chung Lou, for their full participation in the second and final reviews, and to Chun-Zhang Chen, the Under-Secretary-General and Dr. Jian Cao from the Secretariat, as well as the two editors from the Electronic Industry Publishing House, who worked 8–11 h a day for more than 20 days with high intensity. The review not only displayed the devotion of the participants to their work and their rigor, but also built a wonderful atmosphere of academic solidarity, mutual respect, and tolerance of different opinions. During the last 2 days of the review, Prof. Yongwen Wang was unable to eat because of gastrointestinal discomfort. Though he could only drink water, he persevered until the review was over. The spirit of science, democracy, solidarity, patriotism, professionalism, and integrity that all our colleagues exhibited during the review process was a valuable spiritual legacy for the furthering of China’s IC industry. I was deeply convinced that through the writing and compiling of the Handbook, we have come together as a team and that we are the backbone of China’s IC industry. During the two reviews, we had summed up the following tenets: Observe one bottom line of honesty and independent originality and give credit where it is due when quoting others’ work. Observe the two principles of firstly making innovations on the basis of learning and inheritance so as to offer new and updated knowledge to readers, and secondly separating the wheat from the chaff and extracting gold from sand.

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Observe the three directives of paying tribute to the old generations of predecessors, displaying worthiness to the current generation, and inspiring future generations by showcasing our philosophy and rationality in scientific development. Observe the four equal emphases on text and graphics, vertical (historical lineage) and horizontal (international breadth), market and technology, and on academic worth and popular utility. Observe the five-word precept: namely, trustworthiness, expressiveness, elegance, precision, and accuracy. Trustworthiness is about the norms of writing; expressiveness is about the ability to articulate; elegance means to show certain literary grace; precision means to be exact; and accuracy means to be correct. From July 14 to 27, 2017, with the support of the National Integrated Circuit Industry Investment Fund Co., Ltd., the final review of the chapters, appendices, keyword index, English-Chinese index, and the binding design of the Handbook was conducted. This was the third stage of the compilation. At this final review meeting, the Editorial Committee reported the results of duplicate checking. Through the collective efforts of the authors and reviewers of each chapter, based on a manual white-listing of the definitions, theorems, laws, special terms, policy/statutory documents that are declared immune from duplicate checking, and a sorting out the references cited, our duplicate checking was executed by PaperPass, currently the most astringent contrast system on Chinese document similarity. The result revealed that the repetition rate was zero in four chapters, less than 1% in another four chapters, and less than 1.5% in two other chapters. A consequent manual analysis found that duplicates were mainly due to the greater probability of the concurrence of some text descriptions, but these did not involve intellectual property rights. As we laid particular emphasis at this final review on fully respecting others’ intellectual property rights while protecting our own, we demanded that all references, charts, and data used in the Handbook should be authorized. To ensure the purity and authority of the Handbook, Jian Cao, Lele Jiang, and Xiaohai Xu were invited to take charge of the authorization. The Editorial Committee also decided to hire Xiaoqing Tian, full-time legal officer of the Electronic Industry Publishing House, as legal adviser of the Handbook. It was on the hottest summer days after 2.5 years of hard work that we finally brought the compilation of the Handbook to a close. It was like a toiling farmer tilling the land at high noon as one ancient poem famously describes: “With sweat dropping into the soil, he is hoeing away the weed at noon.” Indeed, for our Handbook, “Who knows but that every single [word] in it is the fruit of hard labor?” Every sowing has its harvest, and every harvest has to be won by hard work. When we got together again for the appraisal of the Handbook, we shared our serious discussions at the Preparatory Meeting, the deliberation of words while writing the entries, the joyful and bitter arguments during the review, and the sweet aftertaste when the compilation was over.

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Ours is a flourishing age. Our writing and compiling project is blessed with the privileges of the right time, the right place, and the right people. They are the proper conditions for making a canon. The right time means a prime opportunity. Technologies of integrated circuit have ushered mankind into the information era. And information revolution has created countless platforms for innovation in government administration, economic prosperity, national security and talent cultivation. The level of development of the IC industry has become an important index of the comprehensive strength of a nation’s power. The successive promulgation of the State Council Documents No. 18 [2000] and No. 4 [2011], the release of the National Integrated Circuit Industry Development Promotion Program, and the establishment of the National Integrated Circuit Industry Investment Fund have provided important opportunities for the country to develop its IC industry. As a result, China’s IC industry has taken off rapidly since the turn of the twenty-first century. In terms of technological development, the IC industry has entered a post-Moore era. New device models, design methods, processes, and packages are emerging, providing us with a wonderful opportunity for “innovative development.” Our role may be able to change from a “follower” to a “leader” in some areas. On May 28, 2018, General Secretary Jinping Xi said at the Academicians’ Congress of the Two Academies: “We must clearly realize that our intersection with history may sometimes produce historic resonance, while at other times we may simply pass it up.” He also stressed that “practice has repeatedly told us that the critical core technologies cannot be obtained by request, purchase, or entreaty.” We therefore should not pass up our historic encounter with the postMoore era and must keep in our grip the critical core technologies of the integrated circuit and push China’s IC industry to the middle-to-high-end level on the global value chain. Good place means that the environment is optimal. As China is the originator of the Belt and Road Initiative, many of our products are being launched in the world market. Ranging from high-speed rail, to smart phones, and regular products such as televisions and computers, the label of “Made in China” is shining brightly in the international market. China is also the largest consumer market of integrated circuits, providing enormous space for all kinds of IC products, no matter whether it is the high-end Beidou Navigation System or the more common consumer products. Being the second largest economy in the world, China has the ability not only to support the development of its own IC industry but also to digest all kinds of IC products from abroad. Whatever new forms of information science and technology and economy may take, such as AI systems, big data, Internet, Internet of Things, and cloud computing, they are still based on integrated circuits and systems and software. With the development of its information technology and economy, China is sure to become a powerful player in the IC industry. The right people are the key. General Secretary Jinping Xi stressed at the abovementioned Academicians’ Congress that “both hard power and soft power depend ultimately on people.” All rivalries in the world boil down to rivalry for talent. It was exactly with such talents as Xuesen Qian, Ganchang Wang, and Jiaxian Deng who developed the country’s first atomic and hydrogen bombs and man-made satellite

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that China won the right to speak in the international arena. It was with Kun Huang, Xide Xie, Shouwu Wang, and other pioneers that China began to delve into the field of semiconductor research. It was with the large number of home-trained scientists as well as scientists, educators, and entrepreneurs who returned from abroad that China created its own discipline of microelectronics, its first IC design system, its first 300 mm OEM production line, its special IC equipment for export, as well as this Handbook written by 468 people. As a crystallization of the energies of all the contributors, reviewers, and editors, the Handbook is a manifestation of the harmony among the right people. After the above three reviews, the plenary meeting of the Editorial Committee was held on July 27, 2017, and reached the following points of agreement: 1. The formal lists of the chief, deputy chief, executive editors and other editors of the adjusted chapters were adopted. 2. The drafts of all the chapters were approved after the final review. The chief, deputy chief, and executive editors signed their respective chapters in confirmation and formally submitted them to the Electronic Industry Publishing House. 3. In order to guarantee the authority of the Handbook, I proposed a two-month Objection Period after the final review. The chief, deputy chief, and executive editors of each chapter should send their chapters by e-mail to all the members of the Editorial Committee and other relevant professional authorities for comments. 4. The design scheme of the Handbook by the Electronic Industry Publishing House was adopted. Based on the opinions we had gathered by September, the Handbook was finalized and jointly signed in confirmation by the five Chief and Deputy Chief Editors of the Editorial Committee. In a short while, this crystallization of good timing, place, and people will be sending off its inky fragrance from the desks of the editorial members and the shelves of bookstores. When describing the arduous compilation of the Handbook, Deputy Chief Editor Yongwen Wang quoted a poetic stanza from the Qing-Dynasty scholar Guowei Wang’s essay of criticism Notes and Comments on Poetry: “All those in pursuit of great undertakings and great learning, ancient or modern, must of necessity go through the following three states. First, ‘the west wind having withered the green trees last night, the solitary man went atop the tall tower alone, scanning for path that leads to the end of the world.’ Second, ‘one’s girdle grows slacker with the day, yet one cares for none but his love for whom he pines away.’ Third, ‘Having searched a thousand times in vain for my love in the crowd, I, with a sudden turn of my head, spot her right in the shadow of the fading light.’” The first state was that of groundwork. On August 31, 2015, I proposed to the MIIT to compile the Series and the Handbook. On February 26, 2016, the Preparatory Meeting of the Editorial Committee was held at Southern University of Science and Technology in Shenzhen, at which a preliminary list of the Editorial Committee members was drawn up, a top-level design of the overall structure was made, and a

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specific work plan was adopted. On May 7, 2016, the Editorial Committee was formally established. Since then, the journey had begun of “the solitary man going atop the tall tower alone, scanning for path that leads to the end of the world.” The second state was that of engagement. Since May 7, 2016, all the writers had begun the first draft of the Handbook. On February 19, 2017, the first review meeting of the first draft was convened in Shenzhen. From May 7 to 21, 2017, the second review meeting was held in SMIC, Shanghai, and another was held in Wanshou Hotel, Beijing, from May 25 to 31, 2017. From July 14 to 27, 2017, the final review meeting took place at China Workers’ Home in Beijing. This means that over the 15 months from May 2016 to August 2017, writers and reviewers of the Handbook had entered the state in which “one’s girdle grows slacker with the day, yet one cares for none but his love for whom he pines away.” The second and final reviews were especially challenging. All the chapter editors, deputy chief editors of the Handbook, as well as members of the Secretariat devoted all their energy and effort, laying the foundation for a work which is authoritative, exact, professional, and up-to-date. As of September 2018, we will enter the third state of “searching a thousand times in vain for my love in the crowd and spotting her right in the shadow of the fading light with a sudden turn of my head.” Looking back on the difficult journey of the past 3 years, we will relish it with heartfelt gratification and will never recall this period of our life with regret. There is no end to progress; there is no stop to the fight.

When the Handbook comes out in 2018, it will fall on the 60th anniversary of the invention of the integrated circuit. Back in 1958 on his summer vacation, Jack S. Kilby analyzed various schemes, believing that there was no way out for further miniaturizing existing components. Only by integrating active and passive components on a semiconductor substrate could it be possible to really reduce costs, break free the predicament he was in, and head for a new prospect. Then he demonstrated on September 12, 1958, the first integrated circuit he designed and developed, which was a germanium-based phase-shifting oscillator. In October Kilby successfully developed germanium-based flip-flops, for which Texas Instruments applied for a patent on May 6, 1959. Then on July 30, 1959, Robert N. Noyce, co-founder of Fairchild Semiconductor Company, also developed his silicon planar integrated circuit by planar process and applied for a patent. Noyce’s invention was of the two more suitable for mass production. Both Kilby’s and Noyce’s contributions were recognized by the US government, and they were successively inducted into the National Inventors’ Hall of Fame. Flipping through the pages of the 60 years’ development of the integrated circuit, we find that it was essentially a history of innovation. The application of CPU, memory, and other inventions and innovations had brought about an information civilization. In 2000, the Royal Swedish Academy of Sciences awarded Kilby the Nobel Prize for Physics in recognition of his invention of the integrated circuit. Noyce’s early death in 1990 made it impossible for him to win the same prize.

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When Kilby was invited to visit Peking University in 2001, he said to me, “I knew the integrated circuit I invented was useful, but I never expected it to be so useful.” Yet the rapid development and wide application of the integrated circuit over the past 60 years were only natural given its very nature. Having expanded into integrated systems, it now incorporates functions of information acquisition, processing, storage, transmission, and random execution into one single tiny chip and can be manufactured in large quantities with high reliability and low cost. Because of its high price-performance ratio, good reliability, and great ability to process information, the all-pervasive integrated circuit has found extensive use in various civil and defense military systems. Like cells that make up the human body, it has become the basis of various information systems. While it certainly cannot work without software, the growth of software technology springs from demand for applications, and the integrated system which ultimately fuses software and hardware can lend support to the developing of various information systems. Therefore, nowadays the IC industry has inevitably become the foundation of the national economy and defense system. It is where the core competency of a country lies, and one of the indexes to a country’s comprehensive strength. At the same time, with the reduction in the feature size of integrated circuits, 7 nm circuits have entered into small-batch production, and 5 nm/3 nm integrated circuits have also begun to be developed. Some people thereby believe that this is about the limit of device physics, claiming that the days of integrated circuits are numbered and that their future is doomed. This is a grave misconception, because in the postMoore era, the practical meaning of feature size has changed. If we change our mindset and measure the progress of integrated circuits and systems by reducing power consumption, improving performance and the power/performance ratio, we will, just as an ancient Chinese poem spells out, enter a new realm where “in the midst of the overlapping mountains and winding rivers, one doubts whether there is a way out, yet dark willows and bright blossoms reveal another village ahead.” This is the first feature of the post-Moore era. At present, the integration of the integrated circuit has reached 1011 transistors. The power consumption of a single unit is only a few picowatts (pW), with an area about 100 nm2, which is smaller than a human cell. It can even be embedded in the human body, human brain and various artificial intelligence devices, thus opening a whole new field of innovation. Information is the most active factor of all factors in the information era. Mastering and utilizing information is a revolutionary innovation. Information and its utilization system will penetrate all fields of science and technology, as well as all aspects of human life and production. Thus it is clear that the development of the integrated circuits and systems has only just begun and that the future is limitless. Even the industrial production of silicon integrated circuits will not shrink in the short term. It will exist in the twentyfirst century and the century beyond. Of course, its materials, processes, device structures, and packaging forms are constantly improving and innovating, just as the aircraft invented by the Wright brothers back in 1903 is still progressing rapidly after more than a century. Likewise, the train was invented in 1814 and has had a history

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of more than 200 years, yet it still needs to be developed into new means of highspeed transportation. China’s integrated circuits still have a long way to go. Since the 18th National Congress of the Communist Party of China held in 2012, the country’s integrated circuits have been developing at a high speed. The average growth rate over the past 5 years is 2.7 times that of the world growth rate. Yet, there still remains the problem that the core technologies are not in our own hands. We must therefore fully grasp the dual properties of the integrated circuit in strategic significance and market value and keep its sustainable growth by its own objective laws. We should rid ourselves of all impetuosity, remain determined, and make steady, rapid, and orderly headway. The IC industry is capital-, technology- and talent-intensive. Ever since the establishment of the National Integrated Circuit Industry Investment Fund, there have been signs of gradual increase in capital flow. But the key still lies in talent. Capital ultimately calls for talent. Scientific and technological innovation is the result of human creativity supported by capital. Only when combined with talent can capital work magic. The shortage of talent is the biggest obstacle to the development of the integrated circuits in China. The country’s opening up to the world has attracted talent from all over the world to invest, start business, and seek opportunities in China. But in the end, we have to depend on ourselves for the cultivation of high-quality talent who can take it upon themselves to meet the country’s strategic requirements. We welcome more entrepreneurs, particularly leading talent in the chain of the IC industry. To this end, we must deepen our reform across various fields such as the existing talent-evaluation system, disciplinary distribution, faculty building, curriculum system, and better merge teaching with industry. We must upgrade the discipline of Microelectronics and Solid-State Electronics from a Grade-2 Discipline to Grade-1 (tentatively named “Micronanoelectronics Science and Integrated Circuit Engineering”) and adapt it to the national strategic needs and market development. A sufficient talent supply serves as the only means of achieving the grand goal of building a strong and modernized socialist country. To achieve breakthroughs in key technologies, we should first give support to universities and research institutes to carry out basic research. Second, we should vigorously support enterprises to carry out their R&D. Third, we should emphasize the fusion of industrial application with teaching and research, establishing an industry-university-research alliance. Only by persistence and perseverance can we truly grasp the key technologies in the IC industry. Ever since the outbreak of the Opium War in 1840, the Chinese nation had gone through numerous historical hardships and difficulties. Now, under the leadership of the Communist Party, it was reborn from fire and is quickly striding towards prosperity and revival. In this information age, China is to take integrated circuit and software as its support for furthering the sustainable development of its national economy, achieving the Two Centenary Goals put forward by the Communist Party’s Central Committee and building a strong, beautiful, democratic, civilized, harmonious, and modernized socialist power.

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Today, The Handbook of Integrated Circuit Industry has been written and compiled in this spirit. In the future, we will continue our compilation edition after edition. When the time has come for the next compilation to be made, I may not be the Editor-in-Chief, but the younger generations will certainly carry on. General Secretary Jinping Xi said at the Academicians’ Congress: “The youth are the prospect of the country, the hope of the nation, and the future of innovation.” There is no end to progress and there is no stop to the fight. I believe younger generations will surely do better than us, just like the waves of the Yangtze River keep driving on those ahead, each higher than the ones ahead. During the writing and compiling of the Handbook, our contributors and reviewers were very diligent and conscientious. The chief editors of each chapter organized reviews and revisions of their chapters many times, and the Editorial Committee convened three review meetings. The second review was the most rigorous of all as it inspected and revised the Handbook chapter by chapter, entry by entry over a period of more than 6 months. When it was finally completed, the Handbook had gone through six revisions. It is fair to say that we have done our best. Still, we must allow that every contributor is a product of his time and place. His knowledge is certainly limited; his writing may be inadequate, even incorrect. We hope readers will not hesitate to criticize and correct the mistakes wherever there are and offer suggestions for future improvement and reprinting. As I said at the founding meeting of the Editorial Committee, we would pay close attention to the feedback of the readers after the publication and consider bringing out versions in traditional Chinese and English in due course. So there is still room for improvement and development. There are also drawbacks in the overall planning of the Handbook. For one thing, the Handbook has not listed the management of the IC industry as an independent chapter, though it is a great subject on its own. It is where efficiency and productivity come from, especially when we are now in the middle of deepening the reform. While almost all universities have management schools and there is a wealth of management talent, both experience and talent in writing have yet to be accumulated as far as management of the IC industry goes. In the case of our Handbook, the content related to management is scattered over chapters. With the Series, however, we have listed “Management of the Integrated Circuit Industry” as a single volume, hoping to present a monograph on this subject. Similarly, we have not been able to set industrial development, education, and talent training as a separate chapter. Even if we have, education, as a constant concern of human society and basis of social development, cannot be dealt with properly by a single chapter in our Handbook. A look at the history of the IC industry shows that it always develops first in places where education is advanced and talented people are gathered, such as the Silicon Valley of the United States, Zhongguancun of China, and Tsukuba of Japan. The links between the two are worth pondering. For this reason, we have listed education and talent training as a separate volume in the Series. It is hoped that the above shortcomings will be remedied when the Handbook is reprinted. There is no such thing in the world as a thorough text, a complete book, or a perfect person. I know

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problems and shortcomings are inevitable, especially when the writing styles of 468 authors and 125 reviewers are so very different. “The sea refuses no river. It is huge because of its capacity.” It is of great benefit for readers to allow different academic viewpoints to exist under unified rules. I sincerely hope that readers will not only tolerate but also point out the shortcomings, problems, and mistakes in the Handbook so as to help us produce better editions in the future. Acknowledgments Finally, I would like to thank all the administrators, enterprises, entrepreneurs, scientists, technicians, engineers, and publishers for their support for and participation in the writing, compilation, and publication of the Handbook. Without the support of the National Advisory Committee and its Secretariat, as well as the MIIT (especially its Division of Electronic Information), this Handbook would not have been possible. It was also the result of the joint efforts of 468 writers, 125 reviewers and editors. They are the backbone and mainstay of China’s IC industry and the country’s development in science and technology. We should cherish their enthusiasm and safeguard their intellectual contribution as we protect our own eyes. Just as the Confucian scholar Xi Zhu of the Southern Song Dynasty (1127–1279) says in a poem, “Why does the pool remain so clear? For running water keeps flowing in from its source, keeping it alive and fresh,” it is the trickles of these people’s dedication that makes the river of originality flow forever. I would also like to express my special thanks to Southern University of Science and Technology, Shenzhen National Integrated Circuit Design Industrial Base, Shenzhen National Microelectronics Co., Ltd., SMIC Co., Ltd., Huada Semiconductor Co., Ltd., National Integrated Circuit Industry Investment Fund Co., Ltd., and Beijing Huada Jiutian Software Co., Ltd., among others. They have generously supported the convening of the preparatory meeting, the three review meetings, and the acceptance meeting of the Handbook. I would also like to thank the Institute of Microelectronics and Nanoelectronics, Peking University, for its generosity in obtaining copyright licenses for data, charts, and all the references, thus enabling our Handbook to have complete intellectual property rights. Pertaining to this, I would also like to thank all the members of the Secretariat of the Editorial Committee for their hard work in duplicate checking, copyright consultation, and conference organizing. My sincere thanks also go to Editor-in-Chief Jiuru Liu, Senior Editor Jian Zhang, and Associate Senior Editor Haiyan Liu, of the Electronic Industry Publishing House, for their full participation, close cooperation, and effective coordination in transforming the drafts into the Handbook. The elegant design proposals they offered are pleasing to our eyes. We hope the Handbook will become “a classic of this flourishing age” in China’s IC library and bring good luck to the compilation of the Series. I hope the Series will continue to emerge as a spring of wisdom and culture and be with us all our lives to nourish the continuous development of the IC industry and science and technology in our country. The innovative growth of the IC industry and its related science and technology in China will surely make a unique contribution characteristic of the Chinese nation to

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the continuous expansion of the global IC industry. The heyday of China’s IC technology as well as industry will not keep us waiting for too long! First draft during the Spring Festival 2018 in Shenzhen Revised in midsummer 2018 in Peking University

Acknowledgments

The authors would like to acknowledge contributions for the following listed individuals. Contributions to Section 2: Yongle Qi, Xiaoyu Sun, Wentao Li, Xinke Liu, Cong Hu, Ning Wang, Jack Pan, Yunfei Liu, Peter Feng, Yuzhen Liu, Chole Ma, Hongsha Wang, Ting Ma, Yu-Hua Chen, Song Chen, Xiao Luo, Monica Liu, Kanglin Xiao, Haotian Zhong, Kuan-Chang Chang, Hang Zhou, Huiling Lu, Xiaoliang Zhou, Yang Shao, Ming-Jiang Wang, Lu Zhang, Hao Liu, Congwei Liao, He Huang, Wei Wang, Bowei Huang, Wengao Lu, Hang Zhou, Xuanjie Liu, Qi Liu, Yuzheng Liu, Qianli Ma, Guoxin Zhang, David Xu, Shipeng Sun, Yuxin You, Lingyun Zhang, He Sun, Hao Ma, Qiuping Li, Yufan Feng, Yingying Wu, Bohang Li, Kangsheng Zhou, Cong Jiao, Xian-Nian Lu, Qiquan Zhang, Yong Zhao, and Han Xiang. Contributions to Section 6: Yu Wang, Jiajia Liu, Gang Du, Jun Ge, Zhaoyi Zhang, Shaiying Shen, Jun Chen, Hao Wang, Wei Tian, Pin Li, Jian Wang, Yi Xiao, Yongxiang Wen, Zhongwei He, Feng Qian, Rongzhong Xia, Weituan Jiang, Yong Wang, Chuanfeng Xin, Yongliang Zhu, Hai Jiang, Zhiyong Yang, Gang Sun, Yijiao Wang, Zhaozhao Xu, Huiyong Liu, Kaixuan Yu, Jianming Li, and Wei Su.

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Volume 1 Section I Technology and Industry Development of Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Min-Zheng Zheng, Yong-wen Wang, and Ke Li 1

Invention and Technological Progresses of Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yong-Wen Wang and Min-Zheng Zheng

1

3

2

Characteristics and Strategic Significance of IC Industry . . . . . . . Yong-Wen Wang and Min-Zheng Zheng

25

3

The Development Law of the IC Industry . . . . . . . . . . . . . . . . . . . Yong-Wen Wang and Min-Zheng Zheng

31

4

Development of World IC Industry Da-Kang Mo and Ke Li

........................

45

5

Development of Regional IC Industry Guoming Zhang and Ke Li

......................

81

6

Information Security in Integrated Circuits . . . . . . . . . . . . . . . . . . Chaohui Wang, Qinsheng Wang, and Qian Peng

91

7

Integrated Circuit Intellectual Property . . . . . . . . . . . . . . . . . . . . . Bulu Xu

109

8

International Competition and Cooperation . . . . . . . . . . . . . . . . . Guoqiang Li, Zhaozhao Xu, and Min-Hwa Chi

115

9

Integrated Circuit Enterprise Management . . . . . . . . . . . . . . . . . . Ke Li, Kai Zheng, and Min Zhu

123

10

Talent Cultivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ke Li, Yong-Wen Wang, Yumei Zhou, and Chun-Zhang Chen

147

xxiii

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Contents

Section II Classification and Applications of IC Products Shengming Zhou, Chun-Zhang Chen, and Xin-An Wang

.........

155

11

Development and Classification of IC . . . . . . . . . . . . . . . . . . . . . . . Song Zhang, Kaiwei Zhang, and Yutao Huo

157

12

Classification of IC Products by Manufacturing Processes . . . . . . Xinnan Lin, Mingxia Qiu, Fei Wang, Lenian He, and Jesse Jen-Chung Lou

165

13

Products of Digital Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . David Hu, Alex Lin Jia, Fan-Yi Jien, Xia Ai, and Chun-Zhang Chen

187

14

Analog and Mixed-Signal IC Products . . . . . . . . . . . . . . . . . . . . . . Yuheng Guan, Fan Lai, Yuhua Chen, Yi Sun, and Gangyi Hu

233

15

Radio Frequency IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bo Wang, Yan Li, and Xin-An Wang

279

16

Products of Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xinnan Lin, Zheng Gong, and Jesse Jen-Chung Lou

303

17

Products of Optoelectronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . Yizhe Sun, Wen Yu, Letao Zhang, and Shengdong Zhang

335

18

Products of Sensors and MEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . Yu-Fei Han, Yun-Zhuo Sun, Mingjiang Wang, Qiang Liu, and Ran Tao

357

19

Applications of IC Products in Consumer, Computer, and Communication Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . Yieji Zhu, Hui Liu, Yongxin Liu, Guoqiang Li, and Shengming Zhou

20

21

Applications of IC Products in Automotive, Industrial, and Medical Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quan Yan, Qiquan Zhang, Xin-An Wang, and Huan Liu Applications of IC Products in Aero-Mil . . . . . . . . . . . . . . . . . . . . Gang Liu, Qiquan Zhang, Fang-Lin Yan, Yuewen He, and Chuan Deng

Section III Integrated Circuit Industrial Economy and Investment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zixue Ζhou, Yue Liu, Fangfang Li, Ying Cai, and Ke Feng 22

Economic and Financial Theories Related to IC Industry . . . . . . . Zixue Zhou, Fangfang Li, Yaoliang Qi, and Bojing Zheng

383

403 423

449 451

Contents

xxv

23

Development Law and Development Index of IC Industry . . . . . . . Tong Feng, Kai Zheng, and Kelu Hua

24

Financial Management Practice and Analysis of Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ying Cai, Yuwen Xue, Yanlun Yan, and Jianyue Pan

473

507

Investment and Financing of IC Industry . . . . . . . . . . . . . . . . . . . Yingping Hu, Yang Liu, Ming Yin, and Cheng Zhang

533

Section IV Integrated Circuit Production Lines . . . . . . . . . . . . . . . . . Richard Chang, Lei Jiang, Yibo Wang, and Yonghang Yu

557

26

Development History of IC Production Lines . . . . . . . . . . . . . . . . . Janet Zeng

559

27

Location and Environmental Impact Assessment of IC Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thomas Hsu

25

565

28

Designing IC Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . T. C. Wang

583

29

Clean Room and Air Conditioning Systems . . . . . . . . . . . . . . . . . . Deyuan Xiao

603

30

Central Gas and Chemical Supply Systems . . . . . . . . . . . . . . . . . . Deyuan Xiao

611

31

Construction and Management of IC Production Lines Shuying Wang

........

621

32

Hazardous Chemicals Management . . . . . . . . . . . . . . . . . . . . . . . . Deyuan Xiao

639

33

Energy Savings and Development Trends Deyuan Xiao and Janet Zeng

...................

647

Section V Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . Shaojun Wei, Xiaolang Yan, and Yuhua Cheng

657

34

Overview of IC Design Shouyi Yin

..................................

659

35

Basics of Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . Cheng Huang, Qinsong Qian, Chao Chen, Wei Ge, and Jian Cao

667

36

Digital Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . Jun Yang, Peng Cao, Weiwei Shan, Longning Qi, and Xinning Liu

693

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37

Analog Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . Yuhua Cheng, Song Ma, Lele Jiang, Long Zhao, and Bao Li

711

38

RF Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pengcheng Xiao, Yumei Huang, Wei Li, Na Yan, and Xiaoyang Zeng

727

39

Power Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tianshen Tang, Hao Ni, and Xiaoyan Liu

743

40

Design of Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xiaolang Yan, Jianyi Meng, and Zhijian Chen

757

41

Memory Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fujun Bai, Xiaowei Han, and Liyang Pan

779

42

SoC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xiaolang Yan, Kai Huang, and Jianyi Meng

803

43

Programmable Logic Circuit Design Shaojun Wei and Shouyi Yin

.......................

821

44

Electronic Design Automation Tools . . . . . . . . . . . . . . . . . . . . . . . . Xiaoming Liu, Yi Liu, Taotao Lu, Fan Yang, and Junqi Yang

829

Section VI IC Manufacturing and Management . . . . . . . . . . . . . . . . . Min-Hwa Chi, Nanxiang Chen, Hanming Wu, Haijun Zhao, and Weihai Bu

861

45

The Evolution of IC Manufacturing Technology . . . . . . . . . . . . . . Weihai Bu and Wenbo Wang

863

46

Silicon-Based Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . Weihai Bu, Wenbo Wang, and Poren Tang

871

47

Compound Semiconductor Device and IC . . . . . . . . . . . . . . . . . . . Min-Hwa Chi, Ying-Kun Liu, and Long Qin

883

48

Micro Electro-Mechanical Systems (MEMS) . . . . . . . . . . . . . . . . . Yunqian He, Aisheng Yu, Xuanjie Liu, and Yuelin Wang

895

49

Unit Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hanming Wu, Hong Xiao, Weihai Bu, Shan Yu, and Poren Tang

913

50

Module Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hanming Wu, Shan Yu, Hong Xiao, and Poren Tang

937

51

Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Min-Hwa Chi

951

52

Types of Integrated Circuit Corporations . . . . . . . . . . . . . . . . . . . Nanxiang Chen, Shilin Fang, Rufei Chai, and Guoqiang Li

979

Contents

53

Management and Mode of IC Manufacturing Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xiangdong Chen, Jianxin Yan, and Liang Ma

xxvii

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Volume 2 Section VII Packaging and Testing of IC Products . . . . . . . . . . . . . . . 1013 Keyun Bi, Xiekang Yu, Hongwei Sun, and Daquan Yu 54

Development of Packaging and Testing Industry . . . . . . . . . . . . . . 1015 Jian Cai, Guoliang Yu, Hongwei Sun, Jian Wu, and Lin Tan

55

Integrated Circuit Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1027 Guoliang Yu, Haizhong Shi, and Honghui Wang

56

Key Technologies and Processes for Traditional Packaging . . . . . . . 1069 Daquan Yu, Zhi-Quan Liu, Ming Li, Linghua Zhu, and Xiaowei Guo

57

Process and Key Technology of Typical Advanced Packaging . . . . 1093 Steve Xinfu Liang, Chihchung Liang, Hongyan Guo, Weidong Liu, and Xusheng Bao

58

Design Technologies for Advanced Packaging . . . . . . . . . . . . . . . . 1129 Jun Li, Yunyan Zhou, Min Miao, Wei Wang, Fei Su, and Fengman Liu

59

Integrated Circuit Testing Technology . . . . . . . . . . . . . . . . . . . . . . 1153 Zhiyong Zhang, Jianhua Qi, Kun Yu, and Qin Wang

60

Integrated Circuits Packaging Reliability . . . . . . . . . . . . . . . . . . . . 1185 Anjun Huang, Rongzheng Ding, Hanwu Xiao, Jian Lu, and Hongwei Luo

61

Standardization of Integrated Circuits Packaging . . . . . . . . . . . . . 1207 Le Luo, Jing Wang, and Kun Li

Section VIII IC Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221 Tianchun Ye, Zhiyao Yin, Jinrong Zhao, Yuan Pu, and Baoqin Chen 62

The Development of the IC Equipment Industry . . . . . . . . . . . . . . 1223 Guoming Zhang

63

Manufacturing Equipment for Silicon Wafer . . . . . . . . . . . . . . . . . 1237 Bin Liu

64

Mask Manufacturing Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . 1285 Baoqin Chen, Boru Feng, and Jesse Jen-Chung Lou

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Contents

65

Lithography Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327 Rongming He, Jianrui Cheng, and Fan Wang

66

Diffusion and Ion Implantation Equipment . . . . . . . . . . . . . . . . . . 1361 Zhaoyang Cheng, Xiaozhen Liu, Junyu Xie, and Zhuliang Zuo

67

Thin Film Growth Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383 Yang Xia, Peijun Ding, Jinrong Zhao, Bin Yin, and Xiaoping Shi

68

Plasma Etch Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1441 Yuan Pu

69

Wet Cleaning Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 Fuping Chen, Xiaoyan Zhang, Xi Wang, Zhaowei Jia, and Yinuo Jin

70

Metrology and Inspection Equipment Feng Yang

71

Packaging and Assembly Equipment . . . . . . . . . . . . . . . . . . . . . . . 1569 Lezhi Ye and Qiangsheng Guo

72

Main Common Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603 Zhaoyang Cheng, Dongshan Li, Changhua Mou, Jinwei Dong, and Chunlei Li

73

Integrated Circuit-Testing Equipment . . . . . . . . . . . . . . . . . . . . . . 1629 Yanfeng Jiang, Zhiyong Zhang, Kun Yu, and Jianhua Qi

. . . . . . . . . . . . . . . . . . . . . . 1527

Section IX Integrated Circuits Materials . . . . . . . . . . . . . . . . . . . . . . . 1643 Deren Yang, Jingfeng Kang, and Xuegong Yu 74

Silicon Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645 Deren Yang and Xuegong Yu

75

Silicon Wafer Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665 Deren Yang, Xingbo Liang, and Xuegong Yu

76

Defects and Impurities in Silicon Materials . . . . . . . . . . . . . . . . . . 1677 Deren Yang and Xiangyang Ma

77

Compound Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697 Deren Yang, Jingfeng Kang, and Xuegong Yu

78

Photomask and Photoresist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717 Deren Yang, Ying Shi, and Xuegong Yu

79

Auxiliary Material in Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743 Deren Yang, Maojun Wang, and Xuegong Yu

Contents

80

xxix

Package Structure Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1775 Deren Yang, Tong Yuan, and Xuegong Yu

Section X Basic Research and Frontier Technology Development of Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801 Xing Zhang, Jun Xu, Longxing Shi, and Lifeng Liu 81

Non-traditional New Structure Devices . . . . . . . . . . . . . . . . . . . . . 1803 Yimao Cai, Jun Xu, Renrong Liang, Qianqian Huang, and Zongwei Wang

82

New Type ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829 Nanjian Wu, Huaxiang Lu, Yongpan Liu, Leibo Liu, and Baoyong Chi

83

New Materials Used in IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847 Yunyi Fu, Tianli Duan, and Hongyu Yu

84

Advanced IC Manufacturing Processes . . . . . . . . . . . . . . . . . . . . . 1865 Hanming Wu, Jesse Jen-Chung Lou, Hong Xiao, Yimao Cai, and Yuancheng Yang

85

New Technology in Integration and Interconnection . . . . . . . . . . . 1873 Zheyao Wang and Xue Feng

86

Modeling and Simulation of Nano-devices . . . . . . . . . . . . . . . . . . . 1881 Fei Liu, Yijiao Wang, Lang Zeng, Gang Du, and Xiaoyan Liu

87

Flexible Semiconductor Devices (FSD) . . . . . . . . . . . . . . . . . . . . . . 1893 Yi Shi, Yun Li, and Sai Jiang

88

Integrated Microsystem Technology . . . . . . . . . . . . . . . . . . . . . . . . 1915 Wei Wang, Haixia Zhang, and Zhenchuan Yang

89

Advanced Characterization and Testing Techniques . . . . . . . . . . . 1923 Runsheng Wang, Jianhua Feng, and Jiayang Zhang

90

Aerospace Microelectronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939 Yuanfu Zhao, Suge Yue, Hongchao Zheng, and Liang Wang

Appendix A: List of Semiconductor Enterprises . . . . . . . . . . . . . . . . . . 1953 Appendix B: Reference Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962 Appendix C: Abbreviations of IC Terminology . . . . . . . . . . . . . . . . . . . 1975 Appendix D: Common Glossaries of IC Industry . . . . . . . . . . . . . . . . . 1993

About the Editors

Yangyuan Wang is the Honorary Dean and Professor of the School of Integrated Circuits at Peking University. He is an Academician of the Chinese Academy of Sciences, an IEEE Life Fellow, IET (IEE) Fellow, and CIE Fellow. His research in the field of microelectronics primarily focuses on new devices, new processes, and new structured circuits. He has authored more than 400 academic papers and 14 books and holds over 130 invention patents. Contributions include 20 major scientific and technological achievements, and so far he has been awarded 21 national and ministry awards, including the National Science Congress Awards, the National Invention Awards, the National Science and Technology Progress Awards, and the inaugural Yuanpei Tsai Award of Peking University. Throughout his career, He has mentored over 100 MSc students, PhD students, and postdoctoral researchers. In 1958, he graduated from the Physics Department of Peking University and began teaching at the same institution. He was the Director of the Institute of Microelectronics, the Director of the Department of Microelectronics of Peking University, the Director of the National ICCAD Expert Committee, the Director of the National ICCAT Expert Committee, and the Director of the National Integrated Circuit Product Development Expert Committee. Additionally, he has served as the Vice Chairman of the Chinese Institute of Electronics. As one of the founders of SMIC Manufacturing Co., Ltd., he has served as the chairman of entities and listed companies. He also established the IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

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About the Editors

Yangyuan Wang currently also serves as a Consultant of the Electronic Science and Technology Committee of the Ministry of Industry and Information Technology, and as the Associate Chief Editor of the Journal of Semiconductors and Journal of Electronics (English edition). Min-Hwa Chi GTA Semiconductor Shanghai, China Dr. Min-Hwa Chi received his BS, MS, and PhD in EE at National Taiwan University, University of Rhode Island, and University of California-Berkeley (1982), respectively. He has served VLSI industry in Intel (1982–1988), KFI technology (1988–1994), and National Semiconductor (1994–1997) in NVM, CMOS-Imager, and module process development. He served foundry industry for TSMC (1997–2005 as Sr. Director/R&D), GlobalFoundries (2011–2015 as Sr. Fellow/Dir), SMIC China (2006–2011 and 2015–2018 as SVP), and SiEn (QingDao) Integrated Circuits (2018–2021 as SVP/TD). He is now the chief scientist at GTA Semiconductor. He served as guest professor at Qingdao University (2019~) and Peking University (2010–2011) and honorary professor at Fu-Dan University (2008–2010) at China. He is IEEE Life Sr. member (2001). He has 262 US patents (or >600 international patents) and has published 3 books and more than 105 technical papers in areas of CMOS Logic/FinFET, Flash memory, CMOS Imager, DRAM, and power devices. Jesse Jen-Chung Lou Peking University Beijing, China Professor Jesse Jen-Chung Lou graduated from the Department of Physics and the Institute of Physics of Tsinghua University (Taiwan). He received his Ph.D. from the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley, USA. Prof. Lou has taught in the Department of Electrical Engineering of Tsinghua University (Taiwan) and the Department of Electronic Engineering of Chiao Tung University (Taiwan) for many years, and

About the Editors

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then severed as a full professor in the Department of IC & Intelligent System Engineering at the School of Software and Microelectronics of Peking University (2010–2021). His research interests include high-K dielectric growth technology, low-K dielectric materials, silicon selective epitaxial growth technology, advanced lithography process, defect and failure analysis technology in integrated circuits, advanced RRAM materials and device structures, MOCVD growth LED quantum well and high brightness LED technology, GaN and SiC heteroepitaxial growth technology, high power SiC devices, etc. Prof. Lou’s team has participated in research projects and training programs of TSMC, UMC, PowerChip, MXIC, ITRI, BCD (Shanghai), SMIC (Shanghai), Applied Materials (Taiwan), Changzhou Jingyuan Optoelectronics (China), and other companies. Prof. Lou has published 104 papers and obtained 20 patents. In addition, he has translated 5 books on integrated circuits and has been awarded as “an excellent teacher” at the School of Software and Microelectronics of Peking University seven times. Currently, he continues to lead a research team to assist the integrated circuit Fabs to develop products. Professor Lou also participated in the establishment of the Semiconductor Academy, acted as a technical consultant to several enterprises, assisted the industry in developing training systems, and implemented a number of integrated circuit personnel training programs. Chun-Zhang Chen Peng Cheng Laboratory Shenzhen, Guangdong, China Dr. Chun-Zhang Chen is currently a research fellow at Peng Cheng Lab in Shenzhen, Guangdong, China. He is a professor adjunct at both University of Chinese Academy of Sciences (teaching a summer class since 2014) and Zhejiang University (since 2021). His research interests include design and verification methodology of integrated circuit (IC), system-on-chip (SoC), and high-speed interface IP. Research on IC design is extended to its reliability including mechanism of radiation resistance. In his job at Cadence Design Systems (1997–2013), he has contributed to the industry

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About the Editors

timing-driven design (TDD) flow and hierarchical methodology in IC/SoC design in the late 2000. Towards SoC design using EDA, he co-authored a book on digital IC physical design methodology and has translated a book of mixed-signal IC design guide. He has worked in a variety of roles, from a field application engineer (AE), EDA instructor, technical director, etc. In 2003, he also spent 3 years in a joint venture named ZCIST, a.k.a. Cadence University, to lead then a worldclass IC training program of IC talents. Dr. Chen’s previous career was as a research scientist. He spent 8 years (1987–1995) at Brookhaven National Lab, University of California – San Francisco, and Columbia University, where his areas of focus were the effects of ionizing radiations (X-, γ-rays, n, e, α, etc.) on biological targets (mammalian cells, chromosomes, and DNAs). After graduating from the University of Science and Technology of China, he worked at the Institute of Biophysics of the Chinese Academy of Sciences, followed by receiving an MSc and PhD on Radiation Physics (1984, 1987) from St. Andrews University.

Contributors

Xia Ai Cadence Design Systems, Inc., Beijing, China Fujun Bai Xi’an UniIC Semiconductors Co., Ltd., Xi’an, Shaanxi, China Xusheng Bao JCET Group Co., Ltd., Wuxi, China Weihai Bu Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, China Jian Cai School of Integrated Circuits, Tsinghua University, Beijing, China Yimao Cai Institute of Microelectronics, Peking University, Beijing, China Ying Cai Summitview Capital, Beijing, China Jian Cao School of Software and Microelectronics, Peking University, Beijing, China Peng Cao National ASIC System Engineering Center, Southeast University, Nanjing, China Rufei Chai China Resources Microelectronics Ltd., Wuxi, China Baoqin Chen Institute of Microelectronics (IME), Chinese Academy of Sciences, Beijing, China Chao Chen National ASIC System Engineering Center, Southeast University, Nanjing, China Chun-Zhang Chen Peng Cheng Lab, Shenzhen, China Fuping Chen ACM Research (Shanghai), Inc., Shanghai, China Nanxiang Chen Yangtze Memory Technologies Co., Ltd., Wuhan, China Xiangdong Chen Hangzhou Silan Microelectronics Co., Ltd., Hangzhou, China Yuhua Chen Peking University, Beijing, China Zhijian Chen Institute of VLSI, Zhejiang University, Hangzhou, China xxxv

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Contributors

Jianrui Cheng Shanghai Micro Electronics Equipment (Group) Co., Ltd (SMEE), Shanghai, China Yuhua Cheng Institute of Microelectronics, Peking University, Beijing, China Zhaoyang Cheng Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China Baoyong Chi Institute of Microelectronics, Tsinghua University, Beijing, China Min-Hwa Chi GTA Semiconductor Co., Ltd., Shanghai, China Chuan Deng National IC Design Shenzhen Industrial Centre, Shenzhen, China Peijun Ding Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China Rongzheng Ding China Key System Co., Ltd (CKS), Wuxi, China Jinwei Dong Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing, China Gang Du Institute of Microelectronics, Peking University, Beijing, China Tianli Duan Southern University of Science and Technology, Shenzhen, China Shilin Fang China Resources Microelectronics Ltd., Wuxi, China Boru Feng Institute of Optics & Electronics (IOE), Chinese Academy of Sciences, Beijing, China Jianhua Feng Institute of Microelectronics, Peking University, Beijing, China Tong Feng Semiconductor Manufacturing International Corporation, Beijing, China Xue Feng Department of Electronic Engineering, Tsinghua University, Beijing, China Yunyi Fu Institute of Microelectronics, Peking University, Beijing, China Wei Ge National ASIC System Engineering Center, Southeast University, Nanjing, China Zheng Gong Tunghai University, Taiwan, China Yuheng Guan Huada Empyrean Software Co. Ltd., Beijing, China Hongyan Guo Zhejiang Hexin Semiconductor Co., Ltd., Jiashan, China Qiangsheng Guo CETC Beijing Electronic Equipment Co., Ltd., Beijing, China Xiaowei Guo Huatian Technology (Xi’an) Co., Ltd., Xi’an, China Xiaowei Han Xi’an UniIC Semiconductors Co., Ltd., Xi’an, Shaanxi, China Yu-Fei Han Harbin Institute of Technology, Shenzhen, China

Contributors

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Lenian He Zhejiang University, Hangzhou, China Rongming He Shanghai Micro Electronics Equipment (Group) Co., Ltd (SMEE), Shanghai, China Yuewen He Shenzhen Institute of Micro-nano IC and System Application, Shenzhen, China Yunqian He Huawei Technologies Co., Ltd., Shanghai, China Thomas Hsu SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China David Hu EtownIP Microelectronics Co. Ltd., Beijing, China Gangyi Hu China Electronics Technology Group Corporation 24th Institute, Chongqing, China Yingping Hu Hua Capital Management Co., Ltd., Beijing, China Kelu Hua Semiconductor Manufacturing International Corporation, Shanghai, China Anjun Huang Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Wuxi, China Cheng Huang National ASIC System Engineering Center, Southeast University, Nanjing, China Kai Huang Institute of VLSI, Zhejiang University, Hangzhou, China Qianqian Huang Institute of Microelectronics, Peking University, Beijing, China Yumei Huang School of Microelectronics, Fudan University, Shanghai, China Yutao Huo China Center for Information Industry Development, Beijing, China Alex Lin Jia Cadence Design Systems, Inc., Shanghai, China Zhaowei Jia ACM Research (Shanghai), Inc., Shanghai, China Lele Jiang Shanghai Research Institute of Microelectronics, Peking University, Shanghai, China Sai Jiang School of Electronic Science and Engineering, Nanjing University, Nanjing, China Yanfeng Jiang Beijing Institute of Automatic Test Technology, Beijing, China Fan-Yi Jien Advanced Memory Semiconductor Co. Ltd., Jiangsu, China Yinuo Jin ACM Research (Shanghai), Inc., Shanghai, China Jingfeng Kang School of Electronics Engineering and Computer Science, Peking University, Beijing, China

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Contributors

Fan Lai China Electronics Technology Group Corporation 24th Institute, Chongqing, China Bao Li Shanghai Research Institute of Microelectronics, Peking University, Shanghai, China Chunlei Li Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing, China Dongshan Li Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing, China Fangfang Li Publishing House of Electronics Industry Co., Ltd., Beijing, China Guoqiang Li Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd., Shanghai, China Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, China ICWise Market Information Consulting (Shanghai) Co., Ltd., Shanghai, China Jun Li Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China Ke Li Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China Kun Li China Electronics Standardization Institute, Beijing, China Ming Li School of Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China Wei Li School of Microelectronics, Fudan University, Shanghai, China Yan Li Shenzhen University, Shenzhen, China Yun Li School of Electronic Science and Engineering, Nanjing University, Nanjing, China Chihchung Liang JCET Group Co., Ltd., Wuxi, China Renrong Liang Institute of Microelectronics, Tsinghua University, Beijing, China Steve Xinfu Liang JCET Group Co., Ltd., Wuxi, China Xingbo Liang Ql Electronics Co., Ltd., Ningbo, China Xinnan Lin Electronic and Computer Engineering, Peking University, Shenzhen, China Bin Liu The 45th Research Institute of China Electronics Technology Group Corporation (CETC45), Beijing, China Fei Liu Institute of Microelectronics, Peking University, Beijing, China Fengman Liu Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

Contributors

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Gang Liu China Electronics Technology Group Corporation 14th Institute, Nanjing, China Huan Liu Southern University of Science and Technology, Shenzhen, China Hui Liu Huaqiang Electronic Industry Research Institute, Shenzhen, China Leibo Liu Institute of Microelectronics, Tsinghua University, Beijing, China Qiang Liu Shanghai Institute of Microsystem and Information Technology, Shanghai, China Weidong Liu Tianshui Huatian Technology Co., Ltd., Tianshui, China Xiaoming Liu Huada Empyrean Software Co., Ltd., Beijing, China Xiaoyan Liu Silicon Storage Technology Inc. (SST), Shanghai, China Institute of Microelectronics, Peking University, Beijing, China Xiaozhen Liu Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China Xinning Liu National ASIC System Engineering Center, Southeast University, Nanjing, China Xuanjie Liu Semiconductor Manufacturing Electronics (ShaoXing) Corporation, Shaoxing, China Yang Liu Hua Capital Management Co., Ltd., Beijing, China Yi Liu Huada Empyrean Software Co., Ltd., Beijing, China Ying-Kun Liu Hebei Semiconductor Research Institute, Shijiazhuang, China Yongpan Liu Department of Electronic Engineering, Tsinghua University, Beijing, China Yongxin Liu Shenzhen Institute of Micro-nano IC and System Application, Shenzhen, China Zhi-Quan Liu Shenzhen Institute of Advanced Electronic Materials, Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China Jesse Jen-Chung Lou School of Software and Microelectronics, Peking University, Beijing, China Institute of Microelectronics, Peking University, Beijing, China Huaxiang Lu Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China Jian Lu WiFi CMC Electronics Co., Ltd., Wuxi, China Taotao Lu Huada Empyrean Software Co., Ltd., Beijing, China

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Contributors

Hongwei Luo China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou, China Le Luo Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China Liang Ma Hangzhou Silan Microelectronics Co., Ltd., Hangzhou, China Song Ma Shanghai Research Institute of Microelectronics, Peking University, Shanghai, China Xiangyang Ma State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China Jianyi Meng Department of Microelectronics, Fudan University, Shanghai, China Min Miao Beijing Information Science and Technology University, Beijing, China Da-Kang Mo Truth Semi Group, Shanghai, China Changhua Mou Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing, China Hao Ni Semiconductor Manufacture International Corporation, Shanghai, China Jianyue Pan Summitview Capital, Beijing, China Liyang Pan Institute of Microelectronics, Tsinghua University, Beijing, China Qian Peng Bank Card Test Center, Chengdu, China Yuan Pu Advanced Micro-Fabrication Equipment Inc. (AMEC), Shanghai, China Jianhua Qi Sino IC Technology Co., Ltd., Shanghai, China Longning Qi National ASIC System Engineering Center, Southeast University, Nanjing, China Yaoliang Qi Hua Capital Investment Management Co., Ltd., Beijing, China Qinsong Qian National ASIC System Engineering Center, Southeast University, Nanjing, China Long Qin Hebei Semiconductor Research Institute, Shijiazhuang, China Mingxia Qiu College of New Materials and New Energies, Shenzhen Technology University, Shenzhen, China Weiwei Shan National ASIC System Engineering Center, Southeast University, Nanjing, China Haizhong Shi TongFu Microelectronics Co., Ltd., Nantong, China Xiaoping Shi Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China

Contributors

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Yi Shi School of Electronic Science and Engineering, Nanjing University, Nanjing, China Ying Shi Integrated Circuit Materials Innovative Alliance, Peking, China Fei Su Beihang University, Beijing, China Hongwei Sun National Center for Advanced Packaging Co., Ltd., Wuxi, China Yi Sun University of Chinese Academy of Sciences, Beijing, China Yizhe Sun Electronic and Computer Engineering, Peking University, Shenzhen, China Yun-Zhuo Sun Harbin Institute of Technology, Shenzhen, China Lin Tan School of Integrated Circuits, Tsinghua University, Beijing, China Poren Tang Semiconductor Manufacturing International Corp, Shanghai, China Tianshen Tang Leapfive Technology Co., Ltd., Guangdong, China Ran Tao Synopsys, Shanghai, China Bo Wang Electronic and Computer Engineering, Peking University, Shenzhen, China Chaohui Wang Beijing Huada Infosec Co., Ltd., Beijing, China Fan Wang Shanghai Micro Electronics Equipment (Group) Co., Ltd (SMEE), Shanghai, China Fei Wang School of Microelectronics, Southern University of Science and Technology, Shenzhen, China Honghui Wang TongFu Microelectronics Co., Ltd., Nantong, China Jing Wang China Electronics Standardization Institute, Beijing, China Liang Wang Beijing Microelectronics Technology Institute, Beijing, China Maojun Wang School of electronics engineering and computer science, Peking University, Beijing, China Mingjiang Wang Harbin Institute of Technology, Shenzhen, China Qin Wang Shanghai Jiao Tong University, Shanghai, China Qinsheng Wang IC Design Branch, China Semiconductor Industry Association, Beijing, China Runsheng Wang Institute of Microelectronics, Peking University, Beijing, China Shuying Wang SiEn (Qingdao) Integrated Circuit Corp, Qingdao University, Qingdao, China T. C. Wang SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China

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Contributors

Wei Wang Peking University, Beijing, China Institute of Microelectronics, Peking University, Beijing, China Wenbo Wang SiEn (Qingdao) Integrated Circuit Co., Ltd., Qingdao, China Xi Wang ACM Research (Shanghai), Inc., Shanghai, China Xin-An Wang Electronic and Computer Engineering, Peking University, Shenzhen, China Yijiao Wang Institute of Microelectronics, Beihang University, Beijing, China Yong-Wen Wang Institute of Microelectronics, Peking University, Beijing, China Yuelin Wang Shanghai Institute of Microsystem Information of Technology, Chinese Academy of Sciences, Shanghai, China Zheyao Wang Institute of Microelectronics, Tsinghua University, Beijing, China Zongwei Wang Institute of Microelectronics, Peking University, Beijing, China Shaojun Wei Institute of Microelectronics, Tsinghua University, Beijing, China Hanming Wu School of Micro-nanoelectronics, Zhejiang University, Hanzhou, China Jian Wu National Technology Innovation Strategic Alliance for IC Assembly and Testing, Wuxi, China Nanjian Wu Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China Yang Xia Institute of Microelectronics, Chinese Academy of Sciences (IME), Beijing, China Deyuan Xiao SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China Hanwu Xiao Wuxi ZhongWei High-tech Electronics Co., Ltd., Wuxi, China Hong Xiao KLA-Tencor, Milpitas, CA, USA Pengcheng Xiao School of Microelectronics, Fudan University, Shanghai, China Junyu Xie China Electronics Technology Group Corporation (CETC), Beijing, China Bulu Xu Shanghai Silicon Intellectual Property Exchange Centre, Shanghai, China Jun Xu Institute of Microelectronics, Tsinghua University, Beijing, China Zhaozhao Xu Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd., Shanghai, China Yuwen Xue Zhongjing Industrial, Xi’an, China Fang-Lin Yan Shenzhen Yixingbiao Technology Co., Shenzhen, China

Contributors

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Jianxin Yan Hangzhou Silan Microelectronics Co., Ltd., Hangzhou, China Na Yan School of Microelectronics, Fudan University, Shanghai, China Quan Yan Mentor Graphics, Shanghai, China Xiaolang Yan Institute of VLSI, Zhejiang University, Hangzhou, China Yanlun Yan Summitview Capital, Beijing, China Deren Yang State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China Fan Yang Huada Empyrean Software Co., Ltd., Beijing, China Feng Yang Raintree Scientific Instrument (Shanghai) Corporation (RSIC), Shanghai, China Jun Yang National ASIC System Engineering Center, Southeast University, Nanjing, China Junqi Yang School of Microelectronics, Fudan University, Shanghai, China Yuancheng Yang Institute of Microelectronics, Peking University, Beijing, China Zhenchuan Yang Institute of Microelectronics, Peking University, Beijing, China Lezhi Ye Department of Material and Manufacture, Beijing University of Technology, Beijing, China Bin Yin Institute of Microelectronics, Chinese Academy of Sciences (IME), Beijing, China Ming Yin Publishing House of Electronics Industry Co., Ltd., Beijing, China Shouyi Yin Institute of Microelectronics, Tsinghua University, Beijing, China Aisheng Yu SAIC(Shanghai Automotive Industry Corporation) Motor R&D Innovation Headquarters, Shanghai, China Daquan Yu School of Electronic Science and Engineering, Xiamen University, Xiamen, China Guoliang Yu TongFu Microelectronics Co., Ltd., Nantong, China Hongyu Yu Southern University of Science and Technology, Shenzhen, China Kun Yu Sino IC Technology Co., Ltd., Shanghai, China Shan Yu China Semiconductor Industry Association, Beijing, China Wen Yu Electronic and Computer Engineering, Peking University, Shenzhen, China Xuegong Yu State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China

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Contributors

Tong Yuan China Electronics Materials Industry Association, Beijing, China Suge Yue Beijing Microelectronics Technology Institute, Beijing, China Janet Zeng SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China Lang Zeng Institute of Microelectronics, Beihang University, Beijing, China Xiaoyang Zeng School of Microelectronics, Fudan University, Shanghai, China Cheng Zhang Zhihu Inc., Beijing, China Guoming Zhang NAURA Technology Group Co., Ltd., Beijing, China Hwatsing Technology Co. Ltd., Tianjing, China Haixia Zhang Institute of Microelectronics, Peking University, Beijing, China Jiayang Zhang Institute of Microelectronics, Peking University, Beijing, China Kaiwei Zhang Huada Semiconductor Co. Ltd, Beijing, China Letao Zhang Electronic and Computer Engineering, Peking University, Shenzhen, China Qiquan Zhang Harbin Institute of Technology, Shenzhen, China Shengdong Zhang Electronic and Computer Engineering, Peking University, Shenzhen, China Song Zhang China Center for Information Industry Development, Beijing, China Xiaoyan Zhang ACM Research (Shanghai), Inc., Shanghai, China Zhiyong Zhang Sino IC Technology Co., Ltd., Shanghai, China Jinrong Zhao Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China Long Zhao Shanghai Research Institute of Microelectronics, Peking University, Shanghai, China Yuanfu Zhao China Academy of Aerospace Electronics Technology, Beijing, China Bojing Zheng Hua Capital Investment Management Co., Ltd., Beijing, China Hongchao Zheng Beijing Microelectronics Technology Institute, Beijing, China Kai Zheng Semiconductor Manufacturing International Corporation, Beijing, China Min-Zheng Zheng Department of Information Technology Industry, Ministry of Industry and Information Technology, Beijing, China Shengming Zhou Southern University of Science and Technology, Shenzhen, China

Contributors

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Yumei Zhou Institute of Microelectronics, Chinese Academy of Science, Beijing, China Yunyan Zhou Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China Zixue Zhou China Federation of Electronics and Information Industry, Beijing, China Linghua Zhu Wuxi Zhongwei High-tech Electronics Co., Ltd., Wuxi, China Min Zhu Shanghai HLMC Co., Ltd., Shanghai, China Yieji Zhu Huaqiang Electronic Industry Research Institute, Shenzhen, China Zhuliang Zuo China Electronics Technology Group Corporation (CETC), Beijing, China

Spring Blossoms and Autumn Fruits: History of Compiling The Handbook of Integrated Circuit Industry

Introduction The motion to compile The Handbook of Integrated Circuit Industry sprang at the end of 1991. At that time, Professor Yangyuan Wang of Peking University served as part-time Deputy Director of the Division of Microelectronics and Basic Products of the then Ministry of Mechanical and Electronic Industry. Minzheng Zheng, Xiaotian Xu, Xian Chen, and Yongwen Wang also worked there. As managers in industry, they often encountered macro-problems such as industrial development strategy, market analysis, industrial economy, and industrial management, and microproblems such as product application, product design, product technology, and materials and equipment. To solve these problems, they had to consult references or experts. However, books on integrated circuits published at the time were mostly technical works or academic monographs, such as Semiconductor Physics (Kun Huang, Xide Xie), Design Principles of Integrated Circuits: Bipolar Logical Integrated Circuits (Pushan Tang as Editor-in-Chief), Computer Aided Plate Making Software System for Large Scale Integrated Circuits (edited by Xianlong Hong, et al.), Polycrystalline Silicon Film and Its Application in Integrated Circuits (edited by Yangyuan Wang and T. I. Cummings), and Integrated Circuit Technology Foundation (edited by Yangyuan Wang, Xudong Guan, and Junru Ma). Books about packaging, testing, and special equipment and materials on the industrial chains of the integrated circuit were rare. Most of the staff who had direct contact with industrial management came from a background of science and engineering without systematic knowledge about economy and management. It was also difficult to find monographs on economics and management of the IC industry which they could consult. For this reason, Xian Chen and Yongwen Wang, among others, came up with the idea of compiling a monograph. This monograph should first be “complete.” At the macro level, it should include contents such as the direction of the development, strategic initiatives, market data, historical evolution, forecast, and outlook. At the technical level, it should cover the entire chain of the IC industry, including classification, application, design, processing, packaging, testing, equipment, material, and plant construction of the IC products. Second, this book should be like a dictionary, or a desk reference that could be used at any time by managers, technicians, and teachers in the IC field. This xlvii

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motion was immediately seconded by Director Dasheng Li of the Division of Microelectronics and Basic Products and likewise won the support of other directors. Vice-Director Yangyuan Wang was unanimously elected Editor-in-Chief of the book, and the subtitle was designated “Technology, Economy, and Management.” In 1991, conditions for writing books were very tough. There was no computer with text editing software, no network, no mobile phone. Even the telephone was mostly a wheeled dial extension; calls to the outside had to be transferred through a switchboard. Texts had to be written by hand with a fountain pen on a 400-word sheet of paper. Charts had to be drawn by hand with a duck-billed pen dipped in drawing ink. References had to be consulted by the author in person in the library. All paper manuscripts had to be sent by post. As conditions were inadequate for convening a professional meeting of exchange, all information exchange had to be done using letters with 8-cent stamps stuck to them and put into green mailboxes, which took about a week to go back and forth in China. Peony Garden Hotel, located in Beijing’s North Taipingzhuang area, was the destination where all the manuscripts went. In 1992, 114 authors and 2 editors from the Electronic Industry Publishing House joined in the busy work of writing and editing. In April 1993, the 9.67-million-word The Handbook of Integrated Circuit Industry was officially published (see Fig. 1). Today, Shouwu Wang, Lanying Lin, Shoujue Wang, Zhijian Li, Chunguang Liang, Dasheng Li, Weiqin Zheng, Xiaoyu Zhang, Huiquan Zhang, Jiasheng Xu, Tongzeng

Fig. 1 The 1993 edition of The Handbook of Integrated Circuit Industry

Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . .

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Zhuang, Lanfang Gong, and Xian Chen have left us, but their contribution to the development of China’s IC industry will never be forgotten.

A Long-Cherished Wish In April 1993, the State Council undertook institutional restructuring. The Ministry of Mechanical and Electronic Industry was dissolved and the Ministry of Machinery Industry and the Ministry of Electronic Industry were established instead. After the restructuring, Yangyuan Wang returned to Peking University to continue his teaching and research, but his enthusiasm for advancing the IC industry never slackened. He provided suggestions for Projects 908 and 909 and published dozens of articles in various media on strategic research and industrial construction of integrated circuits, expressing his wish to “pursue the dream of China’s IC industry on the fast track.” In 2000, together with colleagues home and abroad, he founded Semiconductor Manufacturing International Corporation Co., Ltd. (SMIC) and served as Chair from 2000 to 2009. The establishment of SMIC has significantly narrowed the gap between China’s manufacturing technology of the integrated circuits and the advanced international level and has become a milestone in the construction of China’s IC industry. Since 2008, Wang and his collaborators have co-authored monographs such as The Road to the Development of Integrated Circuit Industry in China, Green Micronanoelectronics, and Strategy: The Foundation of Survival and Development. Yet, one wish had remained long-cherished and unfulfilled in his heart, which was to re-compile The Handbook of Integrated Circuit Industry. This was because, since 1993, the global IC industry has undergone tremendous changes. New technologies and devices popped up one after another such as deep ultraviolet lithography, copper interconnection, FinFET, high k gate dielectrics, immersion lithography, multi-gate transistors, and 3D packaging. Generation after generation of new IC products have opened up new application markets. Digital cameras, notebook computers, tablets, mobile phones, the Internet, wearable devices, and endless applications are transforming people’s lifestyles and ways of production with each passing day. Since 2000, the Chinese government has promulgated the Notice of the State Council on Issuing Policies to Encourage the Development of Software Industry and Integrated Circuit Industry (State Council No. 18, [2000]) and the Notice of the State Council on Issuing Policies to Further Encourage the Development of Software Industry and Integrated Circuit Industry (State Council No. 4 [2011]). It has also launched the National Promotion Program of the Integrated Circuit Industry in an attempt to put forward important measures to accelerate China’s IC industry. Obviously, the 1993 edition of The Handbook of Integrated Circuit Industry has not been able to meet the new needs of practitioners, investors, industrial planners, market pioneers, and users. It is imperative to compile a new edition. On August 31, 2015, Academician Yangyuan Wang, the leading figure allying production, teaching, and research, proposed to the MIIT to compile A Series of Books on the Integrated Circuits and The Handbook of Integrated Circuit Industry. His proposal had the full backing from Academician Jinpeng Huai, then head of the

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Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . .

National Advisory Committee, and many other experts in the industry. Huai believed, “This will be a very beneficial pursuit. It showcases our scientists’ intellectual aspirations and will be a major event in developing our country’s IC industry. I recommend strong support for it!”

Flowering in Spring February 26, 2016. While it was cold early spring in Beijing, it was already warm in Shenzhen. The greenery in Southern University of Science and Technology was exuding vigor and vitality, and the limpid lake was sending out ripples from its center. In the conference room was Yangyuan Wang presiding over the preparatory meeting of the Editorial Committee of the Series of Books on the Integrated Circuits and The Handbook of Integrated Circuit Industry. The meeting drew up the preliminary list of the Editorial Committee, established the basic structure of the Handbook, adopted the tentative design of its chapters, and formulated the working plan for the compilation. A seed waiting for germination had been quietly sown in the fertile soil of reform and opening up. April 6, 2016, the last month of spring in Beijing. The pink peach blossoms were in flower, the willows had turned a light yellow, the grass had become green, the water was lucid, and the new buds were shooting forth. The preparatory committee issued a “Letter of Inquiry” to 101 experts from the IC industry in China. The majority of them responded positively, agreeing to serve on the Editorial Committee and expressed their full support for the compilation. May 7, 2016. As flowers came in a riot of colors, showing off the charming roses, graceful cloves, and bright peonies, China’s IC industry had also ushered in a blossoming spring. Senior scientists in their 70s and 80s, middle-aged scientists in the prime of life and career, elite returnees from abroad who were working hard in the production line, and enthusiastic youths who were venturing into the industry all gathered in Beijing’s Wanshou Hotel for the compiling of the Handbook. The Editorial Committee was thus formally established on this day. Nearly 100 people attended the meeting, including officials from the Division of Electronic Information, MIIT, and the China Semiconductor Industry Association, as well as scholars, experts, and executives from universities, research institutes, enterprises, and publishing houses. Academician Yangyuan Wang chaired the meeting. Representative of the Division of Electronic Information, MIIT, congratulated the establishment of the Editorial Committee and made suggestions on its work. To enhance the sense of honor and responsibility of the members of the Editorial Committees, letters of appointment to the Editor-in-Chief and Deputy Chief Editors of the Handbook as well as other members of the Editorial Committee attending the meeting were issued. Academician Yangyuan Wang made a keynote speech, elaborating on the following four aspects:

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1. The significance of compiling the Series and the Handbook 2. The method of selecting members of the Editorial Committee and the working methods of the Editorial Committee 3. Issues related to funds and intellectual property rights 4. Expected achievements of the Committee by the end of 2020, during the 13th Five-Year Plan period Detailed plans for the compilation including chapter design, book length, and rules for writing the entries were then discussed, a timetable was worked out, and chief editors for each chapter were appointed.

Sharpening Up With the dream of building a powerful IC industry in China which we took to be the mission entrusted to our generation, the chief editors of the chapters began to organize their teams and embarked on the writing of more than a thousand entries and a million words. After 9 months of hard work, 468 writers finished the first draft. It was as if they had excavated a huge rock from the mountain of knowledge. Whether it contained precious jade inside or it was just common stone still needed to be tested by practice. From February 19 to 24, 2017, 1 year after the preparatory meeting of the Editorial Committee, the first review meeting of the Handbook was held in Qilin Mountain Villa, Shenzhen. Yangyuan Wang emphasized four basic principles of review at the meeting. 1. Correct and scientific. The content must be correct and scientific, or it will mislead young people. Words written down can last longer than life. It must be able to stand the test of history and withstand the challenge of tens of thousands or even hundreds of thousands of readers. 2. Independent and innovative. To ensure that every entry is written independently, we must stop plagiarism and must not allow any of it to be incorporated into the Handbook. When citing other people’s work, we must make sure to indicate the source in the reference. The intellectual property rights involved will be obtained by uniform payment. 3. Rational and systematic. Is the distribution of content between each chapter reasonable? Is there repetition? Is the Handbook systematically organized? Quality, not quantity, is our priority. Do not rush. High quality is the first criterion we must follow and the first goal we must pursue. 4. Comprehensive and forward-looking in vision. Does the content cover all aspects of the IC industry and the related science and technology both home and abroad? We must ensure forwardness in our vision so as to make our Handbook more useful, or it is likely to fall behind the times and lose practical value. Members of the Editorial Committee present at the meeting read and commented on the draft submitted by the executive editors of each chapter verbatim with great

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prudence. The conclusion was that “achievements are great, problems are many, and prospects are bright.” The achievements referred to the 1200 entries with 1.6 million words; the problems meant various degrees of academic misconduct spreading across entries; the prospects were that there was indeed jade inside and that it could eventually be sculpted into the “most lustrous gem” of the industry. Compared with the writing method of the 1993 edition, we now have the software for editing words and graphs available at any time and the Internet for accessing information available at any time. Only the Internet is both a double-edged sword and a key. Used properly, it opens the treasure house of culture and brings us a wealth of knowledge; used improperly, it may enact Pandora’s Box, leading to the disaster of intellectual property infringement. Intellectual property rights are the exclusive rights of mankind over their intellectual creation in social practice. The World Intellectual Property Organization was established in 1967, and China became a full member in 1980. The Copyright Law of the People’s Republic of China was adopted at the Fifteenth Meeting of the Standing Committee of the Seventh National People’s Congress on September 7, 1990. In 2012, the State Copyright Administration published the Third Amendment to the Copyright Law, which intended to raise the maximum compensation standard for copyright infringement from 500,000 yuan to 1,000,000 yuan. How to avoid infringement of intellectual property rights became the top priority of the first review meeting in Shenzhen. The solution lies in personal integrity (honesty and self-discipline) and legal restraint (the rule of law). Respect for others’ knowledge is the bottom line, the insurmountable red line, which all students and scholars should observe. It is absolutely forbidden to patch up one’s own writing by means of “copy and paste,” or to quote others’ work without proper citation, or to use others’ diagrams and data without authorization. To this end, Yangyuan Wang requested that the Secretariat of the Editorial Committee perform duplicate checking to find out whether the drafts provided by the contributors were identical or very similar to published documents. Wang expressed serious concern over the unsatisfactory results obtained by using the PaperPass Chinese Document Similarity Contrast System on the first draft. Blemishes must be mended; defects must be eradicated. Passing muster in duplicate checking became the top concern after the Shenzhen meeting. It was also like the first knife to sculpt the rock into jade, or the sword of Damocles which served to warn us to be always on guard against intellectual property infringements.

Forging Ahead Duplicate checking demonstrated our reverence for knowledge and respect for others. Its purpose was to eliminate dishonesty and impetuosity. After more than 2 months of revision and adjustment, the second review meeting was held on May 7, 2017, in SMIC, Shanghai (see Fig. 2), exactly 1 year from the establishment of the Editorial Committee. Among the objects of the review were to make sure that the entries were written authoritatively and accurately with professionalism and sophistication; that the English and traditional Chinese words were correct; and that the

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Fig. 2 Participants of the second review meeting held in Shanghai who worked on Chap. 2 of the Handbook

vocabulary, sentences, and references were standardized. At the same time, another round of duplicate checking was conducted on each revised chapter. This meeting was one of high intensity, quality, and efficiency. During the 15 days from May 7 to 21, 2017, Chaps. 2, 4, 6, 7, 8, and 9 were reviewed, and 774 entries totaling 1352 pages were printed and bound into a “mock” book. From May 25 to 31, 2017, the reviewers went north to hold another review session in Beijing. Chapters 1, 5, and 10 were reviewed. A total of 622 pages covering 293 entries were printed and bound into another “mock” book. These two meetings in Shanghai and Beijing reviewed 1974 pages of all the 9 chapters and 1037 entries of the Handbook. Counted by 1600 words per page (including charts), this second review examined a total of about 3,160,000 words, with an average of 160,000 words per day. In view of the fact that Professor Zixue Zhou was chief editor of Chap. 3, the review of Chap. 3 was postponed to June 25 to 30, 2017. After nearly 3 months of careful revision, the results of the second duplicate checking showed that the probability of the drafts being the same or similar to other documents had been greatly reduced, and disputes over intellectual property had been greatly curbed. PaperPass can do a wide range of searches, including all media documents such as books, magazines, and materials from the Internet. However, as a software application, it cannot judge whether duplication is plagiarism and may produce misjudgment on contents such as 1. Referenced literature or data 2. Descriptions of definitions, theorems, and laws 3. Publicly available laws, regulations, data, official documents issued by the state, and excerpts of leadership speeches

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4. Proper nouns (including names of persons, places, things, books, etc.) 5. General descriptions that do not involve intellectual property rights After manual clearing of the above contents, the repetition rate of all the reviewed drafts was reduced to the lowest, with 0 rate for most of the chapters and less than 1% for the rest. A total of 25,969 yuan was paid for the duplicate checking. When the problem of duplication was solved, the payment of references, data, and charts was put on the agenda. These were the second and third “barriers” that we could not bypass and must cross. In other words, we should not only specify the sources of all the referenced documents, charts, and data in detail but should also pay to obtain authorized permission from copyright holders, including publishers, authors, and statistical organizations, in order to ensure that our Handbook did not have any flaws in intellectual property. After nearly 2 months of careful work, the Editorial Committee thought it was time for the final review of all the drafts and decided to hold this meeting in China Workers’ Home in Beijing from July14 to 27, 2017 The aim of this gathering was to carry out the final review of all the chapters, appendices, vocabulary index, English-Chinese index, and the binding design of the Handbook. More than 70 people attended the meeting, including the Editor-in-Chief; Deputy Chief Editors; members of the Secretariat of the Handbook; chief, deputy chief, and executive editors of each chapter; as well as leaders and editors from the Electronic Industry Publishing House. At this final review meeting, Editor-in-Chief of the Handbook Yangyuan Wang delivered a keynote report entitled “Topless is the mount of learning, but we scale it by the path of diligence; boundless is the sea of knowledge, but we sail it by the boat of assiduity.” He thanked all the 134 editorial members, 468 contributors, and 125 reviewers for their hard work in writing and reviewing the 1052 entries totaling 2.4 million words. He also thanked the Deputy Chief Editors and the Secretarial team for their unity, cooperation, perseverance, and conscientiousness in compiling the Handbook. Wang said that the Handbook would first be published in simplified Chinese, and then in English in cooperation with well-known publishing institutions abroad. That would engage more overseas contributors in the writing of the English version. In addition, he would consider issuing a traditional Chinese edition, according to the market demand. SMIC’s Chairman Zixue Zhou, former CEO of SMIC, Rujing Zhang, and Jiuru Liu, Chief Editor of the Electronic Industry Publishing House, made enthusiastic speeches. They believed that integrated circuits would surely take root and grow in China. It was of great significance to make this Handbook, which we could proudly present to future generations as a work representing the highest academic standard of the country in our time. Not only could it pay tribute to the present age, but it would benefit posterity for many years to come. This masterpiece would undoubtedly become a fine addition to the national library. In July 2017, an application was submitted by the Electronic Industry Publishing House for the Series of Books on Integrated Circuits to the Planning and Management Office of the National Publishing Fund. On February 8, 2018, the Office

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officially approved the application and announced the grant of the National Publishing Fund for the Series. The National Publishing Fund is the most influential national cultural fund in the publishing industry, and the third largest national fund after the National Natural Science Fund and the National Social Science Fund. As the first volume of the Series, The Handbook of Integrated Circuit Industry adopted the logo of the National Publishing Fund on its cover.

Fruits in Autumn August 7, 2017, was the day that marked the beginning of autumn according to the Chinese lunar calendar. Bidding farewell to the hot summer, Beijing was now ushering in the golden autumn with cool breezes and a clear sky. The compiling of the Handbook was also nearing its end, just as the ears of rice in the harvest time are drooping and the branches are full of fruits. The Editorial Committee decided to accept Chaps. 1, 4, 5, 6, 7, 9, and 10 from August 24 to 29, 2017, and Chaps. 2, 3, and 8 from September 21 to 28. September 29, 2017, saw the plenary meeting attended by the Editor-in-Chief and Deputy Chief Editors of the Handbook, as well as chief, deputy chief, and executive editors of each chapter. The meeting was briefed on duplicate checking and copyright licensing for citing documents, graphs, and data. For 110 graphs and documents that should be authorized, authorization had been obtained after contacting the relevant parties such as IEEE and the individual authors. The total fee paid was $3700.64. For data referencing, WSTS indicated that Historic Billing Reports and other content published on its official website could be used; IC Insights indicated that public data were available, and private data could be purchased from its McClean Report; SEMI indicated that the content it had audited could be quoted; Gartner indicated that the content of its official website could be quoted but should be quoted strictly according to its required format; Semicast Research and Yole allowed quoting content from its official website; CCID Consulting and China Semiconductor Industry Association said their statistics could be cited. As a result, 103 items of domestic and foreign market data were authorized, of which 32 were from IC Insights, with a payment of 50,954.41 yuan. The fees for checking duplicates and purchasing intellectual property rights of documents, charts, and data totaled 101,347.6 yuan, all of which was funded by the Institute of Microelectronics, Peking University. The costs of all the meetings were funded by Southern University of Science and Technology, Shenzhen Guowei Electronics Co., Ltd., SMIC (Shanghai) Co., Ltd., Huada Semiconductor Co., Ltd., National Integrated Circuit Industry Investment Fund Co., Ltd., and Beijing Huada Jiutian Software Co., Ltd. To them the Editorial Committee hereby expresses its appreciation. After a series of adjustment, such as verifying content, unifying writing standards, degrading duplicate checking, and obtaining authorization, the rock collected from the peak of knowledge had its skin peeled off, cracks avoided, defects eliminated, and scratches smoothed to become admirable jade. With the polishing and decorating done by the Electronic Industry Publishing House, it was now ready to be presented to readers home and abroad.

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At the acceptance meeting, Editor-in-chief Yangyuan Wang commented on the project like this, “Integrated circuits are the Midas touch of the industry, capable of turning stone into gold. The writing of this Handbook is a process of ‘sweeping and sifting the sand until gold peeps through the blown dust’. It is about keeping the valuable and discarding the valueless, or disentangling truth from falsehood. There is no shortcut on the road to science, and no room for falsehood in the pursuit of science. Honesty and credit are the basis of building this Handbook; they are the yardstick that can stand the test of time and the scrutiny of the reader. The Handbook also adheres to three directives, namely, ‘paying tribute to old generations of predecessors, displaying worthiness to the current generation, and inspiring future generations.’ While recording the arduous course of the predecessors’ hard work, it also reveals the overall evolution of the macro-economy and technological advancement, as well as the philosophy and thinking embedded in scientific development.” If life is a journey, then books are the footprints human travelers leave in the world. They convey ideas, spread information, store wisdom, and interpret culture. While we integrate experience and knowledge into our lives like a river that never ceases to flow, books continue as if our life forever. Writing a book is like a test of the soul through which one gets purified. It is also a process of constant absorbing and producing knowledge. The Handbook of Integrated Circuit Industry records how the present generation carries forward past traditions and blazes a trail for posterity. It is an important part of the cultural construction of the integrated circuit and a valuable asset we offer future generations. Kilby invented the integrated circuit back in 1958. Sixty years later, in 2018, The Handbook of Integrated Circuit Industry is exuding life in the field of the IC industry. Here, with a poem let us congratulate its publication as well as the 60th anniversary of the invention of the integrated circuit.

Ode to the Publication of The Handbook of Integrated Circuit Industry The bell, the drum, the beacon fire, Also the stage post and the flying pigeon, And the fish and the wild goose

Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . . For carrying the letters of love, They were how messages were passed in the past. Indeed, I marvel at the romances of the gods, For the fantasies and phantoms they weave. But sages of today offer their wisdom, And make a wonderful idea come true. Like gold extracted from sand, wisdom is condensed in a tiny chip. Family and friends gather together in front of the screen, Spanning both ends of the world, And living lives past and present All at the snap of a finger. Pen and ink make words that last among men. Now that I think of these past three years, What a rough and rugged journey we have made! Talents gathered from around the country. Tilling and plowing, they created a classic, In a volume of ten chapters. Out of debates and discussions, Emerged this history of 60 years, And a guide of the industry, spread far and wide, East and west, north and south, A masterpiece of sweat and blood it is for sure. Why is my heart attached to it so? For the same spirit runs right through Age and youth.

Editorial Committee of The Handbook of Integrated Circuit Industry June 2018

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Section I Technology and Industry Development of Integrated Circuit Min-Zheng Zheng, Yong-wen Wang, and Ke Li

Introduction As one of the greatest inventions of the twentieth century, integrated circuit technology opened a new era in the history of electronic development. Since its invention, integrated circuits have undergone 60 years of development. Through technology research and development, product innovation, and industrial change, integrated circuit plays a leading role in the development of the electronic information industry and the entire scientific and technological community. This section, stands at the beginning of the book, sorts out the development history of global integrated circuit technology and industry, focuses on reviewing the development history of China’s integrated circuit industry, and reviews relevant policies, core links, key institutions, and important events. Information security, intellectual property rights, international cooperation, business management, and personnel training have been comprehensively analyzed. This chapter is written to help readers understand the development history and current status of integrated circuit technology and industry. In the process of writing this chapter, we have received the support and help of China Semiconductor Industry Association, Northern Microelectronics Equipment Company, and industry colleagues, and we would like to express our gratitude. In addition, we have done our best to clearly describe all related subjects in this chapter. Any updated information will be provided in future.

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Invention and Technological Progresses of Integrated Circuits Yong-Wen Wang and Min-Zheng Zheng

Contents Integrated Circuit (IC) and IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology Preparation Before the Invention of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invention and Applications of Electron Tubes and Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invention of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Milestones of Information Acquisition, Storage, and Processing in IC Industry . . . . . . . . . . . . . . . Milestones of Development in IC Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Milestones in IC Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . From Industry Age to Information Age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Market Demand and Driving Force of Information Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Integrated circuits (ICs) refer to circuits that can be fabricated on single crystalline substrates to perform specific functions of logic, analog, memory, RF, and power. IC technology and industry have been progressed for 60 years. IC applications have gradually expanded from the initial military field to all aspects (e.g., industrial, agricultural, transportation, government, finance, security, communications, education, media, and entertainment). The first-generation semiconductor materials are mainly germanium (Ge) and silicon (Si). The second-generation semiconductor materials are mainly gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and cadmium sulfide (CdS). The thirdgeneration semiconductor materials typically have a wide forbidden bandwidth

Y.-W. Wang (*) Institute of Microelectronics, Peking University, Beijing, China e-mail: [email protected] M.-Z. Zheng Department of Information Technology Industry, Ministry of Industry and Information Technology, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_1

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(greater than 2.2 eV), such as silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), and aluminum nitride (AlN). The manufacturing of ICs in a broad sense mainly includes design, fabrication, and packaging (with testing). Keywords

Integrated circuits (ICs) · Logic · Analog · Memory · RF · Germanium (Ge) · Silicon (Si) · Manufacture · Packaging

Integrated Circuit (IC) and IC Industry Integrated circuits (ICs) refer to circuits fabricated on single crystal substrates that can perform specific functions of logic, analog, memory, RF, and power. The circuits or systems can integrate active devices (e.g., transistors, diodes, etc.) as well as passive components (e.g., resistors, capacitors, inductors, antennas, etc.) together on semiconductor wafers, such as silicon (Si) or gallium arsenide (GaAs). Jack S. Kilby (Texas Instruments) and Robert N. Noyce (Fairchild Co.) invented IC technology in 1958 and 1959, respectively. By 2019, IC technology and industry have been progressed for 60 years. Since the invention of ICs, there was active development in 1960s and 1970s, and IC industry was in impressive progresses. In 1965, Fairchild’s Gordon E. Moore published a prediction on the development of ICs in the Journal of Electronics. He believed that the complexity of ICs would double every year at the lowest component cost; this was the original “Moore’s Law.” In 1975, Moore revised the trend to “double the IC complexity every 2 years.” So far, the change in the number of transistors on the CPU is consistent with Moore’s prediction; and the number of transistors in memory ICs doubled approximately every 18 months. The initial manufacturers of ICs are basically “self-produced and self-sold” system manufacturers. This kind of IC manufacturer that designs by itself, processes with its own production line, packages, tests, and sells its own IC chips is called IDM (Integrated Device Manufacturer). With the evolution of IC technology into the 1980s, several different independent enterprises have emerged with dedicated focuses on IC packaging, design, or manufacturing, respectively. They formed industry structures consisting of enterprises dedicated on IC packaging and testing, IC design houses (or fabless production lines), professional chip manufacturing lines (IC Foundry), and intellectual property houses (IP vendor) without actual designing ICs. The IC industry also includes electronic design automation (EDA) tool vendors, IC materials manufacturers and IC equipment vendors, as well as personnel training, industrial investment, intermediate technical services. The line width of earlier IC manufacturing was in the range of 10 μm. Along with the emergence of new technologies (e.g., copper (Cu) interconnection, DUV immersion lithography, and 3D packaging) the line width for IC manufacturing in 2023 has reached 3 nm technology node. The diameter of Si wafers has grown from the original 1 in. (or 100 , 25.4 mm) to the present 300 mm (about 1200 ). In the early stage, the diameter

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(or size) of the Si wafer was in units of an inch (e.g., 300 , 400 or 500 ) and later changed to units of millimeters (mm) when the diameter of Si wafer reached 150 mm. In the general public, the silicon wafer with a diameter of 150 mm is commonly known as a 6 in. silicon wafer in the domestic industry. The diameter of 200 mm silicon wafer is commonly known as the 8 in. silicon wafer, and a silicon wafer with a diameter of 300 mm is commonly known as a 12 in. silicon wafer. The IC technology, as born in 1958, opened the door for human society advancing toward an information society. IC applications have gradually expanded from the initial military field to all aspects (e.g., industrial, agricultural, transportation, government, finance, security, communications, education, media, entertainment, etc.). The science, technology, and industry of IC not only become the driving force to accelerate the sustained economic growth and change the way of human production and lifestyle, but also become an important factor related to the outcome of modern war. The scale, level of science and technology, as well as innovation ability of IC industry are becoming important symbols to measure the comprehensive national strength of a powerful country. Integrated circuit technology has created a new information world for human beings and has made indelible historical contributions in the development of human society. Furthermore, in the information society, integrated circuit has become the tripod of the strong country, the treasure of the rich country, the tool of the national renewal, and the foundation of the national stability.

Technology Preparation Before the Invention of ICs Human understanding of electricity comes from the triboelectrification. Wang Chong of the Eastern Han Dynasty discussed the phenomenon of “Dunmu Tuzhu (顿牟掇芥)” in his book Lun Heng - Disorderly Dragon (论衡•乱龙). Dunmu, namely, means amber, and Tuzhu, namely, to attract small and light things. However, the amount of charge generated by the triboelectric effect is small and unsustainable. 1745: Professor Pieter van Musschenbroek of Leiden University in Leiden city, the Netherlands, invented the container “Leiden bottle” that can store charges. However, the charge in the Leiden bottle still cannot store enough electricity, and the flow of charge cannot be controlled. 1752: Benjamin Franklin, an American scientist, carried out his famous experiment of “kite electrification” and came up with terms such as “electric current,” “positive charges,” and “negative charges.” 1799: Alessandro Volta, an Italian physicist, succeeded in making the world’s first battery, a “voltaic pile.” Since then, human society has an artificially made and controllable “power source.” 1820: Hans C. Oersted, a Danish physicist, discovered the magnetic effect of electric current. 1826: Georg S. Ohm, a German physicist, published the famous Ohm’s law.

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1827: André M. Ampère, a French physicist, published the book of Mathematical Theory of Electrokinetic Phenomenon and invented the electric current meter. 1831: Michael Faraday, a British physicist, discovered the phenomenon of electromagnetic induction, so that the human mastered methods of the mutual transformation between electromagnetic fields and motion as well as the mutual transformation method between mechanical energy and electrical energy. 1864: James C. Maxwell, a British physicist, published a paper of “The Dynamics Theory of Electromagnetic Fields.” 1865: The British physicist Maxwell predicted the existence of electromagnetic waves and proved that the speed of electromagnetic waves in a vacuum is equal to the speed of light, which became the basis of modern radio technology. 1866: Werner Siemens in Germany invented the self-excited DC generator. 1888: Nikola Tesla, a Serbian-American, invented the AC multiphase power transmission system, which significantly promoted the process the second industrial revolution and made human society rapidly enter the age of electricity. In the same year, the German physicist Heinrich R. Hertz confirmed the existence of electromagnetic waves predicted by Maxwell with experiments. 1897: Joseph J. Thomson, a British physicist, discovered the direct evidence for the existence of electrons from experiments. The discovery of electrons revealed the nature of electricity. 1900: Max K. E. L. Planck, a German physicist, put forward the hypothesis that the radiation energy of matter is discontinuous, introduced the concept of energy Quantum, and established the Quantum theory. 1913: Niels H. D. Bohr, a Danish physicist, proposed a new model of quantized atoms. 1926: Erwin Schrödinger, an Austrian physicist, systematically expounded the theory of wave mechanics and proposed the Schrödinger eq. 1928: Max K. E. L. Planck, the founder of quantum theory, put forward the basic idea of solid “Energy Band Theory.” The theory elaborated that under the action of an external electric field, the electric conduction of semiconductor is performed by two kinds of carriers: the holes in the valence band and the electrons in the conduction band. The conduction process in which “holes” participate is called p-type conduction, and the conduction process in which electrons participate is called n-type conduction (the basic operation principle of bipolar and MOS integrated circuits). The energy band theory scientifically stated for the first time that solids can be divided into conductors, semiconductors, and insulators according to their electrical conductivity. 1930: Paul A. Maurice Dirac, a British physicist, wrote the book Principles of Quantum Mechanics, to put forward the famous Dirac equation, and theoretically predict the existence of positron and magnetic monopole. 1931: Alan H. Wilson, a British physicist, proposed the physical model of semiconductor on the basis of energy band theory and explained the mechanism of “impurity conduction” and “intrinsic conduction.” All the varying properties and wide application value of semiconductors are determined by the conduction

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mechanism of impurities. The Wilson model laid the theoretical foundation of semiconductor physics. 1939: Germany’s W. H. Schottky, Britain’s N. F. Mott, and the Soviet Union’s Davydov (Б вавыдов) almost simultaneously applied the concept of “Potential Energy Barrier” of metal-semiconductor contact to establish the “diffusion theory” that explained the rectification of metal-semiconductor contact. Thus, these three interrelated and gradually developed semiconductor theoretical models, namely, energy band theory, mechanism of semiconductor conduction, and diffusion theory, constituted the theoretical basis for establishing the technological invention of the transistor. At this point, scientists had made theoretical and practical preparations ready for the invention of transistors.

Invention and Applications of Electron Tubes and Transistors At first, the key components of electronic equipment were the electron tubes, which controlled the movement of electrons in a vacuum. 1879: Thomas A. Edison, an American inventor, lit up the first practical light bulb. On January 27, 1880, Edison filed a patent for the invention of the electric light bulb. 1904: J. A. Fleming, a British inventor, based on the “Edison effect” to add a metal plate (anode) into the “light bulb” with only a filament, then invented a vacuum diode and obtained a patent. After that, vacuum diodes have been used for detection and rectification in radio technology. 1907: De F. Lee, an American inventor, created the first electronic vacuum triode by adding a grid to the diode. The triode combined the “magnification,” “detection,” and “oscillation” functions in one. This makes it a core component of radio transmitters and receivers. 1918: The United States produced more than one million electronic tubes in a year. This amount is more than 50 times that before the First World War (1914–1918). By the mid-1950s, home radios were all made with electronic tubes. 1946: The University of Pennsylvania developed the world’s first Electronic Numerical Integrator and Computer (ENIAC). John von Neumann was a member of the R&D team. ENIAC utilized 17,468 electronic tubes, consumed electric power of 150 kW, weighted 30 t, and occupied an area of approximately 170 m2. It performed 5000 addition operations or 400 multiplication operations per second. The calculation speed was 1000 times faster than that of the relay computer and 200,000 times that of the manual calculation. The main disadvantages of the electronic tube were that it took time to heat the filament with a prolonged start-up process. At the same time, the heat generated by the filament must be discharged from time to time, and the filament life was short. For example, it was possible to burn a tube almost every 15 min and causing the entire computer to stop running. It took more than 15 min to find the damaged one in 17,468 tubes. Therefore,

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Fig. 1.1 Transistor inventors. (From left: Bardeen, Shockley, Brattain)

ENIAC’s average trouble-free working time was only 7 min. For these reasons, there is an urgent desire to replace the electron tube with a device that does not require a preheated filament, and which consumes less power and can control the movement of electrons in the solid. 1946: Bell Labs founded a solid physics research group consisting of William B. Shockley, John Bardeen, and Walter H. Brattain (Fig. 1.1). On December 16, 1947, Brattain and Bardeen had successfully experimented a point-contact germanium (Ge) transistor, which was the world’s first transistor, as shown in Fig. 1.2. The preliminary test results showed that the device had a voltage gain of 100 and an upper frequency up to 10,000 Hz. Brattain thought of its resistancetransformation characteristics, that is, it worked by transferring current from “low-resistance input” to “high-resistance output,” so it was named as “Transresistor,” and later shortened it to “Transistor.” 1948: Shockley proposed the theory of the pn junction transistor, and in 1950, together with Morgan Sparks and Gordon K. Teal, successfully developed the germanium npn triode (as Ge-npn transistor). The invention of the transistor pioneered the subject of microelectronics. Compared with the electronic tube, the transistor has the advantages of long lifespan, less power consumption, small size, no preheating, impact resistance, and vibration resistance, so it soon gets the favor of the market. 1953: Hearing aids were introduced to the market as the first commercially available devices using transistors.

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Fig. 1.2 The world’s first transistor

Oct. 18, 1954, the first transistor radio “Regency TR1” was launched to the market and contained only four germanium (Ge) transistors. By 1959, transistors were already used in half of the ten million radios sold. Jan. 1954, Bell Labs assembled the world’s first Transistor Digital Computer, TRADIC, with 684 transistors, as shown in Fig. 1.3. 1957: IBM started to sell computer IBM-608 that used 3000 transistors; it was the world’s first commercially available computer. The IBM-608 computer consumed 90% less power than a computer using electron tubes. Its clock frequency was 100 kHz and supported 9 instructions. Its average time of multiplying two 9-bit BCD numbers was only 11 ms, and the weight was about 1 t.

Invention of ICs Although the weight of the transistor computer IBM-608 was only 1/30 that of ENIAC, the weight of 1 t was still impossible for the Army’s soldiers to carry, and it was also not likely to be loaded on an aircraft. In the early 1960s, a calculator capable of four arithmetic operations, powers, and taking the square root was comparable in weight to a 2100 CRT TV set, and its volume also far exceeded that of the abacus and calculation ruler. To this end, the National Bureau of Standards (NBS), US Air Force, and US Navy were all committed to the research and development of electronic equipment miniaturization. In the United States, there were three aspects to the development of electronic equipment miniaturization: (1) The Army’s Signal Corps supported the Micro Modules to miniaturize and integrate components on existing ceramic substrates; (2) The Navy focused on supporting the thin film

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Fig. 1.3 TRADIC

technology; (3) The Air Force supported the integration work called “molecular electronics.” 1952: The concept of integrated circuits was first introduced and described by a British scientist, G. W. A. Dummer, at an electronic components conference at the Royal Signal and Radar Establishment. He said: “With the advent of transistors and comprehensive research on semiconductors, it now seems possible to imagine that the future electronic equipment will be a solid module without interconnecting wires.” Although Dummer’s idea was not implemented at that time, he pointed out the direction for further research. 1958: Jack S. Kilby, who was responsible for the miniaturization of electronic equipment at Texas Instruments (TI), proposed the idea of integrated circuits. He said: “Since capacitors, resistors, transistors, and all other components could be made of one material, I thought we would make them on a piece of semiconductor material and then interconnect them to form a complete circuit” (this was Kilby’s dialogue with Prof. Yangyuan Wang during his visiting to Peking University in 2001). On September 12 and 19, 1958, Kilby completed the manufacture and demonstration of a phase-shifted oscillator and trigger, respectively, which marked the birth of the integrated circuit (Kilby’s integrated circuit was made of germanium transistors due to the limitations of TI’s production conditions at that time). On Feb 6, TI applied for a patent of a Miniaturized Electronic Circuit, Patent No. 3,138,743 and on May 6, 1959, applied patent 3,138,744, both were approved on June 23, 1964. Kilby and the first integrated circuit patent are shown in Fig. 1.4.

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Fig. 1.4 Kilby and the first IC patent

On March 6, 1959, TI announced the invention of the “Solid State Circuit,” or Integrated Circuit (IC) at a press conference of the Institute of Radio Engineers (IRE, the predecessor of the Institute of Electrical and Electronics Engineers, IEEE) in New York. On July 30, 1959, 5 months after TI patented the invention of integrated circuit, Robert N. Noyce of Fairchild Co. applied for a patent of IC based on Si planar technology (Patent No. 2,981,877, approved on April 25, 1961). Noyce and his planar IC patent are shown in Fig. 1.5. Noyce’s invention is more suitable for the mass production of integrated circuits. In 2000, Kilby was awarded the Nobel Prize for Physics [1]. The Nobel Prize committee said that Kilby “laid the foundation for modern information technology.” Unfortunately, the Nobel Prize is not awarded to a deceased person, and Noyce died on June 3, 1990, thus failing to receive the honor. When we saw the first sample of an integrated circuit, we were surprised at its simplicity and roughness, but it was always worth pondering the broad and profound wisdom it contains.

Milestones of Information Acquisition, Storage, and Processing in IC Industry Technology is the method and principle of problem-solving. It is the method that people use existing things to form new things, and/or change the function and performance of existing things. The development of technology is progressed by mainly asking questions of why (demand), what to use (material), and how to do it (process). At first, human beings could only obtain information directly through their senses, such as Chinese medicine’s looking (vision), smelling (hearing), asking (hearing), and cutting (touch).

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Fig. 1.5 Noyce and his planar IC patent

Imaging sensor and micro-electro-mechanical system (MEMS) are two milestones of IC in the field of information acquisition. Since visual information accounts for the largest proportion of the total amount of information acquired by human beings (about 83%), how to convert this image information into digital signals has become the most urgent demand of people. In 1969, Willard S. Boyle and George E. Smith of Bell Labs invented the Charge Coupled Device (CCD). CCD solved the problem of converting optical images into digital signals. In 2009, these two inventors won the Nobel Prize in Physics. In 1992, Eric Fossum of the Jet Propulsion Laboratory (JPL) invented the CMOS Active Pixel Sensor. Compared with CCD, CMOS has the advantages of smaller size, less than 1/10 of the power consumption of CCD, and the price is 1/3 cheaper than CCD. Currently, the photosensitive devices of digital cameras (including mobile phones) are mostly CMOS image sensors. The development of MEMS started with silicon micro-pressure sensors. In 1959, Richard P. Feynman proposed the idea of micro-machinery. In 1988, Richard Muller and colleagues in the Berkeley Sensor & Actuator Center (BSAC), of UC Berkeley,

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fabricated from silicon the world’s first operating micromotor [2], with a rotor diameter of 60–12 μm. MEMS can integrate speed, temperature, humidity, altitude, sound, pressure, orientation, gas, and other sensors, so that people can intuitively feel the analog information (quick or slow, hot and cold, dry and wet, strength, etc.) which can be accurately digitized. After the data collected by sensors are stored and processed in MEMS, data can be output to internal actuators, such as gyroscopes and motors, and can also be exchanged with external devices. The most significant contribution of semiconductor memory is for the storage of massive information. Humans originally stored information through the brain, and the way they transmitted information was by oral instruction. Subsequently, information about the development of human history was stored in natural objects (such as rocks, tortoiseshells, bamboo slips, sheepskins), man-made artifacts (such as bronzes, pottery), and buildings. Paper is the most extensive and oldest medium used by man to store information. The memory of electronic computers was first electromechanical devices (e.g., relays) and later magnetic media (e.g., drums, tapes, cores). However, magnetic medium still has the disadvantages of large volume, large mass, and small storage capacity. After Frank Wanlass and Chi-Tang Sah of Fairchild put forward the concept of metal-oxide-semiconductor (MOS) in 1963, in July 1967, two types of semiconductor memory were invented simultaneously: One was the Dynamic Random Access Memory (DRAM) invented by Robert Dennard, who worked at IBM. The other is the non-volatile Semiconductor Memory (NVSM) invented by Simon Min Sze, a Chinese-American scientist, and Dawon Kahng, a Korean scientist working in Bell Laboratories in the United States. In 1969, Intel successfully developed the 64-bit bipolar Static Random Access Memory (SRAM) chip C3101as the pioneer of semiconductor memory. In 1984, Fujio Masuoka of Toshiba of Japan developed the Flash Memory based on the original NVSM concept. DRAM stores data for a short time and requires refreshed periodically. DRAM is generally used as computer memory. Flash memory can hold data for a long time and is generally used as the external storage of a computer. In 1970, Intel introduced 1Kbit MOS DRAM (Type C1103) using a 12 μm process. The commercialization of 1 Kbit DRAM led to the rapid replacement of magnetic core memories in computers by semiconductor memories. Today, the memory capacity of DRAM has reached the order of magnitude of 109 bits. In 1988, Intel was the first to produce 256 Kbit flash chips and put them on the market. Today, the maximum capacity of Solid State Drive (SSD) made up of flash memory has reached the order of magnitude of 1013 bits, which is likely to replace Hard Disk Drive (HDD). The earliest data processors can be traced back to arithmetic, the abacuses, slide rulers, mechanical computers, and later, electronic tube computers and transistor computers. Although the latter was much faster than the former, its size, weight, and power consumption were difficult for ordinary enterprises, families, and personal users to handle.

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In 1971, Intel’s Hoff invented the Central Processing Unit (CPU) model 4400, which played the most important role in the historical stage of information processing. So far, the Microprocessor Unit (MPU) has become an indispensable core component of all electronic devices.

Milestones of Development in IC Materials The first-generation semiconductor materials were mainly germanium (Ge) and silicon (Si). The earliest semiconductor material was Ge, and the world’s first transistor and the first IC were based on Ge. In 1886, the German chemist C. A. Winkler firstly produced germanium, in honor of his home country. He named the new element germanium, derived from the Latin German name Germania. In 1950, American G. K. Teal and J. B. Little adopted J. Czochralski’s method (also known as CZ method) and pulled out Ge monocrystalline. The thermal conductivity of Ge is relatively low, 64 W/(m•K). Devices fabricated with Ge can only operate below 90  C. When the temperature is higher than 90  C, the leakage current of germanium devices increases significantly. The melting point of germanium is only 937  C, and it is difficult to withstand such as doping, activation, annealing, and other high temperature processes. At the same time, the oxide of Ge is soluble in water and the structure is unstable. Therefore, it is impossible to make MOS devices. More importantly, the mechanical properties of germanium are poor, the diameter of germanium single crystal should not be very large, and the processing and transportation of germanium chips also have certain safety problems. In 1952, Teal and E. Buehler pulled out a single silicon crystal with the CZ method. Subsequently, Texas Instruments (TI) successfully manufactured the first Si transistor in 1954. Si has a large band gap width (1.106 eV) and the high thermal conductivity (145 W/(m•K)). Silicon dioxide (SiO2) is the best dielectric insulating material, and Si is one of the most abundant elements on earth (about 26% of the weight of the earth’s crust). Because of these advantages, Si has become the mainstream material of semiconductors since 1960s. The second-generation semiconductor materials were mainly III-V compound materials such as gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and cadmium sulfide (CdS), which are suitable for the production of high-speed, high-frequency, high-power, and light-emitting electronic devices. They are excellent materials for making high-performance microwaves, millimeter-wave devices, and light-emitting devices. They are also widely used for satellite communication, mobile communication, optical communication, and for applications such as the global positioning system (GPS) and other fields. The third generation of semiconductor materials mainly refers to silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), and aluminum nitride (AlN) represented by wide band gap (band gap width greater than 2.2 eV) semiconductor materials. These materials have many excellent properties, such as wide forbidden band gap, high breakdown electric field, high power density (the power density of

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GaN is 10–30 times that of GaAs), high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, they are more suitable for making high-temperature, high-frequency, radiation-resistant, high-power devices, and semiconductor lasers. At present, the more mature third-generation semiconductor materials are silicon carbide and gallium nitride. However, silicon carbide is more mature than gallium nitride. With the development of new devices, there is much more extensive research on high-k dielectric materials (e.g., oxides of Mg, Ca, Sr, Ba, Zr, La, Hf, etc.), metal gate materials (e.g., TiN, Al, Ni, lanthanide metals, rare earth metals, etc.), interconnect materials (e.g., Al, Cu, Ti, Ta, W, etc.), memory materials of various transition metal oxides (e.g., BaTiO3, SrTiO3, TiO2, ZrO2, NiO, MoO3, V2O5, WO3, ZnO, etc.), epitaxial and substrate materials (e.g., strained silicon, FD-SOI, etc.), and carbon-based materials (e.g., carbon nanotubes, graphene, etc.). For example, III-V group materials are used for the Fin Field-Effect Transistor (FinFET) to increase the carrier’s mobility. In interconnect structures, titanium (Ti), cobalt (Co), nickel (Ni), or ruthenium (Ru) are used to form wires, and titanium nitride (TiN), Ta, or TaN as barrier materials. In addition, Intel has applied metal Co for local interconnection M0 and M1 in 14 nm technology node, and TSMC also applied Co as local interconnection metal in its 7 nm technology node.

Milestones in IC Manufacturing Generalized IC manufacturing mainly includes IC design, chip manufacturing, and chip packaging (including testing) three aspects. The initial design method of integrated circuit was all manual design, such as manual drawing, manual-carved multilayer masks for exposure, etc. Manual design was only suitable for small-scale integrated circuits. In 1970s, the first generation of integrated circuit Computer Aided Design (CAD) system came out. Because computers at the time did not have enough memory storage, and the computing speed was also not fast enough, CAD tools could only handle simple tasks of layout level design. In the late 1970s, simulation, automatic layout, and routing tools emerged to improve the efficiency of integrated circuit design. In 1983, Workstation emerged on the market and strongly supported the development of CAD technology, also the beginning of commercial EDA. The second generation of CAD system or EDA now appeared, which increased the function of logic-level design capabilities. In the 1990s, EDA entered the third generation, which brought behavior-level design into the scope of automation design by means of Hardware Description Language (HDL). After entering the twenty-first century, IC Design develops toward Design for Manufacturability (DFM), and its important technical directions include hardware/software co-design, IP library, low power design, reliability design, as well as System on Chip (SoC) and System in Package (SiP). Integrated circuit manufacturing is the process of making specific patterns on specific thin films. Among them, oxidation, epitaxy, doping (diffusion, ion implantation), and deposition (physical vapor deposition, chemical vapor deposition) are

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thin film manufacturing process, and photolithography (exposure and etching) process are patterning processes. Exposure and etching are the core technologies for the fabrication of IC patterns. The first step is to reduce the wavelength of exposure light source for shrinking the feature size. Before the mid-1970s, the exposure source was mercury lamps, as multiwavelength light sources with a wavelength range from 400 nm to 700 nm. In 1982, the exposure light source was modified to Ultraviolet (UV) G-line (wavelength 436 nm) and I-line (wavelength 365 nm). In 1994, the wavelength of exposure light source entered the field of deep ultraviolet (DUV), and mainly are excimer laser KrF (wavelength 248 nm) and ArF (wavelength 193 nm). In December 2003, the company Advanced Semiconductor Material Lithography (ASML) of the Netherlands released the world’s first commercial immersion lithography equipment. By filling the pure de-ionized water between the lower surface of the last lens of the objective projection lenses and the silicon wafer, thus the effective wavelength of the exposure light source is shortened to extend the 193 nm lithography to 32 nm CMOS technology nodes. In addition, by using double exposure/ double patterning technology (DPT), 193 nm immersion lithography has been extended to 10 nm/7 nm technology nodes. After a specific pattern exposure of the film, but also to remove the unwanted part to get the desired graphics, this is the etching process. The initial etching technique is wet etching, because of isotropic etching, so the controllability of pattern size is poor. After 1980, the etching technology entered the era of dry etching, including plasma etching and Reactive Ion Etching (RIE), which is the current mainstream etching technology. When all the transistors are made on silicon wafers using thin film technology and lithography, millions or billions of transistors must be connected by interconnection technology, according to the design rules, to form real circuits. The initial interconnection material is aluminum (Al), and studies have shown that the delay generated by the interconnection has exceeded the gate delay in the case of 0.25 μm process (with aluminum wire, SiO2dielectrics). In 1997, IBM announced the introduction of chips using copper (Cu, with conductivity of 59.6  106 S/m or resistivity of 1.7 μΩ cm) interconnection technology, known as the famous mosaic (Damascene) technology. The whole machine or system is the interface between ICs and the final consumer. The value of the integrated circuit can be realized only through its application in the whole machine or system. Packaging is the interface between the integrated circuit chip and the whole machine or system. Only the packaged chips can be loaded into the system and play their due role in the system. The original IC packaging followed the transistor outline (TO) packaging form. In the mid-1960s, dual in-line package (DIP) became the mainstream of IC packaging. In the 1980s, the surface mount technology (SMT) was developed rapidly, with the emergence of various packaging forms, such as plastic leaded chip carrier (PLCC) package and plastic quad flat pack (PQFP).

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Fig. 1.6 Milestones in the developing process of IC manufacturing technology

From 1980s to 1990s, the leads of IC packages evolved from perimeter type to surface arrays, such as pin grid array (PGA) packages. Since the Ball Grid Array (BGA) packaging in the 1990s, the “plug-in” concept of packaging was subverted by SMT, in which “pins” were replaced by “solder balls.” At the end of the twentieth century, the Chip Scale Package (CSP) solved the contradiction between a small chip area and the large package area, which led to the revolution of package technology. In the future, IC packaging will develop toward the System in Package (SiP). The most important technology in 3D packaging is the Through Silicon Vias (TSV), based on IBM’s Merlin Smith and Emanuel Stern’s invention, patented in 1964, and has been used in integrated circuit packaging since 2010. Another trend in IC manufacturing technology is the continually increasing diameter of silicon wafers. Take Intel production line as an example. In 1972, the diameter of silicon wafer was 3 in. (or 75 mm), and in 1992, it was 200 mm. In 2002, Intel established the first 300 mm silicon wafer production line. In summary, important milestones in the development of IC manufacturing technology are shown in Fig. 1.6.

From Industry Age to Information Age Before the eighteenth century, the world was in the period of agricultural civilization. As an indicator of economic development, the gross domestic product (GDP) had been at a low level and only slightly increased with the natural growth of the population. From the first year AD to 1820, the world’s population had a compound annual growth rate of 0.0084%, and the GDP had a compound annual growth rate of 0.105%.

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In 1776, James Watt invented the first practical steam engine and triggered the first energy-based industrial revolution. In the arena of industry and society, the increased production efficiency and improved life quality arrives at the cost of energy, especially the disposable energy. Without the intervention of energy, there could be no progress in industry society. As shown in Fig. 1.7, from 1820 to 1950, the world population increased to 2.42 times of 1820, energy consumption increased to 3.36 times of 1820, and GDP increased to 7.73 times of 1820 [3]. The annual growth rate of world energy consumption and GDP from 1965 to 2015 is shown in Fig. 1.8 [4].

Fig. 1.7 Growth of population, energy, and GDP in industrial society

Fig. 1.8 Annual growth rate of world energy consumption and GDP in 1965–2015 [2]

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Fig. 1.9 Global transistor yields

In 2014, semiconductor manufacturers worldwide produced 2.5  1020 transistors (see Fig. 1.9), or 8 trillion transistors per second. At the time, the total number of transistors shipped worldwide since the invention of the technology was 2.9 sextillion (2.9  1022). However, as the manufacturing process continues to improve in accordance with Moore’s Law, by 2018, the world has made a total of 13 sextillion (1.3  1023) MOSFET transistors, that is, in 4 years, MOSFET transistor manufacturing total increased by 10 sextillions. By 2022, the total number of MOSFET transistors manufactured worldwide has exceeded 30 sextillions, compared with 60 billion transistors per Intel CPU today. According to IC Insights statistics, in 2015, the global IC market size was USD$286.9 million and reached $ 452.3 million in 2021 [5]. As can be seen from Fig. 1.10, the average annual growth rate of world GDP in agricultural societies from A.D. 1 to 1820 was only 0.105%. In the early industrial society from 1820 to 1950, the average annual growth rate of global GDP reached 1.585%. In the post-industrial society from 1950 to 1998, the annual average growth rate of global GDP further reached 3.908%. From 1998 to 2012, when human society entered the early stage of information society, the average annual growth rate of global GDP jumped to 6.622% [6]. Between 2012 and 2019, the growth rate has been maintained between 2.33% and 3.28% [7].

Market Demand and Driving Force of Information Technology Language is the first carrier for representing human’s information. Writing is the first tool to record language (sound information) and has become the second carrier of human recording information. In 1877, the American inventor Thomas A. Edison invented the phonograph. In 1887, the German inventor Emile Berliner invented records that could be reproduced in large numbers. In 1898, the Danish scientist Poulsen Valdemar invented the steel wire recorder.

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Fig. 1.10 Innovation is the source of value: changes in the global total GDP

In 1935, German company AEG built the world’s first practical reel-to-reel tape recorder, K1, which was demonstrated at the Berlin Radio Show. In 1963, the Dutch company Philips (now NXP) invented the cassette tape recorder. In 1980, Sony and Philips jointly developed the technical specification of CDs (compact disks). The storage medium of sound changed from the magnetic domain to physical deformation (depression) of the carrier (plastic), and the method of accessing sound information changed from electromagnetic conversion to photoelectric conversion. That is, what recorded was no longer analog sound but digital audio. In 1995, Karlheinz Brandenburg, a German, developed the MP3 format, and digital music recording and playing with Flash memory gradually became the mainstream of portable recorders. The earliest recorded information by mankind was the image information. Generalized image information includes written words, paintings, artifacts, costumes, sculptures, architecture, etc. In 1826, the Frenchman Joseph Nicéphore Nièpce first left light on the object (a lead-tin alloy was coated to the asphalt); for the first time, a “chemical reaction” was added to the information processing method. In 1895, the French brothers Louis and Auguste Lumière invented the motion picture machine, which turned the still images into moving images for the first time. In 1960, the American Ampere company successfully developed the first video camera. Continuous images were recorded through the change of magnetic field, in

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which the carrier was plastic, and the information processing method changed from chemical reactions to electromagnetic conversion. In 1975, the American Kodak company invented the “digital camera,” so that images can be converted to digital. In 1993, the Chinese company Wanyan produced the world’s first VCD (Video Compact Disc). The information recorded on the disc was represented as carrier deformation (depression), and the information processing method was photoelectric conversion. In 1995, Sony and Toshiba groups launched DVD (Digital Versatile Disc) products in different formats respectively. In the twenty-first century, with the rapid development of the integrated circuit industry, the capacity of semiconductor memory has expanded dramatically, and the working speed of the processor has also improved rapidly, making it possible to take and playback photos or videos including audio in real time. In addition to sound and image information, abstract data is also an important way of information expression. The tools used by humans to record and process data and information have evolved over a long period of time from string recording, arithmetic, abacus, mechanical computer, slide rule, and perforated paper tape. In 1945, Von Neumann, an American scientist, a Hungarian origin, proposed the principle of stored program, which formed the von Neumann architecture of computers that have continued to this day. In 1946, the research and development team of the University of Pennsylvania developed the world’s first Electronic Computer ENIAC (Electronic Numerical Integrator and Computer). In 1948, An Wang, a Chinese American, invented a magnetic core memory made of ferrite material. In 1950, IBM introduced reel-to-reel magnetic tape as the computer data storage. In the same year, Yoshiro Nakamats of the Tokyo University invented the floppy disk. In 1953, the first magnetic drum was used in the IBM 701 computer. In 1956, the IBM 305 RAMAC computer used disks as its external storage for the first time. In 1970, Intel’s semiconductor memory quickly replaced the magnetic core memory. In 1971, Ted Hoff and Stanley Mazor conceived Intel’s 4004 4-bit device, the first integrated CPU. As the most important role, IC appeared in history for data storage and information processing. In 1976, Steven Paul Jobs assembled the first microcomputer and founded Apple Computer Company, today’s Apple Inc. In 1981, IBM officially produced the Personal Computer (PC). Since then, the storage and processing of all kinds of information, including text, sound, images, and data, have really stepped into the era of electronic computers. The activity of information exchange is an integral part of human civilization, and information generates value through sharing and exchange. The earliest information transmission activities were carried out through beacon towers, carrier pigeons,

Transmitting of information media Time period Method of information transmission Principal subject of information processing

Record carrier of information

Time period Record form of information Record media of information

17–18C Post-stand, post office

Human, mechanics

Ancient Voice-sound, hand delivery

Human

Writing, object,

Paper, wood, metal

Carrier form (abacus, slide rule, punched tape, mechanical computer)

Color, tracing, shape, structure

Bone, shell, stone, bamboo, wood, clay, cloth, paper, metal, etc. Language, writing

17–18C Analog information

Ancient Script, drawing, sculpture, construct

Table 1.1 Evolution of information technology

Mechanics, chemistry

19C Telephone, telegram

Conducting wire, electric code

Carrier form (hand-cranked phonograph) Magnetic field change (steel wire, magnetic recorder) Chemical change (photo, movie) Metal, plastic

19C Analog information

Electron tube, transistor, IC, software

20C Broadcasting, TV

EM wave

Carrier form (CD) Magnetic field change (audio recording, video recording, magnetic core, magnetic disk, magnetic drum) Electric charge change (semiconductor storage, audio recording, video recording, writing and image processing) Metal, plastic, semiconductor

20C Analog information, digital information

IC, software

21C Internet, satellite

EM wave

Semiconductor

Electric charge (RT information capture, RT information storage, RT information processing, RT information transmitting)

21C Digital information

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drifting bottles, etc. Since then, the way of conveying information through the combination of people and vehicles of transportation has been used up to now. In 1837, Samuel F. B. Morse, an American, invented Morse code, which solved the problem of instant text transmission. On March 7, 1876, Alexander Graham Bell, an American, invented the telephone and solved the problem of instant (wired) transmission of sound. Bell received the first patent for an “apparatus for transmitting vocal or other sounds telegraphically.” In 1906, the American physicist Reginald A. Fessenden used radio broadcasting stations to achieve the wireless transmission of sound. In 1923, the Russian American physicist Vladimir Kosma Zworykin invented the photoelectric camera tube for converting the image into electrical signal for the first time and opened a new method for image transmission. In 1929, Vladimir Kosma Zworykin manufactured the television picture tube and carried out the complete test of television image transmission, which completed the process of making television camera shooting and display fully of electronic process. In the twenty-first century, due to the progress of microelectronics technology, liquid crystal and plasma flat panel displays (FPD) have gradually replaced the Cathode Ray Tube (CRT) displays. Image sensing, transmission, and visualization all are performed in “solids” of electronic devices, which make it possible for mobile devices to transmit information. Microelectronic technology has created a new information world for human beings and created indelible historical achievements in the development of human society. Table 1.1 summarizes the evolution of information technology.

References 1. Invention of the integrated circuit, https://en.wikipedia.org/wiki/Invention_of_the_integrated_ circuit 2. Fabrication of micromotor, https://www.sciencedaily.com/releases/2003/07/030724084133.htm 3. X. Wu, X. Xu, Y. Ye, et al., Madison World Economic History Millennium (Peking University Press, Beijing, 2003) 4. Statistical review of world energy 2016; Spencerdale presentation. http://www.bp.com/en/global/ corporate/energy-economics/statistical-review-of-world-energy/downloads.html. Accessed 01 June 2023 5. IC Market Size, https://icinsights.com/news/bulletins/Worldwide-IC-Market-Forecast-To-Top500-Billion-In-2021/. Accessed 01 June 2023 6. W. Yangyuan, W. Yongwen, Strategy: The Foundation of Survival and Development (Science Press, Beijing, 2015) 7. World GDP Growth Rate 1961–2022, https://www.macrotrends.net/countries/WLD/world/gdpgrowth-rate. Accessed 01 June 2023

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Characteristics and Strategic Significance of IC Industry Yong-Wen Wang and Min-Zheng Zheng

Contents ICs and Green Economy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICs and Social Life and Culture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Value Goes to Where the Knowledge Is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

IC technology has both strategic and marketable dual characteristics. The former displays strategically the importance of electronic content is so high and critical, including (1) in national information security of political, economic, and military aspects; and (2) in national defense system, such as weapons equipment, spacecraft, satellites, etc. The latter manifests IC applications in the core of the Internet and the Internet of Thing, through network, routers with chips and operating systems, and these essential devices. It is acclaimed that IC is yet a middle-product, and the enduser determines the market needs. Market driving force and technology progress have been promoting IC development and application. China consumed 474.2 billion pieces of IC products (72% imported) in 2016, this consumption is estimated for a total production by 237 1200 -fabs, each to run at 30,000 WPM and to produce 2 billion chips per year. In 2021, the import value of IC in China was $433B, for a total 538.4 billion pieces, displaying continuously a tremendous impact on IC market. Therefore, IC industry results in values and leading forward the development of technology, such as in the green economy, social and cultural life.

Y.-W. Wang (*) Institute of Microelectronics, Peking University, Beijing, China e-mail: [email protected] M.-Z. Zheng Department of Information Technology Industry, Ministry of Industry and Information Technology, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_2

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Keywords

Green economy · Internet · Internet-of-Things (IoT) · Energy consumption · PC

ICs and Green Economy The progress of industrial society has gradually extended human physical labor to mechanical operations, but people have also paid a huge energy price for this, e.g., coal, oil, and natural gas buried underground millions of years ago to maintain the high-speed operation of industrial economy. While enjoying the convenience, speed, comfort, and pleasure brought by industrial products, people also began to experience the bitter fruit brought by industrial pollution. In order to no longer breathe the air full of hazes, no longer drink muddy polluted river water, no longer face the fine land eroded by wind and sand, no longer sigh for the disappearance of rain forest, human beings began to save the earth’s selfsalvation. Governments around the world have put forward the environmental protection and green economy on the agenda. It has been announced that, since 1973, individuals, communities, civil society, businesses, and governments around the world marked World Environment Day to be June 5 – by making commitments and calling for action to restore millions of hectares of ecosystems all around the world for the benefits of people and nature [1]. Microelectronic technology is playing an important role in energy saving and ecological civilization construction. Just take the lamp as an example: an ordinary 60 W incandescent lamp consumes 1 kWh power for 17 h, an ordinary 10 W energysaving lamp consumes 1 kWh power for 100 h, and a LED lamp of the same illumination consumes 1 kWh power for 1000 h. That means LED lamps consume only 1/60 of the energy of incandescent lamps. Figure 2.1 is a forecast result for the US electricity consumption based on the Semiconductor Technology and Applications Energy Efficiency Outlook Model

Fig. 2.1 Forecast results for the US electricity consumption based on the Semiconductor Technology Application Energy Efficiency Outlook Model [2]

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(by The American Council for an Energy-Efficient Economy, ACEEE). If the technical performance remains the same, the electricity consumption of economic development in the United States could increase to 6.502  1012 kWh by 2030. According to the US Energy Information Administration, the widespread use of semiconductor technology and devices could reduce the consumed electricity to 4.606  1012 kWh. If some policies are introduced to encourage the development and application of semiconductor technology, the electricity demand can be further reduced by 1.242  1012 kWh. In addition, microelectronics technology has excellent potential in the monitoring and control of air pollution, water pollution, and soil pollution and other aspects of improving the environment. Compared with traditional industries, microelectronics industry itself is also an industry with lower energy and water consumption. As can be seen from Fig. 2.2, the industry with the highest energy consumption is coking industry, with the energy consumption of 3.407 t standard coal per ¥10,000 RMB (or CNY) of output value. As a representative of microelectronics manufacturing industry, SMIC’s energy consumption per ¥10,000 RMB of output value is only 0.115 t of standard coal. As can be seen from Fig. 2.3, the water consumption of microelectronic manufacturing industry is relatively high, which is 4.413 m3per ¥10,000 RMB of output value. Due to the use of reclaim water, SMIC’s actual water consumption is 0.387 m3 per ¥10,000 RMB of output value (90% of SMIC’s water is recyclable reclaim water and the actual consumption of city water is 10%), which is only 3% of that of the cotton and chemical fiber textile printing and dyeing industry.

Fig. 2.2 Comparison of comprehensive energy consumption per 10,000 CNY output value in different industry sectors [3]

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Fig. 2.3 Comparison of water consumption per CNY10,000 output value in different industries [4]

ICs and Social Life and Culture Integrated circuits first came into people’s lives with the help of audio and visual equipment, including radios, tape recorders, video recorders, DVDs, and televisions. In 1976, Steve Wozniak and Steve Jobs developed the microcomputer Apple I. In 1981, IBM successfully introduced the Personal Computer (PC) using Intel’s 8088 microprocessor and Microsoft operating system MS-DOS to the market and named this new Computer as “Personal Computer,” initiating the PC era. In 1990, the global PC penetration rate was 0.53 units/100 people, and it began to become the main product driving the electronic product market. Soon after, laptop computers and tablet computers have started to hit the market. In 2006, the global PC penetration rate reached 15.4 units/100 people, and 67.5 units/100 people in developed countries (according to the World Bank data). The application of the PC and related software has dramatically improved the work efficiency. Its text and graphics editing and data processing functions have replaced manual writing, typesetting, ink printing, drawing, drawing tables, and other complicated and inefficient manual operation. In 1978, Bell Labs of the United States successfully developed the Advanced Mobile Phone System (AMPS) and built the cellular mobile communication network. In the 1980s, the mobile communication was analog signal communication, and Motorola 8900 [3] (commonly known as “big brick” and “Mobile phone”) was the first generation of analog communication mobile phone that entered China. In the 1990s, the digital mobile communication emerged. In1982, at the Conference of European Posts and Telecommunication Administrations (CEPT), a Group Special

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Mobile (GSM) under the Technical Committee of European Telecommunications Standards Institute (ETSI) was established. Its task was to develop a standard for pan-European mobile communication roaming, which was also the Global System for Mobile Communications (GSM; originally short for French Groupe Spécial Mobile, Special Mobile Group, now officially short for Global System for Mobile Communications). According to the Communications Business statistics bulletin data of the Ministry of Industry and Information Technology in 2015, the total number of mobile users in China reached 1.3 billion, the penetration rate of 94.5%, and almost everyone had a mobile phone. The birth of the Internet further changed people’s lifestyle. The Internet originated from ARPANET (Advanced Research Projects Agency Network, an experimental computer network). ARPANET was funded by the Advanced Research Projects Agency, or ARPA in the late 1960s, which was developed by the Defense Advanced Research Projects Agency (DARPA). The network was put into use in 1969. In 1974, Transmission Control Protocol (TCP) and Internet Protocol (IP) are available and together called the TCP/IP protocol. The disclosure of the core technology of TCP/IP finally led to the rapid development of the Internet. In 1991, CERN (Conseil Européen pour la Recherche Nucléaire), the predecessor of the European Laboratory for Quantum Physics, published the World Wide Web (WWW, developed in 1989 by Tim Berners-Lee); WWW offered an interface-friendly information service for retrieving and reading about servers connected to the Internet servers. In 1991, the Internet was officially launched. In 1992, there were about 720,000 computers connected to the Internet worldwide. After 1995, the PC market entered a mature stage and began to gradually enter urban civilian families. The number of networked computers increased to 6.64 million units. In 2004, the number of PCs in the world reached 580 million units, and the number of networked computers exceeded 100 million units. Integrated circuits have led to the spread of computers and smartphones, which have created a whole new network culture including various applications (or APPs), such as sending and receiving emails, browsing news, WeChat in 2011, Weibo in 2009, games, audio, video, health data sensing and recording, telemedicine, network broadcast, online shopping, payment, travel booking, education, making friends, catering, and other software. It covers almost everything people need for information. The network enables the dissemination of culture to break through the limitations of time and space and brings a profound revolution to the development of human culture. Of course, every new thing has two sides. The virtual nature of the network can also be used by people with ulterior motives to blackmail, cheat, steal information, spread viruses, and bring in people’s competitiveness and innovation under new threats. We need to continually clean up the dirt on the Internet and continually keep protecting the healthy growth of the Internet. German poet, critic, and literary historian, Wolfgang Menzel (1798–1873), first recorded in 1512 the German proverb saying, “Schüttet das Kind mit dem Bade aus,” which in English is “Throw the baby out with the bathwater.” What people can learn from this phrase is to make a right judgment, that is, to take advantage of the benefits of modern technology while cleaning up the dirt.

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The Value Goes to Where the Knowledge Is The development of IC technology has brought humanity into the information society. In 2016, the global semiconductor market was $338.931 billion USD, and the total market value of electronic system was $1457 billion USD (statistics data of IC Insights). In 2020, the global semiconductor market has grown to $425.96 billion, and the total market value of electronic system market compound annual growth rates (CAGRs) from 2017 to 2021 was between 3.3% and 6.4% by Statista [5]. As a major manufacturer of electronic information products in the world, China’s annual output in mobile phones, televisions, computers, and other products has long been ranked the top in the world. However, the output first does not mean the labor value first. International economic competition shows that without advanced microelectronic technology, it is impossible to have an advanced electronic product manufacturing industry, and the core products without mastering micro-electronic technology can only be at the low end of the industrial chain in the international division of labor and play the role of “workers” who are eaten and exploited by others in the distribution of benefits in the international market. Currently, although the export value of China’s electronic products is relatively high, but most of the values are earned by processing products with imported materials. At present, many Chinese machinery companies do not master the core technology of microelectronics, because of the dependence on imported integrated circuits and related technology, resulting in a very low product profit margin; its net interest rate is only about 1%. As an example, an iPhone that sells with a profit for $600 USD, Apple’s profit is $360 USD (60% of total profit), and Foxconn’s assembly revenue is only $6.54 USD (barely 1.1% of total profit). On a $40 USD mouse, Logitech makes 22.5% of its profits, while the assembly company makes only 7.5%. The rapid development of IC technology and the knowledge behind has resulted in tremendous market value. The profit distribution of the example in the above has demonstrated an economic cycle of value from technology and technology from knowledge. In the past a half century or so, the market has shown that “the value goes to where the knowledge is.”

References 1. World Environment Day 5 June, https://www.un.org/en/observances/environment-day. Accessed 15 May 2023 2. J. Laitner, C.P. Knight, V.L. McKinney, et al., Semiconductor Technologies: The Potential to Revolutionize US Energy Productivity: Report Number E094 (ACEEE, Washington, DC, 2009) 3. Shanghai Economic and Information Technology Commission, Shanghai Statistics Bureau Shanghai Industrial Energy Efficiency Guide 2011 Edition (11-26-2011), http://www. sheitcgovcn/cynxzn/65384htm. Accessed 02 Apr 2017 4. W. Yongwen, W. Yangyuan, Ten years of grinding a sword: Discussion on the history review and development law of integrated circuit industry. China Integr. Circuit 16(3), 9–14 (2007) 5. Statista, https://www.statista.com/statistics/783608/worldwide-electronic-system-cagr-by-cate gory/. Accessed 15 May 2023

3

The Development Law of the IC Industry Yong-Wen Wang and Min-Zheng Zheng

Contents Moore’s Law and Bell’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gene’s Law, Gilder’s Law, and Metcalfe’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development Pattern of IC Technology and Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The End of Moore’s Law and the Innovations of Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Economic Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32 34 35 40 41 41 42 44

Abstract

Moore’s Law has great significance in the development of integrated circuit industry. In general, we can say that the number of components in IC doubles every 18 to 24 months. As a complement to Moore’s Law, Bell’s Law predicted that by keeping a computer’s capabilities unchanged, the price and volume of the microprocessor would reduce by half in every 18 months. Gene’s Law indicated that the power consumption/performance ratio of DSP reduces by 2 orders of magnitude every 10 years. Metcalfe’s Law states: The value of the network is proportional to the square of the number of network users; that is, N connections can create benefits. Like Moore’s Law, both Gilder’s Law and Metcalfe’s Law are empirical, approximate descriptions and predictions to be validated. Along with the IC development path as forecasted by Moore’s Law, the line width of IC technology is gradually scaled down. In 2023, the IC manufacturing technology

Y.-W. Wang (*) Institute of Microelectronics, Peking University, Beijing, China e-mail: [email protected] M.-Z. Zheng Department of Information Technology Industry, Ministry of Industry and Information Technology, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_3

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is at 3 nm node and entering the scope of mesoscopic physics. There are three constraints for continuous scaling of technology: physical constraints, power consumption constraints, and economic constraints. Keywords

Moore’s Law · Bell’s Law · Gene’s Law · Metcalfe’s Law · 3 nm

Moore’s Law and Bell’s Law On April 19, 1965, Gordon E. Moore, then director of the Fairchild Semiconductor’s R&D Laboratory, was invited to write a review for the 35th anniversary issue of Electronics magazine, entitled “Cramming More Components onto Integrated Circuits.” Figure 3.1 shows the home page of the review. In the middle of the right side of the second page, the summary of the report further elaborated: “The complexity for minimum component costs has increased at a rate of roughly a factor of 2 per year. Certainly, over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per IC for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer.” This was the original “Moore’s Law.” In 1975, Moore published the article “Progress in Digital Integrated Electronics” at the IEEE International Electron Devices Meeting (IEDM). This paper revised the annual doubling by saying doubling every 2 years: “The new slope might approximate a doubling every two years, rather than every year, by the end of the decade.” Figure 3.2 shows the “Moore’s Law” published in 1965 and its revisions made in 1975.It is worth noting that Moore himself has never stated that “the integration degree of integrated circuits doubles in 18 months.” In an interview with Scientific American magazine in September 1997, he specifically stated that “I predicted we were going to change from doubling every year to doubling every two years, which is kind of where we are now. I never said 18 months.” The American Semiconductor Industry Association (SIA) cited the argument of doubling every 24 months in the 2001 edition of ITRS and extended it all the way to 2020. The increase in the number of components in microprocessors did follow the Moore’s forecast of doubling in 24 months, but the increase in the number of components in DRAM was slightly faster than that in microprocessors, to the extent of doubling in 18 months, as shown in Fig. 3.3. Therefore, we can generally say that the number of components in the integrated circuit doubles every 18 to 24 months. However, this is not a law, but a statistical result of IC manufacturing practice. It does really reflect the objective law of the development and change of things under certain conditions. In this sense, it is not unreasonable to translate “Moore’s Forecast” into “Moore’s Law,” but it is not a strict law in mathematics, physics, and other scientific disciplines.

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Fig. 3.1 The home page of Gordon Moore’s review published on Electronics in 1965

In 1972, Gordon Bell, working for Digital Equipment Corporation (DEC), made the following prediction about the development of microprocessor technology for the VAX (PDP): If the computer’s capabilities remain constant, the price and the size of the microprocessor would reduce by half in every 18 months. As a complement to Moore’s Law, Bell’s predictions became known as Bell’s Law.

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Fig. 3.2 “Moore’s Law” published in 1965 and its revisions made in 1975 (original article illustration)

Fig. 3.3 The growth of numbers of components in CPU, DRAM, and 3D-NAND

Gene’s Law, Gilder’s Law, and Metcalfe’s Law In 2006, TI’s chief scientist, Gene Frantz, told the reporter of Electronic Engineering Times (EE Times) at the TI Developer Conference: “Many DSP experts agree that millions of multiply-accumulate operations per second (MMAC/s) is simple and fair test indicator. I have carefully studied the power consumption for each MMAC/s of the DSP, that is, the power consumption per MMAC/s reduced to half every 18 months.” His words can also be expressed as “The power consumption/performance ratio of DSP decreases by two orders of magnitude every 10 years.” It means

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Fig. 3.4 Gene’s Law

that the power consumption/performance ratio of a DPS 10 years ago was 100 times that of today. This is the famous “Gene’s Law.” It is shown in Fig. 3.4 [1]. In 1996 George Gilder, an American economist, put forward a prediction in his book Telecosm that the bandwidth of the backbone network would double every 6 months over the next 25 years, and its growth rate would be four times faster than that of CPU predicted by Moore’s Law. This argument was known as Gilder’s Law. Mr. Gilder also asserted that the transmission price per bit would jump to free in an “asymptotic curve,” with a price point infinitely close to zero, and that free Internet access would be imminent. Metcalfe’s Law was developed by the 3Com founder and computer networking pioneer Robert M. Metcalfe and named in 1993 by George Gilder, publisher of the Gilder SciTech Monthly. The law states that the value of a network is proportional to the square of the number of users on the network, which means that N connections can create N2 benefits. That is, if a network is worth ¥1 RMB to each person in the network, then the total value of a network 10 times larger is equal to ¥100 RMB; a network 100 times the size has a total value of ¥10, 000 RMB. When a network grows 10 times in size, its value increases 100 times. In the era of network economy, the higher the degree of sharing, the larger the user group, the more its value can be reflected to the greatest extent. In short, the more people online, the more benefits they generate. However, this description is currently controversial or flawed in that it assigns the same “value” to all connections or groups. This led to the emergence of a network bubble at the end of the twentieth century, which only pursued growth rather than profit. Like Moore’s Law, Gilder’s law and Metcalfe’s law are empirical, untested predictions and rough descriptions, not laws in the sense of physics.

Development Pattern of IC Technology and Industry Throughout the development of microelectronics over the past 50 years, the progress of microelectronics technology, industry, and market has shown the following laws.

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Fig. 3.5 Sales of the global semiconductor market and Y/Y % change from 1996 to 2021

1. Driven by continuous advancements of technologies in microelectronics design, manufacturing, packaging, materials, and equipment, the scale of the microelectronics industry has expanded rapidly, and the sales volume of the semiconductor market have been on the rise [2], as shown in Fig. 3.5. 2. The semiconductor market performance is also characterized by regular fluctuations in growth rates, that is, an “M” shaped change appears approximately every 10 years, as shown in Fig. 3.6. The reasons for fluctuations in the growth rate of the semiconductor market are complicated, but the main reasons are market traction and technology driven by investment. The relationship between the growth rate of world GDP and the growth rate of semiconductor market is shown in Fig. 3.7. 3. The manufacturing technology of semiconductor products has reached a new level in about every 10 years, as illustrated in Table 3.1. 4. Typical microelectronic products take about 10 years from R&D to mass production as shown in Fig. 3.8, and Fig 3.9 shows a typical integrated circuit that takes about 10 years from R&D to mass production.

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Fig. 3.6 Changes in the growth rate of the global semiconductor market from 1975 to 2020

Fig. 3.7 Correlation between global semiconductor sales growth rate and global economic growth rate from 1986 to 2020

5. Engines that drive the information market have undergone a new change about every 10 years or so, as shown in Fig. 3.10. 6. The price of transistors in integrated circuits is declining by two orders of magnitude every 10 years (prices were 100 times higher 10 years ago), as shown in Fig. 3.11. While DRAM/DDR market maintained up and down, price of 1 Gb dropped to < $1, the Flash memory market [3] started to rise (2013–2020).

2 ~ 4in

Manual

From TO to DIP

Design tools

Main package form

From logic editing to P&R DIP

4 in ~ 150 mm

150 mm, 200 mm From synthesis to P&R From DIP to QFP

101 ~ 102

105 ~ 106

From 386 to 486 16,32

1 ~ 0.35 μm 1 ~ 64 MB

365 nm

Gen 3 1985–1995 I-Line

From synthesis to DFM DIP, QFP, BGA

200 mm, 300 mm

102 ~ 103

Various packaging SiP

SoC, IP

200 mm, 300 mm

108 ~ 109 Multi-core architecture Non-standard frequency

64

32,64 106 ~ 107

Core

193 nm (DPT Immersion Lithography & DPT) 65 ~ 22 nm 1 ~ 16 GB (Chipset)

Gen 5 2005–2015 ArF

Pentium

0.35 μm ~ 65 nm 64 MB ~ 1 GB

248 nm

Gen 4 1995–2005 KrF

SiP, 3D

Multi-core architecture Non-standard frequency 200 mm, 300 mm, 450 mm SoC, IP, SiP

22 ~ 7 nm 16 GB-1 TB or above 1 TB (Chipset)

13.5 nm

Gen 6 2015–2025 EUV, EPL

The increase of CPU clock frequency will lead to a sharp increase in power consumption, and the main frequency increase is no longer the main factor of design pursuit. Under the condition of keeping the dominant frequency unchanged, it has become the mainstream of CPU design by simplifying pipeline structure, reducing design complexity, improving unit performance and processor energy efficiency, and adopting multi-core architecture.

a

104 ~ 105

103 100 ~ 101

From 8086 to 286 8,16

From 4004 to 8080 4,8

CPU Products (Intel as an example) CPU word length / bit Transistor number of CPUa CPU clock frequencya/MHz Wafer diameter

~ 100

3 ~ 1 μm 16 KM ~ 1 MB

12 ~ 3 μm 1 KB ~ 16 KB

Feature size Memory

1

436 nm

Multi-wavelength

10

Gen 2 1975–1985 G-Line

Gen 1 1965–1975 Mercury lamp

Stage Period Main litho light source Typical wavelength

Table 3.1 Manufacturing technology of semiconductor products advanced one generation for about every 10 years

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Fig. 3.8 Typical microelectronic products take about 10 years from R&D to mass production

Fig. 3.9 Typical cases of IC, from R&D to mass production needs about 10 years

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Fig. 3.10 The change of engines that drive the information market

Fig. 3.11 The declining pattern of transistor price in integrated circuits. (a) Unit price of DRAM transistor kept dropping (1968–2013); down: (b) the Flash memory market [2] started to rise (2013–2020)

The End of Moore’s Law and the Innovations of Software Along the development path of integrated circuits predicted by Moore’s Law, the line width of ICs is gradually scaled down, and the minimum line width has reached 3 nm in 2021, which has entered the category of mesoscopic physics. From the point view

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of technology, continuing to narrow the channel line width simply will be constrained by three factors.

Physical Constraints Mesoscopic scale materials, on the one hand, contain a certain number of particles, which cannot be solved by the Schrödinger equation alone. On the other hand, the number of particles is not large enough to neglect the statistical fluctuations. This situation poses many physical obstacles to the further development of IC technology, such as Fermi-Pinning, Coulomb Blockade, Quantum Tunneling, Impurity Fluctuation, and Spin Transport. They need to be solved by mesoscopic physics and quantum-based processing methods.

Power Consumption Constraints Figure 3.12 shows a contradicted trend between improving device performance (the clock frequency as a representing parameter) and reducing power consumption. With the advanced technology nodes, the clock frequency of each generation of devices increases by 20%, but the power density of device also increases greatly. If the power density is kept at 40 W/cm2, the maximum clock frequency cannot be increased, and even the clock frequency decreases after the adoption of 14 nm technology nodes.

Fig. 3.12 The contradiction trend between increasing the clock frequency and reducing power consumption [4]

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Economic Constraints Figure 3.13 shows the variation trend of gate cost with technology nodes, where the cost per 100 M gates ($/100 MGates) of the 90 nm technology node is $4.01. After that, the cost of 65 nm, 40 nm to 28 nm shows a downward trend. Among them, the 28 nm is one of the last planar technology nodes. However, after entering the 20 nm technology node with 3D FinFET structures, the cost per 100 Mgates will no longer decline according to the Moore’s Law, but instead, it will rise. This is driven by the increased complexity of fabricating these chips with advanced device structures. That is to say, in the future, in the three aspects of higher speed, lower power consumption, and lower cost, if the cost is taken as the main indicator, performance and power consumption will hardly be significantly improved. On the contrary, chip manufacturers and users who focus on performance and power consumption will have to pay the corresponding price instead of enjoying the “benefits” of cost reduction brought by the Moore’s Law. However, if new materials and new device structures are adopted, whether the integrating degree of IC continues to grow along Moore’s Law remains to be tested by future practice. Integrated circuits depend more on ecosystem and need hardware and software co-development. For example, CPU competition is not only about CPU chips themselves, but also about its software ecosystems. For instance, Intel’s CPU and Microsoft’s operating system have built a stable Wintel industry development environment. ARM and Google have also built ARM-Android system in the field of mobile terminals. The information industry was initially driven by hardware (IC) technology. With the progress of IC processing technology, the integration degree of single chips is getting higher, the speed of IC is getting faster, and the memory storage capacity is getting larger. Thus, the software loaded on the IC can be more abundant, the functions of software become more powerful, and more kinds of application software are available. Figure 3.14 shows the positive correlation between the memory Fig. 3.13 The variation trend of gate cost with technology nodes [5]

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Fig. 3.14 CPU dominant frequency, DRAM storage capacity, and the memory space occupied by the operating system

Fig. 3.15 Trends of the software-driven information industry

space occupied by the Windows operating system, the Intel CPU dominant frequency, and the storage capacity of typical DRAM during the same period. At present, the capacity and speed of integrated circuits have been able to meet the needs of almost any software. In this case, the trend of the information industry driven by software began to emerge, that is, according to different operating systems to develop the hardware suitable for the software. Mobile communications are a prime example. Currently, Android and iOS are the mainstream operating systems in the market. Recently, on August 4, 2023, Huawei officially released HarmonyOS 4, which is the third largest smartphone platform after iOS and Android. At present, the number of devices using HarmonyOS ecology has exceeded 700 million.

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HarmonyOS is a distributed operating system developed by Huawei, officially known as Huawei Terminal HarmonyOS Intelligent Device Operating System software. HarmonyOS system uses the “decentralized” technology to combine multiple devices such as mobile phones, computers, tablets, TVS, cars, and smart wearables into a hyperterminal that allows users to easily operate and share the resources of various devices. Therefore, all hardware solutions should be developed according to these three operating systems. All different mobile phones could be manufactured by using different embedded CPUs, receiving and transmitting chips, and human-machine interface chips that come from different manufacturers, if they would work in the systems mentioned above. This is a software-defined system, which determines the design and production of integrated circuits, as shown in Fig. 3.15. Gene Frantz, TI’s chief scientist, considers that: “The bulk of the innovation will be in the software on top of the hardware. Hardware will become part of the platform on which innovative designers will develop their ideas” [6]. Therefore, following the trend of information industry development driven by software as an essential part of the strategic layout, the corresponding software discipline research should be coordinated deployment in line with market demand.

References 1. G.A. Frantz, Power: The Final Frontier for Technology Breakthroughs. Unpublished lecture PPT in school of electronics and information engineering, Soochow University, 11-Sep-2009: 1–13 2. WSTS, https://www.semiconductors.org/global-semiconductor-sales-units-shipped-reach-alltime-highs-in-2021-as-industry-ramps-up-production-amid-shortage/. Accessed 23 May 2023 3. Statistics, Flash Memory Market 2013–2021, https://www.statista.com/statistics/553556/ worldwide-flash-memory-market-size/. Accessed 23 May 2023 4. L. Chang, D.J. Frank, Technology Optimization for High Energy – Efficiency Computation, Short Course on Emerging Technologies for Post 14nm CMOS, IEDM (2012) 5. 10nm node offers lower gate costs, https://archive.eetasia.com/www.eetasia.com/ART_ 8800713357_1034362_NT_9ca5570a.HTM. Accessed 23 May 2023 6. Texas Instruments Microcontrollers (MCUs) & processors: https://www.ti.com/microcontrollersmcus-processors/overview.html. Accessed 23 May 2023

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Development of World IC Industry Da-Kang Mo and Ke Li

Contents Global GDP and GDP per Capita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Supply Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wafer Foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evolution of IC Industrial Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revenue Change of the Top 10 World’s Semiconductor Companies (1985–2021) . . . . . . . . . . . . Revenue, Distribution, and Product Category of Global Semiconductor Market (1997–2021) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . World Semiconductor Council (WSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Equipment and Materials International . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Semiconductor Alliance (GSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . International Technology Roadmap for Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Worldwide Major Institutions of IC Research and Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interuniversity Microelectronics Center (IMEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Very Large-Scale Integration (VLSI) Consortium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Manufacturing Technology Research Consortium (SEMATECH) . . . . . . . . . Semiconductor Leading Edge Technologies, Inc. (SELETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Market Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Days Sales of Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Annual Growth Rate of the Semiconductor Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Book-to-Bill Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . World Semiconductor Trade Statistics (WSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Worldwide Major IC Market Research and Consulting Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Insights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gartner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TrendForce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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D.-K. Mo (*) Truth Semi Group, Shanghai, China K. Li Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_4

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Perspectives of IC Science and Technology in Post-Moore Era . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Abstract

The major IC enterprises facing to the market directly are fabless design enterprises (no production line), integrated device manufacturers (IDM), and intellectual property (IP) providers. EDA enterprises primarily provide design methodologies and tool suites but not for providing chip fabrication services, while wafer foundry (or Fab) can provide IC fabrication services. In the IC industry chain, IPs are commonly provided as process-proven and can be embedded in chips or known good dies (KGD); packaging and testing companies mainly provide services for Fabs, and IDM companies, materials companies, and special equipment companies mainly provide the required materials and equipment, respectively, for chip manufacturers. The industry is subject to the influences by several semiconductor organizations, such as World Semiconductor Council (WSC), Semiconductor Equipment and Materials International (SEMI), and Global Semiconductor Association (GSA). Additionally, there are also several IC market research and consulting companies, World Semiconductor Trade Statistics (WSTS), IC Insights, Gartner, Trend Force, and Yole, whose roles as if are IC liaisons in between IC designs and research, chip manufacturing, and product marketing. Keywords

Fabless · Integrated device manufacturers (IDM) · Intellectual property (IP) · Foundry · SEMI · GSA

Global GDP and GDP per Capita Gross domestic product (GDP) means the market value of all final products and services produced by all resident units over a certain period in a country (within national boundaries). GDP is the core index of national economic accounting. It is also an important indicator to measure the overall economic situation of a country or a region. The variation in the total amount of the world GDP from the first year of AD (Anno Domini 1, AD 1) to the year of 1973 is shown in Fig. 4.1. It is obvious that the GDP growth of agricultural society is extremely slow before AD 1820. The total world GDP was Int$102.36 billion dollars (1990 international dollars) in AD 1 and Int$694.442 billion dollars in 1820, respectively. The total GDP increased 6.8 times over about 2000 years period. After 1820, the first industrial revolution and the second industrial revolution greatly raised the growth speed of the world GDP. The GDP increased from Int$694.442 billion dollars in 1820 to Int$16,059.180 billion dollars 1973. The total amount of world GDP increased 22 times over 153 years.

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Fig. 4.1 The total amount variation of world GDP from the first year AD to 1973. 1990 International dollar (Int$, also known as the Geary-Khamis dollar, G-K$). It is a method to convert different national currencies into a uniform currency or an international dollar based on the parity comparisons in multilateral purchasing power. Originally created by Irish economic statisticians R. G. Geary, then developed by S.H. Khamis. (Data source: Millennium History of the World Economy, By Angus Madison, translated by Xiao-ying Wu)

Fig. 4.2 The variation in the total amount of world GDP from 1960 to 2021. (Data source: Millennium History of the World Economy, By Angus Madison, translated by Xiao-ying Wu; World Bank)

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The variation of the total world GDP from 1960 to 2021 is shown in Fig. 4.2. It indicated that the world GDP grew steadily from 1960 to 1980. Thereafter, there was a world economic stagflation due to the depression in the United States and the slow economic growth in Europe during 1980 to 1985. Thus, the United States grew by
0.2% in 1981 and
1.9% in 1982. In the European Union, meanwhile, the corresponding growth rates of the Europe Union were 0.3% and 1.0%, respectively. The growth rate of world GDP boosted rapidly from 1986 to 1996. As shown in Fig. 4.2, the slope of GDP growth is significantly higher than that of the previous period from1960 to 1980. During this period, the average annual growth rate of world GDP was 2.9% and the total GDP doubled. Besides, Asia-Pacific region grew at an average annual growth rate of 4.9% and its GDP grew 2.6 times. Moreover, with an average annual growth rate of 10.1% and an aggregate GDP growth rate of 2.9 times, China has made an important contribution to the world GDP growth. Total world GDP changed slightly between 1997 and 2001 as a result of the Asia financial crisis. Since 2001, the information industry gradually surpassed the traditional industry and then became the world’s largest industry. This newly growing industry has made a great contribution in GDP to the world economy. Therefore, the slope of total world GDP growth in 2001 to 2021 was much higher than that in 1986 to 1996. Of which, in 2009, due to the global finance crisis trigged by the subprime mortgage crisis in the United States, total world GDP amount declined again. In addition, COVID-19 pandemic has also resulted in a serious decline of total world GDP (84.75T USD) in 2020. The COVID-19 pandemic led to the negative GDP growth in most of countries in 2020. Therefore, 2021 GDP growth is measured from a lower starting point of 84.75T USD (2020) to 94.935T USD (2021). This can make the GDP growth rate appear higher. To recover from the pandemic shutdown, almost all mature economies, emerging markets, and developing economies experienced positive GDP growth in 2021. As shown in Fig. 4.3, in 2021, the world GDP growth rate is 5.9%, 8.9% in India, 8.1% in China, 6.6% in emerging markets and developing economies, 5.9% in USA, 5.5% in Euro area, and 5.1% in all mature economies. In addition, the GDP growth rate of ASEAN-10 and Japan is 3% and 1.7%, respectively. The variations of GDP proportion for various regions, including China, the United States, Japan, etc., to the global total is shown in Fig. 4.4. In the agricultural era, as a major agricultural country in the world, China’s GDP accounted for more than 22% of the world’s GDP, and even reached to 32.9% in 1820 (the last year of Jiaqing era of Qing dynasty). After the Opium War in 1840, the national strength of Qing dynasty was declining day by day. It was only in 1913 that China’s share of world GDP had fallen to 8.9%. At that time, American GPD share was 19.1% which was more than twice of China’s share. In 1961, China’s GDP accounted for 3.49% of the total world GDP, while Japan overtook China and accounting for 3.77% of the world’s total. In 2009, China’s GDP accounted for 8.46% of the world’s total, surpassing Japan’s GDP. The variation in the GDP per capita of China, the United States, and the world from A.D. 1 to 1820 is shown in Fig. 4.5. In the period of A.D. 1 to 1700, China [just mentioned this in previous para.] and the GDP per capita was equal to or slightly

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Fig. 4.3 The GDP growth rate for regions of world in 2021

Fig. 4.4 The proportional variations of China, America, and Japan to total world GDP from the first year AD to 2019. (Data source: Millennium History of the World Economy, By Angus Madison, translated by Xiao-ying Wu; World Bank)

higher than the world GDP per capita. However, after 1700, China’s GDP had failed to keep pace with the industrial revolution; therefore, GDP per capita of China began to gradually fall below the world average. Meanwhile, Europe and the United States relied on the power of industrial revolution to achieve a rapid growth in GDP per capita.

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Fig. 4.5 The variation in GDP per capita of China, America, and world from the first year AD to 1820. (Data source: Millennium History of the World Economy, By Angus Madison, translated by Xiao-ying Wu)

Fig. 4.6 The variation in GDP per capita of China, the United States, and the world from 1960 to 2019. (Data source: World Bank)

Additionally, the variation in the GDP per capita of China, the United States, and the world from 1960 to 2019 is also presented in Fig. 4.6. China’s GDP per capita maintained a slow growth from 1960 to the end of the twentieth century. However, the total amount of GDP rapidly increased since the beginning of the twenty-first century, and the GDP per capita also started to increase annually, reaching

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$10,261.68 USD in 2019. In any case, it was still slightly below the world GDP per capita of $11,441.73 USD, compared with $65,297.52 USD in the United States.

IC Supply Chain The composition of the semiconductor industrial chain (including ICs and discrete devices) is presented in Fig. 4.7. The main enterprises facing the market directly are fabless design enterprises (no production line), integrated device manufacturers (IDM), and intellectual property (IP) circuit module vendors. Additionally, EDA enterprises, which primarily provide design methodologies and tool suites, can not to provide chip fabrication services. Thus, they are usually entrusted to contracts only. The wafer foundry (or Foundry, Fab) provides IC fabrication services. IPs are commonly provided as process-proven and can be embedded in a chip or welldesigned modules. Furthermore, IP modules are classified into three types: soft core, firm core, and hard core. IP providers include chip design companies, foundry Fabs, EDA enterprises (e.g., Synopsys), professional IP companies (e.g., ARM), and design services companies. Furthermore, packaging and testing companies do not have their own products and mainly provide services for foundry Fabs and IDM companies. Materials companies and specialty equipment companies mainly provide the required materials and equipment to chip manufacturers, respectively. The much broader concept of the industrial chain should also include Industry Associations, Intermediary Service Agencies, Venture Capitals, Market Research Institutions, Talent Training Centers, etc. The development of IC technology originates from the progress of each link in the IC industry chain. The value created by each industrial link constitutes the overall contribution of the IC industry to society. As the base for talent training and basic research, fundamental and theoretical

Fig. 4.7 The composition of semiconductor industry chain

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research conducted by universities and research institutes is also an important link in the construction of the IC Industry chain. The ideas of technological innovation often create a revolutionary impact on the progresses of technology, such as the invention of Fin Field-Effect Transistor (FinFET). The main products manufactured with semiconductor technology are integrated circuits (accounting for about 82–87% of the total semiconductor market) and semiconductor discrete devices. Furthermore, the main IC products include application specific standard products (ASSPs), microprocessor units (MCUs), memory devices, applications-specific ICs (ASIC), analog circuits, and general logic circuits, while the main products of semiconductor discrete devices include diodes, triode tubes, power devices, high voltage devices, and microwave devices. These discrete devices, optoelectronics, and sensors are listed as DOS product sector.

Wafer Foundry The original meaning of foundry is a casting plant or a casting factory. TSMC (Taiwan Semiconductor Manufacturing Co.) pioneered the new business model of entrusting contracts to fabricate integrated circuits for customers in 1987. At this time, the industry used the term “foundry” to represent the IC foundry fabs. In the 1980s, a new business model emerged in the IC industry. That is, from the traditional IDM model of the past to the evolution of today, IC design, IC manufacture, and IC packaging and testing relatively are independent models. Foundries only provided the service of IC manufacturing, not their own IC design and product development. Later, the foundry business model took two different forms. One was the pure foundry factory, and the other one was the IDM, which provided some surplus capacity as foundry service. In general, the main clients of foundry fabs were IC design companies. China Taiwan was the birthplace to initiate the semiconductor foundry industry, and TSMC was the most important foundry enterprise in the world. However, due to two issues, the foundry model had not been favored by other manufacturers in the world for a long period of time. The first issue was that the previous technology level of foundry was at least 1–2 generations behind IDMs; thus the foundry could only supply a capacity deficiency for IDMs when their capacity was in short. The second issue was that the IDMs of global semiconductor industries could only provide IC products for computers, while fabless enterprises had not yet developed substantially. One milestone after another for the global foundry industry started in the beginning of the twenty-first century. On the one hand, the applications of the Internet have promoted a faster updating cycle for terminal electronic products. On the other hand, due to the rapid improvement of technology and the substantial increase of plant construction costs, objectively, there is an urgent demand of foundry services to reduce the development cost of IC products in the semiconductor industry. At the same time, the technological capability of foundry enterprises such as TSMC, etc., has also been greatly improved to meet the requirement of advanced process

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technology. As of 2022, TSMC has provided the foundry services for 5 nm, 4 nm, and 3nm technology nodes. This technical achievement has surpassed the IDM giant Intel currently. In addition, the gradually matured industry of intellectual property (IP) companies has joined the development of foundry services. All these factors have led to the rapid growth of global semiconductor foundry industry. Presently, the smartphone and computer markets are gradually becoming saturated. Additionally, the products of the new application market driving the rapid growth of semiconductor industry have not yet appeared. The whole IC industry needs more R&D for the development of advanced technology up to 3 nm and below. Therefore, the growth of the global semiconductor industry may start to slow down. Under this new situation, how to deal with this negative trend and maintain a relatively higher growth rate than that of the whole industry has become a common issue for both fabless enterprises and foundry enterprises. The revenue of major global foundry enterprises in 2019 is shown in Table 4.1. The capacity of global wafer foundry enterprises in 2016–2021 is shown in Table 4.2. According to Trend Force, TSMC took 53.6% of the foundry market share in the first quarter of year 2022. Samsung, ranked second, was the only company to see its market share decline. In addition, the total foundry market share of mainland chip companies, including SMIC, Huahong, and Hefei Wafer Integration, exceeded 10% for the first time.

Evolution of IC Industrial Structure From 1960 to 1967, all manufacturers producing and applying ICs were electronic system manufacturers (e.g., TI, Fairchild, HP, etc.). At that time, the fabrication of ICs had not really formed a separate industry yet. System manufacturers not only produced ICs for their own internal supporting devices, but also provided some products to the IC market and procured some products from the IC market. Intel and AMD were founded one after another in 1968 and 1969, respectively. They created a new era in the global IC industry. Instead of electronic system companies, they acted as pioneers to supply general-purpose IC products only (neither manufacturing systems nor procuring IC products from the market). The kind of IC manufacturers that design, process, package, and test with their own production lines and then sell final chips by themselves are called Integrated Device Manufacturers (IDM). By 1990, the sales amount of IDM accounted for about 80% of the world IC market. As the integration of ICs was still in the period of small-scale integration (SSI) and medium-scale integration (MSI), the technical content of IC packaging was lower than that of process and design, and the investment of packaging equipment was also lower than that of process equipment. From the viewpoint of efficiency and benefit, some systems manufacturers of IC began to outsource the packaging, testing and other post-processing work, etc., or transfer factories that were engaged in IC packaging and testing to developing countries. In 1961, Fairchild Semiconductor

2019 list 2018 list Company 1 1 TSMC 2 4 Samsung 3 2 GF 4 3 UMC 5 5 SMIC 6 8 Tower Jazz 7 7 Shanghai Huahong 8 9 VIS 9 6 PSC 10 10 DongBu The sum of the top 10 Top 10 total market share Sum of other wafer factories Total wafer factory sum

Fab types Pure foundry IDM Pure foundry Pure foundry Pure foundry Pure foundry Pure foundry Pure foundry Pure foundry Pure foundry

Table 4.1 2019 world sales of main wafer foundries Head quarter China Taiwan Korea USA China Taiwan China Israel China China Taiwan China Taiwan Korea

2018 sales (million USD) 34,196 4634 6176 5009 3360 1304 1610 961 1659 607 59,520 92.7% 4922 64,216 2018 growth rate 6.5% 4.6% 0.0% 1.3% 8.4%
6.0% 13.5% 17.8% 8.9% 1.0% 5.3% – 4.9% 4.5%

2019 sales (million USD) 33,983 12,380 5639 4758 3116 1242 933 893 907 579 64,430 92.6% 5143 69,573

2019 growth rate
1.2%
0.7%
9.1%
6.2%
7.2%
4.8% 0.2%
6.7%
28.6%
3.3%
3.2% – 4.5% 8.3%

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2019 list Company 1 TSMC 2 UMC 3 GF 4 SMIC Main foundries wafer total 2021 rank 1 2 3 4 5

2017/million wafers 23.51 6.13 6.84 4.31 40.78

Company Samsung TSMC Micron SK Hynix Kioxia/WD TOTAL

2016/million wafers 21.61 5.44 6.17 3.96 37.18

2020 rank 1 2 3 4 5

2020 capacity 3.364 2.647 1.931 1.881 1.283 11.104

2017 growth rate 8.78% 12.59% 10.79% 8.89% 9.69% 2020 share % 17% 13% 10% 10% 7% 56%

2018/million wafers 24.19 6.15 7.11 4.88 42.33

Table 4.2 World foundries capacity from 2016 to 2019 (200 mm wafer equivalent)

2021 capacity 4.050 2.803 2.054 1.982 1.328 12.217

2018 growth rate 2.90% 0.41% 3.96% 13.11% 3.78%

2019/million wafers 22.88 5.92 7.16 5.04 41.00

2021 share % 19% 13% 10% 9% 6% 57%

2019 growth rate
5.42%
3.74% 0.73% 3.28%
3.14%

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invested and set up an IC packaging plant in Hong Kong, China. By 1978, 80% of ICs manufactured in the United States had been shipped overseas for packaging [1]. Due to the progress and popularization of computer technology, the design of ICs had entered the computer-aided design (CAD) stage from the original manual design style. The emergence of CAD tools greatly improved the efficiency and successful rate in IC design, and also provided the initial capability to quickly match the market demands. In the 1970s, a group of EDA tool manufacturers represented by CV (Computer Vision), Applicant, ECAD, Daisy, and Valid emerged one after another. Mentor and Cadence were founded in 1981 and 1983, respectively. CAD tools or companies providing IC design solutions came to be known as EDA tools or companies. Intel introduced the 386 micro-processor in 1983, and its senior managers found that the total investment cost of 386 chips was $100 million USD, while that of 286 chips was $50 million USD. In other words, “the value added by IC design has exceeded the value created by IC manufacturing.” Therefore, when others realized this, the separation of IC design from IDM became a natural necessity. Since 1983, many new enterprises like Altera, Syntek, Cirrus Logic, Xilinx, Qualcomm, and ATI have been born. These IC design companies had no IC manufacturing lines and were known as fabless in the IC industry. Additionally, IP vendors that did not manufacture any IC products are known as chipless companies. ARM (Advanced RISC Machines) was founded in 1990 as the first IP provider. ARM6, the first embeddable RISC core, was introduced in 1991. In January of 1987, TSMC was established. This company has created a new IC production model focusing on IC manufacturing services only. Because the company did not have its own products, it only provides wafer foundry services, so it is also called “foundry.” According to the statistics data from IC Insights, in 2020 the total sales amount of the top 10 IDM enterprises was $257.4 billion USD. These IDM enterprises still dominated the IC market. The total sales amount of fabless enterprises and foundry enterprises is $127.9 billion USD and $82 billion USD, respectively. The evolutional stages of global IC industry are shown in Fig. 4.8. In terms of company headquarters location, Fig. 4.9 shows the total global share of IC market, as well as the market share of IC sales of IDMs and fabless companies. Pure foundry players are not included in this data. By 2021, the global market shares of IDMs, fabless companies, and total IC sales volume are still led by US-based companies. Since 1990 the market share of both Japanese companies and European companies has gradually declined to only 6%. At present, Chinese companies (excluding foundry fabs) hold only 4% of global IC market share by 2021. Additionally, in 2022, the Semiconductor Industry Association of the United States (SIA) also predicted that the market share of mainland companies (including IC design enterprises, IDMs, foundries, and testing and packaging plants) in the global semiconductor market will grow from 9% in 2020 to 17% in 2024, while the market share of South Korean companies will remain around 20% in the next 3 years. From the perspective of IC demand, China is planning to boost its own semiconductor production which is aiming to be more selfreliant, and increase the global market share of Chinese companies by 2035.

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Fig. 4.8 Evolution of world IC industry

Revenue Change of the Top 10 World’s Semiconductor Companies (1985–2021) The progress of the global semiconductor industry mainly relies on two wheels. First, it relies on the progress of the shrinkage of technology process node. With the development of advanced technologies, the critical dimension (CD) of IC scales down by a factor of 0.7 every 1.5–2 years. The shrinkage ratio has been maintained all the way up to 14 nm in 2015, 10 nm in 2017, 7 nm in 2019, 5 nm in 2020, and 3 nm technology in 2022. Based on experience, the 2 nm and below technologies are also possible in the near future. Secondly, it relies on pushing the progress to increase the wafer size. From 400 (inch) wafer in the 1980s, 150 mm wafer in the early 1990s, 200 mm wafer in the late 1990s, and 300 mm wafer in 2002, it is clear that 300 mm wafer size still play a major role in today’s IC product lines. At present, the technology of 450 mm wafer is feasible. However, the R&D and mass production of 450 mm silicon wafer technology are at a standstill because of the economic

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Fig. 4.9 Worldwide IC company market share by headquarters location in 2021

reasons. It is apparent that the continuous scaling down of technology nodes is the primary factor to accelerate the growth of IC industry. The market of terminal electronic products is the main driving force to promote the industrial progress. As shown in Fig. 4.10, it was figuratively likened to an inverted triangle before, in which the global electronic product market is at the bottom side, which then determines the size of the global semiconductor industry, the corresponding semiconductor equipment, and semiconductor materials market. Driven by technology and applications of terminal electronic products, the growth performance of the global semiconductor industry is variable, with the ranking of the top 10 constantly changing. In the 1980s, Japan’s semiconductor companies such as NEC, Hitachi, Toshiba, and Fujitsu occupied 50% global market share, and the success of Japan’s memory IC products was more obvious. However, in early years of the twenty-first century, South Korea’s Samsung and Hynix also relied on the mass production of memory ICs, and then surpassed Japanese companies. Since 1992 to 2016, Intel also successfully managed to reach No. 1 with its CPU. The market share is the main factor to determine the change of global ranking for top 10 semiconductor enterprises. Intel has held the top global ranking for 25 consecutive years (as of 2016), but Samsung and others are catching up. The ranking order variation of the top 10 global semiconductor manufacturers from 1985 to 2021 is listed in Table 4.3. In 1990, there were six Japanese companies ranked within top 10, indicating that Japan’s enterprises reached the top at that time. Intel took the top spot in 1992 and kept ranked No.1 until the end 2016. Samsung Electronics followed

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Fig. 4.10 The upstream and downstream relationship of electronic industry. (Note: 80% of the main investment in semiconductor industry is for equipment procurement, that is, the market scale for semiconductor equipment. (Data source: IC insights))

Intel to be ranked No.2 in 2005 and maintained its position until 2016, and then topped the list from 2017 to 2018. However, Intel ranked as No.1 semiconductor enterprise again in 2019 and 2020. By 2021, Samsung regains the top spot. In addition, TSMC, led by Dr. Morris Chang, entered the top 10 list for the first time in 2010 and still maintained a good momentum of development in the third place for many years. Despite this, only one Japanese enterprise, Kioxia (new name of Toshiba Memory Co.), made it into the top 10 in 2019. Nvidia of the United States

1985 NEC TI Motorola Hitachi Toshiba Fujitsu Philips Intel National Panasonic

1990 NEC Toshiba Hitachi Intel Motorola Fujitsu Mitsubishi TI Philips Panasonic

1995 Intel NEC Toshiba Hitachi Motorola Samsung TI IBM Mitsubishi HY

2000 Intel Toshiba NEC Samsung TI Motorola ST Hitachi Infineon Philips

Data source: IC Insights Note: Due to the limited space, this table only shows the rank of every 5 year

Ranking 1 2 3 4 5 6 7 8 9 10

2005 Intel Samsung TI Toshiba STMicro Renesas Hynix Freescale NXP NEC

2010 Intel Samsung TSMC TI Toshiba Renesas Hynix ST Micron Qualcomm

Table 4.3 The ranking order variation of the top 10 global semiconductor manufacturers in the last 35 years 2015 Intel Samsung TSMC SK Hynix Qualcomm Micron TI Toshiba Broadcom Avago

2021 Samsung Intel TSMC SK Hynix Micron Qualcomm Nvidia Broadcom MediaTek TI

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and MediaTek of China Taiwan are also ranked in top 10 semiconductor companies in 2021.

Revenue, Distribution, and Product Category of Global Semiconductor Market (1997–2021) According to the WSTS statistics, the global semiconductor market sizes shown in Fig. 4.11 are $137.0 billion USD in 1997, $204.4 billion USD in 2000, $227.5 billion USD in 2005, $298.3 billion USD in 2010, $335.2 billion USD in 2015, $468.7 billion USD in 2018, $412.1 billion USD in 2019, and 555.89 billion USD in 2021. The corresponding year-on-year growth rate in 2021 is about 26.2%. Over the past 30 years, the average annual compound growth rate has reached 8.9%. Changes and advances in various end electronic products have effectively promoted the continuous progress of semiconductor industry, such as mainframe computers in 1970s, personal computers in the 1980s, notebook computers in the 1990s, smartphones and tablets at the beginning of the twenty-first century, etc. Up to now, wearable devices, smart home products, automobile electronics, etc., are emerging. The market share of the global semiconductor market by region from 1986 to 2019 is shown in Fig. 4.12. The chart shows the market share in the Americas, Europe, Japan, and Asia-Pacific region (excluding Japan), respectively. In 1986, Japan accounted for 39.7% of the global semiconductor market, making it the largest regional market. The Americas and Europe account for 32.3% and 20.3% of the global market, respectively, while Asia-Pacific (excluding Japan) accounts for only

Fig. 4.11 Global semiconductor market (1997–2021). (Data source: WSTS)

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Fig. 4.12 Global semiconductor market share by regions (1991–2019). (Data source: WSTS)

7.8% of the global market. However, Japan’s market share in 1986–2000 shows a significant downward trend. In 2000, Japan’s share of the global market fell to 22.9% with a reduced amount of 16.8% comparing to that in 1986. At the same time, the market share in the Americas and Europe is relatively stable. In 2000, the Americas and Europe accounted for 31.3% and 20.7% of the global market, respectively, virtually unchanged from 1986. In addition, Asia-Pacific regional market (except Japan) has maintained a rapid development to get 25.1% global market share in 2000 and became the world’s second largest regional market only after the Americas. Since the beginning of the twenty-first century, the Asia-Pacific market (excluding Japan) has continuously maintained rapid growth, while the market share of the Americas, Europe, and Japan has shown a declining trend. As of 2019, the AsiaPacific market (excluding Japan) has already accounted for 63% of the global market, while the Americas market accounted for 19% of the global market. However, Europe and Japanese markets both fell below 10% of the global market share. In 2021, US President Joe Biden declares to increase the US market share in the semiconductor field and regain the global leadership in the semiconductor industry. The European Union also announces that it will increase the European market share to 20% in the semiconductor industry. By 2030, a new round of global semiconductor industry landscape will gradually change. The product structure of the global semiconductor market from 2006 to 2019 is shown in Fig. 4.13. In 2006, the market size of discrete semiconductor devices was about $16.61billion USD, accounting for about 8% of the semiconductor market. By 2019, the market size of discrete semiconductor devices grew to $23.88 billion USD, and its share in the semiconductor market dropped to 5.7%. In 2006, the market size of optoelectronic devices was about $16.29 billion USD, accounting for about 6.6% of the semiconductor market. By 2019, the market size of optoelectronic devices has reached 41.56 billion USD, accounting for 10.1% of the semiconductor market. In

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Fig. 4.13 Global semiconductor market share by product sections (2006–2019). (Data source: WSTS)

2006, the size of the sensor market was about $5.35 billion USD, accounting for about 2.2% of the semiconductor market. By 2019, the sensor market reached $13.51 billion USD, accounting for 3.3% of the semiconductor market. In 2006, the integrated circuit market size was about $209.74 billion USD, accounting for 84.6% of the semiconductor market size. By 2019, the market size of integrated circuits reached $333.15 billion USD; however, the market share was slightly dropped to 80.8%. Analog ICs, MCU, logic ICs, and memory ICs are four main products in the category of integrated circuits. Figure 4.14 shows the product structure of the global IC market from 2004 to 2019. In 2006, the market size of analog ICs was about $36.94 billion USD, accounting for 18% of the integrated circuit market. By 2019, the market size of analog circuit was up to $53.90 billion USD, accounting for 16% of the integrated circuit market. In 2006, the market size of MCU ICs was about $53.94 billion USD, accounting for 26% of the IC market. By 2019, the market size was $66.43 billion USD, still accounting for 26% of the IC market. For logic ICs, the market size in 2006 was about $60.16 billion USD, accounting for 29% of the IC market; the market size then raised to $106.38 billion USD with a 32% market share in 2019. Memory ICs in 2006 occupied a market size of $58.47 billion USD with a 28% market share, and its size had reached to $106.43 billion USD with a 32% market share in 2019. Additionally, because of the rapid development of CMOS technology, the market share of bipolar process products has declined rapidly and now accounts for less than 1% of the global semiconductor market size. Therefore, after 2004, WSTS no longer listed bipolar IC products as a separate item in the category of IC. Bipolar technology-related products are included in the above four categories of products.

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Fig. 4.14 Global semiconductor market share by IC product sections (2006–2019). (Data source: WSTS)

World Semiconductor Council (WSC) The World Semiconductor Council (WSC) is an international non-governmental organization for the global semiconductor industry. It was established on Aug. 2, 1996. Due to the continuous trade disputes between the United States and Japan in the semiconductor industry, the Semiconductor Industry Association of the United States and the Electronics Industry Association of Japan initiated and established the WSC with their respective government support. WSC played a role as a negotiation platform for the semiconductor industry and a competent group to discuss issues related with trade disputes, intellectual property rights, electronic transactions, environmental safety, etc., before these issues were appealed to the World Trade Organization (WTO) and the World Customs Organization (WCO). Additionally, the WSC will provide the WTO with the expertise of the semiconductor industry. In April of 1997, the European electronic components association and Korea Semiconductor association joined the WSC. The United States, Japan, Europe, and South Korea became initial founding members. On June 15, 2006, after 5 years of repeated negotiations and discussions on the basis of “one-China principle,” Mr. Zhongyu Yu, chairman of the board of directors of China Semiconductor Industry Association (CSIA), on behalf of CSIA, signed the “Memorandum of China Semiconductor Industry Association joining the World Semiconductor Council” with Mr. Brian Halla, the rotating chairman of WSC and

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the president of the Semiconductor Industry Association of America (SIA) in 2006. Later, CSIA officially joined WSC. Additionally, the Semiconductor Industry Association in Chinese Taipei (TSIA) had joined the WSC in 1999. The current members of WSC are the China Semiconductor Industry Association (CSIA), Semiconductor Industry Association in Chinese Taipei (TSIA), Semiconductor Industry Association in Europe (ESIA), Semiconductor Industry Association in Japan (JSIA), Semiconductor Industry Association in Kores (KSIA), and Semiconductor Industry Association in the United States (SIA). The semiconductor industries of these six WSC member countries and regions represent the economic scale and development level of the global semiconductor industry. They own more than 90% of the global semiconductor industry share. The WSC platform provides a global authority on the achieved consistent agreements that related with world semiconductor industry market data, industrial policy, intellectual property rights, global trade, and other related issues. Thus, the WSC can provide professional advice pertaining to the semiconductor industry for WTO and WCO. The WSC holds three meetings every year: the Joint Steering Technology Committee (JSTC), whose main attendants are the staffs of secretariat in each semiconductor association; the WSC council, whose main participants are CEOs and chairmen of various semiconductor companies; the Government/Authorities Meeting on Semiconductors (GAMS) whose main participants are officials in charge of semiconductor affairs in government/authority of a country/region. The JSTC generally meets in February every year, the WSC council meets in May every year, and the GAMS regularly meets in October every year. The GAMS conferences mostly focus on issues affecting the semiconductor industry and reach consensus on these issues. Moreover, GAMS receives and discusses reports as well as recommendations on policy issues from the industry. The joint statement of GAMS mentions that the parties have achieved virtually barrier-free trade with each other in semiconductors, including the elimination of tariffs. They also jointly seek to a global barrier-free trade and investment environment to support and coordinate the recommendations of the World Trade Organization (WTO) – including the information technology agreement (ITA). Meanwhile, policies adopted by all parties in protecting intellectual property, carrying out basic scientific research, and protecting global environmental with positive ways are conducive to the sustainable economy growth. In addition, more people will continue to benefit from the information age. These policies will increase the global demand for semiconductors. The chairmanship of GAMS rotates among the founding members for a 12-month term. The chairman will draft the conference resolution and conclude the annual meeting’s summary with reference to the WSC’s recommendations and the previous GAMS resolutions. In addition, with the agreement of each member country, the chair country may also organize symposiums to discuss the specific issues affecting the semiconductor industry. In recent years, the GAMS has hosted several related workshops, including policy discussions on encryption products and discussions on semiconductor stimulus policies in various regions, etc.

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In recent years, several GAMS meetings have made significant progress on many key trade policy measures. For example, to get unanimity on agreements of duty exemptions for next generation semiconductors (hereinafter referred to as multicomponent semiconductor, MCO) applied in a wider information technology, to take ban policy restricting the use of encryption technology, to establish fair and open rules to support for local government projects, to ratify agreements of trade facilitation for WTO to simplify semiconductor trading processes, to protect intellectual property rights, to ban counterfeit semiconductor products from entering the market, and to protect the environment. Since joining WSC in 2006, CSIA has organized industry leaders, professionals, and lawyers to participate in various activities of WSC Joint Steering Technology Committee (JSTC), WSC Council, and Government/Authority Meeting on Semiconductors (GAMS). They also participate in the discussion of various working groups and raise relevant issues. Furthermore, CSIA expresses clear opinions on issues about the rules for country of origin, intellectual property rights, environmental safety and health (ESH), multicomponent semiconductor (MCO) and/or integrated circuits, and the product range of transducers, so as to strive for discourse power for China’s industrial development. It has effectively promoted the development of China’s semiconductor industry.

Semiconductor Equipment and Materials International Semiconductor Equipment and Materials International (SEMI) is a global organization of industry association. It is dedicated to promoting the overall development of supply chain system in the industries of microelectronics, panel displays, and solar photovoltaic. Its members include manufacturing, equipment, materials, and service companies in the supply chain system of the above industry. Since 1970, SEMI has been dedicated to assisting member companies in getting market information quickly, increasing profitability, creating new markets, and overcoming technical challenges. SEMI has 14 offices around the world. They are based in China (Shanghai, Beijing, Hsinchu), Japan (Tokyo), South Korea (Seoul), Singapore, India (Bangalore), Belgium (Brussels), Germany (Berlin), France (Grenoble), Russia (Moscow), and the United States (San Jose, Austin, Washington). The main activities of SEMI include organizing conferences and exhibitions, promoting international standards, developing public policies, conducting market research, as well as advocating industry environment, health, and safety issues. By 1970, the semiconductor industry has built up the momentum of development for at least 10 years. At that time, the global revenues were only a few million dollars. However, this industry has brought together many visionary leaders to create a focused forum for suppliers of semiconductor equipment and materials. This organization is SEMI, and this is how SEMI is formed. The biggest contribution of SEMI to the semiconductor industry is to hold the Semicon Equipment and Materials Exhibition annually in the United States, Japan, South Korea, China, and other places. It brings the world’s latest products of

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semiconductor equipment and materials, including technology to industry. At the same time, various SEMI standard meetings are held too. SEMI can provide customers with information that including monthly orders/ sales (i.e., Book-to-Bill ratio, B/B) of semiconductor equipment, a monthly or 3-month moving average value of equipment sales, the annual ranking of the top 10 semiconductor equipment suppliers worldwide, the revenue of semiconductor front-end materials, the revenue of semiconductor back-end materials, and the statistics of global IC foundry production line number. SEMI has reinvested the proceeds from the exhibition to its business and published the SEMI standards plan. SEMI has more than 30 years of history from its earliest success in standardizing the specification of silicon wafers, devoting to factory automation and software, to promoting market competition and reducing semiconductor manufacturing costs. SEMI standards have also promoted the development of new industries, including current wafer foundry models. As the industry has grown, SEMI has developed more products and services for its members, such as technology seminars, education and training activities, and market data collection and analysis. SEMI speaks for the industry and represents the common interests of its members. It concerns public policy, the environment, health, safety, human resources, and investor relations. Therefore, SEMI contributes to the development of semiconductor industry.

Global Semiconductor Alliance (GSA) The Global Semiconductor Alliance (GSA) was renamed from the Fabless Semiconductor Association (FSA) in 2007. The FSA was established in 1994. In the 1990s, the global semiconductor industry began to evolve from the former IDM model to the development of individual design, manufacturing, as well as packaging and testing, respectively. The purpose to set up FSA was to provide a platform for IC design companies and their cooperation partners, such as wafer foundries and package-testing plants, to further create a more beneficial environment for industrial innovation. With the growing industry, the FSA changed its name to GSA in 2007. Currently, the GSA members from 30 countries and regions around the world have covered more than 350 companies throughout the entire supply chain. GSA provides supports for the industry and its cooperative partners. GSA can cope and propose solutions to various challenges that arise within the supply chain, including IP, electronic design automation (EDA) design, wafer fabrication, testing, and packaging. GSA actively promotes the cooperation between global semiconductor companies and their cooperative partners, and also provides a globalized communication platform. Meanwhile, GSA continues to analyze and research opportunities in the semiconductor market to encourage and support startup entrepreneurship. Additionally, GSA also provides comprehensive market research reports for enterprises. In recent years, GSA has actively promoted the development of the global semiconductor industry and held various seminars. For example, in June 2017,

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GSA successfully held the “2017 GSA Memory+ Forum” in Shanghai to discuss how to push the current storage technologies and system architectures to the next generation to meet the requirements for future cloud computing, mobile, and new applications. This forum delivered insights of the current situation, development trends, and cooperation prospects of the global memory industry. The success of forum promotes the cooperation between Chinese enterprises and the global semiconductor industry. In recent years, several large mergers and acquisitions (M&A) in semiconductor industry have also been driven by the GSA. In March of 2011, Dr. David Wang, then the president and CEO of SMIC, was elected as the director of GSA. On May 9, 2016, Dr. Leo-Liyou Li, the chairman and CEO of Spreadtrum Communications Inc. (new name Ziguang Zhanrui), was appointed as the chairman of GSA board of directors. In December 2020, the GSA BOD appointed Simon Segars, CEO of Arm, as chairman of the GSA Board of Directors.

International Technology Roadmap for Semiconductors The International Technology Roadmap for Semiconductors (ITRS) publishes a set of documents jointly completed by experts from the Semiconductor Industry Association of the United States (SIA), the Semiconductor Industry Association of Europe (ESIA), the Semiconductor Industry Association of Japan (JSIA), the Semiconductor Industry Association of Korea (KSIA), and the Semiconductor Industry Association of China Taipei (TSIA). This set of documents is intended for technical evaluation only and has no commercial tendency to any independent products and equipment. The purpose of ITRS is to ensure the performance improvement of ICs, while trying to achieve higher cost efficiency for the use of IC products and applications, so that the overall industry can maintain a sustained healthy and successful development [2]. The fabrication of ICs or any semiconductor devices requires a series of process steps, including lithography, etching, and deposition. In the early stage of industrial development, most IDM companies used their own developed process equipment to fabricate IC products. However, with the continuous development of technology and the ongoing expansion of the industrial scale, the business model for an IDM company to invest tremendous R&D budgets for self-use production lines becomes unsustainable. Consequently, equipment manufacturing departments and material supplying departments are gradually spun off from IDM companies to form independent external suppliers. Therefore, the industry urgently needs a clear development roadmap for products, markets, and technologies to guide each manufacturer’s product and R&D plans. The SIA was the first to do that. It led and coordinated major manufacturers to develop the US version of the technology roadmap, namely, the National Semiconductor Technology Roadmap for Semiconductors (NTRS).

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In 1998, SIA cooperated with ESIA, JSIA, KSIA, and TSIA to release the first international roadmap, which was the first version of the International Technology Roadmap for Semiconductors. It is expected to continuously update contents and publish a new complete version in odd-numbered years [2]. The International Semiconductor Roadmap Committee (IRC) is responsible for overall coordination of ITRS, hosting and conducting ITRS workshops, and editing and publishing ITRS reports. Two to four members from Europe, Japan, Korea, China Taipei, and the United States, each group has 2–4 members to represent an individual region in IRC to collect information. The technology section of ITRS is edited by the International Technical Working Groups (ITWG). The International Technical Working Groups are divided into a focus group and a lateral working group [3]. There are 17 ITWG to edit the ITRS of 2013 version, including system drivers, design, testing and test equipment, process integration, devices and structures, RF and analog/mixed signal technology for wireless communication, new devices research, front-end processes, photolithography, interconnection, factory integration, packaging and assembly, micro-electromechanical systems (MEMS), new emerging materials research, environment, safety and health, yield improvement, metering, modeling, and simulation, respectively [3]. With the popularization of the Internet and the development of Internet of Things (IoT), the IRC was launched in 2012, and then the reorganization of ITRS to ITWG was completed in 2014. The original 17 working groups were reorganized into seven working groups in 2015. Specifically, there are System Integration, Heterogeneous Integration, Heterogeneous Components, External System Interconnection, More Moore, Beyond CMOS, and Factory Integration [1]. The new roadmap is called as the ITRS 2.0. As the industry generally believed that Moore’s law was reaching its limits, the final version of ITRS was released in 2016. Then a much broader roadmap named as the International Roadmap for Devices and Systems (IRDS), which was created through the IEEE’s initial plan for “restart computing,” will serve as a roadmap. IRDS will be the continuation of ITRS [3].

Worldwide Major Institutions of IC Research and Development Integrated circuit industry is a typical knowledge-intensive, technology-intensive, capital-intensive, and talent-intensive high-tech industry, which requires enterprises not only to have strong economic strength, but also to have a profound foundation of technologies and talents. For the purpose to promote the overall healthy development of the IC industry, each country continues to establish R&D institutes and public service platforms to carry out industrial generic technology and key technology research, assist IC enterprises to breakthrough technology bottlenecks encountered in development, and continue to cultivate talents with theoretical capability and practical experiences for the industry. There are several successful examples for IC research and development described below.

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Interuniversity Microelectronics Center (IMEC) The Belgium research center for microelectronics, also known as The Interuniversity Microelectronics Center (IMEC), was founded in 1984. IMEC is a non-profit microelectronics research center that mainly organizes universities and research institutes to establish connections with industrial production. Its board of directors consists of people from universities, governments, and industry. After more than 30 years of development, IMEC has become the largest and most active non-profit microelectronics R&D center in the world, which continuously contributes new technologies, new talents, and new companies to the industry. Currently, IMEC has a high-tech R&D infrastructure including EUV lithography equipment. It brings together more than 2500 top industry experts from 74 countries and has established a network of cooperative partners with upstream and downstream links of the industrial chain such as Fabless, IDM, Foundry, semiconductor equipment suppliers, and terminal equipment suppliers. IMEC has built an industrial ecosystem with innovative research and development, which effectively connects university’s technologies that have been ahead of the market for 10–15 years with those of the industry that have been ahead of the market for 2–3 years. Meanwhile, IMEC also supports various forms of innovation from all stages including basic research, product development, prototype verification, small batch production, and mass production. Meanwhile, IMEC has also built an innovation ecosystem around the world. In addition to the Belgian headquarters, it also has established offices in the Netherlands, the United States, China, India, Nepal, and Japan. In China, IMEC has established talent training programs, an R&D center, and an IMEC fund. In 2015, IMEC’s R&D expenditures reached 415 million euros and had gradually become the global technology sources and innovation center of the “semiconductor plus.”

Very Large-Scale Integration (VLSI) Consortium The Very Large-Scale Integration Consortium (VLSI Consortium) was founded in 1976. It is a joint technology research and development organization promoted by the Japanese government to develop VLSI to compete with the United States. Its members include NEC, Toshiba, Hitachi, Fujitsu, Mitsubishi Electric, and other large Japanese semiconductor companies. The consortium implements the management mechanism of joint research on generic technologies and relatively independent research and development for products. In addition, the government mainly supports the research and development of generic and basic technologies with a subsidy up to 50% of the total R&D expenditure. The enterprises in the consortium can use the consortium’s patents for free. Before the launch of this consortium, more than 80% of Japanese semiconductor manufacturing equipment was imported from the United States, and by the mid-1980s, all semiconductor manufacturing equipment was localized. The consortium also successfully developed a key equipment for semiconductor manufacturing, that is, the projection lithography machine, which

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laid the foundation for Japan to establish a dominant position in the entire semiconductor equipment field.

Semiconductor Manufacturing Technology Research Consortium (SEMATECH) The Semiconductor Manufacturing Technology Research Consortium (SEMATECH) was founded in 1987. It is an industrial alliance established by the US government for the purpose of integrating the capitals and resources of various enterprises, sharing R&D technology and financial risks, improving the semiconductor manufacturing technology of the United States, and regaining the share of the United States in the global semiconductor market. The successful operation of SEMATECH resulted in a 59% reduction in research investment by member firms, with a benefit-cost ratio of 2.8. Since its launch in 1987 to 1995, SEMATECH had promoted American semiconductor industry back in the competitive position with the number one rank again in the world. At the same time, it had a significant impact on American trade policy, industrial policy, industrial institutes, national innovation system, as well as the technological innovation theory and cooperation strategy management. The SEMATECH ended in 2015 after the mission was accomplished.

Semiconductor Leading Edge Technologies, Inc. (SELETE) Since Japan lost its leading position in semiconductor industry with the establishment of SEMATECH in the United States, therefore, Semiconductor Leading Edge Technologies Inc. (SELETE), a Japanese industry group, was founded in 2006. It was a new attempt for Japanese industry to organize SELETE to regain the number one position in the world. SELETE adopts a hierarchical organization structure. Among the 11 team members, Fujitsu, NEC Electronics, Renesas, and Toshiba are the core companies. Relying on their technology leadership, SELETE accelerates the whole R&D progress and takes the lead in three advanced technologies: front-end technology focusing on practical high-k metal gate (HKMG) materials; back-end technology focusing on porous low-k materials; as well as lithography and masking technology for 45 nm node, 32 nm node, and beyond. In this way, the Japanese semiconductor industry has better integrated the strengths of industry, academia, and the state.

Semiconductor Market Analysis Market analysis and forecast are inseparable from the support of data, and the data in the semiconductor industry are mainly collected and analyzed by market analysis companies.

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Because the data and their definitions of semiconductor market analysis companies vary, such as semiconductor sales, OEM sales, Fabless sales, etc., in addition, the sources of the data are also different; therefore, it is critical to focus on the continuity of data provided by market analysis companies. The world’s leading market analysis companies and institutions include WSTS, SEMI, IC Insights, Gartner, TrendForce, IHS, iSuppli, etc. In general, market analysis companies usually publish forecasts at the beginning or end of each year. During the middle of the year, these forecasts will be revised several times according to the actual conditions of the market. For the development trend of the semiconductor industry, it is impossible to obtain a comprehensive picture of the industry just based only on a certain data acquisition. Therefore, it is often necessary to combine multiple data for observation. However, to avoid the misjudgment, these data from various companies should not be mixed. It is worth noting that the development of the semiconductor industry is inseparable from the general situations of regional politics and economic trends, such as the impact of the global financial crisis in 2009 and the US-China trade conflicts starting from 2018. Currently, due to the shortage of a large number of IC vehicle applications since 2020, the United States, the European Union, and Japan begin to plan to establish an independent integrated circuit industry chain in their own country, which will change the current global division of IC industrial structure. All these changes will affect the market development of regional integrated circuit industry in the next 5–8 years. There are certain criterions in the market forecast, e.g., the quarterly forecasts of 3 months must be very accurate, then the annual forecasts should be valuable, and furthermore, the forecasts in the next 3 years must have good value for reference. Some commonly used market data are listed below.

Days Sales of Inventory Days Sales of Inventory are also called turnover days. It refers to the number of days that starts from the inventory acquisition to consumption and sale of inventory in an enterprise. The shorter the inventory turnover days, the faster the inventory becomes cash.

The Annual Growth Rate of the Semiconductor Industry The annual growth rate of the semiconductor industry (%) ¼ the growth rate of Unit (%) þ the growth rate of ASP (%). For example, global semiconductor industry sales reached $335.8 billion USD in 2014, an increase of 9.8% compared to 2013. Based on the above formula, the Unit (shipment) of global semiconductor industry in 2014 was 76.4 billion pieces, up 8.6%, and the ASP (average selling

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price) up 1.2%. Therefore, the growth rate of global semiconductor industry in 2014 was 8.6% þ 1.2% ¼ 9.8%.

Book-to-Bill Ratio The Book-to-Bill Ratio (B/B Ratio, B/B) is mainly used to measure the prosperity of the semiconductor equipment industry. Usually, when the B/B ratio is less than 1, it indicates that the equipment industry is in a downturn. If the B/B ratio is larger than 1.0, it indicates that the semiconductor equipment industry is booming. The reason for this analysis is that the orders of semiconductor equipment are customized according to the customer’s demands. In addition, the specifications of each equipment are different; therefore, it is impossible to manufacture equipment in advance and put them in warehouses for sale. Typically, the manufacturing cycle for equipment is about 6 months. A large Book value indicates the urgent need to expand its capacity or add new technologies to semiconductor production lines. Therefore, the Book value is as larger as possible. Larger B/B ratio indicates that the load on the semiconductor production line will increase in the next 6 months. Similarly, when the industry is in a downward trend, the Book value will decrease. Even before the shipment of equipment, the customer may request a delay in delivery or cancel the order directly. Therefore, the industry calls the B/B ratio a “barometer” of industrial prosperity. In fact, the B/B ratio can be used not only in the semiconductor industry, but also in other fields. At present, SEMI is the authority to release the B/B ratios, and it calculates the B/B ratio of US semiconductor equipment on a monthly basis, which reflects the prosperity of the US semiconductor industry as well as the prosperity of global semiconductor industry.

Semiconductor Content Semiconductor Content of the semiconductor industry can be described by a simple definition, that is, the total value of semiconductor components in an electronic product as a percentage of the product value. Therefore, it is a concept of average value used to measure the future progress of semiconductor industry. The variation of semiconductor content in electronic products from 1999 to 2021 is shown in Fig. 4.15. It reveals that the value share of semiconductor content in electronic systems has increased from 18.8% in 1999 to 33.2% in 2021. After entering the twenty-first century, semiconductor components have entered thousands of households and the whole industry, such as household appliances, wear belt electronic products, medical equipment, vehicles, industrial automation equipment, and other related products. All these electronic products contain a large number of semiconductor components. Therefore, the trend of Semiconductor Content will be further developed with the development of the social civilization.

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Fig. 4.15 The semiconductor content changes in electronic products from 1999 to 2021. (Data sources: ST, TI, IC Insights)

World Semiconductor Trade Statistics (WSTS) World Semiconductor Trade Statistics (WSTS) is a semiconductor industry statistics company whose members include the major semiconductor manufacturers in the world. WSTS’s monthly chip sales (Billing) reports have been widely adopted by the industry. WSTS is currently recognized as one of the most important statistical organizations for semiconductor market data. Research institutes including the Semiconductor Industry Association (SIA) of America and many market analysis organizations adopt WSTS’s data as the basic data to judge the chip industry and predict the prosperity of the industry. The WSTS office is located in Bruckm€ u hl, Germany. According to the WSTS official website, WSTS used to have 62 member companies, which accounted for more than 75% of the global semiconductor market by sales. The market data provided by WSTS covers a wide range with high precision and detailed contents. WSTS collects and analyzes information from member companies to provide more information needed by the semiconductor industry. This will not only improve the efficiency of the entire industry but also assist to convince governments to adopt

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strategies that support the development of the semiconductor industry. WSTS adopts a membership system in which each member company pays a certain annual membership fee. WSTS publishes monthly, quarterly, and annual data to member companies. Some of these reports require additional fees, but member companies can enjoy preferential prices. The membership fee of WSTS is based on individual member’s revenue. According to data released by WSTS, for example, AMD’s 2011 revenue is $6.57 billion USD, and the annual membership fee is $1700 USD. WSTS has a global semiconductor sales database available for reference which contains sales data by month, quarter, year, and regional (the world is divided into four regions: America, Europe, Japan, and Asia Pacific) for 30 consecutive years from 1986 to the present. AMD announced its withdrawal from WSTS at the end of 2011, and Intel also announced its withdrawal from WSTS in March 2012; therefore, the monthly global chip sales statistics of WSTS will no longer include data from these two chip vendors. Since no Chinese company has joined WSTS so far, only few references are available to the media about China. Usually, WSTS will release two important market data forecasts twice a year in the spring and autumn to provide regional distribution data and product structure data of the global semiconductor market. In addition, WSTS provides global semiconductor sales (Billing) reports, which include the 12-month dynamic averages for the four major regions, as well as the statistics and the forecasts data for global semiconductor sales.

Worldwide Major IC Market Research and Consulting Companies There are several worldwide market research and consulting companies for the integrated circuit industry including IC Insights, Gartner, TrendForce, and Yole. Their majors are described below.

IC Insights Founded in 1997, the company is headquartered in Scottsdale, Arizona, USA. IC Insights is a market research firm focused on the semiconductor industry. Its analyst team has an average of more than 30 years of industry experience. The company provides analysis reports and information services covering integrated circuits, photoelectric devices, sensors, and discrete devices. The most famous of these reports was the McClean report on the IC industry published in 1998. This report provides an overview of the current industry status from the perspective of the impact of global macroeconomic conditions on the industry, the capital expenditure plans of enterprises, the production capacity of wafer foundries, and details of each product market. The McClean report also forecasts global and regional market trends for the next 5 years, including developments in IC manufacturing and packaging

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technology, market share of products, shipments, and price trends. IC Insights has earned a good reputation for its professionalism and accuracy in forecasting data, and the released data is often used as a reference standard for market analysis in the IC industry.

Gartner Founded in 1975, Gartner is headquartered in Stamford, Connecticut, USA. Gartner is the world’s first research and consulting company in the IT field, as well as an authority in this field. This company’s main businesses focus on research and consulting, evaluation, and the Gartner community. The revenue in 2015 is $2.16 billion USD. Its research covers the whole range of the IT industry from the most upstream hardware design and manufacturing to the most downstream end applications. More than 1100 professional analysts conduct research on 1304 subjects, focusing on the business and technology issues that drive the economic development, and serving clients in more than 90 countries. Supported by unique research methods such as the original Hype Cycle model and a powerful industry benchmark database, Gartner can accurately gauge the development cycle of a technology and further make horizontal or vertical comparisons to a certain IT company. In addition, Gartner hosts many expert conferences around the world every year, with the Gartner Symposium being a high-profile event for the IT industry. The topics of the conferences and Gartner’s forecast of future strategic technologies will serve as forwardlooking indicators for determining the development trend of the IT industry.

TrendForce It is a professional research institute providing in-depth market analysis and industrial consulting services, as well as an industrial information matching platform. Nowadays, there are more than 500,000 registered members worldwide. These professionals come from all major emerging industries and technology industries. TrendForce has five main research departments – DRAMeXchange, WitsView, LEDinside, EnergyTrend, and TRI. Research areas include DRAM, flash memory, personal computers, smart phones, notebook computers, tablet computers, displayrelated industries such as LCD TV, panel and touch screen technology, green energyrelated industries such as LED, lighting market, solar energy, electric cars and lithium battery, semiconductor, telecommunication, intelligent appliance (IA), as well as the regional market, such as the research on the structural trend of hightech industry in greater China. TrendForce [4] has a team of professional analysts who are familiar with various industries. These analysts effectively use a variety of research methods to combine the information of buyers and sellers with the latest technology developing trend to provide professional consulting services. TrendForce holds at least five international seminars in Shanghai, Guangzhou, Shenzhen, and Taipei every year [4].

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Yole Founded in 1998, Yole Development Group is a market research and strategy consulting company based on “Beyond Moore’s Law.” This company focuses on MEMS and sensors, medical imaging technology, compound semiconductors, RF electronics, LED displays, optoelectronics, power electronics, battery and energy management, advanced packaging, semiconductor manufacturing, and other fields. Yole provides market consulting, technology and strategy consulting, media services, and financial operation services [5].

Perspectives of IC Science and Technology in Post-Moore Era In the post-Moore era, the science and technology of IC will develop in four directions. The first is “More Moore,” that is, the conventional CMOS will shift to non-conventional CMOS. The half pitch of devices will continue to be scaled down, and non-conventional device structures such as thin gate, multi-gate, and all aroundgate will be adopted. The second is “More than Moore”; devices/components with different process and applications, such as digital circuits, analog devices, RF devices, passive components, high voltage devices, power devices, sensors, MEMS/NEMS, and biological chips, are integrated together through packaging process and then combine with the non-conventional CMOS devices to form new micro-nano systems such as SoC or SiP. The third is “Beyond Moore (or Beyond CMOS),” that is, the basic units of ICs are quantum devices, spin devices, magnetic flux devices, carbon nanotubes, or nanowires devices formed by bottom-up process. The fourth is “Much Moore.” With the high overlap and integration of micronanoelectronics, physics, mathematics, chemistry, biology, and computer technology, new formed discoveries will create many new breakthroughs in science and technology. Then this makes it possible to create a new form of information technology and its industry, as shown in Fig. 4.16. The main characteristic of the circuit system in the post-Moore era is the performance per power ratio. Intel CEO Paul Otellini put forward the concept of “performance per watt ratio” in 2005. He emphasized that “They are trying to meet broader set of user needs. It is not just performance that matters most right now, but performance per watt.” Academician Wang Yangyuan pointed out in his book Green Micro/Nano Electronics that the driving force of the IC industry and the development of science and technology in the future is to reduce the power consumption. Technology nodes are no longer to increase the integration by reducing the critical dimension only, but to improve the performance/power consumption ratio of devices, circuits, and systems is the criterion. Devices with new structures include ultra-thin body (UTB) Silicon-on-Insulator (SOI) MOS devices, FinFETs, FD-SOI devices, planar double gate, vertical double gate, tri-gate, Ω-gate, gate-all-around (GAA) devices, etc. Nanoelectronic devices include carbon nanotube (CNT) devices, nanowire (NW) devices, quantum devices, single-electron devices, spin devices, and resonant tunneling devices. Graphene

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Fig. 4.16 Prospects for the development of micro-namoeiectronics

devices are also one of the carbon-based devices under investigation. At present, the research of memory devices is developing toward the direction of charge free memory devices. The main hotspot of research and development focuses on Ferroelectric Random Access Memory (FeRAM), Magnetoresistive Random Access Memory (MRAM), Phase Change Memory (PCM), metal-oxide-based Resistive Random Access Memory (RRAM), Polymer RRAM, Polymer FeRAM, Carbon Nanotube (CNT) Memory, Molecular memory devices, etc. The development roadmap of the micro/nanoelectronic devices released by ITRS in 2012 is shown in Fig. 4.17. Question marks in Fig. 4.17 indicate the prediction result. Currently, the technology node of IC fabrication has reached 14 nm and 10 nm in 2014 and 2017, respectively. In addition, 7 nm technology and 5 nm technology are in production in 2019 and in 2020, respectively. The 3 nm technology is also kicked off in 2022 and 2 nm technology is to be ready in 2024–2025. In the aspect of new device design, the main research directions are low-power design technology, system-level design technology, and new general-purpose processor platform technology. In terms of manufacturing process, the main research directions are EUV lithography, computational lithography, multi-e-beam direct write, and nano-imprint lithography (NIL). The development direction of packaging technology is multi-functional integrated system-in-package (SiP). The main technical direction is 3D packaging,

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Fig. 4.17 The development roadmap of micron-nanoelectronic devices

including package stacking, chip stacking, TSV technology, and silicon substrate technology. The main application fields include artificial intelligence (AI) brain, deep neural network (DNN) processor, composite biological signal processor, quantum communication technology, holographic glasses, assisted driving, large-scale distributed e-commerce processing platform, industrial control security platform, etc.

References 1. Y.-Y. Wang, Y.-W. Wang, The Development Road of IC Industry in Our Country (Science Press, Beijing, 2008) 2. ITRS 2.0, www.itrs2.net/. Accessed 29 May 2023 3. IRDS Roadmap, https://irds.ieee.org/editions. Accessed 29 May 2023 4. About TrendForce, http://www.trendforce.cn/about. Accessed 29 May 2023 5. About Yole development, https://www.yolegroup.com/. Accessed 29 May 2023

5

Development of Regional IC Industry Guoming Zhang and Ke Li

Contents IC Industry Development in the United States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Industry Development in Europe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Industry Development in Japan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Industry Development in South Korea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Industry Development in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Industry Development in Chinese Mainland . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Industry Development in Chinese Taiwan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

The development of China’s IC industry began with the successful development of the first Si-based digital IC in 1965. The period of 1965–1978 was the beginning of China’s IC industry, to establish a number of research institutes and semiconductor devices factories. From 1978 to 1990, it was the stage that the IC industry introduced the foundry technology, equipment, and explored the development roadmap. In the last decade of the twentieth century, China’s IC industry entered a period of key construction including a 150 mm silicon-based IC production line. Entering the twenty-first century, the industry has stepped into a golden period of development. In order to speed up the development of its IC industry, the state council issued “the Notice of the State Council on Printing and Distributing the Policies for Encouraging the Development of the Software Industry and the IC Industry”, “Notice of the State Council on Issuing Several G. Zhang (*) NAURA Technology Group Co., Ltd., Beijing, China Hwatsing Technology Co. Ltd., Tianjing, China e-mail: [email protected] K. Li Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_5

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Policies on Further Encouraging the Development of the Software and Integrated Circuit Industries”, and “the Guidelines for National IC Industry Development” (referred to as the Guidelines). Among the organizational efforts, the Chinese Semiconductor Industry Association (CSIA) has played a liaison role. Keywords

Roadmap · State council · Software industry · IC industry · Guidelines · CSIA

IC Industry Development in the United States The United States is the birthplace of the integrated circuit industry. Jack S. Kilby of Texas Instruments in 1958 made the first IC concept sample by using germanium material and filed a patent application. In 1959, Robert Noyce of Fairchild Semiconductor proposed the “semiconductor devices-wired structure” based on silicon material, which was soon patented, officially marking the birth of the integrated circuit. Since the birth of IC, the United States has been in a leading position in the global IC industry in terms of technology, scale, and industrial structure. In the early days, the development of the American IC industry mainly relied on government orders. Fairchild, Texas Instruments, and Motorola were important enterprises in the early stage of the development of the American IC industry. These companies were responsible for the development and manufacture of IC products for the “Militia Missile”, “Apollo Guidance Computer (AGC)”, and W2F aircraft data processor. With the support of government procurement, American IC companies have achieved initial rapid growth. In the meantime, the American IC industry rapidly expanded its scale with the help of venture capitals. Five young scientists and three engineers resigned from Shockley Semiconductor Laboratory and then founded Fairchild Semiconductor. These eight are often referred to as the “traitorous eight,” namely, Julius Blank, Victor Grinich, Jean Hoerni, Eugene Kleiner, Jay Last, Gordon Moore, Robert Noyce, and Sheldon Roberts [1]. On July 18, 1968, Gordon Moore and Robert Noyce co-founded Intel, and Andrew Grove joined Intel the same day as the third employee. In 1969, Jerry Sanders and seven others from Fairchild co-founded AMD. Co-founder Jack Gifford later went on to work at Intersil, a unit of General Electric, and founded Maxim Integrated Products in 1983. From the perspective of industrial structure, the structure of American IC enterprises is constantly changing with the market competition. On the one hand, the IDM model from the initial stage of the industry has gradually shifted to the separation model based on the industrial chain. For example, AMD has completely turned into an integrated circuit design company after it removed its foundry business. In addition, Qualcomm is currently the world’s largest fabless company. On the other hand, some semiconductor companies have also become subsidiaries of enterprises manufacturing end products, and some expanded the direction of producing end products for whole machine systems. In addition, the processor chips of Apple’s iPhone are developed by Apple itself, manufactured by foundry companies such as

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TSMC and Samsung, and packaged and tested by ASE and other companies. That is, Apple has created a new model of virtual IDM. In the late 1980s, the U.S. semiconductor industry was once surpassed in size by Japan. This was mainly because the high demand for DRAM at that time, and American companies withdrew from the DRAM market, while Japanese companies had an absolute market competitive position in DRAM field. In November 1989, the U.S. Semiconductor Advisory Committee, headed by Ian M. Ross, submitted a report of “The Strategic Industry in Crisis” to the then President of the United States, George Bush, and proposed recommendations on the development strategy for the U.S. semiconductor industry. George Bush adopted these recommendations and implemented a series of measures that eventually led the United States to regain its leading position in 1993. In 2016, the size of the American semiconductor industry accounted for about 50% of the global semiconductor industry. According to IC Insights data, 22 of the world’s top 50 semiconductor suppliers are American enterprises, in which Intel, Qualcomm, Micron, and Texas Instruments ranked among the top 10 in the world. There were 21 U.S. companies in the world’s top 50 Fabless, including Qualcomm, Apple, Avago Technologies (Broadcom), Nvidia, AMD, Marvell, and Xilinx, etc., and 6 companies of them are in the top 10. In addition, GlobalFoundries ranked No. 2 among the top 10 Foundry in the world, and Amkor ranked No. 2 among the global top 10 OSAT. In 2021, the United States has six companies in the world’s top 10 semiconductor suppliers. They are Intel, Micron, Qualcomm, Nvidia, Broadcom, and TI, with Intel ranking No.2. In addition, the American IDM and fabless enterprises own 54% of the world’s market share. This means that American semiconductor enterprises are still very competitive in the global semiconductor industry.

IC Industry Development in Europe Europe is an important part of the global integrated circuit industry. Its processors, analog circuits, power devices, and other products have strong competitiveness in fields of industrial control, automotive electronics, smart cards, and others. Compared with the United States, South Korea, Japan, and Taiwan of China, the characteristics of European IC industry are more dispersed. Although Germany, France, Italy, the United Kingdom, the Netherlands, Belgium, and Spain all have certain IC strength, but due to the lack of unified resource allocation and development capability, the overall industrial competitiveness is relatively weak. At the end of the twentieth century and the beginning of the twenty-first century, many well-known European IC enterprises have become independent of the entire system manufacturers. Based on the parent system manufacturers in the relevant industry background and customers, these European IC enterprises have strong competitiveness in the market of IC products. For example, Infineon, which became independent from Siemens AG in 1999, has inherited and continued Siemens’ business and product lines, and is in a leading position in the fields of industry, automobile, and smart card. Another example is NXP, spun out of Philips in 2006. It has inherited and continued the business and product lines of Philips and maintains its leading position in

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consumer electronics, communications, networking, smart cards, and other fields. ST Microelectronics (STM) is an example of joint European multinational corporations. With the headquarter in Geneva [2], STM was founded in 1987 through the merger of SGS Micro-electronica of Italy and Thomson Semiconductors of France. Europe’s advantages in fundamental scientific research and talent training have laid a good foundation for the development of IC industry. Belgium’s IMEC has made a great contribution to the technology exportation for global industry. At present, ARM based in the United Kingdom is the world’s largest chipless integrated circuit design house (Chipless Design House, CDH). The company’s intellectual property (IP) rights on ARM processors are applied to almost all mobile terminal processors. Imagination Technology’s graphics processor supports Apple’s mobile phone with excellent performance. Also, Dialog, a German company, is the world’s leading fabless emulator manufacturer. In addition, Europe is highly competitive in the field of lithography equipment. ASML’s high-end lithography tools have unique advantages in the global market. In particular, the trend of technology node continuously keeps scaling; ASML is leading the research and development of EUV lithography and equipment manufacturer in the field of lithography. In 2016, the size of the European IC industry accounted for about 10% of the global market, while in 2021 the share had dropped to 6%. According to IC Insights data, five European companies were among the top 50 semiconductor companies in 2016, with Infineon, NXP, and ST Microelectronics in the top 20. Dialog was ranked 14 among the global top 50 fabless enterprises. In 2021, ASML Holdings and NXP were listed in top 20, while Infineon and ST entered the top 30 [1]. Not a single European Foundry or OSAT company is in the top 10 globally.

IC Industry Development in Japan Japan is a powerful country in the global integrated circuit industry. The development of its IC industry originated from the technology transfer of American semiconductor industry in the late 1960s. In 1963, NEC of Japan licensed the planar IC technology from Fairchild Semiconductor Corporation. Under the request of Japanese government, this technology license was shared with other Japanese companies; thus Mitsubishi, Kyoto Electric Appliances, and other enterprises began to enter the semiconductor industry, which kicked off the development of the IC industry in Japan [3]. Subsequently, the Japanese IC industry embarked on a low-risk development path of “introduction and catch up” [1]. During this period, the Japanese IC industry continued to import technology and patents from the United States to enhance its manufacturing capacity. From 1976 to 1979, Japan began to implement the VLSI alliance, which narrowed the technology gap with the United States and established Japan’s position in the global IC industry in the 1980s. The VLSI alliance has obtained more than 1000 patents in total. The 64 Kbit DRAM technology was successfully developed 6 months ahead of the United States, and the 256 Kbit DRAM technology was successfully developed 1 year ahead of the United

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States. At the same time, the Japanese industry adopted the model of the IC industry development driven by civil electronic products. With the help of this model, Japan occupied the global market with its own manufactured end products and American IC products to create the space for the development of its own IC industry. By the 1980s, Japanese companies had taken the lead in DRAM products. NEC, Toshiba, and Hitachi had long been the top three semiconductor suppliers in the world, while Intel ranked fourth place. Eventually, from 1985 to 1992, Japan overtook the United States to become the world’s largest manufacturing country of semiconductors. In 1989, the market share of Japanese IC products once reached 53% of the global market, far ahead of the 37% of the United States, which opened the golden age of Japanese integrated circuit industry [3]. In 1990, six Japanese companies were among the global top 10 semiconductor companies. They were NEC, Toshiba, Hitachi, Fujitsu, Mitsubishi, and Panasonic. At that time, Japanese IC products mainly relied on DRAM. However, in the mid-1990s, the United States began to refocus on the IC industry. Furthermore, the development of new emerging applications such as personal computers and mobile communication products, etc., and the rapid rise of DRAM industry in South Korea and Taiwan, the proportion of Japanese IC industry in the global market size has begun to decline. By 2012, the only remaining Japanese DRAM company, Elpida, had been acquired by Micron Technology while its technology was still at the forefront. The technology in the Japanese IC industry remains strong and influential despite its declining proportion in global IC market share. In terms of products, Renesas was the world’s largest MCU supplier in 2015. Toshiba is the world’s second large NAND Flash supplier, and SONY is the world’s largest supplier of CMOS Image Sensors (CIS). Meanwhile, Hitachi, Renesas, Toshiba, Mitsubishi, and Fujitsu are the world’s largest suppliers of power devices. In terms of semiconductor materials, Japan produces more than 50% of the world’s semiconductor materials. Shin-Etsu Chemical is an important silicon wafer supplier worldwide. Toppan Printing is the largest photomask supplier in the world. In terms of semiconductor equipment, Japan has five companies among the global top 10 semiconductor equipment manufacturers. They are Tokyo Electron, DNS, Advantest, Hitachi, and Nikon. In 2016, Japanese IC industry accounted for about 11% of the global semiconductor market, and in 2021 the share was 6%. According to IC Insights data, eight Japanese companies were among the world’s top 50 semiconductor companies in 2016. However, Toshiba was the only Japanese company in the global top 10 semiconductor companies. MegaChips of Japan was ranked 25th among the top 50 fabless enterprises in the world. None of the world’s top 10 foundry FABs or OSAT companies are Japanese. In 2021, Tokyo Electron was ranked number 14.

IC Industry Development in South Korea South Korea is a leading country in the global IC industry, with the semiconductor industry accounting for 5% of the national GDP. At present, there are more than 20,000 enterprises supporting its semiconductor industry. The South Korean IC

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industry originated in the 1960s, when US semiconductor companies moved their packaging capacity to South Korea. Starting in 1966, American companies such as Fairchild, Motorola, and Signetics had begun to use South Korea’s low-cost advantages to invest in setting up packaging or assembly plants in South Korea to transfer related production capacity. Subsequently, local South Korean companies represented by Nanya, LG, and Hyundai also began to enter the semiconductor packaging and testing segment. Meanwhile, based on the normalization of diplomatic relations between Japan and South Korea, Japanese semiconductor manufacturers represented by Toshiba also began to invest and build factories in South Korea. The above laid the foundation for the development of the South Korean IC industry [4]. In 1973, South Korea established the National Science and Technology Commission. In 1975, the Korean government formulated a 6-year plan to promote the development of the semiconductor industry and established the Korea Advanced Institute of Science and Technology (KAIST). In 1976, South Korea then established the Korea Institute of Electronics Technology (KIST) to conduct the research on VLSI. In 1974, Korean American expert Kang Ki-Dong founded the first Korean semiconductor company, Korea Semiconductor Corporation (later acquired by Samsung), which marked the country’s own semiconductor manufacturing company. By the end of the 1970s, South Korea had acquired the manufacturing technology for IC industry through the United States and Japan to achieve the technological level of producing VLSI [4]. In 1981, the Korean government formulated the “Comprehensive Development Plan for Semiconductor Industry” to support the development of 4 Mbit and 256 Mbit DRAM [4]. At the same time, with the governmental supports, Samsung, Hyundai, and LG began to enter the field of integrated circuit manufacturing. In 1982, Samsung established a semiconductor research and development laboratory, which focused on the reverse engineering and technology absorption of bipolar and metal-oxide-semiconductor ICs. In 1983, several major semiconductor companies in South Korea began to manufacture DRAM chips for IBM, Texas Instruments, and Intel. In 1986, South Korea started to independently develop memory chips, including 4 Mbit DRAM as a national project. At the same time, Samsung, LG, and Hyundai then formed an alliance, with the Korea Institute of Electronics Technology (KIST) acting as a coordinator between manufacturers, universities, and government. During the 3 years from 1986 to 1989, South Korea invested a total of $110 million USD in 4 Mbit DRAM research and development, of which the government provided 57%. This amount far exceeded budgets of other national projects. The successful research and development of 4 Mbit DRAM has narrowed the gap between South Korea, the United States, and Japan in DRAM technology. In addition, large companies such as Samsung, Hyundai, and LG have established their own research and development capabilities. In 1992, South Korea developed and manufactured 64 Mbit DRAM chips during the same period of the United States and Japan. In 1995, South Korea took the lead in manufacturing 256 Mbit DRAM products, which was already ahead of the United States and Japan.

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In addition to its leading position in the memory field, South Korea also has strong competitive in IC fields such as application processors and ASICs. Samsung Electronics is one of the world’s two largest manufacturers with 3 nm production capacity. Moreover, South Korea is highly competitive in the field of semiconductor equipment and materials. Companies such as SEMES, WONIK IPS, KC Tech, Nepes, and SK Materials have made great contributions to the localization of South Korean semiconductor industry. Meanwhile, South Korea’s memory capacity is also moving overseas. China’s Xi’an and Wuxi have taken over the memory production capacity from Samsung and SK Hynix, respectively. In 2016, South Korea’s IC industry accounted for 17% of the global market, ranking second in the world. According to IC Insights data, Samsung and SK Hynix ranked second and sixth among the global top 10 semiconductor companies in 2016, respectively. Also, Silicon Works ranked 22nd among the global top 50 fabless companies in the world, and DongBu Hitech was ranked 9th among the world’s top 10 foundry companies. In the nearly 5 years from 2017 to 2021, Samsung is further ranked as the first among semiconductor company in 2017, 2018, and 2021 [4]; it ranked second in 2019 and 2020, respectively. The total sales revenue in 2021 was $91.3B, up 30.5% from the previous year.

IC Industry Development in China This section includes two topics: (1) IC Industry Development in Mainland China and (2) IC Industry Development in Taiwan, China.

IC Industry Development in Chinese Mainland As early as in 1956–1958, the two founders of semiconductor technology, Kun Huang (Peking University) and Xide Xie (Hsi-teh Hsieh, Fudan University), once held a professional training class on “Semiconductor Physics” at Peking University, which was attended by 300 people from five universities in China. The course covers Solid State Physics, Semiconductor Physics, Semiconductor Experiments, Semiconductor Materials, Semiconductor Devices and Transistor Circuits, etc. Subsequently, the Chinese textbook Semiconductor Physics (in Chinese) co-authored by Kun Huang and Xide Xie was published in 1958 [5], which has been widely recognized laid the theoretical foundation of semiconductor research and development of IC industry in China. From the training class, academicians Yangyuan Wang and Juyan Xu and others, Shoujue Wang and Shouwu Wang, to name a few, have become pioneers in China’s IC Industry. In 1945–1947, Kun Huang received his Ph.D. from Nevill F. Mott (Nobel prize winner in Physics in 1977) of Bristol University; Huang then in 1947 collaborated with Max Born (one of the founders of quantum mechanics and Nobel prize winner in Physics in 1954) at Edinburgh University; they published a book in 1954 [6].

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In 1965, the first silicon-based prototype IC was developed by using the epitaxy method for the pn junction at the Institute of Metallic Research and the planar method at Shanghai 5th Devices Factory. Meanwhile, the research of p-channel MOS, n-channel MOS, and CMOS technology started at Peking University. With the strong support of the State, from 1965 to 1977, high-speed ECL logic circuits, 1 kbit DRAM, p-channel 1 kbit MOS shift registers, GaAs film growth by MOCVD technology, and GaAs microwave field effect transistors were successfully developed. In Feb. 1998, Beijing Nonferrous Metal Research Institute built China’s first 200 mm silicon single crystalline wafer polishing production line. In Feb. 1999, the first 200 mm IC production line of Shanghai Huahong NEC Electronics Co., Ltd. was officially put into operation. Initiated and founded in 2000 by Academician Yanguan Wang and Dr. Richard Chang, Semiconductor Manufacturing International Corporation (SMIC), supported by scientists and entrepreneurs from both mainland and Taiwan, collaborates with domestic capital and international capital to target the domestic and global IC markets. Headquartered in Shanghai, the first 200 mm fab of SMIC was in production in 2001, followed by a 300 mm fab built in Beijing in 2004, to produce 130 nm/90 nm processes for microprocessors and SoC products. By the end of 2005, the IC production capacity of this 300 mm fab reached 20,000 WPM. Subsequently, the process nodes have been progressed to 65 nm/55 nm and 45 nm/40 nm. In recent years, the IC fabs of SMIC have stepped into the mass production of 28 nm and 14 nm technology nodes, and under the continuous leadership of the new board of directors, its 7 nm technology has made rapid progress in 2023. SMIC was incorporated in the Cayman Islands with funding from worldwide; and today the domestic government has become the major investor. Entering the twenty-first century, several design companies, such as Zhanrui (Spreadtrum) and Hisilicon (of Huawei) had been ranked in top 10 global fabless enterprises in 2016. At present, China’s development in the field of IC Design [7], IC Manufacturing, IC Packaging and Testing, Semiconductor Equipment, IC Materials, etc., is focusing on the overall technological development of the semiconductor industry chain. Today, academic research on semiconductor and/or IC is positive and active, both in institutions and in university education.

IC Industry Development in Chinese Taiwan In 1966, GI Corporation of the United States took the lead in setting up an IC packaging factory in Kaohsiung, Taiwan province. In 1969, TI and Philips began to move their industry and then set up packaging plants in Taiwan. In the same period, the first semiconductor manufacturing enterprise in Taiwan, Fine Product Electronic Corporation, was established, which laid the foundation for the initial development. In 1974, “Industrial Technology Research Institute of Taiwan” established the Electronic Research Institute, and the full name of the institute was Electronic Research and Service Organization, short for ERSO. ERSO concentrated manpower,

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material resources, and financial resources to develop the independent IC technology, and thereafter signed a technology transfer agreement with RCA in 1976 to import RCA’s 5 μm IC manufacturing technology and design technology. In 1978, ERSO successfully mastered the CMOS technology and acquired its own design and mask manufacturing capabilities to set up a CMOS IC demonstration plant. With the participation of the Taiwan governmental authorities and the industry, IC manufacturing plants, the foundry model [7], such as UMC, TSMC, and Winbond, were established in Taiwan in the 1980s. The connection and exchange between Taiwan resources and the US Silicon Valley technology had been opened, which had enabled the rapid development of the IC industry in Taiwan and formed a virtuous circle. At present, Taiwan has become one of the largest semiconductor industrial forces outside the United States, Japan, South Korea, and Europe. The production value of Taiwan’s semiconductor industry totaled $146.76 billion USD in 2021 [8], accounting for a 26% market share of semiconductor revenue, ranking second in the world. In addition, its IC design and packaging and testing industries also account for a 27% and 20% global market share, ranking second and first in the world, respectively. According to IC Insights data in 2021, there are eight Taiwanese companies ranked on the top 50 semiconductor suppliers in the world, among which TSMC ranked third and MediaTek ranked top 10 in 2021. Also, there are 15 companies in Taiwan ranked on the global top 50 IC design companies, of which MediaTek is the fourth largest fabless semiconductor company globally. In addition, TSMC, UMC, Powerchip, and VIS are also among the top 10 foundry fabs in the world. Also, ASE, SPIL, PTI, and ChipMOS are among the top 10 packaging and testing companies in the world. Semiconductor enterprises of Taiwan have begun the cooperation between the semiconductor industry across the Taiwan Strait. For example, TSMC has established a 300 mm wafer foundry fab in Nanjing to manufacture 16 nm wafers; Powerchip and Hefei Municipal Government jointly established a 300 mm wafer foundry fab named as Nexchip.

References 1. T. Charboneau, The “traitorous eight” and the rise of Fairchild semiconductor. All about Circuits, Feb. 28, 2022. https://www.allaboutcircuits.com/news/the-traitorous-eight-and-the-rise-of-fair child-semiconductor/. Accessed 24 May 2023 2. STMicro, https://www.st.com/content/st_com/en.html. Accessed 24 May 2023 3. Semiconductor History Museum of Japan, https://www.shmj.or.jp/english/integredcircuits/ic60s. html. Accessed 24 May 2023 4. W. Li, Samsung Takes Semiconductor Crown from Intel in 2021. Counterpoint, 28 Jan. 2022. https:// www.counterpointresearch.com/semiconductor-revenue-ranking-2021/. Accessed 24 May 2023 5. K. Huang, X. Xie, Semiconductor Physics (Science Press, 1958). In Chinese ISBN 978 70303 46148 6. M. Born, Kun Huang: Dynamic Theory of Crystal Lattices (Oxford Clarendon Press, 1954). ISBN 0-19-850369-5 7. DigitimesAsia, The rise of top 10 IC design companies in China. 19 May, 2022. https://www. digitimes.com/news/a20220519VL202/china-ic-design.html. Accessed 24 May 2023 8. M. Liu, Taiwan and the foundry model. Nat. Electron. 4, 318–320 (2021)

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Information Security in Integrated Circuits Chaohui Wang, Qinsheng Wang, and Qian Peng

Contents IC and Information Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Kinds of Attacks to Information Security in ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-invasive Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invasive Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semi-invasive Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Information Security Protection in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anti-Sniffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anti-Data-Remanence Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prevention from FIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Information Security Protection in CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anti-FIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anti-sniffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defense Against SCA to the Implementation of Cryptography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defense Against FIA to the Implementation of Cryptography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Tolerance Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Robustness and Information Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Information security is the foundation of information systems and the forever theme of the information society. The main issues of information security including non-invasive attacks, invasive attacks, and semi-invasive attacks have C. Wang (*) Beijing Huada Infosec Co., Ltd., Beijing, China e-mail: [email protected] Q. Wang IC Design Branch, China Semiconductor Industry Association, Beijing, China Q. Peng Bank Card Test Center, Chengdu, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_6

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become the hot topic of concerns and focus. As the basic components of electronic information systems, IC plays a critical role in the era of the IoT (Internetof-Things) and is indispensable for all operations and applications in information security system. The attack and defense technology based on ICs becomes a very important research topic in the field of information security and has been also widely used in many industries practically. Keywords

Information security · Non-invasive attacks · Invasive attacks · Semi-invasive attacks · Attack and defense

IC and Information Security Information security is the foundation of information systems and the forever theme of the information society. With the wide applications of computers, networks, Internets, etc. the issues of information security have attracted widespread attention and research. With the rapid rise of smart devices such as smart phones, smart wearable devices, smart homes, smart cars, and intelligent robots, the information security issues of these products have also become a hot topic of concerns and focus [1]. Information security plays an increasingly important role in the era of Internet of Things (IoT). As the basic components of electronic information systems, integrated circuit chips are indispensable in all operations and applications in information security system. Therefore, they are closely related to information security and are the key components supporting information security. With the continuous progress of IC manufacturing technology, the function of integrated circuit is increasingly more powerful, and the internal structure is more and more complex. SoC chips, as the relatively independent information processing system, are getting more and more widely used; therefore, the security of sensitive information in SoC chips often determines the security of the upper systems and applications. Cryptographic algorithm is the core technology to protect the information security, which can be divided into symmetric cryptographic algorithm and asymmetric cryptographic algorithm. Symmetric encryption algorithm is applied for data encryption and decryption operations. The encryption and decryption operations use the same key, which is secretly stored and protected by the encryption and decryption parties. Typical symmetric cryptography algorithms include DES, AES, and SM4. Asymmetric cryptographic algorithm is also known as the public key cryptography, which provides security functions such as digital signature, encryption and decryption, and key negotiation. The key used for digital signature and decryption is called the private key, which must be stored and protected by the users in secret. The key used to verify digital signatures and encryption is called the public key, which can be made public. Typical asymmetric cryptographic algorithms include RSA (RivestShamir-Adleman), ECDSA, and SM2.

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The implementation of cryptographic algorithm in integrated circuits can not only achieve higher cryptographic performance but also provide better protection for key and other sensitive information, including the protection of key storage, read/write, and key participated cryptographic operations. Integrated circuits realize the security control of password algorithm, such as smart card chips, USB key chips, and various secure-element chips, and have become key information security devices on the Internet and Internet of Things security application systems. At present, there are two main reasons to promote the wide use of security controllers: first, sensitive data including keys must be stored in a way to avoid unauthorized access, and security controller can provide a good storage protection; secondly, the security controller provides secure computing methods and environment for the processing of these sensitive data. To discuss the problem of information security in ICs, it is necessary to understand all kinds of attacks against the information in ICs first, then to understand and study the corresponding defense measures, and evaluate and test the effectiveness of these defense measures. Attacks on information in ICs have been around for a long time. For ICs without cryptography algorithms, the main target of the attacker is to clone circuits, obtain or manipulate the sensitive data in memory. For security controllers, the attacker’s goals also include acquiring or manipulating the key in security controllers. The attack and defense technology for information security in ICs is not only a very important research direction in the field of information security but also has been applied in many industries as a practical technology. Typical applications, such as financial IC card chips, have established the corresponding security testing standards and testing certification system both at home and abroad, to enhance and protect the overall information security level of industry applications. The Common Criteria Evaluation Assurance Level (EAL) test evaluation system and EMVCo’s vulnerability assessment method are mainly used to carry out the assessment and testing internationally. The relevant standards for domestic financial IC cards include the “JR/T 0098.2-2012 China Financial Mobile Payment Inspection Specification Part 2: Security Chips” issued by the People’s Bank of China and the “Q/CUP 040.12016 Security Specification for UnionPay Card Chip Part 1: The IC Security Specification” issued by China UnionPay. The national standard GB/T 18336 (equivalent to ISO/IEC 15408 (CC)) puts forward the general security assessment criteria for information security products and systems, which is suitable for information security level assessment in integrated circuits.

Kinds of Attacks to Information Security in ICs The attacked object of an attacker is a security controller, and there are many ways to classify the attacking behavior [2]: 1. According to the degree of invasion of the attacked object, it can be divided into non-invasive (non-intrusive), invasive, and semi-invasive attacks.

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(a) Non-invasive attack does not need to open the chip package or contact the internal circuit of the device. During an attack, the chip can be placed in the test circuit for analysis, and the chip can also be monitored and analyzed in the normal working environment. (b) Invasive attack would require unwrapping the chip and removing the passivation layer with a focused ion beam (FIB) or laser to reach the internal circuitry buried deep beneath the passivation layer. (c) Semi-intrusive attack, like the intrusive attack, needs to open the chip package, but the chip passivation layer remains intact, does not require to make electrical contact with the IC surface, and will not cause mechanical damage to the IC. 2. Based on whether the attacker interacts with the attacked object, the attack methods can be divided into active and passive attacks. (a) In an active attack, the attacker interacts with the attacked object to make it in a state favorable to the attack or to make use of the favorable state or fault information to achieve the purpose of attack. (b) In a passive attack, the attacker does not interact with the attacked object, but only monitors the operational results and status information of the attacked object, and then utilizes the operational results and status information to achieve the purpose of attack. 3. According to the tools and means used by attackers, the known attacking methods include microprobe technology, reverse engineering, software attack, eavesdropping technology, and fault injection attack. (a) Microprobe is used to directly access the chip surface and can be used to observe, modify, or interfere with the operation of integrated circuits. (b) Reverse engineering is a technique used to understand the structure and function of software and hardware. It can be used to derive the internal structure of integrated circuits and to learn or emulate its functions. (c) Software attack refers to finding the defect of security protection in the protocol, cryptographic algorithm, or cryptographic algorithm execution module through the communication interface of the security controller. (d) Eavesdropping technology refers to that the attacker can accurately monitor the interface communication protocol of the security controller, the simulation characteristics during normal operation, and any electromagnetic radiation and then deduce the key data in the security controller by analyzing the obtained information. (e) Fault injection attack (FIA) means that an attacker causes a data or operational failure of the security controller to gain additional data or the ability to read and write the security controller.

Non-invasive Attack Non-invasive attack is easy to implement and does not need a lot of overhead to repeat attacks, leaving no traces of attack, which is considered to be the biggest security threat to security controllers.

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Non-invasive attack [2] can be passive or active. Passive non-invasive attack is also known as side-channel attack (SCA). The attacker does not interact with the attacked targets, but usually only monitors and collects the electrical signals or electromagnetic radiation information of the attacked targets. Common SCA includes power analysis (PA) and timing attack (TA). An active non-invasive attack interferes with the security controller, such as a power pulse attack that adds a pulse signal to the chip’s power cord to put the chip in the desired state or workflow of the attacker. 1. Timing attack: Some operations related to information security will use the input data and keys. Different input data and keys will lead to different execution time of the security operation in the chip. The attacker can recover the keys through clock measurement and analysis. Many cryptographic algorithms are vulnerable to timing attacks, especially software cryptographic algorithms, including program branches, operating conditions, the use of caches, and the operation of non-fixed time processing, which will lead to the difference in execution time due to the difference of input data and key, thus leading to security risks. Timing attack can also be used to crack personal identification numbers (PINs) in security controllers. In general, the risk of PIN verification is that the different check times are performed for correct and incorrect PINs. To prevent timing attacks, PIN verification should ensure that correct and incorrect PINs are the same at the check time, which can be done by adding additional dummy operations to the program. 2. Brute force attack: Brute force attack has different meanings for cryptographic algorithms and ICs. Brute force attacks for cryptographic algorithms are attempts to find the correct matching key by trying a large number of keys. The brute force attack for ICs, one is to try a large number of logic combinations to try to obtain the function of the integrated circuit, which is especially effective for small logic devices. Another is to apply an external high voltage signal (usually twice the supply voltage) to the chip pins in an attempt to get the chip into test mode or programming mode. 3. Power analysis: The power consumption of an operational circuit depends on its current state. According to the characteristics of CMOS transistors, the dynamic power consumption of each unit module is higher than its static power consumption. When the input voltage is applied to the inverter, it causes a short circuit in the transistor, and the increase in the current of this transistor is much larger than the parasitic leakage current consumed in the static state. For cryptographic algorithm circuits, the power consumption state of input data and key is quite different, and the key can be analyzed by measuring the current fluctuation on the power line. There are two methods of power analysis: simple power analysis (SPA) and differential power analysis (DPA). The SPA is to directly observe the power consumption information of IC during cryptographic operation, so as to analyze the key values during the operation. This method requires the attacker to be familiar with how cryptographic algorithm is executed. DPA is a more effective analysis method. The attacker does not need to know how the cryptographic algorithm is executed, but to obtain the hidden key value by analyzing a

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large number of power consumption curves. That is, statistical methods are used to identify the subtle differences in power consumption, so as to obtain the value of a certain bit or a certain segment of the key. Template attack: The template attack is to construct a template with information leakage characteristics for all the keys in the key space of the cryptographic algorithm in advance. Then based on the leaked information obtained from the security controller to find the most matching template, and then deduce the most likely correct key or effectively reduce the key search space of an attack. Template attacks are often combined with SCA, called template-enhanced SCA. Glitch attack: The glitch attack is a non-invasive fault injection attack, which affects the normal operation of the security controller by rapidly changing the signal input to the security controller. A pulse is usually applied to a power supply or clock signal, or it can be an external transient electric field or electromagnetic pulse. (a) Clock glitch attack: Clock glitch attack usually aims at the instruction stream in the security controller; it has no effect on the security operations performed by the hardware. If the internal clock of the security controller is difficult to synchronize with the external clock, it is difficult for an attacker to estimate the accurate time window to implement a clock glitch attack. In addition, the random delay is added to the instruction stream, which will also increase the difficulty of the clock glitch attack. (b) Power glitch attack: Fluctuations in the power supply voltage can lead to the threshold level of the transistor to drift. As a result, some triggers are sampled at different times, and the state of their inputs or security fuses are misread. Power glitches can be applied to a security controller with any programming interface that can affect CPU operation and hardware security circuitry. Each transistor and its associated circuitry form an RC circuit with time-delay characteristics, and the maximum available clock frequency of the processor depends on the maximum delay of this circuit. Similarly, each flip-flop has a time characteristic window between the received input voltage and the resulting output voltage, which is determined by a given voltage and temperature. If a clock glitch or voltage glitch affects some transistor within the chip, causing one or more flip-flops to go into the wrong state, the processor will execute many different wrong instructions, some of which cannot even be supported by microcode. Temperature attack: Temperature attacks are non-invasive fault injection attacks. The attacker interferes with the normal operation of the security controller by changing the external temperature, causing data or operational failures to obtain the desired state or data. Data remanence analysis: When the security controller executes the password algorithm, it usually needs to store the key temporarily in the static RAM (SRAM). When detecting the attack, it will execute the power off operation to make the contents in the SRAM disappear to protect the key from being stolen. It is well known that contents in SRAM can be “frozen” at temperatures below
20  C, so many security controllers treat temperature below this threshold as an attack event. Experiments have shown that data residue in static RAM can also be

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a security issue at temperatures higher than
20  C. The data residue of SRAM is related to the chip power consumption, and the lower the power consumption, the longer the data residue time. Data residual security problems exist not only in SRAM, but also in DRAM, EPROM, EEPROM, and Flash. As a result, some residual information of the data can still be obtained from these erased memories, which brings a great threat to the security controller. Unlike SRAM with only two stable logic states, EPROM, EEPROM, and Flash cells actually store memory charges in the form of analog quantity in the floating gate of transistors. Floating gate charges change the threshold voltage of the transistor, which can be detected by sensitive amplifiers when the memory cell is being read. Experiments have shown that the electrons do not completely leave the floating gate even after multiple erasures, making it feasible to obtain the erased content.

Invasive Attack Invasive attacks [2] require good equipment and rich cracking experiences, and as the size of IC features scaling and complexity increasing, the cost of attacks becomes more expensive. Intrusive attacks generally include the following process: 1. Preparation of sample. Intrusive attacks first require partial or complete removal of the package of the chip, usually using chemical or laser methods. The chemical method usually involves dropping a strong acid onto the surface of the chip package to dissolve the epoxy resin encapsulating the IC, and then cleaning it with acetone/deionized water. 2. Reverse engineering. The structure and function of ICs can be understood through reverse engineering. Usually, the IC is stripped layer by layer in physical or chemical way, and then photographed by optical or electron microscope, and the layout of the IC is reconstructed by analyzing the optical image. 3. ROM information extraction. No matter what kind of encoding method is used in ROM, its encoding characteristics can be generally recognized, and the data stored in ROM can be obtained after a special processing. The ROM programming methods are mainly lead hole mask programming, active region mask programming, and ion implantation mask programming. In ROMs with lead hole mask programming and active region mask programming, the stored data is related to the structure of the line, and the structural characteristics can be directly observed. The different features of the 0 and 1 codes in ion-implanted ROM can be observed only by staining methods. 4. Use microprobe technology. The passivation layer is removed with a laser cutter so that the microprobe can reliably contact the top wiring layer to capture or inject a signal. To obtain keys or other sensitive data in memory, microprobes are usually placed on the data bus. If necessary, the connection with the IC can be established through FIB workstation, and the test point can be led out at any position in the IC, so that the microprobe station can directly observe the internal signals of the IC.

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5. Modify the chip. Keys or other sensitive data in memory may not be necessarily only available on the data bus through the microprobe. For some security controllers, FIB can be used to cut off the internal metal interconnects or destroy the security control circuits to shield the security protection, and then read the key or other sensitive data in the IC without security protection.

Semi-invasive Attack With the shrinkage of IC feature size and the increase of complexity, the requirements for implementing invasive attacks will become higher and higher, and the cost will become more expensive. Semi-intrusive attacks are suitable for small featuresized ICs, which do not require expensive tools, and can get results in a shorter time, making them more attractive to attackers. Semi-invasive attacks typically use ultraviolet (UV) light, X-rays, lasers, electromagnetic fields, and heat, and can be used alone or in combination. 1. UV attack: UV attacks are effective against many OTP and UV EPROM controllers. It just requires opening the package of the IC, finding the security fuse, and resetting the security fuse to an unprotected state with UV light. 2. Backside imaging technique: The first step in the analysis of ICs is to observe them under a microscope. For ICs with small feature sizes, it is difficult to see anything in natural light, while using infrared, near-infrared microscopes, and infrared sensitive lens, whether direct or reflected, these small features can be seen from the back of the chip. The back-side imaging technique can obtain the contents of the ROM or observe the internal interconnections of the chip using a focused ion beam (FIB). 3. Active photon probing technology (active photon probing): A scanning laser beam is applied to an IC to ionize the specific areas of the IC when the energy of the photon is greater than the bandgap of the silicon, then a specific region of the IC can be ionized. In the analysis of ICs, there are two main laser scanning techniques: one is Optical Beam Induced Current (OBIC), which is used on chips without bias voltage; the other is Light Induced Voltage Alteration (LIVA), which is used on chips in operation. The OBIC can be directly used to generate images of ICs. For LIVA, images of ICs can be generated by monitoring voltage changes. If photons reach near the pn junction, the photocurrent will be generated due to the photoelectric effect. When photons enter the p or n region, conduction carriers are injected to lower the channel resistance of the memory cell, which allows the state of the storage cell to be read from the scanned image. 4. Fault injection attack (FIA): The semi-intrusive fault injection attack usually uses the laser irradiation to affect the state of the target transistor, so as to produce a temporary fault, and use the output or influence generated by the fault to obtain sensitive information such as the key in the security controller.

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Information Security Protection in Memory The security controller is designed to provide a secure environment for storing and processing sensitive data including keys. Therefore, it is necessary to provide all-round security protection in memory [3], CPU, and cryptographic operations to cope with various possible security attacks. The following describes the security protection technology of the memory.

Anti-Sniffing There is a consensus to protect the stored contents of security controllers from microprobe sniffing. The initial protection method used was to implant sensitive information into the ROM, but the attacker quickly discovered a way to learn the contents of the ROM. As a result, designers of security controllers began to adopt more secure measures, and one of the initial adopted countermeasures was memory address scrambling. However, the attacker quickly overcame this obstacle by using a computer program to reassemble the plaintext from the scrambled storage information. Thus, simple address scrambling is generally replaced by memory and internal bus encryption, creating a truly effective hedge against sniffing and reverse engineering. In order to prevent attackers from using the test port to attack, the test port circuit of the security controller is usually destroyed during production. The use of a shielding layer is also a common anti-sniffing method. In the 1990s, active shielding measures covering the entire chip surface became popular, and the shielding layer also provided good protection against illegal access and physical attacks. Security controller designers can also consider signal rewiring, such as hiding key signal lines or placing key signal lines at the bottom of the chip, which can increase the difficulty of microprobe sniffing, and can also provide PIN protection for the secure storage area to prevent illegal access.

Anti-Data-Remanence Analysis In order to prevent the analysis of data residue in the memory of the security controller, the designers of the security controller and the developers of the security applications should follow the following design guidelines: (a) Do not store keys, PINs, and other sensitive data in static RAM for long periods of time, change their storage location frequently, and clear the value of the original location. (b) Set the temperature sensor in the security controller to activate the protection state when the rated low temperature is detected and perform the protection operation.

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(c) Before writing any sensitive information to EEPROM and Flash, use a random number loop to erase 10–100 times to eliminate any detectable effects caused by using the new cell. (d) Before erasing sensitive data, the corresponding units of EEPROM and Flash are programmed with random numbers to eliminate the influence of detectable residual charges. (e) Note that some non-volatile memory devices still leave a copy of sensitive data in a specific area after erasing it. (f) Using the latest and highest density memory devices, because the latest storage technology usually makes data recovery more difficult. (g) Using proper encryption methods makes it more difficult to recover data from erased storage units. For secure applications in a secure controller, the ideal state is that every memory in the controller is under its protection.

Prevention from FIA A security controller must consider preventing an attacker from FIA (fault injection attacks) against the memory in it. One of the earliest defenses still used today in low-end security products is the parity protection, where an extra parity bit is added to each portion of memory content (e.g., 1 byte) to check whether the sum of the bits is odd or even. Obviously, the level of parity protection is very low, the success rate is only about 50%, that is, about half of the attacks will be successful, so people will not be satisfied with this kind of security protection. Hardware-supported secured fetching is another way to protect storage from failinjection attacks. Secured fetching usually means that the contents of memory are checked for integrity before being processed on the way to the CPU. These measures have many possibilities for design and implementation, such as the use of arithmetic error detection codes in high-security chips, which can not only detect one or more errors but also have error correction functions. In designing and implementing the secure fetching mechanism, we should pay attention to the balance between the computing performance and security of the security controller. In addition, the process of the memory content being processed in the CPU should also be protected. Otherwise, the secure fetching mechanism is meaningless to defend against some attacks. It is possible to prevent some FIA against memory with tamper-proof sensors and security fuses. Using multiple fuses is better than using single fuses to improve the security of memory. The distance between multiple fuses can be set relatively large, which makes it very difficult to implement the fault injection attack. The security fuse can also be provided with two units, and the fuse can be shielded only when both units are in a fusing state to further enhance the safety of the fuse. A dual-track logic design can also be used to prevent fail-injection attacks (FIA). One approach, for example, is to use dual-track logic on the data line, in which signal 0 or 1 is no longer a high or low voltage on a single line, but a combination of a pair of line signals, for example, 0 may be LH and 1 may be HL. When using the self-

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synchronous dual-track logic, LL stands for static, and HH is a redundant state, so HH can be used as an error signal. This signal can be obtained by a tamper-proof sensor, and the presence of the HH signal will cause the component to lock, preventing the output of sensitive information. To succeed, the attacker must inject both failure states at the same time to make the transmission line switch from LH to HL; otherwise the transmission line will instantly enter the HH state and immediately trigger an alarm.

Information Security Protection in CPU The CPU and memory in the security controller are the attack points that the attacker is interested in. Therefore, it is necessary to adopt various security protection measures in the design [4].

Anti-FIA An attacker may find opportunities to introduce faults during the CPU processing to obtain keys or manipulate software execution. Early ways to protect the CPU from fail-injection attacks were to install sensors that detect environmental conditions, such as clocks, voltages, light, or temperatures. However, fault injection attacks are still possible for other CPU faults, such as laser and electromagnetic radiation attacks, or direct attacks through physical methods, such as FIB manipulation, microprobe, and other technologies. As with the protection methods originally employed by memory systems, the initial solution to enhance CPU security is to use parity bits. The parity bits in CPU registers are very easy to implement without having to design a security controller from scratch, but this simplicity comes at a huge cost to security. The CPU parity protection, like memory parity protection, also has significant drawbacks, so there is a need for better ways to protect the CPU. A very simple way for the CPU to defend against fail-injection attacks is to perform the same operation twice in sequence, compare the results of the two operations, and issue an alarm if the results do not match. However, this approach will degrade CPU performance and can be bypassed by an attacker by performing two fault-injections. Nowadays, multiple fault injection (MFI) attacks are often used by attackers, and the MFI appears more frequently in the process of IC security evaluation and authentication. The typical multiple operation defense approach (with redundancy on the time scale) is vulnerable to multiple failure injection (MFI) attacks because the corresponding attack devices are already present and can override the microcontroller instructions and clock cycle time scales to disrupt the security precautions made through the time scale redundancy. A more secure measure involves the use of tightly integrated dual CPU cores, with both cores constantly checking on each other’s operations and conditions. If the CPU can perform encryption operations, the

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two cores can even use different dynamic keys to greatly enhance the protection against multi-fault injection attacks from multiple times and/or multiple zones.

Anti-sniffing In addition, the CPU must be protected from sniffing attacks. In the development history of security controller in recent decades, the CPU basically works in plaintext mode, which means that an attacker eavesdropping on the CPU can completely obtain the plaintext data processed in the CPU. Early sniffing attack defenses included adding several metal layers to protect valuable signals from theft; shielding measures to fully cover the chip later emerged, some with self-checking capabilities or dynamic arbitrary digital feedback capabilities to check the integrity of the shielding. Today, these measures have very limited effectiveness in the face of FIB, microprobe, microsurgery on a chip, and other attack methods. In addition, there are attack methods that steal the contents of the CPU without any actual manipulation, such as light radiation analysis. This is because silicon transistors emit a very small amount of light during operations, which can be used to read the contents of registers. Security controller designers have recognized the need to enhance the CPU security. The advanced method used today is for the CPU to dynamically encrypt its calculations, so that an attacker can only access the encrypted data. This approach requires a redesign of the CPU, which is not as simple as modifying an existing CPU, but this effort has significant security advantages.

Defense Against SCA to the Implementation of Cryptography For the security controller, the implementation of cryptographic algorithms is closely related to security. The implementation module of cryptographic algorithms should be able to resist various side-channel attacks (SCA) [2] effectively. The side-channel information (such as power consumption curve, electromagnetic radiation curve, time, etc.) disclosed by the operation involved in the key is related to the input data including the key. The security implementation of cryptographic algorithms should mask or eliminate this correlation. Both symmetric and asymmetric cryptographic algorithms are implemented in the security controller to eliminate the following relations as the guiding principle of defending against side channel attacks. That is, 1. the relationship between the data of the key operation and the disclosed side channel information and 2. the relationship between the actual data used in the key operation and the input data.

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Taking the power analysis protection of the asymmetric cryptographic algorithm as an example, the following methods can be used to eliminate the above relationship: power consumption compensation, so that the same power is generated when the private key bit value is 0 or 1; unified operation, so that the private key bit value is 0 or 1 to perform the same operation; to randomize the input data or intermediate value of the private key operation, that is, to mask the real data with a random number before performing the calculation. In order to defend against the power analysis implemented by symmetric cryptographic algorithms, the power consumption compensation and the randomization of the intermediate data (also known as random masking) used in the key-participating operation are also the main methods. The core idea of the mask method is to randomize the intermediate data of the symmetric cryptographic operation, so that the power consumption does not depend on the real intermediate value, which destroys the basic condition of differential power analysis (DPA) implementation. The attacker cannot correctly group large amounts of plaintexts according to the intermediate value and cannot calculate the expected assumed power consumption from the intermediate value. The operations of masking intermediate values with random numbers mainly include exclusive OR, addition, and multiplication. The corresponding masking methods are called Boolean mask, addition mask, and multiplication mask, respectively. The initial method to deal with the side channel attack (SCA) is to apply various noises to the output signal of the chip, but this method is not very effective, especially the analysis method such as DPA has a strong noise filtering capability. At the circuit level, dual-track logic can be used to defend against side channel attacks (SCA). Another advantage of dual-track logic is that all states have the same power consumption weight, making power analysis difficult to perform. However, the implementation cost of dual-track logic is relatively high. It is the most effective and economical way to resist side-channel attack to set up a random number generator in the chip and use random numbers to protect the cryptographic operation.

Defense Against FIA to the Implementation of Cryptography The cryptographic algorithm implementation module in the security controller can also resist various fault injection attacks (FIA) effectively. At present, the main protection methods include fault tolerance technique and fault detection technique.

Fault Tolerance Technique Taking the ECC algorithm as an example, the fault injection attacks (FIA) against ECC can be divided into three categories: security fault attack, weak curve attack, and differential fault analysis (DFA). Security failure attacks implement the analysis

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based on failures that do not change the output. Weak curve attacks attempt to move the point multiplication operation from a strong elliptic curve to a weak elliptic curve to obtain the private key or random number as the multiple of the point multiplication operation by solving the discrete logarithm problem of the elliptic curve. The DFA derives the multiple of the point multiplication bit by bit through analyzing the difference between the correct and incorrect outputs. The corresponding defense methods of these attacks include using error detection technology to detect whether the parameters of elliptic curve are correct, whether the point multiplication base point is on the elliptic curve, and whether the fault is inserted into the data in the point multiplication operation. Once the fault is detected, the execution of the point multiplication operation is aborted, and the output of any results is rejected. The fault-tolerant technique can be used to select an elliptic curve so that even if a fault is introduced into the point multiplication operation, the attacker cannot derive the multiple of the point multiplication from the wrong result, such as twist-strong curves that are fault-tolerant under twist-curve attacks. In addition, some side-channel attack defense methods of ECC also have the capability to defend against some fault injection attacks (FIA), such as the Montgomery ladder and the randomized multiple of point multiplication operation, which make secure fault attacks more difficult to implement. The base point blinding method of point multiplication can defend against the weak curve attack. For the RSA (Rivest-Shamir-Adleman) algorithm, the private key used in the signature can be analyzed based on incorrect and correct signature results. Therefore, it is necessary to perform the fault detection or verify the signature results in the private key operation process. Once faults or incorrect signature results are found, the signature results are rejected. For the public key encryption algorithm that achieves the IND-CCA2 security level, the algorithm itself has built-in error detection technology, which naturally has certain capabilities to defend against fault injection attacks. In the symmetric cryptographic algorithm, the key operation is mainly adding the round key or the S-box substitution, so this also becomes the main attack point selected by the fault injection attacker. Fault injection attacks (FIA) can be classified into temporary and permanent fault injection attacks. In a temporary fault injection attack, an attacker can use techniques such as irregular clock pulses, radiation, and transient high voltage to change a bit in the cache or memory. In a permanent fault injection attack, the attacker can use ultraviolet light or the like to clear a bit in the EEPROM or use a microprobe to set or clear a bit in the EEPROM. Bit fault is an effective fault injection attack in which only one bit is introduced into the encrypted intermediate result while the other bits remain unchanged. As this method is applied to the symmetric cryptographic algorithm, if the attacker repeatedly introduces a bit fault into the intermediate encryption result that is about to enter the last round of encryption, that is, the fault introduced in each encryption changes some of the intermediate result while ensuring the other bits remain unchanged, it is possible to obtain the round key of the last round. DFA is an effective cryptographic analysis

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technology. The basic idea of DFA is to obtain the correct and incorrect ciphertexts corresponding to the plaintext through the fault induction in the encryption process after selecting the plaintext, and then analyze the data of these two ciphertexts to obtain the key.

Error Detection Technique In the implementation of symmetric cryptographic algorithms, the error detection technique is the main principle to defend against fault injection attack. The error detection technique can detect the fault inserted in a symmetric cryptographic operation. Once the fault is detected, the execution of the cryptographic operation is stopped, and the output of any result is rejected. Error detection technique for symmetric cryptographic algorithms includes redundancy-based error detection techniques, code-based error detection techniques, and a mixture of these two techniques. Error detection technique based on redundancy can be classified into hardware redundancy and time redundancy (1). The hardware redundancy-based error detection technique directly copies the cryptographic algorithm hardware as a self-checking method and compares the output of the replica circuit with the result of the original circuit. If it does not match, it indicates an error. (2) The error detection technique based on time redundancy performs the second encryption/ decryption operation on the same data, then compared with the result of the first encryption/decryption operation. This method increases the extra time cost by 100% and can only defend against a single fault injection. (3) Hardware redundancy and time redundancy techniques can be combined to find a balance between hardware and time cost, and an error detection scheme suitable for symmetric cryptographic algorithms to be implemented securely in a security controller can be designed. The simplest error-detection code is the parity code, which can be set to one or more check bits as needed. However, the error detection coverage of parity code is not high enough. When using parity code in the implementation of symmetric cryptographic algorithm, it is necessary to analyze whether its error detection coverage is enough to deal with the possible fault injection attack of the security controller. In order to improve the error detection coverage, the Concurrent Error Detection (CED) method for symmetric cryptographic algorithm is proposed. The CED detects the operation in the symmetric cryptographic operation of the security controller to ensure the correctness of the output. If the CED detects an incorrect calculation, the security controller will discard the wrong result before the output, so the chip can resist the threat of FIA. The coverage of CED error detection is usually much higher than the parity, but it also depends on the coding mechanism adopted and the hardware implementation details.

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Robustness and Information Security Robustness was originally a term used in statistics. It began to be popular in the study of control theory in the early 1970s to characterize the insensitivity of control systems to characteristics or parameter perturbations. In practical applications, the disturbance of system characteristics or parameters is often inevitable. There are two main reasons for the disturbance: one is that the actual value of the characteristic or parameter will deviate from its design value due to the imprecision of measurement; the other is the slow drift of characteristics or parameters caused by environmental factors in the process of system operation. Robustness has become a fundamental issue that must be considered in the design of all types of control systems. In terms of integrated circuits, disturbances come mainly from three aspects: process disturbances; high electrical noise, such as voltage transients and electrostatic discharge (ESD); operating temperatures (such as
40  C to +125  C required by automobile industry). Robust design is required to enable integrated circuits to operate reliably in all extremes of these three parameters. Although robustness and information security are two different concepts, there is a strong correlation between these two concepts in the security controller. The attacker may implement the fault injection attack by changing the environmental factors of the chip. Some measures to deal with fault injection attacks, such as error detection technique and fault tolerance technique, come into play after the occurrence of faults, and the purpose of robust design is to avoid the occurrence of faults. In addition, the robustness of the security controller can also ensure that the security module can play the normal security protection function under the disturbance of various environmental factors. By setting temperature, clock, light, and voltage sensors in the security controller, abnormal fluctuations of temperature, clock, light, and voltage can be detected, and corresponding security protection measures can be taken. However, these security sensors cannot shield faults or damages caused by ESD on integrated circuits. With the continuous shrinkage of feature size and the reduction of oxide layer thickness, integrated circuits are more sensitive to ESD strikes. The wide application of lightly doped drain (LDD) and silicide technologies has greatly reduced the ESD protection performance of previously used ESD protection circuits, such as field devices, MOS transistors, and diodes. The SCR (silicon controlled rectifier) structure of the ESD protection circuit has the highest ESD protection performance per unit area due to its low holding voltage characteristics, so it has become the mainstream ESD protection device. The robustness of the security controller has a significant gain effect on some aspects of its security and has become a key characteristic index of many security controllers. For example, in the financial field with a huge number of smart cards, due to the diverse acceptance environment of financial IC cards, robustness and security are key indicators of financial IC card chips, especially ESD protection capabilities.

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References 1. M. Areno, 4 integrated circuit security threats and how to protect against them. Physical Security. https://www.darkreading.com/physical-security/4-integrated-circuit-security-threats-and-howto-protect-against-them/a/d-id/1341486. Accessed 23 May 2023 2. ADI, Cryptography: Planning for Threats and Countermeasures. https://www.analog.com/en/ technical-articles/cryptography-planning-for-threats-and-countermeasures.html#:~:text¼A% 20security%20IC%20can%20be%20attacked%20by%20one,array%20tampering%2C%20such %20as%20a%20cold%20boot%20attack. Accessed 23 May 2023 3. D. Neustadter, Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks. https://www.design-reuse.com/industryexpertblogs/53687/secure-ddr-dram-against-ro-hammerrambleed-and-cold-boot-attacks.html. Accessed 23 May 2023 4. L. Constantin, The second Meltdown: New Intel CPU attacks leak secrets. https://www. csoonline.com/article/3395458/the-second-meltdown-new-intel-cpu-attacks-leak-secrets. html. Accessed 23 May 2023

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Integrated Circuit Intellectual Property Bulu Xu

Contents Silicon IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status of IC Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Transactions, Cooperation, and Sharing of IPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

The supplies of China’s Si intellectual property (IP) cores are mostly from the overseas companies, e.g., ARM, Synopsys, and others. The “China’s IC Industry Intellectual Property Annual Report,” which is published by the department of intellectual property of China Semiconductor Industry Association (CSIA) and Shanghai Silicon Intellectual Property Exchange Inc., introduces the annual status, including the applications, reuse and service platforms, of IP cores. Si intellectual property cores (IP cores, or briefly IPs) refer to pre-designed and verified functional circuit modules in the design of ICs, including logic, circuit, or layout designs. With the development of VLSI design and CMOS manufacturing technology, SoCs are the products based on VLSI design and supported by the submicron/nano-scale technologies, IP cores, and standard IC modules with the capability of reuse and portable, as well as hardware and software co-design. Keywords

IP cores · VLSI · CMOS · SoCs · IP reuse

B. Xu (*) Shanghai Silicon Intellectual Property Exchange Centre, Shanghai, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_7

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Silicon IP Core In terms of technology, the silicon IP core is an important category of IC intellectual property. It refers to the pre-designed and verified functional circuit modules in the design of ICs with intellectual property rights (including but not limited to silicon), including logic, circuit, and layout unit. Because of high performance, low power consumption, high technology intensity, congregational feature of intellectual property, and high commercial values, the silicon IP core is the most critical industrial factor and the embodiment of competitiveness in the IC design industry. The concept of IP core has been used in IC design for nearly 30 years, while the standard cell library was an early form of IP. At present, the SoC design platform based on IP reuse is adopted by almost all major IC design companies. In practical applications, IP cores include the following connotations: IP must be specially designed according to certain standards for easy reuse and conform to the application interface protocol after the optimization, so as to emphasize the readability of IP codes, the openness of applications, process applicability, debug measurability, port standardization, and data confidentiality. IP design is different from IC design. IPs are used by third-party design companies. In order to make IPs run in the SoC system designed by the third party, it is necessary to establish a compatible environment, including the specification of documents, evaluation environment, and verification methods, especially those configurable and large IPs. The commercial IP core should be equipped with good development documents and reference manuals, including data sheets, user guides, simulation, and reuse models, so as to meet the future SoC integration. In order to solve the applicability problem of IPs, there have been several IP standardization organizations such as Virtual Socket Interface Alliance (VSIA, 1996–2008, USA), Structure for Packaging, Integrating and Re-using IP within Tool-flows (SPIRIT Consortium, merged with Accellera [1] in 2009), Open Core Protocol International Partnership (OCP-IP, acquired by Accellera in 2013), and IP trading organizations such as Design and Reuse (D&R [2], 1997-, France), Virtual Component Exchange (VCX, 1997-, UK), and SSIPEX (2003-, China). IP core owner may use or license the IP core to others. In this sense, the term silicon intellectual property is derived from existing patents and/or original code copyrights (licensing models) in the design industry. Based on features by Gartner, IP is divided into processor IPs (such as MP, DSP), physical IPs (such as PHY, SRAM, DRAM, Flash, I/O, GPS), other digital IPs (such as graphics IP, CODEC, Embedded PLD), wireless interface IPs (such as BT, WLAN), wired interface IPs (such as USB, DDR, PCI, HDMI, MIPI, SATA, Ethernet), and analog mixed-signal IPs (such as AD, DA, AFE, PLL, PM, RF). In the legal field, silicon intellectual property also has specific derivative meanings, that is, patents, copyrights, layout-designs, and process secrets related to all branches of the industry chain in the field of ICs. In 1989, the World Intellectual Property Organization adopted the “Treaty on Intellectual Property in Respect of

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Integrated Circuits”. In addition, the Intellectual Property Agreement regulates the layout design of ICs. Its contracting parties shall provide protection for it in accordance with the conventions mentioned before. The layout design protection of IC in China is relatively late. On March 28, 2001, the State Council passed the Regulations on the “Regulations on Protection of Integrated Circuit Layout Design”, which took effect on October 1, 2001. In accordance with the “Regulations on Protection of Integrated Circuit Layout Design”, the “Detailed Rules for the Implementation of the Regulations on the Protection of Integrated Circuit Layout Design” are hereby formulated and shall come into force on October 1, 2001. In accordance with the “Regulations of the People’s Republic of China on the Protection of LayoutDesign of Integrated Circuits”, the “Administrative Law Enforcement Measures on Layout-Design of Integrated Circuits” were formulated, which took effect on November 28, 2001.

Status of IC Intellectual Property With the development of VLSI design and CMOS manufacturing technology, SoC supported by IP core reuse, hardware and software co-design, and ultra-deep sub-micron/nanometer design has become an important development direction of VLSI. The IP core reuse and transaction of IC modules and supporting files that meet certain standards not only shorten the system design cycle but also improve the success rate of system design. More than 90% of current SoCs in the industry are designed with IP cores as the main design, and a lot of silicon intellectual property such as IP core code and patents are reused. On the whole, IP core field as the upstream in the IC industry, the market presents an unprecedented situation of monopoly and aggregation. From the statistics of the 2014 IP cores sales provided by Gartner, the global semiconductor IP market size reached $2.683 billion USD, of which license revenue was $1.439 billion, royalty income was $1.056 billion, and service income was $188 million. Among the suppliers, the UK ARM’s income was $1.23 billion USD (46% of the market share), the US Synopsys’s income was $370 million (13.8% of the market share), and the British Imagination’s income was $240 million (8.8% of the market share). The top 10 IP providers accounted for a total of 82.6% market share, with a compound growth rate of 12.5% (higher than the average growth rate of 9%). According to the statistics of SSIPEX and D&R, there are 440 global IP suppliers. On the top 50 suppliers, 30 suppliers are American companies. The IP cores sales were reported to be $5.2B in 2021; expected to reach $7B by 2026 and $9B by 2030, growing at a CAGR of 5–6% approximately. The IP core industry values the establishment of the entire ecosystem. It is difficult for companies that only provide a single type of high-performance IP core products with technological advantages to gain a foothold in the market. Correspondingly, in addition to IP cores, but also providing EDA tools, IC manufacturing, design solutions, system supports, and other services of the company, even if the

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performance of IP cores is slightly inferior, however, combining its comprehensive advantages, the formation of a large ecosystem can still obtain customers’ favor. At the same time, IP suppliers can also form a competitive advantage through providing multiple types of IP cores, establishing a small ecosystem, and saving overall costs for customers. At present, the industry’s leading IP companies are constantly through mergers and acquisitions (Ms&As), on the one hand, to establish a comprehensive competitive advantage in the whole process, on the other hand, also continue to enrich their IP product series. With the rise of artificial intelligence (AI), algorithmic IP is becoming a new active IP category, such as gesture, recognition, semantic recognition, expression recognition, panoramic view of audio algorithm, flight control algorithm, and image stabilization algorithm. These algorithms are gradually integrated into large IP cores or IC chips on the terminal to form chips with AI functions. This trend has already emerged, for example, Apical Technology for the visual algorithm IP was acquired by ARM (2016). Qualcomm has also acquired many high-tech companies in recent years.

The Transactions, Cooperation, and Sharing of IPs The silicon intellectual property IP core transaction is essentially authorized by the IP provider due to the excessive concentration of IP providers. In addition, foundry and design service companies can provide their own process IPs and some related IPs. In terms of IP cooperation and sharing, TSMC has proposed and built the Open Innovation Platform (OIP) design ecosystem, through which customers can be provided with design assistance tools, IPs, and process technology, so that customers can shorten the time from product design to mass production. There are two modes of patent transaction in the field of integrated circuit: One is that the patent holders give authorization personally, and another is that the IP operating companies are involved in the trade. The latter model has been commercially successful in recent years. A few typical cases are as follows. In 2010, Intel and the Federal Trade Commission (FTC) jointly announced that they had reached a preliminary settlement over allegations that Intel illegally suppressed the competition in the processor chip market. Intel would revise its intellectual property agreements with AMD, Nvidia, and VIA to give them more freedom to consider mergers or joint ventures with other companies without the threat of lawsuits over Intel’s patent infringement. It also extended its x86 licensing agreement with VIA for another 5 years, through 2018, from the current agreement. In 2012, Bridge Crossing LLC, a consortium affiliated with the patent-operated company AST, acquired ownership of MIPS’ 580 existing patents and 498 pending patents, for which the group would pay $350 million USD. Of this, $167.5 million USD would be paid by ARM. Imagination acquired the operating business of MIPS, the remaining 82 patents, and would permanently retain the royalty-free access to all patents sold to AST for $60 million USD.

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At the end of 2015, the patent operating company WiLAN [3] acquired 3300 patents from Freescale. At the beginning of 2016, Xiaomi purchased 332 US patents from Intel Corporation. As a knowledge-intensive and capital-intensive international industry, intellectual property is the key competitiveness of IC enterprises. According to the SSIPEX statistics, as of the filing date of May 31, 2014, Intel Corporation had a total of 38,392 US patents and 6866 Chinese patents. According to the information in the Intel CPU Design Technology Patent Database, Intel has 5511 US patents and 926 Chinese patents in the field of CPU design. Patents have always been the effective and main means to protect the IC technology innovation in the world, and the patent licensing is also an important source of income for enterprises. For example, Qualcomm’s 2013 financial report showed that the ratio of license business revenue to baseband chip business revenue was about 1:2, but the contribution of pre-tax profit ratio was nearly 9:1. In this way, Qualcomm has combined its standard patent licensing business with the baseband chip design and manufacturing business. Patent operation in the form of license and lawsuit is an integral part of IC industry ecology. From 1997 to 2007, there were more than 900 semiconductor patent litigation cases handled by federal courts in the United States. In recent years, many large IC companies have entrusted patents to specialized patent management agencies. The typical cases about patent litigation are as follows. Marvell, the world’s 8th largest semiconductor design company, agreed to pay Carnegie Mellon University $750 million USD to settle the patent litigation on Feb. 17, 2016. In the Beijing Intellectual Property Court and the Shanghai Intellectual Property Court, Qualcomm accused Meizu of infringing a number of Qualcomm patents covering various smartphone features and technologies, including those related to 3G (WCDMA and CDMA2000) and 4G (LTE) wireless communications standards. These patents are related to radio frequency (RF) circuits. The case, which was accepted by Hangzhou Intermediate People’s Court in Zhejiang Province, was that the (United States) Analuo Corporation accused Hangzhou Silan Microelectronics Co., Ltd., of infringing the exclusive right of the IC layout design. The case, which was accepted by Shanghai Intermediate People’s Court, was that the (United States) Analuo accused Shanghai Belling Co., Ltd. of infringing the exclusive right of IC layout design. The case, which was judged by Nanjing Intermediate People’s Court, was that Resources Silicon PowTech Co., Ltd. accused Nanjing Yuanzhifeng Technology Company of infringing the exclusive right of IC layout design (one of the ten intellectual property cases of Chinese courts in 2010). The dispute between Shenzhen Runteng Micro Technology Co., Ltd. and Shanghai Yachang Electronic Parts Co., Ltd. over the exclusive right of IC layout design (one of the top ten intellectual property cases of Chinese courts in 2014), which was judged by Shanghai High People’s Court. In addition, a typical case of copyright infringement includes the dispute over copyright infringement between Microchip Technology and Shanghai Haier IC Co., Ltd.

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References 1. Accellera Systems Initiative, https://accellera.org/. Accessed 23 May 2023 2. Design & Reuse, https://www.design-reuse.com/. Accessed 23 May 2023 3. About WiLAN, http://www.wilan.com/news/news-releases/news-release-details/2015/WiLANAnnounces-Patent-Acquisition-From-Freescale-Semiconductor/default.aspx. Accessed 23 May 23

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International Competition and Cooperation Guoqiang Li, Zhaozhao Xu, and Min-Hwa Chi

Contents Customer-Owned Tooling (COT) and Foundry-Owned Tooling (FOT) . . . . . . . . . . . . . . . . . . . . . . . Technology License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IP License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Corporation Merge and Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Future Trend and Business Model of Foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Alongside integrated circuit (IC) invention, IC chip design companies need to own not only EDA design tools but also fabrication line, testing tools, and packaging line. Such company is referred to as the integrated device manufacturer (IDM). This situation lasted into the late 1980s, and then the pure-play foundry enterprises and fabless IC design companies appeared into existence. As the foundry model appeared, the IC industry has entered a mature stage. At this stage, in order to realize the strategic intentions of enterprises, mergers and acquisitions (M&A) occur one after another. At present, each sector, IC design, manufacturing, packaging, and testing of global IC industry, is still in the process of integration. In the next few years, M&A in global semiconductor industry will continue to occur.

G. Li (*) · Z. Xu Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd., Shanghai, China e-mail: [email protected] M.-H. Chi GTA Semiconductor Co., Ltd., Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_8

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Keywords

Design tools · Fabrication line · Testing tools · Packaging line · IDM · Mergers and acquisitions

Customer-Owned Tooling (COT) and Foundry-Owned Tooling (FOT) In the early stage of the development of the semiconductor industry in the 1950s, integrated circuit (IC) chip design and IC manufacturing technology were in the exploratory stage. One company designed a certain chip, and at the same time, the company also had to develop the corresponding fabrication technology, such as manufacturing, testing, and packaging, to support the IC production. No one company provided manufacturing services for other companies. In addition, a process technology may only be applicable to some IC chips, and chip design companies engaged in similar products will be competitors. Therefore, companies engaged in IC chips development generally have both chip design technology and chip manufacturing technology, which is called Integrated Device Manufacturing Company (IDM). There are also a few companies that have not only design teams and manufacturing plants but also end product development teams. Such companies are referred to as system companies. Global Information, Communication, Telecom, and ICT Industry, after decades of development and accumulation, it had entered the stage of large-scale commercial applications by 1987. Personal computers (PC) have become ubiquitous in society; the telecommunication industry was mature, Stored Program Control (SPC) exchange system had been widely used; the first generation of wireless communication technology was fully commercialized; and the second generation of wireless communication technology began to be developed. The large-scale commercialization of the ICT industry benefited from the mature semiconductor industry at that time, and its essence was the complete variety of semiconductor chips and the complete maturity of semiconductor technology. At that time, semiconductor technologies were mostly owned by IDM, system companies, or Customer-Owned Tooling (COT) [1]. In the era of IDM and system companies, the relationship between IC chip design and fabrication technology was complementary and inseparable. This situation continued until the late 1980s, when the fabless IC design industry was born. In order to further enhance the market competitiveness, some fabless IC design companies have developed their own differentiated technologies, which have become an integral part of the customer-owned technologies. The technology research and development of pure wafer foundry enterprises has a sequence of process from the purchase authorization to the independent research and development. In the early stage of foundry industry, pure wafer foundry enterprises generally purchase technologies from third-party technology research institutions or IDM companies to establish the basis of independent technology research and

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development. When the process technology accumulation and R&D capability reach a higher level, pure wafer foundry enterprises gradually carry out independent technology research and development and gradually establish an independent technology system, such as standard cells and some IPs. These technologies are referred to as Foundry-Owned Tooling (FOT) [2] or Foundry Model [3] and are typically available to all or some of the company’s customers (IC chip design companies), including current IDM companies. The technology research and development achievements of pure wafer foundry industry are remarkable, among which Taiwan Semiconductor Manufacturing Company (TSMC) is the typical enterprise. The main performance of TSMC is as follows: First, it has formed the technical standard of foundry industry (T-like) and become the industry benchmark; second, it creates the situation of providing manufacturing services for systems-on-chip (SoC), lays a solid foundation for the outbreak of the smart phone industry, and has strongly promoted the development of the global semiconductor industry. At present, the application of the technology category independently developed by pure wafer foundry enterprises has covered most semiconductor chips, and basically only high-end memory chips (NAND and DRAM) and CPUs are still dominated by IDM companies. In the future, the technologies independently developed by the pure wafer foundry industry will be expanded in several ways, including the development of advanced technologies and the integration of various technologies, such as the integration of radio frequency (RF) technology and embedded non-volatile memory (eNVM) technologies.

Technology License Technology licensing in semiconductor industry mainly includes IP (Intellectual Property) and manufacturing technology licensing.

IP License The term IP in the semiconductor industry has two meanings: One is commonly defined as the intellectual property (IP) right (e.g., patents); the other is a circuit module (i.e., IP cores) with specific functions designed based on some patented device structures or circuit topology. IPs can be reused and ported to a variety of technology platforms, with multiple IPs often integrated in some IC chips. In this context, the IP mainly refers to the second type. In the early twenty-first century, with the rise of System-on-Chip (SoC) applications in mobile phone industry, the IP industry has entered a stage of rapid development, among which the most famous IP company is ARM Holdings. After years of development, the current IP category can cover many aspects of IC applications, mainly used in a variety of general or dedicated processors, microprocessors, microcontrollers (MCU), digital signal processors (DSP), and other products.

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In terms of type, IPs mainly include library core and other IPs such as interface IPs. Libraries mainly include Standard Cell Library, Input/Output Library (I/O), Read Only Memory (ROM), and Random Access Memory (RAM). IP cores mainly include embedded processor and microcontroller IPs, non-volatile memory (MVM) IPs, power supply IPs, signal conversion IPs, and interface IPs. Take ARM as an example. Its A-series application processor cores have been widely used in mobile phones and other application processor products. Typical products include Apple’s application processor in mobile phones and tablets, Qualcomm’s/Mediatek’s/Huawei’s mobile application processors, AMD’s server processors, etc. For the microprocessor class, take ARM again as an example. The company’s Cortex-M series 32-bit microcontroller cores have become the mainstream product of 32-bit microcontroller core in the current market. Non-volatile memory IPs mainly include embedded Flash IP, one-time programmable (OTP) storage IP, multi-time programmable (MTP) storage IP, and embedded EEPROM IP. Power IPs include Power on Reset (POR) IP, Reference Voltage (Vref) IP, Voltage Regulator (VR) IP, Low-Dropout regulator (LDO) IP, Charge Pump IP, Voltage Detector (VD) IP, etc. Signal conversion IPs mainly include Analog-to-Digital Converter (ADC) IP and Digital-to-Analog Converter (DAC) IP. There are many types of interface IP, including USB, CAN, LIN, RS-232, RS-485, UART, HDMI, SerDes, PCIe, parallel port, and network port IPs. There are two main IP licensing modes: purchase of “the right of use” and “onetime buyout”. The purchase of “the right of use” refers to the cooperation mode in which the chip design company or the semiconductor manufacturing company purchases the verified IP from an IP owner for limited use, and the purchaser needs to pay IP usage fee and royalty fee. IP usage fee is paid in a lump sum, while royalty fee is charged on the basis of wafers or chips. A “one-time buyout” is a cooperative model in which the buyer buys a verified IP address for unlimited use from an IP owner and only pays for the IP usage. In the case of embedded non-volatile memory (NVM) IPs, some of these IP technologies are so tightly integrated with the fabrication process, and the purchase of IP means the purchase of the fabrication process or even the proprietary equipment from the licensor. In this case, the purchaser can develop a customized IP based on the licensor’s technology to meet the specific demands of the customers.

Process Licensing Process licenses can be divided into complete set of process licenses and process module licenses. In terms of complete sets of process authorization, advanced process license and differentiated process license are more common, such as IMEC of Belgium licensed 65 nm logic process to Shanghai Huali Microelectronics.

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The upfront fee is similar to the royalty fee model for IP licensing, where the buyer pays the upfront fee and/or royalty fee.

Semiconductor Corporation Merge and Acquisition According to data released by WSTS in 2022, the growth rate of the global semiconductor industry from 1987 to 2021 is shown in Fig. 8.1. During the 15 years from 2007 to 2021, the industry experienced negative growth in 2008, 2009, 2012, 2015, and 2019. In recent years, the growth rate of the global semiconductor industry has been lower than 10% except for a few years, indicating that the semiconductor industry has entered a mature stage. At this stage, in order to realize some strategic intentions of the enterprises, merger and acquisition (M&A) [4] events emerge one after another. Currently, the design industry, the manufacturing industry, and the packaging and testing industry in the global semiconductor industry are still consolidating, and the semiconductor industry will continue to see mergers and acquisitions in the next few years. Since 2014, there have been many of mergers and acquisitions in the semiconductor industry. According to IC Insights, the total value of major M&A in the global semiconductor industry in 2015 (see Fig. 8.2) reached $103.3 billion USD. According to statistics, by 2021, mergers and acquisitions in the global semiconductor industry reached a new height in 2016 (see Table 8.1). Among the top ten mergers and acquisitions, the largest M&A is Qualcomm’s acquisition of NXP,

Fig. 8.1 Growth rate of the global semiconductor industry, 1987–2021

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Fig. 8.2 Total annual value of major mergers and acquisitions in the global semiconductor industry from 2010 to 2021

Table 8.1 Major M&A cases in semiconductor industry in 2016

Number 1 2 3 4 5 6 7 8 9 10 11 12

Buyer Qualcomm Softbank ADI Samsung Siemens Microchip Renesas ASML CSCEC Infineon CSCEC SMIC

Seller NXP ARM Linear Harman Mentor Graphics Atmel Intersil Hermes NXP BP Wolfspeed IML LFoundry

Total ($B) 470.0 320.0 148.0 80.0 45.0 35.6 32.0 31.4 27.5 8.5 1.36 0.55

valued at $47 billion USD. This set a new record in the history of global semiconductor industry M&A. However, this merger was eventually called off in 2018 after China failed to approve it. The lowest of the ten M&A deals was Beijing JAC Capital’s $2.75 billion USD acquisition of NXP’s standard product business. The types of M&A are generally classified into pure financial investment and business development. Pure financial investment focuses on the return and withdrawal of capital, and does not seek to control or change the business of the acquired enterprises, such as SoftBank’s acquisition of ARM Holdings and Beijing JAC capital’s acquisition of NXP’s standard product business. Business expansion mergers and acquisitions generally integrate their own businesses and expect the acquired target to help the existing business to achieve “1+1 > 2”, such as scale expansion, business supplement, monopoly of a certain market, etc. Typical cases

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are Qualcomm’s acquisition of NXP and SMIC’s acquisition of LFoundry. The challenge in such M&A is to integrate the acquisition object with the existing business, including the integration of technology, management teams, and corporate culture.

Future Trend and Business Model of Foundry The wafer industry is expected to maintain a high growth rate of around 11% from 2016 to 2021, but the market is becoming increasingly competitive for three main reasons. First of all, because the wafer foundry industry has invested tremendously in advanced process production lines over the years, the global 300 mm wafer production capacity has expanded rapidly from 48 million wafers per month in 2012 to 62 million wafers per month in 2016. Furthermore, data released by SEMI showed that global shipments of silicon wafers had increased by 14% year-on-year in 2021, with total shipments reaching 14.165 billion square inches (MSI), and revenue went up 13% year-on-year to $12.62 billion. Secondly, although the growth of the global economy was slow, even the annual growth rate was 3.6% for 2020, a 6.52% decline from 2015; however, from 2016 to 2021, the compound annual growth rate (CAGR) for the global semiconductor market was 11.0%, due to a very strong period, including the dramatic surge in DRAM and flash memory markets in 2017 and 2018, as well as the strong post-Covid recovery in 2020 and 2021. Nevertheless, IC Insights forecasts that total semiconductor sales will rise at a more moderate compound annual growth rate of 7.1% over the next 5 years. More semiconductor chip demand is needed to fill the capacity expansion, but the market demand is far below the capacity growth rate. Therefore, the fierce competition has become a fact. Finally, because the end products or applications with high demand for emerging semiconductor chips in the current market have not yet emerged, the existing computer market has entered recession, and the smartphone market is increasingly saturated, resulting in the slow growth of the semiconductor market. To cope with market challenges and better support and serve customers, the upstream and downstream enterprises of the semiconductor industry chain, including wafer foundry companies, chip design companies, packaging and testing companies, equipment manufacturers, IP suppliers, and end product design companies, should establish a closer cooperation to achieve win-win situations. This is the strategic alliance of virtual IDM models between all members of the chain. The virtual IDM model first appeared in high-end System-on-Chip (SoC) projects, such as Application Processor (AP), which has more than one billion transistors, including multiple large/small processor IPs, multiple image processor IPs, embedded memory IPs, noise reduction processor IPs, various high-speed interface Ips, and many other IPs. It is essential to use advanced EDA design tools to accomplish these advanced chip designs of this scale. At the same time, in order to minimize the chip space, large capacity NAND Flash memory, DRAM memory, and application processor are often packaged into system-in-package (SiP) types to save the space,

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such as A-series of Apple processors. In this case, it requires the strong support of packaging and testing vendors are required to step in, even at the design stage, to choose the appropriate pin locations for the future packaging and testing. This is the typical virtual IDM cooperation model. Recently, an enhanced version of virtualIDM business model, referred to as “Commune-IDM” (C-IDM), has been proposed, which tightly ties the ownership of the design, the system, and the fabs together. The market demand of China’s domestic semiconductor industry is huge. In recent years, with the increasing demand for integrated circuits in various domestic industries, especially in memory, communication chips, various sensors, and other high-end fields, the import quantity and amount of integrated circuit products are also soaring. According to the 2021 annual market summary report released by China General Administration of Customs and China Semiconductor Industry Association (CSIA), the total IC import value was about $ 432.6 billion USD in 2021, ranking first among overall China imported goods. Although there are many domestic chip design companies, most of the chips developed by domestic companies are low-end or peripheral supporting chips, such as various household appliances, portable products, computer accessories, and peripheral chips of various mobile terminals and mobile phones. Only a few are high-end or core chips, and the overall output value is low. On the one hand, most of the domestic chip design companies have not accumulated enough preliminary technology or application knowledge in many fields to design high-end chips with complex functions and high reliability. At present, only a few companies in China, such as Huawei HiSilicon and Unisoc, have made breakthroughs in core chips of mobile phones and can design and mass produce high-end chips such as mobile application processors and baseband processors. On the other hand, many domestic end-product manufacturers are reluctant to use chips designed by domestic companies. How to promote the application of domestic semiconductor chips in domestic manufacturing industry, the virtual IDM or C-IDM enhanced cooperation model is one of the effective measures. Domestic system manufacturers, chip design companies, and related enterprises jointly define the required chips and apply the required IC chips, which can promote the transformation and upgrading of domestic manufacturing industry, promote the application of domestic chips and the development of semiconductor industry, and achieve a win-win situation. Recently, the Huawei Mate 60 and Mate 60 Pro/Pro+ / RS are high-end smartphone products released by Chinese company Huawei in 2023. It uses the Kirin 9000 SoC chipset designed by Hisilicon and produced by SMIC Foundry. Mate 60 smartphone can support satellite network communications and 5G. It is a big breakthrough in China’s IC industry.

References 1. ASIC Model vs. COT Model, https://anysilicon.com/asic-model-vs-cot-model/. Accessed 23 May 23 2. F.C. Tseng, Foundry Technologies IEEE Xplore 06 Aug. 2002. https://doi.org/10.1109/IEDM. 1996.553030. Accessed 23 May 23 3. M. Liu, Taiwan and the foundry model. Nat. Electron. 4, 318–320 (2021) 4. Mergers & Acquisitions (Ms&As), https://en.m.wikipedia.org/wiki/Mergers_and_acquisitions. Accessed 23 May 23

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Contents Types of IC Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Division of Industry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Segments of Semiconductor Industry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Management Structure of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Four Aspects of IC Enterprises Operation Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Fields that IC Enterprise Management Must Break Through . . . . . . . . . . . . . . . . . . . . . . . . . . Production Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Production Support Business . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asset Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed Assets Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intangible Assets Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inventory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monetary Capital Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Information Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Management IT System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Manufacturing IT System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The IT Service System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Information Security Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Output Management at Intel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three Core Concepts of “High Output Management at Intel” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Managerial Leverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increasing Managerial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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K. Li (*) Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China e-mail: [email protected] K. Zheng Semiconductor Manufacturing International Corporation, Beijing, China M. Zhu Shanghai HLMC Co., Ltd., Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_9

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Concentrating on High-Leverage Activities and Ignoring the Rest . . . . . . . . . . . . . . . . . . . . . . . . Meetings: The Medium of Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decision-Making . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Management by Objectives and Key Results (OKRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

The IC industry has progressed rapidly for nearly 60 years. The business model of IC industry has evolved from “all in-house” to specialty focus, which means from the vertical integration model (e.g., IDM) to the specialty division model. The specialty division includes fabless design house, IC manufacturing (also known as wafer foundry), IP design and services, outsourced semiconductor assembly and test (OSAT), etc. Organizational structure is a system established by managers to effectively realize planning, organization, command, coordination, and control. The operation management of IC enterprises can be divided into four aspects, i.e., strategic, sales, human resources, and financial. The production management of enterprises generally includes three parts: production process management, enterprise logistics management, and enterprise quality management. Asset management is an important part of enterprise management, which is mainly divided into three parts: current asset management, fixed asset management, and intangible asset management. Keywords

Business model · OSAT · Organizational structure · Operation management · Production management · Asset management

Types of IC Companies Since the invention of integrated circuit in 1958, after over 60 years of rapid and sufficient development, the IC industry has changed from the initial “all-purpose” enterprise structure model to the current structure model featuring cluster and specialized division of work. That is, the evolution from the vertically Integrated Device Manufacturer (IDM) [1] to the specialized division model. Specialized division model includes no production line IC design (fabless), IP design and services, Original Equipment Manufacturer (OEM, such as wafer OEM, Foundry), Outsourced Semiconductor Assembly and Test (OSAT), etc.

The Division of Industry Chain At present, the scale of IDM [2] is still dominant in the global integrated circuit industry chain, which basically maintained at $200 billion USD from 2010 to 2015, about 1.2 times the total revenue of Fabless, Foundry, and OSAT [3] in 2015. From

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2010 to 2015, Fabless and Foundry are growing rapidly globally, with an annual compound growth rate of 6% and 12%, respectively.

The Segments of Semiconductor Industry Chain According to business types, IC enterprises located in the main link of the industrial chain can be divided into integrated device manufacturers (IDMs), module manufacturers (MM), electronic design automation vendors (EDA) [4], chipless design house (CDH or IP house), fabless design house (FDH), photo mask manufacturer (PMM), open wafer foundry (OWF), outsourced semiconductor assembly and test (OSAT), etc. Integrated device manufacturer (IDM). An IDM refers to a company that sells its own branded products within enterprise organization that covers the entire manufacturing process from IC circuit design, wafer fabrication, to package and testing. Representative companies include Intel, Samsung, SK Hynix, Micron, Texas Instruments, Toshiba, and Infineon. Some IDM manufacturers also have the capability of designing and manufacturing system-in-package (SiP) products. Electronic design automation vendor (EDA). This refers to an EDA tool supplier that provides IC design-related software tools and computer-aided design (CAD) technology. Typical vendors include Cadence, Siemens (Mentor Graphics), Synopsys, and Empyrean. Chipless design house (or IP house). It is an enterprise that designs IP cores used in an IC with intellectual property rights and provides corresponding services by using process technology of wafer manufacturing. Typical enterprises include ARM, Silicon Image, Rambus, Ceva, D&R, eMemory, etc. Fabless design house. It specializes in design and sale of hardware devices and IC chips while outsourcing the fabrication of IC devices to wafer foundry. Typical enterprises include Qualcomm, Broadcom, MediaTek, Huawei HiSilicon, Unisoc, Huada Semiconductor, and so on. Semiconductor or IC foundry. It has been specializing in manufacturing semiconductor chips for a variety of fabless companies at the same time. Typical foundry enterprises include TSMC, Samsung, GlobalFoundries, UMC, SMIC, HLMC, HHGrace, and so on. In addition, the wafer manufacturers provide wafer products to these IC foundries; some top silicon wafer vendors include Shin-Etsu (Japan), Sumco (Japan), Global Wafer (Taiwan), Siltronic (Germany), Soitec (France), Okmetic (Finland), ZingSemi (China), etc. Outsourced semiconductor assembly and test (OSAT). An OSAT company provides chip packaging and testing services for customers. Typical enterprises include ASE, Amkor, SPIL, Changdian Technology, Tianshui Huatian, Fortis Microelectronics, etc. The structure of IC industry chain is shown in Fig. 9.1. It is worth noting that with the continuous development of the industry, there are signs of business convergence within the upstream and downstream of the IC

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Fig. 9.1 Structure of semiconductor industry chain

industry chain. For example, EDA suppliers, fabless design houses, and wafer foundries also develop IP business. Some IC foundries have begun to involve advanced packaging and testing process. In the future, the IC industry will continue to evolve with the development of economy and technology.

Management Structure of IC Enterprises Organizational structure is an organizational system established by managers to effectively realize the functions of planning, organization, command, coordination, and control. Through this system, managers can reasonably allocate the resources of the organization and successfully accomplish the goals of the enterprise. Typical enterprise organizational structure can be divided into linear system, linear functional system, divisional system, matrix system, and so on. The current large-scale IC enterprise usually adopts the division-based organizational structure, or a business unit with a typical example shown in Fig. 9.2 for reference. Functions of various organization structures of a typical business unit (BU) in Fig. 9.1 are described as below. The general meeting of shareholders is the highest authority of the company. It is composed of all shareholders and makes decisions on major matters of the company. The general meeting of shareholders shall have the power to elect, appoint, and remove directors and shall have broad decision-making power over the operation and management of the company. The board of directors is elected by the general meeting of shareholders and is the business executive organ. It is responsible for the command and management of the business activities of the company or the enterprise. Additionally, it is also responsible for reporting on its work to the general meeting of shareholders of the company and reports on its work. The board of directors must implement the decisions made by the general meeting of shareholders or the general meeting of staff shareholders concerning major matters of the company or the enterprise. The board of directors is a decision-making organization composed of directors, which controls the affairs of the company internally and represents the company externally.

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Fig. 9.2 Organizational structure of a typical business unit (BU)

The board of supervisors is composed of supervisors elected by the company’s employees democratically. It is responsible for supervising the company’s daily operation activities and correcting the behavior of directors, managers, and other personnel violating the system and regulation of association. The president is the main responsible person or administrative leader of an IC enterprise and has the right of planning, suggestion, veto power, and scheduling for the company’s production and operation. The president is authorized to have the right to examine and verify the completion of the tasks by the various subordinate functional departments and have the guiding power and examination power over the work of managers of subordinate functional departments. In addition, the president is responsible for organizing and coordinating the completion of the company’s annual production and operation plan and responsible for organizing and promoting the company’s medium- and longterm development plan. If the serious distortion of research information affects the company’s major decisions and causes losses to the company, the president should assume corresponding economic and administrative responsibilities. The planning and development department mainly analyzes the development trend of the industry and the situation of competitors, formulates the company’s business development plan, provides strategic analysis suggestions for the decisionmaking of the company’s senior management, and makes business strategies for new businesses. The public service department is mainly responsible for archival document management, confidentiality, stamp management, and other work. The general affairs department is overall in charge of the administration and general affairs of the whole company. The legal department mainly has three functions: the review of contract documents, the custody and management of finalized documents, and the establishment and survival of companies. The review of contract documents mainly includes the

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review, modification, and confirmation of all contracts, agreements, memoranda, letters of intent, and other documents signed externally, the negotiation and consultation of major documents, the review and modification of all external documents that need to be sealed, and the collaborative review of contracts coordinated with consultants and lawyers. The technology research and development (R&D) department is mainly responsible for the formulation of the overall technology R&D plans of the company, as well as the R&D of new products, new technologies and new processes, the design of technology transformation projects, the technology management of production processes, the organization of the application of new technologies and new processes, and technology exchange activities. The factory operation department is mainly responsible for the production management of the IC factory, including organizing production lines and setting up production management systems, preparing production plans, controlling production schedule, inventory, quality, and cost, as well as ensuring customer product delivery according to the production schedule. The marketing department is mainly responsible for the management, supervision, coordination, and service of all sales links in the process of realizing the value of the company’s products. Its main work includes market research, marketing planning, preparing and organizing the implementation of annual marketing plans, being responsible for the review and implementation of specific sales contracts (orders), customer management and credit risk management, after-sales service management, being responsible for the management of marketing revenue and sales expenses, brand building, building the marketing personnel team, participating in the preparation of the annual work report of the enterprise, responsible for providing relevant data to the finance department, participating in the formulation of science and technology development strategy, providing the technical department with domestic and foreign market situation and trend analysis report, participating in annual new product development, providing market information to technical department, etc. The engineering service department is fully responsible for the production support work of the wafer manufacturing factories or packaging test factories and is generally subordinate to the factory administration, safety, environmental protection, health department, and procurement department. The factory affairs department is fully responsible for the water, gas, electricity, air conditioning and clean room environment in the production process, as well as whether the production equipment is in normal operation conditions to meet the production requirements and ensure the normal and orderly production activities. In addition to ensuring the normal operation of the production process, the factory affairs department also formulates plans to reduce production costs. The Department of Environmental Health and Safety (EHS) is mainly responsible for the safety of the factory operation, including the fire protection system, environmental protection, safety production, and other related services.

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The procurement department is mainly responsible for the preparation and management of purchasing plans for equipment and raw materials needed in the production process. The Human Resource Management (HRM) is mainly responsible for the formulation of employment system, personnel management system, employee compensation system, personnel file management system, the preparation of staff manual, training programs, etc. At the same time, HR department implements recruitment, training, performance, compensation, and employee relations five modules of management, to provide and cultivate qualified personnel for the company. The logistics support department provides material services for the smooth implementation of functions of other departments, including canteen, accommodation, cleaning, security, vehicle scheduling and management, greening, office supplies, IT support, etc.

Operation Management of IC Enterprises The Four Aspects of IC Enterprises Operation Management The management of IC enterprises can be generally divided into strategic management, marketing management, human resources management, and financial management.

Strategic Management Strategic management refers to the long-term and overall plans made by enterprises for their survival and development based on summarizing historical experiences, investigating the current situation, and predicting the future in the fierce market competition environment. The most classic IC enterprise strategy is Intel’s “TickTock” strategy, also known as the “pendulum” strategy. The key to this strategy is Intel’s 2-year cycle of product and process development. In the first year, the “Tick” year releases CPU products manufactured on the new process. In the second year, the “Tock” year, an improved version of the CPU is released based on the previous year’s process. The “Tick-Tock” strategy enables Intel to continue to move forward along Moore’s Law and gradually grow into the world’s largest IC enterprises. However, for advanced nodes of 14 nm, 10 nm, and beyond, Intel says it will move away from “Tick-Tock” in 2016 and take advantage of the 3-year rhythm in process, architecture, and optimization strategy. Marketing Management Marketing management is the intermediate link between market demand and enterprise response, and it is also an important method to defeat competitors and gain profits. Enterprise marketing activity is a systematic work, and its management

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process should use systematic methods to find, analyze, and select market opportunities, and then turn market opportunities into profitable opportunities for enterprises. Marketing management mainly includes identifying market opportunities through research, selecting target markets, determining marketing mix, developing marketing plans, as well as implementing and controlling marketing plans. Different types of IC enterprises provide different types of products and services, and they also face different customer situations. Fabless companies sell their IC products to the downstream application manufacturers in the industrial chain, not only through direct sales, but also through distributors or agents. IDM enterprises not only sell products, but also open some capacity of production lines to other IC manufacturers, and their customers are more complex. Foundries and OSATs provide manufacturing services to IDM or fabless, so the focus of marketing management for these two types of IC companies is to meet customers’ process technology requirements, ensure stable orders, and maintain high levels of capacity utilization.

Human Resource Management Human resources refer to the total number of management personnel, technical personnel, operation personnel, and auxiliary personnel in an enterprise. Human resource management (HRM) refers to the planning, organization, leadership and control of human resource acquisition, training, rational allocation of human resources, and full use of human resources. There are seven aspects specifically involving human resource planning management, job analysis and job design management, enterprise recruitment and employment management, enterprise performance management, enterprise compensation and welfare management, enterprise human training and development management, and enterprise labor relations management. Different types of IC enterprises have great differences in human resources allocation, and the specific management content is also different. IDM enterprises include three main links of IC industry chain, among which the composition of human resources is the most complex. Fabless, on the other hand, relies heavily on intellectual workers. In addition to IC design, which including systems, circuits, and software, fabless enterprises also recruit Application Engineers (AE) and Field Application Engineers (FAE) to accelerate the alignment of application requirements. Especially in recent years, fabless enterprises have increasingly hired technicians with process and packaging backgrounds to speed up the time-to-market and better connect with foundries and OSATs. Process yield is one of foundry’s core competencies, so in addition to production line operators and process development engineers, foundry companies also need a significant number of operation management personnel. In addition, foundry companies are also increasingly hiring IC designers and IP managers as it expands into design services alongside manufacturing. In a word, although from the perspective of the enterprise operation, the three-core links of the industrial chain – design, manufacturing, and packaging and testing – are developing independently, the human resources of the three links are continuously integrated.

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Financial Management Financial management is the general term of a series of economic management activities in which enterprises organize the capital operation and deal with financial relations. It is an important part of enterprise operation and management, mainly including capital raising, capital investment, capital operation, income distribution, and financial analysis.

The Fields that IC Enterprise Management Must Break Through In addition to many similarities with traditional enterprises, IC enterprises, as capital and technology-intensive high-tech manufacturing enterprises, must make breakthroughs in the following areas of management.

Cost Management At present, most IC enterprises only do the standard cost management down to the processing layer, which means that the cost of wafer only roughly depends on the number of mask layers. However, some enterprises have developed a special standard cost accounting process. That is, according to fixed assets budget, depreciation of fixed assets, expense budget, master production plan, standard process flow, and cost element apportionment method, the standard detailed cost can be calculated by recipes. Then according to these data, combined with the actual number of fabrication steps taken by the product in the production management system, the actual manufacturing cost of the current period can be calculated. The cost of equipment depreciation accounts for more than 50% of the cost of integrated circuit enterprises. And the standard cost in the operation management system can be treated as the daily accounting, in which the formulation method is the key. Supply Chain Management The supply and demand as well as the input and output are the basic problems faced by every manufacturing enterprise. Due to fluctuations caused by the business cycle, investment in production equipment is extremely expensive, and many chemicals and gases are involved in special procurement restrictions; therefore, it is necessary to establish a series of management methods related to medium and long-term strategic planning, production planning, order delivery management, calculation of equipment processing capacity, etc., so as to support capacity planning and distribution, wafer fabrication planning, order delivery, and other complete planning of different data sources. In addition, since most of equipment spare parts and raw materials are imported, the quantity planning, logistics control, and inventory capital must be considered comprehensively. For example, the technological process of different products must be carried out according to the production plan, and alternative materials should be considered in combination with safety stock, fixed quantity of materials, on-site

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allowance, and other attributes of material procurement. All abovementioned factors should be incorporated into enterprise specific material requirements planning.

B2B Data Exchange Due to the industry characterized by an extremely high degree of automation and the production performed according to the customer orders, this industry must convey information of customer interest in a timely and accurate manner. Therefore, it is necessary to establish a B2B system with the automatic data transmission mechanism between enterprises and customers. A common way to do this is to provide the real-time B2B information about Working in Process (WIP) and shipping. WIP information enables customers to keep up to date with the production process. On the one hand, the ship information can inform customers of actual shipping information. On the other hand, engineering-related information can be transferred to downstream manufacturers by customers. This not only greatly increases the speed of delivery but also avoids human error to a certain extent. Paperless Complex Business Processes In the actual work of enterprises, there are many complex processes related to business systems and production systems. The efficiency of factories and business departments can be improved only by making complex business processes paperless, such as process change review and management, instrument management, circulating product management, work order management, and recipe change. Quality System Construction There are various types of downstream manufacturers and end customers of ICs. In order to meet the demands of different groups on product quality, it is necessary to establish a complete quality management system, and through the third-party certification, such as ISO 9001, ISO 27001, TS 16949, etc. At the same time, full attention should be paid to the management of all business secrets, such as enterprise’s independent patents, design intellectual property rights (IP), and independently developed software.

Production Management of IC Enterprises The production management of enterprises generally includes production process management, enterprise logistics management, and enterprise quality management. For IC enterprises, IDMs, foundries, and OSATs are the main enterprise types to manufacture IC products. Integrated circuit production management refers to the production activities formed by planning, organizing, directing, supervising, and adjusting related resources according to the established goals of the company. Its goal is to minimize costs and maximize output under the premise of ensuring safety and quality. IC production management includes clean room safety management,

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clean room personnel protocol management, production equipment operation management, online product management (on-time delivery, exceptional handling), lean production, automatic production scheduling, etc. Integrated circuit production management is generally divided into three major businesses, namely, security business, on-site production business, and production support business. Integrated circuit enterprises usually run 24 h a day throughout the year. According to the working hours, the production management department is divided into shift personnel (4 shifts and 2 operations) and daily personnel.

Security The security service refers to the full-time security manager and online security personnel. Through the connection with the company-level security department, to ensure the production line is under safe operation by full-time online security personnel for 24 h a day. The largest investment in the integrated circuit industry is concentrated in the clean room, so the safe operation of the clean room is the most important, because every small security risk may cause huge losses. The safety team is organized by the production line employees, who are more familiar with the site and have shorter response time for abnormal situations, so that the hidden dangers can be eliminated as soon as possible to avoid greater losses later. The security personnel shall consist of one daily staff member and at least one security officer per shift.

Field Production The main responsibility of the field production operation is to manage all the machines and products on site by adopting the “4 shifts and 2 operations” mode. The clean room area is relatively large, usually 10,000 ~ 30,000 m2, generally grouped and managed by process module, usually divided into photography, etching, cleaning, diffusion, ion implantation, chemical vapor deposition, metallization, planarization, copper process, and in-out inspection. There are 1–2 on-duty managers for each shift and 1 team leader for each district. Employees are usually calculated according to the man-machine ratio. The man-machine ratio of automatic production line is 1:10, and that of semi-automatic production line is 1:3. Usually, the staff is responsible for the basic 6S work in their team area, monitoring the machine status and product processing status, managing non-product silicon wafers, contacting and informing abnormal problems, and accepting special treatment as instructed by the engineering department. Semi-automatic production lines need to perform the wafer lot handling according to the production control requirements, while automatic production lines only need to supervise the processing sequence of wafer lot handling in equipment.

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Production Support Business Production support services include employee qualification training, assessment and certification, automated production control, lean production promotion, as well as production planning and on-time delivery for order (OTDO) control.

Employee Qualification Training, Assessment, and Certification A complete operator training system and electronic assessment process shall be established to ensure that each operator has been fully certified before working in the production line and should be re-certified annually. Automatic Production Control Integrated circuit enterprises generally adopt information-based production management system, including enterprise resource planning (ERP), manufacturing execution system (MES), automatic material handling system (AMHS), equipment automation program (EAP), automatic process control system (APC/FDC/SPC), real-time dispatcher (RTD), etc. Through the pre-programmed standard process flow, the information of product to be processed, as well as EAP/APC/FDC/SPC online equipment status and process parameters, will be fed back to MES system in real-time. After the operation of the RTD system, the assign production tasks will be delivered to the AMHS and EAP system of equipment to achieve the automation and standardization of manufacturing process, seek the optimal solutions of manufacturing process, and provide reasonable product scheduling algorithms for the production real-time dispatching system. Lean Production Promotion Through the integration of big data, systems, and platforms, the data sharing within the enterprise can be achieved to identify bottleneck equipment in production lines and then make the capacity improvement request to equipment, process, and engineering departments. Production Planning and OTDO Control According to the balance of customers’ orders and production lines, the planning department and sales department of the counterpart company promise the delivery date and quantity of orders to customers, ensure that products are put in place, and timely deal with all kinds of urgent needs of customers and abnormal situations of production lines.

Asset Management of IC Enterprises Asset management is an important part of enterprise management, which is mainly divided into three parts: current asset management, fixed asset management, and intangible asset management. The asset management of IC enterprises refers to that such enterprises aim at improving the utilization rate of assets and reducing

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operating costs, based on enterprise information management system, to implement the whole process management from requisition, purchase, acceptance, use, and maintenance to scrapping of the enterprise-owned assets, including physical assets management and the value of the asset management. Physical asset management is usually led by the finance department or a separate asset management department, and is jointly implemented by the procurement department, production planning department, equipment management department, warehouse management department, and manufacturing department. The asset value management is the responsibility of the finance department. In terms of asset types, IC enterprise asset management can be divided into fixed asset management, intangible asset management, inventory management, and monetary fund asset management.

Fixed Assets Management The fixed assets of integrated circuit enterprises usually include machinery and equipment, power systems, tools and appliances, and office equipment. IC equipment is usually very valuable. The equipment investment of an advanced integrated circuit production line is usually more than ¥10 billion RMB or even more than tens of billions of RMB. Therefore, the management of fixed assets is an important part of asset management of IC enterprises. From the management practice of fixed assets in integrated circuit enterprises, the first is to reasonably define the standard classification of fixed assets. The accounting standards for enterprises issued by the Ministry of Finance no longer specify the value standard of fixed assets. Therefore, it is necessary for enterprises to reasonably define the classification standard of fixed assets according to the value, service lifetime, use mode, and other factors of assets, taking into account the objectives and efficiency of asset management in accordance with the principle of importance. A fully covered fixed assets management system should be established. In order to meet the refined requirements of IC enterprises for asset management and ensure the implementation of asset management responsibilities, enterprises need to combine their own organizational structure, according to the principle of management responsibility without blind spots, with the help of enterprise management information system (ERP), to establish a full coverage of fixed asset management system.

Intangible Assets Management As a technology-intensive industry, integrated circuit enterprises usually have a large number of intangible assets, including patent rights, non-patented technologies, concessions, etc. Once the occurrence of intellectual property disputes, it will cause huge losses to enterprises. Therefore, integrated circuit enterprises need to attach great importance to the management of these assets without physical form, especially to pay attention to the correct maintenance and use management of

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intangible assets. Enterprises can set up specific departments responsible for the management according to the category of intangible assets. For independently researched and developed self-intangible assets, the whole process management covering project approval, implementation tracking, achievement evaluation, patent examination, and other links shall be established. For the purchased intangible assets, the whole process management covering procurement examination and approval, acceptance, use management, and other links shall be established.

Inventory Management Inventories refer to the finished products or commodities held by the enterprise in its daily sales activities, products in the process of production, and materials consumed in the production process or materials for providing services. IC enterprises consume many kinds of materials and materials in the production process, some of which also need to be imported. There are many varieties of finished products and products in the production process, and each product has many production steps. Once the supply of raw materials is interrupted (commonly known as “raw material breakage”), the loss will be huge. Therefore, there is a high demand for inventory management. The objective of inventory management is to reduce the inventory cost and the capital occupation as much as possible under the premise of ensuring smooth production and operation. For the materials consumed in the production process, integrated circuit enterprises usually set up the special materials management department, together with the production planning department, procurement department, manufacturing department, etc., according to the regularly updated production plan, to dynamically adjust materials procurement and arrival plans. For finished and semi-finished products, they are usually managed and monitored dynamically by the production planning department.

Monetary Capital Management Monetary capital usually includes cash assets (cash, bank deposits, etc.) and quasicash assets (marketable securities, accounts receivable, etc.). The objectives of the monetary capital management of IC enterprises are basically the same as that of other enterprises, that is, on the premise of ensuring the turnover and security of monetary capital, to improve the benefit of monetary capital as much as possible.

Information Management of IC Enterprises Enterprise information management refers to the collection, processing, input, and output of information. The ultimate goal of information management is to improve the utilization efficiency of enterprise and social resources. The main contents of enterprise information management include formulating information planning, collecting

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Fig. 9.3 Enterprise information management architecture

information, processing information, storing information, maintaining information, and outputting information. The construction of informatization for IC enterprises refers to the process in which enterprises continuously improve the efficiency and level of production, operation, management, and decision-making by using a series of modern technologies, such as computer technology and network technology, through the development and utilization of information resources, so as to improve the economic benefits and competitiveness of enterprises. As shown in Fig. 9.3, the information management structure of chip manufacturing enterprises mainly includes four systems that are management information technology, manufacturing information technology, information technology service, and information security.

The Management IT System The functions of management information technology system in enterprises mainly include administration management, business management, customer relationship management, accounting system management, planning system management, procurement system management, data application integration, and so on.

The Manufacturing IT System Manufacturing information technology system mainly refers to the automatic management system of production chain, including the manufacturing execution system, the equipment automatic control system, and the engineering data analysis system. The manufacturing process of integrated circuit chip is many and complicated. Dozens or even hundreds of products run on the production line every day. A large amount of

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data will be generated in the manufacturing process, including the data reflecting the state of the production equipment, the data reflecting the parameters of product performance, and the data reflecting the yield. At the same time, due to the particularity of semiconductor chip production, the production management of the whole factory is not only responsible for the automation control of the whole production process, but also responsible for the automation control of each equipment and its connection with the manufacturing execution system. In addition, a large number of regular reports should be provided to management and engineers to monitor the production line. Therefore, this makes the whole factory production management system face with real-time, accuracy, stability, high automation, and other requirements. (a) The Manufacturing Execution System (MES) is mainly responsible for manufacturing system architecture design, project management, development, and maintenance, to achieve continuous improvement of production efficiency and quality, assist in production cost control, and support the achievement of key performance indicator (KPI). It mainly involves workflow, real-time dispatch (RTD), simulation-based scheduling (SBS), statistical process control (SPC), plant management system (PMS), equipment constraint system (ECS), and alarm management system (AMS). (b) The equipment automation control system mainly involves the integration of advanced process control (APC), fault detection and classification (FDC), recipe management system (RMS), automatic material handling system (AMHS), equipment automation program (EAP), and manufacturing execution systems (MES). The basic workflow includes: ① To collect, analyze, and confirm user’s requirements for the equipment automation system ② To analyze, inspect, and verify the characteristics and functions of the equipment ③ To perform the program development, testing, and user interface design of the equipment automation system ④ To conduct online testing of equipment automation systems and equipment ⑤ To deploy the equipment automation system on the associated equipment (c) The engineering data analysis system provides professional and efficient reliability system solutions for the plant process integration department, manufacturing department, and quality control reliability department. Meanwhile, this system provides timely and reliable system support and services for customer’s production schedules and process monitoring yield data requirements, as well as provides professional and reliable data support for product shipment and quality analysis.

The IT Service System The information technology (IT) service system mainly provides efficient, safe, and stable office information system for enterprise users by integrating and improving internal resources according to the business development requirements

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of the company. Furthermore, the IT service system will provide 24 h a day (7D/24 h) hardware and software services for enterprise users and production systems to ensure timely, rapid, and efficient quality of service. Main missions are described below: ① To maintain the daily operation of the database and deal with the related faults of the database to ensure the normal operation of each system and ensure the reliability of the system operation ② To maintain the daily operation of the system platform, the database, backup systems, and troubleshoot the related software and hardware failures of IT systems to ensure the normal operation of each system and improve the reliability of the system operation ③ To plan, supervise, and control the infrastructure of data voice communication services so as to ensure the security, efficiency, and stability of data voice communication services ④ To monitor, maintain, troubleshoot, back up, and restore the network and communication systems to ensure high availability of the network systems ⑤ To analyze and optimize network and communication systems to ensure the good performance of systems

Information Security Systems Information security system (ISS) mainly involves the design, development, and maintenance of information security system architecture. There are two key points: one is to guard against external invasion, such as viruses, hackers, and malicious software, so as to prevent from internal communication system and production management system paralysis. Second, to prevent internal leakage of semiconductor enterprises’ production processes, production recipes, production test data, etc. Security operations are required; and only authorized personnel can carry out relevant operations.

High Output Management at Intel Dr. Andrew Grove is one of the founders of Intel. As the CEO from 1987 to 1997, he increased the company’s market value from $4 billion to nearly $200 billion with 64,000 employees. In other words, he was in the big leagues of Intel Cooperation. He is considered one of the best CEOs in Silicon Valley. Of all the management books he had read over the years, his favorite is The Practice of Management, written in 1954 by Peter Drucker, the legendary Master of Management Theory [5]. As Intel was founded, organized, and managed, Dr. Grove found that all Intel employees “produced” in some sense – some made chips, others prepared bills, and still others created software designs or advertising documents. He also found that when we approached any work done at Intel with this basic understanding in mind, the principles and discipline of production gave us a

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systematic way to manage, just as the language and concepts of finance created a universal approach to evaluate and manage investments. Based on his 20 years of management work in semiconductor industry, Dr. Grove introduced Intel’s management methods in his famous book High Output Management [6]. The most important sentence in his book is that the output of a manager is the output of the organizational units under his supervision or influence [7]. The high output management consists of three core concepts.

Three Core Concepts of “High Output Management at Intel” 1. You can apply the principles and discipline of IC manufacturing to management. 2. Intel’s work is done by teams, not individuals. 3. Teams only perform well when they elicit the best performance from their members.

Managerial Leverage As a manager, your output is equal to the output of your organization plus the output of neighboring organizations you influence. Output can be positively or negatively affected through one or more of the five management activities: 1. Information-gathering: Reading reports, customer complaints, or memos and talking to people inside and outside the organization. This is where all other management work is based and where you should spend the most of your time. 2. Information-giving: Transferring knowledge to members of your team and groups you influence. In addition to facts, you must communicate objectives, priorities, and preferences. This is extremely important because subordinates need the context to know how to make their own decisions. 3. Decision-making: Sometimes, you’ll make a decision. Prefer to participate in decision-making by providing input, promoting better choices, reviewing decisions, and providing feedback. Decision-making comes in two forms: proactive decision-making (identifying a set of activities) and response to developing problems, which may be technical or may involve people. 4. Nudging: You should not always provide instruction but push people in a preferred direction of action. 5. Role modeling: You are a role model for your organization, your subordinates, your peers, and even your supervisors. All these activities can improve output, but you need to spend your time where the leverage is the greatest. For some, this is in large groups. For others, one-on-one is the best in a quieter, more intellectual environment.

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Increasing Managerial Output For every activity you perform, the output of your organization should increase by a certain degree. The extent to which it increases is determined by leverage. Leverage is a measure of the output generated by a given activity. The higher the leverage, the more output a given activity produces. But not all activities raise output and doing more may often reduce output. That is why the key to raising output lies in increasing leverage, not economic activity. In summary, you can increase management efficiency in three ways: 1. By doing things faster 2. By improving the leverage of existing activities 3. By shifting the activity portfolio from low leverage to high leverage High-leverage activities include: • To affect many people • To change a person’s activity or behavior due to a brief interaction over a long period of time • To influence the work of a large team by providing critical information

Concentrating on High-Leverage Activities and Ignoring the Rest Delegating as Leverage When you delegate tasks, you are still responsible for getting them done. Supervising delegated tasks is the only practical way to ensure this. And it is easier to monitor what you know, so if you have a choice, delegate what you know best. As with any production flow, it is monitored at lowest-value stage. Furthermore, it is better to review rough drafts, not final reports. The second principle we have borrowed from IC production is variable inspection. Different sampling rates are applied to different subordinates. How often you check should be based on your subordinate’s maturity relative to the task, not what you think they can do in general. As the mission-related maturity of your subordinate increases, you will monitor less often. Finally, enter details randomly. To check everything is like stopping the product line and check for faults. Remember, always choose in-process testing, not stopproduction testing. Production Principles for Time Management As a manager, most of your time is focused on the allocation of resources: manpower, money, and capital. But the most important resource you can allocate is your own time. Your time is your only truly limited resource. Improving the way you spend your time is the most important thing you can do to make yourself more productive.

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You can use production principles to better manage your time: (a) Identify the limiting step: Determine what is immovable and manipulate it with more flexible activities. (b) Batch similar tasks: Everything requires some mental preparation. Effective work relies on grouping related activities. (c) Build forecasts: Most of your work is prediction-based, and the medium is your calendar. Most people use the calendar as a place to receive orders. You should use it as a production planning tool. Schedule non-time pressing tasks between a limiting number of steps each day. Just as factory managers refuse to take on extra work when the factory is at capacity, you should also refuse to take on tasks that overload your system. (d) Say no earlier: Stop working before things get more expensive. (e) Allow slack in your schedule: One distraction should not ruin your whole day. (f) Keep the original list: In the form of projects that do not need to be completed now but can improve your team’s productivity in the long run. This also prevents you from interfering in the work of your subordinates. (g) Standardization: At the same time continue to think critically about what you do and the methods you use.

Meetings: The Medium of Management Meetings are just a medium for management. You need to choose the most influential medium to achieve your goals. Meetings fall into two categories: Category 1: Process-oriented. These meetings are held regularly to facilitate knowledge sharing and information exchange. Category 2: Mission-oriented. These special meetings aim to resolve specific issues by making decisions.

Category 1: Process-Oriented Meetings The goal of regular process-oriented meetings is to improve efficiency. Participants should know how the meeting will be conducted, what important issues will be discussed, and what the goals of the meeting will be. This ensures that the meeting has a minimal impact on output. There are three types of processoriented meetings: 1. One-on-one: Meet with you and report back directly. 2. Staff meetings: Meetings with you and all your direct subordinates. 3. Operational reviews: You can meet people there that you do not usually see. Operational reviews should include formal presentations in which managers describe their work to other managers who are not directly responsible, as well as colleagues in other parts of the company.

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One-on-one: At Intel, one-on-one is a meeting between you and your direct subordinates. It is the primary way to maintain and deepen your relationship. They can be incredible high impact, as the amount of time you spend together can affect the subordinate’s work for weeks. The main purpose of one-to-one is mutual teaching and information exchange. You pass on your skills, know-how, and problem-solving advice to your team members, while they provide information about what they are doing and what they care about. One-on-one arrangements are based on the job- or task-related maturity of each subordinate. Always meet one-on-one (once a week) with those who are less experienced in the given situation, and reduce the number of meetings to, say, once a month for experienced veterans. You should reserve at least an hour for the meeting. Anything meeting less an hour tends to limit people to simple problems that can be solved quickly. The key thing to understand is that one-on-one meetings are reporting meetings. They should set the tone and agenda. This increases your leverage because you do not have to plan for every direct subordinate. It is also important because it forces your subordinates to think ahead what they want to talk about. Meetings usually begin by reporting on management metrics, such as order rates, production output, or project status. Watch for signs of trouble. You should also cover anything important that has happened since the last meeting: recruitment issues, staffing issues, organizational issues, and new initiatives. The criterion for inclusion is whether the issue is bothering your subordinates. Your role is to learn and mentor. When they stop talking about a topic, ask another question until you feel you have got to the root of the problem. You should all have a copy of the agenda and take notes. Note-taking promotes active listening and ensures that the action requested by either party is not lost. Consider using a “hold” file where you can accumulate essential but not urgent issues for future discussion. Encourage heart-to-heart conversations where possible. One-on-one is a great place to tackle subtle issues at work. Scheduling regular oneon-one interviews is a good practice. Set the next task to the end of current task so that other tasks can be easily explained and cancelled. Staff meetings: Staff meetings include you and your team members, and allow for interaction between colleagues, as they are in an ideal place for decision-making. Anything that affects more than two people is fair game. If something deteriorates into a conversation between two people, end it and move on to something that affects more people. It is recommended that two people make separate appointments to discuss the meeting. Staff meetings should be relatively compact, with an agenda prepared in advance so that everyone has a chance to prepare. You should also include irregular times so that people can ask whatever questions they want. If necessary, matters raised at irregular time can become part of the agenda for future meetings. Your role is to be the leader, observer, facilitator, questioner, and decision-maker when necessary. But ideally, you just keep things on track while your team works issues out.

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Operation reviews: Operation reviews are the interactive media for those who do not have the opportunity to meet. They allow employees at different organizational levels to teach and learn from each other. Operation reviews involve four groups: 1. Organizing managers: They help speakers decide what issues and details to present, book meetings, and are timekeepers. 2. Review managers: The review manager is usually a senior management person. They ask questions, offer opinions, and are role models for junior managers in the room. 3. The presenters: The presenter spends 4 min for each slide presentation and discussion, using visual aids where possible. 4. The audience: Audience participation is the key, so they should ask questions and make comments.

Category 2: Mission-Oriented Meetings Mission-oriented meetings are designed to produce concrete outputs, such as decisions. The key to their success is the chairperson, who has the biggest stake in the outcome. Mission-oriented meetings are held for a specific purpose. If you call the meeting, you are responsible for the logistics, arranging the agenda, and writing the minutes. Once the meeting is over, you must share the minutes quickly before the participants forget what happened. They should be as clear and specific as possible, telling the reader what was decided, who did it, and when. You need to get attendees to finish the minutes as quickly, so they don’t forget what happened. In practice, 80% of problems should be solved in daily meetings. Ad-hoc meetings are needed to deal with the rest. A special session is needed to deal with the remaining issues. If you spend more than 25% of your time in impromptu meetings, that is a sign of poor organization.

Decision-Making Participation in the decision-making process is an essential part of management. Traditionally, the chain of command has been precisely defined, and a person’s ability to make decisions is determined by his position on the organizational chart. Today, businesses deal mainly with information and technology. This can lead to a large gap between one person’s power based on position and another person’s power based on knowledge. Increasingly, people at the top of companies are not suited to making decisions. Subordinates usually have a better idea of the right solution. They are closer to the problem, immersed in it every day. The faster the business changes, the greater the divergence between knowledge and position power will be. As a manager, your job is to make sure the best decisions are made, not to make them alone. The ideal decision-making processes: The ideal decision-making process begins with free discussion and open debates of all perspectives and aspects of the

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issue. The greater the disagreement, the more important it is to have free discussion. When things get heated, people tend to hang back and wait for the possible outcome. Once they know, they support the idea and avoid being associated with a losing position. All these outcomes are bad decisions because knowledgeable people reserve their opinions to themselves and whatever decisions are made are based on potentially incomplete information and insights. A good way to avoid this is to have the most junior person state their opinion first. The next step is to make a clear decision. Again, the greater the disagreement, the more important this step is. You need to communicate your decision clearly and make sure everyone understands it. Once a decision is made, everyone must be on board. Not everyone has to agree that it is the right decision, as long as they commit to supporting it. The bottom line is, disagree but a commitment to support. This process may seem simple, but it is more acceptable in theory than in practice. It is hard to express your viewpoints forcefully and make unpleasant decisions, and even against groups. But it pays to make the best decision. When decisions need to be made, the senior people who have been guiding, mentoring, and driving the team must make decisions. If the ideal decision-making process has been followed, the decision-maker has heard all points of view, facts, opinions, and judgments and has the information needed to make the decision. Like all other management activities, focus on output which in this case is the decisionmaking.

Management by Objectives and Key Results (OKRs) Finally, we should mention Management by Objectives and Key results (OKRs) system, which was invented by Intel management team and widely used by Silicon Valley’s top technology companies [2–4]. At Intel, it is called Intel Management by Objectives (IMBO). Once the requirements are defined and the plan is completed, you can use management by objectives and key results (OKRs). The idea behind OKRs is simple: if you don’t know where you’re going, you are not going to get there. To use OKRs successfully, you need to answer two questions: 1. Where do I want to go? The answers provide your objective. 2. How will I know if I get there? This gives you your key results. The purpose of OKRs is to provide feedback related to the task at hand, telling you how you are doing and whether adjustments need to be made. In order for feedback to be effective, you need to receive it as soon as possible. Therefore, the OKRs setup time should be relatively short. If you plan for a year, you should set a quarterly or even monthly OKRs. Minimize the number of goals. If you focus on everything, you may focus on nothing. A few carefully selected OKRs can make the system work.

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References 1. IDM, https://semiengineering.com/knowledge_centers/manufacturing/integrated-device-manu facturer-idm/. Accessed 23 May 2023 2. I. Cutress, Intel’s New IDM 2.0 Strategy. 23 Mar. 2021. https://www.anandtech.com/show/ 16573/intels-new-strategy-20b-for-two-fabs-meteor-lake-7nm-tiles-new-foundry-services-ibmcollaboration-return-of-idf. Accessed 23 May 2023 3. OSAT: Top 10 OSAT Companies in World, https://www.marketresearchreports.com/blog/2019/ 04/24/top-10-osat-companies-world. Accessed 23 May 2023 4. EDA: List of EDA companies, https://en.wikipedia.org/wiki/List_of_EDA_companies. Accessed 23 May 2023 5. P.F. Drucker, The Practice of Management, Reissue edn. (Harper Business, 2006). ISBN-10: 0060878975, ISBN-13: 978-0060878979 6. S. Andrew, Grove, High Output Management (Vintage Books, A Division of Random House, Inc., New York, 1995) 7. J.Z. Xie, C. Damin, The Big Bang of Chip, Chinese edn. (Shanghai Publishing Group of Science and Technology, 2018). ISBN-10: 7547840760, ISBN-13: 978-7547840764

Talent Cultivation

10

Ke Li, Yong-Wen Wang, Yumei Zhou, and Chun-Zhang Chen

Contents Development of Modern Science Education . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Training of IC Talents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Talent Needs of Semiconductor Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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The essence of competition in comprehensive national strength is the competition in integrated circuit (IC) talents. At present, the rapid development of China’s IC industry is in urgent need of a large number of IC professionals and specialists. Since 2000, China has published a series of policies to strengthen the effort in training IC talents or professionals, and to promote the development of microelectronics discipline. Around the strategic development and talent demand of the IC industry, the talent training in the IC industry is characterized by the combination of the national policy guidance and the market mechanism. Keywords

IC talents · IC professionals · Training · Policy guidance · Market mechanism

K. Li (*) Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China e-mail: [email protected] Y.-W. Wang Institute of Microelectronics, Peking University, Beijing, China Y. Zhou Institute of Microelectronics, Chinese Academy of Science, Beijing, China C.-Z. Chen Peng Cheng Lab, Shenzhen, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_10

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Development of Modern Science Education The essence of competition in comprehensive national strength is the competition for talents. Hu Yuan, a scholar of the Song Dynasty in China, wrote in his Songzi County Study Notes that “The governance of the world depends on talents, the cultivation of talents depends on education, and the school is the foundation of education.” The reason why China failed to keep up with the pace of the first and second industrial revolutions is mostly due to a lack of science education. From 1776 when James Watt made the first practical steam engine to 1906 when radio broadcasting was implemented, the period of 130 years witnessed the vigorous development of natural science and technological inventions, and the transition of human society from agricultural society to machine society and further to electric society. At the same time, the Qing Dynasty of China gradually declined from strong to weak. In 130 years, a wave of advancements of natural sciences and technologies was emerged, but China’s performance was lackluster in this wave. The suite of Confucianism Four Books and Five Classics was still regarded as the supreme principle and guidance of the government rulers, while the concepts of “studying the science of things” that could increase social wealth, enhance the efficiency of production, and improve people’s lives were disdained. During the 130 years in China, when those scholars who planned to go to Beijing to take the examinations were still reading at night under candlelight, but western electric power had already lit up people’s lives. While Chinese soldiers and local warriors still opened the way for officials wearing feathers in sedan chairs, European cars and airplanes had already become the new favorite means of transport. When the Chinese rich flaunted their wealth in silks and satins, synthetic fabrics and dyes have made their way into history. While military messages were still being sent by horses in the Qing Dynasty of China, the transatlantic telegraph was already actively used in the West. These big differences in concept and social life are the main cause of China’s weak national situation in the past centuries. Only education can change the past decadent situation. University education has nurtured pioneers in various fields for the Renaissance and Industrial Revolution. Some milestones are described below: 1088: The University of Bologna was established in Italy. It was declared the “Mother of the University” (Alma Mater Studiorum) in the “European University Charter” by 430 universities in Europe. Three masters of the Renaissance: Leonardo da Vince, Michelangelo (Buonarroti), and Raphael (Raffaello Sanzio da Urbino), scientist Galileo Galilei, and astronomer Nicolaus Copernicus all studied at the University of Bologna. 1209: The University of Cambridge was founded. Among the well-known alumni included scientists Isaac Newton, Charles Darwin, Francis Bacon, James Clerk Maxwell, Ernest Rutherford, and Stephen Hawking, economist John Maynard Keynes, and philosopher Bertrand Russell. 1257: University of Paris (Université de Paris) was founded. Among the well-known alumni were physicists Pierre Curie, Madam Marie Curie, and Louis de Broglie.

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1472: The University of Munich (Ludwig-Maximilians-Universität München) was founded. Among the famous alumni included physics masters Wilhelm Conrad Roentgen, Wilhelm Wien, Wolfgang Pauli, Max Planck, Heinrich Rudolf Hertz, and Werner Karl Heisenberg, chemists Adolf von Bayer, and Peter Debye. 1724: St. Petersburg University (Saint-Petersburg State University) was established. Among the well-known alumni included chemist Dmitri Mendeleev, radio inventor Alexander Popov, biologist Ivan Pavlov, writers Nikolai Gogol, Ivan Turgenev, and Nikolai Chernyshevsky. Both Vladimir Lenin and Vladimir Putin studied at St. Petersburg University. 1734: Göttingen University (Georg-August-University of Göttingen) was established. Among the well-known alumni were mathematicians Carl Friedrich Gauss (Gauß) and Bernhard Riemann, physicist J. Robert Oppenheimer, and Enrico Fermi. The famous Chinese students were Zhu De, Ji Xianlin, and Ganchang Wang. 1740: The University of Pennsylvania was founded. Among the well-known Chinese alumni were architect Phyllis Lin (a.k.a. Lin Huiyin) and semiconductor material expert Lin Lanying. 1754: Columbia University was established. Among the well-known Chinese alumni included physicists Tsung-Dao Lee (Li Zhengdao in pinyin) and Wu Chien-Shiung (Wu Jianxiong in pinyin), poet Xu Zhimo, scholar Wen Yiduo, educator Tao Xingzhi, philosopher Feng Youlan, Peking University former president Jiang Menglin, and Hu Shi, chemist Hou Debang, and Tang Aoqing. 1810: Humboldt University of Berlin (Humboldt-Universität zu Berlin) was established. Among the well-known alumni included physics masters Gabriel Lippmann, Wernher von Braun, Albert Einstein, Erwin Schrödinger, and Max Born (teacher of Huang Kun), mathematics masters John von Neumann, philosopher Georg Wilhelm Friedrich Hegel, Ludwig Feuerbach, and poet Heinrich Heine. Karl Marx and Friedrich Engels studied at Humboldt University. Among the famous Chinese students at Humboldt University included Zhou Enlai, physicist Wang Ganchang, geophysicist Zhao Jiuzhang, and historian Fu Sinian. 1826: University College London (UCL) was established. Among the well-known alumni were telephone inventor Alexander Graham Bell, vacuum tube inventor John Ambrose Fleming, fiber inventor Charles Kuen Kao (Gao Kun in pinyin), and former dean of the Chinese Academy of Sciences Chia-Si Lu (Lu Jiaxi in pinyin). 1861: The Massachusetts Institute of Technology (MIT) was established. Among the well-known alumni included physicist Samuel Chad-chung Ting (Ding Zhaozhong in pinyin), former UN Secretary-General Kofi Annan, scientist Qian Xuesen (also spelt as Tsien Hsue-shen), architect Pei Ieoh Ming (I. M. Pei), semiconductor physicist Xie Xide, founder of IC foundry model Zhang Zhongmou (Morries Zhang), and electronics scientist Ge Shouren. 1868: The University of California, Berkeley (UCB), was established. Among the well-known alumni were historian Jian Bozan, founder of Moore’s Law Gordon Moore, and mathematics master Cheng-sheng Chen. 1895: Beiyang University (predecessor of Tianjin University) was established.

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1898: Peking University, China’s first national multi-disciplinary comprehensive university, was established. 1911: Tsinghua University was founded by using Gengzi indemnity (Boxer indemnity). From the University of Bologna (in 1088) to Beiyang University (in 1895), 8 centuries (807 years) passed. From 1609, when Galileo, the pioneer of experimental physics, observed celestial bodies through a telescope and denied the “Geocentric theory,” to 1905, when the Qing Dynasty abolished the imperial examination system, China abandoned “Science” for nearly 300 years. The backwardness of China’s science leads to its economic decline, which in turn leads to military weakness. Then the fate of being bullied and slaughtered is inevitable.

Training of IC Talents Around the strategic development and talent demand of the IC industry, the talent training in the IC industry is characterized by the combination of national policy guidance and market mechanism. Since 2000, the Ministry of Science and Technology has approved the establishment of eight national IC design industrialization bases in Beijing, Shanghai, Shenzhen, Wuxi, Guangzhou, Xi’an, Chengdu, Jinan, and other regions with certain advantages in scientific research, education, industry, and talents. Through years of development, each base has established a certain basic IC design technology service platform, in addition to carrying out technical services, but also carry out personnel training and professional technology training services to radiate IC enterprises in each base area. Under the guidance of national policies, in order to implement the requirements of “Running the National International Training Base for Software and Integrated Circuit Talents” put forward in “Several Policies for Further Encouraging the Development of Software and Integrated Circuit Industry, the State Administration of Foreign Experts Affairs has entrusted China Foundation for International Exchange of Talents to set up” “National International Training Base for IC Talents” in Xiamen, Dalian, Beijing, Fuzhou and Shanghai, and “National International Training Center for IC Teachers” in Hangzhou. According to the needs of the base, foreign experts will be invited to work in China, personnel will be trained abroad, foreign intellectual resources such as advanced technology, scientific research achievements, and knowledge systems will be introduced, and international, compound, practical, and innovative personnel training will be carried out. In order to implement the “Outline for promoting the Development of the National IC Industry,” the Ministry of Industry and Information Technology has also organized and implemented the “Software and IC Talent Training Program” and set up the national IC talent Training platform. Through the cooperation with

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Interuniversity Microelectronics Center (IMEC) at Belgian and other institutions, the ministry has carried out comprehensive technical training in the field of IC for “senior management training”, “engineer training”, “university teacher training”, and “doctoral student training”. At the same time, the strong market demand for talents in the IC industry also gave birth to a number of market-oriented IC training institutions, which provide high-skilled personnel and social training for IC design, manufacturing, packaging, and other fields. Domestic manufacturing process R&D centers and packaging process R&D centers also open platforms to provide practical training programs for IC enterprises, universities, and research institutes, and to carry out process technology training and IC packaging training. With the rise of Internet education, new formats for online training have emerged in the IC industry one after another.

Talent Needs of Semiconductor Industry Semiconductor and/or integrated circuit industry is typically divided into six major areas or sectors (see Fig. 10.1). These sectors may include (1) IC and IP design, (2) IC manufacturing, (3) packaging, board design (PCB), and testing (OSAT), (4) EDA methodology, (5) semiconductor equipment, and (6) semiconductor materials. This short discussion covers major topics related to the first three sectors, together with requirements of technical background and engineering knowledge involved in these sectors. Technical, engineering, and textbooks are collected and listed in the reference at the end of this chapter. Due to the nature of variety of technologies and engineering processing involved, the talent development and management in these sectors vary. Skilled engineers and

Fig. 10.1 Semiconductor/IC industry chain

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professional talent demands are changing labor markets. Well-trained personnel in STEM (science, technology, engineering, and mathematics) subjects are obvious and essential in each of these sectors; trainings in some other subjects may be hidden or cross-over. Overall, very few talents can technically cover or explain thoroughly the detailed demands in the whole map presented in Fig. 10.1. Qualification of talents for design, manufacturing, and packaging-test are respectively discussed. In the sector of IC/IP design, including System-on-Chip (SoC) design or Application-Specific Integrated Circuits (ASIC) design, talents of the following major three types of design areas should be highlighted. (A) Custom IC (CIC) design that includes analog [1–4], RF [5], analog-mixed signal/AMS [6] designs, circuit simulation [7], and layout design [8, 9]. The research of device modeling and study of standard cell characterization are also falling into this area. (B) Digital IC (DIC) design [10–18] that includes register transfer level (RTL) design, logic synthesis, and physical implementation [19, 20]. Achieving good performance, low power, and smaller area of the DIC are ultimate goals in this area. (C) Electronic System-level Design (ESD) which covers architectural configuration [21–24], hardware-software codesign (HSC), high-level synthesis (HLS), RTL or logic design [25–28], IP design and SoC and ASIC integration [29–32], and system verification [33–35]. An additional detail related to this sector is found in Sect. 2 (Classification and Application of IC Products) and Sect. 5 (Integrated Circuit Design). In the sector of manufacturing foundry operation, or IC fabrication (FAB), the demands of talents are from understanding of solid physics of microelectronic devices; manufacturing of these CMOS based technology [36–40], developing nanometer process techniques, and modern fabrication operations [41–43]. An additional detail related to this sector is found in Sect. 4 (Integrated Circuit Production Lines) and Sect. 6 (IC Manufacturing and Management). In the sector of packaging, printed circuit board (PCB) design, and test, the demands of talents are to deal with IC products, to accomplish the assembly of the products, and to assure the quality of the components to be used in the final electronic devices or equipment. The demands of talents can be simply classified into PBT areas, i.e., packaging [44, 45], board [46–48], and test [49, 50]. An additional detail related to this sector is found in Sect. 7 (Packaging and Testing of IC Products). For the sectors of EDA, IC Equipment, and Integrated Circuits Materials in Fig. 10.1, the requirements of talent expertise vary from one field to another; each of these sectors involves variety of specialties of STEM subjects. For example, EDA for IC [51, 52] needs skills of system architect, extensive SW programming, and HW partition. Additional information can be found in Sect. 8 (IC Equipment) and Sect. 9 (Integrated Circuits Materials). The oldest university and in continuous operation, University of Bologna [53], in the world, for example, delivers students STEM courses over a thousand years; on the other hand, complex as it is, training classes for semiconductor talents need fixed long-term classes, mid-term courses, and many short-term classes too.

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References 1. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd edn. (McGraw-Hill Education, New York, USA, 2017) 2. P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, 2nd edn. (Oxford University Press, Oxford, England, 2002) 3. J.W. Nilsson, S.A. Riedel, Introductory Circuits for Electrical and Computer Engineering (Prentice Hall, New Jersey, USA, 2001) 4. R.E. Best, Phase-Locked Loops: Design, Simulation, and Applications, 6th edn. (McGraw Hill, New York, USA, 2007) 5. R. Ludwig, P. Bretchko, RF Circuit Design: Theory and Applications (Prentice Hall, New Jersey, USA, 2000) 6. J. Chen, M. Henrie, M.F. Mar, M. Nizic, Mixed-Signal Methodology Guide (lulu.com, North Carolina, USA, 2012) 7. J. Baker, H.W. Li, D.E. Boyce, CMOS: Circuit Design, Layout and Simulation (Wiley, New Jersey, USA, 1998) 8. D. Clein, CMOS IC Layout (Elsevier Science, Amsterdam, Netherlands, 2000) 9. A. Hastings, The Art of Analog Layout (Pearson Education, London, England, 2001) 10. N.H.E. Weste, K. Eshraghian, Principles of CMOS VLSI Design, 2nd edn. (Addison-Wesley, Boston, USA, 1994) 11. J.F. Wakerly, Digital Design, Principles and Practices, 5th edn. (Prentice-Hall, New Jersey, USA, 2018) 12. J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edn. (Prentice Hall, New Jersey, USA, 2002) 13. M.J.S. Smith, Application-Specific Integrated Circuits (Addison Wesley Longman, Boston, USA, 1997) 14. K. Martin, Digital Integrated Circuit Design, The Oxford Series in Electrical and Computer Engineering (Oxford Univ. Press, Oxford, England, 2001) 15. M.M. Mano, Digital Design, 6th edn. (Prentice Hall, New Jersey, USA, 2018) 16. S.M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 4th edn. (McGraw-Hill, New York, USA, 2014) 17. D.A. Hodges, H.G. Jackson, R.A. Salah, Analysis and Design of Digital Integrated Circuits: In Deep Submicron Technologies, 3rd edn. (McGraw-Hill, New York, USA, 2003) 18. N.H.E. Weste, D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th edn. (Addison-Wesley, Boston, USA, 2010) 19. C.-Z. Chen, X. Ai, G.X. Wang, Physical Implementation of Digital IC Design, Chinese Book Series 2 of 5 (Science Press, Beijing, 2008). ISBN 978-7-03-022031-8 20. A. Kahng, J. Lienig, I.L. Markov, J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, 2nd edn. (Springer, Berlin, Germany, 2022) 21. J. Hennessy, D. Patterson, Computer Architecture: A Quantitative Approach, 6th edn. (Morgan Kaufmann, Massachusetts, USA, 2017) 22. D. Patterson, J. Hennessy, Computer Organization and Design MIPS Edition: The Hardware/ Software Interface, 6th edn. (Morgan Kaufmann, Massachusetts, USA, 2020) 23. S. Harris, D. Harris, Digital Design and Computer Architecture: ARM Edition (Morgan Kaufmann, Massachusetts, USA, 2015) 24. D. Patterson, A. Waterman, The RISC-V Reader (Strawberry Canyon LLC, 2018) 25. P. Coussy, A. Morawiec, High-Level Synthesis: From Algorithm to Digital Circuit (Springer, Berlin, Germany, 2008) 26. C.H. Chin, Principles of Verilog Digital Design (CRC Press, Florida, USA, 2022) 27. P. Samir, Verilog HDL: A Guide to Digital Design and Synthesis (Pearson, London, England, 2003) 28. M.M. Mano, M. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and System Verilog, 6th edn. (Pearson, London, England, 2017)

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29. H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, L. Todd, Surving the SoC Design (Kluwer Academic, Amsterdam, Netherlands, 1999) 30. N. Horspool, P. Gorman, The ASIC Handbook (Prentice Hall, New Jersey, USA, 2001) 31. W. Wolf, Modern VLSI Design: IP-Based Design, 4th edn. (Prentice Hall, New Jersey, USA, 2008) 32. P. Rashinkar, P. Paterson, L. Seingh, Syetem-on-a-Chip Verification, Methodology and Techniques (Kluwer Academic, Amsterdam, Netherlands, 2001) 33. B. Bailey, F. Balarin, TLM-Driven Design and Verification Methodology (Lulu Enterprises, Inc., North Carolina, USA, 2010) 34. S. Rosenberg, K.A. Meade, A practical Guide to Adopting the Universal Verification Methodology (UVM), 2nd edn. (Lulu.com, North Carolina, USA, 2010) 35. P.R. Schaumont, A Practical Introduction to Hardware/Software Codesign (Springer, Berlin, Germany, 2010) 36. J.D. Plummer, M.D. Deal, P.B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling (Pearson, London, England, 2000) 37. R.C. Jaeger, Introduction to Microelectronic Fabrication, 2nd edn. (Pearson, London, England, 2001) 38. R.M. Warner, B.L. Grung, Semiconductor-Device Electronics (Oxford University Press, Oxford, England, 1995) 39. S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, 2nd edn. (Oxford University Press, Oxford, England, 2001) 40. R. Doering, Y. Nishi, Handbook of Semiconductor Manufacturing Technology, 2nd edn. (CRC Press, Florida, USA, 2007) 41. R. Zhang et al.: Manufacturing Process of Nanometer Integrated Circuits, 2nd Ed. (Tsinghua Univ. Press 2017. in Chinese ISBN 978-7302452331) 42. H. Geng, Semiconductor Manufacturing Handbook, 2nd edn. (McGraw Hill, New York, USA, 2017) 43. Y. Lian, Semiconductor Microchips and Fabrication: A Practical Guide to Theory and Manufacturing (Wiley-IEEE Press, New Jersey, USA, 2022) 44. B. Wu, A. Kumar, S. Ramaswami, 3D IC Stacking Technology (McGraw Hill, New York, USA, 2011) 45. M.Z. Xu, Advanced Microelectronic 3D-IC Packaging, 4th edn. (Wunan Culture Enterprise, 2023). (in Chinese ISBN 978-957-763-880-9) 46. H. Johnson, M. Graham, High-Speed Digital Design: A Handbook of Black Magic (Pearson Education, London, England, 1993) 47. S. Monk, Make Your Own PCBs with EAGLE: From Schematic Designs to Finished Boards (McGraw Hill, New York, USA, 2014) 48. B.R. Archambeault, J. Drewniak, PCB Design for Real-World EMI Control (Springer, Berlin, Germany, 2002) 49. A.L. Crouch, Design-For-Test (Prectice Hall, New Jersey, USA, 1999) 50. G. Blokdyk, Automatic Test Equipment A Complete Guide (5STARCooks, 2020) 51. L. Lavagno, I.L. Markov, G. Martin, L. Scheffer, Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology, 2nd edn. (CRC Press, Florida, USA, 2016) 52. T.C. Hu, E.S. Kuh, VLSI Circuit Layout: Theory and Design, IEEE Press Selected Reprint Series (IEEE, 1985) 53. University of Bologna, https://en.wikipedia.org/wiki/University_of_Bologna

Section II Classification and Applications of IC Products Shengming Zhou, Chun-Zhang Chen, and Xin-An Wang

Introduction The development of integrated circuits (ICs) is progressing with each passing day. The applications of IC as a core technology in various electronic products are emerging in an endless stream; in a sense, electronic systems relying on ICs today are a verdict that ICs are global needs and secure measure of an enterprise to survive. IC products have become standard judgment of life quality; they serve as an exchange or corporation tools among people. IC products are the critical part of people’s daily life; we cannot live without them. The world is colorful; IC products are comprehensive and complex. Viewing from the manufacturing processes, IC products have developed from discrete devices to integrated system chips; observing from the research and application pathway of ICs, they have walked from military camp to individual household, and to folks of all walking. Then the question now is: How to collect and organize the IC products? What to emphasize of key IC products while not to list every odds and ends? We have tried our best to introduce them, while we invite readers to navigate through 11 chapters in this Section, to find out your admired items. There are three parts in this section. Part one introduces the development and classification of IC products, presented in Chaps. ▶ 11 and ▶ 12. Part two describes the types of IC products based on the design methodology and manufacturing technology, collected in Chaps. ▶ 13, ▶ 14, ▶ 15, ▶ 16, ▶ 17, and ▶ 18. Part three lists various applications of IC products in different occasions, summarized in Chaps. ▶ 19, ▶ 20, and ▶ 21. We wish to appreciate the contributions from 117 writers, 37 reviewers, and members of Chap. ▶ 12 committee; our acknowledgment is extended to the Editorial Committee of the three-volume book, for their patient guidance and careful editing. Though the writers and reviewers come from various industry backgrounds and have divergent work experiences, the common goal achieved here is to offer readers an often referenced desk handbook.

Development and Classification of IC

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Song Zhang, Kaiwei Zhang, and Yutao Huo

Contents Overview of the Development of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Products in the Mainframe Era . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Products in the Era of PC and Internet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Products in the Era of Mobile Phones and Mobile Internet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Products in the Era of Smart Terminals and IoT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classification of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function and Structure of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

An overview is presented to describe the development of IC products at various stages, which include the mainframe, PC and Internet, mobile communication, and Internet-of-Things (IoT) eras. Various types of IC products were developed which closely follow the trends in these eras; the technology and functions of IC products are continuously enhanced. The IC products are thus classified, based on materials, into the Ge-Si process, compound process, and other processes. The functions of IC products can be classified into digital, analog-mixed signals, RF, power devices, and others. Keywords

Mainframe · Personal Computer (PC) · Internet of Things (IoT) · Process · CMOS · SoC

S. Zhang (*) · Y. Huo China Center for Information Industry Development, Beijing, China e-mail: [email protected] K. Zhang Huada Semiconductor Co. Ltd., Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_11

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Overview of the Development of IC Products The development of IC technology and their related products has experienced the Mainframe era, Personal Computer (PC) and Internet era, Mobile Telephony and Mobile Internet era, the Intelligent Terminals (including smartphones), and Internetof-Things (IoT) era.

IC Products in the Mainframe Era The development of IC technology and products originated from the demand for information in national defense and military affairs and were then widely used in such important fields as weaponry and aerospace. Early mainframe computers mainly adopted vacuum tubes that were procured by the national defense department. ENIAC (Electronic Numerical Integrator and Computer), the first generalpurpose computer completed in 1946 which was designed to calculate the ballistic trajectory for the United States Department of Defense, was composed of 17,468 vacuum tubes, with a total weight of 30 t and a floor area of 167 km2 [1]. Then, in 1954 came the supercomputer TRADIC (TRAnsistor DIgital Computer or TRansistorized Airborne DIgital Computer), the size of which shrunk to that of a wardrobe and was composed of 684 transistors and 10,358 diodes. Transistors solved the problems of poor reliability, large power consumption, and large volume of these vacuum tubes (or electronic tubes) and extended the functions of electronic products from pure scientific calculation to data processing, process control, and many other aspects. As a result, transistors replaced electronic tubes quickly and gave rise to an electronic revolution. Announced in April 7, 1964, IBM System/360 (S/360) became the first computer that used an integrated circuit as the integration process improved so that multiple transistors could be installed in a single integrated circuit [2]. As a mainframe, the cost of IBM System/360 was more than 5 billion dollars to develop and was sold at an extremely high price—2.5 million dollars, but thousands sets were ordered within a short period of time and then widely used in the financial and defense systems of the United States.

IC Products in the Era of PC and Internet With R&D personnel constantly improving semiconductor process and design architecture, IC products have become increasingly smaller in size, more integrated functions, and systemized. Fairchild Semiconductor and Texas Instruments have successively introduced commercial ICs, and medium and small-scale ICs manufactured with such processes as resistor-transistor logic (RTL), diode-transistor logic (DTL), emitter coupled logic (ECL), transistor-transistor logic (TTL), MOS, and CMOS came out one after another, symbolizing the inception of the IC era [3]. The Internet was originated from the ARPANET (the Advanced Research Projects Agency Network) of the US army, funded by DARPA (Defence Advanced

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Research Projects Agency) in late 1960s. The NSFNET, established in 1985 (by National Science Foundation, NSF), replaced APARNET, thus, to become the US nationwide backbone networks and open to the public as the Internet in April 1995. Access of the public using personal computers (PCs) to the Internet promoted and accelerated the PC business that boomed the CPU products to new climax one after another. In 1971, Intel introduced the first commercial computer microprocessor—4004, ushering in a new era of micro-programmable computers. In 1981, IBM introduced the commercial PC with Intel microprocessor 8008, marking the emergence of the personal computer (PC) system based on microprocessors. Afterward, Intel successively introduced a multiple of processor chips including Pentium series (1, 2, 3, 4, M), and Core series (Celeron, Core Solo, . . .Core i3, Core i5, Core i7), while adopting “Tick-Tock” strategy to upgrade architecture and process and finally established its dominant role in the desktop processor area. At the same time, Intel cooperated with Microsoft in setting up the “Wintel” alliance or duopoly which defined the PC era and promoted the collaborative development of CPU and operating system in the PC field.

IC Products in the Era of Mobile Phones and Mobile Internet With the vigorous development of mobile communication around 1990, an application processor (AP) suitable for mobile intelligent terminals was invented by simplifying the complex functions of CPU before integrating it with GPU. Furthermore, with the continuous improvement of radio frequency chips and baseband chips, feature phones and smartphones have undergone explosive growth. Taking advantage of low-power consumption of ARM architecture CPUs, ARM formed an alliance with Google who owns Android OS; Apple who owns its own iOS, together with Qualcomm, Samsung, MediaTek, Spreadtrum, and other mobile phone manufacturers, who focused on application processor (AP) and baseband (BB) chip designs, quickly grabbed the mobile Internet market shares. From GSM in the 2G era to WCDMA, CDMA, TD-SCDMA in the 3G era, and then to FDD LTE and TDD LTE in the 4G era, the processing capacity of communication chips has been continuously enhanced. Qualcomm, MediaTek, and Spreadtrum expanded their market volume rapidly through the chips developed based on ARM architecture. As 4G has been used extensively for commercial purpose, 5G communication directed at 2020 and the future has become global R&D hotspot, which puts forward new demands for communication infrastructure and various newborn chips.

IC Products in the Era of Smart Terminals and IoT With the rapid rise of cloud computing, big data, Internet of Things (IoT), and other emerging application fields, the era of the IoT focusing on smart terminals is coming, offering new opportunities for the growth of IC industry [4]. To connect electronic

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equipment and provide related services via mobile Internet, low-power wide-area network (LPWAN) is a demand; the third-generation partnership project (3GPP) aimed at mobile IoT (MIoT) for LPWAN is a new topic; based on RF technology standard, the narrowband IoT (NB-IoT) [4] established in 2016 is still a hot topic. These new schemata have brought in new areas of development in digital ICs, analog ICs, AMS ICs, RF ICs, optoelectronic and MEMS products, and their applications. According to International Technology Roadmap for Semiconductors (ITRS), the development of IC products will be continued in three directions [5]. First, IC products continue developing according to Moore’s Law, namely its feature size keeps shrinking, and classical CMOS devices are replaced by CMOS multi-gate FET, for example, the FinFET and the gate-all-around FET (GAAFET). Secondly, IC products will extend Moore’s Law by innovatively focusing on heterogeneous device system integration which means integrating various components and parts such as passive RF components, power devices, and biosensors into the same chip through three-dimensional packaging or other technologies, so as to improve chip functions and realize higher product value. Third, IC products will transcend Moore’s Law by relying on new principles, new processes, new materials, new devices, and equipment instead of narrowing of device line width. For concurrent innovative technologies, including AI chips for machine learning, quantum computing devices, the third-generation semiconductor material devices and the two-dimensional materials, are stepping on stage to expanding the development of semiconductor technology and IC products.

Classification of IC Products IC products can be divided into computer ICs, consumer ICs, and communication ICs. There are also emerging IoT ICs and automotive ICs according to the market segments they applied to. Of those applications, computer ICs take the greatest market share. However, the market size of computer ICs declined obviously since 2014, and consumer products including smartphones and tablet PC became a new momentum driving the IC market. In 2016, as smartphone market was slow, and the market growth then also slowed down gradually. Instead, IoT, cloud computing, and automotive electronics became the target of market. IDC (Internet Data Center), a market research institution, forecasted that the market volume of the IoT would reach 1.1 trillion by 2023 [6]. According to manufacturing technology, ICs can be classified as Ge-based and Si-based processes, compound materials process, and other process, as shown in Fig. 11.1. Advanced technologies include CMOS (Complementary Metal-OxideSemiconductor Transistor), FinFET (Fin Field-Effect Transistor), and FD-SOI (Fully Depleted Silicon on Insulator). As the feature size of semiconductor components was reduced to less than 20 nm, the traditional CMOS technology begun to be confronted with challenges in many aspects. In such circumstances, Intel first adopted FinFET (they called it 3D Tri-gate) in 2011 using 22 nm technology, and IBM first proposed the FD-SOI technology came out as brand-new solutions.

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Fig. 11.1 Classification of IC products by manufacturing technology

Fig. 11.2 Classification of IC products by functions

According to product function, ICs can be divided into digital ICs, analog-mixed signal (AMS), RF ICs, power devices, optoelectronic devices, sensors/MEMS ICs, etc., as shown in Fig. 11.2. Based on the function, structure, and nature of the

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semiconductor manufacturing processes, sometimes for convenience, people may refer to the digital, memory, logic, and analog/AMS/RF products as the “IC products” while combining discrete devices, optoelectronic, and sensors/MEMS as the “DOS” products.

Function and Structure of ICs The basic units of IC are active transistor devices and passive components such as resistors and capacitors. Analog ICs use the amplification characteristics of transistors to adjust signal amplitude and power, while digital ICs use the switching characteristics of transistors to accomplish information processing and transmission. Most of the early IC used bipolar junction transistor (BJT). As the manufacturing process of complementary metal-oxide-semiconductor (CMOS) became mature, CMOS technology was widely used in IC [7]. Based on the functional and structural features of IC modules, various applications can be fulfilled through system integration of these modules. A simplified IC system suitable for an IoT application is shown in Fig. 11.3, the function and structure of these modules are indicated by their names. The IC system includes a digital sub-system and an AMS sub-system. The digital sub-system applied for digital signal processing, write/read and control processing, can be realized through CPU, memory (e.g., SRAM), and external memory (e.g., NAND Flash), interface (I/F) modules (e.g., timer and USB). AMS sub-system is applied to process RF and analog signals, through RF circuit, analog circuit, and analog-mixed signal (e.g., ADC, DAC, Op-Amp) to carry out these tasks. There are varieties of IC products. The modules in Fig. 11.3 themselves can be listed as independent IC products; different combinations and some of them, of these

Fig. 11.3 A simplified IC system suitable for an IoT application

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modules, can realize new functions and become new products. Towards the early twenty-first century, due to the increased size of the electronic systems, to maintain portability, while increase the performance, higher degree of integration, a new concept of system-on-chip (SoC) [8] was proposed to integrate many single or individual chips or IPs into a single chip. SoC has become a common name today; yet it remains much more complicated, it aggregates at lease CPU, memory, logic module, and analog module; in Fig. 11.3, it demonstrates a relatively simple SoC product.

References 1. ENIAC. https://en.wikipedia.org/wiki/ENIAC. Accessed 12 Feb 2020 2. IBM System/360. https://www.ibm.com/ibm/history/ibm100/us/en/icons/system360/. Accessed 12 Feb 2020 3. Y.Y. Wang, Y.W. Wang, Development Road of China’s IC Industry: A Country from Consumption to Production (Science Press, Beijing, 2008), pp. 148–179. ISBN 9787030216557 4. NarrowBand – Internet of Things (NB-IoT). https://www.gsma.com/iot/narrow-band-internet-ofthings-nb-iot/. Accessed 12 Feb 2020 5. ITRS 2.0. (2015). http://www.itrs2.net/itrs-reports.html. Accessed 12 Feb 2020 6. IoT Ecosystem and Trends. https://www.idc.com/getdoc.jsp?containerId¼IDC_P24793. Accessed 12 Feb 2020 7. IC. https://www.dictionary.com/browse/integrated-circuit. Accessed 12 Feb 2020 8. G. Martin, H. Chang (eds.), Winning the SoC Revolution: Experiences in Real Design (Kluwer Academic, Boston, 2003)

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Xinnan Lin, Mingxia Qiu, Fei Wang, Lenian He, and Jesse Jen-Chung Lou

Contents IC Manufacturing Processes and Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar Junction Transistor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Planar CMOS ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Diffused Metal Oxide Semiconductor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar Complementary Metal Oxide Semiconductor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar Complementary Double-Diffused Metal Oxide Semiconductor ICs . . . . . . . . . . . . . . . . . . Fin Field-Effect Transistor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon-on-Insulator IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gallium Arsenide Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indium Phosphide Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gallium Nitride Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon Carbide Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heterojunction Bipolar Transistor (HBT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System in Package IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro/Nano-Electro-Mechanical System and IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Products of Other Advanced Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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X. Lin (*) Electronic and Computer Engineering, Peking University, Shenzhen, China e-mail: [email protected] M. Qiu College of New Materials and New Energies, Shenzhen Technology University, Shenzhen, China F. Wang School of Microelectronics, Southern University of Science and Technology, Shenzhen, China L. He Zhejiang University, Hangzhou, China J. J.-C. Lou School of Software and Microelectronics, Peking University, Beijing, China Institute of Microelectronics, Peking University, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_12

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Abstract

The invention of the first IC by Jack Kilby in 1958 led to the bipolar junction transistor (BJT) process, while the first planar IC process conceived by Robert Noyce in 1959 evolved into planar CMOS process by C. T. Sah and Frank Wanless in 1963. The planar CMOS process has been the most widely used process to date for IC designs from the early technology node of 10 um in 1971. The combination of BJT and CMOS processes has also brought in several new technologies, such as double-diffused metal oxide semiconductor (DMOS), bipolar CMOS (BiCMOS), and Bipolar-CMOS-DMOS (BCD) processes. In 1998, the FinFET technology, a “3-D transistor” or a non-planar process, had been demonstrated at UC Berkeley. Meanwhile, the SOI technology, being immune to the latch-up issue, was developed to meet radiation-resistant requirement in space applications. These IC technologies together with several technologies based on III-V compound semiconductor materials, including gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), and others, are discussed in this chapter. Keywords

BiCMOS · FinFET · BJT · DMOS · BCD · SOI · GaAs · InP · GaN · SiC · HBT · SiP · MEMS

IC Manufacturing Processes and Products The first Si-based process of integrated circuit (IC) by Jack Kilby at TI in September 1958 would lead to a bipolar junction transistor (BJT) process. In January 1959, the planar IC process was conceived by Robert Noyce then at Fairchild Semiconductor International. In 1963, C. T. Sah and Frank Wanless of Fairchild first reported in a conference paper about CMOS configuration, which was patented in 1967. Thereafter, the planar CMOS process was widely used and well known as it is easier to integrate more devices on a large scale as Noyce initially noted. Meanwhile, MOSFETs have become the mainstream products of modern IC due to their high-input impedance, low-static power consumption, and high density of integration. To achieve faster speed, the bipolar complementary metal oxide semiconductor (BiCMOS) IC has been developed, due to the advantages of both BJT and CMOS. With the continuous shrinking of the mainstream CMOS from a few μm to 0.18 μm and then to 28 nm technology nodes, the device performance continuously improved. However, as the CMOS devices continue to further scale down, their electrical performance becomes more and more difficult to control due to the shortchannel effect (SCE), which results in a series of problems, e.g., the poor sub-threshold characteristics and large leakage current. In order to suppress the short-channel effect effectively, it is necessary to develop a novel device structure with stronger gate control capability. Consequently, the multi-gate field-effect

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transistor (MuGFET) and silicon-on-insulator (SOI) techniques have been proposed and developed successively. The main forms of MuGFET are FinFET and gate-allaround FET (GAAFET). The FinFET has become the main device structure since Intel’s 22 nm node [1], the 14 nm/10 nm/7 nm FinFET processes are widely or increasingly used in applications, e.g., CPU and/or microprocessor unit (MPU), memory, system-on-chip (SoC). At present, the 5 nm FinFET is for a risk production in 2020; R&D on 3 nm and 2 nm GAAFET is underway. In the field of high-frequency devices, the semiconductor compound materials, such as gallium arsenide (GaAs) and indium phosphide (InP), are listed as the second-generation semiconductor materials. With their wide band gap and high carrier mobility, the second-generation semiconductor materials have been used to fabricate high-performance and high-frequency devices, which are widely used in the electronics of high speed and communications. In the 1990s, as the manufacturing technology of semiconductor materials became matured, researchers began to study the third-generation semiconductor materials, such as gallium nitride (GaN), silicon carbide (SiC), and other materials with band gap of more than 3 eV. The third-generation semiconductor materials are very suitable for high-voltage devices with high-voltage resistance due to their strong atomic bonds, high thermal conductivity, and high critical breakdown voltage. At the same time, new ICs with two-dimensional channel materials, such as carbon nanotube (CNT) and graphene, have been developed and expected to become mainstream technologies for next-generation ICs due to their excellent electronical characteristics. At present, the matured CMOS processes are expanding into other research areas including the emerged MEMS/NEMS technology as well as to the integration of other materials such as GaAs and SiC. In the future, they will extend to new IC manufacturing, which is based on two-dimensional (2D) materials like carbon nanotubes, graphene, and black phosphorus. It will find a feasible way toward smaller device sizes and better device performance for microelectronics technology. Using three-dimensional (3D) IC technology combined with micro-sensors, microactuators, micro-mechanical structures, micro-power supplies, and signal processing/control circuits, a variety of micro-devices and systems can be fabricated to fit various application needs.

Bipolar Junction Transistor ICs Bipolar IC is consisted of bipolar junction transistors (BJTs) which are mainly used in multimedia terminals, power amplifier, radio communication, and industrial control. The first BJT was a contact crystal triode; it was invented in 1947 in Bell Labs by Brattain, Bardeen, and Shockley. With further study of the materials and processes, alloyed junction transistor, surface-barrier transistor, graded-base transistor, diffused transistor, and thin-film transistor were developed.

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Fig. 12.1 Schematic diagram of basic structure and current flow of an npn transistor

Figure 12.1 shows a basic structure and current flow of npn-type transistor. It is consisted of two pn junctions and the current is produced by both types of charge carriers (electrons and holes). With respect of npn bipolar junction transistor, the middle region is p-type Base (area), the left region is n++ heavy doped area which mainly supplies electrons as referred to as Emitter, and the right region is the Collector which mainly collects electrons. When apply a small current on the p-type base, a large current will occur between the Emitter and the Collector which is called the current amplification effect of the bipolar transistor. Such characteristics enable the bipolar device widely used in signal amplification, switch circuit, and so on. Using the BiCMOS process, BJTs can be integrated with highspeed CMOS digital logic circuit. To make use of the known temperature and current relation between the Base and Emitter under a positive bias, BJT can be used to form a temperature sensor. According to I-V characteristics between Base and Emitter, BJT can also be used in operational circuit for logarithmic operation. Despite the conventional junction bipolar transistor, there is still heterojunction bipolar transistor (HBT), which performs well in high-frequency signal processing in hundreds GHz; and HBTs are widely used in super-high-speed circuit and radiofrequency (RF) circuit systems. Bipolar junction transistor plays an important role in the modern electronic and electric devices which can be both used as discrete devices and combined in other systems like thyristor and insulated gate bipolar translator (IGBT).

Planar CMOS ICs A planar complementary metal oxide semiconductor (CMOS) field-effect transistor (FET) is used for voltage amplification that is composed of a p-type planar MOS field-effect transistor (pMOSFET) and an n-type MOS field-effect

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transistor (nMOSFET). When the input is at low voltage, the pMOSFET is turned on, the nMOSFET is turned off, and the output is at high voltage; when the input is at high voltage, the nMOSFET is turned on and the pMOSFET is turned off, and the output is at low voltage. Under this working principle, the p-type and n-type MOSFETs are in opposite states for most of the time except during the high- and low-voltage transition of the input signal. The electronic phase of input and output of the planar CMOS is also opposite. This operation mode can greatly reduce the static power consumption of CMOS devices, also with high noise immunity, extremely low-static power consumption, high-input impedance, and good temperature stability. After the advent of planar CMOS, it has become the mainstream technology for designing and manufacturing large-scale ICs, although its fan-out capability is weaker, and its speed is relatively slow as compared with bipolar transistors. A schematic cross-sectional view of a typical planar-enhanced CMOS IC is shown in Fig. 12.2. It uses p-type silicon as the substrate and forms an n-well by locally doping and diffusing on the surface. First, a pMOSFET is fabricated in the n-well; then, an nMOSFET is fabricated on the p-type substrate and finally form the Source (S) region, Drain (D) region, and Gate (G) region. In 1963, C. T. Sha and Frank Wanlass from Fairchild Semiconductor invented CMOS IC [2] in 1967, Wanlass filed US patent 3,356,858. In 1968, the RCA successfully produced the world’s first planar CMOS IC. Thereafter, planar CMOS IC can be continuously scaled down in accordance with Moore’s Law, thereby continuously increasing the integration density of transistors per unit area. In 1971, Intel released the first microprocessor chip 4004 based on planar FET technology, which contained 2250 transistors. In 1985, Intel released the 386-microprocessor based on 1.5-μm technology node. In 2002, Intel introduced a planar CMOS IC at 90 nm node, which adopted the strain technology and high-speed copper (Cu) interconnect technology to improve the overall circuit performance. In 2007, the 45 nm node technology is released by Intel for the planar CMOS IC, with new features of high-κ (or high-k) metal gate (HKMG) for the first time and prompted a new multi-core processor based on this technology.

Fig. 12.2 A schematic cross-sectional view of a typical planar enhanced CMOS IC

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Double-Diffused Metal Oxide Semiconductor ICs Double-diffused metal oxide semiconductor (DMOS) FET is widely used as highvoltage power device. By adding a lightly doped drift region between the source and drain, the DMOS device can sustain most of the voltage across the lightly doped drift region, thereby increasing the breakdown voltage of the device [3]. Based on the structure difference, the DMOS devices can be regarded as two types: lateral double-diffused MOS (LDMOS) and vertical double-diffused MOS (VDMOS). In 1969, Y. Tarui et al. proposed a lateral double-diffusion MOS technique, as shown in Fig. 12.3a, using a secondary diffusion method. This kind of device formed a lateral channel according to the different doping concentration. The lightly doped drift region can guarantee the high breakdown voltage of the device [4]. The different diffusion regions of conventional LDMOS devices are isolated, which reduces unnecessary capacitance effects. Meanwhile, the three electrodes of source (S), drain (D), and gate (G) in the LDMOS device lie on the surface of the chip device, which is suitable for the large-scale production by using traditional semiconductor lithography process although the integration of silicon wafer devices will be slightly lower. In 1979, H.W. Collins et al. proposed a vertical double-diffused MOS structure [5]. As shown in Fig. 12.3b, similar to LDMOS, the VDMOS devices also use double diffusion to form the different regions, though the channel of the lightly doping drift region is vertical. The drain electrode (D) is distributed on the bottom surface of the device, thereby improving the high breakdown voltage of the device and suitable for high-voltage application at harsh environment. The VDMOS vertical structure can reduce integration cost of the chips, due to the drain electrodes on the bottom surface and other electrodes on the upper surface. Compared with common conventional CMOS devices, the DMOS device adds a low-doping drift region, which can improve the high-voltage capability. Since the

Fig. 12.3 DMOS device structure

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LDMOS and VDMOS are significantly different in the direction of the drift channel, they are utilized in different application areas. The LDMOS technique is a relatively mature process and is more compatible with other semiconductor processes, which is easy to integrate with traditional CMOS devices suitable for high-voltage and low switching speed. The VDMOS has been widely used in various consumer electronics and industrial control applications due to its faster switching speed and lower power consumption. At present, the DMOS process is mature and widely used. Several Fabs such as TSMC, GlobalFoundries, Samsung, and SMIC have already achieved mass production of DMOS. DMOS devices are common in a variety of electronic circuits, especially those requiring high voltage and high frequency for applications depending on the operating voltage. For example, under a working voltage of less than 20 V, DMOS is used in mobile phones and digital cameras; at a working voltage between 20 V and 100 V, DMOS can be used in computers, set-top boxes, car audio, motor controllers, and monitors; at a working voltage between 100 V and 800 V, VDMOS is used in TVs, water heaters, washing machines, power adapters; for a working voltage above 800 V, it is the most obvious advantage of VDMOS, such as high-voltage inverters, generator sets, and substation equipment.

Bipolar Complementary Metal Oxide Semiconductor ICs Bipolar technique used to be the major integrated circuit (IC) technique. Since 1980, complementary metal oxide semiconductor (CMOS) device has been developed to be dominant in the market. The bipolar and the CMOS techniques have different merits, and bipolar complementary metal oxide semiconductor (BiCMOS) technique can take advantages of these merits of both in the circuit system, as shown in Fig. 12.4. The CMOS process has progressed to nanoscale toward high speed and even approaching the speed of bipolar device. BiCMOS IC is the technology that integrates both bipolar junction transistor (BJT) and CMOS transistor in a single IC. Bipolar device offers high-speed, low-output resistance, whereas CMOS technology offers low-power logic gates, high-input resistance, high signal-noise ratio, and high integration in process. As a result, BiCMOS IC exploits both advantages of bipolar and CMOS, with benefits of Fig. 12.4 The speed vs power dissipation for Bipolar, CMOS, and BiCMOS

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Fig. 12.5 Cross-sectional diagram of a BiCMOS structure [1]

less power dissipation and higher packing density than bipolar IC, and better switching speed and analog circuit performance than CMOS IC [6]. The major fabrications of BiCMOS IC are based on the standard CMOS process with additional process to form bipolar transistors. Compared to the standard CMOS process, the fabrication of BiCMOS IC requires only a few extra masking steps and costs for the additional process for bipolar portion. A typical structure of BiCMOS IC is shown in Fig. 12.5 [6]. BiCMOS IC is widely employed in microprocessors and radio frequency (RF) communications. In early stage, it was used to fabricate static random-access memory (SRAM). In 1993, Intel used BiCMOS IC technology to introduce the first Pentium microprocessor [7]. BiCMOS IC has applied in the amplifier, RF transceivers, and oscillator in telecommunications [6]. In RF application, the BiCMOS heterojunction bipolar transistor (HBT) offers higher cut-off frequency comparing to bulk CMOS technology, and it is employed in RF amplifiers and receivers. The main manufacturers for BiCMOS IC in RF telecommunication include IBM, TowerJazz, STMicroelectronics, GlobalFoundries, Hua Hong Semiconductor, Advanced Semiconductor Manufacturing Corporation (ASMC), and Taiwan Semiconductor Manufacturing Company (TSMC). As it is required to achieve highquality data transmission in wireless communications, the BiCMOS IC has exploited the high analog circuit integration to expand the applications in IC products for the fourth-generation (4G) and fifth-generation (5G) communications [8, 9].

Bipolar Complementary Double-Diffused Metal Oxide Semiconductor ICs Bipolar complementary double-diffused metal oxide semiconductor (BipoIarCMOS-DMOS, BCD) IC is manufactured by simultaneously preparing IC chips of Bipolar, CMOS, and DMOS structures on the same silicon substrate. The devices fabricated by the BCD process not only have the advantages of high frequency and strong load of bipolar devices, but also have low loss and high density of CMOS devices, and have high resistance, strong driving, and fast switching speed of DMOS devices. They have been widely used in the preparation of power management devices, high-voltage power devices, display drivers, and automotive electronics [10].

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Fig. 12.6 Schematic diagram of the cross-sectional structure of the 700 V BCD process integrated circuit

In 1986, STMicroelectronics (ST) used the first generation of BCD process technology in driver ICs. Based on the bipolar device junction isolation process and compatible with the vertical 4 μm 60 V DMOS structure, the BCD process can be applied to the fabrication of driver ICs [11]. In 2014, a high-voltage AC LED driver chip was developed to re-verify the application of the high-voltage BCD process in this field [12]. By the end of 2016, the technical node of the BCD process has grown from the first generation of 4 μm to the ninth generation of 0.11 μm with expanded applications. In the field of high-voltage devices, a 700 V high-voltage BCD compatible process platform has been successfully built [13]. The full-injection technique is adopted on p-type single crystal substrate, which can realize the monolithic integration of 700 V BCD devices only with 10 more photomask plates than CMOS process. The section structure diagram of the 700 V BCD process integrated circuit is shown in Fig. 12.6. The 700 V BCD process can be used for the preparation of highvoltage and high-power integrated device products. The BCD process is also applied to the preparation of power management chips. In 2012, Dialog developed a low-power power management chip using TSMC’s 0.13 μm BCD technology. In the future, with the establishment of advanced CMOS and DMOS mature process platforms, the BCD integration technology will be more widely used in low-power, high-efficiency, and energy-saving power electronic products.

Fin Field-Effect Transistor ICs The Fin Field-Effect Transistor (FinFET) is a novel three-dimensional CMOS transistor. The prototype structure of FinFET based on SOI technology was firstly proposed by D. Hisamoto’s team from Hitachi in 1990 and referred to as DELTA structure [14]. Later, Hisamoto joined the group of Professor Chenming Hu at the University of California, Berkeley, which first proposed the n-channel FinFET in 1998 [15] and p-channel FinFET in 1999 [16]. Because the shape of the transistor gate is similar to a fin, Chenming Hu’s group named it as “Fin Field-Effect Transistor.” An SEM (scanning electron microscope) image of FinFET published

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Fig. 12.7 SEM image of FinFET by Intel

by Intel is shown in Fig. 12.7. The channel of FinFET rises from the surface of the silicon substrate to form a vertical channel structure, and then, the gate is fabricated on the upright channel, so that the three faces of the channel can be controlled by the gate. The 3D structure increases the control area of the gate to channel and leads to greatly enhanced gate-to-channel controllability; suppressed short-channel effect (SCE); and reduced sub-threshold leakage. In addition, the channel of FinFET is usually lightly doped or even undoped, so it can effectively improve the mobility of carriers due to the suppressed scattering effect and reduce the variations of device performance. At present, FinFET has been developed into a variety of structures, which can be divided into double gate, triple gate, surrounding gate, and so on, wherein the surrounding gate has the strongest control on the channel. Although FinFET has excellent control over the channel, its channel surface roughness is subject to process variations, e.g., lithography and etching to impact the device performance and yield. In addition, the Fin becomes thinner in future further scaled device, which causes the channel resistance to increase and the effective current to reduce. The superior performance of FinFET has led major semiconductor companies to develop new products based on FinFET technology. In 2012, Intel firstly announced the use of FinFET into its products, starting with the 22 nm processors [17]. In 2015, Samsung and TSMC used the FinFET to fabricate 14 nm and 16 nm A9 chips, respectively, which greatly improved the performance of the A9 chip [18]. Compared with the 20 nm process node, the speed of new products increased by 40% and the power consumption was reduced by 50%. In January 2016, AMD released a GPU chip based on 14 nm FinFET. In July 2016, Qualcomm also produced processors based on Samsung’s 10 nm FinFET technology.

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Silicon-on-Insulator IC Silicon-on-insulator (SOI) process was developed in 1960s. In order to obtain better radiation hardness in IC for military use, P. K. Weimer [19] developed a process of silicon on sapphire (SOS). SOS is actually an example of SOI processes. However, the high dislocation density due to the lattice mismatch at the sapphire/silicon interface often results in serious leakage current, and this SOS process did not achieve sustained development [20]. In 1966, M. Watanabe [21] implanted oxygen ions into silicon and obtained the SiO2 layer. This SiO2 with new process has the same breakdown voltage, dielectric constant, and other parameters as the SiO2 grown with the thermal growth method. In 1978, after K. Izumi [22] injected oxygen into silicon, a continuous SiO2 buried layer with excellent electrical properties was obtained, which was called separation by implanted oxygen (SIMOX) technology. SIMOX technology promoted the development of SOI in IC. In 1992, the appearance of plasma-assisted chemical etching (PACE) promoted the development of wafer bonding which was another SOI technology. In 1995, M. Bruel [23] developed smart cut technology which was later widely used in the FD-SOI (Fully Depleted SOI) technology with small line width. The cross section of MOSFET on SOI is illustrated in Fig. 12.8. Unlike conventional silicon-based IC, SOI can reduce junction capacitance and wire capacitance. In addition, thin-film SOI process has lower vertical electric field, lower surface scattering effect, and higher mobility, which can lead to better speed characteristics. Furthermore, the SOI process can eliminate the vertical parasitic devices, obtain the dielectric isolation of components, so that parasitic effects like latch-up can be avoided, and the crosstalk between components can be reduced. Therefore, the IC manufactured by SOI process can achieve very high integration density and have excellent radiation hardness feature, and anti-error triggering ability. SOI process can be applied to different IC according to the thickness of top silicon, mainly including FD-SOI CMOS, partially depleted SOI (PD-SOI) CMOS, bipolar CMOS (BiCMOS), power/high-voltage ICs, micro-electromechanical systems/sensors (MEMS/Sensors), etc. The applications with different top silicon thicknesses for SOI are shown in Fig. 12.9. Fig. 12.8 Cross section of MOSFET on SOI substrate

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Fig. 12.9 SOI is applied to different ICs according to the thickness of top silicon [20]

In the field of advanced semiconductor technology with small linewidth, FD-SOI and FinFET technologies have both attracted the attention of the industry. Between these two technologies, FD-SOI is produced on SOI substrates, which can follow the original CMOS process. FinFET uses the traditional silicon substrate, but its process is different from the traditional CMOS process. Therefore, FD-SOI is easier to implement, but its substrate technology is more demanding. By early 2017, large IDMs (e.g., Intel) clearly promoted FinFET development, while those represented by GlobalFoundries had devoted to FD-SOI process development. At present, Samsung provides customers with these two technologies at different linewidth nodes. Some manufacturers such as Freescale would try to combine FD-SOI and FinFET technology together.

Gallium Arsenide Devices and ICs Gallium Arsenide (GaAs) is III-V compound semiconductor material. It has a sphalerite crystal lattice structure with a lattice constant of 0.565 nm, a melting point of 1238
C, and a forbidden band width of 1.424 eV. It is one of the most important semiconductors after silicon and germanium (SiGe). GaAs devices have special features like high frequency, high speed, high temperature resistance, bottom noise, strong radiation resistance, etc. However, due to the defects of GaAs materials, its integration scale is limited, and the cost is high. GaAs devices are widely used in the microwave field. They are fully classified as microwave discrete devices, microwave hybrid IC, microwave analog, digital singlechip IC and so on. In 1967, Turne’s team produced the first GaAs-FET with a diffused gate structure [24], which opened a new wave of research on microwave semiconductor devices. In 1974, Fujitsu produced a GaAs MESFET with a power breaking through one-Watt in the X-band (8–12 GHz) [25]. In 1980, Fujitsu and other companies developed a first high-electron mobility field-effect transistor

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(HEMT) with GaAs as the channel using modulation-doped super-lattice technology [26]. The GaAs heterojunction bipolar transistor (GaAs HBT) developed in the early 1980s is superior in frequency and speed characteristics. Compared with GaAs FETs, GaAs HBT has higher transconductance, lower output conductance, and stronger current handling capability. Due to the continuous improvement of chemical ratio of material, defects, controllability of impurities, the improvement of thermal stability and uniformity, the high-quality single-crystal substrates have been obtained that makes mass production and expansion of gallium arsenide integrated circuits possible. GaAs digital and analog circuits have been put into mass production, mainly for military fields such as radar, laser-guided missiles, and satellite communications. Also in the consumer applications, GaAs integrated circuits are mainly used in wireless communications, automotive electronics, and so on. In addition, GaA materials have a direct transition energy band structure; thus, it has high photoelectric conversion efficiency in the preparation of solar cells. In terms of bulk devices and quantum effect devices, GaAs materials also have great potential applications. At present, GaAs integrated circuits are fabricated on 4-in/6-in wafers. GaAs materials are mainly from four major companies such as Freiberger Compound Materials, Hitachi Cable, Sumitomo Electric, and AXT. In recent years, the development speed of China’s GaAs industry has accelerated. In 2016, Sichuan Tonglineng Photovoltaic Technology, Zhongke Gallium Semiconductor, and Lion Dongxin Microelectronics are building up a number of 6-in GaAs integrated circuit production lines.

Indium Phosphide Devices and ICs Indium Phosphide (InP) is an III-V compound semiconductor, which has a sphalerite crystal lattice structure with a lattice constant of 0.5869 nm, a forbidden bandwidth of 1.344 eV at ambient temperature, and a melting point temperature of 1062
C. Similar to GaAs, it has high-electron mobility, which is suitable for high-frequency microwave devices and circuits. Solar cells prepared with InP have high photoelectric conversion efficiency. In 1975, Barrera’s team first produced a MESFET based on InP [27]. In 1987, the first InP high-electron mobility transistor (HEMT) was fabricated [28]. The InP HEMT is considered as the most promising three-terminal device in the field of microwave and millimeter-wave devices and circuits. Due to the high peak current, fast electron drifting speed, and high thermal conductivity of InP materials, InP HEMT can exhibit high operating frequency and output power. With the development of epitaxial material process and lithography, the performance of InP HEMT has been continuously improved. Reports show that the InP HEMT frequency has reached fT ¼ 610 GHz, fmax ¼ 1.5 THz, and a very low room temperature noise figure [29, 30]. Compared to GaAs devices, InP HEMT have higher cut-off

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frequency, higher conversion efficiency, and better reliability, making them ideal for millimeter-wave applications. In 2016, Urteaga reported an InP HEMT with fT ¼ 500 GHz, fmax ¼ 1 THz, and current density greater than 25 mA/μm2 at the International Electron Devices Meeting (IEDM) [31]. At present, the operating frequency of InP circuits has reached the W band (75–110 GHz) and has been practically applied to weapons and equipment. InP devices have been widely used in microwave communication, image sensors, artificial satellites, and other fields. InP devices and circuits have excellent performance, but their high cost and low yield are the key factors limiting their widespread application. The InP research is focused on simplifying polycrystalline synthesis process, increasing wafer size, reducing defect density, and improving material surface quality. At present, industrially grown InP single crystals mainly adopt vertical gradient freeze (VGF) solidification method, vapor controlled Czochralski (VCZ) method, high pressure horizontal Bridgman (HPHB) method, and so on. Internationally, the process of fabricating devices on 4-in InP chips is mature and commercialized. Crystacomm has released 4-in InP chips in 1997. AXT uses the VGF method to prepare InP. Sumitomo Electric has a large number of patents in InP researches and has successfully produced 6-in InP single crystals. In addition, several companies (e.g., InPACT of France, MCP of UK, CGC of Germany, and HSRI of China) have made great progress in InP material research.

Gallium Nitride Devices and ICs Silicon power devices have been widely used in high-power switches, like batteries, motor control systems, factory automation, and automotive electronic devices. These silicon power devices are mainly concerned about the descending of power loss. In these applications, higher breakdown voltage and lower on-resistance are the key points to reduce the power loss. However, the performance of silicon power devices has been reaching the theoretical limitation. Besides, many power electronic systems require ultra-high breakdown voltage and switching frequency. Silicon power devices are not able to meet such high requirements yet. Thus, wide bandgap semiconductors attract much attention. The power devices prepared by wide bandgap semiconductor can act as a high-voltage switch with low on-resistance. Therefore, they can take place of silicon power devices. Furthermore, the wide bandgap heterojunction field-effect transistors have high carrier density, 2D electron gas channel, and high critical electric field strength, among which such as gallium nitride (GaN) is able to prepare excellent power switch. The structure of GaN HEMT device has been shown in Fig. 12.10. Due to the polarization effect, one layer in GaN HEMT will generate 2D electron gas. It can act as a channel of the device. Gate functions as the switch by depleting 2D electron gas. Like other FETs, GaN FETs also have high frequency. Thus, they can be used as high-frequency digital switch, e.g., mobile phones, satellite television receivers, voltage converters, radar, and microwave communications.

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Fig. 12.10 Schematic cross section of a GaN HEMT [32]

Silicon Carbide Devices and ICs Silicon carbide (SiC) has superior electrical properties. The forbidden band width is 2.3 eV–3.3 eV, which is about 3 times of silicon. The breakdown electric field is in the range of 0.8  106 – 3  106 V/cm, and it is about 10 times larger than that of silicon. The saturation drift speed (2.7  107) is 2.7 times that of silicon, and the thermal conductivity (4.9 W/(cmK)) is about 3.2 times that of silicon. The physical parameters of Si, GaAs, and 4H-SiC are shown in Table 12.1. Readers can refer to Appendix B for more complete information [33]. Silicon carbide (SiC) is mainly used in high-voltage power devices, and many devices based on SiC material have been put into use. The SiC industry chain includes SiC material production, chip manufacturing, device sales, and equipment supply. At present, the United States is in a leading position in chip manufacturing and device sales of SiC, and Japan is mainly in the leading position in the supply of SiC equipment. SiC is a new generation of wide bandgap semiconductor materials with great potential for semiconductor applications. The military applications of SiC include missile chips, phased array radars, and aircraft carriers. Its application of new energy sources includes LED green lighting. In terms of energy saving and environmental protection, SiC chips can be used for power generation/transmission inverter switches, which can save 50%–70% of power loss during power transmission. In terms of electric vehicles, the SiC chips can save energy and reduce consumption and can save about 80% of space in volume, which has greatly helped the development of the electric vehicle industry. In high-end equipment manufacturing, a large number of SiC chips are required for new energy vehicles, ships, aerospace, space shuttles, and communication systems. The global research on SiC materials and the development of commercialized SiC power devices are still in their infancy. The industry needs to integrate SiC

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Table 12.1 Physical parameters of three semiconductor materials, Si, GaAs, and 4H-SiC Material Band gap Electron mobility, cm2/Vs Breakdown electric field, MeV/cm Thermal conductivity, W/cmK Saturation velocity, cm/s Dielectric constant

Si 1.11 1400 0.3 1.5 1.0  107 11.8

GaAs 1.43 8500 0.4 0.54 2.0  107 12.8

4H-SiC 3.26 900 2.2 4.9 2.7  107 10.0

technology into the entire product chain. The purification technology of SiC raw materials, the SiC crystal growth equipment, the SiC crystal growth technology, SiC chip production technology, the related SiC device design, and manufacturing technologies are all important to be developed.

Heterojunction Bipolar Transistor (HBT) Unlike general bipolar transistors, different materials were used at the Emitter region and Base region in the heterojunction bipolar transistor (HBT). The structure of the HBT is shown in Fig. 12.11. The semiconductor materials used in emitter region have a large bandgap, a pn heterojunction is formed between the emitter region and the base region. Compared with conventional bipolar transistors, HBT can operate at higher frequencies (usually up to hundreds of GHz), with higher conversion efficiency and high base emissivity. Based on these advantages, HBT is mainly used in radio frequency (RF), high power, and high-speed circuits and mobile phones [34]. Because the wide bandgap semiconductor material is used in the emission area of the heterojunction, the discontinuity will occur at the energy band of the heterojunction. For a npn heterojunction bipolar transistor, a large abrupt change in valence band energy will prevent the hole from injecting into the n-type emitter from the p-type base region. The emission efficiency of the heterojunction is basically the same (that is, the electron moves through the emitter area to the base area), and the emission efficiency is independent of the doping concentration of the emitter area and the base area. Therefore, the emission efficiency of HBT emitter junction (also known as amplification factor) is independent of the concentration of both sides of the emitter junction, so the doping concentration in the base area can be higher than that in the emitter area, and then, the frequency band can be optimized by amplifying the coefficient, so that HBT can work in the millimeter-wave range. The maximum current gain (without considering base recombination) formula of HBT is as follows: βmax ¼ I En =I Ep 1 exp ΔEg =kT The ratio βmax of HBT to traditional BJT can be determined by the energy difference of the bandgap ΔEg:

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Fig. 12.11 Schematic of basic structure of HBT

βmaxðHBTÞ =βmaxðBJTÞ ¼ exp ΔEg =kT Generally, ΔEg > 250 meV, the gain of HBT is 104 times that of traditional BJT [35]. The applications of HBT were as following: 1. Low noise amplifier (LNA): Noise factors and correlation gain are very important parameters for receiver/transmitter in mobile communication equipment, and low noise amplifier (LNA) in the front-end design has a great impact on these parameters. The excellent noise characteristics of HBT can improve the performance of LNA. 2. Multiplexer: In 1993, the German scientist H.U. Schreiber et al. developed a 16 Gbit/s with 2:1 ratio of multiplexer using a double-mesa self-aligned SiGeHBT (T ¼ 40 GHz); in 1999, a 30 Gbit/s selective chip with a total power consumption of 1.1 mW was developed using the same type of SiGe-HBT. 3. Power Amplifier (PA): SiGe-HBT monolithic IC and BiCMOS have been greatly developed and laid the foundation for the integration of mixed signal systems. SiGe-HBT has excellent characteristics at temperature, radiation resistance, and frequency. It is also compatible with existing CMOS processes and rapidly developed in all aspects of applications.

System in Package IC System in Package (SiP) was technically in analogous to system-on-package (SOP) that developed at Georgia Institute of Technology in 1997 [36]. The novel concept for electronic package featured the integration of all the functional devices into a single-chip carrier, which can hence possess all necessary function. SiP has become an essential technology for advanced electronic package and system integration. Besides, this technology is believed to be promising in the pursuit of the shrinking and multi-functional electronic goods.

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Fig. 12.12 (a) SoC-SiP package, (b) MEMS-SiP Hall sensor

In SiP, chips (or dies) can be stacked vertically or placed horizontally on a carrier, while SoC (System-on-Chip) features a highly integrated single chip [37]. Moreover, package cap cannot contact the microelectromechanical devices in a MEMS (Microelectromechanical Systems) package, which is different from the conventional electronic package [38]. A SoC design using SiP and a MEMS design with Hall sensor using SiP are shown in Fig. 12.12a, b, respectively. With the emerging market of high-speed wireless communication, materials for package become more demanding for high-frequency application, while the smaller package size and low cost are expected. A novel SiP module embedded into Apple iWatch included NFC (Near Field Communication), Bluetooth, MEMS, and flash memory has been succeeded, it is the SiP module that enabled the wearable multiple functions and delicate design.

Micro/Nano-Electro-Mechanical System and IC Since the middle of the twentieth century, microelectronic technology and related fabrication techniques have been developed fast. Based on that, micromachining technology has also been significantly improved especially for the micro-sensors and micro-actuators. Micro-Electro-Mechanical Systems (MEMS) is an integrated system with microelectronic device, microstructure, and micromachinery parts such as micro-sensors and micro-actuators. MEMS typically involves physical or chemical exchange between electric domain and other energy domains, which is a crossdiscipline of various research fields. In addition to the traditional components of microelectronic and micromechanics, MEMS has recently emerged with some other areas including micro-heat, micro-optics, micro-magnet, micro-fluidics, microbiology, and micro-chemistry, as shown in Fig. 12.13. Micro-sensor and micro-actuator are also called transducers. Developed from the IC technology, MEMS has kept many fundamental processes such as lithography, implantation, doping, sputtering, evaporation, PECVD, LPCVD, oxidation, and wet etching. Many featured processes have also been developed during the development of MEMS, such as surface micromachining,

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Fig. 12.13 Scheme for the development of MEMS subjects

Fig. 12.14 Self-powered wireless sensor network

bulk micro-machining of silicon, wafer bonding, LIGA technology for structure with high aspect ratio, and non-silicon processes. MEMS products are mainly applied for the consumer electronics, especially for the automobiles and the cell phones. For instance, MEMS-based gyroscope, temperature sensor, humidity sensor, microphone, display sensor, proximity sensor, and light intensity sensor have been widely used in smartphones. Moreover, MEMS is usually integrated with various sensing components, actuators, and some related IC microprocessors. Ideally, it should also be integrated with micro-energy (such as energy harvesting devices [39–41]) and communication components. Figure 12.14 shows a self-powered wireless sensing network consisting of the MEMS energy harvester, IC, and wireless communication components. Nano-Electro-Mechanical System (NEMS) is developed based on MEMS, while the feature size of the NEMS device and system is as small as nanoscale. Some effects other than the macro scale properties such as the surface effect and scaling effect of the material may emerge at nanoscale, which would dominate the

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performance of the device and system. With respect to the material and the process, NEMS device is not merely scaling down the MEMS device. It typically explores new function by utilizing some novel nanomaterials such as graphene, fullerene, carbon nanotube, and other 2D materials and biomaterials. Advanced techniques such as E-beam lithography and nanoimprint process have also been widely used to fabricate NEMS devices. NEMS has mainly been applied for sensors with super-high sensitivity, biomedical devices, dense data storage, and high-frequency resonator, etc. The sensing mechanism includes various physical principles such as the resistive response, frequency response, fluorescence, and magnetic response of the nanomaterials and nano-structure. For example, silicon cantilever of 50 μm  6 μm  0.17 μm has been fabricated with a batch of carbon nanotubes at the free end to adsorb hydrogen gas. The cantilever is driven electrostatically, whose resonance frequency in a vacuum pressure of 107 Pa is shifted upon a tiny change of the effective mass [42, 43]. With a feedback control, the resonant frequency of the cantilever can be 1 MHz, and the quality factor of the device in vacuum could be as high as 50,000, which gives a mass resolution of 5  1018 g. With such excellent mass resolution, it is possible to detect 150 million molecules of hydrogen gas.

IC Products of Other Advanced Processes With the increasing requirements of integrated circuit performance, there are three main development directions of process technology: (1) the three-dimensional technology to integrate the system, including three-dimensional packaging, and multi-active layer three-dimensional process; (2) novel materials and processes technology, and (3) new physical mechanisms and novel device structures. Many new semiconductor materials have emerged in recent decades of research, and many novel devices have been fabricated based on these new materials and related processes. For example, SiGe heterojunction bipolar transistors (SiGe-HBT), SiC devices, GaN blue light devices, and various nano-electronic products. Taking the strained silicon process as an example, the strained silicon is valued for their high mobility [44]. The preparation methods of strained silicon can be divided into two categories: global strained silicon process and local strained silicon process. With the rapid development of IC technology, the device size has shrunk dramatically; the physical and process integration technology of devices has become more and more complicated. The carrier transport will exhibit significant quantum mechanical properties. Therefore, low-dimensional semiconductor devices are based on quantum effects stand out. Graphene is a typical two-dimensional material, which is a honeycomb planar film formed by carbon atoms in a sp2 hybrid manner. Graphene has high-electron mobility, low resistivity, and good thermal conductivity as well as mechanical properties, making the graphene devices be regarded as the electronic components for future integrated circuits [45]. In 1991, S. Iijima discovered carbon nanotubes (CNTs) from carbon fibers produced by the arc method [46]. CNT is a one-dimensional nanomaterial with a tubular carbon molecular structure. It

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has high modulus, high strength properties, good thermal conductivity, and special electrical properties. Hence, it has a good application prospect in future molecular devices or nano-electronic devices. Stanford University has developed a computer prototype based on CNT, which is expected to evolve into a faster and more efficient computing device than Si-based computers [47]. Quantum dots are a zerodimensional material, and its unique electronic density of states makes them more suitable for lasers.

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Products of Digital Integrated Circuit

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David Hu, Alex Lin Jia, Fan-Yi Jien, Xia Ai, and Chun-Zhang Chen

Contents Digital Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Random Access Memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Random Access Memory (DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double Data Rate (DDR) SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Double Data Rate SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics Double Data Rate SDRAM (GDDR SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OTP and MTP Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . One-Time Programmable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Time Programmable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Solid-State Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multimedia Card and Embedded MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Chip Package Memory and eMCP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X86 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IA-64 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIPS Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARM Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UltraSPARC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-SKY Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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D. Hu EtownIP Microelectronics Co. Ltd., Beijing, China A. L. Jia Cadence Design Systems, Inc., Shanghai, China F.-Y. Jien Advanced Memory Semiconductor Co. Ltd., Jiangsu, China X. Ai Cadence Design Systems, Inc., Beijing, China C.-Z. Chen (*) Peng Cheng Lab, Shenzhen, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_13

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Graphics Processing Unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RISC-V ISA and RISC-V Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application-Specific Integrated Circuit and System on Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Network Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secure Cryptoprocessor and Cryptographic Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Among all semiconductor and IC products in the global market, digital IC contributes to about 70%, which includes memory, CPU, logic, ASIC, and IP products. Over the past 50 years or so, various types of memories have been developed, including embedded SRAM, DRAM, their derivatives (DDR, LPDDR, and GDDR), and external flash memories (NAND, NOR). Started from 8086 in 1978, the x86 CPU series from Intel has the longest development history, variety of CPU instruction set architecture (ISA) are co-exiting in the industry today, including POWER series from IBM, MIPS from Imagination, and ARM series from ARM Holdings. Broadly speaking, MPU, MCU, and DSP are also members of CPU family. This chapter reviews the digital IC products of memories, CPUs, ASIC, and FPGA. Keywords

SRAM · DRAM · DDR · Flash · x86 · MIPS · ARM · MCU · DSP · RISC-V · FPGA · ASIC

Digital Integrated Circuit Digital integrated circuit (IC) products offer various features, such as high density in integration, portability, low power consumption, and high reliability so as to be processed in electronic systems. Digital IC products in the form of CPU, DSP, SoC, memory chips, special functional die, and modules, presented in electronic systems or equipment form(s), are widely used in communications, consumers, Internet of things (IoT), and medical devices, as well as in industrial controlling, aeronautics and astronautics, military, robotics, and artificial intelligence (AI) products. In 1968, the first commercial CMOS digital IC 4000 series was released by Radio Corporation of America (RCA). In 1970, Intel Corporation released the 1103 chip, which used the 8 μm pMOS process and was mass produced in 1971 [1]. The 1103 chip has 1 Kbit dynamic random access memory (DRAM) and remarked the emergence of large-scale integration (LSI, more than 500 transistors on a chip). Intel released the first microprocessor 4004 in 1971; it integrated 2300 transistors on 10 μm process. In 1980, very large-scale integration (VLSI, more than 104 transistors

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on a chip) IC was released. The era of ultra-large-scale integration (ULSI, more than 106 transistors on a chip) IC arrived in 1989 [2]. In 2005, the scale of digital IC was more than 1 billion components (more than 109 transistors on a chip), and it ushered the era of SoC products. In 2019, Cerebras Systems announced a Wafer Scale Engine (WSE) chip containing 1 trillion (1.2
1012) transistors on a single wafer [3]. Digital IC usually integrates various functional modules. For example, a digital memory product (ROM or RAM) is composed of many memory units that are called ROM or RAM cells. A SoC product integrates the CPU, many logic standard cells, digital memory units, input/output (I/O) cells, and other IP modules. There are various types of digital IC products, which have different functions and applications. In the 1990s, the main products of digital IC were CPU, DSP, and memory cells, microcontroller unit (MCU), microprocessor unit (MPU), and ASIC, and the applications focused on “3C,” then so-called computer, communication, and consumer. Early ASIC products are designed for specific applications, such as color graphics adapter (CGA) and video graphics adapter (VGA) chips for monitor display of computers and televisions. As the demand of chips was growing, in home appliances and consumer products, MCU and MPU have been developed. In the early of twenty-first century, SoC has been highly valued and promoted. People liked to integrate the multiple independent chips such as CPU and memory on one chip, which greatly promoted the development of smart electronic products. In the last decade, various new digital IC products appeared, which are based on more complex system designs, such as GPU, integration based on heterogeneous system architecture (HSA), and AI chips, such as these chips in machine learning applications, etc.

Static Random Access Memory (SRAM) In semiconductor, a patch of data is stored in “memory.” According to their state after power is cut off, for those data no longer in existence is called volatile memory (VM), and for those after the power is cut off, data still stored are called nonvolatile memory (NVM). For example, the most commonly known NVM is the flash memory, or simply, flash. The static random access memory or SRAM and the dynamic random access memory (DRAM) both belong to the VM category. The first 1 Kbit 6T-SRAM was developed by Intel in 1976 [4]. In 1980, T. Iizuka et al. successfully developed a pure CMOS-based SRAM having capacity of 16 KB [5]. The single integrated SRAM chip during that period is normally having capacity of 32 B–128 KB. In general, embedded SRAM from a few kilobytes to megabytes is found in the stand-alone single chip for common electronic products such as electronic toys, digital cameras, mobile hand-phones, and digital music instruments. SRAM according to their accessing speed and operational manner can be categorized as single-port SRAM and double-port one. Signal processing circuit, as in the digital signal processor (DSP) has no restriction in accessing the memory, so dual-ported SRAMs are widely used for faster operation [6]. A typical SRAM chip consists of one or multiple core cell arrays, line and column decoder, sense amplifier, and control circuits. The SRAM makes use of a transistor’s on/off state to form a

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flip–flop circuit; their switching speed is in nanoseconds. The 6T-SRAM cell is commonly comprised of 2x PMOS and 4x NMOS transistors. There is also 4T-SRAM, which has four transistors plus two resistors. Other than the 4T- and 6T-SRAM, there are also 8T-SRAM and 10T-SRAM, but that would compromise the chip area and hence less used in the commercial applications. Less than 4T-design is found in the DRAM, which requires highest compact density such as 1T-DRAM or 3T-DRAM. Whether “refresh” is needed or not during operation is the key difference between DRAM and SRAM. SRAM does not need to refresh, and the data previously stored are always there. However, DRAM if not refreshed from time to time, the data stored may be lost. Comparing to DRAM, SRAM has higher speed and low power consumption, especially during its idle state, but also higher price. Therefore, SRAM is commonly used in the high bandwidth and low power consumption or both; SRAM has advantages of easy to control, random access, and read/write faster but it suffers low capacity and low density and bigger areas than DRAM of similar capacity. Therefore, SRAM is not suitable for large memory-required applications. SRAM is normally used as cache of the first-level buffering unit (L1) or second-level buffering unit (L2). Since 80,486 of Intel’s microprocessor series, the high speed is partially attributed to the fast-accessible cache memory from SRAM embedded inside the microprocessor chip, and later, in its Pentium CPU the L1 and L2 cache memories became the norm. The L1 cache memory is commonly designed inside the CPU, and the L2 is built at outside of the CPU. With both L1 and L2 cache memories, the CPU single-chip size is relatively big. The current CPU architecture making use of ARM core also introduces the cache memory to solve the speed mismatch issue with the core DRAM. As DRAM cell can only have one transistor and one capacitor (1T1C), hence it is used largely in the internal memory of a computer, which requires maximum capacity and density with minimum chip area. Intel, Samsung, and TSMC have all mass productions of 6T-SRAM in 45 nm, 32/28 nm, and 16/14 nm technology nodes. The current competition is in their 10 nm tech node, making use of FinFET with small area but high-performance 128 megabit SRAM products [7]. With the development of high-speed dynamic audio/video image exhibitions, such as in the applications of virtual reality (VR), augmented reality (AR), and artificial intelligence (AI), the ultrafast read/write SRAM is increasingly demanded, it is therefore the search of new types, and high-performance SRAM device have ever intensified.

Dynamic Random Access Memory (DRAM) In the 1970s to mid of 1990s, dynamic random access memory (DRAM) normally used the asynchronous interfaces [8]. An asynchronous DRAM (“ADRAM”) corresponds with the control input signal at any time, and this asynchronous interface also provides direct control of internal timing.

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DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and one transistor (1T1C) per data bit. The horizontal lines connecting each row are known as word lines. Each column of cells is composed of two bit lines, each connected to every other storage cell in the column. They are generally known as the “+” and “” bit lines. A sense amplifier is essentially a pair of cross-connected inverters between the bit lines. The first inverter is connected with input from the “+” bit line and output to the “” bit line. The second inverter’s input is from the “” bit line with output to the “+” bit line. This cross-connection circuit results in positive feedback, which stabilizes after one bit line is fully at its highest voltage and the other bit line is at the lowest possible voltage. The concept of synchronous DRAM (SDRAM) was introduced as early as in the 1970s. It was well adapted even though most of the DRAM is still using asynchronous interface for example in the early Intel microprocessor. However, it was only widely accepted in the electronic industry ever since 1993. Samsung demonstrated their KM48SL2000 SDRAM in 1993 [9]. Not until 2000, SDRAM has eventually replaced “ADRAM ” and becomes dominant in computer memory. SDRAM has the below features comparing with a normal DRAM. Its operation can be multiple piped. The data transfer rate can be raised when the speed of MCU increases. It also prevents failure rate due to the input signal distortions, and it has low power consumption and high band width. All instruction signals are synchronized with the master clock; therefore, it is easy and quick to manage; however, it is rather more complex than the synchronous interfaced one. SDRAM has architecture of multiple banks, and each bank can be regarded as an individual RAM array, which consists of row and column address lines and word buffers. The most significant change, also the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of “bank address,” which accompany each command, a second bank can be activated and begin reading data while a read from the first bank is in progress. By alternating banks, an SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot. Each bank of the SDRAM shares a common input/ output (I/O) with one another. The capacity of SDRAM is determined by its number of addresses (#Addresses), number of bits (#Bits), and number of banks (#Banks), namely the capacity (density) of SDRAM ¼ (#Addresses)
(#Bits)
(#Banks). As a type of volatile memory, DRAM has simpler structure compared to SRAM. It only needs one transistor and one capacitor, 1T1C, to formulate a bit cell. Hence, the highest density and capacity can be achieved in a small single stand-alone chip. It is widely used in the internal memory for computer, and with the development of the CPU, and high-performance computing (HPC), the requirement for the ever faster accessing memory is increasingly challenging. The older framework of the DRAM is no longer suitable, to make it simple, as far as the read/write is concerned, there are SDRAM and “ADRAM ”. In terms of the data rate, there are single data rate (SDR) and double data rate (DDR); also, there is quad data rate (QDR) SDRAM. For

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applications, the DRAM can also be categorized into GDDR just for the graphical use, or depending on the level of voltage, there are ordinary DDR and low power DDR (LPDDR). If the DRAM is embedded together with other functional blocks such as CPU, it is also called embedded DRAM or eDRAM [10].

Double Data Rate (DDR) SDRAM Synchronous DRAM (SDRAM) if based on the data accessing rate can be differentiated as single data rate (SDR), double data rate (DDR), and quad data rate (QDR) SDRAM [11], as illustrated in Fig. 13.1. A computer bus operating with double data rate (DDR) transfers data on both the rising and falling edges of the clock signal. The manufacturing process of DDR is the same as the SDRAM, and the manufacturer only needs a little modification to the equipment can readily put DDR in mass production. The development of SDRAM has been through five generations unto the present: The first generation is SDR; 2nd generation is DDR; the third generation is DDR2; and the fourth is DDR3; and the fifth generation is DDR4 (see Table 13.1). On March 30, 2017, JEDEC has published the DDR5 specifications, which have been finalized on May 2019. It is simply based on the DDR4 with double data bandwidth and the array density of DDR4; DDR5 is expected twice as fast as its previous precursor. In the meantime, lower the power consumption and increase the read/write speed. This development is in line with the graphic advancing with the virtual reality (VR) and its applications. There are two commonly packages of stand-alone SDRAM found in the market. The first one is the early product of 168 pins dual in-line memory module (DIMM)

Fig. 13.1 Comparison of data speed between SDR, DDR, and QDR

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Table 13.1 Detailed comparison of different specifications of DDRs Specs Internal clock/MHz Bus clock/MHz Data transfer rate/(Mb/s)

DDR 133–200 133–200 200, 266, 333, 400

DDR2 133–200 266–400 400, 533, 667, 800, 1066

DDR3 133–200 533–800 800, 1066, 1333, 1600, 1866, 2133 12.8

Theoretical bandwidth, GB/s Operating voltage

1.6, 3.2

6.4

2.5 V

1.8 V

1.5 V (1.35 V/ 1. 2 V DD3L)

I/O interface Prefetch Burst length/bit Number of banks Single-chip density On-die termination, ODT

SSTL2 2n 2/4/8 2, 4, 8 128 Mb–1 Gb None

SSTL18 4n 4/8 4, 8 256 Mb–4 Gb Medium, Dynamic

SSTL15 8n 8 8 512 Mb–8 Gb Medium, dynamic

Package

TSOP or BGA FBGA

FBGA

DDR4 133–200 1066–1600 1600,1866, 2133, 2400, 2667, 3200 19.2, 25.6

POD12 8n

4–16 Gb | Medium, dynamic, park FBGA

Remarks Master clock

Lower power better heat dissipation Buffer depth Burst length Bank number Improved signal transfer rate and lower the power Higher speed, improved EMI

Note: Prefetch represents the buffer size. For example, for DDR3, its Prefetch buffer size is 8n, representing every single buffer depth to be 8

but that was ceased in production since 2012. In place of it is the newer 184 pins DDR memory chips. At present, DDR DIMM, DDR2 DIMM, and DDR3 DIMM also DDR4 DIMM are all incompatible with one another. So be aware of this and mix usage is not permitted.

Low-Power Double Data Rate SDRAM A low-power double data rate SDRAM (LPDDR SDRAM, or simply LPDDR) is a special type of DDR SDRAM. It is extensively used in the mobile communications and hence acquired the name of mDDR; here, m stands for mobile or mobile DDR. The product series includes LPDDR/2/3/4, and its standard was defined by JEDEC targeting only to the low power and small die area, because its small die size, LPDDR, is specialized in the application of mobile product [12]. Many improvements have been made to the LPDDR. The most significant one is to reduce the operating voltage from 2.5 V to 1.8 V and also introduced the temperature-compensated refresh technique; hence, the power consumption is further reduced. LPDDR2 has some further improvement in its array technology; the low-power feature is almost the same as LPDDR, but both LPDDR and LPDDR2 are incompatible with DDR1 and DDR2, respectively.

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Table 13.2 Major feature comparisons of LPDDR2, LPDDR3, and LPDDR4 FEATURES Internal clock/MHz Bus clock/MHz Data rate/(Mbit/s) Band width/(GB/s) Prefetch VDD2/VDDQ/VDD1 Command/ADDR bus Bank number Chip density Interface I/O width Package

LPDDR2 200 400 800 6.4 4n 1.2 V/1.2 V/1.8 V 10 bit, DDR 4/8 64 Mbit to 8 Gbit HSUL_12 16 bit/32 bit MCP/PoP

LPDDR3 200 800 1600 12.8 8n 1.2 V/1.2 V/1.8 V 10 bit, DDR 8 4 to 32 Gbit HSUL_12 (OR ODT) 16 bit/32 bit MCP/PoP

LPDDR4 200 1600 3200 25.6 16n 1.1 V/1.1 V/1.8 V 6 bit, SDR 8/CH, total 16 8 to 32 Gbit LVSTL 16 bit/CH, TOT 32 bit MCP/PoP

In May 2012, JEDEC has officially announced the LPDDR3 standard. It is in support of the package on package (PoP) in order to meet the various requirements of mobile application [13]. The power consumption feature of and the interface to signal of LPDDR2 can be also found in the LPDDR3. In addition, one key feature of LPDDR3 is the introduction of write leveling and CA Training and on-die termination (ODT). Comparison of LPDDR2, LPDDR3, and LPDDR4 can be found in Table 13.2. JEDEC defined in early 2019 the (I/O) data rate of LPDDR5 to be 6400 MT/s (T stands for I/O throughput), while Samsung announced LPDDR5 in July 2018 and released mass production of LPDDR5 in July 2019 on 10 nm process at data rate of 5500 Mb/s, with chip density 12 Gb, which can be expanded to 12 GB package [14].

Graphics Double Data Rate SDRAM (GDDR SDRAM) The modern GPUs are demanding higher-performing solutions to keep pace with their ever-increasing bandwidth requirements of data access. The graphics double data rate synchronous dynamic random access memory (GDDR SDRAM or simply GDDR) is designed with high bandwidth to speeding through heavy graphics task. While the GDDR SDRAM shares design similarities with the DDR SDRAM, it achieves higher bandwidth, higher clock speed, lower power consumption, and heat dispersal requirements. The GDDR is not compatible with DDR for several specifications, such as operation voltage, package, and interface, especially the huge difference of performance. The first-generation GDDR is developed from DDR technology. The GDDR is nearly same as DDR, but clock speed is up to 900 MHz, while DDR is up to 600 MHz.

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Table 13.3 Specifications of GDDR3/GDDR5/GDDR6 Specifications Density (Gb) VDD, VDDQ Clock speed (MHz) Data rate (Gbit/s) I/O width per channel Number of banks Prefetch Burst length Cyclic redundancy check (CRC) Package

GDDR3 1–2 1.5 V (1.35 V) 800/900 1.6–1.8 4, 8.16 8 8n 4 burst chop N/A BGA-78/96

GDDR5 4–8 1.5 V, 1.35 V 1750 5–8 32/16 16 8n 8 Yes BGA-170

GDDR6 8/16 1.35 V 1750 12–16 32/16 16 16n 16 Yes BGA-180

The second-generation GDDR2 is developed from DDR/DDR2 and NVIDIA first-made improvement on GDDR2 for GeForce FX 5800 in 2003 [15], and it is two times faster as DDR. The third-generation GDDR3 specification was promoted by ATI (AMD-acquired ATI in 2006) and DRAM vendors and finally was adopted as JEDEC standard. GDDR3 comes from DDR2, which is specially designed for GPUs. GDDR3 could send two 32-bit wide data words per clock cycle. It has two unidirectional and single-ended data strobe that could save read/write turnaround time. It is operated at lower voltage and leads to lower power consumption, lower heat output, and high clock frequencies. The first card to use the GDDR3 SDRAM was NVIDIA GeForce FX 5700 Ultra in early 2004. The fourth-generation GDDR4 SDRAM is developed by JEDEC. GDDR4 is developed from DDR3 technology and was intended to replace GDDR3. ATI used the GDDR4 for few types of GPUs from 2006, while other manufacturers used the GDDR5 to replace the GDDR3 directly. The fifth-generation GDDR5 SDRAM is based on DDR3 SDRAM and is developed by JEDEC and several other companies [16]. GDDR5 is twice the data rate of GDDR3. GDDR5 is widely used in the last couple generations of GPUs from 2008. In January 2016, JEDEC standardized a new GDDR5 version GDDR5X, whose data rate is twice of GDDR5. In 2017, JEDEC standardized GDDR6 SDRAM [17], which offers max data rate up to 16 Gbit/s and lower operating voltage (Table 13.3), and the power consumption is farther reduced. The industry-leading graphics vendors have adopted widely in market applications of the graphics GDDR, for high-performance computing, networking, and data centers.

OTP and MTP Memories There are two categories of programmable memories, viz. one-time programmable memory and multi-time programmable memory.

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One-Time Programmable Memory One-time programmable (OTP) memory is a type of memory, which cannot be erased once it has been programmed. Programmable read-only memory (PROM) is a typical OTP memory [18]. It was invented in 1956 by Wen Tsing Chow [19], an American Scientist, to fulfill the requirement of data memory in airborne computers for United States Air Force. There are two common PROM types: bipolar fuse PROM and Schottky PROM. By introducing high current, the former can be programmed by melting down fuse, shown as Fig. 13.2, and the latter by permanently breaking down Schottky diode. In 1971, Dov Frohman from Intel invented erasable PROM (EPROM), which is mainly used for storing program code of microcontroller. Storage content can only be removed by an EPROM eraser. For this purpose, a fused quartz window is installed on the package of EPROM (see Fig. 13.3). Storage content can be erased by exposing EPROM die to ultraviolet light through the fused quartz window, which therefore should be covered to protect data after programmed [20]. OTP EPROM was produced by mounting die directly into opaque package. Without fused quartz window, OTP EPROM cannot be erased after programming. Major OTP EPROM manufacturers are Atmel, STMicroelectronics, and NEC.

Multi-Time Programmable Memory Multi-time programmable (MTP) memory is a type of memory, which can be programmed multiple times. Erasable programmable read-only memory (EPROM) [3] and electrically erasable programmable read-only memory (EEPROM or E2PROM) are common MTP memories. EEPROM can electrically erase storage content. It can be written, modify, or erased by a programmer. Therefore, EEPROM is used to memorize data, which require modification for multiple times. An EEPROM cell array is composed of floating gate transistors (see Fig. 13.4). Floating gate technology was invented and published by Simon M. Sze and Dawon Fig. 13.2 Simplified schematic of bipolar PROM

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Fig. 13.3 ERPOM

Fig. 13.4 Cross-sectional view of floating gate transistor

Kahng from Nokia Bell Labs in 1967 [21, 22]. In 1977, EEPROM using Fowler–Nordheim tunneling was invented by Eliyahou Harari from Hughes Aircraft, which was acquired by General Motors in 1985. In the early days, EEPROM can only allow single-byte operation. It now can allow multi-byte page operations for more than one million times. The erase speed limitation of EEROM results in the invention of flash memory, which has an advantage in the capability of operating erase in a block. Emerging nonvolatile memories, such as phase change memory (PCM) or resistive random access memory (RRAM), are gradually replacing EEPROM in specific applications. Advanced Memory Semiconductor Co. (AMS) in Jiangsu, China, launched a PCM-based EEPROM in 2019.

Flash Memory Flash memory is a kind of nonvolatile memory (NVM). Common flash memory restrains two types of technologies: NOR flash and NAND flash memory. Fujio Masuoka, an engineer from Toshiba, invented NOR flash in 1984 and NAND flash in 1987; he received the IEEE Morris N. Liebmann Memorial Award in 1997.

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In 1988, Intel launched the first NOR flash product. NOR flash technology featured as eXecuted In Place (XIP), which can execute programs without copying the code into RAM. Based on NOR flash technology, Mitsubishi and Hitachi invented divided bit-line NOR (DINOR) structure [23]. Compared with NOR flash, DINOR flash is slightly slower in byte-write operation, but it is also faster in block-erase and block-write operations. Major NOR flash manufacturers are four IDMs, including Micron Technology, Spansion (merged in 2014 to Cypress, who was in 2020 merged to Infineon), Macronix, and Winbond. NAND flash was launched by Toshiba in 1989. It has higher erase/write operation speed but has simpler erase circuitry than NOR flash. Based on NAND flash technology, ultra NAND [24] is invented by AMD and Fujitsu. Ultra NAND is compatible with conventional NAND flash, with better reliability and higher storage efficiency. Ultra NAND flash is suitable for high-reliability application, such as SSD. Characteristics and applications of flash memories are listed in Table 13.4. Major NAND flash manufacturers are four IDMs, including Samsung, Toshiba, SK Hynix, and Micron. Among them, NAND flash comes with the highest capacity. It is commonly used in a variety of digital terminal devices. The data content in NAND flash is stored in memory cells, which are characterized as three types, including SLC, MLC, and TLC cells (single-level cell, multi-level cell, and trinary-level cell). Numonyx (acquired by Micron in 2010) produced floating gate structural NAND flash made in SLC and MLC type and is capable of write and erase for 105–106 cycles count. SLC, MLC, and TLC NAND flash characteristics are compared in Table 13.5. In advanced technology process node, the oxide layers in NAND flash become thinner and consequently weaken the reliability of the NAND flash. Without moving to more advanced technology, 3D NAND flash memory (3D NAND) can expand capacity from planar NAND flash by stacking memory array layers. Memory vendors launched variable 3D flash, e.g., V-NAND (vertical NAND) developed by Table 13.4 Characteristics and applications of flash memories Type NOR flash

NAND flash

EEPROM flash

Characteristics eXecuted In Place, high reliability, fast random access read/write operation, slow block read/write operation, byte writable but not byte erasable Fast block-write operation, bad block management, low cost, slow random access read/write operation, no byte read/write operation, driver required Combination of EPROM and NOR Flash. faster random access read operation than NOR Flash, fast read/write operation, lower cost than EPROM

Applications Suitable for smaller capacity application, such as BIOS memory in PC Suitable for high-capacity application, such as SSD

Suitable for small capacity. Replacing EPROM, such as MCU programming code memory

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Table 13.5 SLC, MLC, and TLC NAND flash performance comparison Type SLC MLC TLC

Bit number per cell 1 bit/cell 2 bit/cell 3 bit/cell

Erase/write life time 105 cycles 3
103 – 104 cycles 5
102 cycles

Features High speed, long lifetime, high cost Intermediate speed, life time, and cost Low speed, short lifetime, low cost

Samsung, and bit cost scaling (BiCS) 3D NAND co-developed by Toshiba and SanDisk [25]. 3D NAND technology has been a research hotspot since 2017. Samsung, Toshiba, Western Digital, Micron, and SK Hynix strengthened investment in the development of 64- and 72-layer 3D NAND. The first 3D flash was launched by Western Digital in June 2017. The 128-Layer 3D NAND was in production in 2021 at YMTC, followed by the 192-layer 3D NAND Flash in 2022.

Solid-State Drive Solid-state drive (SSD) is mainly composed of controller, nonvolatile memory (NVM), and circuit board. NAND flash is primarily adopted as NVM in SSD. Compared with hard disk drive (HDD), SSD takes advantages in better vibration tolerance, lower power consumption, no noise, and higher speed. The capacity of SSD exceeds HDD. However, the price of SSD is slightly higher than HDD of the same capacity. SSD is applied to four major fields. The first one is the consumer electronics market, including applications in laptop, desktop, and all-in-one computer. The second field is embedded systems including car PC (or vehicle PC), industrial PC (IPC), and advertising player (computer). The third is the enterprise and data center application in server and storage array. The last one is the application for military, aviation, or medical use. There are several type interfaces of SSD to choose from, including fiber channel (128 Gbit/s for server), PCIe (PCI Express, Gen3 X4, 31.5 Gbit/s), USB (10 Gbit/s), and serial attached SCSI (SATA, 12 Gbit/s for server) [26]. In the consumer electronics market, SATA is commonly adopted, but PCIe is gradually widespread. In the enterprise and data center market, SATA and PCIe are dominant. With the development of PCIe Gen3 X4, PCIe gradually dominant SSD interface in the server due to its higher transmission rate. Each SSD contains an embedded processor as a controller, which integrates memory and interface circuits. The development of IC packaging technology and the trend of slimmer handheld devices push more on SSD to adopt small size BGA package. PCIe SSD usually adopts BGA package compliant with PCI-SCG standard. It usually come with 11.5 mm
13 mm, 16 mm
20 mm, 22 mm
24 mm, 22 mm
28 mm, and 28 mm
28 mm. BGA SSD simplifies PCB and reduces the cost by integrating controller and flash memory. Compared with conventional 2.5 in HDD, BGA SSD is

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smaller in volume and area. Therefore, BGA SSD can fulfill the storage requirement of tablet, Ultrabook, and server by saving space and power. In 2016, enterprise SSD reached 20 PB (petabyte) in capacity and protected data with redundant array of independent disk (RAID) functionality. Samsung, Toshiba, and Micron pushed SSD to higher capacity and started mass production of 64-layer 3D NAND in 2017.

Multimedia Card and Embedded MMC Multimedia card (MMC) was released in 1997 by SanDisk and Siemens. In 1998, 14 companies jointly established the MMC Association (MMCA), which is currently managed by JEDEC [27]. MMC is mainly used for digital video, music, smartphones, PDAs, e-books, toys, and other electronic products. Like the SD card, the MMC is compatible with the same connector slot. There are many types of MMC, for example, reduced size (RS)-MMC. The size is about half of the MMC, similar to the MiniSD card. Early MMC used pluggable design, but it is with low capacity, performance, and having reliability issues. MMC package type is also used for embedded multimedia card (eMMC); see Fig. 13.5. Defined by JEDEC in early 2019 [28], the latest standard v5.1A for eMMC is specifically designed for embedded memory devices, primarily used for tablet pads or iPads, smartphones, smart TV boxes, educational electronics, etc. As eMMC is using Surface Mount Technology (SMT) package, so it is highperformance reliable storage devices. Inside the eMMC are a logic control chip and a few flash (NAND flash) chips. It is integrated in a JEDEC standard BGA package [29], as shown in Fig. 13.6. The functions of the logic controlling chip include (1) providing a standard eMMC interface for managing the flash memory chip, which is used for receiving external data from the eMMC interface, writing to the flash chip; (2) reading data from the flash chip and transmitting it to the external device via the eMMC interface [30].

Fig. 13.5 Package form of eMMC

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Fig. 13.6 Logic components of eMMC

Table 13.6 Comparison of MMC and eMMC Feature Components Dimensions

MMC MMC controlling chip and flash chip MMC: 32 mm
24 mm
1.4 mm RS-MMC: 24 mm
18 mm
1.4 mm

Types of capacity Applications

128 MB, 256 MB, 512 MB, 1 GB, 2 GB Early digital camera, functional mobile phone, or basic smartphones

eMMC eMMC controlling chip and flash chip 11.5 mm
13 mm
1.0 mm (153球) 12 mm
16 mm
1.2 mm (169球) 12 mm
18 mm
1.2 mm (169球) 14 mm
18 mm
1.4 mm (169球) 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB Android mobile phone

The major manufacturers of NAND flash are Samsung, Toshiba, SK Hynix, Micron, etc., but their products are not compatible with each other. The memory driver should be re-deployed following each technical characteristics or performance of different NAND flash specifications. While for eMMC (Table 13.6) products, the users only need to follow standard interface to control flash memory, the standard interfaces for MMC and eMMC have contributed greatly in reducing the development difficulty and in speeding up the time to market. The eMMC can also manage both MLC NAND flash and TLC NAND flash very well. The firmware program in the controller can be implemented with “error correcting code (ECC),” “block management,” “wear leveling,” “command management,” “low power management”, etc. Equipment manufacturers only assemble eMMC to PCB board and load standard driver; then, it will work well. There is no need to solve compatibility and management issues. Therefore, eMMC has replaced NAND flash and became the main memory solution for smart electronic products such as smartphones and tablets.

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In February 2015, JEDEC released the eMMC Product Standard 5.1 Edition (eMMC v5.1). The JESD84-B51 defines a new standard for embedded high-capacity flash drives that are widely used in smartphones and other mobile devices. To enhance the end-user experience, the new version of eMMC provides command queues for the first time and improves security.

Multi-Chip Package Memory and eMCP Memory Multi-chip module (MCM) is also called by national semiconductor multi-chip package (MCP) memory, and it is a kind of memory package, where multiple memory chips are contained in one package [31], while embedded multi-chip package (eMCP) memory is a hybrid product that combines MCP memory and eMMC memory together. The chip types included in the MCP memory can be NOR flash, NAND flash, low power DRAM, and pseudo-static RAM (PSRAM). The main purpose of using MCP memory is to save PCB size, as smart handheld and wearable devices have driven the MCP memory technology toward that goal. There are two kinds of memory chips in the BGA (MCP package), and the chips are arranged side by side. Depending on the size and number of internal memory chips, some MCPs may also be stacked on each other (i.e., top–bottom stacks), or stacked side by side. MCP memory can increase PCB placement density, improve system performance, reduce PCB board and system-level size, improve system quality, enhance system functionality, reduce PCB routing complexity, improve memory high-speed performance, and solve signal integrity (SI) issues. MCP supports flip chip, wire bonding, and SMT process; it also supports Package on Package (PoP) process. The application of MCP memory is mainly tablet, wearable electronic products, and smartphones. These products not only have high requirements on smaller dimensions, but also have high requirements for avoidance of SI issues. MCP uses the SiP method to integrate different specifications of the chip into a single package. It has the advantages of short production cycle, low manufacturing cost, low power, and high-speed transmission. It is the most important specification for the built-in memory of portable electronic products. Various types of MCP have also been widely used in digital TVs, set-top boxes, and network communication products. The main package types of MCP memory are WFBGA, VFBGA, LFBGA, PoP, etc. Since the internal memory includes a plurality of types of memory, each of the chips has different uses, so the capacity cannot be added simply, and the storage capacity is separately listed in different types. Typically, the industry denotes or defaults to putting flash (NAND or NOR) capacity in front and DRAM capacity in the back. For example, if an MCP consists of an 8 GB NAND flash and two 2 GB LPDDR2s, its capacity should be labeled 8 GB þ 4 GB. The key to the development of MCP technology is the control of thickness and yield. More chips stacked on the MCP then make MCP thicker, but portable

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electronic products such as mobile phones (especially ultra-thin electronic products) require as thinner as possible, as well as to avoid production difficulties. The thickness defined by the MCP chip at birth is about 1.4 mm (currently 0.8 mm). If one of internal chip fails, the entire module will fail. With the development of technology, the size of MCP cannot meet the requirements of some devices, so there is a through-silicon via technology, referred to as TSV technology. TSV is a new vertical packaging technology for interconnecting stacked chips in 3D integrated circuits [32]. It can optimize the density of chip stacks, interconnect between chips, external dimensions, and improve signal transmission and low power performance. The advantage of TSV technology is to further reduce the package size and increase the space for product design. TSV offers excellent high-frequency characteristics, reduction in transmission delay, and noise reduction as well. So, it can meet higher speed design requirements. TSV also can reduce the power of chip up to about 40% and has the advantages of low thermal expansion coefficient and high reliability. The eMCP memory is a hybrid memory package that combines MCP and eMMC features, as shown in Fig. 13.7. The current mainstream eMCP adds mobile DRAM (LPDDR1/LPDDR2/LPDDR3/LPDDR4) to the eMMC architecture. It meets JEDEC standard and use the MCP package type [33]. Compared with the traditional MCP, the eMCP has more eMMC control chips. An eMCP control chip manages its large-capacity NAND flash memory and reduces the computational burden of the chip; because of its smaller size, it reduces the number of circuit connection designs, facilitates compatibility debugging and testing, and thus facilitates the design and production of smartphone manufacturers. The eMCP has the same size as the eMMC in the size of 11.5 mm
13 mm
1.0 mm (ultrathin size is 11.5 mm
13 mm
0.8 mm). When eMCP assembled eMMC and DRAM together, it created large capacity, yet it also results in some difficulty to design – because it might have introduced signal crosstalk and more performance issues. Normally, the larger capacity needs more chips; however, more chips lead to lower yield; hence, lower yield results in higher cost. Therefore, the consequence of the impacts has become the difficulties for eMCP to serve the high-end market. The scope and difference of mainly MCP and eMCP in mobile phones are shown in Table 13.7 [34]. Fig. 13.7 Structure and package form of eMCP

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Table 13.7 Applications and differences of MCP and eMCP in mobiles phones Types Components Packaging

Storage capacity

Applications

MCP NOR flash+LPDDR2 or NANDF flash+LPDDR2 8.0 mm
9.0 mm
1.0 mm (130 solder balls) 10.5 mm
13.0 mm
1.0 mm (137 solder balls) 10.5 mm
8 mm
1.0 mm (162 solder balls) 2 GB þ 2 GB 4 GB þ 2 GB 4 GB þ 4 GB

Functional mobile phone or low-end smartphones

eMCP NAND flash+eMMC controlling chip+LPDDR3 11.5 mm
13 mm
1.0 mm (162 solder balls) 11.5 mm
13 mm
1.0 mm (221 solder balls)

8 GB þ 4 GB 8 GB þ 8 GB 16 GB þ 16 GB 32 GB þ 24 GB 64 GB þ 32 GB 128 GB þ 32 GB Mid- or low-end mobile phone

Typical features of eMCP memory are the ability to implement more powerful functions through chip integration: (1) increased design density and performance, (2) reduced board and system-level size and quality, (3) reduced PCB board area, (4) reduced PCB routing complexity, (5) reduced additional cost of using other chips in PCB board level, (6) reduced time to market, and (7) reduced product design difficulty. With the development of 3D NAND flash and LPDDR4 standard, eMCP will become larger and faster. In view of the features of eMCP memory, they are used not only in mainstream portable electronic products such as smartphones but also are used in many other consumer electronic products or devices that require data storage.

X86 Processors X86 Instruction Set Architecture (ISA) first appeared in the 8086 CPU of the 16-bit processor that Intel introduced in 1978, and the 8086 CPU evolved from the early Intel 8008 CPU. Since IBM started working with Intel to launch a PC-based 8086 CPU, it has achieved great success in the market, which has made the x86 architecture a PC standard platform and is recognized as the most successful CPU architecture. The term “x86” came from the names of several successors to 8086 processor ending in “86,” including the 80,186, 80,286, 80,386, and 80,486 processors. In addition to Intel, there were other companies that originally design x86 architecture processors, but most of the companies lost in the market competition with Intel and gradually abandoned. The only competitor in x86 architecture processors with Intel is AMD. In 1985, Intel introduced the 80,386 CPU based on 32-bit, which extended the x86 architecture digits and improved the performance of the CPU. The x86 is well

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known as the complex instruction set computer (CISC) architecture with variable instruction lengths. The CISC block (word, 4 bytes) is stored in the corresponding memory in the order of the low byte first and the high byte after, and the memory allows the address not to be aligned when the access is called [35]. Compared with other common ISAs, such as reduced instruction set computer (RISC) and explicitly parallel instruction computing (EPIC), CISC does not have obvious advantages, and even many computing experts believe that CISC is not efficient. Forward compatibility is both a major force driving the development of x86 and a major historical burden that plagues the performance of x86. New version of Intel x86 architecture, which converts x86 instructions into RISC-like microinstructions, is then executed to achieve comparable performance with RISC while still supporting forward compatibility. By 2002, due to the 32-bit digital length limitation, x86 began to reach the theoretical limit of design. When dealing with data storage larger than 4 GB, it would be difficult and inefficient, especially for database and video processing applications. This limitation is more apparently exposed. Intel has decided that the new Itanium processor will adopt the new x86 for 64-bit architecture (IA-64) and will abandon the forward compatibility feature, but IA-64 is inherently incompatible with x86 software, and it can only run x86 software in a variety of analog or virtual ways. Obviously, this kind of support will occupy the corresponding computing resources of the processor, resulting in very inefficient operation and affecting the operation of other parallel programs. AMD used a completely different strategy, inherited and developed the x86 architecture, and expanded the x86 architecture to 64-bit (named AMD-64) based on the 32-bit x86 architecture (or IA-32), and AMD introduced the first 64-bit x86 CPU product based on AMD-64 architecture, including the single-core Opteron and the Athlon 64 processor family in 2003 [36]. AMD-64 meets the customer’s requirements for computing digits and computing power. Since AMD introduced the 64-bit x86-based CPU in the market before Intel, due to Microsoft’s compatibility with operating systems, Intel was forced to adopt the AMD 64 instruction set and added some new instructions based on it. The instructions are extended to their own 64-bit architecture, and Intel using the name EM64T. EM64T was officially renamed Intel 64 (also known as x86-64, x64, x86_64) due to marketing reasons [37]. X86 was extended from 32 bit to 64 bit and was first promoted and launched in 1999–2000 by AMD, not Intel. This major improvement and upgrade made AMD a very good success in the market at that time, once able to compete with Intel. The main products of the x86 architecture-based processors introduced over the years are shown in Table 13.8. The x86 family of processors is very successful, and it is widely used in PCs, servers, workstations, and other fields. Currently, PCs that dominate the market (including Apple MacBook series) are using x86 architecture processors, but Google Chromebook partially uses ARM architecture processors. CISC-based x86 ISA from Intel theoretically limits CPU perform further. To maintain its leading position in the

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Table 13.8 Main products of x86 architecture-based processors introduced over the years Introduction 1978 1982 1982 1985 1989 1992 1993 1995 1996 1997 1998 1999 2000 2001 2003 2004 2005 2006 2007 2008 2009 2010 2011 2011 2011 2011 2012 2013 2015/2016

Prominent CPU models Intel 8086, Intel 8088 (1979), and its derivatives Intel 80,186, Intel 80,188 and its derivatives, NEC V20/V30 Intel 80,286 and its compatible products and their derivatives Intel 80,386 and its compatible products, AMD Am386 (1991) Intel 80,486 and its compatible products, AMD Am486 (1993) Cyrix Cx486SLC, Cyrix Cx486DLC Pentium, NexGen Nx586 (1994), Rise mP6 (1998) Pentium Pro, AMD Am5x86, Cyrix 5x86 Pentium MMX, AMD K5, Cyrix 6x86/MII, Centaur IDT-C6, VIA Cyrix III (Samuel 2) Pentium Overdrive, Pentium II, AMD K6 Celeron, Xeon, AMD K6-2 Athlon, Athlon XP (2001), Pentium III, AMD K6-III Pentium 4, Cyrix III-Samuel, Transmeta Crusoe Itanium IA-32, VIA C3 “Ezra” (C5C), Transmeta Efficeon Pentium M, AMD Athlon 64, Opteron AMD Sempron, Prescott Prescott 2M, Pentium D, VIA C7 Intel Core Solo/Duo DM&P Vortex86, Athlon 64 X2, AMD Phenom Intel Core i7 (Nehalem/Westmere), AMD Phenom II, VIA Nano, Intel Atom Intel Core i5 Intel Core i3 AMD FX, AMD APU C, E, and Z series (Bobcat) AMD APU A and E series (Llano) AMD APU A series (bulldozer, trinity and its derivatives) Intel Core i3, Core i5 and Core i7 (Sandy Bridge/Ivy Bridge) Intel Xeon Phi (Larrabee) Intel Core i3, Core i5 and Core i7 (Haswell/Broadwell) Intel Core i3, Core i5 and Core i7 (Skylake/Kaby Lake/ Cannon Lake)

Linear address/bit 16 16 16 32 32 32 32 32 32 32 32 32 32 32 64 64 64 64 32 64 64 64 64 64 64 64 64 64 64

market, Intel not only improves the performance of x86 through advanced technologies, but also does a lot of optimization and improvement on x86.

IA-64 Processors The IA-64 processors were the abbreviation of Itanium architecture processor in the beginning, which supports 64-bit processing. However, due to the lack of market recognition of Itanium processors, Intel must launch a new Intel architecture, which

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is compatible with x86–64 instruction set. The IA abbreviation usually refers to Intel architecture processor at present. The IA-64 was created by Hewlett-Packard (HP) in 1989 [39]. HP thought both CISC and RISC architectures have some drawbacks. RISC executes only one instruction during each CPU cycle, while CISC architecture is designed to execute multiple instructions under one clock, but it needs a high-performance decoder to decompose instructions into RISC-style microinstructions. HP has proposed a new architecture named explicitly parallel instruction computing (EPIC). It is composed of three instructions into a single–instruction package using very long instruction word (VLIW). Each instruction package contains a series of RISC instructions that can be executed concurrently, which makes EPIC a great potential to replace the other two architectures, but as a system company, HP does not have the ability to develop processors independently. So, in 1994, HP cooperated with Intel to develop EPIC-based processors. In 1999, Intel renamed the processor to Itanium processor. At the beginning, Intel and Hewlett-Packard believed that IA-64 would become the mainstream of the future computer server, workstation, and high-performance computer market. Although the EPIC instruction set is incompatible with x86 architecture processor, while the IA-64 processor has 64-bit data path, 64-bit storage space, and 64-bit parallel computing capability, which breaks through many limitations of traditional 32-bit architecture. These improvements are expected to greatly improve the efficiency of data processing, stability, security, availability, and manageability of the system. Many companies are attracted by the potential of IA-64 and decide to join the EPIC architecture group. Compaq (acquired by HP in 2001) and Silicon Graphics (acquired by HP in 2016) decided to abandon DEC alpha and MIPS architectures and changed to develop IA-64 instead. At the same time, the operating systems based on IA-64 have been developed one after another, including HP-UX (Hewlett-Packard Unix), Solaris (Sun Microsystems, acquired in 2010 by Oracle), Tru64 UNIX (owned by DEC, Compaq, then HP), and Project Monterey (IBM and others). However, IA-64 processor requires lots of transistors for ultra-long instruction words and many caches, which seriously affects the overall performance of the processor. Therefore, when the first generation of Itanium processor was introduced in 2001, their performance was inferior compared to that of RISC and CISC processors of the same generation. In addition, there are many problems in the research of IA-64 processor compiler, which delayed in the progress of development. However, the most important reason for IA-64 architecture failure is incompatibility with x86 instruction set, which requires developers to re-develop programs and create new ecological environment. Meanwhile, as a competition, AMD added 64-bit register based on the x86–32-bit architecture and worked out the AMD-64 architecture processors, which are compatible with 16-bit and 32-bit software forward, which allows the early x86 compiler be used in AMD-64 architecture processors [38]. The good compatibility of AMD-64 architecture led operating system manufacturers to gradually abandon their support for the IA-64 architecture. Oracle and Microsoft quit the IA-64 camp in 2011 and 2013.

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Facing the rapid development trend of AMD-64 architecture and the pressure from software industry, Intel obtained the authorization of AMD X86–64 extended instruction set by cross-licensing with AMD and developed the Intel 64 architecture, namely x86–64 architecture.

POWER Family Processors In 1974, John Cocke and his team at IBM Research began work on designing a controller for telephone exchange, and the project was leading to the first prototype reduced instruction set computer (RISC) in 1980 [39], based on CYK algorithm. The RISC architecture design enabled computers to execute computing tasks with the simplest instructions and execute each instruction per clock cycle or a few clock cycles, which will enable computers run much faster and more powerful. In 1990, the first CPU from IBM that incorporates the Performance Optimized With Enhanced RISC (POWER) instruction set architecture (ISA) was introduced into the market and called POWER1 CPU [40]. In 1993, IBM announced the POWER2 processor, which had leadership performance at that time. In 1998, IBM announced that the POWER3 processor, a 64-bit symmetric multiprocessor, supports 32/64-bit both PowerPC ISA and POWER ISA. The subsequent POWER family microprocessors are all 32/64-bit architectures. In 2017, IBM launched the latest POWER-based microprocessor POWER9. POWER9 is manufactured with a 14 nm FinFET process and the performance is much more powerful than those of x86 processors, POWER10 was made in 7 nm, and POWER11 is being forecasted. POWER architecture products are summarized in Table 13.9. IBM POWER-based server microprocessors are mainly built for high-end server market. Comparing the POWER processor with x86 processor, the former takes the advantages in data-intensive and high-performance computing. In hardware, Table 13.9 Summary of POWER architecture products Release year 1990 1993 1998 2001 2004 2007 2010 2013 2017 2020

Product POWER1 POWER2 POWER3 POWER4 POWER5 POWER6 POWER7 POWER8 POWER9 POWER10

CPU frequency 25–62.5 MHz 55–71.5 MHz 200 MHz 1.1–1.9 GHz 1.5–2.3 GHz 3.6–5 GHz 2.4–4.25 GHz 2.5–5.0 GHz 4 GHz >4 GHz

Technology 1.0 μm 0.25 μm 0.22 μm 0.18 μm/0.13 um 0.13 μm/90 nm 65 nm 45 nm 22 nm 14 nm 7 nm

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POWER architecture uses symmetric multi-processing (SMP), which makes multiple processors work in parallel and use a single operating system and share the common memory and I/O resources. POWER architecture is modular and scalable with increasing the CPU numbers, and the performance will be higher. In software, IBM AIX operating system is secure, scalable, and robust. Many featured software and tools work on POWER system. The x86 servers market share is about 90% with three main reasons. First, the x86 server ecosystem has more than 30 years of development; it is robust and costeffective. Second, the business computing model such as cloud computing will provide competitive services in existing server market, which are going to replace minicomputer. Third, IBM competes with others on chip, system, and server market, while x86 chip vendors as Intel or AMD are focused to provide the chips and corporate with others. In 2013, Google, IBM, Mellanox, Nvidia, and Tyan announced to form the OpenPOWER Foundation. IBM opened up POWER technologies, include chip specifications, microcode and software, and enable third-party vendor join the ecosystem for POWER and build customized hardware. Currently, Google, IBM, Inspur, and Yadro are platinum members of OpenPOWER [41]. To compete with Microsoft and Intel in PC and low-end workstation market, Apple–IBM–Motorola formed an alliance known as AIM in 1991. They developed Performance Optimization With Enhanced RSIC-Performance Computing (PowerPC) architecture, which is based on IBM POWER ISA [4]. In 1993, IBM released the first-generation single-chip PowerPC processor, which is a high–performance superscalar microprocessor, supports 32-bit address bus and 64-bit data bus, and supports 32-bit integer operations and IEEE 754, single- and double-precision floating-point operations, and SMP features. From 2006, PowerPC could be licensed to third-party companies and allow them to design and manufacture the compatible processors. PowerPC has three main product lines, 32-bit PowerPC 700, 64-bit PowerPC, and embedded PowerPC 400 [42]. PowerPC is energy-efficient, ecosystem is limited and slowly updated, and it cannot compete with x86 system. In 2005, Apple adopted a new x86 processor indicating PowerPC failed partially in PC market. Nevertheless, PowerPC is still used in automotive, aviation, and networking.

MIPS Processors Microprocessor without Interlocked Pipeline Stages (MIPS) processor is one of the popular RISC architecture processors that can avoid the conflict and risk of pipeline by software. John L. Hennessy team of Stanford University researched and developed MIPS processor in 1981 and founded the MIPS Computer Systems in 1984.

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Fig. 13.8 Classification of MIPS architectures

The first 32-bit MIPS processor named R2000 was released in 1985 and then released 64-bit processer R4000 in 1991. The series of processors were widely used in SGI workstations, DEC workstations and servers, and other computer systems during the 1990s [43]. There were two MIPS architectures: 32 bit and 64 bit, as showing in Fig. 13.8. Many versions of MIPS ISA existed, such as MIPS I, MIPS II, MIPSIII, MIPS IV, MIPS V, MIPS32, and MIPS64. Both MIPS32 (32 bit) and MIPS64 (64 bit) define a set of control registers and instruction sets, and there are some extensible instruction options available to be selected, such as MIPS-3D [44–46]. MIPS is a module-based architecture, which supports four coprocessors (COP0/1/ 2/3). In general, COP0 is defined as system control coprocessor. COP1 is a floatingpoint unit (FPU). COP2 and COP3 are undefined selected coprocessors. For example, in early PS game machine from Sony, COP0 was defined as system control coprocessor, and COP2 was used as geometry transfer engine (GTE), while at PS2 product, COP0 is R5900 chip design by Toshiba, COP1 is defined as FPU, and COP2 was used as VPU0. MIPS processor was the hotspot of RISC CPU design and widely used in the mid-1980s. About one-third of RISC microprocessors were based on MIPS architecture in the mid- to late 1990s; it was the most competitive RISC CPU architecture in the market at that time. Today, there are three architectures compete against each other: ARM RISC architecture, MIPS RISC architecture, and x86 CISC architecture. MIPS architecture processors were mainly used in the embedded system, router, Internet gateway, media game control center, and other application fields. MIPS Technologies, Inc., was merged by Imagination Technologies Group plc in 2013, and MIPS architecture thus continued. For example, Loongson processor was based on MIPS architecture and be used at Shuguang 6000 supercomputer.

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ARM Processors Acorn RISC Machine (ARM) was the first RISC microprocessor designed in 1985 by Acorn Computers Ltd. in Cambridge, England (founded in 1978). Spun off from Acorn Computers Ltd., advanced RISC machine was established in 1990. ARM Holdings has been a new name at its IPO in 1999 [47, 48]. ARM processors have general characteristics of the RISC architecture. For example, fixed length instruction format, single-cycle command pipelining operation, using many registers, data processing instruction just deal with registers. Only load/store instruction can access memory to improve the efficiency of the operation of the instruction. Early ARM processors support simple instruction set, and they have features of low power and low cost and suited for mobile device and widely used in embedded systems. From ARMv4 (ARM7 series), the performance focused on power-sensitive wireless devices; from ARMv7, the applications have extended to other areas. After Cortex-A9, the performance of ARM processors improved a lot, and gradually used in enterprise devices and servers. The new ARMv8 architecture ARM64 is suitable for the application of large memory, virtualization, security, and ARM development [49]. Table 13.10 lists the technical features, application scenarios, and processor names of the latest CPU architecture Armv7 and Armv8. Table 13.11 lists the release time, versions, names, and applications of the ARM AMBA buses. According to application domains, ARM products can be divided into A, R, and M series. For example, Cortex-A series can be widely used on wireless devices, network infrastructure, home and consumer electronics, in-vehicle infotainment (IVI), and other embedded systems. Cortex-R series can be used in medical equipment, aeronautics, and astronautics, because of their high reliability and high security. Cortex-M series are developed for Internet of Things (IoT), and they belong to smart embedded application processors, which can work efficiently and easy to use. Through coding effort for standard safety system and open platform, Cortex-M can help the designers to develop many kinds of market demanded products in a short time with lower cost.

Table 13.10 Features and applications of ARM processors Architecture Armv7-A Armv7-R Armv7-M Armv8-A Armv8-R Armv8-M Armv9.0-A

Features A32(32b) T32(32b,16b mixed) 32b 32b 32b/64b 32b 32b (16b) 64b

Applications Multicore design

Processors Cortex-A5/A7/A9; A17

High performance Low power Smartphones MMU, MPU MCU/loT AI/IoT

Cortex-R4/R5/R7 Cortex-M0/M0+/M3/M4/M7 Cortex-A53/A57/A72 Cortex-R series Cortex-M0/M0+/M3/M4/M7/m Cortex-A510/A710/A715/X2/X3 etc.

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Table 13.11 Release time, versions, features, names, and applications of ARM AMBA Bus Year of release 1996

Version AMBA

Bus/ Interface ASB, APB

1999

AMBA2

AHB

2003

AMBA3

AXI, ATB

2010/11

AMBA4

AXI4, ACE

2013

AMBA5

CHI

Full name Advanced system bus, and advanced peripheral bus High-performance bus Advanced extensible interface, advanced trace bus Advanced extensible interface 4, AXI coherency extensions Coherent hub interface

Application examples

A7, A9, Cortex-M Series Cortex-A Series, Include Cortex-A9 Cortex-A Series, Include A7/15 Languages, etc. Support (Verification) VIP, SystemVerilog

UltraSPARC Processor UltraSPARC architecture is based on RISC ISA, originally developed at Sun Microsystems aimed at high-end applications; the initial version was the Scalable Processor ARChitecture (SPARC), one of the superscalar instruction sets. To increase its adoption and expand its ecosystem, Sun authorized several vendors to use, which included TI, Cypress, and Fujitsu; later fully opened up to any company, organization, or individual to develop SPARC-based processor or other products, as long as they are authorized to. The design goal of SPARC processor [50] was for increased efficiency of the compiler, easy to implement the HW pipeline instructions, and thus to increase operational and executable speed, such that to help users to reduce time and period of the product development. Due to the provided scalability and benefit of cost efficiency, the technical specifications of SPARC can be used as embedded, or CPU of servers. There were three important revised versions of SPARC, viz. 32-bit SPARC V7 in 1986; 32-bit SPARC V8 in 1990; and 64-bit SPARC V9 [51] in 1993. All of these were forward compatible. SuperSPARC [52] is based on SPARC V8 ISA, developed in 1992 by Sun and fabricated by TI in Japan. SuperSPARC had two derivatives: SuperSPARC+ and SuperSPARC-II, and the later was replaced in 1995 by UltraSPARC. SPARC64 V (Zeus) was based on SPARC V9 and designed by Fujitsu [53]. The SPARC64 V became the basis for a series of successive processors designed for servers and later supercomputers. The server series are the SPARC64 V+, VI, VI+, VII, VII+, X, X+, and XII. As of October 2017, the SPARC64 XII is the latest server processor, and it is used in the Fujitsu and Oracle M12 servers. Based on SPARC V9 ISA, UltraSPARC was developed in 1995. UltraSPARC III chip first appeared in June 1999. Adopted Visual Instruction Set (VIS), it supported 64-bit, clock 600 MHz, fabricated on then advanced 0.18 μm process. The obvious

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feature was that it supports up to 1000 processors of the same type for a co-processing; the highly expandability is most suitable for large server, providing high-performance computing; and for workstations as well. In 2006, Sun announced the new specifications of UltraSPARC, named as UltraSPARC Architecture 2005 [54]. UltraSPARC Architecture 2005-based processors are mainly for workstations, for example, Sun and Fujitsu designed SMP servers. Specifically, Sun developed Solaris OS for UltraSPARC, and others, such as NeXTSTEP (NeXT Computer), Linux, FreeBSD (Berkeley Software Distribution), OpenBSD, and NetBSD systems also provided OS for SPARC versions. Sun promoted several 64-bit UltraSPARC III processors, which were succeeded by UltraSPARC IV processors. UltraSPARC IV+ had a clock frequency of 1.5 GHz. In 2009, Oracle Corporation acquired Sun Microsystems and continued to promote HPC processors. Oracle published in 2007 the Roadmap of SPARC and its related Solaris.

C-SKY Processors C-SKY architecture-based processors, with independent intellectual property (IP) of local 32-bit series-embedded CPU cores, are developed by C-SKY Microsystems founded in 2001 [55]. Users have option to design their own processor based on the C-SKY V2-independent instruction architecture, configured by different hardware units, tailored to their needs. C-SKY processors (CK products) have experienced two stages of development: 1) adopted SIMCODE instruction set to develop two embedded CPUs (CK510 and CK610); 2) developed its own instruction set from 2004. Alibaba Group Holding [56] acquired C-SKY Microsystems in 2018. According to market needs, C-SKY processors are divided into series of low cost, low power, and medium performance, such as CK801, CK802, and CK803, and series of high efficiency, high performance, and high computing power, such as CK610, CK807, CK810, and CK860. The technical features of CK-CPU series are listed in Table 13.12. Focused on various technical sectors, C-SKY processors are applied in specific fields (expressed as tailorable hardware function module), mainly in the following Table 13.12 Features of CK-CPU products Features Instruction width, bit Pipeline Issue width Memory management General register, bit Performance, DMIPS/MHz

CK610 16 8-stage Dual MMU 16 þ 16 1.78

CK810 32/16 8-stage Dual MMU 32 þ 16 2.5

CK807 32/16 8-stage Dual MMU 32 þ 16 2.0

CK803 32/16 3-stage Single MPU 16 1.5

Remark: Dhrystone million instructions executed per second (DMIPS)

CK802 32/16 2-stage Single MPU 16 1.0

CK801 32/16 2-stage Single MPU 8 0.7

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four aspects. (1) Security: CK-CPU can be applied to debit cards security, where CPU technology with the highest level of confidentiality is a must, as well as to the sensitive information and code isolated by trusted execution environment (TEE) technology, to application signature and to accelerated password algorithm. The security technology of CK-CPU covers such fields as resistance to time attack, differential power analysis, error injection resistance, and resistance to buffer overflow. (2) High-efficient computing: CK-CPU offers highly efficient computing ability through configured vector engine for multimedia, digital signal processing (DSP) engine and floating-point unit (FPU), and other hardware units. CK-CPU can enable extra computing power and perform common operations such as Fourier transform, trigonometric functions, and various filters, to allow these computing tasks more convenient and efficient. (3) Storage subsystem: CK-CPU supports cache, scratch-pad memory (SPM), and storage enhancement, and CK-CPU enhances the software operating efficiency. (4) Multicore: It supports symmetrical and asymmetrical multicore designs, making C-SKY processors able to deal with more complicated in hybrid and high-level SoC architecture design, and it can maximize its energy efficiency as a central processor. CK-CPU processors are equipped with processor design and verification platform, compiler and debugger, embedded operating system, C-Sky Development Suite (CDS), and CDK (C-Sky Development Kit), and support mainstream embedded operating systems, such as Alibaba YunOS, FreeRTOS, uCos, and eCos. These are useful for SoC designs to adopt CK-CPU for both hardware and software developments. Gradually, CK-CPU series processors are being widely used in China, and their product forms are diversified and scalable, to be further applied in SoC security and cloud services infrastructure.

Graphics Processing Unit (GPU) A graphics processing unit (GPU) [57] is an accelerator-type of ASIC design that used to create and process 2D/3D graphics operations and output data to display devices. Before the term GPU has been widely used, many ASICs are designed as accelerate engine for 2D graphics or limited 3D graphics operations. In 1999, Nvidia announced the GeForce 256 as “the world’s first GPU” [58]. It was defined as a “single-chip processor with integrated transform, lighting, triangle setup/clipping, and rendering engine, which can process over 10 million polygons per second” [58]. ATI Technologies created the term “visual processing unit” (or VPU) with the release of the Radeon 9700 in 2002, which is similar to GPU [59]. In computer industry, the GPU is a stand-along chip in video card or embedded on the motherboard or as a submodule, which is integrated into central processing unit (CPU). In mobile device, GPU generally is an IP and is integrated into SoC. GPUs are widely used in game consoles, personal computers, workstations, and mobile devices for graphics operation and display. They are also equipped to datacenter and supercomputer for data processing.

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Generally, applications make calls to graphics Application Program Interface (API) and to command GPU computing 3D geometry. A typical 3D GPU will do following operations. First step is the processing of vertex of 3D model, such as transform, and lighting using Vertex Shader. Second step is the processing triangle setup transform vertex of 3D model to 2D-based viewpoint, and the complex polygon will be resolved into triangle and discard the overlap part. Third step is to transform the vectorgram to bitmap, using what is called Rasterizer. Forth step is the use of Pixel Shader to process each pixel, use texture mapping unit (TMU) to find out the pixel texture, and calculate the color and transparency. Fifth step is to use Raster Operations Pipeline (ROP) to do final operations, and the composited images are transferred to fame buffer for display; see Fig. 13.9. In the graphics processing, computing efforts are spent on the large data workloads of vertexes/triangles and pixels/fragments; the modern GPUs are required for real time, high speed, and parallel processing. With the development of architecture, software programmability, and progress of manufacturing process, GPUs are opt to not only work for graphics but also work in general-purpose data processing, the so-called general-purpose computing on GPU (GPGPU) [60]; see Table 13.13. In some type of GPGPUs, the display part is removed and dedicated to data processing only. More and more GPGPUs are installed in supercomputers and highperformance computers and provide them the power to accelerate the data processing. CPUs using very long instruction word (VLIW) architecture can approach instruction-level parallelism (ILP), while GPUs are for data parallelism, a new architecture called heterogeneous system architecture (HSA) [61], is developed to make these various devices work together on the same bus with shared memory and task. The HSA combining CPU and GPU designs is widely used on gaming and entertainment, cloud and data center, self-driving cars, deep learning in AI, autonomous machines, design, and visualization areas.

Fig. 13.9 An example of GPU workflow

GeForce 900 Radeon Rx 200

2015–

2009–2014

2007–2009

2003–2007

2001–2002

Product GeForce 256 Radeon GeForce 3 Radeon R200 Radeon R300 GeForce FX GeForce 8 Radeon R600 Radeon HD5000 GeForce 400

Year 1999–2001

Unified shader/HSA/multithread

Unified shader/ IEEE754 float point Unified shader/CUDA/multithread/ IEEE754 double floating point

Vetex+pixel shader

Vetex+pixel shader

Feature Fixed function pipeline

GAPI DirectX 7/ OpenGL 1.2 DirectX 8/ OpenGL 1.3 DirectX9/ OpenGL 2.0 DirectX 10/ OpenGL3.3/ DirectX 11/ OpenGL4.x/ OpenCL1.1 DirectX 12/ OpenGL4.x/ OpenCL1.2

Table 13.13 Development of parallel architecture and software programmability of GPUs

28 nm–12 nm

40 nm–28 nm

80 nm–55 nm

150 nm–90 nm

150 nm

Process 220 nm–180 nm

Y

Y

Y

Y

Limited

Programmability N

Y

Y

Y

Limited

N

General purpose N

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In the last century, SiS, VIA, S3 Graphics, 3dfx, and Matrox were the vendors in personal computer for 2D/3D cards, and today, Nvidia and AMD are the leading GPU vendors. In mobile device including smartphones and tablets, the GPU products are seeking applications and competing with others such as Imagination, Qualcomm, and ARM. The latest products from Nvidia include high-performance Tensor Core GPU A100 and H100. A100 is manufactured with TSMC 7 nm, containing 54
109 transistors and maximum power 400 W, while to date H100 containing 80
109 transistors can reach a computility of 67 TFLOPS at FP32. It is said that H100 is seven times better than A100 for HPC applications.

Microcontroller Unit A microcontroller (MCU), also called single-chip microcomputer, is a small computer on a single IC [62, 63]. It is believed that TI engineers Gary Boone and Michael Cochran created the first microcontroller TMS 1000 in 1971, which became commercially available in 1974. The TMS1000 family MCU then enjoyed a tremendous success in consumer electronics at that time. The diagram of MCU architecture is shown in Fig. 13.10. The CPU is the core of MCU and is responsible for arithmetic processing and controlling. The memory consists of on-chip program memory and data memory. The memory can be ROM, one-time programmable (OTP), multiple-time programmable (MTP), eFlash, or SRAM, which may appear in various product forms. All the memories can transfer instructions or data by CPU through bus or interface. The direct memory access (DMA) controller is used to transfer data between memory and I/O directly with high speed. The MCU can integrate different interface controllers according to

Fig. 13.10 Diagram of MCU architecture

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applications, such as inter-integrated circuit (I2C) bus, integrated inter-chip sound (I2S), universal asynchronous receiver/transmitter (UART), serial peripheral interface (SPI), controller area network (CAN), universal serial bus (USB), and serial digital interface (SDI). Timer is a basic component in an MCU; it can be categorized into general-purpose timer (GPT), real-time clock timer (RTC), motor control timer, and pulse-width modulation timer (PWM). As a small system-on-chip design, the MCU integrates power, clock, and reset controlling components. Low dropout regulator (LDO) is used for power on/off and reset; oscillator/PLL is responsible for stable, reliable on-chip clock source. There is also power on/off controlling logic to optimize power consumption according to the performance requirement. Besides, the MCU can also integrate ADC, DAC, operation amplifier, or other analog components. The MCU can be classified into 8-bit, 16-bit, 32-bit, or 64-bit series according to the instruction bit width of the CPU. Intel 8051 is a typical 8-bit MCU. A popular 32-bit one is usually with ARM Cortex-M core. MCU provides many kinds of processing performance or operating frequency according to which CPU is used. The 8-bit and 16-bit CPU have more advantage on power consumption and area, but less processing performance, than 32 bit and 64 bit. The MCUs can also be classified into ROM-type, OTP/MTP-type, eFlash-type, according to their memory form. The ROM-type MCU offers low price; however, its program and data cannot be changed after manufacture. The eFlash-type MCU supports million times of reprogramming which is more flexible, but with higher cost. The OTP/MTP-type MCU ranks at medium price, but only supports one time or multiple times of reprogramming; however, it is suitable for products which require some flexibility and are costsensitive. MCU has a wide variety of applications. The 4-bit and 8-bit MCU are mainly applied to radio, telephone, pager, liquid crystal display controller, calculator, vehicle instrument and meter, toy, tire pressure monitor, thermometer, hygrometer, electronic scale, remote controller, electricity meter, facsimile printer, motor controller, household appliance, and industrial control product. The 16-bit and 32-bit MCU are mainly applied to mobile phone, digital camera, digital video, modem, GPS terminal, PDA (personal digital assistant), set-top box (STB), router, laser printer, IoT terminal product, and so on. The 64-bit MCU are mainly applied to multimedia interaction and workstation systems. With the increasing performance of 8-bit MCU and the decreasing price of 32-bit MCU, the boundary of 8-bit and 32-bit product is not that clear and their application market is intersected.

Digital Signal Processor Digital signal processor (DSP) is a kind of special microprocessor, which optimizes signal processing in architecture. The first single-chip DSP was the MAC4 microprocessor developed at Bell Labs in 1979. The first complete DSPs appeared at the IEEE ISSCC (International Solid-State Circuits Conference) in 1980. They were NEC’s uPD7720 processor and AT&T DSP1 (started in 1977) processor. The chip

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Fig. 13.11 Schematics of DSP system

that finally opened up the DSP market was the TMS32010 produced by TI in 1983 [64, 65]. DSP can measure, filter, and compress continuously changing analog signals in the real world. A typical digital signal processing system is shown in Fig. 13.11. The principle of digital signal processing system is to convert the signal (e.g., the sensor signal from audio video) from analog signal to digital signal and carry out effective digital signal operation. The operation of DSP module in a design usually needs to be completed by combined microprocessor chip. Most microprocessors can complete the operation of digital signal processing algorithm, but they cannot be applied to mobile devices and Internet of thing (IoT) devices that require low power consumption. In order to meet the requirements of low power consumption and ensure good performance and fast processing speed, special digital signal processing chips, voice signal processing chips, image processing chips, and visual signal processing chips have been developed for mobile devices [66]. The clock frequency of TI’s C6000 series is 1.2 GHz, and the fastest execution speed is 8000 MIPS. Freescale (merged by NXP in 2015) multicore DSP, each core clock frequency is 1 GHz. XMOS’s multi-threaded DSP execution rate is 400–1600MIPS [67]. CEVA has 16-bit or 32-bit DSPs, single or two MAC DSPs, which can be structured in either super-long instruction or single-instruction data flow. Based on the super Harvard architecture, ADI designs floating-point and fixedpoint DSPs with a mega floating-point operation range of 198–2400 MFLOPS (corresponding frequency of 66–400 MHz). Cadence Tensilica Vision P6 is an image processing chip for computer vision applications that simultaneously supports OpenVX, the vector single-precision floating-point accelerator [68].

RISC-V ISA and RISC-V Processors RISC-V (pronounced “risk-five”) is a free, open-source, extensible instruction set architecture (ISA) that is based on established RISC principles. RISC-V processors are processors implemented on the basis of RISC-V ISA. RISC-V ISA was invented at University of California, Berkeley, by Professor Krste Asanovic, his Ph.D. students Yunsup Lee and Andrew Waterman, and advised by David Patterson, with many more contributors from industry and academia [69]. It emerged at the backdrop of the slowdown of Moore’s Law and Dennard Scaling, when the industry embracing domain-specific architecture (DSA), and customers’ demand for agile and cost-effective custom silicon designs.

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Chip builders choosing RISC-V have the advantage of knowing there are many competing suppliers for RISC-V IP. They can select among multiple commercial RISC-V IP vendors or use an open-source core, or even roll their own. This is even more important for a second-generation chip product, where selecting a proprietary ISA would have led to vendor lock-in or worries about vendor long-term viability. Chip customers will also be assured of many sources of supply for RISC-V parts spanning a wide range of applications. To help prevent ISA fragmentation while supporting customization, RISC-V has been designed to be modular and extensible. RISC-V ISA has a small simple fixed base ISA and modular fixed standard extensions that work well for the large majority of code, while leaving ample space for application-specific extensions that do not interfere with the standard ISA core [70]. The current RISC-V ISA base and extensions are presented in Table 13.14. RISC-V ISA has been designed to have features to increase computer speed yet reduce cost and power use. These include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, simplified standard-based floating point, a design that is architecturally neutral, and placing most significant bits at a fixed location to speed sign extension. Sign extension is said to often be on the critical timing path. The instruction set is designed for a wide range of uses. It supports three word widths, 32, 64, and 128 bits, and a variety of subsets. The definitions of each subset Table 13.14 RISC-V ISA bases and extensions Name Base RV32I RV32E RV64I RV128I Extension M A F D G Q L C B J T P V N

Description

Version

Status

Base integer instruction set, 32 bit Base integer instruction set (embedded), 32 bit, 16 registers Base integer instruction set, 64 bit Base integer instruction set, 128 bit

2.0 1.9 2.0 1.7

Frozen Open Frozen Open

Standard extension for integer multiplication and division Standard extension for atomic instructions Standard extension for single-precision floating point Standard extension for double-precision floating point Shorthand for the base and above extensions Standard extension for quad-precision floating point Standard extension for decimal floating point Standard extension for compressed instructions Standard extension for bit manipulation Standard extension for dynamically translated languages Standard extension for transactional memory Standard extension for packed-SIMD instructions Standard extension for vector operations Standard extension for user-level interrupts

2.0 2.0 2.0 2.0 N/A 2.0 0.0 2.0 0.90 0.0 0.0 0.1 0.2 1.1

Frozen Frozen Frozen Frozen N/A Frozen Open Frozen Open Open Open Open Open Open

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vary slightly for the three word widths. The subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale rack-mounted parallel computers. The instruction set is variable width and extensible so that more encoding bits can always be added. Space for the 128-bit stretched version of the ISA was reserved because 60 years of industry experience has shown that the most unrecoverable error in instruction set design is a lack of memory address space [71]. Due to its open nature and extensible modern design, RISC-V has quickly gained traction across the industry. RISC-V Foundation, initiated by the RISC-V inventors in 2015 and now part of the Linux Foundation, has grown to more than 200 members by June 2019. There is also a thriving group of companies who either license their commercial RISC-V processors cores or open source their core designs, including SiFive, Western Digital, NVIDIA, Andes, Codasip, and many others. By July 2019 when this was written, there are 65 various cores and SoCs that endeavor to implement the RISC-V specification [72].

Field Programmable Gate Array Field programmable gate array (FPGA), also known as field programmable device, is a semi-customized integrated circuit, developed on the basis of programmable devices, such as programmable read-only memory (PROM), programmable logic device (PLD), programmable logic array (PLA), gate array logic (GAL), and complex programmable logic device (CPLD). Therefore, FPGA has the characteristics of hardware programmability. In 1985, Xilinx introduced CX2064, the world’s first FPGA, which uses 2 μm manufacturing process and contains 64 logic blocks (1200 logic gates) [73]. In 2003, Xilinx launched a series of Spartan-3 products with 90 nm manufacturing process, followed by a series of Virtex-5 products with 65 nm manufacturing process and a series of Virtex-6 products with 45 nm manufacturing process. In 2011, Xilinx and Altera (acquired by Intel in 2015) launched a series of FPGA on 28 nm manufacturing process, which have high efficiency for logic integration and lower power consumption. In 2016, Xilinx and Altera launched the FPGA on 16 nm manufacturing process. The main components of the FPGA are programmable input/output units (I/O blocks), configurable logic block (CLB), embedded RAM, programmable wiring, underlying embedded functional units, and embedded dedicated hardcore. CLB is the basic logic unit of FPGA. It consists of trigger and look-up table (LUT). FPGA contains millions of logic units. It is very complex to configure them to achieve specific logic functions. Therefore, it is necessary to compile corresponding configuration files or binary code streams using special EDA development tools. The main EDA development tools of the mainstream FPGA manufacturers are Quartus from Altera, ISE and Vivado from Xilinx [74], ispLEVER from Lattice, pASSP from Atmel (acquired by Microchip in 2016), and Libero from Actel (acquired by Microsemi in 2010).

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The development of the design method of FPGA can be divided into three eras, namely the era of hardware description, the era of embedded soft core, and the era of heterogeneous systems. The era of hardware description is the first era of FPGA design. The designers use the hardware description language (HDL) to complete the research and development based on the circuit functions to be designed. Since the modular digital circuit can be packaged into an intellectual property (IP) core, the final design of the FPGA can be accomplished by using an IP core, which can greatly increase efficiency. The era of embedded soft core is the second era of FPGA design, which is represented by Altera’s microprocessor soft core named Nios II and Xilinx’s microprocessor soft core named microblaze. Designers use the logic resources inside the FPGA to build the microprocessor soft cores and then connect the IP soft cores such as I/O interface to the microprocessor soft core bus to form a programmable system on chip (PSoC). Designers can use C, C++, and other high-level languages to control the operation of the PSoC to co-design software and hardware. Driven by factors such as power consumption, performance, and development cycle, FPGA design has entered the era of heterogeneous systems. The CPU-centric architecture such as Harvard architecture (or Feng’s structure) and programmable logic circuits exist in the FPGA at the same time, making heterogeneous systems more comprehensive. For example, both Altera Cyclone V-series and Xilinx Zynqseries include ARM hardcores. At the same time, with the introduction of high-level synthesis (HLS), the EDA tools of FPGA have been further developed, and hardware programming of FPGA can be directly used in languages such as C and C++, which greatly improves the design efficiency of FPGA. After 2010, neural network technology has been widely used in the field of artificial intelligence. FPGA has attracted much attention due to its high parallelism, high throughput, low power consumption, and reconfigurability. It has become important devices for improving performance-to-power ratio in systems that implement deep learning algorithms.

Application-Specific Integrated Circuit and System on Chip ASIC products are customized digital integrated circuit (IC) for special purposes. Compared with digital IC products in the form of CPU, DSP, and FPGA, ASIC products have the advantage of being able to design for needed applications and implementing specific functions [75]. Microprocessors, memories, and other IPs are often included in modern ASIC products. A classical type of IP, named customerowned tooling (COT) module, less common to others, is commonly used in ASIC products. System-on-chip (SoC) design in general has embedded CPU, memories, including ROM and RAM, and various IPs (e.g., PLL, LVDS, ADC, and LDO), input/ output (I/O), and external memories (e.g., flash) integrated to process system-related functional tasks. The application processor (AP) is an upstart in mobile devices, where it undertakes primary functions (OS, audio, imaging, security, camera). AP

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belongs to SoC design category. In practice, the terms of ASIC and SoC are often mixed up names in use. The mainstream design flow of ASIC [76, 77] is based on the system design and specification. RTL code for ASIC design can be written with Verilog HDL (hardware description language) or VHDL language, followed by functional simulation and test. The gate-level netlist (GLN) that generated by EDA synthesis tool from RTL is passed by logic verification and/or conformal checking, and then, design for test (DFT) circuit is added. GLN is delivered to physical design team for place and route (P&R) and meeting the signoff demands such as clock tree synthesis (CTS), static timing analysis (STA), and power dissipation analysis. Physical verification and DFT also must be passed before the signoff and tape-out to chip foundry for production. A typical ASIC design flow is shown as Fig. 13.12. There are two mainstream design methods of ASIC, full custom and semicustom, respectively. In a full custom design, the implementation is to follow a standard design flow, while in a semi-custom design, one of the goals is to optimize various design-related resources, such as reuse and integration of mature IPs to achieve specific functions. The vendors offer a variety of solutions including but not limited to memories, standard cells, and complicated IPs. ASIC saves more development time and less R&D costs with existing platform in comparison with the COT mode that the entire back-end process would be completed by designers. In addition, structured ASIC can improve design performance, decrease the cost of non-recurrence expense (NRE), and reveals characteristics of both ASIC and FPGA at the same time, for example, the product model of eASIC company.

Fig. 13.12 Typical flow chart of ASIC designs [76]

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Fig. 13.13 Advanced technological nodes used for ASIC designs by global semiconductor manufacturers

As the semiconductor process becomes more advanced, reduction of transistor gate width, on the same area of the chip, ASIC product can integrate more transistors (e.g., in 2017 in an IBM design, 30
109 transistors are integrated [78] on a 5 nm chip) and achieve lower cost and higher performance. Figure 13.13 shows as the advanced technology node and relative process that ASIC products used by global semiconductor manufacturers of 2012–2018. The development of ASIC products cannot be separated from the software development of electronic design automation (EDA), which includes system design and verification tools, such as incisive, VCS; logic synthesis for GLN and physical design tools, like Innovus, Calibre; circuit design and simulation tools, for instance, Hspice, Spectre; and PCB design tools, like Sigrity and Xpedition. Currently, Cadence, Mentor Graphics (acquired by Siemens in 2017), and Synopsys can able to offer various tool methods to composite complete ASIC design flows. ASIC and SoC products are widely used in smartphones, computers, communication devices, automotive electronics etc. The common ASIC products can be seen in the series of Snapdragon 800/600/400/200 chips from Qualcomm, the series of Kirin of HiSilicon, and the series APU (CPU combined with GPU) based on Opteron processor from AMD, as well as GeForce graphics card GPU series of NVIDIA. ASIC or SoC design is typically for a single customer; when ASIC product aims to a number of customers, it is called application specific standard product (ASSP); thus, ASSP seems more a generic special case of ASIC. ASSP can be used as readymade products, such as independent USB interface chips, while ASIC is usually used in specific systems requiring specific functions.

Network Processor Unit Network processor unit (NPU) is used to process variety of network communication tasks, including processing of data packets, protocol analysis, routing search, voice and data collection, establishing internet firewall, and ensuring quality of service (QoS) of networks [79]. NPU is widely used in routers of Internet connections,

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Internet switches, and Internet monitor and protector equipment. As these electronic units are located at the Internet exchange point (IXP) to process data communication, the NPU is sometime called IXP network processor. There are some special requirements in network data processing, such as congestion management, queue scheduling, data stream classification, and QoS function, to meet extreme high searching and transferring tasks. The general-purpose CPU (e.g., x86), limited by the speed of PCI bus, is not most suitable for network communication processing. Combining software algorithm and hardware design, specially designed NPU can resolve the above listed problems. NPU can follow the development of the firewall, with its programmable flexibility, to simplify the application needs. The advantages of NPU are as follows, increased processing ability by using of multicore parallel processors; increased system performance using special hardware coprocessor; optimized reduced instruction set architecture (ISA) for processing network protocols; memory hierarchy to apt various applications; enriched I/O interface providing strong processing capability on its parallel hardware; and scalable massive and high-performance network processing tasks by using clusters formed of multiple NPUs. The widely used NPU products include IXP Series from Intel, who authorized IXP2800 to Netronome in 2011. Based on x86, Netronome has lately designed Agilio LX SmartNIC products that have data rate of 2
40 GbE or 100 GbE (Gbps or Gbit/s Ethernet). The router and switch products, EX9200 series, from Juniper Networks, a software-defined networking (SDN) company, can provide 480 Gbps per slot, up to 3.2/9.6/13.2 Tbps backplane bandwidth capacities. Broadcom announced in early 2019 that their Tomahawk® 3 is for routing and switching at a 12.8 Tbps performance on a single 7-nm process chip [80]. Marvell’s Prestera Series using ARMv7 CPU supports 40 GbE and total of 1.2 Tbps. Acquired Alcatel-Lucent in 2015, Nokia provides 10/40/100 GbE speed with 7450 Series, and the total speed of their switch product is 2–4 Tbps [81]. Neux 9500 Series Switch Chassis from Cisco can support up to 172.8 Tbps bandwidth, it can be configured to 32-port 100 GbE, and the number of port channel is up to 512. CE12800 Series Switch Chassis from Huawei has a backplane bandwidth of 178 Tbps [82]. Acquired EZchip in 2016, Indigo NPS from Mellanox supports Open System Interconnect (OSI) protocol, using ARMv8 and 100 A53 cores on 28 nm, and the data rate is 240 Gbps [83]. Compared with general processors (CPU and MPU), NPU chips (switch and control) require high performance and high data rate and require software technique, such as in software-defined networks (SDN). In today’s application of NPU in cloud computing services, such as in data center, one needs to not only consider the throughput of data, but also the security of data, which adds additional period of R&D effort and increased the complexity of architecture design.

Secure Cryptoprocessor and Cryptographic Processor Secure cryptoprocessor is a processor that can generate secure key; it does not generate secured data or programming instructions [84]. The applications of cryptoprocessor include the widely used smart cards, automated teller machines

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(ATM), TV set-top boxes (STBs), and military application systems. According to the design technology and methodology, there are two categories of cryptoprocessor 1) based on non-volatile memory (NVM) cryptography technology; 2) based on physical/physically unclonable function (PUF) cryptography technology [85]. Under secure circumstances, for a cryptographic processor, it combines cryptoprocessor (or cryptoprocessor) and an encryption scheme together, and the electronic data encryption, storage, and read-out via bus are then realized. The most common encryption technique used in cryptographic processor is the data encryption standard (DES) algorithm. Cryptographic processor using NVM cryptography is a mature technology and widely adopted. In this IC type design, the key and code are executed in the embedded CPU. Through the logic protection circuit, the internal encryption algorithm and programmable operation can protect the data to be encrypted by using the password or by other meanings. The certification process can be done via the trusted platform module (TPM), executed under the trusted execution environment (TEE), so the uploaded password and data maintain their privacy and integrity. NVM-based cryptographic processors can be installed in a Hardware security module (HSM), which is usually made of a single plug-in card or an external device. HSM can contain one or more cryptographic processors and is connected to a PC or a server when in use, so to prevent malicious tampering and peeping on the buses. PUF design technique was first reported in 2002 by Gassend et al. [86], and it has received increased attention in 2010–2013, to be expected as silicon fingerprint used in smart card. The special features of PUF, with the key and certification combined, are that the system protocol becomes non-reproducible, new encryption protocol fused with its original system architecture. There are two types of cryptographic processors on the market: The first type is made of the traditional logic chip using I2C (or I2C) interface protocol, with internal hardware protection circuit and external EEPROM to establish a protection with an encryption algorithm. The second type is an internal encryption chip in a smart card using I2C (I2C) or GPIO interface on either internal clock or external crystal. These encryption chips are programmed with a MCU that is partial algorithm, code and data are executed in the MCU. In addition, these chips must meet EAL5 security standard. In practice, the user needs to select a cryptographic processor first and then select a secure, rational, and effective encryption technique, such that the data can be protected. Secure cryptoprocessor and IC design can result in new innovative techniques. For example, back to 1989, Charles Bennett et al. of IBM have proposed to combine cryptology with quantum mechanics to become quantum cryptology for quantum key distribution (QKD), compared with human security network (HSN), and QKD offers advantages of automation, high reliability, and low cost [87]. Examples of cryptoprocessor are smartcards, TPM (with RSA encryption) chip, and hardware security module (contains one or more cryptoprocessor) chip. Intel claims that the Xeon chip has improved performance of Advanced Encryption Standard (AES) cryptofeature that is suitable for datacenter security.

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Advanced Processors In addition to various existing processors, such as CPU, MPU/MCU, and DSP, several new types of processors have been developed over the past decade(s). For example, parallel computing type graphic processing unit (GPU) is on the popular list. A fusion of CPU and GPU, the accelerated processing unit (APU) [88], is another example. In artificial intelligence (AI) development, for a cognitive computer, many processors on a single neuromorphic CMOS chip, TrueNorth, were developed at IBM in 2014 [89]. Similarly, based on an application-specific integrated circuit (ASIC) design, Google has developed a tensor processing unit (TPU) in 2016 [90]. 1) APU and HSA. AMD acquired a GPU technology-based Canadian company ATI in 2006. This has led from traditional CPU of serial computing to GPU of parallel computing, which is further fused to a single-chip APU. Table 13.15 lists APU products at AMD [88]. This has led to the heterogeneous system architecture (HSA) that integrates CPU and GPU on the same bus, with shared memory and computation tasks. In a HSA application [61], the core HW components are the CPU and GPU, in some cases to add DSP for specified tasks. Meanwhile, the SWs are developed in correspondence to the HSA needs. These include system-level languages C/C++, Python supporting multiple operating systems (OS), the Open Computing Language, OpenCL) for sharing computing in HSA, for the Open Graphics Library (OpenGL), the Open Multi-Processing (OpenMP) Application Program Interface (API), and the Compute Unified Device Architecture (CUDA) developed by NVIDIA. OpenCL has become a new industry standard for task-parallel and data-parallel processing in HSA designs. HSA Foundation was formed in June 2012, and the founding members were AMD, ARM, Imagination, MediaTek Qualcomm, and Samsung. Focused on the development and definition of various processors in the same system, the HSA Foundation emphasizes the specifications and interfaces of CPU, GPU, and DSP, together with graphic memory GDDR, the system virtual memory (SVM) was defined (Fig. 13.14). Table 13.15 APU generations and applications developed at AMD Year Jan. 2011, Gen. 1 Oct. 2012, Gen. 2 Jan. 2014

APU (former name Fusion) Project APU Llano, K10 arch., 2–4 CPU cores integrated with GPU Radeon HD 6000 Series; renamed HSA in 2012 APU Trinity, Piledriver arch., 2–4 CPU cores and GPU Radeon HD 7000/8000 Series APU Kaveri, Steamroller arch., integration of CPU with 195–512 core GPU

Process Features and Applications GF 32 nm HKMG SOI, 65–100 W, the first APU multicore design. Used in desktops and laptops GF 32 nm HKMG SOI, CPU 1.4–4.2 GHz, better CPU than Llano, used in desktops and laptops, Sony PS4 GF 28 nm HKMG bulk, 3.9–4.1 GHz, 15–95 W, for Sony PS4 and MS Xbox One. Better performance than similar Intel products

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Fig. 13.14 Schematics of SW and HW in a HSA

Some latest CPUs can be combined with GPU in HSA designs. For example, in 2016, AtomTM x5-Z8350 processor using 14 nm process from Intel has 4-core 4-thread, 2 MB L2 cache to work at maximum 1.92 GHz. Intel also announced 72-core Xeon Phi serial processor 7290, manufactured in 14 nm process, integrates 16 GB memory to work at 1.5 GHz. In 2018, Intel announced its 8th/9th-generation 4(8)-core processor Core-i7 serials, which can work at 4.5–4.7 GHz. 2) Neuromorphic Chip and TrueNorth. John McCarthy first used the phrase artificial intelligence (AI) in 1956, so as called the father of AI. Through machine learning (ML) algorithms of AI, the development and design of IC products are rapidly growing. Geffrey Hinton et al. published a paper of back-propagation algorithm in 1986; the work made a new progress in 2006 that is today know as deep learning (DL). Based on DL of ML, the convolutional neural network (CNN), or the deep neural network (DNN), and the long short-term memory (LSTM, a type of recurrent neural network, RNN) methods have promoted various designs of AI chips. IBM undertook the research project SyNAPSE from DARPA for the cognitive computer design. IBM announced in 2014 for a neuromorphic network, the TrueNorth many-core chip design [89] that contained 4096 CPUs. The CMOS chip has a total of 5.4
1012 transistors, and power consumption is only 70 mW. TrueNorth can simulate 2.68
1012 synapses in a human cerebrum; each CPU core can simulate 256 programmable neurons, which is equivalent to a total of 1
106 neurons. TrueNorth can be used in ML for AL training purpose. 3) AI Training and Cambricon Chips. In AI training, CPU is slower than GPU; while original GPU was not designed for such purpose, the advantage of performance is drawn back by its high-power consumption. Cambricon [91] announced in 2014 DianNao chip (Cambricon-1) and DaDianNao chip (Cambricon-2) to first demonstrate high performance and low power versus GPU in the market. Released in 2016, PuDianNao chip (Cambricon-3) could process seven difference AI algorithms including k-means, support vector machine (SVM), and deep

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neural network (DNN). ShiDianNao chip (Cambricon-4) in 2018 further improved data read/write (R/W) delay. In ML algorithm such as sparsely neural network (SNN), reduce the number of weighting factors of SNN for high performance, and the latest AI-chip Cambricon-1H8 aims for visual application; the third-generation Cambricon-1 M on 7 nm process aims on DL for video and ADAS data processing, which shows an energy efficiency of 5 TOPS/W, has been integrated in a smartphone Kirin 980 of Huawei. 4) TPU and TensorFlow. Google has started their tensor processing unit (TPU) chip design in 2013, through PCIe interface to optimize the CPU and GPU groups. The TPU was specially designed for a DL platform TensorFlow, which can transport complex datasets to AI neural network for analysis and processing. Acquired DeepMind of England in 2014, Google developed AlphaGo to defeat Lee Sedol in May 2016 and later AlphaGo 2.0 to defeat the 19-year-old Chinese prodigy Ke Jie in June 2017. Both systems are operated on TPU. In real-time completion of GO in TPU, maximum of 1920 CPU and 280 GPU were in use. Google released TPU architecture on April 5, 2017, through their official blog. The TPU has a 15–30 times AI process speed of other combined GPU and CPU mode, and the energy efficiency of computation is 50–80 times. Though other processors, such as application processor (AP) and baseband processor (BB) in mobile device, are called or listed under ASIC or SoC designs, these technical progress and advancement have brought in new stimuli for advanced designs for future processor market.

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16. GDDR5. https://en.wikipedia.org/wiki/GDDR5_SDRAM 17. GDDR6. https://en.wikipedia.org/wiki/GDDR6_SDRAM 18. PROM/OTP. https://en.wikipedia.org/wiki/Programmable_read-only_memory 19. C.W. Tsing, W.H. Henrich, Storage matrix, US Patent 3,028,659 (Apr. 10, 1962; Filed Dec. 27, 1957) 20. EPROM. https://en.wikipedia.org/wiki/EPROM 21. EEPROM. https://en.wikipedia.org/wiki/EEPROM 22. D. Kahng, S.M. Sze, A floating-gate and its application to memory devise. Bell Syst. Tech. J. 46(4), 1288–1295 (1967) 23. M. Nakashima, N. Ajika, DINOR Flash Memory Technology (Wiley/IEEE Press, Piscataway, 2007), pp. 313–336 24. NAND Flash Eyes Mass Storage Mart. https://www.electronicdesign.com/technologies/ memory/article/21759067/nand-flash-eyes-mass-storage-mart. Accessed 14 Feb 2020 25. 128-layer 3D NAND. https://www.digitimes.com/news/a20190604PD203.html. Accessed 14 Feb 2020 26. SSD. https://en.wikipedia.org/wiki/Solid-state_drive. Accessed 14 Feb 2020 27. MMC. https://en.wikipedia.org/wiki/MultiMediaCard. Accessed 14 Feb 2020 28. JEDEC defined eMMC. https://www.jedec.org/standards-documents/technology-focus-areas/ flash-memory-ssds-ufs-emmc/e-mmc. Accessed 14 Feb 2020 29. Package of eMMC. https://www.longsys.com/product/emmc/. Accessed 14 Feb 2020 30. What is eMMC. https://www.datalight.com/solutions/technologies/emmc/what-is-emmc. Accessed 14 Feb 2020 31. Multi-chip module. https://en.wikipedia.org/wiki/Multi-chip_module. Accessed 14 Feb 2020 32. TSV package. https://en.wikipedia.org/wiki/Through-silicon_via. Accessed 14 Feb 2020 33. Samsung eMCP. https://pdf.directindustry.com/pdf/samsung-semiconductor/samsung-emcp/ 34290-460883.html. Accessed 14 Feb 2020 34. Sebastian Pop, Samsung eMCP Memory Is Part NAND Flash and Part DRAM, https://news. softpedia.com/news/Samsung-eMCP-Memory-Is-Part-NAND-Flash-and-Part-DRAM-247687. shtml. Accessed 14 Feb 2020 35. X86 ISA. https://en.wikipedia.org/wiki/X86. Accessed 15 Feb 2020 36. X86 40 Years. https://newsroom.intel.com/editorials/x86-approaching-40-still-going-strong/. Accessed 15 Feb 2020 37. IA64. https://en.wikipedia.org/wiki/IA-64. Accessed 15 Feb 2020 38. Intel 64 and IA-32 Architectures. https://software.intel.com/en-us/articles/intel-sdm. Accessed 15 Feb 2020 39. B. Frey, PowerPC Architecture Book, Version 2.02 (2005). https://www.ibm.com/ developerworks/systems/library/es-archguide-v2.html. Accessed 15 Feb 2020 40. IBM Power microprocessors. https://en.wikipedia.org/wiki/IBM_POWER_microprocessors. Accessed 15 Feb 2020 41. OpenPOWER Foundation. https://en.wikipedia.org/wiki/OpenPOWER_Foundation. Accessed 15 Feb 2020 42. PowerPC. https://en.wikipedia.org/wiki/PowerPC. Accessed 15 Feb 2020 43. MIPS processor. https://en.wikipedia.org/wiki/MIPS_architecture_processors. Accessed 15 Feb 2020 44. MIPS ISA. https://www.linux-mips.org/wiki/Instruction_Set_Architecture. Accessed 15 Feb 2020 45. MIPS-3D. https://en.wikipedia.org/wiki/MIPS-3D. Accessed 15 Feb 2020 46. MIPS processors list. https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors. Accessed 15 Feb 2020 47. ARM Holdings. https://www.techopedia.com/definition/5900/advanced-risc-machine-arm. Accessed 15 Feb 2020 48. ARM. https://www.arm.com/. Accessed 15 Feb 2020 49. ARM Products. https://developer.arm.com/products/architecture. Accessed 15 Feb 2020 50. SPARC. https://en.wikipedia.org/wiki/SPARC. Accessed 15 Feb 2020

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51. The SPARC Architecture Manual, Version 9 (1994), https://cr.yp.to/2005-590/sparcv9.pdf. Accessed 15 Feb 2020 52. SuperSPARC. https://www.infogalactic.com/info/SuperSPARC. Accessed 15 Feb 2020 53. SPARC64 V. https://www.fujitsu.com/global/products/computing/servers/unix/sparc-enter prise/technology/performance/processor.html. Accessed 15 Feb 2020 54. UltraSPARC Architecture 2005. https://www.oracle.com/technetwork/systems/opensparc/t106-ua2005-d0-9-2-p-ext-1537734.html. Accessed 15 Feb 2020 55. C-Sky solutions. https://www.alibaba.com/showroom/sky-c.html. Accessed 15 Feb 2020 56. Alibaba Group Holding. https://www.alibabagroup.com/en/about/overview. Accessed 15 Feb 2020 57. GPU. https://en.wikipedia.org/wiki/Graphics_processing_unit. Accessed 15 Feb 2020 58. GeForce 256. https://www.nvidia.cn/geforce/. Accessed 15 Feb 2020 59. ATI Radeon R300. https://en.wikipedia.org/wiki/Radeon_R300_series. Accessed 15 Feb 2020 60. GPGPU. https://wiki.archlinux.org/index.php/GPGPU. Accessed 15 Feb 2020 61. HSA Foundation. http://www.hsafoundation.com/. Accessed 15 Feb 2020 62. V. Bansal, Microprocessors and Microcontroller Engineering Handbook (Engineering Handbook, Kindle Edition, 2019) 63. MCU. https://en.wikipedia.org/wiki/Microcontroller 64. Texas Instruments Incorporated, First-Generation Tms320 Users Guide (Prentice Hall and Texas Instruments Digital Signal Processing Series, Grand Prairie, Texas, USA, 2012) 65. Y.M. Yang, Digital Signal Processing (China Machinery Press, Beijing, 2012). ICBN 9787111342625 66. Mobile DSP. https://adexchanger.com/mobile/mobile-dsp/. Accessed 15 Feb 2020 67. XMOS DSP. https://xmos.com/. Accessed 15 Feb 2020 68. Cadence Tensilica User Manual. https://ip.cadence.com/ipportfolio/tensilica-ip. Accessed 15 Feb 2020 69. D. Patterson, A. Waterman, The RISC-V Reader: An Open Architecture Atlas (Strawberry Canyon, Berkeley, 2017) 70. RISC-V Architecture. https://cacm.acm.org/magazines/2019/2/234352-a-new-golden-age-forcomputer-architecture/abstract. Accessed 15 Feb 2020 71. Krste Asanovic. https://riscv.org/leadership/. Accessed 15 Feb 2020 72. RISC-V Cores. https://riscv.org/risc-v-cores/. Accessed 15 Feb 2020 73. FPGA invention by Xilinx. https://www.xilinx.com/about/company-overview.html. Accessed 15 Feb 2020 74. S. Churiwala, Designing with Xilinx ® FPGAs: Using Vivado (Springer, Cham, 2017) 75. ASIC. https://en.wikipedia.org/wiki/Application-specific_integrated_circuit. Accessed 15 Feb 2020 76. C.-Z. Chen, X. Ai, G. Wang, Physical Design of Digital Integrated Circuits (Science Press, Beijing, 2008). ISBN 978-7-03-022031-8 77. M.J.S. Smith, Application-Specific Integrated Circuits (Addison-Wesley Longman, Menlo Park, 1997) 78. IBM 5nm Chip. https://www.engadget.com/2017/06/05/ibm-5nm-chip-manufacturing. Accessed 15 Feb 2020 79. NPU definition. https://en.wikipedia.org/wiki/Network_processor. Accessed 15 Feb 2020 80. NPU from Broadcomm. https://www.broadcom.com/products/embedded-and-networking-pro cessors. Accessed 15 Feb 2020 81. NPU from Nokia (Alcatel-Lucent). https://www.al-enterprise.com/en/products/switches. Accessed 15 Feb 2020 82. NPU from Cisco. https://www.cisco.com/c/en/us/solutions/enterprise-networks/index.html. Accessed 15 Feb 2020 83. NPU from Mellanox. https://www.mellanox.com/products/processors/np-5. Accessed 15 Feb 2020 84. Secure cryptoprocessor. https://en.wikipedia.org/wiki/Secure_cryptoprocessor. Accessed 15 Feb 2020

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Analog and Mixed-Signal IC Products

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Contents Analog IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specialty Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Power Supply Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Dropout Regulator (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Light-Emitting Diode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Liquid Crystal Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serializer/Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Communication and Universal Serial Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet Interface IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface for Standard-Definition Television and High-Definition Television . . . . . . . . . . . . . . . . . High-Definition Multimedia Interface IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Technology Attachment Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Y. Guan Huada Empyrean Software Co. Ltd, Beijing, China F. Lai · G. Hu China Electronics Technology Group Corporation 24th Institute, Chongqing, China Y. Chen (*) Peking University, Beijing, China e-mail: [email protected] Y. Sun University of Chinese Academy of Sciences, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_14

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Protocol Converter IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Area Network Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-Integrated Circuit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Frequency Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Video Broadcasting Modulation/Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mobile Communication IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Codec IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Line Communication (PLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Subscriber Line (DSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passive Optical Network and Cable Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Among all semiconductor and IC products in the global market, analog and mixed-signal and RF ICs contribute to about 15% of the total. Different from digital products, AMS and RF products can be used in stand-alone, or they can be embedded in SoC/ASIC designs. Analog and AMS ICs have experienced from operational amplifiers (Op-Amp), comparators, voltage regulators, to the more complicated ones (e.g., PLL) The types of analog and mixed-signal (AMS) products are versatile and include very commonly used ADC, DAC, Op-Amp, LDO and various drivers, SerDes, Ethernet, USB interfaces, and audio/video codecs. This chapter introduces commonly used commercial analog and AMS IC products, their basic functions, features, applications, and some typical product names. Keywords

AMS · ADC · DAC · LDO · Drivers

Analog IC Analog IC is applied to process analog signals; analog and mixed-signal (AMS) ICs are used to process analog signals and digital signals on one silicon chip. Hereinafter, analog IC and AMS IC are collectively referred to as analog IC(s). Analog IC is integrated into electronic system to generate, convert, and process signals and provide power supply, specifically, works to sample, amplify, transmit, and drive analog signals and manage power supply. Application diagram of analog signal processing is shown in Fig. 14.1. The working process diagram among analog IC technology, design, and application is shown in Fig. 14.2. According to the relation of input to output, analog IC features both linear circuit such as operational amplifier and nonlinear circuit such as analog multiplier. By function, it includes amplifier, comparator, power supply, power management, analog switch, data converter, and RF IC. By application, it has general-purpose IC and application-specific IC, specifically, operational amplifier, voltage regulator,

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Fig. 14.1 Analog IC applications in a signal processing chain

Fig. 14.2 Relations between analog processing, design, and applications

phase-locked loop (PLL), active filter, analog-to-digital converter (ADC), and digital-to-analog converter (DAC) for the former; audio circuit and television receiver for the later. The world first IC was an analog IC that made by Jack S. Kilby in 1958, which was an oscillator on germanium (Ge) substrate featuring five components. At that time, analog IC was usually fabricated in bipolar process featuring one single function. Later, Fairchild semiconductor launched μA709 operational amplifier in 1965. In 1968, David Fullagar [1] developed μA741 operational amplifier, which had widest applications. Then, OP serial operational amplifier, 12-bit ADC AD565,

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8-bit DAC DAC08 by ADI [2], and MC78/79 series voltage regulator by Motorola were popular in the market for more than 30 years. As market grows and technology develops, analog IC process has made a great progress in bipolar, CMOS, BiCMOS, BCD, etc., as well as in substrate technology of Si, SiGe, and SOI. At present, we have analog IC products featuring high-speed converter in GHz range, 24-bit ADC, switch regulator in MHz switch frequency range and 95% efficiency, sub-μV offset amplifier, and voltage reference of sub-1
106/ C. We can find various kinds of analog IC products on market, with new products being constantly launched. The mutual push between customer demand and technology development is the essential driver for analog IC industry. Single-functional analog ICs are designed for higher resolution, ultra-wideband, ultra-high speed, lower noise, higher linearity, and higher power density. As technology develops, digital and analog circuits are integrated on a single chip for special and novel applications, with the help of auxiliary and calculation, in ways that enhance AMS IC development. The typical products include ADC, DAC, direct digital frequency synthesizer (DDS), frequencyto-voltage converter, phase-locked loop (PLL), and analog front-end (AFE) circuit. In 2017, Xilinx released a programmable RF SoC in 16 nm CMOS process, featuring FPGA, 12-bit 4GSPS (SPS: sample per second) RF-ADC, and 14-bit 6.6GHz RF-DAC on a single chip. In 2019, RF SoC was released featuring input/output frequency up to 6 GHz at the full sub-6GHz band and ADC sample rate ranging from 4 GSPS to 5 GSPS and resolution from 12 bit to 14 bit. It works to realize 2GHz bandwidth RF signal directly sampling and transmit-mode software-defined radio (SDR). Heterogeneous integration of analog IC and AMS and MEMS is the mainstream for the development of intellectual sensor industry.

Analog-to-Digital Converter (ADC) Analog-to-digital Converter (ADC, A/D, or A-to-D) is a kind of IC that converts analog signals to digital signals. With reference to conversion ways, analog-todigital converter is categorized as flash ADC, multistep ADC, successive approximation register analog-to-digital converter (SAR ADC), pipelined ADC, sigma-delta ADC (  Δ ADC), hybrid ADC, and time-interleaved ADC. Flash ADC works well for ADC with resolution from 1 bit to 8 bit. SAR ADC is fit for ADC with resolution from 5 bit to 10 bit, and pipelined ADC for 8 bit to 16 bit. -Δ ADC is perfect for 16-bit to 32-bit ADC. Hybrid ADC is a good choice when the trade-off between power and speed matters. Time-interleaved ADC consists of many single-channel ADC for high-speed applications where sample frequency is multiplied by using time-interleaved sampling and parallel conversion. Resolution (bit), sample rate (samples per second, SPS), and power are key performance parameters for ADC. As desired resolution increases, the sample rate needs to increase, and power increases as well. In that way, 4-bit to 6-bit ADC is expected featuring GSPS (106 kSPS) sample rate, but 32-bit ADC has sample rate of 38kSPS at the top due to high power.

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Look back the development of ADC, ADC employed successive approximation structure in bipolar and CMOS process with larger critical dimension. It featured 6-bit to 12-bit and sample rate of kSPS. In 1978, by using thin-film resistors, Paul Brokaw of ADI launched the first monolithic ADC AD571 in bipolar process. It featured 10-bit resolution, 25kSPS sample rate, and 180 mW power. With technology in sub-micron and deep sub-micron, ADC features hundreds of MSPS sample rates by using pipelined structure. In 2001, ADI launched AD9235 in 0.35 μm CMOS process featuring resolution of 12-bit, sample rate of 65MSPS, and power of 300 mW. In 2009, linear technology introduced a series product of LTC2204, LTC2207, LTC2208, and LTC2209 in 0.35 μm CMOS, which had sample rate of 160MSPS, 16-bit resolution, and 1.45 W power. The technology developed fast around 2012 emerging a great number of highperformance ADC. These products, in CMOS process, feature sample rate being multiplied while unit power being multiple decreased. For example, ADI AD9625 is a 12-bit 2.5GSPS ADC and AD9680 a 14-bit 1.25GSPS ADC. Texas Instrument (TI) provided ADC54J60 featuring 16-bit 1GSPS. Being fabricated in 65 nm CMOS process, all products feature more than five times of speed than ever with power not being increased. In 2016, it was reported that Broadcom’s ADC intellectual property (IP) features much less power than that of monolithic ADC [3]. ADI has published 12-bit 10GSPS ADC in 2017 International Solid-State Circuits Conference (ISSCC) that enter the age of medium resolution 10GSPS ADC for high-speed mobile communication in next generation [4]. ADCs are designed for higher resolution, higher conversion rate, lower power, single power supply, and lower voltage. In advanced CMOS power, ADC performance is enhanced by using time-interleaved sampling and various digital auxiliary calibration technologies. More and more low-power high sample rate ADC IP emerges as IC technology develops. At present, ADC products tend to find wide applications in industrial control, instrument, communication, auto-electronics, aviation and space, medical electronics, and customer electronics.

Digital-to-Analog Converter (DAC) Digital-to-analog Converter (DAC, D/A, or D-to-A) is an IC, which converts digital signals to analog signals. DAC features conversion rate and resolution. With respect to sample rate, it has Nyquist rate DAC and oversampling DAC. Nyquist rate DAC can be categorized into resistor ladder DAC, resistor network DAC, capacitive charge redistribution DAC, current-steering DAC, and hybrid or sectional DAC [5]. In terms of applications, it has general-purpose and application-specific types. Application-specific DAC has wide applications in wideband communication base/ medium frequency/radiofrequency signal generation, video/audio output, industrial control drive, and other things. In the 1970s, DACs were fabricated in bipolar, CMOS process, such as μDAC AD550 in 1970, 10-bit/500 ns multiplier AD7520 in 1974, 8-bit/80 ns DAC08 in

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1976, 10-bit/250 ns band-reference current output AD561, 12-bit/1 μs multiplier AD565, 8-bit/150 ns band-DAC buffer, and μP interface AD7524. ADI, TI, Maxim, and E2V are main competitors in the market of DAC products. At present, typical DAC products are as follows: 16-bit 12GSPS AD9162/AD9164 by ADI in 65 nm CMOS process, dual-16-bit 12GSPS AD9172 by ADI in 28 nm CMOS process, 14-bit 9GSPS DAC38RF8x Series by TI in 40 nm CMOS process, and 12-bit 6GSPS EV12DS460 by E2V in 0.35 μm SiGe Bipolar process. DACs have wide applications in industrial control, high-end measuring instrument, communication, automotive electronics, medical electronics, and customer electronics [6]. Besides its applications in baseband signal generator and mediumfrequency synthesizer, high-speed DACs start to find applications in wideband RF direct synthesizing and output. Digital signal process function is integrated into digital-to-analog converter, such as digital up-conversion, digital pre-distortion, and equalization. Two to four channels products with SerDes high-speed interfaces in series are presented working to integrate high-speed DAC and high-speed ADC as an integrated transceiver front end. Also, an RF front-end transmitter was launched by integrating high-speed DAC and RF up-converter. As process and design technology develops, DAC products feature high resolution, high dynamics, low power, multiple channels, and multifunctions, building up a great foundation for electronic system of “software definition” and “cognitive adaptation.”

Comparator Comparator is used to compare input current or voltage to references to generate the output digital as shown in Fig. 14.3. Usually, it is considered as a 1-bit analog-todigital converter, serving as basic cells for analog-to-digital converter of high resolution. At the very beginning, comparator was realized by integrating operational amplifier (Op-Amp), featuring narrow input range, low speed, low compatibility between output and referred digital level, no latch function, and other issues [7]. Typical early products include BG307, LM111, and LM119, which possess delay time of μs in bipolar process without latch function. In 1985, linear technology published LT1016 TTL comparator featuring delay of 10 ns. AD9696, AD8561, and Maxim’s MAX903 from ADI also reached the same performance.

Fig. 14.3 Schematic diagram of a comparator

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Comparator performs well depending on output digital level, response delay time, resolution, and power. Referring to output digital level, comparators are categorized as TTL/CMOS comparator and ECL/CML comparator. There is high-speed comparator, high-resolution comparator, and low-power comparator in terms of speed, resolution, and power, respectively. ECL/CML comparator features shorter response delay than TTL/CMOS comparator does. The conventional TTL/CMOS comparator has response delay of 4 ns, such as AD 8611/8612 by ADI. High-speed comparator tends to use ECL/CML level output, such as AD96685/AD96687, featuring response delay lower than 2.5 ns. Comparator is one of fundamental parts for analog IC, with wide applications in high-speed analog-to-digital conversion, high-speed sample and hold, crystal oscillation, clock recovery, zero-crossing detection, phase detection, voltage monitoring, etc. [8]. In future, comparators develop toward features of shorter response delay, better sensitivity, and adaptability for high-speed digital applications.

Operational Amplifier Operational amplifier (Op-Amp or OP) is a circuit being utilized to amplify weak signals. Input signals can be usually DC coupling, AC coupling, single-end input, and differential input signals. It outputs single-end or differential signals. Key performances matter for Op-Amp, such as offset, noise, low-frequency gain, bandwidth, power, output swing, common-mode rejection ratio, and other things. Fairchild semiconductor was the first company who developed Si-integrated operational amplifier in 1960 and launched μA709 [9] and μA741 in 1965 and 1968, respectively. ADI introduced OP07 in 1975, featuring offset voltage of 30 μV, temperature drift of 0.3 μV/ C, and time drift of 0.3 μV/month. Both μA741and OP07 were and are typical products with wide applications at present. At the 1970s, by using junction field-effective transistor (JFET) [10] and metaloxidation semiconductor field-effective transistor (MOSFET) at input stage, Op-Amp features better input impedance and lower input current in ways that well amplify and process weak signals. Op-Amp has various categories by different applications, such as general-purpose Op-Amps, high-speed Op-Amps (bandwidth greater than 50 MHz), high precision products (offset voltage less than 1 mV), and low-voltage/low-power ones (with power supply lower than 1 mA). General-purpose products work to amplify signals. High-speed ones feature high slew rate and high wideband, finding wide applications in communication equipment, video system, and test instruments. AD8003 of ADI is one of typical products, featuring bandwidth of 1.65GHz and slew rate of 4300 V/μs. Low-power Op-Amp has low operational voltage and low static current, with applications in portable and wearable electronic products. As cellphone and tablet market blooms, low-power Op-Amp develops fast. As for high accurate Op-Amp, it is widely applied in instruments and meters, sensors, and medical equipment for testing and measuring. The product ICL7650 features offset voltage of only 0.7 μV and unit gain bandwidth of 2 MHz. So far, Op-Amp products

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develop lower noise, wideband, and high slew rate, being fabricated in bipolar, JFET, CMOS, and other processes.

Instrumentation Amplifier Instrumentation amplifier (IA) is a kind of looped-gain amplifier, featuring high input impedance (>109Ω), high common-mode rejection ratio (>70 dB), low noise p (10nV Hz), low linearity error (typical value 0.01% and lower than 0.0001% is available), differential input with flexible gain setting, and single-end outputs [11]. As shown in Fig. 14.4, an instrumentation amplifier typically has two operational amplifiers A1 and A2 working to buffer and amplify signals in a way that guarantees high input impedance and decreases load effective of weak signals by instrumentation amplifier. Op-Amp A3 is used to amplify the difference between the two buffered signals from the latter two Op-Amps and restrain the common-mode signals at two input ends for better common-mode rejection ratio. When R1 equals R2 and R3 equals R4, gain G is calculated as shown in eq. G ¼ (1 þ 2R1/RG)RF/R3, so that circuit gain can be adjusted by regulating RG. ADI launched typical product AD627, AD620, AD8420, AD8229/8429, and TI introduced INA188 p and INA333 [11]. Hereinto, AD8229/8429 featured ultralow input noise of 1 nV/ Hz for measuring tiny signals. It is simple and easy-to-operate instrumentation amplifier by setting gain resistor RG to attain required gain. Figure 14.5 shows how instrumentation amplifier processes bridge signal, wherein the number of peripheral devices is small and circuit debugging is simple and effective. Instrumentation amplifier has wide applications in amplification of weak signals for sensors and accurate voltage-to-current conversion, such as signal sample equipment by using bridge signals (voltage, temperature, Fig. 14.4 A typical structure of IA

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Fig. 14.5 Signal application of an IA processing bridge

and others), industrial process control equipment, electrocardiogram monitoring instrument, and high-end audio.

Specialty Amplifier Specialty amplifier is an IC for special applications, which provides amplified signals. It consists of operational amplifier as core and peripheral devices as being specific costumed. Specialty amplifier features a variable gain amplifier (VGA), differential driving amplifier (DDA), linear isolation amplifier, and video amplifier (VA). The typical products are shown in Table 14.1. As for signal processing, VGA works to convert unfixed-input signals into fixedoutput signals resulting enhanced dynamic performance for system signal process [12]. In terms of control mode, the VGA is categorized as analog and digital VGA, being ideal for wireless communication, instrumentation, high-performance signal sampling, ADC signal conditioning, etc. Differential drive amplifier (DDA) is a wideband signal buffering and driving amplifier at front end of ADC, enabling impedance isolation and driving. It is typed as fully differential amplifier and single-end-to-differential amplifier. Differential drive amplifier works to, respectively, set differential and common-mode output voltage and flexibly configure common-mode voltage for ADC signal conditioning. It has wide applications in medical imaging, industrial process controlling, and portable equipment [13]. On condition of indirect electrical connection, linear isolation amplifier enables signal amplification and transmission to improve the capability of system security and anti-interference. It is ideal for safety and security application of medical electronic equipment and industrial process control. So far, the advanced iCoupler technology and enhanced capacitive isolation technology substitute for conventional optocoupler and shunt regulation in ways that provide isolation solution for applications in linear feedback power supply and sensor signal transmission. Video amplifier is specially designed for video signal processing, enabling enhancement in video brightness, color, and simultaneous signals to guarantee

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Table 14.1 Product list of typical specialty amplifier Specialty Amplifier Variable gain amplifier

Type AD8331

Company ADI

PGA281

TI

Differential driving amplifier

AD8137 ADA4940

ADI

Linear isolation amplifier

ADuM3190 AMC1301

ADI TI

Video amplifier

THS7319

TI

Description There is an ultralow noise preamp; a VGA with 48 dB of gain range, and a selectable gain postamp with adjustable output limiting in each channel. The gain control interface provides linear in dB over a wide dynamic range It is an instrumentation amplifier with three amplifiers, enabling signal gain control with digital codes It features low noise, low distortion, and ultralow power. It is ideal for high-resolution ADC signal conditioning, single-end to-differential conversion, differential buffering, and signal driving ADI uses magnetic isolation coupler and TI employs enhanced capacitive isolator to realize the linear isolation amplifier. Both perform excellent in isolation and common-mode transient rejection. Linear isolation amplifier enables improvements in stability and lifetime as compared to opt coupler isolator The THS7319 incorporates functions of level shifting, low-pass filtering, and fixed-gain amplification. It is ideal for three-channel high definition or RGB video signal transmission, featuring low power and small-sized package

high-quality image signals through long-distance transmission. As video resolution is improved, video amplifier tends to require higher bandwidth, lower distortion, higher speed, and lower power to meet the requirement of high-resolution video signal process. Besides, specialty amplifier also includes transconductance/transresistance amplifier, charge integral amplifier, limiting amplifier, logarithmic amplifier, current-sense amplifier, linear variable differential transformer, sensor amplifier, and sample/hold amplifier. Specialty amplifier has wide applications in portable equipment, testing and measuring instrument, medical system, and special signal processing. It develops for higher bandwidth, lower distortion, and lower power with various novel amplifiers for special applications.

Power Management IC Power management IC (PMIC) works to offer management solutions for voltage conversion, sequential control, charge-and-discharge management, energy distribution, and detection. It provides a stable power supply for the load, enabling a highly

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efficient, low power, and smart power system. PMIC is categorized into linear power supply, switch power supply, μ-module, digital power, and protection chip [14]. As portable smart technology grows, PMIC develops featuring multiple functions, multichannels, low power, and highly integration. Power management unit (PMU) is innovated and goes popular. For example, a PMU in cellphone is integrated with multichannel DC/DC, low dropout regulator (LDO), communication interface, and management units, in ways that realize higher power conversion efficiency, lower power, less components, and smaller size. Linear power regulator works in the linear region of amplifier, featuring small ripple wave, small number of peripheral devices but low efficiency. Three-terminal regulator and LDO of 78xx and 79xx product series are all linear power supply. Switch power supply operates at switching status. According to negative feedback principle, switch controller works to regulate the on-to-off switch ratio of power devices, such as MOSFET, enabling a stable output voltage. Switch power has isolation and non-isolation types. As for the former, optical isolators, transformers, and capacitive couplers are usually employed as isolation components in DC/DC converters. The non-isolation type usually uses peripheral components, such as inductors. Switch powers are small-sized, light, and high efficient, with wide applications in power technology. The μ-module products went public about 10 years ago, wherein switch power controllers, power transistors, inductors, and capacitors were packaged into one module. It features large output current, high efficiency, and small size. In October 2007, Linear Technology launched the first μ-module product LTM46xx, taking the lead in technology. Then, easy-to-use product LMZ13609 series were introduced by TI in 2011, which had wide applications in power management system. As for small power management system, it mainly uses monolithic chip to offer over-voltage, over-temperature, and ESD protections, as well as power supply and driving function, with applications in circuit power supply, battery-to-supply switch, and USB management. PMIC enables a high-efficient, low-power, smart power supply system and develops fast with accelerated production (productivity) to meet the requirement of wireless charging technology for mobile products.

AC/DC Converter AC/DC converter is used to convert alternating current (AC) into direct current (DC) [15]. Depending on how it rectifies, AC/DC converters are classified into halfwave rectifying converters and full-wave rectifying converters and are available for three-phase AC and single-phase AC. AC/DC conversion module can be directly plugged and played on PCB, so it has wide applications in switch device, interface, mobile communication, microwave communication, optical communication, routers, and motor electronics, aviation, and space applications.

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Monolithic AC/DC converter is ideal for small power driving applications, by integrating magnetic modules with AC/DC conversion controller on a single chip. Power Integrations [16] launched the first three-terminal isolation PWM AC/DC switch in 1994 and then in 2000 presented 290 W TOP250 single chip of AC/DC converter, from TOPSwitch-GX family wherein high-voltage MOSFET, PWM controller, ESD, and other control circuits were integrated on a CMOS chip. ROHM developed an AC/DC converter enabling the control IC BD7682FJ-LB. As IC analog design technology makes use of power devices in SiC process, the gate driver of SiC-MOSFET can be integrated on the chip enabling miniaturization and high conversion efficiency. The chip had wide applications in large power inverter (high-voltage multiplies large current) and servo in industrial equipment. A novel flyback topology goes popular and is used for power circuits. TI launched 5 W–100 W flyback AC/DC converter in 2014, featuring low-power stand-by status of 5 W–10 W, minimum constant output current tolerance of 5%, and average efficiency more than 88% [17]. In 1980s, AC/DC converters use switch power for low-power applications such as computers. At the moment, AC/DC switch power IC remarkably grows in the market of portable products and digital consumer electronics. The way to improve the performance of AC/DC switch power is concluded as follows. Firstly, its switch frequency is improved by using zero-voltage switching (ZVS) and zero-current switching (ZCS) soft-switch technology for greater power density and smaller size. Secondly, intelligent control components are used to decrease power consumption through second rectification. Thirdly, material (Mn-Zn) performance is improved and new materials are used for better performance. Besides, both miniaturized passive module and surface mount technology (SMT) play a part in the improvement of switch power. In the future, microgrid will develop with the help of distributed AC/DC power IC. Mirogrid AC/DC technology tends to provide a solution for an ideal trade-off between power quality and power flow, well-performed voltage and frequency control and power management. It also solves the problems concerning stability, reliability, and over-voltage/current protection, dynamic modeling, and operation with low cost.

DC-DC Converter DC-DC converter works to realize voltage conversion for a stable voltage. It belongs to a branch circuit of switch power supply. DC-DC converter [18] has wide applications in telecommunication, portable digital devices, computers, office automation system, and industrial equipment, military use, spacecraft, and motor transportation. In 1980, the initial product was a monolithic DC-DC converter L4960 family from STMicroelectronics. Vicor Corporation takes the lead in soft switching DC-DC converter worldwide, whose products feature maximum power of 300 W, 600 W, and 800 W, correspondingly power density of 6.2 W/cm3, 10 W/cm3, and 17 W/cm3, and efficiency of 80%–95%. The soft switching technology keeps developing for

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high-frequency and high-power density, and its frequency reaches megahertz range. With the development of semiconductor and packaging technology, high-frequency soft switching technology grows enabling power density exceeding 50 W/cm3 and efficiency over 90%. To meet the requirement of DC test equipment, computer video display, and computer and military communication, low-power DC-DC converter grows remarkably in market, especially for 6–25 W DC-DC converter. As for applications in medical instrument, industrial control system, and telecommunication, DC-DC converter develops from lower power to medium and high power ranging from 251 W to 750 W. As a part of power management, DC-DC converter works to serve not only computers but also other applications such as the driver of cellphones and active matrix organic LED of portable devices. Digital DC-DC converter [19, 20] is available as DC-DC converter technology develops. Digital DC/DC products bring variety of intelligent module DC power supply. More types of intelligent DC-DC converters are coming to market for applications in distributed power system of spacecraft and aerospace network.

Switching Power Supply Controller Switching power supply controller [21] is used to realize closed-loop control and other protection functions for switch power supply. As a core part, it consists of reference, error amplifier, oscillator, PWM comparator, latch circuit, and output stage. Switching power supply controller features high integration, good consistency, and simple peripheral components. Switching power supply controller is sorted into pulse-width modulation (PWM), pulse-frequency modulation (PFM), phase-shift resonant (PSR) controller, and synchronous rectifier controller. PWM controller features highest efficiency among other switch power supplies on a wide load range, which makes it the most mature product and has widest applications. On condition of a consistent output signal frequency, PWM controller regulates the pulse width (duty cycle) of power switch controlling signals to control charging/ discharging time of inductor for a stable output voltage. The topologies of singleend, push-pull, semi-bridge, buck, boost, isolation, and non-isolated type are used. The typical products are SG1525A from Microsemi, UC1843 from TI, and UC1825 and LT3845 from ADI. How PWM feedback control works is shown in Fig. 14.6. On condition of a consistent pulse width of power switch control signals, output signal frequency, PFM controller regulates the frequency of output signals by using feedback control circuit to control charging/discharging time of inductor for a stable output voltage. Sine wave is substituted for square wave, which greatly decreases high-frequent noise of switch power supply. PFM controller works to enable zerovoltage switching (ZVS) or zero-current switching (ZCS) of switch tubes. As switch tube is on and off at zero voltage or zero current, the voltage and current crossover loss is evidently decreased and power efficient is increased. The size is decreased, and quality is improved by increasing switch frequency. The products, such as

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Fig. 14.6 Feedback control principle of PWM

UC1860, UC1864, and UC1868, feature operation frequency over 1 MHz, driving current larger than 200 mA. With wide applications in full-bridge topology, PSR controller has invariable frequency and duty cycle of output signals at each channel. By adjusting the phase of power switch drive signals at bridge arms, the converter works to regulate operation pulse width for a consistent output voltage. It features advantages that PFW and PWM have. It regulates the pulse width the way PWM does and keeps zero voltage (or zero current) status while the switch is on and off. Finding wide applications in large power switch power supply, it has typical products, such as UC1875, UC1876, and UC1879. Synchronous rectifier controller is designed to solve the problem of high positive voltage of rectifier Schottky diode, as the Schottky diode has forward voltage drop above 0.3 V. The synchronous rectifier is replaced by power MOS device, which enables low on-resistance of several milliohms (mΩ) resulting lower on-resistance consumption and higher switch power conversion rate. Synchronous rectifier controller has applications in non-isolation DC-DC converter, such as LT3844 and LT3845. Digital converter is a novel switch power controller, consisting of analog-todigital converter, discrete compensator, and digital PWM. The main product is TMS320LF2407A from TI. The performance of high-power density, high reliability, and low noise matters for switching power technology and products. The way to improve power density and reliability is mostly realized by increasing conversion rate and being miniaturizing. Downing the road, the switch power controller develops for higher operation frequency and digitalized controlling way. The improvement of operation frequency is helpful to not only decrease the noise and the size of capacitors, inductors, and invertors, but also ameliorate dynamic performance of power supply.

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Low Dropout Regulator (LDO) Low dropout regulator (LDO) is a linear regulator featuring low output/input voltage drop and offering a stable output voltage at limited power supply. In 1967 for the first time, Robert Dobkin [22] presented a low-voltage-drop linear regulator featuring the difference of 0.7 V of input and output voltage. Fabricated in BCD process, the LDO operates featuring 115 mV at 3A output current, with power and size being evidently decreased. Board-level power or batteries bring large voltage fluctuation, so voltage regulators are used to improve the quality of power supply for electronic components at back-end input power supply. Compared with DC-DC switch regulator, LDO is a voltage linear regulator, featuring low noise itself and high-power supply rejection ratio (PSRR) in ways that greatly improve the quality of front-stage power supply. LDO has low static power, small size, low cost, and simple peripheral applications. It features higher conversion power and lower efficiency than DC-DC converter does. As shown in Fig. 14.7, low dropout regulator uses negative feedback controller to output a stable voltage. The core part of LDO consists of a reference, error amplifier, and regulator tube and feedback resistor. The regulator tube works at linear area and serves as an adjustable resistance. When input voltage or load transiently changes, the output voltage from regulator tube is consistent by employing sample, error amplification, and negative feedback. According to the types of regulator tubes, LDO types include npn quasi-LDO, pnp-LDO, pMOS LDO (p-FET LDO), and nMOS LDO (n-FET LDO). The transmission transistor, respectively, uses npn transistor, pnp transistor, and pMOS and nMOS transistors in sequence of from highest to lowest dropout voltage. Concerning the power supply types, it has positive LDO to regulate positive voltages and negative LDO to regulate negative voltages. To meet the requirement of system-on-chip and high-performance devices, LDO is not developed for low power and large current anymore, but for high PSRR and highly integration [23]. Power clutter is decreased, and noise band of power supply suppression is enlarged, which meets the demand of power supply for RF, high-end Fig. 14.7 Structural diagram of LDO

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ADC and DAC. A novel frequency compensation method is employed to realize off-chip capacitor design, in a way that enables multiple LDO integrated on SoC. As a mainstream, LDO develops for highly integration of SoC with multiple LDOs. Speaking of this, key issues for LDO technology are concerned: load transient response, over-hoot resistance, and recovery time. TI developed an LDO product for various applications. For example, low noise TPS7A88 is launched for RF and analog circuits, featuring noise root mean square (RMS) of 3.8 μV. For battery supply, TPS782 features static current of 500 nA. TPS7A4001 has enlarged input voltage up to 100 V for transient voltage of wide input range. To eliminate the switch noise of FPGA and DSP, TPS7A84 has output current up to 3A, noise RMS of 4.4 μV, and accuracy of 1%.

Light-Emitting Diode Driver Light-emitting diode (LED) driver is a power supply regulator device being used to drive LED lighting or LED modules. Initial LED only features red, green, and yellow lights for signal indication. It was driven by switch current-limiting drive. Several novel drivers were developed for lighting and display applications. In 2005, a novel AC LED was launched without driver [24]. LED driver works to provide constant voltage or current for LED in ways that expand the lifetime of LED device and enable stability of LED lighting, brightness control, and improvement in efficiency of the driver. According to the way of LED driver works, it is categorized into constant voltage resistance-limiting current drive and constant current drive. The way constant voltage resistance-limiting current driver works is shown in Fig. 14.8, wherein the driver works to provide pulse voltage to regulate LED visual brightness. But the constant current driver tends to regulate the LED brightness by changing the internal reference voltages. As for RGB Fig. 14.8 Principle of constant voltage resistance and current-limiting LED driver

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color model, full-color display is realized by controlling the brightness of red, green, and blue lights. The constant current drive LED driver is categorized into linear constant LED driver and switch constant current-driven LED driver as, respectively, shown in Figs. 14.9 and 14.10. As for constant voltage resistance-limiting current LED driver, the current is defined by LED voltage dropout and the dropout at limiting current resistor of LED in series. The driver tends to control on–off status of voltage signals. Due to the negative temperature characteristic of LED, the drive current is not immune to environment conditions, featuring bad stability. LED lifespan is directly related to

Fig. 14.9 Principle of linear constant LED driver

Fig. 14.10 Principle of switch constant current-driven LED driver

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drive current. So the driver is used for low-end products, such as the LED driver of single- and dual-colored display, wherein the LED lifetime is not strictly required. Linear constant current LED driver employs linear regulator with reference error amplifier and power tubes integrated. It works to control the voltage at current sample resistor which is connected to LED in series in a way that keep a constant current through LED. The driver features good constant current but low efficiency, because the driver must take large voltage dropout resulting from the difference between input voltage and LED voltage at amplification status. Switch constant current LED driver uses the way switch power supply controls by controlling the voltage at sample resistor to enable a stable LED current. As it operates at switching status, the power device features low power consumption and high efficiency but tiny ripple-wave current through LED. Attention must be paid to EMI issue when it comes to switch driver. Filter is required to filter EMI when necessary. Constant voltage resistance-limiting current LED driver tends to provide pulse voltage to regulate LED visual brightness. Constant current LED driver works to control LED brightness by changing internal reference voltage. So far, LED finds wide applications. LED driver providers are mainly TI, Maxim, etc. Only speaking of TI, it produces various LED drivers exceeding 300 categories. LED driver develops higher efficiency and lower power consumption in an environment-friendly way.

Liquid Crystal Display Driver Liquid crystal display (LCD) driver is used to regulate phase, peak, and frequency of level signals at both ends of LCD in real time in ways that display electronic devices through liquid crystal. Comparing to CRT (cathode-ray tube), LCD features low operation voltage, low power, easy to be colorful, high definition, no electronic–magnetic radiation and long lifetime. For early calculators and timers, only color (usually black) and colorless (Twisted Nematic, TN) are available for the liquid crystal display. Later, super-twisted nematic (STN) LCD is introduced featuring wider visual angle and finer character. The thin-film transistor (TFT) LCD features short image developing time for dynamic pictures and real-time display, which has wide applications in digital camera display and large-sized flat panel TV displays. According to the relation between control electrode and each pixel, the LCD driver is categorized into static and dynamic driving [25]. In the static driving, each segment of display has an independent drive circuit. Directly regulate the relative voltage and phase between segment electrode and common electrode to change the segment display. The static driving method has advantages of simple structure and well-performed display with applications in stroke liquid crystal display of numbers, letters, and special figures. It is impossible for pictures requiring millions of pixels to use static driving method. Dynamic driving method is introduced, wherein electrodes are displayed in

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matrix way. The electrode matrix is controlled by logic circuit side and liquid crystal drive side. Logic circuit side works to transmit and latch display data according to required display. And liquid crystal drive side tends to control corresponding line driver and column driver according to the data from logic circuit side. It updates the data column by column. When all data of updated line are latched, it starts to switch from line to line. There are gate drive and source drive circuits available for LCD driver. When scanning, the gate driver controls to switch on transistors in column and the source driver works to control the brightness, greyscale, and hue line by line. Driving output at drive side usually has more than one ends, which determines the ability of the LCD driver. The main LCD providers are Renesas Electronics, Samsung, Magnachip, etc. At present, character LCD driver and graphic dot matrix LCD driver are popular in the market with wide applications in MSTN (monochrome super-twist nematic), CSTN (color super-twisted nematic), TN, TFT, and OLED displays. The control signals of LCD driver come from LCD controller which transmits LCD image data of system storage to external LCD driver. In future, developing for large-size, LCD display is about to provide large rail-to-rail output swing to enable large dynamic range required by video operational amplifier.

Motor Controller Motor controller, also named as motor driver, consists of several circuits for controlling speed, moment, position, and overload protection. According to input signals and other sensing signals, motor controller operates to control the direction of motor winding current by using internal algorithm, in ways that start, stop, forward rotate, and backward rotate the motor. Motor controller tends to set and stabilize rotation rate, level off, and set a limit to a rotation moment and protect the motor when it comes to overload and locked rotor. General-purpose motor controller [26] is used to keep an expected operation status. Some of the special application motor controllers, such as servo controller, work to control the whole servo system (including motor, decelerator, and sensor) at a normal operation status. Motor controller is integrated with logic and power drive circuits. On condition of electronic–magnetic interference, motor controller is designed and fabricated in bipolarCMOS-DMOS (BCD) process with highly strict requirement. The operation voltage range, continual current output, peak current output, and ESD are the key specifications of the motor controller. Monolithic power switch motor control finds applications in tiny-small power devices, such as printer, office automation, fans, and camera. Large power motor controllers for washer and vacuum cleaner, featuring hundreds or thousands watts, are configured with programmable processors for motor controller. It has power switch devices to realize large current controller. Motors have various categories with each having unique control mode; thus, there are DC brush motor driver, DC brushless motor driver, and stepper motor driver [27]. As semiconductor technologies and motor control technologies are progressed

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over past years, some IC companies are able to provide full solutions for motor controller, including TI, ST, Allegro and MicroSystems, as well as Chinese enterprises, such as Hangzhou Silan Microelectronics, Sinotech Mixic Electronics, Shanghai Bright Power Semiconductor, and Fortior Technology.

Serializer/Deserializer The serializer/deserializer (SerDes) is characterized in that the data and the clock are transmitted in the same channel, and the clock information contained in the data is extracted by the clock data recovery (CDR) technology at the receiving end and sampled and received by the clock. The basic SerDes function is made up of two functional blocks: the parallel-in serial-out (PISO) block (aka parallel-to-serial converter, PSC) and the serial-in parallel-out (SIPO) block (aka serial-to-parallel converter, SPC). Currently, most high-speed signal transmission uses the SerDes structure. The transmitter (TX) of SerDes includes parallel–serial converter, encoder, transmitter equalization, and driver. The receiver (RX) of SerDes includes receiver attenuator, receiver equalization, clock data recovery, decoder, and serial–parallel conversion. At present, SerDes mainly includes (1) parallel clock SerDes, (2) embedded clock SerDes, (3) the 8b/10b SerDes, and (4) bit-interleaved SerDes [28]. 1. In the parallel clock SerDes scheme, the clock and data are separated, and the data and control/address bit signals are respectively transmitted, wherein the data and the clock signal are, respectively, transmitted through a specific line, which is commonly used for low-speed transmission. The advantage is that no clock data recovery circuit is required, the circuit is simple, and the jitter requirements are low; the disadvantage is that an additional clock line is required, and the clock line causes electromagnetic interference (EMI) and crosstalk, so it cannot be used on a high-speed link. Currently, this type of SerDes is used in DDRs and other similar designs. 2. The architecture of embedded clock SerDes is a standard SerDes architecture in which the clock is embedded in the data signal and recovered at the receiving end via the CDR. The advantages are that the effects of electromagnetic interference and crosstalk caused by separate clock lines are eliminated, reducing the impact of the clock line on the PCB layout; the disadvantage is that the remote clock recovery requires small jitter. PCIe, USB 3.0, USB 3.1, and SATA all use this SerDes solution. 3. The 8b/10b SerDes scheme adds additional code to the serial data to balance the DC component and reduce the CDR pressure. The encoding is not necessarily 8bit/10bit, but also has a more efficient encoding, such as 128-bit/132-bit encoding used in PCIe3.0. The advantage is that the inserted bits prevent long “1” or “0” patterns, and thus, it is enough to let the CDR receive 0/1 hopping to ensure its normal operation; the disadvantage is that the inserted bit will be redundancy. The 8-bit/10-bit encoding can achieve up to 20% redundancy.

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4. The bit-interleaved SerDes scheme combines multiple low-speed serial data into one high-speed serial data. The advantage is that it can increase the rate and reduce the number of data transmission channels, which is beneficial to the PCB layout, and reduce crosstalk; it requires additional clocks, selectors, and CDR circuits. Ten gigabit attachment unit interface (XAUI) is implemented through this architecture. Due to the continuous increase in data transmission speed, the SerDes architecture has been continuously developed. When the early signal transmission speed is only kbit/s to Mbit/s, the parallel interface is sufficient. However, as IC manufacturing processes are progressed and transmission rates increase, crosstalk caused by high-speed signals, especially clock signals, to other transmission lines is increasingly serious and impacts transmission quality. At the same time, miniaturization of application products requires reduction of the lines on PCB. Therefore, the SerDes that uses a serial line and does not require a separate clock line is the best choice. The SerDes architecture is widely used in civilian high-speed interface protocols. At present, major companies use SerDes architecture to implement high-speed interface products, such as Synopsys USB/PCIe/SATA IP, Huawei 10 Gbit/s Enterprise SerDes, and Xilinx 26 Gbit/s SerDes launched in 2011. Intel in 2019 is showing off 112Gbps SerDes that was produced in 10 nm FPGA process [29].

Serial Communication and Universal Serial Bus Interfaces In 1960, Electronic Industries Alliance (EIA) issued the first serial communication standard, namely RS-232 (Recommended Standard). RS-232 standard initially serves for telephone/telegraph signal transmission and then for interface connection between PC and peripheral equipment (such as printers). RS-232 tends to provide standards of transmission distance less than 15 m, rate of 20 kbit/s, for single driver, and single receiver. EIA published RS-422 in 1994, which says that data transmission rate up to 10 Mbit/s, transmission distance up to 1200 m. In 1998, RS-485 standard was issued, wherein 32 bus receivers were available as bus multipoint output was realized by adding three-status output function. The standard interface features 9 and 25 pins. Specifications of the three standards are shown in Table 14.2 and interface modes in Fig. 14.11. Now, these interfaces are gradually replaced by universal serial bus (USB) and Ethernet interface. RS series protocols are typically adopted for universal asynchronous transceiver (UART) in serial port communication of asynchronous serial communication computers. In 1994, Inter, Microsoft, IBM, and Compaq proposed USB protocol, which was highly related to high-speed serializer/deserializer (SerDes) technology. A USB interface enables serialization and deserialization; wherein multichannel parallel low-speed data signals are converted into serial signals at transmission end and transmitted through coaxial line at high speed, the signals are then deserialized into multichannel parallel low-speed data signals. This is called P2P serial

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Table 14.2 Parameters of RS-232, RS-422, and RS-485 serial communication standards Protocols Transmission mode Number of BUS node (maximum) Cable transmission length (maximum) Transmission rate (maximum) Output driving voltage (maximum) Load impedance at drive end Slew rate (maximum) Input voltage at receiving end Input range at receiving end Input impedance at receiving end Common-mode voltage at drive end Common-mode voltage at receive end

RS-232 Single-end transmission 1 driver/1 receiver 15 m

RS-422 Differential transmission 1 driver/10 receivers 1500 m

RS-485 Differential transmission 1 driver/32 receivers 1500 m

20 kbit/s 25 V

10 Mbit/s 0.25 V to +6 V

10 Mbit/s 7 V to +12 V

3 to 7 kΩ 30 V/μs 15 V 3 V 3 to 7 kΩ

100 Ω – 10 V to +10 V 200 mV 4 kΩ (min)

54 Ω – 7 V to +12 V 200 mV 12 Ω

–

3 V to +3 V

1 V to +3 V

–

7 V to +7 V

7 V to +12 V

Fig. 14.11 Interface modes of RS-232, RS-422, and RS-485

communication technology which takes less transmission channel and device leads in a way that realizes high-speed transmission and saves the cost at communication transmission. USB interface internally consists of only two cables and two signal lines working to transmit signals at serial mode. According to USB transmission protocol, data are packed up by USB transceiver chip, converted into serial data flow and sent at highspeed through the two signal lines (D+, D-). USB at receive end works to receive and deserialize the serial data which ends the whole data transmission. USB interface system consists of hub, host computer, and function peripherals. Hub and function peripherals are called as external devices. USB standards are updated at high frequency of which the regulated data transmission rate is greatly improved, as shown in Table 14.3 [30]. The physical size of USB connectors has been keeping down. In 2007, USB-IF published micro-USB (micro-A, micro-B) standard, featuring similar width to miniUSB (mini-A, mini-B) standard but half thickness of the mini-USB. In 2014, USB

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Table 14.3 Parameter comparison of different USB standards Version USB 1.0 USB 1.1 USB 2.0 USB 3.0 USB 3.1 USB 3.2 USB 4.0

Data transmission rate 1.5 Mbit/s 12 Mbit/s 480 Mbit/s 5 Gbit/s 10 Gbit/s 20 Gbit/s 40 Gbit/s

Mode Low speed Full speed High speed Super speed Super speed+ Super speed+ Super speed+

Issue year 1996 1998 2000 2008 2014 2017 2019

Fig. 14.12 Profiles of USB interfaces (not proportional)

type-C protocol published by USB-IF gave a definition of a smaller and thinner connector which substitute for type-A and type-B connector. Cables can be positive and negative plugged. The plug works at both host computer and peripheral equipment, which enables a simple connection. On September 2012, Apple Company launched a novel lighting interface specialized for data bus of specific use computers and power cable connection. It works to substitute for Apple 30-pin base connector for Apple mobile portable devices. USB interfaces are shown in Fig. 14.12 [31]. USB interfaces meet the requirement of cascade connection between devices and feature simple connection, high-speed transmission, plug in and out, and no need for extra power supply. It finds wide applications in keyboard, mouse, flash memory, and camera which makes it a standard interface for all computers and many other electronic devices.

Ethernet Interface IC Ethernet is a kind of computer network technology (CNT) enabling communications at local area network (LAN) and metropolitan area network (MAN). Interfaces that work to realize connection between these network devices are called as Ethernet interfaces; all network interfaces in the market are named as Ethernet interfaces. Some of them are common and popular including RJ-45 interfaces, RJ-11 interfaces, SC fiber interfaces, fiber distributed data interfaces (FDDI), adaptive user interfaces (AUI), Bayonet Neill–Concelman (BNC) interfaces and console interfaces.

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In 1980, 3Com, DEC, Intel, Xerox, and other companies together published agreement of the DIX (Digital Intel Xerox) Standard providing data speed of 10 Mbit/s Ethernet features 48-bit target and source address and global 16-bit Ether-type fields [32]. Original Ethernet data transmission reached 10 Mbit/s by using carrier sense multiple access with collision detection (CSMA/CD). IEEE 802.3 protocol was established in 1983 which formally standardized Ethernet protocol. As demands for network application grow, Ethernet attains higher data transmission rate and longer transmission distance for network data transmission. So Ethernet protocol was improved to meet the requirement [33]. On October 1993, Grand Junction provided the first fast network interface card (FastNIC 100) and hubs (10/100 Mbps fast Ethernet switch) which succeeded in commercial application. 3Com, Intel, Bay Networks, and SynOptic successively launched various fast Ethernet devices. In March 1995, IEEE published IEEE802.3u fast Ethernet standard in the form of 100Base-T. Gigabit Ethernet technology is going popular in application, and Terabit Ethernet starts to find applications. Terabit Ethernet works to support 10 Gbit/s transmission rate in IEEE802.3ae standard. IEEE802.3ae standard is based on IEEE802.3 standard. Ethernet physical structure consists of medium access control (MAC) and physical interface transceiver (PHY). MAC chip works to control the physical medium of physical layer and provides a system to address and control channel access, which enables multiple terminals or network nodes to communicate between multiple accesses network with shared medium. PHY transceiver chip enables transmission/ receiving function of Ethernet physical interfaces. The chip works to convert parallel data into serial data for transmission, convert data coding into analog signals according to coding rules of physical layer, and transmit the analog signals. For receiving data, it works in reverse procedure. Besides, PHY transceiver features carrier sense and collision detection. Main Ethernet interface products include 10/100 megabit Ethernet and gigabit Ethernet PHY transceivers, such as Cisco WS-C2960 series and WS-C3850 series and Huawei S57xx series gigabit Ethernet with wide application in network printer, Broadband Gateway, smart TV, set-top box (STB), smart grid, and building automation system. For applications in Web virtual reality technology, distributed artificial intelligence, 4K high-definition TV (HDTV, UHD), network virtual game, and network bandwidth demand grow fast which beef up terabit Ethernet technology to substitute for gigabit Ethernet.

Interface for Standard-Definition Television and High-Definition Television Standard-definition television (SDTV) technology generally supports the “standarddefinition” video formats such as VCD, DVD, and TV programs; SDTV is typically 480i signal, where 480 represents the vertical resolution, and letter i represents interlaced. SDTV technology is often used in multimedia equipment, like TV sets, TV set-top boxes, cameras, and video conference. The video signal transmission

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interface of SDTV, like CVBS, S-Video, and VGA, is mostly using analog signal. The pixel display aspect ratio (DAR) of SDTV has 4:3 and 16:9 two types. The CVBS interface stands for composite video broadcasting signal (CVBS) or composite video blanking and sync (CVBS) [34]. The CVBS interface, also known as baseband video or RCA (Radio Corporation of America) video, is a traditional image data transmission method for television signals developed by the U.S. National Television System Committee (NTSC) since 1954, which uses analog waveforms to transmit data. The S-video interface (separate video interface) specification was developed in Japan, which separates the luminance signal and the chrominance signal to avoid interference of luminance and chrominance when the mixed video signal is transmitting [35]. The S-video is a five-core interface consisting of two video brightness signals, two video chrominance signals, and one common shielded ground wire. The S terminal is commonly available in 4-pin, 7-pin, 8-pin, and 9-pin models. The video graphics array (VGA) interface belongs to the analog interface. The standard VGA (640
480, 60 Hz) interface transmits 3 RGB analog signals, horizontal sync (HS), and vertical sync (VS) [36]. Firstly, VGA converts the digital signal into an analog signal in computer and sends the signal to the LCD display, and then, the display converts the analog signal into a digital signal to a picture. Generally, when the analog signal exceeds 1280
1024 resolution, obvious error will occur. The higher the resolution is, the more serious the error is. Therefore, VGA is being gradually replaced by the high-definition multimedia interface (HDMI). High-definition television (HDTV) mainly supports the following three formats: ① progressive scan 1080p, 1920
1080p, about 2.07MP (megapixels) per frame; ② interlaced (interlaced scan) 1080i, 1920
1080i, about 1.04MP per field or 2.07MP per frame; and ③ progressive scan 720p, 1280
720p, about 0.92MP per frame. The aspect ratio of HDTV includes 4:3 and 16:9. HDTV format has been widely used in terrestrial broadcast television, cable television, satellite television, DVD, etc. [37]. The MPEG-1 (Moving Picture Experts Group Phase 1), which was developed in 1993, brings three standards for Digital Video Broadcasting (DVB): ① DVB-S (for satellite television), ② DVB-C (for cable television), and ③ DVB-T (for terrestrial broadcast television). DVB supports both MPEG-2 and H.264, also known as MPEG-4 AVC (advanced video coding) standards. AVS (Advanced Video coding Standard) and AVS+ are the audio and video standard proposed by China, and its encoding performance is basically equivalent to H.264 (or H.264/AVC). H.265 (or H.265/HEVC) is a new-generation standard of high-efficiency video coding (HEVC) based on H.264, while AVS2, the new-generation standard of AVS, has a competitive performance of H.265/HEVC. From SDTV and VGA to HDTV and DVB, as well as related standards of HEVC and AVS2, these standards contain a very rich content, and the application scenarios are also very broad, so that many types of interface IC chips are needed and to be developed. These requirements create many challenges for the IC design of HDTV products.

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High-Definition Multimedia Interface IC High-definition multimedia interface (HDMI) is a proprietary audio/video interface for transmitting uncompressed high-definition (HD) video data; multichannel surround sound audio data and consumer electronic control (CEC) signal over a single cable between electronic devices [38]. HDMI can be utilized with high-bandwidth digital content protection (HDCP) to prevent unauthorized copying of audio and video content for copyright protection. HDMI also supports digital audio formats such as DVD audio, which enables multichannel 96 kHz or stereo 192 kHz digital audio transmission and uncompressed audio and video signal transmission. The HDMI system module is shown in Fig. 14.13. HDMI can be used in set-top boxes, DVD players, personal computers, game consoles, amplifiers, digital speakers, and televisions. As EDID (extended display identification data) and DDC (display data channel) are both supported by HDMI, devices with HDMI feature “plug and play” and a “negotiation” is performed between the source and display device automatically to select the most appropriate video/audio format. HDMI 2.1, the latest version officially announced in January 2017, adds support for 4K and 8K ultra-high-definition videos with a maximum data rate 14.4 Gbit/s. Meanwhile, there is no need for digital/analog or analog/digital conversion before any signal transmission.

Fig. 14.13 HDMI system module. DDC display data channel, EDID extended display identification data, CEC consumer electronic control, HEAC HDMI, Ethernet, audio, control, HPD hot plug detect

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Commonly used HDMI chips are HD transmitter, HD receiver, HD splitter, HD switch, HD converter, HD matrix, etc. Well-known manufacturers are Silicon Image, Pericom, Explore, CAT, etc. Additionally, the DisplayPort (DP), the successor of DVI (Digital Visual Interface) and VGA, has been mainly used between computers and monitors, and the newer video cards and computers in DP [39] are integrated with HDMI and DVI. Recently, HDMI Licensing, LLC, [40] has released the HDMI transfer mode developed by HDMI Founders for the USB type-C specification, which allows HDMI-enabled source devices to connect to HDMI-enabled displays directly, using USB type-C connectors. This enables local HDMI signal transmission, without any demand for protocols and connectors, adapters, or hardware protection devices, but over a single cable.

Advanced Technology Attachment Interface In 1984, IBM launched Advanced Technology (AT) Personal Computer (PC) which featured parallel interface Advanced Technology Attachment (ATA); the original parallel ATA was then called PATA since Serial ATA (SATA) was launched in 2003 [41]. At present, SATA dominates over PATA according to the market share. ATA is highly related to disk drive which is realized by integrated drive electronics (IDE). Generally, ATA is a disk-controlling technology and IDE a disk-driving technology. Normally either of them stands for the other. Development and applications of ATA are related to IDE, as they belong to IDE technology. Initially, IDE was only used as an interface between controllers and disks. International standard organizations provided disk industrial standards according to ATA interface specifications in a way that generates ATA Standard. Small computer system interface (SCSI) is used to connect computers to peripheral devices [42]. SCSI standard defines commands, protocols, electrical interfaces, and optical interfaces. SCSI mostly has application in disk drive and magnetic tape drive and connection to other equipment, such as scanner and CD driver. SCSI is a set of parallel interface standards developed by ANSI, while PATA was made from ATA interface, as one kind of SCSI interfaces for early PC product. Synonyms and other informal names of ATA/ATAPI are used at the moment, especially Extended IDE (EIDE) and Ultra ATA (UATA). Either ATA or SATA of host computer control chip is integrated into each mainboard, enabling connection to four devices at least. Most microprocessors and motherboard controllers are configured with SATA interfaces, such as products from Intel, IBM, and AMD. Up to date, ATA (IDE) interfaces can be categorized into ATA-1 (IDE), ATA-2 (Enhanced IDE/Fast ATA, EIDE), ATA-3 (Fast ATA-2), Ultra ATA, Ultra ATA/33, Ultra ATA/66, Ultra ATA/100, and Serial ATA. ATA interfaces are modified and improved many times. First generation of ATA interfaces is ATA-1, namely the first standard specification being used in desk 386 series of Compaq (acquired by HP in 2013). It is regulated as master/slave structure with following version being published successively ATA-2, ATA-3, ATA-4, ATA-5,

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ATA-6, ATA-7 and Compact Flash6.0. ATA-4 regulates the transmission rate of 16.7–33.3 MB/s, that of ATA-7 up to 133 MB/s, and that of Compact Flash6.0 up to 167 MB/s. First-generation SATA interface (SATA version 1.0) was released on January 2003, featuring communication rate of 1.5 Gbit/s. The second-generation SATA version 2.0 (3 Gbit/s, 300 MB/s and Serial ATA-300) was published on April 2004, compatible with SATA 1.5 Gbit/s version. Physical layer specifications of SATA version3.0 (6 Gbit/s, 600 MB/s and Serial ATA-600) were drafted by SATA International Organization (SATA-IO) in July 2008. And its final version 3.0 was provided on May 2009. SATA version 3.3 was published in February 2016, featuring transmission rate up to 16 Gbit/s. At present, ATA interface products have broad applications in computer data processing and transmitting devices, including mainboard, disks, CD-ROM, and other things. These products are usually integrated on internal devices in the form of chips, featuring simple connection, high-speed transmission, and meeting the requirement of cascade connection of multiple devices. It became one of indispensable interfaces for computers.

DDR SDRAM Interface Double data rate synchronous dynamic random-access memory (DDR SDRAM) is briefly denoted as DDR. Samsung demonstrated the first DDR SDRAM prototype in 1996, with the DDR interface double pumping (transferring data on both the rising and falling edges of the clock signal), to achieve double data rate (or two words per clock cycle) than a SDR SDRAM (single data rate SDRAM, SDR SDRAM,). DDR interface connects DDR to DDR physical interface (PHY) and DDR controller. A DDR interface (DDR I/F) entails each DDR module transferring data to/from the memory controller by means of several digital data streams [43], which are accompanied by a strobe signal. As these data can flow both from the controller to the DRAM (write operation) and from the DRAM to the controller (read operation), these digital lines are bidirectional in nature. The DDR interface standard is defined, upgraded, and maintained by the JEDEC organization. The existing protocol standards are DDR (JESD79), DDR2 (JESD792) DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209). LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), and LPDDR4X (JESD209-4-1); LPDDR5 and DDR5 protocols are under development. There is also a GDDR (graphics DDR) interface for graphics processing chips. The characteristics of the DDR interface protocols are shown in Table 14.4 [44–46]. From the system level, the main chip needs to access the memory DRAM (in the synchronous working state, that is, SDRAM) through the DDR interface, so the DDR controller and the DDR physical interface (PHY) need to be included in the main chip design. The DDR controller is used to process SoC access to DDR

Bank group Maximum bank number Monolithic width/bit On chipresistor matching Reference voltage training CRC DBI

Burst length (BL) I/O voltage Command/ address bus

Feature Peak data transfer rate/ (Mbit/s) Bus feature

4, 8

1.8 V SDR command sampling 0 8

4, 8, 16

ODT signal required N

N N

2.5 V SDR command sampling 0 4

4, 8, 16

N

N

N N

Single channel

Single channel

2, 4, 8

DDR2 800

DDR1 400

N N

N

ODT signal required

4, 8, 16

4 (burst chop, BC), 8 1.5 V/1.35 V SDR command sampling 0 8

Single channel

DDR3 2133

Table 14.4 Comparison of DDR/LPDDR standards

Y Y

Dynamic, ODT signal not required Y

4, 8, 16

4 (burst chop, BC), 8 1.2 V SDR command sampling 2, 4 16

Single channel

DDR4 3200

N N

N

N

16, 32

1.8 V DDR command sampling 0 4

2, 4, 8, 16

Single channel

LPDDR 400

N N

N

N

16, 32

1.2 V DDR command sampling 0 8

4, 8, 16

Single channel

LPDDR2 1066

N N

N

Support DQ

16, 32

1.2 V DDR command sampling 0 8

8

Single channel

LPDDR3 2133

N Y

Y

Support (CA, DQ)

16, 32

1.1 V SDR command sampling 0 8

Multichannel 16 bit per channel 16, 32

LPDDR4 4266

N Y

Y

Support (CA, DQ)

16, 32

0.6 V SDR command sampling 0 8

Multichannel 16 bit per channel 16, 32

LPDDR4X 4266

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Fig. 14.14 Structural diagram of DDR main chip

commands. It supports bus multiport arbitration and maps the arbitrated command address to the DDR address space. The DDR PHY converts the DDR controller’s access SDR signal into a DDR dual-edge data access signal and sends it to the appropriate DRAM (or SDRAM) according to the electrical characteristics required by the DDR PHY; the sampled read data are converted to a single edge data transfer to the DDR controller. The structure of the DDR main chip is shown in Fig. 14.14. Some DDR PHYs also include DDR initialization, eye diagram training, and ZQ calibration. The DDR controller is interconnected with the DDR PHY by a DFI (DDR PHY Interface) bus defined by the DDR PHY. This interface defines the handshake between the DDR controller and the DDR PHY, normalizing the interface design, and the current major controllers and PHY IP vendors follow this protocol. At present, the mainstream suppliers of DDR SDRAM chips are Samsung, SK Hynix, and Micron. Each company can provide a full range of DDR SDRAM chips of various capacity and speed grades, such as DDR4 SDRAM, DDR3 SDRAM, DDR2 SDRAM, DDR SDRAM, GDDR, LPDDR4, LPDDR3, and LPDDR2. These DDR chips are packaged in VFBGA, WFBGA, TFBA, PoP, FBGA, and UFBGA. The application market of DDR SDRAM is very broad: For the consumer market, there are many DDR chips with multiprotocol interface. For example, monitoring products and set-top boxes mainly use hybrid DDR chips (DDR3, DDR4, and LPDDR3). In-vehicle devices mainly use DDR3 and LPDDR2, LPDDR4 and other chips that meet the vehicle standard; smart watches generally use LPDDR3, LPDDR4, and LPDDR4X; mobile terminals generally use LPDDR4, and some use LPDDR4X to further improve performance and reduce power consumption; UAVs generally use DDR4, LPDDR3, and LPDDR4; in the server market, low-end PCs typically use DDR3 UDIMMs, DDR4 UDIMMs, and high-end servers use DDR4 RDIMMs, DDR4 RLDIMMs, and NVDIMMs [46, 47].

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Protocol Converter IC Protocol converter, also called interface converter, works to convert one device protocol into the other device protocol including data information, events, commands, and time synchronization information in ways that realize mutual operation among devices. The ICs for interface conversion are referred to as interface conversion ICs. Protocol converter electronics [48] has broad applications in electricity generation, transmission and distribution of electricity, oil and gas, automation, public utility, remote monitor, and control. Interface conversion ICs (or converters) include the following categories: ① Specific interface conversion chip works to enable seamless connections among various customer electronics, commercial computers, and commercial multimedia devices, such as ST Mystique Series DisplayPort and HDMI interface converter. ② Special interface conversion chips are used as a specific network processor. It tends to convert network data format into general data format based on TCP/IP protocol. ③ Embedded network protocol chip works to realize interface conversion by employing protocol conversion function of the embedded system. It operates in two ways, viz. by processing software directly and by hardware chip from hardening of software, such as ARM’s embedded system. ④ Network control chip and single MCU chip, which can be functionally expanded according to various demands. With main applications in network protocol conversion, interface conversion ICs are connected to host computers with various high laver protocols for mutual collaboration that realizes distributed applications [49]. At present, the circuit is categorized into E1/Ethernet protocol converter, RS-232/485/422/CAN converter, RS-232/USB converter, and protocol converter based on field bus. For instance, Silicon Laboratories’ CP2102/CP2103 tends to realize mutual conversion between RS-232 protocols and USB protocols. Protocol converter or interface conversion ICs are capable of realizing connectivity between various technology standards. When updating, reforming, and restructuring existing communication, users can apply the circuit into original applications to enable multipoint networking of standards and telecommunication with no necessity to rewrite original communication software.

Controller Area Network Bus Controller area network (CAN) bus is a bus standard, initially designed to communicate between the microcontroller and device, used in automobiles, without a host. CAN bus is an ISO international standardized serial communication protocol, featuring high performance and high reliability. It is one of the most widely used field buses. In 1986, Robert Bosch GmbH (or Bosch) of Germany first proposed the CAN bus technology [50], and officially released at the Society of Automotive Engineers (SAE) conference in Detroit. The first CAN controller chip produced by Intel and Philips was launched in 1987. The 1988 BMW 8 Series is the first vehicle to be produced on a CAN bus-based multiroute system. Subsequently, the CAN bus

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technology is certified to ISO 11898 (the 2003 standard was updated in 2015) standard [1] and ISO 11519 (vehicle area network, VAN) standard [51]. The CAN controller converts the transceiving information into a compliant CAN frame on the bus via the CAN transceiver. The CAN controller chip can be a standalone chip or a chip containing a microcontroller. The CAN transceiver is the physical interface between the CAN protocol controller and the CAN bus, which has a level-shifting function that converts digital protocol information into analog signal communication. In automotive electronics, the CAN bus is often used in key areas such as engine control, ABS systems and airbags, and those important parts to guarantee car safety [52]. Therefore, the CAN bus system has strict requirements on electromagnetic interference (EMI) and electrostatic discharge (ESD) standards. It is necessary to ensure that the system is not affected by external interference or interfere with the normal operation of other electronic components. In addition, for some devices used outdoors, the CAN bus interface also needs to use a large current surge protection circuit to improve system protection. CAN bus is also widely used in the fields of train, aviation, ship, building, medical equipment, machinery manufacturing, traffic management, etc., due to its high reliability, real-time performance, and flexibility. These unique technical features, such as a wide range of applications, and as an international standard, have further promoted the rapid development of CAN bus.

Inter-Integrated Circuit Bus In 1982, Philips Semiconductor (now NXP) developed a two-wire, synchronous, multimaster, multislave, packet-switched, single-ended, and serial computer bus, which is called inter-integrated circuit (I2C, I2C, or IIC) bus [53]. The I2C bus is used for the communication connection between integrated circuits. The I2C bus supports IC connections from any manufacturing process (nMOS, CMOS, bipolar) devices. The I2C bus has two bidirectional signal lines, a serial data line (SDA) and a serial clock line (SCL), which are connected to the power supply through a current source or pull-up resistor. When the bus is idle, both SDA and SCL are pulled high, as shown in Fig. 14.15. The typical supply voltage VDD1 is +5 V or

Fig. 14.15 Multisupply voltage devices sharing a I2C bus

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+3.3 V. It also allows other supply voltages (VDD2/VDD3) to be used. Devices with different supply voltages can share the same bus. The I2C serial bus has fewer connections and a simpler structure, thus greatly simplifying the hardware design and reducing power consumption of the system. Usually, I2C bus is divided into low-speed mode (10 kbit/s), standard mode (100 kbit/s), fast mode (400 kbit/s), and high-speed mode (3.4 Mbit/s) according to different data transmission speeds, among which fast mode and high-speed mode are more widely used in embedded systems. The I2C bus is a multimaster bus with multiple devices with the ability to control the bus. With SDA and SCL, the host (usually a microprocessor) can control the transfer of data on the bus; each device connected to the I2C bus is assigned a unique address that the host addresses and communicates with. Simple interface mode and efficient transmission rate make the I2C bus widely used in the field of microelectronic communication control, with a wide variety of related products. For example, the I2C bus is used for buffers, repeaters, hubs, and expanders in addition to audio and video chips. The I2C bus can also be used for level shifters of different power supply voltages and communication channels for IC sensors. Besides, a large number of I2C buses are used in smartphones. The improvement and expansion of the I2C bus have greatly facilitated the development of the bus. For example, Intel, NEC, TI, ST, etc., have also developed some similar standards. Intel defined the system management bus (SMBus or SMB), a subset of the I2C bus, in 1995; SMB [54, 55] is most commonly found in computer motherboards for communication with the power source for on/off instructions.

High-Frequency Tuner The high-frequency tuner is mainly used to tune the received TV signal, that is, to select, amplify, and convert the video signal received by the antenna, which is the forefront circuit of the TV signal channel. The block diagram of the high-frequency tuner circuit is shown in Fig. 14.16. It includes VHF (very high-frequency) tuner and UHF (ultra-high-frequency) tuner to

Fig. 14.16 Block diagram of the high-frequency tuner circuit

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Table 14.5 Classification of high-frequency tuner Divided by tuning method Mechanical high-frequency tuner Electronic high-frequency tuner

Divided by the range of receiving TV channels VHF high-frequency tuner UHF high-frequency tuner Ordinary full-channel high-frequency tuner Cable TV full-channel high-frequency tuner

process signals in different frequency bands. The VHF tuner includes input circuit, high-frequency amplifier, local oscillator circuit, and mixer circuit. The UHF tuner includes input circuit, high-frequency amplifier, and frequency conversion circuit. The working principle of the two tuners is basically the same, receiving highfrequency television signals of different channels from the antenna, selecting the television channel through the input circuit, and suppressing interference of adjacent channels and other signals; after frequency selective amplification, mixing with the local oscillator signal, and finally, the IF (intermediate frequency) TV signal is output through the UHF intermediate amplifying circuit. Since the high-frequency tuner is susceptible to electromagnetic interference, the high-frequency tuner is usually placed in a metal box to shield electromagnetic interference. The high-frequency tuner can be divided into mechanical high-frequency tuner and electronic high-frequency tuner according to different working modes, as shown in Table 14.5. Regardless of tuning method, the tuning parameters of the input circuit, the high-frequency amplifier, and the local oscillator circuit must be changed together to switch the TV channel. Depending on the application, common electronic high-frequency tuners have antenna high-frequency tuner, HDTV ATSC (Advanced Television Systems Committee) high-frequency tuner for watching high-definition digital TV, radio high-frequency tuner such as FM (frequency modulation, 88–108 MHz) radio tuner, TV high-frequency tuner card (for watching TV on computer), and TV digital network high-frequency tuner [56, 57]. As the front-end component of the TV signal channel, the high-frequency tuner plays a decisive role in the performance of the whole machine. There should be several aspects to be noted in the design process: first, to achieve impedance matching with antennas, feeders, and amplifier circuits; second, to achieve higher power gain and smaller noise figure, while stronger automatic gain control capability of high-frequency amplifier; third, its local oscillator frequency is stable and has a proper pass band with good selectivity. With the development of technology, circuit integration and reliability requirements are getting higher and higher. Highfrequency tuner is also made more sophisticated with more excellent performance.

Digital Video Broadcasting Modulation/Demodulation Digital Video Broadcasting (DVB) is an internationally recognized standard for digital television broadcasting, maintained by the DVB Project [58]. The DVB Project is an international industry consortium with more than 300 members,

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initiated by Joint Technical Committee (JTC) of European Telecommunications Standards Institute (ETSI) [59], European Committee for Electrotechnical Standardization (French for Comité Européen de Normalisation Électrotechnique, CENELEC), and European Broadcasting Union (EBU). Compared to traditional analog TV transmission systems, the DVB standard is used in television transmission systems using all-digital technology for communication. The main components of the DVB standard include data scrambling, error correction coding, digital modulation, equalization and synchronous clock extraction, as well as baseband interfaces, baseband filters, and IF filtering. The core technologies of the DVB system are error correction coding, digital modulation, and echo equalization. Digital modulation includes quadrature phase-shift keying (QPSK), quadrature amplitude modulation (QAM), and orthogonal frequencydivision multiplexing (OFDM). The DVB standard is a general-purpose digital television system specification based on the conversion of different transmission methods. The transmission of DVB digital video broadcasting system mainly transmits through cable (corresponding standard is DVB-C/C2) [59], satellite (corresponding standard is DVB-S/S2), and terrestrial wireless (corresponding standard is DVB-T/T2). The main difference between these transmission methods is the different modulation schemes used for different applications. (1) Digital Video Broadcasting—Cable (DVB-C) that uses VHF/UHF carrier and QAM (16-QAM, 32-QAM, 64-QAM, 128-QAM, or 256-QAM) modulation, with cable TV networks as transmission medium, has a wide range of applications. (2) Digital Video Broadcasting—Satellite (DVB-S) uses SHF carrier and QPSK, 8-PSK, or 16-QAM modulation. Compared to DVB-S, DVB-S2 [60] has more modulation modes like QPSK, 8-PSK, 16-APSK, or 32-APSK. With satellite as the transmission medium, DVB-S2 is designed for the transmission characteristics of satellite signals which meet the bandwidth requirements of satellite transponders. This type of transmission has a wider coverage and a larger number of programs. (3) Digital Video Broadcasting—Terrestrial (DVB-T) uses VHF/UHF carrier with combined modulation method of 16-QAM or 64-QAM (or QPSK) and coding orthogonal frequency-division multiplexing (coded OFDM, C-OFDM) [61] and also can support layered modulation. Four sets of TV programs can be transmitted in 8 MHz bandwidth, with high transmission quality, and are well covered in local area. It has outstanding advantages in the mixed transmission with the current analog TV. The block diagram of DVB transmit and receive system is shown in Fig. 14.17. DVB transmitter encodes then multiplexes audio and video signals and finally transmits the modulated RF signal. DVB receiver implements the opposite working process of the transmitter, receives the RF signal for demodulation, de-multiplexes, and finally decodes completing the reception. Since different digital video broadcasting systems correspond to different modems, demodulator chips integrated with digital cable broadcasting system standards (DVB-C), digital satellite live broadcasting system standards (DVB-S), and digital terrestrial broadcasting system standards (DVB-T) have been produced. The chip is implemented in small size and multistandard demodulation scheme, which simplifies hardware and software

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Fig. 14.17 Block diagram of DVB transmitting and receiving system

design. In addition, the integration of multistandard protocols in one chip reduces the number of pins, thereby reducing the number of peripheral components and providing a highly integrated system solution.

Mobile Communication IC Though not all cell phones are mobile, people today use “mobile” and “cell” interchangeably as mobile or cell phones have the same features. Mobile communication network connects the terminals and network devices through a wireless channel in cellular wireless networking manner to perform information exchange between mobile users. Terminal mobility is the main feature of mobile communication networks. It can be used for handoff and automatic roaming across local networks to transmit voice, data, video images, etc. [62]. The progressing of mobile communication networks drives the development of communication ICs, toward higher integration, faster speed, more functions, and lower power consumption. Core IC in the mobile terminal includes radiofrequency (RF) IC and baseband IC. The RF IC is used for implementing RF transceiver, frequency synthesis, and power amplification; the baseband IC is responsible for signal processing and protocol processing, synthesizing the baseband signal for transmission, and decoding the received baseband signal. In addition, power management and multimedia processing ICs are also important parts of mobile terminals. The third-generation (3G) mobile communication technology combines wireless communication with multimedia communication such as the Internet, which can process various media forms such as images, music, and video data streams.

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Compared with the previous two generations (1G, 2G), the data transmission speed of the third-generation mobile communication network is relatively fast, and data communication bandwidth is generally above several hundred kbit/s [63], so the IC chips are required to have strong data storage and processing abilities. Qualcomm RF and baseband ICs are technologically advanced in the industry, and they have a monopoly on code-division multiple access (CDMA) technology patents. Infineon, Maxim, Freescale, MediaTek, Broadcom, and other companies have also launched their own mobile phone RF transceiver and baseband chip solutions. The fourth-generation (4G) mobile communication technology that combines 3G technology with WLAN enables high-quality video image transmission and faster data transmission rate. The typical download rate is 15 Mbit/s (4G, LTE Cat4) and can reach 90 Mbit/s (4G+, LTE-Adv Cat16), which basically meets the requirements of all users for wireless transmission applications. The requirements of the 4G system for communication ICs have also increased accordingly. HiSilicon IC design at Huawei has increased the market share of domestic 4G mobile phone chips. The performance of HiSilicon Kirin 960 chip has reached the same level as Qualcomm Snapdragon 820; HiSilicon’s Kirin 980 (2019) has announced with world-leading performance. Table 14.6 shows the comparison of 1G–5G wireless communication methods, typical data rates and year of implementation. With the rapid development of smart terminal technology, mobile data traffic has increased dramatically. In addition to 1G adopting analog mode of wireless mobile communication, the existing wireless 2G–4G digital communication technology has continuously improved the transmission speed. HD video such as VR, AR, and smart home propose higher requirements on the transmission speed of the fifth generation, 5G, mobile communication [64]. For 5G, some upload speed has reached 60 Mbit/s (suitable for 8K UHD) and expected to be 100 Mbit/s whenever needed, and the download speed is 1 Gbit/s and peak to be 20 Gbit/s. It is the worldwide interest and activity to promote 5G networks, and major semiconductor companies are investing heavily on 5G communication ICs [65]. Table 14.6 Comparison of 1G–5G wireless communication methods Technical generation 1G 2G 2.5G 3G 3.5G 4G 5G

System technology AMPS (Analog) GSM, TDMA, CDMA GPRS, TDMA WCDMA, CDMA2000 HSDPA, HSPA WiMax, LTE, Wi-Fi 5G NR, Wi-Fi

Upload rate, download rate 14.4 kbit/s, 14.4 kbit/s 9.6 kbit/s, 14.4 kbit/s

Enabled time 1970 1990

9.6 kbit/s, 115 kbit/s 64 kbit/s, 2 Mbit/s

2001 2004

384 kbit/s, 14.4 Mbit/s

2006

8 Mbit/s, 20 Mbit/s

2012

60 Mbit/s, 1 Gbit/s

2019

Feature Voice only Data and voice Internet access Cell phone and PDA Higher data rates Supports HD video Supports FR1, FR2

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Audio Codec IC An audio codec is a device or program that is capable of encoding or decoding audio data streams. The IC for audio codec often appears as an IP design, viz. IP audio codec. The audio codec can represent high-fidelity (Hi-Fi) audio signals with a small number of bits while maintaining audio quality, effectively reducing the storage space and the bandwidth required for transmitting audio files. Audio codecs are widely used in smartphones and multimedia phones, digital cameras and digital video cameras, portable media players and portable audio players and telephone accessories. In the implementation of the hardware chip design, the audio encoding process converts analog audio signals into digital information and performs encoding. Besides, the audio decoding process decodes digital signals and converts them into analog audio signals. That is, the audio codec contains analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) that operate at the same clock and can be used for sound cards that support audio input and output. Moving Picture Experts Group (MPEG) is a working group of the ISO. MPEG-1 is designed to compress VHS-quality raw digital video and CD audio down to 1.5 Mbit/s (26:1 and 6:1 compression ratio, respectively). The MPEG-1 technology has made video CDs, digital cable and satellite TV, and DAB possible. The bestknown part of MPEG-1 is perhaps the MP3 audio format. Audio coding includes the following technologies: (1) MPEG-1 (VCD), which mainly solves multimedia storage problems, is a lossy data compression method [65]; (2) MPEG-2 (DVD), whose development can be divided into three phases as increased low sampling frequency for MPEG-1, multichannel extension for MPEG1 and Advanced Audio Coding (AAC) for MPEG-2 [66]; (3) MPEG-4 compression efficiency is further improved, with better interactivity, and it can store and transmit a variety of audio contents [67]; (4) AC-3 (Active Coding-3) [68], introduced in 1991, is a multichannel encoding technology based on AC-1 and AC-2, all developed at Dolby Laboratories. Among them, AAC (successor of MP3) [66] and AC-3 (or Dolby Digital, originally named Dolby Stereo) are high-fidelity, with high sampling rate audio standards, which are mostly used in high-definition digital TV, digital cinema, and other fields. AC-3 is a 5.1 format, which means that it provides five full-bandwidth channels: (1) front left, (2) front right, (3) center, (4) surround left, and (5) surround right. There is also a low-frequency effect (LFE) channel included, known as the subwoofer channel, for the sound needed for special effects and action sequences in movies. ADI, Cirrus Logic, IDT, and Maxim Integrated are audio codec IC providers. Some of the products available are using audio codec IC, VoIP technology-based phones, digital and analog media servers, and gateways. Other audio codec IC products include wearables such as smart watch, home speaker, or media player [69].

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Video Codec A video codec is a circuit or software that compresses and decompresses digital videos. Codec is a concatenation of “encoder” and “decoder.” The original videos were stored on tape as analog signals, and with the advent of optical disks, digital form storage gradually replaced analog form storage. Since recording and transmitting raw videos require a very large amount of storage and bandwidth, there is an urgent need for a method to reduce the amount of data used to represent original videos, whereby a solution for compressing digital video data came into being, and some related technologies were also been developing. The format of compressed data is in accordance with the video compression specification. Usually, the compression is lossy, that is, the compressed video loses some information existing in the original video. Since there is not enough information to accurately reconstruct the original video, the decompressed video quality will be lower than the original uncompressed video quality. There are more complex relationships among video quality, the amount of data used to represent videos, the complexity of encoding and decoding algorithms, the sensitivity to data loss and errors, the ease of editing, random access, and end-to-end latency. Common video encoding methods are H.26X series (including H.261, H.262, H.263, H.264, and H.265), MPEG series (MPEG-1, MPEG-2, MPEG-4), and other encoding methods such as AMV and AVS. There are many types of software video codec on personal computers and consumer electronics, and users can install multiple video codecs on these devices to meet different needs. Video codecs are widely used in DVD/VCD playback, video recording, video broadcasting, and other applications. MPEG was established in 1988 by the initiative of Hiroshi Yasuda (Nippon Telegraph and Telephone) and Leonardo Chiariglione. The first MPEG standard was MPEG-1. It provides the video resolution of 352
240 at 30 fps (frame per second). The quality of MPGE-1 is lower than VCR (video cassette recorder). Released in 1997, MPEG-2 is used on DVD and supported by Blu-ray disk; it provides the resolution of 720
480 and 1280
720 at 60 fps. MPEG-3 was designed for HDTV but was abounded and incorporated into the MPEG-2. Standardized in 1998, MPEG-4 has a higher video quality than its precedents. The wellknown MP4 video file is related to MPEG-4. MPEG-7 was standardized in ISO/IEC 15938, and it is a multimedia content description standard. There is also MPEG-21 for digital data processing and creating a dynamic and interactive multimedia format. IC design for video codec-based technology is usually in the form of various IP designs [70]. These IP products are offered for processing HEVC (High-Efficiency Video Coding, known as H.265), IP for UHD (4K 60 fps), VCU (Video Codec Unit), 24bit Audio ADC/24bit Video DAC, etc. For images of multimedia and the related interface technology, separate MIPI standards are to be followed; typical MIPI IP includes MIPI controller and MIPI PHY [71].

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Power Line Communication (PLC) Power line communication (PLC), also known as power line carrier communication, is a communication technology that uses power lines as a transmission medium [72]. The PLC technology can make full use of the extensive line resources of the power distribution network to transmit data on power lines of different voltage levels such as high-voltage power lines (35 kV and above), medium-voltage power lines (10 kV class), or low-voltage distribution lines (380 V/220 V). The PLC technology transmits data by loading the modulated high-frequency signal on the transmission current, transmits the signal to the receiving end, and then filters and demodulates to recover the original signal, thereby realizing information transmission. PLC technology can be divided into broadband over power line (BPL) communication technology and narrowband over power line (NPL) communication technology. (1) BPL communication bandwidth is generally limited to 2–30 MHz, the communication rate 1 Mbit/s or more. Nowadays, spread spectrum communication techniques of which OFDM as the core are widely used, and a broader bandwidth provides a wider development space for a variety of broadband data services and broadband markets. (2) The NPL communication bandwidth is limited to 3–500 kHz, and the communication rate is lower than 1 Mbit/s. The common PSK (phase-shift keying) technology, DSSS (direct-sequence spread spectrum) technology, and chirp technology are mainly used to control communication with the data acquisition network, which can satisfy the communication requirement of low data volume well, with a low cost and easy to implement. The PLC chip is a two-way transmission system composed of modules such as a modulator, an oscillator, a power amplifier, a T/R (transmit/receive) switch, a coupling circuit, and a demodulator. When transmitting data, the oscillator provides carrier signals to the modulator, and data signals modulated by the modulator are amplified at the amplifier stage and loaded onto the power line through the T/R switch and the coupling circuit. When receiving data, modulated signals enter the demodulator via the coupling circuit and the T/R switch, and demodulated and extracted raw data signals are sent to the digital device received by the next stage. PLC can convert a common power grid into a communication network, enabling smart grid connections including the connection of smart meters, smart homes, automated monitoring, and streetlight monitoring. At first, power companies could only transmit data on the power line at a speed of 1 Mbit/s. With the maturity of PLC technology, PLC of 2 Mbit/s, 14 Mbit/s, and 45 Mbit/s bandwidths has gradually spread. PLC technology is also moving toward higher speed to above 200 Mbit/s. For the domestic grid environment, it needs to optimize the SoC design of the power line communication. For example, the analog front-end (AFE) design of the power line modem becomes very challenging. In addition, because the power line produces noises, these factors need to be considered in the architecture design to ensure data reliability. At the same time, developers need to optimize the design for different applications and working environments and comply with relevant protocol standards and modulation schemes. PLC products

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are available from several companies [73–76] worldwide, including various PLC-related products and applications.

Digital Subscriber Line (DSL) Digital subscriber line (DSL) technology is a digital communication technology based on ordinary telephone lines, which can transmit voice and data signals on the same telephone line. DSL mainly includes ISDN DSL (IDSL), high-speed DSL (HDSL), symmetric DSL (SDSL), asymmetric DSL (ADSL), rate-adaptive DSL (RADSL), and very high bit rate DSL (VDSL), etc., which are collectively called xDSL technology [77]. Since DSL technology can achieve a downlink transmission rate of 100 Mbit/s (VDSL2+) on a common telephone twisted pair, it is widely used in digital broadband communication because it meets the requirements of low cost and high bandwidth and can be used as a supplement to the passive optical network (PON). DSL can achieve high-speed digital data transmission on ordinary analog telephone lines by using high signal transmission frequency and specific modulation technology on twisted-pair copper lines. There are four kinds of code modulation and demodulation methods: 2B1Q, QAM, CAP, and DMT. Since DSL technology needs to be separately modulated and demodulated at both ends of the transmission line, xDSL ICs take the form of a chipset solution in practical applications. The xDSL chipset mainly includes the analog part and the digital part: The main function of the analog part is to transmit and receive data signals, through analog front end (AFE) and lines drivers, and digital-to-analog conversion, analog-to-digital conversion, anti-aliasing, signals filtering, gain controlling, lines driving, and other functions are implemented. The digital part is mainly composed of framer/mapper module, DSP module, microprocessor core, and other functional modules to realize DSL frame structure processing, data encoding, communication schedules controlling, and other functions. DSL and its related ICs include modems or routers or a modem/router combo; these modems/ routers can connect to work with copper wires at the input; the output can be a data wire(s) or wireless—the latter has become much more common today.

Passive Optical Network and Cable Modem Optical fiber communication is a communication method for transmitting optical wave signals by using optical fibers, which has the advantages of wide transmission frequency band, large communication capacity, strong anti-electromagnetic interference capability, small signal attenuation, and high transmission quality. Besides, it is one of the main technologies of modern communication. The currently widely used fiber-optic communication system is a digital code–intensity modulation–direct detection system, which consists of a light transmitting part (a light source and an optical transmitting end), an optical transmitting part (an optical fiber and an optical

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repeater) and a light receiving part (a light receiving end, a light detecting and a converting module). The optical transmitting end converts data electrical signals into optical signals of light intensity modulation, sends them to the optical fiber, and transmits optical signals to the optical receiving end through the optical fiber. Then optical signals are detected and converted into an electrical signal by the receiver and demodulated to recover the original data information [78]. With the development of high-speed Ethernet, passive optical network (PON) has become a key technology for broadband access. PON is mainly divided into APON (Asynchronous Transfer Mode PON, ATM PON, i.e., earlier ITU-T G.983 standard), GPON (Gigabit PON), and EPON (Ethernet PON). Chips design companies are introducing ICs for new-generation PON network equipment, striving for high integration and providing cost-effective solutions for system vendors to achieve the lowest system cost. The ITU-T G.987 standard defines that the downlink transmission rate of GPON is 10 Gbit/s, and the uplink transmission rate is 2.5 Gbit/s; according to the IEEE 802.3av and IEEE 802.3ah technologies, EPON can simultaneously achieve two downlink transmission rates of 10 Gbit/s and 1 Gbit/ s. The transmission line on the PON server consists of an optical line terminal (OLT) and multiple optical network units (ONUs), or optical network terminals (ONTs) at the customer premises. The IC requirements corresponding to GPON/EPON include the OLT chips at the service center, the ONU/ONT chips at the user end, and the relay chips of the optical transport network (OTN). Coaxial cable communication is a wired communication method. The coaxial cable is composed of some coaxial tubes. The common specifications are 2, 4, 6, 8, 12, 18, and 22 pieces of wire, which can be divided into small coaxial, medium coaxial, and so on. The coaxial cable has good transmission quality, small loss, and large capacity during transmission. Coaxial cable communication is mainly used for long-distance trunk line communication, which plays an important role in long-distance news communication trunk lines that require high-quality transmission and multiple service transmissions. Cable modem is used to modulate a certain transmission band of cable TV. The data to be transmitted is first transmitted through the cable television network, and cable television signals are sharing communication medium [79]; after reaching the receiving end, it is demodulated by the cable modem, and the transmission rate can reach 10 Mbit/s or more. Cable modem can be divided into two-way symmetric transmission and asymmetric transmission, one-way data transmission and two-way data transmission, synchronous and asynchronous. There are also external form, builtin from, and interactive set-top boxes of its appearances.

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70. Video Codec IP. https://www.design-reuse.com/sip/?q¼Video+Codec. Accessed 16 Feb 2020 71. MIPI. https://mipi.org/. Accessed 16 Feb 2020 72. PLC. https://en.wikipedia.org/wiki/Power-line_communication. Accessed 16 Feb 2020 73. HD-PLC. https://www.panasonic.com/global/corporate/technology-design/technology/hd-plc. html. Accessed 16 Feb 2020 74. PLC modem and MCU. https://www.renesas.com/us/en/solutions/key-technology/connectiv ity-wired/plc.html. Accessed 16 Feb 2020 75. PLC Drivers. https://www.microsemi.com/products/. Accessed 16 Feb 2020 76. Powerline Communication (PLC). https://www.cypress.com/products/powerline-communica tion. Accessed 16 Feb 2020 77. International Engineering Consortium. Digital Subscriber Line 2001 Comprehensive Report (IEC, 2001). ISBN 978-0-933217-95-9 78. GR-1209 Issue 4: Generic Requirements for Passive Optical Components (Telcordia Technologies, Arlington Heights, IL, USA, 2010) 79. IEEE Recommended Practices for Broadband Local Area Networks/IEEE Std 802.7-1989. Inst of Elect & Electronic (Piscataway, NJ, USA, 1990)

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Bo Wang, Yan Li, and Xin-An Wang

Contents RF and Microwave IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Frequency Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Duplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwave Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Millimeter Wave Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terahertz Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio (Receiver) Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Navigation Receiver IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wireless Fidelity Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bluetooth Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZigBee Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Frequency Identification Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

280 281 283 284 286 288 289 290 292 293 295 295 296 297 298 299 300

Abstract

RF CMOS products are in principle part of analog, mixed-signal IC products; RF ICs together with analog, mixed-signal contribute to about 15% of the total semiconductor products in the global market. In engineering practice, due to the specific nature, such as RF products in general operating at much higher frequency of 500 MHz and up to today’s 300 GHz, RF IC products are therefore listed in a separate catalog. Widely used in wireless communications (e.g., B. Wang · X.-A. Wang Electronic and Computer Engineering, Peking University, Shenzhen, China Y. Li (*) Shenzhen University, Shenzhen, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_15

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cellular networks, Bluetooth, ZigBee, Wi-Fi, GPS, etc.), RF IC products are commonly found in applications of mobile phones, IoT networking (e.g., RF ID), automotive radar, and many others. Typical RF CMOS IC includes RF power amplifier (PA), RF switch, low-noise amplifier (LNA), RF Mixer, Oscillator, Duplexer, and Filter; other RF products include microwave (MW) devices, millimeter (MM) wave devices, and terahertz (THz) devices. This chapter introduces commonly used commercial RF CMOS IC products and RF devices, their basic functions, features, applications, and some typical product names. Keywords

RF IC · Wi-Fi · RF PA · LNA · Wireless communications

RF and Microwave IC Products Radio frequency integrated circuits (RFICs) have been developed quickly since 1990s and become the main-stream RF products by replacing discrete RF devices gradually. RFICs and microwave ICs are found in the household, offices and industry applications, connection of the computers, mobile phones, electrical appliances, TVs, intelligent home, digital cameras, printers, projectors, etc.; and also enter the domain of municipal facilities and environment monitoring, such as noncontact payment, borrowing book at open library, building and frontier security monitoring, etc. On one hand, this benefits from the cost down due to the CMOS technology scaling, the main stream technology node advanced from 0.5 μm node (middle 1990s) to 130 nm node (2005), down to 16/14 nm node (2015). Due to the cost down, RFIC (e.g., Bluetooth, Wi-Fi, navigation chips) enters little by little into the civic applications in our daily life. On the other hand, the performances of CMOS technology have increased dramatically, approaching and even overpass the discrete devices or the III/V (element materials) devices. For example, the noise performances of the early CMOS devices were poor; they could not meet the strict requirements of the wireless communications, so only the more expensive III/V devices could be used. After 2000, as the technology evolved, the noise performances of the CMOS devices gradually achieved the strict requirements of the wireless communications and became main-stream products. Besides, the frequency of the RFIC increases continuously, from 500 MHz in the middle 1990s to 70 GHz at the beginning of 2000s, and up to 300 GHz in 2017. The applications of RFIC cover the frequency band of below 10 GHz, (e.g., 2G/3G/4G communication, navigation, Wi-Fi, RFID, Bluetooth), and the frequency band above 10 GHz (e.g., millimeter wave and THz applications) for broader applications. As the CMOS integration density increases and the chip size decreases, it appears that RFIC products can integrate multiple functions on a single chip. For example, in the wireless communication domain, the multimode multiband chips can be compatible with different communication systems. As more functions integrated in a single chip, the design of RFIC is also increasingly challenging.

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The main RFIC products include the following. 1. Radio Frequency IC Module: including the power amplifier (PA) which amplifies the output power, the low-noise amplifier (LNA) which amplifies the weak input signal and suppresses the noise, the mixer which up-convert or downconvert the RF signal, the oscillator which provides the high-frequency low-noise clock signal, the duplexer which separates the reception and transmission signals, and the filter which removes the signals with different frequency band, etc. 2. RF Devices: including the microwave devices, millimeter devices, and THz devices. 3. RF Integrated Chips: including the radio chips, navigation chips, Wi-Fi chips, Bluetooth chips, Zigbee chips, RFID chips, NFC chips, etc.

Radio Frequency Power Amplifier In 1996, Motorola successfully demonstrated an integrated power amplifier circuit on a silicon substrate based on GaAs and bipolar technology. Currently, GaAs is the most widely used and mature technology. PA is widely used in wireless communications and audio-driven applications, etc. Radio Frequency Power Amplifier (RF PA) can transform low-power RF signal into high-power signal, i.e., through amplifying small RF signal to produce a large output power. Basic applications of RF PA include driving another high-power signal source, transmitting antennas, and stimulating a microwave cavity resonator, among them driving antenna load is the most common [1]. According to the difference of the conduction angle of the device, PA can be categorized under Class-A, Class-B, Class-AB, and Class-C. A typical Class-A PA is illustrated in Fig. 15.1. A typical power amplifier consists of input matching network, transistor amplifier circuit, impedance conversion network, DC bias, and output impedance matching network. The load of Amplifier circuit is usually replaced by large inductance for enlarging the output range at constant supply Fig. 15.1 A typical Class A RF PA circuit

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voltage. In order to reduce the peak voltage of the output transistor and improve efficiency, a matching network is inserted between the amplifier and the output load in order to reduce the load resistance and thus transmit the power under lower output swing. The indices of RF PA performance mainly include: 1. 2. 3. 4.

Output Power Efficiency: (a) Drain Stage Efficiency Pout, (b) PAE (Power Added Efficiency) Power Gain Linearity, which includes: 1 dB Compression Points; IP3 (Third-order Intercept Point), and ACP (Adjacent Channel Power Ratio)

The additional power amplifier’s linearity and PAE, the range of which is between 10% and 60% have been the critical technology for PA and the key focus and hotspot of research. Currently the technology of enhancing linearity is mainly including feedforward, predistortion, power back-off, EER (Envelope Elimination and Restoration), LINC (Linear Amplification of Nonlinear Components), and Doherty amplifier. According to the performance, based on the work modes (linear or constant envelope), PAs are classified to linear PA and switch mode PA. Linear PA (Class A, B, AB, and C) has lower efficiency yet broader applications; switch mode PA (Class D, E, F) is an efficient nonlinear PA. In ideal condition, it can achieve 100% power efficiency. Driven by overdrive voltage, the output transistor is equivalent to an ideal switch, so that the transistor current waveform and voltage waveform will not overlap and improve the output efficiency. Performance of each type of PA is compared, as shown in the Table 15.1 below. With the development of the submicron CMOS technology, the characteristic frequencies of CMOS devices are greatly increased, RF PA in CMOS technology will be more prevalent as driven by the market [3]. Table 15.1 Performance comparison among different types of RFPA [2] Type of Class Working mode Conduction angle Output power Theoretical efficiency Typical efficiency Gain Linearity Drain voltage peak value

A Current source 2π

AB Current source π~2π

B Current source π

Medium 500%

Medium Medium 50%~78.5% 78.5%

35%

35%~60%

Low Super 2Vdc

Medium Good 2Vdc

C Current source 0~π

D E F Switch Switch Switch π

π

π

Low High 78.5%~100% 100%

High 100%

High 100%

60%

70%

75%

80%

75%

Medium Good 2Vdc

Low Bad 2Vdc

Low Bad 2Vdc

Low Low Bad Bad 3.6Vdc 2Vdc

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Low-Noise Amplifier The low-noise amplifier (LNA) effectively amplifies the signal while contributing very low noise. It is generally applied to the front of the signal receiving branch of the radio receiver and amplifies the received weak signal for later processing. LNA has a broad range of applications, such as high-sensitivity electronic detection equipment, radar systems, near-field communication, satellite communication cards. The factors that affect LNA are Noise Figure (NF), gain, input inflection loss, stability, bandwidth, and power consumption. Since the noise figure generated by the amplifier is directly superimposed on the input signal, it will severely interfere with the input signal. It is necessary to reduce the noise and improve the signal-noise ratio SNRin to improve the ability to suppress noise. The NF is defined as NF ¼ SNR , where out SNRin is the input signal-noise ratio, SNRout the output signal-noise ratio. The noise level of the amplifier cannot be zero, so the output noise is always greater than the input noise. The circuit of LNA connected to the input signal and it is equivalent noise model are shown in Fig. 15.2a, b, where AV is the gain of LNA, U 2n,RS is the thermal noise of antenna. U 2n is the output noise of LNA. One can reduce NF of circuit by increasing the circuit gain, but this method usually decreases the linearity. Since LNA does not have a large effect on the linearity of the receiver in most applications, its linearity is rarely considered in design. The input reflection loss of the low-noise amplifier, that is, the matching degree of the input resistance, is defined as the ratio of the reflected power to the incident power. Γ¼

2

zin  Rs , zin þ Rs

where RS is the equivalent signal source impedance, zin is the equivalent input impedance of LNA, in unit of dB. The lower the input reflection loss, the better will be, which requires the input impedance to match the source impedance as much

Fig. 15.2 Low-noise amplifier circuit and equivalent noise model

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as possible. LNA usually trades off the Noise Figure and Power consumption during design. The main topology of LNA can be divided into common source, common gate, and broadband topologies [1]. With the development of CMOS technology and the improvement of highfrequency performance, future LNA will develop in the direction of low-power consumption, high gain, and wide bandwidth [4].

RF Mixer RF Mixer or Frequency Mixer used in RF design is an important circuit in wireless transceivers that performs frequency conversion through the nonlinear or timevarying characteristics of the circuit itself. The main function of mixer is to convert the RF signal received by the analog front-end of the receiver into a low-frequency signal by down-conversion, and convert the low-frequency signal of the analog front-end of the transmitter into a RF signal by up-conversion. At present, mixers have been widely used in radar, communications, radio and television, remote sensing telemetry, and other fields. The working principle of mixer is to multiply the two input signals in the time domain to complete the addition and subtraction of the frequency in frequency domain. When two sinusoidal signals ω1 and ω2 are input to the multiplier, an output consisted of a sum frequency component (the frequency is ω1 þ ω2) and a difference frequency component (the frequency is ω1ω2) can be obtained. Therefore, the frequency is converted [5]. A mixer typically has two inputs (a local oscillator input and a receiving or transmitting signal input) and an output port. The symbols and functions are illustrated in Fig. 15.3. Mixers can be divided usually into active and passive mixers [1] while active mixers can be divided into double-balanced mixers, single-balanced mixers, and unbalanced mixers. And passive mixers can be divided into mixers based on a single CMOS switch, single-balanced passive mixers, and double-balanced passive mixers. The single-ended CMOS mixer is the simplest mixer structure. It has two singleended inputs and mainly consists of three parts in circuit structure: switch stage, transconductance stage, and load stage, as shown in Fig. 15.4. Single-ended CMOS mixer is simple in circuits, but the isolation of the RF port and the LO (Local Oscillator) input port causes loss of the RF signal, so the isolation of the circuit is not high.

Fig. 15.3 Schematic of symbols and function of a mixer

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Fig. 15.4 Schematic of single-ended CMOS mixer

Fig. 15.5 Schematic of double-balanced passive mixer (Gilbert mixer)

The current commutated active mixer with double-balanced structure is shown in Fig. 15.5. This type of mixer is characterized by its ability to effectively suppress interference, useful intermodulation components, and provide a certain conversion gain with better isolation. These excellent properties make them widely used in wireless transceivers. The main performance indicators of the mixer are noise figure (ratio of input signal-to-noise ratio to output signal-to-noise ratio), conversion gain (ratio of output signal to input signal), linearity (usually described by 1 dB compression point and third-order intercept point and determines the maximum input signal), and port isolation (the degree of interaction between the three ports in mixer) [6].

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In the future, how to implement high-performance mixer is a hot topic, and the key to solving these problems lies in the innovation of circuit architecture and the research and application of new semiconductor materials.

RF Oscillator Oscillator is an electronic circuit used to generate periodic analog signals usually in the form of voltage. Its main function is to generate an accurate reference frequency. Oscillators are used in a wide range of applications, including wireless communications, sensors, computers, medical equipment, and other fields. With self-sustaining mechanism, noise of a specific frequency inside the oscillator will be amplified and finally a stable periodic signal is formed and output. Most oscillators can be viewed as a feedback loop and analyzed in the perspective of feedback. The oscillator feedback analysis is shown in Fig. 15.6. Its transfer function is Uout ðωÞ H ðjωÞ ¼ : U in ðωÞ 1  H ðjωÞ If certain phase shift and loop gain conditions (Barkhausen conditions) are satisfied, the feedback system can realize the output of a stable oscillating signal with a specific frequency determined by its frequency selective network. Oscillator implemented in CMOS circuits is typically ring oscillator (RO), LC oscillator, and RC relaxation oscillator. Among them, RO is achieved by connecting an odd number of inverters in series in a closed-loop feedback form, and the output signal frequency is determined by the number of ring oscillator stages and the inherent delay of the inverter. A simple three-stage RO circuit is shown in Fig. 15.7. RO is very simple in circuit structure with a wide tuning range and multiphase output. From a perspective of manufacturing, RO can be manufactured in a standard CMOS process with a very small layout area. However, it is difficult for a RO to obtain lower oscillation frequency and low frequency-temperature sensitivity. Passive resonant devices for LC oscillators include inductors and capacitors. By connecting inductor L and the capacitor C in parallel, a LC oscillator is implemented and will resonate at a frequency of p1LC. Cross-coupled oscillator is a typical LC Fig. 15.6 Schematic of feedback analysis of oscillator

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Fig. 15.7 Schematic of a three-stage ring oscillator circuit Fig. 15.8 Schematic of a LC oscillator circuit

oscillator, as shown in Fig. 15.8. LC oscillator has excellent performance in high output frequency, high quality factor, and low noise, but remains great challenges in modeling the inductor device, increasing its narrow tuning range and decreasing the large power consumption. The performance indicators of an oscillator include mainly oscillation frequency, quality factor Q (the higher the Q value, the better the frequency selection characteristic), phase noise (the circuit output phase jitter caused by the device noise), and frequency stability (the ability for an oscillator to maintain a constant frequency in the long or short term) [7]. With the scaling of CMOS technology with lower chip voltage; how to design and implement high-performance oscillators with low-power consumption, high frequency, low noise, and large tuning range are hot research topics in future Internet of Things (IoT) era. RF oscillators are commercially available [8, 9].

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RF Duplexer Duplexers are used to isolate receiving and transmitting signals, so that receiving and transmitting circuit modules can share one channel (a pair of antennas). The duplexer is an important part of modern communication systems. The main functions of Duplexers include: suppressing mutual interference between receiving and transmitting signals; isolating frequency band, which means that it can separate multiple frequency bands which are contained in one signal source and, making impedance change so that signals can be transmitted with maximum power [10]. In the 1960s, Matthaei and Cristal first proposed a duplexer integrated design method for star-shaped common junctions. In the late 1970s, another method of synthesizing common junction microwave duplexer was proposed by Haine et al. In this method, channel filters are synthesized into dual-terminal filters. Since then, duplexers have been studied extensively [11]. The duplexer is a three-port device (Fig. 15.9). The common terminal (port 1) is connected with the external antenna, the transmitting side is connected with the external transmitting module via the transmitting filter TX and port 2, and the receiving side is connected with the external receiving module by the receiving filter RX and port 3. According to its working principle, duplexers can be divided into two types: time division duplexer (TDD) and frequency division duplexer (FDD) [12]. A TDD uses the same frequency band to transmit and receive signals, but do not transmit at the same time. TDD behaviors like a switch: when the signal is to be transmitted, the receiving module is cut off; when the signal is to be received, the transmitting module is cut off. A FDD can process different frequency signals at the same time. The implementation method is using filters to separate the transmission and reception channels. That is to say, two filters are tuned at the radio frequency rate and reception frequency respectively so that the two filters can isolate the sending and receiving ports and let the signals of the port pass through. There are three traditional methods to realize this type of duplexer: ① adding a directional coupling loop between the antenna and the two filters; ② tuning the circuit by using the admittance-elimination circuit (or reactance-elimination circuit) attached to the public terminal, thereby Fig. 15.9 General structure of duplexer

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reducing the mutual interference between the filters; and ③ the “fully complementary” duplexer, i.e., its input admittance (or input impedance) remains unchanged in the full spectrum. It can effectively cancel the interference between two channels. Frequency division multiplexing (FDM) is widely used [13] because of its higher efficiency and better anti-jamming ability. The traditional design methods mentioned above do not start from the overall structure, but only consider the influence of each filter separately, so these methods have limitations. At present, the mainstream of research is to find a more general design method which can synthesize the characteristic polynomials of duplexers and eliminate the influence among the filters. At the same time, the size of the duplexer is decreasing, and its developing trend is modularization. The main design indicators of duplexer are working frequency (the working frequency of duplexer should be larger than the frequency band of sending and receiving modules), bandwidth (the respective bandwidths of transmitting and receiving bands), isolation degree (to measure the isolation between transmitting and receiving ports), insertion loss (the attenuation of useful signals in the corresponding passband of each port), the matching impedance (duplexer should match the impedance of transmitting port, receiving port, and antenna, usually 50Ω). RF Duplexer Products are commercially available [14].

RF Filter A filter can effectively remove signals outside the selected frequency band to obtain the desired signal in the selected frequency band. The main purpose is to obtain or eliminate the signal at a specific frequency. Filters are generally used for signal transmission and processing, and have been widely used in aerospace, military, medical, telecommunications, communications, machinery, energy, and other fields. The original filter circuit is a passive circuit composed of a resistor, a capacitor, an inductor, etc. The rapid development of modern high-tech information technology and the improvement of the process of IC transistors are gradually promoting the rapid development of various new filter circuits such as RC active filters and digital filters. The basic principle of a filter is to block or turn on a specific frequency signal in a signal by utilizing the impedance characteristics of the inductor and capacitor. The filter has the characteristics of a frequency selective network, which is traditionally powered by electricity. A frequency selective network circuit is composed of a frequency selective function component such as a resistor, a capacitor, and an inductor. A common frequency selective network circuit composed of RC filters is shown in Fig. 15.10. The important performance indicators of the filter include cutoff frequency, ripple amplitude, passband bandwidth, quality factor, and amplitude-frequency characteristics. The cutoff frequency of the filter refers to the frequency value generated when the average value of the amplitude-frequency characteristic of the filter is attenuated to 3 dB. In a general circuit, the smaller the ratio of the waveform amplitude to the

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Fig. 15.10 Frequency selective network circuit composed of RC filter

amplitude-frequency characteristic of the filter is designed, the higher the performance of the filter; and the amplitude-frequency characteristic generally exhibits the shape of the ripple in the circuit simulation. The bandwidth of the difference between the two cutoff frequencies of the filter is the passband bandwidth. There are many types of filters. Signal-based processing and analysis functions can be divided into analog and digital filters. Based on the frequency response method, filters can be divided into low-pass filters, high-pass filters, band-pass filters, band-stop filter (or band-rejection filter). In addition, the digital filter can be implemented either by a DSP processor or by an FPGA through digital design [15, 16]. As variety of filters are used in modern high-speed communications, the design requirements for filters are increasing. In recent years, new structures and new materials, such as Defected Ground Structure (DGS), Substrate Integrated Waveguide (SIW), multimode structure, and Low-Temperature Co-fired Ceramic (LTCC) have emerged. The emergence of these new structures and new materials will lead the way in the development of new filters in the future. RF Filter Products are commercially available [17].

Microwave Devices Microwave devices work in the microwave band (300 MHz to 300 GHz), they are usually used in electronic products such as signal transmitters, signal receivers, radar systems, mobile communication systems, etc. Microwave devices include microwave vacuum device and microwave semiconductor device, the latter has a property of integration and is described here. According to the working principle and function, microwave semiconductor devices can be divided into microwave diodes and microwave transistors. In terms of noise suppression of microwave at receiving signals, microwave diode possesses good feature in noise reduction. Representative devices include mixer diode and varactor. In microwave control device applications, microwave transistors play a major role in the representative devices with enhanced metal-semiconductor fieldeffect transistor (MESFET), junction gate field-effect transistor (JFET or JUGFET), and high electron mobility transistor (HEMT), etc. A diode can be used for Frequency Mixer or RF Mixer that utilizes the metalsemiconductor contact principle. Under forward bias, when the work function of the

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metal is greater than or equal to the work function of the n-type semiconductor, carriers in the n-type semiconductor migrate into the metal to form a current. Since the turn-on voltage is low, the series resistance is small, and the current is generated. Similarly, under reverse bias, due to its higher reverse breakdown voltage, the resistance is small, and a small current is generated. The main indicators of the mixing diode are breakdown voltage, zero-bias junction capacitance, series resistance, and noise figure [18]. Varactor diodes are mainly used in basic frequency conversion circuits such as parametric amplification, mixing, and frequency multiplication. The original varactor diode was fabricated from silicon and its cutoff frequency did not reach 100 GHz. Therefore, its low-noise parametric amplifier has a low operating band. The rapid development of new GaAs materials has facilitated the updated iteration of varactors. Varactor diodes can effectively control epitaxial layer concentration distribution and interface steepness. The main parameters of varactors are breakdown voltage, varactor ratio, and cutoff frequency [19]. The depletion type of MESFET has been widely used, its current drive capability is strong, and the circuit formed has a large logic swing; however, the device consumes a large amount of power and the circuit is complicated, so the degree of integration is limited. The enhanced type of MESFET is just the opposite. Its simple circuit and low-power consumption make the circuit with a low logic swing. The main factors affecting the enhanced MESFET are the threshold voltage and the barrier forward turn-on voltage. Enhanced MESFET performance indicators for enhanced MESFETs include reliability power, output power, and breakdown voltage [20]. The junction field-effect transistor (JFET) consumes low power and has a large turn-on voltage of the pn junction. For example, the turn-on voltage of the heterojunction FET can reach 1.4 V, so the output swing of the circuit is large. JFETs have greater radiation tolerance than MESFETs. The disadvantage is that the pn junction gate has a large edge capacitance, which is slower during ion migration than the same size MESFET circuit. The main performance indicators of JFET are forward current greater than or equal to 3.5A, reverse breakdown voltage greater than or equal to 1700V, and transconductance greater than or equal to 0.52S [21]. High Electron Mobility Field-Effect Transistors (HEMTs) are fabricated from semi-insulating GaAs substrates using MOCVD techniques to grow high-purity GaAs and doped with multilayer structures such as Al, Ga, As, and GaAs. Since the electron affinity in the narrow-bandgap GaAs is large, the free electrons in the wide-bandgap AlGaAs layer transit to the AlGaAs boundary layer in the high-purity GaAs to generate a two-dimensional electron gas. HEMT has better high-speed performance in the circuit than MESFET, and the impurity scattering in high-purity gallium arsenide is very weak, with high electron mobility. The main performance indicators of HEMT are output power and frequency characteristics [22]. Future microwave devices will have better stability, thermal conductivity, heat resistance, pressure resistance, and radiation resistance. Products of Microwave Devices are commercially available [22].

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Millimeter Wave Devices Millimeter Wave (mmW), which is also called extremely high frequency (EHF), has a frequency band from 30 GHz to 300 GHz and wavelength of 10 mm–1 mm [23] by ITU (International Telecommunication Union). The band of the mmW is subdivided by IEEE into Ka-Band (26.5 GHz to 40 GHz), V-Band (40 GHz to 75 GHz), W-Band (75 GHz to 110 GHz), and D-Band (110 GHz to 170 GHz), G-Band (140 to 220 GHz), H-Band (220 to 325 GHz), etc., while NATO has K-Band (20–40 GHz), L-Band (40–60 GHz), M-Band (60–100 GHz) [24]. Due to its short wavelength and narrow beam characteristics, the influence of weather variation on mmW performance is limited, so mmW devices meet the requirements for all-weather operation. The mmW was originally proposed by Heinrich R. Hertz in 1889. In 1897, scientists studied the transmission characteristics of 5 mm band mmW on ionospheric attenuation and rainwater scattering environment. The mmW technology developed slowly due to high requirements for basic material properties and processing techniques. In the 1960s, with the advancements of materials science and processing techniques, 6 mm frequency band mmW was applied on radar system, and 1 mm frequency band mmW was used for the radio telescope of astronomical applications. Since the 1980s, advances in materials science and microelectronics greatly promoted the research work of mmW technology, and new mmW devices have been widely used in the fields such as radar communication and medical applications. 1. Millimeter Wave Radar. Due to the short wavelength and the narrow beam of millimeter wave, the mmW radar is often small and light. The mmW has strong anti-interference ability when the climate changes, so that mmW devices can meet the requirements for all-weather work. The mmW radar has the characteristics as high resolution, long detection range, and stable performance, which make it been widely used in precision guidance, intelligent driving, navigation, and detection. 2. Millimeter Wave Satellite Communication. The mmW has a high carrier frequency, which allows it to have a broadband signal to meet the requirements of high-speed information transmission. By using its characteristics as short wavelength and narrow beam, multibeam narrowband mmW antenna of strong directivity can be realized, and its coverage area can be expanded by band conversion. Due to the strong anti-interference ability of the mmW, the quality of communication under poor weather conditions is also guaranteed by the mmW antenna. Because the air in the outer space is thin, the mmW has very little energy loss during the propagation in that environment, and only a small power is required to realize long-distance communication. Based on the above characteristics, mmW technology has been widely used in long-distance communication satellites to ground or satellite to satellite systems. 3. Millimeter Wave Medical Treatments. The Eigen frequency of biological tissues such as human body is in the frequency range of mmW. Therefore,

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based on resonance, the mmW can produce a series of biological effects on human biological tissues. For example, it promotes ion movements in the body; changes the activity of proteins, amino acids, and enzymes; and regulates the metabolism of cells; and so on. In recent years, the researches on tumor immunity, endocrine system, and digestive system have been gradually carried out by using mmW technology. Due to its extremely low radiation, high resolution, and privacy protection, the mmW is also applied on scanning imaging security gates. The mmW security gates are one of the main research directions in the field of safety-check, and it is possible to replace the X-ray security gates which currently widely used in subway stations, airport, and railway stations. The mmW technology plays an increasingly important role in people’s daily activities. Devices based on mmW technology can realize ultra-high-speed wireless data transmission by increasing spectrum bandwidth, which has become one of the key technologies of 5G communication systems and has important market value. System vendors who master the core technology of the mmW radar include Bosch, Continental, and Delphi, etc. In terms of integrated devices that dominate the market, S32R27 by NXP is used for radar control system, STRADA431 (24 GHz) and STRADA770 (77 GHz) by STMicroelectronics are designed for medium/long-range distance detection, and BGTx0 and RXN7740 by Infineon are RF front-end chips.

Terahertz Devices Terahertz (THz) frequency ranges from 0.1 THz to 10 THz and wavelength ranges from 0.03 mm to 3 mm; while for communications, ITU designated Terahertz ranges to be 0.3 THz–3 THz, wavelengths of 1 mm–0.1 mm [25]. In electromagnetic spectrum, the THz is between microwave and infrared, and has the advantages such as wide spectrum, high signal-to-noise ratio, high coherence, and low photon energy. As early as 1896, scientists studied the electromagnetic waves of the THz band. Because of the limit in materials and processing techniques, the lack of THz wave source and high-sensitivity detectors made the research work progressing very slowly. Since the 1980s, with the progress of materials science and the advance of processing techniques, new impetus had been injected into the development of THz technology and attracted attention of the world. With many applications using new materials and new processes, significant progress has been made in THz wave sources and THz devices. The THz wave sources include both wideband THz sources and narrowband THz sources. The broadband THz sources, which contain ultra-wide spectral components of up to tens of THz, have a low radiation power and are currently used in spectroscopy systems. The narrowband THz source is mainly used as a THz oscillation source or a coherent THz source and has been applied in the fields such as sub-millimeter wave oscillator and free electron laser.

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THz devices can be classified as passive and active components. The passive components include transmission lines, filters, couplers, and antennas. The active components include mixers, frequency multipliers, detectors, amplifiers, and oscillators. THz technology can be widely used in the fields as astronomy, detection, and communication. The THz application systems such as terahertz radio telescope, Thz detection technology, and THz communication technology have been invented. 1. THz Radio Telescope. By studying the spectral characteristics of terahertz in cosmic radiation, we can learn the composition of molecular clouds and explore the origin of the universe. By analyzing the spectral information contained in the scattering of atoms and molecules in cosmic rays, we can study the internal mechanism of the formation of new cosmic galaxies. With the progress of THz technology, the THz radio telescope becomes an important scientific means of observing space and studying cosmic rays. 2. THz Detection Technology. THz detection technology mainly includes two aspects: time-domain spectroscopy and transmission imaging. The time-domain spectroscopy uses terahertz waves to illuminate objects. After passing through object, transmitted and reflected waves affect the electric field of the THz, so that measurement of the change of electric field strength can show the spectral characteristics of the object irradiated by the THz. The structure and composition information of the object can be obtained by analysis of the spectral properties of the material. This technology can be used for food and drug quality regulation. Transmission imaging utilizes the penetration characteristics of the THz wave. The THz wave has good penetrability for solid materials without moisture but is less penetrating for living bodies that contain a large amount of moisture. Based on this feature, THz imaging can scan through concrete to detect the distribution and activities of human being in covered areas, such as indoors or under ruins. This application has great value in anti-terrorism and disaster rescue. 3. THz Communication Technology. Taking the THz wave as the carrier frequency, the wireless data transmission speed can reach 10 GB/s. The working environment of satellite communication system in universe is like vacuum. In that condition, the propagation loss of THz wave is very small, so that THz technology-based communication systems can greatly increase the data transmission speed, which reaches more than a thousand times of current ultra-wideband technology. While wide commercial applications of THz technology are limited by the short of high-quality terahertz signal sources and antennas, with continuous emergence of new materials and processing technics, the researches on THz devices develop rapidly and the THz communication has become an important tendency of future communication systems. THz technology has great value in the field of industrial monitoring and quality control. In the field of nondestructive testing and medical imaging [26], the application of THz technology largely promoted the growth of concurrent electronics market.

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Radio (Receiver) Integrated Circuit Radio has three operation modes: Frequency Modulation (FM), Amplitude Modulation (AM), and Shortwave (SW). The frequency range of FM broadcast is 76 MHz to 108 MHz (88–108 MHz in China, 76–90 MHz in Japan). The frequency range of AM broadcast is 530 kHz to 1600 kHz. SW generally adopts amplitude modulation technique, and its frequency range is usually between 1.6 MHz and 30 MHz. The AM has a long transmission distance, but because it is sensible to weather variation, it is used for provincial radio stations. Many countries use SW for worldwide broadcasting. In earlier 1920s, LW (Long-wave) broadcast was used. LW generally indicates that the wavelength of carrier frequency is longer than 1000 m (which is equivalent to a frequency lower than 300 kHz). The integrated circuit or chip used in a radio receiver refers to integrate on a same substrate both antenna and audio processing module, and full radio set function is achieved by a single chip. Radio chip generally provides functions such as frequency tuning, band selection, volume control, and stereo processing (digital-to-analog conversion). The radio chip has a variety of digital configurations. Some radio chips use an external microcontroller (MCU) to configure the tuning and receiving modes of FM/AM/SW signals. Some radio chips integrated full receiver and control system that processes FM/AM/SW signals directly without the need of an external MCU. In 1958, Jack S. Kilby developed the world’s first IC. Over the next 30 years, modules based on IC gradually replaced radio set circuits that are made of discrete transistor components, significantly increasing system integration. With the progress of microelectronics technology, digital signal processing (DSP) techniques became applicable for all-digital radio solution. In 2006, Si Labs introduced Si473 X-series radio chips, the world’s first single-chip radio set, supporting short-wave, mediumwave, long-wave, and very high-frequency bands of the radio system. Radio receivers include traditional AM/FM/SW radios, home theater receivers, for example to support AC-3/7.1 audio channels of 100 W each channel, other radio types are HAM and amateur radios [27]. Receiver ICs [28] at large are suitable for TVs, radios, GPS devices, cellphones, wireless devices, and many other applications; while radio receiver ICs are specifically for radios, and focused on SDR (software-defined radio) technology in twenty-first century [29].

Navigation Receiver IC A navigation receiver integrated circuit (IC) receives radio signals transmitted by satellites in space, thereby enabling to provide all-weather three-dimensional coordinates, speed, and time information to users for all locations on the Earth’s surface or near-Earth space. At present, there are four global navigation satellite systems (GNSS) [30]: the Global Positioning System (GPS) of United States, the Global Navigation Satellite

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System (GLONASS) of Russian, the Galileo satellite navigation system (Galileo) of European, and the BeiDou navigation satellite system (BDS) of China. Satellite navigation chips are widely used in land-sea-air applications. In land applications, the chips are applied in fields including atmospheric physical observation, vehicle navigation, engineering survey, resource exploration, crustal motion monitoring, municipal planning and disaster relief. In marine applications, the chips are applied in fields including cargo dispatching, ship navigation, marine rescue, hydrological surveying, and offshore platform positioning. In aerospace applications, the chips are applied in fields including aircraft navigation, missile guidance, aerial remote sensing, low-orbit satellite orbit determination, and aviation rescue. The satellite navigation chip is the core device of satellite navigation industry. The satellite navigation chip can be classified into two categories: front-end RF signal processing chip and back-end baseband data processing chip. As high-level system integration is requiring, a single-chip navigation system that integrates both front-end RF signal processing and back-end baseband digital signal processing becomes the target for both industry and research [31]. In a satellite navigation chip, such as in a typical GPS receiver, there are several key components, including the antenna, LNA (low-noise amplifier), SAW (surface acoustic wave) filter, LDO (low-dropout regulator), TCXO (Temperature Compensated Crystal Oscillator), and GPS RF/receiver [32]. The fully integrated GNSS (GPS, Galileo, GLONASS, and BeiDou) receiver is commercially available [33, 34]. As of August 2019, there are 31 operational satellites in the GPS constellation. The BDS consists of five geostationary orbit satellites and 30 nongeostationary orbit satellites. By November 2016, there are already 23 satellites working in the BDS. In 2012, the BDS had achieved in covering the Asia Pacific region. The BDS plans to realize global coverage around 2020.

Wireless Fidelity Products Wireless network products are devices that use wireless local area network (WLAN) for data transmission. They work in local area, such as household, schools, and offices. In area covered by wireless local network, users can remain connected while keep moving. Wireless Fidelity (Wi-Fi) is one of wireless technologies that widely applied. Wi-Fi is a short-range wireless communication technology, which follows IEEE 802.11 standard [35] that provides a unique IP address for all devices connected in, and build a wireless network through IP addresses for data communication. The working frequencies of Wi-Fi devices have two bands at 2.4 GHz and 5 GHz, supporting a data rate from 1 Mbps to 150 Mbps, covering an effective communication distance from 30 to 100 m. The Wi-Fi technology was invented by Australian Commonwealth Scientific and Industrial Research Organization (CSIRO) in the 1990s and patented in the United States in 1996. In 1999, IEEE officially confirmed Wi-Fi technology as the IEEE 802.11 standard. The carrier frequency of Wi-Fi is 2.4 GHz or 5 GHz, which belongs to Industrial, Scientific, and Medical (ISM) band that defined by International

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Telecommunications Union (ITU). The band is free to use, without the need for a telecom operation license. Compared to other short-range wireless communication technologies such as Bluetooth (2.4 GHz to 2.485 GHz) and ZigBee (main 2.4 GHz to 2.484 GHz), the Wi-Fi provides a higher transmission rate. The Wi-Fi technology is the main way for users to obtain wireless network services and has been widely used in mobile devices. At present, the main Wi-Fi chip [36] providers include Broadcom, Texas Instruments (TI), Marvell, Qualcomm, Ralink, and Realtek. Among them, Broadcom, Marvell, and TI have mature technology and good performance of their products, they have formed a full industrial chain made on Wi-Fi chips. Ralink and Realtek provide Wi-Fi chips to dominate the market of low-end routers. As the high-power consumption of Wi-Fi chips limits its application in Internet of Things (IoT), low-power Wi-Fi chips are always a focus in industry. Independent Wi-Fi chips only provide the function of connecting and transmitting signals, and a separate processor is necessary for transport protocol processing. Therefore, a complete wireless connection technology solution contains both the Wi-Fi chip and an external microcontroller (MCU) [37], which increases system cost. Driven by the huge demand for IoT applications, a SoC chip integrating Wi-Fi, Bluetooth, and MCU becomes the latest technology trend. On the other hand, based on the IEEE 802.11n standard, 600 Mbps data transmission rate of the earlier Wi-Fi chip does not meet the requirements for large amount data transmission demanded by newly emerging IoT applications. In 2012, the IEEE 802.11 ac standard is promoted, which allowing 1 Gb/s wireless data transmission speed on the 5 GHz frequency band. The Wi-Fi chips that meet the IEEE 802.11 ac standard become the main choice for wireless router products.

Bluetooth Products Bluetooth is a point-to-point short-range wireless data transmission technology, which was firstly studied by Ericsson in 1994. Bluetooth uses spread spectrum communication technology based on frequency hopping. Its frequency range is from 2.4 to 2.485 GHz, which belongs to Industrial, Scientific, and Medical (ISM) band that defined by International Telecommunications Union (ITU). This band is free to use without applying for a telecom operation license. The communication distance of Bluetooth is classified as Class A and Class B. The Class A type has a communication distance about 20 to 30 m, but its power consumption is too large to fulfill the requirements of personal communication products. The Class B type has a communication distance about 5 to 10 m, and it is widely used in consumer electronics as its power consumption reaches a very low level. According to different application scenarios, Bluetooth released different versions; Bluetooth 1.1 meets IEEE 802.15.1 standard [38]. Bluetooth 1.1/1.2 works in simplex mode, with a data transmission rate about 748 to 810 kbit/s. Bluetooth 2.0 works in duplex mode and improves data transmission rate, which is about 1.8 to 2.1 Mbit/s. Bluetooth 3.0 is designed for high-speed applications and its data

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transmission rate reaches up to 24 Mbit/s. Bluetooth 4.0 (Bluetooth Smart) integrates the classic Bluetooth, the high-speed Bluetooth, and Bluetooth Low Energy (BLE), and largely applied in mobile products because of its low-power dissipation characteristics. Bluetooth 4.0 reaches a data transmission rate up to 25 Mbit/s. Bluetooth 5.0 was released in June 2016, supporting a 255-Byte data packet to improve transmission efficiency. Bluetooth 5.0 [39] reaches a maximum data transmission rate of 50 Mbit/s, and its signal coverage area is also significantly improved. Bluetooth 5.1 has been released in January 2019. Bluetooth products are now widely used in wireless interconnection of mobile wireless products such as computers, mobile phones, printers, digital cameras, headsets, keyboards, computer mouse, etc. Since 2013, the rapid development of smartphones and products related, such as tablets and wearable devices; drove an explosive growth of Bluetooth chips. The largest supplier of the Bluetooth chips in the world is Cambridge Silicon Radio (CSR), which was acquired by Qualcomm in August 2015. There are three main aspects for the Bluetooth development: (1) Develop Bluetooth networking capabilities. To build a low-power Internet-of-Things (IoT) system by connecting smart home systems and wearable devices based on low-power Bluetooth technology. (2) To integrate Bluetooth devices with sensors, making the sensors intelligent by sending data collected by the sensors directly to cloud for processing and feedback through the Bluetooth devices. (3) To establish Bluetooth-based mobile products for indoor positioning.

ZigBee Products ZigBee is a low-power short-range wireless communication technology. ZigBee is based on IEEE 802.15.4-2006 – IEEE Standard [40] and has three carrier frequency ranges. The frequency range of 2.4 to 2.484 GHz is the main one, the one of 902–928 MHz is allowed in North America and the one of 868.0–868.6 MHz is also used in Europe. ZigBee Alliance. ZigBee was first proposed in 1998 and the IEEE 802.15.4 standard was set in 2003. ZigBee is developed and managed by ZigBee Alliance [41], which was established in 2001 as a nonprofit organization of top international semiconductor manufacturers, technology vendors, and worldwide end-users. The first version, ZigBee V1.0, was released by the ZigBee Alliance in 2004. In 2006, ZigBee 2006 was launched with optimization of system architecture. In 2007 and 2009, ZigBee PRO and ZigBee RF4CE were introduced successively, the system becomes more flexible and easier to use by remote control. Features of ZigBee. ZigBee terminal can be self-connected to form a ZigBee network for communication. The coverage of the ZigBee network is extendable by using different topologies such as star, patch, and mesh. ZigBee is designed for low data rate applications, while it has the advantages as low standby power, short latency, and high capacity. The power dissipation of ZigBee devices is lower than the one based on Bluetooth, and ZigBee is one of the lowest power consumptions

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among all short-range communication technologies. The maximum transmission distance of ZigBee between two neighboring nodes is 10–100 m. For communication of two nodes which are farther, the range can be extended by routing between adjacent nodes. To meet technical requirements of different applications, ZigBee provides three data rates, which are 250 kbit/s for 2.4 GHz, 40 kbit/s for 915 MHz, and 20 kbit/s for 868 MHz respectively. ZigBee Products. The mainstream ZigBee chips in market are CC243X and CC253X series from Texas Instruments, MC1321X and MC1322X series from Freescale, EMBER series from STMicroelectronics (ST), and JN516x series from NXP. These products integrate both RF front-end and protocol stack on a single chip, largely improving the integration of ZigBee system. ZigBee technology has been widely used in various fields such as industrial control, agricultural automation, and medical device control. In a sensor information collection network based on ZigBee, data acquisition is automatic and then all data are sent to back-end system for big data analysis and processing, providing an important technical way for industrial control and strategy. In agricultural automation, ZigBee-based sensor network can provide automatic and intelligent precision network production by comprehensive collection and analysis of the information of crop moisture, soil nutrient, and climate. In medical applications, ZigBee-based sensor network is used to connect various medical monitoring devices for realtime continuously monitoring on vital signs information as blood pressure, body temperature, and heart rate, enabling the medical monitoring system more intelligent.

Radio Frequency Identification Products Radio Frequency Identification (RFID) is a wireless communication technology that enables wireless data transmission by noncontact ways, which is either magnetic coupling or electric transmission by RF, to identify specific targets. The RFID technology does not need to have a mechanical or optical connection between identification system and target, so that it is easy to use with fast recognition speed. The RFID devices have the characteristics as simple to use, long service life, and high safety. The RFID is one of the core technologies of Internet of Things (IoT) and it is now widely used in business automation tools, transportation management, and logistics. RFID devices are classified into two kinds: passive devices and active devices. (1) The passive RFID device has no power supply. There is generally an energy storage coil inside for energy supply which is sent by external terminals through electromagnetic coupling. When the energy received reaches its driven threshold, the circuit of the passive RFID device turns on and exchanges information with outside identification system by backscattering modulation. Limited by energy available, the passive RFID device has generally a short recognition range and a low data transmission rate. (2) The active RFID device contains a miniature battery or an internal power supply, and it generally works in a very low-power standby mode. As there is

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a power supply inside, the active RFID device has a faster respond speed. In working mode, the active RFID device exchanges information with the outside identification system by means of radio frequency communication, which provides a large area of recognition and a high data transmission rate [42]. RFID tags such as pass cards, tickets, and access cards work in 13.56 MHz. The RFID tags are widely used in automatic access control system, providing an effective identification process which greatly simplifies passage recognition procedure and significantly improves system efficiency. Traditional manual toll collection system for highway booth and parking lots has a low-efficient and can cause road congestion. Electronic Toll Collection (ETC) system operating in 5.8 GHz that enables remote data exchange by installing an On-Board Unit (OBU), which is an active RFID tags, on vehicles. The OBU exchanges data with the toll booth via wireless communication, highway toll collection is carried out in a background settlement way, which does not need to stop the car at the highway entrance or exit, greatly improving the efficiency of vehicle traffic management. Applying the RFID tags on warehouse goods not only enables intelligent automatic management of goods entering and leaving but also provides real-time monitoring of stock. In freightage, it is also possible to realize remote intelligent monitoring on transportation path and environment through the RFID tags installed on goods, largely improving logistics automation.

References 1. R. Behzad, RF Microelectronics, 2nd edn. (Prentice Hall, New York, 2011) 2. B.Y. Chi, Z.P. Yu, B.X. Shi, Analysis and Design of RF IC (Tsinghua University, Beijing, 2006) 3. T. Johansson, J. Fritzin, A review of watt-level CMOS RF power amplifiers. IEEE Trans. Microwave Theory Tech. 62(1), 111–124 (2014) 4. LNA. https://www.macom.com/LNA. Accessed 16 Feb 2020 5. H. Thomas, Lee: The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn. (Prentice Hall, Cambridge, 2018) 6. S. Tang, Research on the Design Technology of High-Performance CMOS Mixer (Southeast University, Nanjing, 2005) 7. Y. Deng, Research and Design of a High Precision CMOS Oscillator with Temperature Compensation, MSc Thesis (Southwest Jiaotong University, Chengdu 2012) 8. RF Oscillator. https://www.eleccircuit.com/rf-radio-frequency/. Accessed 20 Feb 2020 9. RF Oscillator Products. https://www.pasternack.com/rf-oscillators-category.aspx. Accessed 20 Feb 2020 10. W. Zhou, Multiplexer Theory and Practice, PhD Dissertation (Dalian Maritime University, Dalian, 2001) 11. X. Zhang, A Study of Duplexer Synthesis Technique, MSc Thesis (University of Electronic Science and Technology of China, Chengdu, 2012) 12. J. Hong, Duplexer Design and Implementation, MSc Thesis (Beijing University of Posts and Telecommunications, Beijing, 2014) 13. Z. Zhang, Study of Duplexer Design Method and Miniaturization Modeling, MSc Thesis (Xidian University, Xi’an, 2013) 14. Duplexier Products. https://www.rfwireless-world.com/Vendors/RF-duplexer-diplexer-manu facturers.html. Accessed 20 Feb 2020

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15. P. Liu, Design and Implement of FIR Digital Filter Based on FPGA, MSc Thesis (Northwestern Polytechnical University, Xi’an, 2006) 16. C. Wei, A Study of Key Technology of New-Type Microwave Filter, PhD Dissertation (University of Electronic Science and Technology of China, Chengdu, 2013) 17. RF Filter Products. https://www.ctscorp.com/products/rf-filters/. Accessed 20 Feb 2020 18. C. Jung-Kubiak, A. Maestrini, A. Cavanna, et al., Conception and Fabrication of GaAs Schottky Diodes for Mixers, in 20th International Symposium Space Terahertz Tech (Charlottesville, 20–22 April 2009) 19. C. Tian, H. Yang, J. Dong, et al., Design and fabrication of GaAs Planar Schottky Varactor diode with the exponential doping structure. Chi. J. Electron Devices 34(1), 29–32 (2011) 20. P. Gupta, P. Kaushik, Comparative analysis of GaAs MESFET with different dimensions, in 2015 Annual IEEE India Conference, (INDICON, New Delhi, 2015) 21. G. Chen, S. Bai, Y. Li, Progress of a high voltage SiC JFET. Res. Progr. Solid State Electron. 33(3), 224–228 (2013) 22. X. Zhang, Study of GaN-Based Millimeter Wave HEMT Device, PhD Dissertation (Hebei University of Technology, Tianjin, 2014) 23. EHF. https://en.wikipedia.org/wiki/Extremely_high_frequency. Accessed 20 Feb 2020 24. IEEE Band. http://www.alternatewars.com/BBOW/Radar/Radar_Bands_Wavelengths.htm. Accessed 20 Feb 2020 25. THz by ITU. https://en.wikipedia.org/wiki/Terahertz_radiation. Accessed 20 Feb 2020 26. THz Applications. https://terasense.com/applications/. Accessed 20 Feb 2020 27. Radio Receiver Types. https://www.electronics-notes.com/articles/radio/radio-receivers/ receiver-types.php. Accessed 20 Feb 2020 28. Radio Receiver ICs. https://www.globalspec.com/learnmore/semiconductors/audio_video_ic/ radio_receiver_ics. Accessed 20 Feb 2020 29. SDR. https://www.sdr-radio.com/. Accessed 20 Feb 2020 30. GNSS. https://en.wikipedia.org/wiki/GNSS_applications 31. A. Miskiewicz, A. Holm, R. Weigel, System considerations and RF front-end design for integration of satellite navigation and mobile standards. Adv. Radio Sic. 7, 151–154 (2009) 32. A GPS Receiver. https://www.electronicdesign.com/communications/adding-gps-chipset-yournext-design-easy. Accessed 20 Feb 2020 33. ST Fully Integrated GNSS Receiver. https://www.st.com/content/ccc/resource/technical/ document/datasheet/group0/06/59/a9/d4/28/85/43/67/DM00148095/files/DM00148095.pdf/ jcr:content/translations/en.DM00148095.pdf 34. NTLab GNSS Receiver. http://www.ntlab.com/section/sec:v:36729.htm 35. WLAN Standards. http://www.ieee802.org/11/. Accessed 20 Feb 2020 36. WLAN Products. https://e.huawei.com/en/products/enterprise-networking/wlan. Accessed 20 Feb 2020 37. WLAN Controller. https://www.cisco.com/c/en/us/products/wireless/wireless-lan-controller/ what-is-wlan-controller.html. Accessed 20 Feb 2020 38. IEEE 802.15.1 Standard. https://standards.ieee.org/standard/802_15_1-2002.html. Accessed 20 Feb 2020 39. Bluetooth 5.0. https://www.rfpage.com/specifications-and-applications-bluetooth-5-0/. Accessed 20 Feb 2020 40. IEEE 802.15.4 Standard. https://standards.ieee.org/standard/802_15_1-2002.html. Accessed 20 Feb 2020 41. Zigbee Alliance. https://zigbeealliance.org/. Accessed 20 Feb 2020 42. I. Ahmed, Radio Frequency Identification from System to Applications (Scitus Academics LLC, Wilmington, DE, USA, 2017)

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Xinnan Lin, Zheng Gong, and Jesse Jen-Chung Lou

Contents Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PiN Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unipolar Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Recovery Diode (FRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulated Gate Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide-Bandgap Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Superjunction Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Turn-Off Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Gate-Commutated Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emitter Turn-Off Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOS-Controlled Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Power devices are typically used in applications where high voltage, large current, and high frequency are requirements. For example, power devices are required in high-voltage transmission, power electronic equipment, electric X. Lin Electronic and Computer Engineering, Peking University, Shenzhen, China Z. Gong Tunghai University, Taiwan, China J. J.-C. Lou (*) School of Software and Microelectronics, Peking University, Beijing, China Institute of Microelectronics, Peking University, Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_16

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vehicles, and in locomotives, etc. As silicon-based materials are approaching their performance limit, high bandgap materials, such as gallium nitride (GaN) and silicon carbide (SiC) are becoming mature and entering the application market. Power devices include power diode, power BJT, power MOSFET, insulated gate bipolar transistor (IGBT), super junction thyristor, gate turn-off thyristor (GTO), insulated gate-commutated thyristor (IGCT), emitter turn-off thyristor (ETO), MOS controlled thyristor (MCT), etc. These devices are briefly described in this chapter with their basic structures, working principles, and mechanisms. Keywords

Power device · IGBT · GTO · IGCT · ETO · MCT

Power Devices Power devices, usually regarded as power electronic devices, are semiconductor devices specifically designed for power processing. Power devices potentially can support high voltages (from tens of volts to thousands of volts) and pass large currents (up to several thousand amperes). They are widely applied in high-voltage power systems, such as transformer substation, energy storage devices, and power electronic equipment for the control and manage of power distribution [1, 2]. The most common power devices are power metal-oxide semiconductor fieldeffect transistor (MOSFET), thyristor, Triode for Alternating Current (TRAC), Gate Turn-Off (GTO), Insulated Gate Bipolar Transistor (IGBT), Integrated GateCommutated Thyristor (IGCT), Emitter Turn-off (ETO) MOS controlled transistor, MOS Controlled Thyristor (MCT). The early power devices are mainly large power diodes and thyristor, etc., usually applied on industrial and electrical systems. With the rapid development of power MOSFET and other new power device such as IGBT, power devices have found more and more applications. There are several ways to classify power devices. Power devices can be classified into two types depending on the switching characteristics. ① Semi-controlled devices. The signal of gate can only control the device to conduct but not to turn off, such as SCR. ② Full-controlled devices. The signal of gate can control both turn-on and -off, such as bipolar transistor, IGBT, IGCT, ETO Thyristor, MCT, and GTO Thyristor, etc. The control type of power devices includes gate control and base control. Therefore, power devices can be divided into two types. ① Current-controlled devices: The control signal of the gate is the current flowing in or out, such as SCR. ② Voltage-controlled devices: The control signal of the gate is voltage; the current consumption is small, such as IGBT. Power devices can be classified into three types depending on the conductive carriers. ① Unipolar devices: Only one type of carrier participates in conduction, such as MOSFET. ② Bipolar devices: Electrons and holes participate in

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conduction, such as BJT. ③ Hybrid devices: Devices are composed of unipolar devices and bipolar devices, such as IGBT. Technically, power devices are developing into the direction of improving fast recovery performance, reducing turn-on resistance, improving current control capability, increasing rated blocking voltage, improving temperature resistance, and reducing power consumption. With the gradual maturity of silicon-based power devices and process, their performance has gradually approached material limit, materials with higher performance limit should be adopted to make a breakthrough. The wide-bandgap semiconductor materials such as gallium nitride (GaN), silicon carbide (SiC), and so on, have the advantage of high critical electric field strength, high electron saturation rate, high temperature resistance, radiation resistance, etc. Power devices based on wide-bandgap semiconductor materials have also entered the growing market. GaN is mainly used in power semiconductors for power amplification, rectification, and high-frequency switching. Its market is growing rapidly in the 300 V-1 kV medium voltage power electronics. In addition, the demand for high-efficiency medium- and high-voltage inverter in the energy-saving industry will also accelerate the growth of the GaN power semiconductor market. The technology of growing GaN thin films on sapphire substrates by MOCVD has matured in the LED industry. Therefore, in the emerging power electronics market, the development of technology for fabricating power devices by forming GaN-on-Si structures on large-sized silicon substrates by MOCVD has great industrial potential. The blocking voltage of SiC is much higher than that of GaN, power MOS, and Si-IGBT. It is suitable for power electronics with high voltage (higher than 1 kV) and high current. The main market is in railway traffic and high-voltage power grid. The life cycle is a major factor to consider. In addition, the United States Cree company also has mass production on microwave devices of GaN-on-SiC structure.

Power Diode Power Diode is a discrete power semiconductor device with a much wider range of voltage and current applications than typical small signal diodes. It can be used for rectification, clamping, transient voltage suppression, freewheeling, absorption, modulation, conversion, etc. Power diodes are divided into two types: PiN (P-intrinsic-N) diodes and single-pole Schottky Barrier Diodes (SBD).

PiN Diode The PiN diode is a current-controlled device, a minority carrier, with low input impedance and a large driving power. There are minority carriers stored near the pn junction when turn-on, resulting in slower switching speed of the device. Si-based

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Fig. 16.1 Schematic of PiN diode structure and carrier concentration

PiN diodes typically operate at less than 1 kHz. Schematic of structure and carrier concentration of the PiN diode are shown as Fig. 16.1, adding a specific thickness low-doped n-type drift region (or p-type drift region) between the heavily doped p+ layer and the n+ layer as a voltage resistance layer. When a forward bias voltage is applied to the PiN diode, a large number of minority carriers are injected into the drift region to produce a conductance modulation effect, which reduces the on-state resistance and voltage, thereby greatly reducing the on-state power consumption. In the reverse bias, the space charge region of the p+n junction mainly extends to the low-doped n-type drift region, and the reverse blocking voltage is absorbed by the depletion region of the n-type drift region, so that the PiN diode can block very high reverse voltage with small leakage current. Usually the maximum reverse operating voltage is 2/3 times the avalanche breakdown voltage. In the forward biasing, the p+ region injects a large number of holes into the n-type drift region, and the n+ region also injects a large number of electrons into the n-type drift region. The nonequilibrium minority concentration is much higher than the original implanted doping in the n-type drift region, as resulting in a decrease in on-state resistance and increase in on-state current for good electrical conduction. At this time, the large on-state current is not limited by the low doping and thickness of the n-type drift region [1, 3]. Reducing the thickness of the drift region of the PiN diode results in a punchthrough structure, and the thinner drift region reduces the stored charge in the on-state and increases the turn-off speed. Deep level recombination centers can be introduced into the Si forbidden band by diffusing gold (Ag), platinum (Pt), proton or electron irradiation, which can reduce the minority carrier lifetime and shorten the reverse recovery time, thus increase the turn-off speed. The wide-bandgap silicon carbide (SiC) PiN diode not only have a higher breakdown voltage, but also a thinner drift region structure can reduce the reverse recovery current and increase turn-off speed, so it can operate at large current and high blocking voltage (greater than 10 kV).

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Unipolar Schottky Diode The Schottky contact barrier formed between the metal and the silicon-based semiconductor can produce rectification, but the barrier height is lower than pn junction. Therefore, the general small-signal Schottky diode has a lower forward voltage drop and a lower reverse breakdown voltage, with larger reverse leakage current as shown in Fig. 16.2. Adding a low-doping n
drift region to the Schottky diode forms a power Schottky diode structure consisting of a Schottky junction, n
drift region, and an n+ cathode region. The on-state voltage drop is determined by the metal semiconductor interface voltage, n
drift region resistor, and ohm voltage drop at the substrate. Since the unipolar Schottky diode is majority carrier device with no carrier storage and conductance modulation effects, rather it has fast switching and low on-state voltage drop, so the power consumption at high frequencies is low. At reverse bias, the blocking voltage is determined by the width of the n
drift region. Theoretically, the largest electric field strength occurs at the metalsemiconductor contact, where the breakdown occurs when the electric field strength is equal to the critical electric field strength of the semiconductor. However, the breakdown voltage of the reverse blocking is limited by the edge breakdown of the metal electrode, so the edge termination technique shall be used to increase the breakdown voltage of the power Schottky diode. Generally, the breakdown voltage of the Si-based Schottky diode is operated at less than 200 V, so the Si-based Schottky device is more suitable for high-frequency applications (i.e., not for high current and high-voltage applications). The wide-band SiC Schottky Barrier Diode (SiC-SBD) has a breakdown voltage of more than 3 kV, it is suitable for operating at higher voltage and power level. The Si-IGBT+SiC-SBD module unit composed of Si-based IGBT can greatly reduce the power consumption. The leakage current of a power Schottky diode includes current generated by a space charge in the depletion region, a diffusion current generated by carriers in the neutral region and a hot electron emission current generated at the Fig. 16.2 Schematic of power Schottky barrier diode (SBD)

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metal-semiconductor contact. The thermal electron emission current is dominated by temperature and Schottky contact barrier. Since the Schottky contact barrier height is relatively small, the leakage current is dominated by the thermal electron emission current. The use of a relatively large Schottky contact barrier can reduce leakage current and reduce power dissipation at the blocking state, while avoiding the Thermal Runway and allowing the power Schottky diode operating at higher ambient temperatures. Power diodes are the first-generation power semiconductor devices that can be used independently or used for freewheeling and fault energy absorption for all power semiconductor devices. Modern power semiconductor devices such as IGBT require at least one or two power diodes for their freewheeling and energy absorption.

Fast Recovery Diode (FRD) The power diode for rectification must have a low forward voltage drop to increase the on-state current and reduce the on-state power consumption, also it should have a high breakdown voltage, but the requirement for reverse recovery time is not high. Switching power diodes require higher switching speed, so the reverse recovery time must be shortened, and on-state voltages can be reduced. For fast recovery diodes (FRD), the free-flow power diodes must have fast recovery speed and low on-state, at the same time have a high softness (also called a recovery coefficient, i.e., tf/td, the ratio of the current fall time tf and the delay time td during reverse bias) to ensure the operational reliability of the power electronic system. The recovery speed of power diodes can be improved by diffusion of gold, platinum or irradiation. Power diodes diffused with gold or platinum not only have larger turn-off leakage current, but also have higher peak voltage of conduction, so the switching power consumption is larger. The turn-off leakage current of the electron irradiation power diode is low, but the too large reverse recovery peak current is not easy to achieve soft recovery, thus, resulting in large switching power consumption. The proton-irradiated power diode has a lower reverse recovery peak current, so it is easy to achieve soft recovery; the switching power consumption is lower. The position of the irradiation overlaps with the p+n junction region of the PiN power diode will increase the high-temperature leakage current of the device and deteriorate the breakdown characteristics of the diode. The Field Shielded Anode (FSA) diode with anode region composed of a thin p+ region and a slightly thicker low-doped p region forming a PiN power diode of p+pn
n+ structure can improve the breakdown characteristics. With proper low-energy irradiation, the defect region containing a highly recombination center can be only located in the thin p+ region without overlapping with the space charge region of the pn junction, reducing the anode injection efficiency make reverse recovery speed more faster, and also reduce the high-temperature leakage current, improve the high-temperature breakdown voltage of the power diode [4].

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Changing the anode or cathode structure of the diode can also improve the recovery speed of the high-power diode and reduce the switching power consumption. Reducing the doping concentration of the anode and reducing its thickness can reduce the minority sub-injection concentration in the on-state. Although the on-state characteristics of the device are deteriorated, a faster reverse recovery characteristic can be obtained, which can be used in switching and freewheeling applications to reduce switching power consumption. The structure of the Selfadjusting p+ Emitter Efficiency Diode (SPEED) is shown in the Fig. 16.3, a highly doped p+ region is formed in the low-doped p-anode region by ion implantation [5]. At low-current density, the implantation efficiency of the pn junction is low, so the on-state voltage drop is determined by the low forward voltage drop pn
n+ junction; at high current density, the high injection of the p+pn
junction produces the conductance modulation effect which causes the diode’s voltage drop to be determined by the p+ pn-n+ portion of the forward voltage drop. Since the SPEED structure has a small change in forward voltage drop at high current density, it can improve the device’s Surge Current capability and has a high reverse recovery speed to serve as a typical fast recovery diode. In addition, as shown in Fig. 16.4, the combination of PiN diode and Schottky diode in parallel (Merged PiN and Schottky, MPS) can improve the blocking voltage of Schottky diode and reduce the forward voltage drop [6]. The MPS diode is a fast recovery diode, and it has advantages of both PiN and Schottky diodes. The PiN diode does not conduct at low-current density, but when the current density is increased, the p region will inject a large number of holes into the n
drift region to produce a conductance modulation effect, causing the forward voltage to drop and allowing a large current flow through a metal-semiconductor contact. The conduction mechanism of the MPS diode changes with the gradual increase of the applied forward voltage, and the unipolar operation state dominated by the initial Schottky junction is converted into the bipolar operation state dominated by the pn junction. When the MPS diode in reverse biased, the pn junction space charge region expands into a single piece and shields the Schottky junction, so that the Schottky Fig. 16.3 Schematic of the self-adjusting p+ emitter efficiency diode (SPEED)

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Fig. 16.4 Structure of MPS diode and work principle

junction no longer withstands the applied reverse bias voltage, while the barrier of the reverse bias pn junction is subjected to the external reverse bias voltage to improve the breakdown voltage of MPS diode. The MPS diode is a standard fast recovery diode which has a bias voltage characteristic of withstand voltage and fast recovery. The main application of FRD is to combine with switching devices (such as GTO thyristors, IGCT, IGBT, etc.) to convert DC signals and AC signals. Taking IGBT as an example, IGBT can improve the utilization efficiency of power, and FRD can be used as an auxiliary device for IGBT in reverse bias operation, which can increase the stability and reliability of the system.

Thyristor Thyristor, also known as Silicon-Controlled Rectifier (SCR), is a three-terminal device with a pnpn four-level structure. Thyristor is capable of both forward blocking and reverse blocking and applying a small gate current can trigger it to enter the conducting state from the forward blocking state and maintain stable conduction characteristics. When in the on-state, SCR can be regarded as a conducting state PiN rectifier diode. The rated current of a single Power SCR has reached 5000 A and the rated voltage can reach 8000 V, which means that the power can reach 40 MW. Multiple Power SCRs in series can withstand more than 100 kV to meet the needs of high-voltage power transmission. SCR can operate in a stable state of high current and low voltage, or high voltage and low current. It has the advantages of low-power consumption and high efficiency, which make it suitable for AC power supply circuits and commonly used device in high-power electronic systems. A variety of power electronics such as gate turn-off (GTO) thyristor and integrated gate-commutated thyristor (IGCT) have been derived from SCR. An n+pn
p+ thyristor is consisted of three pn junctions, J1, J2, and J3, as shown in Fig. 16.5 [7]. When a negative voltage is applied to the anode of the thyristor, J1 and J3 are reverse biased and J2 is forward biased so the thyristor enters the reverse

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Fig. 16.5 Circuit symbol, doping density, and structure of SCR

Fig. 16.6 Schematic of SCR in the forward blocking state

blocking state. Due to the high-doping concentration on both sides of J3, it can only withstand lower voltage and therefore the negative voltage applied to the anode is mainly withstood by J1. The doping concentration and thickness of the n
drift region determine the reverse blocking voltage value of the Power SCR and a similar base open bipolar transistor is formed between J1 and J2. The breakdown voltage of the SCR is determined by the breakdown voltage of J1 junction in the base open pnp bipolar transistor, but not the avalanche breakdown voltage of the pn junction. When a positive voltage is applied to the anode, which is mainly withstood by the n
drift region, J1 and J3 are forward biased and J2 is reverse biased so the thyristor goes into the forward blocking state. The forward blocking voltage is determined by that the breakdown voltage of J2 junction in the base open npn bipolar transistor, but not the avalanche breakdown voltage of the pn junction [3]. The schematic of SCR in the forward blocking state is shown in Fig. 16.6. As shown in the figure, the base of the npn transistor is connected to the collector of the pnp transistor, and the base of the pnp transistor is connected to the collector of the

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npn transistor. In the forward blocking state, applying a small gate current IG increases the base current IB2 of the npn transistor and the current gain, thus making IC2 larger. Because IC2 is the base current IB1 of the pnp transistor, the increasing IB1 then amplifies IC1 of the pnp transistor and further a bigger IB2 is obtained. This positive feedback forces the transistors into saturation region so that the three junctions are all forward biased, at which point the SCR is conducting. Once the SCR enters the on-state, even if the external gate current IG is cut off, the positive feedback can still maintain the current flow. The characteristic I-V curve of the Power SCR is shown in Fig. 16.7. A positive voltage UAK applied across the SCR anode-cathode will make it enter the forward blocking state. Though no gate trigger current (IG ¼ 0), when UAK is increased to Breakover Voltage UBO, transition conduction will also occur, making SCR like a diode. This type of pnpn two-side structure device (no gate) becomes a Breakover Diode (BOD). The BOD can be used as an overvoltage protection device in circuits. A gate trigger current IG applied to the SCR in the forward blocking state can cause the transition conductance at a lower UAK. Therefore, it is available to use IG to control the conductance timing of the SCR. A larger IG will lower the transition voltage and lead SCR to conduction in advance. After the SCR is turned on, the current IA does not change with IG. Even if the IG is lowered or removed, the SCR can still maintain the conduction state through positive feedback. Currently, SCR works in a stable high current and low voltage state with low consumption. Only the anode current IA is lower than the Holding Current IH, the SCR will return to the blocking state. A negative voltage UAK across the SCR anodecathode will make it enter the reverse blocking state. By optimizing the width and doping concentration of the p-base and the n
drift region, it is accessible to increase the reverse blocking voltage, lower the leakage current and operational power consumption as well as maintain the stable working state of SCR under high voltage and small current. Fig. 16.7 Characteristic I-V curve of power SCR

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Power BJT The traditional bipolar transistor is a current-driven amplifier, and the analysis of its signal amplification characteristic is mainly based on small injection current. That means, when the transistor is working in the common-emitter state, a small base current can be input to control the collector current at the output end and obtain a large power gain. Power bipolar junction transistors (Power BJT) work in the same way as traditional bipolar transistors for signal amplification, but it can withstand high voltage in the off-state. Therefore, a thick lightly doped n
drift region is added between the p
base region and the n+ collector to block high voltage. When conducting, it is in the state of large current injection. Large current injection in the base and the collector regions will reduce the current gain of the Power BJT, so the control circuit needs to provide a large current to drive the Power BJT, and the design of the control circuit is more complicated and costly. In addition, the current amplification factor and characteristic frequency of Power BJT decrease rapidly with the increase of current. The increasing on-state voltage drop due to large resistance in the n
drift region, as well as the storage charge injection and extraction during the on and off processes all result in high-power consumption of the Power BJT. Though the Darlington Configuration multistage power bipolar transistors can increase current gain, the on-state voltage drop and power consumption increase dramatically, thus increasing power consumption. At present, the blocking voltage of power bipolar transistor can reach 1.8 kV, and the control current has reached 800 A [3]. The structure of the npn Power BJT is shown in Fig. 16.8, in which the n+ diffusion layer is the emitter, the p diffusion layer is the base, the n
epitaxial layer is the drift region, and the n+ substrate is the collector. Like the function of the n
drift region in a PiN device, the capability to withstand voltage of a Power BJT is determined by the doping concentration and thickness of the n
drift region. When a large current is injected into the base, it generates voltage drop in the base region due to base resistance, causing the bias voltage of the central part of the n+p junction between the emitter and base to be lower than that of the edge area, so the emitter and collector current density is uneven, and the emitter edge close to the base

Fig. 16.8 Structure of npn power BJT

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Fig. 16.9 The design layout of npn power BJT

contact has a larger emitter current density. This is known as Emitter Current Crowding. The Emitter Current Crowding can cause a sharp decrease of current gain and also affect the power consumption of the Power BJT during on and off. Therefore, as shown in Fig. 16.9, in the layout of the Power BJT, the interdigital base is around the interdigital emitter to form a symmetrical Interdigitated Finger Geometry, for not only reducing the Emitter Current Crowding effect of emitter current, but also enhancing the heat dissipation capability of the device. A Current Overshoot of the collector current IC will occur when a Power BJT turns on and a Voltage Overshoot of the collector voltage UC will occur when it turns off. The large current and voltage caused by these overshoot phenomena will increase the power consumption of the Power BJT and the probability of destructive device failure. When the Power BJT operates in the positive active region of the characteristic curve, the emitter current with uneven current density distribution will form a local thermal fluctuation on the emitter junction. The part with a higher current density in the local area of the emitter junction has a higher temperature, so that the Built-in Potential of the pn junction in this region decreases with the increase of temperature, which promotes more current to be injected into the region and increases the dissipation power. Therefore, the local temperature further rises, and hot spots are generated inside the transistor due to positive thermal feedback on the emitter junction. The high temperature generated by the hot spots will sharply reduce the Built-in Potential of the pn junction depletion region and short-circuit the collector, and the transistor will enter the thermal low voltage and large current secondary breakdown state. The transistor can be restored to work by adding a current-limiting protection device to the external circuit. If the current protection device is not added, the temperature of hot spots will rapidly rise and damage the material composition and device structure, resulting in permanent damage to the power bipolar transistor. In addition, in the case of high voltage and large current forward bias, the collector current rise will lower the potential barrier of the p base and n
drift region and the maximum electric field intensity will move to the n
/n+ junction, which produces

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avalanche collision ionization near it. Then the transistor enters the forward bias low voltage and large current secondary breakdown state and is prone to destructive failure. Now when the power bipolar transistor is turned off, it is reverse biased. The collector current will be immediately concentrated in the central region of the emitter, making the current density in this region increase by more than ten times. As the collector voltage reaches the peak, the transistor is in the reverse bias state of high voltage and large current, and the electric field peak at this time appears at the interface of the n
drift region and the n+ substrate. Electrons move toward the collector at a saturation speed; this lowers the voltage of the collector junction J1, increases the collector current, and leads to a reverse bias avalanche breakdown with damages in the device. Because this breakdown is caused by that the peak electric field moves from the J2 junction to the n
/n+ junction, resulting in the avalanche region of the n
/n+ junction injecting holes into the collector region and causing the low-voltage avalanche ionization effect, it is called reverse bias secondary breakdown. Introducing a buffer layer with a slightly higher doping concentration between the n
drift region and the n+ substrate, or increasing the junction depth at the edge of the strip emitter can reduce the peak electric field intensity at the interface, so as to avoid the avalanche breakdown at low voltage. The technology of power bipolar transistors is mature, but due to small current gain and low input impedance, Power BJT has been gradually replaced by IGBT with better performance for high-voltage applications.

Power MOSFET Power metal-oxide semiconductor field-effect transistor (Power MOSFET) is considered as an ideal switching device because of its high input impedance, fast switching speed, and negative temperature coefficient (the current decreases with temperature increase). The Power MOSFET can be divided into Vertical Doublediffused MOSFET (VDMOS) and Lateral Double-diffused MOSFET (LDMOS). The source and drain of the vertical device are fabricated on the top and bottom and on both sides of the wafer. Because current flows vertically through the wafer, vertical devices are not suitable for ICs, and are typically encapsulated as discrete devices that can withstand large currents. The structure of traditional VDMOS is shown in Fig. 16.10. Ultra-high voltage devices (above 600 V) require an epitaxial layer thickness of about 100 μm, and the on-state resistance is large. The structure of the trench gate MOSFET is shown in Fig. 16.11. The trench gate MOSFET has a higher channel density and a lower on-state resistance. Backside Grinding technology can be used to grind the wafer thickness to less than 100 μm, which helps to reduce the internal resistance of the trench gate MOSFET [3]. The structure of LDMOS is shown in Fig. 16.12. If the manufacturing process can provide Shallow Trench Isolation (STI) structure, then STI can be added near the trench in the drift region to enhance LDMOS’s capability to withstand voltage, as shown in Fig. 16.13. LDMOS can be combined with integrated circuits. The device

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Fig. 16.10 Structure of traditional VDMOS

Fig. 16.11 Structure of trenched gate MOSFET

shown in Fig. 16.13 has a thickness of about 10 μm and can withstand voltage of 100–200 V. Combined with low-voltage control circuit and protection circuit; it can be made into an intelligent power IC and a display drive circuit. Ultra-high voltage LDMOS capable of withstanding voltage over 600 V requires thick and long drift region (close to 100 μm). In 1979, Appels and Vaes proposed that device characteristics can be optimized by employing a thin epitaxial layer and depleting it completely into a space-charge region to get Reduced Surface Field (RESURF) [8]. The schematic of device depletion in drift region is shown in Fig. 16.14.

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Fig. 16.12 Structure of LDMOS

Fig. 16.13 Schematic of LDMOS with STI structure

Fig. 16.14 Schematic of LDMOS with thin epitaxial layer RESURF structure resulting in a depleting drift region

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Fig. 16.15 Schematic of LDMOS with dual RESURF structure

Fig. 16.16 Schematic of LDMOS with ternary RESURF structure

This concept was followed by the development of multiple RESURF devices, as shown in Figs. 16.15 and 16.16 [9, 10]. If a lateral ultra-high voltage device is integrated into an intelligent power IC, the upper limit of its current is affected by the packaging process, usually about 2A. The structure of the Super Junction (or superjunction) and the trench gate can be fabricated in LDMOS. Similar device structures can also be fabricated by the SOI process, as shown in Fig. 16.17.

Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor (IGBT) was invented by B.J. Baliga [11]. This device solves the problem of large on-resistance of power MOSFETs in high-voltage applications. The manufacturing process of IGBT has gradually matured since the production in 1986. IGBTs are available in vertical (suitable as discrete devices of high voltage and high current) and lateral (suitable for integration with ICs).

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Fig. 16.17 Structure of SOI LDMOS with superjunction drift region

Fig. 16.18 Vertical IGBT structure diagram and equivalent circuit

The vertical type device is shown in Fig. 16.18. It is formed by four layers of alternating npnp semiconductors. The structure of the gate is the same as that of VDMOS. However, the n+ drain of VDMOS is changed to p+ structure. When the gate voltage control channel is turned on, the emitter electrons are injected into the drain of the MOS structure via the channel. This electron current forms the base current of the vertical pnp transistor, triggering the pnp transistor to turn on (see Fig. 16.18a), leading the collector to inject holes to the upper emitter. The IGBT amplifies the current of the VDMOS with a pnp transistor (the gain is β times), so the on-current is larger than that of the VDMOS, i.e., the on-resistance is smaller. When the gate voltage is turned off, the electron current of the MOS channel disappears and turns off the pnp transistor. The switching of the entire device is controlled by the gate voltage, but the IGBT device is a bipolar device. The holes stored in the drift region need to be recombined as the reverse recovery of diodes. Therefore, the operating frequency of IGBTs is usually lower than that of MOSFETs. The central rectangular frame area in Fig. 16.18b is a parasitic thyristor structure. Once this parasitic thyristor is turned on, the device current cannot be turned off even if the gate voltage is turned off, and the gate will lose control. This is the latch-up of IGBT which is like the CMOS latch-up effect. The parasitic

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thyristor operation must be suppressed in the device design to make IGBT work like a transistor [3]. In accordance with the order of the structure and technique improvement, the evolution of IGBTs is as follows. 1. Planar Punch-Through IGBT (PT-IGBT) appeared in 1988. The conduction mechanism of the IGBT is different from that of the MOSFET, which can reduce the on-resistance and solve the contradiction between the blocking voltage and resistance. However, the main disadvantage is that the epitaxial layer acts as a drift region, and the higher collector injection efficiency results in a larger switching loss and a lower withstand voltage. 2. Improved Planar Punch-Through IGBT (Improved PT-IGBT) appeared in 1990. Compared with PT-IGBT, the electric field suspension technique is applied in the improved structure, and the buffer layer with a doping concentration lower than that of the heavily doped p+ region is used to cut off the electric field in the buffer layer, which is advantageous for thinning the thickness of the base region and alleviating the contradiction between withstand voltage and resistance, as shown in Fig. 16.19. 3. Trench IGBT appeared in 1992. The direction of the channel changes from surface parallel to vertical in the body (as shown in Fig. 16.20), which reduces the influence of surface defects on the withstand voltage and reduces the device area, so that the device can withstand a larger on-current per unit area. Both static power and dynamic power have been greatly improved. A disadvantage of the trench structure is that too dense current at the gate affects the short circuit capability of the device. 4. Planar Nonpunch-Through IGBT (NPT-IGBT) was introduced in 1997. The epitaxial layer of the traditional planar penetrating device is thin, and the electric field intensity in the drift region is trapezoidal. The epitaxial layer of the Fig. 16.19 Schematic of improved planar punchthrough IGBT structure

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Fig. 16.20 Schematic diagram of trench IGBT structure

Fig. 16.21 Schematic diagrams of various vertical IGBT structures

conventional planar feedthrough device is thin, as shown in Fig. 16.21a. The thickness of the overall device is large, and p+ substrate accounts for most of the thickness. Planar nonpunch-through IGBT uses a thinner n-type substrate, and the electric field intensity in the drift region changes in a triangle shape. As shown in Fig. 16.21b, the doping concentration of the collector region is controlled by ion implantation. Thickness of the overall device is smaller, and the doping concentration of the control collector region can reduce the carrier injection efficiency of the collector. There is no need to use irradiation techniques or doping gold and platinum to reduce carrier lifetime, optimizing the

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trade-off between on-state voltage drop and turn-off power. At the same time, the base of the parasitic npn transistor becomes thicker, which can reduce the current gain and has a positive temperature coefficient, which overcomes the shortcomings of the conventional IGBT and is beneficial to the parallel operation of the device. 5. Planar Field-Stop IGBT (FS-IGBT) appeared in 2001 (see Fig. 16.21c). In order to solve the problem that NPT-IGBT is difficult to be applied to high-voltage places, FS-IGBT adds an n-type electric field cutoff layer with higher doping concentration than the drift region at the bottom of the drift region, which is used to cut off the electric field and reduce the injection efficiency of the collector. Under the same withstand voltage conditions, the chip thickness required for the FS-IGBT structure is reduced by 1/3 compared with the NPT-IGBT structure, and there is no need to reduce the carrier lifetime. 6. Trench-Gate Field-Stop IGBT (TG FS-IGBT) was introduced in 2003 (see Fig. 16.21d). TG FS-IGBT combines the advantages of the field stop layer and the trench gate, and has become a mainstream. If a portion of the collector p+ layer is changed to n+, the portion forms a reverse-biased diode and is connected in parallel with the original IGBT. This device is called a reverse-conducting IGBT (RC-IGBT) (see Fig. 16.22). There is no need to connect an external parallel diode in the circuit system. The advantages of RC-IGBTs are savings in package cost, smaller size, and improved switching speed. The Lateral IGBT (L-IGBT) structure is similar to the LDMOS except that the n+ drain is changed to the p+ structure, as shown in Fig. 16.23. L-IGBTs with a withstand voltage of 200 V or less, the current increase is not greater than that of LDMOS, but it is subject to the risk of latch-up and high-temperature instability. The length of the L-IGBT with a blocking voltage of 600 V or more is greater than the

Fig. 16.22 Schematic of RC-IGBT structure

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Fig. 16.23 Schematic diagram of lateral IGBT structure Fig. 16.24 Schematic diagram of lateral SOI-IGBT structure

thickness, and the horizontal electric field strength at the time of conduction may be smaller than the vertical electric field strength, so that holes injected from the collector are easily diffused into the substrate to form a leakage current. Therefore, the research on L-IGBTs is more focusing on silicon-on-insulator (SOI) structures, as shown in Fig. 16.24.

Wide-Bandgap Semiconductor Devices In the design of the power device, the ratio of the breakdown and the Specific On-State Resistance (unit: V/Ω cm2) can be used as the evaluation index. The higher the value, the better is the characteristics of the device. The on-state characteristic

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resistance is defined as the device’s on-resistance multiplied by its top view area. The on-resistance value determines the power loss and the breakdown voltage determines the blocking voltage when the device is turned off. Theoretical derivation shows that for the parallel electrode pn junction (one-dimensional electric field), the on-state characteristic resistance of the ideal drift region is [3] Ron-ideal ¼

4BV2 es μn E3C

where BV is the breakdown voltage; εs is the dielectric constant of the semiconductor; μn is the electron mobility; Ec is the critical electric field strength causing the 2 breakdown. Ron-ideal ¼ e4BV in the denominator is generally named as the Baliga’s μ E3 s n C

Figure of Merit (BFOM) of the power device. This is a sign of the influence of semiconductor material properties on the resistance of the drift region. It can be seen from the above equation that in a conventional one-dimensional electric field power device, the on-state resistance is proportional to the square of the breakdown voltage if the breakdown voltage is increased by a factor of two, then the on-state resistance is increased by a factor of four. Wide-bandgap semiconductors generally refer to silicon carbide (SiC), and gallian nitride (GaN). Common parameters of semiconductor materials are shown in Table 16.1. If Baliga’s Figure of Merit of silicon, BFOM(Si), is 1, then BFOM(GaAs) is 15.6, BFOM(SiC) is 528, and BFOM(GaN) is 718. At the same breakdown voltage, the on-state characteristic resistance of a wide-bandgap semiconductor device is approximately two-thousandths of the resistance of a silicon device. A line graph as shown in Fig. 16.25 is drawn according to the formula at the beginning of the section and the data of Table 16.1, wherein the line corresponding to silicon is called the silicon limit. Researchers often plot the on-state characteristic resistance and breakdown voltage of their products on a table to examine the gap between their products and theoretical limits. Under a one-dimensional electric field, when the drift region of the power device is parallel to the electrode, the relationship between the Ron-sp and the breakdown voltage of the wide-bandgap semiconductor is far below the silicon limit. Table 16.1 Table of common parameters of semiconductor materials Parameter Eg/eV μn/(cm2/(V  s)) μp/(cm2/(V  s)) EC/(V/cm) vgal/(cm/s) εS

Si 1.12 1400 600 0.3  106 1.0  107 11.8

GaAs 1.43 8500 400 0.4  106 2.0  107 12.8

Note: The values will vary under different conditions.

4H-SiC 3.26 900 100 3.0  106 2.7  107 9.7

GaN 3.50 1250 200 3.0  106 2.7  107 9.5

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Fig. 16.25 Relationship between Ron-sp and breakdown voltage of different semiconductors

Fig. 16.26 Comparison between superjunction structure and traditional structure

Superjunction Thyristor The super junction (or superjunction) of semiconductor power devices was invented in 1993 by Xingbi Chen, University of Electronic Science and Technology of China, the basic structure is shown in Fig. 16.26a [12]. The VDMOSFET with the superjunction structure as the drift region is shown in Fig. 16.27. The theoretical basis is that when the doping concentration of the n
region and the p
region is equal, and the volume is also equal, the positive and negative charges are completely canceled, which is equivalent to a semiconductor with extremely low impurity. Essentially, the thickness of the drift region can be much smaller than the thickness of a conventional device, and the on-state resistance is much smaller. The 600 V VDMOSFET with superjunction has a drift region thickness of approximately 20 μm and an on-resistance of 20% of a conventional 600 V device.

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Fig. 16.27 VDMOSFET with superjunction structure as drift region

Since the built-in electric fields of the n
region and the p
region are horizontal, when a voltage is applied to the device (vertical direction); a two-dimensional electric field is formed in the drift region. Theoretical derivation shows that the relationship between the on-state characteristic resistance and the breakdown voltage of this type of device is Ron-sp ¼

2BVp eS μn E2C

where p is the sum of the width of n
region and p
region [3]. The relationship between the Ron-sp and the breakdown voltage of the superjunction device is shown in Fig. 16.28. Because of the multidimensional electric field, its characteristics have exceeded the silicon limit of the one-dimensional electric field, but still not as widebandgap devices. The superjunction can be used for both the drift region of a vertical IGBT and the drift region of a lateral device. The lateral thyristor structure with superjunction drift region is shown in Fig. 16.29.

Gate Turn-Off Thyristor The current amplification factor and on-state characteristics of bipolar power transistors decrease rapidly with the increase of voltage level, thus inhibiting the development of bipolar power transistors in applications with voltage higher than 2 kV, such as electric locomotives. In DC circuits, the need to design thyristor structures so that gate signals can be used to control the opening and closing of thyristors promotes the development of gate turn-off (GTO) thyristors. The turn-off of GTO thyristor is achieved by applying a large reverse current. The gate current must be large enough to eliminate the charge stored in the p-base region and to stop the internal transistor coupling to turn off the current [3]. Such devices have an upper

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Fig. 16.28 Diagram of the relationship between Ron-sp of superjunction device and breakdown voltage Fig. 16.29 Lateral thyristor structure with superjunction drift region

current limit called the maximum switchable current or the maximum controllable current. When the current exceeds this limit and a larger back-gate current is applied to turn off the device, it will lead to the p-type base region to conduct with the n+ cathode and fail to turn off the current. The maximum switchable current density of GTO thyristor is about 1000 A/cm2, and the maximum turn-off gain (the ratio of the device current to the reverse gate current) is about 5. The structure and electric field distribution of a symmetric GTO transistor are shown in Fig. 16.30. Although similar to the traditional thyristor structure, the GTO structure does not include cathode short connection. In the case of forward bias, the

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Fig. 16.30 Structure and electric field distribution of a symmetrical GTO thyristor

Fig. 16.31 Structure and electric field distribution of an asymmetric GTO thyristor

voltage drop is across the p-type base/n-type base junction. The forward blocking capability is determined by the breakdown voltage of the transistor npn with base region open circuit, which is consistent with the traditional thyristor. In reverse bias, the voltage drop is mainly concentrated across the p+ anode-n base junction. Because GTO thyristor is used in DC circuit, its reverse blocking capability does not need to be as strong as its forward blocking capability. The structure and electric field distribution of asymmetric GTO thyristors are shown in Fig. 16.31. An n-buffer layer is added to the n-base region adjacent to the p+ anode region, as shown in Fig. 16.31a. The doping concentration of the n-buffer layer is much higher than that of the lightly doped portion in the n-base region. The trapezoidal electric field distribution of an asymmetric GTO thyristor is shown in Fig. 16.31b. To obtain

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the same forward blocking voltage, the net thickness of the n-base region in the asymmetric GTO thyristor is smaller than that of the n-base region required for the symmetric GTO thyristor, which will reduce the on-state voltage. At the same time, the n-buffer layer also reduces the current amplification factor of the pnp transistor, which can increase the turn-off gain of GTO thyristor. The n-buffer layer is usually shorted to the anode to reduce the turn-off time. GTO thyristor can turn off the current in the DC power circuit, so GTO thyristor has been used to control the drive current in the motor drive equipment of the electric locomotive. These new generations of motor drive equipment are widely used in high speed rail transport systems.

Integrated Gate-Commutated Thyristor Integrated gate-commutated thyristor (IGCT) is a power semiconductor electronic device for switching currents in industrial equipment, which was jointly developed by Mitsubishi and ABB. The basic structure of IGCT is shown in Fig. 16.32. IGCT is similar to GTO thyristor, but there are multiple gates in parallel. IGCT can be controlled to turn on and off by the gate signal, has lower conduction loss than GTO thyristor, and can withstand higher voltage rise rates, making a buffer unnecessary for most applications. In IGCT, the switching-off current is larger than the anode current due to the parallel connection of multiple gates, which shortens the time for eliminating a few carriers completely and makes the IGCT device switching-off faster. Also, the inductance and resistance connected to the gate driving circuit become lower because of the parallel connection of the gates [13]. Compared to GTO thyristors, an IGCT has faster turn-off time, so it can work at frequencies up to several kHz in a short period of time. Fig. 16.32 Basic structure of IGCT

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Fig. 16.33 Structure comparison between GTO and S-IGCT

IGCT can be fabricated into devices with or without reverse blocking capability. However, due to the need for a long and low-doped drift region to improve the reverse blocking ability, it will increase the forward voltage drop. IGCT capable of preventing reverse voltage is called symmetrical IGCT (S-IGCT), and its structure is in analogous to the electric field distribution and GTO thyristor, as shown in Fig. 16.33. Normally, the reverse blocking voltage rating of S-IGCT is the same as that of forward blocking voltage rating. A typical application for S-IGCT is a current source inverter. The IGCT, which cannot block the reverse voltage, is called asymmetric IGCT (A-IGCT). It usually has a reverse breakdown voltage of several tens of volts. However, the forward voltage drop is lower than that of S-IGCT since the drift region is shortened by the addition of the n-type buffer layer. A-IGCT is used in parallel application of reverse conducting diode (e.g., in a voltage source inverter) or in the absence of reverse voltage (e.g., in a switching power supply or DC traction chopper). If the p+ collector is partially changed to an n+ region, the portion becomes a reverse conducting diode in parallel with the IGCT. Asymmetric IGCT fabricated with reverse conducting diode in the same package is called RC-IGCT, which is an IGCT used for reverse conducting. IGCT is mainly used in variable-frequency inverters, drives, and tractions, for example, in a motor-driven towing vehicle.

Emitter Turn-Off Thyristor Emitter Turn-Off (ETO) thyristor has the ability to block high voltages and high currents of the gate-off thyristor and the advantages of easy control of the MOS gate. Other features include high-voltage current rectification capability and device

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Fig. 16.34 Structure and circuit symbol of ETO thyristor

current sensing capability. The structural schematic diagram and circuit symbol of ETO thyristor are shown in Fig. 16.34. As shown in Fig. 16.34, VQG acts as a gate switch and is connected to gate 1. ETO thyristor is a power device consisting of an emitter switch, that is, a low-voltage MOSFET (VQG is a pMOSFET, VQB is an nMOSFET) and a GTO thyristor in series. A positive voltage is applied on gate 2 and gate 3 to turn on the device. At this point, VQG is turned off, VQB is turned on, and the cathode voltage is applied to the GTO thyristor by VQB to turn on the GTO thyristor. When negative voltage is applied on gate 2 and gate 3, the device is turned off. At this time, VQB is turned off and VQG is turned on, and the current of GTO thyristor flows to the cathode through the gate 1 and VQG. Since the current from the anode flows only through the pnp transistor without flowing through the first pn junction J1, the positive feedback loop of the GTO thyristor is destroyed, causing the device to turn off [14]. In open pnp mode, turning off npn transistor is the key to achieving high speed and large cutoff current capability. ETO thyristors use anode current to provide shutdown energy. Compared with IGCT technology, ETO thyristors greatly save the driving power required for high-frequency operation. Both turn-on and turn-off are controlled by the gate voltage of low-voltage MOSFET.

MOS-Controlled Thyristor MOS-controlled thyristor (MCT) is a power device combining a bipolar power transistor and a MOS power transistor. The two MOS gates are mainly used to control the conduction current of the thyristor to obtain better turn-off characteristics [15, 16]. As shown in Fig. 16.35a, one MOS is used to turn on the device and the other is used to turn off the thyristor. MCT not only provides the working characteristics of bipolar technology and MOS technology, but also provides a suitable

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Fig. 16.35 MCT structure and equivalent circuit diagram

alternative for existing power devices. MCT is a new kind of composite device that combines the high-power handling capability of thyristors with the ease of control and high speed of MOS gate devices [17]. MCT technology is compatible with IC technology as illustrated in Fig. 16.35a with one of the cells and Fig. 16.35b its equivalent circuit. A small MCT has about 10,000 cells. As seen by the equivalent circuit, the gates of the two MOSFETs are connected to the gate (G) of the MCT. When the gate voltage is biased positive with respect to the cathode, the nMOSFET is turned on (the pMOSFET is off) and the current flows from the anode into the base of the npn transistor to turn the device on. When the device is turned on, the voltage of the anode is only slightly higher than the cathode voltage. At this time, if the gate voltage is negative relative to the anode, the pMOSFET is turned on, and the current flows directly to the anode through the pMOSFET without passing through the emitter junction of the pnp transistor. Then the positive feedback of the thyristor is closed due to being destroyed. If there is only one MOSFET in the power device that triggers the turn-on thyristor without the MOSFET that turns off the thyristor, the device is called a MOS-gated thyristor (MGT). The advantages of MCT: ① High voltage and high current; ② Low on-state voltage drop (1/3 of IGBT, about 1.1 V); ③ Extremely high di/dt and dv/dt tolerance (di/dt ¼ 2000 A/μs, dv/dt ¼ 20,000 V/μs); ④ High switching frequency, low power consumption; ⑤ High operating temperature (above 200  C); ⑥ Simple gate drive circuit; ⑦ Device is not closed broken and damaged. A Power BJT has the ability to pass high currents and withstand high voltages. The strong conductivity modulation effect by the high current injection can lead the BJT at a lower on-state voltage drop, so the conduction power consumption is lower. BJT power devices are minority carrier transport devices with long minority carrier

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storage time, resulting in slower switching speed of the devices; and because they are current control devices, the matched drive circuits are relatively complex. In contrast, MOS power devices are based on majority carriers, so the switching speed is very fast. In addition, the input impedance of MOS power device is capacitive with high impedance, and the switching of the device is controlled by voltage, so the design and manufacture of driving circuit are very simple. Especially when operating at low frequencies, compared with the BJT power device, there will be faster switching speed. The MOS power device has a temperature coefficient of positive resistivity, and since there is no phenomenon of conductivity modulation, the MOS power device has a large on-resistance Rds at a high voltage. As MCT is a BJT-MOS composite device that combines the advantages of BJT power devices and MOS power devices in operation, it is suitable for low frequency, high voltage, and high power applications. Its voltage blocking capability can reach 10 kV. However, the energy consumption during switching transient limits the maximum operating frequency of MCT structure (less than 100 kHz). Compared with the structure of GTO device, the advantage of MCT structure is that the gate control circuit matching its MOS gate structure is relatively simple, and because the shunt path is short, the anode voltage of MCT can begin to rise immediately after the gate voltage reaches the negative gate power supply voltage, so the charging interval during the shutdown process is shorter. Compared with IGBT, MCT has smaller on-state voltage drop and better power loss curve, but lacks a forward-biased full-working area, so it is difficult to replace IGBT.

References 1. C. Wang, New Devices of Power Semiconductor and Its Manufacturing Technology (China Machine Press, 2015). ISBN 9787111475729 2. Power Devices. https://en.wikipedia.org/wiki/Power_semiconductor_device. Accessed 21 Feb 2020 3. B. Jayant Baliga, Ch. 5, P-i-N rectifiers, in Fundamentals of Power Semiconductor Devices (Springer, Raleigh, NC, USA, 2008), pp. 203–276 4. S. Matthias, J. Vobecky, C. Corvasce, et al., Improved recovery of fast power diodes with selfadjusting p emitter efficiency. Proc. ISPSD 88–91 (2011) 5. H. Schlangenotto, J. Serafin, F. Sawitzki, et al., Improved recovery of fast power diodes with self-adjusting p emitter efficiency. IEEE Electron Device Lett. 10(7), 322–324 (1989) 6. B. Jayant Baliga, Ch. 4, Schottky rectifiers, in Fundamental of Power Semiconductor Devices (Springer, Raleigh, NC, USA, 2008), pp. 167–200 7. K. K. Ng, Complete Guide to Semiconductor Devices, 2nd edn. (Wiley, New York, NY, USA, 2002) 8. J.A. Appels, H.M.J. Vaes, HV thin layer devices (RESURF devices), Proceedings of the International Electron Devices Meeting (1979), pp. 238–241 9. M.M. De Souza, E.M. Sankara Narayanan, Double RESURF technology for HVICs. Electron. Lett. 32, 1092–1093 (1996) 10. M. Qiao, Y. Li, X. Zhou, et al., A 700-V junction-isolated triple RESURF LDMOS with n-type layer. IEEE Electron Device Lett. 7(35), 774–776 (2014) 11. B. Jayant Baliga, Enhancement and depletion mode vertical channel MOS-gated thyristors. Electron. Lett. 15, 645–647 (1979)

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12. X. Chen, Semiconductor Power Devices with Alternating Conductivity Type High-Voltage Break Down Regions, US Patent, 5216275 (1993) 13. Integrated gate commutated thyristors. https://en.wikipedia.org/wiki/Integrated_gate-commu tated_thyristor. Accessed 21 Feb 2020 14. B. Zhang, A.Q. Huang, Y. Liu, et al. C. IEEE Conference Record of the 2002 IEEE Industry Applications Conference (2002), pp. 559–563 15. V.A.K. Temple: J. IEEE Electron Device Meeting, Abstract 10.7:282–285 (1984) 16. M.K. Kazimierczuk, N. Thirunarayan, B.T. Nguyen, et al., R/OL. AIP Conf. Proc. 271, 459–468 (1993). https://doi.org/10.1063/1.43187 17. B. Jayant Baliga, Advanced High Voltage Power Device Concepts (Springer, Raleigh, NC, USA, 2011)

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Yizhe Sun, Wen Yu, Letao Zhang, and Shengdong Zhang

Contents Optoelectronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avalanche Photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Organic Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Matrix Organic Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quantum Dot Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thin-Film Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Laser Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Photomultiplier Tube (PMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optical Communication Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

The optoelectronic devices refer to those functional devices, whose operation principles are based on photon-electron or electron-photon conversion effects, e.g., photovoltaic, photoconductive, and photoelectron emission effects. According to the working mechanism and applications, these optoelectronic devices are mainly classified into three categories. The first is photodetector or photoelectric receiver. The second is the electroluminescent device that realizes the conversion of electrical signal to optical signal. The third is the solar cells that convert solar energy into electricity and storage. The basic structures and working principles of these devices are briefly described in this chapter.

Y. Sun · W. Yu · L. Zhang · S. Zhang (*) Electronic and Computer Engineering, Peking University, Shenzhen, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_17

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Keywords

Photon-Electron Effect · Electron-Photon Effect · Photodetector · ElectroLuminance · Solar Cell

Optoelectronic Devices The optoelectronic devices refer to those functional devices with photon-electro (or electro-photon) conversion effect as the working principle. As early as 1873, Willoughby Smith [1] discovered the photoelectric phenomena of semiconductor selenium (Se), 74 years before the invention of transistor in 1947. This led to the application of selenium photovoltaic cells. However, due to the limited knowledge at that time, the development of optoelectronic devices was relatively slow. In 1887, Heinrich R. Hertz, a German physicist, observed the escape of electrons from the surface of an object under light radiation in his electromagnetic wave experiments, thus this revealed the physical basis of optoelectronic devices – the photoelectric effect. In 1916, Albert Einstein perfected the basic principle of photon-object interaction based on quantum theory, presenting the essence of photoelectric effect to the world; because of this, he won the Nobel Prize in physics 1921. After the 1930s, the research on the physical properties of semiconductor, especially the optical properties of semiconductor, has further consolidated the physical basis of optoelectronic devices. Photoelectric effect is divided into photovoltaic effect, photoconductive effect, and photoelectron emission effect. According to the difference of working mechanism and application, optoelectronic devices are mainly classified into three categories. 1. The first category includes photodetectors or photoelectric receivers, such as Avalanche Photodiodes (APDs), which are widely used in sensing, detection, and communication fields today. Under radiation conditions, the electrical properties of these devices can be changed, so that the detected optical signals can be converted into electrical signals, and the required information can be obtained through the analysis results of electrical signals. 2. The second kind of device realizes the conversion of electrical signal to optical signal, namely electroluminescent device, Light-Emitting Diode (LED), and Laser Diode (LD) are typical examples. LED have many advantages, such as long life, low cost, wide spectrum range, etc., and they are widely used in display and lighting fields. LD has narrow spectra and strong directivity, they are widely used in large-capacity, long-distance optical fiber communication systems, and optoelectronic integrated circuits. 3. The third kind of devices, typically represented by photovoltaic devices (PV) or commonly known as solar cells, can convert light energy into electricity and store it. They can directly convert solar energy into electricity with high efficiency, providing permanent power with low operating cost.

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Nowadays, optoelectronic devices have penetrated every corner of society and life, such as remote sensing, guidance, infrared detection, medical detection, mobile phone, camera, display, and so on. Their applications have expanded from military defense to civilian products, with their corresponding industrial structure and scale increasingly large. At the same time, a variety of high-performance optoelectronic devices will continue to emerge with continuous discovery of new technologies, materials, principles, and applications.

Photodiodes Photodiodes (PDs) are usually composed of a pn junction that generates photocurrents under incident light. I-V characteristics of PD are shown in Fig. 17.1. Under reverse bias, the current is small in dark. The dark current, which is called reverse saturation current, maintains its level before it reaches reverse breakdown voltage. Under illumination, electron-hole pairs (EHPs) are generated in the semiconductor. Since EHPs remain inside the semiconductor, this is called the internal photoelectric effect. Under bias condition, the electron and holes generated in the pn depletion region rapidly drift toward the opposite direction of polarity, whereas the EHPs within a diffusion length to the depletion area enter the depletion area through diffusion and drift mechanism, which also generates photocurrent. Since there is no electric field in the area far away from the depletion area, the EHPs generated there cannot contribute as photocurrent and generally disappear by recombination. The greater the intensity of the illumination, the more EHPs are generated, and the larger the reverse current is formed, as illustrated in Fig. 17.1. In the manufacturing process, to improve the light absorption efficiency, the area of the pn junction should be larger. Since most light is absorbed at the surface, the position of the pn junction should be as close to the surface as possible. High-quality semiconductor materials with low defects are necessary to form photodiodes with Fig. 17.1 The I-V properties of photodiodes

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low dark current. Therefore, the rapid development of semiconductor epitaxial growth technology plays an important role in improving the performance of photodiode detectors by eliminating defects in epi-layer. Due to the advantages of small size, low cost, good linearity, wide response in spectral range (190 nm to 1100 nm), low noise, high reliability, long life, and low voltage power supply, silicon pn photodiode plays an important role in optical communication, camera, video equipment, and photodetection. However, pn photodiodes still suffer from disadvantages such as low sensitivity, insufficient detectivity, and slow response. The emergence of PiN (p-i-n bipolar) photodiodes can solve these problems. Photodiodes have a wide range of applications and commercial values in ultraviolet (UV) detection, visible light detection, infrared (IR) detection, and X-ray imaging. Different materials are suitable for certain detections, depending on their band gap width. High-quality germanium (Ge) single crystal materials are widely used around the area of near infrared (NIR) detection because of their high sensitivity. This detector generally needs to be cooled to 77 K to reduce the dark current, which increases the cost and limits its applications. With the continuous development of Ge technology on Si substrates, the process cost of Ge photodiodes has been greatly reduced, and its application has been extended to the area of optical communications [2]. Due to their wide linear dynamic range, photodiodes are commonly used as optical power meters in the market, which can detect light with various wavelength. If a narrow-band semiconductor photodiode is used to detect ultraviolet light, it is necessary to use a filter to block visible light. Meanwhile, it requires cooling to reduce the dark current. If wide-band semiconductor photodiodes are adopted, the above problems do not exist, but suitable substrate with advanced epitaxial growth technology is required. In medical X-ray imaging technology, photodiodes can be used in the direct or indirect detections. In the case of indirect detection, X-rays are usually absorbed by a thick layer of scintillator material and then converted to visible or ultraviolet light, which is detected by photodiode devices.

Avalanche Photodiode Avalanche Photodiode (APD) is a photodiode with a high-current amplification gain. As shown in Fig. 17.2, under reverse bias, the electric field in the depletion region increases with the increase of the applied voltage, and the drifting speed and kinetic energy of the carrier in the depletion area also increase accordingly. When the kinetic energies of electrons or holes reach a certain level, collision ionization occurs [3]. That is, electrons or holes with high energy colliding with the lattice, which break their chemical bonds, creating new electronic-hole pairs, and the new electron-hole pairs continue to accelerate under the electric field and collide with the lattice again. This process forms positive feedback and continues, resulting in an effect that is similar to the avalanche, which brings a photoelectric response with high internal gain. The main difference between APDs and ordinary photodiodes is that after the

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Fig. 17.2 (a) Structure of avalanche photodiodes. (b) The distribution of electric field

semiconductor absorbs one photon, it creates more than one pair of electron and hole, i.e., the quantum efficiency is greater than 1. The multiplication factor M is used to measure its photoelectric gain, which is defined as: M¼

i , i0

where i is the output current, i0 is the original current before avalanche effect takes place. In order to ensure a uniform multiplication of carriers throughout the whole photosensitive area, the semiconductor material must have no defects and the interface must be smooth. To obtain low-noise avalanche photodiodes, the rate of ionization between electrons and holes should be large. Silicon has a high ionization rate ratio (≈20), so it is an ideal APD material. However, most III-V semiconductors, such as indium gallium phosphate (InGaAsP), have an ionization rate ratio of approximately 1. Usually by adopting a super-lattice structure, the III-V semiconductor ionization rate ratio can be improved to achieve a low-noise avalanche photodiode [4]. In terms of photodetection, the detection of long wavelength photons, such as infrared, mainly uses narrow-band semiconductors such as germanium, indium gallium arsenic (InGaAs), and mercury cadmium telluride (HgCdTe). Polycrystalline silicon carbide materials (4H-SiC) with a band gap of 3.36 eV are widely adopted for UV detection that is close to visible blindness. Compared with gallium nitride (GaN), SiC is relatively more mature for manufacturing; it has superior thermal stability and high dissociation rate ratio [5]. In recent years, avalanche photodiodes have been increasingly applied in commercial, military, and scientific research applications. Compared with PiN photodiodes, APDs can detect light with lower intensity and can meet the demands of long-range optical communication and

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optical path testing; nonetheless, they require more stringent requirements for bias and temperature stability. Because of its high sensitivity and fast response, APD has attracted lots of attention around the area of photon counter in recent years. Photomultiplier tube (PMT), which is a vacuum-based device, was first applied to photon counter. The appearance of APD devices has turned solid single-photon detectors into reality. Silicon-based single-photon APDs can achieve high-efficiency, low-noise visible photon counter. However, due to the lack of ideal IR absorption materials, the current performance of IR photon counter is not as good as that of visible photon counters [6].

Light-Emitting Diode Light-Emitting Diode (LED) is a diode that emits specific wavelength of light by the recombination of electrons and holes. The common white light is composed of red, green, and blue lights. The energy of radiated photons, i.e., wavelength of the light, is determined by the bandgap of the semiconductor. Therefore, the development of LED is mainly focused on materials with various bandgap. Nick Holonyak from the American General Electric Laboratory fabricated GaAsP-based red LED for the first time in 1962 [7]. The GaP-based green LED was fabricated and reported in 1968 [8]. However, the white light could not be obtained due to the technical difficulty of fabricating blue LED before 1990. At the beginning of 1990s, the LED technology achieved a breakthrough, the blue LED was successfully fabricated [9] by Shuji Nakamura, Isamu Akasaki, and Hiroshi Amano, who won Nobel prize in physics 2014. Nowadays, LEDs have been widely applied in house lighting, pilot lighting, back light of liquid crystal display (LCD), and so on. The physical principle of LED is shown in Fig. 17.3. When the p-type and n-type semiconductors are brought together, the holes in p-type or the electrons in n-type semiconductor material will diffuse toward the other side because of the concentration gradient. A space charge area is thus formed at the interface, leading to the drift of the holes or electrons against the diffusion direction as well. Diffusion and drift current will be finally balanced. If a positive voltage is applied to the p-type material, the built-in electric field will be weakened, leading to increased diffusion current. The outcome is large amount of electrons and holes will be recombined, resulting in light emission. The structure of a LED is far more complicated than the one shown in Fig. 17.4. This is because luminous efficiency of a simple pn structure is quite low; or even worse, the efficiency will further reduce with increased injected current. Taking blue LED case for example, a practical device structure is shown in Fig. 17.4: a Multiple Quantum Well (MQW) is inserted between p-GaN and n-GaN to improve the combination efficiency of electron-hole pairs. Besides, to achieve better luminous efficiency, p(n)-type AlGaN will be introduced between the MQW and the p(n)-type GaN so to further confine the injected electrons and holes.

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Fig. 17.3 Schematic of LED

Fig. 17.4 Structure of blue LED

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Organic Light-Emitting Diode An organic light-Emitting diode (OLED) is a light-emitting diode (LED) device based on organic semiconductors. The discovery of OLED can be traced back to the observation of the phenomenon of light emission of organic materials biased at a high voltage in the 1950s [10]. In 1983, Ching W. Tang et al. fabricated a heterojunction OLED and proposed a method for manufacturing small-molecule organic phosphorescent emitting layers [11, 12]. Since then, the OLED research boom has been kicked off. In 1990, the discovery of electroluminescence of polyphenylene vinylene (PPV) further promoted the research of polymer OLED [13]. In 1998, the discovery of phosphorescent materials greatly improved the quantum efficiency of OLED devices [14], which led to a breakthrough in the research of polymer OLED. Nowadays, phosphorescent OLED has become the basic technology for energysaving light sources and low-power flat panel displays (FPDs). A typical small molecule OLED device has two layers of organic materials located between the anode and cathode as shown in Fig. 17.5. When an OLED is forward biased, holes in Hole Transport Layer (HTL) and electrons in Electron Transport Layer (ETL) transport to the interface of HTL and ETL and accumulate at the interface. An exciton is formed after recombination of an electron and a hole. When excitons return to the ground-state energy level, they release photons. Shown

Fig. 17.5 Schematics of small molecule OLED: (a) structure; (b) energy band Fig. 17.6 Schematic of polymer OLED

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in Fig. 17.6 is the schematic of a single-layer polymer OLED. Under forward bias, electrons and holes recombine after transporting in the polymer layer, and then excitons are formed. As a new type of energy-saving light source, OLED lighting meets the standard of green lighting. A major advantage of OLEDs is that they can be produced using a thin film deposition process. In addition, OLED lighting is surface-emitting light source, so that a more uniform illumination effect can be achieved. Companies such as LG in Korea, Sumitomo Chemical in Japan, and Philips in the Netherlands have exhibited products related to OLED light sources. In the next few years, OLED lighting products may usher in rapid development. However, OLEDs still have lower luminous efficiency, and the lifetime of the shortest-lived blue OLEDs in RGB-OLED is estimated to be about 10,000 h. With the development of technology and the improvement of material properties, blue OLEDs are expected to meet the life expectancy of 40,000 h. Another important application of OLEDs is for flat panel display. Compared with traditional LCD displays, OLED display panels do not require a backlight and can be thinner, more energy saving, and portable. In addition, flexible and curved display can be realized. In recent years, with the extensive applications of OLED panels in smart phones, televisions, and other fields, OLED market is rapidly developing. For instance, the current displays for big three of Virtual Reality (VR) products are Sony PlayStation VR, Oculus Rift, and HTC Vive displays all adopt OLED technology. Since the OLED requires current driving, the driving device, that is the thin-film transistor (TFT), is required to have high field-effect mobility. The field-effect mobility of the current mainstream amorphous-silicon TFTs cannot meet the requirements of OLED displays. Although the polysilicon TFTs have higher mobility, they mainly are limited in small-sized panels due to the poor large-area uniformity. Besides, the metal oxide TFT technology can meet the requirements of OLED displays.

Active Matrix Organic Light-Emitting Diode The active matrix organic light-emitting diode (AMOLED) display is a rising display technology. The active matrix (AM) and organic light-emitting diode (OLED) respectively refer to active matrix addressing technology, and organicbased electroluminescent device. Compared with the incumbent liquid crystal display (LCD), AMOLED technology possesses significant advantages, such as faster response, higher contrast ratio, wider viewing angle, capability of low-temperatures(40  C) operation, etc. As a promising candidate of future displays with great potential and broad market prospects, AMOLED display features are well broadcasted [15]. Each pixel of AMOLED consists of two thin-film transistors (TFTs) respectively for addressing and driving the OLED. The TFT circuits are prepared on the glass substrate to form AM, and the OLED is prepared on top of or next to the TFTs. Unlike the voltage-driving LCD, the brightness of current-driving OLED is directly

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Fig. 17.7 Comparison of light-emitting principle between TFT-LCD and AMOLED

determined by the current of driving TFT. Therefore, the pixel circuit needs a TFT gating circuit of switching function and also a TFT drive circuit to provide current for OLED. Figure 17.7 shows the schematic cross sections of TFT-LCD and AMOLED. Since the liquid crystal does not have self-luminous capability, a backlight is necessary in the TFT-LCD. For AMOLED, three separate stacks of red, green, and blue electroluminescent materials work together to form a true color. In addition, without additional backlight source, the self-luminous AMOLED display is more energy efficient and thinner [16, 17]. Two kinds of AMOLED luminescent structures are comparatively illustrated in Fig. 17.8. In the bottom emission structure, the pixel circuits cannot become effective display region, resulting in a low aperture ratio. In contrast, since the OLED in top emission structure can cover all pixel regions, a high aperture ratio can be readily achieved, thus enabling this structure the focus of display research. For the current smartphone market, there are a considerable number of products equipped with AMOLED screen with a continuously rising market share. In the fields of wearable devices and virtual reality, AMOLED screen shows great prospects due to its thinness, flexibility, and low-power consumption [18].

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Fig. 17.8 Two luminescent structures of the AMOLED

Micro Light-Emitting Diode Micro Light-Emitting Diode (MicroLED), also known as micro-LED, mLED or μLED [19], is a miniaturizing and matrixing technology of Light-Emitting Diode (LED). Specifically, it enables the integration of the originally large LED onto the chip by using the micromachining technology, forming a high-density pixel matrix with the pixel pitch reduced from millimeter level to micrometer level and each pixel independently addressed and lightened. Since 1990s, the liquid crystal display (LCD) technology has become the focus of display industry, with the LED panels emerging as backlights. At the beginning of twenty-first century, the LCD backlight module based on white LED technology has thoroughly replaced the traditional cold cathode tube (CRT) backlight module in a short time; and it has been extensively applied to all kinds of display products. However, LCD is not a self-emissive display technology, which leads to a low photoelectric efficiency. In addition, the color saturation provided by white LED is still not as good as that of tricolor LED; and its outdoor contrast is low as seriously affecting the visual effect. In order to overcome these problems, another display technology that is directly implemented with three primary colored LEDs as selfemissive pixels has gradually attracted people’s attention, as referred to as “MicroLED” display technology. With the continuous improvement of the production technology, Sony Corporation demonstrated a 55-inch FHD “Crystal LED Display” prototype in 2012, by using Surface-Mount Technology (SMT) or Chip on Board technology (COB) to mount LED chips onto the circuit boards. As many as 6.2 million LED chips greatly improved the display resolution with contrast ratio as high as one million to one; and even the slow response, inflicting LCD on criticism, could

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Fig. 17.9 Comparison of basic structures of the display technology of TFT-LCD, OLED, and MicroLED

be solved. However, the commercial mass production of MicroLED is still hindered by many problems, such as technique and cost challenges. MicroLED is essentially a pn junction diode. When the pn junction is in conducting state under forward bias, the working current promotes the recombination of electron-hole pairs in luminescent layer, thereby emitting desired monochromatic light. MicroLED has a high color saturation and a full width at half-maximum (FWHM) around 20 nm. Besides, benefited from its self-emissive nature, MicroLED has simple structure with reasonable high extraction efficiency, low power consumption, and high brightness (>1000 nits, 1 nit ¼ 1 cd/m2). The fabrication of MicroLED display starts with the miniaturization of LED structure and further matrixing of these devices by adopting thin-film technology. Then, the LED arrays are transferred to the backplane, consisting of bottom electrodes and transistors. The protective layer and top electrode are then implemented with physical deposition process, followed by the final packaging of top substrate. In Fig. 17.9, the basic structures of Thin-Film Transistor Liquid Crystal Display (TFT-LCD), Organic Light-Emitting Diode (OLED), and MicroLED are compared.

Quantum Dot Light-Emitting Diode Quantum Dot Light-Emitting Diode (QLED) is an LED technology using Quantum Dots (QDs) as fluorescent emitters. Quantum dots are quasi-zero-dimension nanomaterials, which can be fabricated by solution process. The emission spectra of QDs depend on the crystal size, so OLED lighting has good spectral tunability. In addition, QDs have excellent material properties such as wide color gamut, high saturation, good stability, etc. At present, QLED has become a vital research direction in the display field, e.g., most leading panel manufacturers have launched R&D programs for QLED commercialization. In 1994, Armand P. Alivisatos’ team at UC Berkeley first reported their research on QLED [20]. Since the concept of QLED was proposed, researchers have explored new materials and device structures. As a result, the device performance of QLED

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has been improved rapidly and the performance gap between QLED and OLED has been gradually narrowed. Nowadays, the external quantum efficiency of red QLED has exceeded 20%, its lifetime has exceeded 100,000 h, and its full-width at halfmaximum (FWHM) is less than 30 nm. The device performance of green or blue QLED is very close to or even exceeds that of phosphorescent OLED. In 2011, Samsung Electronics made a prototype of a 4-inch full-color active-matrix QLED (AMQLED) display using organic and inorganic layers as electron and hole transport layers of the QLED, respectively. Not long after that, QD Vision (merged with Samsung in 2016) also released a 4-inch full-color AMQLED panel. AMQLED has advantages in display quality and manufacturing cost, which has attracted extensive attention in the display industry. Currently, there is still a long way for QLED to realize its commercialization and some important technical problems need to be further addressed and improved, such as efficiency of blue light, device stability, cadmium-free QDs, fabrication process, and panel development [21, 22]. QLED is one of the self-emissive devices. Its device configuration and operating mechanism are not very different from OLED. Direct charge injection is the core operation mechanism of QLED. As shown in Fig. 17.10, in a typical planar structure, electrons and holes are injected into the emitting layer through electron transporting layer and hole transporting layer, respectively, and then excitons are generated inside of QDs, realizing electroluminescence via radiative recombination. Compared with present mainstream liquid crystal display (LCD) technology, the energy loss during optical conversion is avoided for the electroluminescent QLED device. Meanwhile, the display screen can be made lighter and thinner since QLED is a self-emitting device, which does not require additional backlight unit. Besides, many functional layers used in QLED can be fabricated by solution process, which helps reducing the cost of mass production.

Fig. 17.10 Schematic structure and working mechanism of QLED lighting

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Thin-Film Transistor Thin-film transistor (TFT) is a three-terminal active semiconductor device, which falls into the category of field-effect transistor (FET). The basic structure of a TFT is shown in Fig. 17.11. TFTs can be divided into two types according to their structures, bottom-gate structure, and top-gate structure. The operation states of TFTs are controlled by the gate voltage. The gate voltage regulates the conductivity of the active layer by field effect, to decide the on and off states of the device. The voltage difference between the source and drain electrodes results in a lateral electric field in the active layer, which determines the current in the active layer when the device is turned on. TFT technology has been investigated and developed for decades. As early as 1934, Julius Lilienfeld proposed the concept of field effect device [23]; and the first TFT device was successfully realized in 1962 [24]. TFTs with amorphous silicon (a-Si) as the active layer appeared in 1979. Since then, amorphous-silicon (a-Si) TFT has been the mainstream technology of TFT-LCD displays. Polysilicon TFT appeared in 1980s [25], but it was not until the maturity of low-temperature polySi (LTPS) technology in the 1990s that realizing poly-Si TFT panels on glass substrates. After 2000, the development of AMOLED displays enabled poly-Si TFT technology to be really applied in industry. In 2004, indium-gallium-zinc oxide (InGaZnO, IGZO), an oxide semiconductor material with amorphous structure, was first reported as the active layer of a TFT. The device showed excellent electrical characteristics. After that, metal oxide TFT technology represented by IGZO became a hot research topic. At present, among TFT technologies, a-Si TFT and LTPS TFT have achieved large-scale mass production, while a small number of products based on IGZO TFT backplane technology are also available in the market. In general, with the continuous development of display technology and applications, the traditional a-Si TFT technology can no longer meet the requirements of the nextgeneration advanced displays. Instead, poly-Si TFT and metal oxide TFT technology will gradually be the mainstream TFT technology. One of the main applications for TFTs is to work as the driving and switching devices of active matrix displays, which are the core components in display technology. In addition, TFT technology has promising application prospect in photoelectric detection field. In 2003, ZnO TFT optical detection characteristics were

Fig. 17.11 Schematic diagram of a typical TFT structure

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Fig. 17.12 ZnO TFT photoelectric detector [26]

reported by H. S. Bae et al. from Yonsei University of Korea. The structure schematic of the ZnO TFT is shown in Fig. 17.12 [26]. From Fig. 17.11b, the electrical characteristics of the ZnO TFT are not sensitive to red light illumination, while they are very sensitive to incident light with a wavelength shorter than that of green light. When the photon energy of the incident light is less than the forbidden band width of ZnO, photons will excite the electrically neutral oxygen vacancy in the forbidden band to form photo-generated current. When the photon energy of the incident light is greater than the forbidden band width of ZnO, photons will directly excite electrons from the valence band to the conduction band so as to generate electron-hole pairs, resulting in a larger photo-generated current. Besides, the significant changes of device characteristics under ultraviolet (UV) ray irradiation show the application potential of metal oxide TFTs in detecting UV. Another application of TFTs in photoelectric detection is X-ray detection. The detection of X-rays can be divided into direct detection and indirect detection. For indirect detection, the scintillator material absorbs X-rays and emits visible light, and then hydrogenated amorphous silicon TFT or oxide TFT can convert this optical signal into electrical signal to realize the detection to X-rays.

Laser Diode Laser diode (LD) is a semiconductor diode device that achieves stimulated emission by injection pumping. The direct bandgap semiconductor is used as optical gain medium, which produces optical gain by recombining electrons and holes injected from a pn junction, and then a positive feedback is generated through the resonant cavity within the device, thereby realizing laser emission. In 1962, two US research groups at GE and IBM almost simultaneously [27] developed a gallium arsenide (GaAs) homojunction laser diode which achieved stimulated emission successfully at a temperature of 77 K. In the following decade, the laser diodes based on heterojunctions were also studied systematically [28]. In

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1980s, the emergence of quantum well theory opened a new world for the development of laser diode. The output power of laser diodes based on quantum well structure has been significantly improved. The laser diode plays an irreplaceable role in many fields. In addition, various complicated device structures have been designed to increase the gain of active region and further develop toward the direction of high power. Among them, the stripe structure reduces the threshold current of the device and significantly improves the output power and reliability of the device. In recent decades, with continuous efforts of researchers, laser diodes already have the advantages of small size, high efficiency, and high reliability. The device structure diagram of LD is shown in Fig. 17.13. The photoactive semiconductor material is located between the p-junction and n-junction. Both end surfaces of the photoactive semiconductor material are perpendicular to the pn junction surface, which have a light reflection effect after polishing, thereby forming an optical resonant cavity. The other two less smooth sides can eliminate the laser outside the main direction [29]. The working principle of LD relies on the stimulated emission. In order to make the excited light output from the device, it is necessary to achieve the inversion of carrier number and reach a certain threshold. When the injection current is sufficient, the distribution of carriers will change and even be contrary to the distribution of thermal equilibrium, that is, the number of carriers are reversed. Since a small number of photons generated by spontaneous emission are reflected by end faces of resonant cavity, induced radiation is generated, resulting in positive feedback of frequency selective resonant, and the medium has gain. When the number of carriers are reversed to a certain extent (threshold) and the gain is greater than the loss within the active medium, the pn junction can emit laser with a good spectral line [30]. At present, LDs found wide applications in optical communications industry. LDs are also widely used in scientific testing equipment, such as spectrometer, interferometer, etc. Despite the industrialization of traditional LDs, new materials that can replace III-V groups and the application of LD in emerging fields are still being explored. Therefore, LD is likely to bring more surprises for us in future.

Fig. 17.13 The device structure diagram of LD

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Photomultiplier Tube (PMT) Photomultiplier Tube (PMT), also short named Photomultiplier, can convert ultralow optical signals into electrical signals, and amplify (and multiply) the electrical signals. PMTs play an extremely important role in the field of ultra-low light detection. PMT was invented in 1930s [31] and has evolved with a wide variety of applications. In 1990s, a silicon photomultiplier (SiPM) was invented and widely applied to high energy physics, nuclear medicine, and other fields. The detection principle of PMT is shown in Fig. 17.14, which is based on external photoelectric effect and secondary electron emission theory [31]. Photons generate electrons by excitation at the cathode; these electrons are then accelerated by electric field in vacuum under the applied voltage at the focusing electrode and enter the multiplication tube. These electrons can excite more electrons in the tube with multiple dynode stages; the detected signal is finally amplified and measured at the anode. PMTs can multiply the current produced by incident light by as much as 100 million times or 108 (i.e., 160 dB) in multiple dynode stages and can enable (for example) individual photon to be detected with low incident flux of photons. The internal structure of SiPM is shown in Fig. 17.15. Its basic unit consists of an avalanche photo diode (APD) and a resistor. Many such units are connected in parallel to form a plane array [32]. Under reverse bias, the photon-induced APD produces an avalanche effect and outputs an instantaneous current pulse, which finally superimposes the pulses generated by each basic unit and shows output by a common terminal. Typical gain factor of a SiPM is in the range of 105–107. Fig. 17.14 The schematic of detection principle of vacuum PMT (end-window type)

Fig. 17.15 Schematic of the internal structure of SiPM

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Photomultiplier tubes (PMT) are widely used in many fields, including electronics, astronomy, aviation, space research, medical treatment, metallurgy, and chemical industry. They can detect optical signals in different bands. SiPMs are mainly used in the fields of high energy physics and nuclear medicine. In recent years, SiPMs have been developed rapidly in the field of nuclear medicine and are used to detect ultra-low light. Although PMT has been relatively mature and widely used in various fields, the manufacturing technology of PMT is still evolving as driven by higher measurement accuracy, more complex environment, modularization, integration, etc. Specifically, the optimization of photocathode manufacturing process is critical for improving quantum efficiency for good detection sensitivity. The application of new composite materials in the cathode can expand the detection range of PMT to shorter wavelengths, such as X-rays. Those new techniques with on-going developing of new PMT systems aim at better gain level, dynamic range, and time characteristics. Furthermore, the development of new type of composite device structures combining PMT and SiPM is also promoting the advancement of photomultiplier tubes.

Infrared Devices Infrared (IR) devices can perform certain functions by using characteristics of infrared light, such as IR radiation and IR detection. IR radiator can emit coherent or incoherent IR radiation signal. Coherent IR radiator or so-called IR lasers can produce a very high IR spectral intensity in a small bandwidth, which is expected to be widely used in the fields of space optical communication and optical fiber communication systems, high-sensitivity gas sensor, high-resolution spectra, etc. Thus, the first lead salt IR laser was developed in 1964 [33]. At present, the band coverage of IR lasers made of IV-VI materials, such as PbSe or PbTe ranges 3–30 μm; required to work below 200 K in general for applications in high-resolution spectra. IR lasers made of III-V materials and poly-compounds such as HgCdTe [34] have also appeared in recent years. Relevant researches now are mainly focused on improving the output power and operating temperature of lasers, including improving the working temperature of devices by using strain, quantum well, and superlattice and other energy band structure technologies. In addition, the concept of realizing IR laser through quantum well sub-band transitions was first proposed in 1971, and its light-emitting comes from the electron transitions among the discrete sub-bands on the conduction band (or valence band) energy level in semiconductor heterojunction. Such quantum cascade lasers were presented in 1994. It produces laser transition by using the separation of energy levels in quantum wells, and the active layer of device consists of many quantum wells in cascade, so that a single electron is able to generate multiple photons. At present, quantum cascade lasers have good performance in increased output power level and operating temperature.

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Incoherent IR radiators usually adopt diode structures. When the diode is in forward bias, holes and electrons are injected into p region and n region respectively, and then recombination occurs to generate IR radiation; when the diode is in reverse bias, the carrier concentration of the light-emitting active layer decreases and the blackbody radiation of the device is turned off, thus enabling it to have the characteristics – lower than the background IR radiation. Therefore, such diode structured IR light-emitting device has the capability of simulating a temperature to be lower than or higher than the surrounding environment and can be used as a reference radiation source for calibrating IR thermal imagers. IR detectors obtain the required information by converting the received IR radiation into other physical quantities. This can be traced back to the seventeenth century when Wilhelm Herschel discovered the radiation other than visible red band by using a mercury thermometer. Since then, many detectors [35] and thermometers all were using thermal effect for detection. Thermal detectors have the advantages of working at room temperature and low cost, but they are not sensitive enough and slow in response, thus photon detectors were invented, widely researched and quickly developed. Photon detectors use photoelectric effect, which are very sensitive and have quick response, but required usually to work at low temperature. When using photon detectors, the incident IR radiation is absorbed by the semiconductor material, making its free carrier concentration change, thus the detection is realized by measuring this change. So far, various semiconductor photon detectors have been developed, which realized highly sensitive detection in the whole infrared spectrum range. Among many detector materials, HgCdTe semiconductor is the most performance-excellent material. GaAs/GaAlAs multiquantum well detectors have been developed rapidly in recent years. Due to the adoption of mature GaAs technology, very uniform large arrays can be obtained. At present, IR detectors have been widely used in both industrial and scientific fields, such as remote temperature sensors, spectrometers, and IR imaging systems. Of course, military application is the most important driving force for IR detection technology research. Using IR detection technology can realize long-distance detection and tracking of targets, passive night vision, and visual enhancement in smoke environment. IR detectors have experienced a development process from single-element, multielement, linear array to starring focal plane devices. At present, IR detectors with an array size of more than 1024  1024 have appeared. In addition, two-color or multiband uncooled detectors were also being developed continuously.

Optical Communication Devices Optical communication is a kind of communication way carried by light wave. In comparison with traditional electrical communication, optical communication has a number of advantages such as large throughput, high carrier frequency, and low

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Fig. 17.16 Schematic of optical communication process

transmission loss. The optical communication devices could be classified by their function into several categories: light source, carrier (optical fiber), repeater, etc. Optical communication is realized as shown in Fig. 17.16. Firstly, the optical signal is modulated from input electrical signal by optical transmitter and transferred in optical fiber. The transmission loss in the telecommunication wavelength of the optical fiber normally 1550 nm is quite low; but the accumulated loss by long distance must be considered and the optical repeater is required to amplify the signal during transmission. Here are two kinds of optical repeater such as optical-electricaloptical and direct optical fiber amplifier. Then the optical receiver, including optical detector and amplifier circuit, realizes optical-electrical signal transformation and sends the electrical signal back to the electrical receiver. Optical source is the key of optical communication devices. LED is an incoherent light source with weak intensity and bad monochromaticity, and it is normally used in low speed and short-distance communication system. In comparison, semiconductor lasers can be used in optical communication due to its small size, efficient coupling, and quick response. Fiber is the carrier of optical signal. Fibers should be carefully designed at the specific wavelength, and compatible with other communication devices. With stateof-the-art fiber fabrication technique, novel fibers such as flexible polymer fiber [36] and large bandwidth semiconductor fiber [37] are developed recently. The simplest optical amplifier mechanism is population inversion in two level system of resonant optical pump [38]. The core of erbium-doped fiber amplifier (EDFA) is an erbium-doped optical fiber. When the fiber is pumped with a laser at a wavelength of 980 nm or 1480 nm, an optical gain for EDFA in the 1550 nm region can be produced. Besides the devices mentioned above, there are many auxiliary passive devices in optical communication system, such as coupler, wavelength division multiplexer, optical switch, and modulator. With the rapid development of science and technology, more devices are expected to further improve the capacity of optical communication.

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References 1. Willoughby Smith discovers the photoconductivity of Selenium. http://www.historyofin formation.com/detail.php?entryid¼1349. Accessed 22 Feb 2020 2. J. Michel, J. Liu, L.C. Kimerling, High-performance Ge-on-Si photodetectors. Nat. Photonics 4(8), 527–534 (2010) 3. S.M. Sze, K.K. Ng, Physics of Semiconductor Devices, 3rd edn. (Wiley, Hoboken, 2006) 4. F. Capasso, W.T. Tsang, A.L. Hutchinson, et al., Enhancement of electron impact ionization in a superlattice: a new avalanche photodiode with a large ionization rate ratio. Appl. Phys. Lett. 40(1), 38–40 (1982) 5. M.D. Eisaman, J. Fan, A. Migdall, et al., Invited review article: single-photon sources and detectors. Rev. Sci. Instrum. 82(7), 071101 (2011) 6. M. Ghosh, M. Mondal, A. Acharyya, 4H-SiC avalanche photodiodes as UV sensors: a brief review. J. Electron Devices 15, 1291–1295 (2012) 7. N. Holonyak Jr., S.F. Bevacqua, Coherent (visible) light emission from Ga(As1-xPx) junctions. Appl. Phys. Lett. 1, 82 (1962) 8. K.K. Shih, G.D. Pettit, Properties of GaP green-light-emitting diodes grown by liquid-phase Epitax. J. Appl. Phys. 39(11), 5025–5029 (1968) 9. S. Nakamura, The roles of structural imperfections in InGaN-based blue light-emitting diodes and laser diodes. Science 281, 956–961 (1998) 10. A. Bernanose, M. Comte, P. Vouaux, A new method of emission of light by certain organic compounds. J. Chim. Phys. 50, 64–68 (1953) 11. C.W. Tang, S.A. Van Slyke, Organic electroluminescent diodes. Appl. Phys. Lett. 51, 913–915 (1987) 12. C.W. Tang, S.A. Van Slyke, C.H. Chen, Electroluminescence of doped organic thin films. J. Appl. Phys. 65(9), 3610–3616 (1989) 13. J.H. Burroughes, D.D.C. Bradley, A.R. Brown, et al., Light-emitting diodes based on conjugated polymers. Nature 347(6293), 539–541 (1990) 14. M.A. Baldo, D.F. O’Brien, Y. You, et al., Highly efficient phosphorescent emission from organic electroluminescent devices. Nature 395(6698), 151–154 (1998) 15. AMOLED Info. https://www.oled-info.com/amoled 16. M. Hack, M.S. Weaver, J.J. Brown, et al., Invited paper: AMLCD and AMOLEDs: how do they compare for green energy efficiency? SID Symp. Digest Tech. Pap. 41(1), 894–897 (2012) 17. J. Chung, J. Lee, J. Choi, et al., Transparent AMOLED display based on bottom emission structure. Sid Symp. Digest Tech. Pap. 41(1), 148–151 (2010) 18. K. Takahashi, T. Sato, R., Yamamoto et al.: 13.3-inch 8k4k 664-ppi foldable OLED display using crystalline oxide semiconductor FETs. Sid Symp. Digest Techn. Pap. 46(1), 250–253 (2015) 19. H. Jiang, J. Lin, S. Jin, et al., U.S. Patent, 6410940 (2002) 20. V.L. Colvin, M.C. Schlamp, A.P. Alivisatos, Light-emitting diodes made from cadmium selenide nanocrystals and a semiconducting polymer. Nature 370(6488), 354–357 (1994) 21. G.J. Supran, Y. Shirasaki, K.W. Song, et al., QLEDs for displays and solid-state lighting. MRS Bull. 38(9), 703–711 (2013) 22. Y. Shirasaki, G.J. Supran, M.G. Bawendi, et al., Emergence of colloidal quantum-dot lightemitting technologies. Nature Photon. 7(1), 13–23 (2013) 23. J.E. Lilienfeld, Device for controlling electric current. US Patent 190001 (March 7, 1933) 24. P.K. Weimer, The TFT a new thin-film transistor. Proc. IRE 50(6), 1462–1469 (1962) 25. S.W. Depp, A. Juliana, B.G. Huth, Polysilicon FET devices for large area input/output applications. Int Electron Devices Meet. 8–10, 703–706 (1980) 26. H.S. Bae, M.H. Yoon, J.H. Kim, et al., Photodetecting properties of ZnO-based thin-film transistors. Appl. Phys. Lett. 83(25), 5313–5315 (2003) 27. Laser Diode-History. https://www.liquisearch.com/laser_diode/history. Accessed 22 Feb 2020 28. Semiconductor heterostructures and laser diodes. https://www.nobelprize.org/prizes/physics/ 2000/summary/. Accessed 22 Feb 2020

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29. F. Song, Modern Technology and Application of Optoelectronic Devices (National Defense Industry Press, 2004), p. 405. ISBN: 9787118034714 30. C. Dong. Quality Evaluation of Light Beam from Semiconductor Laser, MSc Thesis (Xidian University, Xi’an, 2011) 31. B.K. Lubsandorzhiev, On the history of photomultiplier tube invention. Nucl. Instr. Methods Phys. Res. A 567(1), 236–238 (2006) 32. S. Piatek, What is an SiPM and how does it work? https://hub.hamamatsu.com/jp/en/technicalnote/how-sipm-works/index.html. Accessed 22 Feb 2020 33. J.F. Butler et al., PbTe diode laser. Appl. Phys. Lett. 5(4), 75–77 (1964) 34. W.D. Lawson, Preparation and properties of HgTe and mixed crystals of HgTe-CdTe. J. Phys. Chem. Solids 9, 325–329 (1959) 35. HgCdTe (MCT) Detectors. http://www.irassociates.com/index.php?page¼hgcdte. Accessed 22 Feb 2020 36. M. Beckers, T. Schlüter, T. Vad, et al., An overview on fabrication methods for polymer optical fibers. Polym. Int. 64(1), 25–36 (2015) 37. A.C. Peacock, N. Healy, Semiconductor optical fibers for infrared applications: a review. Semicond. Sci. Tech. 31(10), 103004 (2016) 38. A. Yariv, Quantum Optics (Cambridge University Press, New York, 1989)

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Yu-Fei Han, Yun-Zhuo Sun, Mingjiang Wang, Qiang Liu, and Ran Tao

Contents Sensors and MEMS Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistance Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductance Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Piezoelectric Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Effect Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pressure Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMS Inertial Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF MEMS Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microfluidics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMS Magnetic Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge-Coupled Device (CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMOS Image Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fingerprint Recognition Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Touch Controller IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bio-MEMS IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

MEMS stands for micro-electro-mechanical system, generally integrated with microsensors, microprocessors, and micromechanical structures. Based on miniaturization technology, MEMS sensors, actuators, and microsystems, such as Y.-F. Han · Y.-Z. Sun · M. Wang (*) Harbin Institute of Technology, Shenzhen, China e-mail: [email protected] Q. Liu Shanghai Institute of Microsystem and Information Technology, Shanghai, China R. Tao Synopsys, Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_18

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pressure sensors, inertial sensors, RF components and modules, micro-optoelectro-mechanical system (MOEMS), image sensors, biochemical and biomedical systems, energy harvesters, have been developed. They are widely used in auto industry, internet of things (IoT), smart phone, health care-related industry, etc. Several MEMS sensors are discussed in this chapter. Their progresses of technology, basic structures, and main applications are briefly described. Keywords

Sensor · Actuator · MEMS · Microsystem · MOEMS

Sensors and MEMS Devices Sensor is a kind of subsystem that is used for detecting surrounding events or measuring physical parameters and converting them into signals, which can be read by other electronic instruments. According to the detected physical parameters, sensors could be classified as pressure sensor, displacement sensor, speed sensor, temperature sensor, flow sensor, gas sensor, etc. Based on the working principles, sensors can be categorized as resistance sensors, capacitance sensors, inductive sensors, pressure-resistance sensors, photoelectric sensors, etc. The development of sensors has lasted for a long time and the first sensor, a thermocouple, was invented by German physicist Thomas J. Seebeck in 1821 [1]. In recent years, sensors are widely adopted in industry to enhance the production efficiency. For example, in manufacturing processes, key parameters such as temperature, pressure, liquid level, and flow rate are continuously monitored by sensors, which help to control various production status in real-time through the central control room. This application significantly promotes the development of sensors. Meanwhile, driven by the development of semiconductor technology and industry, sensing technologies are also continuously updated, with new types of sensors such as pn-junction temperature sensor, integrated temperature sensor, and semiconductor-based thermocouple sensor, infrared sensor, microwave sensor, acoustic sensor emerging. Nowadays, various kinds of sensors are widely adopted in industry, environment protection, ocean exploration, bioengineering, medical diagnosis, etc. MEMS (Micro-Electrical-Mechanical Systems, or micro electrical mechanical systems) are kind of micro device or system that generally integrated with microsensors, microactuators, and micromechanical structures. In 1960s, Bell Labs and Honeywell research center had developed the first silicon-diaphragm pressure sensor and strain gauge [2]. In 1979, Angell and Roylance developed piezoresistive microaccelerometers. In 1993, Analog Devices developed the first fully integrated silicon microaccelerometer using surface micromachining technology. MEMS has combined the advantages of electrical systems in collecting data and processing and the superiority of mechanical system in operating and controlling [3]. Through

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miniaturization technology, several novel components or systems with special functions were developed, which is based on various subjects including microelectronics, material science, mechanics, and chemistry. When considering the specific applications, MEMS devices can be further grouped as sensing MEMS, biology MEMS, optical MEMS, and RF (radio frequency) MEMS. There are various MEMS manufacturing techniques, including the traditional photolithography, etching, thin film depositing, micromachining of both silicon and other materials, precision machining, etc. Compared with traditional sensors, MEMS (systems or devices) have the characteristics of miniaturization, high integrated density, and easy to be mass-produced. Common MEMS devices include microphone, accelerometer, gyroscope, magnetic sensor, bulk acoustic wave (BAW) filter, pressure sensor, fingerprint sensor, distance sensor, circumstance optical sensor, etc. Each MEMS device is an independent small system. The main application fields of MEMS are shown in Fig. 18.1; and the main application scope of MEMS actuators is displayed in Fig. 18.2. At present, MEMS sensors are widely used in auto industry, especially in the ADAS (advanced driver-assistance systems). To realize intelligent driving assistance through processing the information collected by various sensors, ADAS combines different sensing technologies with various sensors such as camera, radar, laser, and ultrasonic to detect light, heat, pressure, etc.

Fig. 18.1 Main application fields of MEMS sensors

Fig. 18.2 Main application fields of MEMS actuators

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Resistance Sensor Resistive sensors convert physical nonelectrical change into a corresponding resistance change and recorded by the detection circuit. Resistive sensors for temperature detection are also referred to as temperature sensors (see Sect. “Temperature Sensor”). Resistive sensors include potentiometer sensor, gas-sensitive and humidity-sensitive sensors, and resistance strain sensor. (1) A potentiometer sensor is a sensor that converts mechanical displacement into corresponding resistance and voltage changes. (2) Gas-sensitive and humidity-sensitive resistance sensors [4] are sensors that use materials sensitive to small content of gases or water from humidity and convert into resistance and voltage changes. (3) The resistance strain sensor commonly applies a force to deform the materials such as a wire, a foil or a semiconductor and thereby generates a resistance change, and then detects and outputs in the form of voltages or currents. For example, a circular cross section of wire with an initial resistance value R ¼ ρ  ðL=AÞ where ρ is the resistivity of the wire, L the wire length, and A the cross-sectional area. When the wire is stretched by the force F, the length of the wire changes, and its area and resistivity change accordingly. The relative change rate of the resistance value is as follows: ΔR ¼ K0 e R where, K0 is the sensitivity coefficient of a single wire; ε is the axial relative strain which is equal to ΔL/L. When ΔR/R is measured and K0 is known, the strain value ε of the wire can be obtained. The resistance strain sensor is based on wide variety of materials. For example, weighing scale and resistive touch screen generally use Indium Tin Oxides (ITO) materials, which have weak conductivity, good light transmittance, and transparency. Resistive touch screens currently have four-wire, five-wire, eight-wire, etc., but the reliability of such resistive touch screens is not high. Long-term pressing can cause deformation of the upper layer of ITO, causing damage to the device and affecting the lifetime of the whole machine. Resistance sensors have been long in development time and wide range of applications [5, 6]. At present, combined with MEMS technology, resistance sensors will continue to play an important role in fields such as power electronics, rail transit, medical education, and military.

Capacitance Sensor Capacitance sensor is a kind of sensor that measures the change of physical parameters through the change of dielectric capacitance [7, 8]. The core portion of the capacitance sensor includes two electrodes, an insulator, and a substrate. The relationship between capacitance of the sensor and other parameters is as follows:

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C¼

eSb er e0 Sb ¼ δ δ

where C is the capacitance, ε denotes the dielectric constant of the dielectric material between plates, Sb is the area covered by the upper and lower plates corresponding to each other, δ is the average distance between the plates, the ε0 is the dielectric constant of vacuum, and the εr is the relative dielectric constant. When the dielectric medium is air, we have ε ¼ 1. There are three types of capacitance sensors, namely, capacitive sensor with variable pole distance, variable area, and variable dielectric. (1) The capacitance sensor with variable pole distance is obtained by measuring the capacitance due to the variation of the length between the two capacitive plates. Variable pole capacitance sensors measure subtle movements and some changes in length caused by stress or vibration. When such sensors are used to measure amplitude, distance, and metal surfaces, unilateral capacitive sensors are usually used. (2) The area-variation capacitance sensor exploits the area variation between two plates to obtain the measurement results. The area-variation capacitance sensor is usually used to measure angular displacement and certain linear displacement. Compared with the dielectric-variation capacitance sensor, this type of sensor has a larger measurement range. (3) Dielectric-variation capacitance sensor uses the permittivity change of dielectric material between two plates. Dielectric-variation capacitance sensors are often used to measure material level and many dielectric characteristics. Capacitance sensor can be used to measure the amount of water, pressure, sound intensity, angle, liquid level, density, vibration, displacement, thickness and humidity, and other physical parameters. Therefore, it is very suitable to measure the rotation precision for precise shafts, high-frequency vibration, and amplitude of a series of mechanical quantities. In recent years, capacitance sensors are used in capacitive touch screen as well as in fingerprint recognition products. Capacitive touch screen includes surface touch screen and projection touch screen. The surface touch screen uses single-point control, while the projection touch screen uses multipoint control. For the surface capacitive touch screen, when the x direction is electrified and the y direction is not, an electric field is formed along the x direction and a potential change is formed along the x direction. The x coordinate corresponds to the potential. The coordinate information of this potential point can be calculated by detecting the current change corresponding to this potential point. At present, projective multipoint touch screen is generally improved by interpolation algorithm. MEMS-based sensor is an important research field of current sensors. It is compatible with IC process, integrating the sensitive micromechanical sensor chip and the corresponding interface circuit on the same silicon wafer. To use the characteristics of IC manufacturing, it can be mass manufactured to reduce the cost. Also, it has good repeatability and consistency, high sensitivity, and resolution. MEMS capacitance sensor combines the advantages of capacitance sensor and MEMS sensor. With the gradual improvement of MEMS technology level, the sensor capacitance becomes smaller and smaller, and the change of sensor capacitance caused by external physical parameter is even smaller. MEMS capacitance

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sensors, and the pressure, inertia, and other kinds of MEMS sensors based on MEMS capacitance changes have become hot topics in the field of sensors. With the development of material technology, and semiconductor technologies, the category of capacitance sensors are increasing, and their applications become wider.

Inductance Sensor Inductance sensors are based on the principle of self-inductance. The measured change of self-inductance is converted to an electronic output signal of a measurement circuit [9]. The coil self-inductance L of inductive sensor is defined as L¼

N2 Rm

where N is the number of turns of the coil; Rm is the total reluctance of magnetic circuit. Since the air gap thickness δ is small, it can be assumed that the air gap magnetic field distribution is uniform, so the total magnetic resistance is Rm ¼

li 2δ þ ui Si u0 S

where li is the length of the magnetizer; Si is the cross-sectional area of each segment of the magnetizer; δ is the thickness of the air gap; ui is the permeability of the magnetizer; u0 is the vacuum permeability; S is the air gap cross-sectional area. Substituting Rm into the first formula, one get L ¼ N2 =

li 2δ þ ui S i u0 S

After the basic material and the structure of the sensor are confirmed, when δ is unchanged, and S is the only external variable, this type of sensor is called variablesection inductive sensor. When S remains unchanged, this type of sensor is called a variable-air gap inductive sensor. When a cylindrical armature is added into the coil to change the amount of self-inductance, this type of sensor is called a spiral tube inductive sensor. The air gap type inductive sensors have the advantages of high sensitivity and good linearity, and can be used in most environments. The cross-section type uses the change of the magnetic cross-sectional area to produce a self-inductance change, which has the advantage of linearity, though some nonlinear errors may occur in actual use. The solenoid type inductive sensor is an air gap sensor. The shape and size of the coil bobbin are required to be constant during manufacture, and the coil is wound uniformly.

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The conductance sensor products [10] have the advantages of simple structure, strong anti-interference ability, less strict requirement on working environment, good reliability and stability, etc., so they are widely used in various fields such as semiconductor IC production, automated machinery production, and product quality inspection.

Piezoelectric Sensor Piezoelectric sensor is a kind of self-powered sensor made of piezoelectric materials [11, 12]. Piezoelectric effect refers to the phenomenon of electric charge on the surface of piezoelectric material when it is subjected to external force. According to the characteristics of piezoelectric materials, there are positive or inverse piezoelectric effects. There are many kinds of piezoelectric materials. Quartz crystal and piezoelectric ceramics are widely used in industry. Dextrorotatory quartz crystal structure is shown in Fig. 18.3. It has the strongest piezoelectric effect on the edge plane perpendicular to the X-axis, which is called the electrical axis. Under the conditions with electric field, the mechanical deformation in the y-axis direction perpendicular to the opposite side of the hexagon is the largest, so the y-axis is called the mechanical axis. However, there is no piezoelectric effect in the z-axis direction, which is called the neutral axis. The piezoelectric equation represents the relationship between stress electrical displacement and strain tensor of electric field strength in a piezoelectric body. The electric charge generated on the corresponding surface of the piezoelectric component, when it is subjected to a certain external force F in a certain direction. The electric charge Q can be expressed as follows: Q¼Fd where d is the piezoelectric constant. Fig. 18.3 Dextrorotatory quartz crystal

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Piezoelectric sensors are widely used in automotive engines, automatic ignition devices for gas stoves, piezoelectric loudspeakers, and many kinds of ultrasonic generators. Gravity sensors have become an important part of the smartphones. Gravity sensor attaches a weight to a piezoelectric piece and calculates the horizontal direction by measuring the voltage generated in both directions. Gravity sensors can be used to achieve automatically switching the phone between landscape and vertical screens. In some game devices such as balanced ball, racing, etc., gravity sensors are used for interactive control. The main disadvantage of piezoelectric sensor is the high output impedance, which requires the use of low capacitance and low-noise cables, and no static output [13]. Due to its reliability, sensitivity, high signal-to-noise ratio, and characteristics of spontaneous electricity and reversibility, piezoelectric sensors have been expanded their applications in the market.

Temperature Sensor Temperature sensor, also known as thermal sensor, is a sensor device that converts the measured temperature-related physical parameter into a charge or voltage variation. There are many physical properties related to temperature, which can be selected according to the different temperature-sensitive areas [14]. Temperature sensors used on the market are mainly thermometers, resistance sensors, thermocouples, thermistors (or thermal resistors), etc. When the temperature of the measured object is relatively high, the noncontact thermal sensor is generally used for measurement; when temperature of the measured object is relatively low, it is generally measured using thermocouples or semiconductor and metal resistance sensors; when it is near normal temperature, and the measurement is generally performed using a semiconductor thermal sensor or thermistor [15]. Contemporary advanced temperature sensors can be designed with SoC, where the microcontroller unit (MCU) sends commands to the sensor through the data bus (I2C) for temperature sensing. The measured data (ambient temperature, target temperature, etc.) by the infrared temperature sensor are stored in RAM. To obtain a high-precision temperature signal (output voltage), the temperature sensor circuit is usually implemented by a base-emitter voltage multiplying circuit including constant current sources, bipolar transistors, and resistors. The base current error compensation circuit can also compensate the base current of the bipolar transistor flowing through the resistor. Temperature sensors are widely used in air conditioner systems, refrigerators, rice cookers, servers, PCs, mobile phones, and other products. In the past a few years, with the rapid development of microelectronics and MEMS technology, MEMS sensors have demonstrated advantages of smaller size, lighter weight, and smaller inherent heat capacity compared with traditional sensors. MEMS temperature sensors are gradually replacing traditional temperature sensors. In recent years, sensor technology has rapidly advanced toward high reliability, high precision, high resolution, high security, intelligence, and contactless.

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Hall Effect Sensor Hall Effect sensor refers to sensor devices that convert the change of nonelectrical and nonmagnetic physical parameters into the change of electrical parameter by the Hall Effect and then collects, amplifies, and outputs the change of electrical parameter. Hall Effect was discovered by A. H. Hall in 1879 [16], the working principle of Hall Effect sensor [17] is shown in Fig. 18.4a. Hall Effect voltage, UH, can be expressed as follows: U H ¼ RH IB=d, where RH is the Hall coefficient whose value is determined by the wafer material, B is magnetic induction intensity gauss, G (1G ¼ 1  104 T), d is the thickness of Hall module, and I is the current passing through the wafer, which is called excitation current. The basic structure diagram of Hall Effect sensor is shown in Fig. 18.4b. A pair of electrodes is installed on each side of the semiconductor substrate. Along the direction of current, so called excitation electrodes A and B are connected to excitation voltage to generate the excitation current. Electrons or holes of excitation current move and then deflect under the influence of Lorentz force. The electric voltmeter connects electrodes C and D to measure the Hall voltage generated inside the semiconductor, so it is called Hall electrode. Hall Effect sensor can be used to measure pressure, strain, mechanical vibrations, acceleration, microdisplacement, magnetic induction intensity, active power, reactive power, phase, current, voltage, surface roughness, rotating speed, and other parameters. Hall Effect sensors are widely used in, such as multiplier, divider, and square calculator, gyrator composed of modulation and demodulation, triangular wave generator, contactless sender, synchronous transmission devices, etc. Hall sensors have been widely used in market, e.g., the smart clamshell phones. When the cover is closed, the phone goes into hibernation; as the cover is opened, the phone is awakened with no buttons pressed during the process.

Fig. 18.4 The Hall sensor: its working principle (a) and the basic structure diagram (b)

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Besides, Hall Effect sensor has many advantages, such as long lifetime and small body weight, can realize brushless electronic and noiseless. It is expected that soon, it will be further used in variety of applications such as automotive electronics and electronic communications.

Pressure Sensor Pressure sensor is a device, module, or subsystem for measuring pressure force and transforming it into electrical signal. In 1938, E. E. Simmons of the California Institute of Technology designed a paper-based bonded wire resistance strain gauge. In 1969, Hans W. Keller designed, and mass-produced semiconductor pressure sensors based on silicon using IC technology [18]. Pressure sensor is classified into three types according to different reference pressure: gauge pressure sensor, absolute pressure sensor and differential pressure sensor. Gauge pressure sensor can measure the reference atmospheric pressure, absolute Pressure sensor is for measuring the reference vacuum pressure, and differential pressure sensor is used to detect the difference of pressure at the two measuring ends. According to the switching speed when measuring the pressure signal, pressure sensor is sorted as static pressure sensor and dynamic pressure sensor. Static pressure sensor is suitable for static and quasi-static pressure measurements with varying frequency within tens of Hz. Dynamic pressure sensor is appropriate for measuring pressure signal with rapid variations. The general operating parameters of dynamic pressure sensor are frequency response characteristics, intrinsic frequency, and response time. According to different working mechanisms, dynamic pressure sensors are mainly classified as two types: Si piezoresistive sensor and piezoelectric sensor. In the same way, (quasi) static pressure sensors are sorted as Si piezoresistive sensor, piezoelectric sensor, Si capacitance sensor, metal capacitance sensor, ceramic capacitance sensor, Si resonant sensor, quartz crystal resonant sensor, sputtered thin film strain sensor, etc. According to the operating ambient temperature, pressure sensors are divided as high-temperature pressure sensors and normal temperature pressure sensors. Hightemperature pressure sensors generally operated at temperatures above 130  C. High-temperature pressure sensors are further divided as sputtered thin film high-temperature pressure sensor, SOI high-temperature pressure sensor [19], Si-sapphire-based high-temperature pressure sensor, and piezoelectric hightemperature pressure sensor. Piezoelectric high-temperature pressure sensor can operate up to 175  C. SOI high-temperature pressure sensor and Si-sapphire-based high-temperature pressure sensor can operate at temperatures above 350  C [20]. According to the operating mechanism, pressure sensors are sorted as capacitive pressure sensor, piezoresistive pressure sensor, and resonant pressure sensor. Among them, Si capacitance pressure sensor, Si piezoresistive pressure sensor, and Si resonant pressure sensor are with very low-test error around 0.01% [21]. Si resonant pressure sensor can convert the variation of pressure into a resonant frequency shift

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of the Si resonant beam, and this shift corresponds to the varied pressure value. Si resonant pressure has two working modes, including electrostatic excitation and electromagnetic excitation. Si resonant pressure sensor is appropriate for highaccuracy pressure sensing. At present, Si semiconductor pressure sensor is widely adopted for its significant advantages, such as high performance, low cost, and wide applications. The weight of this sensor can be even less than 0.01 g, and its measuring range varies from several thousand Pa to several hundreds of MPa. The main development direction of pressure sensors is to be with high accuracy, high-temperature resistance, and high integrated density. The monolithic integration technology of pressure sensors has been developed for more than 20 years. However, the present products are still focused on low-range, medium-precision applications, mainly adopted by automotive industry and civilian use. There is still lack of fundamental breakthrough in high-temperature applications.

MEMS Inertial Sensor MEMS inertial sensor is fabricated with MEMS technology, and it can independently measure the azimuth, attitude, velocity, acceleration, and other motion parameters of the vehicle in a reference coordinate. MEMS inertial sensor mainly includes MEMS accelerometers and MEMS gyros (gyroscope). According to the operating mechanism, MEMS accelerometers are sorted as piezoresistive type, capacitive type, resonant type, tunnel-current type, and thermal-convection type. MEMS gyros are usually Coriolis vibrating gyros (CVGs). They are divided as vibration type and rotation type according to different excitation modes. The vibration exciting modes mainly include hemisphere type, tuning-fork type, and frame type. The gyro rotation is mainly excited by a dynamic tuning gyro. Piezoresistive accelerometer is the first MEMS inertial device. In 1962, a piezoresistive accelerometer adopted with butterfly-shaped semiconductor strain gauge was produced to detect vibration and shock. In 1968, the 2266 series accelerometer with a diffused semiconductor strain gauge was developed, whose detecting range reached 2  104 g (g is gravitational acceleration, 1 g ¼ 9.8 m/s2). In April 1974, the 7070 series accelerometer was emerged with a range of 1  105 g, where the key component piezoresistive strain gauge was fabricated with a bulk silicon release process. In 1983, the 7270A series accelerometer was produced with a detecting range of 2  105 g and a resonant frequency of 1.2 MHz [22]. Modern capacitive accelerometers are mainly produced with surface silicon processes and simultaneously integrated with large-scale electronic circuits. ADI’s ADXL50 is the first monolithic integrated capacitive MEMS accelerometer that widely used in automotive airbags [23]. In theory, resonant accelerometer has a better measurement accuracy and is convenient for digital signal processing. In 2005, the stability and repeatability of resonant accelerometer reached a resolution of below 1  106 g, and it had been installed in the inertial navigation of strategic missiles.

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Fig. 18.5 The hinge structure of the piezoresistive accelerometer [24]

The hinge structure of the piezoresistive accelerometer is shown in Fig. 18.5. In 1960s, miniaturized gyros had emerged, such as vibrating spring gyros, tuned tuning fork gyros, and dynamic gyros, and they were emerged in MEMS fields in 1990s. In 1990, tuning fork MEMS gyroscope with piezoelectric vibration component and piezoresistive detecting function was realized. In 1994, vibrating frame gyro with a glass-silicon structure was developed. In 1997, all-silicon vibrating disc gyroscope was developed. In 2008, MEMS rotating gyros appeared. In 2014, the bias stability of silicon-based vibrating disc resonator gyroscope reached 0.1 deg/h [25], which could be applied to inertial navigation.

RF MEMS Switch Radio frequency (RF) microelectromechanical system switch is one of the most important devices in the field of MEMS. The first RF MEMS switch is proposed and manufactured by Peterson of IBM R&D Center in 1979 [26]. The switching performances of the first RF MEMS switch were poor as fabrication technology was immature at that time. With the continuous improvement of the MEMS process, RF MEMS switch has been developed rapidly. Figure 18.6 shows the basic structure of an RF MEMS switch. By applying a voltage between the driving electrode and the fixed electrode, electrostatic force will be generated between these two electrodes. The generated electrostatic force drives the driving electrode moving toward the fixed electrode until the movable contact-point in the middle of the silicon beam contacts the fixed contact point, which means turning-on of the switch and conducting of the signal line. If the voltage is removed, the electrostatic attraction disappears, and the movable contact points are automatically separated from the

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Fig. 18.6 Basic structure of RF MEMS switch

fixed contact points of the signal lines by the elastic restoring force of the silicon beam, thus the signal lines are disconnected. RF MEMS switches have better switching performance, compared with the conventional switches. Many new functional modules can be formed by integrating with various components and greatly expand the applications of RF MEMS switches [27]. RF MEMS switch has the advantages of low-power consumption, high isolation, low insertion loss, high linearity and small size in wireless communication system, national defense radar system, automobile radar, satellite communication system, etc. For the commercialization of RF MEMS switches, the practical issues include low reliability, high cost, difficult packaging, and high operating voltage. In 2009, Omron of Japan launched a high-reliability RF-MEMS dual-bit selection switch [28] with market success. With the progress of technology, other RF MEMS products will gradually become mature. Currently, many enterprises in the United States, France, Germany, Korea, and China, are actively promoting the research and development of RF MEMS switch.

Microfluidics Microfluidics refers to the technology of measuring, manipulating or operating fluid with feature size of submillimeter or even micrometer in microchannels. The system can process or manipulate small amounts of fluidics (109 to 1018 L ) [29]. The microfluidics technology has been generally considered to be derived from capillary electrophoresis and fluid injection analysis in analytical chemistry. In 1990, A. Manz and H. M. Widmer of the Central Institute of Analytical Research in Basel, Switzerland, for the first time proposed the concept of utilizing micromachining methods to achieve miniaturized total chemical analysis system in the journal “Sensors and Actuators, Chemistry” [30], which is recognized as the naissance of microfluidics.

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Compared with previous analysis systems, the main problem caused by the reduction in size of microfluidics is that the domination is either surface characteristics or diffusion characteristics [31]. When the surface characteristics dominate, the microfluidics chip can increase the target molecular capture amount on the wall thanks to the large surface area, thereby improving the detection sensitivity or reaction efficiency. At the same time, the large surface area also makes the nonspecific adsorption of the microfluidics serious, and even leads to corresponding reaction failure, so functional modification or passivation of the surface becomes a key to microfluidics. When the diffusion characteristics dominate, the microfluidics chip can realize the separation of substances based on diffusion principle through careful geometry design. At the same time, since the material exchange at the microscale can only rely on diffusion, it lacks efficient mass transport methods. Therefore, microfluidics has not yet fully matured today mainly due to main challenges of high-efficiency on-chip mixing method. The structure of a typical microfluidics chip is shown in Fig. 18.7. The basic functional units include the inlet (connecting external reaction liquid or sample), the microchannel (fluid transport structure, space for function realization), the functional structure (providing function, such as temperature control), and the outlet (connecting external reservoir or waste liquid pool). In addition, to achieve multifunctional integration, some microfluidics systems need to integrate micropumps, microvalves, and other functional units with the microchannels. In recent years, many microfluidics technologies based on surface-driven and centrifugal-driven have great potential applications [32] because of their simple and easy implementation of liquid-driven. The most mature and commercially successful microfluidics chips include the MEMS inkjet printer and the MEMS microfluidic pump. Fig. 18.7 Structure of a typical microfluidic chip (continuous flow polymerase chain reaction chip) [2]

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MEMS Magnetic Sensor Magnetic Field Sensor, also known as Magnetometer, is a sensor that measures the magnetic induction and direction of the environment. At present, the main MEMS magnetometers [33] include magnetoresistive magnetometers, fluxgate magnetometers, Hall Effect magnetometers, tunnel-effect magnetometers, resonant Lorentz magnetometers, etc. 1. Fluxgate magnetometer includes an iron core that made of a soft magnetic material with high magnetic permeability. In the case of simultaneous alternating and constant magnetic fields, the voltage induced by the detecting coil wound on the iron core contains even harmonic components, especially the second harmonic; the harmonic voltage is positively correlated with the magnetic field strength. Therefore, the magnetic field strength can be detected by measuring the harmonic voltage of the detection coil. 2. Hall Effect magnetometers are based on the Hall Effect. A conductor is placed in a magnetic field and energized, the magnetic field produces a lateral force on the electrons in the conductor, thereby creating a voltage difference across the conductor, and measuring the voltage difference yields the strength of the magnetic field [34]. The Hall Effect magnetometer is characterized as small probe size, high sensitivity, and good linearity. 3. Magnetoresistive magnetometers are available in both semiconductor magnetoresistive and thin film magnetoresistive types. A semiconductor magnetoresistive magnetometer is a sensor that measures the strength and direction of a magnetic field using materials such as InSb or GaAs, it is based on the fact that the semiconductor material changes its resistance affected by a magnetic field. The thin film magnetoresistive magnetometer is made of NiFe or NiCo alloy, and it works based on the anisotropic magnetoresistance effect of the thin film magnetoresistive material. 4. Tunnel-effect magnetometer has a deep cavity structure with a thin film and a silicon tip (Si-tip). The electrostatic force is used to pull the film to a distance of 1 nm from the Si-tip, and a microampere tunneling current is generated between the film and the Si-tip under the bias voltage. The film has a coil structure in which an alternating current is applied. Under the action of the magnetic field, a Lorentz force is generated in the coil to cause the film to vibrate up and down. When the distance between the film and the Si-tip changes with the vibration of the film, the value of the tunneling current will also change, and the intensity of the external magnetic field can be obtained by measuring the change of tunneling current. 5. Resonant Lorentz force magnetometer has an excitation coil on its structure. The excitation coil that is connected to the alternating current is subjected to an alternating Lorentz force in the magnetic field so that its structure results in a resonant state, and the strength of the external magnetic field can be obtained

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indirectly by measuring the magnitude of vibration amplitude of the structure. When the current frequency is consistent with the natural oscillation frequency of the torsion beam, the system will resonate, at which point the output amplitude reaches a maximum and is proportional to the strength of the external magnetic field. Most Lorentz force magnetometers measure amplitude by piezoresistive or capacitive sensing methods. Since the MEMS resonant structure has a high Q value, hence the sensitivity of the magnetometer is high [35]. Moreover, such magnetometers do not require magnetic materials, and the processing process is relatively simple, and the yield is relatively high. In general, magnetic field detection is one of the important directions in the field of MEMS sensing. In recent years, the related MEMS magnetometer technology has been promoted with the emergence and development of new concepts such as atomic magnetometers. At the same time, MEMS micromachining methods have greatly reduced the size of magnetometers and reduced the cost, and this leads to broader applications.

Infrared Sensor Infrared (IR) sensor is a sensor system for IR radiation detection, also known as IR detector. According to the operating temperature, the IR detectors are divided into cooled and uncooled types; according to theory of operation, the IR detectors are divided into photoelectric effect and thermal effect types. Cooled IR detectors are usually image based on photoelectric effect. Most used photodiode materials include HgCdTe, InSb, InGaAs, and InP quantum well (InPQW). Cooled IR detectors usually work in Dewar for higher signal-to-noise ratio and resolution. However, cooled IR image systems are complex, which have higher power consumption, larger volume, and mass, and more expensive. Uncooled IR detectors [36] are usually image based on thermal effect, which means the detector temperature changes with heating due to IR radiation. The typical uncooled infrared detectors include pyroelectric, microbolometer, thermal diode, thermopile, etc. The uncooled IR detector can work at room temperature, with the characteristics of low cost, low-power consumption, small volume, small mass, and fast start. With the development of technology, the performance of uncooled IR detector has gradually caught up with that of cooled IR detector. Nowadays, uncooled IR detectors are widely used in thermal image sight, missile guidance, vehicle vision system, security monitoring, fire rescue, electric power monitoring, forest fire monitoring, and other fields. Resistive microbolometer is the mainstream technology of uncooled IR detectors. According to the materials used, the resistive microbolometer can be divided into vanadium oxide (VOX), amorphous silicon (a-Si), and other types. Honeywell in USA was the first company to successfully develop a microbolometer IR detector based on vanadium oxide. CEA-LETI in France was the first to successfully develop

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a microbolometer IR detector based on a-Si, which is currently produced by ULIS and Lynred in France [37]. The readout circuit of uncooled IR detector is very important. The readout circuit array is connected to the sensor array; the analog signal according to IR radiation is selected, amplified, corrected, and converted to the digital signal. Finally, the desired thermal image can be achieved through the digital signal process. Advanced technologies such as TEC-less analog front-end, on-chip nonuniformity correction, and digital process can further improve detector performance; reduce system’s power consumption and cost. Nowadays, the minimum noise equivalent temperature difference (NETD) can be achieved as low as 20 mK, and the pixel pitch can be as small as 12 μm. The array size is also expanded to 1280  1024, and the maximum frame frequency can be up to 100 Hz. In 2015, Raytheon [38] demonstrated a thermal imaging camera with 12 μm pitch of 206  156 pixels uncooled IR detector, which can be used in mobile terminals such as iPhone. With the further reduction in size and cost, infrared thermal imaging technology is expected to be widely used in automotive electronics, drones, mobile phones, and other mobile intelligent terminals.

Charge-Coupled Device (CCD) Charge-Coupled Device (CCD) is a semiconductor device arranged in sequence by the basic units of MOS capacitors. When a voltage is applied to a MOS capacitor unit, the charge in the capacitor unit can be transferred to the neighboring unit sequentially. Image sensor is a successful application of CCD. The working principle of CCD is that, firstly the charge generated by the photoelectric effect is collected in a region called the photosensitive region, and then it is transferred to an area where the charge can be read and processed, and finally the signal is output through the peripheral circuit for subsequent transmission and processing [39]. The CCD was invented in 1969 by Willard S. Boyle and George E. Smith of Bell Labs [40]. Since 1980s, Sony gradually became the largest supplier of CCD. Electron Multiplying CCD (EMCCD) adds a gain register between the read register and the output amplifier, which causes the electron to “impact ionization effect” during the transfer process, generating new electrons and realizing electron multiplication. The signal-to-noise ratio of EMCCD has been greatly improved, especially suitable for low-light conditions such as single-photon detection, live cell microscopic observation, and fluorescence for imaging in cell [41]. Early CCD operated in frontal illumination mode; that the incident light came from the front, through the polysilicon (poly-Si) electrodes and dielectric layers and was absorbed inside of the semiconductor material in the chip to produce electron-hole pairs. Since the incident photons pass through the poly-Si which strongly absorbs the short-wavelength light, it will result in a loss of incident light intensity and then lead to a decrease in the quantum efficiency of the CCD. With the improved back-illuminated CCD, light enters from the back side of the chip instead of passing through the poly-Si electrode, thereby improving the

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quantum efficiency of the CCD. Back-illuminated CCD can achieve target imaging under low-light conditions and has a wide range of applications in aerospace fields such as target detection, positioning and navigation, resource exploration, and environmental monitoring [42]. Time Delay Integration (TDI) CCD is an array structure that works in a line scan. It supports high response sensitivity for light, high signal-to-noise ratio, erasable image shift, and selectable TDI levels to control exposure time. It is the core device for image acquisition and target recognition of space borne and airborne remote sensing cameras [43]. At present, most of the world’s remote sensing cameras in the aerospace industry use TDI CCDs. Compared with vacuum camera tubes, pyroelectric tubes, and silicon camera tubes, CCD has the advantages of small size, small weight, low-power consumption, long working lifetime, high sensitivity, wide spectral response range, large dynamic range, and global shutter imaging. CCD was a revolutionary breakthrough in the field of image sensors [43] and it was once widely used in civil markets such as security surveillance and digital cameras but gradually replaced by the newer technology of CMOS Image Sensor (CIS) technology. Currently, CCD is still widely used in certain special applications such as military, aerospace, and astronomical observation.

CMOS Image Sensor CMOS image sensor (CIS) comprises of photodiodes and MOSFET amplifiers. In 1968, P. J. Nobel from Plessey created a passive-pixel sensor (PPS) based on MOS device [44]. Began in 1992 with a proto-type CMOS active-pixel sensor (APS), NASA Jet Propulsion Laboratory (JPL) successfully manufactured CMOS APS in 1999 [45], which integrated an amplifier in each pixel unit. Later, JPL spun out a new company, Photobit, which is specialized in commercialization of CIS technology. Structurally, CIS mainly consists of photodetector, photocurrent readout circuit, timing pulse generator, A/D converter, and on-chip digital image processing circuit. CIS has the advantages of low cost and low-power consumption in virtue of its high degree of integration and single power supply. The basic working principle of CIS is depicted in the Fig. 18.8. The pixel cells are arranged in a two-dimensional array in X and Y directions, each of which could be selected by an address decoder in X and Y directions, respectively. The column amplifier magnifies the output signal of each column pixels. Then the magnified signal is sent to A/D converter through the MOSFET switch. After A/D converter, the digital signal is readout by interface circuit. The key parameters for CIS performance evaluation are spectral range, external quantum efficiency (EQE), noise, fill factor, output characteristics and dynamic range, modulation transfer function (MTF), etc. Due to the relatively well accumulation of technology in the field of CCD image sensor, Sony Corp. of Japan developed and commercialized the backside illuminated (BSI) CIS. This is a 3D stacked CIS technology achieved by placing the active-pixel sensor unit on top of the semiconductor silicon layer while all other peripheral

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Fig. 18.8 Basic working principle of a CIS diagram

analog and digital signal processing circuits are placed at the bottom of the silicon layer, interconnected by through silicon via (TSV) technology. The BSI topology greatly improves the photoelectric sensing, signal processing, and overall image sensing of CIS. OmniVision (merged by Ingenic Semiconductor in 2016) also launched BIS CIS products with more than 20 million pixels in corporation of foundry manufacturing at TSMC, HLMC, and XMC. The OmniVision OV6948 is a BSI sensor with 200  200 pixels; that measured 0.575 mm  0.575 mm to be the smallest by Guinness World Record [46]. CIS has been widely used in various mobile and consumer electronic systems, including smart phones and personal computers. Also, it has found wide applications in the fields of security monitoring, industrial electronics, medical electronics, etc.

Fingerprint Recognition Chip The Fingerprint Recognition Chip or sensor is used for fingerprint recognition. The fingerprint identification process includes fingerprint image acquisition, information processing, matching, and judgment of the collected images. Fingerprint recognition technology involves a wide range of disciplines, especially for the feature processing of fingerprint images, which requires the use of mathematical morphology and wavelet analysis and other disciplines [47]. Pattern recognition and machine learning algorithms are normally used for fingerprint image matching and recognition. The fingerprint identification system mainly includes fingerprint sensor and fingerprint recognition algorithm processing module. For applications with special function or large amounts of memory, additional peripheral memory modules are also required. The new fingerprint processing and authentication chip integrates fingerprint recognition accelerator components, as well as RAM or Flash with certain capacity. Fingerprint sensors are usually available in four scanner types: optical, capacitive or CMOS, ultrasonic, and thermal scanner. (1) Optical: The principle of optical fingerprint sensors uses refraction and reflection of light, which is, different optical images produced by the texture of the fingerprint. Therefore, once the fingers are contaminated with dust or water stains, they will exhibit different characteristics

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under the light source. However, using a certified fingerprint and fabricate a fake hand model, it can “deceive” the recognition system. (2) Capacitive: The capacitive fingerprint sensor utilizes the principle of capacitance charge and discharge, which has the ability to detect electric charge changing between the capacitance plates, the changes of charge are recorded and formed into different fingerprint images according to certain rules. For some contaminated fingers, the charge collection of sensors will be affected because of the impurities or water stains on the fingerprint, in these cases, fingers are usually not well recognized. From the user experience, if the finger has water, or the hand is dirty, the device in use cannot be unlocked. (3) Ultrasonic: The ultrasonic fingerprint sensors are based on the principle of medical ultrasound. Those sensors can produce two-dimensional images of fingerprints, and even recognize the 3D features of fingerprints. Acoustic waves are generated by a piezoelectric transducer, and the high-frequency sound waves penetrate the epidermal layer of the skin to image the superficial tissue under the skin. Therefore, the ultrasonic sensor does not have a high requirement for the cleanliness of the fingers and whether the skin of the epidermis is damaged. (4) Thermal: This type of scanner can sense the temperature differences on the contact surface, in between fingerprint ridges and valleys. So far, all fingerprint scanners are susceptible to be fooled by some techniques, such as (a) photographing fingerprints; (b) processing the photographs using special software; and (c) printing fingerprint replicas using a 3D printer. Fingerprint image is the main object in the fingerprint identification process. The main steps of collection and discrimination are as follows: (1) Fingerprint image acquisition. (2) Fingerprint image compression. The fingerprint data collected by the sensor are very large. To reduce the load on the memory, the data need to be compressed. The main methods include JPEG, Wavelet Scalar Quantization (WSQ), and Embedded Zerotree Wavelet (EZW) algorithms. (3) Preprocessing of fingerprint images [48]. The fingerprint image directly obtained by the sensor has a lot of noise, and the preprocessing is very necessary before the feature recognition. (4) Fingerprint area detection. Locate the area to be measured. (5) Fingerprint classification. The main classification method is based on the pattern and texture. (6) Feature extraction. The main concentrated area of the fingerprint characteristics is determined by the coordinates of certain patterns. In the coordinate system, details such as the initial point, the trend, and the position of the last intersection of the line are marked. (7) Fingerprint comparison. The first step is to match roughly and classify according to the pattern; the second step is to match the image accurately based on detailed information; the third step is to judge whether the fingerprint is matched according to the similarity, if the fingerprint is not in the fingerprint library, it will not be authorized. Fingerprint recognition technology is widely used in various fields such as employee attendance system, mobile phone and laptop unlocking system, security payment system. Capacitive fingerprint recognition chip is normally used in mobile phone designing. Meanwhile, traditional optical fingerprint recognition sensors are

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widely used in other occasion like collection fingerprint information for second generation ID card, the fingerprint identification of customs clearance. The main trend of the fingerprint recognition sensor is to improve the recognition rate of the fingerprint and improve the recognition and unlocking speed of the fingerprint at the same time.

Touch Controller IC Touch controller IC refers to the chip that can integrate and complete single-point or multipoint touch technology, which has many characteristics. (1) The traditional touch module contains mechanical buttons; that shorten their lifetime after frequent use. The touch control chip is based on touch technology and works in a touch manner, thus greatly extending the service lifetime; (2) Touch operation interface is smooth and beautiful; (3) The sensitivity of the touch screen is flexible and adjustable, which can be adjusted by changing the value of its built-in reference capacitance; (4) The built-in capacitor has its own unique characteristics, such as heat insulation performance, moisture-proof performance, and so on [1]. It is because of its excellent characteristics that the touch control chip is not affected by temperature, humidity, and other environmental factors. Capacitive touch control chip is the main type of touch control chip [49] at present. When the user touches the chip with fingers or other body part, the effective cross-sectional area or spacing of the capacitor changes slightly, causing the capacitance value to change. There is a built-in reference capacitor in the touch chip. As the chip is touched, the input capacitor changes that leading to the variation of electrical signal. This signal is amplified by the analog amplifier circuit and then output. At present, R&D companies of touch control chips in Europe and the United States, such as Atmel (acquired by Microchip in 2016) [50], Cypress [51], Synaptic [52], etc. are far ahead in technology. These enterprises have accumulated a lot of good technical experiences in the long-term R&D, which effectively reduces the noise of the chip and improves the sensitivity, stability, and resolution of the chip. In the touch controller IC industry, AMOLED products are characterized by accurate positioning and long service lifetime. Touch controller IC is faced with the challenges of precise positioning of touch point, low energy consumption, long lifetime, and other technologies. At present, gesture touch is becoming a new direction of touch controller IC development. The gesture touch controller IC not only needs to accurately locate the coordinate of the touch point, but also needs to accurately identify the gesture and record the swing track of the gesture, which requires the touch chip to transform the data processing ability from one dimension to three dimensions. In the short-term, the application field of touch controller IC will continue to expand in intelligent home, such as intelligent access control, intelligent ventilation system, intelligent safe, etc.

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Bio-MEMS IC The biochip is used in sensing biological information, including macromolecules such as proteins, antibodies, nucleic acids, and the whole cells, etc. The biochip is different from an electronic chip because the surface of electronic chip integrates electronic units while the biochip surface is the antenna array [53]. Currently, there is no classification standard for biochips. In general, there are three types of BioChips: DNA microarray, microfluidic chip, and protein microarray. The general classification includes two approaches. One approach is based on the mode of interaction, and another one is based on the types of biological samples, for example, biochips can be classified as gene chip, protein chip, cell chip, laboratory chip, etc. According to the interaction mode, biochips can be sorted to passive or active. The passive biochip itself contains no power supply and is inactive until the signal is applied. It will only collect signals during the experimental steps with high parallelism and occupies a large proportion in the current biochip market. The basic structure of a passive chip consists of three parts: electronic chip, transducer, and prober. Biological information can be read and recorded through this general architecture. The active biochip highly integrates experimental steps of biological signal analysis and can complete the detection and analysis by one-step reaction. So, the active mode has high efficiency and simple operation [54]. Biochips are mainly used for molecular composition analysis and medical applications. Molecular composition analysis is mainly for detection of various biological macromolecules, such as nucleic acid, protein, and antibody, etc. The most widely application is for the sequencing analysis of DNA (Deoxyribonucleic Acid) and RNA (Ribonucleic Acid) [55]. There are three major molecular composition detection methods including fluorescence disclosure, grid method, and microdeposition method. Fluorescence method reads the information by the energy intensity of fluorescence reaction. The grid method is a two-dimensional method. The polymer material in the chip and the detected object are interacted. Through reading the molecular chain information of polymer material, biological information of detected subjects will be directly obtained. The grid method has the disadvantage of poor repeatability and lower sensitivity. In the microdeposition process, it is first to depose a macromolecule layer on the detected material surface, and then analyze the material through the surface topography of deposition. Atomic force microscope (AFM) is often used for the surface morphology detection with certain requirements on surface characterization, contact angle of deposition, and the amount of the detected material [54, 55]. In medical field, biochips are mainly used for diagnosing diseases and screening drugs. Through collecting the genome information of normal people, building up the standard gene map, comparing the patient’s DNA or RNA sequence to normal sample, the DNA map information of the lesion will be obtained. Therefore, the database of lesion DNA map information can be established. DNA lesion database can be used as an important means of disease diagnosis, especially for early cancer, it has great significance. With biochips, the body’s response to a variety of different

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drugs also could be detected. It is an important method for drug screening and targeted material screening [56]. Bio-MEMS IC is for the purpose of biological medical diagnosis or biological information analysis. It is a micron scale device which includes sensors, actuator, and mechanical structures. Its main applications include the identification and analysis for biological information, medical diagnosis, tissue cell engineering, medical injection, and surgical assistance, etc. [57]. Bio-MEMS has similar application for identifying and analyzing biological information to the biochip technology. The difference is that mechanical structures of MEMS can better integrate functions for information detection and analyses. For examples, silicon beam or diaphragm can be used for selectively detecting the surface free energy of biological surface; the electrical signal variation, such as resistance and capacitance, can directly reflect biological information. Thus, the medicine diagnosis using the biological MEMS has advantages of quick response and more automation. Microinjectors made of GaN can complete the injection without touching human skin or nerves, to achieve destruction free of cell tissues and painless sensation [57].

References 1. Seebeck effect. https://www.britannica.com/science/Seebeck-effect. Accessed 22 Feb 2020 2. B. Bhushan (ed.), Springer Handbook of Nano-technology, 3rd edn. (Springer, Berlin/Heidelberg, 2010), pp. 30–41 3. Z. You, B. Li, S. Yu, et al., Applications of MEMS Devices in Nanosatellite, Proceedings of the 2nd International Conference Recent Advance in Space Technologies, Istanbul, Turkey, 2005) 4. J.-M. Tulliani, B. Inserra, D. Ziegler, Carbon-based materials for humidity sensing: a short review. Micromachines (Basel) 10(4), 232 (2019) 5. Resistance sensors. https://www.ametekncc.com/products/industrialcontrols/liquidlevel. Accessed 22 Feb 2020 6. Types and Trend of Resistance Temperature Sensors: https://www.koaglobal.com/product/ library/sensor/trend?sc_lang¼en. Accessed 22 Feb 2020 7. Capacitive-sensors. https://www.lionprecision.com/products/capacitive-sensors/. Accessed 22 Feb 2020 8. H. Zhang (ed.), Complete Technology of MEMS (BUAA Press, Beijing, 2007), pp. 1269–1305. ISBN: 9787811242331 9. H. Zhang (ed.), Complete Technology of MEMS (BUAA Press, Beijing, 2007), pp. 1306–1330. ISBN: 9787811242331 10. Conductivity Sensor. https://www.yokogawa.com/us/solutions/products-platforms/process-ana lyzers/liquid-analyzers/conductivity-sensors/. Accessed 22 Feb 2020 11. P. Regtien, E. Dertien, Sensors for Mechatronics, 2nd edn. (Elsevier, Amsterdam, 2018) 12. H. Zhang (ed.), Complete Technology of MEMS (BUAA Press, Beijing, 2007), pp. 734–813. ISBN: 9787811242331 13. S. Lin, Study on the radial vibration of a new type of composite piezoelectric transducer. J. Sound Vib. 306(1–2), 192–202 (2007) 14. Temperature Sensors. https://www.electronics-tutorials.ws/io/io_3.html. Accessed 22 Feb 2020 15. F. Reverter, X. Perpiñà, E. Barajas, et al., MOSFET dynamic thermal sensor for IC testing applications. Sensors Actuators A Phys. 242, 195–202 (2016)

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42. M.P. Lesser, CCD backside coatings optimized for 200–300 nm observations. Proc. SPIE Int. Soc. Opt. Eng. SPIE 4139, 8–15 (2000) 43. B.K. Gibson, P. Hickson, Time-delay integration CCD read-out technique – image deformation. Mon. Not. R. Astron. Soc. 258(3), 543–551 (1992) 44. P. Noble, Self-scanned silicon image detector arrays. IEEE Trans. Electron Devices 15(4), 202–209 (1968) 45. CMOS APS. https://www.spacefoundation.org/space_technology_hal/active-pixel-sensor/. Accessed 22 Feb 2020 46. Smallest BSI Sensor. https://www.ovt.com/sensors/OV6948. Accessed 22 Feb 2020 47. Fingerprint Recognition Technology. https://www.biosmart-tech.com/technologies/fingerprintrecognition/. Accessed 22 Feb 2020 48. Fingerprint Technology and Algorithm: https://www.innovatrics.com/fingerprint-technology/. Accessed 22 Feb 2020 49. S. Massie, B6TS Touch Sensing IC (White Paper, OMRON Electronic, August 2006) 50. Atmel’s product. https://www.mouser.com/pdfdocs/maXTouch-T-brochure.pdf. Accessed 22 Feb 2020 51. Cypress’ product. https://www.cypress.com/products/truetouch-touchscreen-controllers. Accessed 22 Feb 2020 52. Synaptics’ product. https://www.synaptics.com/products/touch-controllers. Accessed 22 Feb 2020 53. E. Southern, K. Mir, M. Shchepinov, Molecular interactions on microarrays. Nat. Genet. 21(Suppl 1), 5–9 (1999) 54. N. Kimura, T. Nagasaka, J. Murakami, et al., Methylation profiles of genes utilizing newly developed CpG island methylation microarray on colorectal cancer patients. Nucleic Acids Res. 33(5), e46 (2005) 55. A. Kumar, O. Larsson, D. Parodi, et al., Silanized nucleic acids: a general platform for DNA immobilization. Nucleic Acids Res. 28(14), e71 (2000) 56. R. Toomey, D. Freidank, J. Rühe, Swelling behavior of thin, surface-attached polymer networks. Macromolecules 37, 882–887 (2004) 57. S. Steven, Saliterman: Fundamentals of BioMEMS and Medical Microdevices (SPIE- The International Society for Optical Engineering, Bellingham, 2006)

Applications of IC Products in Consumer, Computer, and Communication Electronics

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Yieji Zhu, Hui Liu, Yongxin Liu, Guoqiang Li, and Shengming Zhou

Contents Electronic Games and Toys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Home Appliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consumer Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application in Internet of Things . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart City . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Personal Computer, Desktop, and Their Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supercomputers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mobile Phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Networking and Communication Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Telecommunication Core Network and Access Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unified Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Y. Zhu · H. Liu Huaqiang Electronic Industry Research Institute, Shenzhen, China Y. Liu Shenzhen Institute of Micro-nano IC and System Application, Shenzhen, China G. Li Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd., Shanghai, China Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, China ICWise Market Information Consulting (Shanghai) Co., Ltd., Shanghai, China S. Zhou (*) Southern University of Science and Technology, Shenzhen, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_19

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Abstract

This chapter introduces the main applications of IC products in the fields of consumer electronics, computers, and communications. The context contains a total of 14 entries, covering the IC products used in daily consumer and home electronics (e.g., electronic games and electronic toys), home appliances, personal consumer electronics and peripherals, various smart cars, concurrent Internet of Things (IoT) applications, smart homes, and smart cities. The second category includes personal computers, office workstations and external equipment, and high-end supercomputers. The third category of communication products encapsulate mobile phones, data centers, network communication equipment, wireless communication core network and access networks, and future integrated or unified communication fields. Keywords

Consumer electronics · Computers · Smart cities · IoT · Network

Electronic Games and Toys There are a couple of game machine manufacturers in the world. Nintendo Corporation, founded in 1889 in Japan, is a television game developer and machine manufacturer [1]. Microsoft entered the home game market at the end of 2001, its product Xbox [2] is a part of Microsoft’s strategy map, and its positioning is not only a game machine, but also a home Internet platform connecting game players. Microsoft’s subsequent Xbox 360 and Xbox One have also been successful. Sony’s home television game machine PlayStation (e.g., PS4) has become one of the most famous home game machines [3]. Japan Nintendo is the pioneer of electronic video games. In the television era, Nintendo launched a variety of game products with advanced ideas and game technology (such as Nintendo Wii), developed a number of classic games, and established the dominant position in game industry. The major semiconductor chips used in these above-listed common electronic game machines and toys are voice chip, microcontroller unit (MCU), sensor chip, and so on, while the high-end game machines of Microsoft, Nintendo, and Sony adopt higher performance application processors (APs) and graphic processor units (GPUs). (1) Voice chip converts analog voice signal into digital signal by sampling and stores it into chip’s ROM. If necessary, it can also recover the digital voice signal in ROM to analog voice signal to fulfill man-machine interaction. (2) Microcontroller (unit) can simplify design and fulfill diversified functions and can meet application requirements. At present, microcontroller has been widely used in electronic toys. (3) In modern toy products, sensors with different functions are often used to empower toy with some intelligent functions. In the video game console of a Sony PlayStation, various IC components can be found, including R3000A CPU by MIPS, Geometry Transfer Engine (GTE)

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coprocessor, motion decoder (MDEC), system control coprocessor, memory (DRAM and ROM) chips, GPU by Toshiba, sound processing unit (SPU), I/O, and peripherals [4]. With the development of artificial intelligence (AI) and robotics technology, interactive robot and entertainment robot with AI function gradually become accessories in people’s daily lives, and game machine will meet prosperous future.

Home Appliances Home appliances are divided into white goods and black goods, which entered general families in the late stage of the second industrial revolution. (1) White goods generally refer to those appliances which can help people to reduce labor intensity, replace some housework, or improve the quality of life, its appearance color is mainly white [5]. The typical white goods consist of air conditioner, washing machine, refrigerator, and other common home appliances (electric heater, Hoover, air cleaner, humidifier, electric fan, etc.), as well as emerging sweeping robot and health monitoring appliances, such as weighing scale, PM25 detector, baby monitoring intelligent camera, sphygmomanometer, blood glucose meter, etc. As a new category of white goods, living appliances and health monitoring appliances continuously come to market. Sometimes brown goods is used as a synonym for white goods. (2) Black goods are generally referred to those home appliances for communication and entertainment. Typical products of black goods include TV set, video camera recorder, VCD/DVD/BluRay players, set-top box (STB), Hi-Fi entertaining equipment and home theater system, etc. At present, the main manufacturers of home appliance are Philips, Sony, Toshiba, Siemens, Samsung, and so on. China has become a global manufacturing center of home appliances in the world, and there are many world-class great enterprises of home appliance with revenue of more than RMB 100 billion, such as Haier, GREE [6], and Midea [7]. The wave of digital, networking, and intelligence originated from personal computers, and then extended to personal digital products and cellphones. Now it has extended to home appliances, it changed products’ function and form of home appliances, and even customers’ habit. For example, cable TV, satellite TV, and Internet TV have basically replaced or been replacing the traditional TV set and DVD/BluRay players, and become the main source of home video content. TV set is getting more and more powerful in the performance, storage, and network connection, which integrated lots of functions besides multimedia, interactive on-demand services, game, education, shopping, etc. The new generation of intelligent speaker integrates voice interaction and artificial intelligence (AI). White goods is also getting intelligent and networking, which integrates with stronger data collecting, processing, storage, and communication functions. It is a general trend that black goods and white goods and communication devices will be integrated with each other. For example, Xiaomi’s water purifier, rice cooker, sweeping robot, and air cleaner can be remotely controlled by wireless network; Haier has launched a network fridge with camera and display screen, which can issue

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orders to shop, and even automatically issue order according to the consumption status of items in the fridge in the future. The main chips used in traditional white goods are microcontroller unit (MCU), motor driving chip and power management unit (PMU), etc. In the era of the Internet of Things (IoT), white goods will use a number of application processors (APs), wireless connectivity chips, diversified sensors, and high-density memory chip. For example, current sweeping robot has embedded with MCU, Wi-Fi chip, and a variety of sensors. The main chips in black goods consist of display driving chip, display control chip, multimedia processor chip, PMU, etc.

Consumer Electronics Consumer electronics show (CES) started in 1967 in Chicago. In 1998 CES became an annual event where developers showcase their new technology and innovations, in Las Vegas in January [8, 9]. Consumer electronic products can be divided into personal consumer electronic product and household consumer electronic product. Due to the different level of consumption and technology, there are different types of personal consumer electronic product in different time periods. In 1970, the very first VCR (video cassette recorder) was presented to the world; in 1978 the first home computers were present at CES; in 1996, the very first DVD (digital versatile disc) was showing off. For the general public, at the early stage the representative products were radio, Walkman, home video game machine, and so on. At the later stage the representative products consist of MP3/MP4 player, digital still camera, and digital video recorder. Since 2010, with the increasingly powerful video entertainment function integrated in smartphone, the unit shipment of both traditional personal video entertainment products and digital products of photography and videography had declined, and then transformed to more specialized and subdivided market. The popularity of smartphone has brought in new types of smart wearable products, such as smart watch, smart ring, motion camera, motion healthy tracker, and virtual reality (VR) glasses. The development trend of smart wearable products is becoming more intelligent, networking, miniaturizing, specializing, and diversified. The new generation of smart watch has combined with Bluetooth headphone, and integrated with multifunctional modules, such as sport records (such as runner records and calorie consumption data), health (such as heart rate monitor and sleep monitor), entertainment (such as radio and high-quality songs), communication (such as using embedded SIM card), and other functions together. The main chips used in personal audio and video entertainment products consist of multimedia processor chip, audio codec chip, memory chip, and power management ICs. The main chips used in photographic products include CMOS image sensor (CIS) chip, image digital signal processor (DSP) chip, touch

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controller chip, display control chip, and power management IC. The main chips used in the new smart wearable product include sensors, controller, and processor chip, wireless connectivity (Wi-Fi or Bluetooth) chip, and power management IC. Due to tough requirement of wearable products in cost, dimension, and power consumption, many functional chips are designed to be integrated and/or packaged into one chip as system-in-package (SiP) product.

Smart Card Smart card, also known as IC Card, is the general name of all kinds of cards embedded with semiconductor chips. Compared with traditional cards with a magnetic stripe, the main advantages of smart cards are large data storage capacity, strong anticounterfeiting ability, antimagnetic, durable, and store digital key, digital certificate, or fingerprint information, with high security and reliability. One of the most common smart cards is the credit card, which is 85.5 mm  54 mm in length  width and 1 mm in thickness. According to the contacting mode, smart cards can be divided into contact smart cards and noncontact smart cards. Contact smart card is a chip card that communicates the IC inside the card with the external reading device through contacts. Typical products are such as subscriber identity module (SIM) cards in mobile phones. The working principle of the contactless smart card is that the reader/writer sends out fixed-frequency electromagnetic waves with the same frequency as the LC series resonant circuit in the card, and the contactless smart card, resonates. By accumulating capacitive charges, the circuit of the contactless smart card provides working voltage and current, and then realizes the data operation in the card. After years of development, smart cards are widely used in many applications, such as communication, financial services, urban management, health culture, public transport, and intelligent security. According to the applications, smart cards can be divided into e-government cards, financial telecommunications cards, and other cards, as shown in Fig. 19.1. Smart card industry in China began to develop in the 1990s and has formed a complete industrial chain in security standards and industrialization in the field of e-government, such as second-generation identity cards, and achieved a domestic milestone. Financial smart cards deal with finance business, the cards must meet the secure regulations and standards. The secure regulations of international financial cards include the certification of Common Criteria (CC) for Information Technology Security Evaluation [10] and the certification of EMV standards [11]. The EMV standards are initiated by Europay, MasterCard, and Visa (EMV), and joined later by Japan Credit Bureau card (JCB), American Express, China UnionPay, and Discover. CC certification is defined by Common Criteria Recognition Arrangement (CCRA), there are 26 member countries by 2016 [10].

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Fig. 19.1 Classification of smart card applications

Application in Internet of Things When Internet of Things (IoT) was first proposed, it specially indicates the sensor network depending on the radio frequency identification (RFID) technology. In 1999, Massachusetts Institute of Technology (MIT) first proposed the concept of, and coined the term, IoT, and the opinion that everything can be interconnected via a network and expounded the basic meaning of IoT [12]. The International Telecommunication Union (ITU) issued “ITU Internet Report 2005: IoT” on the World Summit on Information Society held in 2005, which extended the connotation and extension of IoT [13, 14]. The architecture of IoT is shown in Fig. 19.2. IoT involves data collection, data processing, and data transmission. There are four technologies related to IoT. (1) The first technology is radio frequency identification (RFID) technology. If an object is interconnected or is connected to Internet, it first has an identifiable address. The RFID is the mainstream technology with bright prospect in identification. (2) The second technology is the sensor technology. After an object is identified and is connected to the network, the analog information perceived by sensors shall be converted to digital signals, which will be provided to local or remote computing center for processing. (3) The third technology is the embedded technology. Some sensors will process information locally in some applications and then valuable data are uploaded. The IoT terminal will operate for a long period. Therefore, local embedded processors shall satisfy strict power

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Fig. 19.2 Architecture of IoT [13]

consumption, cost, and performance requirements. (4) The fourth technology is the radio communication technology. The radio communication technology of the IoT is divided into two categories, including short-distance communication technologies (e.g., ZigBee, Wi-Fi, Bluetooth, and Z-Wave) and LPWAN (low-power wide-area network). LPWAN can be further divided into two types. The first type includes technologies such as LoRa and SigFox without authorized frequency spectrum. Another type includes 2G/3G/4G cellular communication technologies working in authorized frequency spectrum such as EC-GSM, LTE Cat-M, and NB-IoT. The IoT application chips include RFID label chip, MEMS sensor, wireless connection chip, and MCU. The RFID system is composed of the transmission terminal and receiving terminal. Generally, the radio communication technology is used to identify a target and read/write related data. RFID label is used as a transmitter. Each label includes unique electronic code to identify target objects. RFID labels can be divided into low-frequency (LF) radio frequency card working at 125 kHz and 134.2 kHz frequency, high-frequency (HF) radio frequency card working at 13.56 MHz, and ultrahigh frequency (UHF) radio frequency card working at 433 MHz, 915 MHz, 2.45 GHz, and 5.8 GHz [15]. RFID labels can also be divided as read-only card, read/write card, and CPU card. The RFID chips are composed of RF/analog front end, MCU core, and memory.

Smart Home The IC application in smart home concept aims to serve for convenient, comfortable, secure, healthy, and energy-saving living experiences by using advanced technologies for daily life, e.g., IoT, cloud computing, mobile Internet, and big data [16]. Smart home is the basic units of a smart city.

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Smart furniture interconnects home electrical appliances and home devices via communication technologies (e.g., Bluetooth, Wi-Fi, ZigBee, PLC, etc.), then it connects to the Internet via home gateway, and finally smart furniture can be controlled via smartphones and the Internet. The smart home concept is expanded from the smart furniture, which intends to improve consumer’s home experiences via services and with truly useful home information. In practice, the smart home application is designed to solve the elderly’s chronic disease management and emergency call via smart medical treatment, improve home air quality via smart air management, and reduce home energy expense via smart energy management. The smart furniture controls and instructs the hardware in a smart home. Smart home and smart furniture can realize control and automation of multiple systems, e.g., lighting, heat collection, ventilation, air-conditioner (smart environmental control) and security, and home appliances (e.g., washer, dryer, oven, refrigerator, and icebox). The main electronic hub components in a smart home can be composed of bedroom, kitchen, bathroom, nursery, living room, garage, and backyard or garden, etc. A smart home is the minimal unit of a smart city. With the home service as the core, the smart home provides services with hardware to improve consumer’s home life experiences as the root foothold. Main participants of the smart home industry include Internet companies, real estate companies, smart home platform companies (integrated solution provider), service providers, hardware manufacturers, chip manufacturers, software manufacturers, operational integrators, etc. The smart home is an integrated system with multiple hardware and diversified IC chips [17], such as sensors (temperature, humidity, smoke, hazard gas sensor, etc.), communication (Wi-Fi, Bluetooth, ZigBee, PLC, etc.) chips, embedded processor chips (MCU and AP), power management chips (PMU), etc.

Smart City The smart city targets to integrate ICT (information and communication technology) and IoT (Internet of Things) together and to become more intelligent and efficient operations and management [18]. A smart city includes concepts of peace city, smart traffic, smart e-government, smart home, smart medical treatment, smart education, smart building, smart energy, smart city governance, smart logistics, smart tourism, smart water, and smart rubbish management system. Therefore, it is a complicated, interconnected, interactive, and integrated system. The fundamental technologies needed in a smart city include software and hardware of IoT, cloud computing, big data, information security, and mobile application, as shown in Fig. 19.3. No doubt, a smart city will utilize ICs in wide spectrum for diversified state-of-art technologies for supervision, control, and analysis, in various applications. The smart city industry is projected to be a $400 billion market by 2020, with 600 cities worldwide. These cities are expected to generate 60% of the world’s GDP by 2025 [19]. The technology behind the smart city is IoT, which is a network of

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Fig. 19.3 Fundamental architecture of smart city industry

physical connected devices, like vehicles or home appliances, which enable these “things” to connect and exchange data [20]. The IC products for IoT related and used in the smart city can be classified into several categories, such as for energy saving, transportation, data handling, infrastructure, and mobility.

Personal Computer, Desktop, and Their Peripherals There are three major types of personal computers (PCs), namely desktop computer, laptop or notebook computer, and tablet computer. (1) Desktop computer is the most traditional product, its host computer and display monitor are relatively independent and bulky, so that they are on desk. (2) Compared with desktop computer, laptop or notebook computer has smaller size, lighter weight, more portable for carry-on at traveling, and suitable for mobile operation [21]. The development trend of notebook computer is to be ultralight and ultrathin. (3) Tablet has better portability, replacing keyboard with touch screen, and users can input with fingers or handwriting pen [22]. The IC in tablet is either the ARM architecture or 86 architecture. The representative tablet based on ARM architecture is Apple iPad and Android tablet, which are closer to smartphone; the representative tablet based on 86 architecture is Microsoft’s Surface, which is closer to notebook computer. The main ICs used in desktop and notebook computer consist of CPU, North Bridge chip, South Bridge chip, memories, I/O, and other peripherals. CPU chip is the core chip of personal computer. North Bridge chip is one of the most important chips on PC motherboard, also known as the main bridge. North Bridge chip is in charge of connecting high-speed devices such as DRAM and video graphics card. It is nearest to the CPU for close communication with the CPU. South Bridge chip is another important chip in the motherboard chipset, mainly for communication among I/O buses. South Bridge chip does not directly connect with CPU, but through North Bridge chip. It is generally far away from CPU for easy layout. In

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addition, there is dynamic random-access memory (DRAM), which is a large-scale IC that can access, read/write, data at any time, and consists of many memory cells. To expand memory size easily, several DRAM chips are soldered on the DRAM bar together. Computer manufacturers write data into read only memory (ROM), users cannot usually modify the data in ROM, and these data will not lose even if the power of computer is turned off. ROM is usually used to store the basic input/output system (BIOS) information of the computer. The computer’s peripheral devices [23] are the joint name of input/output devices of computer system. It can be divided into input devices, output devices, input/ output interface, and external memory, including display monitor, keyboard, mouse, printer, scanner, mobile storage, etc. The major chips used in computer peripheral devices are touch controller chip, modem chip, flash memory chip, and so on. Touch screen is an electronic product that fulfills human-computer interaction through touch controller chip. At present, capacitive touch screen is widely used. Its basic principle is that the touch of human finger will change the capacitor value of the corresponding position of touch screen, the corresponding position can be identified and obtained by its algorithm, and the corresponding operation can be called by application software. Modem chip generally consists of three hardware modules: controller, data pump, and data processor. Nowadays, most of peripheral devices still generally use NOR flash memory chips for code storage, while data storage products such as U-disk and SSD solid-state hard disk have fully used NAND flash memory chips. The professionals in semiconductor, IT, and scientific research industries still widely use workstation for conventional working equipment instead of PCs. The features of the workstation are prominent performance, large size display screen, clear image, and visual comfort [24]. The users of workstation are usually interconnected through local area network (LAN), use multiuser operating system, and call the shared software and data for analysis. Depending on the amount of staff, the center of the LAN is often composed of one or more server farms.

Supercomputers There are demand for computers with high performance in the areas of commerce, industry, transportation, defense, etc., therefore servers, mainframe computers, and supercomputers are widely used. Servers, mainframe computers, and supercomputers are high-performance computing devices. High-performance computing is measured by the number of floating-point operations per second (FLOPS), as replacing the unit of MIPS (million instructions per second) used by general-purpose computers. In 2015, supercomputers can hit the capacity record of PFLOPS (Peta FLOPS). Previously there were two supercomputers run on Unix, to date, all of the top 500 supercomputers are operating on Linux system. Servers are commonly available [25] today as they are typically used by companies and governments to serve many customers simultaneously over the network. The server has many advantages in terms of reliability, scalability, and

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manageability, and it is usually required that the server has capabilities of highthroughput computing and multitask computing. Mainframe computers use specialized instruction sets, operating systems, and application software to handle the application tasks of large organizations, such as census, industrial, and consumer statistics, enterprise resource planning, and other large-scale data processing tasks. A supercomputer is a huge computer system that is mainly used to undertake strategic major scientific research, such as quantum mechanics, weather forecasting, oil exploration, missile rockets, medical research, and so on. Supercomputers began in the 1960s [26]. In 1983, China successfully developed a galaxy supercomputer capable of more than 100 million operations per second. In 2004, Sugon entered the world’s top 500 supercomputers [27] for the first time, ranking tenth. In 2010, the Tianhe-1 supercomputer was completed in Tianjin, with its peak computing speed of 4700  1012 FLOPS and its continuous computing speed of 2566  1012 FLOPS, ranking the first in the world. In 2013, Tianhe-2 was successfully developed, and was ranked the sixth world supercomputer champion. In June 2016, it reached 54  1015 FLOPS, setting a new world record. In 2017, Sunway Taihulight is equipped with 40,960 SW26010 high-performance processors, ranking first in the world. In 2017, the top 10 supercomputers are shown in Table 19.1, the top 2 and 3 supercomputers all use Intel processors, the top 4 use AMD processors, and the top 5 use IBM processors.

Mobile Phone In April 3, 1973, Martin Cooper of Motorola used a mobile phone to place a very first wireless phone call [28], the patent for DynaTAC (dynamic adaptive total area coverage) was filed on October 27, 1973 (US patent No. 3,906,166). The mobile phone measured 22.86 cm long, 12.7 cm deep, and 4.44 cm wide and weighed 1.1 kg. Ten years later, the first ever portable mobile phone in 1983 was commercially released as the Motorola DynaTAC 8000X [29], it costed $4000! So far, the development of mobile phones has gone through three stages: from feature phones that can only make calls and provide short message service (SMS) to multimedia phones that have added multimedia functions (such as video and music), and up to now become the fully functional smartphones. Various chips in a mobile phone can provide wireless WAN, wireless LAN, nearfield communication (NFC), and application processing functions. Currently, the development is toward the direction of “integration,” “multicores,” “multifunctions,” and “small size with low cost.” Important ICs in a mobile phone include baseband (BB) chip, application processor (AP), RF chip, memory chip, sensor, PMU, etc.; see Fig. 19.4. 1. Baseband chip: mainly used to process 2G/3G/4G multiple communication protocols, to modulate or demodulate baseband signals or radio (for example, audio signal may have a baseband range from 20 Hz to 20 kHz). At present, there are generally two schemes: one is put an application processor (AP) into the system

Maximum computation speed measured value/PFLOPS 93.015

33.863

19.590

17.590 17.173 14.015 13.555

10.510

8.587 8.101

Rank 1

2

3

4 5 6 7

8

9 10

10.066 11.079

11.280

27.113 20.133 27.881 24.914

25.326

54.902

Maximum computing speed peak/PFLOPS 125.436

Table 19.1 2017 Supercomputer top 10 ranking (49th annual) [27]

Mira Trinity

Titan Sequoia Cori OakforestPACS K Computer

Piz Daint

Name Shenwei Taihuzhiguang Tianhe-2

Blue gene Gray XC40

Fujitsu

Cray XK7 Blue gene Gray XC40 Fujitsu

Cray XC50

TH-IVB-FEP

Version MPP

A2 (Power) Xeon E5

SPARC64

Opteron A2 (Power) Xeon Phi Xeon Phi

Xeon E5

Xeon E5

Microprocessor SW26010

Institute for Advanced Research in Computing Science, Japan America, ANL America, LANL

Country and manufacturer Wuxi National Supercomputer Center, China Guangzhou Supercomputer Center, China Swiss Cray Supercomputer center ORNL, USA LLNL, USA Energy research, USA HPC Collaborating center, Japan

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Fig. 19.4 Schematic diagram of mobile phone chip [1]

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on chip (SoC), referred to as integration scheme, the representative manufacturers are Qualcomm, MediaTek, SpreadTrum, and Huawei; the other uses a separate modem baseband chip, the representative manufacturers are Qualcomm and Intel. Application processor (AP): developed to process various functions (except communication function) in a mobile phone, such as audio/video playing, image processing, etc. Rapid development of AP has gone through from single core to multicore, and from single function to multifunction; AP has evolved to become a complex SoC in a mobile. As in 2018, popular AP enlisted are Apple A13 Bionic [30], Qualcomm Snapdragon 855, Hisilicon Kirin 990, Samsung Exynos 9825, etc. RF Chip: used for amplification, frequency modulation, and transmit/receive RF signals. There are a large number of RF chips used in mobile phones, including power amplifiers, RF switches, and filters. The mainstream manufacturers are Skyworks, Qorvo (merger of RFMD and TriQuint), Avago, and Anadigics. Memory chip: The main types of memory chips are DRAM (dynamic randomaccess memory) and NAND flash (data storage). The mainstream manufacturers are Hynix, Samsung, etc. Sensor: It is mainly used to collect various natural signals and then convert them into electrical signals for application. There are a variety of sensors, including accelerometers, electronic compass, gyroscope, proximity and ambient light chip, camera, infrared sensor, fingerprint recognition chip, etc. Power management chip: manage the power conversion, distribution, and detection. It mainly includes power management unit (PMU), low dropout regulator (LDO), battery charging chip, wireless charging chip, overcurrent protection chip, etc. Mainstream manufacturers include Microchip, ON Semiconductor, ADI, MTK, Qualcomm, and Hisilicon.

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7. Driver chip: convert the digital signal from the baseband chip into the corresponding analog voltage value, and drive the components to work, including universal serial bus (USB) driver, liquid crystal display (LCD) driver, TouchPanel (TP) driver, etc.

Data Center Data center is the critical infrastructure of enterprise information which can help enterprise to share and work together with the centralized data [31]. In general, a date center includes computer system and associated equipment (communication system and storage system), redundant data communication connections, environmental control equipment, and many kinds of security devices such as servers, Internet switches, storage device, UPS power, Internet monitor equipment, Kernel-based virtual machine, server control, etc. Fig. 19.5 shows the structure of the data center. With the development of big data and cloud computing, several models of cloud service have been proposed [32], viz. infrastructure as a service (IaaS), platform as a service (PaaS), software as a service (SaaS), etc. All the implementation will bring up the new requirement for the HW/SW codesign technique of electronics industry including high-performance CPU design, high-speed memory design, and highspeed interface design. The main chips used for data center are server chip and Internet switching chips. (1) Server chip includes CPU and chipset. Chipset can be divided to North Bridge and South Bridge chips according to their location in the board. Intel 86 is the

Fig. 19.5 Schematic of data center network

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dominant CPU technical specification and standards for servers. Intel Xeon and AMD Opteron are the typical CPU of sever chips and make up most of the server CPU market. IBM POWER chips are mainly used for high-level market. Currently, ARM is also trying to design CPU architecture for servers. AMD and Broadcom have already designed chips on ARM architecture. (2) The performance of switch always determines the degree of the intelligence and informatization of the data center. The specific IC can improve the switching efficiency by switching the data information in parallel from all the ports at the line with high speed, which can achieve higher performance than traditional bridge switches. Cisco switch takes in-house chips, and other switch uses the Broadcom chips. Top server manufacturers by market shares in 2018 include Dell, HPE, Inspur, Lenovo, and IBM/Huawei/Cisco on par.

Networking and Communication Equipment Communication net consists of transmission, switching, and terminal. Physically, it is usually made up of networking communication equipment and transmission medium, such as network cards, hub, switch, router, network line, RJ-45 connector, etc. Networking and communication equipment [33] mainly include switches, routers, servers, etc. Broadly speaking, there are two types of switch, wide area network (WAN) switches and local area network (LAN) switches. WAN switches are mainly used in the telecommunication field and provide basic communication platform. LAN switches are used in local area networks to connect terminal devices, such as PCs and network printers. According to the network hierarchy, switches can be divided into three types: access switch, convergence switch, and core switch, as shown in Fig. 19.6. The core chips of switches mainly include high-performance CPU, highperformance network processor (NP), special ASIC, and high bandwidth interface chips. The mainly used network switch chips are designed by Broadcom, Marvell, and others. The high-end switches mostly use Broadcom switch chips. At present, Hisilicon Semiconductor has successfully developed the Ethernet processor of the switch for high-end applications in China. Router is a data packet forwarding device working in the network layer, and its typical function is data channel and control. The key technology of new generation core and high-end router is network processor (NP) supporting multirouting protocols, which is usually composed of several high-performance CPUs and several hardware coprocessors (in ASIC form). Server refers to the equipment that runs the application software under the network environment and provides users with shared information resources and services. Servers consist of processors, hard disks, memory, system buses, etc. They are customized for specific network applications, and usually are the center of the network. They have the characteristics of high performance, high reliability, high availability, high I/O throughput, large storage capacity, strong networking, and

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Fig. 19.6 Location of switches in network

network management capabilities. There are CPU chips, memory control chips, and network interface chips in server solutions. In today’s networking and communication equipment assembly, switchboard and server are physically bulky; traditional installed switchboard has expanded its function from merely telephone exchange to networking and telecommunication instrument sets include routers and servers in the distribution and application [34].

Telecommunication Core Network and Access Network The core network [35] is a main portion in a telecommunication network, which offers numerous services to the customers who are interconnected by the access network [36]. Stored program control (SPC) exchange is a very important milestone in the development of telecommunication network, especially in digital SPC exchange, which is a significant point that communication technology transits from analog to digital. In the first place, central office (CO) is constructed by exchange room, power room, and MDF (main distribution frame) room, and cables are initially aggregated from MDF room to exchange room. With the development of technology, new access technology is adopted such as remote module, V5, and 450 MHz wireless loop; mobile communication

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subsequently has been used; mobile switch centers (MSC) are setup in CO and a lot of BSS (base system stations) are setup everywhere. At present, communication network architecture is evolving from traditional circuit domain to flat IP domain. The core network is named as IP multimedia subsystem (IMS), and communication services generally include voice communication, broadband service, video service, audio and video conference, multimedia service, etc. 1. Communication core network and access network based circuit switch mode Circuit switching is characterized by communication from call setup, call connection to call termination. The entire process requires exclusive user circuits, trunk circuit, and TSI (time-slot interchanger). SPC is a core equipment in circuit switch mode (CSM), it is an extremely complex telecom system, the architecture of CSM design is modular, and through combination and stacking different modules can provide more functions and capacity. SPC system is constructed of central process unit, switch net, clock, trunk, signaling, as well as user and power subsystem. 2. Soft switch Character of soft switch is independent between call control module and media bearer, it includes two function entities, call server (CS) and media gateway (MG). Call server implements user register, user authentication/authorization, call control, signaling, route, and final account functions. Media gateway provides user access and media resources. CS and MG are connected through IP MAN or WAN; MG can be located in aggregation of residence community so lengthy copper cable can be saved. 3. IP multimedia subsystem (IMS) Character of IMS is IP and flat network. It includes fixed public switched telephone network (PSTN) based CSM, 2G/2.5G (GSM/GPRS) mobile telecom network, full IP 3G/4G mobile telecom network, and WLAN based Wi-Fi and HFC (hybrid fiber coaxial) network–based cable modem. Increasing number of ICs has been used in telecom equipment, in addition to main chipset, CPU, memory, and flash; there are also PCI (peripheral component interconnect) controller, USB controller, Ethernet controller, UART, power management chip, TSI (time-slot interexchange), E1/T1 trunk interface, FPGA, user interface ASIC and DSP, etc.

Unified Communication Unified communications (UC) is a business and marketing concept describing the integration of enterprise communication services [37] such as instant messaging (chat), presence information, voice (including IP telephony), mobility features (including extension mobility and single number reach), audio, web, and videoconferencing, fixed-mobile convergence (FMC), desktop sharing, data sharing

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(including web connected electronic interactive whiteboards), call control, and speech recognition. With the booming development of communication services, short messaging service (SMS), broadband, video, games, and Internet applications other than traditional voice services have become important services of communication networks. These network services developed through the rapid growth of computer technology, and have gradually generated to the form of content delivery/distribution network (CDN), Internet protocol television (IPTV), Internet data center (IDC), and other new infrastructure applications in communication field. Finally, those services have increasingly become an important part of telecommunication network. The main purpose of using content delivery/distribution network (CDN) technology is to increase access speed, solving the problem in cross-domain interconnection, large capacity, and high concurrency of new services such as games and videos, and to improve user experience. CDN initially appeared in around 2005, and it gradually integrated the communication network with Internet, involving technologies such as domain name system (DNS), content store, dispatching and broadband bearer networks. Currently, telecom operators and various Internet operators have deployed CDNs. There are even some vendors that specialize in CDN operation services [38] due to the huge demand. With the rapid growth of video, games, and other communication services, CDN is driving its business climax in the past decade. In addition to the acceleration on telecom carrier network technology, CDN also uses many PC and storage technologies, especially for high-performance CPUs, high-speed communication buses, and large-scale memory control chips that are supposed to of higher demands. In the future, higher performance, reliability, and security are expected, and local area network (LAN), ultrahigh speed fiber-optic communication, flash memory, and control will become the key technologies. The convergence of traditional telecommunication networks, broadcasting networks, and computer networks is a trend with the development of Internet protocol (IP) technology. In the future, all digital communication facilities will support the communication of all services including data, voice, and video. The typical representative of tri-network integration [39] is network TV service. It uses broadband network and a new generation of AV technology to integrate Internet, multimedia, and communication technologies, providing home users with a variety of interactive services such as digital TV. The usual IPTV system is a large-scale solution covering set-top box devices, such as terminal set-top boxes, streaming media server CDNs, content management systems (CMS), and encoders. In recent years, smart homes have also promoted the rapid development of IPTV. Home entertainment and communication solutions such as IPTV with the concept of tri-network integration involve many converged technologies, such as AV codec, storage and distribution, content security and protection, etc. That technology has largely driven related IC industry to fast development. Among them, set-top box chips, home gateway chips, digital certificate authority (CA), and digital rights management (DRM) security chips have been widely used; typical chips such as Hisilicon Hi3716, Hi3798, etc. were also used.

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34. Schneider Distribution switchboards. https://www.electrical-installation.org/enwiki/Distribu tion_switchboards. Accessed 24 Feb 2020 35. Core Network. https://www.techopedia.com/definition/6641/core-network. Accessed 24 Feb 2020 36. What is Access network?. https://whatis.techtarget.com/definition/access-network. Accessed 24 Feb 2020 37. Unified communications. https://en.wikipedia.org/wiki/Unified_communications. Accessed 24 Feb 2020 38. Content delivery/distribution network. https://firstsiteguide.com/cdn-guide/. Accessed 24 Feb 2020 39. China’s Tri-network Integration. http://en.people.cn/90001/90776/90881/7189988.html. Accessed 24 Feb 2020

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Quan Yan, Qiquan Zhang, Xin-An Wang, and Huan Liu

Contents In-Vehicle Infotainment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Body Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Powertrain Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automotive Active Safety System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . New Energy Vehicles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Driver-Assistance System (ADAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rail Transit System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application of New Energy Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medical Imaging Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medical Electronic Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medical Monitoring Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medical Electronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implanted Medical Electronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medical Robot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

ICs and electronic products in automobiles, industrial, and medical care are closely related to people’s daily transportation, convenience, safety, and health. The continuous advancement of products in these fields continues to improve Q. Yan Mentor Graphics, Shanghai, China Q. Zhang Harbin Institute of Technology, Shenzhen, China X.-A. Wang (*) Electronic and Computer Engineering, Peking University, Shenzhen, China e-mail: [email protected] H. Liu Southern University of Science and Technology, Shenzhen, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_20

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overall the quality of our life. ICs are playing an increasingly important role in the performance improvement, cost reduction, feature enrichment, and humanization of products in these fields and even play a decisive role in the transformational success of certain types of products in a certain period. These are also areas where the demand for ICs is steadily increasing. Keywords

Automobiles · Industrial, medical care · Integrated circuits · Quality of life

In-Vehicle Infotainment Automobiles are becoming intelligent and networked. As a means of transportation, automobiles have also become a platform for people to entertain and access information. In-Vehicle Infotainment (IVI) refers to vehicle systems designed to meet drivers and passengers’ comfort, entertainment, and information needs [1]. IVI not only controls it through vehicle-borne special processor, operating system, controller local area network (LAN), and so on, but also connects the external world through public 3G/4G and upcoming 5G mobile network, satellite navigation technology, Wi-Fi, Bluetooth, and USB communication technology to realize mobile Internet services. IVI originated from automobile audio and video system, including radio, tape player, and CD player. With the development of science and technology, the IVI has integrated many functions and applications, such as audio and video broadcasting, real-time road condition and navigation, voice control, security diagnosis, games, e-mail, news and information, mobile phone interworking, and so on. In the future, the IVI will be further integrated with functions such as automatic driving. The increasing informationization of society has led to the increasing complexity of IVI, such as supporting a variety of mobile operating systems. GENIVI Alliance [2], a nonprofit organization, was established in 2009 to promote collaboration between automobile manufacturers and software developers, share an open source platform for the development of standard IVI, shorten the development cycle and the process of listing, and stimulate the innovative potential of IVI. IVI is not only a hardware component, but also a content service. It realizes seamless information exchange between the inside and outside of the vehicle, improves the safe interaction between drivers and the outside world, and integrates many kinds of vehicle infotainment projects, e.g., Internet, multimedia, navigation, and information.

Body Control Module The Body Control Module (BCM) system is a general term used to monitor and control the various electronic control unit-operating modules in the body and electrical designs [3]. The BCM is analogous to the central nervous system in the

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human body. The coordination of the human body is controlled by transmitting signals, while the control module regulates the operation and coordination between different parts of the car by using signals. The BCM controls a variety of automation and comfort functions (Fig. 20.1) in addition to controlling power windows, power mirrors, air conditioners, antitheft systems, central locks, and more (such as wiper control, headlight control, relay control, etc.). BCM is used to monitor and control vehicle body-related functions, as well as Controller Area Network (CAN) and Local Interconnect Network (LIN) communication support. CAN [4] is a high-speed dual-line differential data bus, which controls the communication between microcontroller and various electronic modules in the vehicle. It is a message-based protocol originally used for multiple wires in cars. LIN [5] is an inexpensive serial network protocol for communication between vehicle components, which can effectively support remote applications in vehicle networks. Because LIN is relatively slow, it is suitable for the electromechanical nodes in the layered network in the car as supplement to CAN network. At this stage, BCM demand is developed through the development of a centralized BCM governance structure, which can avoid the fragmentation that may occur when BCM is developed by different business units. By centralizing, the various components of the plan can be better integrated and aligned with overall business goals of the organization. The two main components of the BCM design are the control system and the power system. Unlike traditional hardware control, microcontroller units (MCUs) can be divided into hardware peripherals and software algorithms. The advantage of the MCU is that it can realize self-diagnosis within the system, effectively improving the robustness and reliability. The main load driver types for the central controller are lighting and relay drivers. BCM systems are also sometimes required to supply power to high-power loads, primarily through relays or relay drivers. Current monitoring of distributed loads can be used for car battery charging and load management. The power supply of the BCM is usually a 12 V or 24 V power supply network, and the voltage can be adjusted as needed for DSP, memory, IC, etc. Since the MCU needs to work when the car is not in operation, it must support the standby Fig. 20.1 System architecture of the Body Control Module

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mode of the MCU. At the same time, the car usually faces a higher-temperature environment, and the power supply needs to have an over-temperature protection function. Common radio frequency identification (RFID) technology has also been widely applied to engine antitheft lock systems and door and alarm systems. The frequency of BCM is 315 MHz (US/Japan) or 433 MHz (Europe) to achieve high-frequency transmission and reception; these frequencies are as well as used in remote control and tire pressure monitoring systems (TPMS) [6]. The BCM is a very important part of the vehicle. With the development of technology, more Active Body Control (ABC) templates are added into the system design [7] and are connected with power control module and other functional modules such as communication or sensing. This requires the BCM continuously toward higher degree of integration and scalability, in order to meet the high-speed development of automotive electronics industry.

Powertrain Control Module Powertrain control module (PCM) used on motor vehicles [8] is considered the “brain” of the engine control systems (ECS), which is also called the electronic control unit (ECU). PCM controls the clutch’s disengagement and shifting action and also controls the engine’s oil supply through other electronic devices, thus realizing joint-control of powertrain (engine, clutch, transmission, etc.). The subsystems of data sensing and ECU are the key components of PCM. Datasensing subsystems are primarily composed of various sensors. For example, each sensor collects relevant parameters required for the shift action and passes the signal to the ECU. The vehicle must be driven by following the driver’s intention. PCM must correctly understand and realize the driver’s control [9]. The sensor senses the changes of the control mechanism, such as the accelerator pedal, the brake pedal, and the steering wheel angle, and understands the driver’s intention after analysis by the ECU. In addition, other signals can be passed through switches and controllers. As ECU is the heart of the control system [10], it changes the working state and the shifting gear according to the driver’s intention based on the detected vehicle running state signal. The main functions of the ECU include data acquisition, data preprocessing, vehicle status recognition, driver operation intent recognition, shift decision, and quality control, as well as fault diagnosis, output, display control, and so on. ECUs today use high-performance 16-bit/32-bit microprocessor (MPU), and even fully customized microprocessors, or microcontroller units (MCUs) to enhance circuit functionality and improve control reliability. Through sensor’s sampling, PCM receives the signal and sends it to the ECU; the latter processes the data and sends the control signal to the actuator to realize the control of the powertrain, adjust the working state of the powertrain, and ensure the control of the vehicle.

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PCM generally has three control modes: two-machine or multimachine control; single ECU controls the engine and the transmission as a whole; and using a CAN bus for overall control.

Automotive Active Safety System Automotive safety system consists of automotive active safety system (AAS) and passive safety system (PAS) [11]. Active safety system detects potential safety risks on the road and takes actions actively to avoid hazards of potential collisions. Passive safety system protects the driver and passengers from getting further harm when the accident occurs; it composes of the general Global Outstanding Assessment (GOA), seatbelts and seatbelts’ pretightening function, air bags, special made safety window glasses, and steering column energy attraction device [12]. Thus, such electronic system should be based on various special automotive ICs [13] with high reliability and powerful functions. Active safety system includes the following components. 1. Collision avoidance system (CAS), also known as Forward Collision Warning System (FCW). CAS is used to avoid possible collision by detecting the forward risky situation of automotive. Normally FCW is formed of part of radar system, laser detector and electronic camera, etc. Radar system finds the risky situation forwardly, and it includes transceiver RF circuits, ADC circuit, data-processing CPU, and central control unit, warning display, and voice process circuits. Laser-detector module assesses the risky level of automotive, and it includes semiconductor laser, opto-electronic transceiver, fiber-optic transmission circuit, data-processing CPU and central control unit, warning display, and voice process circuit. Electronic camera module observes the complex road condition and takes action to protect automotive in safety. It is comprised of CCD camera, CCD image control unit, warning display, and voice-processing circuit [14]. 2. Lane Departure Warning system (LDW). By comparing the position change of moving automotive inside the lane, LDW system will issue a warning for deviating behavior of automotive. Now it mainly uses image recognition technology to predicate lane departure behavior. 3. Electronic Stability Control system (ESC). Keep automotive in best stability status by controlling driving force in unusual circumstance. ESC covers MCU control unit and sensors for measuring the automotive track deviation, angular velocity of the wheel, the steering angular offset, and hydraulic slowdown control device. 4. Antilock Braking System (ABS). Protect brake system from lock mode and make sure the driver still can control the driving direction under braking condition [3]. ABS contains MCU, sensors with angular velocity of the wheel, and hydraulic brake control units.

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5. Electronic Brake-force Distribution system (EBD). Normally work with ABS and reassign brake force to ensure driving safety. It covers sensor of wheel speed, electronic control unit, and hydraulic actuator. 6. Traction Control System (TCS). When automotive braking or speeding up on the road is having less friction force, TCS will adjust the output of wheel torque to assure automotive in better control and driving direction stability status. As a supplement of ABS, both TCS and ABS employ same control system, e.g., MCU, sensors with angular velocity of the wheel, and hydraulic brake control units. 7. Emergency Brake Assist system (EBA). Help driver to reduce the braking distance in emergency. It includes MCU, sensor, and control actuator. 8. Brake Override System (BOS). Ensure safe braking action by control gasoline emission level. 9. Tire Pressure Monitoring System (TPMS). Monitor whether the tire pressure is in normal range. It is made of pressure and temperature sensors, radio transceiver circuit, and display warning circuit. 10. Intelligent Parking Assist System (IPAS). Help driver to park safely. It covers CCD camera, ultrasonic transceiver circuit, and image and voice warning unit [4].

New Energy Vehicles New energy vehicles (NEVs) refer to the vehicles that use nontraditional gasoline or diesel fuel as power sources, which include pure battery electric vehicle (BEV), fuel cell electric vehicle (FCEV), hybrid electric vehicle (HEV), and so on [15, 16]. ICs are more widely used in NEVs than in traditional cars. In addition to the wellknown In-Vehicle Infotainment (IVI) System, Body Control Module (BCM) System, Powertrain Control Module (PCM) System, Automotive Active Safety System (AAS), and Advanced Driver-Assistance System, the Electronic Control System (ECS) of NEV generally includes the Electric Motor Control System, the Vehicle Control System, and the Battery Management System (BMS), the core of which is the BMS [17, 18]. BMS is an important part of new energy vehicles; its main role is to improve the utilization of batteries in new energy vehicles, balance battery power to maintain battery consistency, extend battery life, and assess and monitor battery capacity accurately. The core part of BMS consists of hardware circuits, underlying software and application layer software. The current mainstream battery detection ICs in the industry are mainly from Linear (LTC6803), ADI (A7280A), TI (BQ76PL536), Maxim (Max1 1080), and so on. In a BMS IC design for lithium (Li) battery cells, the primary function is to maintain the cells working within the safe operation region. The BMS IC should be ensured that when the voltage of the battery cells is lower than the rated voltage, BMS IC must prohibit the cells from discharging. On the other hand, the charging

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process should also be monitored and controlled. For example, to prevent battery damage or reduced life span, sensors are used to monitor and control the status of the battery, such that the battery is at a contact charging current at the beginning or at a very low current toward the end of the charging process. Therefore, BMS IC design can include both traditional MCU in combination with sensors or MEMS; the MCU and MEMS can be integrated in a SiP for better performance.

Advanced Driver-Assistance System (ADAS) Advanced Driver-Assistance System (ADAS) is a subset of the driver assistance system for supporting the driver in their primary driving task. It can detect and evaluate the environment of the vehicle by means of sensors, and then inform and warn the driver, provide feedback on driver actions, increase comfort, and reduce the workload by actively stabilizing or maneuvering the car [19]. ADAS can be characterized by all the following: (1) support the driver in the primary driving task; (2) provide active support for lateral and/or longitudinal control with or without warnings; (3) detect and evaluate the vehicle environment; (4) use complex signal processing; (5) direct interaction between the driver and the system. Adaptive Cruise Control (ACC), Lane Departure Warning System (LDWS), Collision Avoidance System, Lane Change Assist, Automatic Parking System, and Automatic Emergency Brake are all examples of ADAS [19]. In general, three types of chips are adopted in ADAS: (1) sensor chips including video, radar, LiDAR, ultrasonic and infrared (IR), etc. ADASs require numerous sensors to accurately determine situational assessment and action implementation. For example, video sensors record the lane markings on the road. The record information is transformed and sent to central media processor in real time. The central media processor will evaluate if the vehicle drifts out of the lane and send out warning message to display and operation command through CAN bus; (2) automotive transceivers or data interface, such as radar transceiver, Dedicated Short Range Communications (DSRC) transceiver, CAN/LIN transceivers, Ethernet, etc. These chips are applied to form in-vehicle network for transferring detected information from sensors to processors and sending control signals from processors to the controllers. They can also be applied in communication between cars, infrastructure, and vulnerable road users to increase driver safety. The built network must provide dedicated secure safety channel operation to enable the secure communication of safety message and other data in real time. In future, it will also be connected to cloud service and help self-driving; and (3) microcontrollers and processors. Digital Signal Controllers (DSCs), Digital Signal Processors (DSPs), and many applicationspecific microcontrollers are responsible for processing, evaluating all the data sent through network, and then generating control signal to support the driver. For example, S32V vision processors from NXP are 32-bit MPUs offering an Image Signal Processor (ISP) and power 3D Graphic Processor Unit (GPU) for ADAS.

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SH7766 is similar image recognition SoC from Renesas with an SH-4A core, a distortion compensation engine, and graphics and image recognition engines. NXP semiconductors, Infineon Technologies, Renesas Electronics, and STMicroelectronics are the main IC suppliers for automotive electronics; the products in future market would be more distributed after Intel, Qualcomm, and Nvidia announced to engage in this field [20–22].

Rail Transit System Rail Transit System includes variety of transportation systems: railway trains, highspeed railways, and Maglev (magnetic levitation) trains, as well as trams (which runs on tramway tracks along public urban streets), subways, light rail, intercity trains, straddle monorail, new transit systems, etc. [23]. Urban rail transit system generally consists of rail route network, stations, running vehicles, traction system, maintenance base, communication system, supply and transformation system, station operation equipment, and the control and command center that is responsible for the coordination of the whole transit system. The wide application of all automation equipment in urban rail transit system has greatly improved the operation efficiency of the transportation system. For example, the automatic control equipment of the train can automatically command, track, dispatch, and drive the running train according to the actual situation. The automatic management of power supply system in rail transit system can be used for remote control and telemetry of the main transformer voltage station, the special substation for electric traction power supply for tram, and the equipment system for voltage reduction. Automatic environment monitoring system and fire alarm system can automatically control the station environment and trigger alarm according to the situation. The automatic ticket machine and ticket checking machine can replace manual ticket selling and checking. Each automation system forms its own internal network, which is coordinated and scheduled by the central control computer. Insulated gate bipolar transistor (IGBT) modules are used as main electronic and electric devices in high-speed railway, urban rail, and subway train systems [24–26]. The IGBT module in the auxiliary system can provide better DC/DC frequency conversion voltage isolation and DC power supply, so it is widely used in traction converters and various auxiliary converters as well as train air conditioning, ventilator, air compressor, battery charger, and lighting system.

Smart Grid Smart Grid is an electrical network consisting of various intelligent instruments, smart electrical equipment, and supplies of renewable energy and high-efficiency energy. The first official definition comes from the Energy Independence and Security Act, approved by the United States Congress in January 2007 (EISA2007) [27, 28].

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Fig. 20.2 The schematic of smart grid

The schematic of components of smart grid is shown in Fig. 20.2. In 2009, China State Grid Corporation proposed a project named “Strong Smart Grid.” “Strong Smart Grid” is a modern grid with ultrahigh voltage (UHV) grid as the backbone and supported by the communication platform. It covers all aspects of power generation, transmission and transformation, distribution and dispatching, and realizing the integration of “power flow, information flow and business flow.” The project is planned and completed in three stages: 2009–2010, pilot stage, planning and formulating standards of management and technology, development of key technologies, and equipment modulation; 2011–2015, comprehensive construction stage, speeding up the construction of ultrahigh voltage (UHV) power grids, distribution networks of urban and rural; and 2016–2020, a unified “strong smart grid” will be built in an all-round way [29]. The Smart Grid can quickly diagnose and determine solutions for a particular grid outage or blackout. The related technologies include distributed intelligent agents (control systems), analysis tools (software algorithms and high-speed computers), and operation applications (Supervisory Control and Data Acquisition, SCADA), substation automation, demand response, etc. Smart Grid has a huge demand for power devices and high-voltage IC products. Various IC products such as PLC chips can be used in controls, computers, power lines, and new technologies and equipment [30, 31].

Application of New Energy Sources New Energy Sources usually refer to renewable energy sources developed and utilized by new technologies. Renewable energy refers to the energy collected from renewable sources, such as solar, wind, tides, waves, and geothermal [32]. Renewable energy currently provides energy for four important areas: power

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generation, air and water heating/cooling, transportation, and rural (off-grid) energy services. Solar power generation systems mainly include solar cell modules (arrays), controllers, batteries, inverters, user-class loads, etc. [33]. According to the excitation mode, the inverter can be divided into self-excited oscillation inverter and otherexcited inverter. The main function of the inverter is to invert the direct current (DC) stored in the battery into an alternating current (AC). The inverter adopts a Synchronized Pulse Width Modulation (SPWM) processor through a full-bridge circuit. After modulation, filtering, and boosting, the alternating current that conforms the requirements of the state power market can be obtained for the end-users of the system. Wind power is a clean fuel source, sustainable and cost-effective; yet good wind sites are often located in remote locations resulting in challenges of equipment installation, facility management, and transmission of electricity. Tidal energy uses the gravitational pull of the Earth and Moon to generate electricity; wave energy uses the kinetic force of waves to produce electricity. Both wave and tidal power can be extracted from the ocean to generate electricity, by spinning a turbine similar as in hydroelectric dams or wind farms. Geothermal energy comes from deep inside the earth, due to slow decay of radioactive particles inside the earth. By 2013, more than 11,700 MW of large, utility-scale geothermal capacity was in operation globally, with another 11,700 MW in planned capacity additions on the way [34]. Various semiconductor materials, sensors, and ICs are used in different new energy systems such as photovoltaic (PV) system and large-scale grid-connected power station systems. In solar power generation system, powerline communication (PLC) chips can be used to acquire and transmit real-time, diagnostic data regarding energy output of individual solar panels to the array controller and subsequently to a solar farm control station, over the existing DC powerline [35].

Medical Imaging Equipment More and more imaging technologies have been applied to the medical field with the development of technology, helping doctors to better diagnose diseases, greatly improving the intuitiveness and accuracy of diagnosis. Currently the primary imaging technologies include Computed Tomography (CT), B-Scan UItrasonography, and Magnetic Resonance Imaging (MRI). 1. Computed Tomography (CT): CT imaging, combination of computer-processing technology and X-ray imaging, forms a tomographic image of a specific area of the scanned object from different angles, so that the internal condition of the object can be clearly seen without cutting it open destructively. CT is also known as CAT (computed assisted tomography) scanning; the technology was invented in 1972 by Allan Cormack of Tufts University and by Godfrey Hounsfield of EMI Laboratories; and they were awarded the Nobel Prize in Physiology or Medicine 1979 [36].

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Figure 20.3 shows the working principle of CT. A three-dimensional (3D) image of the object interior being scanned can be generated through digital image processing, which is derived from a series of two-dimensional (2D) X-ray images generated by a rotating detector around a single axis. X-ray of CT is the most common application for medical imaging, whose cross-sectional image can be used for a variety of medical diagnoses. Because there is a different obstruction of different body structures for X-Ray, CT will produce a series of operational data to determine different body structures. Although imaging is presented in the form of a cross-section or axis, namely, the configuration of the human body is presented in a vertical way, with the current image-processing techniques, this exact series of data can be used to reconstruct the cross-section and even display the body configuration in 3D. In addition to application in medical aspects, CT is also used in other fields, such as nondestructive testing (NDT) of materials and archaeological applications. 2. B-Scan Ultrasonography: B-type ultrasonic imager (B-ultrasound for short) is a two-dimensional imaging system of high-frequency acoustic ranging from 1 to 18 MHz; its schematic diagram of working principle is shown below in Fig. 20.4. The B-Scan technology was called Diasonography, invented in 1963 as the world’s first obstetric ultrasound machine, for the examination of the unborn, by Professor Ian Donald of the University of Glasgow, Scotland, UK. The first to appear is actually A-Scan Ultrasound Bionmetry (also known as Amplitude Scan), which is primarily used to measure the size of tumor. With the help of B-ultrasound, detailed imaging of various organs can be clearly displayed on the

Fig. 20.3 Schematic diagram of CT working principle

Fig. 20.4 Schematic diagram of B-ultrasonography working principle

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screen, to provide a visualized and reliable evidence for medical diagnosis; that is why, currently the B-ultrasound technology has been widely used in examinations such as obstetrics and gynecology examination, vascular disease examination, breast examination, thyroid examination, abdominal organs examination (liver, kidney, and gallbladder), prostate examination, and so on [37]. There comes one after another of new B-ultrasound technologies such as Color B-ultrasound, three-dimensional B-ultrasound, and four-dimensional B-ultrasound with the development of imaging technologies, leading to much more specific details in scanned images. 3. Magnetic Resonance Imaging (MRI) Scan: Raymond Damadian of State University of New York was first to perform a full body scan of a human being in 1977; Damadian invented the apparatus and method called nuclear magnetic resonance (NMR) and now well known as magnetic resonance imaging [38]. The medical imaging technology with the application of radiology uses magnetic resonance image to obtain electromagnetic signals from the human body and to reconstruct the information of it therefore to determine the physical condition of the target. It is proven that MRI is a highly universal imaging technology that can be used not only for the medical field but also in the domains of strong magnetic fields, radio waves, and so on. It is usually the hydrogen atoms that are used to generate a detectable radio frequency (RF) signal which can be received by the antenna in clinical research of MRI. The hydrogen atoms are known to be ranked among the top of others in human body and other biological organisms, especially in water molecules and fatty tissues. Out of this reason, the location of water and fat in the human body can be clearly displayed by most MRI scans. On the basis of the relaxation properties of hydrogen atoms, different tissues can be compared through changing the parameters of the pulse sequence. The composition of the MRI system is shown in Fig. 20.5. The signal processing, control, and display applications through medical imaging equipment have used a variety of IC products. In recent years, MRI combined with analysis of Machine Learning results in demand of additional ASIC design is a new trend.

Fig. 20.5 Composition of the MRI system

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Medical Electronic Equipment Traditional medical electronic equipment widely used in clinics may include X-ray machine and generator, and electrocardiography (ECG). 1. X-ray generators: X-ray is a high-energy photon beam. Its wavelength is extremely short, only 0.001–10 nm; its penetration ability is extremely strong. When X-rays penetrate the human body, different tissues result in different absorption rates for X-rays. Dense tissues, such as bones, absorb most of the radiation, and the corresponding areas of the film are lighter in color. Soft tissues, such as muscles, absorb less radiation, and these areas of the film are darker. Therefore, the X-ray machine designed and produced based on the X-ray has quickly become an important diagnostic tool in medical field, since its early time, and is widely used in the diagnosis of diseases such as fractures and gastrointestinal diseases [39]. German scientist Wilhelm Röntgen discovered X-ray on November 8, 1895; thus, X-ray is often called Röntgen radiation. Today, in the field of X-ray machine, digital radiography has the advantages of fast filming efficiency, low radiation dose, high-quality imaging effect, etc., and the traditional film X-ray machine was eliminated gradually. The digital X-ray machine system is mainly divided into four parts: diagnostic bed, high-frequency inverter power supply, console, and image-processing computer system. 2. Electrocardiography: Electrocardiography is the process of producing an electrocardiogram (ECG or EKG); electrocardiography instrument places electrodes on the body surface and detects heart signals through these electrodes. These electrodes detect small potential changes in the skin caused by the electrophysiological pattern of depolarization and repolarization of the heart muscle during each heartbeat. These electrodes are placed in the left leg, right wrist, left wrist, and chest. At present, ECG have been widely used in the medical field and have an irreplaceable position in cardiac testing projects. ECG machines have a long history [40, 41]. In 1887, scientists recorded electrical changes on the surface of the human skin caused by myocardial beating during the beating of the human heart. This record is considered to be the first electrocardiogram of human beings. In 1903, physiologist Willem Einthoven invented the first electrocardiograph called the “string galvanometer” at Leiden University. After a large number of clinical studies and animal experiments, Einthoven proposed a relatively complete theoretical model, linked the ECG signal to cardiac activity, and successfully interpreted the ECG results. Einthoven won the Nobel Prize in Physiology or Medicine 1924. The system structure of the ECG is shown in Fig. 20.6. ECG is a noninvasive, painless test with quick results. The tests are often done in a doctor’s office, a clinic, or a hospital room. They have become standard equipment in operating rooms and ambulances [42].

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Fig. 20.6 ECG machine system structure

Fig. 20.7 The typical system structure of the medical monitoring equipment

Medical Monitoring Equipment Medical monitoring equipment can be an electronic device that can observe disease condition or monitor some medical parameters in real time. Through continuous monitoring of the patient’s vital signs, the medical staff can better make a correct judgment of the patient’s physical condition and determine the appropriate treatment plan. According to the function, the medical monitoring equipment or devices can be divided into bedside monitoring equipment (for directly connecting with the patient in bed and monitoring patient’s condition in real time), discharge monitoring device (which is relatively small, easy to carry around, and can collect the patient’s medical information or data within a certain period of time), and central monitoring equipment (which can simultaneously monitor multiple objects over a network) [43, 44]. The prototype of the medical monitoring equipment, formerly the oscilloscope in the physics lab, appeared in the 1950s. After years of research and improvement, it has been finally applied to clinical medicine. The typical system structure of the medical monitoring equipment is shown in Fig. 20.7. Preset sensors allow for the monitoring of a wide range of physiological parameters. After the biomedical signal is converted into an electrical signal by the preprocessing module, it is processed and judged by the signal processing system, including interference suppression, signal filtering, and amplification. The electrical signal after the secondary processing can be visually displayed by the display device, and then subjected to sampling, quantization, and various calculation and

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consequent analysis, and the result is compared with the threshold set in the alarm device. When there is a critical situation, the alarm device can automatically notify the medical staff. In addition, the recording device can also archive the detected data, so that the medical staff can understand the changes in the patient’s physical condition. If some parameters need to be monitored, the built-in control system enables real-time monitoring [45]. Based on various applications, there are home medical monitoring equipment, hospital medical monitoring equipment, and patient medical monitoring equipment.

Medical Electronic Devices There are many kinds of medical electronic devices. Three types are introduced here: electronic sphygmomanometer, blood glucose meter, and pulse monitor. Electronic sphygmomanometer is a medical device which is commonly used in the household to measure blood pressure with modern electronic technology. The electronic sphygmomanometer has some advantages such as simple operation and self-tests at home. At present, wrist electronic sphygmomanometer is commonly used as shown in Fig. 20.8. It is a fully automatic intelligent electronic device, mainly including liquid crystal display screen, pneumatic pump and trachea, pressure sensor, controller module, and so on. The controller module generally uses a single chip as the control core, measures the air pressure through a pressure sensor, determines the actual diastolic pressure and systolic pressure according to the corresponding algorithm, and finally displays on the liquid crystal screen. The electronic sphygmomanometer in the market today has realized network management, which can transmit the measured data to the health management platform through the network, and generate the corresponding physiological reports for feedback to users; most of these sphygmomanometers are based on digital IC technology [46]. The future development direction of electronic sphygmomanometer is to improve the accuracy and portability, to facilitate more people to measure Fig. 20.8 Wrist electronic blood pressure monitor

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blood pressure and prevent diseases anytime and anywhere, and more importantly, to achieve continuous real-time blood pressure measurement without using a traditional balloon. Blood glucose meter is an electronic device for measuring blood sugar, especially for patients to detect blood sugar level and take correct measures to prevent life-threatening issues. In 1970, Anton H. Clemens, of the Ames Reflectance Meter (ARM) division of the Miles Laboratories in Indiana, developed the first blood glucose meter and glucose self-monitoring system [47]. The blood glucose meter has experienced five generations of development since it was invented in 1968. Its basic principle has evolved from light reflection method to electrochemical method which is widely used at present. Most modern blood glucose meters are minimally invasive or noninvasive. They use a fixed bias to stimulate the electrochemical reaction between the test paper and the blood to obtain a current signal. Then the chip measures the current signal, and then performs the operation and displays it as a digital output. Online data sharing, dynamic blood glucose testing, and noninvasive blood glucose testing are the main directions for the development of modern blood glucose meters. While convenient to use, they will further improve measurement accuracy, stability, and cost performance [48]. Pulse monitors can quickly detect diseases, especially cardiovascular diseases, by real-time monitoring of pulse conditions, so as to achieve the goal of protecting human health; there are variety of products to be chosen from in the market [49]. A pulse monitor is mainly composed of sensor, control unit, and display module. The control unit mainly uses single chip to read sensor data, confirm and display the number of pulses, and give prompts or warnings when abnormalities occur. At present, pulse monitors are mostly integrated into other wearable devices, such as sports bracelets. Besides pulse monitors, hand rings can also monitor ECG signals, respiratory rate, and so on. In addition, pulse monitors are also the basis of other physiological parameters measurements, such as blood oxygen measured by pulse value to get blood glucose value, which illustrates the importance of pulse monitors. In the future, pulse monitors need further development in expanding additional functions.

Implanted Medical Electronic Devices Typical implantable medical electronic devices [50] include cardiac pacemaker (CPM) and implantable nerve stimulator (or neurostimulator). 1. Cardiac pacemaker: Cardiac pacemaker is an electronic therapeutic instrument implanted in vivo to treat cardiac dysfunction caused by some arrhythmias. It is powered by batteries inside the instrument. The pulse generator in the instrument generates a pulse current of a certain frequency, which stimulates the myocardium

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through electrodes, and restores the normal expansion and contraction of the heart. In 1958, Arne Larsson (1915–2001) became the first to receive an implantable pacemaker, which completely or partially replaced the pacing function of the heart itself. He had 26 devices during his life and campaigned for other patients needing pacemakers [51]. With the development of technology, cardiac pacemaker has been continuously optimized. It has experienced the fixed rate pacemaker mode, on-demand pacemaker, atrial synchronous ventricular pacing, atrioventricular sequence inhibition pacemaker, physiological pacemaker, and other modes in the early 1960s. Since the 1980s, with the application of pacing mode with physiological pacing function, pacemakers with automatic control function have been developed rapidly. The emergence of digital pacemaker after the twenty-first century has made great contributions to the collection of clinical samples of heart disease and the research of treatment schemes. The basic components of cardiac pacemaker are pulse generator, electrode, main control chip, connecting wire, and battery. The function of pulse generator is to generate electric pulses with fixed intensity and frequency. Now it is commonly implemented in monolithic ICs. The role of electrodes is to transmit electrical pulses to myocardium, to stimulate myocardial cells to achieve the purpose of cardiac pacing, and then to sense the electrical signals of the heart and transmit them to the control part of the pacemaker in order to adjust the parameters to adapt to the physiological state. A similar implantable cardioverterdefibrillator (ICD) is a small battery-powered device placed in patient’s chest to monitor the heart rhythm and detect irregular heartbeats. An ICD can deliver electric shocks via one or more wires connected to patient’s heart to fix an abnormal heart rhythm [52]. 2. Neurostimulator: The implantable nerve stimulator [53] or neurostimulator is an electronic medical device installed on the body surface or in the body, for example, Cochlear Implant, and the Food and Drug Administration of the United States has authorized some implantable nerve stimulators to be used in clinical treatment, mainly Spinal Cord Stimulation (SCS) for pain relief; Deep brain stimulation (DBS) is mainly used in the treatment of Parkinson’s disease, tremor, and dystonia; Vagus Nerve Stimulation (VNS) [53] is used to treat epilepsy and depression; Sacral nerve stimulation (SNS) for the treatment of urinary incontinence, etc. In addition, the practice has proved that the implantable nerve stimulator can treat more than 20 kinds of nerve or mental diseases, and the effect is well known. The basic components of a neurostimulator are Implantable Pulse Generator (IPG) and electrodes that are mounted on one or two lead(s). IPG generates electrical pulses according to the parameters set by doctors, and the electrodes are responsible for transmitting the electrical pulses to the target nerve [54]. If the IPG and electrodes are far apart from the patient’s subcutaneous area, an extended wire is needed for signal transfer.

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Medical Robot Medical robots are specialized robots used in the medical sciences to assist with certain medical behaviors. Medical robots can be used in several medical and health fields, such as assisting surgery, locating microinjury locations in the body, and diagnosing and healing. It combines electronics, mechanics, and computer and medical disciplines and is the result of multidisciplinary cross-integration, which can greatly improve the efficiency of medical treatment. At present, there are many types of medical robots [55], with various components of doctor’s console, robotic arm system, imaging system, sensing system, communication system, data processing, and analysis system. These systems are mainly composed of a core processor and image-processing chips, and the sensing system includes MEMS medical sensors. In 1990s, the California Radiation Medical Center developed the first surgical robot PUMA 560 (Programmable Universal Machine for Assembly, or Programmable Universal Manipulation Arm), which can assist doctors in neurosurgical biopsy [56]. The emergence of the PUMA 560 opened a door for robots participating in the medical field. After PUMA 560, medical robots with different functions and capabilities have been developed according to different services and work contents. For example, in minimally invasive surgery, the surgeon can perform minimally invasive procedures by manipulating the surgical robot to improve efficiency and success rate of the procedure. In the postoperative rehabilitation process or the daily life of thedisabled groups, the rehabilitation robot can greatly reduce the work load of the nursing staffs. Service robots mainly include drug delivery automation robots, wheelchair robots, rescue robots, transfer robots, disinfection robots, nurse robots, etc., which are mainly used to replace people with simple repetitiveness and laborious work. After nearly 30 years of development, medical robots have been continuously improved and developed, and a relatively mature and complete medical robot system has emerged. Among them, the typical representative is the da Vinci surgical robot system developed by Intuitive Surgical of the United States, which is mainly composed of a surgeon console, a robot arm, and an imaging system [57]. With the rapid development of deep learning research in the era of artificial intelligence (AI), medical robots for disease diagnosis will become the main area of future research.

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Contents Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aircraft Flight Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications of ICs in Satellites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Military Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electronic Warfare IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Missile Guidance and Control Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Night Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avionics Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Airborne Early Warning Aircraft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Cognitive Sensors in Smart Robots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Robot Network Communication System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intelligent Manufacturing Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unmanned Aerial Vehicle System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binocular Vision System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Reality/Augmented Reality/Mixed Reality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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G. Liu (*) China Electronics Technology Group Corporation 14th Institute, Nanjing, China e-mail: [email protected] Q. Zhang Harbin Institute of Technology, Shenzhen, China F.-L. Yan Shenzhen Yixingbiao Technology Co., Shenzhen, China Y. He Shenzhen Institute of Micro-nano IC and System Application, Shenzhen, China C. Deng National IC Design Shenzhen Industrial Centre, Shenzhen, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_21

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Abstract

The applications of aeronautics, astronautics, military equipment, and the emerging areas strongly require reliable ICs, including power devices. For example, the GaN/GaAs-based RF circuit modules play an irreplaceable role in high-frequency applications, such as radar and electronic warfare ICs; a variety of compound semiconductor-based circuits are the important payload of the aircraft and spacecraft; the CMOS-based detectors expand the human sight into the infrared spectral range; and the emerging applications of artificial intelligence are putting forward the demand of computing platform with higher energy efficiency ratio, etc. This chapter introduces applications of ICs in various critical environment and presents the important roles of power devices in these fields. Keywords

High power · High frequency · Compound semiconductor device · Emerging applications

Radar Radar (radio detection and ranging) is an electromagnetic system that transmits electromagnetic signals, receives echoes from targets within its power coverage, and extracts position and other information from the echoes for target detection, target location, and target recognition [1]. The radar appeared in the mid to late 1930s. At that time, aircraft and ships were the main combat weapons of the warring parties. Detecting the orientation of enemy aircraft and ships and guiding their own aircraft for interception was an urgent task to perform. As the main means of detection, radars emerged and played an important role in World War II (WWII). After WWII, radar systems are still developed rapidly. In the military field, navigation, weapon guidance, battlefield reconnaissance, antimissile early warning radar systems have emerged; in the civilian field, there are radar systems for port traffic control, air traffic control, weather, and earth observation imaging. Today’s mainstream radars can operate from a few megahertz (MHz) to millimeter waves (mmW) and terahertz (THz). Phased array radar has become the mainstream system of modern radar [2]. The general development trend of advanced radar in the future is: (1) multifunctional integration: combined function of detection, communication, electronic countermeasures, etc.; (2) intelligent processing: radar information processing in relation to environment, target, and jamming; (3) functions defined by software: open architecture, reconfigurable software for different radar systems; and (4) system-on-chip (SoP): power amplifier, RF transceiver, and digital processing system on chip. The distribution of typical digital phased-array radar [2] and its use of IC are shown in Fig. 21.1.

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Fig. 21.1 Typical IC components and distribution in a digital phased-array radar

The ICs used in the radar system can be divided into four clusters, namely: power devices cluster, radio frequency (RF) chips cluster, digital chips cluster, and an optoelectronic chips cluster. 1) Power devices clusters: Microwave solid-state power devices have evolved from the first-generation silicon bipolar transistors (BJT) to the second-generation silicon MOS devices, the third-generation “wide bandgap” semiconductor materials for GaN, SiC power devices, and graphite semiconductor in the future [2]. Currently, solid-state high-power devices [3] are developing in the direction of wide bandwidth, high power, high efficiency, high linearity, light weight, small size, integration, and intelligence. 2) RF chips cluster: Radio frequency IC (RF IC) is mainly used in the transmit channel and receive channel of the radar receiving system. It includes a low-noise amplifier (LNA), mixer, gain controller, and other RF devices [3]. With the development of digital technology, ADC, DAC, DDS, DDC, FPGA, and other IC chips are widely used in digital receivers. The trend of RFIC is broadband, digitalization, and high integration. RF system-on-chip (RF SoC), which integrates RF front-end with digital baseband, will be widely used in phased array radar for its high integration, low power consumption, and low cost.

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3) Digital chips cluster: Various kinds of chips, e.g., processors, FPGA, dedicated ASIC, MCU, network switching, Flash, DDR, DC/DC, etc., are widely used in radar array processing, signal processing, data processing, display, and control subsystems. With the transition of radar array processing from high speed realtime and synthetic processing to general cluster processing platform, the heterogeneous multicore and reconfigurable computing will be the mainstream of the next generation processors. The development trend of protocol switching chips and interface chips is toward wider switching bandwidth, lower switching delay, and wider data transmission bandwidth. 4) Photoelectric chips cluster: In the current radar system, the transmit channel controls data and timing signals, the data from thousands of receive channels, and the digital processing platforms use optical fibers for data transmission and exchange. Small-signal RF/microwave photonic link technology is being developed. The development trend is the full signal link from RF microwave signals to digital signals. The digital radar based on all-photon technology will potentially transcend traditional radar.

Aircraft Flight Control Aircraft flight control (AFC) system is mainly used to stabilize and control the centroid motion (lift, forward, left, and right) and angular motion (pitch, yaw, and roll) of an aircraft. Aircraft generally refers to airplanes, but also includes airships, balloons, helicopters and rotorcrafts, etc. The AFC system and the aircraft constitute a closed loop, and the control and stabilization of the aircraft are based on the feedback control principle. In the loop, the controlled variables are the height of the flight, as well as its speed, lateral deviation, and attitude angle; the controlling variables are the displacement of the throttle rod and the deflection angle of the pneumatic control surface [4]. A typical AFC system is shown in Fig. 21.2.

Fig. 21.2 A typical AFC system

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The AFC system was developed through two stages: manual control and automatic control. (1) In the manual control stage, the pilot controls the throttle rod and control surface through the mechanical system of the aircraft to control the attitude and flight of the aircraft. In the automatic control stage, the aircraft is equipped with a flight control system which manipulates the throttle rod and control surface, thus controlling the aircraft flight automatically. In this process, the pilot is only required to carry out necessary monitoring and does not control the aircraft directly. (2) Automatic flight control system, also called advanced flight control system (AFCS), is the core of the AFC system [5, 6]. The four stages of development represent the development of the AFC system. In the first stage, AFC device developed from an automatic stabilizer to autopilot; in the second stage, an autopilot developed into an automatic control system; in the third stage, an adaptive flight automatic control system appeared; and in the fourth stage, an integrated aviation system was developed. AFCS was formerly found only on high-performance aircraft. Currently, due to advances in digital technology for aircraft, modern aircraft of any size may have AFCS. ICs and related components used in AFC system mainly include power supply components, inertial guidance components, internal memory, I/O interfaces, clock circuits, and interrupt controllers. With the rapid development of ICs, the structure of the AFC system is becoming increasingly complex, and its functions are becoming more and more comprehensive and powerful. The future development trend is to integrate parameter control such as speed, track, and attitude with various functions such as course keeping, automatic navigation, and terrain following/avoiding. These new functions should involve more complex IC designs.

Applications of ICs in Satellites The satellite is a celestial body that orbits a planet orbit and follows the closed orbit. The rapid development of science and technology has led to the emergence of artificial satellites. With the feature of high spatial location and wide coverage, artificial satellites can achieve a variety of military and civil applications such as communication, navigation, reconnaissance, broadcasting, observation, detection, and space test [7]. After several decades of rapid development, the satellite platform and payload are moving toward the trend of design generalization, function integration, object specialization, and processing intelligence. These trends require a high integration of functions in satellite systems. With the increasing integration of ICs and the use of new RF and power components, the quality of artificial satellites is getting higher and higher, and the volume is becoming smaller and smaller. It is possible to develop small satellites, microsatellites, nano-satellites, and even picosatellites. The common ICs for the satellite platform and payload are shown in Fig. 21.3. High-performance digital ICs include large-scale FPGAs, ASICs, CPUs, DSPs, SRAMs, and PROMs, which are used for signal processing, process control, logic operation, program, and data storage. Analog and RF circuits include amplifiers,

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Fig. 21.3 Common ICs used in the satellite platform and payload

filters, power management circuits, ADCs, DACs, phase-locked circuits, and modem circuits. Analog ICs are widely used, and they are mainly used for RF signal processing, analog-to-digital conversion, and control management. Hybrid ICs mainly include hybrid integrated DC/DC converters, decoding drivers, voltage drivers, voltage stabilizers, and bus transceivers. With the advancement of compound semiconductor (GaAs, InP, and GaN) design and process technology, microwave monolithic ICs (MMICs) have begun to be widely used in artificial satellite loads. For example, the use of various types of chips, such as GaAs monolithic amplifiers, monolithic mixers, monolithic phase shifters, and GaN power amplifiers, has greatly improved the reliability and integration of satellite loads. ICs for satellite applications should have aerospace reliability specifications for the corresponding orbit and life requirements [8], such as total ionizing dose (TID), single event latchup (SEL), and memory single event upset (SEU).

Military Communications Military communication is a kind of information transmission activity that the army utilizes comprehensively various means of communication to achieve a certain military purpose. It is also a basic means to ensure the command of the army. The basic requirements of military communication differing from civil communication are rapidity, confidentiality, reliability, and continuity. There are many kinds of classification methods for military communication. According to the different transmission media, it can be divided into wired and wireless communication, among which wireless communication can be further divided into microwave, scattering, laser, satellite and mobile communications, etc. According to the types of services carried, it can be divided into voice, telegraph, data and multimedia communication, etc. According to the requirements of

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communication support and the scope of contact, it can be divided into strategic, campaign, and tactical communications, etc. According to the different types of communication tasks, they can be divided into command, coordination, and logistics support communications [9, 10]. Military communication system [11] refers to the communication and liaison system established by using various military communication technologies to accomplish military tasks. Since the invention of telegraph in 1852 and telephone in 1876, communication technology has become an indispensable carrier of communication and command in the military field, bringing about significant changes in military communications and supporting the development of military science and technology. Since the World War II, especially after the 1960s, with the rapid development of various wireless technologies, especially digital programmable switching technology and computer technology, wireless communication modes (e.g., microwave communication, scattering communication), satellite communication and optical fiber communication have been combined with wired communication modes (e.g., data communication network and computer network). A multilevel distributed military communication network with core network, access network, and user equipment as the main body has gradually formed. Since the end of the twentieth century, driven by the continuous demand for space and ocean communications, the multidimensional space-earth integrated communication system with a multidomain, multi-network system, multimode, and multiservice has been gradually formed from space to underwater. The communication confidentiality, cognitive performance, and anti-interference ability have been continuously enhanced. The improvement of modularization, intellectualization, and miniaturization of military communication equipment cannot be separated from the promotion of IC applications. Especially since the 1980s, the progress and industrialization of microelectronics and semiconductor technology have greatly promoted the updating of solid-state devices and large-scale ICs, which affect directly the form and presentation of military communication technology and military infrastructure. The typical schematic block diagram of military communication system and equipment is shown in Fig. 21.4. Military communication system has experienced from the earliest use of discrete devices to build functional modules, to the largescale hierarchical use of ICs. It can be said that the development of microelectronics technology and the performance of IC products determine the capability of military communication system in terms of communication capacity, rate, coverage, and safety and reliability. The main ICs used in military communication system include central processing unit (CPU), digital signal processor (DSP), field programmable gate array (FPGA), mass memory, high-speed interface circuit (HSIC), high-speed and high-precision converter, etc. At present, the realization of communication processing function based on programmable system-on-chip (PSoC), also known as system-on-programmable chip (SoPC), has become the mainstream. Storage, conversion, and interface circuits are integrated together on the SoPC to form the single-chip baseband with processing capability. Radio frequency discrete devices and connecting components are highly integrated to realize integrated radio frequency chip so that the signal

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Fig. 21.4 Typical principle block diagram of military communication system and equipment

frequency conversion capability is formed. With the development of the thirdgeneration semiconductor technology, high-power density power devices and power monolithic circuits have been realized, resulting in better signal transmission capability.

Electronic Warfare IC Electronic warfare (EW) is a collective term for the applications of using electromagnetic energy to determine, detect, weaken, or suppress the enemy military’s use of the electromagnetic spectrum and protect its own applications. In the early twentieth century, EW technology has been developed more than a century since radio interference activity from British navy in the Mediterranean. In the World War I [12], only the simple direction-finding techniques were used. In the Vietnam War, new technologies of infrared (IR) and laser were used. In Gulf War and Kosovo War, EW entered the era of systemic confrontation. In the twenty-first century, EW is the main means of modern warfare and its importance has become more prominent. With the development of EW to electromagnetic spectrum warfare, networked collaboration, intelligent sensing, and precision attack will become the new features of future EW [13, 14]. Since the appearance of EW, electronic devices have been an integral part of EW equipment. In the early stages, from vacuum electronics to semiconductor discrete devices, from advanced RF, microwave, millimeter (mm) wave, and photonic devices to VLSI (very large-scale integration) ICs, these applications have largely supported the equipment of EW. In fact, modern microelectronic IC has become an important cornerstone of modern electronic information systems, while EW equipment is more dependent on a variety of advanced ICs and devices. Taking radar confrontation as an example, ultra-wideband (UWB), high-dynamic/ high-power RF systems, and broadband phased array systems require extensive use of various advanced microwave and mmWave broadband IC, such as gallium

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arsenide (GaAs) with broadband performance, low-noise amplifiers, gallium nitride (GaN) power amplifiers, and monolithic ICs (MMICs) such as switches and phase shifters. UWB ICs that instantaneously cover RF, microwave, and mmWave, such as UWB low-noise amplifiers (LNA), wideband frequency synthesizers, UWB mixers, etc., are the essential components for UWB reconnaissance receiving systems. For example, UWB receivers developed by WJ Corporation of the United States use many UWB microwave ICs, and their operating frequencies cover all frequency bands from RF to mmWaves. Advanced digital IC is another key component indispensable for wideband digital multi-beam reconnaissance and jamming system, and it is the basic guarantee for the accurate reconnaissance and interference function of EW equipment, including ADC, DAC, FPGA, and ICs such as DSP, high-speed data memories, and high-speed interfaces. Similarly, digital radio frequency memory (DRFM) implemented by the above IC is recognized as a “radar buster” because of its ability to quickly store and accurately replicate threat signals. In addition, new microwave photonic IC devices with broadband advantages can greatly expand the spectrum adaptation range of EW equipment and to create a new capability for EW. With the development of nano-electronics, heterogeneous and three-dimensional (3D) integration, integrated with antenna, RF, acquisition, signal processing, power management, and control, it can achieve system-on-chip (SoC) integrated microsystems with multiple functions. It will become a new demand for the development of EW, and it will also promote the rapid development of EW equipment towards intelligence, networking, and miniaturization.

Missile Guidance and Control Systems Missile guidance and control system is a system that applies various methods to guide a missile to its predetermined target. It is composed of missile guidance and missile attitude control systems. Missile guidance system includes a measuring device and a calculating device. It measures the relative position or speed of a missile and its target, calculates according to the predetermined guidance law, and generates guidance signals to guide the missile to reach its target. Missile attitude control system includes a sensing device, a calculating device, and an actuator. Its main function is to ensure the stable flight of the missile accept the guidance signals transmitted by the guidance system, control the flight attitude angle of the missile, adjust its movement direction, and ensure the missile hits the target accurately [15, 16]. The classification of missile guidance and control systems is shown in Fig. 21.5. The concept of the missile guidance and control system can be traced back to the World War I (WWI), when airborne bombs were guided remotely to their targets. By the end of WWII, the V-series missiles developed by Germany used a simple guidance system for the first time. The V-1 missile was guided by autonomous magnetic gyro and used mechanical controls. The V-2 missile was mainly controlled by radio. The radio control, which is vulnerable to interference and requires

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Fig. 21.5 Classification of missile guidance systems and control systems

complicated equipment, is not suitable for modern warfare. Since 1950s, with the continuous improvement of the accuracy of inertial instruments, as well as the rapid development of error separation and compensation techniques and computer technology, the inertial guidance system becomes more popular and has been used by ballistic missiles worldwide to improve their accuracy. During this period, other guidance methods, such as infrared (IR) and laser guidance, have also developed. In 1970s and 1980s, the compound guidance method was used more widely, and the missile hit accuracy was improved greatly. For example, the Trident II ballistic missile developed by the United States used inertial and celestial guidance, and achieved a hit accuracy deviation of 400 m, which was improved by an order of magnitude than in 1950s and 1960s. Since the Gulf War in early 1990s, the precision guidance system and responsive control system have been used widely, so the missiles can now achieve extremely high hit accuracy and the combat effectiveness has been improved. ICs and related components used in missile guidance and control system mainly include a CPU (central processing unit), DSPs (digital signal processors), RF microwave devices, memory chips, IMUs (IR measurement units), FPGAs (field programmable gate arrays), analog/digital converters, and digital/analog converters. In 1962, Texas Instruments developed 22 sets of ICs for the US Minuteman-I and Minuteman-II missiles, which was the first application of ICs in missile guidance and control systems. At that time, only small-scale ICs were used, namely simple diodes, transistor logic circuits, NOR/NAND circuits, trigger circuits, etc. With the improvements of the missile guidance and control performance requirements and the rapid development of ICs, and information processing technology, medium-scale integrated (MSI) and large-scale integrated (LSI) circuits are being used more widely. The guidance and control system of the US MX missile used complementary metal-oxide semiconductor (CMOS) MSI and LSI ICs. At present, as the third-generation semiconductor materials (e.g., GaN) are used more widely in ICs, the performance of missile guidance and control systems will be further improved.

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Infrared Night Vision Infrared (IR) night vision is based on photoelectric conversion or thermoelectric conversion effect. It receives IR radiation from natural objects through a specific IR detector, converts the IR radiation of the object into a weak electrical signal, and performs signal processing through specific amplification and enhancement, and finally the imaging display process to form image on display [17, 18]. Therefore, IR night vision can also be called IR thermal imaging or IR night vision imaging. Based on the wavelength distribution, the IR ray is in a wavelength region other than the red wavelength, the wavelength of the IR ray is 0.76 μm to 1 mm, its shortwave end is close to the visible light, the long-wave end is nearby to the millimeter (mm) wave of the radio wave, and both of visible light and radio wave are the part of electromagnetic spectrum [18]. According to the working mechanisms, IR detectors can be divided into heat detectors and IR photon detectors. Heat detector is based on thermoelectric effect. Under the action of the external bias signal of the detector, the processing circuit converts the temperature of the detector or other physical behaviors caused by the temperature to achieve the conversion between radiation signal of the object and electrical signal, and to detect the IR radiation from objects. The heat detector has a wide spectral response range for IR radiation, and it performs no significant wavelength selectivity. IR photon detector is based on the absorption of the IR radiation of the relevant band by the IR sensitive material, and the bound electrons in the material are excited into conduction electrons, and processed by the subsequent circuit of the detector, then form electrical signal, and finally the output. In order to successfully reach the photoelectric conversion of IR radiation of the IR photon detector, the IR radiation photon must meet certain energy requirements, so the IR photon detector has wavelength selectivity to the IR radiation. In order to realize high signal-to-noise ratio and high-resolution imaging requirements for IR night vision, it is necessary to finely process the weak electrical signals generated by the IR radiation absorbed by the IR detector (such as analog domain or digital domain preprocessing, amplification, etc.). Through the multiplex processing, a signal output with specific format that is easily received and processed by the back end processing circuit is created. Therefore, IR detector needs to be equipped with a special IR low-temperature, low-noise amplifier (LNA) circuit to achieve high signal-to-noise ratio amplification and driving of weak electrical signals generated by IR sensitive elements. As the pixel unit size of the IR detector array is further expanded, the sensitivity is further improved, and the function is further increased, it is required to perform signal processing such as high-gain and low-noise amplification on the weak electrical signal generated by the IR radiation of the object received by the IR detector array. Therefore, an application-specific IC with unique properties such as low noise, low power consumption, and low temperature operation are required. The circuit processes the weak electrical signal output by the IR detector array, mainly including pixel level processing (input, integration, etc.), row and column amplification and conversion (amplification, multiplexing, etc.), and detector array signal

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buffer output, etc., thereby forming analog signal output, or perform as a digital signal output after analog/digital conversion. Such specific IC is called an IR focalplane readout IC [19]. The IR focal-plane readout circuit is a special IC that is typically designed and fabricated by using standard complementary metal-oxide semiconductor (CMOS) technology [20]. The block diagram of the infrared focal-plane readout circuit is shown in Fig. 21.6. The interconnection of the IR focal-plane readout circuit and the IR array chip is shown in Fig. 21.7. Generally, the IR focal-plane readout circuits use the indium (In) column flip-chip interconnection method to realize the connection with IR sensor photo-sensor array and the input of the weak signal, completing the detection and signal output of the IR radiation signal, and finally achieve highperformance IR night vision imaging by external signal and image processing.

Fig. 21.6 The block diagram of the infrared focal-plane readout circuit

Fig. 21.7 The block diagram of the interconnection of the IR focal-plane readout circuit and the IR array chip

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The IR focal-plane readout circuit based on CMOS IC and process technology integrates nonuniformity correction, scene-based parameter adaptive matching, and digital enhancement processing on the chip, which will greatly enhance the IR night vision imaging technology and performance of the equipment with high sensitivity, high integration, high working frame rate, and full digitalization.

Avionics Instruments Avionics instrument is the general term of all instruments on the aircraft which provide relevant information for the pilot. The pilot controls the aircraft based on the information from the avionics instruments. Avionics instruments [21] in turn demonstrate the results of the pilot’s control. The classification of avionics instruments are shown in Fig. 21.8. The development of avionics instruments can be divided into four stages: mechanical instruments, electrical instruments, electromechanical instruments, and digital display instruments. (1) Mechanical instruments have single direct-reading structures with each component, are mechanical, and can only measure a single parameter. After 1930s, avionics instrument gradually developed into electrical instrument. Different from mechanical instrument, the sensor and the indicator are installed apart and connected through signal transmission. (2) Electrical instruments use electrical transmission instead of mechanical drive as obvious advantages of improved reaction speed, transmission distance, and accuracy, and reduced volume. (3) Electromechanical instruments appeared after 1940s. The feedback principle is used to ensure consistent input/output for improving sensitivity and accuracy. (4) Aviation instrument has gradually developed into electronic display instrument due to the rapid development of electronic information technology. Its basic Fig. 21.8 Classification of avionics instruments

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structural unit is a low-power servo system for signal conversion, calculation, and transmission. At the same time, as the types and quantity of aviation equipment increase, most aviation instruments are now integrated with display instruments. ICs and devices used in aviation instrument mainly include microprocessor chips, ADC, DAC, and various sensors concerning pressure, temperature, and inertia. Due to the increasing demand for miniaturization, microelectromechanical system (MEMS)-related technologies are being used more widely in the sensors applied in aviation instrument [22]. The future development trend of aviation instruments is intelligence, network, and openness. With the development of computer technology, the architecture of distributed control system (DCS) [23] has been continuously improving. Digital and open DCS will gradually be applied to aviation instruments. The traditional DC analog signal transmission will be replaced by two-way digital communication in the bus, and then intelligent transmitter and intelligent actuator will be applied. The range and accuracy of aviation instruments will be greatly improved as well as further improved reliability and usability. DCS is like supervisory control and data acquisition (SCADA), but DCS tends to be used on large continuous process system where high reliability and security are required.

Airborne Early Warning Aircraft Airborne early warning (AEW) aircraft is a special mission aircraft equipped with AEW radar [24, 25]. Its initial operational function was to compensate for the low-altitude detection blind areas of ground or shipborne radar through its airborne radar. As military demands increase and electronic technology and aviation technology improve, modern AEW aircraft has been equipped with advanced airborne longrange AEW radar to complete its mission of battlefield early warning and detection tracking. It is also equipped with various electronic systems for communication navigation, command and control, friend or foe identification, electronic reconnaissance, and electronic warfare, etc. It can not only detect and track various types of invading air and sea targets at an early date but also guide and control allied war crafts and other weapons. Modern early warning aircraft can be classified as landbased fixed-wing AEW aircraft, ship-based fixed-wing early warning aircraft, shipbased rotor-wing AEW aircraft, etc. AEW aircraft first appeared by the end of World War II. After more than 70 years’ development, it has now developed to the third generation and is entitled “the Air Commander,” which obviously shows its core status and importance in the combat system. At present, the representative third-generation AEW aircraft in the world mainly include the United States’ E-2D, Russia’s A-100, Israel’s G550 “Gulfstream,” and China’s KJ-2000 [25]. These AEW aircraft have the technical characteristics of “networked, diversified, integrated and lightened,” and can unify and manage comprehensively the resources based on the battlefield situation. They can multiply the system combat effectiveness and have become the core strength of modern information combat system.

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Mission electronic system is the foundation of AEW aircraft’s functions, and ICs and related devices are the important parts of mission electronic system. For example, CPU chip, digital signal processing chip, digital/analog conversion circuit, radar raster scan display, memory, solid-state microwave power device, microwave low-noise receiving circuit, microwave oscillator, and some special ICs form the basis of electronic system’s functions. The solid-state microwave power device is helpful to bring radar detection, communication navigation, electronic detection, confrontation, and other electronic systems into all-solid state. Subsystems consisted of microwave devices such as transmitter, receiver, antenna system, and display can be used in radar, electronic warfare system, and communication system. In addition, low-phase-noise microwave oscillator is one of the most important factors that affect the radar range of electronic system. As operational environments and operational needs change sharply, airborne early warning aircraft’s position in the whole combat system and its technology form will change drastically as well. System operational environment, which is based on the information system, requires early warning aircraft to develop from single platform combat to systematic confrontation. This puts forward new and higher requirements to the electronics in AEW aircraft. At present, major IC technologies represented by nano-electronics, the third-generation semiconductors, and integrated micro-systems enable electronic devices to develop towards miniaturization and integration. With these new technologies and products, the AEW aircraft can be further developed for reduced volume, weight, and energy consumption, as well as more integration in functions.

Environmental Cognitive Sensors in Smart Robots In practical application scenarios, smart robots need to recognize the surrounding environment. Smart robots should not only be able to avoid obstacles through environmental cognition but also can extract, understand, express, and reason relevant environmental knowledge. Environmental cognition enables a smart robot to have the ability to correct its own position and deduce relevant environmental knowledge. The simultaneous localization and mapping system (SLAM), first proposed by Smith, Self, and Cheeseman in 1986 [26–28], has been regarded by many scholars as the key to truly realizing fully autonomous mobile robots. SLAM usually refers to the acquisition, calculation, and fusion of various sensor data to generate position, attitude position, and scene map information. SLAM is widely used in service robots, unmanned aerial vehicles, and other fields, supporting the mobility and interaction ability of robots and other systems. There are many kinds of robot environmental cognitive sensors, among which lidar, vision sensor, and ultrasonic sensor are widely used. The laser radar can directly provide the distance information between the robot body and the surrounding obstacles with fast measurement speed, high precision, and small calculation. The laser radar ranging mainly has the pulse and phase types of ranging. Pulse ranging can determine the distance between the laser radar ranging

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system and the target object by directly measuring the time of the laser pulse transmitting back and forth from the laser radar ranging system to the target object. Such sensors are expensive. By measuring the phase change of the continuously modulated light wave when it propagates back and forth between the laser radar ranging system and the target object, the time is indirectly measured. Therefore, it can calculate the distance between the laser radar ranging system and the target object. Such sensors are less expensive. In the intelligent machine cognition system, the vision sensor provides the most outside information to robots. With the rapid enhancement of CPU and GPU capabilities and the improved performance of visual sensors, the high-precision real-time visual perception technology has been advanced significantly. The research on vision sensor mainly includes monocular camera, binocular or multi-eye camera, and depth camera (RGB-D). In addition, there are special vision sensing methods such as fisheye, panoramic, and so on. In general, to reduce the computational load of visual image matching, the information measured by other inertial units can be combined for fusion processing. Monocular camera is low cost, but its biggest drawback is that it cannot accurately provide the depth information of the target object. Binocular cameras can estimate depth information, thus eliminating the disadvantages of monocular cameras. The configuration and calibration of binocular or multi-lens cameras is complex, and the depth range is also limited by the camera’s baseline length and image resolution. As a result, the calculation of depth calculation is complicated, and the overall cost of the system is high. RGB-D camera is a composite camera that uses structural light source to perform environmental irradiation and uses consistent structural light geometric information to realize distance resolution after imaging by plane array sensor. Its outstanding feature is that it can directly give depth information, so it can provide more direct information than monocular cameras and binocular cameras. However, most RGB-D cameras still have some disadvantages, such as large distance measurement noise, limited field of vision, and less measurement range [29]. Ultrasonic sensors are widely used in obstacle avoidance of mobile robots. Ultrasonic sensors have many advantages. They can not only transmit in many materials but also are less affected by the environment and have good directivity. Therefore, mobile robots with ultrasonic sensors are widely used in many fields, such as industry, biomedicine, and national defense.

Robot Network Communication System With the development of science and technology, the application field of robotics is expanding constantly. At the same time, higher requirements are put forward for the reliability and stability of robotic data communication. Considering the multi-node, distributed network, long distance communication, harsh environment, real-time performance, and high reliability required by industrial communication, CAN, EtherCAT, PROFINET, and ROBBUS have gradually become the main means of robotic communication networks.

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The controller area network (CAN) is one of the most widely used industrial fieldbuses [30]. Due to the high reliability and stability, it has been widely used in industrial automation, ship, medical instrument, multi-sensor measurement and control, and other fields. CAN controller is used to generate CAN communication protocol frame and convert data frame into binary bit stream, which is transmitted to CAN transceiver and sent out. In general, CAN controller integrates logic controller, FIFO, and CAN protocol core controller. Ethernet for control automation technology (EtherCAT) is an open architecture fieldbus system based on existing Ethernet. EtherCAT industrial Ethernet has flexible topological structure and low development cost, and its added real-time channel makes data transmission more efficient and high speed. The implementation of EtherCAT master station is relatively simple, requiring only a network interface card or a network card integrated with the computer motherboard. EtherCAT master stations are generally supported by real-time operating systems (RTOS) running on platforms such as ARM/x86/ZYNQ. EtherCAT takes the communication mechanism of “centralized frame” for reference in data frame processing. It extracts the data related to the machine from the address of the station according to the field bus memory management units (FMMU) and at the same time uploads the feedback data to the address. EtherCAT extends the protocol support for CAN and serial communication servo system on the application layer protocol toward zero cost communication across the bus [31]. PROFINET (a portmanteau for Process Field Net) is an automatic bus standard based on industrial Ethernet technology, which is widely used in motion control, distributed automation, fault safety, network security, and other automation fields [32]. According to application scenarios, PROFINET can be divided into PROFINET component-based automation (PROFINET CBA) and PROFINET IO (related to number of I/O points). PROFINET CBA is suitable for software-based communication scenarios based on TCP/IP protocol, while PROFINET IO is suitable for application systems requiring real-time communication support, and the two can coexist in a network at the same time. In order to meet the requirements of high real-time applications in the robot field, PROFINET provides users with a real-time data transmission channel. Under the real-time channel, PROFINET real-time communication (RT) response time fell to 5–10 ms, and PROFINET isochronous real-time (IRT) technology, under the condition of 100 nodes, lowered the typical response time to 1 ms, able to meet the response requirements of high-speed motion control systems [33]. The robotic communication bus (ROBBUS) is a standard proposed by China machinery industry federation in June 2010 and organized by China institute of automation. ROBBUS adopts several ISO11898-1:2003, ISO11898-4:2004, and ISO11898-5:2007 standards associated with CAN [34]. The standard bus is designed for low-cost, modular robots, is a masterless bus, with good real-time, expandability, and strong anti-interference ability. It is suitable for the communication between modules in the modular robot system and has multichannel property. The standard specifies the data format and program specification of the communication bus in the modular robot system, including protocol level, format definition, and workflow.

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Intelligent Manufacturing Systems Intelligent manufacturing system (IMS) refers to an intelligent system that can conduct a series of intelligent activities like human beings, such as inferring problems, analyzing problems, and making decisions in the manufacturing process [35]. IMS is designed to perform manufacturing processes with various components of intelligent, flexibility, and the use of technical means (e.g., artificial intelligence (AI) to learn and mimic human thinking activity), so that they can replace part of the human’s mental work further for automatically adjust parameters in manufacturing to achieve optimized conditions. In 1980s, the United States put forward the concept of intelligent manufacturing, which was highly concerned and valued by various countries and regions. All countries and regions in the world have included intelligent manufacturing into the future development plans of their countries or regions, successively launched specific R&D programs, increased investment in scientific research, and promoted further implementation of intelligent manufacturing. Some important concerns in IMS have been reviewed in a recent article [36]. With the rapid penetration of information technology (IT) into manufacturing, modern industrial informatization has entered the stage of intelligent manufacturing. Enterprises worldwide in various fields continue to speed up integrated innovation, promote the continuous reform of production management and business model, and form a series of new models, new forms of business, and new characteristics in the field of intelligent manufacturing [37]. Industry 4.0 is a project proposed in 2011 by the German government, aiming to improve the intelligence level of the manufacturing industry, integrate the resources of customers and business partners in the business and value process, and build a smart factory with adaptability and resource efficiency. Industry 4.0 is based on the Internet and the Internet of Things (IoT) system, from centralized control to distributed enhanced control mode, to establish a highly flexible personalized and digital production mode of products and services. The Industry 4.0 term also refers to the fourth industrial revolution, from intelligent factory, intelligent production, intelligent logistics, new materials and smart technologies, logistics, etc. The Fourth Industrial Revolution are technologies and systems such as artificial intelligence, machine learning, 3D printing, the Internet of Things, virtual and augmented reality, big data, and mobile networks [38].

Unmanned Aerial Vehicle System The unmanned aerial vehicle (UAV) is a kind of powered, unmanned aircraft, which can fly autonomously or remotely, and can be used once or repeatedly. It is also called “aerial robot” [39]. The UAV can fly in unmanned conditions by using radio remote control equipment and self-equipped process control devices. At the same time, it can complete complex flight missions and load tasks. Frame components, flight control system and sensor equipment, data communication system, power supply system, launch and recovery system are indispensable

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Fig. 21.9 Unmanned aerial vehicle system framework and IC diagram for use

parts of the UAV system. The architecture of the UAV system and the IC used are shown in Fig. 21.9. The UAV flight controller mainly includes the UAV attitude measurement, stability control, airborne mission management, and fault-tolerant calculation modules. The flight control system hardware includes GPS module, inertial measurement unit, barometer and ultrasonic measurement module, embedded CPU, motor drive regulator, communication equipment, etc. Currently, famous open source projects of flight system include Paparazzi UAV project, Dronecode/PX4 project, OpenDroneMap project, and Drone Journalism Lab. The UAV data communication device is mainly responsible for performing the remote control of the UAV and information transmission function of the airborne sensor device data, including the digital radio station, picture transmission radio, remote control and receiver, ground station system, etc. A typical communication scenario for a drone is shown in Fig. 21.10 [40]. The UAV power drive device includes motors and electronic speed control (ESC). ESC controls the speed and power of the motor or engine of UAV. At present, the ESC of UAV in the market also has auxiliary functions such as starting protection, battery protection, auxiliary braking, etc. Sensor equipment carried by UAV is the necessary hardware equipment for UAV to realize automatic detection, control, and stable flight. These sensors mainly include vision sensor, IR sensor, ultrasonic sensor, millimeter wave (mmW) radar, barometer, GPS/GLONASS, other positioning sensors, IMU and compass dual redundancy sensors [41], etc. They can help UAV acquire real-time image, depth, location, and other information during flight, construct 3D map around the aircraft, and determine its own location. The UAV battery management system is one of the core issues to optimize the duration of UAV. It is mainly composed of instruction control chip, MOS tube, battery management chip, and other devices, and combined with the corresponding embedded software. At present, the main power management

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Fig. 21.10 A typical communication scenario for UAV

devices in the market include discrete power management chip (PMIC) and integrated power management unit (PMU). For example, TI’s BQ30Z55 series chips are commonly used in power management system of the UAV intelligent lithium battery [42]; in addition, some well-known devices include power controller IC (e.g., MC3377x system from NXP) and power monitor (e.g., ADM66xx series from ADI) are also in adoption.

Binocular Vision System Binocular vision system uses two cameras with different positions to shoot images from different perspectives, calculates the matching relationship of the pixels one by one through matching algorithm, and then obtains the depth information of the object image according to the offset between the matching points, and then constructs the three-dimensional (3D) information of the image. Compared with some existing 3D information acquisition methods, binocular vision technology requires simple equipment, only ordinary cameras, and does not need to actively emit light, which is conducive to reducing overall power consumption. Binocular vision system technology includes binocular matching, visual positioning, depth map fusion, high-level applications, and other different levels according to the implementation process [43]. Depth image acquisition based on binocular matching is the basis of binocular vision system. In the scene with fixed camera position, the depth map obtained by binocular matching can be directly used for attitude recognition and other tasks and has important applications in the field of human-computer interaction. In mobile platform scenarios, the location of the camera is another basic task. Based on binocular vision technology, the motion trajectory of the camera can be restored by time correlation of depth map sequence,

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and then used in autonomous navigation, 3D fusion, and other high-level applications. It has important applications for mobile robot platform [43]. At present, in the actual use of binocular vision technology system, the most important problem is real-time capture and accuracy. Firstly, extracting 3D information from binocular images is a complex algorithm problem, which is vulnerable to nonideal factors, e.g., noise and occlusion in real scenes. In addition, the binocular vision correlation algorithm has a high computational complexity, and the traditional general-purpose processor cannot meet the requirements of real-time processing. To solve the above problems, most of the research work only optimizes the accuracy of the results from the algorithm level, which is based on general purpose processors and cannot achieve real-time processing. To solve the real-time problem, parallel computing is another hot research direction in this field. The common parallel computing devices are FPGA (field programmable gate array) and GPU (graphics processing unit). Among them, due to the high flexibility of computing and storage structure, the FPGA can better meet the needs of parallel image processing for high parallelism and high internal bandwidth [44], so it has been widely used. The real-time processing of high-resolution images can consider GPU parallel computing, which can effectively improve the speed of multitask operation. Some progress has been made in these areas [45]. At present, products in the market support 3D depth of field calculation, binocular image matching, and visual positioning and related processing algorithms.

Virtual Reality/Augmented Reality/Mixed Reality Today, these terms, VR (virtual reality), AR (augmented reality), MR (mixed reality), and CR (cinematic reality), are no stranger to people. The VR visions that are computer-generated are actually false; the AR is to enhance the reality; the real world and the virtual world mixed together to produce a new visual environment in real-time is MR; while CR is a pre-step producing a cinematic effect for MR. 1) Virtual reality (VR): Virtual reality (VR) refers to the use of a computer, which generates a virtual environment. VR enable users to “invest” into the environment through a variety of dedicated devices and directly interact with that specified environment. VR technology allows users to use human’s natural skills to perform in the virtual world, while providing visual, hearing, touch, and other intuitive and real-time natural perception. The current mainstream VR products are HTC VIVE and Oculus Rift Headsets, which generate realistic 3D images from software through high-performance computers and graphics processing unit (GPU), and the illusory scenarios are finally displayed in VR glasses [46]. The block diagram of HTC VIVE headsets display is shown in Fig. 21.11. Virtual reality can be widely used in the games, education, entertainment, training, travelling, designing and simulation training, etc. 2) Augmented reality (AR): Unlike the full immersive effect of virtual reality, AR is dedicated to creating a world of virtual and real. It superimposes

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Fig. 21.11 The block diagram of HTC VIVE headsets

computer-generated objects onto real scenarios, providing users with a hybrid scene of virtual information and real scenes through optical perspective helmet displays, glasses, projectors and mobile phone screens, etc. Google has released Google Project Glass AR glasses, while observing the surrounding environment, the glasses can take the photos by sound control, obtaining environmental information such as weather, location, etc., as well as access to the Internet and emails checking. AR has a wide range of applications, such as assistance information, traffic navigation, CAD interfaces supporting and training or learning understanding enhancement. Several good AR glasses are listed for 2019 [47]. 3) Mixed reality (MR): Mixed reality (MR) is designed to integrate the virtual world with the real world. The wearable helmet display and other devices provide the basic tools for immersive observation of mixed reality scenes, and the computer provides virtual and real fusion scene that is compatible with user’s observation. The generation of virtual and real fusion scenes is essentially the mutual embedding of different spatiotemporal scenes, referring to geometric consistency and illumination consistency. MR provides a natural interface for users to interact with virtual world. By understanding human actions and behaviors, MR builds the bridge between users and virtual worlds of reality, objectively providing intuitive connection between virtual world and real world. In a world of virtual and reality, human’s intelligence can understand the truth by observing the mixed scenes of virtual and real, driving the virtual world on demand by natural interactions, and obtaining scene or data feedback from computer. Finally, MR achieves the immersive deep interaction between human and computer, and then results to deep integration of machine intelligence and human intelligence. MR involves both VR and AR technologies; some known companies in the world may include Facebook, Microsoft, Google, Samsung, Sony, Nintendo, Huawei, and others.

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AI System Artificial intelligence (AI) is a discipline that studies, develops, and simulates theories, methods, techniques, and applications of human intelligence. Research on AI systems includes robotics, speech recognition, image recognition, natural language processing, expert systems, etc. At present, ICs are widely used in AI systems. For example, the MultiSense S7 sensor is used in the head of the Boston Atlas robot for front view. In addition, in the field of deep learning, graphics processing units (GPUs) use their unique parallel computing architecture to significantly reduce model training time under big data samples, greatly saving development resources. As a special processing chip tailored by TensorFlow, the 2016 deep learning framework for deep learning, the tensor processing unit (TPU) has played an important role in artificial intelligence projects. Companies such as IBM and Samsung have also developed dedicated chips for AI. It can be said that the development of AI and the development of ICs are the same, driven and promoted. The overall schematic diagram of the AI computing system is shown in Fig. 21.12. The graphics processor, also known as the display core, is a microprocessor that performs image computing operations on personal computers, workstations, game consoles, and some mobile devices. In 2006, NVIDIA and ATI (merged with AMD in 2006) introduced the Compute Unified Device Architecture (CUDA) programming environment and Close-To-Metal (CTM, originally called “Close-to-theMetal”) programming environment, respectively. As a new computing architecture, CUDA enables GPU to quickly solve complex computing problems [48, 49]. TPU is a processor designed by Google for machine learning (ML). As the core discipline of contemporary artificial intelligence, ML has spread throughout our agenda. The high-performance source of TPU is its nonuniversal design logic (quarterly single design principle), which uses dedicated logic circuits, single work, and fast speed. With the same transistor capacity, the TPU can run more operations per unit of time, resulting in smarter results by using more complex and powerful machine learning algorithms. In real life, many applications in Google use TPU and have achieved very good results, such as Google Street View and AlphaGo, etc. In early 2019, Google announced TPU-based TensorFlow V2, which can run on multiple CPUs and GPUs with CUDA, and on Google Cloud Platform [50]. In 2011, IBM first proposed the Artificial Brain Project, which aims to develop a complete AI system to simulate human behavior. The system innovatively developed the advanced chip TureNorth that mimics the human brain neural network. In

Fig. 21.12 Overall schematic diagram of AI system

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this project, the IBM neuron is the basic processing unit, the size and stamp size are equivalent, the power consumption is only 65 mW, but it integrates one million spiking “neuron” circuits [51]. The biological signal processor is a dedicated processor equipped with a bio-signal sensor that can receive and process human biological signals. These new processors are still in their infancy and are only used in medical fields and mobile wearable devices [52]. Bio-Processor, a bio-signal processor released by Samsung at the 2016 CES conference, uses the latest bio-signal fusion technology. The technology is based on enhanced data conversion resolution and wide-area dynamic range to capture biological signals that are faint and easily disturbed.

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Section III Integrated Circuit Industrial Economy and Investment Zixue Ζhou, Yue Liu, Fangfang Li, Ying Cai, and Ke Feng

Introduction As the IC industry has become an essential part of trades around the world, it has also developed into an essential indicator for researchers to identify economic trends and implications in this field. To reach this purpose, they need to understand not only the market characteristics and capital composition but also the roles played by firms, consumers, and the governments in the economy as demand increases. This section presents the characteristics of IC market by analyzing the trends in supply and demand based on macroeconomic theories, as well as the empirical conclusion in the market. It also provides a set of tools for measuring firm performance and explains their meanings to the economy. There are four chapters in this section: Chap. ▶ 22 illustrates the development of the IC market from the perspective of economics; Chap. ▶ 23 explains the capital composition and market characteristics of IC industry, Chap. ▶ 24 collects essential terms and concepts of corporate performance and demonstrates their implications on investor’s decision, and finally, Chap. ▶ 25 introduces main investment methods used in China’s IC industry. Finally, we would like to express our sincere gratitude to the authors from diverse backgrounds who have generously devoted their rich experience and unique perspectives to this section. We also feel grateful to the inspiring opinions from the committee and the reviewers’ rigorous work.

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Zixue Zhou, Fangfang Li, Yaoliang Qi, and Bojing Zheng

Contents IC Industry and Macroeconomy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of Scale Economies in the IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Economic View of Moore’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Economy and Industrial Cluster in IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Blue Ocean and Red Ocean of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Globalization and Open Market for IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Value Chain and Smiling Curve of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Life Cycle of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longtail Effect and Customized Products in IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equity Valuation Model of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Principal-Agent System in IC Enterprise Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capital Structure of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Integrated circuits are the cornerstone of electronic information. There is a highly positive correlation between IC industrial development and the macroeconomic situation. IC is a global industry, which not only shows the cooperation of the global value chain, but also reflects the competition among regions for the leading power of industrial development. Both industrial clusters and scale effects have displayed the role strong leaders may sustain. The winner-take-all phenomena persist, while the blue ocean market and longtail effect have given start-ups a chance for survival and development. In order to promote healthy competition Z. Zhou China Federation of Electronics and Information Industry, Beijing, China F. Li Publishing House of Electronics Industry Co., Ltd., Beijing, China Y. Qi · B. Zheng (*) Hua Capital Investment Management Co., Ltd., Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_22

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among enterprises in different regions and scales, this chapter also discusses the appropriate strategies of integrated circuit enterprises in financial and corporate governance. Keywords

Global value chain · Corporate governance · Industrial competition · Moore’s law

IC Industry and Macroeconomy Digital integrated circuit (IC) industry is important for national strength, and therefore crucial in the political, economic, and military competition among nations. With the rapid development of global informatization and knowledge economy, IC industry has become closely related to the areas of national security, economy, society, etc., and thus could contribute a lot to macroeconomy [1]. It is also noticeable that the development of IC industry will also be affected by macroeconomy. The IC was invented in 1958 and was first applied in the military field: Texas Instruments provided computational IC solutions for the US Air Force and National Aeronautics and Space Administration (NASA). Texas Instruments also developed the world’s first IC-based computer for the US Air Force in 1961. Subsequently, NASA and the US Air Force improved their intelligence by applying IC technology to specific products. The fast-growing IC started to gain attention from industry field in the 1970s and has been widely used in the market for electronics and PCs since 1980s. From 1990, the demand for communication chip brought by mobile phones has exploded, such as systems evolved from global system for mobile communications (GSM), code division multiple access (CDMA), and long-term evolution (LTE). All systems mentioned above hold explicit demands for radio frequency (RF) chips, base band processor chips, memory units, and power amplifier devices. Smart phones resulted in more demands for IC products: sensors, logic circuits, and nonvolatile memory are required in addition to the basic communication modules. IC is the fundamental constituent of the Internet, the most effective factor of the economic structure in the twenty-first century. The positive impact of IC on macroeconomy is as important as that of other innovative technologies, but it has not been so critical until the IC entered the private market. The rapid expansion of the IC industry has driven the continuous growth of the global economy, which can be viewed from the correlation between the fluctuation of IC industry and that of global macroeconomy (see Fig. 22.1). Though the proportion of the semiconductor industry in the macroeconomy is gradually increasing, the absolute value remains small. The semiconductor industry is the core of the information industry. In spite of fluctuations, the proportion kept increasing from 0.194% in 1987 to more than 0.517% in 2020, as shown in Fig. 22.2. The ratio of the global GDP in 2020 to that in 1987 was 5.01, while the ratio between the sales volumes of semiconductor products in the same years was 13.35, which

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Fig. 22.1 Correlation between global semiconductor sales growth rate and global economic growth rate in 1992–2021. (Note: the proportion of IC sales amount is the largest in total semiconductor sales amount, which remains stable at about 80%. Source: World Semiconductor Trade Statistics (WSTS) and World Bank)

was more than double the global GDP. The sales volume of the semiconductor industry possesses the potential for rapid growth in the future. Overall, semiconductor industry will become an increasingly important role in macroeconomy. Let’s look at the impact of macroeconomy on the IC industry. Fluctuations of IC industry are more closely related to GDP fluctuations. The reason is that IC products are not only alternative for each other, but also suitable for almost all fields [1]. IC plays the role of multiplier in every practical field, promoting other industries and enhancing national strength. The development of computers, household appliances, new-coming intelligent devices, and wearable devices all depend largely on the advancement and application of IC chips [2]. The demand for electronic products is very flexible: consumers’ purchasing scale of smart phones, PCs, automobiles, and many other mechanisms and services can make a huge influence on the global electronic industry. When the economy boosts, so does the disposable income of consumers, and they tend to consume electronic products and consequently drive the growth of the semiconductor market and vice versa. The global GDP growth rate is close to semiconductor market growth rate, as shown in Fig. 22.3. The correlation

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Fig. 22.2 Proportion of global semiconductor sales in the global economy in 1987–2020 (dotted line is linear trend line). (Source: Statista)

Fig. 22.3 Correlation between global GDP growth rate and semiconductor industry growth rate. (Source: IC Insights McClean Report 2017)

coefficient between global GDP growth rate and semiconductor market growth rate has increased from 0.35 in 1980–1989 to 0.93 in 2010–2015 (the closer this value, the higher the correlation is). There was a typical historical example illustrating the relationship between the IC industry and macroeconomy. From 1985–1990, the US share in the global semiconductor market declined from 51.4% to 37.9%, while that of Japanese companies rose from 39–50% [3], which made explicit influences on the annual growth rate of per capita IC output value, per capita electronics industry, and per capita GNP. Japan’s

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performance in every field mentioned ended up with much better results than those of the USA. However, in the late 1980s, the USA adopted a series of policies to promote the development in the field of IC theory and practice, and finally regained its leading position. So far, the US economy has maintained a high-speed growth, the main reason is the innovation of information technology and the rapid development of the industry, and the information industry is based on the integrated circuit industry. In the future, the rapid expansion of the emerging branching markets such as the Internet of Things, artificial intelligence, and cloud computing will require large quantities of IC chips with ultrastrong computing power, ultralarge storage capacity, ultrafast transmission speed, and ultralow energy consumption. Thus, the IC industry will continue to play the critical role in macroeconomy.

Effect of Scale Economies in the IC Industry Effect of scale economies refers to that the larger the production scale, the lower the average production cost. This effect also exists in the IC industry. In general, the economy of scale in a certain industry is inversely proportional to the scale of demand. The more unified the demands are, the more obvious the effect of scale economies will be. On the contrary, the less unified the demands are, the less obvious the scale economies will be. The economies of scale effect show different scales in each industry sector of IC industry: this effect is larger in heavy-asset segments with unified demand (e.g., IC manufacturing industry), while smaller in light-asset sectors with longtail effect (e.g., IC design industry). The heavy-asset sectors in IC industry require more and more investment in equipment and research and development (R&D), which will eventually lead to the concentration of production capacity. Enterprises must continuously improve their production capacity to reduce the marginal cost of products so as to ensure that the revenue can cover equipment expenses. The IC manufacturing industry is the most obvious example. As the wafer size gets bigger and the manufacture process becomes more advanced, the cost of equipment increases exponentially. Hence, IC manufacturing corporations must continue to upgrade manufacture process while expanding production capacity to form the scale advantage in the market competition. The effect of scale economies is closely related to process standardization and the broader application of products. In industrial sectors asking for highly standardized processes and the products with broad application, enterprises can improve their competitiveness by expanding production and reducing fixed costs. In other words, the effect of scale economies is significant in the expansion of market share. The R&D expenditure of the world’s top 10 IC manufacturing enterprises in 2020 and 2021 is shown in Table 22.1. Among the top 10 IC manufacturing companies, Intel, Samsung, and TSMC, for example, their R&D expenditure in 2021 reached 14.9 billion, 6.5 billion, and 4.4 billion US dollars, respectively. In 2021, the total R&D expenditure of global IC manufacturing enterprises reached 81.5 billion US

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Table 22.1 The Expenditure of the world’s top 10 IC manufacturing enterprises in 2020 and 2021 Expenditures of top 10 semiconductor R&D 2021 R&D 2020 Rank Company Exp ($M) 1 Intel 14,941 2 Qualcomm 7176 3 Samsung 6500 4 Broadcom 4854 5 Nvidia 5200 6 TSMC 4410 7 SK Hynix 3672 8 MediaTek 3350 9 Micron 2663 10 AMD 2784

Rate of change (%) 10% 20% 18%
2% 33% 19% 18% 25% 2% 40%

2020 R&D Exp ($M) 13,556 5977 5500 4968 3780 3720 3100 2684 2600 1983

Rate of change (%) 1.45% 10.73% 22.22% 5.79% 33.62% 25.72% 25.35% 30.04% 6.47% 28.18%

Source: Chip Insights

dollars. Among them, the total R&D spending of the top 10 semiconductor companies in 2021 was 55.5 billion US dollars, up 15.7% from 2020. Intel’s R&D spending accounted for 26.83% of the combined R&D spending of top 10 semiconductor companies. In 2021, 17 semiconductor companies spent more than 1 billion US dollars in R&D, reaching a total of 67.5 billion US dollars, an increase of 16.3% over 2020. The technical and monetary threshold of IC manufacturing technology will be higher and higher, which makes the expenditure of IC industry gradually concentrated in several technology-dominating monopoly enterprises. These monopoly enterprises are willing to carry out a large amount of capital expenditure because they can gain an advantage in market competition through high expenditure. In the highly capitalized IC industry with significant economies of scale, one must either catch up with the market or go bankrupt. The effect of scale economies of IC industry is clearly reflected on the concentration of market. In the field of equipment, the top two companies occupy 40% market, and the top 10 companies occupy about 70% market totally. Other companies can only compete for the remaining 30%, and the gross profit margin of the companies is positively related to their market share. In the etching market, Lam Research accounts for 47%; in the deposition market, Applied Materials accounts for 47%; and ASML accounts for 74% in the lithography market: the whole market is almost monopolized by a leading enterprise [4]. The concentration of IC industry determines the number of enterprises, especially in the field of IC manufacturing and memory. If blindly expanding, new enterprises will not survive due to long-term losses. Therefore, governors can promote mergers and acquisitions among enterprises in these fields to form one or two giant enterprises with compatibility in the international market. In areas where economies of scale are relatively weak, governors can promote new ideas to help small and medium-sized enterprises and provide solutions to diverse market demands.

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Economic View of Moore’s Law Moore’s law, proposed by Intel cofounder Gordon Moore, is not a “law” of science such as mathematics, physics, etc.: it is the prediction of the trend of the integrated circuit industry. Based on the history of the integrated circuit industry, especially the development history of Intel, Moore’ law can be summarized as the following: the number of transistors on an integrated circuit chip that one can buy would double with the same price every 18 to 24 months, as does the performance of an IC. It means that the performance of IC at price of one dollar would double every 18 to 24 months [5]. Moore’s law demonstrates the speed of the development of technology. The storage capacity of the DRAM – the main type of the memory devices – has grown from the original 1kbit to 16Gbit (DDR4) and even 64Gbit (DDR5). Meanwhile, the microprocessor has been upgraded from the Intel 4004 to these processes with multiple threads and multiple cores. Moore’s law works when IC technology is still immature. The learning effect is great, and the economic law of increasing marginal benefit stays at the dominant place when IC technology still needs to be improved. When the IC technology becomes mature, the traction effect of the technology will gradually disappear, and the learning effect will decrease. Hence, the law of diminishing marginal utility will come into play, and, accordingly, the Moore’s law will lose its effectiveness. Finally, the IC industry will become a traditional industry like agriculture, which means that the law of diminishing marginal utility of the traditional economics will work on IC industry. As Brian Arthur said, “So we can usefully think of two economic regimes or worlds: a mass-production world yielding products that essentially are congealed resources with a little knowledge and operating according to Marshall’ s principles of diminishing returns, and a knowledge-based world yielding products that are essentially congealed knowledge with small amounts of resources and operating under increasing returns.” The information industry, developed according to the Moore’s law, is the main engine of the modern economy. Moore’s law precisely describes the development of technology economy of IC industry which is the core product of the electronic information industry. It is hard to say when Moore’s law would eventually reach its limit. Nevertheless, it leaves us with the thought about the high-tech industry has guiding significance for us to put forward the concept of market competition combining the technology monopoly and the economic compatibility. From the perspective of the market, Moore’s law demonstrates the regularity of the market competition in IC industry. The competition mainly involves technology and human resources. The aim of these competitions is to show the leadership in R&D of technology, the introduction of preliminary customers, and the control of knowledge resources. The regularity of the market competition includes both technological competition and economic competition. Of which, the technological regularity is that the industry can maximize the amount of IC components on one chip with ultrafine line width through the innovative utilization of the complicated technologies in IC industry such as layout design,

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materials, equipment, technique, detection, testing, etc. Thus, it can meet the requirements of lighter, thinner, smaller, and mobile characteristics of the electronic products, which is to optimize the performance and functions. The economic regularity can be further classified into the investment regularity and the distribution regularity, among which the former one means that in order to meet the prerequisites for the traction effect of technological law, the investment scale is required to have the features of high (investment amount), rapid (investment), continuous (investment), and large (increasing investment volume). In this way, achieving the technological leadership can be guaranteed. Similarly, the latter one indicates that in order to meet the prerequisites of the traction effect of the law of technology and adapt to the new mode of production, the IC industry needs to gather as many of the best elites as possible, so as to maximize their revitalizing ability to the utmost extent. The leading position of technology is manifested as a technology monopoly in the market. To remain on the position of monopoly as long as possible, an enterprise or a country must continuously increase investment and hence attract more and more talents, resulting in strong economic compatibility. In turn, the superior economic compatibility will support the monopolistic dominance and thus generate more profit from the technological monopolies. The profit can be ploughed into the next intensive round of competition, which would finally become a positive spiral circulation [6]. The value of a technology may eventually run out. However, the economic thoughts will never dry up. Moore’s law demonstrates the truth of the sustainable innovation in an industry and society as a whole. The quintessence of Moore’s law is the idea of market competition, which integrates the technological monopoly and the economic competition. It is manifested by the entrepreneurship, innovation activities, and the pace of innovation. As long as the sustainable innovation remains, the rule of increasing return will remain, which means Moore’ law will be not going away.

Scope Economy and Industrial Cluster in IC Industry Scope economy refers to the positive effects that different companies can achieve to each other within a certain geographical range. The scope economy is more obvious in high-tech industries that have a quantitative demand for infrastructure, which makes the industry create a strong industrial agglomeration effect to a certain location, and eventually forms corresponding industrial clusters. Industrial cluster refers to a group of related enterprises and institutions in a specific field, concentrated in a certain geographical area, forming a flexible organic complex with the complete structure of the industrial chain and comprehensive peripheral supporting industrial system [7]. The development of the IC industry has shown the characteristics of scope economy, forming various world famous IC industry clusters. By scope economy,

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enterprises in the cluster can enjoy basic resources within a certain geographical range, including industrial supply chains, scientific research institutions, transportation infrastructure, and information platforms. Under such circumstances, the cluster can attract more qualitative production factors. For example, Taiwan has formed three major IC industrial clusters in the Hsinchu Science Park, the Central Science Park, and the Southern Science Park. The IC wafer manufacturing industry is mainly concentrated in the Hsinchu Science and Technology Park, where various supporting subindustries of the wafer manufacturing industry are also concentrated. The chip design industry is concentrated in the education center near Taipei because of its technological orientation. China’s mainland has formed three major IC industrial clusters in Beijing and Tianjin area (around the Bohai Sea), the Yangtze River Delta, and the Pearl River Delta. The industrial cluster distribution of integrated circuits in China is highly consistent with the location of the economic center, and basically consistent with the higher education center. In other words, the location choice of China’s IC industry cluster is highly market oriented and capital oriented, which is closely related to the reserves of scientific and technological talents. This phenomenon also appears in countries with advanced IC industries, such as the USA, South Korea, and Japan. At present, due to the characteristics of integrated circuit industry itself, the location of IC industry is more dispersed in different regions, but the main body remains concentrated. This does not conflict with the characteristics of the scope economy and industrial clusters. On the contrary, it indicates that the IC industry is developing to maturity. In this situation, the resources in one region are insufficient to support large-scale IC enterprises. Overall, the main markets of the IC industry are still in North America, Europe, Japan, and Asia Pacific region. However, in order to maximize profits and minimize cost of production factors, enterprises need to locate their factories as close to the location of production factors and markets as possible. Based on this trend, the production of the IC industry, although decentralized, is still mainly concentrated in specific regions, such as China in recent years. While IC industry gets improved, this feature will remain steady.

Blue Ocean and Red Ocean of IC Industry While the Red Ocean represents all the industries that already exist today, namely the known market space, the Blue Ocean refers to the industries that do not yet exist now, that is, the unknown market space. In the Red Ocean, the boundaries of every industry and the rules of competition are well known. As the market space becomes more crowded, the prospects for profits and growth are dimming. In contrast, the Blue Ocean denotes the market space that requires immediate exploration, indicating the opportunity to create new demands and a high-profit growth. Although some of the Blue Ocean is explored totally outside the boundaries of existing industries, most

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of the Blue Ocean is opened through extending the boundaries of existing industries within the Red Ocean [8]. ICs are indispensable core components of electronic products, claiming an extensive scope of applications. The degree of competition in these large downstream markets varies. There is no way to list all the markets individually based on which is in the Red Ocean and which is in the Blue Ocean. Generally speaking, the competitive strength/profitability depends on factors such as technical level, capital level, and the number of competitive enterprises. An IC enterprise can hold downstream demands in its own hands and explore the Blue Ocean markets better by the following ways. Keep fingers on the pulse of the Blue Ocean market resulting from newly emerging demands. Downstream demands for IC products are always continuously escalating, and an important milestone in technology always means a market opportunity for updating IC products. For example, Qualcomm, a fabless enterprise, made a plan in advance for new generation patented communication technology in the era of 2G mobile communication network. The patent barriers made it impossible for every downstream enterprise to avoid the “great wall” of patents that Qualcomm had built well beforehand, and Qualcomm seized the opportunity to charge mobile phone enterprises high patent licensing fees. Another example is ASML, an enterprise specializing in manufacturing photolithography equipment. Taking advantage of the innovation opportunities of 193 nm immersion lithography technology, ASML preceded its rivals such as Nikon and Canon in launching the equipment to meet the demands from downstream foundries and outperformed its peers in a short period of time. After that, it took the lead in developing the EUV photolithography equipment through industry chain mergers and acquisitions, achieving the position as the sole leader in the field of wafer photolithography equipment. Like other industries, the IC industry also follows the law that “first come, first served.” At present, there are many new application markets for ICs, e.g., artificial intelligence, Internet of Things, and wearable devices. If IC enterprises are able to seize on the newly emerging demands from downstream markets, they will have more tremendous market opportunities than their competitors [9]. Grasp the Blue Ocean market resulting from segmented demands. Even in a similar and fiercely competitive market, there are segmented demands that are difficult for general products to meet. These segmented demands may have special application conditions and performance factors that require customized products to meet. Once these segmented demands are satisfied, customer trust will always exist, resulting in steady and considerable profits. No matter what it says above, the capability of an enterprise in R&D is a necessary factor. For a relatively long period of time in the past, China’s IC enterprises in the R&D investment is insufficient, resulting in highly homogeneous products and fierce price competition. Under such circumstances, China’s IC enterprises should keep an open mind, invest more talents and capital in research and development, and achieve the industrial upgrading from capital advantage to technological advantage.

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Globalization and Open Market for IC Industry The globalization and market opening of IC industry is a global industry. Its development and production is a very complex and huge industry chain. When developing IC industry, no country can shut its doors to do it. Opening up and international cooperation are the mainstreams of the industry. 1) Development and production of IC products. The IC industry is a global vertical division of labor. Every chip from design and production to sales will inevitably experience a global division of labor. Take the baseband chip of Apple’s iPhone as an example. It is licensed by ARM in the UK, designed in the USA, manufactured in Taiwan and Korea, then packaged and tested in China, and eventually sold around the world. The equipment and materials used in the production of ICs are from the Netherlands, the USA, Japan, and other countries. Through the global open division of labor and the cooperation of industrial chain to achieve the optimal allocation of resources, all enterprise can concentrate on their own advantages, constantly promote technological innovation, and optimize the performance and cost of the chip as much as possible. 2) Marketing of IC products. The cost of IC chip product development is high, and high investment will bring high risks. At the same time, IC wafer manufacturing industry follows Moore’s law, and its product technology is evolving toward higher integration, lower power consumption, and lower cost. Therefore, IC products must be shipped on a large scale in order to share development costs and earn profits. Only an open market facing the whole world can meet the demand of sales scale of IC products to the greatest extent. ITA1 (Information Technology Agreement 1), ITA2 (Information Technology Agreement 2), and other information technology tax rate agreements reflect this from the demand side. These agreements have eliminated tariff barriers for member countries to enter the international market of ICs and promoted the development of trade in the information technology industry.

Global Value Chain and Smiling Curve of IC Industry Michael Porker first proposed the value chain theory in 1985 [10]. In the 1990s, Zhenrong Shi, founder of Acer, put forth the “smiling curve” theory based on the value chain, making the summary of the value growth principle in general manufacturing industry chains: Generally speaking, R&D and marketing service are located at the front end and the back end of an industry chain, respectively, belonging to technical field and market field, with higher added values. Production and manufacturing are in the middle part of the industry chain, having little influence on the design and marketing of products, with lower added values [11]. Similarly, the IC industry has its own “smiling curve,” but its form is somewhat different from the general manufacturing industries, as shown in Fig. 22.4.

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Fig. 22.4 The “smiling curve” of the value growth in the value chain of IC industry

The special smiling curve in the IC industry is plotted roughly in the order of materials and equipment – design – manufacturing – packaging and testing – design. As compared with the “smiling curve” in the general manufacturing industries, its specific characteristics are mainly in the following aspects. The design section appears at both ends of the smiling curve. In the IC industry, a fabless design house develops the plan according to the demands from downstream clients and connects with foundries as well as packaging and testing enterprises for production. The IC products are eventually sold to clients also by the fabless, which means that the design house is responsible for the design and marketing sections at the same time. The wafer manufacturing section has a higher added value. Foundries have well mastered the core manufacturing technology in the IC industry, providing the main impetus for the sustainable development of Moore’s law, with a strong technical strength. In fact, the theories about the smiling curve and the value chain point to the reasons of the present situation why the work in the IC industry is shared internationally: since such sections as equipment, materials, and design in the industry chain have higher added values while sections such as packaging and testing have lower added values, in the context of globalization, major multinational factories usually transfer the sections of low added values such as packaging and testing to later-developed regions. To catch up with early-developed regions, most of the laterdeveloped regions start with undertaking the sections of low value-added industries, gradually buildup industrial strength, and then upgrade to the sections of high valueadded industries. The development history of China’s IC industry has proved the universal principle that an industry achieves the industrial upgrade along the “smiling curve.” For a relatively long period of time in the past, due to the relatively low labor costs, China was relatively standout in the packaging and testing section among the international divisions of the IC industry. With continuous technical accumulations, as well as constant capital and talent inputs, a number of outstanding fabless chipmakers and foundries have emerged in China since 2000. The growth rate of design and

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manufacturing industries is far higher than that of packaging and testing industry, and the proportion in the output value of IC industry has increased rapidly. Based on the regular pattern in history and the current situation, China’s IC industry will upgrade along the “smiling curve,” starting from the sections of lower added values such as packaging and testing, gradually switching to the sections of higher added values such as manufacturing and designing, and achieving a synergetic development in the whole industry chain.

Life Cycle of IC Products Raymond Vernon, professor at Harvard University, first proposed the theory of product life cycle in the article “International Investment and International Trade in the Product Life Cycle” in 1966. Product life cycle, that is, the entire process of a new product from entering the market to being eliminated from the market, can be divided into four stages: introduction stage, growth stage, maturity stage, and decline stage [12]. At different stages of a product life cycle, sales, profit, purchasers, and market competition all have different characteristics. For these characteristics, see Table 22.2. There are reasons for the periodic changes that happen in a product life cycle, mainly including the upgrading of the product resulting from technological advancements, as well as the continuous updating of the product caused by the constant escalation of downstream demands. IC products basically accord with the periodic characteristics suggested by the theory of product life cycle, which is mainly reflected in the following two aspects. 1) Life cycle within a product Among IC products, some have a long life, with their basic architectures and design methods having not undergone any fundamental changes since their invention. Due to technological upgrade, however, the performances of products are continuously improved, and now have reached the targets that are imagined at Table 22.2 Characteristics in different stages of product life cycle Stage Sales

Introduction Low

Growth Rapid

Profit

Small or negative Those with curiosity Less

High

Maturity Early phase Continuous growth Peak

Relatively high in numbers Emerging

Common people Increasing

Purchasers Market competition

Later phase Downward tendency Gradually declining Common people Fierce

Decline Down Low or negative Subsequent users Reduced

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the time of invention. CPU and DRAM are the best typical examples of this type of products. 2) Life cycle of a product form As the downstream constantly makes new demands, the forms of IC products will also continue evolving. For example, products such as system-on-chips, neural network chips, GaAs/GaN chips, SiGe chips, and biochips have become new development fields, and low power consumption is one of the most important indexes for evaluating chips. During the evolution process, new products are constantly developed to meet market demand, while being continuously replaced with latest products. Due to the rapid changes in the market, the cycle of IC products has been obviously shortened. Although mainstream products overlap with accumulated nonmainstream ones in the market for a certain period of time, many products are quickly eliminated. Generally speaking, the life cycle of the IC products for industrial applications is somewhat longer than those used as consumer goods.

Longtail Effect and Customized Products in IC Industry The model of longtail effect is shown in Fig. 22.5. The ordinate values corresponding to the main client base are relatively high, that is, their individual purchases are relatively large, and the relevant abscissa values are small, that is, their quantities are relatively small. The opposite is true of the longtail client base, which corresponds to a lower ordinate value and a larger abscissa value, that is, although individual clients make small purchases, the quantity of the client base is large. This curve features a longtail, and, therefore, the condition represented by this curve is called the “longtail effect.” Similarly, there is a longtail effect in the IC industry, which is evident in industrial customers for the following reasons: Industrial clients may have special

Fig. 22.5 The model of longtail effect

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requirements for working conditions, confidentiality, power consumption, and other performance of IC products, and are generally willing to pay higher prices for relevant products. As their equipment/product has a relatively long updating cycle, e.g., machine tools, instruments, and automotive front assemblies, industrial clients pay more attention to the reliability and stability of ICs, tending toward long-term cooperation with suppliers. Industrial clients take their demand for equipment as the upper limits on the quantities of the chips they can purchase, while individual clients make small purchases. However, the quantity of industrial clients is large. Even though the demand from individual clients is low in volume, the total volume of demand from the industrial market is still significant. In order to meet the specific requirements of longtail clients, it is always necessary to provide these clients with customized products. The customized products may differ from standard mass-produced products in terms of specification index, quantity, color, smell, package, and logo. In IC industry, a fabless enterprise or a design department in IDM directly links with the market, and, therefore, the customization is mainly achieved in the design phase by integrating all the required functions and by designing IC products according to the requirements of clients. These products are not uniformly customized, which mainly depends on the scales of downstream clients as well as the marketing strategy. Although the customization of ICs is achieved mainly in the design phase, some customized products still require a perfect combination of special materials and special technological processes, because ICs are products of the combination of software and hardware. For example, the power-amplifying chips in the communication base stations have more strict requirements for performances on power intensity, working frequency range, and high-temperature endurance, which are difficult for the conventional GaAs materials to meet, requiring the use of the new generation material of GaN. Because of its sensor part, MEMS needs the micromachining on silicon surface to form a membrane settling on the surface of a silicon crystal, which is then partially separated from the body of silicon before presenting a movable structure. The higher the level of customization is, the better the overall profitability is. Considering the cost of the tape-out, however, not every precise requirement should entail a customized development. IC enterprises should carefully analyze the requirements from clients, evaluate the purchasing abilities of clients, and strive to reach a balancing point on the profitable level and profitable scale.

Equity Valuation Model of IC Enterprises To evaluate the enterprise value accurately, the first step is to choose the correct valuation model according to the basic characteristics of the enterprise. There are two types of valuation models: absolute valuation model and relative valuation model. The absolute model is based on the analysis of the historical statistics, current

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business measurements, and the prediction of future financial status to value the enterprise, focusing on the intrinsic value of the target enterprise. Commonly used methods are discounted cash flow (DCF), option pricing, etc. Relative model is to compare the target enterprise with similar or related enterprises in terms of P/E ratio, P/S ratio, P/B ratio, enterprise value multiples (EV/EBITDA), and other metrics to estimate the value. Here we introduce some commonly used methods for each model. 1) Absolute valuation model, DCF The discounted cash flow (DCF) is considered to be the most comprehensive valuation method. The assumption is that “the basic component of enterprise value is the future cash flow discounted to present using the rate reflecting future risks.” This method calculates the value of an asset as the sum of expected future cash flows discounted to present value: DCF ¼

CF 1 CF 2 CF n þ þ⋯þ 1 2 ð1 þ r Þn ð1 þ r Þ ð1 þ r Þ

where CF is the cash flow for each term and r stands for weighted average cost of capital (WACC). It is almost impossible to estimate the cash flow of each future period; therefore, a practical way is to estimate cash flows with a fixed growth rate or viable rates based on reasonable assumptions. Integrated circuit enterprises, especially design-oriented ones, usually grow rapidly in the beginning and then enter a stable growth period, so that each period will need a different estimated growth rate. It can be seen that this method is based on certain hypothetical predictions which introduce errors and uncertainties. For integrated circuit companies that are not established for a long time or those whose profit model is still not stable, it is very likely that their historical financial reports are incomplete. In this case, multiple methods need to be applied, and the relative valuation model is used to jointly evaluate the enterprise. 2) Relative valuation model i. P/E ratio: The P/E ratio model evaluates IC enterprises according to the industry average. This model links the value to the earning or net income of the enterprise, which is fundamentally easy to understand. That is, the price per share of the enterprise equals the earnings per share from its financial report, multiplied by the industry P/E ratio from the average of comparable enterprises: Price per share ¼ r  Earnings per share where r is the average P/E ratio from the industry, which is estimated by a list of similar enterprises. Thus, we can calculate the value of the enterprise with the estimated price per share.

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ii. Enterprise value multiple (EV/EBITDA): The enterprise value multiple is also commonly used for the valuation in the integrated circuit industry. It is a relative valuation method similar to the P/E ratio introduced above, where the ratio is replaced by EV/EBITDA. The numerator EV stands for the market value of all the capital invested in the enterprise. EV ¼ r  EBITDA, where r is the average enterprise value multiple of the industry, and the EBITDA stands for earnings before interest, tax, depreciation, and amortization. iii. P/S ratio: The price-to-sales ratio (P/S ratio) is also an effective valuation method especially when profit is negative, similar to the P/E ratio method. By using the industry average P/S ratio and the revenue per share of the target enterprise, we can get the estimated price per share as below. Price per share ¼ r  Sales per share where r is the industry average P/S ratio. The advantage of the relative valuation model is simple and easy to use, but there are caveats: First, no two enterprises are exactly the same, so “comparable” is more of a subjective judgment which causes errors in estimation; second, each enterprise’s valuation errors will be introduced and propagated into other enterprises’ estimation, and thus multiplied to cause more substantial misjudgment of the whole market. To reduce these impacts in the IC industry, the analyst needs to select comparative enterprises with the same product types, the same application market, and similar gross profit margins for reference. For IC manufacturing enterprises and packaging/ testing enterprises, reference enterprises with the same production scales and close processing levels should be selected. Enterprise values are relative in nature. No matter what method is used, it can only be estimated and cannot be accurately calculated. Here we take the major integrated circuit manufacturing companies as an example in Table 22.3. By the end of 2018, the market value of TSMC has grown to US$191 billion (B), 10B less than Intel’s. The company had been growing steadily in the past 15 years before 2018 with an annual growth rate of 9% in free cash flow. If we assume a free cash flow growth of 9% over 5 years, a 3% sustainable growth rate after 5 years, and an average market return of 7%, we could calculate that the current market value of TSMC is around $164B. It can be seen that the rapid growth has brought strong expectations to the market, and its market value is still growing after 2018. From the relative valuation in 2018, we use a rough average of 15 times P/E value, 2 times P/S value, and 5 times EV/EBITDA value for TSMC, taking into account three comparable companies: Intel, UMC, and SMIC. The valuation would

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Table 22.3 Comparison of major market performances of Intel, TSMC, UMC, and SMIC on 2018 year end and 2021 year end ($B) Company Name Listed exchange: stock code Fiscal year Market value (@year end) Enterprise value Revenue Operating income Net income Net margin FY EBITDA P/E(x) P/S(x) EV/EBITDA(x)

Intel NasdaqGS: INTC 2018 2021 212.8 209.5

TSMC TSEC:2303

UMC TSCE:2330

SMIC SEHK:981

2018 191.4

2021 575.4

2018 4.3

2021 29.2

2018 4.3

2021 18.9

226.6 70.9 23.24

215.1 79.0 22.08

172.9 34.2 12.77

561.7 57.3 23.47

4.3 5.0 0.18

26.7 7.7 1.86

6.8 3.4 0.01

20.5 5.4 0.73

21.05 29.7% 32.87 10.48 3.10 6.90

19.87 25.1% 33.87 10.54 2.65 6.35

12.04 35.2% 22.97 15.93 5.60 7.50

21.37 37.3% 38.47 26.92 10.05 14.60

0.25 5.1% 1.89 17.98 0.94 2.29

2.01 26.2% 3.48 14.53 3.80 7.68

0.13 13.1% 1.13 18.92 1.30 6.04

1.70 31.3% 2.50 11.11 3.47 8.19

Note: The exchange rate is based on the exchange rate of December 31, 2018, and December 31, 2021

be $180B, $68.4B, and $114.9B, respectively. We can see that the results vary in a big range, which indicates different opinions from different valuation methods. Thus, it is unlikely to make an accurate estimation of the valuation. But considering that the market is definitely changing and introducing more opportunities and risks, TSMC will definitely encounter more challenges if it wants to keep its growing market value. Mergers and acquisitions (Ms&As) have occurred quite frequently in the integrated circuit industry. Rather than pursuing short-term interests and gains, both parties in M&A seek long-term development plans, including supplementing existing product ecosystems, opening up new markets, and enhancing competitiveness. Therefore, when evaluating the target companies or assets, the ultimate rule behind various models and methods is that “valuation reflects future expectations.” For example, Softbank acquired ARM for $32B. Although the transaction price exceeded ARM’s market capitalization for 43% by then, and the price-to-earnings ratio of the purchase was nearly 70 times, which was significantly higher than the average price-to-earnings ratio of integrated circuit companies in the international market; Softbank was still determined to make an offer. The reasons are not difficult to find out – ARM’s net profit maintained a rapid growth of around 30% in the five years before the acquisition (data from ARM’s 2012–2016 public financial report); its free cash flow also had an annual growth rate of 16%. If the next decade is the period that the Internet of Things will usher in a big outbreak as Softbank has imagined, we can calculate ARM’s valuation: let’s assume that ARM’s cash flow grows at 25% for 3 years, then 15% for 3 years, and then 3% for the years after that. The average opportunity cost in the market is 7%. Based on DCF, its 2016 valuation

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should be $30.9B, which is roughly the amount of the deal announced. ARM’s products are mainly intangible intellectual properties which can be copied and disseminated indefinitely. The company never invests much in heavy assets from the beginning. But the ARM ecosystem has a significant impact on the entire mobile industry. From sensors to smartphones, servers, and IoT applications, ARM works with more than 1400 companies including Qualcomm and TSMC, covering all major chip markets around the world, forming up a broad industry alliance. All these factors make ARM a perfect target for Softbank to invest in IoT with a lightweight strategy. The acquisition of $32B is jointly achieved by the two parties after considering the long-term development goals. The success of the transaction also maximizes the benefits for both ARM and Softbank. In summary, an accurate valuation cannot be achieved. But with multiple methods combined, we can get a more comprehensive understanding of the market value. The undergoing of an M&A between IC enterprises is usually the positive expectation of both parties to maximize their long-term interests, not just short-term benefits.

Principal-Agent System in IC Enterprise Management In the general corporate governance structure, there is a close relationship among the shareholders’ meeting, the board of directors, the senior management, and the board of supervisors. There are two levels of principal-agent relationships: the entrustment of the shareholders’ meetings to the board of directors and the entrustment of the board of directors to senior management. The board of directors is trusted and entrusted by the shareholders’ meeting to be responsible for the property and operation of the company as the business decision-maker. The board of directors selects and appoints the managers of the company based on the ability of management and profitability. Managers, especially general manager (GM) or chief executive officer (CEO), have management and agency rights to operate the company as resolution agents of the board of directors. Management rights refer to the management functions of managers on the internal affairs of the company. Agency rights refer to the commercial agency rights of managers in and out of litigation. The reasonable matching between board members and the formation of an effective and complementary structure will help the board of directors to make scientific decisions. Board members not only need to have rich experience in company operations, relevant industry experience, and resources, but also need a high strategic vision to invest and layout for the company’s long-term development. As the company expands and its operations become more complex, the board needs to listen to the opinions from more experts in technology, legal, and finance. These experts can be internal directors of the company or independent directors who have no relationship with the company. Taking the board of directors of Semiconductor Manufacturing International Corporation (SMIC) as an example, according to its 2016 annual report released on April 27, 2017, SMIC’s board of directors is composed of 13 members, each with their own expertise, forming an effective complementarity. It includes chairman Zixue Zhou (economic expert, in-depth

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research on industrial economy, finance, and taxation, etc.), executive director Ciyun Qiu (enterprise operation and management expert, IC industry technology expert), executive director Yonggang Gao (financial management and industrial investment expert), nonexecutive director Shanzhi Chen (communication industry expert), nonexecutive director Jie Zhou (securities industry expert and investment expert), nonexecutive director Kai Ren (industry investment management expert), nonexecutive director Jun Lu (credit, industry investment, and fund investment expert), independent nonexecutive director Guohua Tong (communication industry expert and management science expert), independent nonexecutive director Liwu Chen (venture capital expert), independent nonexecutive director William Tudor Brown (IC design expert), independent nonexecutive director Yihua Zhou (cross-border investment and trading expert), independent nonexecutive director Shangyi Jiang (IC development and operation expert), and independent nonexecutive director Jingsheng Cong (computer-aided design expert for IC and academic expert). The IC industry is a typical knowledge-intensive, technology-intensive, talentintensive, and capital-intensive high-tech industry. These characteristics determine that its development requires not only the continuous investment of large-scale funds, but also the continuous accumulation and innovation of technology. The dependence on talents is particularly prominent and higher requirements are placed on the management of IC companies. For example, the CEO of IC foundry company is required to have the capabilities in technology, research and development, business development, plant operations, and company management. The products produced by IC foundry are not common commodities, so the CEO must understand the complex IC manufacturing process system, the overall technical structure, and the frontier technological development direction to face the increasing demands of customers and the pursuit and challenges of competitors. The operation of the IC factory is the most advanced manufacturing management in the world. The complexity of the process, the accuracy and stability of the process technology, and the automation of the equipment are the highest in all industries, requiring highly systematic management tools and management talents with highly comprehensive abilities. It is difficult to be qualified for this job without long-term experience in IC factory. IC foundry companies are capital-intensive enterprises that require sustained capital expenditures to support their technology research and development and capacity expansion, and management to make comprehensive investment considerations to achieve targets of corporate profits, development, and long-term benefits for shareholders. Therefore, the principal-agent management of an IC company requires the board of directors and the shareholders’ meetings to first understand the characteristics of the IC industry, and to select and hire senior management personnel with rich industry experience and comprehensive capabilities. In the process of principalagent management, the board of directors and shareholders need to maintain close communication with the management patiently, respect the professional opinions of the management, and fully ensure that the professional managers can exert their management capabilities.

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Capital Structure of IC Enterprises Enterprises obtain funds through debt or giving up equity. This combination of liabilities and equity is called capital structure. Liabilities generally include bonds, long-term notes payable, and equity including common stock, preferred stock, etc. The ratio of liabilities and equity reflects the risks of enterprises in a sense, so the “D/E (debt/equity) ratio” has become an indicator that analysts take into consideration. Due to the tax shield effect, liability will bring certain tax deduction and do not affect the ownership of the enterprise. When interest rates are low, debt is more comfortable to obtain, and enterprises pay less cost overall comparing to giving up equity. However, the advantage of giving up equity is that, unlike debt, the fund in exchange for the equity does not need to be paid back eventually. Besides, more debt means higher risk, and it also means a higher return rate. On the whole, different companies have different D/E ratios. The decision-makers of enterprises will consider the costs and risks of various funds, and then explore the best D/E ratio based on the actual situation of the industry characteristics to formulate the most suitable strategy for their own development. IC manufacturing companies need to maintain a strictly neutral position among its customers to ensure their long-term stability and independent growth. Therefore, its major shareholders cannot be its customers, nor can it make a significant equity investment to any of the customer. In addition, integrated circuit manufacturing companies are such capital-intensive companies that large-scale capital investment is required in the initial stage to build plants and purchase equipment, which can last at least 3–5 years to achieve an economic-scale effect. Such an enormous capital demand determines that its capital structure must be composed of both debt and equity. In the case of TSMC, with the increase in total assets over the years, the total amount of debt has also increased, from the 430 million Taiwan dollars (TWD, about USD14 million) in its early years to TWD625 billion in 2017 (about USD20 billion, according to TSMC’s 1999–2017 public financial report). On the other hand, integrated circuit manufacturing is also a talent-intensive industry. Unlike integrated circuit design companies whose success could be achieved by a smaller number of talented partners, the demand for the high-level talent pool of the IC manufacturing industry is so large that almost no start-up teams can meet the demand. Therefore, the success of an IC manufacturing enterprise is sporadic. In terms of IC design-oriented enterprises, they are more like software companies. They require less capital at the beginning, and their capital structure is more flexible. Therefore, the debt-to-equity ratios of different enterprises are quite different, which are more related to the development goals. As long as they have sufficient solvency and controlled risks, IC design start-ups will often focus on taking debt to support R&D and product design, which will ensure that the company’s equity is in the hands of the founding team. When a large fund is required for tape out or more advanced process design, IC design start-ups often give up some equity in exchange for cash. Because of this flexibility, China’s IC design start-ups have developed rapidly over the past decade, and many outstanding enterprises have emerged.

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References 1. M. Yu, Basic ideas for developing Heilongjiang’s IC (design) industry, in Presented at “Revitalizing Old Industrial Bases in Northeast China”, (Expert Forum, China, 2007) 2. Z. Zhou, Research on Investment and Financing of China’s IC Industry, 1st edn. (Publishing House of Electronics Industry, Beijing, 2015), p. 76 3. Y. Liu, Strategic Orientation and Development Strategy of China’s IC Industry, M.S. thesis, Dept. Economics, Shanghai Jiao Tong University, Shanghai, China, 2002 4. Z. Zhou, Research on Investment and Financing of China’s IC Industry, 1st edn. (Publishing House of Electronics Industry, Beijing, 2015), p. 64 5. L. Sydell, X. Feng, The 50th anniversary of Moore’s Law’s being proposed, English Digest, pp. 41–44, Sept 2015 6. Z. Zhou, An investigation on regularities of the development of the electronic information industry. Electron. Account. 7, 1–4 (2007) 7. J. Zou, The Integration of Government Policy, Finance into Development of Chinese Semiconductor Industry, Ph.D. dissertation, Shanghai Jiao Tong University, Shanghai, China, 2013 8. W.C. Kim, M. Renée, Blue Ocean Strategy (The Commercial Press, Boston, 2005) 9. Observations on Semiconductor Industry. How has ASML become a photo-etching tycoon. Zhihu, 28 Sept 2022. zhuanlan.zhihu.com/p/21632080. Accessed 22 Nov 2022 10. M.E. Porter, Competitive Advantage: Creating and Sustaining Superior Performance (Free Press, New York, 1985) 11. S. Zhenrong, Rebuilding Acer (Shanghai Fareast Press, Shanghai, 1996) 12. G. Guo, A General Introduction to Market Selling (Renmin University Press, Beijing, 1999)

Development Law and Development Index of IC Industry

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Contents Developing Trend of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Business Characteristics of Memory IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Government Policies and IC Industry Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Investment and Growth of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technomic Factors for IC Industry Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changes in Total Investment and Market Scale of Worldwide Semiconductor Industry . . . . . . CAPEX and R&D Expense of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entry Barriers of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regional Migration of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Industry Investment and Industrial Ecology Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relationship Between Investment and Technology Advancement in IC Industry . . . . . . . . . . . . . Cost Structure Analysis of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Production Scale Optimization for IC Manufacturing Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Profit and Loss Characteristics of IC Manufacturing Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shareholder Structure of IC Foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prosperity Indicators of Statistics for IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prosperity Indicators of Securities for IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

This chapter provides useful guidance to investors by analyzing current trends and potential directions of the IC industry. This chapter also includes core information about investment in the industry, including investment scale, cost structure, scale of return, barriers to entry, and associated risks. As newcomers in the IC market, IC practitioners in China face high entry barriers and hence more T. Feng · K. Zheng (*) Semiconductor Manufacturing International Corporation, Beijing, China e-mail: [email protected] K. Hua Semiconductor Manufacturing International Corporation, Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_23

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challenges and difficulties. Investors must be fully aware of this fact in their decision-making process. Keywords

Investment scale · Regional development · Monopoly · Barriers to entry · Cost structure · Production of scale optimization · Prosperity indicators

Developing Trend of IC Industry The development trend of IC Industry is a technology-intensive, capital-intensive, and talent-intensive industry. In recent years, the IC industry presents the following characteristics: Steady development, decreasing volatility, and slowing growth; capital expenditure increases, the stronger the stronger pattern has been formed; the shift of market and manufacturing focus to the Asia-Pacific region has been accelerated; the R&D and manufacturing of high-end advanced technology based on the continuous reduction of feature size is still the mainstream of progress in IC manufacturing technology, but the rhythm of feature size reduction slows down; market hotspots converge on mobile and intelligent areas. 1. Industrial Development Has Stabilized, Volatility Has Decreased, and Growth Has Slowed Down Over the past 15 years, the IC market has maintained overall growth, but due to the impact of the economic crisis and the “silicon cycle,” the industrial development has experienced significant fluctuations. For example, in 1999, 2002, and 2009, there were significant declines; since 2014, the development of integrated circuit industry has stabilized and the fluctuation range has been moderate, showing a steady upward trend. The global semiconductor market grew at an average rate of 7.6% in 2000–2008, compared with 4.4% during 2009–2016, indicating a significant slowdown in growth. With the slow pace of technological evolution and the dramatic increase of investment intensity, the semiconductor market will continue to grow slowly in the coming years if there is no particularly huge market demand. 2. Capital Expenditure Increases and the Stronger the Stronger Pattern Is Formed The competitive market environment of IC industry requires more capital expenditure and R&D costs to scale up production scale and develop new technologies and products. With the shrinkage of IC feature size, especially after entering the nano (nanometer) era, the cost of high-end product research and development has increased, the investment of IC production line is huge, and the investment return cycle has become longer. Many enterprises have been unable to bear the burden of large amounts of capital. Enterprise mergers and acquisitions occur frequently, and

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industrial development is becoming more and more concentrated in some innovative large enterprises. The pattern that corporate champion leads market is formed gradually. The trend of “bigger and stronger” is obvious [1]. Statistics in 2016 showed that the top three fabless IC design companies, Qualcomm, Broadcom, and Unicom, account for 40% of the global chip market share; the top five wafer foundries, TSMC, GlobalFoundries, Unicom, Samsung, and SMIC account for 80% of the global market share; the top three packaging and testing enterprises, such as ASE Technology Holding Co., Ltd., Amkor Technology, Inc., and JCET Group Co., Ltd., account for 40% of the world’s packaging and testing market share. 3. Accelerating the Shift of the Focus of Integrated Circuit Market and Manufacturing to the Asia-Pacific Region In terms of market share, the Asia-Pacific region is the fastest growing region, accounting for about 60% of the global market share, so there is a saying that “the Asia-Pacific wins the world.” Especially with the rise of China’s electronic products processing industry and the improvement of people’s consumption capacity, China has gradually become the largest consumer market of electronic products in the world. In terms of industrial structure, the manufacturing industry is increasingly moving to the Asia-Pacific region. From 1985 to 2000, Asia’s expenditure on chip expansion accounted for more than 70% of the world’s total. Especially after 2000, the expansion of chip production mainly concentrated in China and South Korea. Since 2014, Made-in-China 2025 and industrial funds in the field of integrated circuits have greatly promoted the investment and construction of local governments, private capital, multinational corporations, and leading domestic enterprises in China. From 2015 to 2016, 44 new and planned IC production lines have been built in China, reaching the highest number in history. 4. The Rhythm of Feature Size Reduction Slows Down At present, the industrial large-scale production of integrated circuit technology is still a semiconductor technology based on silicon material. According to the current development, it can be divided into three stages: the planar device process before 22 nm, the FinFET process at 14 nm/7 nm/5 nm/3 nm, and the GAA process below 3 nm, as shown in Fig. 23.1. There are different voices in the industry about the development direction of integrated circuit technology in the future, but it is certain that in the next few years, the silicon-based technology with feature size reduction as the development route will still be the mainstream of integrated circuit manufacturing technology; The rhythm of feature size reduction will slow down, and the Fig. 23.1 Process development stages of silicon integrated circuit

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number of transistors on chips will be increased by two times. The cycle has been extended to 30 months or longer (Moore’s law is about 18 months). However, due to the parallel development of multi-generation new processes adopted by some leading enterprises in the industry, new processes can still be delivered to the market in accordance with the rhythm of Moore’s law. At present, Intel, TSMC, Samsung, and other semiconductor giants have achieved 7 nm mass production. Both TSMC and Samsung also have achieved mass production of 5 nm products in 2020 and announce to implement the mass production of 3 nm products in 2022–2023. It should be noted that TSMC is still using FinFET process in the 3 nm process and plans to reuse GAA process at more advanced technological nodes. 5. Market Hotspots Gathering to Mobile and Intelligent Fields At present, the main application markets of integrated circuits are still computers, communications, and consumer electronics. With the emergence and development of new industries such as mobile internet, Internet of Things, cloud computing, big data, artificial intelligence, and so on, the hotspot of future integrated circuit market may shift to the above industries. Looking at today’s information industry, its development trend presents three characteristics: the Internet of everything, information explosion, and mobile use. In the future, the fifth generation mobile communication will no longer be a communication concept in the traditional sense, but an extension and expansion on the basis of the internet. Users can exchange and communicate information between any items. Such Internet of everything has brought about a high expansion of information, and the whole society has become an ocean of information. Terminal information products are increasingly communicated through mobile networks. As an important material carrier of the information industry, the integrated circuit industry has three characteristics; “reducing the power consumption,” “narrowing the line width and reducing the cost” emphasized by Moore’s law. In pursuit of higher speed and lower cost, integrated circuit enterprises will focus more on meeting the low power consumption requirements of products.

Business Characteristics of Memory IC Industry Typical integrated circuit products include logic circuit, memory, processor, analog circuit, and so on. In 2021, the sales of integrated circuit products amounted to US$556 billion (B), of which memory sales amounted to US$154.8 B, accounting for 27.8%. At present, half of the top 10 semiconductor companies in the world are involved in the memory business. The development of the integrated circuit industry often starts with memory. Japan and South Korea have surpassed the field of integrated circuits through the development of memory.

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1. The Memory Market Fluctuates Periodically Since the invention of transistors in 1947, the integrated circuit industry has been following Moore’s law. When the price remains unchanged, the number of transistors per unit area can be roughly doubled every 18 months, and so can the performance. In other words, the price of an integrated circuit with the same performance drops by half every 18 months. However, the price of memory products is in a cycle of rising and falling. Its periodicity is obviously stronger than the overall periodicity of the semiconductor industry, showing a strong correlation with social GDP. Take DRAM, a typical memory product, as an example, because of its special industrial characteristics and large fluctuations in supply and demand, so the price has the characteristics of long-term sharp ups and downs, and a large cycle will take place in about 8 to 10 years. The market size and growth rate of DRAM from 1991 to 2016 are shown in Fig. 23.2. For example, in 1998, the industry supply exceeded demand, and the industry suffered a large loss. In 2000, the internet technology bubble burst, and the demand from the upstream integrated circuit market suddenly dropped, and the price of single products dropped by more than 30%. In 2008, due to the impact of the financial crisis, the overall market demand was weak and product prices plummeted. The price of 16Gbit capacity DDR2 dropped more than 90% from $6 per unit in the fourth quarter of 2006 to $0.6 per unit in the first quarter of 2009. Starting in 2012, the industry has witnessed a new round of growth driven by the sustained growth of smartphones and the promising future of the Internet of Things [2]. Memory is in great demand, with the characteristics of high standardization, a single variety, suitable for IDM organization design, production, and sales of the entire process. However, due to the difficulty of differentiating products, such products are not enough to form enough customer stickiness and product premium,

Fig. 23.2 DRAM Market Scale and Growth Rate (1991–2016). (Data source: IC Insights)

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which leads to the fact that manufacturers can only compete on the technology and industrial scale. When the industry is in an upstream cycle, manufacturers constantly introduce new technologies to reduce the product feature size and expand the factory capacity. While the industry is in a downward cycle, manufacturers continue to cut shipment prices to maintain market share. Factors such as capacity expansion and technology iteration of memory manufacturers lead to sharp fluctuations on the supply side of the market, resulting in a special cyclical storm in the memory market. 2. The Memory Industry Has Formed an Oligopoly Structure Because of the high technical difficulty and capital expenditure of memory manufacturing, it needs a very high capacity scale and shipment volume to gain a foothold in the market. At the same time, the market fluctuates enormously, often in the environment of sharp falls and surges. In the downturn of the industry, enterprises will incur huge loss, and small manufacturing enterprises become unable to continue operating, leading to bankruptcy or acquisition by large enterprises. At present, the global memory industry has entered a highly monopolistic era. In 2008, the top five memory chip companies in the world were Samsung, SK Hynix, Micron, SanDisk, and Elpita (acquired by Micron in 2012), accounting for 75% of total revenue. By 2016, the top five global memory chip companies were Samsung, Micron, SK Hynix, Toshiba, and SanDisk, with total revenue accounting for 95%. 3. Mainstream Memory Enterprises Adopt IDM Development Model There are few independent design enterprises in the memory industry, which presents a completely different ecological situation from the logic circuit industry. At present, most of the mainstream storage enterprises in the world adopt the IDM development mode, which integrates design and manufacturing. For example, Samsung, Micron, and SK Hynix all have their own wafer manufacturer and back-end sealing and testing factory, and the industrial layout is relatively perfect. There are three main reasons for this phenomenon. First, this is determined by the product characteristics of the memory. Memory is a highly standardized product, and the key is to improve the storage density. The difficulty of manufacturing is that the coordination and communication between designers and manufacturers must be very frequent, while memory enterprises often need to strictly control the core technology and rarely outsourcing orders through OEM. Secondly, with the improvement of technology level, the cost of memory production line increases exponentially, and the development of new technology needs a lot of manpower and financial support. Finally, the core competitiveness of memory enterprises mainly lies in the large-scale production capacity with high yield, and the profits of IDM enterprises are more concentrated than the division of labor among three industries.

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To sum up, the memory cycle follows Moore’s law economically, and is mainly driven by the mainstream applications such as personal computers, smartphones, Internet of Things, and so on. The capacity scale is mainly influenced by the oligarchy operation mode of IDM. Besides, it incorporates the boom cycle of social economy, which becomes a complex data model.

Government Policies and IC Industry Development The IC industry serves different strategic functions from other industries, which requires the government to formulate specific policies for IC industry. In the field of national defense construction and national security, IC products can play an essential role in areas like weapons, communications, and data storage in a large scale, and hence enables the state to maintain sovereignty in wars. It can also indicate the core compatibility of a nation in economic construction and national power area [3]. Based on what mentioned above, countries are very cautious about the exportation and technology transfer related to the IC industry: they never treat the IC industry as a completely market-oriented industry. Therefore, states always control the trade of IC products restrictively. Under this circumstance, the development of the IC industry in a country cannot merely rely on the market, especially the latecomer countries. It is even more necessary for them to issue and implement policies to make the healthy development of the industry. The fiscal and taxation policies that the government can adopt include: changing financial support from government, adjusting the scale of credit loans for commercial finance; adopting relevant support policies for venture capital and private equity fund markets, guiding investment focus on the IC industry; supporting setting up and carrying out loan guarantee insurance and credit insurance business; establishing a fiscal and tax preferential policy system to directly serve the IC industry, including turnover tax, income tax and tariff, and depreciation policy applicable to IC enterprise accounting; establishing PPP (public-private partnership) mode to improve the development of IC industry; and setting up a transfer payment project for the IC industry. The industrial policies that the government can use include: supporting alliances cross industrial enterprises to help the establishment of an industrial chain ecology; assisting to form patent pools in the IC industry, establishing and guiding intellectual property strategic alliance, and promoting the use and protection of intellectual property rights in IC field; establishing standards in major innovation areas of IC, giving full play to technical standards and building an elite system in the IC industry [4, 5]. Throughout the history of the global IC industry, government policies have played an essential role. The new-coming countries use government policies to catch up with the developed countries, while the developed countries use government policies to protect their advantages and dominance in international competition. In South Korea, for example, in order to achieve economy growth

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policy, the government has issued policies mainly involving large enterprises. To ensure the compatibility of large IC enterprises, the government not only provides special treatments in terms of financial and taxation policies for large IC companies, but also provides preferential policies of low interest rates and low exchange rates for large IC companies. The governors monitored the direction of enterprise and even directly intervened in its activities. The government also developed special policies to encourage cooperation between large enterprises and SMEs (small and medium-size enterprises). The Korean Industry Association has also played an important role while promoting Korean economy, trade, and the development of large companies by providing member companies with reliable information and services for foreign trade training in a timely manner. The Korean government has also provided sufficient financial support for the development of the company, which means the company has invested heavily in research and development (R&D). This set of policies has laid the foundation for the sustained growth of economy [6].

Investment and Growth of IC Industry The IC industry has never been completely determined by the market. Government support is common in its history. In the early stages of development, private capital was generally reluctant to invest because of chronic losses. This requires the government to play a leading role and continue to invest in this strategically important industry, guide the private capital to gradually enter, and then gradually exit after the industry returns to market leadership. From the perspective of investment, the development of IC industry generally needs to be carried out into three steps within 15–20 years. The first step is based on government support. This stage needs to go through a period of about 5–7 years of corporate losses. The government laid the foundation for the healthy development of the industry and helped the company to survive the survival period and gradually find a position in the market competition. The second step is the combination of government and private capital. This stage is about 5–7 years. It needs more private capital investment to support the industry and cultivate one or two market players with international compatibility to make corporations adapt to the rhythm of market competition. The third step is based on the company and the government, but mainly on the former. This stage is expected to last 5–7 years. In this stage, the state-owned capital gradually exits, and private capital takes its place, which makes enterprises adapt to the market completely, and finally makes a virtuous circulation. To judge the growth stage of the company, we can refer to some economic indicators, such as gross profit margin. These indicators can also be used to analyze whether the industry should enter the next stage. In different stages, the government invests different amount to achieve the best match between the government and private capital, so as to achieve the best results.

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Technomic Factors for IC Industry Evolution Since the 1960s, the global IC industry has experienced three revolutions. The economic reasons that drive the revolutions also drive the transformation of the business mode of the IC industry. An analysis of these economic factors can provide insight into the evolution of the IC industry and help us anticipate future trends in IC business models. Every time the economic factors like market demand, capital threshold, and degree of economic division change, IC companies begin to find new entry points in the industry chain, which renews business model through continuous corporation and distribution of labor. The revolution of the business model of the IC industry is shown in Fig. 23.3 [7]. This section mainly analyzes the economic reasons for the transformation of the business model of the IC industry and the development trend of the future business model. In general, there are three main economic reasons driving the transformation of the IC industry business model: changes in market demand, restriction of capital thresholds, and the further refinement of industrial labor redistribution. Each change in the business is the result of the interaction of several reasons. In 1970s, the IC industry was still in its infancy with relatively simple and small market demand in scale. The industry’s funding threshold was relatively low, too. A company could complete the design, manufacture, and packaging steps of IC products by itself. Thus, most of the foreign IC companies adopted the Integrated Device Manufacturer (IDM) mode. Since the 1980s, the demand for IC market began to grow rapidly, and hence the demand for IC products has become more diversified. Some integrated device manufacturers are unable to adapt to the rapid change of market. In this context, the private equity fund helped a small group of

Fig. 23.3 Evolution of the business model of the IC industry

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experienced engineers set up a small IC design company to quickly design new products to meet market demands – this is the Fabless model. Also, since integrated device manufacturers have complex industry chains and long production periods, it is easy to lose market opportunities if corporations are negligent or delayed in a specific field. The Fabless model just made up for the weakness of integrated device manufacturer model. After the invention of Fabless mode, the semiconductor industry entered a new stage of the vertical distribution of labor [8]. The IC manufacturing industry is characterized by economies of scale. Largescale production can reduce the unit cost of product and thus enhance compatibility. In the late 1980s and 1990s, as the process upgraded faster, the capital threshold for manufacturing industry was constantly raised. Only a few manufacturers were able to expand their productivity. The larger and more specialized the corporation was, the more advantage it has in the market because of the economy of scale. The market in Taiwan was so small that local enterprises must enter the international market. So be the foundry mode (Foundry) and TSMC. The foundry mode lowered the threshold of the design industry and promoted the prosperity of small and medium IC design vendors, which mostly adopted the Fabless mode. The rapid development of Fabless and foundries has promoted the prosperity of vertical distribution of labor. Since then, the IC industry entered the era of international cooperation. After the 1990s, the division of labor in the IC industry was further refined. In pursuit of higher economic and industrial efficiency, most Fabless mode companies used design company IP (Intellectual Property) to speed up the product design process. It saves the company effort and shortens the time to market. During this period, professional IP companies, represented by ARM (founded in 1990), had emerged. EDA (Electronic Design Automation) tools in IC design had also been greatly improved. EDA technology greatly improved the efficiency and operability of circuit design and hence reduced the intensity of designing works. EDA companies continue to grow, and the competition is increasingly fierce. To help design companies reduce verification time and accelerate the process of the product appearing on the market, the three major EDA companies (Cadence, Synopsys, and Mentor) are committed to develop hardware simulation tools and manage the related market. The semiconductor industry hence entered an era of complete distribution of labor according to their professions. From the perspective of the historical trend, the distribution of labor can promote efficiency in industries. Despite this, IDM vendors still exist. Throughout the global semiconductor industry, IDM vendors including Intel, Samsung, SK Hynix, Micron, Texas Instruments, Toshiba, and NXP are among the top 10 semiconductor manufacturers. The IDM mode needs to meet three prerequisites: First, they possess the advantage on internal integrated resources, which requires a close cooperation among IC design, manufacturing, and packaging and testing. Second, they have technological advantages. Most IDM vendors have their own IP developing departments. After long-term technology research and experience accumulation, these departments possess sufficient technical reserves, strong development capacity, and leading position in technology. Finally, the product process is unreplaceable, which means the procedure cannot be done by foundry, such as CPU and memory.

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As the industry becomes more mature, the business mode is likely to change further, while the integration of manufacture, design, and packaging and testing will remain to exist. Based on the manufacture industry, the deep cooperation between IC design and packaging and testing manufacturers can make all links in the industry chain move quickly and hence improve industrial efficiency. In fact, both distribution of labor and integration are methods for industrial innovation. Every time the distribution of labor and innovation of business mode can make progress on society. After the distribution of labor, one corporation can focus on a certain field and develop core technologies, and then integrate its resource based on its profession. By this process, it may become indispensable in the industry.

Changes in Total Investment and Market Scale of Worldwide Semiconductor Industry Throughout the global semiconductor industry, the change of market scale shows a cyclical fluctuation pattern of overall upward and individual year downward. The investment of semiconductor industry is basically consistent with the changing trend of global semiconductor industry market scale. 1. Global Semiconductor Industry Market Scale The market size variation of the global semiconductor industry shows a cyclical fluctuation pattern of overall increase and individual annual decline. As shown in Fig. 23.4, the scale of semiconductor market grew nearly 100-fold from 1976 to 2021. Influenced by the financial crisis and the global economic environment, the

Fig. 23.4 The global semiconductor industry market scale changes (Data source: WSTS.)

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semiconductor market declined significantly in 1998, 2001, 2002, 2008–2009, and 2019. The figure above shows the compound annual growth rate (CAGR) from 1980 to 2021. 2. Investment Scale of Semiconductor Industry Investment in semiconductor industry is mainly divided into two parts: Fixed assets investment (i.e., capital expenditure), such as the expenditure of workshops, clean rooms, equipment, and materials used by wafer factories for the production line construction, the expenditure of purchasing servers and electronic design software by design enterprises, and intangible assets investment (mainly R&D investment). That is, the development cost of advanced technology. Capital expenditure of global semiconductor industry is slightly higher than R&D investment. For example, in 2021, the capital expenditure of global semiconductor industry is 153.9 billion US dollars (see Fig.23.5), and R&D investment is 71.4 billion US dollars. With the expansion of the semiconductor market scale, the total investment and the proportion of the semiconductor industry also show a growing trend. Similarly, affected by the financial crisis, the fluctuations in 2002 and 2008–2009 went down, which is basically consistent with the changing trend of the global semiconductor industry. That is, when the market scale expands, the corresponding investment will occur. It will also improve. 3. The First and the Second Countries Have Different Levels of Investment, with the Latter Spending Slightly Less on Research and Development As Moore’s Law reveals, the IC industry is developing rapidly at the rate of about two generations of technology nodes. The investment scale of leading enterprises

Fig. 23.5 Capital Expenditure in the Global Semiconductor Industry. (Data source: IC Insights.)

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(the first enterprise to complete the technological renewal, which is mostly the first state-owned enterprise) is slightly higher than that of the follower enterprises (those enterprises that have invested in the R&D of the technology after the technology has been conquered by the leading enterprises are mostly technology follower enterprises). This is mainly reflected in its R&D funding. The integrated circuit industry has the characteristics of “one generation technology, one generation equipment, and one generation product.” Especially for advanced technologies, it is necessary to purchase new equipment and build new factories [9]. Therefore, for new technologies, there is little difference between the scale of fixed assets investment required by leaders and technology followers. In terms of investment scale of intangible assets (mainly R&D), leaders need to spend a lot of manpower and material resources to plan research technology routes and find new materials to promote the latest technology; while technology followers can refer to research direction of leading enterprises to reduce R&D costs, as shown in Fig. 23.6. 4. Later-Developing Countries Must Invest More than First-Developing Countries to Achieve Technological Transcendence The advancement of technology directly determines the rise and fall of enterprises. The new technology products that are updated first have higher profit margins, and correspond to a large number of market demands, while the technology followers are difficult to make profits. Due to the relative weak technological foundation and the lack of professional talents and other factors, the latter countries need to complete a higher amount of investment than the first countries in order to achieve technological transcendence.

Fig. 23.6 Leader and follower R&D funding for different technology nodes (Data source: WSTS.)

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CAPEX and R&D Expense of IC Industry The integrated circuit industry is highly capital-intensive and technology intensive. Capital expenditure and technology R&D expenditure have become the two major expenditures in the investment of integrated circuit industry. 1. Capital Expenditure According to IC Insights, the capital expenditure of the semiconductor industry reached 152.67 billion US dollars in 2021, up 38% from 2020. The top three are Samsung, TSMC, and Intel. Samsung’s capital expenditure in 2021 was $38.1 billion, TSMC’s was $30 billion, and Intel’s was $20.3 billion. Memory manufacturing and wafer substation factories have become the main capital expenditure, accounting for 10 of the top 10 companies in capital expenditure. TI capital expenditure is 2.5 billion US dollars, an annual increase of 279%, which is the largest increase among the top 10 semiconductor enterprises. The top 15 semiconductor companies listed in Table 23.1 had capital expenditure of $134.7 billion in 2021, accounting for 88.2% of total capital expenditure. Memory manufacturers and wafer factories dominated the mainstream position of capital expenditure. Major memory factories accounted for 44.8% of total capital expenditure in the semiconductor industry. The data of major wafer factories also reached 27.4%. 2. Technology R&D Expenditure R&D investment is an important indicator reflecting the industry development and enterprise competitiveness. According to statistics from IC Insights, the global semiconductor industry’s R&D expenditure in 2021 totaled 71.4 billion US dollars, as shown in Table 23.2. Unlike capital expenditure, design firms, together with IDM, pure-play foundry, and memory companies, play a major role in R&D expenditure. IC Insights statistics show that with the continuous advancement of integrated circuit technology, the cost of new technology research and development is also increasing. Take Intel as an example. Over the past two decades, the overall trend of R&D expenditure as a proportion of revenue has increased, which was 16.4% in 2010, but by 2021, the proportion has reached 21.3%. 3. Different Investment Structures in Different Sectors From the perspective of economic return on investment, the integrated circuit industry as a whole requires long-term and patient investment. However, the strategic and economic duality of different links in IC industry is different, and the investment structure of different links is slightly different. Integrated circuit design industry belongs to the light assets sector. Although the cost of streaming and human resources is increasing year by year, it still belongs to light investment compared with manufacturing and packaging industries. Moreover, the production and sales

7

8

9 10

11 12

7

8

19 12

10 11

Texas Instruments Huahong Semi

CXMT

YMTC

Company Samsung Electronics TSMC Intel SK hynix Micron Technology SMIC

Data source: Gartner.

STMicroelectronics Kioxia (Toshiba Memory) 20 13 GlobalFoundries 14 14 UMC 13 15 Infineon Technologies Top 15 Companies’ Total ($Billion) Total Worldwide Capital Spending ($Billion)

2020-21 Rank 1 2 3 4 5 6

2020 Rank 1 2 3 5 4 6

Americas China(Taiwan) EMEA

Region South Korea China(Taiwan) Americas South Korea Americas China (Mainland) China (Mainland) China (Mainland) Americas China (Mainland) EMEA Japan • •

•

•

•

•

Foundry

Table 23.1 List of capital expenditures of semiconductor enterprises from 2020 to 2021

3.00 0.65 1.80

• •

•

•

0.50 1.00 1.08 95.74 110.24

1.28 1.10

3.50

•

• • •

2020 27.40 17.07 14.45 8.65 9.02 5.25

IDM •

1.80 1.72 1.61 134.66 152.67

1.83 1.80

2.46 2.38

3.40

3.75

2021 38.11 29.96 20.33 10.82 10.56 4.12

260% 72% 49% 41% 38%

43% 64%

279% 32%

13%

7%

2020-21 Change (%) 39% 76% 41% 25% 17%
22%

1.18% 1.13% 1.06% 88.20%

1.20% 1.18%

1.61% 1.56%

2.23%

2.46%

2021 Share (%) 24.96% 19.63% 13.32% 7.09% 6.91% 2.70%

23 Development Law and Development Index of IC Industry 487

Company Intel QUALCOMM SAMSUNG ELEC BROADCOM Nvdia TSMC

Region Americas Americas South Korea

Americas Americas China (Taiwan) 7 SK HYNIX South Korea 8 MediaTek China (Taiwan) 9 MICRON TECH Americas 10 AMD Americas Top 15 Companies’ Total ($Million) Total Worldwide Capital Spending ($Million)

4 5 6

2021 Rank 1 2 3

•

•

• •

•

Fabless

•

Foundry

Table 23.2 2019–2021Semiconductor enterprises R&D expenditure list

2,473 2,101 2,441 1,547 40,854 56,300

•

4,696 2,829 3,048

2019 13,362 5,398 2,959

•

•

IDM •

2,600 1,983 48,251 68,400

3,100 2,751

4,968 3,924 3,895

2020 13,556 5,975 5,500

2,663 2,845 56,141 71,400

3,672 3,469

4,854 5,268 4,504

2021 15,190 7,176 6,500

2.42% 43.47% 16.35%

18.45% 26.12%


2.29% 34.25% 15.64%

2020-21 Change (%) 12.05% 20.10% 18.18%

3.73% 3.98% 78.63%

5.14% 4.86%

6.80% 7.38% 6.31%

2021 Share (%) 21.27% 10.05% 9.10%

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cycle of chips in the market is relatively short, the investment recovery is fast, and the economic results can be quickly reflected. This kind of knowledge-based product is very risky, not suitable for traditional investment and financing methods, and difficult to obtain bank loans, thus only suitable for venture capital (VC). In the mature period of industrial development, there is also a need for sustained capital investment and other forms of capital intervention, such as private equity (PE) funds. Integrated circuit manufacturing industry and feudal testing industry belong to the heavy assets sector. The cost of plant construction and equipment investment in the early stage is high, and the investment return cycle is long. At the same time, driven by Moore’s law, its production lines and technologies have been constantly improving, with the characteristics of “one generation technology, one generation equipment, and one generation products.” It requires not only a large amount of investment, but also needs sustained investment. Therefore, from the beginning, it must be PE þ government + market + bank + other capital joint investment. The investment in manufacturing is characterized by large investment, long-term investment, and high investment barriers, and it is difficult and lack of confidence for private capital to enter. The integrated circuit industry is the guarantee of national information security, which is of great strategic significance, so it needs national investment funds to guide its development.

Entry Barriers of IC Industry Entry barriers are unfavorable factors that a new enterprise may encounter while entering an industry. Entry barriers protect existing enterprises in the industry and therefore become the first difficulty that newcomers must overcome. The IC industry possesses high density of capital and technology. Hence, with the continuous advancement of science and technology, the entry barriers are increasing. At present, the entry barriers are mainly the following aspects. 1. Patent Barrier In recent years, China’s IC industry has developed well, but the patent reserve is low. American companies still dominate the list of companies with the largest number of chip patents. For example, Intel and AMD have almost monopolized the CPU market. Intel has established barriers on the entire business including intellectual property, technology accumulation, scale cost, and software ecology, which have never shown sign of decline. For another example, the patent protection term in the United States is 20 years. While the original patent of FPGA design has not expired [10], companies involved in the FPGA industry must develop products by themselves. Before the FPGA patents expired, there were no FPGA companies in China. Hence, China’s FPGAs have fallen behind for at least

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20 years. In order to achieve the sustainable development of China’s IC industry, Chinese enterprises must independently master the core technologies quickly. Without core technology and focusing only on the expansion of the industry, it will be easy for competitors to block themselves through patents in the future competition. Therefore, entering the IC industry will face higher patent barriers. 2. Political Barriers In the information era, information security has become the core field of political and economic combats among countries. As the core of the information field, ICs are of great strategic significance for ensuring national security. Thus, some newcomers also need to overcome political barriers. 3. Technical Barriers The IC industry is a typical technology-intensive industry. Therefore, if an IC enterprise wants to grow, it must possess technical compatibility. Also, because of the rapid metabolism of IC technology and products, IC companies are supposed to possess ability for continuous revitalization and hence meet the changing market demands. Besides, the manufacturing process of IC is complex, and the precision is high. Therefore, to revitalize technology and manufacturing process, IC enterprise needs to go through long-term, large-scale research and practice. With the development of the packaging and testing industry, advanced packaging technology has become the barrier for new entrants. For reasons above, new entrants also need to take technical barriers into consideration. 4. Capital Barriers The IC industry always needs large investment, but the investment returns are slow while the risk is high. The existing capital barriers are mainly shown in two aspects: First, the development of industry requires a large amount of capital investment; second, the investment have a long return period and low return, which means the investors need to wait for a long time. The IC manufacture industry currently receives the largest investment in the whole manufacture industry. For example, a 300 mm 14 nm production line requires the investment of up to 10 billion US dollars: each process node needs to be invested continuously for at least 5 years before it will yield revenue [11, 12]; Also, the IC design industry requires a large amount of money for R&D employees, the imported equipment and technology, and the R&D of products. Finally, the new packaging technology also requires huge capital investment. Therefore, no matter which part the entrant prepares to participate in, it must consider that whether the capital investment can maintain various expenditures or whether new entrants can take the financial risks themselves. Therefore, the new entrant also needs to overcome capital barriers to enter into the IC industry.

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5. Human Resource Barrier The IC industry is a high-tech industry. Admittedly, policies and funds are indispensable factors, but the core factor for enterprises to become bigger and stronger is technology, which depends on professional elites. At present, the professionals in China’s IC industry are very scarce, unable to meet the need of the industry. Therefore, for newcomers, human resource barriers are one of the major problems they have to face. In the IC design industry, creative technical elites and experienced managers can help enterprises improve efficiency and maintain their leading position in technology field; in IC manufacturing industry, enterprises need process technology R&D elites; in IC packaging and testing industry, the new packaging and testing technology elites are essential for a company. No matter how these elites are introduced, the cost and difficulty for bringing them is high. Thus, human resource is also a restrictive barrier for newcomers to the industry.

Regional Migration of IC Industry Where there is a market, there is the industry. From the 1960s to the present, the IC industry has undergone three distinct regional evolvements as the market has changed [13]. In the 1960s, the integrated circuit industry experienced its first regional evolution. The reason for this evolution is that the United States has a comparative advantage in IC design, while Asia has a comparative advantage in labor costs. As a result, the international division of labor and transfer of integrated circuit industry began: the testing industry and packaging industry began to shift from the United States to Asia. At present, China, Malaysia, and Korea are the main IC packaging and testing bases in the world. In the 1970s, there were barriers to trade in integrated circuits between Europe, the United States, and Japan. The trade cost of exporting integrated circuits was very high. American enterprises reduced the trade cost by establishing manufacturing factories in Japan and Europe. At the end of 1980s, Taiwan IC foundry industry, represented by TSMC, seized this historic opportunity, avoided the vicious competition dilemma of American and Japanese enterprises, and took a new path. It chose to provide wafer manufacturing OEM for semiconductor companies in these countries, thus transforming competition into win-win cooperation and others. The success of the national and regional semiconductor industry has led to the rapid growth of wafer manufacturing agent business in Taiwan, China. Dedicated Foundry TSMC has rewritten the business model of the semiconductor industry. After the establishment of TSMC, integrated circuit manufacturing industry began to shift to China. This is the second significant regional evolution of the integrated circuit industry, in which the industrial transfer is mainly concentrated in the manufacturing sector.

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The third regional evolution is mainly the transfer of integrated circuit design industry, which aims to be closer to the local market and reduce risks. The design industry began to shift from the United States to Japan and Europe in the 1970s, to Taiwan and Singapore in the late 1980s, and to mainland China in the twenty-first century. Many international chip companies, including Intel and Texas Instruments, have established R&D centers in China, mainly engaged in the development of system software and product solutions. With the three regional evolutions of global integrated circuit industry, the market demand, enterprise development, and investment structure of integrated circuit industry have also undergone regional changes. We have observed the trend of its evolution from the United States to Japan, to South Korea, and then to China.

IC Industry Investment and Industrial Ecology Development Industrial ecology refers to the comprehensive environment in which industries are in the process of development. Unlike the industrial chain, it is influenced by many external factors, such as the national policy and regulation of the IC industry economy and investment, the reformation of the mechanism system, the research and development technology revitalization, and the investment and financing situation, etc. For the IC industry, industrial investment will greatly affect the construction of the IC industrial ecology. Reasonable investment and acquisitions will help to build the IC industrial ecology. Blind investment or diversification of investment will seriously damage to the industrial ecology. For example, Taiwan had also invested heavily in the memory industry, but it has not worked well. There are three main reasons: From the perspective of developing mode, Taiwan adopted the foundry mode to develop memory enterprises, which mostly failed in DRAM; from the perspective of technology, Taiwan DRAM manufacturers relied too much on technology transplantation, which means a lack of self-developed technology; in terms of the market, the enterprises’ performance in the global memory market is not satisfactory, while past investments have made the first two-third of Taiwan’s total production aimed in the storage industry, which results in an over-supply situation. As a result, the prices of DRAM and NAND flash memory have fallen a lot, which is unfavorable for Taiwan’s memory companies [14]. In contrast, after the 1980s, the Korean government began to support the DRAM industry, to be specific, the Samsung Semiconductor. The government organized a DRAM R&D project jointly undertook by the official and unofficial powers. The support from the government has strongly promoted the DRAM industry and created a healthy industrial ecology. Moreover, when the global semiconductor market was unfavorable and the DRAM industry was in a downturn, Samsung has adopted a counter-cyclical investment strategy to double investment in its R&D in self-developed technology to cultivate high-end elites and expand production. This strategy makes it become one of the most advanced memory manufacturers in the world [15].

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In summary, every achievement requires a variety of factors. No strategy can be easily replicated, so as the investment for the IC industry. It is helpful for the IC industry to scientifically plan for the development of the IC industry and select appropriate investing strategy by combining the characteristics of the nation, the local place and enterprise itself. Appropriate strategy is conducive to the establishment of the ecology with a virtuous circulation, which is of great significance to the IC industry.

Relationship Between Investment and Technology Advancement in IC Industry The integrated circuit industry is a capital-intensive industry. Its investment characteristics are large scale, high risk, and long return cycle [16]. With the progress of integrated circuit technology and the increasing complexity of integrated circuit technology, integrated circuit enterprises must keep up with the latest technology and increase investment in R&D personnel, plant, and equipment. Therefore, the production and R&D costs of integrated circuit are getting higher and higher, and the scale of investment is getting larger and larger. 1. The Scale of Investment in IC Industry Increases with Technological Progress For the semiconductor industry, technology is life. Only by mastering the most advanced technology can we hold a place in the market. The progress of technology nodes will increase capital expenditure and R&D expenditure. Take the integrated circuit manufacturing industry as an example, with the reduction of feature size, each new generation of technology, especially advanced technology, requires the re-purchase of new equipment, which leads to the continuous expansion of investment scale. As can be seen from Table 23.3, after entering 32 nm, the investment cost of each technology node is about 1.5–2 times that of the previous generation technology, and it needs continuous high-intensity investment to build production lines to form a strong scale advantage. 2. The IC Industry Has Not Only a High Investment Threshold, but Also a High Investment Risk Table 23.3 Estimates of wafer fab investment for different technological nodes Technological nodes IP/EDA, etc. designer cost ($Million) Capex ($Million) R&D spending ($Million) Monthly capacity

90 nm/65 nm 15~20

32 nm/28 nm 60~70

22 nm/20 nm 100~150

16 nm/14nm 200~300

2500~3000 200~400 35000~50000

3600~4500 600~800

4600~5700 1000~1300

5600~7000 1700~2500

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With the increasing demand for investment scale in the IC industry, the investment risk is becoming greater and greater, thus, most IC enterprises are afraid to upgrade their technology. As shown in Fig. 23.7, technology giants with strong R&D teams can hardly support the continuation of technology. Only a few companies insist on investing in the latest technology. 3. The IC Industry Must Continuously Invest in the Development of Advanced Technology Although the expansion of investment scale and the existence of higher investment risks increase the difficulty of investment, integrated circuit technology is bound to progress, and related enterprises need to invest in the development of the latest technology. First, human society has entered the information age. New emerging industries such as artificial intelligence, Internet of Things, big data, and mobile internet need more advanced integrated circuit products to support them. Market is the foundation of enterprise survival. Driven by the market, technology must also progress. Second, the integrated circuit industry has been following Moore’s law. Once the new generation of technology breaks through, the price of the products of the previous generation of technology nodes in the market will fall rapidly. The non-hedging characteristics of information products prompt enterprises to transfer to advanced technology. Third, the main share of future industrial growth still comes from advanced technologies (see Fig. 23.8). In summary, the integrated circuit industry must continuously invest in the development of advanced technologies. .

Cost Structure Analysis of IC Products The cost of integrated circuit products mainly includes manufacturing cost and design management cost. 1. Manufacturing Cost Each IC is manufactured through a series of steps including photolithography, etching, ion implantation, metal deposition, interconnection, wafer testing and die cutting, core packaging, and final grade testing. The cost of these processes is the cost of IC manufacturing. The manufacturing cost can be divided into three parts: chip cost, test cost, and packaging cost [17]. Manufacturing cost ¼

Chip Cost þ Packaging Cost þ Testing Cost Yield

Chip cost can be understood as the cost allocated to the chip which formed through the wafer cutting step. Generally, chip cost accounts for 50–60% of manufacturing cost.

Development Law and Development Index of IC Industry

Fig. 23.7 Worldwide Fab Facilities list within 130 nm ~ 3 nm technological nodes (including mass-produced and researching) (* Intel’s chips with 7 nm process haven’t mass-produced in 2021, but the density of Intel chips with 10 nm process can be compared with TSMC’s and Samsung’s 7 nm products.)

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Fig. 23.8 2006–2025 Actual and projected turnover of the global pure-play foundry market for integrated circuits (Data source: Gartner)

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Chip costs can be simply calculated and expressed by the following formula: Chip cost ¼

Wafer cost number of chips per wafer ⁎ Yield

Packaging is to bond bare chips with substrates to form integrated circuit products sold in the daily market. Packaging costs account for 30–40% of manufacturing cost. The traditional packaging cost is proportional to the pin number and power consumption of the chip. However, with the development of technology, the number of pins is no longer the main reason to determine the packaging cost. Each chip has to undergo a series of test steps to test its key characteristics, such as the maximum frequency, power consumption, calorific value, etc., before it leaves the factory. Usually, the test cost accounts for about 10–15% of the manufacturing cost. The traditional test cost is proportional to the number of pins on the chip. With the development of 3D packaging technology, the test cost will no longer follow this rule. In addition, enterprises that do not own their own intellectual property rights have to pay licensing fees to the corresponding IP vendors for each produced wafer, which usually accounts for about 5% of the manufacturing cost. 2. Design Management Cost Design management cost is close to the manufacturing cost, which can be simply divided into design R&D cost, management cost, and marketing cost. Design and R&D costs include engineer’s manpower cost, EDA tool cost, third-party IP cost, etc. Management cost refers to the expenses incurred by the administrative departments of enterprises to organize and manage production and operation activities, such as wages and welfare, office expenses, posts and telecommunications expenses, insurance premiums, and other expenses. Marketing cost refers to expenses related to marketing activities. For integrated circuit enterprises, design and development costs account for the highest proportion of design and management costs. The development of integrated circuit industry cannot be separated from the promotion of advanced technology, and advanced technology cannot be separated from human control. The lack of high-end talents will restrict the development of integrated circuit enterprises. It is particularly important to respect talents and give full play to their advantages. Appropriately increasing the cost of design management can attract and retain more excellent professional and technical personnel as well as excellent management personnel who are familiar with the laws of industrial development. 3. Variation of Product Cost of Different Technical Nodes As predicted by Moore’s law, the core cost of the chip which achieves the same function decreases after adopting advanced technology. For those high-density chips, this downward trend is more obvious. For each generation of technology

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below 28 nm node, the decline rate of core costs tends to moderate. When the next generation chips with complex functions come out, they will enter the era of high price and high quality.

Production Scale Optimization for IC Manufacturing Industry Integrated circuit manufacturing industry is an industry with slow investment effect, high risk and obvious scale effect. Enterprises must invest heavily in the research and development of new technologies to ensure competitiveness in the market and to be able to withstand the risks brought by industrial cycle fluctuations. Under the premise of insufficient supply in China’s integrated circuit market, enterprises should estimate a minimum production scale, that is, marginal cost equals average cost. Then production is carried out to ensure that new production lines can maintain a basic balance of revenue and expenditure without losing money. Today, compared with the 1970s, the investment capital required for the new generation production lines has increased tens or even hundreds of times. At present, the investment of 200 mm production line is more than 1 billion US dollars [18]. The investment of 32 nm/28 nm production line of 300 mm is even more than 5 billion US dollars, and the investment of 14 nm production line can reach 10 billion US dollars [18]. For the integrated circuit manufacturing industry, the expenditure of each production line can be roughly divided into two parts: Variable Costs that increase or decrease with the change of production quantity, such as the cost of consuming raw materials, patent fee, administrative expenditure, sales expenditure, and technological research and development expenditure. Fixed costs that are relatively independent of production, such as design costs, construction costs, and equipment purchase costs. The larger the proportion of fixed costs, the more the costs are spread over a larger number of products, and the more marginal costs are lower than the average costs. On the contrary, the difference between marginal cost and average cost is not significant, and the impact of scale on revenue is relatively small. The following is an example of a 28 nm production line with a maximum 300 mm wafer capacity of 50,000 pieces. The fixed cost investment of the production line is US$5 billion, depreciated by 7 years, and the depreciation cost of each wafer is about US$1200 at full production. Assuming that $1200 accounts for about 50% of the total cost (and the variable cost of a single wafer is also $1200), we can roughly calculate the minimum production scale (calculated at a net return of 0) based on the following formula [19, 20]. Chip price ¼

fixed cost investment þ variable cost ⁎ ð1 þ net returnÞ depreciation years ⁎ 12 ⁎ monthly copacity

For example, when a single wafer sells for $3600 in the market, its minimum production scale is about 25,000 pieces per month. Under the above conditions,

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Fig. 23.9 Analysis of quantity-cost-profit of production line model. Based on US$5B investment, maximum 50,000 wafers (300 mm) per month is deduced

Fig. 23.9 shows the relationship between production scale and benefit. Because the influence of different production scales on variable costs is ignored, the relationship between production scale and benefit is linear. Through the above model, we can get the reverse trend of wafer price and minimum production scale. That is to say, the lower the price of a single wafer and the smaller the profit margin, the higher the requirement of minimum production scale, the greater the pressure on factory production. Figure 23.9 shows the Quantity-Cost-Profit of Production Line Model based on an investment of $5 billion and a maximum monthly capacity of 50,000 pieces (diameter 300 mm).

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After reaching the minimum production scale, according to the law of diminishing marginal returns, we can theoretically calculate an optimal production scale. However, from a macro point of view, the supply of the entire Chinese integrated circuit industry market is less than the demand, that is, the existing semiconductor production line capacity has not yet met the market demand. Therefore, it is not the marginal profit that determines the scale of production, but the market capacity and whether the designed maximum production scale can be reached. On this premise, the larger the scale, the higher the revenue will be. Compared with the shortage of supply in China’s integrated circuit market, the global integrated circuit industry should consider its strong monopoly characteristics. According to the development experience of the global integrated circuit industry in the past decades, the top companies often occupy the majority of market share in the subdivision field, presenting the oligopoly development pattern of “the bigger is the bigger.” According to the US Semiconductor Manufacturing: Industrial Trends, Global Competition, and Federal Policy, the IC market is an imperfectly competitive market, which will result in a special “optimal scale of production” [21]. That is, in this market, the price of products is higher than the average cost, and the average cost is higher than the marginal cost. Monopoly firms can make economic profits. However, because the overall market demand is limited, they cannot expand production capacity indefinitely. At the same time, they need to consider the competitive relationship with other monopoly firms, so they need to keep producing. Quantity oligopoly games should continue to find the best scale of production.

Profit and Loss Characteristics of IC Manufacturing Industry The integrated circuit manufacturing industry is a typical asset-heavy link in the integrated circuit industry. It has the characteristics of slow investment, high risk, and obvious scale effect. While enterprises continue to invest a lot of money in new technology research and development to maintain market competitiveness, they also need to bear the risks brought by industrial cycle fluctuations. Throughout the whole IC manufacturing industry, due to the high depreciation caused by the high investment of assets in the early stage, its profit and loss is usually characterized by the pressure of loss in the early stage. After 5–7 years of high depreciation and capacity climbing period, its profitability gradually improves. The reasons for the profit and loss characteristics are as follows. 1. Large Investment, Long Period of Return, and High Risk in Industry Taking the production line construction as an example, the investment of 65 nm production lines with a monthly capacity of 50,000 pieces of 300 mm is about 3 billion US dollars, and the investment of 32 nm/28 nm production lines is even 5 billion US dollars [16]. Besides the huge investment in the early stage, it will take a long time to achieve large-scale production and generate benefits. In addition, enterprises need to continue to invest a large number of R&D personnel and capital

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to improve their technical expertise; otherwise, they will be gradually squeezed out of the historical stage because of backward technology. The above two kinds of investment are indispensable, which intensifies the investment risk. 2. Greater Depreciation and Amortization of Fixed Assets (Equipment, Plant Construction) Integrated circuit wafer manufacturing enterprises are typical asset-heavy enterprises, whose capital expenditure such as Depreciation and Amortization accounts for a large proportion. Take the integrated circuit manufacturing company SMIC as an example, referring to the Financial Statement of CITIC International in 2016, its annual revenue is about 2.914 billion US dollars, the gross margin is about 850 million US dollars, and its sales cost is 2.064 billion US dollars (depreciation and amortization is 729 million US dollars), that is to say, 35.32% of its cost is depreciation and amortization items. Compared with asset-heavy enterprises such as integrated circuit manufacturing, the impact of depreciation and amortization on fixed assets in light-asset companies such as IC design companies is minimal. According to the financial report of Broadcom in 2016, its annual revenue was about 13.24 billion US dollars, gross profit was about 5.94 billion US dollars, and sales cost was 5.295 billion US dollars. Among them, the depreciation and amortization amount was 763 million US dollars, accounting for 14.4% of its sales cost, which is much lower than the depreciation and amortization cost of IC manufacturer SMIC. The capital expenditure of IC manufacturing enterprises mainly includes the expenditure of plant and equipment. Equipment expenditure generally accounts for 80% of capital expenditure, while land, plant, and other expenditures account for about 10%. In addition, fluctuations in product prices and sales may also affect the profit and loss situation of wafer manufacturing enterprises. Non-hedging is a common feature of electronic products. According to Moore’s law, advanced technology products of integrated circuits are renewed every 2 years or so. The new technology products that are updated first not only have a high profit margin, but also correspond to a large amount of market demand. This huge market demand and corresponding profit margin can make each manufacturer continuously expand the production capacity of more advanced products during the industry’s upward cycle. However, with the increased number of IC companies that have made technological breakthroughs, the price of this kind of products will drop dramatically. Considering the market competition factors, all but the most advanced companies in the industry have very little profit margins.

Shareholder Structure of IC Foundry IC foundry companies have their unique share-hold structure, that is, upstream and downstream companies cannot hold a controlling stake in it. In the face of all design enterprise customers, foundry companies must maintain their absolute

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independence in area of intellectual property. If an IC design company or a group of industrial capital with a design department enters the foundry field, this foundry field will lose customers because customers will doubt the independence. This also makes it hard for a specific capital to hold a large proportion of foundry enterprises, especially a design enterprise or a group industrial capital with a design department and vice versa. In order to ensure the intellectual property security of design enterprises, the corporate governance (equity design) of the foundry enterprises is highly selective. Otherwise, foundry enterprises will lose their independence in this industry mode, thus losing the market (customer), and eventually diminish. In addition to protecting the intellectual property rights of customers (design companies), OEMs also pay great attention to the protection of their own intellectual property rights in the case of founding factory offshore. At present, international competitive IC companies have invested in wholly-owned enterprises in mainland China, including Samsung and Intel. These companies adopt this model mainly because they are worried about the loss of core technology and thus lose their advantage in competition. The protection of intellectual property rights from IC foundry enterprises can be divided into three aspects: design companies, foundry companies, and industrial chain partners. The intellectual property of customers and partners in the industry chain is more important than that of others. Thus, to protect the intellectual property of customers and industrial chain partners, foundry enterprises must design their own shareholding structure to maintain their independence and neutrality.

Prosperity Indicators of Statistics for IC Industry In the study of the prosperity in IC industry, three statistical indicators are generally used: B/B ratio, capacity utilization rate, and WSTS forecast. The B/B (book-to-bill) ratio is used to survey the upstream purchasing situation of IC enterprises, serving as an ex-ante indicator. The capacity utilization rate is for studying the equipment utilization rate in IC enterprises, serving as an intermediate indicator. The WSTS forecast is used to investigate the income purchased from IC enterprises by downstream clients, serving as an ex-post indicator. The interaction between the three forms a system of statistical indicators to measure the prosperity of IC industry. The B/B ratio is discussed in detail in Sect. 1. The capacity utilization rate refers to the utilization efficiency of the production equipment capacity in IC manufacturing enterprises. Due to that the cost of equipment purchases accounts for a large proportion of the total investment in an IC manufacturing enterprise, it will directly affect the productively beneficial level of the manufacturing enterprise whether the equipment capacity can be fully

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utilized. From a micro perspective, the capacity utilization rate reflects the busy degree of the equipment in the manufacturing enterprise. From the macro point of view, it indirectly reflects whether the downstream demand is high enough. Generally speaking, a capacity utilization rate above 90% indicates the strong downstream demand for the design of chips, and the industry is in a period of prosperity, which typically prompts the manufacturing enterprise to build new production lines. WSTS collects and processes the monthly sales data from its member companies to sort out and analyze them, while making predictions for the future. Since WSTS’ data is directly from each member enterprise, WSTS’ periodic statistics and forecast is already beyond the scope of indirect indicators and are more similar to a largescale survey. With certain authority, it has become one of the statistical indicators to judge the prosperity in global IC Industry.

Prosperity Indicators of Securities for IC Industry Two indicators of securities, the PHLX Semiconductor Sector Index (SOX) and the Taiwan Stock Exchange Semiconductor Index (TWSESCI), are typically used for reference to assess prosperity of the IC industry. 1. SOX SOX is one of the main indicators reflecting the prosperity of the global IC industry, which is the stock price weighted option index. The SOX index was established on December 1, 1993, and was listed for trading since September 7, 1994, under the option index symbol SOX. By the end of 2016, SOX was composed of the stock prices of 23 companies primarily involved in manufacturing, design, equipment, and distribution in the semiconductor industry. The list of enterprises is shown Table 23.4. 2. TWSESCI Similar to SOX in nature, TWSESCI is an industrial data indicator that reflects stock prices and market value of semiconductor enterprises listed in Taiwan, based on the change of stock prices. The indicator adopts June 29, 2007, as the base date and 100 as the base index, and has been released since July 1, 2007. IC giants listed in Taiwan include TSMC, MTK, ASE, UMC, and SPIL. The stock prices for all semiconductor companies listed on Taiwan Stock Exchange are included in TWSESCI’s assessment. Because the capacity of IC industry in Taiwan ranks among the top in the world, TWSESCI, similar to SOX, is one of the important reference indicators reflecting the prosperity of the regional IC industry and even the global IC industry.

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Table 23.4 List of SOX enterprises No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Securities Code SWKS AVCO ON MXIM МСНР CREE TSM LRCX TXN MU INTC CAVM TER ADI KLAC AMAT ASML LLTC XLNX MRVL NXPI NVDA QCOM

Enterprise Name Skyworks Solutions Inc. Broadcom Limited On Semiconductor Corp Maxim Integrated Products Inc. Microchip Technology Inc. Cree Incorporated Taiwan Semiconductor Manufacturing Lam Research Corp Texas Instruments Inc. Micron Technology Inc. Intel Corp Cavium Networks Inc. Teradyne Inc. Analog Devices Inc. KLA-Tencor Corp Applied Materials Inc. ASML Holdings Linear Technology Corp Xilinx Inc. Marvell Technology Croup NXP Semiconductors NVIDIA Corporation Qualcomm Inc.

Chinese Name 思佳讯 博通 安森美 美信 微芯 科锐 台积电 泛林 德州仪器 美光 英特尔 泰瑞达 亚德诺 科天 应用材料 阿斯麦 凌力尔特 赛灵思 美满 恩智浦 英伟达 髙通

Note: After Avago acquired Broadcom for a price of 37 billion US dollars, the newly formed parent company was named Broadcom.

References 1. Z. Zhou, Research on investment and financing of Chinse IC industry (Publishing House of Electronics Industry, Beijing, 2015), pp. 111–144 2. P. Chen, R. Dong, Memory Industry Series II: Taking History as a Reference, Discussing the Opportunities China Faces from the Historical Law of Memory Development (Haitong Securities Company Limited, Shanghai, PRC, 2015) 3. X. Rui, Research on development strategy of integrated circuit industry in China, M.S. thesis (Dept. Business Administration, Fudan Univ., Shanghai, China, 2009) 4. State Council of China. 2014. Outline of National Integrated Circuit Industry Development and Promotion. 5. Jinliang Yun, “Research on Tax Preferential Policies to Promote Innovation of High-Tech Industries.”, Ph.D. dissertation, Dept. Business Administration, Univ. of Inner Mongolia, Hohhot, China, 2012 6. Z. Zhou, Development practice and enlightenment of Korean information industry and big companies, vol Chapter 3 (Publishing House of Electronics Industry, Beijing, China, 2006) 7. Z. Zhou, Research on investment and financing of China's IC industry, 1th edn. (Publishing House of Electronics Industry, Beijing, China, 2015), pp. 131–132

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8. M. He, Research on International competitiveness of IC industry in Mainland China., M.S. thesis (Shanghai Normal University, Shanghai, China, Dept. Economics, 2008) 9. Z. Zhou, Research on investment and financing of chinse IC Industry (Publishing House of Electronics Industry, Beijing, 2015), pp. 7–24 10. F. Liu, A comparative study of patent systems in ASEAN countries. Intellectual Property 15(1), 51–57 (2015) 11. Z. Zhou, Promoting the accelerated development of IC industry with supply-side reform. Review of Industrial Economics, 5–8 (2016). https://doi.org/10.19313/j.cnki.cn10-1223/f. 2016.01.001 12. Z. Zhou, analysis on the situation and development characteristics of IC industry. Review of Industrial Economics 4, 5–9 (2014). https://doi.org/10.19313/j.cnki.cn10-1223/f.2014.06.001 13. Z. Zhou, Research on Investment and Financing of Chinse IC Industry (Publishing House of Electronics Industry, Beijing, 2015), pp. 131–136 14. D. Mo, The dream of electronics memory in Taiwan broken, http://www.elecfan.com/article/90/ 156/2017/0109471445.html?148394373. Accessed 01 09 2017 15. Enlightenment of Samsung Electronics Memory Development to China. http://www.360doc. com/content/17/0203/11/30123241_626174512.shtml. Accessed 02-03-2017 16. Z. Zhou, Research on investment and financing of chinse IC industry (Publishing House of Electronics Industry, Beijing, 2015), pp. 61–73 17. Capital expenditures based on NAICS 3344 (semiconductors and other electronic component manufacturing) from the U_S_Census Bureau's Annual Capital Expenditures Survey. http:// www_censusgov/programs-surveys/acms_html_ .Accessed. 03-15-2017 18. Z. Zhou, Research on Investment and Financing of Chinse IC Industry (Publishing House of Electronics Industry, Beijing, 2015), pp. 61–64 19. M. He, Research on International Competitiveness of Integrated Circuit Industry in Mainland China, M.S. thesis (Dept. Electron. Eng., Shanghai Normal University, Shanghai, China, 2008) 20. Capital expenditures based on NAICS 3344 (semiconductors and other electronic component manufacturing) from the U.S. Census Bureau http://www.census.gov/programs-surveys/aces. html. Accessed 03 15 2017 21. M.D. Platzer, G. J. Harrison, 2016. The U. S. automotive industry: National and state trends in manufacturing employment. Washington, DC: Congressional Research Service [OL /666, press release June 27.

Financial Management Practice and Analysis of Enterprises

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Ying Cai, Yuwen Xue, Yanlun Yan, and Jianyue Pan

Contents Financial Statements and Analysis Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Balance Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Income Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cash Flow Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capital Expenditure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Market Share . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gross Margin Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Depreciation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EBITDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Financial Indexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Price-to-Earnings Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Goodwill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equity Incentive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Common indexes, concepts, and indicators of financial management practices, and analysis of enterprises, are introduced in this chapter. An overview is presented to describe financial statement, the most important tool used to observe and analyze the financial situation of a company. The key financial indexes frequently used to study IC enterprises, like CAPEX, profit and earning, depreciation, and R&D are discussed. Common concepts that will be used in IC enterprises management reports or market reports are introduced, like shipment, Y. Cai (*) · Y. Yan · J. Pan Summitview Capital, Beijing, China e-mail: [email protected] Y. Xue Zhongjing Industrial, Xi’an, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_24

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ASP, market share, and product category. Three special topics are introduced: Price-to-Earnings ratio is one of the most fundamental indicators to analyze enterprise’s valuations; Goodwill frequently arises from mergers and acquisitions; Equity incentive is an effective complement to a company’s salary system, especially for IC enterprises. Keywords

Financial statement · Profit · Depreciation · Market share · ASP · Price-toearnings · Equity incentive

Financial Statements and Analysis Methods When we observe and analyze the financial situation of a company, the most important tool is the company’s financial report, including financial statements and related information disclosed at the same time (generally presented in notes). The financial statements should include at least three major statements, these are Balance Sheet, Income Statement or Profit and Loss Statement, and Cash Flow, which are referred as “Three statements.” In some smaller companies or start-ups, the reporting structure is simpler and sometimes does not include the cash flow statement. The financial statements prepared by the enterprise that fully implements the enterprise accounting standards shall also include the Statement of Stockholders Equity.

Balance Sheet Balance sheet is an accounting statement that reflects a company’s financial situation at a particular date. The purpose of a balance sheet prepared by a company is to faithfully reflect the amount of assets, liabilities, and owner’s equity and its structure, in order to help users evaluate the quality of corporate assets and short-term solvency, long-term solvency, and profit distribution capacity. For IC enterprises, special attention should be paid to items such as accounts receivable, inventory, intangible assets, goodwill, accounts payable, short-term loans, and long-term loans. In addition, as for IC manufacturing enterprises and packaging enterprises that invest heavily in capital expenditures, more attention should also be paid to fixed assets, projects under construction, long-term prepaid expenses, and other projects.

Income Statement The income statement is an accounting statement that reflects the business results of the company during a certain accounting period. The purpose of preparing the income statement is to faithfully reflect the income made by the enterprise, the expenses incurred, the gains and losses that should be included in the current profit,

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and other comprehensive income and its structure, and to help users analyze and evaluate the profitability, the composition, and the quality of the company [1]. For IC companies, most should be concerned about operating income, operating costs, operating expenses (selling expenses, general and administrative expenses, financial expenses, as well as research and development expenses), operating profits, net profits, as well as the proportion of various costs, expenses, and profits to revenue, that is, gross profit margin, operating profit margin, net profit margin, etc. The cost of research and development (R&D) is also a kind of operating expense. In technology-intensive industry, IC companies generally invest more in R&D. R&D expenditure directly reflects the investment of IC companies in technology, which also provides the opportunities for IC companies to gain technology competitive advantages in the future. According to the “Accounting Standards for Business Enterprises” formulated by the Ministry of Finance of China: the expenditures of R&D projects within an enterprise should be divided into the research phase and the development phase. The expenditures in the research phase should be recorded in the current profit and loss, that is, the income statement. When certain conditions are met, the expenditure in the development phase can be recognized as intangible assets and capitalized, which can be amortized through intangible assets without affecting the current profit and loss [2]. At present, the processing of R&D expenses of China’s corporate accounting standards has adopted the treatment methods of International Financial Reporting Standards (IFRS). However, in the United States Generally Accepted Accounting Principles (US GAAP) the R&D expenses are not allowed to be capitalized and should be recorded in the R&D expenditure under the operating expenses of income statement. Attention should be paid to the impact of differences led by accounting standards in comparing R&D expenses and profitability of IC companies among various countries.

Cash Flow Statement The cash flow statement is an accounting statement that reflects the inflows and outflows of the company’s cash and cash equivalents during a certain accounting period. The purpose of preparing the cash flow statement is to faithfully reflect the cash inflows and outflows of various activities of the company, and to classify three activities of operation, investment, and financing according to their purposes, so as to help users to evaluate the cash flow and capital turnover of the enterprise [1]. For IC manufacturing enterprises and packaging enterprises, the depreciation of fixed assets cannot be recognized as cash outflow, but under accrual basis and matching principle, the acquisition costs of these assets should be reasonably amortized during the beneficial period in which they are used, though with no cash actually paid. Same as EDA tools and purchased IP, for IC design companies, they are generally amortized as intangible assets with no cash outflows. Therefore, although the IC enterprise may have a negative net profit in the income statement due to huge depreciation and amortization expenses, its actual positive cash flow can still ensure the company continues to operate normally.

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In practice, the analysis of financial statements mainly adopts the financial ratio method, comparative method, and factor analysis method. The financial ratio method determines the ratio by comparing the relevant data of several important items on the same financial statement to determine the ratio, which mainly evaluates the company’s profitability, solvency, growth ability, and turnover ability. The comparison method can be made with the company’s history (vertical comparison), with similar companies (horizontal comparison), or by budget ratio (budget difference analysis). The factor analysis rule is based on the mutual driving factors between the indicators to quantitatively analyze the degree of mutual influence between the factors. In addition, special attention should be paid to the notes (or appendixes) section of the financial statements, where key factors and events affecting a specific indicator are often disclosed, as well as many details of a company’s operations, which are indispensable information sources about the company’s financial situation.

Capital Expenditure Capital Expenditure (CAPEX) refers to the expenditure incurred while purchasing or upgrading physical assets such as equipment, factories, and production lines by the enterprise to maintain current performance and develop new businesses. It also reflects the management team’s opinions on the future market and the future direction of development. Since the benefits brought by these expenditures will last for several years, instead of being attributed to a single fiscal year, capital expenditures need to be capitalized and divided into multiple financial statements in the form of depreciation of fixed assets and amortization of intangible assets. The Table 24.1 shows the comparison among capital expenditures, cash from operations, and net income of mainstream integrated circuit enterprises in the most recent fiscal year. Overall, the pattern of capital expenditure is strongly related to the asset portfolio IC enterprises: For IC design enterprises, their fixed assets account for a relatively low proportion, and the capital investment required for daily operation is also small. Their capital expenditures concentrate in design-related fields such as tools and simulation experiments. For example, Nvidia’s operating cash flow in 2021 was US$9.11 billion, and its net profit was US$9.75 billion. Its CAPEX was US$980 million, accounting for 10.76% of total operating cash flow and accounting for 10% of net profit. For IC manufacturing enterprises, factory facilities and production equipment are huge fixed assets. They require a massive amount of initial investment as well as long-term follow up cash inflow for upgrade and expansion from time to time. Also, maintenance, replacement, and relative facilities, as well as the training of workers also consume a substantial amount of funds. Take TSMC as an example. In 2021, operating cash flow was $40.13 billion; capital expenditures reached $30.28 billion, that is, more than its full-year net profit.

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Table 24.1 Comparison of capital expenditure, net profit, and total income of mainstream listed Integrated Circuit Companies in 2021 ($B) Classification IC design

Integrated device manufacturing IC foundry

IC packaging and testing Equipment

Enterprise Qualcomm Broadcom Nvidia MTK AMD Intel TI Micron TSMC SMIC UMC ASE Amkor Changdian Lam ASML AMAT

Cash from operations 10.54 13.76 9.11 1.70 3.52 29.99 8.76 12.47 40.13 3.01 3.26 2.95 1.12 1.17 3.10 12.33 5.44

Net income 9.04 6.74 9.75 4.02 3.16 19.87 7.77 5.86 21.37 1.70 2.01 2.31 0.64 0.47 4.61 6.69 5.89

Capital expenditure 1.89 0.44 0.98 0.61 0.30 20.33 2.46 10.03 30.28 4.12 1.73 2.56 0.78 0.69 0.55 1.02 0.67

Fiscal year end datea 9/26/2021 10/31/2021 1/30/2022 12/31/2021 12/25/2021 12/25/2021 12/31/2021 2/9/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 6/26/2022 12/31/2021 10/31/2021

Note: aThe exchange rate is the exchange rate at the end of the fiscal year Table 24.2 Worldwide semiconductor capital spending and equipment spending forecast, 2016–2020 ($Million) Global semiconductor capital spending Wafer-level manufacturing equipment Wafer fab equipment Wafer-level packaging and assembly equipment

2016 679.9 358.6 340.3 18.3

2017 699.4 380.1 359.8 20.3

2018 736.1 384.9 362.4 22.5

2019 783.6 417.8 392.7 25.1

2020 758.0 398.3 372.5 25.7

Source: Gartner

In the short term, capital expenditures reflect the company’s plans for its business development. Except for the equipment replacement and production line iteration for maintaining the existing business, the company’s investment in developing new products shows its vision and deployment for the future business. Generally, emerging enterprises will regard the CAPEX more significant than their net profit. Large, established enterprises might also want to push up spending amount as they enter a new business area, such as TSMC and SMIC in the above table. Moreover, changes in capital expenditures can reflect future recessions or recoveries of the entire industry. For example, Table 24.2 showed Gartner’s January 2017 forecast for the global semiconductor industry’s overall capital expenditure by 2020. Gartner believed that from the perspective of capital expenditure, the semiconductor industry would remain its growth till 2019 and would decline in 2020. Basically,

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Gartner’s previous report has shown a right trend of the global semiconductor industry’s capital expenditures. China’s IC industry is in a period of rapid development. This can be seen in the growth of the Capital Expenditure of packaging and assembly enterprises over the past 5 years, as shown in Table 24.3.

Shipment Shipment (or sales volume) refers to the quantity of products that an enterprise sells to its direct customers and agents (or intermediaries). Considering the factors of inventory, the quantity of shipment may be larger or smaller than product’s output. From a macro point of view, the global semiconductor product shipments reflect the development trend of the whole industry in terms of the quantities of products. According to IC Insights forecast in April 2021, global semiconductor unit shipments will grow 13% in 2021 to 1135.3 billion (1.1353 trillion) units in 2021to set a new all-time annual record. It would mark the third time that semiconductor units have surpassed one trillion units in a calendar year – the first time being in 2018. Global semiconductor unit shipments include ICs and optoelectronics, sensors, and discrete (O-S-D) devices. Starting with 32.6 billion units in 1978, the compound annual growth rate for semiconductor units is forecast to be 8.2% through 2021. Given the cyclical and often volatile nature of the semiconductor industry, this is a very impressive growth figure over 43 years for such a long period of rapid growth coming from a virtuous circle formed by the interaction between the semiconductor industry’s technological development and global economic demand [3]. The strong CAGR also demonstrates that new market drivers continue to emerge, driving the demand for more semiconductors (Fig. 24.1). For IC design companies, IDMs, and packaging and testing companies, the product form is the chip that has been cut and packaged, so the shipment is counted by “units” (or “pieces”) of the chips. Generally, IC design companies ship on the order of one million pieces, so the industry often uses KK (million) as the unit of chip shipments. The analysis of the production unit and sales unit of GigaDevice in 2021 is shown in Table 24.4. For IC foundry companies and package and testing companies that provide wafer level packaging (WLP), their shipments are based on the number of wafers in units of “pieces.” Wafers come in different sizes. The size number represents the diameter of the wafer. Generally, when doing statistics, a wafer of one size can be converted to another wafer size according to the proportion of the actual area of the wafer. Commonly industry tends to convert to 200 mm wafers or 300 mm wafers as the base unit. Take TSMC as an example. The unit of shipments announced in the TSMC annual report started to use 300 mm wafer as the benchmark from 2013, and other wafer sizes will be converted to 300 mm equivalent wafers. Before 2013, the units were based on 200 mm wafers. This change reflects the transition of TSMC’s main production platform from 200 mm to 300 mm.

Company SMIC Hua Hong semiconductor Jiangsu Changdian technology Nantong Fujitsu microelectronics Huatian technology

2014 4050.7 471.7 1190.4 663.7 599.5

2015 7991.0 1181.1 2363.5 1251.1 897.4

2016 19144.4 1171.3 4768.2 1561.5 1484.6

2017 14882.2 898.5 4284.1 1656.5 1800.1

2018 12436.6 1580.7 4311.1 2230.8 1635.9

2019 13017.6 6421.8 2803.6 2108.8 1955.7

2020 34436.3 7098.3 3330.4 3630.0 3044.7

Table 24.3 China’s major integrated circuit manufacturing and packaging and testing enterprise Capital Expenditure (RMB Million) 2021 26174.5 5964.5 4358.2 6405.1 5535.0

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Fig. 24.1 Global semiconductor unit shipment. (Source of data: IC Insights, April 7, 2021) Table 24.4 Analysis of the production and sales of GigaDevice in 2021 (Unit: million/KK)

Main products Memory chip Micro controller Sensor

Production 3520.9 474.0 193.8

Shipment 3288.3 394.5 164.5

Inventory 337.3 89.5 53.1

Data source: Annual report of GigaDevice in 2021

The average selling price (ASP) of a product can be calculated by dividing the revenue of the product by the volume of shipments of the product, meanwhile a company’s ASP can be calculated in this way too. Table 24.5 lists TSMC’s ASPs from 2013 to 2021. TSMC maintained continuous growth of wafer ASP together with the continuous growth of total shipment volume and wafer revenue. This reflects the improvement of ASP brought by the higher proportion of wafers in the advanced process of TSMC. The vertical and horizontal comparison of ASP is an important reference to analyze the overall IC market trend and the market position of a certain product or a certain company.

Market Share Market share is the percentage of total sales (or sales) that a particular entity accounts for in a market. This index is used to describe the entity’s influence over the market during a certain period of time. From a global macro perspective, the market of integrated circuits can be divided by regions to observe the industrial strength of different areas. Take the IC design as an example. In 2021, the global IC design industry sales volume was 177.7 billion US dollars, of which the US-based design companies had a market share of 68%; the Taiwanese design companies had a market share of 21%. The fastest-growing market share was in China, where it almost doubled compared to 2010. Table 24.6 shows the market share of IC design in different countries/regions. Compared with 2010,

Year Total shipment Unit: convert to 300 mm equivalents in thousand Wafer revenue Unit: Billion NTD Wafer ASP Unit: NTD

Table 24.5 TSMC 2013–2021 shipment and ASP 2014 8263 724 87,583

2013 6963 561 80,526

91,624

803

2015 8763

89,649

861

2016 9606

83,784

875

2017 10,449

84,756

911

2018 10,752

92,105

927

2019 10,068

95,052

1178

2020 12,398

99,111

1405

2021 14,179

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Table 24.6 Market share in different regions of the global IC design industry [4]

Country/Region USA China Taiwan China Mainland Japan Europe Other

2010 69% 17% 5% 1% 4% 4%

2021 68% 21% 9% 1% IC packaging and testing companies. As for the supporting segments, the IC equipment and materials industry have high entry barriers and have been highly concentrated, so they have high gross margin rate. The gross margin rates of major IC companies in the world in FY2021 are shown in Table 24.8. Although the gross margin rate is affected by the industries and segments, there are still large differences in the gross margin rate among companies

Table 24.8 Gross margin rate of the world’s major IC companies in FY2021 Classification Design

Integrated device manufacturing

Foundry

Packaging and testing

Equipment

Enterprise Qualcomm Broadcom Nvidia MTK AMD Intel TI Micron TSMC SMIC UMC ASE Amkor Changdian Lam ASML AMAT

GM% 57.5% 73.9% 64.9% 46.9% 48.2% 55.4% 67.5% 37.8% 51.6% 30.8% 33.8% 19.4% 20.0% 18.1% 45.7% 52.7% 47.4%

Source of data: Public financial report of the companies listed in the table

Fiscal year end date 9/26/2021 10/31/2021 1/30/2022 12/31/2021 12/25/2021 12/25/2021 12/31/2021 9/2/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 6/26/2022 12/31/2021 10/31/2021

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in the same industry segment. Leading companies of an industry usually obtain considerable profits of the industry, resulting to the lower gross margin rate of the rest of the companies. IC design companies with high sales revenues have large market share, and hence have a great voice in product pricing. IC design companies with large sales revenue have strong bargaining power to IC manufacturing, packaging, and testing, and a lesser cost of design tools allocated to each product, so their ability to control production costs is superior to small companies. Therefore, leading companies with large sales revenues have higher gross margin rates. The gross margin analysis of an IC company can be carried out based on business sectors, products, customers, sales areas, etc., depending on the purpose of the analysis and the information available. It also can be compared horizontally with companies in the same industry, or vertically study the historical changes in gross margin rate. In addition, the simple high gross margin rate is not enough to support the sustainable development of an IC company, the company also needs to consider the combination of the company’s shipment volume, sales revenue, product planning, research and development capabilities, and other factors.

Depreciation Depreciation is an accounting method that reallocates the costs of a tangible asset over its lifetime. Since a reasonable amount of fixed asset lasts more than one fiscal year, when calculating the net profit of business activities, enterprises must correctly quantify the costs and expenses generated by the business activities after the depreciation. There are usually two types of depreciation methods: Straight-line method and Accelerated method. The Straight-line method means that the depreciation is charged for the same amount in each accounting period. Accelerated method means that the initial charges are larger and will be reduced gradually. The enterprise will select a different depreciation period for different types of assets based on its own needs, and the final depreciation expense will be the combination. For example, TSMC generally adopts straight-line depreciation method. The depreciation life of ground facilities is more than 20 years; the depreciation life of buildings is 5–20 years; the depreciation life of machines and equipment is 2–5 years; the office equipment is depreciated in 3–15 years, and the leased fixed assets are amortized in 20 years. The integrated circuit wafer manufacturing is a high risk industry with typical scale effect. Historically, one can find out that the leading companies in wafer manufacturing have taken almost all the cake, showing a pattern of “Winner takes all.” Newcomers must reach a particular business scale before they can generate enough income to self-sustain. On the other hand, the integrated circuit wafer manufacturers also need to be continuously updated. The equipment cannot go beyond technology nodes. As a result, manufacturers have to constantly replace old product lines with new ones to stay competitive. For each new fab built, the cost could reach tens of billions of dollars, according to 5–10 years of depreciation. That

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is, the average cost per second is around 25–50 dollars (with or without income). At the end of the depreciation, equipment usually cannot be used anymore because the market demand should have changed. If the new process nodes become the mainstream, it is necessary to consider selling the old equipment in advance. For the newly built integrated circuit wafer manufacturing enterprises, they have to experience high depreciation pressure brought by the large-scale initial investment in the first few years. Currently, the revenues still continued to struggle at low levels. Thus, the company might suffer for net losses for several years. As the production capacity is released over time and new market shares are obtained, a positive production cycle begins to be maintained. As revenue increases, the proportion of depreciation to revenue will decrease, yet it still depends on the enterprise’s subsequent investment of the business. In the case of SMIC as shown in Fig. 24.5, the percentage of depreciation to operating revenue is quite high at the beginning of its establishment, ranging from 46% to 72% between 2003 and 2009. In the past 9 years (2013 to 2021), as SMIC’s operating revenue continued to rise, the major equipment has also passed the depreciation period, and its depreciation accounted for 23–35% of its operating revenue. The enterprise maintained the continuous profitability. Some well-developed integrated circuit wafer manufacturers, after expansion to a certain extent, almost no longer make any production capacity and technology investment. Then, after all depreciation is completed, the depreciation part of the cost becomes zero or a small number. At this time, the profit level of the enterprises will be improved. However, in the long run, no capital expenditures will make the company’s production capacity and technology stand still, and the competitiveness of enterprises will gradually decline, which will eventually lead to the decline in profits and even losses. For intangible assets, their costs need to be systematically amortized to each accounting period in their useful life span. Amortization shall begin on the date on which the intangible assets are available for a period but no more than 20 years. The method of amortization should reflect how the enterprise consumes the economic benefits of intangible assets. If the method cannot be reliably determined, the straight-line method is used. Amortization for each period should be recognized as

Fig. 24.5 Trends in SMIC’s depreciation rate (data from SMIC’s 2004–2021 annual report)

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an expense unless other International Accounting Standards allow or require it to be included in the carrying amount of other assets.

EBITDA Before discussing Earnings Before Interest, Taxes, Depreciation, and Amortization (EBITDA), the relevant indicator Earnings Before Interest and Tax (EBIT) needs to be firstly explained. In general, EBIT is referred to the operating profit reflecting the operating results of the company’s main business. Since the interest expense and tax are excluded, the company’s operating results will not be affected by the amount of liabilities in the capital structure nor the income tax. EBIT could be calculated as the prime operating revenue minus operating costs and operating expenses. Depreciation and amortization directly related to product manufacturing are included in the operating costs. EBITDA is based on EBIT and then added to back depreciation and amortization. The calculation formulas for EBIT and EBITDA are as follows: EBIT ¼ ðRevenue  Operating CostÞ  Operating Expenses ¼ Net Profit þ Income Tax þ Interest Expense EBITDA ¼ EBIT + depreciation expense + amortization expense ¼ Net Profit þ Income Tax þ Interest Expense þ Depreciation Expense þ Amortization Expense Compared to net profit, EBIT excludes the income tax, interest, and other operating revenue, which is convenient to analyze and compare the profitability of the main business of same type enterprises with different income tax rates and different capital structures. EBIT is also more comparable than net profit, while the profitability of companies’ main businesses is analyzed vertically. Since depreciation and amortization are included in the cost of acquiring equipment or intangible assets in the previous accounting period, rather than the cash outflows in the current period, EBITDA avoids the impact of various depreciation policies and deprecation abnormalities on the operating performance of different enterprises while EBITDA further eliminates depreciation and amortization on the basis of EBIT. It should be noted that EBITDA cannot simply be equated with operating cash flow. Since EBITDA does not consider the impact of factors such as changes in inventory and current accounts on cash flow, and the calculation of EBITDA does not exclude items such as asset impairment losses and investment income, there is a certain difference between EBITDA and the net cash flow generated by operating activities. However, EBITDA could be considered as an inaccurate surrogate indicator of the company’s net cash flow from operating activities.

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EBIT is an indicator to present the profitability of a company’s main business, while EBITDA is an indicator of a company’s ability to generate cash flow from the main business. EBIT and EBITDA are highly valued indicators in enterprise management, mergers and acquisitions, as well as in the secondary market. The calculation of profits can be consistent by eliminating some factors in calculating profits, which is convenient for analysis and comparison. Since the IC industry is a capital-intensive high-tech industry, the depreciation brought by the construction of capital investment in manufacturing capacity, or the amortization of intangible assets brought by using IP and EDA tools, will affect the profit statements of IC companies at different stages. EBITDA can be used to measure management performance more objectively over a period of time. For example, comparing early-stage companies and mature companies with stable depreciation and amortization, their EBIT or net profit levels may vary greatly. It is impossible to determine whether the difference comes from operation management or depreciation and amortization. At this time, the differences and real operational performance of two companies could be reflected by comparing EBITDA. EBITDA is an important parameter for the acquirer to acquire and evaluate the acquisition target. The acquirer will choose applicable tax rate calculation method and new capital structure to calculate the acquiree’s financial status. It means the depreciation and amortization will be excluded, and the merger will be replaced by an estimate of the acquiring company’s future capital expenditure. With the increase of investment and mergers and acquisitions in IC industry, investors need to understand the characteristics of the industry chain in which the investment target is located. The establishment of a financial model and the reasonable estimation of profitability are the key basis for making investment decisions. Taking the industry of IC manufacturing, which requires long-term and highintensity capital investment as an example, depreciation and amortization caused by large-scale initial investment at the beginning of the establishment of the enterprise is very likely to cause negative EBIT and net profit. At this point, the cash flow of business activities must be positive, and EBITDA is a visual indicator in this respect. However, as a return for the long-term investment of the company’s shareholders, the net profit of IC manufacturing companies is still a key indicator of business operations after the intensive investment period. EBIT and EBITDA of world’s major IC companies’ annual financial reports for FY2021 are shown in Table 24.9.

Other Financial Indexes Other financial indexes include several categories: (1) CAPEX and OPEX; (2) Net Asset; (3) ROE; (4) Net Income; (5) GAAP and Non-GAAP, as discussed below. 1. Operating Expenses: the cost incurred by the company for normal business operations, usually referred to as OPEX. In contrast to capital expenditure (CAPEX), OPEX is the continuous or consumable expenditure of the running

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Table 24.9 EBIT and EBITDA of world’s major IC companies from annual financial reports of FY2021 EBIT Classification Company Billion $ Design Qualcomm 9.79 Broadcom 8.68 Nvidia 10.04 MTK 3.90 AMD 3.65 Integrated device Intel 22.08 manufacturing TI 9.02 Micron 6.80 Foundry TSMC 23.47 SMIC 0.73 UMC 1.86 Packaging and ASE 2.24 testing Amkor 0.77 Packaging and Changdian 0.48 testing Equipment Lam 5.38 ASML 7.43 AMT 7.26

EBIT/ Operating income 29% 32% 37% 22% 22% 28% 49% 25% 41% 13% 24% 11% 12% 10% 31% 35% 31%

EBITDA Billion $ 11.37 14.72 11.22 4.25 4.06 33.87 9.92 13.01 38.47 2.50 3.48 4.12 1.33 1.03 5.72 7.95 7.65

EBITDA/ Operating income 34% 54% 42% 24% 25% 43% 54% 47% 67% 46% 45% 20% 22% 21%

Fiscal year end date 2021/9/26 2021/10/31 2022/1/30 2021/12/31 2021/12/25 2021/12/25 2021/12/31 2021/9/2 2021/12/31 2021/12/31 2021/12/31 2021/12/31 2021/12/31 2021/12/31

33% 38% 33%

2022/6/26 2021/12/31 2021/10/31

Note: Exchange rate using the rate at the end of the fiscal year Source of data: Public financial report of the companies listed in the table

enterprise. For example, the expense of purchasing a photocopier is capital expenditure (CAPEX), while the cost of paper, ink, electricity, and maintenance is an operating expense (OPEX). Operating expenses usually consist of two parts. The first part is Research and Development Expenses (R&D). The second part is Selling, General, and Administrative expenses (SG&A). To take part in the fierce competition of the integrated circuit industry, an enterprise could try hard with low product price to get more market share. Another way is to get ahead in technology. The enterprise’s Research & Development expense is an indicator that directly reflects its investment in technology. Table 24.10 showed the top enterprise’s R&D expenses in 2017. Compared with other industries, the R&D expenses of integrated circuit companies are considerable both in absolute numbers and as a percentage of revenue. SG&A (Selling, General, and Administration) represents the sum of the company’s major non-production expenses. Selling expenses include all direct and indirect sales expenses, such as employee salary, advertising expenses, and rental expenses. General expenses are the enterprise’s comprehensive operation process. Administration expenses include salaries of administrative personnel and related taxes and fees.

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Table 24.10 2017 Global semiconductor enterprise R&D expenses ranking 2017 Rank 1 2 3 4 5 6 7 8 9 10

Company Intel Qualcomm Broadcom Samsung Toshiba TSMC MTK Micron Nvidia SK Hynix Top 10 Total

R&D expense($M) 13,098 3450 3423 3415 2670 2656 1881 1802 1797 1729 35,921

R&D/Sales(%) 21.2% 20.2% 19.2% 5.2% 20.0% 8.3% 24.0% 7.5% 19.1% 6.5% 13.0%

17/16% Change in R&D 3% 4% 4% 19% 7% 20% 9% 8% 23% 14% 6%

Source: IC Insights

2. Net Assets: The net value of the enterprise after deducting liabilities from the total assets. It consists of two parts. One is the capital invested at the beginning of the establishment of the enterprise. The other is the assets created during the operation. Net Asset is also called the owner’s equity. It represents the value of owner’s property in the enterprise, including paid-in capital, provident fund (surplus accumulation fund, capital reserve), undistributed profit, and so on. 3. ROE: The rate of Return on Common Stockholders’ Equity. ROE is the ratio of net profit (after tax) to net assets, representing the return of the equity, which is used to measure the profitability of the company’s capital and fund efficiency of a company’s capital. It is commonly used as an indicator for enterprise valuations in mergers and acquisitions. 4. Net Income Exclude Unusual Items: It refers to the profit value after deducting non-recurring gains and losses from the net profit. Since non-recurring gains and losses do not reflect the profitability of IC enterprise, it is a common practice to exclude them. Ordinary non-recurring gains and losses include the sale of assets, gains, and litigation losses. Net Income Exclude Unusual Items ¼ Net Income  NR Where NR stands for non-recurring gains and losses. Non-recurring gains and losses are non-cyclical and difficult to predict. If the amount is large, it will interfere with the analysis of the enterprise’s operations. For example, some start-up IC design companies will occasionally sell the patent or intellectual property for a substantial amount of revenue compared with their primary business. Therefore, it is necessary to omit this income and then evaluate it. 5. GAAP items and Non-GAAP items: General Accepted Accounting Practice (GAAP) is a set of fair standards recognized by the US Securities and Exchange Commission for the accounting of the enterprise. Chinese IC companies adopt

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these standards to meet the requirement for frequent international comparisons. The GAAP indexes refer to the indexes in line with GAAP, which is the common item in the official financial statements, including revenue, net profit, etc. However, in the actual operation, there are one-time and unconventional expenditures, changes in tax rates and other factors that cause the standard financial indicators to not reflect the overall profitability of the enterprise. Therefore, many enterprises and financial institutions use the so-called “Non-GAAP items” to adjust and more accurately reflect the real state of the company’s operations. Daily Non-GAAP items include EBITDA, Free Cash Flow (FCF), etc. The significance of individual items is not apparent, but the combination of multiple indicators will place IC enterprises in the entire industry for horizontal international comparison, which will lead to more accurate judgments.

Price-to-Earnings Ratio The Price/Earnings (P/E) ratio (unit: multiple) is the ratio of a stock’s price to its earnings per share: Price=Earnings Ratio ¼ Stock Price  Earnings Per Share P/E ratio is one of the most fundamental indicators used to evaluate stocks and enterprises. It reflects the market’s comprehensive estimation of the enterprise’s risk and growth potential. If an investor captures the enterprise’s growth expectation better than the market does, he/she can decide to buy or sell short of the enterprise’s stock accordingly. The idea is, the lower the Price/Earnings ratio, the better the value for investment is. However, the so-called “high” and “low” are relative concepts. There is hardly a universal rule or reference book that tells the answer. In reality, investment decisions are made based on the accumulation of long-term observation and comparison with other entities in the market, and the risk of loss is also limited in a reasonable range. The real-time P/E ratios are fluctuated greatly, reflecting a lot of market’s sentiment at real-time. However, the average value over a specific period will show the enterprise’s value and market expectations more comprehensively. For example, Qualcomm’s average annual P/E Ratio on the US stock market has risen from 15 times to more than 20 times since 2015, in line with the steady growth of its business. The P/E Ratio of Some Large Listed Integrated Circuit Enterprises is shown in Table 24.11. Compared to Europe and North America, the integrated circuits sector has higher average P/E ratio in China’s stock market. China’s IC industrialization has just emerged. The expansion space is ample, and the upward trend is evident. In this case, the Chinese market is very optimistic about the industry’s future. A group of leading enterprises with pioneering spirit came to the front stage, leading the progress of the whole industry and forming up an industry chain with considerable scale. However, the profit cycle of integrated circuit enterprise is generally longer. In addition, there are certain restrictions on the listing approval and board transfer of the

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Table 24.11 P/E ratio of some large listed integrated circuit enterprises Company ASML Applied Materials AMD Broadcom Intel Lam Research Micron Nvidia Qualcomm Texas Instruments Hangzhou Silan Microelectronics Jiangsu Changdian Technology Shenzhen Goodix Nations Technologies Ingenic Semiconductor United Microelectronics TSMC MediaTek ASE Technology Holding

Stock exchange market Amsterdam Euronext NASDAQ

Shanghai Stock Exchange

Shenzhen Stock Exchange Taiwan Stock Exchange

P/E (times) 53.5 24.6 44.4 44.4 10.0 24.3 14.4 90.7 23.2 24.2 96.0 19.9 42.4 115.8 91.9 17.7 28.2 19.6 10.9

Source: S&P capital IQ platform data as of December 31, 2021

domestic A-share market, which pushes up the P/E ratio of already listed enterprises. As the industry matures and the listing process accelerates, it is foreseeable that the overall P/E ratio will gradually decline, and investors will return to rationality, and the industry will enter a period of stable growth.

Goodwill Goodwill is the capitalized value of a company’s intangible predictable future excess profitability. In company value assessment, it is possible that the fair market value of the company is higher than the sum of the tangible net assets of the company and the evaluation value of the intangible assets. This part of the value is considered to be derived from the objective goodwill of the company. There are many sources of goodwill. Anything that can generate excess profits can be included in the scope, such as the reputation of the company, the prestige of the company’s top management, the superior geographical position, good customer relationship, good labor relations, and broad market prospect of products, etc. Goodwill cannot exist independently of the company, and its value can only be reflected when the company is sold as a whole or integrated. In corporate mergers and acquisitions, the excess earning value brought by goodwill is the value paid by the acquiring company for the target company

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exceeding the target’s book value. In fact, this “purchase premium” is usually formed by various factors, such as the negotiating power of both parties, the fair value of the expected synergy of the acquiring company, and the target company. The value of goodwill disclosed in the balance sheets of major global IC companies in 2021 is shown in Table 24.12. It can be found that companies with high goodwill values are frequently involved in mergers and acquisitions, such as Broadcom. In February 2016, Avago completed the acquisition of Broadcom with US$28.758 billion and renamed the entire company to Broadcom. Its goodwill value on the financial statement balance sheet published on April 30, 2017, was US$24.7 billion, of which US$23 billion came from the acquisition of Broadcom’s premium and US$83 million from the 2015 acquisition of Emulex. On November 4, 2019, Broadcom completed its acquisition of the Symantec Business, US$6.6 billion of the total US$10.7 billion purchase price was allocated to goodwill. There are several methods for dealing with goodwill in corporate mergers and acquisitions: 1. It is recognized as an asset separately and amortized within its expected useful life, either as a cost or as a write-off of retained earnings. 2. It shall be written off immediately at the time of the merger and deducted from the retained earnings directly. 3. Goodwill is treated as a permanent asset and is not amortized unless there is evidence that its value has continuously declined. Table 24.12 Goodwill value of major global IC companies in 2021 financial reports Industry segment IC design

IDM

IC Foundry

IC package and testing

IC Manufacture Equipment

Company Qualcomm Broadcom Nvidia MTK AMD Intel TI Micron TSMC SMIC UMC ASE Amkor Changdian Lam ASML AMAT

Goodwill Billion USD 7.2 43.5 4.3 2.4 0.3 27.0 4.4 1.2 0.2 0.0 0.0 1.9 0.0 0.3 1.5 5.2 3.5

Note: Exchange rate using the rate at the end of the fiscal year Source of data: Public financial report of the companies listed in the table

Report date 9/26/2021 10/31/2021 1/30/2022 12/31/2021 12/25/2021 12/25/2021 12/31/2021 9/2/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 12/31/2021 6/26/2022 12/31/2021 10/31/2021

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Take the deal by Zhejiang Wansheng Co., Ltd., a company listed on the Shanghai Stock Exchange, to issue new shares to purchase assets as an example. Based on the adjustment of national industrial structure, the company has identified the IC industry as the key direction of its strategic transformation. In May 2017, the company announced the “Issuance of Shares to Purchase Assets and the Raising of Matching Funds and Related Transaction Plan.” The company intended to issue new shares to acquire 100% the shareholder’s shares of Jiang Xin Zhi Ben (Shanghai) Technology Co., Ltd. from 7 shareholders including Jiaxing Haida and State Grand Fund. Jiang Xin Zhi Ben has completed the acquisition of all shares of Analogix, a US company in Silicon Valley. Therefore, Zhejiang Wansheng Co., Ltd. will indirectly hold 100% of Analogix after the acquisition deal closes. The transaction price of Wansheng to acquire Jiang Xin Zhi Ben is 3.75 billion RMB, which is more than the net asset value of the underlying assets. According to the “Accounting Standards for Enterprises,” the difference between the merger cost and the fair value of the identifiable net assets of the underlying assets acquired in the merger shall be recognized as goodwill. The goodwill is not amortized but is subject to an impairment test at the end of future fiscal years. Once the impairment of goodwill is calculated, it cannot be rolled back in future fiscal years. Therefore, Wansheng has made the following risk warnings in the “Transaction Plan”: “If the underlying assets do not perform as expected in the future, the goodwill formed by this transaction will have a high risk of impairment. Investors should pay attention to the risk of impairment of goodwill.”

Equity Incentive Equity Incentive is a long-term incentive mechanism that gives target employees part of the company’s equity under certain conditions to encourage and retain core talents. In the long run, it serves as an incentive method that enables motivated employees to further participate in company business decision, profit sharing, and risk taking as shareholders. More than 80% of the top 500 companies in the world have implemented the equity incentive system in their corporate management. There are many forms of equity incentives, such as performance stocks, stock options, virtual stocks, restricted stocks, and stock appreciation options. The common forms of equity incentives for Chinese listed companies are restricted stocks and stock options. For high-tech enterprises, equity incentive is an effective complement to the company’s salary system. Under the condition of achieving performance appraisal, giving the management team and core employees corresponding incentives is an important measure to ensure the stability of the company team and to attract talents. The target of equity incentive is the core talents with strategic value to the company. It can be those who master core technologies or control key business and resources. The importance of talents is ranked the first in the production factors of the IC industry. The capital can only be brought into play under the condition that an

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Table 24.13 Qualcomm’s annual SBC expense unit: Million US dollar

SBC expense In: Cost of revenue In: R&D expense In: SG&A (selling, general, and administrative) expense Total SBC expense

2018 financial year 38.0 594.0 251.0

2019 financial year 35.0 725.0 277.0

2020 financial year 34.0 872.0 306.0

2021 financial year 47.0 1234.0 389.0

883.0

1037.0

1212.0

1670.0

Source of data: Public financial report of Qualcomm in 2018-2021

effective team is formed with all types of talents. Compared with the traditional industries, IC industry has a wider incentive range which includes at least senior management, key technical employees, and sales employees. For many start-up IC design companies in China, talent is the key to survival and development. Attracting and retaining talent largely depends on equity incentives. However, Chinese company will face the issue that the number of incentive employees is limited, and the equity incentive cost will affect company’s profitability if the company plans to go public in China. Since the essence of equity incentive is the remuneration paid by the company for its employees’ services, the company should amortize the expenses incurred by equity incentive to the years in which the employees provide services. The equity incentive cost is included in the corresponding accounting subjects according to the department of the employee and the type of service provided. If the employees granted incentive equity are the executives of a listed company, the cost of equity incentive is usually included in the management fee. If employees granted incentive equity are in the production department, the cost of equity incentive should be recorded in the corresponding production costs. In the notes to the annual report of listed companies, the current period expenses, accumulated liabilities, and the fair value of the equity instruments about the equity incentives will be disclosed. For employees, equity incentives are salary remuneration and are subject to individual income tax. For the company, it is the employment cost and can be deducted as a pre-tax operating cost. For example, as a high-tech research and development company, Qualcomm’s annual stock-based compensation (SBC) expenses account for a large proportion of its research and development expenses, as shown in Table 24.13.

References 1. The Chinese Institute of Certified Public Accountants, Accounting, (China Financial & Economic Publishing House, Beijing, 2012) 2. Ministry of Finance of the People’s Republic of China, Accounting standards, (Economic Science Press, Beijing, 2017)

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3. IC Insights, Semiconductor units forecast to exceed 1 trillion devices again in 2021. icinsights.com. https://www.icinsights.com/news/bulletins/Semiconductor-Units-Forecast-ToExceed-1-Trillion-Devices-Again-In-2021. Accessed 26 Nov 2022 4. IC Insights, Chinese companies hold only 4% of global IC market share. https://www.icinsights. com/news/bulletins/Chinese-Companies-Hold-Only-4-Of-Global-IC-Marketshare/. Accessed 26 Nov 2022 5. J. Lin, IC Insights: Top 10 Analog IC suppliers for 2021, en.ctimes.com.tw, IC Insights: Top 10 Analog IC suppliers for 2021 – CTIMES news. Accessed 26 Nov 2022

Investment and Financing of IC Industry

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Yingping Hu, Yang Liu, Ming Yin, and Cheng Zhang

Contents Venture Capital and Private Equity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Major Financing Sources for IC Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Financing Sources for IC Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Investment Methods of Industry Funds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . China Integrated Circuit Investment Fund and Sino IC Capital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Government Investment Funds on IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . International IC R&D Investment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mergers and Acquisitions in IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPO and Going Private . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Procedure of Venture Investment for IC Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Due Diligence in IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asset Evaluation of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

This chapter introduces the information about investment in the Chinese IC industry, including main funding sources and investors, listed IC corporations, and activities among Chinese IC firms in recent times. The main investors in Chinese IC industry include domestic and foreign VC/PE, industry funds, and national or local government investing programs. The chapter also provides a brief description of the due diligence investigation and decision-making procedures when an investment in the IC industry is made. Y. Hu · Y. Liu (*) Hua Capital Management Co., Ltd., Beijing, China e-mail: [email protected] M. Yin Publishing House of Electronics Industry Co., Ltd., Beijing, China C. Zhang Zhihu Inc., Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_25

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Keywords

Fund · Venture Capital · IPO · M&A · Due Diligence Investigation · Asset Evaluation

Venture Capital and Private Equity Venture capital (VC) is also known as venture capital funds, commonly referred to as VC. It refers to a form of capital investing action that one invests funds raised through the issuance of fund beneficiary bonds and commissioned by the special investment management agency – fund management companies to the emerging companies with potential compatibility (typically high-tech companies). Through this capital management service, one can directly participate in the entrepreneurial business startup process. The beneficiary of venture capital fund and the fund management company share investment profit according to the agreement [1]. The concept of Private Equity (PE) derives from the private fund. According to the direction of investment, private fund can be divided into private equity securities investment funds and private equity funds. Private equity investment funds mainly invest in stocks, bonds, warrants, etc. PE funds, on the other hand, invest mainly in the equity or corporate bonds of unlisted companies. In the broad sense, PE refers to the equity investment before the Initial Public Offering (IPO), that is, the investment made by enterprises in the seed stage, the IPO stage, the development stage, the expansion stage, the maturity stage, and the pre-IPO stage. In the narrow sense, PE mainly refers to the private equity investment of mature enterprises that have formed a certain scale and are generating stable cash flow, that is, it mainly refers to the private equity investment in the later stage of VC [1]. In China, industrial investment fund, equity investment fund, venture capital fund, merger and acquisition (M&A) fund, and other non-securities investment funds are included in the private equity investment fund. Due to the high risk and high return nature of high-tech industry, VC/PE equity investment has become its main financing method. The main purpose of VC/PE investment in high-tech industry is to obtain excessive returns. It also promotes the development of high-tech industry to a large extent. With the establishment and promotion of China’s new third board and growth enterprise board, as well as the improvement of the primary market, VC/PE exit methods are more abundant, and the investment intention is also enhanced. In recent years, VC/PE has developed rapidly in China. As of the end of 2020, the number of private equity fund management institutions registered with the Asset Management Association of China reached 14,986, the size of funds under management was about 11.64 trillion yuan (RMB), the cumulative number of exit cases was 26,708, and the cumulative withdrawal principal was 1475.767 billion yuan. With the establishment and promotion of China’s New Third Board and ChiNext, and the improvement of the primary market, VC/PE has more exit methods. Although the exit method is still mainly based on agreement transfer, going public is the fastest-growing exit method. The ratio of the withdrawal amount and the number of withdrawals in the open

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market were 27.95% and 17.00%, respectively, which was a significant increase from 16.94% and 12.98% in 2019. In 2020, according to the statistics of the actual number of projects withdrawn in the year, the exit methods of Chinese private equity fund projects are mainly agreement transfer (37.43%), corporate repurchase (20.57%), open market (17.00%), others including liquidation, dividends of invested companies, debt transfer, etc. (16.85%), financier repayment (6.93%), and overall acquisition (1.22%) [2] (Fig. 25.1). The venture capital fund in the modern sense originated from the United States and played a significant role in promoting the emerging industries in the United States after the World War II. Both Xerox and IBM have received strong support from VC in their development process. In the 1980s, VC in United States began to develop rapidly. The amount of VC investment increased from 2.5 billion US dollars in 1979 to 600 billion US dollars in 1997. IC companies such as Intel and Apple have received strong support from VC too [3]. However, with the maturity of the industry, US VC now basically no longer invests in domestic IC companies, but transfers to China instead. VC funds and private equity funds in the field of IC in China began to be active, which greatly promoted the industry. The development of the IC industry has its own characteristics, such as high cost, long payback period, and high risk. If you prepare to invest to the IC industry, you must master its industry characteristics. Insufficient capital has always been one of the core issues that restrain the IC industry. To catch up with the globalization trend and the characteristics of that the winner takes it all of the IC industry, there must be a trend of industrial integration and mergers and acquisitions in the future. The main body of IC enterprises must be small but strong. Traditional financial support methods not only have certain problems, but also cannot support the IC industry

Fig. 25.1 2006–2021 China VC/PE fundraising situation. (Source: Zero2IPO Group)

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that is costly and requires patience of investors. Hence, to support the whole industry, one must take advantage of the effective market mechanism to foster and introduce long-term institutional investors represented by VC/PE.

Major Financing Sources for IC Companies The financing channels that IC enterprises can use include government investment, bank loan, capital market, etc. These financing channels have the characteristics of dynamic change, which is closely related to the maturity of the industry. Generally speaking, the more mature the industry is, the lower the return provided for investors while the lower the risk. Thus, the financing of the mature industry depends more on bank loans and investment in the secondary capital market. The less mature the industry is, the higher the risk and lower return will be. Therefore, the investment in the primary capital market and the self-raised capital of enterprises will become the main sources of financing. Throughout the history, the financing channels of IC enterprises in most countries have experienced the change from government investment to VC/PE intervention and then to the secondary market while the industry developed. It is also notable that since the IC industry in different countries is usually at different stages, the main financing channel of IC enterprises in different countries might be completely different. Besides, due to the different characteristics of different industrial steps, the financing channels of each step also reveal different characteristics. Government investment includes not only direct channels like industrial investment fund to invest equity in enterprises but also indirect channels such as government procurement, government policy loans, and government-backed syndicated loans. The United States is the first country in the world developing the IC industry, which started with the support of government procurement from NASA and the Air Force. During the gulf war in the 1990s, precision-guided weapons backed by IC technology were first used on a large scale by the US military. Government procurement played an important role in the maturation of the US IC industry. On the contrary, the Korean IC industry obviously relies on indirect financing channels of government, because the capital ownership of Korean high-tech enterprises is always the lowest among that of enterprise in developed countries [4]. Indirect government financing is also often used to protect Korean IC companies from cyclical downturns. For example, the asset-liability ratio of Samsung reached 223% in 1997. During the industrial recession in 2001, 2006, and 2007, the assetliability ratio of Samsung also increased significantly, as shown in Fig. 25.2. There are many ways for IC enterprises to obtain equity financing. No matter how the enterprise chooses listing, VC, or industrial investment funds, they can share risks and solve the quantitative capital demand in the development of enterprises. Thus, they can all be regarded as effective financing channels [5]. For example, in China, a capital market is consisting of the Main Board, small and medium Enterprise Board, Growth Enterprise Market, and new over-the-counter (OTC) Market. IC enterprises can freely choose suitable listing channels based on their own conditions.

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Fig. 25.2 1997–2021 changes in the asset-liability ratio of Samsung. (Source: annual report of Samsung from 1997 to 2021)

Corporate bonds, bank credit, and financial leasing are the main ways of debt financing. Compared with equity financing, corporate bonds are superior to bank credit in financing scale and duration, and superior to stock market financing in financing cost. Companies that issue bonds for financing have more autonomy while keeping the control of existing shareholders. Operating on debt is conducive to the financial leverage. Due to the diversification of financing channels, the combination of the proper use of debt financing and rational allocation of enterprise capital structure can achieve the lowest financing cost and the best capital structure. Financial leasing has low requirements on the credit status of enterprises, which is suitable for the financing of strategic emerging enterprises in the initial stage. As an innovative way of off-balance sheet financing, financial leasing will not lead to a transfer of ownership or affect the credit status. It is in line with the requirements of multi-channel financing for IC enterprises. The IC industry requires a large amount of investment in the early stage, which can be appropriately reduced by the financial leasing mode.

Financing Sources for IC Manufacturing IC manufacture industry is heavy asset industry, which means that it has a great demand for capital. No matter where the capital comes from, it means the same to enterprises. But different investors have different demands. The basic pursuit of the national IC industry investment fund (the national fund) is to improve China’s IC industry as soon as possible through investment on the premise of reasonable returns, which means “the unification of national strategy and market economy.” This is the principle (mission) of the national fund. The behavior that the fund holder, broker, or retail and trader on capital market buy the stock of IC companies is also a

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kind of investment. No matter how long they hold the share, the goal is to gain the biggest interest. The independence and international nature of IC industry determines its capital sources mainly in six categories. 1. Publicly raised public capital (listing): An IC company sells its shares to the public to raise capital. 2. Private equity investment fund (PE): PE includes national equity investment funds, such as national or other relevant national equity investment and government guiding funds, and IC equity investment funds and related equity investment funds and guidance funds set up in various places. These funds are allocated to support enterprises. 3. Self-accumulation of the enterprise. Enterprises can raise capital through surplus reserves (after-tax profits). To raise capital through this way, IC enterprises are required to have certain profitability and fast depreciation ability, which enables them to accumulate capital by themselves after achieving high profit. 4. Employee Stock Ownership. Employee stock ownership is a long-term performance reward plan that encourages employees to hold stocks and options of the company. 5. Debt financing. Enterprises can borrow money through bank credit, debt financing, private credit, bond financing, commercial credit, leasing, etc. Debt financing can improve the return rate of enterprise ownership funds. Since the IC manufacture industry needs large investment while it has a long return period, the manufacturing enterprises choosing this mode should correctly evaluate their own scale and repayment ability, and hence choose the right mode of debt financing to minimize the financial risk. 6. Mergers and Acquisitions (Ms&As). In order to fulfill their strategic intention and increase their market share, IC enterprises can carry out capital integration through merger and acquisition. Mergers and acquisitions generally refer to combining an enterprise with the purchaser’s enterprise by purchasing it. A merger is a combination of two or more independent businesses to form a business: usually, one dominant company absorbs other companies. Acquisition refers to that one enterprise uses cash or issue of securities to buy the share or assets of another enterprise, and hence acquire the ownership of all the assets of the newly bought enterprise, or a certain asset, or the control of the latter. Manufacture in IC industry possesses typical feature of economies of scale. In the process of becoming bigger and stronger, shareholders from various aspects will be affected by different demands of various capital owners and even cause intense conflicts, which will seriously affect the development of enterprises. It is notable that there are two types of forbidden investment for IC manufacturing enterprises: First, industrial capital with upstream and downstream connections – it will affect the independence of enterprises; second, the capital that solely controls other IC manufacture enterprises – it will cause the separation of capital, talent, and market [6].

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Investment Methods of Industry Funds In order to promote the industry, cultivate advantageous enterprises, and obtain returns, industrial funds need to adopt different investment methods. There are five investing methods of industrial funds, as discussed below. 1. Direct capital increase The industrial fund increases its investment and buys shares in an IC enterprise for the enterprise’s mergers and acquisitions or independent R&D. When the industry fund satisfies the withdrawal period requirement, it can transfer the equity it holds in the company to other companies or sell the equity on the secondary market. 2. Adopt “listed enterprises + PE” type industrial merger fund “Listed enterprises + PE” mode can take two aspects for listed enterprises into account. It has also been applied in various enterprises. This mode can greatly enhance the merger and acquisition ability and reduce the capital pressure of listed companies. A typical case for this mode is the acquisition of STATS ChipPAC. In this case, the industrial fund joined forces with two listed companies, Jiangsu Changjiang Electronics Technology Co., Ltd. and SMIC, to help the former acquire large international companies. In the total $780 million investment, $260 million comes from Long Telegram Technology, $100 million comes from SMIC Subsidiary Core Electric Semiconductor, $300 million comes from industrial funds ($140 million comes from the shareholder loan with convertible share and the other $160 million comes from equity investment), the remaining $120 million comes from the Bank of China Wuxi branch loan [7]. The industry and capital are well combined: Industrial funds can use listed enterprises’ understanding of the industrial chain to reduce the information asymmetry in the process of Ms&As and hence find investment targets. Also, when necessary, they can directly transfer their equity to listed enterprises, which is a good method to exit. 3. Merger and acquisition with enterprise consortium The industrial fund and the IC enterprise shall reach a consensus on the relationship, and jointly implement the external M&A project: the enterprise controls the project, and the industrial fund participates. Under appropriate conditions, the holding company shall acquire the equity held by the industrial fund by cash or stock exchange. 4. With the joint stock enterprises set up a special investment fund The industrial fund and holding company jointly set up special investing sub-funds for equity investment in the field of IC as limited partner and general partner. By doing this the partners can make full and flexible use of social capital through fund holding; it is also suitable for the requirements of equity investment and can regulate the investment behavior according to the market requirements. In the future, the fund investors can exit with profit by IPO or equity transfer.

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5. Finance leasing companies shall be established to support manufacturing enterprises In order to promote IC industry, the industrial fund can encourage the upstream and downstream enterprises to cooperate on investing and set up new enterprises. The industrial fund can intervene in newly established enterprises by equity investment to promote the cooperation between upstream and downstream enterprises. Besides, the industrial fund can purchase equipment for large-scale production for the joint venture. The industrial fund may also establish or invest in equipment leasing companies to lease equipment for large-scale production to IC enterprises or joint ventures. Both parties shall sign a lease agreement and promise to pay the rent on time.

China Integrated Circuit Investment Fund and Sino IC Capital In June 2014, a government document, the “National Integrated Circuit Industry Development Promotion Outline” was officially released and implemented, clearly setting up a national industrial investment fund, and supporting the establishment of local integrated circuit industry investment funds to encourage various types of venture capital and equity investment funds to enter integrated circuit fields. China Integrated Circuit Industry Investment Fund (CICIF) is a corporate private equity investment fund mainly engaged in the equity investment business of the integrated circuit industry. The fund manager of CICIF is Sino IC Capital (Sino IC). The fund company was incorporated in Beijing on September 26, 2014. Its business is to invest in integrated circuit chip manufacturing, taking into account the chip design, packaging and testing, equipment, materials, and other industrial links. The fund companies aimed to create good returns for shareholders in a period of 10 years and can be extended for a maximum of 5 years, subject to the approval of the shareholders’ meeting of the fund company. At present, the total share capital of the fund company is 138.72 billion Yuan, which is jointly funded by 19 shareholders, as shown in Table 25.1. Shareholders include enterprises in the central financial and integrated circuit industry clusters, entities in the real economy, some financial institutions, integrated circuit industry chain related enterprises, and some private capital. Shareholders have clear financial returns to the fund and set a threshold for the fund. The fund company is a joint stock limited company established in accordance with the “Company Law of the People’s Republic of China.” The shareholders’ meeting is the highest authority of the fund company. It exercises its powers in accordance with the “Company Law of the People’s Republic of China” and the “Articles of Association” of the fund company. The fund company has a board of directors (the board), who are elected by the general meeting of shareholders, and the board is responsible for the shareholders’ meeting. Senior management is appointed by the board. The behaviors of fund companies are strictly in accordance with Chinese laws and market rules, and the identity of employees is also transparent to the market.

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Table 25.1 China Integrated Circuit Investment Fund Co. Ltd. Shareholder Composition Shareholder name Ministry of Finance of The People’s Republic of China CDB Finance Co., Ltd. China National Tobacco Corporation Beijing E-Town International Investment & Development Co., Ltd. China Mobile Communications Group Co., Ltd. Shanghai Guosheng (Group) Co., Ltd. Wuhan Financial Holding (Group) Co., Ltd. China Telecom China Unicom China Electronics Technology Group Corporation China Electronics Corporation Datang Telecom Technology Industry Holding Co., Ltd. Sino IC Capital Beijing Ziguang Communication Technology Group Co., Ltd. Shanghai Wuyuefeng Pujiang Equity Investment Partnership (Limited Partnership) Cybernaut Investment Group Co., Ltd. National Council for Social Security Fund, The People’s Republic of China PICC Asset Management Company Limited China Life Insurance (Group) Company

Shareholder type Common stock Common stock Preferred stock Common stock Preferred stock Common stock Common stock Preferred stock Common stock Common stock Common stock Preferred stock Common stock Preferred stock Common stock Common stock Common stock Common stock Common stock Common stock Common stock Preferred stock Preferred stock Preferred stock

In accordance with the principle of separation of ownership and management rights, the fund company entrusted Sino IC Capital as the sole manager of the fund. The registered capital of Sino IC Capital was 1.2 billion Yuan, which was jointly funded by 8 shareholders. CICIF and Sino IC Capital belong to the contractual relationship of entrusted management. Sino IC Capital manages the investment business of the fund and collects the management fee according to the agreement. After the investment project exits and meets the threshold income of the fund company’s shareholders, Sino IC Capital and the fund company shareholders share the excess investment income according to the agreed ratio. At present, Sino IC Capital’s shareholders include CDB Finance Co., Ltd., Saidi Industrial and Information Technology Research Institute Co., Ltd., Beijing Saipinke Technology Co., Ltd., Yingfu Taike Venture Capital Co., Ltd., Suzhou Yuanhe Holdings Co., Ltd., China Mobile Communications Group Co., Ltd., Beijing E-Town International Investment & Development Co., Ltd., and Shanghai Digital Industry (Group) Co., Ltd. The fund investment business adopts a market-based decision-making mechanism, which mainly focuses on the growth of the project and is not subject to government intervention. The enterprises invested by the fund do not distinguish

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between ownership and domestic and foreign investment. The fund’s investment projects will be withdrawn in a market-oriented manner after the expiration of the fund company’s existence. Generally speaking, this fund is similar to other private equity funds. Before investing, it mainly measures the technological innovation level, profitability, corporate management team, market share, investment risk, and other factors. The National Fund has made a total of 43 effective investment decisions involving 35 enterprises by December 31, 2016. The guaranteed fund reached 81.8 billion RMB and the actual fund reached 56.3 billion Yuan, accounting for 59% and 41% of the total initial phase of the fund. The investment project covers all aspects of the industrial chain such as integrated circuit design, manufacturing, packaging and testing, equipment, materials, and ecological construction.

Government Investment Funds on IC International Government Investment Fund is effective to promote IC industry and thus widely used. It can not only make a huge influence on the market competition and the value of a certain enterprise, but also the overall situation of the global IC industry. Obviously, except the financing from the equity of industrial investment funds, debt financing such as syndicated loans is available to promote the industry too. In June 2014, “The Outline for Promoting the Development of the National Integrated Circuit Industry” was officially issued and implemented, which clearly proposed the establishment of a national industrial investment fund, supported the establishment of local investment funds for the integrated circuit industry, and encouraged all kinds of venture capital and equity investment funds from the society to enter the integrated circuit field. Under the guidance of this document, the National Integrated Circuit Industry Investment Fund was established in September 2014. Local government investment funds have also been established in Beijing, Shanghai, Fujian, and other places. Both national and local funds have played an important role in promoting the development of China’s IC industry. And unlike China, few other countries focus on integrated circuits as an industry. Therefore, the following funds do not focus on IC industry, but have significant influence on it instead. In European and American IC industry, direct financing is used more by market due to the feature of it being highly market oriented, hence the government usually adopted indirect ways to support the industry. Conversely, Japan and South Korea governments usually employ indirect financing channels to support the industry. Therefore, all the following funds are government investment funds in Southeast Asia and West Asia. Singapore Temasek is a fund 100% owned by the Ministry of Finance of Singapore. It is the most famous government investment fund in Singapore, whose investment represents the will of the government. Prior to Temasek, the Economic Development Board (EDB) and its financial resources had taken the same part in Singapore’s IC industry. In 1991, EDB established the Singapore Microelectronics Research Institute, which is mainly engaged in the R&D of value-added products in the electronics industry related to microelectronics. From 1991 to 1994, EDB had

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invested a total amount of more than 50 million US dollars to the Singapore Microelectronics Research Institute. In 1991, Temasek began to take control of the IC industry by acquiring 95% stake in Chartered Semiconductor Manufacturing (CSM) and transformed it to a foundry. Chartered Semiconductor has also formed a governance structure similar to Temasek: one of the seven members of the board of directors is appointed by the government, and the other six are inside and outside the company; the general manager is elected by the board of directors, and if the performance of the company did not improve, the Ministry of Finance had the right to remove the management team [8]. Prior to this, Chartered Semiconductor split out of the design center Tri Tech, which was wholly owned by Singapore Technology Venture Capital. In 1992, EDB and Tech Instruments, Canon and Hewlett-Packard jointly invested on Tech Semiconductor, with a total amount of 325 million dollars. EDB invested 26% and provided low-interest loans and tax incentives. This is also the first storage and DRAM manufacturing company in Singapore. The huge success of the investment has greatly improved Singapore’s foundry techniques. In 1995, Temasek established STATS ChipPAC, a sister company of Chartered Semiconductor. Later, EDB also invested in Philips (later transferred its equity to NXP) and TSMC’s joint venture project in Singapore (Systems on Silicon Manufacturing Co Pte Ltd) [9]. So far, Singapore has established an IC industry chain system through the government funds. However, because of the overcapacity of global IC industry and the constant loss of enterprises since 2000, the Singapore government investment fund was considering withdrawing from the IC industry. In the 2008 financial crisis, Temasek had to sell Chartered Semiconductor and Star Branch. In 2010, Temasek sold a 62% stake in Chartered Semiconductor to its parent company, Advanced Technology Investment Co (ATIC), for $2.424 billion. In 2014, Ion Investment, a subsidiary of Temasek, sold its stake in Seoul Semiconductor for $176 million ($242 million in 2009). In 2015, Temasek sold the Star Branch Jin Peng, which has been the world’s fourth largest packaging and testing company, to Jiangsu Changdian. At present, Temasek has basically withdrawn from the IC industry. The UAE government investing fund has increased its investment in the IC industry in recent years. Its main investing institution is the Mubadala Development Company established in 2002 by the government, and the Abu Dhabi Advanced Technology Investment Corporation (which was wholly owned by the former in 2011) established in 2008. At present, Mubadala Development Company has a total size of US$63.5 billion. The investing target of the UAE government investment fund in the field of IC is mainly AMD and the factory of GF in New York. In 2009, the UAE government investment fund and AMD jointly established GF, and then acquired AMD’s shares in the grid, making it a wholly owned enterprise. After that, the company continued to grow through the merger of Singapore Chartered Semiconductor and IBM Microelectronics Division. In 2016, the UAE government investment fund invested $2 billion in the Core to develop its 7 nm process. Except the property above, the UAE government investing fund also owns 8.1% of AMD shares. GF has invested and established its factory in China in 2017.

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Khazanah Nasional Berhad (KNB) was established in 1965 and is 100% owned by the Malaysian Ministry of Finance. It currently has $32.5 billion in assets. The treasury holdings have invested certain amount of money to the IC industry, but only accounts for about 2% of its total assets. Its main investment is SilTerra, the world’s 15th-ranked foundry (sole proprietorship, established in 1995), and test equipment manufacturer Aemulus (shared 15%). SilTerra’s overall financial situation is not good: the accumulated loss in 2011–2014 has reached RM1.7 billion (about 380 million US dollars); Aemulus has remained profitable.

International IC R&D Investment Many successful IC R&D projects are supported and invested by the government. Thus, the government’s support and investment have greatly helped the development of the IC industry. The Interuniversity Microelectronics Center (IMEC) is a non-profit organization founded in 1984 by the Faradez Provincial Government of Belgium. Its purpose is to combine the academic research strengths of universities in the Dutch-speaking region and hence commit to the R&D of IC pioneer technology which in turn drives the development of peripheral related technologies. In the beginning, due to the limited budget of the Belgian government, only 62 million EUR were invested. In 2007, according to the agreement between IMEC and the government, the provincial government of Faradez provided IMEC with a total of 210 million EUR in 2007–2011. In the past 5 years, the total budget of IMEC has exceeded 1.2 billion EUR. Nearly 1 billion euros are all earned by research and development income. IMEC’s R&D projects are closely combined with industry development, which creates a unique business mode that cooperates with companies to jointly develop and share results [10]. After 33 years, IMEC has become the most influential IC technology R&D center in the world and has made great contribution to the world’s IC industry. Japan’s Very Large Scale Integration (VLSI) alliance is a typical case of an IC investment project. With the help of this alliance, Japan surpassed the United States in micro-process memory chips and began to replace the United States as the monopoly in semiconductor industry. It continuously occupies more than half of the global semiconductor market. In the process of industrial development, the government has provided many subsidies to the alliance. From 1976 to 1979, the government subsidies of VLSI Alliance were 29.1 billion Yuen, accounting for 40% of the total funding of 73.7 billion Yuan. The R&D expenditure of the VLSI Alliance generally accounts for 20% to 60% of the total R&D expenditure of the Japanese semiconductor industry. Toshiba, Hitachi, and other IC companies have supported the R&D of VLSI. According to the agreement, the R&D results are first used to return government subsidies while enterprises can hold technical patents. In 1976–1979, the VLSI Alliance obtained more than 1000 patents, which greatly supported Japanese companies to occupy the global market. In 1980, Japan successfully developed 64Kbit dynamic random-access memory, which was half a year

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earlier than the United States; in the same year, it developed the 256Kbit DRAM, which leads ahead the United States for 2 years. In 1985–1992, Japan became the world’s largest semiconductor producer. Based on the experience of Japan’s development, South Korea chooses to select breakthroughs, introduce and absorb foreign technology, which finally result in technological independence. The main reason for the results of the Korean IC industry is still the government’s guidance and support. In 1981, the Korean government officially adopted the Semiconductor Industry Comprehensive Development Plan, which mainly developed four fields: ultra-large scale IC, computers, communication equipment, and electronic components. In 1983, the Ministry of Commerce and Industry published the Semiconductor Industry Breeding Plan and invested 260 billion won in the next 4 years to establish a semiconductor production basement. In 1986, the South Korea Semiconductor Consortium, which was founded by 13 companies, invested 140 billion won in 3 years. The government and the consortium each invested half of them to develop ultra-large-scale IC of 4 Mbit DRAM or more. Since the 1990s, the Korean IC industry has risen rapidly, and Korean companies are also far ahead in the global rankings.

Mergers and Acquisitions in IC Industry Table 25.2 lists some of the mergers and acquisitions (Ms&As) events that have happened in China’s semiconductor industry since 2009. It can be seen that, from 2003, Ms&As is an increasingly frequent occurrence in IC industry, while convenient financing channels and strong capital strength also makes listed companies become the initiators for most of Ms&As. The reasons for the frequent occurrence of industrial mergers: on the one hand, after 60 years of development, the trend toward industrial concentration is increasingly obvious, and leading enterprises have obtained more market shares thanks to their technical and capital advantages, squeezing other enterprises into smaller market shares; on the other hand, with the emergence of new application fields such as mobile Internet, Internet of Things, and cloud computing, semiconductor technology will still continue evolving, but domestic IC industry is still a long distance away from an internationally advanced level in terms of R&D of new technologies, reserves of talents, and scales of production, and therefore, the extensional development through Ms&As is one of the ideal approaches enabling domestic enterprise to transcend barriers and rapidly increase competitiveness. Firstly, external mergers completed by an IC enterprise can help achieve such objectives as obtaining advanced technologies and improving production lines: in the first place, it is to obtain the assets of the target enterprise with intellectual property rights such as technologies and patents; in the second place, it is to join hands with the technical team of the target enterprise and strengthen the ability for research and development; in the third place, it is to use the target enterprise to extend its own sales channels so as to produce a synergetic effect. For example, in the case of TFDME buying out the two subsidiary companies of AMD Penang and

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Table 25.2 Some of the events of mergers in China’s semiconductor industry since 2009 Time of completion 2009 2011 2013

2014

2015

2016

2016 2017

2018 2019

2020 2021

Buyer Inspur Good Ark Tsinghua Unigroup Unigroup Guoxin Taiji Huatian Technology Unigroup Goer PDSTI Unigroup Guoxin Huatian Technology Summitview Capital, Hua Capital, E-Town Capital Jaccapital Liyuan Info (A-share: 300184) SMIC TFME Hua Capital Changjiang Electronics NAURA Liyuan Info Jaccapital Chipone etc. Liyuan Info Shanhai Capital Canyon bridge Wanye Enterprises Huatian Technology GTA Semiconductor China Wafer Level CS Gigadevice Semiconductor PNC Process Systems Will Semiconductor Wingtech Technology Primarius Technologies Ingenic Semiconductor Will Semiconductor

Seller Qimonda AG China R&D Center Mingrui Optoelectronic Spreadtrum Communications Shenzhen State Microelectronics Xinyihui Electronics Kunshanxitai RDА Dynaudio Holding A/S Montage Technology Xi’an Huaxin FlipChip International LLC ISSI NXP RF Power DXY LFoundry AMD Suzhou, AMD Bingcheng Omni Vision Technologies STATS ChipPAC NMC Feat China NXР Standard products business iML Wuhan Powertek Analogix Imagination Kingstone Unisem ASMC Anteryon SILEAD Bandweaver OmniVision Technologies,SuperPix Nexperia Platform Design Automation ISSI Synaptics Mobile LCD TDDI Business

Note: The M&A deals completed by the members of China Semiconductor Association and by some of relevant listed companies for the purpose of holding a controlling number of shares should be taken as the main source. The names of both buyer and seller are in short form. The mark represents a case of privatization of US stocks

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AMD Suzhou, AMD’s subsidiary companies have the world advanced large-scale platform for high-end packaging process in mass production. The merger can not only enable TFME, a domestically major packaging and testing enterprise, to reach the world top level in the field of flip-chip packaging but more importantly, improve its productivity and competitiveness in terms of high-end advanced packaging process as well, so that it can provide customers at home and abroad with scalable customized high-end packaging and testing services. Secondly, through Ms&As, the optimization and consolidation of resources can be achieved within the industry so as to produce a scale effect. The characteristics of capital-intensive industries are especially obvious in the field of IC manufacturing. The technological processes of manufacturing are continuously upgrading, tending to require an investment of several billions or tens of billions of US dollars and posing a huge challenge to the enterprises. Only the enterprises whose production is on a considerable scale can achieve the goal of making profits. At present, the development in China’s IC industry is characterized by low concentration, modest corporate scale effects, serious homogeneous competition, and discretely distributed resources unfavorable for a healthy industrial development. Under such circumstances, Ms&As are an effective measure without doubt. For example, in 2013, Huatian successfully bought 63.85% of the shares in Kunshanxitai, rapidly increasing its capacity for advanced packaging process, and enhancing its own competitiveness. At last, the Ms&As in the market in the form of industrial cooperation can help achieve the goal of multiple wins. For example, not only has the acquisition of STATS ChipPAC by JCET enabled Changjiang Electronics to obtain advanced technologies and strengthened its position as a domestically leading packaging and testing enterprise and an industrial oligarch, the two enterprises also have strong complementary and synergetic effects on each other in terms of market shares, capacities, and human resources, able to enter high-end international market in the future and get closer to China’s market and clients, improving global competitiveness. It is worth mentioning that industrial parties such as the China Integrated Circuit Industry Investment Fund and SMIC have been introduced to this acquisition, and this has great reference value for domestic IC enterprise to explore the models of overseas Ms&As from now on and for the cooperation between upstream and downstream enterprises in the industrial chain.

IPO and Going Private Initial Public Offering (IPO) is the process that a company to be listed offers shares on a securities market to the public and raises funds for the first time, and requires the issuer to issue shares to the public in a securities underwriting institution and to be listed on a stock exchange after meeting necessary conditions and being approved by or registered in a security regulatory agency, and thus the company becomes a listed

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public company [11]. In China, the existing Securities Law specifies that public offering of stock is the precondition for listing and transaction, so the two concepts, IPO and listing, are closely connected and are always mixed up. Chinese A Share market, Hong Kong stock market, and the US stock market are three IPO targeting markets popular with Chinese IC enterprises. Because IC industry is a typical capital-intensive industry, and there is a “winnertake-all” phenomenon in the industry, enterprises whose market shares rank among the finest have motive force to extend their scales to obtain more market shares. No doubt listing is the ideal route for the development of an enterprise; with strong “hematopoiesis capability,” enterprises can obtain powerful financial support through more R&D input for endogenous growth or through merging for external growth. For example, the case in which JCET acquired STATS ChipPAC fully reflects the capital advantages of listed companies. Whether enterprises listed in different places can obtain higher valuation is related to their comprehensive capabilities and is subject to restriction of the market growth space corresponding to development stages of different industries, especially for the IC industry and even the whole semiconductor industry. With 60 years of development, the semiconductor industry in the United States now has entered a mature period from incubation stage and growth stage, and the growth slows down; in China, huge population brings a vast market. And with perfect electronic product design, perfect production and industry ecology and policy encouragement and support, the semiconductor industry is now flourishing, and the market is growing powerfully. Correspondingly, difference in the industrial development stage between China and the United States is directly embodied through the valuation of individual stocks of the semiconductor industry: higher price-earnings ratios (P/E ratios) of relevant enterprises on A Share market reflect recognition for excellent development trend of the IC industry at the growth stage. Certainly, difference in valuation between the Chinese stock market and the US stock market is related to other factors, such as the continuous high growth rate of Chinese economy in recent years, unopened capital accounts in balance of international payments and listing entry threshold of stock market higher than that of US stock market. Going private of a listed company is a capital operation behavior to delist a listed company and to make it become a nonpublic company. Going private sometime occurs when the market value of a listed company is lower than its book value. Some cases of going private are initiated to merge listed companies to realize industrial integration. Going private also is initiated to transfer company stock to another market to get a higher valuation level so as to obtain capital premium, and the stock market value does not fall below the book value by this time. Going private is always proposed by the management or majority shareholders (can also be initiated by other investors) who buy the shares of the listed company from other shareholders with cash or securities, then submit application for delisting to the exchange and then complete delisting. Going private of a company is common on mature capital markets in the United States and Hong Kong. However, the opportunity of being listed on Chinese A Share market is rare and cases of going private are also rare in China.

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IPO and going private are not contradictory and are both ways to obtain better development opportunities for enterprises. Furthermore, many companies choose to be listed again after going private. For example, ISSI was listed in Taiwan, China, and the United States successively and then delisted through going private. Sometimes, going private is also a link of industrial integration. For example, Broadcom was acquired by Avago and thus was delisted from the NASDAQ market in 2016. From 2013 to 2016, some Chinese companies listed in the United States choose to go private and seek to return A Share, some of which are IC enterprises. For example, Spreadtrum and RDA were acquired by Tsinghua Unigroup in 2013 and 2014, and Montage Technology completed going private in 2014. Firstly, the IC industry in the United States has entered its mature period, and investors in the United States cannot completely understand the operation mode and value of Chinese IC enterprises which are in the growth and rapid development period as growth of the whole global market slows down, affecting valuation of enterprises. Secondly, the increasingly mature domestic market and various auxiliary policies provide convenient financing channels and policy environment for excellent IC enterprises. US enterprises including OmniVision accepted the offer of going private from Chinese financial groups, proving that Chinese efforts in promotion for development of IC industry are being recognized by all parties. From a point of view of historical experience, the reason why the IC industry in the United States keeps flourishing is that the multi-layer capital market with continuously emerging creative financing tools provides powerful support. Therefore, Chinese IC enterprises should seek to be listed in appropriate time and places and give exit channels for early venture investors, forming a virtuous cycle of “investment-exit-reinvestment-reexit” for capital in the industry.

Procedure of Venture Investment for IC Companies The concurrent IC industry in the electronic information field has huge demand for venture capital, which covers various industrial links including design, manufacturing, assembly and test, equipment, and materials. Venture investment in the IC industry is featured with high level specialization, so during each investment stage, professional teams are needed to promote the success rate. Generally, the procedure of venture investment is shown as in Fig. 25.3. During decision making for venture investment in an IC enterprise, its financial and legal status, management experience, and operation status are taken into consideration, and the target enterprise is subject to analysis according to some features inside the industry. For details, see Table 25.3. Venture investment in the IC industry always focuses on enterprises at the early development stage, which determines the long period and high risk for investment. In counties and regions with mature industries and capital markets, the main source of venture capital is market-oriented institutional investors and enterprises. With

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Fig. 25.3 Procedure of venture investment project

Table 25.3 Industrial features need to be evaluated for venture investment in the IC industry Industrial features Intelligence intensive Capital intensive

Long input cycle

Coordination of industrial chain

Global competition

High industrial concentration

Corresponding concerns Expertise and technical talents Rapid technological development and leading technologies High capital threshold, especially in such fields as manufacturing, assembly and test, and equipment High one-time capital input, for example, purchasing advanced manufacturing equipment Long R&D period for new technologies Continuous input period for product R&D is usually calculated in terms of years, for example, 1–3 years Many chain links for promotion of products and customers Design, manufacturing, and assembly and test need excellent industrial coordination Chips, components, and complete-machine manufacturing need industrial coordination and cooperation Complete-machine manufacturing, brand construction, and terminal sales are closely tied to each other and form a chain Global allocation of technical and management talents Global sharing of supporting technologies, such as production process Global purchase of equipment and materials Global distribution of markets and customers When a segment market develops to a certain extent, leading enterprises have greater market shares The rate of margin of an enterprise and its market share has a positive correlation

regard to the emerging Chinese IC industry, factors such as high entry threshold, great demand for investment capital, long period, and obvious uncertainty make it difficult for enterprises to obtain market-oriented capital. Therefore, government funds first invest in the industry experimentally through establishment of guidance funds and then lead private capital to following up, which can create excellent investment and financing environment and promote development of the industry. Venture capital institutions in the IC industry can provide capital and also highquality post-investment value-added service for target enterprises. Firstly, investment

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Table 25.4 Some IC enterprises supported by venture capital and their investment institutions Enterprise name Spreadtrum RDA SMIC GigaDevice Montage Technology

Some institutions involved in venture investment (random order) Shanghai Industrial Holdings Limited, CSC Group, Lenovo Capital and Incubator Group, Northern Light, New Enterprise Associates (NEA) Warburg Pincus, International Data Group (IDG) Jade Bird Universal, Shanghai Industrial Holdings Limited, Goldman Sachs, Walden International TusHoldings, Zhonghai Venture Capital Investment, Westsummit Capital AsiaVest Partners, Intel Capital

teams can take advantage of their experience in technologies and management accumulated in the industry to provide suggestions and help for development of enterprises; secondly, investment teams can help enterprises connect downstream, upstream, other institutions, and social resources and build a cooperation network. As an investment behavior, the final purpose of venture investment is to obtain returns through project exit, and exit is the final link of the whole investment process. The way of exit of venture investment mainly includes being listed and stock right transfer. When an enterprise invested in is listed, venture capital institutions can obtain considerable investment returns, and the enterprise invested in can also obtain continuous financing capacity, which can be considered as an ideal way of exit. In the market, such ways of exit as buying-back by original shareholders, purchased by the management, M&A, and transferred to other institutions are also quite common. For a part of IC enterprises supported by venture capital and their investment institutions, see Table 25.4.

Due Diligence in IC Enterprises Generally, an equity investment institution takes mainly three steps in making a decision on the investment in an IC enterprise: the first step is to collect the information about potential target enterprises according to the development in the market and in IC enterprises, analyzing the investment values of the target enterprises in the light of the organization’s own concept of investment and selecting a suitable enterprise from them before having the project registered and authorized; the second step is to verify the investment feasibility and value certainty, carrying out due diligence in the target enterprise, comprehensively studying the enterprise’s operational status and the potential for development, evaluating the potential risks from all aspects and producing a due diligence report; the third step is for the investment committee to make a decision whether an investment should be made or not according to the results from the due diligence. Among them, the due diligence is a very important step – if it is found during the due diligence that the target enterprise carries a potential uncontrollable huge risk or that a similar situation exists, the investment committee may veto the project.

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The due diligence (“DD” for short) is an investigation of a potential investment, generally including but not limited to such aspects of the target enterprise as business, finance, and legal affairs. The investment institution may engage an external team, for example, the experts in the industry, accountants, lawyers, etc., to take part together, and then a checklist for the due diligence needs to be made. For the highly professional IC industry, it is necessary to fully take into account all the factors at macro-to-micro levels in the industry and in the enterprise, such as the periodicity of the market for IC industry, fast technical and product upgrading, effects of oligopoly in refined industrial segments, and the technical barriers facing newcomers. After the checklist for the due diligence is made, the team will collect the information about all the aspects step by step and carry out a detailed analysis. In the light of the characteristics of IC industry, Table 25.5 gives examples of some important items to be analyzed during the due diligence. In reality, there is no such enterprise that is perfect in every aspect. For the enterprises at different developmental stages, the focus of the due diligence differs. Generally speaking, by carrying out the due diligence, the investment institution’s goal is to understand the enterprise in detail, and analyze the future growth potential and competitiveness of the enterprise in the market according to the collected information, so as to make a reasonable decision on investment. Table 25.5 Examples of the items to be analyzed during the due diligence in IC industry Industrial characteristics Intelligence-intensive

Capital-intensive

With a long period of investment return

With industry chain synergy In global competition

Industrial intensity

Examples of the items analyzed in due diligence Background of the founder and the core team, professional ability Core technology and reserve in the enterprise, IP autonomy Competitiveness of core technology Input into the R&D of new products Financial health index (e.g., cash flow) Ability of continuous operation and of addressing risks from the market History of financing and structure of equities Return on investment in product (ROI) Competitiveness of product in the market (e.g., placement in the market, costs, average selling prices, gross margin) Marketing and sales channel development ability (e.g., sales team) Trend of industry transfer (e.g., “smiling curve”) Upstream and downstream synergy, operational efficiency Competitive landscape in refined market segments Corporate governing structure (e.g., equity incentives mechanism for the core team) Global service support Advanced tools and equipment Target market segments and target client base Developmental stages in refined market segments and competition policies Industrial strategic objective (e.g., industrial leader or oligarchy) Operational execution index (e.g., gross margin, market share)

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Asset Evaluation of IC Enterprises For such purposes as operational management and asset transactions, enterprises need to carry out asset evaluations, with the targets including real estate, chattels, intangible assets, corporate values, asset losses or other economic rights, and interests. The evaluations are generally conducted when such events take place as transformation into shareholding systems, public offering, mergers and acquisitions, mortgage loans on assets, external financing and equity transfer, and the results of evaluations will serve as a frame of reference for the pricing of assets. There are four basic approaches to evaluation, that is, income approach, cost approach, market approach, and liquidation approach. Except the liquidation approach that is applied in cases of bankruptcy, the other three approaches are relatively applied in general use. In terms of “Assets Evaluation Norms-Corporate Value,” the income approach is a method of capitalizing or cashing in expected earnings so as to determine the value of the target of evaluation [12]. The use of the income approach requires a comprehensive consideration about the previous operational condition of the target under evaluation and the predictability of a future income, as well as reasonable assumptions about various factors in the impact on discount. The income approach is mostly employed for evaluating the value of an enterprise as a whole but the result is prone to the impact of subjective judgment or unforeseen elements. The cost approach (called Asset-Based Approach in evaluation of corporate values) is a process where the replacement costs of various assets to the targets under evaluation are measured, calculated, added together, and reduced by the factors in devaluation before the evaluated values come out. The cost approach has a relatively large scope of application but is premised on whether the assets to the targets under evaluation can be replaced, recognized, and evaluated, therefore unsuitable for evaluating the targets with relatively much intangible assets as in high-tech industries. The market approach refers to the method of determining the values of the targets under evaluation through the values of the benchmarks (e.g., consult and follow listed companies or comparative cases of transactions), similar or comparable to the targets under evaluation in an active and effective market of fair trade. The above three approaches each have their own applicable conditions and limitations, and should be flexibly applied according to conditions during actual operation. In the asset evaluation of IC enterprises such as asset-light fabless ones and those with heavy asset in the categories of materials and equipment as well as pure-play foundries and packaging and testing enterprises, it is necessary to choose a suitable approach to evaluation according to the characteristics in the properties of the assets to different enterprises. Apart from ledger assets, a typical fabless enterprise in the industry also owns plenty of intangible resources including certifications, teams, services, and marketing resources, and the application of income approach can take into account more comprehensively with intangible resources as well as the synergistic effect produced between other assets within the enterprise, reflecting the value of the overall assets to

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the enterprise in the future in terms of profitability. Therefore, in the evaluation of such events as mergers and acquisitions that involve shareholders’ equities in an enterprise in the category of design, the income approach is relatively used more often. The cases of this type include Navinfo (stock code: 002405) buying out AutoChips [13], Tongfang Guoxin (currently Unigroup Guoxin, stock code: 002049) buying out Shenzhen StateMicro Electronics, and so on [14]. The asset-based approach (cost approach) builds on corporate balance sheets, separately evaluating the value of each asset, with the results serving as a relatively highly objective basis and easy to be accepted by both the parties of the seller and the buyer in such transactions as mergers and acquisitions. For example, in the case of SevenStar Electronics (currently NAURA, stock code: 002371) buying out North Microelectronics, the evaluation company has adopted the income approach and the asset-based approach. Given that China’s IC equipment industry to which North Microelectronics belongs is still in its early stage of development, it will take time for the industry as a whole to reach the internationally advanced level. Although the enterprise has a good potential for growth, it is uncertain whether any technical breakthrough is made so as to establish a core competitiveness and profitability. Therefore, in the final evaluation report, the results from the evaluation of all the shareholders’ rights and interests with the asset-based approach prevail [15]. If the target for evaluation has a certain number of comparable enterprises (listed companies) in the capital market whose sizes, positions in the industry, asset structures, and operational models are all similar to those of the target under evaluation, the results delivered through the application of the market approach and after certain corrections made to corporate developmental qualities and corporate characteristics can reflect the judgment of the market on the general value of the enterprise of the same type. For example, in the case of Jiangsu Changjiang Electronics Technology (stock code: 600584) planning to buy out Suzhou Long Telegram and New Investment, the evaluation company has chosen the market approach and the income approach to evaluate all the shareholders’ rights and interests in Long Telegram and New Investment. Moreover, it is taken into account that the market approach is based on the comparison of financial operation and income status with comparable enterprises at the time of evaluation, which can better reflect the value of a rational investment. Therefore, in the final report, the results obtained with the market approach prevail [16]. In the stages of transaction, although the asset evaluation does not play a decisive role, the results of the evaluation have great significance for reference. With the rapid development in domestic IC industry, there are increasingly more cases of mergers between and consolidation of enterprises. If the target enterprise is comprehensively taken into account and a reasonable method is chosen to comprehensively evaluate the value of the enterprise, it is helpful for a transaction to proceed smoothly.

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References 1. F. Chen, Research on the linkages and development strategies of VC, private investment fund and industrial investment fund in China. Financ. Theory Pract. 1, 86–90 (2010) 2. Annual Industry Development Report of Private Equity Investment Fund in China, Asset Management Association of China (China Finance and Economics Press, 2021) 3. D. Chen, The development course of venture capital and its role: One of the series of venture capital research in the world (Region). Sci. Technol. Econ. Market 4, 8–12 (1999) 4. Z. Zhou, Development Practice and Enlightenment of Korean Information Industry and Big Companies (Publishing House of Electronics Industry, Beijing, 2006).: Chapter 3 5. J. Wang, Research on Financial Support for the Growth of Strategic Emerging Industries in China, Ph.D. dissertation, Department of Finance, Anhui University of Finance and Economics, Hefei, China (2013) 6. Z. Zhou, Financing and Corporate Governance of Integrated Circuit Manufacturing Industry. Rev. Indust. Econ. 1, 2–3 (2017). https://doi.org/10.19313/j.cnki.cn10-1223/f.2017.01.001 7. X. Wang, X. Li, Case analysis of Jiangsu Changjiang Electronics Technology Co., Ltd. Merger and Acquisition of Star Branch Jinpeng, Application of IC (2015) (no. 2, pp. 24–25) 8. C. Zhang, Microelectronics industry in Singapore and Malaysia. J. Semiconduct. Technol. 4, 17–21 (1995) 9. J. Matthews, W. Li, Oriental silicon Island: Singapore’s semiconductor industry. J. Theory Stud. Explor. 3, 76–79 (2002) 10. IMEC Cooperative R&D Road (2009-02-27): Interview with IMEC Executive Vice President. Available: http://www.eeworld.com.cn/manufacture/2009/0227/article_140.html 11. Securities Association of China, Stock Issuance Market. Accessed 23 Nov 2022. https://tzz.sac. net.cn/rsbd/scjs/201209/t20120914_59754.html 12. China Appraisal Society, Appraisal Standards 2011-227, China Asset Evaluation Association, December 30, 2011. Available: http://www.cas.org.cn/pgbz/pgzc/47398.htm 13. China Zhong Tong Hua Ping Bao Zi No.:173, May 13, 2016, The asset evaluation report into the project for Navinfo to plan to buy out equities in AutoChips (Hefei), China Alliance Appraisal Co., Ltd., Beijing, Available: http://www.cninfo.com.cn/new/disclosure/detail? plate¼szse&orgId¼9900012447&stockCode¼002405&announcementId¼1202325364& announcementTime¼2016-05-17%2008:04 14. Zhuoxindahua Appraisal, The asset evaluation report into the appraisal project on Tongfang Guoxin planning to buy 96.4878% equities in Shenzhen StateMicro Electronics, Zhuoxindahua Appraisal. Zhuoxindahua Report No.: 036, August 6, 2012. Available: http://www.cninfo.com. cn/new/disclosure/detail?plate¼szse&orgId¼gssz0002049&stockCode¼002049& announcementId¼61422236&announcementTime¼2012-08-15%2006:30 15. Beijing Yachao Appraisal, The report about the evaluations of all the items of the shareholders’ rights and interests in the Equipment and Technology Research Center of North Microelectronics Bade involved in SevenStar Electronics planning to issue shares for purchasing assets and raise funds accordingly, Beijing Yachao Appraisal No.: A196((Part One), December 30, 2015. Beijing, China. Available: http://www.cninfo.com.cn/new/disclosure/detail?plate¼szse& o r g I d ¼9 9 0 0 0 0 6 1 3 7 & s t o c k C o d e ¼0 0 2 3 7 1 & a n n o u n c e m e n t I d ¼1 2 0 1 9 7 3 4 2 4 & announcementTime¼2016-02-05 16. Zhong Lian Appraisal, The asset evaluation report about the project for Jiangsu Changjiang Electronics to plan to issue shares to buy the equities in Suzhou Long Telegram and New Investment, Zhong Lian Appraisal Report No.: 36, January 11, 2017. China United Assets Appraisal Group. Beijing, China. Available: http://www.cninfo.com.cn/new/disclosure/de-tail? plate¼sse&orgId¼gssh0600584&stockCode¼600584&announcementId¼1203012127& announcementTime¼2017-01-13

Section IV Integrated Circuit Production Lines Richard Chang, Lei Jiang, Yibo Wang, and Yonghang Yu

Introduction Integrated circuit (IC) is regarded as the “bread-and-butter” of modern industry with technology level and manufacturing scale as the symbols of industrial competitiveness of national power. IC production lines and facilities have progressed rapidly toward the “smart manufacturing” with full automation, artificial-intelligence (AI), big-data analysis, etc. This chapter covers the development history of IC production lines in China and worldwide, as well as the knowledge related to the establishment of IC production lines. The IC production line (or plant) is also commonly referred to as IC manufacturing facility, wafer fabrication lines, or simply fab or Fab. It includes an introduction of development history, site selection and methodology for environment impact assessment, design of IC production lines, clean room and air condition systems, central gas and chemical supply systems and monitoring systems, plant construction and management, energy saving and consumption reduction schemes, hazardous chemicals management, waste water and solid material treatments, and current status and trends of future IC production lines.

Development History of IC Production Lines

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Contents History of IC Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 History of IC Production Lines in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Abstract

This chapter overviews the development of IC production lines worldwide and specifically the establishment of IC manufactures in mainland China. It started with a few state-owned factories of discrete products and some institutions of R&D and then gradually developed with the mass production capabilities by both international-invested and domestic companies. Some of them are already among the largest and most advanced IC factories in the world. Regarding the technology nodes, as of 2020, there are two companies in China continuously investing on the IC fabrication services at 14 nm technology node. Keywords

Production line · Wafer · Fabrication · Mass production · Technology node

IC product lines have been continuously developing worldwide, starting from the 1960s, while in China it has a relative short history. Information for further reading is found in references [1–4].

J. Zeng (*) SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_26

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History of IC Production Lines 1960: H. H Loor and E. Castellani invented photolithography as an enabling technology for modern IC production. 1963: F. Wanlass at Fairchild Semiconductor invented low-power circuit using complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs). 1964: R Noyce at Fairchild Semiconductor invented planar IC technology. Soon after, there were multiple semiconductor manufacturing lines established in the USA using 1–200 (inches) of wafers. 1968: The first CMOS gate-array semiconductor product was manufactured by Radio Corporation of America; Poly-Si replaced aluminum (Al) as the material of gate electrode. 1970: Intel for the first time launched 1 Kb commercial Dynamic Random Access Memory (DRAM) based on n-type MOS (nMOS) technology. 1971: Intel launched the very first microprocessor chip 4004. 1970s: Ion Implantation (II) technology, invented by W. Shockley and his colleagues, began to be widely used in semiconductor manufacturing. 1980s: The USA started building 400 IC production lines. The low-power CMOS technology with dual-doped poly-Si gate and self-aligned metal silicide process was introduced and gradually became mainstream technology. The overall automation in process equipment can greatly reduce the number of operators and also contamination to IC chips from operator’s handling. The IC production lines were maturing gradually with wafer sizes available from 200 , 300 , 400 , and 5,00 to 150 mm and mainly manual operations (e.g., wafer carrying, storing, loading/unloading to equipment, executing processing recipes, etc.). To save operating costs and meet cleanliness requirements, usually wall panels are used to separate areas between high and low cleanliness. 1980s: 200 mm IC production lines using SMIF (Standard Mechanical Interface) with microenvironment were established in operation. Chemical Process Polishing (CMP) technology was invented and widely used for planarization to achieve the required flatness in multilayer interconnection. 2000: In the beginning years, there were 300 mm IC production lines established and in operation. Wafer cassettes with SMIF microenvironment became the mainstream in IC production lines. 2007: Intel successfully adopted HKMG (high-k metal-gate) technology at 45 nm technology node. 2011: Intel was first to manufacture FinFET devices at 22 nm technology node. 2020: The cylindrical gate-all-around (GAA) nanowire [1, 2], nano-sheet, and 3D-stacking transistor [3, 4] technologies are developing rapidly and expected to be adopted at 5 nm node and beyond. See Table 26.1 for a summary of development history of IC production lines.

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Table 26.1 Development history of IC production lines Year built 1958 1964

Wafer size 0.7500 1.2500

1968

200

Company owns representative IC manufacturing line Texas Instrument Fairchild Semiconductor RCA

1971

300

Intel

1974 1980

300 400

Intel Intel

1982 1985 1989

500 150 mm 200 mm

Intel Intel Intel

1993 1995

200 mm 200 mm

Intel Intel

1997 1999 2002 2003

200 mm 200 mm 200 mm 300 mm

Intel Intel Intel Intel

2006

300 mm

Intel

2007

300 mm

Intel

2009

300 mm

Intel

2011

300 mm

Intel

2014

300 mm

Intel

2017

300 mm

Intel, Samsung, TSMC, and Global Foundries

2018

300 mm

Samsung, TSMC

2020

300 mm

Samsung, TSMC

Representative products Oscillator circuit p MOS integrated circuits Double doped polySi gate CMOS 1Kbit DRAM､4004 microprocessor 8080 microprocessor 8086/8088 microprocessor 286 microprocessor 386 microprocessor 486 DX CPU microprocessor Pentium processor Pentium proprocessor Pentium II processor Celeron processor Itanium 2, Pentium 4 Pentium M Celeron M processor Core 2/Celeron duoprocessor Atom processor Xeon 5600 series processor Ivy Bridge processor Broadwell-U processor Cannonlake, System on Chip (SoC) System on Chip (SoC) System on Chip (SoC)

Technology node About 100 μm 25 μm 10 μm 6 μm 5 μm 3 μm 15 μm 1 μm 800 nm 600 nm 350 nm 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm (HKMG) 32 nm (HKMG) 22 nm (FinFET) 14 nm (FinFET) 10 nm (FinFET, QWFET) 7 nm (FinFET) (estimated) 5 nm (GAA) (estimated)

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History of IC Production Lines in China 1960s: Many factories in China established semiconductor production lines using domestic equipment for mostly discrete transistor products. Among those established factories, there were better known ones, e.g., the 5th Shanghai Components Factory, the 7th Shanghai Radio Factory, the 14th Shanghai Radio Factory, the 19th Shanghai Radio Factory, Suzhou Semiconductor Factory, Changzhou Semiconductor Factory, the 2nd, 3rd, 5th, 6th Beijing Device Factories, the 1st Semiconductor Factory, and Xi’An 691 Factory of Ministry of Aviation. 1968: For the first time, ICs based on p-type MOS (pMOS) technology were successfully developed in China by Shanghai 14th Radio Factory. 1970s: Yongchuan Semiconductor Research Academy, the 14th Shanghai Radio Factory, and Beijing 878 Factory, all completed nMOS development and later CMOS ICs that indicated the start of China’s development of CMOS. 1983: Wuxi Radio Components Factory (the 747 Factory) introduced a new production line with 300 wafer from Toshiba Japan and operated in production. The main products were IC components used in color and black-and-white televisions. 1988: Belling Microelectronic Manufacturing Company Shanghai which was established on basis of the 14th Shanghai Radio Factory developed a new 400 IC production line. 1988: Philips Semiconductor Shanghai was founded as a Sino-Dutch joint venture based on the 5th, the 7th, and the 19th Shanghai Components Factory with licensed technologies. It established a new 500 production line. 1990: China Huajing Electronics Company performed the National Project 908 to build a 150 mm IC production line. 1991: Shougang NEC Electronics Company established a 150 mm IC production line. 1999: Shanghai Huahong NEC Electronics Company performed National Project 909 to establish a large-scale 200 mm IC production line with high automation level. It adopted 0.35 μm technology for mass production of 64 Mb SDRAM. 2001: Semiconductor Manufacturing International Cooperation’s (SMIC) first 200 mm IC production line was in operation in Shanghai. It produced logic IC chips with the most advanced 0.25 μm technology and also offered mask-making services to clients. In the coming year, SMIC reached the goal of mass production for 0.18 μm logic IC chips that significantly boosted five technology nodes for China’s IC production level. Currently, SMIC offers IC foundry service with CMOS technology from 0.35 um to 40 nm nodes. Nowadays, SMIC is recognized as one of the most advanced foundries for IC manufacturing in China. 2003: Shanghai Hongli Semiconductor Manufacturing Corp. and Hejian (Suzhou) Technology Company successively established 200 mm IC production lines and are in operation. 2004: Taiwan Semiconductor Manufacturing Company (TSMC) and Advanced Semiconductor Manufacturing Cor. (ASMC), Shanghai, started Fab construction successively. TSMC is dedicated to foundry services for logic technology. ASMC is

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dedicated to discrete power devices (e.g., Power MOS, power diodes, IGBT, SGE, etc.) 2005: SMIC built China’s first 300 mm IC manufacturing line in Beijing and provides IC foundry services with logic technology at 0.18 um, 90 nm, and 45 nm nodes. 2006: Hynix (Wuxi) built a 300 mm IC production line for memory (DRAM and Flash) products. 2007: 300 mm IC production line of SMIC (Shanghai) started in operation and in mass production in 2008. It provides IC foundry services with logic technology at 45 nm and beyond. 2009: Wuhan Xinxin Semiconductor Manufacturing Company successfully established a 300 mm IC production line offering foundry services of flash memory and CMOS image sensor products. 2010: Shanghai Huali Microelectronics Corp. was founded and performed a main improvement program for National Project 909 by establishing a 300 mm IC production line with products in 90 nm/65 nm/45 nm technology nodes.

References 1. D. Xiao, G. Chen, R. Lee, et al., System and method for integrated circuits with cylindrical gate structures, US, 8884363. Accessed 28 Sept 2010 2. D.Y. Xiao, M.H. Chi, D. Yuan, et al., A novel accumulation mode GAAC FinFET transistor: Device analysis, 3D TCAD simulation and fabrication. ECS Trans. 18(1), 83–88 (2009) 3. S.B. Samavedam, J. Ryckaert, E. Beyne, K. Ronse, N. Horiguchi, Z. Tokei, I. Radu, M.G. Bardon, M.H. Na, A. Spessot, S. Biesemans, Future logic scaling towards atomic channels and deconstructed chips, in IEDM, (IEEE, San Francisco, 2020), pp. 1–10 4. A.K. Gundu, V. Kursun, 5-nm GAA transistor technology with 3-D stacked nanosheets. IEEE Trans. Electron Dev. 69(3), 922 (2022)

Location and Environmental Impact Assessment of IC Production Lines

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Contents Guidelines for Selecting Locations for IC Production Plants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Evaluation of Air . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Evaluation of Surface Water . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Evaluation of Ground Water . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Evaluation of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Evaluation of Soil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environment Risk Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Assessment Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analysis of Contamination in IC Production Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contaminant and Treatment in IC Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

It is a complex process to properly assess the location and environmental impact for the construction of an IC production line. The construction project should be carefully planned under the guidelines of overall planning and regulations. This chapter introduces all major factors of environment impact, including air, surface water, ground water, noise, and soil. Then the environment impact can be assessed by the four steps to identify impact factors, determine pollution factors, set control requirements, and finally select specific indicators for testing and evaluation. This chapter also lists common contaminants in mainstream IC production processes with the control measurement for reference. Keywords

Location selection · Environment assessment · Impact factors · Control requirements · Contaminants T. Hsu (*) SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_27

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The IC production lines with various equipment for manufacturing have significant impacts on the surrounding environment. When selecting suitable locations for the construction of IC production lines (or plants), many aspects shall be carefully considered (e.g., the local environment, energy, city planning, etc.). There are large volume of various chemicals, water, and gases used in IC manufacturing as well as large amount of wastewater, gas, and solid waste produced. Therefore, it is important to perform a thorough assessment of environmental impact before starting a new project of IC production line.

Guidelines for Selecting Locations for IC Production Plants According to “the Law of the People’s Republic of China on Urban and Rural Planning,” the location of an IC production plant shall meet the development and construction requirements of new urban areas with reasonable construction scale and schedule. Municipal infrastructure and public service facilities shall be fully utilized for not only strictly protecting natural resources and the ecological environment but also displaying local characteristic features. According to “the Regulations on Site Selection Planning and Management of Construction Projects” publicized by the State Planning Commission on August 23, 1991, the main basis for site selection of construction projects are: (1) project proposals approval; (2) coordination between construction projects and urban planning layout; (3) connection and coordination between construction projects and urban transportation, communications, energy, municipal administrations, and disaster prevention planning; (4) connection and coordination between supporting living facilities and urban living and public facilities planning; and (5) potential pollution impact on urban environment, and the coordination with the urban planning on environmental protection, including scenic spots, cultural relics, and historic sites. Relevant guidelines and key points of selecting locations for IC production lines are shown in Table 27.1.

Environmental Evaluation of Air The environmental impact assessment of air predicts and evaluates the overall air quality if the exhaust gas pollutants are discharged from the plant during construction and after in long-term operation. This assessment includes the investigation and evaluation of the present air quality, demonstrates the feasibility of project construction, proposes a location for the sewage outlet, formulates the production management rules, and establishes the prevention and control measures for atmospheric pollution. The permission to discharge pollutants from fixed sources can provide a basis for meeting the required environmental air quality standards. The investigation and evaluation of the present ambient air are based on the temporal

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Table 27.1 Guidelines and key points in selecting locations for IC production lines Item Environmental impact Energy and resource supply

Hazardous chemical supply and waste disposal

Pollution

Environmental hazards

Facility layout

Preexisting environmental risks

Key points Comprehensively consider two aspects: the impact of the project on the neighboring and overall environment. Ultrapurify water (UPW) is widely used in IC manufacturing, which requires a comprehensive and in-depth analysis of the water supply capacity and strategic location on the project site. In water- or electricity-deficient areas, the feasibility of local energy supply should be comprehensively and thoroughly analyzed. A large volume of hazardous chemicals are used in IC manufacturing and a large volume of hazardous wastes are also produced. Transportation and storage should be fully considered, especially the safety protection measures and safety distance of flammable, explosive, toxic, and harmful hazardous chemicals For IC projects where wastewater is directly discharged into urban or park wastewater treatment plants, feasibility of the treatment process, treatment capacity, and acceptance of the project’s drainage water quality and quantity should be considered. For projects where wastewater is directly discharged into surface water, specific measures are needed to ensure not increasing the load on the surrounding environment. In addition, consider whether the local air pollution concentration, noise level, and protection distance are up to local standards, verify the living conditions of residents within the protection distance, and implement company-wide environmental safety protection measures and environmental protection relocation programs Strict special emission limits for air pollutants have been implemented in key areas under environmental control in China, and the most feasible and efficient pollution control technologies are required for construction projects in order to achieve stricter emission levels of pollutants. Vibration effects on large-scale mechanical processing enterprises, metro and other rail transit, corrosive gases in large-scale metallurgical and chemical enterprises, etc., as they all pose potential risks on the operation of an IC manufacturing line. Safe distance of exhaust gas emission from IC production line, location and layout of CUB, environmental risks of chemical depot within the facility, etc. The investigation and evaluation on the environmental risks of potential sites should include soil and groundwater properties. Investigation and monitoring of soil environmental quality should include at least two basic items: pH value and cation exchange capacity. Nonmethane hydrocarbon (NMHC) and characteristic pollution factors of toxic and harmful volatile organic compounds, such as benzene, toluene, and xylene, should be considered in the environmental air quality survey and monitoring

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and spatial variation and distribution of the background value, while the impact assessment is based on the temporal and spatial variation and distribution of the concentration value superimposed with the background value and the maximum predicted value of pollutants discharged from construction projects. The industry standard “Technical Guidelines for Environmental Impact Assessment, Atmospheric Environment” (HJ 22—2008) specifies the work grades, content, working procedures, methods, and requirements of the atmospheric environmental impact assessment as summarized below: 1. Confirm the criteria and scope of evaluation: According to HJ 22—2008, there are three work grades for the assessment of atmospheric environmental impact as shown in Table 27.2. The criterion for determining the work grade is to select 1–3 main pollutants and calculate the maximum ground mass concentration of each pollutant as “Pi,” where i is the number of the selected pollutant. If the number of pollutants is greater than one, choose the maximum P value (Pmax) and its corresponding value of D10% (i.e., the furthest distance where the ground mass concentration of pollutants reaches 10% of the standard limit). When there are more than two pollution sources discharging the same pollutant in the same project, the evaluation grade of each pollution source is determined separately, and the highest one is taken as the evaluation grade of the project. The calculation of Pi is as the following: Pi ¼

Ci  100% C0i

where Pi is the largest ground mass concentration of the “No i” pollutant (%); Ci is the largest ground mass concentration of the “No i” pollutant (mg/m3) calculated by the model; and C0i is the environmental air mass concentration standard of the “No i” pollutant (mg/m3). 2. Investigation and evaluation of environmental air quality: In order to understand the ongoing status of pollutants discharged by construction projects, it is necessary to investigate, monitor, and evaluate the preexisting and continuing status of the air quality in the region where the construction projects are located. HJ 22–2008 requires that the conventional pollutants and characteristic pollutants (harmful and toxic substances) discharged from construction projects be screened as monitoring parameters, e.g., nitrogen oxides (NOx), sulfuric acid mist, fluoride, hydrogen chloride, chlorine (Cl), ammonia, nonmethane total hydrocarbons, benzene, toluene, xylene, and so on. Generally, in the third grade Table 27.2 The criteria of evaluation level Work Grade Grade I Grade II Grade III

Criteria Pmin  80%, & D10%  5 km Others Pmax < 10% or D10% < the nearest distance between pollutants source and plant boundary

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of assessment, there are 2–4 key points of evaluation, including the maximum wind conditions in the dominant wind direction, the maximum ground concentration of downwind emissions, the downwind ambient air sensitivity, and the cross-wind ambient air sensitivity. If environmental air monitoring data of at least 3 years are available and can meet the requirements of the impact assessment of the project, the preexisting status assessment may not be necessary. According to the results of the monitoring data, the single parameter pollution index method is used to evaluate the present situation of environmental air quality in the area of evaluation. When the pollution index Pi > 1, it shows that the evaluation parameter in ambient air exceeds the standard pollution index (Pi). The formula is as follows: Pi ¼

Ci Si

where Pi is the single factor pollution index of the “No i” pollutant; Ci is the measured average mass concentration of the “No i” pollutant (mg/m3); Si is the evaluation standard of the “No i” pollutant (mg/m3). With the calculated Pi, the pollution level and variation trend as well as the existing environmental issues and their causes can be analyzed for the area. 3. Impact prediction and evaluation: The atmospheric environmental impact assessment shall be based on the corresponding evaluation parameters and criteria (or target values). The work of impact prediction and evaluation mainly includes the following five aspects. (1) collection, processing, and analysis of meteorological observation data; (2) prediction of surface mass concentration, including determination of prediction parameters, collection of surface meteorological data, collection of high-altitude meteorological data, collection of topographic data, determination of prediction models, preprocessing of forecast meteorological data, and preprocessing of forecast points; (3) forecasting pollution source magnitude and frequency, including various scenario combinations; (4) prediction results analysis, including maximum contribution values and impact assessment (hourly and daily average concentration) under normal conditions, contribution values and impact assessment at environmental sensitive areas under normal conditions, and prediction of abnormal emission from projects; and (5) protection distance calculation of irregular emission. In summary, on the basis of the forecasting results and evaluation of pollutant emission, the feasibility of the proposed project is concluded and further suggestions for improvement are proposed.

Environmental Evaluation of Surface Water In order to understand how the surface water quality is influenced by water pollutant discharge from construction projects, it is necessary to investigate the present condition and existing monitoring data; and if the data is insufficient, then additional on-site sampling and monitoring is needed. The selection of water

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quality parameters mainly includes water temperature, pH value, dissolved oxygen (DO), chemical oxygen demand (COD), and suspended solids (SS), such as ammonia nitrogen, total nitrogen, fluoride, cyanide, anionic surfactant (sodium alkylbenzene sulfonate), petroleum, total phosphorus, arsenic, chromium (hexavalent), copper, silver, nickel, tin, lead, zinc, manganese, etc. The standard index method of single water quality is used to evaluate the present condition of surface water quality. 1. The standard index method for general water quality parameters is: Si,j ¼

ci,j cSi

where Si,j is a unitized water quality parameter “i” at “j” sampling point; Ci,j is the average measured concentration of water quality for parameter “i” at “j” sampling point (mg/L); CSi is the evaluation standard of water quality parameter “i” (mg/L). 2. Standard index formula for calculating pH value, pHO7:0,

7:0  pHj 7:0  pHsd pHj  7:0 ¼ pHsu  7:0

SpH,j ¼

pH > 7:0, SpH,j

In the formulas, pHj is the measured value of pH at “j” sampling point; pHsd is the lower limit of the evaluation standard of pH value; and pHsu is the upper limit of the evaluation standard of pH value. 3. The standard index formula for Do is: DOj PDOs , DOj < DOs ,

jDOf  DOjj DOf  DOs DOj SDO, j ¼ 10  9 DOs 468 DOf ¼ ð31:6 þ T Þ

SDO, j ¼

where DOf is saturated dissolved oxygen concentration (mg/L); DOs is the standard concentration of dissolved oxygen (mg/L); DOj is the dissolved oxygen concentration (mg/L) at “j” sampling point; and T is the water temperature ( C). When the standard index of single water quality is greater than 1, it shows that the water quality parameter is outside the bounds of the water quality standard; then the specific items or multiples outside the standard shall be explained. The requirements of surface water quality assessment scope, investigation period,

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sampling section, location, collection and treatment, water sample preservation and analysis method, as well as evaluation criteria and content requirements are all specified in the Technical Guidelines for Environmental Impact Assessment (HJ/T23–93).

Environmental Evaluation of Ground Water In order to understand the ongoing conditions of ground water (or groundwater) environment at the site of the project, it is necessary to collect monitoring data of the groundwater environment. Monitoring parameters include groundwater level, pH value, total hardness, permanganate index, ammonia nitrogen, nitrate nitrogen, nitrite nitrogen, sulfate, total phosphorus, chloride, fluoride, cyanide, arsenic, iron, copper, zinc, lead, chromium (hexavalent), manganese, silver, tin, nickel, total coliform bacteria, total bacterial count, etc. According to the statistics of monitoring data, the single component evaluation method can be used to evaluate the water quality according to the prescribed water quality classification standards, or the standard index method can be used to evaluate the water quality. The former explains the category of groundwater quality standard (GB/T 14848—2017) which belongs to the evaluation component. The latter adopts the standard index method. Select whichever method is the best for the specific situation. (1) The standard exponential expressions for general water quality components are: Si, j ¼

ci, j cSi

where Si,j is the standard index of water quality component “i” at “j” point; ci,j is the average measured concentration of water quality component “i” at “j” point (mg/L); cSi is the evaluation standard of water quality component i (mg/L). (2) The standard index formula for calculating pH value is as follows: 7:0  pHj 7:0  pHsd pH j  7:0 ¼ pHsu  7:0

pHO7:0,

SpH, j ¼

pH > 7:0,

SpH, j

where pHj is the measured value of pH at “j” sampling point; pHsd is the lower limit of the evaluation standard of pH value; and pHsu is the upper limit of the evaluation standard of pH value. When the index of individual evaluation criteria is greater than 1, the water quality component is not within the bounds of the prescribed water quality standards.

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The standard index method of groundwater quality evaluation generally adopts the third class standard of “Groundwater Quality Standard” (GB/T 14848—2017). The scope of groundwater quality evaluation, the location of groundwater, the sampling of water quality, the frequency of monitoring, the requirements of determination methods, the evaluation criteria, and the requirements of evaluation contents are all specified in the Technical Guidelines for Environmental Impact Assessment (HJ610—2016).

Environmental Evaluation of Noise In order to understand the acoustical environment quality at the project site (or plant boundary) and sensitive areas, it is necessary to monitor the ongoing acoustical environment status. According to the category of acoustic environment functional areas within the evaluation scope and according to the “Acoustic Environment Quality Standard” (GB 3096—2008), the method of meeting the standards of monitoring points is evaluated. If the data are outside the bounds of the standard, the number and distribution of data population shall be explained, and the reasons shall be analyzed. Environmental noise monitoring method is specified in “the Standard for Acoustic Environmental Quality” (GB 3096—2008). Requirements for monitoring sites, assessment scope, and evaluation contents are specified in “Technical Guidelines for Environmental Impact Assessment” (HJ 24—2009). There are many noise sources in the IC production lines, including chillers, fans, pumps, cooling towers, and other power equipment. Based on the analysis of the main noise sources of the proposed project, the noise level and its impact on the surrounding environment during the production and long-term operation are predicted, analyzed, and evaluated. For new projects, the contribution value of specified engineering noise is assumed for the evaluation quantity, and the contribution value of factory boundary noise is calculated by noise distance attenuation estimates according to the relevant parameters of project noise source and noise reduction measures. (1) Distance attenuation mode of point source: LA ðr Þ ¼ LA ðr 0 Þ  20lgðr=r 0 Þ where r0、r is the distance (m) between the reference position and the predicted point; LA (r) is the A sound level (dB) at the distance point source “r”; and LA(r0) is the A sound level (dB) at the distance point source “r0.” (2) Multisource overlay mode: LP ¼ 10lg

k i¼1

100:1LPi

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where k is the number of noise sources, LP is a synthetic sound level (dB (A) with k attenuation values of noise sources, and LPi is the attenuation value of the distance of the noise of the first noise source (dB(A)). According to the predicted results, it is judged whether the noise at the factory boundary can meet the requirements in the “Environmental Noise Emission Standard for Industrial Enterprises” (G 12348 – 2008). If the acoustical environmental sensitive points are distributed in the evaluation range, the corresponding environmental requirements in the “Acoustic Environmental Quality Standard” (GB 3096— 2008) can be judged by superimposing the monitoring values of the acoustical environment status.

Environmental Evaluation of Soil The main object of soil environmental assessment is the soil quality at the construction site. In order to understand the preexisting status of soil quality at the site, it is necessary to collect monitoring data of soil status or perform spot sampling and monitoring. The monitoring includes the soil characteristics, the pollutants from the proposed construction project, and the pollutants concerned by the local public and environmental protection departments. Among them, moisture content, cation exchange capacity, and pH values are the basic items to be measured. Additional key control materials are also included: cadmium, chromium, mercury, lead, copper, zinc, nickel, hexachlorocyclohexane (666), and DDT (di-p-chlorophenyl trichloroethane). Sampling sites, sample collection, preparation, determination, data processing, quality assurance, and quality control are performed in accordance with the “Technical Specification for Soil Environmental Monitoring” (HJ/T 166—2004). The environmental soil quality assessment method is the same as groundwater quality assessment method. According to the statistics of monitoring data, single component assessment method can be used to evaluate soil quality according to classification criteria, or single pollution index and cumulative index methods can be used to evaluate soil quality. The category of “soil environmental quality standard” (GB 15618 – 1995) belonged to this component was explained by the single component evaluation method. Choose the method best fitting the specifics of the project and environment. The calculation formulas of single pollution index and cumulative index methods are as follows: (1) individual pollution index of soil pollutants denotes the measured values of soil pollutants/quality standard of soil pollutants and (2) individual cumulative index of soil pollutants denotes the measured values of soil pollutants/background values of pollutants. According to the evaluation results, if there is no index outside the boundary of the standard, it can be considered that the risk to human health of that evaluation index is acceptable, and it can be preserved as historical data of the background value at the construction site. If the soil at the construction site is polluted, the excessive pollutants will be identified, and the risk assessment of the soil pollution will be initiated.

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Environment Risk Assessment Project environmental risk assessment assesses the impact and damage to personal safety and environment caused by predictable emergencies or accidents (generally excluding man-made damage and natural disasters). These emergencies may cause toxic, harmful, flammable, and explosive substances to leak, or new toxic and harmful substances produced by emergencies during the construction and operation of the project. The risk assessment will also put forward emergency prevention and mitigation measures [1]. The purpose is to analyze and predict the potential risks of construction projects. A variety of special gases and chemicals are needed in the production of ICs. Special gases can be divided into inert, corrosive, flammable/harmful, and alkanes. Chemicals mainly include etching solutions, photoresist, degumming agent, developer and other mixed solutions, as well as hydrofluoric acid, nitric acid, hydrochloric acid, sulfuric acid, and so on. These chemicals have certain environmental risks in transportation, storage, and use. According to the “Technical Guidelines for Environmental Risk Assessment of Construction Projects” (HJ/T 169 – 2004), the working level of environmental risk assessment is divided into two levels, as shown in Table 27.3. Risk source analysis includes maximum credible accident analysis, probability investigation of maximum credible accident risk, and determination of major accident source strength. According to the “Technical Guidelines for Environmental Risk Assessment of Construction Projects” (HJ/T 169—2004), the abnormal model is adopted to simulate and evaluate the leakage of major accident sources under the condition of assumed serious and catastrophic accidents. Meanwhile, engineering control measures, risk management measures, and accident emergency plans are formulated. The flow chart of environmental risk assessment is shown in Fig. 27.1.

Environmental Assessment Factors The assesment of environmental impact should firstly identify the environmental impact factors (or parameters), determine the pollution factors, and put forward control requirements through the analysis of process flow and pollution production Table 27.3 Evaluation level (Level 1 and 2)

Major hazards Nonmajor hazard sources Environmental sensitive areas

Highly toxic and dangerous substances Level 1 Level 2

General toxic hazardous substances Level 2 Level 2

Flammable and flammable hazardous substances Level 1 Level 2

Explosive hazardous substances Level 1 Level 2

Level 1

Level 1

Level 1

Level 1

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Fig. 27.1 Flow chart of environmental risk assessment [1]

links, and finally select the factors for environmental impact to be tested and evaluated for the project. 1) Identification of environmental impact factors: According to the “Guidelines for Requirements and Use of Environmental Management Systems” (GB/T 2401 – 2016), environmental factors refer to the elements that interact with the environment in an organization’s activities, products, and services. According to the action attributes of the proposed project on environmental factors, environmental impacts can be divided into favorable and unfavorable, long-term and short-term, reversible and irreversible, direct and indirect, as well as cumulative and noncumulative impacts. In environmental assessment, it is usually classified according to the different acceptors in the categories of atmospheric and water discharge, soil pollution, the use of raw materials, waste materials disposal, and management. The main environmental impact factors of the construction project during the construction period are construction dust, noise, and waste. The main environmental impact factors after the construction period and in normal

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Table 27.4 Identification table of major factors of environmental impact in the operation period of IC production lines [1] Environmental elements Atmosphere Surface water Ground water Soil Acoustic environment Environmental risk

Pollution factors Waste Waste gas water ● ● ● ● ●

Noise

Solid waste ● ● ●

Hazardous chemicals Storage ● ● ● ●

Hazardous waste ● ● ● ●

●

●

●

● ●

●

operation are hazardous waste materials and chemicals. The main environmental impact factors during the operation period are shown in Table 27.4. 2) Pollution factors: The possible pollution factors (or parameters) are identified and determined through the analysis of process flow and pollution production links. Generally speaking, there are several kinds of pollution factors in the IC industry. (a) Water pollutant control parameters: total 20 items including pH, suspended solids (SS), chemical oxygen demand (COD), ammonia nitrogen, total nitrogen, fluoride, total cyanide, anionic surfactant (LAS), petroleum, total phosphorus, total arsenic, hexavalent chromium, total chromium, total copper, total silver, total nickel, total tin, total lead, total zinc, total manganese, etc. Among them, the monitoring positions of total arsenic, hexavalent chromium, total chromium, total lead, and total silver should be set at the outlet of the pollutant pretreatment unit device. The monitoring location of other substances is set at the total effluent outlet of the plant area. (b) Air pollutant control parameters: total 12 items, including hydrogen fluoride, hydrogen chloride, sulfuric acid mist, nitrogen oxides, ammonia, chlorine, benzene, toluene, xylene, volatile organic compounds (VOCs), tin and tin compounds, as well as lead and lead compounds. Ammonia emission is implemented under “Odor Pollutant Discharge Standards” (GB 14554 – 1993, while other control parameters shall implement the “Comprehensive Emission Standards for Atmospheric Pollutants” (GB16297 – 1996). (c) Special toxicity exhaust gas control parameters: It is necessary to install point treatment systems and control linkage systems on process equipment with special toxic tail gas discharge and acidic or alkaline waste gas treatment systems for further treatment and discharge. The main control parameters are HF, HCl, Cl2, etc. 3) Screening of environmental impact assessment factors: The screening of factors of environmental impact assessment is based on the main pollution factors of construction project emissions, combined with the environmental function requirements of the construction project location or the determined

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Table 27.5 Reference table for selecting factors for environmental impact assessment of IC production line construction project [2] Environmental factors Atmospheric environment Surface water

Acoustic environment Ground water

Soil

Evaluation factors HF, HCl, H2SO4 (Fog), NOx, NH3, Cl2, benzene, toluene, xylene, VOCs (total carbon), tin and tin compounds, lead and lead compounds, etc. pH, SS, COD, ammonia nitrogen, total nitrogen, fluoride, total cyanide, anionic surfactant (LAS), petroleum category, total phosphorus, total arsenic, hexavalent chromium, total chromium, total copper, total silver, total nickel, total tin, total lead, total zinc, total manganese, etc. Boundary (factory boundary, field boundary) noise, sensitive target noise pH, total hardness, permanganate index, sulfate, ammonia nitrogen, nitrate, nitrite, chloride, fluoride, cyanide, arsenic, hexavalent chromium, lead, silver, nickel, tin, copper, iron, zinc, manganese, total coliform bacteria, total bacteria, etc. Arsenic, copper, lead, chromium, nickel, zinc and fluoride, etc.

environmental protection objectives. The selected assessment factors should be able to reflect the main characteristics of environmental impact, the basic situation of regional environment, the characteristics of construction projects, and the characteristics of sewage discharge. Generally speaking, the environmental impact assessment factors of IC production line construction projects are shown in Table 27.5.

Analysis of Contamination in IC Production Line There are various chemicals and gases used in the IC manufacturing. The chemicals and gases commonly used in the main processing processes are listed in Table 27.6. At the end of manufacturing process, most of these chemicals and gases will be discharged into waste water or exhaust gas, except a small amount of chemicals or physical reactions deposited on the wafer. According to the Handbook of Industrial Pollution Source Production and Discharge Coefficient for the First National Pollution Source Census (revised in 2010), the contents of relevant parts of IC industry are listed in Table 27.7.

Contaminant and Treatment in IC Production Lines IC products may have many production links, long process flows, many pollutant discharge points, and complex pollutant components. The main types of waste gases are toxic tail gases, acidic exhaust gases, alkaline exhaust gases, organic exhaust gases, and soldering tin fumes. The main types of wastewater are ammonia-

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Table 27.6 Common chemicals and gases in IC production lines Production process Wet clean Oxidation Gluing Development Wet degumming Wet etch Dry etch Diffusion doping Implant CVD PVD Copper process CMP Dielectric CMP Metal CMP Back thinning Testing

Chemicals and gases HF/H2SO4/HNO3/HCl/NH3/H2O2/IPA/acetone/ethanol, etc. O2/TEOS HMDS/PGMEA/PGME/2-EFA/EGMEA/MMP/DMAC/Methyl amyl ketone/MEK/N-butyl acetate/xylene, etc. TMAH/TEAH/Cyclohexanone, cyclopentanone, butanone, Xylene, potassium hydroxide, etc. Hydroquinone/SPM/NaOH/Acetone/IPA/EG/DMSO/MEA/NMP/BDG/ DGA/diethyl- lenediol amine/DMAC/HAD, etc. HF—NH4F/CH3COOH—NH4F/HF—HNO3—CH3COOH/H3PO4/ HNO3—H3PO4—CH3— COOH/H3PO4—HNO3—H2SO4—HF, etc. CF4/C2F6/C3F8/CHF3/CH2F2/BF3/SF6/BCl3/NF3/HF/HCl/HBr/Cl2/NO/ CHCl3/CCl2F2/O2/H2/CO2, etc. AsH3/B2H6/PH3/BBr3/BCl3/BF3/POCl3, etc. BF3/B2H6/AsH3/PH3/H2, etc. SiH4/SiH2Cl2/SiCl3/BF3/SiCl4/CF4/PH3/NO/N2O/NH3/HF/WF6/HCl/H2, etc. SiH4/SiHCl3/SiH2Cl2/SiCl4/BCl3/TiCl4/WF6/TiF4/BF3/SF6/HF/HCl/HBr, Ti/W/Mo/Cr/Pt/Ta/Co Cu/CuSo4/H2So4/HCl/H2O4, etc. Silica Polishing Agent-KOH/TMAH/NH3.H2O/C2H7NO, etc. Al2O3-CeO2-MnO-H2O2/Fe(NO3)3/C6H8O7/HF, etc. Silicon carbide grinding Silver glue/copper glue/solder paste (tin alloy + flux)/epoxy resin/N-methyl pyrrolidone (NMP)/dimethylfuran (DMF)/bump metal materials (gold/tin/ titanium/chromium/nic- kel/tungsten/molybdenum/etc.)/electroplating bath (gold/silver/tin/etc.)/CH4O3S/surfactant/HNO3/H2SO4/HCl/NaOH/IPA/ CH3COCH3, etc.

containing wastewater, fluorine-containing wastewater, grinding and scrubbing wastewater, chemical polishing wastewater, copper-containing wastewater, and heavy gold. These belong to wastewater, organic wastewater, acid and alkali wastewater, etc. Main pollutants and their sources in IC production lines are shown in Table 27.8. Referring to the “Design Code for Sewage Treatment and Reuse in Chemical Industry” (GB 50684—2011), typical pollution control measures for IC production lines are shown in Table 27.9. IC or semiconductor manufacturing needs to deal with contamination monitoring and analysis, further reading can be found [3].

Integrated circuit chip (200 mm) (Wafers above)

Silicon wafer, photoresist, etching solution

Product Raw material Integrated circuit chip Silicon wafer, (200 mm) Wafers above) photoresist, etching solution

Integrated Circuit Chip Manufacturing

200 K fluoride

NOx

Industrial exhaust gas volume SO2

total nitrogen

NH3-N

Pollutant Process name Scale indicators Integrated circuit 200 K Industrial chip manufacturing wastewater volume COD

Table 27.7 Table of emission and discharge coefficient for IC manufacturing industry

725

475

g/pieceproduct g/pieceproduct

19

12650

90

90

430

Absorption Direct combustion or catalytic reduction Absorption Direct combustion or catalytic reduction Absorption Direct combustion or catalytic reduction

Neutralization + chemical precipitation Neutralization + chemical precipitation Neutralization + chemical precipitation Absorption + adsorption method

(continued)

18 162

95 855

025 0225

12650

325

325

135

Pollution Terminal governance Emission coefficient technology coefficient 345 Neutralization + 345 chemical precipitation

g/pieceproduct

g/pieceproduct g/pieceproduct g/pieceproduct m3/pieceproduct

Unit t/pieceproduct

27 Location and Environmental Impact Assessment of IC Production Lines 579

Silicon wafer, photoresist, etching solution

Integrated circuit chip (200 mm) (Wafers above)

Scale

HCl

Pollutant indicators H2SO4(fog)

HW34 hazardous waste waste acid Integrated circuit 200 K HW35 chip manufacturing hazardous waste (Alkali waste) HW42 hazardous waste (waste organic solvents)

Process name

–

–

–

– kg/piece- 145 product

–

115 1035

Emission coefficient 58 522

kg/piece- 045 product

Pollution Terminal governance coefficient technology 35 Absorption Direct combustion or catalytic reduction g/piece- 100 Absorption product Direct combustion or catalytic reduction kg/piece- 17 – product

Unit g/pieceproduct

Note: The coefficient of discharge and production of 200 mm wafers is shown in the table. If the disc is 300 mm, the output and discharge coefficient of the discharged disc is equal to the output and discharge coefficient multiplied by 12 in the table. If the wafer is 200 mm or more regardless of specifications, the output and discharge coefficient of the wafer is equal to the output and discharge coefficient of the wafer in the table

Raw material

Product

Table 27.7 (continued)

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Table 27.8 Main pollutants in IC production lines and their main sources Pollution source Waste NH3-N water F

Waste water

CMP

CMP Cu solvent Heavy metal

Acid-base wastewater

Waste gas

toxicity

SEX

AEX VEX Solder fume

Major pollutants Alkali, suspended solids, ammonia nitrogen, total nitrogen, and fluoride Acid, alkali, suspension, ammonia nitrogen, total nitrogen, fluoride, total phosphorus Alkali, suspended solids, ammonia nitrogen, total nitrogen, and copper Alkali, suspended solids, and copper Acids, suspended solids, and copper Acid, alkali, suspended matter, organic matter Acid, alkali, suspension, copper, zinc, silver, tin, lead, chromium, cyanide, total phosphorus, total nitrogen, fluoride Acid, alkali, suspended matter, COD-Cr, NH3-N, total nitrogen, petroleum, and anionic surfactant (LAS) Arsene, phosphane, borane, silane, silicon tetrachloride, dichlorodihydrosilane, boron trichloride, boron trifluoride, nitrogen trifluoride, carbon tetrafluoride, ammonia, hydrogen chloride, chlorine, hydrogen bromide, and hydrogen fluoride Hydrogen fluoride, hydrogen chloride, nitrogen oxides, sulfuric acid mist, and chlorine ammonia VOCs (Benzene, toluene, xylene, isopropanol, acetone, etc.) Tin and lead

Major sources ETCH、CMP、AEX

ETCH, SEX (include POU)

CMP

Back thinning and chip cutting ECD,CMP, TAB packaging technology development and degumming Metallized film etching, packaging pin electricity lating, bump plating, and etching Degumming, etching, ultrapure water station, washing tower, package flux cleaning, equipment maintenance, etc. Oxidation, dry etching, diffusion, chemical vapor deposition, and ion implantation

Degumming, etching, copper deposition, POU tail gas, packaging, and electroplating Etch, CMP Coating, degumming, etching, cleaning, and sealing Bumping and packaging

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Table 27.9 Typical pollution control measures for IC production lines Pollution source Waste NH3-N water F CMP

CMP Cu solvent heavy metal

Waste gas

Acid-base wastewater toxicity

SEX AEX VEX

Solder fume

Governance measures Steam (hot air) stripping + acid absorption, sodium hypochlorite oxidation, etc. Flocculation sedimentation method The effluent is fed into the neutralization pond and the final discharge is up to the standard allowable volume. The effluent is fed into the treatment system of ammonia-containing wastewater or fluorine-containing wastewater Filtration, coagulation, and sedimentation Biochemical treatment and chemical oxidation Ion exchange resin treatment, electrolytic precipitation + ion exchange resin treatment, chemical flocculation precipitation, etc. Ion exchange resin treatment, electrolytic precipitation + ion exchange resin treatment, chemical flocculation precipitation, etc. Acid-base neutralization treatment POU+central scrubbing tower. POU devices include combustion + washing devices, countercurrent water elution/plasma-water removal system, electrothermal oxidation/catalytic decomposition, three-stage water washing, adsorption, high-temperature pyrolysisactivated carbon adsorption washing Acid spray absorption method Alkali spray absorption method Water spray absorption + activated carbon adsorption, activated carbon adsorption, Catalytic combustion, zeolite runner concentration combustion and storage, thermal incineration (RTO), regenerative catalytic combustion (RCO), condensation, absorption, etc. Alkali spray absorption method, activated carbon fixed bed adsorption method, high-density fiber filter (HEPA) +activated carbon absorber (filter), and so on

References 1. State Environmental Protection, Administration Technical Guidelines for Environmental Risk Assessment of Construction Projects: HJ/T169–2004 [5] (China Environmental Science Press, Beijing, 2005) 2. Environmental Engineering Evaluation Center of the Ministry of Environmental Protection, Environmental Impact Assessment of Metallurgical Machinery and Electricity (Environmental Science Publishing in China, Beijing, 2012) 3. J.-L. Baltzinger, Bruno delahaye, contamination monitoring and analysis in semiconductor manufacturing, in Semiconductor Technologies, (2010). https://doi.org/10.5772/8561

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Contents Technology Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Investment and Expenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buildings and Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Green Plant Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automated Material Handling Systems (AMHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Water Supply and Drainage Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fire Safety System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ultrapure Water System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wastewater Treatment System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Facility Monitoring and Control Systems (FMCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hook-Up System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

584 585 586 587 588 589 589 592 594 596 598 599 601

Abstract

The key component in designing the IC production line is the manufacturing equipment which is 70–80% of overall project investment. Meanwhile, the required manufacturing equipment can vary significantly based on different product categories and technologies. This chapter provides an overview of essential aspects of designing a well-functional IC production line. It includes main buildings and structures, green plant design concept, green building evaluation and certification system, automated material handling system (AMHS), water supply and drainage system, well-equipped and effective fire-fighting systems, power systems, ultra-pure water system, wastewater treatment systems for five different chemical-based wastewaters, facility monitoring and control system (FMCS) for real-time status, and also the hook-up system connecting manufacturing equipment with all required conditions. T. C. Wang (*) SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_28

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Keywords

Manufacturing equipment · Green buildings · Automated material handling system · Water supply · Fire-fighting system · Power supply · Ultrapure water system · Waste-water treatment system · Facility monitoring and control system · Hook-up system

Technology Considerations ICs can be classified into 2 main categories, that is, digital ICs and analog ICs. Different IC products are designed and manufactured by different technologies; if using line-width as a parameter, technology can be from the early 5 um node to the latest under 7 nm process nodes; if using wafer substrate size as a measure, technologies are mainly in 150 mm, 200 mm, 300 mm generations, and 450 mm generations in the future. The investment amounts of a production line can be easily from tens of millions up to billions of dollars with clean rooms of various sizes from hundreds of square meters to several tens of thousands of square meters; therefore, the selection of a suitable manufacturing process and equipment set is a key fab design task. The design of production lines should be based on product types and combination of products, maximum monthly capability, production cycles, investment capitals, and long-term development goals to decide processes and corresponding equipment sets. Regarding the production nodes at line-width of 0.13 μm and larger, they are mainly in 150 mm and 200 mm fabs; while for line-width 90 nm and under, it is mainly in 300 mm fabs. The processes of producing IC chips is very complicated, it includes over 1000 steps, generally it can be divided into front-end and back-end processes. The front-end-of-line (FEOL) process is used to form the active and passive elements, including cleaning, thin film, photolithography, etching, ion implantation, etc. The back-end-of-line (BEOL) process is used to interconnect IC elements and form protection layers, including photolithography, etching, cleaning, metallization, chemical mechanical polishing (CMP), etc. The mixing of the BEOL and FEOL equipment shall be avoided to prevent metal contaminating and degrading electric characteristics. Regarding production lines with 100 mm and 150 mm wafer sizes, generally open style fab is adopted. As the dust and air quality in the operating area affects device characteristics and yields, the requirement of air cleanness is higher; thus the operating area is normally separated from the equipment areas by wall panels. Further, the use of SMIF (standard mechanical interface) boxes as clean micro environment for device wafers is the main stream in 200 mm and 300 mm wafer fabs. In early days, 200 mm wafer fabs were mainly manually operating the wafer transportation, storage, and distribution; modern 200 mm and 300 mm wafer fabs use automated material handling system (AMHS) [1] with merits of effective use of clean space, lowering handling work for operators, and reducing human errors. In some of the 300 mm wafer fabs, the wafer transfer system can be extended to

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different production areas by utilizing the overhead hoist transfer (OHT) and deliver wafers to equipment side directly. Future AMHS system can further improve production speed, cycle time, and responses to fab needs. As the IC production technology develops further, the corresponding packaging technologies also accelerated. Packaging not only provides interconnection of the IC chips, but also provides mechanical and protection to the chips for normal operation with stability and reliability. Before the 1980s, the most popular packages were the drop-in-hole insertion with TO and dual-in-line package (DIP) with process steps of sort testing, wafer thinning, dicing, die attachment, cleaning, encapsulating, assembly, solder reflow, and final test, etc. Since the 1990s, the ball-grid-array (BGA) packaging and chip-size-package (CSP) were developed rapidly with main types of BGA, CSP, Wafer Level Chip Scale Package (WLCSP), and System in Package (SIP). The main process steps include intermediate testing, thinning, scratching, adhesive, cleaning, plastic sealing, assembly, reflow soldering, marking, testing, packaging, etc. Since the late 1990s, packaging technology progressed to the era of 3D packaging of stacking multiple chips through vertical thru-Si-via (TSV) with advantages of reduced package size and weight and improved signal transmission speed and power. In recent years, 3D packageing technology is maturing rapidly with technology advancement in coating, photolithograph, sputtering, re-coating, electrio-plating, solder reflow, testing, marking, etc.

Investment and Expenses Project investment refers to the total costs to complete and bring the proposed project into operation, including project costs, costs of engineering construction, reserve funds, interest in construction period and liquidity funds. (1) Project costs include purchase and installation fee for production equipment and instruments (e.g., all configuration fee, freight and miscellaneous expenses, installation fee), cost of acquisition and installation of power facilities (e.g., clean room and general electromechanical systems, ultrapure water and wastewater treatment, special gas supply and distribution, chemical supply and distribution, high and low voltage variable power distribution, uninterruptible power supply, emergency diesel power generation system, fire extinguish system, security system, other electromechanical systems, etc.), and construction fee (e.g., cost of building and outdoor works for plant and ancillary facilities). The major portion of the project costs is the process equipment/tools for about 70–80% of the total investment. (2) Other engineering construction cost usually accounts for about 2% ~ 5% of the total investment and includes many items (e.g., land requisition fee, construction unit management fee, upfront consultation fee, environmental evaluation fee, occupational safety pre-evaluation fee, occupational hazard pre-evaluation fee, social stability evaluation fee, energy saving assessment fee, soil and water conservation program fee, radiation protection evaluation fee, trial plan fee, consultation fee, survey and design fee, project supervision fee, investment supervision fee, bidding agency fee, city

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supporting fees, office facilities and training fees, various audit and testing fees, engineering insurance premiums and trial production fees, etc.) (3) The reserve funds usually account for 2% ~ 5% of the total investment and includes the reserve funds for the basic and price increase. The basic reserve funds refer to a design change, no increased costs due to resistance and recovery at the end of excavation and acceptance at the time of acceptance of concealed works, etc. The reserve funds for price increase refer to project cost changes due to the change of prices of labor, materials, construction machinery, etc., during the construction period. (4) Interest in the construction period usually accounts for about 1–2% of the total investment. It refers to the interest occurring during the construction period in the fixed assets (e.g., the payment of bank loans, export credits, bonds and other borrowing interest and financing costs incurred). (5) Liquidity usually accounts for about 2–5% of total investment. It is generally calculated using a sub-detailed estimation method based on the minimum turnaround days for accounts receivable, inventory, cash, and accounts payable. For domestic projects, in accordance with bedding liquidity, foreign and joint venture projects are calculated on the basis of full liquidity.

Buildings and Structures An IC production line (or fab) mainly includes production plant and clean room, power plants, office buildings, substations, raw material warehouses, hazardous chemicals warehouses, bulk gas stations, and silane station, etc., as illustrated in Fig. 28.1. (1) Production plant and clean room mainly layout the process equipment and testing, experimental and other equipment in clean room, but also layout the new

Fig. 28.1 Diagram of building composition of IC production line

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air room, exhaust system, power supply and distribution, ultra-pure water and wastewater treatment, and chemicals and special gas systems. (2) The building floor plane and space layout shall be determined according to the planned manufacturing technologies. As an example, a 300 mm wafer fab for 28 nm node, the maximum production capacity is 35,000 wafers per month with clean room area of about 9000 m2 and building of 3 layers (local 4 layers). The main structure of the plant should adopt a combination of reinforced concrete structure, steel structure or 2 structures with large space and large span column mesh, and should have the performance of seismic, anti-micro vibration, fire prevention, sealing, waterproofing, temperature deformation control, and uneven settlement. (3) Power plants mainly layout those cooling tower system, cold/hot water unit, ultrapure water preparation system, and wastewater treatment system. Because of the large load, the plant structure should adopt reinforced concrete structure. (4) Office buildings are mainly for the fab supporting, R&D, production management, administration, personnel, safety departments, also for café, clinic, parking, and other auxiliary functions. Office buildings are generally designed according to civil building norms and usually connected with a fab and conveniently accessible by employees. (5) Power substations are in an outside configuration and allocated per wafer fab capacity. The inlet line of power supply and distribution systems may use voltage levels of 220 kV, 110 kV, 35 kV, and other voltage levels. (6) Raw material warehouse mainly stores the Class B or C materials and others in production process. Hazardous chemicals warehouse mainly stores class-A dangerous goods materials.

Green Plant Design In China, the concept of green plant design starts from residential and public buildings. The evaluation standard introduces the weight scoring method, which is determined by the score of different provisions according to 8 indexes, for example, land saving and sustainable development site, energy saving and energy utilization, water saving and water resources utilization, use of material and materials resources, outdoor environment and pollutant control [2], indoor environment and occupational health, operation management, technological progress and innovation, etc. The levels of green industrial buildings are “one star” (if score is rated less than 55 points but not less than 10), “2 stars” (if between 55 and 70 points), and “3 stars” (if above 70 points). Green building evaluation system is widely used in the design of green IC fabs based on the Leadership in Energy and Environmental Design (LEED) building Rating System for evaluation. LEED was developed by the United States Green Construction Council and it is mainly based on the sustainability of sites, the use of water resources, energy and atmospheric environment, materials and resources, the quality of indoor environments, and the six indicators of innovative design. More than 30 evaluation sub-keys are subdivided under these indicators. In LEED (V3.0) the regional priority content is the reward score. LEED system for a total of 110 points, according to the total score, there are different levels, for example,

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Table 28.1 LEED distribution of different certification systems Project Sustainable Venues Water Resources Utilization Energy and Atmospheric Environment Use of Materials and Resources Indoor Environmental Quality Innovative Design Regional Priority

LEED-NC points 0 ~ 26 0 ~ 10 0 ~ 35

LEED-CS points 0 ~ 28 0 ~ 10 0 ~ 37

LEED-EB points 0 ~ 26 0 ~ 14 0 ~ 35

LEED-CI points 0 ~ 21 0 ~ 11 0 ~ 37

0 ~ 14 0 ~ 15 0~6 0~4

0 ~ 13 0 ~ 12

0 ~ 10 0 ~ 15

0 ~ 14 0 ~ 17

Certified level (40 ~ 49 points), Silver level (50 ~ 59 points), Gold grade (60 ~ 79 points), and Platinum level (80 ~ 110 points) four levels. The score distribution of LEED certification systems is illustrated in Table 28.1.

Automated Material Handling Systems (AMHS) In conventional wafer fab, the handling of wafers and process materials is performed by using trolleys and human handling. As the wafer size increases from 150 mm to 300 mm, the mass of fully loaded wafer box (Front Opening Unified Pod, FOUP) has increased [3] to about 8.3 kg (somewhat too heavy for manual handling with safety and reliability). Furthermore, the use of automated material handling system (AMHS) [4–6] in the wafer fab becomes a trend with proven advantages in product yields and cleanliness. The AMHS systems include the within process area (intrabay) and process intervals (inter-bay) handling systems. The operation system is also composed of 2 parts. After continuous exploration and optimization, the AMHS systems have developed to be fully automatic. The (intra-bay) handling systems refer to the wafer handling systems between equipment, or between the equipment and storage systems (Stocker) in the same production area (Bay), mainly through the air truck (i.e., overhead hoist transports, OHT) for automatic wafer handling. The process interval (inter-bay) handling systems mainly refer to the wafer handling systems in between different production areas. During the pre-development period of AMHS systems, the intra-bay handling systems are performed by OHT; while the inter-bay process interval handling systems are performed by the air to and from the transport vehicle (i.e., Overhead Shuttles, OHS). The storage systems (stocker) are used for the storage of wafers, but also for the wafer handling within process area and in-between process areas (i.e., as a bridge between the inter-bay and intra-bay systems). The state-of-art AMHS system can perform wafer transport completely by OHT (i.e., tool to tool mode) with the storage system only for storage, together with the newly added storage space in the air (i.e., under track storage, UTS) also providing storage space for wafers in fab. AMHS systems can save manpower, reduce particles, maximize the use of clean room space, ensure efficient operation of

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wafer cassette management, automate production control system, shorten production cycles, and improve capacity utilization of equipment.

Water Supply and Drainage Systems The water supply and drainage system is the general name of the facilities that provide clean water and remove sewage for the need of people’s living as well as for production equipment. It mainly includes water treatment, drainage, rainwater harvesting, and domestic sewage collection and treatment systems. IC production lines also produce wastewater, and their treatment systems are described later (see 10). (1) Water supply systems refer to the overall water intake, conveyance, quality treatment, and distribution facilities. Water supply systems are divided into domestic water supply and production water supply systems. Municipal tap (city) water is used for domestic water supply. The domestic water tanks need to be designed as 2 tanks to ensure the normal water supply during the annual cleaning period. Recycled (or reclaimed) water shall be used as much as possible and gradually replacing the use of city water. (2) Drainage systems refer to the collection, transportation, water quality treatment, and discharge of drainage facilities, mainly including domestic sewage drainage and air condition condensation drainage collection. Domestic sewage mainly includes toilet, laundry room, hand washing, and kitchen drainage. Domestic sewage is discharged into the domestic sewage treatment system. Air conditioning condensate is collected and used as water for production. (3) Rainwater harvesting system refers to the roof and road rainwater collected through rainwater pipelines into rainwater harvesting ponds for storage. After filtration, it can be used for watering as green water. (4) The main treatment objects of domestic sewage collection and treatment system are ammonia nitrogen, phosphorus, biochemical oxygen demand (BOD), and chemical oxygen demand (COD) in sewage. After treatment by biochemical methods, the domestic sewage is discharged from the discharge port to the municipal sewage pipe network (if all these parameters meet the national environmental emission standards), and finally into the municipal sewage treatment plant for unified treatment and utilization.

Fire Safety System Particularly, once a fire in fab occurs, it may be spreading fast and seriously damaging many equipment in clean room as chain effects. Furthermore, it is usually accompanied by explosion, toxic gas leakage, and so on. It is very difficult to rescue and extinguish the fire. Therefore, well-equipped and effective firefighting systems are essential for personnel and property safety: (1) Building Fire Protection systems: It is composed of fire detection and alarm, fire control, combustible gas detection and alarm, and electrical fire monitoring, together with automatic fire extinguishing system, smoke prevention system, and fire separation

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and other fire protection facilities to form a complete set of building fire protection systems. When a fire hazard occurs, the building fire protection system can be the first to make alarm and response, start the relevant fire control equipment, extinguish the initial fire and prevent the spread of fire, while giving personnel sufficient time for evacuation and emergency response. (2) Fire water supply and fire extinguishing facilities: They are set up in the buildings and facilities according to fire resistance grade, the nature of use, fire hazard, and so on. The fire water supply systems in IC production line generally include indoor and outdoor hydrant, automatic sprinkler, water spray fire extinguishing systems, etc., to ensure that the initial fire can be effectively curbed. All the fire water supply systems and fire extinguishing facilities such as alarm valve sets, pipe fittings, nozzles, and other key products should meet the domestic fire-related standards, and should meet the international UL (Underwriter Laboratories Inc.) certification and FM (Factory Mutual) Standards for certification. (3) Carbon dioxide gas fire extinguishing system: It is mainly used in the IC plant where water supply is not proper e.g. rooms for power distribution, computer, uninterruptible power supply, waste solvent collection, etc.). For areas where people often work or enter and leave, a non-toxic, harmless, low concentration of sevoflurane gas fire extinguishing system is preferable. A collation of the common fire extinguishing methods for IC plant is shown in Table 28.2. (4) Smoke prevention system: The buildings should be equipped with the necessary anti-smoking or smoke exhaust facilities to ensure the smooth evacuation and safe haven of personnel in the building at the time of the fire, and the timely removal of toxic and harmful flue gas and heat from the fire site to prevent further spreading of the fire for minimizing the loss of fire. (5) Very early fire detection system: IC plant, clean room, substation, computer room, and other important areas should be equipped with a high sensitivity very early fire detection system. The fire detection equipment can actively monitor and analyze air samples with smoke particles in early stage. If smoke particles are detected, an immediate alert will be issued at a very early stage to control the occurrence and spread of the fire. (6) Building fire prevention and safety evacuation: Clean room fire resistance level should not be less than 2 grades. The ceiling material should be non-combustion body, its refractory limit should not be less than 0.25 h. The straight distance from any point in the plant to the nearest safe outlet shall be in accordance with the requirements in Table 28.3. (7) Fire Emergency Broadcasting System: It includes emergency, fire linkage, and general business broadcasting functions. After the fire, the fire control room can make emergency broadcast to corresponding areas, play pre-recorded voice/instructions, staffs can also make broadcast through microphones, remote command fire extinguishing, and organization of personnel for safe evacuation. Fire protection systems play an extremely important role for personnel and property safety, and plans for regular maintenance and repair tests should be developed to ensure the safe and effective operation of the system.

Zone name Outdoor Cleaning Room Central Power Station Cooling Tower Electrical Equipment Room Gas Supply Room Solvent Supply Room Waste Solvent Collection Room Chlorine hexafluoride Supply Depot Chemical Warehouse Silane Supply Station

√ √ √ √ √ √ √ √ √

Indoor fire hydrant Outdoor hydrant √

√ √ √

Dry powder fire extinguisher

Table 28.2 Common fire extinguishing methods for an IC production line

√

√

√

√

√

√

Carbon dioxide automatic fire extinguishing equipment

√ √

Carbon dioxide Fire extinguisher

√ √ √

√

Automatic water sprinkler equipment

√

√

Water mist fire extinguishing equipment

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Table 28.3 Straight distance from any point in the plant to the nearest safe exit (unit: meter) Production Categories A B C C D

E

Refractory grade Primary and secondary Primary and secondary Primary and secondary Level III Primary and secondary Level III Level four Primary and secondary Level III Level four

Single layer 30 75 80 60 Unlimited 60 50 Unlimited 100 60

Multilayer 25 50 60 40 Unlimited 50 – Unlimited 75 –

Top – 30 40 – 50 – – 75 – –

Basement – – 30 – 45 – – 60 – –

Table 28.4 Power Load grading Load level Level I

Definition Level is consistent with one of the following: (1) When the interruption of power supply will result in personal injury or death (2) When the interruption of power supply will cause significant economic losses (3) Interrupting power supply will affect the normal operation of important power units Level II Meets one of the following conditions: (1) When the interruption of power supply will cause greater economic losses (2) Interrupting power supply will affect the normal operation of more important power units Level III When the impact of power supply interruption does not belong to level I and level II load, then it is level III power load

Power Systems The power systems for IC production lines shall cover the following aspects: (1) Load level: The power load should be graded according to the requirements for the reliability of power supplies and the degree of impact on personal safety and economic loss when power supply is interrupted as shown in Table 28.4. The electric load grade of IC production room is generally more than load level 2, using 2 power supplies. When there is a problem with the first power supply, the second power supply can power the plant load through the contact switch as shown in Fig. 28.2. (2) Voltage level: reasonable supply voltage should be determined according to the local power grid structure and plant load capacity. Inlet power supply voltage has 220 kV, 110 kV, 35 kV, 10 kV, and so on. The low-voltage distribution design for IC production line should meet the requirements of production process equipment and power equipment. (3) Sulfur hexafluoride sealed combination electrical appliances: The sulfur hexafluoride (SF6) gas insulation switch (GIS) is mainly used for electrical circuits with voltage levels of “division” and “fit” 10 kV and above. The

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Fig. 28.2 Illustration of power system architecture in IC production lines

GIS switch is filled with SF6 gas for better insulation and arc extinguishing capability. (4) High voltage power transformer (oil immersion): IC production plant generally uses oil-immersed power transformer to convert high voltage level to low voltage level, and then from medium voltage cabinet to each sub-substation. The main electrical protection of oil-immersed transformer is gas protection, longitudinal differential protection, overcurrent protection, etc., and oil immersion transformer has the function of on-load voltage regulation capability. (5) Closed automatic switching switch: Under normal circumstances, the load is powered by municipal electricity. When the municipal power outage, the load will automatically be switched to the emergency power supply. When the municipal power is restored, the load is automatically cut back to the municipal power supply, and then the emergency power supply is off. Each closed-type automatic switching switch (Closed Transition Transfer Switch, CTTS) should include a power switch unit and a control module that is wired in the disk for complete automated operation. The CTTS voltage is rated on both sides and is instantly connected within an allowed range for constant electrical load (closed-circuit) switching. The maximum connection time is 100 ms. (6) Uninterruptible power supply (UPS) system: Some devices have special requirements for power switching time, for example, the municipal electricity and emergency power supply switching time needs to be in millisecond (ms) level, and needs to set up the UPS system with power supply time no less than 5 min. When a municipal power outage occurs and before the diesel generator set starts, the plant is powered by UPS. Until the voltage of the diesel generator set is stable or the municipal electricity returns back to normal power level,

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the UPS stops supplying power. (7) Reactive power compensation and harmonic control: The facility for IC production line, if not meeting the requirements of the power supply environment, should select a reactive power compensation device to change the power supply environment. The capacitor set should be in the substation. Reactive power compensation device mainly includes main circuit breaker (or fuse switch), automatic power factor regulator, electromagnetic contactor and fuse, dry capacitor and 6% inductor, box and wiring, in-disk lighting, and control switch. If the system harmonics exceed national standards or have an impact on downstream equipment, it is necessary to implement active or passive filters to improve power quality. (8) Lighting: The workplace should use general lighting, when the users have different requirements for different areas within the same workplace, it is best to use different illumination of the light source. When an area or a special object needs to have strong illumination, it is best to use focused lighting. Ordinary lighting should be used in normal workplaces or other auxiliary places without special needs. Important places (e.g., clean rooms, substations, fire pumping stations, and fire control rooms) should be guaranteed with adequate spare illumination in case of emergency. Evacuation lights should be available in the evacuation paths to ensure safe evacuation of personnel. (9) Grounding: It is a connection through a conductor between the local ground and designated points of the power system, electrical devices, or equipment. Grounding is divided into functional grounding, protective grounding, electromagnetic compatibility grounding, building lightning grounding, and so on.

Ultrapure Water System Most processes in the production of IC require the use of ultrapure water (UPW) to clean up contaminants in the production process. As UPW is in direct contact with the wafers, trace impurities in UPW may contaminate the wafers. With the continuous improvement of IC technology, the quality of UPW is increasingly higher. The UPW process for an IC production line is illustrated in Fig. 28.3.

Fig. 28.3 Ultra-pure water (UPW) preparation process in semiconductor plant

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1. Pretreatment of UPW preparation: In order to make the treatment equipment for UPW safe, efficient, and economical, it is necessary to preprocess the raw waters, reduce the content of suspended matter, colloid, macromolecular organic matter, and positive and negative ions in the original water, and adjust the water temperature. Pretreatment is usually carried out by using multi-media filters or ultrafiltration membranes, degasification towers or degassing membranes, ion exchange resins, and activated carbon. 2. The initial preparation of UPW: The raw water after pretreatment, the resistivity can reach more than 18.0 Mohm.cm. The preliminary preparation of UPW mainly uses reverse osmosis (RO) and UV lamps to remove organic matter from the aqueous, uses RO and ion exchange resin to remove positive and negative ions and silica in water, and uses degasification film to remove dissolved oxygen from water. UV lamps are used to sterilize before RO to avoid microbial contamination of RO membranes. 3. UPW preparation of fine treatment: The initial preparation of pure water also through fine treatment, the basic removal of impurity components, and eventually made of UPW. Precision polishing treatment equipment mainly uses UV lamps to remove organic matter and bacteria; the use of polishing resin to remove residual ions; the use of ultrafiltration membrane removal of micro-particles; and the use of plate heat exchanger to control the water temperature in 23  C  1  C. The polishing resin needs to be replaced regularly in order to ensure the removal effect of polishing resin. A filter is arranged before the ultrafiltration membrane in order to ensure the safety of the ultrafiltration membrane. A degasification film can be set up before the ultrafiltration membrane to remove the dissolved oxygen from the water. 4. UPW index monitoring and analysis: In order to continuously supply highquality UPW, it must be monitored both online and offline with control standards. Online real-time monitoring indicators have resistivity, particles, total organic carbon, silica, dissolved oxygen, temperature, etc., as shown in Table 28.5. Offline monitoring mainly uses the method of regular sampling, the sample sent to the laboratory to detect the content of positive and negative ions. Before sampling, the sampling bottle and pipeline should be guaranteed to be clean and sampled according to sampling criteria. 5. The development trend and recovery rate of raw water supply of UPW: Due to the lack of water resources, the use of high-quality recycled water is an inevitable trend to replace tap water as the raw water for UPW. The water resources utilization requirement of UPW process is also higher, and enterprises should build their own. The process of the wastewater recovery treatment system, as illustrated in Fig. 28.4, utilizes activated carbon, RO membrane, and others for removing organic, salt, etc., in recycled water, and continuously recycle and reuse wastewater, to improve the recovery rate and save tap water.

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Table 28.5 Terminal water quality control table

Monitoring metrics Particle concentration of 0 – 1 μm/pcs/l) Total organic carbon concentration/ppb Silicon dioxide concentration/ppb Dissolved oxygen concentration/ppb Resistivity/MΩ
cm Temperature/ C

Target value 0.00

Downtime upper limit 1000.00

Downtime lower limit –

Control upper limit 700.00

Control lower limit –

0.00

3.00

–

1.00

–

0.00

2.00

–

0.50

–

0.00

3.00

–

2.00

–

18.20 23

– 24

17.50 22

– 23.5

18.00 22.5

Note: PCS/L is the number of particles per liter; ppb is 10

9

Fig. 28.4 Process of wastewater recovery treatment system

Wastewater Treatment System Wastewater produced by IC production line can be divided into 5 categories: ammonia-containing, fluorine-containing, copper-containing, grinding, and acid-base wastewater. Ammonia-containing, fluorine (F)-containing, copper (Cu)containing, and grinding wastewater should be diverted into their respective treatment systems, and finally into the neutralization treatment system after treatment. In order to ensure the normal and stable operation of the wastewater treatment system, an online monitoring system [7] is set up in the central control room to automatically control the whole wastewater treatment system. After the treated wastewater meets the discharge standards, it can be discharged from the outlet of the wastewater to the municipal sewage pipe network and eventually into the municipal wastewater treatment plant for further unified treatment and utilization. (1) Ammonia wastewater treatment: The concentration of ammonia wastewater in IC production line is high, and it is usually treated by stripping method. The treatment process is illustrated in Fig. 28.5. (2) Treatment of F-containing wastewater: Lime or calcium chloride flocculation precipitation is the most commonly used treatment method for F-containing wastewater in IC production plant, and its treatment process is illustrated in Fig. 28.6. (3) Cu-containing wastewater treatment: Cu-containing wastewater is treated by adding complexing agent, coagulant, and separated from

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Fig. 28.5 Treatment process of ammonia-containing wastewater by stripping method

Fig. 28.6 Treatment process of fluorine-containing wastewater

precipitation, and then the sludge produced is compressed into cake and treated outside. This technology is a conventional, mature, and reliable treatment process, for meeting the discharge standard. (4) Grinding wastewater treatment: The Grinding wastewater is often treated by flocculation and sedimentation methods. After collecting and adjusting the pH value of grinding wastewater, adding coagulant, mixing fully, discharging into the flocculation tank, adding flocculants, the wastewater into the sedimentation tank, and the treated clarified wastewater into the acid-alkali wastewater treatment system for neutralization, the sludge produced is concentrated and dried and transported to the outside.

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Fig. 28.7 Treatment process of acid-alkali wastewater

(5) Treatment of acid-alkali wastewater: acid-alkali wastewater is usually treated by acid-alkali neutralization. The acid-alkali wastewater is neutralized by adding liquid alkali (e.g., NaOH) and sulfuric acid (H 2SO4), and discharged after meeting the standard of sewage nanotube. The treatment process of acidalkali wastewater is shown in Fig. 28.7.

Facility Monitoring and Control Systems (FMCS) The main function of the plant facility monitoring and control system (FMCS) is that it can continuously measure and collect data on the normal operation of various centralized supply systems, so that the duty officer of fab facilities can monitor the real-time status of all systems. In case of abnormalities, the duty officer can overhaul and maintain the equipment at the earliest time. In order to facilitate the operation of the relevant staff, all subsystems of the monitoring system in the screen style, operation mode, and color definition, etc., are consistent. FMCS is described below. (1) The basic hardware components of FMCS: Including database server, system information collection equipment, alarm printing equipment, engineer base station, and network facilities. The main function of the database server is to collect the signal of the subsystem, so that users can compare the available information according to the basic data analysis of these signals. The main function of the system information collection equipment is to integrate the monitoring screen of the subsystem into the computer of the Monitoring Center in order to achieve unified monitoring of all the equipment. The engineer base station allows the engineer or program writer to modify, develop, and debug without affecting operation of the monitoring system. The function of the alarm printing device is to print out important alerts for users to reference or cooperate with the program analysis software for different stages of historical data analysis. (2) The main software components of FMCS: Including 4 aspects of basic, base, application, and user software. The basic software includes database management system software, engineering and monitoring software, communication software, data banking software, graphical display process visualization software, Ethernet connection communication software, etc. The base software includes operating software, higher level computer communication software, and so on. The application software includes process data acquisition software, abnormal condition alarm software, process measurement software for

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Fig. 28.8 Topology diagram of factory monitoring system network of an IC production fab

display and recording, monitoring and reporting management information software, etc. The user software includes logic control software, equipment operation software, and so on. (3) Network topology: Taking the factory monitoring system of an IC production fab as an example, its network topology is illustrated in Fig. 28.8. Intelligent FMCS is an important part of automation plant, including intelligent inspection system, robot inspection system, intelligent maintenance system, fault intelligent analysis system, knowledge base system, intelligent report system, personnel positioning system, and face recognition system.

Hook-Up System The hook-up systems refer to the system connecting the production equipment with all needed conditions (e.g., water, chemicals, gas, vacuum, electricity, etc.) from the main central supply system with safety and stability for long-term normal operation. Such “secondary piping” system can be divided by function, mainly including the following parts. (1) Cooling water piping system: It is for normal operation of equipment in clean room and auxiliary equipment to have cooling water with stable temperature, pressure, and conductivity. Cooling water piping is configured according to equipment requirements, connecting process and related ancillary equipment from the main system reservation point to the plant and other supporting areas. The connection between the cooling water pipeline and the equipment is enclosed with water supply and return pipeline. Cooling water pipes are stainless steel hard pipe and rubber high-pressure hose and other accessories generally using sub-arc welding. (2) Vacuum piping system: The vacuum system can provide a certain vacuum level for the use in equipment adsorption of wafers. The vacuum piping system is configured according to the requirements of the equipment and is

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connected from the main system reservation point to the equipment and related ancillary equipment in the factory and other supporting areas. The vacuum piping is all made up by high-density polyvinyl chloride (UPVC) hard tubes and fittings, and the use of polyurethane (PU) or polyethylene (PE) hoses and connected to the use point. The connection of the vacuum pipeline is generally bonded. (3) Water pipeline system: Based on the equipment requirements, it is configured and connected from the reserve point of the main system to the process equipment. Tap water pipeline is made up of 304 stainless steel hard pipe and rubber highpressure hose, etc. It is usually welded by argon arc welding. (4) UPW piping system: It is configured according to equipment requirements, from the main system reservation point connected to the plant and other support areas. The materials for UPW pipes and accessories are usually poly-vinylidene fluoride (PVDF) and PTFE (PFA) material; valve selection of poly-vinylidene fluoride (PVDF) diaphragm valve. The UPW pipeline connection is generally welded by automatic hot melt welding machine. (5) Wastewater discharge piping system: It is used in the IC production process to produce wastewater (e.g., ammonia containing wastewater, fluorinated wastewater, Cu-containing wastewater, grinding wastewater, acid and alkali wastewater, etc.) for classified discharge and treatment. The discharge piping is equipped with different emission types according to equipment requirements, connecting equipment, and related ancillary equipment from the main system reservation point to the plant and other supporting areas. (6) Gas piping system: Based on the needs of the process, it is connected to the process equipment and related ancillary equipment in the plant and other supporting areas from their respective cylinder cabinets, valve boxes, or main system reservation points. The materials of the process gas piping system is generally with the inner surface polishing treatment of stainless steel. The connection of process gas pipeline generally adopts automatic trajectory argon protection welding. (7) Exhaust piping system: It is used for separating emissions and treatment of various waste gases generated in the IC production. Piping varies from the main system reservation point to the process equipment and related ancillary equipment in the factory and other supporting areas. The connection of the pipeline is generally made of flange connection. (8) Secondary power distribution system: The power supply from the main system reservation point is connected to the equipment. (9) Chemicals piping systems: It is for the distribution of chemicals and connected to process equipment and related ancillary equipment from their respective chemical valve sets. Process chemical piping materials are generally PTFE (PFA) inner tube or stainless steel inner tube. (10) Equipment base: According to the load-bearing and vibration requirements, IC production equipment need to be equipped with different types of equipment bases. The basic equipment base can be divided into steel plate base frame, steel structure base frame, cement frame, and elephant foot base frame.

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References 1. S.-L. Chung, M.D. Jeng, An overview of semiconductor fab automation systems, in 2003 IEEE International Conference on Robotics and Automation (Cat. No.03CH37422), vol. 1, (Taipei, 2003), pp. 1050–1055. https://doi.org/10.1109/ROBOT.2003.1241731 2. C.C. Chien, C.N. Chang, J. Shyu, E. Hsiao, B.S. Tang, L.-K. Zhu, Innovative preciseenvironment design and technology of removing the pollutant from a clean room, in 2013 e-Manufacturing & Design Collaboration Symposium (eMDC), Hsinchu, (2013), pp. 1–4. https://doi.org/10.1109/eMDC.2013.6756037 3. Y. Kobayashi, S. Kobayashi, K. Tokunaga, K. Kato, T. Minami, Particle characteristics of 300-mm minienvironment (FOUP and LPU). IEEE Trans. Semicond. Manuf. 13(3), 259–263 (2000). https://doi.org/10.1109/66.857933 4. L. Aresi, S. Dauzère-Pérès, C. Yugma, M. Ndiaye, L. Rullière, AMHS vehicle management policies in semiconductor manufacturing: A short review, in 2019 IEEE International Conference on Industrial Engineering and Systems Management (IESM), Shanghai, (2019), pp. 1–6. https://doi.org/10.1109/IESM45758.2019.8948208 5. M. Haddadin, W. Moreno, Automated material handling systems: System of systems architecture examination semiconductor manufacturing perspective, in 2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Milpitas, CA, USA, (2021), pp. 1–6. https:// doi.org/10.1109/ASMC51741.2021.9435681 6. K. Lee, S. Song, D. Chang, S. Park, A new AMHS testbed for semiconductor manufacturing, in 2022 Winter Simulation Conference (WSC), Dermatol Sin, (2022), pp. 3318–3325. https://doi. org/10.1109/WSC57314.2022.10015476 7. A. Jain, R. Bagherwal, Design and implementation of a smart solid waste monitoring and collection system based on Internet of Things, in 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi, (2017), pp. 1–5. https:// doi.org/10.1109/ICCCNT.2017.8204165

Clean Room and Air Conditioning Systems

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Contents Clean Room System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Air Conditioning Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circulating and Cooling Water System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vacuum System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exhaust System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

604 604 606 607 608 609

Abstract

A qualified clean room environment has specific requirements for not only particle control but also temperature, humidity, pressure, and oxygen levels which are supplied and controlled by other essential systems. It includes air conditioning systems, circulating and cooling water system, vacuum system, and exhaust system. Together it provides necessary conditions for manufacturing processes and normal operation. This chapter further gives the introduction with flow charts of those systems. Keywords

Clean room · Particles · Air conditioning system · Circulating and cooling water · Vacuum system · Exhaust system

D. Xiao (*) SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_29

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Clean Room System The fabrication of integrated circuits (IC) must be performed in the clean room environment. Clean room refers to a room, where the concentration of suspended particles is controlled and its construction and use shall reduce the induction, generation, and retention of particles in the room. Other indoor parameters such as temperature, humidity, pressure, and oxygen level are also controlled according to special requirements. More advanced clean room designs are illustrated in references [1–3]. Following is a brief introduction of the filtration system, airflow, static hazards, and preventive measures of the clean room. (1) Clean room filtration system: The system can filter out dust air particles by using the combination of high-efficiency and ultra-high-efficiency filters with efficiency as high as 99.995%–99.999995%. The concentration of air particles after filtering is controlled within the range of cleanroom grade requirements. (2) Airflow in clean room: The personnel and production equipment in the clean room can produce dust particles as a great hazard to the clean room environment, and it is necessary to filter or discharge the dust through the airflow. According to the direction of airflow, it can be divided as one-way flow (e.g., parallel airflow vertically or horizontally), non-one-way flow (airflow mixed by fresh air supply into clean room with indoor air), or mixed flow (airflow combined with one-way flow and non-one-way flow). (3) Electrostatic hazards in clean rooms: The anti-static requirements in the clean room are also stringent. The main hazards of static electricity to ICs are mainly in the following 3 aspects. (a) Electrostatic adsorption: the electrostatic charge accumulated on the product will absorb the dust in the air through electrostatic force and attach on the product. (b) Electrostatic discharge: When the electrostatic charge accumulates to a high enough potential, it will discharge through an adjacent conductive path and result in device breakdown. c) Electrostatic interference: Electrostatic discharge may generate radiation and interfere with adjacent devices (e.g., microprocessors, memories, etc.). (4) Anti-static precautions in clean room: The anti-static control scheme may vary depending on process areas. (a) Electrostatic protection of interior installations (elevated floor, ceiling, partition, etc.). The primary anti-static measure of interior installations in a clean room is grounding. As many materials used in production are insulators (e.g., quartz, glass, plastic, etc.), the static charge generated during production may be removed through local grounding as a key anti-static scheme. (b) Electrostatic protection by ion rods, ion fans, etc.: The ion generators, for example, ion rods and ion fans, can generate positive and negative ions by ionizing particles in the air, and can neutralize the charges accumulated on devices or objects, thereby eliminating static electricity. According to the “Code for Design of Clean Workshops” (GB50073-2013), the integer grade of air cleanliness in clean rooms is shown in Table 29.1.

Air Conditioning Systems Air conditioning systems refer to the air handling systems which provide the necessary environmental conditions for manufacturing processes or normal operation. In IC manufacturing plants, air conditioning systems can regulate and

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Table 29.1 Integer grade of air cleanliness in clean rooms Air cleanliness grade (N) 1 2 3 4 5 6 7 8 9

Maximum concentration limits for larger than or equal to required particle size/(pcs/m3) 0.1 μm 0.2 μm 0.3 μm 0.5 μm 1.0 μm 5.0 μm 10 2 – – – – 100 24 10 4 1000 237 102 35 8 10,000 2370 1020 352 83 100,000 23,700 10,200 3520 832 29 1,000,000 237,000 102,000 35,200 8320 293 – – – 352,000 83,200 2930 – – – 3,520,000 832,000 29,300 – – – 35,200 000 8,320,000 293,000

Note: According to different measurement methods, the effective number of concentration data at different levels should not exceed 3 digits; pcs/m3 is the number of particles per cubic meter

Fig. 29.1 Air conditioning system structure of a typical IC Fab

control the temperature, humidity, and air flow speed in a room or space and supply fresh air and remove dirty air. (1) The air conditioning system includes filters, air scrubbers, coolers, fans, and heaters, as illustrated in Fig. 29.1. (2) The selection, arrangement, and installation of filters in air conditioning boxes should be carefully selected according to the air cleanliness level. The medium or high efficiency filters shall be in the positive pressure section of air conditioning boxes. (3) Humidity control in clean room is performed in 2 aspects. If the external air is wet, then it is firstly cooled by air condition system to a point to achieve dehumidification; and then the air is heated to the desired temperature level. If the external air is too dry, then it is firstly heated, then passed through a humidification system and then sent into the clean room. (4) The fresh air systems (Fig. 29.2) with constant temperature and humidity after treatment is directed into the return-wall of the clean room through air duct and mixed with the return air of the clean room. The fresh air flow is formed in the clean room under the operation of fan filter unit to circulate air throughout the clean room.

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Fig. 29.2 Illustration of a fresh air system in clean room

Circulating and Cooling Water System In the manufacturing of ICs, wafers are processed through 100s of steps (unit processes) with process equipment and tools in active operation and generating heat during production and testing. The circulating and cooling water system provides the needed cooling water in the production line for equipment and tools. When the system is in operation, it needs to provide steady flow, pressure, and temperature as well as good water quality for continuous and long-term operation. The flow chart of a typical system for circulating and cooling water is illustrated in Fig. 29.3. The system includes a water tank (for water storage and collecting return water and adding medicament to adjust water quality), water pump (for enough pressure on cooling water to user side), heat exchanger (for cooling water to exchange heat with ice water to ensure temperature stability of cooling water supply), frequency converter (for maintaining stable outlet pressure of the pump with variable frequency method), and the filter (for filtering out impurities in the water to avoid blockage of equipment or tools).

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Fig. 29.3 Flow chart of a typical system for circulating and cooling water

The circulating and cooling water system can provide cooling water with stable temperature and pressure, and continuously remove the heat generated by equipment during IC production. Temperature stability is achieved by the turn-on of an ice water valve on the side of heat exchanger based on temperature sensor, so that the water supply temperature can be kept within the range as specified by the operation of equipment. The main system can maintain stable pressure by using variable frequency pump for achieving a stable cooling water supply for the end equipment. At the same time, the circulating cooling water system shall keep stable pH value and conductivity of the water within a certain range per the equipment specifications. If the level of water in the storage tank decreases during the cycle, deionized (DI) water will be added to ensure the stability of the circulating and cooling water system. If DI water is not available, then the tap or city water can be used as emergency water supply.

Vacuum System In the production of ICs, the vacuum systems (see Fig. 29.4) are used to provide the vacuum pressure and gas flow required by the production and testing equipment. One practical example of the system is described here for references. The total flow through vacuum ports in a vacuum system is determined by the equipment demand. In general, several vacuum pumps are connected in parallel. (1) The vacuum pressure at the point of use is 150 kPa (+50 kPa). (2) The pressure of the vacuum pump is greater than 80 kPa (absolute value). (3) The vacuum pressure of the system is 80–88 kPa. (4) The system is equipped with a vacuum buffer tank. (5) Cooling water with a rotary bolt vacuum pump is used for cooling. The system operation is briefly described here. The vacuum system extracts air from the pipeline through a vacuum pump to maintain a certain pressure in the chamber. The extracted gas is discharged into the atmosphere or exhaust system

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Fig. 29.4 Working flow diagram of a vacuum system

through the back-end of the vacuum pump. At the same time, the pressure at the end of a single process needs to be constant, so the pressure of the main pipeline needs to be constant in operation. The buffer tank is connected in parallel to the whole system for the purpose of stabilizing the main pressure for a short time when a transient disturbance occurs at the vacuum pump end. When the system is in operation, the vacuum level is measured and continuously monitored by the air pressure sensor outside the buffer tank and the output signal is sent to the centralized controller. When the vacuum level is less than 80 kPa, the intake valve, ice water solenoid valve, and vacuum pump are turned on until the vacuum level rises to the target upper limit (greater than 88 kPa). When the vacuum level drops to the lower limit, and if still declining in vacuum level, then additional vacuum pumps are turned on until all the vacuum pumps are started. When the system vacuum reaches the upper limit, the vacuum pumps are shut off.

Exhaust System Many varieties of special gases and chemicals are used in IC production. The reactions of various gases and chemicals in processes will produce toxic and harmful by-products, which need to be effectively treated and carefully discharged after meeting the emission standards to avoid impacts on environment and human society. Classification and treatment of exhaust systems: (1) Exhaust system of general gas: It refers to an exhaust system that removes waste heat from equipment by a fan or ensuring a negative pressure environment inside the system. The general exhaust does not contain toxic and harmful substances and is discharged directly into the outdoor atmosphere without treatment. (2) Exhaust system of acid gas: It refers to an exhaust system that is used to treat harmful acidic gases containing HCl, H2SO4, etc., through an acidic scrubber and discharged to the atmosphere through a fan. The acidic scrubber neutralizes the harmful acidic gases with alkaline liquids and then separates the liquid and the gases that meet the discharge standards through the fan. Generally, the gas–liquid reverse absorption method is adopted, where the alkaline liquid is sprayed down from the top of the tower in a fog (or in small droplets), allowing the acidic gas to pass through the packed scrubber tower. This treatment serves the purpose of cooling waste gas, regulating gas pH, and removing particles. The exhaust gas is then treated in the defogging section and discharged into the

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atmosphere after meeting the environmental emission standards. (3) Exhaust system of alkaline gas: It refers to an exhaust system that is used to treat harmful alkaline gases containing NH3, etc., using an alkaline scrubber and discharged to the atmosphere through a fan. The alkaline scrubber neutralizes harmful alkaline gases with acidic liquids and then separates liquids and gases that meet discharge standards through a fan. In general, the gas–liquid reverse absorption method is adopted, where the acid liquid is sprayed down from the top of the tower in a fog (or in small droplets), allowing the alkaline gas to pass through the packed scrubber tower. This treatment serves the purpose of cooling waste gas, regulating gas pH, and removing particles. The exhaust gas is then treated in the defogging section and discharged into the atmosphere after meeting the environmental emission standards. (4) Exhaust system of organic solvents: It refers to the exhaust system that is used to treat harmful gases containing organic solvents such as benzene, acetone and isopropanol by a zeolite runner and a combustion furnace. Generally, zeolite runners are installed to absorb organic solvents and discharge into the atmosphere after meeting the environmental emission standards. Organic solvents concentrated by the runner are desorbed by hot air. The wind pressure design includes the pressure specification of the fan to meet the required pressure along the main pipe in the exhaust system. In the design process, it is necessary to consider the pressure loss of the duct, the local pressure losses of the duct fittings, tees, elbows, variable diameters, and air valves, the minimum wind pressure requirement at the end user, and the pressure loss of the treatment equipment. In the wind pressure design, it is also necessary to include a certain margin of wind volume and pressure for the end user. The general reserved wind pressure of the exhaust connection is 400 to 500 Pa, the wind pressure at the end of main pipe is 700 to 800 Pa, and the wind pressure at the inlet header of the fan is generally 1000 to 1300 Pa. In IC production, the negative pressure of the exhaust system must be stable, avoiding excessive fluctuations to trigger an alarm, forced shutdown, and even direct impact on wafer quality in production.

References 1. P. Thu, S.R. Andrei, M.L. Nikolai, Analysis of the air conditioning and filtration systems in clean rooms, in 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Moscow and St. Petersburg, Russia, (2018), pp. 1916–1919. https:// doi.org/10.1109/EIConRus.2018.8317483 2. V.I. Karakeyan, A.S. Riabyshenkov, M.A. Gundartcev, V.P. Sharaeva, N.R. Kharlamov, Structural and objective model for providing a given class of clean rooms for microelectronics, in 2021 International Seminar on Electron Devices Design and Production (SED), Prague, Czech Republic, (2021), pp. 1–4. https://doi.org/10.1109/SED51197.2021.9444530 3. T. Ishiguro, T. Ro, Cleanroom design for Cu-CMP processes, in 2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203), San Jose, CA, USA, (2001), pp. 11–14. https://doi.org/10.1109/ISSM.2001. 962903

Central Gas and Chemical Supply Systems

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Deyuan Xiao

Contents Bulk Gas Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Gas Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chemical Supply Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

612 612 617 619

Abstract

As the semiconductor industry continues to develop, the demand for ultra-pure gases and chemicals also keeps growing. Generally, gases and chemicals supplies can be outsourced to reliable third parties, but on-site central systems are also very critical. This chapter presents the classification and applications of bulk gases, special gases, and chemicals in a typical fab. It also introduces how to monitor and control the chemicals and gas usages for different fabrication processes of ICs. Keywords

Bulk gases · Special gases · Purification · Chemicals · Monitoring and safety protection

Bulk gas supply, special gas systems, and chemical supply systems are key aspects in IC product lines. Recent new techniques for monitoring gas and chemicals are shown in references [1–3].

D. Xiao (*) SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_30

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Bulk Gas Systems Classification and application of bulk gases: Bulk gases are a generic term for nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), and helium (He). (1) N2: Nitrogen generator can separate N2 gas from air after compression, cooling, fractionation, and vaporization. N2 is used for cleaning and diluting raw gas in equipment, providing inert gas environment, and serving as a pressure source for chemical transportation. (2) H2: H2 gas can be directly supplied from transport truck or cylinders to the facility; it can provide a combustion medium for equipment and serve as a reducing reaction gas. (3) O2: The vaporizer converts liquid oxygen into gas. It serves as oxidizer for reaction chamber and also the O2 supply to the ozone (O3) generator. (4) Ar: The vaporizer converts liquid Ar. It serves as the heat conducting medium and inert gas environment for reaction chamber. (5) Helium (He): The vaporizer converts liquid helium for cooling wafer chucks in process. Bulk gas systems: (1) Gas-making station: It includes gas-making facilities, compression storage facilities, filling facilities, auxiliary facilities, buildings, and structures required for gas-making by relevant processes. The quality of output gas of a typical gas station is shown in Tables 30.1 and 30.2. (2) Gas purification station: It includes the building, structure, or room with purification devices of bulk gas, gas filters, pipelines, and auxiliary facilities. The impurities of bulk gases in gas station systems are adsorbed and filtered through a gas purifier and particulate filter, generating high-purity bulk gases used by the process equipment. The quality of output gas of a typical purification station is shown in Table 30.3. (3) Quality and pressure control system: It is a system that collects and displays the quality, flow, and pressure data of the supplied gas through a gas analyzer and data acquisition and monitoring control system. The contents of gas impurity detection in a typical control system are listed in Table 30.4. (4) High purity gas delivery system: It refers to a delivery system from a bulk gas purification device (or station) to service points needed for high purity gas.

Special Gas Systems Special gases are indispensable raw materials and widely used in the production of IC, liquid crystal panels, solar cells, and optical fibers. They are mainly used in process steps in oxidation, doping, vapor deposition, diffusion, and other processes. Special gases are generally classified as non-combustible, toxic, flammable, and corrosive gases according to their properties. Each classification of special gasses is placed in different chemical stations in the facility. Silane stations are generally set up separately due to its spontaneous combustion. As the chlorine trifluoride (ClF3) reacts with water, its storage rooms should also be set up separately. Low-pressure gas is located on the 2nd floor of the clean room. Toxic, corrosive, flammable gasses, and tail gas treatment devices are located in the corresponding areas. A special gas delivery system includes pipelines and equipment that conveys special gasses from cylinders at gas stations to valve distribution boxes in clean

Total hydrocarbon content/ppm
1
0.5
25
0.25
0.25 Oxygen content/ppm
2
2 –
1
1

Hydrogen content/ppm
2 –
1
1
1

Carbon monoxide/ carbon dioxide/ppm
0.5
0.1
0.5
0.1
0.1

Note: ppm is 106; pcs/ft3 is the number of particles per cubic foot, 1ft3 ¼ 0.0283168 m3

Water Gas type content/ppm Nitrogen
5 Hydrogen
5 Oxygen
3 Argon
1 Helium
1

Table 30.1 Gas output quality of a typical gas station Nitrogen content/ppm –
5 –
1
1

Argon content/ppm – – – – –

Particle quantity of 0.1 μm size in diameter/(pcs/ft3)
10
10
10
10
10

30 Central Gas and Chemical Supply Systems 613

Total hydrocarbon content/ppb
1
1
1
1
1

Oxygen content/ppb
1
1 –
1
1

Hydrogen content/ppb
1 –
1
1
1

Carbon monoxide/carbon dioxide/ppb
1
1
1
1
1

Note: ppb is 109; pcs/ft3 is the number of particles per cubic foot, 1ft3 ¼ 0.0283168 m3

Water Gas type content/ppb Nitrogen
1 Hydrogen
1 Oxygen
1 Argon
1 Helium
1

Table 30.2 Gas output quality of a typical purification station Nitrogen content/ppb –
1
1
1
1

Argon content/ppb –
1
1 – –

Particle quantity of 0.1 μm size in diameter/(pcs/ft3)
1
1
1
1
1

614 D. Xiao

Gas type Nitrogen Hydrogen Oxygen Argon Helium

Water content √ √ √ √ √

Oxygen content √ √ – √ √

Methane content √ √ √ √ √

Carbon dioxide √ √ √ √ √

Table 30.3 Contents of gas impurity detection in a typical control system Non-methane total hydrocarbon content √ √ √ √ √

Hydrogen content √ – √ √ √

Carbon monoxide √ √ √ √ √

Particle √ √ √ √ √

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Table 30.4 Monitoring and safety protection devices for special gas equipment in a typical fab

Gas species 1% B2H6/H2 10%GeH4/H2 NH3 CH4 C3H6 CH3F CH2F2 1%GeH4/H2 SF6 CHF3 0.5%O2/He 1.2%He/N2 CF4 C4F8 100 ppmXe/ 3.5%Ar/Ne N2O 4%H2/N2 5%H2/He CO2 30%O2/He 1.25%Kr/He NO 5%B2H6/N2 SiH2Cl2 (DSC) NF3 1%PH3/PH2 1%PH3/N2 CO Cl2 0.95%F2/3.5% Ar/Ne 0.9%F2/1.25% Kr/Ne HCl HBr SO2 20%F2/N2 WF6 HF SiCl4

Sensor Ultraviolet/ infrared sensor √ √

Overflow protection device √ √ √

Spray √ √ √

Smoke sensor √ √

Temperature sensor √ √ √

√ √ √ √

√ √ √ √

√ √

√ √ √ √

√ √ √ √ √ √ √ √

√ √ √ √ √ √ √ √ √

√

√

√

√ √

√ √ √ √ √ √ √

√ √

√

√

√

√

√ √

√ √ √

√ √ √ √ √ √ √ √ √

(continued)

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Table 30.4 (continued)

Gas species C4F6 C5F8 BCl3 SiH4 SiF4 C2H2 ClF3

Overflow protection device

√ √ √

Spray √ √ √ √ √ √ √

Sensor Ultraviolet/ infrared sensor

√

Smoke sensor √

Temperature sensor √

√ √ √

√ √ √ √

Note: The types of special gasses commonly used in IC industry chain are listed in the table. Some kinds of special gas supply equipment do not need monitoring or safety protection devices

rooms, and then to service points of process equipment in accordance with stable gas flow and pressure in operation and safety requirements. Special gas delivery system generally includes gas cabinet (GC), gas rack (GR), bulk special gas supply system (BSGS), special gas mass supply system, mixer system, valve distribution box/panel (VDB/VDP), and valve manifold box/panel (VMB/VMP). A gas detector and information system includes gas detector system (GDS) and gas information system (GIS). GDS includes gas detector, seismograph and local alarm unit (LAU), etc. GIS includes remote input/output (RIO) panel, interchanger, and communication module. The monitoring and safety protection devices for special gas equipment adopted by a typical Fab are shown in Table 30.4.

Chemical Supply Systems A chemical supply system is a general term for pipes and equipment that conveys chemicals in warehouse storage to valve distribution boxes in clean rooms, and then to service points of process equipment in accordance with stable flow and pressure in operation and safety requirement. The distribution of chemicals used in various areas of equipment in a typical fab is shown in Table 30.5. The supply methods of chemical supply systems can be divided into nitrogen pressure supply and pump supply. The nitrogen pressure chemical supply system (Fig. 30.1) uses high purity nitrogen as power source and supplies chemicals to process equipment with stable flow and high demand chemicals. The pump chemical supply system (Fig. 30.2) is powered by a pump which supplies chemicals to process equipment through the pressure of the pump. The chemical systems supplied by the pump also need a regulator to stabilize the outlet pressure to provide stable and high demand for chemicals. The operational requirements for the chemical supply system: (1) Quality control: Before the system is put into use, the quality test needs to be completed and followed by thorough rinse with the chemicals to be delivered. UPW pipeline and water guns are installed in each supply system for cleaning; N2 pipeline and water

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Table 30.5 Distribution of chemicals used in various areas of equipment in a typical fab

Chemical name Hydrofluoric acid Sulfuric acid Ammonia Developer solution Hydrogen peroxide Nitric acid Phosphoric acid Hydrochloric acid Benzodiazole Copper sulfate Citric acid 5% hydrofluoric acid Diluent N-methyl-2-tetrahy dropyrrolidone Isopropyl alcohol Polymer cleaning solution after etching Photoresist remover Cyclopentanone Propylene glycol acetate monomethyl

Process equipment area Wet bench Reclaim clean area area √ √ √ √ √ √ √ √ √ √ √ √ √

CMP area √

Lithography area

PVD area

Clean area √

√ √ √ √ √ √ √ √ √ √

√ √ √ √

√

√

√

√ √ √

Fig. 30.1 Diagram of nitrogen pressure chemical supply system

Fig. 30.2 Schematic diagram of the pump chemical supply system

guns are installed in each supply system for cleaning and drying; high-clean materials should be selected in chemical supply systems; sampling points should be set at source and outlet for quality analysis sampling of each node. (2) Safety measures:

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①The different interfaces of the system are managed by various levels of authority with usernames and passwords set separately. ②Hardware error-proof measures: special connectors should be used in the chemical barrel trough to match the equipment and prevent incorrect chemical supply and incompatible chemical mixing. ③Software measures: The chemical barrel and tank with different chemical types have different codes, matching with their respective equipment and confirmed by scanner. ④Safety protection: The supply system can be shut down in an emergency if there is leakage, fire, earthquake, or a manual alarm occurs. Leakage sensors are installed in the valve box of the equipment. The pipeline is designed with doubledeck to prevent from danger from leakage; N2 purging design is installed in the electric control area; the exhaust systems for chemicals with different types should be plugged into exhaust systems with different types; each chemical room should be equipped with a dedicated exhaust pipeline; components of the supply section should be placed in a safe cabinet (e.g., the supply cabinets containing acid and alkali chemicals are made of polypropylene, and those containing solvent chemicals are often made of 304 stainless steel); high efficiency air filters and exhaust devices should be installed.

References 1. F.-H. Chang, K.-C. Chang, H.-C. Wang, Intelligent explosion-proof gas monitoring and early warning system with semiconductor plant as disaster prevention target, in 2022 17th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei, Taiwan, pp. 1–4 (2022). https://doi.org/10.1109/IMPACT56280.2022.9966677 2. H.-M. Cho, K.-H. Lee, P. Shim, A. Park, A chemical monitoring and prediction system in semiconductor manufacturing process using Bigdata and AI techniques, in IEEE International Conference on Artificial Intelligence in Information and Communication (ICAIIC), Jeju Island, Korea (South), pp. 488–491 (2021). https://doi.org/10.1109/ICAIIC51459.2021.9415241 3. DOROTA OWCZAREK: Chemical Supply Chain: Challenges and Opportunities in the Era of AI., https://nexocode.com/blog/posts/chemical-supply-chain-challenges-and-opportunities-inthe-era-of-ai/ (2021). Accessed 16 July 2021

Construction and Management of IC Production Lines

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Contents Organization and Responsibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Project Planning and Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Project Bidding Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Government Approval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Construction Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contract Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schedule Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Inspection (QI) and Quality Assurance (QA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Utilities Equipment Space Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Construction Safety Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring of Central Supply System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

622 623 624 625 625 630 631 631 632 635 636 638

Abstract

The construction and management of the IC production line is a series of complex and systematic activities executed by the clearly defined responsible organizations. Before starting the construction, all the technical requirements, quality, maintainability, and cost need to be carefully planned and designed. Then the bidding of engineering projects shall be open, fair, and honest, and the construction must be performed strictly in accordance with national laws and local regulations. This chapter introduces the major management concepts over the whole construction project, respectively, such as construction management, contract management, schedule control, quality and safety management, and the finally monitoring of central supply systems. Since each construction and regulation activity can have significant impact on the overall schedule and cost, it is essential to plan in advance and manage strictly the entire construction project. S. Wang (*) SiEn (Qingdao) Integrated Circuit Corp, Qingdao University, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_31

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Keywords

Project plan and design · Bidding · Regulation · Construction management · Contract · Schedule control · Quality management · Safety management

In order to construct IC production lines quickly, safely, and efficiently with good quality of construction, the project management needs to be performed systematically. Mainly the basics of constructing IC production lines are described here with more advanced techniques in references [1–3].

Organization and Responsibility The project organization for the construction of IC production lines (or fabs) is a collection of personnel and facilities with clear responsibilities, authority, and interrelationships that implement or participate in project management. The project organization level, members, and responsibilities of general IC fab construction personnel are shown in Table 31.1. The organization structure commonly used in general IC fab projects is shown in Fig. 31.1. The project manager is the core management personnel of the project. The main duties include (1) implement the relevant laws, regulations, guidelines, policies, and compulsory standards of the national and local government; (2) strictly implement the company’s management system and regulations; (3) safeguard the company’s legitimate rights and interests; and (4) perform all aspects of the project, specifically manage engineering planning and design, engineering technology, schedule control, quality, and safety supervision. The project manager also comprehensively presides over the project construction and management work on behalf of the company, Table 31.1 Project organization level, members, and responsibilities of general IC fab construction personnel Project organization level Decision group Management group Executive group

Operation group

Project members Project manager

Person in charge of design, procurement, construction, etc. Members of the functional department such as technical engineer, quality engineer, safety engineer, materials engineer, and budget engineer Structural labor contractor, clean room, electromechanical, process support system contractor, etc.

Responsibility Planning and coordinating, control the overall situation, overall command, decision-making Division of labor management, work lead, coordination, synergy Exclusive responsibility, implementation, front line command, quality Cooperate, be responsible, obey the command, and concrete implementation

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Fig. 31.1 The organization structure commonly used in general IC fab projects

assumes the contract performance responsibility, and is fully responsible for the final audit of engineering materials and equipment of the project. The project manager is also responsible for project payment, summary, and check according to contract as well as responsible for the project completion inspection and acceptance of the series of work.

Project Planning and Design Project planning and design is an important stage before the construction of an IC production line. Project planning and design should fully consider the technical requirements, quality, maintainability, and cost. The results of planning and design will directly affect the progress and economic benefits of the project. The main work of project planning and design mainly includes the following. (1) Selection of the

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planning and design company: According to the construction requirements, the company shall work on the preliminary planning and design mainly including an overall planning from the selection of the geographical location of the plant to the layout of the building structure, equipment, and facilities of the plant. (2) Planning and design work: Provide construction project planning and designs according to the project schedule, which includes project planning, basic design, detailed design, etc., and finally complete the bidding documents of each system. (3) Schedule control: According to the progress of the project, establish a control table based on bidding document, including the project and organization name, contract number and name, date of contract signing, commencement, completion, etc. for the follow-up and control the progress of planning and design. (4) Review: The planning and design company conducts project planning and design according to the project timeline and completes the government approval and construction completion schedule. (5) Drawings: The planning and design company will discuss and design the preliminary drawings by coordinating the professional designers of civil construction, fire protection, machinery, electricity, water treatment, gas, and chemicals, and the users of related systems. Users in various fields of expertise consider the location and size of the room based on the area and specifications of the equipment. The planning and design company perform a second design with details of the space management drawing of the factory. According to the second edition of the drawings, the professionals coordinate the construction parties to review and further revise the design and submit to the planning and design company for re-audit. Finally, the planning and design company releases the final drawings.

Project Bidding Procedure The bidding of engineering projects shall follow the principles of openness, fairness, impartiality, and honesty. Neither any unit nor individual may turn a whole project into parts that must be tendered according to law or circumvent the bidding in any other way. The bidding shall be handled by the bidder in accordance with the law. Neither any unit nor individual may illegally interfere with the bidding in any way. The bidder is a legal person or other organization that proposes the construction bidding project according to law and conducts the bidding. The construction projects that must be bid according to law shall meet the following conditions before bidding. (1) The bidder has been established by law; (2) the preliminary design and budget estimate which should perform the approval procedures have been approved; (3) the corresponding funds are supported or sources of funds have been made available; (4) design drawings and technical materials required for bidding are prepared. The general bidding process is as follows. (1) Preparation before bidding. Prepare the project proposal (e.g., the project feasibility study report and application procedures for the construction project) and the prequalification and bidding documents (e.g., the sale of prequalification documents, acceptance of prequalification applications of bidders, and prequalification of potential bidders). Then, release the prequalification announcement and issue bidding documents and Q&A and addenda

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(e.g., the sale of bidding documents, on-site investigation of the project before the bid opening, and the pre-bid meeting and addenda). (2) Receiving bid documents. Receive bidder’s bid documents and bid bond, and ensure the sealing of bid documents. (3) Extracting the evaluation experts. (4) Opening the bid. Specify the time and place; check in the participants; check the sealing of bid documents; host the bidding and record the opening process, and keep it on file for future reference. (5) Review of bid documents. It includes the establishment of the bid evaluation committee, the bid evaluation preparation, the preliminary evaluation, the detailed evaluation, the issuance of the bid evaluation report, and the recommendation of the winning bidder. (6) Finalizing the bid. (7) Issuing a notice of winning the bid for construction project. (8) Contract negotiation and signing. (9) Refunding the bid bond.

Government Approval The construction of IC production lines must be performed strictly in accordance with national and local laws and regulations. In the early construction stage as well as the final acceptance stage of the project, all shall be subject to government approval and through the corresponding procedures. Let’s take a typical example to introduce the government approval items. (1) Early stage: After the intention of the project is determined, it is necessary to conduct a feasibility study first. Then go through the corresponding procedures in accordance with the construction formalities, and start construction after obtaining the construction permit. (2) Construction stage: Before piling, the local planning bureau should be required to carry out the gray line acceptance. During the construction of the project, the local quality supervision station shall supervise and inspect (by random inspection) the construction quality and acceptance (interspersed) of some sub-projects. (3) Completion and acceptance stage: The project shall complete the engineering design document requirements and the contents of the contract in accordance with the relevant national and local laws and regulations and engineering construction standards. After the construction unit has obtained the acceptance or permit documents for construction quality, fire protection, planning, environmental protection, urban construction, etc. issued by the relevant government departments (or its associated agencies), the completion and acceptance of the project shall be organized, and the “Construction Project Completion Acceptance Report” shall be completed. The general process for handling engineering construction procedures is shown in Table 31.2.

Construction Management Construction management is to ensure that the construction contractor shall complete the construction as planned, and the content and quality of the project are in accordance with the contract terms, engineering drawings, and related laws and

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Table 31.2 The general procedures for handling engineering construction projects

Stage Early stage

Number 1

2

2.1

2.2 2.3 2.4 Early stage

3 4

5

6 7 7.1

7.2 8 9 10

11

Project phase and related procedures Project intention, market research, and investment opportunity analysis Prepare a feasibility study report for the construction project Implementation of consultation schemes for water supply, sewage, power supply, gas supply, heat supply, and supply of telecommunications sources Prepare the environmental assessment report Obtain the energy pre-evaluation report Obtain soil and water conservation evaluation report Submit the feasibility study report of the construction project Receive the EIA report approval

Fill in the “application form of opinions on site selection for construction projects,” and issue the “opinions on site selection for construction projects” Land survey and pile determination report State-owned land use right certificate Sign the “contract for assigning and transferring the right to use state-owned land” Pay deed tax (including land transfer fee) Obtain approval for construction project Issuance of construction land planning license Entrust survey, design bidding, handle survey, and design bid award notification Fill in the “Application Form for Planning and Design Requirements of the Construction

Competent department (for institutional reform, for reference only) Construction unit

Construction unit or design unit entrusted by the construction unit Construction unit

Institutions with EIA qualifications Local development and reform commission Local environmental protection bureau Construction unit Local municipal or provincial environmental protection bureau/department Local land administration

Qualified land survey and demarcation team Local land administration Local land administration

Local finance bureau Local management committee Local planning bureau Local bidding office

Construction unit

(continued)

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Table 31.2 (continued)

Stage

Number

12

13 13.1 13.2 14 15

16

16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8

16.9

Early stage

17 18 18.1 19

Project phase and related procedures Projects” and attach the topographic map of the Surveying and Mapping Institute Issue planning and design requisition and approve design scope drawing Confirm the architectural design Design and survey units conduct open bidding and tendering Determine the design schemes Survey and issue survey geological report Prepare preliminary (expanded) design texts according to planning and design requirements The government planning and construction departments organize the preliminary (expanded) scheme examination and approval meeting and make an approval reply Planning department approval Aseismatic department approval Fire department approval Civil defense department approval Health department approval Labor protection department approval Environmental protection department approval Water, electricity, gas, telecommunications sector approval Municipal, green, technical and security, traffic patrol, water, and other departments for consultation Construction drawing design Construction drawing review Issue a construction drawing audit report Issue of construction project planning permits

Competent department (for institutional reform, for reference only)

Local planning bureau

Construction unit Local planning commission Design unit Survey unit Design unit

Local planning bureau

Planning department Aseismatic department Fire department Civil defense department Health department Labor protection department Environmental protection department Related water, electricity, gas, and telecommunications sector Related government departments

Design unit Qualified review unit Qualified review unit Local planning bureau (continued)

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Table 31.2 (continued)

Stage

Number 19.1 19.2 19.3 20 21 22

23 24 25

26

27 28 30

Construction stage

Completion acceptance stage

31 1 2

1 2

3

4

Project phase and related procedures Approval of fire design opinions Approval of environmental protection design comments Approval of the opinions on the review of civil air defense Handling temporary water and electricity for construction Handling construction temporary intersection Entrust construction, supervise Bidding, conduct construction, supervise bid award notification Sign construction contract Filing government contracts Issue the capital guarantee letter and relevant certificates, and the five parties sign the quality lifelong responsibility letter Quality and safety supervision declaration, that is, handling quality supervision registration Verify and issue construction permits Registration of the use of bulk cement and clay bricks Road planning and red line piling Entrust contractor lofting Planning acceptance of gray line Supervision and inspection (by random inspection) of the construction quality and acceptance (interspersed) of some sub-projects Project commissioning and rectification Qualification certificate for water supply, power supply, natural gas, telecommunications, and drainage construction Filling the test run of environmental protection completion acceptance Water quality test report (with secondary supply)

Competent department (for institutional reform, for reference only) Fire department Environmental protection department Civil air defense department Water company, power supply bureau Municipal office Bidding office

Construction site of employer Local construction bureau Employer and contractor

Construction bureau engineering safety and quality supervision department Construction bureau Construction bureau Surveying and Mapping Institute Contractor Planning bureau Quality supervision station

All participating units Water company, power supply bureau, natural gas company, telecommunications bureau, municipal office Environmental protection bureau Health and quarantine bureau (continued)

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Table 31.2 (continued)

Stage

Number 5

6

7 8

Project phase and related procedures Fire department complete acceptance, and obtain “fire acceptance opinions” Completion acceptance of greening supporting, obtaining “filling certificate of completion acceptance of greening supporting” Indoor environment test report

19.116

Review opinions on completion settlement of wall materials Review opinions on completion settlement of bulk cement Pre-acceptance of completion data files, and obtain the “preacceptance certificate of completion data file center” Organize completion acceptance Filling completion acceptance of quality supervision Acceptance of environmental protection department and obtaining “environmental protection acceptance letter” Submit the completion files of the construction project and obtain the “certificate of acceptance of the completion data files” Plan completion acceptance, and obtain the “Certificate of completion acceptance for planning” Planning measurement report for completion acceptance Apply for real estate license

16.1

Real estate area mapping

16.2

Handling property code confirmation Payment of maintenance fund

9 10

11 12 13

14

15

15.1

16.3

Competent department (for institutional reform, for reference only) Fire detachment

Greening office

Qualified environmental testing agency Construction bureau Construction bureau Archive center

Quality supervision center Quality supervision center Environmental protection bureau

Construction Committee

Planning bureau

Qualified measuring unit Housing and Land Administration Qualified surveying and mapping units Local land administration Maintenance fund management office

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regulations. The main functions of construction management include as follows: ①prepare a work plan in advance; ②set the target; ③use the organizational power to command; ④supervise, inspect, and adjust the implementation of the plan; ⑤perform comprehensive and holistic coordination. The common control procedures for construction management in the construction process are as follows: (1) document control procedures; (2) recording, transferring, and receiving control procedures; (3) laws and regulations and other requirements control procedures; (4) resource management control procedures; (5) information exchange and communication control procedures; (6) management review control procedures; (7) design process control procedures; (8) procurement process control procedures; (9) construction process control procedures; (10) general contracting and project management control procedures; (11) monitoring and measuring equipment control procedures; (12) environmental factor identification and evaluation control procedures; (13) hazard source identification and risk assessment control procedures; (14) environmental and occupational health and safety operational control procedures; (15) emergency preparedness and response control procedures; (16) monitoring and measurement control procedures; (17) internal audit control procedures; (18) non-conforming product control procedures.

Contract Management Contract management is the core of project management for the entire process of construction. The main points are as follows. (1) Strengthen management awareness. It is necessary to recognize the importance of contract management from the view point of ideology, emphasizing on construction not only according to the drawings but also the contract. (2) Clarify the contract management process and clarify the corresponding workflow. (3) Establish a contract representation system. After the signing of the contract, the contract management personnel must make the contract representation to the project management personnel at all levels and the person in charge of each working group, so that everyone is familiar with the main content of the contract, various regulations and management procedures, and deeply understand the contractor’s responsibility and the scope of works. (4) Establish a system of responsibility distribution. The contract management personnel shall be responsible for distributing the responsibility of various contract events into the working groups or subcontractors so that they have a detailed understanding of their respective scope of work and responsibilities. (5) Pay attention to the text analysis of the contract. Both sides can negotiate on the relevant content before signing, but the contract has legal effect after signing. Therefore, in order to avoid future disputes, it is necessary to pay attention to the text analysis (i.e., the legitimacy and completeness of the contract). (6) Pay attention to contract change management. Due to the frequent changes of contract in engineering practice, it is required to strengthen the management in the implementation of the project. All kinds of documents involved, such as drawings, plans, technical notes, and specifications, should be recorded, collected,

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and organized, and the content of the changed parts should be reviewed and analyzed.

Schedule Control The schedule control refers to the formulation of detailed rules for the schedule management according to the overall schedule of the project construction and the actual situation of project implementation management. It also establishes a series of management systems related to the control and guarantee of the construction schedule, ensuring the smooth implementation of the construction schedule through rigorous procedural operations and systematic guarantee. The construction schedule shall be prepared according to the bidding documents, Q&A supplementary documents, bill of quantities, and other items. The construction sequence and requirements shall be consistent with the actual conditions, and each construction procedure and area shall be reasonably determined to ensure that the overall schedule is completed as scheduled. The schedule management items commonly used in the construction of IC production line are the following: (1) schedule preparation and review; (2) schedule accountability management; (3) deepen the design of schedule management; (4) equipment delivery tracking; (5) equipment approach plan and implementation; (6) schedule reporting system; (7) contingency schedule if failing to complete the progress as scheduled; (8) construction progress assessment, rewards, and punishments. In order to ensure the realization of the construction schedule target and meet the requirements of the duration of total and each node, the total duration should be broken up into several control points according to the key lines and important procedures in the schedule. The rationality of duration arrangement and resource input should be analyzed in depth. So the completion of the total duration shall be ensured by the realization of the control point targets. During the construction, it is necessary to compare the planned budget output value with the actual output value so as to judge the trend of the schedule and determine whether the progress of the relevant sub-projects should be accelerated or postponed. Based on this, the progress of each operation team shall be estimated, and the differences between the site schedule and the overall schedule shall be revised. Finally, it is ensured by various assurance measures related to the progress. The classification construction management process commonly used in the construction of IC production line is shown in Fig. 31.2.

Quality Inspection (QI) and Quality Assurance (QA) The purpose of construction quality management is to ensure and improve the overall quality of the project. A series of quality management organization systems and methods are implemented to ensure the high engineering quality of each construction process meeting the standards set by the engineering drawings design

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Fig. 31.2 Schedule management process commonly used in the construction of IC production lines

specifications and description. The quality management organization is a 3-level management system and responsible for the quality inspection (QI). The management system is led by the project manager, intermediately controlled by the project technical director and deputy manager, and the quality director, and the professional foreman and full-time quality inspector of each department. The system has organizational guarantee and clear job responsibilities, and the quality of the project is acceptable for supervision and inspection by the owner, the supervision unit, and the government quality supervision institution. The organization structure commonly used in the construction quality management is shown in Fig. 31.3. The quality assurance (QA) procedures defined by the construction quality management organization are shown in Fig. 31.4.

Utilities Equipment Space Management The purpose of utilities equipment space management is to rationally arrange the vertical and horizontal public utilities equipment and the service routes of related auxiliary pipelines, air ducts, and cable bridges in the factories on the premise of ensuring the design concept, so as to avoid the obstructions between public equipment and facilities in the construction and installation process and save the costs and shorten the construction duration. Due to the large number of pipelines and complicated spatial arrangement in the comprehensive power station, the entrance room of each pipeline, the technology sandwich of the core area, pipe gallery, pipe rack, roof

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Fig. 31.3 Organization structure commonly used in construction quality management

Fig. 31.4 Quality assurance procedures

exhaust, and other areas, it is easy to see the situations such as space collision or pipeline dislocation, etc. Therefore, Building Information Management (BIM) is often adopted to integrate information in a unified platform. The general implementation steps of space management in the construction process of IC production line are shown in Table 31.3.

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Table 31.3 General implementation steps of space management in the construction process of the IC production line Project stage Design stage

Specific work of space management Compile space management related documents

Establish the design model based on construction drawing

Conduct analysis of building performance

Collision check

Comprehensive planning and optimization of pipeline based on design model

Construction stage

Control the application situations of BIM technology by contractor Establish the model of depth design

Comprehensive pipeline planning and optimization during construction Coordination meeting of space management

Deepen design drawing

Technology disclosure and on-site verification of BIM

Brief description of content BIM implementation template, BIM implementation management manual and process, BIM implementation specifications Establish models of building, structural and electromechanical professional according to full set of construction drawings Conduct project analysis, such as wind environment simulation, sunshine analysis simulation, and flow evacuation analysis simulation Conduct professional collision inspection of buildings, structures, and electromechanical systems Conduct comprehensive pipeline planning, optimize pipeline layout, reasonably control the net height, and provide the net height analysis report; key control of the machine room Plan, organize, control, and review the BIM application of each contractor, and guide the construction Deepen site construction according to construction drawing model, refine equipment interface, add construction details, and establish deepening design model Conduct comprehensive pipeline planning based on deepening design model, optimize pipeline layout, and issue comprehensive pipeline report Holding site coordination meetings based on BIM model regularly to discuss problems found in the models and document solutions After the comprehensive pipeline planning based on the deepening design model, the relevant construction drawing and prefabrication drawing are issued, and the statistical table of pipeline and equipment engineering quantity is given Carry out technical disclosure to the construction unit according to the detailed design drawings and models, and organize the construction unit to conduct site inspection of BIM (continued)

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Table 31.3 (continued) Project stage

Specific work of space management Simulation of overall construction progress

Set up 3d construction log

Completion stage

Establish completion model

Brief description of content Carry out the dynamic simulation of overall construction progress and local construction node simulation according to the main construction progress According to the actual construction progress, combining with the real model, record the real construction progress by 3d dynamic; update the 3d log weekly or monthly according to the site construction log Establish a real and complete completion model in order to provide an accurate basis for the later operation and management based on the three-dimensional model

Construction Safety Management In order to ensure the construction safety of an IC production line, it is necessary to establish sound rules and regulations, clarify the rights and obligations related to safety matters, and conduct construction safety management. The general safety management rules are as follows. (1) The general contractor for construction must possess the registered capital stipulated by the State and meet the requirements of professional and technical personnel, technical equipment, and conditions for safety production. It must have all corresponding registered qualification certificates according to law and contracted the project within the scope of its qualification registration permission. (2) The project manager shall be fully responsible for the safety work of the contracted projects according to law, establish and improve the production safety responsibility system and the safety education and training system, formulate safety production rules and regulations and operational procedures, ensure the investment of funds required for safe production conditions, and conduct regular and special inspections and keep safety records. (3) The person in charge of safety must have corresponding professional qualifications, be responsible for the safe construction of construction projects, ensure the effective use of safe production costs, organize and formulate safe construction measures according to the characteristics of the project to eliminate potential safety hazards, and report timely and truthful safety production accidents. (4) The expenses required for a safe working environment and safety measures included in the proposed project budget shall be used for the procurement and renewal of construction safety protective equipment and facilities, the implementation of safety measures, and the improvement of safe production conditions and shall not be used for other purposes. (5) Establish the corresponding safety management organization, with full-time safety production management personnel. (6) Special operators (e.g., vertical transport machinery

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operators, installation and disassembly workers, lifting signal workers, and ascending erecting workers) must be trained in special safety operations in accordance with the regulations of the relevant state departments and obtain various operation qualification certificates before they can start work. (7) Before the construction of the project, the technical person in charge of the project management shall make detailed instructions on the technical requirements for safe construction to the construction teams and the operators. (8) Obvious safety warning signs shall be set at the entrance of the construction site, construction cranes, temporary power facilities, scaffoldings, access passages, staircases, elevator shafts, hole openings, and storage places of hazardous gas and liquid. (9) The office at the construction site shall be set separately from the operation area and maintain a safe distance. Special protective measures shall be taken to prevent possible damage to adjacent buildings, structures, underground pipelines, etc. due to construction. (10) Establish a fire safety responsibility system at the construction site, determine the person in charge of fire safety, and formulate various fire safety systems and operating procedures for fire, electricity, and use of flammable and explosive materials. (11) Provide safety protective equipment to the operators and inform them in writing of the operating procedures of dangerous positions and the hazards of illegal operations. (12) The operators shall have the right to criticize, report, and sue the safety problems in the operating conditions, procedures, and methods of the construction site, and shall have the right to refuse command in violation of regulations and risky operations. (13) Operators should abide by the mandatory standards, rules, and regulations and operating procedures for safe construction, and use safety protective equipment and machinery properly. (14) All purchased and leased safety protective equipment, machinery, construction equipment, and accessories shall have production (manufacturing) licenses and product qualification certificates. (15) Before the erection of construction lifting machinery and scaffolding, the relevant departments or units shall be organized to conduct inspection and acceptance.

Monitoring of Central Supply System The central supply systems refer to stably transfers raw materials (e.g., gas and chemicals) from the supply equipment to the technology production equipment in order to meet the needs of the IC technology on the premise of fully guaranteeing the technology and safety. In order to meet the requirements of production, the state of the central supply system shall be tested before operation. Let’s introduce the test of the central supply system. (1) Calibration: Use factory calibration, whenever possible, and keep calibration records for verification. Before the system is handed over, the constructor shall issue a valid calibration document for each piece of equipment. The accuracy of equipment used for factory or on-site calibration (if required) must be one level higher than that of the calibrated instrument,

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and the type should be indicated. (2) The factory tests: The contractor shall explain the factory acceptance plan in writing. The test procedure includes a detailed testing process, and all the tests should be conducted with the witness of the owner or his client. These test states should be as close as possible to the expected actual working states (including normal operation and system failure conditions). (3) On-site acceptance tests: The site acceptance tests shall include running acceptance, functional acceptance, and durability tests. (a) The running acceptance tests. Each piece of equipment must be tested for running acceptance. Before the trial run, the constructor must confirm that the parameters of each equipment to be tested are consistent with the requirements and in good working condition. The constructor should check that the instrument is installed correctly and make adjustments appropriately. At least one document containing 5 levels (0%, 25%, 50%, 75%, and 100%) must be prepared to confirm the calibration status. The operating status of all systems in the failure and power down mode shall be verified. Besides, it shall be also verified whether the system can returns to the most recent control and monitoring mode established when it returns to normal and powers on. The constructor shall submit a report in writing to inform the owner or the client to certify that the installed system has been calibrated, tested, and functional acceptance testing is available. (b) Functional acceptance tests. After the successful completion of the running acceptance test and submission of the written report by the constructor, as well as receiving the written permission from the customer or the client, the functional acceptance test can be performed. The constructor should check the site preparation conditions, check whether the site conditions meet requirements of the power wiring and grounding, check the installation of all equipment, use the running diagnostic program to verify whether the system is running normally and whether a communication connection is established between the system and the components, check whether all the inputs and outputs are working normally, and check whether there is a normal communication signal between the system and the factory monitoring system. (c) Durability tests. A specified durability test shall be performed by the constructor to demonstrate the reliability of the system. Durability testing can only be carried out when the constructor notifies the design unit, or the owner, in written form that the trial run has been successfully completed, and the designated training has been completed and the significant errors have been corrected. Durability test must be performed 24 h a day for 7 days, and the operation status of system should be consistent with the requirements. The constructor shall not carry out any maintenance during the test unless authorized by the owner. If there is no failure of the system during the test, the constructor can evaluate it directly after receiving the written permission of the owner. After the successful completion of the durability test, the constructor shall provide the test report and other documents before the owner receives the system. If the test fails, the constructor shall analyze the causes of the failures and repair it, then issue a written report to detail the nature of each failure, the corrective actions, the results of the test, and recommend whether the test continue at this point.

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References 1. T. Wakuda, K. Nagata, M. Kojima, Construction of an energy-saving semiconductor plant, in 1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023), San Francisco, CA, USA, 1997, pp. P57–P60. https://doi.org/10.1109/ ISSM.1997.664623 2. O. Suenaga, S. Kobayashi, T. Ohmi, A proposal for energy saving in semiconductor fabs, in 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314). https://doi.org/10.1109/ISSM.1999.808784 3. A. Sinha, W.A.C. Fernando, Analysing and realising wireless mesh networks as a replacement for lon based distributed control networks for clean room environment, in 2007 Canadian Conference on Electrical and Computer Engineering, Vancouver, BC, Canada, 2007, pp. 357–359. https://doi.org/10.1109/CCECE.2007.97

Hazardous Chemicals Management

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Deyuan Xiao

Contents Procurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

This chapter gives a comprehensive explanation about the management of hazardous chemicals in IC production lines. Hazardous chemicals are under specific management systems following the state’s regulations. All five procedures of procurement, transportation, storage, usage, and disposal of hazardous chemicals require professional and licensed personnel with clear responsibilities. Safety management, such as the education of safety and health information, marking safety labels on special designed tools and equipment with compliant handling methods, should be thoroughly implemented. Reliable hazardous chemical management needs close collaboration from the fab staffs and third-party suppliers; it’s critical to carefully follow every procedure. Keywords

Hazardous chemicals · Safety management · Procurement · Transportation · Storage · Usage · Disposal

D. Xiao (*) SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_32

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Management and handling of hazardous chemicals can be discussed in the following five procedures, i.e., procurement, transportation, storage, usage, and disposal of hazardous chemicals. More recent information of the hazardous chemical management is in references [1–8].

Procurement The procurement of hazardous chemicals shall be performed in accordance with the following requirements: operating according to law; strictly implementing the licensing and filing systems of the state for the management of hazardous chemicals; and operating hazardous chemicals in strict accordance with the scope of business licenses and modes of operation. (1) Purchase staffs or salesmen should participate in training and learning of applicable laws, regulations and related knowledge of hazardous chemicals and safety management, and pass the examinations to be qualified. No person without a witness shall engage in the business of hazardous chemicals. (2) Purchasers and salesmen should study the relevant management system of hazardous chemicals purchasing and selling and other safety management rules and regulations, and be familiar with the safety responsibilities, business processes, and operating procedures. (3) The purchase and sale of hazardous chemicals shall have a detailed account with detail information recorded, e.g., name of the supplier and purchaser, the variety, quality, quantity, and date of purchase. Monthly review of purchasing and sales accounts of hazardous chemicals is required to ensure that accounts, materials, and certificates (vouchers) are in place. (4) Hazardous chemicals shall not be sold to production or business units and individuals that have not obtained production or business licenses or completed the formalities for filing. The quality, packaging, marking, and protection of hazardous chemicals purchased and sold must conform to the national standards, rules, and regulations for the purchase of chemicals. (5) The handling of hazardous chemicals shall strictly implement the relevant management systems for handling and transportation of hazardous chemicals. Shipping companies and workers shall be aware of the physical and chemical characteristics and protection requirements of the loaded and unloaded hazardous chemicals and shall wear and use appropriate protective articles in accordance with regulations. (6) Purchasers, salesmen, and transmitter should be aware of the physical and chemical characteristics, dangerous categories, and grades of hazardous chemicals to be purchased and sold, as well as the safe transport mode, safety protection requirements, and emergency measures. (7) In case of loss or theft of hazardous chemicals in the course of business operation, the leaders of the units, local safety supervision and management departments, public security organizations, and health and environmental authorities shall be notified immediately. (8) If illegal purchasing and selling of hazardous chemicals are found in the course of business operation, they shall be stopped and checked immediately and reported to the local safety supervision and management departments and public security organization.

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Transportation The transportation of hazardous chemicals shall be carried out in accordance with the following requirements. (1) It shall take necessary safety and protection measures in accordance with the provisions of relevant laws, statutes, regulations, and the requirements of national standards, as well as special requirements of specific hazardous chemicals. (2) Containers used for chemical transport shall be manufactured at designated sites by specialized production enterprises and shall be used only after passing the appropriate tests and inspections. The quality inspection department shall perform periodic or irregular inspection on the quality of the containers produced by designated manufacturers in accordance with the regulations. (3) Tanks or containers transporting hazardous chemicals must be sealed tightly to withstand internal and external pressures under normal transportation conditions and ensure that no leakage or rupture occurs due to changes in temperature, humidity, or pressure in the transportation. (4) When hazardous chemicals are transported by road, they must be equipped with escorts and under the supervision of escorts at any time. They are not allowed to be overloaded or to enter areas where vehicles transporting hazardous chemicals are forbidden; if absolutely necessary, the local public security department must be notified in advance. Vehicles must abide by the driving times and routes designated by the public security department. The areas where vehicles transporting hazardous chemicals are prohibited shall be delimited by the Public Security Department of the municipal government with districts and prohibited areas clearly marked. When parking and special accommodation are needed during the transportation of hazardous chemicals or normal transportation is not possible, the report shall be submitted to the local public security department. (5) Vehicles transporting hazardous chemicals should be special-purpose vehicles with obvious signs and conform to the regulations of traffic management departments on vehicles and equipment: trailers and beds must be flat and intact, and the surrounding panels must be firm; motor vehicle exhaust pipes must be equipped with effective heat insulation and a device for extinguishing sparks, and circuit systems should be equipped with devices to cut off the total power supply and isolate sparks. The flag with the word “Dangerous Goods” in black and yellow background must be hung in the left front of vehicles. According to the nature of the dangerous goods loaded, it should be equipped with corresponding fire-fighting equipment and tools. (6) Regularly inspect the radioactive contamination level of special transport vehicles, equipment, moving tools, and protective equipment that transport radioactive isotopes. When the amount of contamination exceeds the allowable level specified, it shall not continue to be used. (7) Vehicles transporting containers, large cylinders, movable containers, etc. must have effective fastening devices. (8) All kinds of handling machinery and tools should have sufficient safety factors. Measures to eliminate sparks must be taken when handling flammable and explosive dangerous goods. (9) The hazardous chemicals that produce a dangerous reaction if in contact with each other or with fire-fighting methods must have different fitting connectors or the chemicals can’t be transported in the same vehicle or ship. (10) Flammable

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and explosive materials can’t be transported in cars and ships with iron bands and bottoms. (11) Flammable goods with flash point below 28  C should be transported at night when the temperature is lower than 28  C. (12) Vehicles transporting hazardous chemicals should have fire and explosion-proof safety measures. (13) It is forbidden for unrelated, or unlicensed, persons to take vehicles and other means of transport for carrying hazardous chemicals. (14) For the transport of explosives and hazardous chemicals requiring vouchers, they should have the “Permit to Transport Explosives” or “Permit to Transport Hazardous Chemicals” issued by the public security departments of prefectures, counties, and municipalities. (15) Hazardous chemicals transported by air shall be carried out in accordance with the relevant provisions of the Civil Aviation Department of the State Council.

Storage The storage of hazardous chemicals should be carried out according to the following requirements. (1) Hazardous chemicals must be stored in accordance with national laws, regulations, and other relevant provisions. (2) Hazardous chemicals must be stored in special hazardous chemicals warehouses approved by the public security department. The hazardous chemicals stored in warehouses by distribution departments and storage quantity must be approved by the public security department. Hazardous chemical storage warehouses shall not be set up at will without approval. (3) Hazardous chemicals should be stored in the open air in accordance with the safety requirements of fire prevention and explosion proof. Explosives, first-class inflammable, wet burning, and highly toxic articles should not be stored in the open air. (4) Warehouses storing hazardous chemicals must be equipped with technical personnel with professional knowledge, and their warehouses and sites should be managed by special personnel that must be equipped with reliable personal safety protective equipment. (5) Hazardous chemicals stored should be clearly marked. When two or more dangerous goods of different grades are stored in the same area, they shall be marked according to the performance of the highest grade dangerous goods. (6) There are three ways to store dangerous chemicals: segregated storage, cut-off storage, detached storage. (7) Hazardous chemicals are stored in different zones, categories, and warehouses according to its performance. All kinds of dangerous goods shall not be mixed with prohibited materials for storage. (8) Smoking and open fire are strictly prohibited in buildings and areas where hazardous chemicals are stored. (9) No basement or other underground building is allowed for storage of hazardous chemicals. Their fire-resistant grades, storage numbers, occupied areas, evacuation requirements, and fire-resistant spacing shall conform to the relevant provisions of the state. (10) Storage sites and building structures shall not only comply with the relevant provisions of the state, but also consider the impact on the surrounding environment and residents. (11) Lightning protection equipment must be installed in buildings storing flammable and explosive hazardous chemicals. (12) Ventilation equipment must be installed in buildings storing

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hazardous chemicals and shall pay attention to the protective measures of equipment. (13) The ventilation and exhaust system for buildings that store hazardous chemicals shall be equipped with grounding devices for eliminating static electricity.

Usage The use of hazardous chemicals should be implemented in accordance with the following requirements: (1) Chemicals used should be marked; and hazardous chemicals should have safety labels and provide safety technical instructions to operators. (2) When purchasing hazardous chemicals, the user must check the safety labels on the package (or container). If the safety labels fall off or are damaged, they shall be relabeled after checking and confirming. (3) When the chemicals purchased by the user need to be transferred or sub-packed into other containers, their contents shall be marked. For hazardous chemicals, safety labels should be attached to the containers after transfer or sub-loading. Containers containing hazardous chemicals should not change the original safety labels before being cleaned of all residual materials. (4) Users shall regularly inspect and evaluate the hazards caused by hazardous chemicals used in the workplace and file the results of inspection and evaluation. The concentration of hazardous chemicals exposed to operators should not be higher than the standards prescribed by the state; if there is no such regulation available, the users shall use them in the case of ensuring safe operations. (5) Users should eliminate, reduce, and control hazards caused by hazardous chemicals in the workplace by the following methods: ① to select non-toxic or low-toxic chemical substitutes; ② to select technologies that can eliminate or minimize hazards; ③ to adopt engineering control measures that can eliminate or reduce hazards (e.g., isolation, sealing, etc.); ④ to adopt working institutions and hours that can reduce or eliminate hazards; and ⑤ to adopt other labor safety and health measures. Users should have first aid facilities in hazardous chemicals workplaces and provide emergency treatment methods. (6) Users shall remove chemical wastes and wash waste containers containing hazardous chemicals in accordance with relevant regulations of the State. (7) The users shall mark the danger of the equipment for loading, transporting, and storing dangerous chemicals in the form of color, sign, and label. (8) Users shall publish safety and health information about hazardous chemicals to their employees, educate them to identify safety labels, understand safety technical specifications, master necessary emergency treatment methods and self-rescue measures, and regularly educate and train them on the safe use of chemicals in the workplace.

Disposal The disposal of hazardous chemicals should be performed in accordance with the following requirements. (1) It is prohibited to store combustible waste in hazardous chemicals storage areas. (2) Packaging containers that leak hazardous chemicals

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must be quickly transferred to safe areas. (3) All hazardous chemical wastes should be stored in special labeled containers and transported to designated sites for waste disposal. (4) According to the characteristics of hazardous chemicals, waste materials should be treated by chemical or physical methods. They should not be discarded arbitrarily to prevent pollution of water sources and the environment. (5) Waste disposal should be carried out according to the relevant operating rules and the relevant personnel should accept the relevant business training. (6) Enterprises shall develop disposal plans for hazardous chemical wastes and equipment that may be generated and assess the occupational safety, health, and environmental impact of this plan. (7) All disposal processes (e.g., sewage discharge, waste disposal, transportation and landfill, and waste gas emptying) should ensure the safety and health of the operators and the protection of the operating and the surrounding environment. (8) Enterprises should set up waste disposal and storage sites with sufficient site space to prevent waste containers from mixing in the normal processing and storage sites. (9) Waste containers should be designed and selected with the following considerations in mind: identification, structure, integrity, and protection. (10) Appropriate personal protective equipment shall be provided to operators during the disposal process and corresponding systems for the use, maintenance, and management of them shall be formulated. (11) When the enterprise does not set up waste treatment devices and supporting facilities in the workplace, it shall be disposed by specialized agencies in accordance with relevant national laws, regulations, and standards. (12) Separate work areas should be set up when waste is disposed by incineration, chemical oxidation, neutralization, and other methods whose design, construction, operation, and management shall meet the requirements of relevant national laws and regulations. (13) The disposal of wastes and containers should be subject to supervision and inspection by the environmental protection administration department. The departments responsible for the supervision and administration about safety of hazardous chemicals shall, upon receiving the reports, promptly handle them according to laws. If the case does not fall within the responsibility of the department concerned, it should be promptly transferred to the relevant department for handling.

References 1. Acquisition of Hazardous Chemicals, https://www1.grc.nasa.gov/wp-content/uploads/ ohpm14.pdf 2. Chemical Management, https://www2.education.vic.gov.au/pal/chemical-management/proce dure/5-procurement-dangerous-goods-and-hazardous-chemicals 3. Chemical Purchase, https://www.polyu.edu.hk/hso/our-services/chemical-purchase/ 4. General Safety Considerations, https://www.uh.edu/ehs/labs/chemical-safety/procurement/ 5. How to transport hazardous chemicals, https://www.royalchemical.com/blog/transportinghazardous-materials

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6. Rules for the Hazardous Chemicals Warehouse Storage in China Effective from July 1, 2023! https:// www.cirs-group.com/en/chemicals/gb-15603-2022-general-rules-for-the-hazardous-chemicals-ware house-storage-released-effective-from-july-1-2023 7. Consumption of hazardous chemicals, https://www.eea.europa.eu/airs/2018/environment-andhealth/production-of-hazardous-chemicals 8. T.S.S. Dikshith, P.V. Diwan, Industrial guide to chemical and drug safety, Ch. 17, in Disposal of hazardous chemicals, (18 April 2003). https://doi.org/10.1002/0471426075.ch17

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Contents Energy Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Measures for Saving Energy and Reducing Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Status and Development Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development Status and Opportunity in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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This chapter discusses the types of energy used in the typical IC production lines and some energy-saving methods for the reduction of power consumption. Generally, electric energy consumption is the main part, while others, e.g., city water, heat, natural gas, and air, are the secondary. To operate a cost-efficient fab, there are a lot of proven energy-saving practices as listed in this chapter, e.g., the optimization in air and water treatment, fab space design, and materials recycle as well as reclaim. Further, as the applications from consumer-end developed rapidly, the advanced IC production has increasingly progressed over recent decades with automation, new equipment, and technologies. China will continuously develop the capabilities in IC production and establish more advanced fabs in fast pace with high efficiency and technology levels. It is much more than massive capital investment, management experiences, and collaboration with partners toward long-term success. As the strong competition internationally, there will be more and faster development of IC production lines in future AI/IoT era.

D. Xiao (*) · J. Zeng SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_33

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Keywords

Energy consumption · Energy-saving · Optimized treatment · Recycle · 300 nm wafer production line · Automation · Manufacturing capacity · Competitiveness · Uncertainty

In this chapter, the following subjects are discussed: (1) energy consumption, (2) energy saving, (3) status and trends in fabs, and (4) development opportunities. More information of the energy saving and development trend, for further reading, is found in references [1–5].

Energy Consumption The energy consumption of IC production lines can be estimated from the power consumed by production equipment and supporting facilities as the majority of the total energy consumption. The production equipment are those used in the manufacturing, e.g., photolithography, thin-film, etching, ion implantation, thermal annealing, chemical vapor deposition (CVD), etc. Supporting facility equipment, on the other hand, includes air-condition system, ultra-pure DI water system, cooling water system, cooling tower and water pump, waste water/gas/ chemical treatment systems, fresh air units, fan filter units (FFU), fans, bulk-gas generation and purification, special gas and chemical delivery systems, etc. After the primary energy consumption is calculated, then various analysis on the energy consumption per wafer per technology node can be estimated for comparison, and indicators of energy saving can be made accordingly. An example of estimation of energy consumption of a typical 300 mm wafer fab is shown in Table 33.1 for references.

Main Measures for Saving Energy and Reducing Consumption The main energy consumption in the IC production is electrical energy. At the same time, secondary energy (e.g., tap water, heat, natural gas, compressed air, nitrogen, oxygen, hydrogen, argon, and helium) is also consumed in the IC production. The distribution of power consumption of a typical fab is shown in Fig. 33.1 for references. The main measures for energy saving and consumption reduction in IC production are as follows. (1) Optimize fresh air treatment: reasonably reduce the air supply and preheating temperature of fresh air fan and utilize the fresh air fan with heat recovery. (2) Reduce the fresh air volume: reduce the exhaust volume of the clean room and reasonably reduce the positive pressure of the clean room. (3)

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Table 33.1 Estimation of energy consumption of a typical 300 mm wafer fab Serial number 1

Energy and types of energy-consuming working fluid Electrical power

2 3

Tap water Ultra-pure water

4 5 6

Process equipment cooling water (PCW) Cooling water at room temperature Natural For canteen gas For organic waste gas treatment systems For point of use (POU) For boiler Compressed air High purity nitrogen Ultra-high purity nitrogen Ultra-high purity hydrogen Ultra-high purity oxygen Ultra-high purity argon gas Ultra-high purity helium

7 8 9 10 11 12 13

Specifications 208 V/380 V/ 480 V – 18.2 Ω
cm, 23  C 16.5  C 32  C/37  C 0.003 MPa 0.015 MPa 0.1 MPa 0.03~0.09 MPa >0.85 MPa 0.85 MPa 0.85 MPa 0.75 MPa 0.75 MPa 0.75 MPa 0.75 MPa

Usage 67,000 kVA 10,000 m3/d 12,647 m3/h 6,857 m3/h 27,000 m3/h 150 m3/h 200 m3/h 300 m3/h 3,520 m3/h 28,752 m3/h 7,547 m3/h 12,789 m3/h 120 m3/h 171 m3/h 99 m3/h 51 m3/h

Note: The data for items 7–13 are the gas volumes at the conditions of 0  C and 1 atm (i.e., 101.325 kPa)

Fig. 33.1 Distribution of power consumption of a typical fab

Adjust the operating time of air conditioning system in the office buildings. In the transitional season, increase the supply of fresh air as much as possible, and then remove the heat of the room through the fresh air. (4) Reasonably layout the floor to reduce power loss in power supply lines. (5) The clean room adopts micro-

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environment control mode, i.e., areas with higher cleanliness level for more critical operations and lower cleanliness level for less critical operations, so that the energy consumption may be reduced significantly. (6) When using filter units in production and supporting areas, it shall be properly allocated to reduce the energy consumption of unnecessary filter units. (7) Reasonably assess the requirements of each area and allocate according to the real need, avoiding excessive energy consumption due to over-spec with unnecessary allocation. (8) The energy consumption of a large clean room with constant temperature can be reduced by using new thermal insulation materials in the outer wall of the building to reduce the heat transfer between the indoor and outdoor environments. (9) Reduce power consumption through natural cooling of external environment. (10) The cooling water of all equipment can be recycled with closed loop system structure to save tap water consumption. (11) Collect rainwater in the whole plant area for irrigation of the trees and grass on site. (12) Recycle high purity cleaning water and DI water after cleaning Si wafer for scrubbing tower and gardening purposes. (13) Utilize the residual pressure of municipal water supply to supply tap water for reducing the use of pumps and electricity. (14) The local drainage is collected, treated, and recycled. (15) Waste sulfuric acid recovered from waste acid treatment stations can be used for sewage treatment systems (e.g., adjust pH values). (16) Maintain power factor of power system to above 0.95 by non-power compensation device for reducing power loss in power transformer and lines. (17) High efficiency and energy saving lamps are selected for lighting system. Street lamps are powered by solar energy and controlled by intelligent switch based on photo-electric principles. (18) Install illumination or motion sensors near the window and inside the office to control the lamp switches and save energy.

Current Status and Development Direction There are about 100 IC fabs with 300 mm wafer size as of 2018 worldwide and with additional 25 fabs by end of 2020. The number of 200 mm wafer fabs also increases in 2018 and reaching to >210 by 2020. There may be slower growth in IC fabs due to recent trade-war since 2019. In view of the nearly astronomical investment as well as uncertain return-on-investment (ROI) and technical obstacles, the construction of 450 mm wafer fab was not actively developed as expected, and the pace of wafer fab transition to 450 mm production line has slowed down significantly. According to current development trends of global IC manufacturing, it’s expected that the majority of IC manufacturing fabs still produce 300 mm wafers to maximize the ROI. At 10 nm node, Samsung, Intel, and TSMC are actively using multi-patterning DUV lithography. At 7 nm node, Samsung, Intel, and TSMC all adopt EUV lithography in production. Comparing with multi-patterning DUV, EUV is a lower

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cost lithography for 7 nm node and beyond as related to its shorter wavelength (13.5 nm) for better resolution and single exposure for patterning. EUV lithographic technology has advantages in better overlay accuracy and less masks and masking steps (vs DUV’s multi-patterning) for high resolution and yield. Most 300 mm IC production lines have Automated Material Handling System (AMHS) with advantages of efficient use of clean room space, effective management of wafers, and reduction of operators’ workload. In some 300 mm IC fabs, handling system can be extended to various areas and transfer wafers to equipment by overhead-hoist-transport (OHT). There are also fabs utilizing automatic guided vehicle (AGV) for materials, parts, and semi-finished goods transferring. Advanced IC manufacturing lines in the future will increase productivity and competitiveness with the help of intelligent automation, including intelligent control through equipment automation, intelligent knowledge management, reduction of costs and enhancement of standardization, improving operation efficiency and product development cycles, and intelligent manufacturing through AI/IoT technologies. Factory management process chart of modern smart IC fab is illustrated in Fig. 33.2.

Development Status and Opportunity in China In the past 20 years, main-stream technologies in China’s IC production lines have been developed from wafer size of 500 and 150 mm (for 0.5 μm node and above) to 200 mm (for 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm, 0.11 μm, and 90 nm technology nodes) and 300 mm (for 90 nm, 65 nm, 45 nm/40 nm, 28 nm, 14 nm, and 7 nm technology nodes). Representative IC manufacturers have been increased, such as SMIC, Shanghai Huali, Wuhan Xinxing, Huahong, China Resource Micro (CRMC), and ASMC. Now SMIC’s technology level has matured to 14 nm/12 nm nodes at 2019. Huali Micro has been developing 28 nm/14 nm technology nodes as well as evaluating FD-SOI technology. CRMC is in leading position in analog and high voltage technologies. 2017 China major IC manufacturing lines are listed in Table 33.2. China has become one of the countries/regions with the most IC production lines as an indication of global IC industry transferring to China. It’s estimated that until 2020, China’s IC manufacturing capacity will reach to 1100–1200 k/month. However, the recent trade war since 2019 between the USA and China may add uncertainty to this trend. At present, the construction of IC production lines appears increasingly larger and complex. For production of logic circuit chips, the capacity of each new 300 mm IC fab is more than 35,000 wafers per month (35 kW/month), while for production of memory chips, the capacity is usually more than 100,000 wafers per month (100 kW/month). When entering the 7 nm node and beyond, the introduction of EUV will bring new challenges to automatic transport equipment, clean room environment control, fire protection, environmental protection, and space management.

Fig. 33.2 Illustration of modern management of smart IC production line

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Table 33.2 Distribution table of 2017 China’s major IC manufacturing lines

Wafer Serial size/mm number Company name 300 1 SMIC (Beijing)

Internal identifier of manufacturing line Fab4 B1/B2

2

SMIC (Shanghai)

Fab8

3

Shanghai Huali Microelectronics Corporation Wuhan Xinxin Semiconductor Manufacturing SK Hynix (Wuxi)

Fab1

4

5 6

200

2.5

Fab1

10.0

Fab2

6.0

7 8

Intel (Dalian) Samsung (Xi’an)

Fab68 -

6.0 10.0

1 2

SMIC (Shanghai)

Fab1 Fab2

12.0

Fab3

3.0

3

4

SMIC (Tianjin)

Fab7

4.0

5

TSMC (China)

Fab1

11.0

6

Shanghai Huahong Semiconductor

Fab1

8.0

Fab2 Fab3

2.0 5.0

7 8

200

Production Technological capacity/(10 K/month) level 3.5 90 nm, 65 nm CMOS 3.5 each 65 nm, 40 nm, and 28 nm CMOS 1.0 90 nm, 65 nm, 40 nm, 28 nm CMOS 2.0 65 nm, 40 nm CMOS

9

Hejian Technology (Suzhou)

Fab1

6.0

10 11

Fab2 Shanghai Advanced Fab3 Semiconductor Manufacturing Corporation

4.0 1.5

90 nm, 65 nm CMOS and NAND Flash 65 nm, 40 nm DRAM 90 nm, 30 nm CMOS 65 nm CMOS 20 + nm, 10 + nm Flash 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm, 0.11 μm CMOS 0.13 μm, 0.11 μm Cu interconnected back-end technics 0.35 μm, 0.25 μm, 0.18 μm CMOS 0.25 μm, 0.18 μm, 0.13 μm CMOS 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm, 0.11 μm CMOS mix signal

0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm, 0.11 μm, 90 nm CMOS 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm CMOS 0.13 μm CMOS 0.35 μm, 0.25 μm CMOS mix signal

(continued)

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Table 33.2 (continued)

Wafer Serial size/mm number Company name 12 China Resource Group-CSMC (Wuxi) 13

14

15

150

16 17 18

19 20

1

2

3

4

5

6

Internal identifier of manufacturing line

Yude Semiconductor (Chongqing) Chengxin Fab11 (Acquired by Texas Instrument) (Chengdu) Jingchen Semiconductor (Zhengzhou) Xiyue Electronics (Xi’an) Fujian Fushun (Fuzhou) Leshan-Phoenix Semiconductor (Leshan Sichuan) Xiamen Jishun Institute of microelectronics, Chinese Academy of Sciences Fab1 China Resource Group- CSMC (Wuxi) China Resource Fab5 Group-CSWC (Wuxi) China Resource Group- Huajing Microelectronics (Wuxi) Shanghai Advanced Fab2 Semiconductor Manufacturing Corporation Shanghai BCD Semiconductor Manufacturing Shanghai Diodes

Production Technological capacity/(10 K/month) level 6.0 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm, 0.11 μm CMOS mix signal 3.0 0.35 μm, 0.25 μm, 0.18 μm CMOS Mix signal 3.0 0.35μm, 0.25 μm, 0.18 μm CMOS mix signal 3.0

0.35 μm, 0.25 μm, 0.18 μm CMOS

1.7

0.5 μm, 0.35 μm mix signal 0.8 μm, 0.5 μm mix signal 0.5 μm bipolar

1.8 3.0

6.0 2.0

0.5 μm, 0.35 μm mix signal 0.35 μm, 0.25 μm, 0.18 μm CMOS

6.0

0.5 μm, 0.35 μm BCD

3.5

0.5 μm, 0.35 μm BCD

5.0

1 2 μm, 0.8 μm analogy

4.0

1 5 μm, 1.2 μm, 0.8 μm, 0.5 μm BCD

5.0

1.5 μm, 1.2 μm, 0.8 μm, 0.5 μm BCD 1 0 μm, 0.8 μm, 0.5 μm, 0.35 μm mix signal

3.0

(continued)

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Table 33.2 (continued)

Wafer Serial size/mm number Company name 7 Wuxi KEC

150

8

Shougang NEC (Beijing)

9

Beijing Yandong

10

Hangzhou Silan

11

Hangzhou Li-On Microelectronics BYD Semiconductor (Ningbo) Jiangsu Dongguang Electronics Zhuhai Nanke

12

13 14 15

Shenzhen Founder

Internal identifier of manufacturing line

Production Technological capacity/(10 K/month) level 3.0 1.5 μm, 1.2 μm, 0.8 μm, 0.5 μm BCD 3.0 1.0 μm, 0.8 μm, 0.5 μm, 0.35 μm mix signal 2.0 1.0 μm, 0.8 μm, 0.5 μm, 0.35 μm mix signal 3.0 1.0 μm, 0.8 μm, 0.5 μm, 0.35 μm mix signal 1.5 0.8 μm, 0.5 μm, 0.35 μm mix signal 3.0 0.8 μm, 0.5 μm BCD 1.5 3.0 2.5

0.8 μm, 0.5 μm, 0.35 μm mix signal 0.5 μm, 0.35 μm CMOS 0.5 μm, 0.35 μm CMOS

References 1. Energy consumption WW.: https://www.iea.org/reports/key-world-energy-statistics-2021/finalconsumption 2. S.-C. Hu, and Chuah, Y.K.: Power consumption of semiconductor fabs in Taiwan. Energy 28 (8), 2003, Pages 895–907. https://www.sciencedirect.com/science/article/abs/pii/ S0360544203000082 3. Derbyshire, K.: Saving Energy in the Fab, 19 Nov 2015. https://semiengineering.com/savingenergy-in-the-fab/ 4. Lapedus, M.: China accelerates foundry, power semi efforts, 22 Nov 2021. https:// semiengineering.com/china-accelerates-foundry-power-semi-efforts/ 5. Leopold, G.: China’s wafer capacity jumps. EETimes-ASIA, 21 Feb 2022. https://www.eetasia. com/chinas-wafer-capacity-jumps/

Section V Integrated Circuit Design Shaojun Wei, Xiaolang Yan, and Yuhua Cheng

Introduction Integrated circuit design is an important part of integrated circuit (IC) industry and also is the core of IC product innovation and technological progress. IC design follows the basis and criteria of IC manufacturing to guide the development direction of manufacturing technology and support the market demand of system manufacturers. In this chapter, the technical basis of IC design is firstly expounded, including the design specifications, design processes, process design package (PDK), customer-owned technology (COT), standard cell library, circuit diagram, input/ output, clock design, leakage current, power consumption, design simulation, functional verification, place and route, as well as physical verification and layout delivery. In addition, the categories including their characteristics, performance indicators, design methods and development trend for digital ICs, analog ICs, radio frequency (RF) ICs, and power ICs are introduced respectively. Furthermore, processors, memories, system chips, and programmable logic circuits are taken as design examples. Their applications, circuit composition, technical features, and practical designs are introduced in detail. Finally, the electronic design automation (EDA) methods are comprehensively analyzed, and various EDA tools involved in IC design process are briefly introduced.

Overview of IC Design

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Contents Overview of Global IC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of IC Design in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supporting Role of IC Design to System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design and Technology Co-Optimization (DTCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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This chapter introduces the development, business model, and market of the global IC design industry. With the introduction of the development process in various stages, it summarizes the development characteristics of China’s IC design industry and the future of this industry. From the point of view of microprocessors, memories, and other chip products, it expounds the supporting role of integrated circuit design industry with respect to the computer industry, and vice versa, the market guiding of the role of the computer industry to the IC design industry. Finally, it is emphasized that IC manufacturing is the basis of chip design and the need of co-development among design and manufacturing teams. Keywords

IC design industry · Business model · System support · DTCO

S. Yin (*) Institute of Microelectronics, Tsinghua University, Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_34

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Overview of Global IC Design An IC design company is also known as a fabless design with no wafer fabrication facility (or Fab) in the company [1]. IC design business is the main body or sector in IC industry with the core business in IC design, technical support, and sales of products. IC design companies do not own IC manufacturing facilities, instead, engage with third party for wafer fabrication (or foundries) and packaging and testing services. The sales revenue of the IC design is about 70% ~ 80% of the total global semiconductor industry (or loosely referred to as IC industry). The business model of IC design companies can be generally divided into three types, i.e., “Design House,” “Design Services,” and “IP Vendor,” or combination as in the following: (1) The “Design House” model is mostly adopted by design companies by defining, developing, and designing IC products according to market needs from end users or system companies. Design companies are the owners of these IC products with revenue from product sales. (2) The “Design Services” company design IC products per specs from their customers (end users or system), and also provide services of wafer production, packaging, and testing, from third parties. However, the ownership of the final product belongs to the customer, and the design service company charges a fee for all technical services. (3) The “IP Vendor,” also known as the Intellectual Property Core (IP Core) provider, is engaged in the design and verification of certain important functional circuit modules (i.e., IP cores) in the form as software codes (soft core) or fully verified layout and performance (hard core). These IP cores can be licensed to other design companies (with fees and loyalty) and readily merged into larger IC designs. Such IP vendors are also known as chipless IC company. All the above business models may be combined together, e.g., design companies may also provide design services, and most design service companies also have the ability of providing IP cores. Today’s IC design companies rely heavily on advanced IC design tools. Thus, those companies that develop IC design tools, also referred to as Electronic Design Automation (EDA) vendors, are included in the IC design business. EDA vendors begin to provide not only EDA tools but also IC design services and IP cores in order to effectively promote their EDA tools. Therefore, EDA vendors are also emerged as a kind of fabless design companies. With knowingly the business model of foundry was mature in packaging and testing sectors, a new business model of IC wafer foundry gradually established in mid-1980s. The design, wafer manufacturing, packaging, and test are interdependent and also relatively independent in IC industry chain; this further accelerated the design industry into fast track. After nearly 40 years of development, the design industry is now an important sector in IC industry. According to relevant statistics in 2021 [2], the IC design industry has sales of about 30% of the global semiconductor market. Among the top 10 semiconductor companies worldwide, five are IC design companies. In terms of national and regional distribution, the USA has the world’s largest and accounting for about 68% of global design sales; China’s design sales account for 9%, and China Taiwan alone accounts for 21% of global design sales [2].

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Overview of IC Design in China The establishment of Beijing IC Design Center in 1986 is the first milestone of China’s IC design industry. After more than 30 years of development, the IC design has become the backbone of China’s IC industry. In 2016, the sales of China’s IC design exceeded the sales of packaging and testing for the first time and ranked on top; furthermore, the sales of IC design in Mainland China surpassed Taiwan, China, as the second largest IC design behind the USA from a global perspective. Currently in 2019, there are more than 2000 fabless design companies in China. There are three development stages of China’s IC design industry. The first stage (from 1986 to 1999) was the period when the IC design environment was established and continuously grown to a solid foundation. The characteristics of IC design in this period are that only handful number of companies who started with basic designs and made small revenues. However, these early-established design companies survived and grew as the backbone as a solid foundation for the rising of China’s IC design industry. The second stage (from 2000 to 2010) was a period of rapid development of IC design. The number of companies exceeded 100, and the top sales exceeding CN¥100 million. The design technology level has approached the advanced level to some extent globally. Some excellent companies landed in domestic and foreign capital markets. By 2010, the sales revenue of IC design exceeded CN ¥50 billion. The main features of this period were the establishment of relatively complete ecological environment and a significant increase in industrial scale. The third stage (from 2011 to present) is a period for continuously growing of the IC design industry with high quality for future. The number of design companies exceeded 1000 in 2016, 1600 in 2018, and more than 2000 in 2019. The IC design industrial is continuously growing rapidly in sales (e.g., more than CN¥160 billion in 2016) and expanding the portfolio of IC products with high-quality grade. Currently in 2019, China’s IC design industry is achieving advanced design level internationally with a few outstanding companies among the top 10 worldwide. The IC design industry in China is continuously growing for future Artificial Intelligence (AI) and Internet-of-things (IoT) AI/IoT era. There are six characteristics in the overall development of China’s IC design industry. (1) The first is the industry’s rapid growth. The sales volume of the design industry has increased from about CN¥300 million in 1999 to CN¥164.4 billion in 2016 [3] and to CN¥1045.8 in 2021 [4] with average compound annual growth rate of 45%. Though the annual growth rate in recent years remained above 20%, this growth rate is unique and impressive. (2) The second is the continuously consolidated industrial base. The popularization of the top-down design technology, the control of the market, the improvement of product definition capabilities, the continuous improvement of the industrial chain, and the accumulation of experience of the talent team continue to consolidate the development foundation of China’s IC design industry. (3) The third is the reasonable industrial layout. At present, China’s IC design industry is located at three largest regions, i.e., the Yangtze River Delta region (with Shanghai as the leader), the Pearl River Delta region (with Shenzhen as

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the leader), and the Beijing-Tianjin-Bohai Rim region (with Beijing as the leader). Currently, the development of IC design industry in China’s central and western regions is also very strong, e.g., Xi’an, Wuhan, Changsha, Chongqing, and Chengdu. (4) The fourth is a complete range of IC products, but lack of high-end chips. Though cell phone ICs are among world’s leading level, but most other highend core chips are lacking, e.g., Central Processing Unit (CPU), Digital Signal Processor (DSP), memory, Field Programmable Gate Array (FPGA), and so on. (5) The fifth is the eye-catching performance of outstanding companies and also the low industrial concentration in China. At present, two Chinese IC design companies are among the top 10 worldwide, though the sales ratio of these two accounts for less than 50% of the total China IC industry sales. Compared with that of 80% sales ratio in the USA, the former sales ratio in China is significantly smaller as an indicator of significantly smaller industrial concentration. (6) The sixth is the huge talent gap. At present, the number of employees in the IC design industry is close to 130,000; and it is estimated that the IC design industry will require a total of 300,000 employees by 2020 [5]. It is urgently in need of reforming the IC engineering education policy and training programs. Due to very strong market demand, the development of China’s IC design industry can be expected to be growing rapidly in future years and playing a critical role in IC design. The development of China’s IC design industry will also contribute to the progress of global IC design industry for the benefit of worldwide technology progress.

Supporting Role of IC Design to System The IC products mainly include microprocessors, system chips, memories and application-specific ICs (ASICs), etc., which are the core components of the entire electronic systems as illustrated in Fig. 34.1. The system chip is usually the main micro-processor; and the entire specific functions of system are implemented by external camera, screen, wireless communication components, input/output peripherals, etc. Fig. 34.1 Common structure of entire machine system

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Fig. 34.2 Intel 4004 Processor

Currently, the entire electronic system with specific functions is increasingly complicated and powerful as related to the enhanced performance of components. The microprocessor is the core portion of the entire system. In 1971, Intel developed the world’s first microprocessor (Intel 4004, as shown in Fig. 34.2) with 2300 transistors integrated by using a process node of 10 μm and clock frequency of 108 kHz; its computing power is very limited. Currently at 2018, the microprocessor has accommodated 10 nm CMOS technology node with 256 billion transistors integrated on the chip; the computing power is greatly enhanced. In addition, another core component of the entire system is the semiconductor memory with large memory capacity and read/write speed which is greatly enhancing the performance of the entire system. Since the birth of semiconductor memory, the global market has reached tens of billions of dollars, and the market size in China has reached CN¥180 billion. The advancement of IC design capability not only enhances the functions and performance of the entire electronic system, but also implies a huge impetus to the IC market. The system manufacturer (or system house) is the closest to the end user applications in the IC industry chain. The connection between the entire system and capability of IC components requires the IC design company to perform IC design to meet detail requirements in system and technology for achieving the best performance of entire system. As an important part of the electronic system industry, the IC design companies must serve as the technical link between system

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applications and IC manufacturing and actively supporting the development of electronic systems with IC technology. Currently, China’s IC design industry has established good qualities and capabilities, with some achieved important accomplishments [6]. It is foreseeable that China’s IC design industry will continue to grow and play an increasingly important role in the future.

Design and Technology Co-Optimization (DTCO) The IC industry is an industry closely collaborated by system manufacturers, circuit design, wafer manufacturing, and process equipment and materials. The IC design serves as a link between the wafer manufacturing and system applications. The IC designers and wafer manufacturers should work closely toward a goal of design and technology co-optimization (DTCO) [7]. The IC design industry is at the upstream of IC industry chain with heavy capital and technology intensive. The IC design performs circuit designs of various chips (IC products) according to the requirements from systems; the physical design (layout) needs to follow design rules based on the requirements from the manufacturing technology. The physical design of layout and routing is critical to achieve the desired circuit speed, signal integrity, and minimum chip areas. With the assistance of EDA tools, IC design solutions can be simulated and optimized to achieve the best performance and yield of IC products. The advances in manufacturing processes can also enhance the functional design capability for IC designers by enabling them with more resources or process margins on chip to achieve better performance and higher on-chip flexibility for reconfigurable architecture. As far as the current situation is concerned, though the level of China’s IC design is keeping up with the leading edge, China’s IC chip manufacturing technology is quite lagging behind the leading edge by 2–3 nodes. Therefore, in order to alleviate the demand of domestic importing of high-end ICs, it is urgent to actively develop China’s IC manufacturing technology as one of the major goals in the National IC Industry Development Promotion Outline [8]. In short, the IC manufacturing technology provides the basis for IC design. The advancement of manufacturing process technology can strengthen the design capability; the advancement of IC design technology also leads to new development directions for manufacturing process. Therefore, both the IC design and manufacturing technology need to be progressed in parallel.

References 1. Fabless Company.: https://www.investopedia.com/terms/f/fablesscompany.asp. Accessed 29 May 2023 2. Sales of Top 10 IC Design Companies., https://www.eetasia.com/top-10-ic-design-companiespost-2021-revenue-topping-100b/. Accessed: 28 Oct 2022

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3. Digitimes Research: China IC production value to rise 15% in 2016, https://www.digitimes. com/news/a20160704PD204.html. Accessed 28 Oct 2022 4. China’s IC Sales in 2021, http://en.c114.com.cn/583/a1190738.html. Accessed 28 Oct 2022 5. Talent shortage hampers China’s IC sector., http://www.ecns.cn/news/sci-tech/2018-08-20/ detail-ifyxccrz0968595.shtml. Accessed 01 Oct 2022 6. S.J. Wei, From entirely machine to machine— on the survival mode of China’s integrated circuit design companies. China’s High and New-Technology Enterprise 1, 30–32 (2019) 7. G. Yeric, B. Cline, S. Sinha, et al., The past present and future of design-technology co-optimization, in Proc. IEEE 2013 Cust. Int. Circ. Conf. 22–25 Sept, (2013). https://doi.org/10.1109/ CICC.2013.6658476 8. X. Yu, Analysis of China’s integrated circuit chip manufacturing industry from the ratio of three industries. Application of IC 10, 6–8 (2014)

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Contents Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital IC Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog IC Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer-Owned Tooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Placement and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge Protection Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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This section focuses on the IC design flow and the related process design kit (PDK). The design flow mainly consists of design specifications, circuit schematics, design functional simulation, functional verification, layout (placement and routing, physical verification), and tape-out. The PDK from process C. Huang · Q. Qian (*) · C. Chen · W. Ge National ASIC System Engineering Center, Southeast University, Nanjing, China e-mail: [email protected] J. Cao School of Software and Microelectronics, Peking University, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_35

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manufacturers (foundries) includes the process manufacturing information and the standard cell library (for semi-automatic digital circuit design process). The quality of input/output (I/O) and clock network is an important factor affecting the reliability of ICs. The scaling of CMOS technology leads to power/energy consumption issues. Leakage current is one of the key indicators of nowadays ICs; moreover, the emergence of customer-owned technology (COT) enables design applications with optimized performance of power consumption, layout area, and trade-offs of technical threshold and investment cost. Keywords

Design flow · PDK · Circuit schematics · Simulation · Functional verification · Layout · Power consumption

Design Specifications Design specifications are proposed to bind the designers to normalize their designs. It is generally a type of combinational information such as the work principle of IC, chip architecture, inputs/outputs, electronic characteristics, and programming interfaces of software. The design specification is often shown as documents, algorithms, source codes, system schematics, and so on. Work Principle is a theoretical description about the global and local functions of the ICs. It is usually showed as mathematical formula, physical performance, state machine, high level models of digital and analog-mixed signal circuits design, and IPs to be embedded. The power, performance, and area (PPA) of the chip design is generally specified. Chip Architecture includes the software and hardware architecture of ICs. The hardware architecture describes the standards about the embedded CPU, on-chip or off-chip memory, algorithm accelerating engine, interrupt controller, system bus, clocks, peripheral interfaces, and so on. The software architecture describes the standards about the hardware abstraction layer, operating system, software communication protocol stacks, and application software definition. Chip Architecture is often showed by top-down design diagrams to describe the internal modules and their interfaces in the chip. Input/Output defines the input and output signals of the target IC, the timing sequence with respect to other chips, the clock pins (pads), power/ground pads, and chip package specification and size. Programming Interfaces of Software describes the definition of programmable registers of chip, such as the address and meaning of registers, hardware peripheral driver, the definitions of the interface functions of hardware abstraction layer, scheduling strategy of operating system, memory distribution strategy, software communication protocol stacks, and so on.

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Design Flow The design flow in VLSI is the sequence of processes/steps involved in designing an IC [1–4]. Because the design complexity increases significantly, the design flow can be divided into several stages or steps. Usually, there are mainly two design flows, which are the digital IC design flow and the analog IC design flow.

Digital IC Design Flow The digital IC design flow mainly includes steps such as system design, logic design, logic synthesis, physical design, physical verification and tape out, etc. As shown in Fig. 35.1, the physical design can be divided into steps, such as data import, floorplan, placement, clock tree synthesis and routing, etc. Iteration is necessary in the digital IC design flow. For example, if the simulation results in physical design cannot meet the specification, the digital IC has to be redesigned in the logic design stage; if the resources cannot be satisfied in routing, the floorplan has to be repeated for more appropriate outcome. Multiple iterations of design flow should be avoided as much as possible in digital IC design.

Fig. 35.1 The digital IC design flow with the physical design divided into more steps

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The specification in the digital IC design flow is used to specify the functions and performances of chip undertaken according to the requirement from the users. In the step of logic design, the logic operations of the design that represent the specification are derived and tested in Register Transfer Level (RTL) description using Hardware Description Language (HDL). Logic synthesis is a process which turns the RTL logic circuits into a design implementation in terms of logic gates. Meanwhile, the latency of logic gates, area, and power consumption are optimized in this process. Physical design is based on a gate-level netlist which is the end result of the logic synthesis. At this step, circuit representations of the components (devices and interconnects) in the design are converted into geometric representations of shapes. This geometric representation is called IC layout. Physical design is usually split into data import, floorplan, placement, clock tree synthesis, and routing. In the step of data import, the netlist generated in the logic synthesis, the script containing the timing constraints, and the libraries provided by the foundry are imported into the EDA tool environment. The floorplan is a process of placing input, output, macros, and core modules in the chip. The placement is a process of placing standard cells automatically according to data import files. In the step of clock tree synthesis, buffers and inverters are inserted along the clock path to balance the skew and minimize the delay. Routing is a process of adding wires automatically to properly connect the placed components while obeying all design rules. The physical verification is a process whereby the layout of IC is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Verification involves design rule check (DRC), layout versus schematic (LVS) and XOR (exclusive OR) check, antenna checks, and electrical rule check (ERC). The tape out is the final design step for IC before they are sent for manufacturing.

Analog IC Design Flow Different from the digital ICs, the design flow of analog IC mainly includes stages such as specification, circuit design, layout design, layout verification, and tape out, as shown in Fig. 35.2. In the step of circuit design, analog circuit is designed by transistors directly according to the specification. Meanwhile, the function and performance of the analog circuit is verified with EDA tools, such as SPICE simulator. The layout

Fig. 35.2 Analog IC design flow

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design is a process drawing the geometric representation of analog circuit according to the design rules. The layout verification is a process before tape out, and it uses EDA tools to verify the layout design of IC, which also involves DRC, LVS, ERC, etc. With the continuous improvement of integration, the cost and cycle of IC design have dominated the cost and cycle of product, especially VLSI products. The EDA tools have become the key of improvement in the IC design efficiency. The trends of digital IC design include but not limit to system-level design, design for manufacturability (DFM), and design for yield (DFY). The EDA tools used in analog IC show their trends in high level abstraction and new technology application, such as deep learning.

Process Design Kit Process design kit (PDK) is a set of process files which describes information related to IC design and manufacturing process; it contains device information, process information, physical rule information, and so on. PDK is the link between process technology and design. PDK was first proposed by Cadence, and implemented in analog circuit design platform Virtuoso based on SKILL language [5]. It usually includes design symbol, device model (SPICE), parametric cell (PCell), technology file, and physical verification rules document, as shown in Fig. 35.3. Design symbol is the schematic symbol of the device; it covers the device’s port information typically, such as the source electrode, drain electrode, and gate electrode of metal oxide semiconductor; the main parameters that affect the performance of the device, e.g., the channel length and width; and number of fingers for layout. Device model (SPICE) refers to the method of describing the voltage-current relationship of devices (MOSFET, triode, and passive components) based on mathematical equation, equivalent circuit, and process data fitting, which provides simulation model files for chip designers and is the basis of transistor level simulation verification. To meet the needs of different simulation tools, process design packages usually contain HSPICE model, Spectre model, and sometimes other model(s). Meanwhile, in order to accurately predict the distribution of chip performance parameters, the device models include process corner analysis model and Monte Carlo analysis model. Parameterized Cell (PCell) is the core of the process design package. It is written with SKILL language (based on popular artificial Lisp language) and is a parameterized layout file that meets the inspection of layout rules and circuit layout consistency. PCell avoids repeated creation of unit layout and simplifies maintenance of unit layout, making layout design convenient and fast. For example, when designers call CMOS parametric unit, device layout of different sizes can be obtained only by modifying property parameters. Technology File refers to the process used in layout design and verification documents; it includes the process feature sizes, types of devices, GDSII design data layer and process mapping, attribute definition of design data layers, design

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Fig. 35.3 Main components of process design kit (PDK)

rules, electrical rules, display color definition, automatic layout rules, and graphical format definition. Sometimes technology file is also called process file in the application field. Physical Verification Rules File includes layout design process rules check (DRC) file, circuit layout versus schematics (LVS) file, layout parasitic parameter extraction (XRC) file, etc.

Customer-Owned Tooling As the fabless design houses were seeking foundry business support model, some integrated device manufacturers (IDM), who originally owned fab facility, have transferred the part of their owned technology and related electronic design automation (EDA) technology to the foundry and EDA companies. This behavior supports the processing and manufacturing of some special products in these companies that

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occur in the process of the transition from IDM to the foundry; therefore, the customer-owned tooling (COT) model has been established. As the widespread acceptance of foundry model, some large companies supported by foundry (such as IBM and Qualcomm, etc.) have developed and formed a specific process technology for their own products in the advanced nodes, such as 65 nm, 40 nm, 28 nm, and 14 nm technology, to support more optimized product manufacturing in performance, consumption, and area. Hitherto, the COT is usually referred to the special process platform based on the custom process, circuit IP, design flow, and methodology, which is provided by the foundry for some special customers (generally large or giant company). The counterpart to COT is the alleged foundry-owned tooling (FOT), namely, a standard or common platform providing for customer is developed by foundry’s standard process and technique. The FOT emphasizes universality and standardization and providing customers with standard processes, IP (including the IP developed by third parties), and design process and methodologies (PDK) based on the mainstream EDA tools. Custom process: The FOT platform adopts the general process supplied by foundry; its process specification fulfills the design demands in area, performance, and consumption for most customers, but cannot satisfy the special process demands of some special customers such as high-performance server CPU, high-end smartphone SoC chip and high performance FPGA, etc., in high performance, low consumption, or specific IC aspects in comparing with COT platform. In this condition, some customers (generally large or giant company) often request for COT (custom process), such as add transistors with more lower threshold to increase speed performance, customize extremely high density SRAM bit cell to reduce the area and cost of SRAM-dominated chip, and customize eDRAM bit cell to decrease the consumption and area of memory. Custom circuit IP: The IC design method supported by FOT platform generally adopts the foundry provided circuit IP to design chips product, such as standard cells, I/O cells, and SRAM. However, some IC enterprises often present the COT requirements of adopting custom circuit IP considering different factors. For example, the FPGA enterprise often customizes SRAM cell and LUT cell to satisfy the FPGA product demand; some large companies often customize all the underlying cells due to the convenience of product transplanting between different nodes; the CPU company often customizes part of dynamic logic library to apply for highperformance data path design. The entire COT platform generally adopts custom circuit IP. Custom design process, EDA tool, and design methodology: Under the FOT platform support, the research and development of IC design method and process are based on mainstream EDA tool which satisfies the demand for most customers’ IC product design. However, the design method and process supported by COT platform of some large companies are often developed based on the in-house EDA tool to enhance the design efficiency and success rate. The current tendency is to use mainstream commercial EDA tool in COT designing. The COT has some advantages that can design products with more optimized performance, consumption and area, but the disadvantages are that it has higher technology threshold and larger

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investment cost, so this technology is generally owned by large companies (such as IBM and Qualcomm). The other characteristic of COT is that the process technology owner can assign its process to different foundries for manufacturing, which can acquire the competitive advantage in wafer manufacturing cost and spread risks.

Standard Cell Library Standard cell library is the basis for modern large-scale digital IC design. It is a collection of semi-customized circuit with a fixed-height and variable-width and used as building blocks in IC design. Standard cell library includes combinatorial logic cells, sequential logic cells, input/output (I/O) cells, and special cells. Combinational logic cells mainly comprise inverters, buffers, simple logic gate circuits, and composite logic gate circuits. Sequential logic cells mainly comprise registers and latches; memory cells fall into sequential cell type, they have different height and width, and they do not belong to standards cells. I/O cells comprise input cells, output cells, and input/output bidirectional cells. Special cells comprise delay cells, layout filling cells, voltage clamping cells, etc. In order to accommodate various designs and to optimize the performance, power consumption, and area of the chip, the same type of cells in the cell library includes different types of variants: (1) drive strength refers to the ability of the cell to drive a larger cell or multiple cells (Fanout >1). Cells with different drive strength can be selected according to the load during logic synthesis or place and route. (2) Doubleheight or triple-height cells refer to the height of cells. At the beginning of the design, cell library of high speed and/or high density and/or ultra-high density can be selected according to the chip’s demand. (3) Transistor threshold refers to the threshold voltage of transistors in the cell. Cells with high, normal, and/or low threshold can be selected to balance the path delay and leakage current during the place and route process or logic synthesis. Standard cell library view refers to the cell model used by different EDA tools in the design flow, including transistor netlist, symbol library, Verilog model, layout model, timing (and) power library, and topology (FRAM) view. For example, Fig. 35.4 is the cell library view of the inverter, wherein transistor netlist describes connections between the cell transistors, the diodes, and the parasitic resistances and capacitances for transistor-level simulation and physical verification. Symbol library model describes the symbol pattern of cells for schematic diagram input. Verilog model describes the function and input/output of the cells. Layout model describes the layout level and the shape of standard cells for merging the whole chip’s layout. Timing power library describes standard cell’s delay data, driving strength, operating conditions, area, timing, and power for synthesis, and place and route. Topology view describes the information required for cell’s physical design, including PINs location and orientation. Standard cell library seamlessly interfaces with EDA tools to effectively support the automated process of chip design.

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Fig. 35.4 Cell library view of the inverter

Circuit Schematics The circuit schematic, also known as the schematic diagram, is a diagram of components and their connections drawn using standardized symbols. It represents the structure of various parts of the IC, component parameters, and so on. Early ICs were all designed with circuit schematics. With the rapid expansion of the scale of digital IC, most digital circuits have adopted more abstract and efficient hardware description language design, while most analog circuits still maintain the traditional schematic design style. As the design scale of IC expands, the circuit schematic generally adopts hierarchical design, and several sub-schematic diagrams are included layer by layer. The hierarchical design can simplify the schematic complexity and improve the readability and maintainability of the schematic. According to the description level, it can be generally divided into system layer, module layer, unit layer, and so on. The circuit schematic is mainly composed of four parts: component symbol, node, connection, and annotation. Symbol: Indicates components in the circuit, e.g., resistors, capacitors, inductors, diodes, and transistors. The component symbol remains the same number of pins as the actual component has one-to-one correspondence. Schematic input software allows designers to use specialized or custom component symbols, as well as generate schematic derived symbol for high-level schematic to call. Node: Refers to the connection relationship between component pins or wires. Each node in the circuit schematic has a unique network tag, also

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known as a network node. All component pins and wires connected to the same node or labeled with the same node name are all connected to each other. Wire: Indicates the electrical connection in the actual circuit. It can represent a single wire or a bus. On the layout of the actual IC design, it refers to the interconnection of multiple metal wires. In addition, the nodes or connections of the same network label indicate that they are electrically connected even if there is no actual connection in the circuit schematic. Annotation: Refers to all the text in the circuit diagram, often used to mark the component name, parameters, schematic drawing information, design instructions, and other information. Figure 35.5 is a typical IC schematic, in which Fig. 35.5a is the top-level circuit schematic diagram, Fig. 35.5b is one of the sub-circuit diagrams of Fig. 35.5a, and its layered nesting constitutes a hierarchical

Fig. 35.5 Hierarchical design schematic and main components. (a) Top circuit schematic, (b) sub-circuit of “ENABLE” in (a)

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schematic design. In Fig. 35.5b, main parts such as component symbols, nodes, wiring, and annotations constituting the circuit schematic are attached.

Input/Output Cells The input/output (I/O) cells are the units which receive off-chip input, or send output signal to drive the off-chip load in the IC. The connection of the I/O units and the pins in the integrated circuit is shown in Fig. 35.6. In logic view, a I/O has a connection “point” thus is called a “I/O pin”; typically by adding a pair of drivers (p-driver to connect to Vdd, and n-driver to Vss) to a pad, an I/O is now called “I/O cell” or “I/O pad.” The I/O cells can be divided into analog I/O cells, digital I/O cells, and power supply cells; according to the signal types, can be divided into input I/O cells, output cells, and bidirectional cells. A standard bidirectional I/O cell generally includes an input buffer, an output buffer, and an ESD protection circuit, whose design quality affects the reliability of the integrated circuit. Input buffer. The main function of the input buffer is to convert the input electrical level. The types of the input buffer include the transmission gate, the inverter, the non-inverting input buffer circuit, and the normal phase input buffer circuit with feedback transistor. The transmission gate input circuit is controlled by the enable signal and supplemented by a protection network. The inverter input circuit consists of a CMOS inverter and a protection network for input inverting and level shifting. The non-inverting input buffer circuit is composed of protection network, level shifting circuit, and normal phase input driver. The normal phase input buffer circuit with feedback transistor is mainly composed of two cascaded inverters. Output buffer. The main function of the output buffer is to improve the drive capability of output signal, especially for large load, where the output driver should provide a sufficiently large drive current to minimize the total delay of the buffer. The design technique of the output buffer circuit includes the inverter chain and the

Fig. 35.6 Connection of input/output units with pads in integrated circuits

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Fig. 35.7 ESD protection circuit

MOS transistor with large ratio of width and length. In CMOS ICs, the inverter chain composed of multi-stage inverters is commonly used as the output buffer circuit, whose delay could be minimized by optimizing the number of the stages in inverter chain and the inverter size. In addition, the transistor with comb-like (interdigitated) structure and large ratio of width and length is advantageous for further reducing the delay. ESD (electrostatic discharge) protection circuit. The functions of ESD protection circuit can be divided into input protection, power protection, and full chip protection, which prevent the instantaneous high pulse current generated by static induction from damaging the chip, as shown in Fig. 35.7. The ESD protection circuit at an output pad is generally made up of inverters with large-sized transistors. The ESD protection circuit at input pad includes a dual diode protection circuit and a vertical bipolar transistor protection circuit, which has the advantages of small area, high driving current, and low clamping voltage. The power ESD protection circuit can be implemented with a gate-grounded NMOS transistor or by a circuit that detects ESD variations. The full-chip ESD protection circuit generally places a power-to-ground ESD clamp protection circuit on each side of the chip.

IC Clock The IC clock is a time reference of the digital circuit and its unit is in Hertz. It is a periodic signal sampled and updated by the sequential logic circuit in the synchronous circuit. The clock signal can be generated by a crystal oscillator, an RC oscillator, or a phase-locked loop (PLL) circuit and transmitted to all timing units, i.e., sequential gates (including registers, latches, etc.) through a clock distribution network. The clock distribution network, also known as the clock tree, refers to the

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circuit that transmits clock signals from the source to all nodes or so-called clock tree leafs. The key metrics are clock jitter, clock skew, clock latency, and clock tree power. Modern ICs are large in scale, and the clock tree power consumption of all timing units is also increasing. In some high-performance processors, the clock tree power consumption exceeds 30% of the total power consumption of the chip. The main types of clock trees are (1) H tree, clock buffer layout similar to H type; (2) Fishbone structure, clock buffer layout similar to fishbone shape; (3) Mesh structure, the clock is driven by a clock driving unit around the circuit and is wired in a grid-like top layer. In addition, there is a hybrid structure in which a plurality of structures is combined. The main indicators that characterize the clock are clock period, rise time, fall time, duty cycle, clock latency, clock jitter, and clock skew. Clock Period, also known as the oscillation period, is the reciprocal of the clock frequency. Due to the setup time constraints of the timing logic, there is a minimum clock period constraint, which is the highest operating frequency at which the circuit can operate. Rise Time and Fall Time refers to the conversion time of the clock edge. The rise time is generally defined as the time required for the clock signal level to vary from 10% to 90% (or derated to 20%–80% or to 30%–70%). The fall time is similar. Duty Cycle is the ratio of the high level of the clock to the clock period. Different types of timing circuits have different clock duty requirements. Register-based designs have no explicit requirements on clock duty cycle, and latch-based designs require higher clock duty cycles. Clock Jitter is a random variation of the clock edge on a node. There are two types of clock jitter: deterministic jitter and random jitter. Deterministic jitter can be divided into periodic jitter, data-dependent jitter, and duty cycle jitter. Random jitter is unpredictable and irregular jitter caused by device noise, power supply time-varying noise. Clock Latency is the average delay from the clock source to the timing logic (registers, latches, etc.). The clock delay is affected by the clock tree topology and the clock tree driver. Clock Skew is the clock edge difference d ¼ ti–tj between any two timing logics i and j due to differences in the transmission path, process variation, environmental effects, and signal load during clock signal transmission (see Fig. 35.8). The clock skew can be divided into positive deviation and negative deviation. When the clock routing direction is the same as the data pipeline direction, the positive deviation is d > 0. Otherwise, the deviation is negative.

Leakage Current With the advancement of IC technology, the threshold voltage (Vt) of CMOS devices is continuously decreasing, and the leakage current through transistor channel is increasingly serious. Static power consumption is an important factor limiting products standby time. The leakage current of a MOS device can be divided into four parts: junction leakage (I1), subthreshold (Sub-Vt) leakage (I2), gate-induced drain leakage (GIDL, I3), and gate oxide leakage (I4I4), as shown in Fig. 35.9.

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Fig. 35.8 Clock source, clock distribution network, and main clock signal parameters

Fig. 35.9 Main leakage current composition of MOSFET

Junction Leakage I1 refers to a small leakage current occurred in a p-n junction at reverse bias, e.g., the junctions of source and drain and the substrate. The reverse biased p-n junction leakage current includes the current generated by the bulk diffusion and thermally generated carriers in the space charge region. The junction leakage current is related to the bandgap of the semiconductor material, operating temperature, and the area of the source and drain regions. Subthreshold (Sub-Vt) Leakage I2 refers to the weak source-drain channel current when the MOS device is in the off region (Vgs < Vth). At this time, the MOS device is in a sub-Vt region or a weak inversion region. The sub-Vt leakage current can be expressed as: V gs

V ds

I sub ¼ I s enkT =q 1  enkT =q ð1 þ λV ds Þ

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Where Is is the leakage current when Vgs ¼ 0, which is related to the carrier mobility and the effective width of the transistor; n is the empirical parameter, which is about 1.5. After the ideal MOS transistor enters the cut-off region, the channel current should drop rapidly. For this purpose, a sub-Vt slope (or referred to as sub-Vt swing) is defined as S ¼ n(kT/q)*ln(10). The physical meaning is that in order to reduce sub-Vt leakage current by a factor of 10, the Vgs needs to be reduced by one S value. The smaller the S, the closer the MOS transistor is to the ideal switch. Gate-Induced Drain Leakage (GIDL) I3 refers to a current generated by bandto-band tunneling (BTBT) effect of high-concentration carriers at reverse biased p-n junction under the gate-drain overlap region as induced by the gate electrical field. The tunneling current generated by GIDL is exacerbated by the increase in traps at the Si/SiO2 interface under the gate-drain overlap region by plasma processing, implant, etc. Gate Oxide Leakage I4 refers to the current that leaks into the substrate through the tunneling effect of the gate oxide layer. As the feature size of MOS devices becomes smaller, the gate oxide layer becomes thinner and thinner (the equivalent SiO2 thickness below 28 nm node is only 1.2 nm), and some electrons have an opportunity to enter the substrate through the oxide layer due to direct tunneling effects. Materials with high-k dielectric constants, such as hafnium (Hf) metal oxides and zirconium (Zr) metal oxides (Hf-dioxide, Zr-dioxide), help to greatly reduce gate oxide tunneling leakage current (by the physically thicker gate dielect at same equivalent SiO2 thickness), so that the gate oxide leakage current can be ignored in advanced CMOS node with high-k processes. For the CMOS process, the sub-Vt leakage current is the major part of the quiescent current. As the semiconductor device enters the nanometer era, the sub-Vt leakage current deeply affects the IC design. The designer uses multiple power domains, power gating, and multi-threshold CMOS (MTCMOS) to achieve low-power designs.

Power Consumption The power consumption of an IC usually refers to the energy consumed by the circuit per unit time, that is, the power required for operating the circuit. The power consumption of the IC at standby state is called standby power consumption, which is especially important in systems at sleep mode for a long time, e.g., the wearable devices. The maximum power consumption with all active circuits in operation in a short time is called peak power consumption, which affects the system encapsulation and heat dissipation. The average energy consumption of multiple operating states over a long period of time is called average power consumption, which determines the battery life for powering devices. As the pitch size of the IC process is reduced to the nanometer level, the power consumption of the ICs has become a key parameter as its operation speed and area size, which directly affects the reliability of the ICs, the chip package and heat dissipation cost, the battery life

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time of portable system, etc. Thus, low-power technology has become one of the driving forces of the development of IC technology. At present, the CMOS process is the dominant process for VLSI, and its power consumption is mainly composed of dynamic power and static power. Dynamic Power refers to the power consumption as required by the logic operation for switching the node states. This power consumption consists of two parts. One part is used for charging and discharging the load capacitance (including the interconnect capacitance and the transistor parasitic capacitance). It is also known as AC switching power consumption and can be expressed as: P¼ i

f clk Ci V 2DD ai

where VDD is the supply voltage, Ci is the node equivalent capacitance, αi is the node switching activity factor, and fclk is the clock frequency. The second part is the short circuit power consumption, which is caused by the momentary short-circuit current through the p-type and n-type MOS during the gate bias transition. The short-circuit power consumption is related to the output load and the flip speed of the circuit node. The power loss of static CMOS circuits is dominated by the dynamic power consumption. Static Power refers to the power consumed by the IC at standby mode. For the CMOS digital circuits, it is mainly caused by the leakage currents of the MOSFET, including sub-Vt leakage current, gate induced drain leakage (GIDL) current, gate oxide leakage current, and junction leakage current, in which the sub-Vt leakage current is the main portion. For the analog ICs, the static power is generally resulted from the operation bias current. Low-power design technology is now one of the mainstream technologies for large-scale digital IC design. The widely used technologies include Clock Gating, Power Gating, and Multi-threshold CMOS (MTCMOS) and sub-Vt or NearThreshold Circuit (NTC) design techniques.

Design Simulation Design simulation is for predicting circuit behavior by EDA simulators before fabrication. By mathematically modeling the circuit electrical characteristics, stimulus is applied to observe the circuit’s response. The results are used to guide designing and optimization. Circuit simulation can be classified into transistor level simulation, gate level simulation, and register transfer level (RTL) simulation according to the objects. Based on identical simulator kernel, pre-simulation and post-simulation are used to simulate the schematic level and physical level, respectively. Transistor level simulation is based on establishing the netlist of circuit components at transistor level which includes transistors, capacitors, resistors, and inductors. The netlist is transformed into nodal equations and loop equations. The

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current and voltage of each node are solved after algorithmic convergence. For facilitating circuit analysis, DC analysis, transient analysis, and small-signal analysis are generally provided to obtain the gain, noise, frequency characteristics, delay, and other circuit parameters. Gate-level simulation is based on establishing the netlist of circuit components at gate level which includes logic gates, flip-flops, and other components. The interactions in the netlist can be transformed into Boolean equation, Truth Table, or Karnaugh map. The nodal logic values are obtained by deducing the transmission of the excitation signals along the circuit paths. In order to facilitate circuit analysis, the simulator also provides system tasks, system functions, and other means to assist simulation. Gate-level simulation is essentially event-driven. Each simulation cycle processes one triggered event. Recalculation cycles terminates till steady state appears. The event triggered simulation provides both design assistance and timing checking. At the same circuit scale, the complexity of simulation is significantly lower than that of transistor-level simulation. Register Transfer Level (RTL) simulation is based on establishing the netlist of circuit components at behavioral model level, which includes circuit registers, arithmetic units, and other large-scale functional modules. These descriptions are transformed into behavioral level models such as signal flow graph, truth table, finite state machine, state graph, and state table. It is similar to gate-level analog deduction of excitation signals to obtain the logic values of internal variables, so as to obtain circuit behavior. Compared with gate-level simulation, RTL simulation is also based on event-driven simulation method, but the abstraction level is higher and the simulation efficiency is further improved (see Table 35.1). Table 35.1 Comparison of design simulations Simulation level Transistor level

Objects Transistors capacitors Resistors Inductors

Gate-level

Logic gates Flip-flops Logical components

Register transfer level (RTL)

Circuit registers Arithmetic units Large-scale functional modules

Modeling Circuit nodal equations Loop equations Boolean equation Truth Table Karnaugh map Signal flow diagram Sequence diagram Truth table Finite state machine State diagram

Application Designing and optimization of analog circuits and digital standard cells

Function and system-level behavioral verification of digital circuits

System behavior level design and verification

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In the early days of IC development, circuit simulation mainly relies on manual calculation, theoretical analysis, and experimental boards. In 1972, the University of California, Berkeley, introduced the SPICE (Simulation Program with Integrated Circuit Emphasis) simulation tool, which is the beginning of practical transistorlevel computer simulation replacing manual work. In the 1980s, the growth of integration scale and the improvement of computer performance led to the emergence of gate-level and RTL-level simulation tools. In recent years, with the increasing complexity of mixed digital/analog circuits, some more efficient multithreaded parallel simulation accelerators such as APS (Advanced Parallel Simulator) have become mature into practice, which significantly improves the design efficiency.

Functional Verification Functional verification is the task of verifying that design circuit conforms to specification. Functional verification is a complex task which participates in many stages of IC design flow. According to the approach of the verification, functional verification can be separated as simulation verification, FPGA verification, and formal verification. 1. Simulation verification is the act of proving the correctness of design circuit by measuring the response after user-defined stimulus in EDA environment. The simulation verification, which is performed at RTL, is called pre-simulation. The simulation verification can also be performed after logic synthesis, but the simulation result does not contain the information about the delay interconnect. The post-simulation is performed after physical design, and it can be used to verify the performance of design circuit more accurately. 2. FPGA verification is the act of proving the correctness of design circuit with FPGA devices and FPGA supported tools, such as logic synthesis, floorplan, and routing. Compared to the simulation verification, FPGA verification has the advantage of fast verification speed, co-verification of hardware and software, and other scenarios for long-term verification. But FPGA verification has the challenge of observability for debugging. 3. Formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics. One approach of formal verification is model checking, or property checking, which consists of a systematically exhaustive exploration of the mathematical model. Another approach of formal verification is equivalence check, which is commonly used to formally prove that two representations of a circuit design exhibit exactly the same behavior. The coverage of formal verification can achieve 100%, but it cannot verify the performance of circuits.

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Fig. 35.10 Digital integrated circuit verification process

The verification of IC exists at many stages of design flow, as shown in Fig. 35.10. In RTL design, the pre-simulation is used to verify consistency between the design and requirement. In order to improve the efficiency of simulation, the stimulus is usually described in behavior level. The test cases in simulation are used as many as possible to search the defect of RTL design. FPGA is usually used in verification of VLSI circuit design for regression and stress test. In synthesis and physical design, simulation verification is used again to verify consistency between the design and requirement. Meanwhile, formal verification is used to prove the logical equivalence between netlists. After physical design, the post-simulation is used to verify the correctness of circuit design by adding the delay of interconnect with parasitic parameters into the netlist.

Placement and Routing The placement and routing (or place and route) of digital circuits is automatically done by software. For analog IC design, the requirements of placement and routing are different from the digital IC design. The integration of analog circuits is small. As a result of the analog signal, it is necessary to deeply consider the parasitic effects of transistors, avoid the parasitic and coupling effects between placement and routing, meanwhile, weight a series of parameters, such as the size of transistors. So the area of the analog circuit is usually large, the placement and routing need to be done

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manually. The following is mainly to explain the automatic placement and routing of digital circuits. Placement, also known as cell placement, is the physical design of arranging the location of each standard cell on the chip in a logical netlist and meeting the design rules. The placement is usually judged by the method of routing congestion, static timing, noise, and power analysis. The main indicators of the placement include routing congestion degree; timing constraints (set-up time constraints and hold time constraints); and maximum voltage drop in the chip. The main methods of placement are usually divided into global placement and detailed placement. The global placement uses the analytic algorithm and the image segmentation method, combined with the geometric method of fast calculation. The detailed placement uses optimization methods such as simulated annealing algorithm. The placement strategy mainly includes the flat placement and the hierarchical placement. The former place all units at one time; the later uses a bottom-up or top-down approach to hierarchical placement. Routing is the process of making interconnect configurations among components, usually after the placement is completed. The principle of routing is to ensure the correct connection among different components, meanwhile complying with certain design rules. Routing should focus on eliminating routing congestion, optimizing timing, reducing coupling effects, eliminating crosstalk, reducing power consumption, ensuring signal integrity, preventing problems in manufacturing, i.e., design for manufacturing (DFM), and improving yield (Yield Enhancement). Routing process includes three steps: global routing and detailed routing. (1) Global routing: it starts with a global plan for subsequent detailed routing. First, set the goal of global routing, and then make specific plans according to the characteristics of the design. For example, the design that needs routing can be a chip or a large custom module. The shape of the chip can be square or rectangular. Global routing should minimize the total length of the connection, distribute the routing evenly, minimize critical path delays, complying timing rules, avoid crosstalk, and keep the bus aggregated. (2) Detailed routing: the routing is among multiple layers of metal that to meet the timing requirement and can automatically search for routing errors and correct errors, or correct routing. Detailed routing must consider all the rules involved (such as density requirements, avoiding crosstalk and parasitic effects, etc.), automatically switch and comprehensively use multiple layers of metal as routing. (3) Routing correction: there are three methods, i.e., automatic correction, progressive correction, and local correction. In general, combined with the actual situation, three correction methods are comprehensively utilized.

Physical Verification Physical verification is used to check whether the designed layout meets the process manufacturing specifications, electrical specifications, and consistence with circuit schematics, including design rule checking (DRC), electrical rule checking (ERC),

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Fig. 35.11 Physical verification examples. (a) DRC verification, (b) ERC and LVS verification

and layout schematic consistency checking (LVS). A verification example is illustrated in Fig. 35.11. 1. DRC rules check whether the layout meets the design rules for manufacturing. DRC rules specify the geometric size and spacing of different graphics in the layout, so as to meet the requirements of mask accuracy and avoid manufacturing risk. Examination items include minimum spacing between graphs, minimum size requirements of graphs, size and spacing of through holes, minimum density of poly-Si and metal, etc. DRC also includes Antenna Check (ANT) to avoid the aggregation effect of free charges on gate oxide layer, which has a risk of the gate oxygen lay breakdown during metal etching. 2. ERC rules check whether the layout meets the electrical rules. ERC tool searches the layout for power supply, ground, and the connection between input/output ports and internal circuits, finds out the following abnormal situations: shorted power supply and ground, shorted output ports, suspended input/output ports, suspended transistor ports, etc. Designers can locate and eliminate the electrical risks according to the coordinates indicated by the ERC tools. 3. LVS checks the consistency between layout and schematic. The LVS tool extracts the transistor level netlist of the layout and compares it with the schematic netlist. The comparison process starts from the input/output ports. A heuristic algorithm searches the connections of each component from transistor level to the top level, seeking the minimum backtracking path associated with the circuit. If a local matching is detected, the matched devices and nodes are marked and identified. If not, the current searching path is terminated and restarts searching process with another path. Finally, matching results are presented in lists and graphics, and inconsistent locations and devices are reported. In summary, as the scale of IC grows by Moore’s law, the number of layout polygons of the whole chip is up to hundreds of millions. At the same time, the number of design rules also increases rapidly with advanced nano-technology in

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developing. DRC rules of advanced technology are up to thousands at 2018, which makes it imperative to improve the efficiency of physical verification. Among all the algorithms, hierarchical physical verification is a promising method to meet both the accuracy and efficiency.

Layout A layout is a planar geometry representation of an IC which is the output of an IC physical design, usually described in GDSII format or OASIS format. The layout consists of multiple layout layers and follows certain design rules. A layout layer refers to the layer that integrated circuit process module abstracts and transforms into conceptualization. Typical layout layers include (1) substrate and well layout layers, usually have p-type (for NMOS devices) and n-type (for PMOS devices); (2) diffusion layout layers (n þ and p+), defining regions where transistors are formed, also commonly referred to as the active region; (3) one or more polysilicon layout layers, which are used to form the gate of the transistor (and also used for interconnections); (4) multiple metal interconnect layers; (5) contact holes and via layouts, used to provide layer-to-layer connections. A layout is a combination of multiple polygons, each of which belongs to a certain layout layer. Design rules are the rules that must be followed by layout layers specified by semiconductor manufacturing plants. Design rules define the minimum size of a graphic in a layout layer, the minimum spacing between graphics in the same layer, and the minimum spacing between multiple layout layers. The design rules for different processes are usually different. Only the layouts that comply with the design rules can ensure that the actually produced IC have predetermined functions and can be mass-produced. Typical design rules include active-to-active-area distance, well-to-well distance, transistor minimum channel length, minimum metal width, metal-to-metal spacing, metal current density, ESD, and I/O design rules and antenna efficiency rules. Typical layout examples of NMOS and PMOS devices with a 40 nm linewidth process are shown in Fig. 35.12; the main layout layers are listed, including poly-Si, active region, via, etc. The main layout design rules are shown in Table 35.2.

Tape-out Tape-out is the process of delivering layout data and project documents to fabrication plants after layout design and verification. Early layout GDSII data is stored on tape, so this data transfer process is named Tape-out. Project documents include basic project information, manufacturing information, and layout information. Based on layout data and project documents, mask graphics is made and wafer manufacturing begins. The storage formats of layout files are GDSII and OASIS. The basic data structure of the layout file is module, each of which is composed of several geometric figures

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Fig. 35.12 Typical layout examples of NMOS and PMOS devices at 40 nm process node Table 35.2 Main layout design rules No. 1 2 3 4 5 6

Description Minimum width of transistor channel Minimum width to N+/P+ active Minimum width between via and metal edge Minimum spacing between vias Minimum spacing between metals Minimum spacing between active

Design rules(nm) 40 80 25 80 70 80

named graphic elements. Graphic element is composed of 16 bits data blocks, which define layer information such as data type, coordinates, line type, width, angle, polygon type, scaling ratio, coordinates, row and column number, etc. The project information mainly includes application, process information, layout data information, IP usage statement, and related information of process design package (PDK). Manufacturing information describes process specifications, including supply voltage, transistor types, number and thickness of metal layers, usage of special devices, and mode and quantity of chip delivery. Layout information describes the information of all layers in the layout file, mainly including layer design number and layer mask number. The fabrication plant generates the mask graphics after a certain mapping algorithm. After the layout data and the above documents transferred, the mask factory maps the layout data to mask graphics by several means: (a) direct mapping, i.e., the layout layer and the photolithographic layer are identical, such as the metal layer; (b) logical operation, through certain logical operation, multiple layout layers are used to generate the required photolithographic layout. For example, n-diffusion region and p-diffusion region are complementary in the layout data. Therefore, n-diffusion lithography layers can be obtained logically from p-diffusion layers.

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(c) Graphic scaling, i.e., the injection layer mask of transistor gate is amplified from poly-Si layer. Mask data includes not only circuit graphics but also some auxiliary graphics needed in chip manufacturing, such as version identification, photolithography alignment markers, exposure information markers, slicing graphics, and optical alignment marking graphics.

Electrostatic Discharge Protection Design Electrostatic discharge (ESD) is a physical transfer process of electric charge between different potentials. When the ESD current flows through the core of integrated circuit (IC), it may cause irreversible physical damage to IC. The ESD protection circuit can effectively prevent the damage to IC under ESD current. The current curves vs. time in ESD models are shown in Fig. 35.13. The ESD models mainly include human body model (HBM), machine model (MM), and charged device model (CDM) [6]. (1) HBM is a transfer process of electric charge between the human body with static electricity and chips. The feature of model includes long duration of time which may cause physical damage to IC due to overheating. (2) MM event is a transfer process of electric charge in which the metal with static electricity is in contact with the pin of IC. The static charge in the metal discharges through the pins of IC, and the peak of the transient current can reach ampere level, leading to failure of IC due to overheating. (3) CDM event is a transfer process of electric charge between IC with static electricity and low-resistance objects. The rise time and duration of CDM event are short, which often causes the overvoltage on IC pins and breakdown of gate oxide. ESD stress is a transient event of high current in a short period of time; the relevant ESD protection circuit can be triggered under the high current event. Further, ESD protection circuits should have the following features: (1) The ESD protection circuit should have fast triggering speed under ESD stress to ensure the

Fig. 35.13 Transient currents of different ESD models

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safety of gate oxide inside IC under high transient overshoots. (2) The robustness of ESD protection circuit must be high enough to ensure that the protection circuit itself is not physically damaged under high energy ESD stress. (3) The clamping voltage of the ESD protection circuit should be low enough to ensure that the IC core is not physically damaged under ESD stress. (4) The ESD protection circuit should not influence the normal operation of the chip. In addition, the leakage of the ESD protection circuit should be low enough to have latch-up immunity and the protection circuit should not be triggered by the normal operation signal of IC. The design of the ESD protection circuit is different from that of the conventional IC design involving multiple stages from design to manufacturing. The optimization of the ESD protection circuit should start from three aspects of process, device, and circuit. The complexity is mainly due to the high current and voltage behaviors of semiconductor devices under ESD stress, which cannot be predicted by conventional IC simulation tools and models. Therefore, ESD design of protection circuit usually requires designers have a deep understanding of ESD characteristics and skills to establish the corresponding ESD models based on these understanding. ESD testing of IC requires a set of equipment that is independent of conventional IC functional testing. Transmission line pulse (TLP) is often used to verify the performance of the ESD protection circuit. In addition, for HBM and CDM events, the industry also has the mature test standards and corresponding equipment to characterize the performance of ESD protection circuits.

References 1. M.J.S. Smith, Application-specific integrated circuit (Addison-Wesley Publishing Company, Menlo Park, CA, USA, 1997) 2. D. Jansen et al., The electronic design automation handbook (Springer, 2003), pp. 398–420. https://doi.org/10.1007/978-0-387-73543-6, ISBN 978–14–020-7502-5 3. C.-Z. Chen, X. Ai, G.X. Wang, Physical implementation of digital IC design (Science Press, Beijing, 2008) (Chinese book series 2 of 5, ISBN 978-7-03-022031-8) 4. A. Kahng et al., VLSI physical design: from graph partitioning to timing closure (Springer, 2011), p. 10. https://doi.org/10.1007/978-90-481-9591-6, ISBN 978-90-481-9590-9 5. J. Ferguson, The process design kit: protecting design know-how. semiconductor engineering, deep insights for the tech industry. Posted 08 Nov 2018. https://semiengineering.com/theprocess-design-kit-protecting-design-know-how/ 6. D.Y. Hu, C.-Z. Chen, Reliability aspects of advanced IC technology with ESD and anti-radiation capabilities. ECS Trans. 60(1), 1185–1190 (2014)

Digital Integrated Circuit Design

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Jun Yang, Peng Cao, Weiwei Shan, Longning Qi, and Xinning Liu

Contents Digital IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Description Language (HDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Floor Planning and Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Level Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

This chapter introduces the classification, design methods, and main features of digital ICs. Circuit partitioning is a valuable method to reduce the complexity of VLSI design, in which hardware description language (HDL) is used to model the concurrent execution process of hardware circuits, including Verilog and VHDL. High-level synthesis (HLS) transforms the behavioral-level description into circuit structure descriptions under certain constraints. Following the logic synthesis that transforms the register transfer level (RTL) description into the gate-level structure description, various methods are used to implement and verify a digital IC design, such as formal verification, the mathematical method to analyze circuit behavior to find circuit functional error, timing analysis to ensure the normal operation of the circuit including setup and hold time constraints, floor planning to place the main modules of the design to meet requirements for die size, as well as timing closure and routing. In addition, design for testability (DFT) is used to J. Yang (*) · P. Cao · W. Shan · L. Qi · X. Liu National ASIC System Engineering Center, Southeast University, Nanjing, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_36

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detect chip manufacturing defects by inserting extra units without changing the circuit function, and the hardware emulation uses dedicated hardware to perform circuit functions for the circuit function verification, etc. Keywords

Digital integrated circuits (ICs) · Circuit partitioning · Hardware description language · High-level synthesis · Logic synthesis · Formal verification · Timing analysis · Floor planning · Hardware emulation

Digital IC Digital ICs are digital logic circuits based on Boolean algebra for processing digital signals. In 1960s, Gordon Moore foresaw that the number of transistors integrated on a single chip will grow exponentially over time, and this concept was later called Moore’s Law. After 1970, digital ICs were mostly designed with CMOS devices. The integration has been continuously improved through the scaling of process technology. Its complexity has been doubled in about 1–2 years and has reached more than 1 billion transistors per chip. Logic gates used in digital ICs are divided into two categories: combinational logic and sequential logic circuits, as shown in Fig. 36.1. The output of a combinatorial logic circuit is the function of its input at any time, and it is independent of the previous working state of circuit. The typical combinational logic circuits include inverter, NAND gate, NOR gate, multiplexer, etc. The sequential logic circuit means that the output at any time depends not only on the input at that time but also on the precious state of the circuit. Typical sequential logic circuits include latches, flipflops, etc.; however, the memory circuit belongs to the sequential logic. Digital ICs can also be classified into two types: synchronous and asynchronous circuits. Synchronous circuits mean that all sequential logic units are driven by a single homologous clock. Any path satisfies the setup time and hold time constraints. The highest working frequency is limited by the longest delay path, which is called critical path. An asynchronous circuit is a type of circuit in which the sequential logic circuit is clock-free or driven by a nonhomologous clock, and its circuit performance (throughput) is limited by its circuit delay. Figure 36.2a shows a typical synchronous

Fig. 36.1 Combinational logic and sequential logic in digital circuits

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Fig. 36.2 (a) Synchronous circuit and (b) self-timed asynchronous circuit

circuit. The logic functions F1, F2, and F3 are implemented in three steps, and its highest frequency is limited by the maximum values of tpF1, tpF2, and tpF3. The circuit can also be designed in an asynchronous way, as shown in Fig. 36.2b. Each logic function is completed by handshake logic HS communication, startup, and identification. According to the logic implementation, CMOS digital circuits can be classified into static and dynamic CMOS circuits. The static CMOS circuit is connected to the power supply or ground through a low-resistance path, thereby achieving logic high and logic low. Typical static circuits are: CMOS logic, proportional logic, and transfer tube logic. Dynamic CMOS circuits maintain logic “1” or logic “0” by the charge held on the parasitic capacitance. The static circuit has better stability but has the disadvantages of large layout area and large latency. The dynamic circuit delay is ideally only 50% of the static CMOS circuit, but it has the problem of poor anti-noise ability and large power consumption. The digital circuit design method can be divided into two categories: semi-custom design based on standard cells and full-custom design based on transistors. Semicustom design is widely used in electronic design automation tool to improve design efficiency. Full-custom circuit design is common in circuits such as processor cores and high-speed serial bus interfaces that require high performance and power consumption.

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The main indicators of digital IC include: design cost, performance, power consumption, and stability. Design cost refers to the sum of chip design and processing cost, packaging cost, and test cost; Performance refers to the throughput of digital integrated circuits that can handle digital signals. It is often replaced by the operating frequency when the architecture is determined. Power consumption refers to the sum of dynamic power and static power consumed by digital ICs. Stability is the ability of the circuit resisting to noise and to process fluctuations.

Hardware Description Language (HDL) Hardware description language (HDL) is used to model the concurrent execution process of hardware circuits, mainly including Verilog HDL (often shortened as Verilog) and VHDL, which were developed in the mid-1980s and adopted as IEEE standards. These two HDLs were used early for large-scale digital circuit verification and later used for register transfer level (RTL) design and logic synthesis. HDL can support multiple description levels of hardware circuits, including the behavior level, the register transfer level (RTL), and the logic gate level. The behavioral level is a description of the hardware mathematical model. The sequential statement describes the circuit function but does not involve any timing information. The RTL describes the description of the register structure in the circuit and the data transfer between the registers. The RTL model can describe the timing information of the hardware circuits on the clock cycle precision. The logic gate level model describes the various logic gate units and the switch connection structures between these logic gates. The logic gate level model can visually indicate the basic logical network structure of the circuits. HDL uses a structured, hierarchical modeling approach. For example, a new module structure can be described by describing the instantiation of individual devices and the connections between these devices. The device here can be either a built-in gate in most HDLs, such as an AND/OR gate, a user-defined unit, or a unit provided by a third party. The HDL supports a variety of variables, including wires, registers, and parameters. The HDL supports continuous assignment and process assignment. Continuous assignment is often used for combinatorial logic modeling. Process assignments can be divided into blocking assignments and non-blocking assignments. Blocking assignments block the execution of statements in subsequent code, and non-blocking assignments do not block the execution of subsequent code. Process assignment can model both combinational logic and sequential logic. HDL supports a variety of delay models, including lumped RC delay models, distributed RC delay models, and pin-to-pin path delay models. The HDL uses an event-driven mechanism, that is, the simulation of the circuit is organized by events in the PROCESS. PROCESS is an independently executed unit in HDL. A digital circuit system described in HDL is composed of several PROCESSes. When the value of any variable in a PROCESS is changed, a new updateevent is generated. As new update-events are triggered, PROCESSes that are sensitive to them will be executed once. The execution of a PROCESS is an

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Fig. 36.3 HDL simulation mechanism

evaluation-event. As shown in Fig. 36.3, during the simulation of the hardware circuit, the system simulation time will be divided into many discrete time slices. In each time slice, based on the update-event of the previous time slice, the evaluationevent for all related processes in current time slice will be executed, and then this operation will also generate new update-event. The evaluation-event and updateevent trigger each other to simulate the hardware circuits. In addition, PROCESS can be activated and suspended. When an activated PROCESS is running, all other PROCESSes will be suspended. Through the above event-driven and PROCESS management mechanisms, HDL can simulate the concurrent operation of hardware circuits. HDL has greatly promoted the development of digital IC design automation technology. In order to adapt to more design requirements, the HDL is also being continuously updated. For example, HDL has extended the support for digitalanalog hybrid circuit modeling, verification extension, and system-level modeling.

Circuit Partitioning Circuit partitioning partitions the circuits into two or more disjoint subsets according to constraints so as to improve EDA software effect. The object of circuit partitioning is generally a circuit composed of macro cells or standard cells to reduce the complexity of the VLSI design and enhance the readability of the partitioned circuits, leading to the area optimization and the line length optimization during place and route. Circuit partitioning typically requires the area of each subset to be approximately equal and needs to minimize the number of interconnects between subsets. Since circuit partitioning belongs to the non-poly (NP, nondeterministic polynomial time) problem, how to find the approximate optimal solution within a

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Fig. 36.4 Schematic diagram of circuit partitioning

relatively small time complexity is the goal of the design partitioning. The schematic diagram of circuit partitioning is depicted in Fig. 36.4. The constraints of circuit partitioning are usually the upper and lower bounds of the total circuit area and the area of the subsets as well as the corresponding main objective functions, including: (1) minimal cut, which means the minimization of the total number of interconnections cut by the subsets; (2) minimal delay, which means the minimization of the maximum delay of all paths from the input to the output of the subsets; and (3) minimization of the maximum subdomain degree, that is, the maximum number of interconnections cut by the subsets must be lower than a certain upper limit bound. The above objective functions ensure that the circuit does not cut the critical path with large delay, the number of interconnections between the subsets is smallest, and the interconnection density is as even as possible. According to the basis of circuit partitioning, the algorithms of circuit partitioning can be divided into constructive and iterative improving algorithms. The constructive algorithm starts from an empty set and gradually increases the number of cells to establish the partitions, which includes the clustering algorithm, the group migration algorithm, and the line network cutting model. The iterative improving algorithm starts from a random initial subset and iterates the modification of the partition result to comply with constraints, which includes the simulated annealing algorithm, the spectral segmentation algorithm, and the genetic algorithm. According to the principle of algorithm, the algorithms of circuit partitioning can be divided into mobile, analytical geometry, combinatorial mathematical, and clustering algorithms. The mobile algorithm usually adopts the method of exchanging

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or moving partial cells to improve the solution and gradually obtains the optimal solution of the algorithm, such as the group migration algorithm, the simulated annealing algorithm and the hybrid genetic algorithm. The most representative analytical method is the eigenvector method. The combinatorial mathematical method considers the effect of the shape and length of the module on delay, which leads to more accurate delay estimation, and is suitable for delay-driven partition, such as the network flow method, the mathematical programming method, and the set coverage method. The clustering algorithm includes the proportional cutting algorithm, the random walking method, the multilevel hierarchical algorithm, and so on.

Floor Planning and Placement Floor planning is a graphical representation of an IC’s main modules in a pilot layout, which is the premise of cell placement and route. During floor planning, the shape or position of modules and the position of the external connection pins are optimized by establishing a mathematical model under certain geometric constraints. The geometric constraint of floor planning is caused by the special placement requirements of some modules, as shown in Fig. 36.5. It mainly includes: (1) Wire bonding, which is usually around the chip. The input and output devices should be as close as possible to it. (2) High-speed macros, usually high-speed circuits (such as high-speed cache, multipliers, barrel shifters, and arithmetic logic units), which should be clustered together to avoid excessive data paths. (3) Hard IP, which usually requires special layout locations, such as signal routing not allowed above the IP. The main objectives of the floor planning optimization algorithm are: (1) determining the die size; (2) ensuring timing closure; and (3) meeting the routing

Fig. 36.5 The geometric constraint of floor planning

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requirements. Module shape optimization is unique to the floor planning phase and can be viewed as a floor planning constraint problem with soft parameters. The algorithm mainly includes: (1) Floorplan sizing algorithms, which can change the aspect ratio of the module in polynomial time to find the minimum layout area. (2) Cluster-growth algorithms, in which the blocks are iteratively added. The clusters are merged horizontally, vertically, or diagonally. The next block position and direction are placed to optimize the layout objective function. (3) Simulated annealing algorithms, which seek continuous improvement of the objective function solution starting from any initial solution. (4) Integrated floor planning algorithms, which map floor planning problems into a set of equations, where the variables represent the position of the block. The research on floor planning notation has experienced great development since the 1980s to the mid-to-late 1990s and up to now. There have been many representations or codes (such as fast sequence pair algorithms) that represent various topological types and corresponding algorithm (such as Hamiltonian path graph algorithm). With the improvement of IC performance, the constrained floor planning (such as layered design, IP core reuse, and connection optimization) has become a hot research topic in the physical design of very large scale IC.

High-Level Synthesis High-level synthesis (HLS), also known as behavior-level synthesis (BLS), is a method and process for transforming a circuit-level or behavior-level description into a circuit structure description under certain constraints. High-level synthesis can greatly optimize the circuit architecture and improve the design quality, whose process is shown in Fig. 36.6 including compiling, transformation, scheduling, allocation, controller synthesis, result generation, etc., where compiling and transformation determine the compatibility and convenience while scheduling and distribution determine the performance and cost of the design. Compiling and Transformation. The compiling and transformation process converts the description of the behavioral characterization to an intermediate representation format, where the description of the behavioral characterization is written by the hardware description language (HDL) and the intermediate representation format generally adopts the syntax analysis diagram. The syntax analysis diagram typically contains the data stream and the control flow, including the abstract operations and their properties (operation type, commutability of operands, etc.), the control dependencies of operations (execution order), the data dependencies (input data and output data for operations), and so on. Scheduling and Allocation. This process features the transformation from the behavioral description to structural description. The scheduling process assigns the operations to the control steps with the goal of minimizing a given objective function while satisfying the constraints, including the total required number of control steps, latency, power consumption, and the amount of hardware resources. The allocation process is to allocate the operations to the corresponding functional unit for

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Fig. 36.6 High-level synthesis

operation, to assign variables to registers, with the goal of minimizing the hardware resources such as functional units, storage units, and data transmission paths. Controller Synthesis. The controller synthesis process provides the required driven signals to the data path through the controller, and the controller can be implemented with hard-wired logic or firmware. The development of the hierarchical synthesis technology experienced three periods. In the first period (from early 1980s to early 1990s), the basic concepts of HLS were proposed by academic institutions. In the second period (from early 1990s to the beginning of the twenty-first century), EDA companies began to release the tentative commercial tools, mostly applying behavioral HDL as the input language. In the third period (from the beginning of the twenty-first century to present), many EDA companies and academic institutions have promoted HLS technology moving toward commercial applications. At present, HLS tools are still far from practical applications with problems facing, e.g., effective search methods for design space, division of large-scale circuits, problems related to IPs, and influence of placing on delay.

Logic Synthesis Logic synthesis is the process by which register-transfer level (RTL) circuit descriptions are transformed into gate-level descriptions (i.e., logic gate-level netlist) to meet design objectives and constraints. Generally, logic synthesis includes three

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Fig. 36.7 Procedure of logic synthesis

stages [1]: logic translation, logic optimization, and mapping, see Fig. 36.7. According to the constraints and strategies set by the designer, the performance, area, and power consumption of the circuit are optimized. The netlist of logic synthesis output is the input to the physical synthesis. Logic translation is to translate RTL descriptions of digital circuits into non-optimized netlists, i.e., logic equations, based on standard cell libraries independent of the process. Logic optimization is to reorganize and optimize netlist according to the constraints of design objectives. The process needs to satisfy three kinds of synthesis constraints simultaneously, i.e., environment constraints, design rule constraints, and logic optimization constraints. Environment constraints describe the external environment, such as temperature, voltage, drive, and load where the circuit works. Design rule constraints describe the maximum transition time, maximum fan-out, and minimum/maximum capacitance allowed by the circuit. Logic optimization constraints include timing constraints and area constraints. The former limits clock networks, timing paths, critical path delays, and asynchronous logic timing, while the latter limits the maximum number of logic units. Complex circuits can adopt top-down and bottom-up logic optimization strategies. The former optimizes the top module together with all its sub-modules and sets constraints for the top module. The latter adopts the idea of divide and conquer, and sets constraints from the bottom; then the sub-modules are integrated and optimized one by one, layer by layer up to the top module. Mapping is to select logic unit instances from target process cell libraries to implement a process-dependent logic netlist, based on the constraints of time sequence and area of design objectives, and the logic relationship, unit

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characteristics, and parameters of delay, power consumption, and area of logic units provided by target cell library under corresponding processes. The history of logic synthesis can be traced back to the manual use of Karnaugh map to achieve circuit logic simplification, but not until the mid-to-late 1980s, the theory and method of logic synthesis developed and matured. In the 1990s, a comprehensive tool for commercial automation logic was formed [2]. With the development of process nodes, the optimization effect of logic synthesis has become the main factor affecting the feasibility of the physical design. The logic synthesis needs to consider more physical effects when using advanced process node.

Timing Analysis Timing analysis is the methodology that checks if circuits meet the timing closure consisting of setup time constraints and hold time constraints. Timing analysis, as the foundation that guarantees regular circuits, can be categorized into dynamic timing analysis (DTA) [3] and static timing analysis (STA) from the perspective of analytical methodology [4]. Figure 36.8 shows the typical path of synchronous circuits. In the ideal condition, the clocks of Register D1 and Register D2 have the same period and phase. Generally, synchronous circuits require the well-built input data for Register D2 before the rising edge of the next clock. This is called the setup time constraint. T > tc
q þ tlogic þ tsetup Here, T is the synchronous clock period; tc–q is the maximum propagation delay of Register D1; tlogic is the maximum delay that signals pass through combinational circuits; tsetup is the setup time of Register D2 and decides the maximum of the combinational logic delay, tlogic. Synchronous circuits also require the input data of D2 to hold on for some time so as to write them into D2 correctly. This is called the hold time constraint. thold < tc
q,cd þ t log ic,cd

Fig. 36.8 Timing paths and timing parameters

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Here, thold is the hold time of D2; tc–q,cd is the minimum delay of D1 (also named contamination delay); tlogic,cd is the minimum delay that signals pass through combinational circuits and decides the minimum of the combinational logic delay, tlogic. In terms of stimulus, timing analysis includes dynamic timing analysis and static timing analysis. Based on cell delay and interconnect delay back-annotated by physical parasitic parameters, dynamic timing analysis synchronously checks logic setup time and hold time stimulated by a set of verification vectors during the dynamical function simulation. Static timing analysis, independent of verification vectors, successively analyzes all the paths within circuits and verifies if the path delay meets both setup time and hold time constraints, on the basis of cell and interconnect delay models defined in standard cell libraries. Static timing analysis takes advantages of fast speed and high coverage but may cause pessimistic analysis due to its weakness at path authenticity judgments. Alternatively, dynamic timing analysis takes the disadvantages of slow speed and low coverage but can achieve high accuracy. Timing closure is the process of iteratively executing timing analysis at different design stages in order to gradually approximate timing constraints of the design. Timing closure is mainly affected by factors of interconnect delay. At the stage of the logic synthesis, interconnect workloads-based interconnect delay prediction leads to the low accuracy. At the stage of the placement, Manhattan distances between cellsbased interconnect delay prediction generates the higher accuracy. At the stage of routing, real routes-based interconnect delay prediction can result in the highest accuracy. According to the interconnect delay at different stages, circuits can meet the timing constraints by methods of modifying driven intensities of cells, adjusting the places of cells, inserting/deleting buffers, and so on. With the rapid development of semiconductor technology, process variations (threshold voltage variations and channel length variations) and environment variations (voltage and temperature variations) during manufacturing have more and more significant effects on circuits delay. Traditional static timing analysis based on process corners has difficulties in characterizing the effects caused by process and environment variations. Statistical static timing analysis (SSTA) based on random variables characterizing circuits delay can analyze the timing constraints of synchronous circuits more accurately than traditional static timing analysis.

Formal Verification Formal verification refers to a static verification method of analyzing circuit behavior by mathematical method and finding out the fault of circuit function. Formal verification does not require stimulus and circuit simulation, and has greater completeness than simulations. Formal validation can be divided into two categories: equivalence checking and attribute checking. Equivalence checking verifies that the circuit is functionally consistent at different stages. For example, verification of RTL (register-transfer level) design and

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Fig. 36.9 Logical equivalence between different netlists

gate-level netlist, synthesis netlist, and post-layout netlist. Equivalence checking also can be used in the process of scanning chain rearrangement, clock tree synthesis, etc. It has been integrated into the standard IC design flow. Equivalence checking compares the functional consistency of the two models by traversing all possible inputs. When contrasting, circuits are typically converted to regular expressions. The two circuits in the following image have the same regular expression, see Fig. 36.9. Although the circuit structures are different, their functions are equivalent. Property checking, also known as model checking, checks whether the circuit meets the property specification by mathematically searching. Property checking generally takes the circuit model, coverage point, assertion, and circuit constraints as inputs and checks all possible states of the circuit in the constrained environment for the assertion. The failure of property checking indicates that a circuit function error is found, and the tool outputs the counterexample. Property checking covers all possibilities of logic and requires a large memory space, which limiting the size of the circuit to be validated.

Design for Testability The design-for-testability (DFT) is a circuit or method that is inserted in the chip without changing the function of the original circuit, implementing detection and testing of chip manufacturing defects and saving test cost. In the early stage of IC development, functional testing was the mainstay. However, with the increasing of circuit scale, functional testing is more and more difficult to cover the defects of the chip. For this reason, DFT and structural testing for fault models become the mainstream. The DFT focuses on improving the controllability and observability of the circuit. Controllability is a measure of the difficulty of target faults or defects. Observability is a measure of the difficulty or fault that can be observed by the test equipment. Fault model is the core of the DFT, which refers to the circuit defects and are abstracted as logical errors affecting the test vector generation. There are “stuck-at-

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0” fault, “stuck-at-1” fault, coupling fault, bridging fault, and other fault models. The main indicators for measuring the DFT are fault coverage and hardware overhead. Fault coverage refers to the percentage of faults that have been tested. Generally, the coverage must be at least 95%. The hardware overhead refers to the proportion of the testability logic area inserted to the total area of the chip. According to the type of the circuit, the DFT can be divided into digital logic DFT, memory DFT, and mixed signal DFT. 1. Digital logic DFT mainly includes scan test, LBIST (logic built-in self-testing), and boundary scan test (BST). Among them, the LBIST uses random vectors to test the logic circuit, which has the advantages of short test time and low test cost. The linear feedback shift register is generally used to generate the test vectors. The boundary scan test adds the shift registers to the inputs and outputs of the chip, to form a boundary scan chain. It is commonly used for chip interconnect testing. IEEE1149.1-1990 is used to the boundary scan test. Scan test is the structured test method. The register of the circuit to be tested is replaced with a scan register, connected as a scan chain, and the test data is moved into/out of the circuit through the scan chain. As shown in Fig. 36.10, the SE signal is set high firstly, the scan chain is in shift mode, and the test vector is shifted to scan register through the SI port; then the SE signal is set low, the scan chain is in the capture mode, and the response of the combined circuit is captured by the scan register; the SE signal is set high at last, the scan chain is shift mode, and the test result is output of the chip through the SO port.

Fig. 36.10 The schematic and timing of scan test

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2. Memory DFT mostly uses MBIST (memory built-in self-testing), which includes test vector generator and test response comparator. The test vector generator generates test data, address, and read/write control signals according to the test algorithm. The test response comparator compares the test data of the memory with the expected data. If the data is inconsistent, there is a fault in the memory. The test algorithms include March C, checkerboard, and so on. In order to cope with the increasingly serious memory yield problem, the memory selfrepair technology becomes more and more important. 3. Mixed-signal DFT is often combined with the functional test and performance test, unlike with the structured DFT. Taking the PLL testing as an example, the on-chip clock jitter test circuit can be integrated to replace the off-chip ATE solution.

Hardware Emulation A hardware emulator is an electronic system that maps a digital circuit into a gate level netlist or a Boolean unit of operations and performs a circuit function with special hardware to quickly complete functional verification. The scale of digital circuit increases with Moore’s law, and the software simulator is difficult to complete the massive verification work in a short period of time for the very large-scale chips. The hardware simulator can significantly shorten the verification time, with cyclelevel accurate results, high simulation speed, and full debugging visibility. The acceleration mechanism, key parameters, and application of emulators are explained below. Acceleration Mechanism of Emulator: Unlike a software simulator that relies on general CPU to simulate the circuits, hardware emulators map circuits to logical units of customized field programmable gate arrays (FPGA) or dedicated Boolean processor arrays. The execution hardware of the hardware emulator has the basic circuit structure such as logic operation unit and memory, and their functions are consistent with the actual circuit, which can realize the logic function corresponding to the circuit, and the execution speed is 1–4 orders of magnitude faster than the software simulation speed. Both the customized programmable FPGAs and Boolean processors provide a circuit-based debug interface with the same debug visibility as the software simulator. Main Parameters of Emulator: (1) Capacity, including the logical gate capacity, the memory capacity, and the number of input and output ports. Capacity determines the maximum mappable circuit size, and the circuit will be divided and mapped to the software simulator and hardware emulator co-simulation when the circuit scale exceeds the hardware emulator capacity. (2) Simulation speed, the number of clock cycles per second. Simulation speed is independent of circuit size, determined by the hardware structure of the hardware emulator. (3) Parallelism, the number of users or the number of threads that perform simulations at the same time.

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Applications of Emulator: Hardware emulators are mainly used for the following applications: (1) regression testing and stress testing, such as large-scale randomness verification; (2) hardware and software co-verification, such as the co-work of system on a chip and embedded operating system; and (3) other complex verification, such as complex software protocol stack and video codec circuit. For comparison of simulators and emulators, see Table 36.1. In addition to expand capacity and increase simulation speed, hardware emulators begin to support multiuser in computing center mode (see Fig. 36.11). The latest hardware emulator can handle more than 2000 parallel jobs at the same time, with a maximum capacity of 9.2 billion logic gates. Table 36.1 Comparison of simulators and emulators Simulation mode Software simulator

Computing hardware X86 CPU

Computing unit CPU core

Simulation speed (cycle/s) 3 V), and the reference output range is limited (>1.2 V). When the power supply is below 1.2 V, the traditional bandgap voltage reference has been unable to meet the requirements. In addition, in the current circuit design process, MOS transistors inevitably have secondary effects (mainly channel length modulation effect and volume effect); therefore, to obtain a more accurate reference voltage, additional circuits are needed for improving the power supply voltage rejection ability and broaden the output range of the reference voltage. The key performance parameters of bandgap reference circuit include temperature drift coefficient, power supply voltage rejection ratio, output noise, power consumption, accuracy, sensitivity, etc. Temperature drift coefficient (TDC) reflects Fig. 37.4 Structure of a basic bandgap voltage reference circuit

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the temperature-dependent offset of the output voltage of the bandgap reference voltage source. Power supply rejection ratio (PSRR) is an important parameter to measure the power noise rejection ability. For reference voltage source, the physical meaning is the change of output voltage when the power supply voltage changes. Output noise is a performance indicator to measure the noise at the output terminal of bandgap reference voltage source. The output noise of the reference voltage source circuit may significantly affect the performance of the low noise circuit. Power consumption is used to measure the current consumed by the bandgap reference circuit under normal working conditions. Accuracy refers to the relative or absolute error between the actual output voltage and the nominal value voltage of the reference voltage source. Sensitivity is defined as the ratio of the change rate of the output voltage to that of the power supply voltage, which is used to evaluate the voltage stabilization characteristics of the reference voltage source. The lower the sensitivity, the better is the stability of the reference voltage source. In the design of high-precision bandgap reference circuit, except for using current mirror and voltage negative feedback technology to improve PSRR, chopping modulation technology is also used to effectively reduce errors caused by operational amplifier offset voltage in reference voltage source, and trimming technology is used to adjust resistance value to achieve accurate temperature compensation; therefore, the accuracy of reference voltage source are improved. In order to reduce the influence of power supply voltage fluctuation on reference voltage, cascode structure and high gain feedback loop are common circuit design techniques for mirror phase current source of the bandgap circuit. In addition, attention should be paid to the matching and symmetry between the devices in layout design, especially the symmetry between MOSFETs which constitute current mirrors, so as to ensure the consistency of the surrounding environment as much as possible.

Filter Design In IC design, filter circuit unit is used to select the frequency of the signal, and only the signal components in a specific frequency range are allowed to pass normally, while the signal components beyond the specific frequency range are effectively filtered out. There are several ways to classify filters. According to the processed signal, it can be divided into analog filter and digital filter. According to the components of the circuit, it can be divided into passive filter and active filter. According to the filter frequency selection range and filter nature, it can be divided into low-pass, high pass, bandpass, and band-stop filters. According to different frequency response functions, it can be divided into Bessel filter, Chebyshev filter, Butterworth filter, Gaussian filter, and so on. In practical application, the choice of filters is determined mainly by the frequency selectivity of the filter. A low-pass filter (LPF) allows low frequency components below the signal cutoff frequency fc to pass through, while components above the cutoff frequency are attenuated. A high-pass filter (HPF), contrary to the

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low-pass filter (LPF), allows high frequency components above the signal cutoff frequency fc to pass through, while components below the cutoff frequency fc are attenuated. A bandpass filter (BPF) allows a signal in a certain frequency band ( fc1  fc  fc2) to pass through, while components below or above that frequency band are attenuated. A band-stop filter (BSF, also known as band-elimination, bandreject, or notch filters), in contrast to a bandpass filter, allows signal components with frequencies below fc1 or above fc2 to pass through, while frequency components between fc1 and fc2 are attenuated. The actual amplitude-frequency characteristics of these four types of filters are shown in Fig. 37.5. Low-pass filter and high-pass filter are the two most basic forms of filters, and the other filters can be composed of these two types of filters. For example, the series connection of low-pass filter and highpass filter is a bandpass filter, and the parallel connection is a band-stop filter. The basic parameters of the filter include gain, cutoff frequency, center frequency, passband bandwidth, quality factor, and out-of-band rejection. Gain, also known as passband amplification factor, is the ratio of the output voltage to the input voltage in the passband. In the amplitude-frequency characteristic curve shown in Fig. 37.5, A0 represents the gain of the filter. The frequency corresponding to the amplitude of 0.707 A0 is called the cutoff frequency of the filter. 0.707 A0 corresponds to a
3 dB point in logarithmic coordinates, that is, the cutoff frequency is a frequency value corresponding to the amplitude that is attenuated by 3 dB relative to A0. For bandpass filters, center frequency f0 ¼ ( fc21 þ fc2)/2. The frequency width of the signal that the filter can pass is called the filter bandwidth, e.g., the range between the up and down cutoff frequencies is the bandpass filter bandwidth or the
3 dB

Fig. 37.5 Amplitude-frequency characteristics of four filters

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bandwidth. The quality factor of the filter, also known as the cutoff characteristic coefficient of the filter, is the ratio of the voltage amplification factor to the bandpass amplification factor when the frequency is equal to the resonant frequency (natural frequency) of the filter. Out-of-band rejection is the amount of attenuation beyond the bandpass frequency range of the filter, characterizing the filter suppression of frequency components outside the bandwidth. The filter design is to search a suitable transfer function to meet the required specifications. After determining the filter type according to the system application requirements, based on the selected filter type (active or passive, digital or analog, etc.), the mathematical characteristics of the filter response need to be carefully analyzed, and then the linear circuit or non-linear circuit is selected according to the circuit parameter, and the optimum design of the pre-distortion circuit, impedance conversion circuit, amplitude equalization circuit, delay equalization circuit, waveform generation and conversion circuit, feedback amplification and large signal output amplification circuit, power amplification, voltage feedback, and current feedback amplifier are made. Filter design is critical in some IC chips, especially in IC designs for wireless communication system applications and is a key analog module unit in IC design.

Analog-to-Digital Convertor Analog-to-digital converter (ADC) or conversion circuit is an IC that converts an analog input signal whose amplitude varies continuously with time into a digital output signal that is discrete in both time and amplitude. The input analog signal of A/D conversion circuit will usually be compared with the standard value and then converted into discrete signal expressed by a multi-bit binary value. In general, for N-bit resolution ADC, the output range of binary data is 0–2N
1, with a total of 2N discrete values. For example, an ADC with 6-bit resolution can encode an analog signal into 64 different discrete values (as 26 ¼ 64). Any analog-to-digital conversion circuit needs a reference value (reference voltage or current) as the standard of conversion, and the output digital signal indicates the magnitude of the input signal relative to the reference value. Analog-to-digital conversion includes four processes of sampling, hold, quantization, and coding. Sampling is the conversion of a time-continuously varying analog signal into a time-discrete sampled signal through a series of equally spaced sampling pulses as shown in Fig. 37.6. The sampling theorem (known as NyquistShannon theorem) was proposed by American telecommunication engineer H. Nyquist of Bell Labs in 1928 [4]. It explains the relationship between sampling frequency and signal frequency and thus establishes the connection between analog signal and digital signal. The sampling theorem is the basis for discretization of continuous signal. To digitalize a sampled output signal, the instantaneous analog signal from the sampled output needs to be held for a period of time as the hold process. During the hold time, quantization and coding are performed, and then the next sampling is started. Quantization, also known as amplitude quantization, is

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Fig. 37.6 Sampling process for A/D conversion

processing the signals that are discrete in time after sampling in order to make them also discrete in amplitude. For example, the amplitude range of the signal is evenly divided into N equal parts, each of which corresponds to an output value, and the sampled discrete signal amplitude is respectively divided into the part closest to its value; thus the signal is discretized in amplitude. Commonly quantization methods include rounding quantization and truncation quantization. Quantization will inevitably introduce quantization error. Quantization error is the difference between the equivalent analog value of the output signal and the analog value of the actual input signal. The encoding process is to encode the quantized signal into a specific digital code output. The usual encoding methods include natural binary encoding and binary complement encoding.

Characteristic Parameters of Analog-to-Digital Converter The main characteristic parameters of the ADC include the static characteristic parameters and dynamic characteristic parameters. 1. Static characteristic parameters. (1) Analog Resolution: The minimum analog increment of the digital code change corresponding to the least significant bit (LSB). (2) Offset: Output drift under zero input conditions. (3) Gain Error (GE): The error of the gradient of the transmission characteristic curve. This parameter defines the deviation of the gradient of the A/D converter from the ideal value. (4) Differential Non-Linearity (DNL): The difference between the actual conversion step width of the A/D converter and the width of its ideal conversion step Δ. Assuming that Xk is the jump point between adjacent codes k
1 and k, then the width of binary code k is Δr(k) ¼ Xkþ1
Xk; thus the differential non-linearity is defined as:

DNLðkÞ ¼

Δr ðkÞ
Δ Δ

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(5) Integral Non-linearity (INL): Used to measure the deviation of the actual conversion curve from the ideal interpolation curve. Another definition is to measure the deviation of the actual conversion curve from the endpoint fitting curve. Considering the endpoint fitting curve, the integral non-linearity is defined as: k

INL ¼ ð1 þ GEÞ

DNLðiÞ

i¼1

where GE is the gain error. 2. Dynamic characteristic parameters. (1) Signal-to-Noise Ratio (SNR): The ratio of signal power to total noise power. (2) Signal-to-Noise-and-Distortion Ratio (SINAD or SNDR): Similar to the definition of SNR, but it also includes the non-linear distortion term produced by the sine wave input. The signal-to-noiseand-distortion ratio is the ratio of the signal power and the sum of harmonic components plus noise (except DC). (3) Dynamic Range (DR): The value of the input signal when SNR or SINAD is 0 dB. (4) Effective Number of Bits (ENOB): SINAD expressed in bits. The relationship between SINAD and ENOB in dB is as follows: ENOB ¼ ðSINADdb
1:76Þ=6:02 (5) Total Spurious Distortion (TSD): The square root of the sum of the squares of the spurious components in the ADC output spectrum. (6) Spurious Free Dynamic Range (SFDR): The ratio of the root mean square of the signal amplitude to the root mean square of the largest spurious spectral component in the first Nyquist interval. (7) Effective Resolution Bandwidth (ERBW): The analog input frequency when SINAD drops by 3 dB versus a low-frequency. (8) Figure of Merits (FoM): A parameter evaluating the power consumption of an ADC. FoM has a variety of definitions, and a common definition is FoM ¼

Power 2ENOB  2  ERBW

Study of ADC testing shows that dynamic parameters are not sensitive to the number of samples or the number of input periods but are sensitive to the input signal amplitude; they can also exhibit significant variations against static errors.

Analog-to-Digital Converter Design Typical ADC include dual-integrated ADCs, sigma-delta (Σ-Δ) ADCs, successive approximation (SAR) ADCs, pipelined ADCs, Flash ADCs, etc.

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Dual-integrated ADC is an indirect ADC. It integrates the input sampled signal and the reference voltage twice to obtain a time interval proportional to the input signal. At the same time, the counter is used to count the standard clock pulse. The count value of the counter is the digital output amount of ADC. In the specific circuit, the offset of the op-amp and comparator is an important performance limiting factor, which needs to be eliminated by automatic zero adjustment. Σ-Δ ADC is also called the oversampled ADC. It consists of a Σ-Δ modulator and a digital filter connected to the modulator. It is especially suitable for applications such as audio signal processing, biomedical signal acquisition, and other requirements such as low-frequency, high-precision, and analog-to-digital conversion. Its high-precision conversion comes from two main technologies, oversampling technology and noise shaping technology. Oversampling techniques turn the signal bandwidth into a fraction of the Nyquist frequency, so the quantization noise is spread over a wider range of frequencies. The noise shaping technique reduces the in-band noise and further improves the signal-to-noise ratio within the frequency band of interest by changing the noise transfer function. The quantization noise within a larger range of band beyond the band of interest can be eliminated using digital techniques. SAR ADC is a direct ADC. It generates a series of comparator voltages, comparing the comparator voltage with the input voltage one by one from high to low, and performing analog-to-digital conversion in a gradual approximation. SAR ADC can use capacitor networks and charge redistribution methods to theoretically achieve lower power consumption. SAR ADC is a medium-speed ADC device. In recent years, a variety of new technologies, especially the use of asynchronous operation, have continuously improved the conversion rate of SAR ADC. Pipelined ADC, also known as the sub-area ADC, consists of cascaded similarstructure low-precision ADC circuits and can provide medium-speed, high-resolution analog-to-digital conversion. Since each level of the pipelined ADC has its own sample/hold circuit, as long as the sampling conversion is completed in some level and the result is input to the next level, the current level circuit can be released to process the next sampling. Therefore, the pipeline operation improves the conversion speed. For pipelined ADC, the most stringent requirements lie in the input sample-and-hold circuit and the first few levels of the pipeline. The error of the DAC will modify the margin of the entire LSB part, thereby affecting the linearity of the entire ADC. Therefore, the accuracy of the pre-stage DAC must be higher than the INL required by the ADC to ensure the linearity of the overall response. Flash ADC is also referred to as scintillation ADC. The input signal is sampled and compared with multiple reference voltages at the same time; therefore, the conversion speed is fast. It is a direct ADC. Flash ADC has several limitations as noted below. First, an N-bit Flash ADC requires 2N–1 comparator. With the increase of resolution N, the circuit area and power consumption will be greatly increased. Second, too many comparators will reduce the input bandwidth. Third, since the resistor string divides the reference voltage into multiple sections to access the comparator, it is necessary for the comparator to ensure a sufficiently small offset and similar delay over a wide common mode input range. Fourth, the mismatch of

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the resistor string brings errors in every comparator level, which affects the linearity of the ADC. Fifth, the comparator’s kickback noise causes the instability of the comparator input. In addition to the single-channel ADC type mentioned above, multiple singlechannel ADCs can be integrated using time interleaved (TI) method to greatly increase the sampling rate. The basic principle of TI ADC is to control the sampling and conversion of each channel ADC at different times by the phase difference of the clock. In theory, the sampling rate of the system can be infinitely increased by increasing the number of the ADC channels. However, TI ADC faces various design challenges during implementation. The first is to design a wideband sample-andhold circuit with sufficient linearity, which requires a comprehensive tradeoff consideration of on-resistance, mismatch, parasitic, signal-coupled interference, power consumption, and so on. Second, the clock jitter is demanding, even at femtosecond (fs) levels. Therefore, the distribution and design of the clock will consume a lot of power and make higher demands on noise and power supply stability. Again, there are mismatch errors between multiple parallel channels, including offset error, gain error, sampling time error, and bandwidth error. These errors vary with process, voltage, and temperature (PVT), which may cause recurring errors after calibration, thus reliable and efficient calibration algorithms and implementation circuits are needed. Finally, when TI ADC and digital signal processor (DSP) are integrated on the same chip to perform ADC calibration and other digital signal processing, it will cause noise coupling from digital circuits to analog circuits, reduce the performance of the entire ADC, and make the noise design of the ADC more difficult.

Characteristic Parameters of Digital-to-Analog Converter Digital-to-analog converter (DAC) is a circuit unit that converts an input digital signal (both time and amplitude are discrete) into an analog signal (amplitude varies continuously with time). DAC is widely used in signal processing, navigation, communication, and measurement. In recent development, the performance of DAC has been continuously improved and developed in different directions. Highprecision, high-speed DAC plays a necessary key role in different application fields. The characteristic parameters of DAC can be divided into static parameters and dynamic parameters. In high-precision applications such as audio signal processing, static performance is the focus of attention, while in high-speed applications such as wireless communication, dynamic performance is the focus of attention. 1. Main static parameters. (1) Offset Error: The deviation of the actual output of DAC from the ideal zero output at zero input. This is an inherent error which can be easily compensated. (2) Gain Error: The deviation of the gain of the actual transfer function of DAC from the gain of the ideal transfer function, expressed as a percentage. Gain errors can usually be corrected by adjusting the full scale of the actual DAC. (3) Differential Non-linearity (DNL): The difference between the actual analog step size of DAC and the ideal analog step size (i.e., 1 LSB)

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between two adjacent input codes. Generally, the DNL is needed to be in the range of +/
0.5 LSB. Otherwise, the DAC will be non-monotonic, which will affect the conversion performance. (4) Integral Non-linearity (INL): The difference between the actual transfer function curve of DAC and the ideal transfer function curve on each input code. 2. Main dynamic parameters. (1) Signal-to-Noise Ratio (SNR): The ratio of the signal (single-frequency sinusoidal) output power to the total noise power of the quantized noise in the Nyquist bandwidth plus the noise caused by the circuit. The SNR of an ideal DAC reflects the level of quantization noise, which is the inherent characteristic of the digital signal that is input to the DAC after sample quantization and processing. However, the actual DAC also causes harmonic distortion (HD) due to its own non-linearity. These harmonic distortion energies are often much larger than those of the noise floor. (2) Spurious-Free Dynamic Range (SFDR): Since SNR characterizes the overall noise performance of DAC, it does not reflect well the relationship between signal energy and local harmonics and thus the characteristics of the DAC. Therefore, a spurious-free dynamic range is introduced to better characterize the dynamic performance of a DAC with non-linearity. SFDR is defined as the ratio of the signal power to the maximum clutter power when a single-frequency sine wave signal is input. (3) Total Harmonic Distortion (THD): In order to reflect the non-linearity of DAC, it is also necessary to analyze harmonic distortion in the required frequency band. THD represents the ratio of the sum of harmonic distortion power to the fundamental signal power. (4) Signal-to-Noise-and-Distortion Ratio (SNDR): Since the actual DAC has non-linear harmonics, not only the noise but also the harmonics should be considered when evaluating its dynamic linearity influences. Similar to the definition of SNR, SNDR is defined as the ratio of signal power to noise and the sum of all harmonic powers in the band. (5) Effective Number of Bits (ENOB): The SNR of an ideal DAC is determined by the number of resolution bits, N, but because the actual DAC has the non-linear factors, it is more suitable to use SNDR to evaluate the dynamic characteristics. To measure the deviation of the actual DAC from the ideal DAC caused by harmonic distortion, the effective number of bits is introduced to reflect the linearity of the DAC.

Digital-to-Analog Converter Design The main function of DAC is to complete the transformation from digital signal to analog signal. The whole conversion involved is the key to affect the performance of DAC. 1. Nyquist DAC. Nyquist DAC is mainly divided into resistive DAC, capacitive DAC, and current DAC. (1) Resistance DAC mainly includes resistance dividing type and R-2R weight type. (2) Capacitive DAC consists of a binary capacitive network and a voltage amplifier. The switching network uses capacitors; therefore there is no static current, and thus the power consumption is low. In addition, in

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CMOS process, a capacitance can achieve higher matching accuracy than a resistance; therefore, the resolution of capacitive DAC can be further improved. However, due to the large capacitance at the summation node, the time constant is large, and the capacitive DAC is not suitable for high-speed applications. The resistive and capacitive DACs mentioned above cannot drive external loads directly and need buffer or conversion circuit to get the final voltage or current output signal; therefore, these DACs will be limited by the bandwidth of buffer and cannot achieve high conversion rate. (3) Current-mode DAC is a more appropriate choice for high-speed applications, such as wireless communications. Current-mode DAC realizes the function of current by adding direct connection with the node of current source and then directly connecting the added current with the load resistance to generate the required output voltage without additional buffer driver. Moreover, the current directly drives the load to form the output voltage; therefore, it can achieve a high working speed. Current-mode DAC is mainly divided into binary weight structure DAC, thermometer decoding structure DAC, and segmented decoding structure DAC. (1) The weight of each switch-controlled current source of the binary weight structure DAC is incremented by a factor of two, and the input binary code is used to control the on and off of the corresponding current source. The increase of current weight in this structure is generated by duplicating the unit current source, and the input signal works directly on the current source switch without additional complicated circuit decoding, which greatly reduces the chip area and power consumption. The increase of the resolution of the binary weight structure DAC makes the current source weight increase exponentially. On the one hand, the larger differential non-linearity (DNL) caused by the matching error of the current source affects its static characteristics. On the other hand, the larger burr introduced when the control signal switches at high speed affects its dynamic performance. (2) The current source array of the thermometer decoding structure DAC consists of a series of currents with equal weights. This switching mode effectively avoids the influence of large burrs introduced during the switching process on the dynamic performance. However, with the increase of the resolution bits of DAC, the number of switches increases exponentially, which dramatically increases the complexity of the circuit of thermometer decoding structure, resulting in larger area and power consumption. (3) Combining the advantages and disadvantages of binary weight structure DAC and thermometer decoding structure DAC, the segmented decoding structure DAC is a tradeoff between performance and circuit complexity. It is divided into two parts: MSB and LSB. Let N be the number of DAC bits, the MSB part of M bit is translated into thermometer code, and the remaining LSB part of N-M bit is still binary code. The DAC includes a decoder that can convert M-bit binary signal into 2M
1 bit thermometer code. The high-bit current source is realized by the thermometer decoding structure, and the unit current value is IT. The low-level current source is realized by binary weight structure, and the unit current value is I. This kind of DAC type can obtain the best compromise between area and circuit complexity

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while achieving good static and dynamic performances. Therefore, most highprecision or high-speed current-mode DACs are segmented decoding structures. 2. Oversampling DAC. Oversampling DAC, as another type of DAC that is different from Nyquist DAC, is often used in high precision applications such as audio signal processing. Oversampling DAC can achieve high resolution by using oversampling technology and noise shaping technology similar to ADC. The difference from over-sampled ADC is that for over-sampled ADC, oversampling is done in analog domain, and continuous time input is converted to the form of sampled data somewhere, while for over-sampled DAC, oversampling is done in digital domain to produce digital results, which is then converted into continuous time analog signal by a lower-bit DAC and a reconstructed filter.

References 1. B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, 2001) 2. J. Chen, M. Henrie, M.F. Mar, Nizic, M., Mixed-Signal Methodology Guide, Cadence/lulu.com (ISBN 978-1300-035206), 2012. (Also in Chinese, Chen, C.-Z., He, L.N., Li, Z.Q. and Ai, X.: Science Press, ISBN 978-7-03-041959-0, 2015) 3. L.N. He, Y. Wang, Analog IC Design and Simulation (Science Press, Beijing, 2022) (Chinese book series 3 of 5, ISBN 978-7-03-021427-0) 4. H. Nyquist, Certain topics in telegraph transmission theory. Trans. A.I.E.E. 47(2), 617–644 (1928) Reprint: Proc. IEEE, 90(2), 280–305 (2002)

RF Integrated Circuit Design

38

Pengcheng Xiao, Yumei Huang, Wei Li, Na Yan, and Xiaoyang Zeng

Contents Radio Frequency Integrated Circuit (RFIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwave and Millimeter Wave Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Defined Radio (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Frequency Transceiver Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Noise Amplifier (LNA) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Synthesizer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Frequency Power Amplifier (RF PA) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Frequency Switch Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Radio Frequency Integrated Circuit (RFIC) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

The radio frequency (RF) usually ranges from 300 kHz to 30 GHz. The RF circuit can perform RF signals which are filtered, amplified, frequency-converted, and modulated. The circuit for processing such as demodulation is an RF circuit. A radio frequency integrated circuit (RFIC) usually consists of basic functional circuits, e.g., low noise amplifiers, filters, mixers, frequency synthesizers, and power amplifiers. The RF transmitting and receiving system constitutes a carrier channel for transmitting and receiving signals of wireless systems, e.g., wireless communication, radar detection, television broadcasting, navigation, and the like. To support the ever-increasing levels of SoC integration with the low-cost requirement, the RFIC design has been moving to the advanced CMOS process nodes. Digital RF technology can transform the continuous-time analog RF functionality into digitally intensive or even all-digital implementations.

P. Xiao · Y. Huang · W. Li · N. Yan · X. Zeng (*) School of Microelectronics, Fudan University, Shanghai, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_38

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Keywords

RFIC · MMIC · SDR · LNA · Mixer · PLL · PA · RF switch · Digital RFIC

Radio Frequency Integrated Circuit (RFIC) Radio frequency (RF) refers to a high-frequency electromagnetic signal that can be radiated into or received from a space through an antenna. The frequency range is usually between 300 kHz and 30 GHz. The RF signals need to be processed by signal filtering, power amplification, frequency-conversion, and modulation by using RF circuits or integrated to ICs referred to as RF integrated circuit (RFIC) [1]. Radio frequency ICs usually consist of basic functional circuits such as low noise amplifiers (LNA), filters, mixers, frequency synthesizers, and power amplifiers. The radio frequency transmitting and receiving system constitutes a carrier channel for transmitting and receiving signals of wireless systems such as wireless communication, radar detection, television broadcasting, navigation, etc. The baseband section implements signal filtering and digital-to-analog/analog-to-digital conversion, as well as digital signal processing. Figure 38.1 illustrates a block diagram of a typical RF system. The salient features of the signals processed by the RFIC include the following: (1) the signal frequency is high. (2) There is a certain bandwidth as generally much smaller than the carrier frequency. (3) The signal received by the antenna is very weak, and the transmitted signal radiated from the antenna is very strong, usually 5–10 orders of magnitude larger than the received signal. These characteristics make the design of RFICs very different from other types of circuits.

Fig. 38.1 Typical RF system structure

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The early RFICs were mainly based on GaAs. In 1976, the first GaAs RF IC was developed [2]. Since then, the GaAs process has been rapidly developed, and there are also some shortcomings: (1) low yield; (2) relatively small wafer size, low mechanical strength, and easy to break; (3) poor heat dissipation; and (4) incompatible with Si process. After the 1980s, SiGe materials became into being, which made up for the shortcomings of GaAs. In 1987, SiGe heterojunction bipolar transistor (HBT) was first reported; and in 1994, SiGe HBT with a cutoff frequency higher than 100 GHz was developed. After that, SiGe HBT has established the role in RFIC. In recent years, GaN, as a wide bandgap semiconductor material, has high electron mobility, high band gap, and high breakdown field strength. At the same time, the power density can reach more than 5 times that of GaAs, which can significantly increase the output power. After reducing system size and cost, GaN RF power devices have entered into a practical stage. Since the 1990s, with the continuous scaling of CMOS technology and the development of circuit design methodology, the CMOS technology has become the mainstream for RFICs with the GaAs and SiGe processes mainly for RF power amplifiers. RFICs have been widely used in wireless communication, RF identification (RFID), navigation, radar, and other systems. Especially in the past 10 years, the development and popularization of personal mobile communication has promoted the rapid progress of RFICs. With the continued development of personal mobile communications, the Internet of Things (IoT), and semiconductor materials and processes, RFICs will be moving forward toward low cost, low power, large bandwidth, high speed, and support for multi-mode, multi-band, reconfigurable, the development of baseband monolithic integration, and other directions.

Microwave and Millimeter Wave Integrated Circuit Generally, the microwave frequency is from 300 MHz to 3000GHz, and the corresponding electromagnetic wavelength from 1 m to 0.1 mm. It can be further divided into four bands, i.e., decimeter wave (wavelength range 1 m-100 mm), centimeter wave (wavelength range 100 mm–10 mm), millimeter wave (wavelength range 10 mm–1 mm), and sub-millimeter wave (wavelength range 1 mm–0.1 mm). Bands below 30 GHz overlap with RF bands, commonly referred to as RF bands; bands above 300 GHz are known as sub-millimeter waves and also commonly referred to as terahertz (THz) bands. The microwave band usually refers to the frequency range of 30 GHz to 300 GHz as microwave millimeter wave. The microwave (μm) and millimeter (mm) wave IC refers to an IC operating in the μm and mm wave band, which has functions of amplification, mixing, filtering, etc. The design of μm and mm wave IC requires a more accurate component model and even requires three-dimensional (3D) electromagnetic field analysis and calculations. Microwave and millimeter wave ICs include bandpass filters, low noise amplifiers, power amplifiers, main amplifiers, preamplifiers, mixers, frequency

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Fig. 38.2 Typical microwave and millimeter wave integrated circuit system structure

synthesizers, and frequency multipliers. The μm and mm wave transceiver system and the RF transceiver system are similar in system structure, but the operating frequency is higher, the bandwidth is larger, and the circuit design is more difficult. The μm and mm wave ICs can be divided into hybrid μm and mm wave ICs and monolithic μm and mm wave ICs according to the implementation form. Figure 38.2 is a system block diagram of a typical μm and mm wave IC. Hybrid μm and mm wave ICs are used on dielectric substrate materials (such as alumina ceramics, quartz, sapphire, etc.), thick film processes (such as low temperature/high temperature sintering process, printing process, etc.), or thin film processes (such as sputtering process, electroplating process, etc.) Prepare circuit topology diagrams of various functions, and then install components or chips of various discrete package forms to corresponding positions to form a certain function of μm and mm wave ICs. Monolithic μm and mm wave ICs are used to fabricate microwave active and passive devices on semiconductor substrates (such as Si, SiGe, GaAs, etc.) using semiconductor processes, as well as various functional circuits with high integration, high reliability, low cost, and other characteristics. GaAs has the characteristics of high electron mobility and good noise performance. The GaAs process was the mainstream process of μm and mm wave ICs. At the same time, the CMOS with SiGe HBT is also a common process for the μm and mm wave IC with higher gain, speed, better noise performance, and lower cost than GaAs process. In recent years, CMOS technology has been continuously improved and met the speed requirements of μm and mm wave ICs higher than the 100 GHz band, which also makes it possible to integrate the RF front end and the digital baseband in a wireless system. The monolithic μm and mm wave ICs based on CMOS process have entered a stage of rapid development. In the early days, microwave circuits and other devices such as tubes and klystrons were used. With the development of semiconductor technology,

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solid-state microwave devices including heterojunction bipolar transistors (HBT), varactors, and field-effect transistors (FET) have been widely used. Subsequently, the system increasingly complex, working frequency is increasing, the consistency of discrete devices is difficult to meet system requirements. In 1976, the development of 7–12 GHz microwave ICs using GaAs technology opened a new era in this field, using GaAs or InP process. Microwave and millimeter wave ICs are widely used in satellite communications, radar, and the like. After 2000, the United States, Japan, South Korea, and other countries have opened the 57GHz ~ 64GHz frequency band, and Europe opened the 77GHz frequency band, further promoting the research of single-chip μm and mm wave ICs based on CMOS technology. At present, the spectrum resources below the 10 GHz band are depleted, and the μm and mm wave band can provide more unallocated spectrum resources. Therefore, the working frequency band of the wireless system will gradually develop to the high frequency band of the microwave above 60 GHz. The advancement of process technology has provided technical support for this development. The speed of CMOS technology is continuously improved. Combined with its high integration characteristics, CMOS process technology for μm and mm wave ICs will develop faster.

Software Defined Radio (SDR) Software-defined radio (SDR) is a wireless communication technology. The wireless communication system, originally composed with amplifier, mixer, and filter, will be replaced by software, digital circuits, and embedded system, so that the system parameters are easily configured for different requirements. The SDR here refers to an integrated software-defined wireless transceiver. Its basic idea is to directly convert the RF signals using analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Figure 38.3 illustrates a block diagram of an integrated softwaredefined radio transceiver system. Software-defined radio (SDR) has a strong flexibility. It can configure and reconstruct RF and IF analog circuits, expand the functions by digital modules, and update circuit designs as process technology evolves. Software-defined radio requires the high performance on analog-to-digital converters (ADCs) in terms of dynamic range, sampling rate, etc. At present, it is difficult to fully implement an ideal software-defined radio transceiver chip. The most reported SDR transceiver chip is a reconfigurable transceiver chip, where the performance of each analog/RF module can be configured through digital circuits in order to realize multi-mode multi-band transceivers and the optimization of the RF specification is realized by adjusting parameters. At the same time, another realization scheme is based on the narrowband adjustable filter or mixer for lowering the carrier frequency of RF signal and reducing the performance requirements of analogto-digital converter (ADC). With the continuous development of IC manufacturing technology and design skills, fully software-defined transceiver chips will be realized in the near future.

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Fig. 38.3 Transceiver system

Software-defined radio (SDR) is different from cognitive radio (CR). The main difference is that CR has the ability of learning and perception. It can select the appropriate spectrum according to the existing communication channels, so as to limit and reduce the occurrence of conflicts and improve communication efficiency.

Radio Frequency Transceiver Design In a wireless system, an RF transceiver is used to process RF signals, and it is generally composed of RF front end and baseband circuits. The RF front-end serves to amplify the RF signal, and up/down convert the signal spectrum, etc. The baseband circuits usually include an analog baseband circuit for amplifying, filtering, and converting the signal and a digital baseband circuit for performing digital signal processing, etc. The existing receiver architecture usually includes a super-heterodyne receiver, a zero intermediate frequency receiver, a low intermediate frequency receiver, a digital intermediate frequency receiver, etc. Among them, the super-heterodyne architecture has a signal image interference problem and requires an RF image suppression filter; and it is less suitable for chip integration. The zero intermediate frequency architecture can perform directly down-convert the RF signal to the DC point without RF image signal interference, and it is more suitable for chip integration. Figure 38.4 illustrates a block diagram of a configurable narrowband zero IF receiver system. The transmitter converts the digital baseband signal into an analog signal through digital-to-analog conversion (DAC) and transmits the signal after filtering, spectrum shifting, and power amplification. The existing transmitter architecture mainly includes a direct conversion transmitter, an all-digital transmitter, a polar modulation transmitter, etc. Figure 38.5 is a block diagram of a commonly zero-IF transmitter system.

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Fig. 38.4 Configurable narrowband zero IF receiver system block diagram

Fig. 38.5 Zero IF transmitter system block diagram

At present, RF transceivers are widely used in the fields of mobile wireless communication, navigation, and data/audio/image data wireless transmission.

Low Noise Amplifier (LNA) Design Among a receiver path in a wireless communication system, low noise amplifiers (LNAs) are the first amplifiers that can amplify the weak RF signal received from the RX antenna [3]. The overall performance includes noise fig. (NF), gain, input impedance match, stability, and so on. 1. Noise Fig. (NF): NF of LNAs dominates the noise performance of the whole receiver. The definition of NF is NF ¼ 10lg

SNRin SNRout

ðdBÞ,

where SNRin is the ratio of signal to noise at the input and SNRout the ratio of signal to noise at the output.

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2. Gain: LNAs must have certain gain to suppress the noise contribution of subsequent stages, especially the noise from the mixer. In modern RF design, the gain of LNAs usually means the voltage gain. Among S-parameters (scattering parameters), S21 is used to measure its amplifying ability. In a receiver system design, LNA gain has some effect on the linearity of the receiver. 3. Input Impedance Matching: From the maximum power transmission point of view, it is necessary to consider the impedance matching between the LNA and the antenna. The performance of impedance matching is measured by S11 and also can be expressed by “return loss” which is given by Γ¼

2

Z in  Rs , Z in þ Rs

where Zin is the LNA input impedance and Rs is the signal impedance. After matching, the LNA is designed for a 50 Ω resistive impedance. 4. Stability: because the LNA must interface with the “outside” world, it necessarily remains stable for all source impedances at all frequencies. The parameter K is used to characterize the stability of LNAs: Κ¼

1 þ jΔj2  jS11 j2  jS22 j2 2 jS21 S12 j

,

where Δ ¼ S11S22  S12S21 and S11, S22, S12, and S21 are the S-parameters of a two-port network. If Δ < 1 and K > 1, the circuit is unconditionally stable. So far, there are mainly three types of LNA topologies. (1) Cascode commonsource (CS) with source inductive degeneration; this kind of LNAs is suitable for narrow-band RF receiver. (2) Cascode common-gate (CG) topology, it is widely used in wide-band receiver. (3) Noise-Cancelling LNAs, noise-cancelling techniques can be adopted in both common-source and common-gate topologies, which can result in good noise performance as well as wideband feature. With the development of portable devices, low power consumption has become an important requirement for RF transceiver IC. For good trade-off among noise performance, input impedance matching and power consumption, an extra capacitor can be added between the gate and the source of the input transistor inside the CS LNA to optimize the noise and impedance matching performances under certain power consumption.

Mixer Design The channel bandwidth of wireless communication is usually very narrow (such as GSM system, whose channel bandwidth is only 200 kHz), and the receiver usually converts the signal from the RF band to the lower or intermediate frequency

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(LF) band and then performs channel filtering. The circuit that completes the band conversion is the mixer. A wireless communication transceiver system usually includes the down-mixer in the receiver and the up-mixer in the transmitter. The main performance parameters of the mixer are as follows: (1) Noise, the noise figure of the mixer is related to the architecture of the receiver or transmitter. For IF receivers, the mixer noise is called single-sideband (SSB) noise; for zero-IF receivers, the mixer noise is called double-sideband (DSB) noise. Ideally, singlesideband noise is 3 dB higher than double-sideband noise. (2) Linearity: Linearity is often measured by the third-order intercept point (IP3) and the second-order intercept point (IP2). The gain of the low-noise amplifier has a large effect on the noise and linearity of the mixer. (3) Gain: The ratio of the effective value of the intermediate frequency output voltage to the effective value of the RF input voltage, that is, the conversion voltage ratio, also known as the conversion gain. A mixer with a certain gain helps to suppress the noise of the subsequent stage circuit in the receiving channel, and the design pressure of the power amplifier can be alleviated in the transmitting channel. At present, the mixer mainly has two structures: (1) A passive mixer with no amplification effect only serves as a switch. The voltage-type zero-crossing passive mixer has a gain of about 4 dB, and the non-zero-crossing passive mixer has a gain of about +1.48 dB. Current-type passive mixers have better noise and linearity performance than voltage types. (2) The active mixer converts the RF voltage into a current through a first-level common source FET; the local clock signal controls the switching transistor to output current; the down-converted intermediate/base frequency current is converted into a voltage signal through the load. Active mixers have higher gain than passive mixers. At the same time, due to the parasitic capacitance effect, the feedthrough effect between the various ports of the mixer needs to be emphasized in the design to enhance the isolation performance.

Frequency Synthesizer Design The frequency synthesizer is a circuit used to generate the high-resolution and highstability clock signal by synthesis methods. At present, there are three main implementations, i.e., the direct frequency synthesis, phase-locked loop (PLL)based synthesis, and direct digital synthesis. The PLL-based synthesizer is the most common one today, which features high integration, low cost, high performance, etc. The primary characteristics of a frequency synthesizer contains tuning range, frequency resolution, phase noise, and so on; the details are as follows: (1) Tuning range, the output frequency ranges from minimum to maximum; (2) frequency resolution, the minimum gap between two adjacent output frequencies; (3) switching time, the time necessary for the loop to settle, when the output frequency is switched from one to another; (4) phase noise, the ratio of noise power in 1 Hz bandwidth at a certain frequency offset to carrier power; and (5) spurious tone, the undesired discrete spectral component with a magnitude obviously higher than the noise floor.

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Fig. 38.6 Sigma-delta fractional-N frequency synthesizer

The PLL-based frequency synthesizer includes the integer-N synthesizer and fractional-N synthesizer. By adjusting the integer division factor, the former outputs a frequency that is an integer-N multiple of the reference frequency. While the latter yields a frequency that is a fractional-N multiple of the reference frequency by dynamically changing the division ratio, thus it is creating a fractional division factor on average. To reduce the fractional spur of the fractional-N synthesizer, nowadays the sigma-delta fractional-N frequency synthesizer has become a critically important architecture owing to the noise shaping function of the sigma-delta technique. As shown in Fig. 38.6, the classical sigma-delta fractional-N frequency synthesizer consists of a phase-frequency detector (PFD), charge pump (CP), loop filter, voltage-controlled oscillator (VCO), programmable divider, sigma-delta modulator, etc. With the continuous progresses in IC technologies, novel techniques and circuit topologies, such as all-digital PLL (ADPLL), multiplying delay-locked loop (MDLL), injection-locked oscillator (ILO), sub-sampling phase detector (SSPD), and so on, are advanced with enhanced performance in flexibility and portability of the frequency synthesizer. Due to the rapid progress of the wireless communications and radar technologies, the frequency synthesizers are developed toward higher output frequency, larger tuning range, lower phase noise, lower power consumption, and higher integration.

Radio Frequency Power Amplifier (RF PA) Design A RF power amplifier (RF PA) is an amplifying circuit that increases the power level of RF signal within a certain power range. It directly affects the performance of the RF transmitting channel. The main characteristics of an RF power amplifier are as follows: 1. Output Power: Total power of RF signal at load, which is output from RF power amplifier, is named as output power, usually expressed in dBm. The dBm is the logarithm of the RF signal power relative to 1 mW. The conversion relationship is:

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PdBm ¼ 10lg

PðmWÞ ¼ 10lgPðmWÞ: 1mW

2. Efficiency: Efficiency is one of the key specifications of RF power amplifier. It is usually characterized by two methods. One is the drain efficiency, which is described as the percentage of output power to DC power, i.e. η¼

Pout  100% PDC

The other is power-added efficiency (PAE), which is described as the percentage of power and increased power to DC power, i.e. PAE ¼

Pout  Pin  100% PDC

3. Linearity: Nonlinear distortion generated by RF power amplifier is expressed in both amplitude and phase. Linearity is usually expressed by 1 dB compression point and third-order intercept point. 4. Stability: Stability of RF power amplifier is determined by the S-parameters of RF amplifier. When K¼

1 þ jΔj2  jS11 j2  jS22 j2 >1 2jS21 jjS12 j

and Δ ¼ S11 S22  S12 S21 < 1, the RF power amplifier is unconditionally stable. There are two types of RF power amplifiers, i.e., linear power amplifier (conventional PA) and switching-mode power amplifier. According to the different conduction angles of transistors, linear power amplifiers are classified into Class A, Class B, Class AB, and Class C amplifiers, respectively. The conduction angle of Class A amplifier is 360 with the efficiency of less than 50%. The conduction angle of Class B amplifier is 180 with a higher efficiency than that of Class A amplifier, but a poor linearity which shows a crossover distortion. The conduction angle of the Class AB amplifier is between 180 and 360 with two-transistor push-pull method to avoid crossover distortion. It has a better linearity and higher efficiency. The conduction angle of Class C amplifier is less than 180 with the efficiency higher than Class A and Class B amplifiers. Switching-mode power amplifier is a kind of high-efficiency power amplifiers whose transistors operate in switching mode. It can be classified into Class D, Class E, and Class F amplifiers, respectively. Ideally, the voltage drop is 0 when the switch is turned on, the resistance is infinite when the switch is turned off, and the theoretical efficiency can reach 100%. Practically, the distortion of the switching power amplifier is much larger resulting in serious restricts on its application. Therefore, how to improve its linearity is drawing more attentions.

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To date, RF power amplifiers are designed and manufactured using three main processes: GaAs, SiGe, and RF CMOS. RF power amplifier in GaAs process is mainly suitable for high power output applications and widely used in wireless communication area. SiGe process is compatible with Si CMOS process, which is helpful to realize integration of RF power amplifier and RF IC. RF CMOS process can help realize higher integration and lower cost, but the performance of CMOS RF power amplifiers is still behind GaAs ones; thus, currently, RF CMOS process is mainly used for Bluetooth and Zigbee applications. In recent years, GaN has received more and more attentions as a new type of material for manufacturing high-power RF power amplifiers.

Radio Frequency Switch Design The RF switch is a RF component that can conduct and cut off the RF signal path. Its performance is mainly characterized by parameters such as isolation, operating bandwidth, insertion loss, switching time, power capacity, input standing wave ratio, and lifetime. A variety of different switch configurations can be constructed depending on the switch selection path. Figure 38.7 shows three typical switch configurations, including single pole single throw (SPST), single pole double throw (SPDT), and single pole multiple throw (SPMT). RF switches can be divided into electromechanical RF switches, solid state RF switches, and micro-machined (MEMS) RF switches. The electromechanical RF switch realizes the on/off control of the RF signal path through the RF relay. It has the characteristics of low insertion loss, high isolation, good antistatic discharge performance, and large power capacity, but its volume is large, the speed is slow, and the life is short. And it is difficult to integrate with RF circuits, mainly used in instrumentation, high-power multi-beam antenna systems, etc. Solid-state RF switches include diode RF switches and FET RF switches. The diode RF switch is a two-port device. It is equivalent to a linear resistor for the RF signal. The resistance is determined by the DC offset. When the bias is positive, the impedance is small and the switch is turned on. When the reverse bias is applied, the circuit is cut off and the impedance is large. The FET RF switch is a three-port device that is controlled by the gate, including GaAs p-HEMT RF switch and CMOS RF switch. Compared with the diode RF switch, the FET RF switch has a simple bias circuit and easy integration.

Fig. 38.7 Schematic diagram of the typical form of the RF switch

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MEMS RF switches are divided into two basic types: capacitive and contact. The capacitive switch uses an air bridge structure to adjust the capacitance to turn the switch on and off. The contact switch uses a cantilever structure to control the cantilever contact and disconnection state through an applied voltage to realize the RF switch. MEMS RF switches have the characteristics of low insertion loss, good linearity, and large bandwidth. At the same time, due to the conduction and cutoff through micro-mechanical structure, the switching time is longer and the service life is shorter. In the specific application, according to the installation form, the RF switches can be categorized into parallel switch, series switch and hybrid switch; while according to the functions, RF switches can be categorized into on/off switch (single pole single throw) and selection switch (single pole and multiple throw). In early wireless communication and radar systems, electromechanical RF switches were used, which were bulky and slow. In the early 1960s, diode RF switches began used as RF transceivers and phase shifters, which effectively improved the size and speed of RF switches, and became the mainstream technology for replacing electromechanical RF switches. They are still used in systems such as phased array radars. Around 1980, GaAs p-HEMT-based FET RF switches gradually replaced diode RF switches in low- and mid-power applications. In the late 1990s, with the development of CMOS technology, CMOS RF switch research and development received more attention. In 2007, Infineon developed CMOS SOI RF switch products. MEMS RF switches began to be researched around 2000. Due to their unique advantages, the development prospects have been optimistic. However, due to the problems of packaging and reliability, they have not been completely solved. Due to system integration with CMOS RF circuits and baseband circuits, the CMOS RF switches will be more commonly used in RF system chips. MEMS RF switches with process compatible with CMOS will be continuously developed. For high power applications, GaAs p-HEMT RF switches and diode RF switches are still used for a period of time.

Digital Radio Frequency Integrated Circuit (RFIC) Design To support the ever-increasing levels of SoC integration and low cost required by the consumer market, the RF circuit design has been progressed with the advanced scaled CMOS nodes; at the same time, the traditional RFIC design methodology also faces new challenges. Around the year of 2000, digital RF technology was advanced forward, which transformed the continuous-time analog RF functionality into digitally intensive or even all-digital implementations. Since the emergence of “digital RF,” there has been discussion whether the RF transceiver can be implemented all-digitally. The performance of some analog RF circuits, e.g., LNAs, off-chip filters, and PA, can be improved or replaced by using digital aids; however they are limited by the requirements for linearity, power consumption, interference suppression, and the CMOS technology.

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Frequency synthesizer is an RFIC that can be realized almost all-digitally. An all-digital phase-locked loop (ADPLL) with system diagram illustrated in Fig. 38.8 includes digitally controlled oscillator (DCO), phase detection, loop filter, and frequency control circuit. DCO generates the desired high frequency, and its function is similar to that of VCO in traditional frequency synthesizer. Phase detection mainly consisted of time-digital converter (TDC) and high speed counter, and its output is compared with the control words, processed by loop filter and then the control words for DCO are generated. The negative feedback loop exists inside the PLL which maintain a stable output frequency of DCO. Figure 38.9 illustrates an all-digital quadrature RF transmitter, in which both front-end baseband and back-end PA are implemented digitally. In order to suppress

Fig. 38.8 System diagram of all-digital phase looked loop

Fig. 38.9 System diagram of all-digital quadrature transmitter

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Fig. 38.10 System diagram of digital RF receiver

far-out noise and repetition spectrum, the pre-distorted baseband signal is up-sampled twice to a certain frequency. A two dimensional digital pre-distortion (DPD) and look-up table (LUT) are developed in the digital front-end (DFE) to restore digital power amplifier (DPA) linearity. Figure 38.10 shows a digital receiver suitable for WiMAX (Worldwide Interoperability for Microwave Access), including Gm amplifier, sampling mixer and two stages switch capacitor discrete-time filters and so on. For the consideration of noises and out-of-band interference suppression, low noise amplifier (LNA) and surface acoustic wave (SAW) are still implemented in the analog way.

References 1. T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn. (Cambridge University Press, 2012) 2. I.J. Bahl, Fundamentals of RF and Microwave Transistor Amplifiers (John Wiley & Sons, New Jersey, 2009), pp. 1–16 3. Z.Q. Li, Z.G. Wang, RF IC and System Design (Science Press, Beijing, 2014) (Chinese book series 4 of 5, ISBN 978-7-03-042254-5)

Power Integrated Circuit

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Tianshen Tang, Hao Ni, and Xiaoyan Liu

Contents Power Device and BCD Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Power Integrated Circuit (SPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Integrated Circuits (PMIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Energy Harvesting and Transformation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Converter and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC/DC Converter and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

This chapter dedicates to the introduction of the power integrated circuit (PIC), including: (1) power device and BCD processes; (2) the definition of smart power integrated circuit (SPIC); (3) power management integrated circuit (PMIC) together with their circuit structures, development trends, and challenges; (4) energy harvesting and transformation control concepts; (5) AC/DC converter and driver; and finally (6) DC/DC converter and driver circuit structures. Keywords

Power integrated circuit · Smart power integrated circuit · Power management integrated circuits · Energy harvesting · Switch control · AC/DC converter and driver · DC/DC converter and driver T. Tang Leapfive Technology Co., Ltd., Guangdong, China H. Ni (*) Semiconductor Manufacture International Corporation, Shanghai, China e-mail: [email protected] X. Liu Silicon Storage Technology Inc. (SST), Shanghai, China Institute of Microelectronics, Peking University, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_39

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Power Device and BCD Process Power devices are devices for power processing. According to the difference of their carriers, power devices can be classified into bipolar and unipolar devices, including power diode, giant transistor (GTR), thyristor, gate turn-off transistor (GTO), and insulated gate bipolar transistor (IGBT). A representative device of the unipolar type devices is the double-diffused MOSFET (DMOS). Based on the differences of the materials, devices can be categorized into silicon-based and wide bandgap material–based groups, e.g., silicon carbide (SiC) and gallium nitride (GaN) [1]. Other power devices are introduced in detail in Chap. 6. We briefly introduce IGBT, DMOS, and wideband devices in this chapter. Formed by the bipolar junction transistor (BJT) and the metal oxide silicon field effect transistor (MOSFET), an IGBT transistor is a composite fully controlled by voltage-driven device. It is characterized by its high input impedance, low conduction voltage, and domination in the market of medium voltage systems above 600 V. DMOS device is of dual-diffusion type, i.e., it is doped twice at the source and drain regions, with high concentration at first time and low concentration at the other time. Compared with IGBT, DMOS device has higher switching frequency. Based on the device structures, the devices can be classified into vertical double-diffused MOSFET (VDMOS) and lateral double-diffused MOSFET (LDMOS). VDMOS is a voltage-controlled device. Due to its poor compatibility with CMOS devices, its development is slow. On the other hand, LDMOS has good compatibility with CMOS devices, hence it has been widely used in RF power circuits. The wide bandgap materials SiC and GaN have the characteristics of wide bandgap width, high saturation drift velocity, and high critical breakdown electric field, which are ideal materials for manufacturing high-power, high-frequency, highvoltage, high-temperature, and radiation-resistant electronic devices [2]. As the improvement of SiC single-crystal growth technology and GaN epitaxial technology, the development and application of wide bandgap power devices are progressing rapidly [2, 3]. Wide bandgap material power devices are mainly used for discrete devices. Since 2009, GaN driven integration trend has become a hot topic industry wide [4]. Before the 1980s, the bipolar process was the mainstream process for manufacturing power devices, and bipolar devices had characteristics of high accuracy and low integration. In comparison, CMOS devices had features of high integration, low power consumption, and simple logic control. Therefore, the integration of bipolarCMOS can complement the merits of the two technologies with each other. On the other hand, DMOS devices can provide high power without DC drive, and are compatible with CMOS technology. Moreover, its advantages of fast switching speed, high input impedance, good thermal stability, and strong reliability make it widely used in high-speed switches. Hence, BCD (bipolar-CMOS -DMOS) technology emerged. BCD technology refers to the integration of the bipolar, CMOS, DMOS, resistor, capacitor, and other devices on the same process platform. The advantages of three types of active devices, namely the high precision of bipolar devices, the high degree of integration of CMOS devices, and the high power

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processing capacity of DMOS devices, are combined in the BCD process, making BCD process widely used.

Smart Power Integrated Circuit (SPIC) Integrating high-voltage power devices, control circuits, protection circuits, detection and diagnosis circuits, peripheral interface circuits, and signal processing circuits on to the same chip forms power integrated circuit (PIC) [4]. Compared to discrete devices, PIC has more advantages in reliability, stability, power consumption, volume, weight, and cost. In the past, the power IC is usually divided into highvoltage power IC and intelligent power IC groups [5]. The chips integrating 200 V and above power devices and control circuits are called high-voltage power integrated circuits [1]. However, with the continuous development of PIC, it is difficult to distinguish them in terms of working voltage and device structure, so they are now collectively referred to as smart power integrated circuits (SPIC). In the late 1970s, intelligent power integration technology emerged. BJT and GTO were popular power devices at that time. However, their requirement for large driving current and sophisticated control circuit structure limited the development and progress of power integrated circuits at that time. In the 1980s, gate-controlled power devices, such as power MOS and IGBT, appeared. Such gate-controlled devices have the characteristics of high input impedance and low driving power consumption [5], solving the problem of large driving current required by previous devices. However, the complicated system structure design and high process cost still limit the application scope of PIC in that era. Since the 1990s, as the continuous improvement of PIC design and technology, the cost-performance ratio has been gradually improved; it has led to its application in automotive electronics, flat panel display, motor drive, motor control, power management, and other aspects. Power control, sensing and protection, and intelligent interface are the three main functional modules of SPIC [1]. The power control module consists of switching power devices and driving circuits, which are mainly used for terminal power processing. The sensing protection circuit is mainly used to protect various abnormal situations, such as overcurrent, overvoltage, undervoltage, overtemperature, short circuit, and open circuit, to improve the stability and service life of the chip [1]. The intelligent interface circuit is implemented by logic CMOS, which is mainly used to process instructions and control the response of power devices, and meanwhile transmit the working status, load information, and other detected information back to the system. As the development of BCD technology, interface circuits can integrate storage modules, RF modules, microcontroller unit (MCU) and other multifunctional modules onto a chip, which results in the broad adoption of such power devices in portable structures and intelligent applications, such as wearable devices, medical devices, wireless transmission, and Internet of Things (IoT) [6]. From the perspective of the development trend of power semiconductor devices and integration technologies, the primary technical challenges at present are making power devices more energy efficient, higher working frequency, and higher working

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voltage range, and optimizing and improving integration technologies with respect to the scale of integration, intelligence, and reliability [1]. Therefore, the main research tasks of PIC might include the following subjects: developing BCD technology with higher voltage, power, and density for higher yield and lower cost [1]; exploring novel device structures with lower power consumption and suitable for denser integration; developing more efficient PIC control methods; developing PIC devices operating stably at high temperature; and developing horizontal power devices with self-protection feature and being controlled by highcurrent high-speed MOS transistors. The critical object for PIC development is to integrate low-voltage circuit with multiple high-voltage power devices on to the same silicon die or a device module so that it has system functions and realizes the integration of the monolithic power system [1].

Power Management Integrated Circuits (PMIC) The major functions of PMIC are to transform, distribute, monitor, and manage other electric energy. Having the advantages of convenient to use, low cost, small size, excellent performance, and high reliability [7], PMIC is widely used in mobile phone, computer, consumer electronic products, power supply, charger, and other applications. According to the differences of internal structures, PMIC is mainly classified into linear voltage regulators, charge pumps, and switching voltage regulators as compared in Table 39.1. A linear regulator controls the transistor working in the linear region [7] via comparing to the reference voltage to the voltage generated by the resistance voltage divider [7], so that the input voltage is regulated by the transistor in the linear region, producing the output voltage required by the application. The characteristics of the linear regulator are: the transmission transistor works in the linear region, without an on-off jump, limited to step-down conversion. Linear regulators mainly include traditional linear regulators and low dropout (LDO) regulators [7]. The traditional linear regulators use BJT as power transistors and adopt the following mode of source; on the other hand, the LDO regulators use mainly PMOS transistors and adopt the mode of the common source connection. The basic structure of LDO is shown in Fig. 39.1. Table 39.1 Comparison of voltage management circuits Parameter Regulation type Noise level Efficiency Power capability EMI level

Linear voltage regulators Buck Low Low Medium Low

Charge pumps Buck, boost Medium Medium Medium Medium

Switching voltage regulators Buck, boost High High High High

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Fig. 39.1 The basic structure of LDO

Fig. 39.2 Dickson pump circuit structure

The following specifications need to be considered in the design of LDO: difference voltage between the input-output voltages, maximum/minimum load currents, linearity/load instantaneous voltage response, transient recovery time, zero/pole, phase margin, and static operating point [7]. The charge pump, also known as switched capacitor regulator, provides voltage conversion using capacitor and several switches [7]. Unlike linear regulators, the charge pump can produce an output voltage higher than or less than the input voltage; the regulator can be used as a booster or step-down regulator [7]. In the design of the charge pump, the on-off is usually realized by MOS transistors, whose size is related to the switching frequency. The higher the frequency is, the wider the channel width of these transistors. However, with the increase of transistor size, dynamic power consumption also increases due to the increase of gate oxygen capacitance [7]. Therefore, a trade-off between the switching frequency and the energy efficiency of the switching capacitor regulator needs to be made [7]. Figure 39.2 shows a typical Dickson pump structure, in which PMOS transistors M1, M2, M3, and MOUT are on and off transistors, and CT1, CT2, CTN, and CSTORE are charge storage capacitors, of which special attention should be paid to BULK connections. Switching regulator (SWR) is widely used in power management systems for its high efficiency, high driving capability, and adjustable output voltage. Switch regulators are characterized by the facts that the switch must be fully switched on or off for any given cycle [7]; the regulator must be equipped with one or more similar inductive and capacitive energy storage elements [7]; the regulator has multiple topological structures (buck, boost, buck-boost, etc.); and the efficiency of SWR is almost 100% when the circuit elements are ideal ones. The switching

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voltage regulator adopts a negative feedback control loop, as shown in Fig. 39.3. The block diagram in the figure is pulse width modulation (PWM), which can be replaced with pulse frequency modulation (PFM), phase control (PWM-PFM), and other methods. According to the differences in energy storage modes, SWR can be classified into two categories. The first category is nonisolating switch voltage stabilizer, which uses inductance to store energy and has no isolation between output power and input power [7]. Its advantages are its simple structure, low cost, and wide range of output voltage regulation. Its basic structure is shown in Fig. 39.4 [8]. The second category is isolation SWR. The basic structure is shown in Fig. 39.5 [8]. It uses a transformer to store energy and achieve the physical isolation between the input and output ends. The advantage of isolated SWR is that it reduces the mutual interference between the output power supply and the input power supply, and improves the antinoise ability. Noise and ripple suppression are two key factors to be considered in PMIC design. The noise is usually the sharp pulse produced by the turning on or off the transistors. The fluctuation of DC stable voltage usually causes ripples [9]. Fig. 39.3 Block diagram of voltage regulator of switch power supply

Fig. 39.4 Nonisolated switch voltage regulator structures

Fig. 39.5 Isolated SWR: forward/back topology comparison

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As the development of information technology, the market demands for high performance, low power consumption, portable, and other devices are increasing, which promotes the growth of PMIC [9]. At the same time, due to the continuous improvement of integrated circuit design capability and increasing maturity of process, PMIC begins to advance toward miniaturization and intelligence, highenergy efficiency and precision, low power consumption and low working voltage, etc.

Energy Harvesting and Transformation Control Energy harvesting is to obtain energy from the environment through energy harvesting technology. In essence, through photovoltaic, thermoelectric, piezoelectric, electromagnetic, and other effects, the energy existing in a broad range in the environment, such as light energy, thermal energy, wind energy, mechanical energy, and so on, is transformed into electrical energy that can be used [10]. The core meaning of energy harvesting is that it can provide energy continuously without consuming additional fuel and materials [10]. Energy levels generated by different energy sources are shown in Fig. 39.6. Currently, there are three important energy sources that can be used for energy harvesting: electromagnetic radiant energy, thermal energy, and mechanical energy [10]. Electromagnetic radiant energy includes solar energy and radiofrequency radiant energy. Solar energy conversion into electricity, namely photovoltaic power generation, is a mature large-scale energy collection technology [10]. Radiofrequency radiation can be the power supply for all kinds of radiofrequency identification (RFID) card and transmit information, has been widely used in public transport, identification [10], etc. A switch control circuit consists of two parts, voltage regulation and protection. The heat energy that can be collected mainly includes temperature gradient and heat flow [10]. The basic principle of thermoelectric batteries or thermoelectric generators is to use the thermoelectric effect to convert heat energy into electricity through temperature difference [10]. However, thermal gradients greater than 10  C at small

Fig. 39.6 Energy levels of different energy sources

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sizes (e.g., 1 cm3) are hard found [10]. As a result, the low efficiency of the microthermoelectric generator limits its application range. Mechanical energy includes all the energy produced by vibration, shaking, rotation, etc. There are three types of vibration collectors: electrostatic, piezoelectric, and electromagnetic [10]. The working principle of an electrostatic collector is mainly based on variable capacitance, which changes the distance or relative area between the plates through external mechanical vibration, so as to change the capacitance, and then convert the vibration energy into electric energy [10]. The piezoelectric collector works through the piezoelectric effect of piezoelectric materials [10]. When mechanical stress is applied to the piezoelectric material, charges are generated on the two plates of the material. On the contrary, when a voltage is applied to the two plates of the piezoelectric material, the material will generate internal mechanical stress [10]. The electromagnetic collector works on the basis of Faraday’s law of electromagnetic induction. A relative movement of the permanent magnet and the coil to each other results in induced voltage in the coil [10]. The following basic requirements need to be considered. The modulator is a closed-loop system. To meet the required stability of the output voltage, the gain of the control circuit loop must be sufficiently high, so to assure the input voltage, load and temperature changes maintained in a certain range. Other requirements of dynamic response speed and range, etc. also need to be considered [7]. This requires the use of multiple feedback techniques and appropriate calibration circuits. In addition, soft start and overcurrent protection, as well as overvoltage protection functions should also be considered [7]. If necessary, the feedback input needs to be isolated from the output of the control circuit. Fig. 39.7 is a schematic diagram of the traditional series transformation control system. The first stage converts the collected energy into DC energy for storage through AC/DC and DC/DC regulators, and the second stage converts the stored energy to the load by a DC/DC regulator, providing stable working voltage and current. Because the input energy is converted two times, the energy conversion efficiency is low [7]. Fig. 39.8 is a schematic diagram of the parallel transformation control system. The primary path of the parallel structure directly converts the energy through the AC/DC and DC/DC voltage regulator to load, work voltage is generated at load. The slave path transforms the redundant energy into DC energy for storage and provides the DC energy to load side through DC/DC voltage converter when needed. This is Fig. 39.7 Schematic diagram of series energy transformation control system

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Fig. 39.8 Schematic diagram of parallel energy transformation control system

why the parallel transformation can improve the power conversion efficiency while keeping the energy storage function at the same time [7].

AC/DC Converter and Driver The energy harvested is usually alternate current (AC) signal, so the signal must be converted to direct current (DC) signal before it can be utilized or stored. AC/DC converter converts the AC signal into DC. It is bidirectional in power transportation [11]. In AC to DC transformation where the current flows from source to the load, it is called rectification; in DC to AC transformation, where the current flows from the load to the power supply, it is called active conversion [11]. After 50/60 Hz AC current is inputted into AC/DC regulator, it needs to be rectified and filtered; high frequency, high voltage, and large current of filtering limit the progress of AC/DC regulator to be modularized [11]. There are two types of AC/DC regulator, one-stage regulator and two-stage regulator. The two-stage power supply consists of power factor correction (PFC) and DC/DC regulator, as shown in Fig. 39.9a. The PFC control and output voltage regulator are separated, and there is a capacitor for energy storage between the two stages. The two-stage power supply is widely used in high-power applications for its high reliability, while the energy efficiency is not high. The one-stage power supply is shown in Fig. 39.9b, which also includes PFC and DC/DC voltage regulator, but combined together there is no energy storage capacitor between them. The one-stage power supply has high energy efficiency but low reliability [12]. In industry, the two-stage AC/DC architecture is mature and standardized technology from both aspects of design and manufacturing. While the modularization progress of one-stage AC/DC architecture is limited due to complex technical and fabrication problems [13]. A rectifier converts AC signal to D. There are mainly three types of rectifiers, half-wave rectifier, full-wave rectifier, and bridge rectifier. Among them, the bridge rectifier is the most commonly used. The bridge rectifier uses four rectifier diodes.

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Fig. 39.9 Two-stage and one-stage AC/DC topology

Fig. 39.10 Two-stage AC/DC voltage regulator circuit structure

Fig. 39.11 Single-stage HB-LED driver circuit structure diagram

Connecting D1, D2, D3, and D4 as shown in Fig. 39.10 is a full-wave rectifier [12]. After an AC power supply passes through the rectifier, the output needs to be reshaped by a PFC to maximize the active power absorbed by the load [13]. The PFC structure is shown in the middle of Fig. 39.10, which generally consists of an inductor LR, a diode D5, and a power switch S1, followed by an energy storage capacitor Cs. DC/DC regulator architecture will be discussed in detail in Section 6. High-brightness light emitting diode (HB–LED) driver bases on high-efficiency AC/DC voltage regulator. Because of its long operation lifetime, green environmental protection, high luminous efficiency, and flexibility of color mixing and dimming control, HB-LED is widely used in homes, offices, and street lighting [14]. The single-stage HB-LED driver circuit structure is shown in Fig. 39.11 [14]. Besides the

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first stage an AC/DC rectifier, the whole circuitry consists of power switches S1 and S2, inductors L1 and L2, magnetic coils N1 and N2, diodes D5–D8, and energy storage capacitor.

DC/DC Converter and Driver In a power system, firstly an AC/DC is used to convert AC signal into DC signal. Then a DC/DC is needed to convert the obtained DC signal to the specific DC voltage required by each circuit module in the subsystem. Advanced power management techniques generally adopt multiple on-chip voltage domains to effectively leverage the balance between latency and power consumption [7]. The system frame structure of DC/DC regulator is shown in Fig. 39.12. Output Uo of DC/DC voltage regulator with input Uin are multiplied by k, where k is the gain factor. There are three basic types of DC/DC: buck, boost, and buck-boost. The three basic topologies of DC/DC are shown in Fig. 39.13. Figure 39.13a is a buck regulator; Fig. 39.13b is a boost regulator; and Fig. 39.13c is a buck-boost regulator, which is a combination of buck and boost. All the three architectures are composed of switches S1 and S2, inductor L, and capacitor COUT. A driver circuit is located between the main circuit and the control circuit, which is mainly used to amplify the signal of the control circuit so as to drive power devices [7]. After receiving the input signal, the drive circuit converts the signal voltage level to control the switching on or off of the power device according to the control target requirements. For example, for a semicontrolled device, the circuit only provides a turn-on control signal; for fully controlled devices, it is necessary to provide two different control signals, namely on and off, as well as electrical isolation [7]. Fig. 39.12 Block diagram of DC/DC voltage regulator

Fig. 39.13 Basic topologies of DC/DC

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Fig. 39.14 Gate driver circuit diagram

Fig. 39.15 Boost gate driver structure based on DC/DC voltage regulator

Gate driver is the interface circuit between the microprocessor (MCU) and power switch (IGBT, MOSFET) [15]. The schematic diagram of a gate driver is shown in Fig. 39.14 [15]. It consists of diode Don/Doff, RG, on/RG, off, and the power transistor. In recent years, because the utilization of gate/source capacitor for energy storage can improve the efficiency of Gate Driver, Resonant Gate Drivers (RGD) [16] technology has been widely studied. However, the complexity of RGD architecture makes it difficult to control [16]. Accordingly, bidirectional gate driver (BGD) comes out. A DC/DC regulator based boost gate driver structure is shown in Fig. 39.15; it consists of three small size transistors M1, M2, M3, energy storage components Cs and Ls, and power transistor Mp. Gate of Mp is driven by the gate driver circuit [17].

References 1. S. Weifeng et al., Status and prospect of development of power semiconductor devices and power integration technology [C]. Science China Inf. Sci. 42(12), 1616–1630 (2012) 2. Z. Bo et al., Gallium nitride power semiconductor device technology [C], research and progress. Solid State Electron. 30(1), 1 (2010) 3. H.-S. Choi, Improvement of turn-off energy loss (Eoff) variations by low Mg doping in p-GaN gate power devices. IET J Mag. 53(3), 196–198 (2017) 4. Z. Bo, L. Xiaodong, L. Zhaoji, Electric Field Optimization Technology of Power Semiconductor Devices (University of Electronic Science and Technology Press, Chengdu, Sichuan, China, 2016) 5. H. Hui et al., The Theory and Design of Power Integrated Circuit Technology (Zhejiang University Press, Hangzhou, Zhejiang, China, 2011) 6. T.-K. Chien, Low-power MCU with embedded ReRAM buffers as sensor hub for IoT applications, [J]. IEEE J. Emerg. Selected Topics Circuits Syst. 6(2), 1 (2016)

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7. K.-H. Chen, Power Management Techniques for Integrated Circuit Design (Wiley, Singapore, 2016) 8. C. Xin, Study on high frequency and high voltage pulse for electric dust removal, Ph.D. Dissertation (Dept. Environ. Sci., Anhui U. of Sci. & Tech., Huinan, Anhui, China, 2014) 9. Satoshi, Fundamental study of influence of ripple noise from DC–DC converter on spurious noise of wireless portable equipment [J]. IEEE J. Mag. 31, 2111–2119 (2016) 10. W. Peihong, Research on micro-electromagnetic vibration energy collector based on MEMS technology (Shanghai Jiaotong University, Shanghai, China, 2010), pp. 1–8 11. E. Salman, High Performance Integrated Circuit Design [ISBN: 978–0071635769], 2012 12. C. Li, X. David, A family of enhanced ZCS single-stage single-phase isolated AC-DC converter for high power high voltage DC supply. IEEE Trans Ind Electron. 64(5), 3629–3639 (2017) 13. S. Nigsch, J. Marquart, K. Schenk, Low Cost High Density AC-DC Converter for LED Lighting Application (PCIM Europe, Nuremberg, Germany, 2016) 14. I. Castro et al., Single-stage AC/DC dual inductor BCM current-fed push-pull for hb-led lighting applications [C], in Energy Conversion Congress & Exposition, (2017), pp. 1–8 15. P.K. Prasobhu et al., Gate driver for the active thermal control of a DC/DC GaN-based converter [J], in Energy Conversion Congress & Exposition, (2017), pp. 1–8 16. Z. Zhang, A high-frequency dual-channel isolated resonant gate driver with low gate drive loss for ZVS full-bridge converters [J]. IEEE Trans. Power Electron. 29(6), 3077–3090 (2014) 17. Y. Juzheng, Gate-drive circuit with efficient energy recovery based on DC/DC converter [J]. Electron. Lett. 52(11), 952–954 (2016)

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Xiaolang Yan, Jianyi Meng, and Zhijian Chen

Contents Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Architecture (ISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Instruction Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Instruction Multiple Data (SIMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multithreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multicore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manycore Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics Processing Unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Central processor unit (CPU) is considered as the pearl on the crown of IC industry. It is an important driving force of Moore’s law in the past decades. This chapter starts with the introduction of some basic concept of the processor, e.g., instruction set architecture (ISA), data path, control logic, coprocessor, pipeline, multi-issue, single instruction multiple data, multithread, multicore, manycore, memory architecture. It also introduces several common types of processor, e.g., digital signal processor (DSP) and graphics processor unit (GPU).

X. Yan · Z. Chen (*) Institute of VLSI, Zhejiang University, Hangzhou, China e-mail: [email protected] J. Meng Department of Microelectronics, Fudan University, Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_40

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Keywords

Processor · Instruction set architecture (ISA) · Pipeline · Multicore · Memory architecture

Processors The processor is a very large scale integrated (VLSI) circuit, and is the core chip responsible for computation and controlling. The most commonly used processor is the central processing unit (CPU), whose main functions are to interpret and execute computer instructions, perform data operations, or control peripherals. As shown in Fig. 40.1, CPU, memory, and I/O device are three core components of an electronic computer. The instruction system is a basic technology applied to the design of processors, which defines the interface between software and hardware, and also determines the application ecosystem of processors. The hardware components of a processor include datapath and control logic; and the fundamental operation of a processor is made up of four (4) basic steps, i.e., instruction fetching, decoding, execution, and write back. In order to improve the computing capability of processors, the instructions are usually executed in a pipelined manner. Technologies were adopted to improve the instruction- and data-level parallelism of the processors over multi-issue technology and single instruction multidata technology. In order to improve the parallel processing capability at the transaction level, most of current processors adopt a multicore architecture, that is, a chip contains multiple processing cores. Manycore processors are specialist multicore processors designed for high degree of parallelism. In addition, different forms of processors such as digital signal processors (DSP) and graphics processing unit (GPU) have also been developed for specific applications. With the development of IC technology and the continuous scaling of technology, the leakage current of transistors has gradually increased, and the power consumption density per unit area has been continuously increased. Therefore, the reduction of power consumption has become a major challenge in the design of processors, which is called “Power Wall” problem. Besides, the

Fig. 40.1 Core components of traditional computer and CPU chip

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processor’s processing capability is heavily dependent on the memory speed, but the increase in memory speed cannot keep up with the increase in processor speed. Thus, memory has become a limitation to the performance of processors, which is called “Memory Wall” problem. The processors may be divided into five categories as per applications, i.e., supercomputer processors, server processors, desktop PC processors, mobile smart terminal processors, and embedded system processors. Each of the above areas has established its own ecosystem of software and hardware. (1) The supercomputer processors mainly include x86 processors of Intel and AMD, POWER and PowerPC processors of IBM as well as SPARC processors of Fujitsu. NVIDIA’s GPUs and Intel’s PHI accelerators have also been applied to the supercomputers. Chinese supercomputer processors include Sunway processors researched and developed by Shanghai High-performance IC Design Center and FeiTeng processors by National University of Defense Technology, which have been respectively applied to “TaihuLight” and “Tianhe” series of supercomputers. (2) The server processors focus on computing capability of a single chip. Currently, such server processors mainly include POWER processors of IBM and x86 processors of Intel/AMD. In recent years, ARM has been also endeavoring to develop server processors. (3) The desktop PC processors pay more attention to computing capability and cost, and are now dominated by x86 processors of Intel and AMD. Shanghai Zhaoxin Semiconductor Co., Ltd. in China has secured the ability to develop x86 processors. (4) The mobile intelligent terminal processors, also called application processors (AP), are widely applied to smartphones, tablet PCs, and smart TVs, which focus on energy efficiency, and are now mainly dominated by ARM. International companies engaged in developing AP based on ARM architecture include Qualcomm, Samsung, and the like, while Chinese companies engaged in R&D of such processors include Hisilicon, Unisoc, MediaTek, Datang Semiconductor, and the like. (5) Embedded processors are widely applied to a variety of embedded systems as microprocessors and microcontrollers. Such processors are diverse in forms and usually embedded in the form of SoC, whose processing capability differs depending on market demands, and have such technical features as low cost and low power consumption. The international mainstream embedded processors are CPUs based on ARM, MIPS, Tensilica, and SPARC architectures. Chinese mainstream embedded processors are CK series of CPUs developed by Hangzhou C-SKY Microsystems and CPU products developed by Suzhou Guoxin through introduction of certain technologies from Motorola and IBM PowerPC. The 4004 processor launched by Intel in 1971 was the first processor in the world. After more than four decades of development, the processors have evolved from 4 bits to 64 bits, with their frequency from MHz to GHz, and their structure from single-stream structure to multithread structure and their architecture from singlecore architecture to multicore and manycore architectures. The processor technologies based on Von Neumann architecture appears maturing. The development tendency of such traditional processors based on Von Neumann architecture is mainly to develop more efficient processor products in combination with more advanced technologies. Quantum computer is a research focus in computer field in

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recent years, and is a new generation of high speed computer based on the laws of quantum mechanics. Thanks to multibit parallel processing capabilities of quantum, quantum computers will contribute to huge improvements in computing capability. Recently, the new processor architecture for brain-like computation has gradually entered the public’s field of vision and has drawn a widely public attention by virtue of its higher processing efficiency than that of Von Neumann architecture based processors in such fields as deep learning of artificial intelligence, and is expected to achieve important applications.

Instruction Set Architecture (ISA) Instructions are machine languages that can be read and understood by the processors, and can define a sequence of commands understood and executable by computer hardware, and are ultimately run on the processors. The instruction set, also called instruction system, is the interface between software and hardware, and includes not only all commands supported by the processor, but also a sequence of specifications necessary for complete operation of a processor such as instruction format, operand type, addressing mode, programming model, memory architecture, interrupts, and exceptions. Different processor hardware may be designed for the same instruction system. The instruction set architecture (ISA) determines the ecosystem of the upper application software. The more plentiful the application software ecosystem is, the more developers will enrich the application software ecosystem. The instruction set architecture is often referred to as the instruction architecture. In designing a processor, the unity of instruction architecture is conductive to the accumulation of software ecological resources. Processor designers can design processor hardware with different performance based on the same instruction architecture so as to achieve software compatibility during constant hardware upgrades as shown in Fig. 40.2. All desktop processors manufactured by Intel are compatible with x86 instruction set.

Fig. 40.2 Software compatibility and hardware optimization based on the same instruction architecture

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Basic instructions of processors usually include three basic categories, i.e., data processing, arithmetic operations, and program flow control. (1) The main functions of data processing instructions are to transmit and prepare for operands and computing results. (2) The main functions of arithmetic instructions are to perform data operations, including arithmetic, logic, bit operations, comparisons, etc. (3) The main functions of program flow control instructions are to implement the jump of the program, and typical control flow instructions include branch instructions, jump instructions, and the like. The instruction format refers to the binary description of the instruction and is also known as the machine code. Usually, a machine code includes several typical fields, i.e., operation code fields, operand fields, and immediate fields. Operand fields are used to indicate the data width of the operand during the computing process. Currently, the common operand widths are 8 bit, 16 bit, 32 bit, and 64 bit, which correspond with character, short integer, integer (single precision floating point) and long integer (double precision floating point), respectively, in C language. The maximum operand (data) width supported by the processor hardware is also typically defined as the processor’s processing width. For example, a processor that supports the computing of up to 64-bit operand is often referred to as a “64-bit processor.” The programming model is a general term for all the hardware resources that software designers have an access during interaction with hardware, and usually includes general-purpose register resources, control register resources, interrupts and exceptions, storage space resources, and the like. The common instruction systems include complex instruction set computer (CISC) and reduced instruction set computer (RISC), which are often referred to as complex instruction set and reduced instruction set, respectively. The CISC processor is characterized by its powerful single instruction, which can contain multiple operations. In addition, the instruction length of the CISC processor, as a variable length instruction system, is usually not fixed. In the past, instructions were usually designed to conduct complex operations due to high storage costs, and such processors usually adopted CISC architectures. The RISC processor is characterized by its simple function of a single instruction, which generally contains one operation only, simplified design of processor hardware, and optimization of compiler. The RISC processor has a fixed instruction length. The current mainstream x86 architecture is based on CISC instruction system with strong computing capabilities and sound compatibility and has been widely applied in such fields as supercomputers, servers, and personal computers. The ARM architecture is based on RISC instruction system with better energy efficiency and low hardware design cost, and is widely used in the embedded field. After nearly four decades of development, the instruction systems supporting the basic functions of the processor have been matured. A variety of instruction architectures have established monopoly in the segments of applications. The instruction systems will be developed further in future by integrating more specific instructions for new applications. Intel has added multimedia, virtualization, and security-related extended instruction sets to x86, and AMD has added a new instruction architecture for 3D and heterogeneous computation. Besides, ARM has also added corresponding extension instructions as to multimedia, security, graphics, etc. for

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the embedded field. In the future, x86 instruction architecture is expected to continue to enjoy market dominance in such fields as high-performance computation, servers, and desktops; the ARM and other RISC architectures will continuously dominate in the mobile phone and embedded systems with low power and low cost.

Datapath Datapath, also known as data channel, is one of core circuits of a processor and is responsible for data storage, transmission, computation, etc. Characterized by its regular circuit structure and single function, it is usually a critical path in propagation delay in processor circuits, i.e., the bottleneck to improve processor frequency. The datapath performs data operations under the control of the control logic, as shown in Fig. 40.3. The common datapath consists of memory (instruction memory and data memory), register file, arithmetic and logic unit (ALU), multiplier and divider (MD) unit, floating-point unit (FPU), and load store unit (LSU). Instruction memory and data memory are memory units in a processor that store instructions and data, respectively. The instruction memory includes read only memory (ROM), flash memory (NAND, NOR), static random access memory (SRAM), and dynamic random access memory (DRAM). The data memory requires real-time read/write operations, and is usually embedded in the form of SRAM and DRAM. The register file, as the main datapath of a processor, is used to store the operands during execution and the result written back after execution. The register file is a high-speed memory unit implemented by registers or flip-flop-based circuit to cache the most frequently used data during program execution. The arithmetic and logic unit (ALU) is a circuit intended for arithmetic and logic operations and is the most basic in a processor. Starting with an 8-bit microprocessor, the ALU is an important part of the processors. Modern CPUs, DSPs, GPUs, and other types of processors all contain different types of ALUs. The multiplier and divider unit (MD) is the execution unit responsible for multiplication and division. In modern processors, unsigned and signed multiplier

Fig. 40.3 Datapath and control logic

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and divider operations are generally implemented in instruction set, which will be executed uniformly within the multiplier and divider unit. In terms of circuit implementation, the multiplier and divider unit includes a multiplier and a divider. The multiplier is the critical path of a processor. In order to speed up the computing, the Booth structure, also known as the Booth’s multiplier, is usually adopted. The floating-point unit (FPU) is a dedicated module that handles floating-point operations in a processor. Floating-point numbers provide a larger range of values and higher data precision than integers. In terms of the type of operation supported, the floating-point unit mainly implements the operations specified in the IEEE-754 protocol, including addition, subtraction, multiplication, multiplication and accumulation, division and square, comparison, data format conversion, and the like. The circuit scale and design complexity of floating-point units are higher than those of other datapath units. The load-store unit (LSU) is a hardware module responsible for data exchange between the processor and the data memory (outside the processor). The data from memory needs to be accessible during the running of the processor, that is, to execute load instruction and obtain data from the memory and put such data into the processor, and to execute storage instruction and put the data in the processor to the memory outside the processor. If the data cache is implemented in the processor, the load-store unit is also responsible for data access and interaction with the cache. Usually, the static random access memory (SRAM) is adopted for the cache. Given the cost constraints, at present, high-performance CPUs are usually designed with a cache of up to 16 MB, and embedded CPUs are usually designed with a cache of up to 64 KB. The main technical indicator of datapath processing capability is the width of arithmetical data. The first commercial processor, the Intel 4004, was 4 bit, and the subsequent Intel 8008 was 8 bit, and later, the processor evolved from x86 architecture to 32-bit architecture, and is now 64 bit. Current supercomputing, server, and desktop processors are 64-bit and 32-bit compatible. The mobile application processor has been 32 bit for a long term before entering the 64-bit era around 2015. Given the continued decrease of costs and power consumption of transistors, current embedded processors are gradually evolving from 8-bit/16-bit data width to 32-bit data width.

Control Logic The control logic is a circuit via which a processor receives the commands from the software program to control the operation of datapath components. The control logic can be understood as a combination of finite-state machine circuits with high complexity. The main components in control logic consists of decoder, branch predictor (BP), out-of-order execution (OoOE), interrupt controller (INTC), and power management unit (PMU) (see Fig. 40.3). The decoder is a control unit responsible for instruction decoding in a processor. All the information required for the current instruction operations can be obtained

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through decoding, including the instruction operation type, the source operand address, the target operand address, the immediate value, and the like. The branch predictor or branch prediction (BP) unit is a control unit that accelerates the processing of branch instructions in a processor. Whether the conditional branch instruction will jump is unknown until the execution phase, which substantially affects the effective prefetching of the instruction. In terms of implementation, the low-end processor performs static branch prediction, and the mid-to-high end processor performs dynamic branch prediction. Compared to static branch prediction, dynamic branch prediction is more accurate, while hardware costs and complexity are also greater. The out-of-order execution (OoOE) technology refers to a mechanism which allows instructions in high-end processors not to be executed in strict accordance with the order in a program. In a high-end processor, instructions in can execute ahead of the previous instructions and then generate computing result. The out-oforder execution is a complex control process under which the execution breaks the order of instruction programming. The processor hardware filters and executes the instructions that satisfy the execution conditions, avoiding blocking execution of subsequent instructions due to a particular instruction, and improving the operation load and performance of the processor. The interrupt controller (INTC) is a control circuit in a processor responsible for peripheral interrupt requests and used to interrupt the execution of the current program of the processor, and allow the processor to process the specified interruption handler. Generally, modern processors implement precision interrupt techniques, that is, to respond to interrupt requests after an instruction has been completed. The power management unit (PMU) is a module in a processor responsible for the operating states of each module, such as power supply, standby, and full-speed operation. The instructions of the processor are designed to implement power management instructions so as to allow the software to program the processor into different low-power consumption states. The processor is also designed to achieve different levels of low-power consumption states, allowing the processor and chip to enter different power consumption states. Advanced control methods can effectively speed up the processor’s processing capability, but the design complexity is also greatly increased. An important indicator to measure the complexity of control logic is the number of pipeline stages. In the early days when IC technology could not keep up with the development of computer architecture, the designers increased the throughput of the processor by deepening the pipeline; however, the irregular jumps of deep pipeline structure during program execution resulted in the reduced processing efficiency of pipeline and the sharp rising of design complexity. As the feature size of IC technology shrinks, overemphasis on main frequency will lead to a sharp rising in switching power consumption. The dominant design focus is to improve the processor’s performance and energy efficiency by simplifying the pipeline structure using reasonable main frequency.

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Coprocessor The coprocessor, as an extension unit of a processor, is usually an acceleration circuit which is specially designed for the tasks that the processor cannot perform directly or efficiently. Generally, the coprocessor and the processor are relatively independent of each other and are connected and communicated via a common bus. In a narrow sense, the coprocessors are some acceleration components inside the processor. In a broad sense, the coprocessors are acceleration components that are loosely coupled outside the processor. The narrowly defined coprocessor is basically driven by the processor which executes certain instructions; the broadly defined coprocessor is located around the processor, closer to the ASIC, and is driven by the processor which is configured with a coprocessor. The most common coprocessor is floating-point coprocessor. Most processors have extended the floating-point operations via a coprocessor, as shown in Fig. 40.4. The ARM processor implements the vector floating-point (VFP) unit via a coprocessor and supports vector floating-point operations. The Phi coprocessor developed by Intel supports multicore floating-point parallel operations via a chip. The main processor and the Phi coprocessor are interconnected and communicated via PCI-E protocol. In recent years, FPGA-based coprocessor architectures have gradually been recognized. Many chip designers have adopted the architecture of hard core or soft core CPU+FPGA coprocessor. In 2010, Xilinx pioneered the provision of the ARM Cortex A9 processor and FPGA scalable processing platform, and later introduced the Zynq-7000 series of programmable processors. In 2015, Intel acquired the FPGA giant, Altera Corporation, at a price of US$16.7 Billion to develop an architecture that integrates CPU and FPGA. In 2016, Intel introduced the architecture of x86 processor +FPGA, which can boost performance by up to 20 times. Accelerating a small number of hotspot programs through FPGAs and constant reliance of most serial programs on x86 architecture processors help to enhance the overall competitiveness of Intel processors. The coprocessor is a technical approach to targeted extension of a processor for the application domain. The general idea of the evolution of coprocessor technology is to design a dedicated coprocessor for a particular domain. In recent years, the deep integration of processors and FPGAs has become an important idea of coprocessor Fig. 40.4 An extended architecture of a typical floating-point coprocessor

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evolution. The architecture of CPU+FPGA has been actively developed for applications in information security, artificial intelligence, deep learning, etc.

Data Processing Pipeline The data processing pipeline is a design technique that boosts the processor’s computational throughput. The working principle of pipeline technique is to divide the execution process of instructions into multiple stages such as instruction fetch, decoding, execution, data access, and write back. At the same time, multiple instructions are executed in parallel in a processor, and the execution results of each stage are temporarily saved in the pipeline registers, as shown in Fig. 40.5. The total performance of a processor is calculated as follows: total performance of a processor ¼ IPC  frequency, where, the instruction-per-cycle (IPC) means the number of instructions that can be executed during each cycle and the frequency means the number of cycles operated per second. Given that the pipeline technique has greatly increased the frequency of the processor, it is very effective in boosting the processor performance (throughput). Regardless of effectively increased processor frequency, the pipeline technique brings about a stream of hardware hazards that affect the processor’s IPC optimization. The following three types of hazards are mainly taken into account in designing the pipeline. 1. Structure hazards: A structure hazard is caused by multiple requests accessing the same physical component. Given that a physical component can only be accessible by one request at a given point in time, other requests will be quiescent at that point in time. A typical example is that the cache will be accessible for the fetch stage and the data access stage at the same time, causing a structure hazard to the cache. The most typical way to resolve structure hazards is to reproduce multiple pieces of hardware resources.

Fig. 40.5 The task of executing instructions is divided into multiple stages for parallel execution via pipeline technique

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2. Control hazards: A control hazard is caused by a branch instruction which changes the program’s sequential execution. When the conditional branch is in the fetch stage, the jump instructions and the target address of such jump are not clarified. At this time, the pipeline will stop prefetching instruction until the branch instruction is properly executed and the branch jump direction and target address are obtained. Branch prediction is the main method to resolve control hazards in the pipeline, which predicts the jump direction of the branch and initiates instruction prefetching in advance. 3. Data hazards: A data hazard occurs when there is a subsequent instruction between the instructions that require the operand or result of the previous instructions that have not been completed, which is also called true correlation. The true correlation of data means that the previous instructions have not yet written the result back to the register file when a subsequent instruction enters the execution phase. The basic method for resolving data hazards is the data forward technique, which forwards the computing results directly from the execution unit. The pipeline technique is an important method for the processors to exploit instruction-level parallelism. Deep pipeline helps to increase the processor’s main frequency, but at the expense of increased cost, power consumption, and design complexity. At present, the pipeline depth of high-performance processors is no longer deepened, and the development focus is directed at improving the IPC. To conduct a larger scale of out-of-order (OoO) execution and exploit the parallelism of more instructions, the development of high-performance pipelines is directed. In terms of low-power-consumption processors, the pipeline is designed to be as short as possible for reducing power consumption and circuit cost.

Multiple Instruction Issue Multiple instruction issue refers to the mechanism by which multiple instructions are issued for execution in a pipeline during a single clock cycle. Traditionally, the issue and execution of a single instruction in a single clock cycle is called a scalar architecture. A multiple instruction issue architecture is a processor architecture whereby hardware supports the issue and execution of multiple instructions in parallel. Compared to single-issue processors, multiple-issue architectures can better exploit instruction-level parallelism of the processors and are therefore widely used in designing modern high-performance processors. Common multiple-issue processor architectures include such two major categories as superscalar architecture and the very long instruction word (VLIW) architecture, as shown in Fig. 40.6. The superscalar architecture has a high fetching bandwidth, and the fetching unit supports prefetching of multiple instructions during a particular cycle, thereby ensuring that sufficient instructions are available for the subsequent execution units. The superscalar architecture also has a wide data processing path, and can execute multiple instructions in parallel during one cycle, which means that multiple

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Fig. 40.6 Difference between the superscalar architecture (a) and the very long instruction word (VLIW) architecture (b)

copies of the hardware are required for the instruction decoding unit, the read port of the register file, the instruction issue unit, etc., and the hardware cost is high. Given the data dependency of the program, etc., the execution bandwidth of the superscalar processor is not as wide as possible, but an optimal solution of performance and cost is available, which generally provides an issue width of 2–4. The very long instruction word (VLIW) architecture is a technology whereby a class of processor hardware implements multiple issues in cooperation with a compiler. The VLIW technique executes instructions in the form of instruction packets. An instruction packet contains multiple instructions. The processor hardware acquires and executes an instruction packet during each clock cycle. The main features of the VLIW technique are stated as follows: Certain requirements are imposed on the format of the instruction packet, that is, the instruction packet must be encapsulated according to a certain format; the compiler solves, completely or partially, the pipeline hazards, and solves various correlation hazards by scheduling or inserting a no-operation instruction. Due to the support of the compiler, the hardware is designed in a relatively simple fashion. However, this technique requires the cooperation of software and hardware, so the parallelism and flexibility of software programming are not friendly enough. In the actual design, the general-purpose processor is more inclined to adopt super-scalar technique, because the backward compatibility of the software should be considered, and each new generation of processors must enable the “old” application software accumulated in the ecosystem to function well on new architecture processors, i.e., software corresponding to the hardware should be transparent; the VLIW technique is more used by digital signal processors, because digital signal processing usually have better data parallelism and lower requirements on compatibility are imposed for segmentation fields.

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Single Instruction Multiple Data (SIMD) The single instruction multiple data (SIMD) is a computer structure that processes multiple data in a single instruction under the Flynn’s classification. The hardware structure of single instruction multiple data (SIMD) is shown in Fig. 40.7. SIMD technology is mainly used in the applications of data processing with uniform data processing algorithm and good data parallelism. A typical computing scenario is an image algorithm that processes each pixel or block as per the same algorithm, and via which many pixels and blocks are processed in parallel. Given that matrix-like operations are widely used in such fields as audio/video, image, and signal processing, under which the processed object programs are the same, and the only difference is the processing of parallel data, SIMD technology is generally adopted in designing acceleration instructions for these applications. Key issues involved in SIMD include data operation width, element width, and operation type. (1) The data operation width means the maximum data width that the instruction can operate, which directly determines the throughput of the SIMD operation; (2) the element width means the width of the element operation in the SIMD, which is basically depending on the application and the data width to be processed; (3) operation type means that the operation should support the SIMD operation, and different requirements on the width should be imposed on different precisions. Taking the Intel processor as an example, Intel implemented the SSE instruction set for video and audio acceleration. These instructions are designed according to the SIMD method, and each instruction can operate 128-bit wide data. In terms of element width, considering that the basic element width in the video and image fields is byte, and the basic element width in the audio field is half-word, and the basic element width in both the high-precision signal processing field and the floating-point field is words, the element width of SSE can support byte/half-word/ word operation. An SSE instruction can operate up to 16 bytes in parallel in conjunction with data operation width and element width. In terms of operation type, the SSE instruction implements typical data operations such as multiplication,

Fig. 40.7 Hardware structure of single instruction multiple data

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multiplication and accumulation, shifting, and logic operations. ARM’s Neon technology also implements the SIMD architecture, whose data operation width is also 128 bit, with the specific operation type similar to that of Intel. The evolution of SIMD technology is directed at the acceleration of applicationspecific algorithmic capabilities. Applications with uniform algorithm structure and good data parallelism tend to be implemented in SIMD processors or coprocessors.

Multithreading Thread is the smallest program fragment in the program execution stream and the smallest unit that the operating system can schedule. Threads are included in the process and are the actual units of operation of the process, so threads can be regarded as sequential control flow with certain functions running on the processor. The difference between a thread and a process lies in the followings: separate memory spaces are available between two processes, while the threads of the same process run in a shared memory space, each of which has its own separate execution stack and program counters to execute the context. A hardware-backed multithreaded processor refers to a processor that can run multiple threads in parallel simultaneously. A processor that adopts hardware multithreading technology allows the hardware to directly schedule other thread instructions that are already ready to enter the execution unit to perform operations in the event of a blocked thread, thereby improving the utilization of the datapath, and improving the overall throughput of multiple threads running. The simultaneous multithreading (SMT) provides a technique to run multiple instructions from different threads in a particular clock cycle. Based on a superscalar processor, SMT is a product generated by extending the ability of the superscalar processor to execute multiple instructions simultaneously into a multithreaded scenario. SMT further enhances the limited instruction parallelism of a single thread on the premise of spanning multiple threads, making full use of superscalar pipeline hardware resources. SMT needs to increase the hardware resources for recording the thread numbers of different running instructions in all stages of the pipeline and related control logic, and also needs to expand the resources shared by the threads such as on-chip cache and translation look-side buffer (TLB), and alleviate the hazards between the threads. Typical processors that have adopted SMT include Sun’s UltraSPARC T2, Intel’s Pentium 4 Xeon, and Core i7. A schematic diagram of multiple threads running on different logical cores is shown in Fig. 40.8. The merit of single-core multithreading technology is that multiple independent threads can share the storage and execution units of the processor, which costs less than multicore hardware. The drawback of single-core multithreading technology is that the multithreaded control logic is designed in a complex manner and has poor

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Fig. 40.8 Schematic diagram of multiple threads running on different logical cores

scalability, e.g., the cores of a processor should be redesigned so as to scale from thread 2 to thread 4. In recent years, with the continuous advancement of technology, hardware cost is no longer a major contradiction, and the low-cost value of multithreading technology is gradually decreasing. Multicore is widely used by virtue of its good scalability and lower difficulty. It has become a trend that multithreading are replaced by multicore.

Multicore The multicore processor is an arithmetic component consisting of two or more (generally no more than 32) independent processor units (also called “cores”), each of which may work independently in the same manner as a traditional singlecore processor does. The fact that multiple processors read and execute instructions of multiple programs in parallel can speed up the parallel computation of multiple independent programs. The multicore processor is a kind of task-level parallel processing technology that emerged due to the bottlenecks of improving the instruction-level parallelism of single-core processors. The multicore processor has separate cache units (L1 cache) and an external storage unit (L2 cache and internal memory) shared by the processors via a bus. The main problem faced by multicore processors based on shared storage architecture (see Fig. 40.9) is the maintenance of data consistency, that is, when a local cache of a processor is modified during operation, the same address segment data in the local cache of other processors are not modified, resulting in data inconsistencies among the processors.

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Fig. 40.9 Schematic diagram of a multicore processor based on shared storage architecture

Such data consistency issue is addressed by a dedicated cache coherency protocol designed for multicore processors. Most multicore processor systems currently adopt a “snooping” based coherency protocol, whose main principle is that all local caches would observe the data updates occurring on the bus through the internal bus in real time, and check and update the local cache on the corresponding address once an update to shared storage is detected. A common snooping protocol is the MESI (modified, exclusive, shared, and invalid) protocol, which designs four states for multiple cache units. When a cache update occurs, the state change of the cache segment will be broadcast to other processors. If the computing cores inside a multicore processor are identical and completely equal, such processor is called homogeneous multicore processor. In terms of a homogeneous multicore architecture, its system is completed by repeatedly implementing a basic computing unit, and designing a unified management communication interface, shared storage, etc. If the computing cores inside a multicore processor are not identical, such processor is called heterogeneous multicore processor. Common computing core categories include CPU, GPU, DSP, ASIC, FPGA, and so on. Heterogeneous multicore processor can be expressed as “CPU+other processors.” Currently, the common heterogeneous multicore processors appear in embedded multicore processors, such as CPU+GPU of AMD, Apple, Qualcomm, Samsung, Huawei, and other companies. With the explosive growth of high-performance parallel computing demands in such fields as cloud computing, computer vision, machine learning, and VR/AR, the energy efficiency of heterogeneous multicore processors is higher than that of homogeneous multicore processors thanks to its introduction of other energyefficient computing units such as GPUs, DSPs, and hardware accelerators, which directs the development of high-performance computing. CPU+FPGA developed by Intel through acquisition of Altera Corporation and AMD’s new architecture APU that incorporates CPU+GPU fall to the categories of heterogeneous computing.

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Manycore Processors The manycore processor is a kind of multicore processor designed to meet the needs of large-scale parallel computing, whose internal core number usually ranges from tens to thousands or more, as shown in Fig. 40.10. Compared with multicore processors, manycore processors seek for higher explicit parallelism and energyefficiency ratios, and tend to adopt a simpler processor core and increase the routing nodes used for communication of each processor node, so as to realize good scalability. Although the single-core performance is not so high, the parallelism of program tasks is greatly increased because of extra processor cores, which enables the manycore processors to achieve better overall system performance. Manycore processors are generally built on a network-on-chip (NoC) to enable direct point-to-point inter-core communication. The network-on-chip can optimize the partitioning and sharing mechanism of the global interconnection for which communication costs can be greatly reduced and communication efficiency improved compared with those of the multicore architecture based on global bus synchronization and shared memory communication. The hardware performance of manycore processors can reach the Tera-FLOPS (floating-point operations per second, TFLOPS) level, but in practical use it is a huge challenge to software programming to determine how to achieve the task partitioning of the target software and map the divided subtasks to the corresponding processor nodes to fully exploit the potential of each processor. The results of the 16-core and 24-core manycore processors researched and developed by a team from Fudan University in China have been published at the International Solid-State Circuits Conference (ISSCC). At present, the programing models applicable to manycore processors mainly include message passing interface (MPI), open computing language (OpenCL), partitioned global address space (PGAS), actor model, open multiprocessing (OpenMP), etc. In 2017, the world’s fastest “Sunway TaihuLight” supercomputer adopts a total of 40,906 SW26010 processors, with a total of processor cores of 10,649,600. Future trends of manycore processors include automated parallel compilation techniques,

Fig. 40.10 Schematic diagram of a manycore processor

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operating system research, high reliability, testability, on-chip synchronization mechanisms, data sharing and allocation strategies, configurable attributes, and massive thread management, and application fields of manycore processors include biocomputing, network security, signal processing, network packet processing, graphics processing, machine learning, etc.

Memory Hierarchy Memory is a hardware that holds the data and is a basic component of the Von Neumann architecture-based computer that is tightly coupled to the processor. Highcapacity high-speed memory provides the basis for processor performance. However, during the development of modern ICs, the development of memory has lagged behind the development of processors for a long time. Depending on the trade-offs among speed, capacity, and price, multihierarchy storage architectures are often employed in modern computers. In light of the storage access latency, the multihierarchy storage architecture is divided into different levels of memory hierarchy, as shown in Fig. 40.11. The lower the level of memory hierarchy (logically closer to the processor) is, the smaller the access latency and the higher the unit cost; therefore, the designed memory capacity is relatively small. The higher the level of memory hierarchy (logically farther from the processor) is, the larger the access latency and the lower the unit cost; thus, it is proper to store large-capacity data not frequently used into higher levels of memory hierarchy. The registers are located inside the processor and typically each register holds one or two words (generally, 32 bits or 64 bits). The caches are also located inside the processor and are set to reduce the cost of access to main memory (access time and power consumption), and to store frequently accessed instructions or data. The caches can be divided into instruction cache and data cache, and can be further

Fig. 40.11 Memory hierarchy

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divided into more hierarchies according to the architecture needs, such as the first level cache (L1) and the second level cache (L2). The main memory is referred to as MM, and is a memory that the CPU can directly access, that is, the CPU can directly read the corresponding instructions and data in the MM for computing. The MM is usually composed of random access memory (RAM). Given the volatility of some particular types of RAM, all data of main memory will be lost in the event of any power outage. The access time of the MM is usually a few nanoseconds or tens of nanoseconds, which needs to be directly or indirectly connected to the CPU through a memory bus, including an address bus and a data bus. The local secondary memory, also known as external memory, is a kind of auxiliary memory, which the CPU cannot directly access. Given that such memory is usually nonvolatile, its data will not be lost after power failure. The auxiliary memory can meet the cost-effective large-capacity storage requirements because its unit price is cheaper than that of main memory by more than two orders of magnitude. Generally, disks are used as the auxiliary memory, whose access latency is in the millisecond range. In the future, the performance of each storage subsystem will continue to be optimized, e.g., the solid-state drives (SSDs), eliminating the seek operation of mechanical hard disk drives of common auxiliary memories, and contributing to extremely low random read latency. In the meanwhile, new types of memories such as phase change memory (PCRAM, PCM, and PRAM), resistive memory (ReRAM or RRAM), and magnetic memory (MRAM) are also emerging. These new memories are expected to be used in the embedded fields, and will change the architecture of embedded system because they are nonvolatile and executable. Currently, these technologies have not fundamentally solved the problems of read/write speed and cost. Therefore, multimedia hybrid storage systems and integrated management are expected to become a major development direction in terms of data storage system.

Digital Signal Processor (DSP) The digital signal processor (DSP) is a dedicated processor designed to optimize digital signal processing (DSP) algorithms, and is commonly used to measure, filter, compress, or otherwise dispose of real-time continuous analog signals. A typical DSP architecture diagram is shown in Fig. 40.12. DSP algorithms require a large number of repeated arithmetic operations on the data over a short period of time. For example, the continuous time domain signals of the audio and video sensors are continuously converted into frequency domain digital signals, which, after quantization and other processing, are transmitted, and finally inversely transformed back into the time domain signals. Usually, stringent requirements on latency are imposed on the DSP application, which means that the processor must complete the signal processing task within a fixed time limit. The DSP architecture is specifically designed for DSP optimization to contrapuntally provide low-cost, high-performance, and low-latency computing

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Fig. 40.12 Typical DSP architecture diagram

capability. DSPs usually have application-oriented features, so it is difficult to get support from general-purpose compilation tools. The programs of DSPs often exist in library files in the form of assembly. DSP needs to process a large amount of data streams, so its storage architecture must be designed to acquire multiple instructions or data at the same time. DSPs often store the data and instructions in parallel, with multiple data buses. In addition, it is more dependent on the use of DMA because the DSP program needs to be specially optimized for the cache so as to further reduce the latency. Given that a large latency occurs to operating systems mapped with virtual memory during process switching, DSPs usually do not support virtual memory or virtual memory protection. The technical development trend of DSPs includes: (1) core instruction parallel capability will be further enhanced, and the single instruction multiple data (SIMD) and the very long instruction word (VLIW) will dominate in the next generation of high-performance DSP; (2) multicore DSP solutions are becoming more common in some high-performance applications; (3) both fixed-point and floating-point computations are supported; (4) digital signal controllers (DSCs), also known as singlechip DSPs, can be integrated with more functions and interfaces through advanced technologies to reduce overall board cost and power consumption and reduce the size; and (5) the convergence of DSP and MCU becomes a trend, the microcontrollers are versatile with low cost but weak digital signal processing capability, incorporating DSP expansion helps simplify design and reduce cost and power consumption.

Graphics Processing Unit (GPU) The graphics processing unit (GPU), also known as the vision processor or display chip in the past, is a microprocessor intended to process graphics and image on personal computers, workstations, game consoles, and mobile devices. The graphics processor converts the display information required by the computer system and ultimately transmits the same to the display. Therefore, the graphics processor is one of the important devices for “human-computer interaction.”

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What makes a difference in designing the graphics processor is data parallelism, for which such technologies as single instruction multiple data (SIMD) or single instruction multiple thread (SIMT) at the instruction level and multicore at the architecture level are often adopted. SIMD packs multiple data elements to process a single instruction, which accelerates the processing of vector data, but fails to handle branches efficiently. SIMT is an improvement of SIMD technology that allows a set of independent threads running simultaneously to share instructions and allows each thread to have a different branch. Graphics processors often contain dozens or even hundreds of stream multiprocessors (SMs), each of which contains dozens of thread processors (TPs). NVIDIA’s TITAN X GPU in 2015 has 3584 processing cores. Graphics processors need to be designed with high-bandwidth on-chip memory devices so as to take full advantage of the computing capabilities of these processors. As big data, cloud computing, and machine learning spring up, the scale of data processing is becoming larger and larger. A widespread attention has been drawn to the application of GPUs to the development of general-purpose GPU (GPGPU) computation. The widely used GPGPU platforms cover OpenCL, OpenGL, CUDA, etc. The open computing language (OpenCL) is an open and free standard for parallel programing of general-purpose computing in heterogeneous systems. The open graphics library (OpenGL) defines a cross-platform and cross-language highperformance graphical program interface. The compute unified device architecture (CUDA) defines a general-purpose parallel computing architecture. CUDA implements parallel programming by dividing the tasks that require a lot of computation into multiple levels. Firstly, CUDA divides the tasks into task blocks, and then divides the task blocks into finer-grained CUDA threads, and finally assigns these threads to the processing cores in the GPU for execution. GPUs not only play an important role in the traditional image processing field, but also drive the development of high-performance computing and artificial intelligence (AI) by virtue of its extremely high data throughput. Such companies as Google, Baidu, and Facebook have successfully built AI (with deep learning) platforms by using GPU clusters as the infrastructure. Google’s AlphaGo artificial intelligence platform successfully defeated the world champion Lee Sedol in March 2016, and AlphaGo’s upgrade Master achieved a 60:0 victory in a game against human in early 2017. With the deepening of research, GPUs will play a more important role in such applications as scientific computing, artificial intelligence, and autonomous driving.

Further Reading 1. J.G. Xu, Wang W.W.: System Architecture of Microprocessor (Science Press, Beijing, 2008) (Chinese book series 5 of 5, ISBN 978-7-03-022807-9) 2. D.A. Patterson, A. Waterman, The RISC-V Reader: An Open Architecture Atlas (Strawberry Canyon, Berkeley, CA, USA, 2017) 3. D.A. Patterson, J.L. Hennessy, Computer Organization and Design RISC-V Edition: The Hardware Software Interface, The Morgan Kaufmann Series in Computer Architecture and Design, 2nd edn. (Morgan Kaufmann, Cambridge, MA, USA, 2020)

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Contents Memory Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cell and Periphery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3D NAND Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FeRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STT-MRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ReRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Semiconductor memories are digital electronic semiconductor devices used for the digital information storage of program code and data. As the demand keeps growing, new memory technologies are continuously introduced and the existing technologies are further developed. A variety of semiconductor memories are in development with different concepts of memory cells for various applications. There are two main categories of memories, i.e., volatile memory (VM) and nonvolatile memory (NVM). VM needs to be provided power constantly to retain data, such as static random access memory (SRAM), which uses several transistors per memory cell, and dynamic random access memory (DRAM), which uses a single transistor and a capacitor per cell. In contrast, NVM retrieves stored F. Bai · X. Han (*) Xi’an UniIC Semiconductors Co., Ltd, Xi’an, Shaanxi, China e-mail: [email protected] L. Pan Institute of Microelectronics, Tsinghua University, Beijing, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_41

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information even after the power goes down. Examples of NVM include readonly memory (ROM), flash memory with floating gate MOS transistor per cell, and several emerging memories, such as ferroelectric RAM (FeRAM), spin transfer torque magnetoresistive RAM (STT-MRAM), resistive RAM (RRAM), and phase change RAM (PCM). Semiconductor memories are available in various forms: IP for system-onchip, discrete components for assembly, memory cards, and solid-state hard drives. Usually a semiconductor memory works with memory controller, which bridges memories and corresponding host computers, and also manages the operation of memories accordingly. Keywords

Semiconductor memory · Memory controller · SRAM, DRAM · Flash · 3D NAND · FeRAM · MRAM · RRAM · PCM

Memory Categories Semiconductor memory devices are widely used in electronic systems such as computers to store program code and data in information technology. They store and retrieve data according to the address specified. Compared with traditional magnetic memory, semiconductor memory devices (briefly as Memory) have the advantages of small size, good performance, and low power consumption. Memory types are as shown in Fig. 41.1. According to the status of data maintenance after power supply termination, we can divide the memory into two categories: volatile memory and nonvolatile memory. Volatile memory includes static random access memory (SRAM) and dynamic

Fig. 41.1 Memory categories

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Table 41.1 Comparison of mainstream memories Types SRAM DRAM

Capacity Low High

NOR flash

Low

NAND flash

High

Speed High Read: Medium Write: Medium Read: Medium Write: Low Low

Power consumption High Medium

Cost High Low

Volatile Volatile Volatile

Medium

Medium

Nonvolatile

Medium

Low

Nonvolatile

random access memory (DRAM). Nonvolatile memory includes not only read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), and flash, but also some emerging memories, such as ferroelectric RAM (FeRAM or FRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM or RRAM), and phase change RAM (PCRAM or PCM). Memories are divided into read only memory (ROM) and read/write memory (RWM) according to their functions. ROM permanently holds its content, which can only be read and cannot be altered. RWM, which provides both read and write functions, can be divided into random access memory (RAM), sequential access memory (SAM), and content-addressable memory (CAM) according to different access modes. RAM supports random order access, while SAM accesses data sequentially, such as FIFO (first-in first-out), LIFO (last-in first-out, used as stacks), and shift registers. Instead of looking for data by address, CAM returns address where data matches the given keyword. There are many kinds of memories with various capacity, speed, power consumption, cost, and volatility, as shown in Table 41.1. SRAM, which has fast access speed and small storage capacity, usually is used as processors’ cache for instructions and data. DRAM has lower access speed but higher density, so that it is often used as main memory. Flash, which is nonvolatile and of the largest storage capacity, is often used to store system programs and files. NOR flash is superior to NAND flash in read/write speed, hence is mainly used for program storage. While NAND flash is used for data storage, because of the extremely low cost per storage unit.

Memory Cell and Periphery Circuit A memory chip consists of memory cell array, row decoder, column decoder, and sense amplifier, as shown in Fig. 41.2. Memory cell, which stores one or more bits of binary code “0” or “1,” is the basic storage unit and can be accessed with the assistant of periphery circuits. For example, the classical 6 T SRAM memory cell consists of six transistors, which forms two invertors with input to output connected to each other to latch data. DRAM memory cell is a 1T1C (one-transistor and one-capacitor) structure, of which the amount of charge in capacitor represents the states of “0” and “1” if with or without charge. Flash memory cell uses different cell transistor’s threshold

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Fig. 41.2 Memory structure

Fig. 41.3 Repair scheme in memory

voltage to represent different states. Floating gate transistor is commonly used as flash memory cell. Memory cells can be organized to form a cell array. For example, a cell array consists of 2p memory blocks (p is the width of block addresses), each of which contains 2n words (n represents the width of word addresses in each storage block). Each word is a group of data written to or read from the cell array at the same time with m bit word width. The memory capacity is 2p+n+m bits in total. Memory can achieve large capacity by using longer word lines and bit lines, but parasitic capacitance and resistance of long word lines and bit lines will slow down memory access speed. Therefore, cell array designers need to make a trade-off between capacity and performance. Optimizing array organization and partition, the word lines and bit lines in a memory block can balance both speed and capacity. Redundant array is added to the normal array to improve yield. When the normal array fails, the redundant rows, columns, or words in the redundant array can be used to replace the faulty ones in normal array. For example, as shown in Fig. 41.3, a redundant array contains two redundant rows (SR0 and SR1), two redundant

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columns (SC0 and SC1), and two redundant words (SB0 and SB1). When the word E in column C3 and row R2 of normal array is wrong, the redundant row SR0 can be used to replace the row R2 directly, or the redundant column SC0 can be used to replace the column C3, or the redundant word SB1 can be used to replace the word E directly. Generally, redundant rows and columns are used to repair row and column defects, and redundant words are used to repair single-bit error. The size of redundant array increases together with normal array. During memory design, it is mandatory to analyze the size of the redundant array needed according to the type and probability of memory array fault, so as to achieve the goal of using the least redundant units to greatly improve product yield. Row decoder controls word line (WL) activation according to input row address. Each active WL selects a row of memory cell. Perpendicular to WL, cells located in the same column but in different rows are connected to the input/output circuit via bit line (BL). Row addresses Ak to An-1 can control 2n-k WLs through row decoder. A0 to Ak-1 is column address, which is input to column decoder, meaning that there are 2k words per WL. Column decoder selects one word out of the total 2k words for operation. Row decoder and column decoder have an important impact on the speed and power consumption of memory. Generally, they are closely placed to the memory array, and fit to the pitch of one or more cells. Sense amplifier (SA) is the core part of memory readout circuit. SA, which is essentially an analog circuit, detects the weak signals on BL and amplifies into a signal with larger output swing. SA can not only compensate for the limited output drive ability of memory cell and speed up read operations, but also reduce the signal swing on BL so that the power consumption due to BL charge and discharge is greatly saved. According to the intrinsic characteristics of memory cell and the architecture of the memory array, different types of SAs are implemented. Differential voltage amplifier is the most common SA in memory. Error correction coding (ECC) is widely used in memories and controllers, see Fig. 41.4. It detects and corrects data errors to improve memory reliability. In order

Fig. 41.4 Memory with embedded ECC

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to support ECC, an additional memory array is added to store parity bits. ECC circuit can be embedded into either controller or memory. Once embedded into memory, ECC makes the memory to be able to self-repair. DRAM with embedded ECC is not only compatible with standard DRAM interface, but also has high reliability and yield. On the contrary, some memories only provide additional parity bits, and ECC algorithm is processed by controller. For example, NAND flash reserves storage space for ECC parity bits which are used in conjunction with ECC circuits in flash controller to enhance endurance of NAND flash significantly.

Memory Controller Memory controller serves as a bridge between memory and CPU. Memory controllers derive from different memory specifications, such as controllers especially for DRAM and controllers for flash. In computer system, memory controllers are needed to exchange data between CPU and memory. It determines the maximum memory capacity, the number of memory block (bank), the type and speed of memory, the data depth and width, and other important parameters. The overall performance of computer systems is highly dependent on controller’s performance. At present, memory controllers are generally integrated in CPU. The disadvantage is that the adaptability is poor, but the advantage is that the data latency is squeezed to achieve higher system performance. Fully buffered DIMM (FB-DIMM) is developed to further release the constraints of memory performance on the overall system performance, through adding an advanced memory buffer (AMB), the communications between controller and memories are high-speed, multichannel, serial, and point to point. Unlike DRAM controllers, flash controllers are not only responsible for the communication between CPU and flash, but also for the management of flash, including bad block management, wear leveling, and so on. The endurance of flash is limited. Through wear leveling technique, flash controller records the usage of whole flash memory space, so that the rewrite data can be written to different address in the flash memory each time, rather than to the same address all the time. Ideally, wear leveling technique ensures that all physical addresses of flash have been used evenly before reusing. By making maximum use of all flash cells, the entire life of the whole flash memory is extended. However, the flash memory will wear out as the number of cycling increases. The bad blocks in flash memory gradually increase due to the fact that failed cells become more and more. Bad block management is introduced and marks the spotted bad blocks. Flash controller builds a bad block table by reading bad block marks. The blocks listed in the bad block table will not be accessed and replaced by a good block by address remapping. From the users’ point of view, although the capacity of flash memory reduced a little, the memory can still work before the number of bad block reaches the preset limitation. Aside from stand-alone controller, eMMC (embedded multimedia card), which packages the flash controller and flash memory together, is widely used, especially in

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Fig. 41.5 ECC principles in memory controller

mobile phones and tablets at present. It provides a standard interface and manages flash memory as well, so that users can focus only on their own product development and do not need to deal with flash compatibility and management issues to shorten the time to market and reduce cost. Many memory controller supports error correction code (ECC) technology, which can detect and correct data errors to improve reliability. Memory only needs to provide additional parity bit storage capacity. The advantage of integrating ECC function to controller is that the algorithm is not hardened in the memory and therefore more flexible for controller designers, while the disadvantage is that it is hard to exploit the best memory performance. As shown in Fig. 41.5, D (k) is the original k bit data, data C (n, k), which is n bits, is generated by ECC encoding with parity bits appended. And then controller writes the memory with C (n, k), which may be read out as C0 (n, k). If the number of erroneous bits in C0 does not exceed the error correction ability of controller ECC algorithm, the corrected data Q(k) ¼ D(k) is obtained by ECC decoding. Otherwise, it may not be corrected or even detected. Since the Hamming code can only correct one-bit error, ECC codes which can correct two- or more-bit errors are gradually adopted with the increase of memory error rate. At present, BCH codes, RS codes, LDPC codes are the mainstream algorithm in use.

SRAM SRAM (static random access memory) has become an indispensable member of semiconductor memory family due to its low power consumption and high-speed performance. SRAM cell uses bistable latching circuitry to store each bit. Compared with DRAM, SRAM has fast access speed, and the data can be held permanently without refreshing as long as the power is constantly on. SRAM cell usually uses six transistors, thus it results in complex design and low density. SRAM can be divided into asynchronous SRAM and synchronous SRAM according to the interface. Asynchronous SRAM has no clock signal, and its access

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is triggered by the change of command signal or address signal such as chip selection, write enable, etc. All access to synchronous SRAM is initiated at the rising/falling edge of clock. Address, data input, and other control signals are all related to clock. SRAM has two different types of application: discrete component and embedded IP. As stand-alone component, discrete SRAM is mainly used in communication systems, high-speed networks, and so on. Embedded SRAM is used as cache, register heap, lookup table, etc. in SoC due to its compatibility with standard CMOS process. SRAM compilers are designed to generate SRAM instances automatically. SRAM compiler can generate files such as layout, netlist, and timing model, according to user-defined SRAM parameters. SRAM cell has different schematics, including 6 T and 8 T structures, as shown in Fig. 41.6. The most commonly used 6 T SRAM memory cell contains a pair of crosscoupled inverters to hold data and a pair of access transistors to read and write. When writing, WL is opened, and data is written to node Q through a pair of complementary bit lines BL and BL. When reading out, the BL and BL are pre-charged and then floated by the pre-charged control signal PREB. When WL is raised for read operation, sense amplifiers (SA) is opened to amplify the voltage difference between bit line BL and BL and then the data is sent to the output circuit. SRAM cell design is one of the most challenging works of SRAM design. While minimizing area occupation, SRAM designers should balance cell static noise margin, readability, and writeability at the same time. For example, the cross-coupled inverters should be strong to overcome read noise but weak to flip during write operation. Usually semiconductor manufactories provide SRAM cells, which are carefully tuned for specific processes. SRAM designers choose cells of area, speed, or power enhancement to meet their products’ specification (Fig. 41.7). Pseudo-SRAM (PSRAM), whose cell is 1T þ 1C as DRAM-like cell, works with a SRAM-like interface. The cell refresh is done internally by PSRAM itself, so it is not necessary to use complicated controller like DRAM. Meanwhile, PSRAM is of higher capacity than SRAM and is suitable for products with certain cache capacity requirements.

Fig. 41.6 SRAM cells with six transistors (6 T) and eight transistors (8 T)

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Fig. 41.7 SRAM read operation diagram

DRAM Dynamic random access memory (DRAM) uses 1T1C (i.e., one access transistor and one storage capacitor) to store a bit as a charge in the cell capacitor. This allows DRAM to reach very high density. But the disadvantage is that since it stores data as charge which leaks, therefore the charge needs to be read and rewritten again every few milliseconds (known as refresh). The DRAM cell is illustrated in Fig. 41.8. The storage capacitor is charged for “1” and discharged for “0.” During read operation, the bit line BL is pre-charged first, and then the word line WL is active. A charge share between BL parasitic capacitor CBL and the storage capacitor Ccell occurs and changes the voltage of pre-charged BL. If BL voltage increases after the charge share, the read-out data will be “1.” The read-out data will be “0” on the contrary. Since the storage capacitance is usually one to two orders of magnitude smaller than the parasitic capacitance of the bit line, the voltage variation due to charge share is as small as around 200 mV. It is necessary to increase the storage capacitance to enlarge the BL voltage variation and also the life time of storage content as charge. Although more capacitance can reduce DRAM soft errors, it comes at the expense of more area. In order to achieve higher DRAM memory cell density and lower cost per bit, the DRAM technology is constantly scaled down in size. DRAM requires special manufacturing process to maintain the performance of memory cells. Stacking capacitor technology, which indicates that

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Fig. 41.8 DRAM memory cell array

Fig. 41.9 DRAM process development trend chart

capacitors are stacked on top of access transistors, is widely used at present. The large storage capacitors are realized by stacking multilayer materials. In addition, trench capacitor technology etches deep holes in the substrate, using its side wall and Si substrate as the capacitor electrode. By extending DRAM cell into a threedimensional structure, the area of a single DRAM memory cell reaches 6F2 (where F is the process feature size) and beyond. The development trend of DRAM process is shown in Fig. 41.9. Generally, a DRAM core block consists of cell array, sense amplifier (SA), and word line driver. Its performance and area are fundamental for the whole DRAM chip. In the cell array, the cells in a row share the identical word line, and the cells in a column connect to the same bit line. The basic operation of DRAM storage array is shown in Fig. 41.10. Sense amplifier adopts differential voltage structure, connecting to a pair of complementary bit line (BL and BLB). SA is responsible for amplifying small voltage difference on bit line while reading data and rewriting cell when writing data. Word line driver controls the switch of word line. DRAM core block supports four basic operations: ACT, WR, RD, and PRE. All cells connected to the same word line (called a page) are activated at the same time in activation operation (ACT). When the word line is opened, the bit line voltage will

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Fig. 41.10 Basic operation of DRAM cell array

rise slightly if the selected cell stores “1,” and will decrease if the cell is “0.” Meanwhile, the charge in cell has been damaged due to charge sharing. After waiting for the voltage difference on the bit line to stabilize, the sense amplifier starts to amplify the BL voltage difference to the full swing and hold the data for further operations. Since the word line is still open, the sense amplifier will rewrite the cell and restores the original data (called refresh). After ACT operation, a page of data is loaded to SA and can perform read and write randomly. Write (WR) and read (RD) operation access SAs according to column address; RD operation reads out data from the corresponding column of the active page from SA, while WR operation writes data to SA by write driver and then to the cell by the SA. Pre-charge (PRE) operation closes the active page, including word line and SA, and pre-charge all bit lines for next ACT operation. DRAM designers need to optimize the circuit and layout design of this core area. It is important to study the DRAM core block by running simulation and reliability analysis to determine the physical width of word lines, bit lines, and data lines. Despite the continuous progress of technology, the access speed of DRAM core block has not been significantly improved from the beginning. DRAM interface can be doubled by data prefetching in core and high-speed data path and high-speed interface design. A series of DRAM products are derived: SDRAM (synchronous dynamic random access memory), DDR SDRAM (double data rate synchronous dynamic random access memory), or simply DDR. Later generations of DDR are DDR2, DDR3, DDR4, and the most advanced DDR5 planned in 2019.

Flash Memory Flash memory or flash is a kind of nonvolatile memory (NVM), in which the threshold voltage (UT) of memory cell represents the data in storage. Floating gate transistor is one of the main technologies used in flash cell, as shown in Fig. 41.11. The amount of charges stored on the floating gate determines the VT of cell. Program (PGM) operation injects electrons into the floating gate through quantum tunneling to increase the cell VT, representing the logic “0.” On the contrary, erase (ERS) operation removes the electrons out of the floating gate, so that the cell VT is reduced to represent logic “1.”

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Fig. 41.11 Flash cell structure

Fig. 41.12 Array structure of NOR and NAND flash memories

According to the differences of array structure, there are two types of flash: NOR flash and NAND flash, as illustrated in Fig. 41.12. NOR flash cells are connected in parallel in array, while NAND flash cells are connected in series. Due to the parallel connection, NOR can realize fast random read operation at the cost of larger array area than NAND flash, and it is mostly used for code storage. In NAND flash array, the contact between serial cells (called a string) can be removed so that the average area of a single cell is close to 4F2 (where F is the process feature size) and more compact than NOR flash. Many NAND flash strings constitute a cell block. The erase operation of NAND flash is performed by block, while read and program operations are performed by page. NAND flash is very suitable for big data storage, such as in smart phones, digital cameras, MP3, and other electronic products. Solidstate drive (SSD), which is a substitute for hard disk, use multiple NAND flash to

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Fig. 41.13 Threshold voltage UT distribution of SLC and MLC

build up a high-volume storage device with the advantages of shock resistance, fast speed, noise-free, and low-power consumption. According to the number of bits stored in a single cell, flash is divided into singlelevel cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and so on. The VT distribution of SLC and MLC are shown in Fig. 41.13. An SLC flash cell stores only one bit. In order to achieve higher storage density, the threshold voltage of flash cell is programmed into multiple levels to store more than one-bit data. At present, MLC (storing 2 bits per cell) and TLC (storing 3 bits per cell) can lower the cost per bit of flash further. It depends on the accuracy of the UT to be programmed and detected that how many bits a flash cell can store. The UT of flash cell can be identified by applying different voltages on corresponding word line. Therefore the bit line discharge current flowing through flash cell (ICELL) is different. The UT value can be judged by sensing the ICELL current value. A NAND flash cell current sensing circuit is demonstrated in Fig. 41.14. First, the node UOUT is pre-charged to UDD, and the bit line is charged through the transistor MN. Because the gate voltage of MN is U1, the bit line is charged to the voltage U1UTHN. Then MN closes and the node UOUT stops charging. When the string in cell array is opened, the bit line starts to discharge, and the gate voltage of the selected cell in string is UREAD. Finally, the MN gate voltage is U2. If UBL < U2UTHN, MN is turned on and UOUT is pulled to a low level, indicating the threshold voltage of cell UT < UREAD; otherwise, when MN is turned off, UOUT keeps a high level, indicating the UT > UREAD. The accuracy of U1, U2, and UREAD voltages directly determines the accuracy of cell threshold voltage detection. It is necessary to carefully design the voltage generation circuit. Retention time, which indicates how long flash cell can maintain the data, is one of the most important features about flash reliability. Actually, the charge on the floating gate will gradually leak out due to defects in the insulating layer around floating gate. Manufacturers usually guarantee a retention time of 10 years. Endurance is another important feature of flash. The cell program-erase cycle time is limited due to several reasons: First, the cell gate oxide will be gradually damaged after high-voltage operations. Second, the coupling interference between adjacent floating gates becomes more serious as the process feature size is shrinking. The

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Fig. 41.14 NAND flash cell current sensing circuit

typical value of SLC endurance is about 100,000 cycles, and that of MLC can be 10,000 cycles or even lower. Charge trap flash cells, which eliminate the coupling interference between neighbor cells, can improve the cell endurance by technology invention and make it possible to keep on shrinking flash process down to 1x nm. On the other hand, the flash chip design can also contribute to maximum the flash endurance by adjusting the voltage and time length of high-voltage operation, introducing verification and prohibition programming mechanism, etc.

3D NAND Flash Memory Compared with traditional flash memory of planar NAND (also known as 2D NAND), 3D NAND flash Memory, whose memory string is three dimensional, can greatly improve capacity and reduce cost. 2D NAND has encountered reliability and performance issues when process is scaled down to less than 1x nm, see Fig. 41.15. In contrast, 3D NAND uses new ideas to solve this problem. It stacks more layers on relatively old processes. This technology not only improves capacity but also ensures performance and reliability. Figure 41.16 is a schematic of a 3D NAND array circuit, which stacks the memory cells in the direction perpendicular to the silicon wafer, thus greatly increasing cell density on silicon wafer. SSL (string select line) determines the selection of one of the multiple cells connected to the same BL; CSL (common source line) is the common ground of the whole array cells, the

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Fig. 41.15 NAND flash process trend Fig. 41.16 3D NAND array

current flows from array cell via BL to CSL when in read operation; while GSL (ground select line) decides if the memory array series is conducting to ground. 3D NAND stacking can be divided into three types: simple stack, vertical channel, and vertical gate. The memory cells use floating gate (FG) or charge trap flash (CTF) technique. Compared with FG, CTF is more reliable, smaller, and more

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Fig. 41.17 3D NAND cross-section

suitable for 3D NAND. A 3D NAND using vertical channel structure based on CTF is shown in Fig. 41.17. The insulator dielectric layer surrounds the polycrystalline silicon channel, and the control gate surrounds the insulator dielectric layer. This design increases the physical area of charge storage, eliminates the coupling interference between cells, and improves the cell performance and reliability. The stack layer number of 3D NAND is increasing with the technological progress. The stacking layer of 3D NAND has increased from 24 layers to 48 and 64 layers in 2016 and 2017, and further increased to 96 and 128 layers in 2018 and 2019; the MLC 3D NAND can reach up to 128 Gb, TLC can be up to 256 Gb or more. Combined with multichip stacking and wire bonding technology, flash component with higher capacity can be realized. 3D NAND is one of the most popular technologies in memory industry. As the demand for storage is increasing and the cost per bit of 3D NAND is decreasing, the solid-state hard disk market using 3D NAND is gradually replacing the traditional mechanical hard disk. At present, Samsung, Toshiba, Hynix, and Micron have produced their own 3D NAND. In addition, with the support of the National Integrated Circuit Fund, Yantz Memory Technology (YMT) at Wuhan China has also developed 64-layers 3D NAND flash memory with the new Xtacking™ technology in 2019.

FeRAM Ferroelectric random access memory (FeRAM or FRAM) is a storage technology based on “programmable ferroelectric capacitor.” FeRAM usually adopts 1T1C cell structure, as shown in Fig. 41.18. The difference between ferroelectric capacitor and

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Fig. 41.18 FeRAM 1T1C cell and sensing principle

Fig. 41.19 FeRAM program principle

general capacitor is a crystalline ferroelectric crystal film deposited in the middle of the two electrode plates. The position of central atom in the ferroelectric crystal represents the polarity of the direction of polarization for digital data “0” or “1.” As shown in Fig. 41.19, when an electric field is applied to the ferroelectric crystal, the central atom moves under the action of the electric field. When the electric field is removed from the crystal, the central atom remains in its position with a stable polarization state. The read operation is to apply a known electric field to the memory cell, the central atom will not move, when its position is in the place as if applied electric field would move it to; on the other hand, the central atom would

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crosses the high-energy level of the middle layer to another position, it will flip into another stable polarization state, which results in an electric pulse. The contents of the memory cell can be detected by comparing the electric pulse with a reference voltage. Because the read operation causes the state of the memory cell to change, the memory using the ferroelectric film capacitance effect is destructive read out (DRO) FeRAM. So a write recovery circuit is needed to keep original data after each read operation. The voltage-mode SA (VSA) is used for sensing data out, as shown in Fig. 41.18. First BL is pre-charged to 0, then WL is activated to VDD þ VTH (VTH is the threshold voltage of transistor), and the plate line (PL) is applied with voltage VDD. When the stored data is 0, CFE ¼ C0, BL voltage becomes V0 ¼ VDD * [C0/(C0 þ CBL)]; when the stored data is 1, CFE ¼ C1, the BL voltage becomes V1 ¼ VDD*[C1/(C1 þ CBL)], and finally SA is enabled and compared with the reference potential Vref ¼ (V0 þ V1)/2 to read the data out. WL voltage is maintained until BL voltage is written back to the memory cell. There is also a nondestructive read out (NDRO) FeRAM using metal ferroelectric semiconductor FET (MFSFET) as memory cell which replaces the gate dielectric layer with a ferroelectric thin film in conventional MOS field effect transistor. The state of the semiconductor surface is modulated by the polarization state of the ferroelectric thin film, thereby modulating the conduction state between source and drain of the transistor to distinguish between digital levels of “0” and “1.” The polarization state of the ferroelectric thin film will not change during read operation, thus the stored cell data is reserved. The advantages of FeRAM are fast speed, low power consumption, several orders of magnitude higher read and write cycles than EEPROM and flash memory, and it is nonvolatile, so it is especially suitable for embedded applications, such as in industrial control and automation, measurement equipment, financial terminals, and medical wearable devices. Although companies like Ramtron and Fujitsu have already introduced embedded and stand-alone FeRAM commercial products, they are limited by high manufacturing cost and poor scalability, and the highest density of FeRAM is still in the Mb range.

STT-MRAM Spin transfer torque (STT) magnetoresistive random access memory (MRAM) is a new type of MRAM technology. Spin-polarized current causes the magnetization direction of ferromagnetic materials to be reversed, thereby changing the magnetoresistance. As shown in Fig. 41.20, STT-MRAM storage medium is a magnetic tunnel junction (MTJ) consisting of three-layer structure: free magnetic layer, barrier layer, and fixed layer. The stored data is determined by the magnetization direction of the upper and lower layers of the film. If the magnetization direction is in parallel, it exhibits a low-resistance state, which represents “1”; otherwise, it exhibits a highresistance state, which represents “0.”

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Fig. 41.20 STT-MRAM 1 T-1MTJ cell structure

For the conventional MRAM, the magnetic field generated by the current passing through the word line and the bit line changes the magnetization direction of the magnetic film. Since the coercive field is relatively constant, a higher current density is required when the size of the memory cell is reduced, which makes it difficult to reduce the size of MRAM. STT-MRAM solves this problem using the currentinduced magnetic switching (CIMS) effect, that is, the spin-polarized current perpendicular to the plane of the ferromagnetic layer causes the magnetization of the ferromagnetic layer to reverse. As current flows from the free layer to the fixed layer, spin-polarized electrons flow from the fixed layer to the free layer. When the spinpolarized current is large enough (e.g., beyond the critical current), the device resistance changes accordingly, to reverse the magnetization direction of the free layer to be parallel with the fixed layer. The R-I characteristic of this nanomagnetic multilayer structure based on the CIMS effect is bistable, so the STT-MRAM is realized by the current-induced magnetic switching (CIMS) effect in MTJ. MTJ has in-plane MTJ with a magnetic torque parallel to the silicon surface, and another one more optimized for reducing the write current, perpendicular MTJ with a magnetic torque to vertical to the surface, is expected to extend below 10 nm. Unlike the traditional memories, emerging memories such as STT-MRAM, RRAM, and PRAM typically use a current mode SA (CSA), as shown in Fig. 41.21. The CSA will limit read margin and speed because of read disturb. When reading, firstly BL is clamped to URD (URD ¼ Uclamp), and then Ucell is discharged according to the state of the cell. When the magnetization directions of the two films are antiparallel, MTJ is characterized by high-resistance RAP, IAP¼URD/RAP. When the magnetization directions of the two films are parallel, MTJ is in low-resistance RP, IP¼URD/RP. The reference current Iref ¼ (IAP þ IP)/2, since IAP < Iref, Ucell > Uref, the final read data is “0,” otherwise it is “1.” STT-MRAM combines the advantages of high speed of SRAM, high density of DRAM, and nonvolatile nature of flash. And it has low operating voltage and low power consumption. Moreover, only two to three masks are needed for fabricating in

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Fig. 41.21 STT-MRAM sensing principle

CMOS logic process, so it is very suitable for embedded applications, such as embedding in FPGAs, CPUs, MCUs, and SoCs. Along with the maturity of pMTJ (perpendicular MTJ) technology, it will also play a role in the field of data storage. Therefore, STT-MRAM technology has broad application prospects. From the perspective of circuit design, the technical challenge encountered by STT-MRAM is that it is difficult to identify because of the low-resistance window (small tunneling magnetoresistance) and the wide resistance distribution. In addition, there is read disturb problem caused by read current. So it is important to focus on reading techniques that improve resolution and reduce read disturb. At the IEDM 2016, Samsung reported an embedded 8-Mbit pMTJ STT-MRAM based on a 28 nm CMOS logic manufacturing process. The R&D team of Hynix and Toshiba reported the first 4-Gbit stand-alone pMTJ STT-MRAM with a cell area of 9F2, which is very close to the DRAM cell size.

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ReRAM Resistive random access memory (ReRAM or RRAM) stores data based on the resistance values of the resistive material. When it is in high resistance state (HRS), it represents “1,” and when in low resistance state (LRS), it represents “1.” As shown in Fig. 41.22, the resistive cell uses capacitor-like metal-insulator-metal (MIM) structure, consisting of a layer of dielectric sandwiched by two layers of metal electrodes. The mechanism is that bias voltage between the electrodes lead to state change in dielectric material, conductive filaments are generated (i.e., SET, HRS becomes LRS, write “1”) or broken (i.e., RESET, LRS becomes HRS, write “0”). Data can be read out by measuring the resistance value. The metal electrode can be a conventional metal material, such as Au, Pt, Cu, Al, etc., and the dielectric layer material is a binary transition metal oxide (TMO), such as the potential candidate hafnium oxide (HfOx) and titanium oxide (TaOx)). Due to the difference of electrode material and dielectric material, ReRAM-resistive cell is divided into unipolar and bipolar. Bipolar cell resistance is related to both voltage amplitude and direction, while unipolar cell resistance depends only on the voltage amplitude in one direction. Currently, the structures of the ReRAM memory cell being studied include one-transistor one-resistor (1T1R, as shown in Fig. 41.22), one-diode one-resistor (1D1R), and one-selector one-resistor (1S1R) capacitors. The selection transistor in 1T1R can achieve isolation between cells, reducing leakage and alleviating cross talk problem, but the cell area is too large, so it is ideal for embedded applications where performance and reliability are prioritized. 1D1R and 1S1R can reach 4F2 (F is the minimum feature size) and are easy to implement cross-point array structure (cross-point) and three-dimensional (3D) stacking, reducing storage costs significantly, so it is very suitable for achieving high-density stand-alone memory. Like STT-MRAM, ReRAM adopts current-mode sense amplifier (CSA) to identify the cell resistance value by applying a small read voltage on BL.

Fig. 41.22 ReRAM 1T1R cell structure

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Compared with flash, ReRAM has the advantages of higher speed, lower operating voltage, longer work life, better miniaturization ability, and easier compatibility of CMOS technology. Therefore, it has broad application prospects and is considered to be the most potential competitor of next-generation nonvolatile memory (NVM) technology. First of all, ReRAM is ideal for embedded applications, its simple device structure makes the fabrication process relatively simple, requiring only one to two additional masks, and the material and integration process is fully compatible with standard CMOS processes. Secondly, with the maturity of 3D integration technology and the application of multilevel storage technology, it is still expected to become an important technology for large-capacity storage, which is widely used in many industrial fields, such as data computing and storage system. Furthermore, it has good anti-irradiation property for medical and aerospace applications. Of course, ReRAM has its own shortcomings. Because its physical mechanism is based on defect with poor controllability, it has poor device uniformity. This poses severe challenges in terms of device structure, integrated process technology, and circuit design technology. Based on its advantages, industry and academia have done a lot of research work on it. Many companies have made important reports at IEDM, ISSCC, and VLSI conferences, but currently only Panasonic and Fujitsu have related products for embedded applications.

PCRAM Phase change random access memory (PCRAM or PCM) stores data based on the resistance change before and after a phase change of the material. The chalcogenide (Ge2Sb2Te5 Ge2Sb2Te5, GST) is a relatively a mature phase change material. It undergoes a rapid reversible phase transition between crystalline and amorphous states after thermal excitation. The crystalline state is a low-resistance state, representing “1,” and the amorphous state is a high-resistance state, representing “0.” As shown in Fig. 41.23, the phase change memory cell consists of an upper electrode, a phase change material, a resistance heater, and a lower electrode. The

Fig. 41.23 PCRAM cell structure

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process of phase change material from crystalline state to amorphous state is called RESET (write “0”). After applying write current, the temperature of phase change layer rises rapidly due to the heating effect of the electric resistance heater. When the melting point of the phase change film is reached, part of the material melts, loses the state of the crystal, and locks it after rapid cooling. The amorphous state is very stable at room temperature. The process of phase change material from amorphous to crystalline is called SET (write “1”). When the material is heated to between the melting temperature and the crystallization temperature, nucleation and crystallite growth occurs rapidly within a few nanoseconds and the material changes to a crystalline state. The read operation is implemented using CSA, which identifies the resistance of the memory cell by applying a small voltage. Three challenges exist in PCRAM. Compared with SET process, the RESET process happens at a higher temperature and requires more current and heat, which is a major obstacle to the reduction of PCRAM size. Further, as the thermal conductivity of the resistance heater is low, in order to convert electrical energy to thermal energy to the greatest extent, it is necessary to increase the thermal conductivity; in addition, the difference between maximum resistance and minimum resistance can reach several orders of magnitude, which is very suitable for multilevel storage. However, the R-T curve of the phase change material must satisfy the step-like shape, and the resistance value of each step remains relatively stable over a wide temperature range to ensure the stability of the stored data. Therefore, the biggest challenge for multilevel storage is resistance drift. The resistance is highly correlated with temperature and the drift reduces read margin and causes read errors. Solving the above challenges requires a lot of work on memory cell materials and structures, as well as circuit design techniques. Phase change memory can be operated in bytes, with fast read and write speed, good endurance, and nonvolatility. In recent years, many companies have been working on it, including Samsung, Micron, IBM, and others. In July 2015, Intel and Micron announced the joint development of 3D X-Point memory technology, claiming that it is a revolutionary storage technology since NAND came out in 1989, the speed is 1000 times faster and the endurance is 1000 times longer than NAND flash, and the storage density is 10 times higher than traditional storage technology. Currently this technology allows a single chip with two layers to store 128 Gb data. In the future, the capacity can be further upgraded by improving lithography and increasing the number of storage layers.

Further Reading 1. T.M. Coughlin, Digital Storage in Consumer Electronics: The Essential Guide, 2nd edn. (Springer, Stanford, CA, USA, 2017) 2. B. Keeth, B. Johnson, F. Li, R.J. Baker, DRAM Circuit Design: Fundamental and High-Speed Topics, 2nd edn. (Wiley-IEEE Press, Piscataway, NJ, USA, 2007) 3. S. Oza-Rahurkar, Low Voltage, Low Power SRAM Design: Design Example (LAP LAMBERT Academic Publishing, Saarbrücken, Germany, 2016) 4. R.P. Tripathi, R.K. Verma, Design of Low Leakage SRAM (LAP LAMBERT Academic Publishing, Saarbrücken, Germany, 2018)

SoC Design

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Xiaolang Yan, Kai Huang, and Jianyi Meng

Contents System-on-Chip (SoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intellectual Property Core (IP Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware/Software Codesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security Enhancement Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Design for Artificial Intelligence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

System-on-a-chip (SoC) is an integrated circuit (IC) which implements CPU, memory, accelerating unit, and some peripheral interfaces into a unique design. With the continuous improvement of integration, more and more external chips or IPs are integrated into a single chip. The performance and functions of a SoC design have become more and more powerful. This chapter introduces the basic concept of SoC and IP cores. The embedded CPUs, system bus, peripheral IP cores, interrupt controllers, and software drivers are also introduced. In addition, the methodology of hardware and software codesign is introduced for realizing a function with both software and hardware. Finally, the security enhancement technology in the SoC is introduced to enhance the ability of information security.

X. Yan · K. Huang (*) Institute of VLSI, Zhejiang University, Hangzhou, China e-mail: [email protected] J. Meng Department of Microelectronics, Fudan University, Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_42

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Keywords

System-on-a-chip · IP core · Embedded processor · System bus · Interrupt controller · Software/Hardware codesign · Security enhancement

System-on-Chip (SoC) The SoC (system-on-chip) integrates various functional modules, including processor, memory, and peripheral interface, of an electronic system on one chip [1, 2]. SoC is essentially a complex IC, it boosts design efficiency with increasing chip scale and complexity, that is more highly integrated than application-specific integrated circuit (ASIC). A typical SoC is shown in Fig. 42.1 and comprises processor, memory, and various peripheral functional modules (IP cores), which are interconnected by system bus. SoC design tasks include such technologies as integration of IP cores, hardware/ software codesign, system functional verification, design for testability, and low-power design. IP literally means intellectual property, and IP cores in SoC refer in particular to circuit modules dedicated for specific functions. IP cores can be entirely reused by different designs, or be sold as a whole to a third party. The reusability of IP cores means the practice of directly integrating proven IP cores into SoC, which significantly shortens the design and development cycle. The hardware-software co-design technology means the technology of defining reasonable hardware and software architecture in accordance with system application requirements, and main indicators to be considered include cost, performance, power consumption, and memory architecture. Connecting circuits among IP cores and among functional modules in SoC are referred to as glue logic. Fig. 42.1 Typical SoC

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System functional verification means the process of employing such methods as simulation to check whether actual operation of the system meets defined requirements and help designers to better improve products. The DFT (design for testability) technology is used to identify errors in the chip-making process and tell defective chips from normal chips and generally includes the scan chain technology, memory self-test technology, and boundary scan technology. The low-power design technology is designed to reduce the power consumption of SoC in various aspects and generally include clock gating technology, multiple voltage domain technology, power gating technology, and voltage and frequency scaling technology. There are many types of SoC, e.g., single-core and multicore SoCs according to the quantity of processors in SoC. Single-core SoCs are used in application aimed only for controlling. Multicore SoCs are used in application scenarios such as largescale computing and stream media processing. If classified according to reliability levels, SoC can be a high-reliability SoC and a consumer-grade SoC. High-reliability SoCs are generally used in such fields as aerospace, military, industry, and automobile,while consumer-grade SoCs are used for consumer electronics. In terms of hardware logic programmability, SoC can be further divided into hardware programmable SoC (PSoC) and traditional hardware nonprogrammable SoC. Due to adoption of the hardware programmable logic technology, hardware programmable SoCs possess hardware programmability, flexible design methods, and reconfigurable, extensible, and upgradeable functions, and has the in-system programmability of hardware and software.

Intellectual Property Core (IP Core) The intellectual property core (IP core) means a circuit module that is applied in SoC and whose specific functions can be reused, and it has such features as standardization and tradable. IP cores are generally well-developed circuit modules that have been proven in industrialization and can be directly integrated by SoC designers into chips to shorten the design and development cycle significantly. Because numerous design techniques especially intellectual properties are adopted, IP cores play the role as an intellectual property carrier. In modern SoC design methods, designers are able to carry out SoC designs including digital/analog IC and modules like field programmable gate array (FPGA) on the basis of IP cores. One SoC architecture based on IP core is illustrated in Fig. 42.2. In terms of the form of delivery, IP cores can be divided into three types, i.e., soft core, hard core, and firm core. (1) Soft core is a process irrelevant design code described by the register transfer level (RTL) hardware description language (HDL). Soft core is based on the description of IP core functions and subjected to behaviorlevel design optimization and functional verification, and can be flexibly applied in various processes. (2) Hard core is the physical realization layout of soft core after logic synthesis, and placing and routing, and takes such forms as mask layout of physical structure of circuits and a full set of process files required for application.

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Fig. 42.2 One SoC architecture based on IP cores Fig. 42.3 Characteristics and requirements on packaging and reusability of IP cores

The advantage of hard core is that circuit placing and routing is bound together with specific process, thus ensuring such requirements as performance and power consumption and shortening SoC design time; its disadvantages are poor flexibility and difficult process transition. (3) The form of firm IP core ranges between that of soft core and hard core, and firm core is generally delivered in the form of gate-level netlist. The final placing and routing of firm cores is generally done by the user, so the shape, size, and port location of such cores can be changed. Therefore, firm IP cores have higher flexibility than hard cores. The reusability of IP cores is an effective methodology to boost SoC design efficiency. In order to enable the reusability of IP cores in different systems, the key is to conduct the packaging of IP cores. The characteristics and requirements of IP core packaging and reusability are shown in Fig. 42.3. IP core packaging requires the description of IP core’s complete information in different aspects, including configuration files, definition of signal port, bus type, and register address allocation. In order to ensure the reusability of IP cores, any information generated by IP core shall

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meet the reusability standard. The compatibility of such information with EDA tools, hardware and software library, and hardware design platform shall be checked, and the quality and reusability level of IP core shall be evaluated. IP core packaging generally obeys the following three principles. (1) Normalization principle: unify design specifications of IP core, e.g., regulate interface signal according to specific naming rules, unify reset modes, and regulate coding styles. Normative design assists subsequent use of IP and reduces introduction errors during system integration. (2) Simplification principle: gradually break down complex functional modules into a number of specific modules with unitary function. Generally speaking, simple designs can be more easily understood and integrated by third parties, which can reduce the introduction problems during designers’ design and verification. (3) Localization principle: define functions within a number of local modules whose functions are mutually independent and orthogonal, and define explicit interfaces among modules. Localization design combines key indicators including function, cost, power consumption, and timing with independent modules, and forms complex IP cores by splicing those modules. In summary, the international IP core standardization bodies including VSIA (Virtual Socket Interface Alliance), OCP-IP (Open Core Protocol International Partnership), and SPIRIT (Structure for Packaging Integrating and Reuse IP in Tool Flow) are working hard on the standardization of IP cores to increase the packaging and reuse efficiency of IP cores. The IP core standardization organizations are alliances set up by the SoC design industry to address the inconsistency of IP core packaging interfaces encountered in the SoC design process. Depending on different types of signals to be processed, IP cores can be divided into digital and analog IP cores. Among others, digital IP cores can be further divided into processor IP cores and peripheral IP cores: processor IP cores include Cortex series from ARM, MIPS32 series from MIPS, and CK series from C-SKY, while peripheral IP cores include DDR, PCIe, DMA, SPI, IIC, and UART. Analog IP cores include ADC, DAC, LDO, and PLL. Companies like Synopsys and Cadence can also supply analog IP cores.

Embedded Processor Embedded processor is the IP core “embedded” in SoC responsible for running software program, and is the control and computing core of SoC. Embedded processor is generally a low-power, low-cost processor. SoC’s requirement for embedded processor is a comprehensive balance of performance, power consumption, and cost. Working power consumption of embedded processor represents the bulk of SoC’s dynamic power consumption. In battery powered systems, the amount of power consumption of embedded processor directly determines the battery time of the whole embedded system. In addition, SoC’s cost control is strict and reducing hardware cost of embedded processor is SoC’s specific requirement. Embedded processor generally adopts the reduced instruction set computer (RISC) architecture, which has numerous single-cycle instructions and simple pipeline architecture. The

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embedded processor design principle is as follows: simplify the design as much as possible while retaining the functions meeting application requirements, and meanwhile carry out design enhancements in such aspects as processing capability, adaptability, and reliability depending on different application scenarios. At present, mainstream embedded processor architectures include ARM, MIPS, Tensilica (of Cadence), and ARC (of Synopsys); and CK series by C-SKY in Hangzhou, M* core and IBM PowerPC by C*core in Suzhou. Nowadays, mainstream embedded processor generally adopts 16-bit/32-bit instruction set, 32-bit/ 64-bit data path, and load/store memory architecture, whose basic instruction set adopts simple, direct instruction encoding method with simple functions and can conduct customization and extension for specific applications. Embedded DSP processor is a type of processor specially used for signal processing and is generally developed through customization of DSP processor or addition of DSP coprocessor to general-purpose processor. Its architecture and instruction algorithm adopt special design. Embedded DSP processors currently in wide use include CEVA DSP processor and Verisilicon ZSP processor. There are generally two development trends of embedded processor: firstly, high performance, e.g., mobile phone–embedded processor and the typical products are ARM Cortex-A processor series; secondly, low power and low cost, e.g., embedded processor used in IoT (Internet-of-Things) field, and ARM Cortex-M series are currently used widely. Embedded processors are generally operated through IP core licensing, ARM provides embedded processor IP core series and is now the world’s largest supplier of IP cores by revenue. In recent years, a number of opensource free processor IP cores have been emerging. A typical representative is RISCV led by University of California Berkeley, which can provide basic instruction set architecture (ISA) and reference prototype design.

System Bus The system bus is a public hardware channel for communication and interconnection among various devices (e.g., embedded processor, memory and peripheral IP cores) in SoC, and it provides an interconnection mechanism for devices to access shared hardware and undertakes the task of data transmission in the digital system. Depending on their different functions, devices connected by system bus are divided into master devices and slave devices. (1) Master devices mean devices that can initiate transaction tasks actively. For instance, a processor may control peripherals and read/write data through bus; some peripherals may also access other peripherals and read/write data through bus. (2) Slave devices are devices that respond to transaction tasks initiated by master devices. For instance, memory may respond to master device’s read operation and return read data. In addition, some devices may actively initiate an access to the bus as master devices, and may also respond to bus transactions as slave devices.

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SoCs are generally designed with many master devices and slave devices. Different slave devices correspond to different nonoverlapping address areas on the bus, and the bus initiates target address of transaction task through master devices. Different bus protocols are designed with different master device access modes. For instance, according to Advanced Microcontroller Bus Architecture (AMBA) 2.0 protocol, the devices on the same advanced high-performance bus (AHB) or advanced system bus (ASB) share a fixed address and data transaction channel. This means that when a master device occupies the AHB bus, all other master devices are in a waiting state. However, advanced extensible interface (AXI) bus in the AMBA 3.0 protocol uses different ID numbers to distinguish master devices, and a particular master device may initiate a request while the access by other master devices is not completed. A SoC architecture based on AMBA 2.0 bus as shown in Fig. 42.4. AHB bus connects high-speed devices like embedded processor and memory, while advanced peripheral bus (APB) connects low-speed devices like serial ports and timer. Bus arbitration mechanism includes polling mechanism and priority mechanism. While transmitting data, the bus may adopt different transmission types to adapt to transmission requirements at different lengths and rates. As a master device in the system, the highperformance ARM processor may access high-bandwidth external memory interface and high-bandwidth on-chip RAM through AHB bus, and may access low-speed devices on APB bus like UART, keyboard, timer, and PIO through AHB to APB bridges. Depending on different working frequencies, buses are designed as high-speed buses and low-speed buses: high-speed buses support high clock frequency and have high data bandwidth and performance with rather high power consumption, and they are generally used for connecting high-speed devices like CPU and DMA; low-speed buses have low working frequency, poor performance, and low power consumption, and they are suitable for connecting low-speed peripherals like keyboard and serial port. High-speed buses and low-speed buses may communicate with one another through bridge. Nowadays, influential buses

Fig. 42.4 One SoC architecture based on AMBA 2.0 bus

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among SoCs in the industry include AMBA bus, CoreConnect bus, Wishbone bus, and OCP bus, etc.

Peripheral IP Core Peripheral IP core refers to the generic terms of peripheral function IP core other than the embedded CPU in a system-on-a-chip (SoC), including the serial bus interface, memory controller, etc. Peripherals are generally connected with processors through buses and usually the slave devices of the bus. After receiving an instruction from the processor, the peripheral offers a specific function. As an important part of SoC, the peripheral assists the processor in completing the control, computing, and other tasks, which increases the work efficiency of the processor. The peripheral generally works under the control of processor, and the processor manages the peripheral through reading/writing the peripheral’s registers. The peripheral registers generally include two categories: The first category is the control register, and the processor writes the configuration of such registers to achieve the control of peripherals; the second category is the state register, and the processor knows the current working state of the peripheral through reading this type of register. According to function classification, there are four types of common peripherals. (1) General data transfer protocol interface peripherals, such as I2C, SPI, UART, MAC, USB, etc., and these peripherals carry out data receiving/sending according to a data transfer protocol. (2) General control peripherals, such as a general-purpose I/O interface (GPIO), a pulse width modulation interface (PWM), etc., which may perform special control over the pins. (3) Accelerator-type peripherals, similar to the coprocessor, accelerating the specific type of computing, such as image codec, highspeed encryption, and convolution operation. (4) System function peripherals, helping the processor to complete the system operation function of SoC, and ensuring the correct execution of the application, such as a timer and an interrupt controller. According to the speed classification, common peripherals are divided into the high-speed peripheral and the low-speed peripheral. (1) The high-speed peripheral performs complex tasks or computing with high working frequency, such as image processing accelerators, high-speed encryption and decryption engines, and highspeed communication interfaces. (2) The low-speed peripheral is generally responsible for low-speed communication of SoC with the outside, and maintaining the SoC system function with low working frequency, such as I2C and INTC. With the increase in peripheral types and improvement of performance, to match the speed, timing, and format between the peripheral and the processor, the peripheral has gradually developed into a circuit with the independent control units and interfaces. With the increasing diversity of peripheral function and the more demand of performance requirements, how to design a peripheral which is highly reliable, simple to control, smart, and easy to extend becomes the future development trend.

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Interrupt Controller Interrupt refers to a hardware request signal to the processer generated by the peripheral IP core in SoC, the peripheral requests the processor to suspend the currently executing task and to perform a specific task required by the peripheral. In interrupt mode, the processor can directly run other tasks after sending a task command to the peripheral, and handle the interrupt when an interrupt request arrives, avoiding unnecessary waiting, and increasing the parallelism between tasks. The generation and processing flow of an interrupt are shown in Fig. 42.5. Interrupt response and processing flow: After receiving an interrupt signal, the processor immediately stops the program currently being executed, save the current state of the processor and program counter, and then enter the interrupt service routine, and then resume original program after handling the interrupt. One interrupt service routine corresponds to one interrupt source, and each interrupt source has its specific interrupt service routine. In the interrupt service routine, a processor generally needs to carry out the work in three parts: the first is save context, i.e., in order to return correctly after interrupt handling, the processor status and the program counter prior to execution of special tasks that an interrupt source requests are saved; the second is to parse the current interrupt and perform a corresponding action; and the third is to restore context and then return to the program prior to interrupt. The interrupt controller is an IP core in SoC used for the interrupt source collection, masking, and priority management. The component generating an interrupt signal is referred to as the interrupt source, and the interrupt generated by the interrupt source is divided into the level interrupt and the pulse interrupt: the level interrupt generates one continuous valid level when the interrupt occurs and the valid level is maintained before the interrupt is cleared; one valid pulse is generated when the pulse interrupt occurs, the pulse is not maintained, and the interrupt controller needs to capture and record the pulse interrupt. In the case that the system application does not need concern over a certain interrupt, the interrupt generated by the

Fig. 42.5 Generation and handling flow of an interrupt

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interrupt source can be masked before being passed to the processor. The interrupt can be masked by setting the interrupt bit to be invalid in the interrupt controller. Both the system module and the peripheral may generate an interrupt, and if multiple interrupt sources generate an interrupt simultaneously, the processor core cannot respond to all interrupt requests at the same time. Therefore, in the case when multiple interrupts occur at the same time, interrupt shall be handled in some order, which means allocating the priority for different interrupts. An interrupt with a high priority is handled first, and that with a low priority is handled later.

Driver Driver is a special kind of infrastructure software that enables application software to communicate with hardware. Its function is to provide calling interface for upper software to control the work of hardware device. Firmware is a kind of driver that is fixed in the hardware by hardware vendors. The software and hardware architecture of SoC can be divided from bottom to top into hardware device, hardware driver, and upper software. And the hardware driver can be divided into hardware-dependent layer (HDL) and hardware abstraction layer (HAL), as shown in Fig. 42.6a. As an important part of the system architecture, the hardware driver mainly offers following functions: initialization and reset the equipment; read the request data transmitted by the upper software to the hardware device and return the response data of the hardware device; and detect errors and handle interrupts. Given a close connection with hardware devices, hardware drivers are usually provided by SOC vendors, which program the hardware driver based on the characteristics of the hardware. The interfaces and functions of hardware drivers needed to be realized are determined by hardware characteristics. From the perspective of the SOC software framework, at a lower level, the hardware driver controls the operation of hardware device, and, at a higher level, it provides the standard calling interface to facilitate the upper software to use. For the upper software, hardware drivers are like independent black boxes, whose function is to enable specific

Fig. 42.6 Block diagram of the software and hardware (including firmware) architecture of SoC

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hardware to provide services for the upper software in a standardized application interface manner, hiding the details of the operation of the device in the process of working. As long as the driver layer calls the same interface, software designers can make the application run on different hardware, and hardware designers can constantly upgrade the hardware without affecting the old software’s running on the new device. When the upper software needs to use a certain hardware function, it will first send corresponding instructions to the peripheral driver, which, after receiving the instructions, will translate them into electronic signal commands that the peripheral controller can understand. In an operating system, the hardware-dependent layer (HDL) is usually provided by hardware vendors in the form of firmware, while the hardware abstraction layer (HAL) is integrated into the operating system, and is provided by operating system vendors in the form of standard device driver, as shown in Fig. 42.6b. Currently, the Windows and Linux operating systems which have leading market shares both integrate the HAL in their system kernel. However, the upper interfaces of device drivers of different operating systems are not the same, and the firmware interfaces of different device vendors are also different. As a result, software developers cannot choose device vendors at will. In the future, standard device driver interface and firmware interface will be further standardized to enable software developers to seamlessly switch between devices from different device vendors.

Hardware/Software Codesign Hardware/Software codesign and co-optimization (HSCO) refers to the process of hardware and software conduct defining and developing together during the cycle of SoC development. When defining SoC, specific functions can be realized either by processors running software or by using specific hardware. Software implementation offers flexibility and scalability, but is less energy efficient; hardware implementation allows high-energy efficiency, but once the design is finished, changes cannot be made. Through the HSCO, we can quantitatively study the advantages and disadvantages of the software-based and hardware-based implementation approaches for each component in the system, so as to find out the optimal solution to SoC design. Thus, hardware/software codesign and co-optimization (HSCO) is a basic design methodology of SoC. Hardware/Software codesign can be divided into three stages, namely hardware and software partitioning, hardware and software cosimulation and verification, and hardware and software synthesis, as shown in Fig. 42.7. The hardware and software partitioning is to divide functions at the system level, with some of the functional modules of the system through hardware implementation and some through software implementation. When dividing the hardware and software functions, design developers should take into account of a variety of factors, such as the development time and costs of the system and the available resources on the market. In the SoC development and design process, the hardware

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Fig. 42.7 Hardware/Software codesign (HSCO) process

and software partitioning is a complex and difficult process, and is the most important part in the development and design of SoC. Hardware and software cosimulation and verification is to verify and evaluate the correctness and performance of hardware and software functional design. In traditional design, hardware and software are usually developed and designed independently. Then, at the later stage of the system design, the hardware and software are integrated together for verification. In the case of codesign, hardware and software are designed interactively, and the system’s software and hardware verification can be carried out at every stage of the design. The purpose of simulation and verification is to use the simulation and verification system to discover problems in design as early as possible in the early stage of design, so as to avoid alteration in the later stage of system design, since that may cause waste of time and more costs. Hardware and software synthesis is a process to transform high-level hardware and software description into low-level software and hardware implementation. Its

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main task is to study and utilize all kinds of hardware and software resources provided by the system under the constraints of system design, and realize the final hardware and software system on the basis of meeting the requirements of system design performance. Study on the methodology of hardware software codesign began in early 1990s, and then it grew rapidly. At present, the hardware/software codesign methodology is widely used in SoC design. A complete set of SoC hardware and software codesign and verification can be provided based on ARM’s RVDS (Real View Development Suite), Cypress’ PSoC Creator IDE, and Synopsys’ Virtual Platform.

Security Enhancement Design Security enhancement design refers to the use of specific design methods and technologies to enhance the security protection capabilities of integrated circuits. Security protection involves the whole hardware and software system. Different from security technology at software level, IC’s security enhancement design refers to the defensive design for side-channel attack (also known as SCA), which are applied to cryptographic chips and on-chip security systems. SCA refers to a series of attack methods aiming at the acquisition of sensitive information from the realization of hardware and software of cryptographic algorithm, and from the physical supporters of the realization. According to the different sources of sidechannel information, SCA can be classified into time attacks, power consumption attacks, electromagnetic attacks, sound attacks, fault injection attacks, etc. These attack methods are great threat to the security function of the chip. Only when the security of themselves are ensured, can these chips truly provide security services for the information society, realize identity authentication, maintain data security, and construct a trusted and reliable network. Security enhancement design is based on three basic principles to counter sidechannel attacks [3]. (1) Randomization: By some measures, the time, power consumption, electromagnetic, sound, and other information of cryptographic chip are randomized, which makes it hard for attackers to carry out data statistics and correlation analysis. (2) Blindness: Due to mathematical and algorithmic design, the attacker will lack critical additional information, cannot predict the sensitive content of the cryptographic calculation process, and cannot carry out the corresponding side-channel analysis. (3) Masking: The cryptographic chip masks the intermediate results of cryptographic operations by generating random numbers as the mask, while the final results of operations can be correctly recovered. Masking results in strong randomness of intermediate results and the difficulty of statistics and analysis of side-channel information increases dramatically. At present, security enhancement design technologies at algorithm level, architecture level, and circuit level have been studied and developed. For symmetric and asymmetric cryptography, corresponding anti-attack algorithms are developed in the algorithmic structure, which can eliminate and hide the side-channel information that may be leaked. The anti-attack algorithm will introduce some redundant operations,

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which will result in additional burden on the performance and power consumption of cryptographic chips. Security enhancements can be designed for microarchitectures of CPUs and cryptographic accelerators, such as repairing vulnerabilities of the microarchitecture, adding security instructions and special hardware units, which can effectively suppress many side-channel attacks. On the other hand, a new type of circuit logic which is highly secured can be proposed to fundamentally solve the side information leakage caused by unbalanced power consumption of CMOS complementary logic. However, much antiattack circuit logic has the problems of large area and high-power consumption. How to balance capability of anti-attack and cost of implementation is also an important research area. As shown in Fig. 42.8, the implementation of chip security enhancement requires systematic and cross-level design techniques, so as to establish security barriers at all design levels and prevent attackers from using vulnerabilities and side-channel information at any level to threaten the security of the core part of the chip.

Fig. 42.8 Multilayer security enhancement design technology

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The emergence of security enhancement design is closely related to the rapid development of SCA technology. The differential power attack method proposed by Professor Paul Kocher in the 1990s [4] is a milestone in the history of side-channel attacks. Since then, academia and industry have fully realized that cryptographic chips must have measures and technologies to defend against side-channel attacks, thus giving birth to the technical direction of security enhancement design. Infineon, NXP, and other companies have accumulated strong technical strength in security enhancement design, which has made their chip products have anti-attack characteristics. In recent years, China has made great progress in the security enhancement design of cryptographic chips. Relevant IC design companies in China have developed smart card chips with certain defensive ability against attacks, and have formed corresponding technical capabilities in security protection. With the vigorous development of Internet and IoT technology, the problem of network space security has become increasingly prominent, and the importance of chip security enhancement design has become increasingly critical. In the future, not only IC design entities, but also various network technology companies and Internet operators will contribute to the important issue of improving chip security. The technology of security enhancement design will continue to develop. At the same time, the industry will develop and improve the whole process automatic detection equipment and integrate development environment for chip protection. The security enhancement design through the whole process will integrate the key technologies of each level and single point into an organic entirety to maximize efficiency, and pay attention to the collaborative development of hardware carrier and software environment to enhance the level of automation and intelligence and ensure a good user experience.

IC Design for Artificial Intelligence At present, artificial intelligence (AI) has become one of the most popular hot spots. AI in research and application fields make computers have capabilities similar to human intelligence that makes meaningful judgments on the input of the environment through research and development of computers. The factors that determine the quality of AI are usually the computing power and the amount of data. The way to achieve AI is adopting machine learning (ML), which allows the machine to gradually approach the effect we hope to achieve through training and learning. With the rapid growth of processors’ computing power and data volume, the way of machine learning is also undergoing revolutionary changes, and the concept of deep learning (DL) has been introduced. Deep learning enhances its nonlinearity through its multilevel morphology, which can lead to stronger fitting ability. In addition, it is similar to the process of layer-by-layer automatic extraction of features from bionics, which guarantees the quality and richness of the extracted features, which improve its performance when compared with traditional ML algorithms. With the development of the algorithm model, the performance of the model is gradually improved, and the depth and complexity of the model itself is greatly increased. Taking the ImageNet Large-Scale Visual Recognition Challenge

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(LSVRC) as an example, released by Alex Krizhevsky of the University of Toronto and his mentor Geoffrey Hinton, AlexNet won the championship with 83.0% Top5 classification accuracy in 2012, and its performance has increased by more than 10% compared to the previous traditional model. AlexNet itself is a convolutional neural network with a five-layer convolutional layer and a three-layer fully connected layer, containing 61 million weight parameters and 7.4 billion multiply-accumulate operations. By the year of 2017, the most complex network model layer has more than 1000 layers, the weight parameters and the number of multiplication and addition operations are several orders of magnitude higher than AlexNet, and the recognition accuracy that can be achieved has surpassed that of human. AlphaGo, which recently defeated many human Go masters, its complex decision-making model requires more than 1300 CPUs and 280 GPUs to provide computing power in its first version of the distributed implementation that defeated Li Shishi. It can be seen that, to meet the strict power consumption and real-time requirements of the increasingly complex artificial intelligence algorithms, a powerful processor is needed as a support; therefore, the refined design of the processor chip is the necessary condition for application requirements of improving and satisfying the computing performance of the chip. Generally speaking, for AI, whether it is model training or forward inference, the computing speed of the processor chip is an indicator that needs to be considered first; and in some low-power scenarios such as application in embedded mobile devices, the hardware power consumption also needs to be strictly controlled. Traditional CPUs are stretched out when facing data and computationally intensive artificial intelligence algorithms due to their serial execution. Therefore, increasing the parallelism in processor computing is a major direction of performance improvement. NVIDIA proposes the concept of general-purpose GPU (GPGPU) computing, which applies GPUs with a large number of parallel computing stream processors to the development of AI algorithms, and provides mature and stable software environment support such as CUDA (Compute Unified Device Architecture) and cuDNN (Compute Unified Deep Neural Networks). Due to the powerful computing power of the GPU, the GPU has been widely used in model training scenarios focusing on model accuracy and data center, and server environment. But we also noticed that common GPU boards consume up to 200–300 W, which limits their use in low-power scenarios. Therefore, considering the application scenario and the type of algorithm, the internal architecture of the chip is customized to improve the overall energy efficiency ratio of the chip, which becomes another mainstream direction for the development of artificial intelligence chips. Generally speaking, for a certain type of AI algorithm, it often has a partitionable characteristic, and the divided subalgorithm blocks have certain similarities. Taking the convolutional neural network which is commonly used in image applications as an example, the most densely convolved convolution layer can be abstracted into a sliding window type multiplication and addition operation, and the size and stride of the sliding window and the number of calculation channels can be abstracted as configurable parameters. In hardware architecture design, the computation path and the storage structure are usually customized and configurable for the algorithm in

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consideration of the way of it is divided and abstracted. Most researchers will quickly and iteratively develop accelerated hardware structures using FPGA chip implementations. A number of research institutions have already released FPGAbased accelerated architecture design at top academic conferences, and industry companies have begun to deploy common algorithm models in applications through FPGA acceleration, and achieve good performance and low-power consumption. Next, we can also design the computing and storage cores as an application-specific integrated circuit (ASIC) to achieve higher-energy efficiency. The outstanding ASIC chip design known today has been able to control power consumption to the milliwatt (mW) level with hundreds of GOPS (billion operations per second) computing power. ASIC has many advantages in high-energy efficiency and low production cost under the premise of wide application market. However, its one-time engineering cost and large development cost often have certain risks in the process of rapid algorithm evolution. Therefore, different platforms should be selected for different R&D and market needs. In recent years, algorithm optimization for hardware implementation has also been evolving, including data quantification, model sparsification, and other technologies that have progressed, and these technologies have helped reduce the on-chip computing resources and storage bandwidth limitations of artificial intelligence chips while achieving higher throughput at a lower hardware cost. The variability of data bit width and the irregularity caused by model sparsity pose a challenge to the realization of hardware implementation. In the future, the AI chip design will be more inclined to hardware and software codesign and co-optimization (HSCO) to achieve more optimized and general solutions.

References 1. W. Fischer, N. Homma (eds.), Cryptographic Hardware and Embedded Systems – CHES 2017, 19th International Conference Taipei, Taiwan, September 25–28, 2017 Proceedings. Springer 2. P.C. Kocher, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, in CRYPTO, (1996), pp. 104–113 3. H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, L. Todd, Surviving the SOC Revolution: A Guide to Platform-Based Design (Kluwer Academic Publishers, Boston, 1999) 4. M. Arora, Embedded System Design: Introduction to SoC System Architecture (Learning Bytes Publishing, Islamabad, Pakistan, 2016)

Programmable Logic Circuit Design

43

Shaojun Wei and Shouyi Yin

Contents Programmable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field-Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrically Programmable Logic Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable System-on-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reconfigurable Computing Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Programmable logic circuit (PLC) has the advantages of high flexibility, short development cycle, and strong scalability. It is widely used in communication, industrial control, military, and other fields. This chapter focuses on the PLC design technology. Firstly, it introduces the main categories and functional characteristics of PAL, GAL, complex PLD (CPLD), and FPGA. After that, the hardware description language, system structure, storage mode, and other core technologies of the representative programmable logic devices (PLD), such as field programmable gate array (FPGA), electrical programmable logic device (EPLD), and programmable system chip, are analyzed. Finally, the main advantages and technical features of the state-of-the-art reconfigurable computing chips in this field are introduced. Keywords

Programmable logic · PLD · FPGA · EPLD · Programmable system on chip · Reconfigurable computing chip

S. Wei (*) · S. Yin Institute of Microelectronics, Tsinghua University, Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_43

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Programmable Logic Programmable logic is a circuit logic that provides multiple functions which can be implemented by programmable logic devices (PLD). Programmable logic has many advantages over fixed logic. First of all, the flexibility of the programmable logic is relatively high, and the required functions can be changed at any time through programming. Secondly, the development cycle of the programmable logic circuit is shorter than the fixed logic circuit (such as ASIC), and the development cost is relatively low; finally, the programmable logic circuit is very scalable, allowing for later functional updates and upgrades. Fixed logic devices are suitable for massive large-scale applications, and for some circuits that require very high performance, fixed logic circuits are more suitable than programmable logic circuits. The first commercial programmable logic device (PLD) is programmable array logic (PAL) from Monolithic Memories, Inc. in 1978. In recent years, the market share of PLD has grown rapidly, and their functions have become more diverse, and high-performance programmable devices have begun to be popular. The current PLDs can be mainly divided into three categories. (1) Generic Array Logic (GAL): Developed on the basis of PAL and invented by Lattice Semiconductor. GAL has the same characteristics as PAL, but GAL can repeatedly be burned or clear the circuit configuration and architecture configuration, while PAL can only be burned once. (2) CPLD (Complex PLD): Compared to PAL and GAL which are suitable for small logic functions, CPLD can realize a larger circuit. There are usually several PALs inside a CPLD, and the interconnections between PALs can also be programmed according to requirements. (3) Field Programmable Gate Array (FPGA): Based on the technology of gate array, it has been developing with continuous innovation. In addition to the logical part, the PLD also contains a storage part. The data storage carriers are mainly Si anti-fuses, SRAM, EPROM, or EEPROM and flash memory. The current development of PLD is mainly implemented by computer programming. The source code is written in hardware description language (HDL). The hardware description language is best known for VHDL and Verilog HDL. The development direction of PLD programmable devices is toward high density, high speed, and low power consumption. As the design of PLDs has grown in size, electronic design automation (EDA) has become the primary design tool.

Field-Programmable Gate Array Field-programmable gate array (FPGA) is based on PAL, GAL, and CPLD. It is a semi-custom circuit that offers lower development cost, expandable functionality, and more logic cells than full-custom circuits. At present, the hardware description language (Verilog or VHDL) is used to describe the circuit logic, which is the mainstream technology for FPGA design verification, and then the relevant software tools are used to perform logic synthesis, layout and routing, etc., and then burn the produced files to the FPGA chip.

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Although FPGAs are slower and have lower performance than application-specific integrated circuits (ASICs), they have the advantage of being less difficult to develop and their internal functions can be modified over and over again. At present, FPGA is almost a must-have component in electronic systems. This is because the convenience and flexibility of FPGAs help electronic products quickly seize the market. While field-optimizable CPLDs and FPGAs both contain a large number of programmable logic cells, their system architectures are greatly different. Compared with CPLD, FPGA has more connection units; it is more flexible but also more complicated. CPLD has fewer connection units and the delay time is easier to estimate. Another obvious difference is that FPGAs have built-in high-level modules and memories such as adders and multipliers, so many new FPGAs can be reconfigured within the system. Currently, the following are mainly the ways to store programs in the FPGA. (1) Programmable read-only memory (PROM): It can be programmed only once, and the programmed content cannot be erased. (2) Erasable programmable read-only memory (EPROM): An erasable and programmable technology that can erase the content in memory with UV light. (3) Anti-fuse: Usually CMOS circuit and can only be burned once. (4) EEPROM: Programmable read-only memory technology that can erase content with electrical signals. (5) Static Random Access Memory (SRAM): Based on static memory technology, programmable within the system. (6) Flash: A special type of EEPROM. Currently, the most well-known FPGA vendors are Xilinx, Altera (now Intel), Actel (now Microsemi), Lattice Semiconductor, and Achronix Semiconductor. The inventor of FPGA, Xilinx, is the largest FPGA supplier in the world.

Electrically Programmable Logic Device Electrically programmable logic device (EPLD) is an erasable programmable logic device that uses electrical signals. The design process of EPLD usually has the following main steps: 1. Use schematic diagram or hardware description language to describe the logic. 2. Before the designer writes the designed logic onto the device, it is necessary to perform verification of the design result, which is generally through computer software simulation to check whether it meets the design requirements, and this is called “pre-simulation.” 3. After computer software compiling the logic description into a simplified Boolean algebra expression, the compiler software adapts the specific expression according to the target device and generate the standard load file (JED file) of the device. This process is usually referred to as “synthesis.” 4. The logic is downloaded to the device for functional verification. The logic functions of EPLD devices can usually be designed using schematic or hardware description languages. The schematic description is very straightforward,

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and the circuit function is directly used to describe the circuit function. The disadvantage is that it is not concise. Commonly used hardware description languages are Verilog and VHDL. The hardware description language can accurately implement the logic functions of the circuit. For simulation and synthesis, the most commonly used tools are ModelSim and Quartus. A programmer is a device that programs a programmable device. The JED file needs to be downloaded to the device by the programmer to let the chip work according to the design logic. The process of programming through downloading means that the computer downloads the JED file into the programmer and then writes the JED file to the device according to the characteristics of that device. EPLDs are a type of PLD that are not yet configured or programmed for a specific purpose. Typically, an EPLD has an array of initially unconnected programmable logic devices; to be configured or programmed by the user electrically, they are used to build reconfigurable devices that can be used in a variety of applications depending on their programming. EPLDs have an undefined function when they are manufactured, which is unlike logic gates that already have a defined set of functions. There are limited reports on EPLDs in recent years on this technology in the literature; a research group at Portland State University has used EPLDs from Cypress Semiconductor for self-testable and self-repairable study as well as for a routing partition fitting problem [1, 2].

Programmable System-on-Chip Programmable system-on-chip (PSoC) is an embedded system design solution developed on the basis of programmable logic devices (PLDs) to meet the increasing demands of system integration [3, 4]. System designers can switch from previous board-level system designs to chip-level system designs and implement various functional units required for design and integrate them into FPGAs in the form of IP (Intelligent Property), thus achieving high efficiency, flexible, and highly integrated embedded systems. PSoC features the entire system on a single chip. The design process is to describe the system function using the top-down method and begins with the top of the system behavior level, i.e., collaborative design from application function, software algorithm, chip architecture, embedded operating system, and circuit module to devices. The core design technologies of PSoC mainly include the following three aspects. 1. Software and hardware co-design and co-verification technology: to comprehensively trade off the system design metrics, perform software and hardware function partitioning of complete system functions, and accomplish design space exploration. 2. IP core generation and multiplexing technology: At present, IP core multiplexing has become the core technology in integrated circuit design. Through the

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inheritance, sharing, and reuse of the IP core, the EDA tool can realize the system function design, synthesis, and verification, which greatly improves the design efficiency, accelerates the development process, and effectively reduces the development risk. 3. System level and inter-module interface design and verification technology: PSoC has various modules such as software and hardware function modules, IP core modules, and circuit modules. Inter-module interface communication becomes a key issue in system design and verification. At present, Xilinx, Altera, etc. have released a variety of PSoC products and solutions, implementing co-processing architecture combining processor cores (such as ARM, NIOS, etc.) and FPGA. PSoC solutions have been widely used in many areas such as network communication, data center, and machine learning. In general, PSoC technology is to integrate large and complete electronic systems into a single programmable system chip as much as possible, to make the electronic system optimally designed in function, performance, power consumption, reliability, size, cost, time-to-market, product maintenance, and hardware upgrades. A PSoC can integrate analog and digital blocks into a single system; PSoC can integrate MCU, ASIC, and FPGA for a single application [1, 2].

Reconfigurable Computing Chip The design of reconfigurable computing chip is based on a reconfigurable computing architecture. Reconfigurable computing is a parallel computing mode of spatialtemporal programming. In contrast, the traditional general-purpose processor is the computational mode of temporal programming, and the FPGA is the computational mode of spatial programming. The reconfigurable computing chip is a disruptive technology in the field of integrated circuits and has wide applicability. The so-called reconfigurable computing refers to the use of programmable computing resources in the system under the control of configuration information to construct the most suitable computing architecture according to the needs of the application, to achieve or close to the high performance of the ASIC. The essence of reconfigurable computing is to reconfigure the functions and interconnections of programmable computing resources multiple times, making the system suffice for high performance, low power consumption, easy maintenance, and low cost. The reconfigurable computing chip hardware architecture consists of a reconfigurable datapath (RCD) and a reconfigurable controller (RCC), as shown in Fig. 43.1. The reconfigurable datapath is responsible for parallel processing of the data stream, and the reconfigurable controller is responsible for configuration information management and task mapping scheduling. In a reconfigurable computing system, the datapath can be dynamically reconfigured by calling or modifying configuration information, which preserves the computational performance of custom circuit (in a hardware way) and the computational flexibility of the general processor (in a software way).

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Fig. 43.1 Diagram of reconfigurable computing chip architecture

The configuration strategy of the reconfigurable computing chip can be characterized into static reconstruction and dynamic reconstruction. The static reconstruction can only reconstruct the function of the datapath of the reconfigurable computing chip before the computing starts but cannot reconstruct the function of the datapath during the computing process due to the large time cost. The most typical reconfigurable computing chip with static reconstruction characteristics is FPGA. A common working mode of an FPGA is to load configuration information from off-chip memory for system reconfiguration when the system is powered on. The size of the FPGA configuration information is generally large, and the reconstruction process typically lasts from tens to hundreds of milliseconds or even up to several seconds. After the functional reconfiguration is completed, the FPGA can perform the corresponding computation. The functionality of the FPGA can no longer be reconstructed during the computing process. If computation is needed, be sure to first interrupt the computing task currently being performed by the FPGA. Because it is a single-bit programming device (fine-grained reconfigurable computing chip), the flexibility of the FPGA is very high, and almost any form of digital logic can be realized without considering the capacity. This is one of the important reasons why FPGAs can be very successful in business. However, the fine-grained reconfigurable size makes FPGA need a lot of configuration information, and the time cost and power cost of reconfiguration become very large. The reconfiguration time of a typical dynamic reconfigurable chip is generally in the range of a few nanoseconds to tens of nanoseconds. Since the time cost of function reconstruction is relatively small, the feature that the datapath of the reconfigurable computing chip can also perform functional reconstruction in the calculation process is called dynamic reconstruction. The most typical reconfigurable computing chip with dynamic reconstruction features is CoarseGrained Reconfigurable Architecture (CGRA). The usual way CGRA works is that

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after CGRA completes a given computing task, it quickly loads the new configuration bit stream for functional reconfiguration. The reconfiguration process usually lasts only a few to a few hundred clock cycles. After the functional reconfiguration completes, CGRA continues to perform the computational tasks for the new configurations. A major feature of reconfigurable computing chips that differs from other circuit implementation is the need to configure the datapath. Once configured, it can perform the specified functions with high performance like an ASIC circuit. As shown in Fig. 43.2, the reconfigurable datapath is loaded externally by the configuration loader, which forms part of the configuration of the reconfigurable datapath. It is important to shorten the configuration time of the reconfigurable datapath, so that switching between different configurations can be completed quickly, and the real-time processing capability of the circuit can be improved. There are two common ways to shorten the configuration time. One is to increase the granularity of the datapath to reduce the total amount of configuration information; the second is to reduce the amount of configuration information input from the outside of the datapath through a hierarchical configuration structure. A hierarchical configuration structure can greatly compress configuration information. Since different levels of configuration information are stored in different memories, and each layer of configuration information contains a list of the next layer of configuration information to be used, the configuration information is fetched layer by layer,

Fig. 43.2 Configuration information fetching technology

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instead of fetching large amount of input from outside. In addition, since the higherlevel configuration information only contains a list of the lower-level configuration information, the lower-level configuration information is repeatedly used by different lists, thereby reducing the total amount of configuration information. When the reconfigurable datapath is configured, the hierarchical configuration structure is fetched layer by layer, and finally each datapath unit will get its own configuration information. By parsing the configuration information, the datapath controlling module controls the operation of each computing unit, the input/output of data, and the loading time of the configuration information, thereby performing scheduling of the entire reconfigurable datapath. In recent years, reconfigurable computing technology has become a new hot spot in integrated circuit research. The reconfigurable computing chip has the characteristics that hardware changes with software changes, and software and hardware can both support programming, which breaks through the traditional hardware-based software programming calculation mode and realizes the energy-efficient dynamic reconfigurable computing technology of “circuit changes with algorithms, architecture changes with applications.”

References 1. D.V. Hall, M.A. Perkowski, C.H. Lee, D.S. Jun, Evolvable Hardware, NASA/DoD Conference on Self-Repairable EPLDs: Design, Self-Repair, and Evaluation Methodology, vol. 1, pp. 183 (2000) 2. M. Chrzanowska-Jeske, S. Goller, Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device, in Proceedings of EURO-DAC 93 and EUROVHDL 93- EDAC, vol. 1, pp. 39–44 (1993) 3. D. Tomanek, What is PSoC?, in 2010 International Conference on Applied Electronics, Sept 8–9 (2010) 4. K. Xue, G.C. Wan, M.S. Tong, Construction and validation for a PSoC wireless transmission system, in 2016 Progress in Electromagnetic Research Symposium (PIERS), 8–11 (Aug. 2016)

Electronic Design Automation Tools

44

Xiaoming Liu, Yi Liu, Taotao Lu, Fan Yang, and Junqi Yang

Contents IC Design Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow Management Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Level Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Capture Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog/Digital Mixed-Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Formal Verification Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design for Testability Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Generation of Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Generation and Optimization of Testing Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Design Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parasitic Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accurate Computation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Modeling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout Verification Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Rule Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout vs Schematic (LVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Rule Check (ERC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout vs Layout (LVL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Power Analysis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Timing Analysis (STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Timing Analysis (DTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Analysis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design for Manufacturing (DFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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X. Liu · Y. Liu · T. Lu · F. Yang (*) Huada Empyrean Software Co., Ltd., Beijing, China e-mail: [email protected] J. Yang School of Microelectronics, Fudan University, Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_44

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Design for Yield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 Design for Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

Abstract

EDA is the acronym of Electronic Design Automation. IC designer uses EDA tools to complete schematic design, layout design, circuit simulation, design verification, chip manufacturing, and packaging testing. The automation and intelligence of EDA tools improve the efficiency and accuracy of IC designs. The main EDA tools used in IC design can be divided into three categories: input design and data management, synthesis design, and verification and optimization. The input design and data management tools help users quickly to input design objects, design requirements, and manage the design data, for instance, hardware description language (HDL) and compiling, input and editing, the design and process management of integrated circuit, and layout. The synthesis design tools help users to convert behavioral RTL design into structural gate-level netlist design, which is accomplished through placement and routing, etc. The verification and optimization tools help users to verify the validity of IC design and the rationality of improved design structure, for instance, IC simulation and verification, physical design rules and LVS check, layout parasitic parameter extraction, sequential and power consumption improvement, manufacturability, yield, reliability, etc. Keywords

EDA · Schematic capture · Layout capture · Simulator · Logic synthesizer · Formal verification · Design for testability · Physical design · Parasitic extraction · Layout verification · Timing and power analysis

IC Design Automation Electronic design automation (EDA) tools, as an important part of IC design automation in IC design industry, can assist design engineers to execute every design stage in IC design flow. EDA tools widely used in IC design can be divided into three categories: design creation and data management tool; design synthesis and design implementation tools; verification and optimization tool [1]. (1) The design creation and data management tools help users quickly create and input design objects, design requirements, and manage design data, for instance, hardware description language (HDL) and design compilation, input and editing, design and process management of IC, and layout. (2) The synthesis design tools help users accomplish the design of each level, for instance, the system design and synthesis, logic synthesis, placement

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and routing, etc. (3) The verification and optimization tools help users verify the validity of their design and the rationality of improved design structure, for instance, IC simulation and verification, physical design rules and LVS check, layout parasitic parameter extraction, sequential and power consumption improvement, manufacturability, yield, reliability, etc. The design flows of digital circuit and simulation circuit associated with EDA tools are shown below in Figs. 44.1 and 44.2. The automatization and intelligence of EDA tools spare users from complicated operations and significantly improves the efficiency and accuracy of design. Based on this perspective, the logic synthesis is the most prominent application of EDA tool. Different companies must obey the same data criterion of EDA tools, e.g., OpenAccess (for the database standard), GDS II and OASIS (for layout data standard), etc. Since all EDA tools have standard data interface, users can easily access to any EDA tools from different companies throughout the design process at different levels and there is no need of data format conversion for different EDA tools. In recent years, EDA technique has rapidly developed. More and more new EDA techniques and tools are emerging in annual global conference – Design Automation Conference (DAC). Nowadays, most EDA R&D enterprises are located in the USA, such as Synopsys, Cadence, Mentor (acquired by Siemens in 2017), etc. Empyrean Software is a representative of China EDA R&D enterprises.

Fig. 44.1 Design flows of digital circuit and related EDA tools

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Fig. 44.2 Design flow of analog circuit and related EDA tools

Flow Management Tool Flow management tool is a standardized management tool which helps IC designer accomplish massive complicated IC design with high quality in a minimum period of time. The “flow” in flow management includes the process from requirement definition to generating layouts at each design stage, the process of checking the quality of intellectual property core (IP core) and standard cell library, and the process of clients’ customization. Flow management tool basically manages design data and configuration data. Design data includes the data from the whole process of IC design, e.g., circuit schematics, layouts, RTLs (register transfer level), netlists, circuit simulation result, timing and power analysis results, parasitic parameter extraction result, etc. Configuration data includes the corresponding design data of IP core, standard cell library, physical verification rules, technology physical property information and SPICE model. Functionalities of flow management tool offer functions such as: 1. Information Sharing: forms dependency between each phase; collects changes from each phase; delivers messages of phase changing to the team members 2. Authority Management: assigns different authorities to different designers; protects the safety of design data 3. Version Management: manages different historical versions for the same data; switches and compares data of different versions

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Fig. 44.3 Design time statistics for different phases

4. Data Synchronization: synchronizes data from different designers; compares and combines conflicting versions 5. Issue Tracking: records issues of each phase; helps designer track the process of each phase 6. Open Interface: provides open development environment and third-party tool interface; facilitates data input and migration; facilitates extension of customized functions 7. Visualization of Flow: collects information at each stage of creating; observation, configuration, execution, tuning, and report; connects each phase together via graphical interface and statistical analysis; helps users with a convenient and straight-forward method manipulate IC design project The design time statistics of different periods, which are used in logic synthesis, design and planning, placement and routing, and chip assembling, is shown in Fig. 44.3. As the chains of IC design and the types of data become more and more abundant, the data volume grows larger, and the demand of collaborative design becomes more urgent. It will be necessary to use flow management tool to manage design processes and design data.

System Level Simulator System level simulator’s functions are modeling and simulating the electronic system at high level so that the iteration from system design to physical implementation and the risk of issues raised during mid- and late-phase of physical implementation are reduced.

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System level simulator supports system modeling flexibly by using built-in or outer estimation algorithm, implementation algorithm, and simulation algorithm to evaluate and to verify the functions and performance of the system. System level simulator uses system modeling language to describe the system. Modeling language has the following features: 1. Builds up system models of every functional module; allows modeling with different levels to describe different modules; allows information exchange between modules 2. Provides choices of different implementation for modules, for instance, using hardware or embedded core to implement, choosing different structures to implement, etc. 3. Provides various module libraries; supports implementing of specific module by using existing design modules or IP cores C/C++, SystemC [2], and SystemVerilog (IEEE 18002017) are commonly used modeling languages. To satisfy the evolving requirement of simulation and system description, new system modeling languages are developing. Some languages describe the system abstractly, which satisfies general system design, such as UML (Unified Modeling Language™) and SysML (Systems Modeling Language); the others support more on the customization of embedded system design, such as SMDL (Semantic Model Definition Language) and SSDL from the system design tool Teraptor ®. Many system-level simulators describe system based on modules with GUI (graphical user interface), such as LabVIEW (Laboratory Virtual Instrument Engineering Workbench, from National Instruments), MATLAB (Matrix Laboratory, by MathWorks), SystemVue (from Agilent), VisualSim Architect (from Mirabilis Design), and Simulink (by MathWorks). In short, system-level simulators are broadly used in system and chip design by many design companies. It plays an increasingly important role in design, verification, and debugging in embedded systems and SoC.

Schematic Capture Tool A schematic capture tool provides interactive schematic editing functions, which can accomplish hierarchical schematic design and provide necessary data support for IC simulation, placement and routing, and full custom layout design. Schematic capture tool supports component symbol input and schematic input according to the hierarchical design of the schematic, corresponding to symbol and schematic view. The function of component symbol input is to create its corresponding component graphical symbols based on the characteristics of the schematic, which is used to reference it at high level IC design. The function of schematic input is to represent the connection between electronic components, the parameters of electronic components, and the characteristics of the circuit.

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Schematic capture tool also provides the function of generating component symbols of components automatically. Figure 44.4 shows the schematic of an inverter and its corresponding component symbol. Schematic capture tool can describe the circuit at system, module, unit, and transistor level. It offers creation and editing of the parameters of components, circuit nodes, and annotation and supports electrical rules checking, such as short circuit and open circuit. The data stored by schematic capture tool is divided into physical information and logical information. Physical information generally refers to graphical data, such as the shape of I/O, the location information of I/O, etc. Logical information refers to the connection information of the schematic which is the topology information of the schematic. There are two types of data exchange provided by schematic capture tool: Electronic Design Interchange Format (EDIF) and netlist. EDIF generally contains physical and logical information of the schematics. The data of the different schematic capture tools can be exchanged in the form of EDIF. Netlist, which is different from EDIF, does not contain physical information and only contains logical information. Depending on the application, different forms of netlist, such as CDL (circuit description language), SPICE, Spectre, and Verilog, are commonly used. SPICE and Spectre are also both used as names of circuit simulators and names of netlists. Due to the development of IC design methodology and increasing difficulty of design, schematic capture tools present two major trends: usability and scalability. For usability, schematic capture tool provides more convenient and flexible functions, such as using different colors to distinguish the connections of wires, real-time electrical rule checking, intelligentized connection, etc. For scalability, schematic capture tool not only satisfies the requirements of creating and editing schematics but

Fig. 44.4 An inverter: (a) schematic view, (b) symbol view

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also provides more interfaces for cooperating with other tools, such as interface of schematic simulation tool, interface of debugging simulation results, interface of schematic driven layout, interface of constraint driven layout, etc.

Circuit Simulator Circuit simulator can be divided into three categories: transistor-level analog circuit simulator, gate-level and RTL-level digital circuit simulator, and analog/digital mixed-signal simulator.

Analog Circuit Simulator The basic flow of analog circuit simulator is shown in Fig. 44.5: The problem of analog circuit is expressed with a partial differential equation as: f ð V t Þ þ Eð V t Þ ¼ I t 

dQt dt

where t is the time, Vt is the node voltage, It is the node-independent current source, Qt is the node charge, f(Vt) is the nonlinear node current, and E(Vt) is the controlled node current. By using Newton-Raphson iteration method, the equations can be solved to get the following iteration result: V t,iþ1 ¼ Y t 1 I t 

dQt  f ðV t,i Þ  EðV t,i Þ þ V t,i dt

where Yt is the Jacobian matrix of f(Vt) þ E(Vt) and i ¼ 1,2,3,. . . is the iteration step: Y t ¼ @ ðf ðV t Þ þ EðV t ÞÞ=@V t Generally, Yt is a sparse matrix whose complexity of calculation can be reduced by LU decomposition algorithm. Before decomposing, re-ordering the rows and columns of Yt reduce the effort of decomposition as well as improve the stability of

Fig. 44.5 Analog circuit simulator process

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iterative computation. Yt of circuits with special structures is a dense matrix which can be solved better by using algorithms such as PCG and GMRES. Charge Qt partially differentiated of time t can be calculated by single-step algorithms such as forward and backward Euler methods or multi-step algorithms such as TRAP and GEAR. The accuracy and stability of the algorithms are influenced by the type of the circuit. The effort taken to solve the equations increases extraordinarily as the number of nodes increases, so lots of acceleration techniques are introduced into commercial analog circuit simulator. 1. Parallel computation: distributes the calculation on current and Jacobian matrices to multiple CPU. 2. Bypass technology: when node voltage changes in slight manner, linear interpolation is used to skip recalculation of nonlinear current and Jacobian matrices. 3. Node folding technology: uses linear interpolation method to eliminate inner nodes of nonlinear components in order to reduce the number of equations. For larger circuits, simulators introduce fast SPICE technologies which reduce the accuracy but increase the speed and capacity of simulation greatly. These technologies include the following. 1. Table model: uses table looking up and interpolation method to calculate the current and charge of nonlinear components. 2. Event-driven: divides the circuit into multiple partitions and solves them only when the port signal is changed. 3. Isomorphism: sharing Jacobian matrices of partitions with the same structure and similar node voltages; solves the equation set once; and uses linear interpolation to correct the tiny differences between partitions. Moreover, parasitic effects can influence the performance and functions of IC, so post-simulation of analog circuit accounting for the parasitic effects is introduced. In post-simulation, parasitic components cause the size of matrices increase extremely and coupling effects cause the matrices denser, so the acceleration technologies are introduced to increase simulation speed and capacitance with little influence in accuracy. Some common technologies are shown below. 1. RC Reduction: simplifies parasitic RC networks into equivalent circuits with relatively small scale via physical or mathematical equivalent methods [3]. 2. Circuit Partition method: divides the circuit into several partitions with little coupling effect, calculates to get the result and substitutes result of all partitions back to the top port matrix to get the solution. Some common methods are Hypergraph-Partition, BBD, and SuperLU [4–6]. 3. Multi-Rate method: partitions circuit according to work frequency; sets relatively small time step for partitions with high-frequency signals to ensure calculation

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accuracy; sets relatively large time step for partitions with low-frequency signals to increase calculation speed.

Digital Circuit Simulator Figure 44.6 illustrates the digital circuit simulation process. Digital circuits are usually described with VHDL, Verilog HDL, and SystemVerilog languages. Those types of languages offer the quantization and test of the sequential relationship of logic signal. Digital circuit simulator uses event-driven method to simulate signal logics, which means the I/O signal of logic unit works at finite logic state and its output is recalculated only when the state of input signal changes. The event-driven method is shown in Fig. 44.7. In digital circuit post-simulation, SDF (Standard Delay Format) file with accurate delay timing extracted from post layout of circuit design can be attached to get more accurate result [7]. Digital circuit simulation is faster but less accurate than analog circuit simulation.

Fig. 44.6 Digital circuit simulation process

Fig. 44.7 Digital circuit simulation with event-driven method

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Analog/Digital Mixed-Circuit Simulator There are analog and digital signal circuit simulators, to simulate at transistor-level, gate-level, or RTL-level. The core of analog/digital mixed-signal simulator is identifying connection node between analog signal and digital signal and conversion algorithms which transfers the continuous analog signal and discrete digital signal in the node back and forth. Analog/digital mixed-signal simulation is illustrated in Fig. 44.8.

Logic Synthesis Tool Logic synthesis tool performs step-by-step to automatically transform a digital design from an RTL description to a gate-level netlist through Boolean minimization and optimization. Figure 44.9 shows the working flow of logic synthesis. Logic synthesis can take the following three inputs: RTL design in Verilog or VHDL language description; target timing, area or power constraints; technology libraries that contain logic gates, such as AND, OR, XOR, NAND, and registers. Logic synthesis compiles, synthesizes, and optimizes RTL circuit description according to the target constraints as described below:

Fig. 44.8 Analog/digital mixed-signal simulation process Fig. 44.9 Working flow of logic synthesis

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1. Compiles RTL input design in Verilog or VHDL hardware description language into technology-independent initial circuit. 2. Performs arithmetic optimization for arithmetic logic operations (such as addition; subtraction, multiplication, division, and complex mixed calculation) from the initial circuit. For instance, there can be different architecture implementation methods for a multiplier to achieve different timing, power, and area trade-off. The appropriate selection of the implementation method based upon the target constraints greatly affects the final synthesis quality of results. 3. Performs technology-independent sequential and combinational optimization. Sequential optimization mainly includes finite state machine (FSM) and register optimization. Combinational optimization mainly involves Boolean optimization. 4. Maps optimized technology-independent sequential and combinational logic into gate-level netlist. Then the synthesis compiler performs technology-dependent optimization to meet target timing, power, and area constraints, based upon those available from technology libraries. After finishing the above process, logic synthesis will then generate an optimized gate-level circuit netlist. It must be ensured that the logic functions are equivalent to the initial input RTL design. As IC design scales continue to grow and manufacturing technologies continue to shrink, synthesis compiler should consider the effects of back-end placement and routing for more accurate timing and area estimations, in order to achieve better correlations between front-end synthesis and back-end place and route. At the same time, to increase the design efficiency, it should also adopt hierarchical and parallel optimization techniques to reduce the turnaround time due to growing design complexity.

Formal Verification Tool Formal verification tools determine whether the functional behavior of a hardware design is correct or not by using mathematical and logic algorithms. There are usually two kinds of methods: equivalence checking and property checking. In IC design process, many steps can edit and change the function of a design, for example, inserting testing logic structures, clock tree synthesis, ECO, etc. Verification by using simulation is very time-consuming and also it is hard to guarantee verification coverage. Through static and mathematical logic algorithms, equivalence checking is used to compare the logic consistence between original design and the optimized design. In theory, the design checking can be fully covered. Given two netlists (initial netlist and revised netlist), suppose that their input signals, output signals, and the number of registers are the same, then an equivalence checking tool usually pairs input signals, output signals, and registers in the initial and revised netlists to generate multiple pairs of combinational logic cones. Then, it uses algorithms such as BDD (binary decision diagram) [8] and SAT solver (conjunctive normal form solver; SAT stands for the Boolean satisfiability problem) to

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Fig. 44.10 Equivalence checking

compare the two combinational logic cones in every pair. If, for all the pairs, the two combinational logic cones’ Boolean functions are equivalent, the static and sequential logic functions of two netlists are the same [9]. The concept of equivalence checking is shown below in Fig. 44.10. When there are different numbers of registers in the initial netlist and revised netlist, the algorithm above usually will find that the Boolean functions of two combinational logic cones in some pairs are not equivalent. In such situation, we cannot conclude that the functions of two netlists are the same or not, and thus we have to use some sequential equivalence checking algorithms to further analyze whether the logic functions of two netlists are consistent or not [10]. Property check is the method of analyzing whether a given design satisfies certain properties or assertions. First, use logic structure to describe system models, such as sequential logic structures and finite state machines; use formal logic expressions to describe desirable properties. Then, use formal verification algorithms to check whether the design satisfies those properties or not. Property checking algorithms can be further classified as theorem proving or model checking. Theorem proving techniques represent the design and property under validation by using certain formal logic expressions, and then those expressions are transformed by using axioms, reasoning rules, and proved theorems to show that the design satisfies those properties. This process usually requires manual involvement and good understanding of how the system is designed and its functionalities. Model checking uses sequential logic structure or finite state machines to describe the design under validation and uses temporal logic to describe the properties that the design should have. Then, it searches design state spaces using techniques such as BDD, SAT solver, and ATPG (Automatic Test Pattern Generation) and checks whether the design satisfies those properties in all possible states or not [11]. If any property is not satisfied by the design, model checking can give counterexamples for better fault location. Model checking algorithms usually do not require manual involvement. However, if the design’s reachable state space is too large, it will encounter the so-called state explosion problem that may prevent it from obtaining final result in a limited time.

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As the complexity of IC designs continues growing, equivalence checking and property checking technologies also need continued improvement to handle designs with growing scale.

Design for Testability Tool Design for testability (DFT) tools in IC industry can automatically generate test logic circuits and test vectors by manual insertion or tool synthesis. Design for testability tools can improve the coverage of test significantly and reduce the difficulty and cost of testing chips in automatic test equipment (ATE).

Auto Generation of Test Circuit Scan-based design is the most common design for testability (DFT) tool. It converts the registers of testing circuit into scan registers and then connects the scan registers to one or more scan chains to transmit testing signals. The generation of testing circuit in DFT involves a series of complex operations which usually requires the help of automatic tools. A typical DFT synthesis flow is shown in Fig. 44.11. There are four main steps in the process: 1. 2. 3. 4.

Converts regular sequential registers into scan registers Checks whether the test circuit meets the DFT rules or not Automatically/manually repairs the part of circuit that violates DFT rules According to DFT constraints and target setting, connects scan chains and composes the required logic to be added

Automatic generation results of testing circuit include gate-level netlist with DFT, DFT operation descripted by STIL (Standard Test Interface Language), and DFT analysis report.

Fig. 44.11 Automatic process of scan-based design for testability

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Automatic Generation and Optimization of Testing Vector Based on DFT netlists and STIL results, Automatic Testing Vector Generator can produce signal of testing vector needed for chip testing automatically. After optimized by compression coding, broadcasting compression, and logic transform compression, testing vectors can reduce the amount of test data, the time taken by testing, and the number of test channels on the premise of guaranteeing the test coverage. D algorithm, also known as multi-dimension path sensibilization method, is the first complete automatic test pattern generation (ATPG) algorithm [12] whose basic ideas are using circuit simplify table and D vector propagation in order to pass the faults to output along all the sensitized paths and then obtaining the final testing vectors via compatibility check. To ensure the validity of choosing sensibilization methods in massive combinational circuits, PODEM and FAN algorithm improved D algorithm [13, 14]. Then SOCRATES [15] improves the efficiency of logic implication, path sensibilization, and multiple back trace. The industrial ATPG tools mostly use methods based on SOCRATES and make further improvements. In addition to those scan-based design DFT methods, there are some more DFT solutions in recent industry. LBIST (logic built-in self-test) adds special hardware or software components into the circuit and tests the circuit itself without external test equipment. LBIST and MBIST (memory built-in self-test) can be used in memory self-tests.

Physical Design Tool The function of physical design tools is to accomplish IC layout design by automatic placement and routing technique or manual editing. Automatic placement and routing can be divided into four steps: floor planning, placement, clock tree synthesis (CTS), and routing [1]. Floor planning ensures chip area, optimizes module shape, and allocates the placement area for standard cells, I/O pad, and macro under certain geometrical constraints. Some commonly used floor planning algorithms are the following: placement dimension-changing algorithm; module placement based on the growth of clusters; simulated annealing algorithm; and mapping problems into analytic solutions of equations. Placement is divided into two categories: global placement and detailed placement. It places standard cells on the legal position in rows of core area and satisfies the design rules, which optimizes the performance requirements of wire length, timing, congestion, and power consumption. The problem of placement is NP-complete problem which cannot be optimized by algorithms with polynomial time complexity. In real applications, we usually search for a feasible solution as an approximation of the optimal solution. Algorithms commonly used in solving placement problems can be divided into three categories which are graph algorithm (depth-first search and critical path), deterministic algorithm (linear programming,

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non-linear programming, and dynamic programming), and stochastic algorithm (simulated annealing algorithm [16]). The placement flow can be solved as below using simulated annealing algorithm. Given initial temperature T¼T0 (T0  0), Iteration time at every temperature N, initial solution state X0 while (T > 0) { for (loop¼1; loop random(0, 1)) { Set Xnew as current new solution } } Lower temperature T } Output the optimized result derived from above

Clock tree synthesis inserts buffer in clock circuit and transfers clock signal to every synchronous cell (flip-flops) so its optimization goal is that the path delay and clock skew are reduced as much as possible. Some common clock tree synthesis algorithms are H-tree algorithm and fishbone algorithm, as shown in Fig. 44.12. In order to reduce clock skew and influence caused by process variations, highperformance clock system design also uses mesh structure but that takes more routing resources and area.

Fig. 44.12 H-tree type clock tree and fishbone type clock tree

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Routing is divided into global routing and detailed routing [17]: global routing reasonably allocates nets to proper routing area and avoids congestion at local zone; detailed routing accomplishes the connection between pins and vias on the routing tracks in order to avoid short and open error. According to the area of routing and the distribution of nodes in the area, detailed routing can be divided into channel routing, switchbox routing and region routing. Results of double channel routing and net vertical constraint graph are shown in Fig. 44.13. With the development of IC technology at 28 nm node and more advanced technologies, physical routing needs to support multiple patterning technology (MPT) so that manufacturability is guaranteed. Additionally in IC physical design environment, one must rely on layout editing tools to input the layout information. Layout editing tools provide a 2-D geometric graphics creating and editing environment based on polygons and offer interactive editing and operation functions according to layout’s features and design rules. It will output physical layouts in GDS II or OASIS format. The basic functions of layout editing tools include the following: (a) supports hierarchical editing; (b) binding with the technique, distinguishes different layers of technique according to specific color, wire type, and filing; (c) supports creating, zoom-in/zoom-out, and stretch of basic shapes such as rectangle, polygon, path, etc.; and (d) uses parameterized cell to reduce duplicate input. As IC design methodology develops, requirements for layout editing tool become more advanced, which mainly reflects as follows: (a) Introduces two types of new technologies by interacting with circuit: SDL and CDL (b) Derives auto placement and routing for analog circuit by combining analog and digital circuits (c) Provides quick display and multithreading query for higher requirements of massive expanded design scale (d) New technology of layout editing is demanded with the development of current techniques, such as grid-aligning technology for FinFET

Fig. 44.13 Double channel routing result and net vertical constraint graph

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Parasitic Extraction Parasitic extraction functions as extracting parasitic parameters of layout interconnect wires and devices according to the process technology data in order to obtain circuit netlists with parasitic parameters for performance analysis and postsimulation of circuit. Parasitic parameters include parasitic resistance, parasitic capacitance, and parasitic inductance. Parasitic parameters have impact on time delay, power, and signal integration significantly. As process develops, parasitic parameters have become the key factors of circuit function and performance. In IC design, parasitic extraction is one of the indispensable steps in IC design. Two typical parasitic parameter extraction methods are available: accurate computation method and fast modeling method. Accurate computation has high accuracy but low speed, so it is usually used in small-scale applications with high requirements in accuracy, such as process analysis, building standard cell library, RF circuit analysis, etc. Fast modeling method has lower accuracy but is thousands times faster than accurate computation method, so it is always widely used in chip-level parasitic extraction.

Accurate Computation Method Accurate computation method, also called field solver method, calculates the parasitic parameters through solving electromagnetic field equations to get accurate field distribution. Accurate computations are similar for parasitic capacitance, resistance, and inductance. The example below shows accurate computation of parasitic capacitance. Accurate computation method of parasitic capacitance is based on numerical method which solves the following Laplace equations with bias voltages [18, 19]. ek ∇2 u ¼ ek

@2u @2u @2u þ þ @x2 @y2 @z2

u¼u @u ¼q¼0 q¼ @n @u @u ea  a ¼ eb  a , @na @na

¼0

within Ωk ðk ¼ 1, ⋯, MÞ above Γu above Γq

ua ¼ ub

above ΓI

where Ω ¼ UΩk is to be resolved domain and Ωk stands for the space possessed by the kth dielectric, M is the total dielectric number, u is the bias voltage, q ¼ @u/@n is the electric flux, and εk is the dielectric constant of kth conductor. Here n denotes the unit vector and a and b are two neighboring media. According to different numerical methods, accurate computation method applies mesh partition to 3-D field and discretizes Laplace equations into integral equations on the mesh. It solves linear equations to obtain the electric field intensity on the surface of conductors. Then it solves for induced charge through the equation below

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Qi ¼

847

Γi

e

@u dΓ @n

which calculates Qi the charge Q of the ith conductor; following the equation, Cij ¼ Qi/Vij, each capacitance value can be calculated. Numerical methods include boundary element method (BEM) and finite element method (FEM). BEM discretizes 2-D boundary of 3-D area, uses weighted residual method, and applies Green formula to convert Laplace equations to discrete integral equations on 2-D boundaries. Meanwhile, it uses boundary conditions to convert the discrete integral equations into linear algebra equations and solve for solution. FEM discretize 3-D area directly. It uses variation principle to convert Laplace equation into extreme problem to minimize the value of error function in every element and then converts integral equations into linear equation sets to solve for solution.

Fast Modeling Method Fast modeling method analyzes geometric graphs of layouts by building parasitic parameter model and then uses pattern matching method to derive parasitic parameters. Commonly used models are 2-D and quasi 3-D models. Since quasi 3-D model considers the property of 3-D structure, its calculation result is more accurate than 2-D model’s, so it is widely used in large-scale layout parasitic extraction. Using parasitic capacitance calculation as an example, quasi 3-D model divides capacitors in 3-D structure into overlap capacitor, lateral capacitor, and fringe capacitor to consider their effects to the total capacitance separately as shown in Fig. 44.14. Each capacitance value is calculated by a table look-up model or analytical formula method. Fast modeling method requires accurate computation method to calculate the typical patterns and to build the model library, produces model parameter of calculated layout geometries according to pattern match method, and searches through model library to get results. As process develops, more and more process factors influence parasitic parameter. 3-D structure grows more and more complex, which sets higher requirements for

Fig. 44.14 Quasi 3-D model diagram

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parasitic parameter extraction. Meanwhile, the circuit scale continuously grows larger, which sets higher requirements for parasitic parameter extractor in speed and accuracy. Parasitic parameter model is so complex that it must consider multiple factor combinations to get better computation accuracy. Especially in FinFET technology, due to the huge difference between device structure and traditional process, parasitic extraction encounters new challenges.

Layout Verification Tool Layout verification tool is used to check whether the layout satisfies design rules, electrical rules, and consistency between layout and schematic or not [1], which plays an important role in reducing risk of design faults. Layout verification tool supports both flat and hierarchical mode. Flat mode is the foundation of layout verification tool; hierarchical mode takes full advantage of layout hierarchy to efficiently avoid repetition errors and to improve the speed of processing layouts. For large-scale layouts, parallel technology is applied to improve the efficiency of layout verification. Layout verification tool mainly includes design rule check (DRC), layout vs schematic (LVS), electrical rule check (ERC), and layout vs layout (LVL).

Design Rule Check Layout design must obey the design rule of manufacturing technology which includes width, spacing, enclosure, density, and antenna check. Any violation in layout design will cause manufacturing failures, for example, open circuit error which might be due to small wire width. The key technology used by DRC includes hierarchical processing and scan-line algorithm. Hierarchical processing technology adjusts layout-line algorithm to cause manufacturing failures, e.g., open circuit. Scan-line algorithm includes scan-line algorithm based on trapezoid and edge. Edge is a line segment and expressed by the coordinates of its two ends. Scan-line algorithm based on edge basically converts one 2-D geometric problem into two 1-D problem, which includes the following steps: (a) Get the location of current scan line. (b) Add new edges into the current scan-line and construct the current scan-line and edge set with the initial edges. (c) Sort the edge set in the current scan-line. (d) Traverse the edge set in the current scan-line and carry out logical process according to different commands. (e) Delete the leaving edges in the current scan-line and go back to step a.

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Fig. 44.15 Use scan-line algorithm to calculate “AND” of two layers

In Fig. 44.15, L1 and L2 are input layers; x1, x2, x3, and x4 are coordinates which guide scan-line terminate to calculate; Result is the result layer.

Layout vs Schematic (LVS) The main functions of LVS tools are checking the consistency between netlists extracted from layouts and those from schematics. Major technologies involved are netlist extraction technology and netlist comparison technology. The main job of netlist extraction is to extract the net, device, and devise properties in circuit. The essence of netlist comparison is the graph isomorphism problem in graph theory. The fundamental theory of LVS comparison is, given initial matching pairs, matching more devices and nets by tracking and given no initial pairing, obtaining initial matching pairs by signature partition [20]. By repeating the above steps, the process stops when all devices and nets in layouts and schematics are matched or no new matching pair comes up. For unmatched devices and net, it checks the environment to repair and to rematch; if repair failure appears, it reports the failure as an error. Among LVS comparison, signature partition method assigns corresponding signature values to devices according to the type of devices and divides devices into different sets according to the signature values. According to the connection between nets and devices, it also assigns signature values to nets and divides them into different sets. In Fig. 44.16, two circuits are extracted from layout and exported from schematic separately where LVS reports an open circuit error.

Electrical Rule Check (ERC) The electrical rule check (ERC) is aimed to verify violations such as open, short, path check, etc. ERC is based on layouts; it can quickly check and directly locate common problems in design without schematics. ERC functions are included in LVS tool.

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Fig. 44.16 Netlist comparison

Layout vs Layout (LVL) Layout vs layout (LVL) tool is applied mainly in two fields. First, when revising layouts, designers need LVL tool to help check the difference before and after revision. On the other hand, since layout data is usually flattened when making mask, LVL tool is used to compare the difference of layouts before and after flattening. LVL check involves key technologies such as hierarchical processing, scan-line algorithm, data compression, parallel computation, etc. In addition, since there are few rules involved, LVL can apply special acceleration techniques according to different types of layouts. After the technology progressed at 40 nm node and beyond with narrower metal lines and spacing and thinner inter metal dielectric layers, the influences among metal lines and coupling with interconnection environment is more significant and

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the optical proximity correction (OPC) takes into effect. The 2D check technology used by classical layout verification tool cannot satisfy the requirements anymore, so there is a need of using 3D and optical analysis to analyze various effects and to develop new checking technologies, such as pattern match, double/multi-pattern, smart fill, etc.

Timing and Power Analysis Tool Timing analysis tool is used to check whether the design of synchronous circuit satisfies given time constraints (setup constraint, hold constraint, etc.). It is divided into static timing analysis (STA) and dynamic timing analysis (DTA). Power analysis tool is a separate analysis engine used to analyze both static power (such as leakage power) and dynamic power (such as clock nets switching) dissipations.

Static Timing Analysis (STA) STA is an adequate method to do time verification for massive gate-level circuits; it does not require testing vectors to calculate timing path delay. To begin with, STA uses statistical wire load model or SDF resistor and capacitor value. According to time model in cell library and topology structure of circuit, it checks whether the setup time and hold time for every flip-flop satisfy the design requirements or not. Its advantages are high coverage rate and high speed; its disadvantage is the disability of analyzing asynchronous logic circuits and analog circuits. Static timing analysis uses PVT (process, voltage, and temperature) corners, such as BC, TC, and WC (best, typical, worst cases; see Fig. 44.17) to reflect different working conditions of circuit under environments with different PVT conditions. Cell library, under each corner, is characterized for the cell timing model (time-delay value and time constraint value). Theoretically, time closure ensures that chips in every working scenario has no time violation. Practically, one or more special corner will be selected for validation.

Fig. 44.17 Timing check at BC-WC mode

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(a) Single model: Uses the same corner condition to analyze the setup time and hold time for each timing path in the whole circuit. (b) Best-case/worst-case model: Uses the best conditions to analyze hold time of time paths; uses the worst conditions to analyze setup time of time paths. (c) OCV (on-chip variation, see Fig. 44.18) model: Uses amplification and reduction multipliers to slow down data path transfer and speed up clock path transfer when analyzing setup time and vice versa when analyzing hold time. With 28 nm node and beyond, advanced OCV (AOCV) appears to extend OCV [21]. It eliminates the pessimistic factors of OCV and checks the list to get time delay value for every cell according to different depths of logic and different physical distances of time paths. In order to tackle the systematic and random changes in chips and between chips, statistical static timing analysis (SSTA) method is introduced [22]. It uses probability distribution functions to calculate the arrival time of each signal at each node in order to eliminate unnecessary timing over correction. The difficulty of SSTA is that the probability distribution function is difficult to calculate and the memory required for calculating massive statistic data is huge associated with long run time.

Dynamic Timing Analysis (DTA) In SoC design at 16 nm technology node and IoT ultra-low voltage designs, STA timing calculation based on corner is not accurate so that dynamic time analysis based on transistor-level simulation is required. It uses parallelism and special acceleration technology to accomplish fast and accurate simulation of critical time paths and obtains exact time information of time paths to help timing convergence.

Power Analysis Tool Power analysis tool gives statistical report based on temperature, switching activity, load, current, voltage, and power of the circuit. It analyzes the circuit power integrity issues due to IR-drop and electromigration (EM). Its main functions include the following:

Fig. 44.18 Timing check at OCV mode

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(a) Signal Integrity Analysis: Checks APL/LIB/LEF library cell data; checks correctness and completeness of DEF/SPEF/IPF/STA/VCD design data (b) Design Defect Analysis: Checks whether the resistance, capacitance, and peak current of power/ground network matching the expected value or not (which might be due to the unreasonable distribution of pad, the non-optimized power/ ground routing and excessively high frequency) (c) Hotspot Analysis: Checks whether static resistance and current, dynamic IR drop, and power electromigration satisfy the sign-off standard; if there is violation, locates the issue in the area and traces back to the find the root causes

Design for Manufacturing (DFM) In semiconductor industry, design for manufacturability or design for manufacturing (DFM) refers to a set of methods applied for the early stage of designs, where the difficulties, specifications, and constraints of manufacturing processes are taken into account. Therefore, the final products hold good manufacturability and yield, and they can be manufactured with lower cost, less time, and higher quality. In IC, for the severe challenges of IC manufacturing process, DFM technology mainly includes the design optimization of the front-end-of-line (FEOL) and backend-of-line (BEOL) of ICs to solve or to partly alleviate the difficulties of process manufacturing, in order to improve the functional yield and parametric yield. As process nodes of IC technology have progressed at nanoscale, IC manufacturing is facing increasingly serious challenges. For example, sub-wavelength lithography processes using light sources with 193 nm wavelength cause serious distortions of patterns on silicon wafers, and chemical mechanical polishing (CMP) process leads to serious deviation of interconnects in its thickness (vertical direction). Therefore, the impacts of IC process variations become more and more serious. In sub-wavelength lithography, even applying resolution enhancement techniques (RET), distortion phenomena such as “round-off,” “short,” and “partial disappearance” are still easy to occur at the ends and corners of interconnects, as shown in Fig. 44.19. The patterns, producing severe distorted patterns on wafers, are termed lithography hotspots, which are prohibited in layouts. Designers need to thoroughly check all hotspots with lithography hotspot detection tools before the tape out. Figure 44.20 describes the effect of dummy filling on chip surface topography after chemical mechanical polishing (CMP). After inserting metal dummies, the height variation of chip surface is obviously smaller than that if no inserting dummies. Unfortunately, the introduced dummies will usually increase parasitic capacitances and deteriorate circuit performances. Therefore, the main challenges of dummy filling tools are how many dummies to insert, where to insert dummies, and what are the shapes of dummies. The above technologies of lithography hotspot detection and dummy insertion are commonly used in DFM.

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Fig. 44.19 Lithography hotspots

Fig. 44.20 The surface topography of chip before and after dummy insertion and CMP

Generally speaking, DFM technologies are an extension and optimization of traditional EDA design flows, which usually includes the following technologies. 1. DFM-aware standard cell design not only considers the manufacturability of the standard cell itself but also considers the interaction of lithography near the boundary of adjacent cells. In standard cell synthesis with DFM, besides meeting the traditional design rules, it also needs to be compatible with a large number of new added DFM design rules. Even in order to improve yield, the standard cell line-gap needs to be optimized. In order to be compatible with non-traditional lithography processes, such as multiple pattern lithography (MPL) and selfaligned double pattern lithography (SADP), and to satisfy constraints of increasing tension of routing channel resources, the pin accesses need to be carefully optimized. 2. In DFM-aware placement optimization, the effects of double/triple/multiple patterning lithography (DPL/TPL/MPL) and chemical mechanical polishing (CMP) should be taken into account during placement of processes under 20 nanometers. 3. DFM-aware routing optimization considers the compatibility with non-traditional lithography technologies such as multiple patterning exposure and electron beam lithography, etc., besides the optimization objectives of routability and total wire length in traditional routing algorithms.

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4. DFM-aware mask optimization technologies include layout decomposition of multiple exposure lithography, DSA (directed self-assembly), electron beam lithography and their hybrids, hotspot detection technology in mask, etc. 5. Metal dummy insertion is used to improve the smoothness of chip surface topography after chemical mechanical polishing. 6. Redundant via improves the reliability of via. When process nodes of IC enter nanoscale, some DFM technologies are now in the reference flows of foundries. They become the necessary steps for designers to follow. In the foreseeable future, DFM technologies will continue to expand with the development of emerging manufacturing and design technologies. With the help of electronic design automation (EDA) tools with DFM-aware function, IC designers need to fully consider the difficulties in manufacturing in the early stage of design, in order to improve the yield of IC chips after tape out.

Design for Yield As IC technology node continues to shrink, the adoption of complex processes has made process variations increasingly serious. Process variation refers to the random fluctuations in geometry and electrical parameters during IC fabrication. For example, sub-wavelength lithography using 193 nm wavelength light source leads to wafer pattern deviations, chemical mechanical polishing results in severe deviations in copper interconnect height, and random fluctuations in doping cause variations in device parameters. The process variations make the performances of ICs exhibit significant random fluctuations. The breaks and shorts caused by process defects such as dust may also lead to functional failure of the circuit. Design for yield (DFY) aims to reduce the impact of process defects and process variations on circuit performance via early design effects. In contrast, design for manufacturability (DFM) tends to solve the manufacturing difficulties such as chemical mechanical polishing (CMP) flatness and sub-wavelength lithography that may exist in chip manufacturing through design effects. Technology used in DFY firstly establishes a stochastic model of the process variations and device models consisting of random parameters. Based on these models, the yield estimation and optimization can be realized through circuit simulation. By building the random delay models of the standard cells, the yield estimation and optimization of digital circuits can also be realized. Analog circuits are more sensitive to process variations, and the effects of mismatch have been taken into consideration for a long time. In DFY, it is necessary to further consider the influences of process variations on the designs. Analog circuit designers generally improve the yield of circuits by adding margins or employing the centralized design methodology. In recent years, there exists research on the automatic yield optimization of analog circuits. Cadence’s Virtuoso design environment provides tools such as multi-process corner optimization and yield optimization.

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The DFY methods of digital circuits can be divided into two categories: cornerbased method and statistical method. In nanoscale IC designs, more PVT corners are introduced to improve the yields of the ICs. Synopsys’ IC Compiler and Cadence’s Innovus provide the abilities of corner-based optimizations. The statistical optimization methods are still under development. IBM developed the statistical timing analysis tool and optimized the yields based on the statistical timing analysis. However, statistical methods have not been widely used in the industry. Synopsys and Cadence have also recently released statistical timing analysis tools, and statistical methods may become the trends for the future IC designs. Yield enhancement includes a variety of techniques. Traditionally, it refers to the redundant via insertion and interconnect widening techniques to reduce the failures caused by dust defects. The yield enhancement today also refers to optical proximity correction (OPC), dummy fill insertion for CMP technology, hotspot detection and correction techniques, and various yield optimization techniques. Recently, post-silicon tuning and self-healing techniques have been introduced to improve the yield after fabrication. These methods introduce some tunable cells in the circuits to adjust the bias, the drive capability, and the loads of the circuits. After the circuit is fabricated, according to the actual variations of the circuits, the tunable cells are manually or automatically tuned to improve the performances or yields. Such a design approach can reduce the unnecessary area and power overheads introduced to deal with process variations. DFY is crucial for the design of nanoscale IC. The process variations should be considered in the design stage to improve the yield. As the technology node continues to shrink, design for yield would be more and more difficult and important.

Design for Reliability Negative bias temperature instability (NBTI), hot carrier injection (HCI), electromigration (EM), electrostatic discharge (ESD), and radiation effects have great impacts on the reliability of ICs. Design for reliability (DFR) aims to reduce the impact of these factors on the function and performance of ICs through design effects, which thus improves the reliability of integrated circuits. NBTI effect refers to the drift of the threshold voltage of PMOS. At higher temperature and negative bias, the Si-H bond at the PMOS interface breaks to create interface traps, and the gate oxide traps capture holes, which causes the PMOS threshold voltage (Vt) to drift, resulting in the degradation of the timing and the failures of the circuits. HCI effect is due to the fact that when the source-drain biased voltage of the channel is high, part of the carriers with sufficiently high energy enters the oxide layer, which leads to the variations of the threshold voltages and thus the timing degradations of the circuits. As the feature size of the circuit continues to shrink, the HCI effect becomes more and more significant. In recent years, the reliability problems caused by NBTI and HCI effects have attained more and more attentions. Firstly, it is necessary to establish models of the

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NBTI and HCI effects on threshold voltages. With these models, it is possible to simulate the circuits considering these two effects in the circuit design stage. Extra margins can be introduced to ensure that the circuit can still work under the influences of the two effects. For NBTI, by avoiding the transistor in the critical path operating under a negative bias for a long time, it is possible to mitigate the effects of NBTI. EM effect is another important factor affecting the reliability of the circuit. When the circuit works, current flows through the metal interconnect. Metal atoms will also be transported along with the electron flow. If the current is too large, there are depletion of metal atoms in interconnect and eventually lead to large cracks and even broken with high resistance or open-circuit failures. In reliability design, the currents of critical interconnects are analyzed, and for interconnects with large currents, the interconnect width is increased to alleviate the effect of the EM effect. FinFET (fin field-effect transistor) devices are widely adopted in technology nodes below 22 nm. Compared to conventional planar transistors, the heat generated by FinFET devices cannot be dissipated through the substrate, causing severe selfheating effects. Self-heating can cause reliability problems in FinFET ICs. For example, if the temperature is too high, the electromigration effect will be more serious; likewise, the circuit performance will be degraded. The heating effect of FinFETs is usually mitigated by improving the process and reducing the power consumptions. ESD effect is the main factor that damages the IC via excessive electrical stress. The ESD protection circuit in I/Os provides a current path for electrostatic discharge, which avoids electrostatic current flowing into the chip. ESD effect can be described with [23] machine model (MM), human-body model (HBM), and charged-device model (CDM). The damage can be caused by one more mechanisms described by these ESD models. Ionizing radiation can also cause the instability of the ICs [24]. Ionizing radiation particles will introduce interface trap in MOS, which leads to changes in parameters such as threshold voltage and mobility, thus affecting the performances of the circuits. The failure caused by such long-term radiation is known as the total ionizing dose (TID) effects. The transient current produced by radiation can also cause short-term state inversion of sensitive devices such as SRAM cells, resulting in soft errors. The failure caused by such radiation is known as single-event effect (SEE). Radiation hardened circuits are widely used in military and aerospace fields. For TID effects, processes, devices, circuits, and layouts can be hardened to improve the stability of the circuits. For the soft errors caused by the transient currents produced by the radiation, triple modular redundancy (TMR) design, error correction code, or re-execution after detecting an error could be employed to improve the stability and reliability. For the reliability problems caused by NBTI, HCI, and EM effects, it is more important to establish accurate physical, circuit-level, and cell-level models for simulation. With accurate simulation, the circuits can be optimized. The ESD protection technique is mature. Radiation hardened circuit design is a specialized

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field in reliability design, mainly used in military and aerospace applications. It reduces the influences of radiation and improves circuit reliability through circuit and process improvements and redundancy design techniques.

References 1. X. Hong, W. Liu, J. Bian, VLSI Computer Aided Design Technology (National Defense Industry Press, 1998) ISBN 7-118-01815-5/ tp.300, 1998.6 2. 1666–2011-IEEE Standard for Standard System C Language Reference Manual. (2012). https:// doi.org/10.1109/IEEESTD.2012.6134619 ISBN 978-0-7381-6801-2 3. B.N. Sheehan, TICER: Realizable reduction of extracted RC circuits, in IEEE/ACM International Conference on Computer-Aided Design, 1999, Digest of Technical Papers, (IEEE, 1999), pp. 200–203 4. N. Selvakkumaran, G. Karypis, Multiobjective hypergraph partitioning algorithms for cut and maximum subdomain degree minimization, in IEEE/ACM International Conference on Computer-Aided Design IEEE Computer Society, (2003), p. 726 5. M. Vlach, LU decomposition and forward-backward substitution of recursive bordered block diagonal matrices. Electron. Circuits Syst. IEEE Proc. G 132(1), 24–31 (1985) 6. L. Grigori, J.W. Demmel, X.S. Li, Parallel symbolic factorization for sparse LU with static pivoting. SIAM J. Sci. Comput. 29(3), 1289–1314 (2007) 7. IEEE 1497–2001, IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process (2001). https://doi.org/10.1109/IEEESTD.2001.93359. ISBN 0-7381-3074-5 8. R.E. Bryant, Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. (1986) 9. C. Leonard Berman, L.H. Trevillyan, Functional comparison of logic designs for VLSI circuits, in Proceedings of the Int’l Conf. On Computer-Aided Design, (November 1989) 10. S.Y. Huang, K.T. Cheng, K.C. Chen, C.Y. Huang, F. Brewer, AQUILA: An equivalence checking system for large sequential designs. IEEE Trans. Comput. (May 2000) 11. J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill, Sequential circuit verification using symbolic model checking, in Proceedings of the ACM/IEEE Design Automation Conference, (June 1990) 12. J.P. Roth, Diagnosis of automata failures: A calculus and method. IBM J. Res. Develop. 10(4), 278–291 (1996) 13. P. Goel, An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans. Comput. C-30(3), 215–222 (1981) 14. H. Fujiwara, T. Shimono, On the acceleration of test generation algorithms. IEEE Trans. Comput. C-32(12), 1137–1144 (1983) 15. M. Schulz, Socrates: A highly efficient automatic test pattern generation system. Proc. Int. Test Conf. 7(1), 126–137 (1987) 16. N. Xu, C. Yang, Hybrid simulated annealing algorithm to solve VLSI layout problem. Microelectron. Comput. 23(10), 51–53 (2006) 17. M. Xie, X. Yan, Research on key technologies of chip level multilayer wiring (ZheJiang University, 2006) 18. X. Ma, J. Zhang, P. Wang, Fundamentals of electromagnetic field (Tsinghua University Press, 1995) 19. W. Yu, X. Wang, Advanced field-solver techniques for RC extraction of integrated circuits (Springer, Tsinghua University Press, 2014) 20. C. Ebeling. Gemini II: A second generation layout validation tool, in Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD-88), (November 1988), pp. 322–325

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21. S. Wang, D. Wang, Application of AOCV in multi-voltage design of 28 nm process. China Integr. Circuit 23(8), 43–49 (2014) 22. D. Blaauw et al., Statistical timing analysis: From basic principles to state of the art. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 27(4), 589–607 (2008) 23. D.Y. Hu, C.-Z. Chen, Reliability aspects of advanced IC technologies with ESD and antiradiation capabilities. ECS Trans. 60(1), 1185–1190 (2014) 24. C.-Z. Chen, Y. Sun, D.Y. Hu, H. Wu, Quality Factors of Ionizing Radiation in CMOS Transistor Gate (CSTIC, Shanghai, March 18–19, 2019), https://ieeexplore.ieee.org/document/8755620

Section VI IC Manufacturing and Management Min-Hwa Chi, Nanxiang Chen, Hanming Wu, Haijun Zhao, and Weihai Bu

Introduction The manufacturing of Integrated Circuits (IC) plays an important role in entire IC industry for continuously driving new progresses of Moore’s law, more-than-Moore, and post Moore era. IC manufacturing not only supports circuit design and product development but also supports semiconductor equipment, materials, testing, and packaging industry. This section systematically reviewed all aspects of VLSI manufacturing technology, including technology evolution, Si-device structures and physics, state- of-the-art unit process and module process, and advanced integration technology, including super junction, strained Si engineering, epi source/ drain, immersion lithography, self-aligned dual patterning technique, CMOS with poly-gate and high-k metal gate (HKMG) technology, FinFET, Gate-all-around (GAA), nano-wires and nano-sheet, 3D device, DRAM, 3D NAND, Floating-gate flash memory, PCRAM, RRAM, MRAM, and Design-Technology Co-Optimization (DTCO). This section also summarized non-Si-based devices and ICs (e.g., compound Semiconductor, MEMS, Photonics) as well as heterogeneous integration technology on Si wafers. Furthermore, this section also discussed the state-of-theart management and business models in IC industry.

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Contents Moore’s Law and Technology Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process of Post Moore’s Law Era . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology Roadmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEOL, MOL, and BEOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

The evolution of IC (integrated circuit) manufacturing technology is mainly based on the scaling of semiconductor devices and processes. The technology scaling trend was predicted by the famous Moore’s Law during the past half of century. The IC development no longer closely follows the forecast by Moore’s Law in recent years, so the post-Moore’s Law era begins. The semiconductor industry organizations jointly proposed general technology roadmaps, e.g., ITRS (International Technology Roadmap for Semiconductors) and IRDS (International Roadmap for Devices and Systems). IC manufacturing processes are generally divided into Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL), with Middle-of-Line (MOL) added after high-k metal gate process and eSiGe process were introduced. Keywords

Moore’s law · Post Moore’s law · Scaling · Roadmap · FEOL · MOL · BEOL

W. Bu (*) Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, China e-mail: [email protected] W. Wang SiEn (Qingdao) Integrated Circuit Co., Ltd., Qingdao, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_45

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Moore’s Law and Technology Scaling CMOS technology is continuously scaled down as one of the most important features in the development of IC (integrated circuit) technology. ICs (also called chips) integrate many components and devices together on the wafer using semiconductor planar technology to form specific functions, such as miniaturized (scaled) transistors, resistors, capacitors, inductors, interconnect lines, and other components. ICs are closely related to the process technology and its scaling capability. Technology scaling means that the scaled devices can be fabricated as the advancement of process technology, so that more devices can be integrated on the same chip area. The key parameters such as the line width and spacing in the active areas, gates, contact holes, metal interconnects, etc. in the IC are called feature sizes or critical dimensions (CD). The technology with a set of feature sizes of devices is called a technology node or generation, such as 0.35 μm technology node in the 1990s, 90 nm technology node in the early 2000s, and 10/7 nm technology node in manufacturing at 2019. At different technology nodes, the feature sizes that determine the integration density of ICs are different. In short, the scaling of the feature size leads to greatly enhanced integration density, chip performance, and costs. Therefore, the advancement of IC technology is aimed at scaling device size with improved price/performance; the IC manufacturing technology is increasingly difficult and complicated. Figure 45.1 shows the rapid increase in the number of transistors integrated on a single microprocessor from 1971 to 2017. In 1989, Intel’s CPU 80486 integrated about one million transistors. In 2015, Oracle’s SPARC M7

Fig. 45.1 Increase in the number of transistors integrated on a single microprocessor from 1971 to 2017

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integrated 10 billion transistors [1] in a chip. Technology scaling (or the advancement of IC) over the past 50 years has followed Moore’s Law [2]. Moore’s Law was first proposed in 1965 by Gordon Moore, one of the founders of Fairchild Semiconductor Corp. and Intel Corp. The general statement of Moore’s Law is that, under the assumption of maintaining the lowest unit cost, the number of transistors integrated in an IC doubled every 2 years and also the performance and integration density. Therefore, each technology node of IC is approximately scaled 0.7 linearly and 0.5 in area from the previous node. Moore’s Law forecasts the pace of information technology development and guides the long-term roadmap and R&D targets for IC industry [4]. Although this trend has been going on for more than half a century, Moore’s Law is considered as a predictive observation on the development of IC technology and industry and essentially an economic law. The realization of Moore’s Law enables consumers to continue buying higher performance products at lower prices. From the development of several technology nodes after 22 nm, the pace of IC development appears gradually slowing down than the Moore’s Law. Currently, Intel takes 2.5 years or longer to introduce a new generation of technology. The long-term effectiveness of Moore’s Law is largely related to the progresses of IC manufacturing technology with innovations in new devices, processes, and materials.

Process of Post Moore’s Law Era The post-Moore’s Law era or the post-Moore era refers to the new era that IC industry and technology are facing after Moore’s law “failing” or “slowing down.” In this era, the IC development no longer closely follows the forecast by Moore’s Law. Since Moore’s Law was proposed more than half a century ago, it has been predicted to be failing more than once. However, in actual development, scientists and engineers can keep Moore’s law valid by using innovative new technologies, devices, materials, etc. in IC technology until the technology feature size more and more approaches the physical limit. From recent technology advancement, Intel, as the world leader in IC, took 2.5 years to develop from 22 nm to 14 nm nodes, and it takes 3 years to develop from 14 nm to 10 nm nodes (Fig. 45.2) [3]. After 10 nm node in manufacturing in 2019, Intel’s 7 nm technology node may be in mass production in 2022. TSMC has adopted a more relaxed design rule (than Intel’s) in the definition of new technology node; thus, it appears that TSMC can still maintain the trend of technology development with one node advancement every 2 years. As of 2019, the maturity of EUV lithography scanner is meeting the requirements of advanced manufacturing. If the 193 nm immersion lithography technology continues to be used in advanced technology nodes, one design layer must be divided into three or even four patterning layers. As a result, the difficulty of patterning in the scaled IC technology is greatly increased. Therefore, it is often mentioned that Moore’s Law is about to end or has ended, so that the IC industry is entering the post-Moore era. Moreover, the traditional naming of technology node (e.g., 0.13 μm) was directly related to the feature sizes of devices (e.g., the minimum physical gate length);

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Fig. 45.2 Intel’s IC technology scaling roadmap

however, in the post-Moore era, the definition of the technology node is no longer directly related to any single feature size, but related to the integration density (e.g., doubled with respect to the previous node). The industry has proposed two options in the development of post Moore’s Law, i.e., “More Moore” and “More than Moore.” “More Moore” means that technology scaling continues as Moore’s law with new device structures, processes, and materials introduced. FinFET is expected to be used up to 7 nm node, and 5 nm node, and beyond may introduce the new gate-all-around (GAA) nanowires (NW), nanosheet, or other new 3D devices [3, 4]. The EUV lithography is expected for mass production at 7 nm or 5 nm nodes. “More than Moore” includes developing various advanced technologies for specific applications in post-Moore era (e.g., RF, Memories, Imagers, etc.). The overall integration density and performance of the chip can be further improved while maintaining the cost reduction with 3D monolithic integration and 3D packaging technologies, such as SiP. The Si-based optical interconnects and other non-Si-based new technologies may also be applied for mass production.

Technology Roadmap The technology roadmap refers to the forecast of trend in technology development for a period of time formulated collectively by IC industry-related associations or enterprises. It generally includes the long-term and short-term roadmaps. IC

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manufacturing technology progresses rapidly as a highly complex process, and the industrial segmentation is relatively fine in the industry chain. IC manufacturers need to face many different IC customers, and also implement various equipment, software and raw materials from different vendors in IC industry. In order to ensure that companies in the IC industry maintain a more consistent pace of development compatible with Moore’s Law, the semiconductor industry organizations jointly proposed general technology roadmaps that follow Moore’s Law. Among them, International Technology Roadmap for Semiconductors (ITRS) is the most representative. ITRS mainly elaborates the challenges and possible solutions faced by various technologies in the field of IC from various technical perspectives. It predicts the time of future technology nodes as well as the specific device and process parameters, electrical targets, etc., and various emerging technologies are also summarized. For a long time in the past, ITRS was an important basis and standard for academic research and industrial development. However, in recent years, due to the increasing challenges in the development of IC technologies, leading IC manufacturers are unable to develop products with the pace of ITRS. However, ITRS still plays a role as reference guidelines. The latest edition of ITRS was released in 2015 with forward looking to the technology trends of 2030. ITRS claims that the mode of PC-driven for the performance improvement of microprocessors will gradually be replaced by the new mode of IC development as driven by the smart terminals for artificial intelligence (AI) and Internet-of-Things (IoT). Therefore, ITRS 2015 is called ITRS2.0 because it has been greatly revised compared to ITRS 2013. ITRS 2015 mainly focused on seven sections, i.e., system integration, heterogeneous integration, heterogeneous components, outside system connectivity, more Moore, beyond CMOS, and factory integration. Table 45.1 shows the ITRS2.0 Roadmap (partial). In addition to ITRS, there are other technology roadmaps proposed by other ICindustry-related organizations, such as Nano Electronics Roadmap for Europe and System Device Roadmap Committee of Japan. In 2016, IEEE also developed the International Roadmap for Devices and Systems (IRDS). Moreover, leading IC manufacturers have also launched their own technology roadmaps, though forecasting over shorter time period but to be updated yearly based on technology and market trends.

FEOL, MOL, and BEOL IC manufacturing process is generally divided into Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL). FEOL generally refers to the manufacturing process of devices and mainly includes isolation formation, gate structure, source and drain, contact holes, and so on. BEOL generally refers to the formation of interconnect metal lines used to transmit electrical signals among devices in a chip, such as dielectric deposition, metal lines, and pads formation. Generally, contact holes

18.0 18.0 24.0 18 20

28.0 28.0 35.0 24 26

Half pitch of mx in MPU/SoC Half pitch of M0/M1 in MPU/SoC Half pitch of CPP (contacted poly pitch) Physical gate-length of HP logic tech. Physical gate-length of LP logic tech.

Basic DR of logic device

2017 11 nm/10 nm FinFET FD-SOI

2015 16 nm/14 nm FinFET FD-SOI

Year of mass production Logic tech. node 逻辑器件结构选项

Table 45.1 ITRS2.0 Roadmap (partial) [4, 5]

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formation is regarded as the divider between FEOL and BEOL. Contact holes are formed by patterning (contact holes) and dielectric etching in vertical direction and followed by tungsten (W) filled as W-plug to connect the first metal layer and the transistors. Via is the connection path between two adjacent metal layers, and located in the dielectric layer between the two metal layers, filled with metal, e.g., aluminum (Al), tungsten (W), or copper (Cu). To improve transistor performance, the high dielectric constant (high-k, or HK) gate dielectric and metal gate process (MG) are introduced since 45 nm / 28 nm nodes. Replacement metal gate (RMG) and Local Interconnect (LI) process are added after transistor source/drain formation. These processes are between FEOL and BEOL, and not used in the earlier conventional process, so it is often referred to as Middle-of-Line process (MOL). Generalized IC manufacturing should also include steps such as testing and packaging. Relative to testing and packaging, component and interconnect manufacturing are the first part of IC manufacturing, and collectively referred as Front-End (FE) process, while testing and packaging are referred as Back-End (BE) process. Figure 45.3 illustrates the IC manufacturing process for clearly indicating the FEOL and BEOL as well as the front end and back end of the entire IC manufacturing processes.

Fig. 45.3 Schematic diagram of the manufacturing process of the IC

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References 1. Transistor count. https://en.wikipedia.org/wiki/Transistor_count 2. Moore’s law. https://en.wikipedia.org/wiki/Moore%27s_law 3. A.K. Gundu, V. Kursun, 5-nm GAA transistor technology with 3-D stacked nanosheets. IEEE Trans. Electron Devices 69(3), 922 (2022) 4. S.B. Samavedam, J. Ryckaert, E. Beyne, K. Ronse, N. Horiguchi, Z. Tokei, I. Radu, M.G. Bardon, M.H. Na, A. Spessot, S. Biesemans, Future logic scaling towards atomic channels and deconstructed chips, in IEDM, (2020), pp. 1–10 5. ITRS2.0 Publication. http://www.itrs2.net/itrs-reports.html

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Contents Bipolar Junction Transistor (BJT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fin Field Effect Transistor (FinFET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fully Depleted SOI (FD-SOI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Super Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Laterally Diffused MOSFET(LDMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Passive Devices (IPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

Bulk silicon (Si) substrates and silicon-on-insulator (SOI) substrates are the basic substrate materials for silicon-based ICs. Refer to Sect. 9 of this book for detailed information of polycrystalline Si, single crystal Si, Si wafer with epitaxy, SOI substrate, and testing of Si wafers. Si-based devices are the fundamental components of ICs. Si-based devices mainly include bipolar junction transistor (BJT), MOSFET, FinFET, fully depleted SOI (FD-SOI), super junction (SJ), lateral diffusion MOS (LDMOS), integrated passive device (IPD), etc.

W. Bu (*) Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, China e-mail: [email protected] W. Wang SiEn (Qingdao) Integrated Circuit Co., Ltd., Qingdao, China P. Tang Semiconductor Manufacturing International Corp, Shanghai, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_46

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Keywords

BJT · MOSFET · CMOS · FinFET · Tri-gate · FD-SOI · GAA · Power device · Super junction · LDMOS · Passive device

Bulk Si substrates and Si-on-insulator (SOI) substrates are the basic substrate materials for Si-based ICs. Refer to Sect. 9 of this book for detailed information of preparation of polycrystalline Si (poly-Si), single crystal Si, Si wafer with epitaxy, SOI substrate, and testing of Si wafers. Si-based devices are the fundamentals of IC. Si-based devices mainly include bipolar junction transistor (BJT), MOSFET, FinFET, fully depleted SOI (FD-SOI), super junction (SJ), lateral diffusion MOS (LDMOS), integrated passive device (IPD), etc.

Bipolar Junction Transistor (BJT) Bipolar junction transistor (BJT) is one of the most important devices in the history of IC development. Different from MOS transistors, when bipolar transistors are in operation, both electrons and holes are involved in conduction and referred to as bipolar transistor. As shown in Fig. 46.1, a BJT can be viewed as two back-to-back pn junctions integrated together. Based on different combinations of pn diodes, BJT can be divided into n-p-n and p-n-p types. Taking one n-p-n transistor as an example, the p-doped region is the base (B), and the two n-doped regions on the side of base are the emitter (E) and the collector (C), respectively. When the n-p-n BJT turns on, the emitter junction (i.e., base-emitter) is positively biased, and the collector junction (i.e., base-collector) is reverse biased. The emitter injects electrons into the base region under positive bias. Some of these electrons will be recombined with holes in base as base current, and most of these electrons will be continuously moved toward and collected at the collector under high reverse electric field as collector current. Because the base region is normally thin and low in doping, the captured base current is much smaller than the collector current; this is the amplification principle

Fig. 46.1 Schematic of BJT structure

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of the base current in bipolar transistor. Figure 46.1 illustrates the structures of npn and pnp bipolar transistors (BJT). BJT is a bulk device, where the electrons and holes are transported in the bulk of semiconductor; thus BJT has the characteristics of high trans-conductance, speed, and power consumption. In fact, before the 1970s, most of ICs were designed mainly on bipolar transistors. With integration density increasing, the power consumption and heat dissipation of ICs becomes more and more prominent, and BJT were gradually replaced by MOS transistors mainly due to the much smaller leakage current of MOS transistors. Though currently most ICs are based on CMOS transistors, BJT is still widely used in analog, RF and high-speed, high power circuits as related to its larger current gain, and higher trans-conductance (than MOS transistors).

MOSFET Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most important elements of ICs. Metal, oxide, and semiconductor serve as gate electrode, gate dielectrics, channels, and source/drain in the MOSFET respectively, i.e. the basic MOSFET consists of gate, source, drain and body. The concentration of electrons and holes in the channel region can be controlled to form accumulation, depletion, and inversion by applying the gate voltage. The transistor realizes the switching on/off functions based on these operations. Depending on the types of channel doping, MOSFETs have two types: n-type MOSFET (or nMOSFET, nMOS, n-MOS, or n-FET) and p-type MOSFET (or pMOSFET, pMOS, p-MOS, or p-FET). These MOSFETs are referred to as complementary MOSFET (C-MOSFET or CMOS). The channel of the planar MOSFET is a plane, and the source and drain (source/drain) is self-aligned with respect to the gate with relatively simple fabrication process. After replacing BJTs, planar MOSFETs dominated in the development of ICs. A conventional planar MOSFET has only one gate, and the single-gate device has limited channel controllability. It faces a dilemma in the scaling of IC technology: on the one hand, the short channel effect related to the small channel length is to be suppressed by higher doping in the channel and thinner gate dielectric; on the other hand, the very high channel doping and thin gate dielectric will result in random doping fluctuation effect, gate leakage, channel mobility degradation, and higher noise. The problem of device leakage and performance degradation becomes more and more serious, especially when IC technology progressed to 20 nm technology node and beyond. To enhance the gate-to-channel control, fully depleted SOI MOSFETs and three-dimensional (3D) multi-gate MOSFETs (or FinFET) become replacements for single-gate planar MOSFETs in advanced 14 nm, 10 nm, and 7 nm technology nodes.

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Fin Field Effect Transistor (FinFET) FinFET is a type of 3D multi-gate devices with features of folded thin-fin like channel with surrounded double or triple-gate as shown in Fig. 46.2. Thinner channel and multi-gate electrode can improve the gate control capability of the channel and ensure that the device operates in a fully depleted mode. Compared with planar CMOS devices, FinFET has obvious capability in suppressing the short channel effects, improving device performance, and reducing leakage current due to its 3D fully depleted structure. With the better control of short channel effects, the channel doping of FinFET can be significantly reduced for improving the mobility degradation and random doping fluctuations. The double-gate or tri-gate FinFET can significantly improve the subthreshold slope of the device to be close to 60 mV/decade [1]. On the same Si wafer area, FinFET can result in larger effective channel width for stronger driving capability. FinFET was named in 1999 by the team of Chenming Hu of the University of California, Berkeley [2]. The original concept was named as DELTA (depleted leanchannel transistor) device [3], or tri-gate transistor [4] by Intel Corporation. In the technical literatures, these Fin-based multi-gate devices (whether double-gate or triple-gate) are all referred to as FinFETs. Prior to 2006, the fabrication of FinFETs did not include the source-drain selective epitaxy and strained Si technology, thus the drive current was generally lower (than modern FinFET). Also the discrete nature of fins leads to less flexibility to adjust the channel width for IC designers. Intel’s paper published in 2006 firstly used source-drain epitaxy at source-drain area for strained Si; thereby the mobility is enhanced and contact resistance is reduced. FinFETs can achieve sufficient drive capability with the drive currents of both nMOS and pMOS to more than 1 mA/μm [5]. In addition, IC designers could adjust channel width of FinFETs by using different numbers of fins.

Fig. 46.2 Schematic diagram of two devices

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FinFETs also face many challenges in mass production, e.g., large aspect ratio of fins to be patterned and etched precisely, smooth surface and defect free, fin doping by implants, and damage-free processes post-fin formation,. The non-planar wafer surface due to the fin structure results in challenges in etching and gap filling, sidewall spacer formation, etc. The increase of fin height can result in larger effective channel width, but the parasitic capacitance also increases. The effective channel width as achieved by the number of fins is discrete in nature and less flexible in IC design. FinFET technology was matured in mass production for the first time by Intel at 22 nm node; it is the mainstream technology for IC manufacturing at 16 nm/14 nm nodes and beyond. In 2015, Intel, Samsung, TSMC, and GlobalFoundries were all capable in manufacturing at 16 nm and 14 nm nodes of FinFET technology. As of May 2019, Samsung and TSMC are in volume manufacturing 10 nm and 7 nm FinFET technology. With high mobility channel materials, such as III-V compound materials for nMOS and Ge/SiGe for pMOS, the performance of FinFET can be further improved at 5 nm node. Currently, the most recent progress in gate-all-around [6] and 3D devices [7] are maturing at 3 nm nodes.

Fully Depleted SOI (FD-SOI) Silicon-on-insulator (SOI) wafer is composed of a top Si layer, a buried oxide layer, and a Si substrate. With the development of IC technology, bulk Si substrate CMOS faces many challenges (e.g., latch-up effect, short channel effect, increased leakage current, threshold voltage shift, increased parasitic capacitance, etc.). ICs on SOI substrate (referring to SOI-IC) can suppress the above problems. SOI-ICs have more efficient dielectric isolation between devices; it can completely eliminate the parasitic latch-up effects. The parasitic capacitance and RC delay are reduced, leading to better operation speed. The short channel effect is suppressed with reduced power consumption. Finally, the fabrication of SOI-IC uses less photomask quantity and has simpler process flow (e.g., no need of STI isolation). The SOI devices can be divided into partially depleted SOI (PD-SOI) and fully depleted SOI (FD-SOI) devices according to whether there is a neutral (i.e., not depleted) region in the channel region when the device is in operation, as shown in Fig. 46.3. The top Si layer of the FD-SOI device is thinner, and the Si layer is completely depleted when transistor is in operation. FD-SOI devices eliminate the Kink effect and the parasitic BJT caused by the neutral region. In the meantime, the ultra-thin top Si layer improves gate-to-channel controllability and subthreshold swing, so FD-SOI devices have good short-channel characteristics. Some analysts believe that from 28 nm and 20 nm nodes, cost per single transistor will not fall any more or even increases, based on bulk Si CMOS and FinFET processes. The main supporters of FD-SOI technology (e.g., IBM, STM, GlobalFoundries, etc.) believe that FD-SOI will be more competitive at advanced nodes. FD-SOI technology has certain advantages in low-leakage and low power applications. Based on its excellent gate control capability, FD-SOI technology can

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Fig. 46.3 Schematic diagram of device structure on different substrates

Fig. 46.4 Schematic of SOI FinFET technology

continuously extend the process of planar CMOS. In addition, some companies and research institutes are also studying the FinFET on SOI technology as shown in Fig. 46.4. Compared with bulk Si FinFET, FD-SOI is still a planar structure and the process is easier and lower in manufacturing cost. SOI process is relatively simple, but the SOI substrate material is a little bit more expensive (than bulk) and somewhat limiting the wide applications. The ecological environment of FD-SOI is also a limiting factor as lack of simulation software, design IPs, and design tools than those for bulk Si technology. Therefore, FD-SOI is mainly used for low power and low leakage applications.

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Super Junction Super junction (or super-junction, SJ) is a technology for manufacturing power field effect transistors. Its name first appeared in 1993 [8]. The breakdown voltage of the traditional high-voltage (n-type) power MOSFET is mainly determined by the voltage tolerance of the depletion region of pn junction (i.e., the n-type epitaxial layer and p-type body). The voltage blocking on the depletion region is mainly on the side of n-epitaxial layer as the p-type body region has higher doping. In order to increase the breakdown voltage, one can use lower doping of epitaxial n-layer and larger thickness. However, both the lower doping and thicker film will increase the on-resistance of the power MOS transistor; this leads to increase the power consumption during. Due to the above trade-off, the on-resistance of the conventional high-voltage power MOS transistors is limited by the breakdown voltage referred to as “Si limit” in the industry. In order to break through this limit, academician Chen Xingbi of the Chinese Academy of Sciences and other scientists proposed three methods to improve the structure of the drift layer from 1988 to 1995. These methods are the basis of super junction. Taksuhiko et al. summarized the idea of super junction and proposed the concept of “super-junction theory” in 1997 [9]. Figure 46.5 illustrates a comparison between a conventional power MOSFET and a typical super junction MOSFET [10]. As shown in Fig. 46.5b, the super junction MOSFET is different from conventional power MOSFETs. It has a p-type region deep into the epitaxial n-layer in the vertical direction. The doping concentration of the p-type region is lower than that of the original p-type body. Such device structure can compensate for the charge at n-epi layer and greatly expand the depletion region of the pn junction to the side of the p-type region. The depletion region works as voltage drop layer and relaxes the requirement of breakdown voltage for n-epitaxy. Under the same breakdown

Fig. 46.5 Schematics of two different structures of power MOSFETs

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voltage, the doping concentration of the n-epi layer of the super junction MOSFET can be increased, and the on-resistance can be greatly reduced. Compared with traditional power MOSFET, super junction MOSFET has many advantages (e.g., lower conduction loss, higher drive current capability, lower gate charge, lower turn-on voltage, faster switching speed, more excellent unclamped inductive switching (UIS) capability, and 100% avalanche breakdown test). However, the super junction structure has some problems and defects (e.g., the structure is more complicated and difficult in fabrication process with higher cost; the np composite structure also leads to a worse reverse recovery of the device). For the fabrication process, the main feature of the super junction power MOSFET process is that multiple parallel n-type and p-type composite implant regions need to be formed in the vertical direction, wherein the n-type region and the p-type region have high aspect ratio and high vertical tilt angle (typically 85
–89.5
). These requirements result in more complexity in the process of super junction power MOSFETs. At present, the mainstream super junction power MOSFET process can be divided into two methods; one is multiple ion implantation and epitaxy and the other is deep trench etching and filling technology. In the method of ion implantation, the depth and the high aspect ratio of the super junction n-type region and the p-type region are often not ensured by ion implantation alone; and usually a combination of multiple ion implantations and multiple epitaxial processes are required. The process of implementing a super junction power MOSFET through a deep trench process is to epitaxially grow n-layer on an n þ substrate firstly, then etching to form a deep and steep Si trench, and then epitaxially filling the p-type Si to form a super junction structure. Infineon is the first company in the world to achieve mass production of super junction MOSFETs. Shanghai Huahong Grace Semiconductor Manufacturing Corporation can provide super junction MOSFET foundry service on 200 mm wafers, and there are products with different voltage levels of 500–900 V based on deep trench process. The super junction technology can also be used for IGBTs (insulated gate bipolar transistors).

Laterally Diffused MOSFET(LDMOS) The structure of a conventional LDMOS device is illustrated in Fig. 46.6. The process scheme is briefly described here. The two impurities as doped in the same window region (p-Ext and n þ source) have different diffusion coefficients, doping levels and polarities. After high temperature process, the impurities with larger diffusion coefficient made a longer lateral diffusion (d1 in Fig. 46.6) and form a channel (d1) with gradient concentration. The polarity of the window region is determined by impurities with higher doping concentration, transistor source formed. Generally, LDMOS devices endure a relatively high drain voltage. Reduced surface field (RESURF) technology can improve the breakdown voltage at drain (BVD). By designing drift region (as n-Well in Fig. 46.6) with low doping

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Fig. 46.6 Structure of a traditional LDMOS device

concentration between the channel and drain, width of drain pn junction depletion layer and breakdown voltage can be increased. Factors such as doping concentration of drift region and pn junction depth affect the drain breakdown voltage. Synchronized optimization of device on-resistance (Ron) and breakdown voltage can be achieved by optimizing the doping profile of the drift region or introducing impurities with the opposite polarity in the drift region. For LDMOS devices, proper design of field-plate (FP) (e.g., oxide thickness, field length, and location) can reduce the electric field at the edge of the field plate; this leads to gentle variation of electric field for higher breakdown voltage. The poly-Si gate is shown in Fig. 46.6 with one portion (d2) controlling the turn on and off of the channel and the other portion extending above the field oxide (see d3) as a field plate. The spikes of electric field at the edge of the field plate on surface can be eliminated and thus premature breakdown of the device can be avoided [11]. Shallow trench isolation (STI) or deep trench isolation (DTI) is introduced in advanced IC technology. The drift region and channel can be formed by ion implantation technology instead of relying on the differences in lateral diffusion of the n and p doping. That results in complementary LDMOS possible [12]. Compared with bipolar transistors (BJT), LDMOS transistors have higher gain, better frequency stability and thermal stability, simpler bias circuit, constant input impedance, lower thermal resistance and noise, and better durability. LDMOS is suitable for communication applications with wide frequency range, high linearity, and long service life. LDMOS [13] is widely used due to its excellent process compatibility with CMOS. The schematic diagram of a fully isolated LDMOS device structure and CMOS compatible flow is shown in Fig. 46.7.

Integrated Passive Devices (IPD) Integrated passive devices (IPD) are the passive components (e.g., resistors, inductors, capacitors, transmission lines, power dividers/combiners, and metal interconnects) integrated on a single chip. Its preparation processes are compatible with IC

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Fig. 46.7 Schematic diagram of the process flow with fully isolated LDMOS device compatible with CMOS process

fabrication processes (e.g., thin film, photolithography, and etching). IPD can reduce product size and improve product performance.

Integrated Resistors There are many types of integrated resistors, which can be generally divided into two types: non-metal and metal resistors. Traditionally, the former are commonly used in Si-based IC processes, while the latter in compound semiconductor processes. However, with the development of Si-based IC, especially the introduction of high-k metal gate process, metal resistors can also be a candidate. The non-metal resistors refer to the resistors made of semiconductor material or poly-Si with the resistivity depending on doping level. Based on this, non-metal resistor can be made by using diffusion, ion implantation, and annealing process, where the doping level of the semiconductor material and poly-Si can be tuned. Simultaneously, the desired shape and size of resistor can also be obtained through the layout design. Metal resistor refers to deposit a thin metal film on the dielectric by using evaporation or sputter coating technique and then remove the excess metal by photolithography etching or lift-off process to form proper resistance value. Commonly used metal resistor materials are nickel-chromium (Ni-Cr) alloy, tantalum nitride (TaN), and titanium nitride (TiN).

Integrated Capacitors They are usually divided into metal-oxide-semiconductor (MOS) capacitors, metalinsulator-metal (MIM) capacitors, PN junction capacitors, interdigital structure capacitors, etc., which can be fabricated by semiconductor processes.

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Integrated Inductors There are three types of integrated inductors: the single turn coil, the multi-turn coil, and the transmission line. Among them, the multi-turn coil is divided into the spiral and the angle type. Capacitors and inductors are fabricated by metal deposition, electroplating thickening, and wet or dry etching processes. These process steps are simple but require precise control. High-quality capacitors and inductors play a direct role in filtering, decoupling, and reducing phase noise in matching circuits.

Interconnections Connection of components on the chip can be realized by using interconnection lines. In order to improve the integration of the chip and reduce parasitic effects, the interconnection lines should be as narrow and short as possible under the premise of meeting the current density requirement. Small current interconnect line fabrication should select the minimum line width as provided in the process. A design with long interconnect line should take the delay into consideration. When the operating frequency is in the microwave and millimeter wave (mm-wave) range, the interconnect lines cannot be treated as pure resistors; the effects of parasitic parameters and skin effect need to be considered.

References 1. C.H. Jan, U. Bhattacharya, R. Brain, et al., A 22 nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra-low power, high performance and high density SoC applications, in IEDM 2012: 2012 International Electron Devices Meeting, San Francisco, 10–13 December 2012[C], (IEEE, San Francisco, 2012) 2. X. Huang, W.C. Lee, D. Hisamoto, et al., Sub 50-nm FinFET, in PMOS: IEDM 1999: 1999 International Electron Devices Meeting, Washington, DC, 5–8 December 1999[C], (IEEE, Washington, DC, 1999) 3. D. Hisamoto, T. Kaga, Y. Kawamoto, et al., A fully depleted lean-channel Transistor (DELTA)-a novel vertical ultra-thin SOI MOSFET, in IEDM 1989: 1989 International Technical Digest on Electron Devices Meeting, Washington, DC, 3–6 December 1989[C], (IEEE, Washington, DC, 1989) 4. R. Chau, B. Doyle, J. Kavalieros, et al., Advanced depleted-substrate transistors: Single-gate, double-gate and tri-gate, in SSDM 2002: 2002 International Conference on Solid State Devices and Materials, Nagoya, 17–19 September 2002[C], (The Japan Society of Applied Physics, Nagoya, 2002) 5. J. Kavalieros, B. Doyle, S. Datta, et al., Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering, in VLSI 2006: 2006 Symposium on VLSI Technology, Honolulu, 13–15 June 2006[C], (IEEE, Honolulu, 2006) 6. A.K. Gundu, V. Kursun, 5-nm GAA transistor technology with 3-D stacked nanosheets. IEEE Trans. Electron. Devices 69(3), 922 (2022) 7. S.B. Samavedam, J. Ryckaert, E. Beyne, K. Ronse, N. Horiguchi, Z. Tokei, I. Radu, M.G. Bardon, M.H. Na, A. Spessot, S. Biesemans, Future logic scaling towards atomic channels and deconstructed chips [C] (IEDM, 2020), pp. 1–10

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8. A. Avron, Super junction MOSFET: Analysis and market outlook of next generation silicon power devices [OL]. (2012-11-12) [2017-06-08]. http://www.p-e-china.com/neir.asp? newsid¼14647 9. B. Tian, X. Cheng, B. Kang, The development and application of superjunction theory. Microelectronics 36(1), 75–83 (2006) 10. A. Claudio, M. Cotorogea, J. Macedonio, Comparative analysis of SJ-MOSFET and conventional MOSFET by electrical measurements, in IEEE International Power Electronics Congress, 24 October 2002[C], (IEEE, Guadalajara, 2002) 11. D.G. Lin, S.L. Tu, Y.C. See, et al., A novel LDMOS structure with a step gate oxide, in IEDM 1995, Washington, DC, 10–13 December 1995[C], (IEEE, Washington, DC, 1995) 12. M.R. Duncan, J.M. Robcitson, R.J. Holwill, et al., CMOS-compatible high-voltage complementary LDMOS devices, in ESSDERC 1989, Berlin, 11–14 September 1989[C], (IEEE, Berlin, 1989) 13. M. Li, J.M. Koo, R. Purakh, V018 μm BCD technology platform with performance and cost optimized fully isolated LDMOS, in EDSSC 2015, Singapore, 1–4 June 2015[C], (IEEE, Singapore, 2015)

Compound Semiconductor Device and IC

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Contents Compound Semiconductor Power Devices and Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SiC Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GaN Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Mobility Channel ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III–V CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tunneling FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2D Material for Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si Photonics ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveguides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Photodetectors, Modulators, and Lasers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Frequency Integrated Circuits (RFICs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwave Monolithic Integrated Circuits (MMIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si-MMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GaAs-MMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SiGe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GaN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Abstract

The first generation of semiconductor material is represented by Si and Ge in Group IV, and the second and third generations of semiconductor materials are mainly compound semiconductors (CS), e.g., GaAs and InP (the second generation) as well as GaN and SiC (the third generation of CS materials). Those compound semiconductor (CS)-based discrete devices and ICs have superior M.-H. Chi (*) GTA Semiconductor Co., Ltd., Shanghai, China e-mail: [email protected] Y.-K. Liu · L. Qin Hebei Semiconductor Research Institute, Shijiazhuang, China © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_47

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capability than Si-based discrete devices and ICs; e.g., GaN is suitable for higher operation frequency, SiC for higher operation temperature and voltage, InAs and GaAs capable for light emission, and MoS2 or WSe2 with higher mobility. These CS materials have superior material characteristics than Si, e.g., larger bandgap, direct bandgap for light generation, etc. However, Group III-V or II-VI CS materials are considered as cross-contaminants to Si devices in modern CMOS fab. Also, only small diameter substrate available (e.g., 150 mm in diameter or smaller), thus it is slow and difficult in developing and manufacturing full CS-based devices and ICs. Instead, enabling technology for forming high quality CS material on SOI or bulk Si substrate (with large wafer size or on selective areas) is highly desirable, so that not only the capability of Si-based IC can be expanded, but also accelerating CS-based devices and ICs in manufacturing toward many new applications. Keywords

Compound semiconductor · Power device · SiC · GaN · High-mobility channel · Si photonics · RFIC · MMIC The first generation of semiconductor material is represented by Si and Ge in Group IV, and the second and third generations of semiconductor materials are mainly compound semiconductors (CS), e.g., GaAs and InP for the second generation as well as GaN and SiC for the third-generation CS materials. Those compound semiconductor (CS)-based discrete devices and ICs have superior capability than Si-based discrete devices and ICs; e.g., GaN is suitable for higher operation frequency, SiC for higher operation temperature and voltage, InAs and GaAs capable for light emission, and MoS2 or WSe2 with higher mobility. These CS materials have superior material characteristics than Si, e.g., larger bandgap, direct bandgap for light generation, etc. However, Group III-Vor II-VI CS materials are considered as cross-contaminants to Si devices in modern CMOS fab. Also, only small diameter single crystal substrates are available (e.g., 150 mm in diameter or smaller); thus it is slow and difficult in developing and manufacturing full CS-based devices and ICs. Instead, enabling technology for forming high quality CS material thin-film on SOI or bulk Si substrate (with large wafer size or on selective areas) [1, 2] is highly desirable, so that not only the capability of Si based IC can be expanded, but also accelerating CS-based devices and ICs in manufacturing toward many new applications.

Compound Semiconductor Power Devices and Integration SiC Integrated Circuits SiC has a wide bandgap and widely used in high voltage and high power devices, e.g., discrete power MOSFET and insulated gate bipolar transistor (IGBT). These power devices integrated with digital and analog IC (e.g., gate driver, regulator,

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and configurator) together to form silicon carbide (SiC) ICs for multiple applications, e.g., high-speed railroad, hybrid automobile, battery charger, avionics, and deep-mining machinery and other applications in extreme environments. The development of SiC ICs is limited by the lack of stability and accuracy of fabrication process. In the twenty-first century, semiconductor manufacturing industry has been developing more stable and advanced new technology, which makes the design of SiC mixed signal integrated circuit and more complex digital integrated circuit begin to be realized, e.g., 15 V 1.2 μm CMOS based flow [3] (HiTSIC flow from Raytheon). Common SiC substrate is mainly 400 in diameter (100 ¼ 25.4 mm), some are 600 (i.e., 150 mm). Recent new method [4] shows that vapor-liquid-solid (VLS) method with metal as catalyst can eliminate or reduce dislocation defects significantly; thus, it is possible to grow single crystals (3C-SiC) in selective area on Si substrate.

GaN Integrated Circuits GaN discrete devices have shown superior performance in power switching and microwave/millimeter wave applications. By integrating the power switch and its driver circuit on the same chip, parasitic inductance can be significantly reduced (for better reliability and performance of power ICs) and the cost of assembly and packaging is also reduced as greater advantages. The main difficulty in realizing GaN ICs is in the formation of p-MOSFET; one flow is shown in reference [5]: (a) epi GaN is grown selectively on the same chip for nMOS and pMOS transistors formation. (b) AlN/Si3N4 dielectric layers are grown by MOCVD as gate dielectric of nMOS and pMOS transistors as in Fig. 47.1. GaN single crystal films grown on different substrates (e.g., SiC or Al2O3) can be used to fabricate GaN-based CMOS ICs, but these substrates (SiC or sapphire) are also small in size (400 or 150 mm) and expensive, so it is highly desirable to develop large area (or specific area) growth on Si substrates, e.g., Technology of Hetero-epitaxy GaN Single Crystal Films [6].

High Mobility Channel ICs III–V CMOS Compared with Si materials, germanium silicon (SiGe), germanium (Ge), and III-V compound semiconductor materials have higher mobility [7]. They can be used as channel materials for CMOS for continuous scaling of Si-based CMOS. These materials still face the following challenges: (a) Ge and III-V compounds have higher dielectric constant and smaller bandgap than Si. If they are used as the channel materials in planar CMOS, they will have larger Short Channel Effect (SCE) and leakage current; but those CMOS with FinFET structure can have better gate control over channel and reduce leakage current. At present, Ge, SiGe, and InGaSb all have higher hole mobility and are more suitable as p-type channel

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Fig. 47.1 Illustration of GaN nMOS and pMOS formation on the same sapphire [5]

materials. InGaAs is the first choice for n-channel materials, but there are still many difficulties in optimizing contact resistance, reducing off-state current, improving reliability, and Si integration. (b) In order to avoid the complication of CMOS integration, a single channel material system [8] is much easier for the formation

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of n-type and p-type MOSFETs with good performance. AlGaSb/InGaSb structure is a good choice due to higher electron and hole mobility as related to their energy band structure. (c) The integration process of non-Si materials: large lattice mismatch (such as Ge lattice mismatch about 4%, In 0.53 Ga 0.47 As lattice mismatch about 8%) will produce a large number of lattice defects in the semiconductor layer.

Tunneling FET Compared with traditional MOSFET, the tunneling FET (TFET) [9, 10] has sharper switching characteristics and more suitable for ultra-low power (ULP) circuits. The operation of TFET is based on the band-to-band tunneling (BTBT) mechanism of electrons (as also referred to as gate-induced-drain-leakage (GIDL) current). The simplest device structure is a gate-controlled p-i-n diode (or gated pin diode). TFET devices can be turned off or on by the gate voltage. The off-state current of TFET is usually several orders of magnitude lower than that of traditional MOSFET. The sub-Vt slope (SS) of TFET is smaller (or sharper) than that of traditional MOSFET (60 mV/decade). In the process design of traditional MOSFET circuits, it is necessary to reduce the gate-induced drain current (GIDL) to reduce the off-state current, but in the TFET circuit, the source should enhance the GIDL inter-band tunnel penetration current to enhance the device’s operating current. Therefore, TFET devices can be optimized by selecting semiconductor materials with smaller bandgap, such as InGaAs or GaAsSb, to generate higher BTBT current. Heterostructured TFETs (such as smaller bandgap materials for source and larger bandgap materials for drain) can further optimize device characteristics by band engineering (such as band arrangement of fracture gap and cross gap structures). Complementary TFET technology is needed in logic circuits; where the design of n-TFET is clear, but the design of p-TFET is difficult due to the influence of Fermi degeneracy, which limits the p-TFET to reach a lower sub-Vt slope ( 1 keV)

Fig. 66.9 Basic structure of a high-current ion implanter

be improved with equipping a decelerator, and the energy contamination can be eliminated by electrostatic deflection. The three-dimensional angle parameters of the ion beam can be detected and controlled to achieve a more fully parallel beam. In addition, the beam size can be adjusted by means of focusing lenses for more applications.

High-Energy Ion Implanter At present, a high-energy ion implanter is capable of providing single-charged ions with the energy more than 1 MeV and higher energy near to 3 MeV for multi-charged ions. In high-energy ion implanters, ion acceleration can be achieved by either RF linear accelerator or DC tandem accelerator technology. DC acceleration is a

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Fig. 66.10 Basic structure of a high-energy ion implanter

conventional technology used in most high-current and medium-current ion implanters. This method has the advantage of less energy divergence (less energy contamination), however, it is difficult to achieve a higher ion beam current. The RF linear accelerator technology performs better stability and reliability compared with the DC tandem accelerator technology. Therefore, high-energy ion implanters with the RF linear acceleration design are currently dominant in the market, such as Eaton NV-GSD/HE series. The basic structure of a high-energy ion implanter is shown in Fig. 66.10. High-energy ion implanters usually adopt the RF acceleration design in the highenergy accelerating section. The RF acceleration unit of the high-energy ion implanter is shown in Fig. 66.11. It is mainly composed of a resonator cavity, an inductor, an electrode, and a quad lens to form an Resistance, Inductance, Capacitance (RLC) circuit. Each terminal of the electrode is equipped with one grounded quad lens which can focus ion beams. The electrode is connected with a 13.56 MHz RF power supply. As the ion beam pocket enters to the gap prior to the accelerating electrode, negative voltage biased electrode starts to pull ions into the electrode at an accelerating voltage. While the ion beam is inside the electrode, it feels no electrical field and continuously drifts to the exit terminal, then immediately the positive voltage biased electrode starts to push the ion beam out further at an accelerating voltage so as to form an accelerated ion beam pocket. With a linear sequence of acceleration cavity design, these ion beam pockets are accelerated in each of the cavities in a pull-push fashion to obtain an expected ion energy. High-energy ion implanters perform wide applications in IC fabrication, such as retrograde well, buried layer, and deep junction formation in logic/storage devices, imaging devices, power devices, etc. In addition to completing deep projected range implantation, high-energy implanters can also backup medium-current implanters to implement some processes. The technical parameters of high-energy implanters are shown in Table 66.3.

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Fig. 66.11 Schematic of RF acceleration unit for highenergy ion implanters

Table 66.3 Technical parameters of high-energy implanter (Refer from Zhongkexin Co.) Parameters Wafer diameter Implantation energy Implantation dose Reproducibility and uniformity of implantation dose

Specification 300 mm 20 keV – 3 MeV 1
1011 – 1
1014 ion/cm2 σ  1% (dose: 1
1011 – 5
1011 ion/cm2) σ  0.5% (dose: 5
1011–1
1014 ion/cm2)

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Rapid Thermal Processing (RTP) System The rapid thermal processing (RTP) system is a single-wafer heat treatment system that can quickly ramp up the wafer temperature to the required process temperature levels (200–1300  C) and also cool down the temperature rapidly. The temperature ramp up/ramp down rate is generally in the range of 20  C/s to 250  C/s. In addition to a variety of heating sources and a wide range of annealing times, RTP systems can perform better surface temperature uniformity (mainly for large wafers) and excellent thermal budget control to recover implantation induced crystal damages, especially for IC devices in nanometer scales. Cluster system with multiple chambers can run different processes simultaneously, in which the cluster system can integrate with the photochemical deposition chamber together, such as Photo-CVD, for low temperature film deposition. In addition, RTP systems can convert and adjust process gases flexibly, therefore, multi-stage heat treatment processes can be sequentially completed in the same system [1, 2]. Rapid thermal annealing (RTA) system is the right equipment for postimplantation annealing in advanced IC fabrication. After ion implantation, the surface crystal structure of semiconductors is damaged by the ion bombardment. Therefore, a high temperature process is required to repair the damaged crystal structure and activate dopants to enhance the conductivity, meanwhile, also to suppress the dopant diffusion. In general, the required temperature to repair lattice defects is about 500  C, while the temperature to activate dopants is about 950  C. Obviously, the RTA system can provide enough high temperature level to activate implanted dopants and keep a suitable short heat treatment duration to suppress the dopant redistribution, because the RTA system has advantages of a rapid temperature raise/drop capability and the controllable short process duration. RTA is mainly divided into the following four categories. 1. Spike annealing: This process is characterized by a rapid ramp up/ramp down in temperature. In practical applications, the wafer temperature rises rapidly from a stable standby temperature to a peak temperature and immediately drops after reaching the peak temperature. It has been found that the activation energy of annealing (about 5 eV) is higher than that of diffusion (3–4 eV), therefore, the annealing process is faster than the diffusion process at the temperature over 1000  C. That is, spike annealing is suitable to maximize the dopant activation at the peak temperature over 1000  C and minimize the redistribution of dopant by a very short peak time (much less than 1 s) to meet the requirement of advanced IC products. Spike annealing has demonstrated a good capability to repair implantation-induced defects and led to better junction quality with lower leakage current. Currently, spike annealing is widely used in ultra-shallow junction processes for the technology node less than 65 nm. The process parameters of spike annealing mainly include peak temperature, peak residence time, temperature spread, and the resistivity of wafer. For peak residence time, the shorter, the better. This parameter mainly depends on the temperature ramp up/ramp down rate determined by the temperature control

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system. In addition, the selected process gas atmosphere in chamber sometimes has a certain impact on the ramp profile of temperatures. For example, helium with a higher diffusion coefficient can facilitate a uniform heat transfer on wafer and then reduce the peak residence time. Therefore, helium is sometimes selected to assist in heating and cooling. 2. Lamp annealing: Lamp annealing technology has been widely used in sub-0.1 μm IC fabrication. As shown in Fig. 66.12, the tungsten-halogen lamp is used as a heating element which can generate intensive heat flow for rapid thermal annealing. The lamp array allows wafers to be uniformly heated by the infrared radiation. Usually, temperature ramp rate is about 75–150  C/sec, thus the ramp up time of a lamp RTP system to reach the required annealing temperatures of 1000–1150  C is less than 10 s, and the ramp down time is very short by turning lamps off. For the technology node above 65 nm, the lamp array RTP system can achieve the junction annealing with minimized dopant redistribution. 3. Laser annealing: For the 45 nm technology node, laser annealing is performed instead of lamp RTP system. Such as the formation of nickel-silicon contacts for post-45 nm LSI logic chips, it requires a rapid heating for wafers from 200  C to over 1000  C in milliseconds. That is, a laser is applied to rapidly raise the surface temperature of the Si wafer to its sub-melting point so as to highly activate implanted dopants, and then cool down the wafer surface very quickly, in about a tenth of a millisecond, to minimize the dopant redistribution because of the high thermal conductivity of silicon. The advantages of laser annealing are that it is capable of an extremely rapid ramp up in temperature, sensitive control, and no filament heating requirement. Basically, there is no temperature hysteresis issue or filament lifetime issue. However, from the technical point of view, laser annealing still has problems with high leakage current and residual defects in devices, so the laser annealing technology affects the device performance yet. 4. Flash annealing: Flash annealing is an annealing technology for applications of ultra-shallow junctions, in which it uses high-intensity radiation to perform spike annealing on a wafer at a specific preheating temperature of a range from 600  C to 800  C. This high-intensity radiation performs a short pulsed illumination to ramp up the wafer peak temperature reaching the desired annealing temperature to achieve the dopant activation, and then the radiation is immediately turned off to minimize the dopant redistribution. The core technologies of RTP equipment mainly include the design of the reaction chamber (including the heating source), temperature monitoring technology, and temperature control technology. In RTP equipment, most of the heat is transmitted to cover the wafer by means of radiation. The main radiant energy sources currently used include tungsten halogen lamps, arc lamps, conventional resistive heat sources (which are seldom used), lasers, and microwaves, in which tungsten halogen lamps are the most commonly used heating elements because of their low cost and long service lifetime. In addition, according to the process performed, RTP reaction chambers can be divided into three types, namely, cold wall, warm wall, and hot wall types.

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Fig. 66.12 Basic structural diagram of the reaction chamber in an RTP system

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Lamp sets (the power of a single tungsten halogen lamp is 1–2 kW and that of an arc lamp is tens of kW) are commonly used as the heating source in RTP system. The design of lamp houses either in array shape shown in Fig. 66.12b or in honeycomb structure shown in Fig. 66.12c significantly affects the temperature uniformity on wafer surface [2]. Meanwhile, the reaction chamber design includes the size, the shape, and the cooling form is also crucial to the performance of the heating system. Because the wafer is circular and the interior of the reaction chamber is mostly symmetrical (round shape or hexagonal shape), therefore, the arranged form of lamp houses is usually in concentric circles. In addition, the lamp houses are divided into several individual zones arranged by different radius, in which each individual zone connects an adjustable power controller to optimize the radiation exposure for the uniform temperature distribution across the wafer. In order to increase the heat radiation efficiency and compensate the significant heat loss near the outer edge of the wafer, usually, the lamp houses above outer edge of the wafer are closer to the wafer than those above the inner area of the wafer. The accuracy and uniformity of temperature across wafer in RTP system significantly affects the process yield. Typically, the temperature measurement in RTP system relies on thermocouples and pyrometers. Thermocouple is a direct contact sensor which is not suitable to measure the wafer temperature in an RTP system. Instead, non-contact type sensors, such as pyrometers, usually are applied to monitor the wafer temperature and feedback signals to adjust the heating power to achieve a uniform process temperature across the wafer. Here, thermocouple can serve as a reference to calibrate other temperature sensors, for example, pyrometers. Heating sources, the arrangement of heating elements, chamber design, materials applied for chamber and parts, power supply, position of pyrometers, feedback circuit design, process gases, dissipation of heat flow, wafer sizes, etc., all are main factors related to the temperature control technology. It is necessary to establish an accurate mathematical model through lots of experimental data for the temperature control unit. With the modified simulation model and the continuous experimental implementation, the optimal temperature control design will be achieved. Figure 66.12 shows the basic structure of the reaction chamber in an RTP system. RTP equipment gradually plays an important role in the field of advanced IC fabrication. In addition to a large number of applications in RTA processes, RTP equipment is also applied in rapid thermal oxidation (RTO), rapid thermal nitridation (RTN), rapid thermal diffusion (RTD), rapid thermal chemical vapor deposition (RTCVD), decoupled plasma nitridation (DPN), metal silicide formation, epitaxy, and other processes, etc.

References 1. H. Xiao, Introduction to Semiconductor Manufacturing Technology (SPIE, 2012) 2. M. Quirk, J. Serda, Semiconductor Manufacturing Technology (Prentice-Hall, Inc, 2001) 3. B.E. Deal, A.S. Grove, J. Appl. Phys. 36, 3770 (1965) 4. A.S. Grove, Physics and Technology of Semiconductor Devices (Wiley, New York, 1967)

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5. R.J. Zato, N.O. Korolkoff, S. Marshall, Solid State Technol. 22(7), 62 (1979) 6. L.E. Katz, B.F. Howells, L.A. Adda, T. Thompson, D. Carlson, Solid State Technol. 24(12), 87 (1981) 7. I. Chavet, R. Bernas, Nucl. Instrum. Methods 51, 77 (1967) 8. N.R. White, M. Sieradzki, S. Satoh, Nucl. Instrum. Methods B96, 445 (1995) 9. J.H. Feeman, Nucl. Instrum. Methods B74, 357 (1993)

Thin Film Growth Equipment

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Yang Xia, Peijun Ding, Jinrong Zhao, Bin Yin, and Xiaoping Shi

Contents Principles of Thin Film Growth and Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Vapor Deposition (PVD) Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chemical Vapor Deposition (CVD) and Epitaxy Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vacuum Evaporator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Current Physical Vapor Deposition (DCPVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Frequency Physical Vapor Deposition (RFPVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magnetron Physical Vapor Deposition (Magnetron-PVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . Ionized Physical Vapor Deposition (Ionized-PVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Atmospheric Pressure Chemical Vapor Deposition (APCVD) System . . . . . . . . . . . . . . . . . . . . . . . Low-Pressure Chemical Vapor Deposition (LPCVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plasma-Enhanced Chemical Vapor Deposition (PECVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Plasma Chemical Vapor Deposition (HDP-CVD) System . . . . . . . . . . . . . . . . . . . . . Metal Chemical Vapor Deposition (Metal-CVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Atomic Layer Deposition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Photo Chemical Vapor Deposition (Photo-CVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Laser-Assisted Chemical Vapor Deposition (LA-CVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electron Cyclotron Resonance CVD (ECR-CVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal Organic Chemical Vapor Deposition (MOCVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Molecular Beam Epitaxy System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vapor Phase Epitaxy (VPE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Liquid Phase Epitaxy (LPE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chemical Beam Epitaxy (CBE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ion Beam Epitaxy (IBE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Energy Ion Beam Epitaxy (LE-IBE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Y. Xia (*) · B. Yin Institute of Microelectronics, Chinese Academy of Sciences (IME), Beijing, China e-mail: [email protected] P. Ding · J. Zhao · X. Shi Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China e-mail: [email protected] © Publishing House of Electronics Industry 2024 Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry, https://doi.org/10.1007/978-981-99-2836-1_67

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Spin Coater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439

Abstract

Film growth equipment is one of the critical aspects in the manufacturing process of integrated circuits. It directly affects the properties of thin film materials such as consistency and dimensional accuracy. This section describes the basic principles of film growth and equipment techniques, including physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxy system, and spin coater. The context presents a comprehensive and in-depth introduction of the various subtechnology of mainstream principles and an overview of the film growth equipment system as well. Keywords

Thin film · Nanometer structure · High K · Low K · Deposition · Epitaxy · Sputter

Principles of Thin Film Growth and Equipment The process to deposit a single-crystalline, or poly-crystalline, or amorphous substance on the substrate surface by either physical or chemical technology is called thin film growth (or thin film deposition), which emerged in the 1960s and is one of the critical processes of IC fabrication. It is also an important technical foundation for electronic, information, sensor, optic, solar energy, and other technologies. Based on different deposition mechanisms, thin film deposition in IC fabrication can be divided into physical vapor deposition (PVD), chemical vapor deposition (CVD), and epitaxy. Table 67.1 classifies different film deposition methods. Table 67.1 Classification of film preparation methods Physical process

Chemical process Chemical vapor Sputtering Evaporation deposition (CVD) DCPVD Vacuum APCVD RFPVD evaporation LPCVD Magnetron PVD Electron beam PECVD Ionized PVD evaporation MCVD Photon CVD Laser-enhanced CVD ECR-CVD

Atomic layer deposition (ALD) Epitaxy process Atomic layer Molecular beam deposition (ALD) epitaxy (MBE) Vapor phase epitaxy (VPE) Liquid phase epitaxy (LPE) Chemical beam epitaxy (CBE) Ion beam epitaxy (IBE) Low energy IBE (LEIBE) MOCVD

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In the micron-scale technology nodes, the configuration of CVD normally adopts the multiwafer atmospheric pressure chemical vapor deposition (APCVD) technology with a relatively simple equipment structure to implement the film growth. The process pressure of APCVD system is about 1 atm. To assemble a conveyor belt in the APCVD system, it can implement a continuous wafer transfer and a continuous deposition process. With the increase in wafer sizes, the single-wafer processing chamber has become dominant. To this end, Applied Materials first introduced the 150 mm single-wafer chamber equipment, that is P5000 CVD system, which has been placed on permanent display in the American Museum of Natural History as an epochal milestone. As the wafer size keeps increasing to 200 mm and 300 mm, IC technology continuously keeps updating. In the submicron technology generation, low-pressure chemical vapor deposition (LPCVD) systems have become the mainstream equipment. A lower process pressure is applied to speed the reactant gas flow in the reaction chamber, thereby improving the uniformity of the deposited film as well as the capability of step coverage and gap-refilling. Meanwhile, plasmaenhanced chemical vapor deposition (PECVD) technology has played an important role in the development of IC technology up to the 90 nm node. Due to the effect of the plasma, the chemical reaction temperature is significantly reduced, the purity of the film is improved, and the film density is enhanced. CVD technology is applied not only for the deposition of dielectric layers and semiconductor materials, but also for various metal film deposition. Since the 65 nm technology generation era, based on silicon epitaxial technology, the selective SiGe epitaxy process has been used in the raised S/D structures to improve the hole mobility of PMOS. In addition, new high-k gate dielectrics and metal gate processes have been applied in 45 nm technology nodes to reduce the gate leakage current of MOS devices. And due to the requirement of ultra-thin thickness for films in 22 nm nodes and below, atomic layer deposition (ALD) process equipment has also been developed to meet the requirements for the ultra-thin film deposition with precise composition control and uniform film thickness. In the 150 mm wafer era, physical vapor deposition (PVD) equipment is dominated by the single-wafer chamber configuration. From the perspective of IC technology development, the requirements for deposit films are more uniform and denser, strong adhesion onto the substrate, and higher purity, therefore, the adoption of sputtering equipment has gradually replaced that of vacuum evaporators. With the development of IC technology generations, PVD equipment must be capable to deposit a uniform flat film as well as to implement a better step coverage on vias and trenches of certain aspect ratios. Thus, this development of thin film deposition processes has required that the operational pressure of PVD chamber be reduced from several millitorrs to the sub-millitorr range or increased to tens of millitorrs. And with the long-throw design concept, the distance between the target material and the wafer has also been significantly increased. These mentioned requirements have been specified in the configuration of equipment development, such as magnetron PVD equipment, radio frequency (RF) PVD equipment, and ionized PVD equipment, etc. In addition to DC power sources, magnetron PVD equipment also assembles RF sources to reduce the incident particle energy, thereby reducing the

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device damage on wafer. The newly developed ionized PVD technology has been widely applied in copper interconnection and metal gate deposition. This ionized PVD equipment assembles an auxiliary magnetic field on the backside of target to enhance the plasma density and the sputtering rate, an auxiliary RF power source inside the chamber to convert metal atoms into metal ions, and a collimator to filter scattered metal atoms and ions. In addition to the heating or cooling function, the wafer susceptor connected to a negative bias RF power source can perform the resputtering to eliminate overhangs and bottom thinning of high aspect ratio structures. These ionized PVD chambers also tend to combine with MCVD and ALD chambers to implement the PVD film deposition and the CVD film growth in the cluster system. Table 67.2 lists the configurations and characteristics of the reaction chambers of thin film deposition equipment (data in the table refer to normal process conditions). Thin film growth has to take into account both the performance and the cost of ownership for each deposition equipment. Table 67.3 lists the main evaluation indicators for thin film deposition equipment, and Table 67.4 lists the processes in which thin film growth equipment is adopted in IC manufacturing. In addition to the field of IC manufacturing, thin film growth is also widely applied in advanced packaging, LED manufacturing, MEMS manufacturing, etc. Many new challenges have emerged in the process development of the thin film deposition. Therefore, the development of the thin film deposition equipment will mainly focus on the following directions in the future. 1. The emergence of various new materials promotes the requirements in the R&D of new equipment and processes. 2. More stringent thermal budget control in device fabrication requires developing much lower temperature processes for the thin film growth. 3. The emergence of more complex 3D structures in devices requires the deposition equipment to provide better capability for film step coverage, void-free gap-filling, and more precise film thickness control in thin film growth processes. 4. In order to control the characteristics of film interface so as to obtain a better device performance, it requires a higher level of system integration to form a cluster equipment which can completely implement a set of processes for one application module. For example, to implement the PECVD SixNy or SixCyNz deposition with a subsequential low-k dielectric deposition in a cluster thin film equipment, the metal film deposition of Ti/TiN/Wseed/Wbulk structure for the contactor metal of device in a PVD/CVD cluster equipment, the thin film etching with a subsequential photoresist removal in a cluster etching equipment, etc. In order to meet as mentioned requirements and challenges, manufacturers of thin film deposition equipment need to continuously introduce or develop new technologies. These new developments include the introduction of new magnetic films for new magnetic storage devices, as well as the introduction of MoS2 and WS2 and other new substrate materials for new 2D devices. The deposition of these new materials requires more R&D for new equipment and processes. Furthermore, in the

Low pressure, 0.1–10 Torr

MCVD equipment

Gaseous precursor

Low temp. growth