Grounds for Grounding. A Handbook from Circuits to Systems 9781119770930

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Grounds for Grounding

IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Sarah Spurgeon, Editor in Chief Jon Alti Benediktsson Anjan Bose Adam Drobot Peter (Yong) Lian

Andreas Molisch Saeid Nahavandi Jeffrey Reed Thomas Robertazzi

Diomidis Spinellis Ahmet Murat Tekalp

Grounds for Grounding A Handbook from Circuits to Systems

Second Edition Elya B. Joffe and Kai-Sang Lock

Copyright © 2023 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. Edition History John Wiley & Sons Ltd (1e, 2010) No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission. Trademarks: Wiley and the Wiley logo are trademarks or registered trademarks of John Wiley & Sons, Inc. and/or its affiliates in the United States and other countries and may not be used without written permission. All other trademarks are the property of their respective owners. John Wiley & Sons, Inc. is not associated with any product or vendor mentioned in this book. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representation or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Further, readers should be aware that websites listed in this work may have changed or disappeared between when this work was written and when it is read. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print, however, may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data Applied for: Hardback ISBN: 9781119770930 Cover Design: Wiley Cover Image: © Turki Alshaber/500px/Gettyimages Set in 9.5/12.5pt STIXTwoText by Straive, Pondicherry, India

To my beloved wife, Anat, to the apple of my eye, our daughter Tami-Lee, to our treasured son-in-law, Roni, who are the center of my universe and… to the youngest member of our Family, our first grandson, Dekel (meaning “palm tree”), born July 30, 2021. Advice from a palm tree: Reach High. Stand Tall and Proud. Soak Up the Sun. Be Flexible. Find Your Oasis. Weather Life’s Storms — Elya B. Joffe To my wife, Eyan, and Angela, Andrew, and Anthony for their love, support, and understanding — Kai-Sang Lock To the Beloved Memory of my mother, Faiga Mary Joffe (nee Bloom), my father, Harry Joe Joffe, my father-in-law, Naftali Herman Shafrir (Steiger), and my mother-in-law, Hanna Shafrir (nee Bauman). Their love for education lives on through me and my Family Love has motivated me, faith has activated me, the power of God has accelerated me, and wisdom has provided the navigation on my journey.

Faiga Mary Joffe (nee Bloom) 1934–1984

Harry Joe Joffe 1930–2016

Prof. Naftali Herman Shafrir (Steiger) 1919–2019

Hanna Shafrir (nee Bauman) 1930–2022

Do not let your fire go out, spark by irreplaceable spark in the hopeless swamps of the not-quite, the not-yet, and the notat-all. Do not let the hero in your soul perish in lonely frustration for the life you deserved and have never been able to reach. The world you desire can be won. It exists. it is real. it is possible. it’s yours. — Ayn Rand, Atlas Shrugged If it wasn’t for our parents, none of us would be where we are today. Although we may not always see eye-to-eye, the love and wisdom they instilled upon us is something that can never be forgotten. This book is dedicated to the beloved memory of my mother, Faiga Mary Joffe, who was taken to be with the Lord in 1984, when she was only 50 years old, to my father, Harry Joe Joffe, who passed to the Eternal East in 2016, aged 86, to my father-in-law, Prof. Naftali Herman Shafrir (Steiger), who passed away in 2019, aged 100 (less 19 days), and to my mother-in-law, Hanna Shafrir, who passed away in 2022, aged 91. Their reassurance and attitude were a source of inspiration and motivation that gave me the encouragement and drive to write this book and now, restart and complete its second edition.

May this Second Edition of the Book be their Epitaph. Thank you, my beloved parents and parents in-law, for being there when I needed you so badly. I am so saddened that you do not see the outcomes of your teachings. Your loving son and son-in-law Elya B. Joffe

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Contents Author Biographies xxi Foreword xxiii Preface to the Second Edition Acknowledgments xxvii

xxv

1

Overview 1 References 7

2 2.1 2.1.1 2.1.1.1 2.1.1.2 2.1.1.3 2.1.1.4 2.1.2 2.1.2.1 2.1.2.2 2.1.2.3 2.1.2.4 2.1.2.5 2.1.2.6 2.1.2.7 2.1.2.8 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5

Fundamental Concepts 9 Maxwell’s Equations Demystified 9 Fundamental Terms 11 Electric Charge 11 Conservation of Charge and the Continuity Equation 11 Electric and Magnetic Forces and Fields 12 Biot–Savart Law 13 Maxwell’s Equations 13 Gauss’s Law for Electric Field 15 Gauss’s Law for Magnetic Field 16 Faraday’s Law of Induction 16 Ampere’s Law 18 Impressed and Conduction Currents 21 Constitutive Relations 21 Divergence-Free (Solenoidal Vector) Fields 22 Curl-Free (Conservative) Fields 24 Boundary Conditions 27 Intrinsic Inductance of Conductors and Interconnects 28 Concept of Inductance 28 Self-Inductance 29 Mutual Inductance 31 Partial Inductance 32 External and Internal Inductance 36 Conductors as Materials 37 Skin Effect and Skin Depth 38 Proximity Effect 43 Nonideal Properties of Passive Circuit Components and Interconnects 47 “Real-World” Resistors 49 “Real-World” Capacitors 50 Antiresonance of Parallel (Nonideal) Capacitors 52 “Real-World” Inductors 55 Interconnects (Wires and PCB Traces) 56 Return Current Path Impedance 57 How Current Flows 58 What Path Should Return Currents Follow? 58 Is the Shortest Path Always the Best? 60 What If Alternate Paths Are Available? 60 Equivalent Circuit Analysis 62

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2.5.5.1 2.5.5.2 2.5.5.3 2.5.5.4 2.5.5.5 2.5.5.6 2.5.5.7 2.5.6 2.5.6.1 2.5.6.2 2.5.6.3 2.5.6.4 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.8 2.8.1 2.8.2 2.8.2.1 2.8.2.2 2.8.2.3 2.8.2.4 2.8.2.5 2.8.3 2.8.4 2.8.5 2.8.5.1 2.8.5.2 2.8.5.3 2.8.5.4 2.8.5.5 2.9 2.9.1 2.9.1.1 2.9.1.2 2.9.2 2.9.3 2.10 2.10.1 2.10.2 2.10.3

Return Current Path at Low Frequencies 63 Return Current Path at High Frequencies 64 Return Current Flow in Inductive Return Paths 64 When is Inductance Minimized? 65 Physical Generalization of the Path of Least Impedance Principle 66 Return Current Path, Conclusion 69 Experimental Validation for the Path of Least Inductance Principle 69 Implication of the Principle 71 Signal Current Return Path on PCBs 71 Signal Current Return Path in Coaxial Cables 71 Signal Current Return Path in Flat (Ribbon) Cables 72 Signal Current Return Path in Twisted Wire Pairs 73 Spectral Content of Signals 73 Radiation Efficiency and Electrical Length 74 Periodic Pulsed Signals 74 Random (Aperiodic) Pulsed Signals 77 Effect of Ringing on the Spectrum of Pulsed Signals 78 Spectrum Conservation 81 Transmission Line Fundamentals 84 Transmission Line Definition 84 Transmission Line Equations and Intrinsic Parameters 84 The Dual View of Signals and Interconnects 86 Transmission Line Termination and Loading Conditions 87 Modes of Signal Propagation 91 Differential-Mode and Common-Mode Signals 91 Common-Mode Interference-Generation Mechanism and Its Mitigation 93 CM Generation Due to “Ground Loops” 94 CM Generation Due to Imbalance in Differential Drivers 95 CM Generation Due to Induction and Coupling 96 CM Generation Due to Signal Skew in Differential Conductors 96 Mitigation of Common-Mode Interference Generation 97 Differential Signaling and Balanced Circuits 98 Common-Mode (CM) to Differential-Mode (DM) Conversion 106 Even- and Odd-Mode Impedances 109 Characteristic Impedance of a Single, Isolated Line 111 Differential Impedance 112 Common Impedance 113 Odd- and Even-Mode Impedance 113 Generalizing Z0, Zodd, and Zeven Relationship 115 Interaction Between Sources to Radiated Fields 118 Radiation from Current-Carrying Conductors 118 DM Current Sources (Small Magnetic Loops) 119 CM Current Sources (Small Electric Dipoles) 120 Flux Cancellation, the Electromagnetics of Balancing 122 Not all Common-Mode Currents are Bad … 125 Out of Band Susceptibility in Solid-state Devices 126 RFI Rectification Mechanism in p–n Junctions 126 Digital and Linear IC Interference Susceptibility 129 Susceptibility of Op-Amps to Ground-Coupled EMI 132 References 135

3 3.1 3.1.1 3.1.2 3.1.3 3.1.4

The Grounds for Grounding 137 Grounding, an Introduction 137 “Grounding,” One Term, Many Imports 137 The Grounding Symbol – Adding to the Confusion 141 Grounding—A Historical Perspective and the Evolution of the Term 144 Grounding-Related Myths, Misconceptions, and Misapprehensions vs. Facts and Sensible Choices

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Myth – Current Goes to Ground 147 Myth – Grounding Brings Everything to Zero Potential, Reducing Touch and Step Voltage to a Safe Value 148 Myth – To Be Safe, Add More Earth Electrodes 148 Myth – Earth Electrodes Keep Us from Getting Shocked 149 Myth – Transient Current in the Grounding Conductors May Introduce Errors in Data Transmission Between Interconnected Equipment 149 3.1.4.6 Myth – Different Currents Should Flow Through Separate Paths 150 3.1.4.7 Myth – Electricity (Only) Takes the Path of Least Resistance 151 3.1.4.8 Myth – Common, Ground, and Neutral Are Equivalent 151 3.1.4.9 Myth – It Is Advisable to Tie Neutral and Ground Together in Multiple Places 151 3.1.4.10 Myth – Single Point Ground Is Necessary 151 3.1.4.11 Myth – for the Sake of Best Equipment Performance, Safety Regulations May Be Compromised 151 3.2 Objectives of Grounding 152 3.2.1 Electrical Safety Grounding 153 3.2.1.1 Grounding for Preclusion of Power Fault Hazards 153 3.2.1.2 Lightning Protection System (LPS) Grounding 161 3.2.2 Grounding for Control of Electromagnetic Interference (EMI) 163 3.2.2.1 Controlled Path for EMI Current 163 3.2.2.2 Image Plane 164 3.2.3 Signal Grounding 166 3.2.3.1 Signal Reference Grounding 166 3.2.3.2 Signal Current Return Path 168 3.2.4 Summary of Grounding Objectives 169 References 170

3.1.4.1 3.1.4.2 3.1.4.3 3.1.4.4 3.1.4.5

4 4.1 4.1.1 4.1.2 4.1.3 4.1.3.1 4.1.3.2 4.1.3.3 4.2 4.2.1 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.2.4 4.2.2.5 4.2.3 4.2.3.1 4.2.3.2 4.2.3.3 4.2.3.4 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8

Fundamentals of Grounding Design 171 Ground-Coupled Interference and Its Preclusion 171 Grounding May Not Be the Solution; Rather, it is Part of the Problem 171 The Good Earth 174 Controlling Common-Impedance Interference Coupling 176 Lowering the Impedance of the Common Return Path 177 Precluding Common Current-Return Paths 184 Designing Noise-Tolerant Circuits 186 Fundamental Grounding Schemes 186 The Need for Different Schemes 186 Fundamental Grounding Schemes 189 Floating Scheme 189 Single-Point Grounding Scheme 190 Multipoint Grounding (MPG) Scheme 197 Composite (Hybrid) Grounding Scheme 201 Frequency-Selective Grounding 204 Grounding Schemes in Complex Systems 208 Distributed Single-Point Grounding 208 “Soft” Grounding 209 “Tree” Grounding 212 “Nested” Grounding 212 Grounding Trees 213 Objectives and Basic Design Considerations 213 Ground Tree Design Methodology 214 Step 1: Identify System Architecture 214 Step 2: Define Chassis Connections at the Circuit/Module Level 215 Step 3: Define Subassembly Signal Returns’ (Ground) Requirements 215 Step 4: Identify Chassis Isolation/Connection Requirements in Subassemblies 216 Step 5: Define Common Grounding Point (CGP) Location 216 Step 6: Determine Return Conductors Connections from the Circuits to the CGP 218 Step 7: Identify Potential Ground Loops 218 Step 8: Consider “Special Cases” Potentially Leading to Violation of the Grounding Scheme

220

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4.3.2.9 4.3.2.10 4.3.2.11 4.3.2.12 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.5 4.5.1 4.5.2 4.5.2.1 4.5.2.2 4.5.3 4.5.3.1 4.5.3.2 4.5.3.3 4.5.4 4.5.4.1 4.5.4.2 4.5.4.3 4.5.5 4.5.5.1 4.5.5.2 4.5.5.3 4.5.5.4 4.5.5.5 4.5.5.6 4.5.5.7 4.5.5.8 4.5.5.9 4.5.5.10 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.7 4.7.1 4.7.2 4.7.3 4.7.3.1 4.7.3.2 4.7.3.3 4.7.4 4.8 4.8.1 4.8.2 4.8.3 4.9 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6

Step 9: Incorporate “Isolation Measures” for Preclusion of Undesired Ground Loops 220 Step 10: Sketch the “Grounding Tree” 221 Step 11: Consider Intra-Circuit Grounding Scheme 222 Step 12: Define the Power Supply Outputs’ Specification 223 Role of Isolated Switch-Mode Power Supplies in Grounding System Design 223 Principle of Switch-Mode Power Supply Operation 224 The Need for Isolation in Switch-Mode Power Supplies 227 Isolation and Grounding in Switch-Mode Power Supplies 230 Isolation Requirements and Testing 232 Ground Loops 234 Definition of a “Ground Loop” 235 “Who’s Afraid of the Big Bad Loop?,” or – Ground Loop Consequences 239 Why Are Ground Loops a Problem? 239 When Are Ground Loops Not a Problem? 240 Ground Loop Interference Coupling Mechanisms 240 Coupled Ground Loop Interactions 240 Ground Loop Interference Due to Load Imbalance 243 Application of the Transfer Impedance Concept to Ground Loop Interference Coupling 245 Ground Loop Interactions: Frequency Considerations in CM to DM Interference Conversion 250 Case A: Totally Floating Circuit 252 Case B: Circuit Connected to SRS (“Grounded”) at One End 253 Case C: Circuit Connected to SRS (“Grounded”) at Both Ends 254 Resolving Ground Loop Problems 255 Isolation Transformers 258 Common-Mode Chokes (Baluns, Bifilar Chokes) 259 Optocouplers and Optical Isolators 263 Capacitive Couplers/Isolators 264 High-Speed Digital Isolators 265 Analog Differential, Instrumentation, and Isolation Amplifiers 266 Galvanically Isolated High-Speed Differential Transceivers 268 Circuit Bypassing 269 Summary of Interface Isolation Techniques 270 Example: Data Line Interface Isolation Design (10/100/1000BaseT) 270 Zoned Grounding 274 Electromagnetic Topology 274 The Zoning Concept as Applied to Grounding 276 Zoning Compromises and Violation 277 Impact of Zoning on Subsystem Grounding Architecture 278 Equipment Enclosure and Signal Grounding 279 External Signal and Safety Grounding Interconnects Between Enclosures 279 Equipment DC Power, Signal, and Safety Grounding 280 Power Distribution Grounding Schemes in Integrated Clustered Systems 281 Centralized Power Scheme with Secondary Power Supplies 282 Fully Centralized Power Distribution Scheme 283 Decentralized (Distributed) Power Distribution Scheme 284 Grounding of Equipment Enclosure Shield 285 Rack and Cabinet Subsystem Grounding Architecture 287 Grounding Ground-Rules in Racks and Cabinets 287 Ground Loops and Their Mitigation in Racks and Cabinets 289 External Grounding of Racks and Cabinets 290 Grounding Strategy Applied by System Size and Layout 292 One Size Fits None 292 Isolated System 292 Clustered System 292 Distributed System 294 Nested-Distributed System 295 Central System with Extensions 295

Contents

4.9.7

Grounding Strategy by System Size and Layout – Summary and Case Study References 298

5 5.1 5.2 5.3 5.3.1 5.3.1.1 5.3.1.2 5.3.1.3 5.3.1.4 5.3.1.5 5.3.1.6 5.3.2 5.3.3 5.3.4 5.3.4.1 5.3.4.2 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.7.1 5.5.7.2 5.5.7.3 5.5.8 5.5.8.1 5.5.8.2 5.5.8.3 5.5.8.4 5.5.8.5 5.5.8.6 5.5.8.7 5.5.8.8 5.6

Bonding Principles 301 Objectives of Bonding 301 Bond Impedance Requirements 303 Types of Bonds 305 Direct Bonds 305 Welding 307 Brazing 307 Soft Soldering 307 Bolts 308 Rivets 308 Conductive Adhesive 308 Indirect Bonds 308 Contact Impedance of Bonds 309 Bonding Impedance Equivalent Circuit 310 Bond Resistance 315 Bond Reactance 316 Bond Effectiveness 319 Enhancing Bonding Effectiveness 322 Surface Treatment 323 Roughness of Mating Surface Conditions 323 Surface Contaminants 323 Surface Hardness 324 Contact Pressure 324 Bond Area 324 Dissimilar Metals and Galvanic Corrosion Control 324 Thermodynamic Basis of Galvanic Corrosion 328 Electrochemical Series 333 Galvanic Series 335 Electrochemical Kinetics of Galvanic Corrosion – Blame it on Faraday 335 Galvanic Couples 340 Impact of Environment on Galvanic Corrosion 342 Effects of Corrosion on EMC Performance 346 Degradation of Equipment Bonding and Shielding 347 Collocation and RF-Coexistence in Spectrum-Dependent Systems 348 Electrostatic Discharge (ESD) Effects 349 Corrosion Protection and Control 351 Use of Similar Mating Metals 352 Applying Protective Conductive Coatings 352 Interposing Metals and Sacrificial Anodic Parts 356 Sacrificial Metal Coating 357 Minimizing Cathode to Anode Area Ratio 358 Breaking the Electrolytic Bridge 358 Protective (Nonconductive) Paint 359 Understand Project Particulars 359 Bonding Verification 360 References 362

6 6.1 6.2 6.3 6.4 6.5 6.6

Grounding in Power Transmission and Distribution Networks 365 Introduction 365 Overhead Transmission Lines 366 Underground Power Cable Transmission and Distribution Networks Earth Fault and Ground Potential Rise 369 Tolerable Step and Touch Voltages 371 Earthing for High-Voltage Substations 372

368

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6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.7.2.1 6.7.2.2 6.7.2.3 6.7.3 6.7.3.1 6.7.3.2 6.7.4 6.8 6.8.1 6.8.1.1 6.8.1.2 6.8.1.3 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 6.8.7 6.9

Bonding Requirements 372 Principal Design Considerations 373 Earthing for Power Distribution System 374 Faults in Power Distribution Systems 374 Electric Shock Hazards 377 Step and Touch Voltage and Transferred Potential Arising from Ground Faults 377 Leakage via Power Line Filter Capacitance 378 Shock Protection by Earthed Equipotential Bonding and Automatic Disconnection of Supply 378 Methods of Earthing in Power Distribution Systems 379 Solid Earthing 379 Impedance Earthing 380 The Ungrounded System 380 Earthing in Low-Voltage Distribution System 382 TN-System 382 TN-S System 383 TN-C System 385 TN-C-S System 386 TT System 386 IT System 388 Temporary Overvoltage in Low-Voltage Installations Due to Faults Between High-Voltage Systems and Earth Earthing Systems and EMC 392 Requirements for the Installation of Equipment with High-Protective Earth Conductor Current 392 Application of Residual Current Devices for Shock Protection 393 Equipotential Bonding to Building Structures and Other Services 394 References 396

7 7.1 7.1.1 7.1.2 7.1.2.1 7.1.2.2 7.1.3 7.1.3.1 7.1.3.2 7.1.3.3 7.1.4 7.1.5 7.1.6 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.1.1 7.4.1.2 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.4.2.4 7.4.3

Grounding for Generators, UPSs, VSDs, and Instrumentation 399 Grounding for Generators 399 Ungrounded Generator 400 Resistance Grounding 400 High-Resistance Grounding 401 NGR Grounding Transformers 402 Grounding of Generators in Parallel Operation 403 Multiple-Point Grounding 403 Single-Point Grounding 403 Neutral Grounding Transformer 404 Grounding and Earth Fault Protection for Generators in Parallel Operation 404 Nuisance Tripping of Generators in Parallel Operation – A Case Study 408 Transfer Switching of Alternate Power Supplies 410 Grounding for Uninterruptible Power Supplies 412 Grounding Scheme for Static Double-Conversion UPS 413 Grounding for Transformerless UPS 415 Grounding for Variable Frequency Drives 416 Stray Currents in VFDs 417 VFD Cables 417 Grounding Requirements for Instrumentation 418 Grounding Practices for Instrumentation 418 Connections to Instrument Earth 419 Connections to Safety Earth 419 Grounding for Fieldbus Systems 419 Power Supply and Isolation 420 Fieldbus Signals 420 Fieldbus Cable System 420 Shielding and Grounding 421 The Least You Need to Know 422 References 423

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8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.6 8.7 8.8 8.9

Grounding for Lightning Protection Systems 425 An Overview of the Lightning Phenomenon 425 Lightning Attachment Point and Zones of Protection 426 The Lightning Protection System 428 The Air Termination Subsystem 428 The Down Conductors 429 The Earth Termination Network 431 Application of Natural Earth Electrodes 433 Reduction of the Transient Impedance of Earth Electrodes 433 Protection Against Transferred, Touch, and Step Voltages 436 Influence of LV Earthing Schemes on Lightning Overvoltage 438 Separate or Integrated Electrical and Lightning Grounds 440 Pitfalls in Earthing and Bonding 445 References 446

9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.2.1 9.2.2 9.2.3 9.2.4

Integrated Facility and Mobile/ Transportable Vehicle Grounding Systems 449 Facility Grounding Subsystems 450 Earth Electrode Subsystem (EESS) 450 Fault Protection Subsystem (FPSS) 450 Lightning Protection Subsystem (LPSS) 450 Signal Reference Subsystem (SRSS) 451 Grounding Practices in Buildings and Fixed Facilities 453 Grounding of Power Distribution Systems in Buildings 454 Grounding in Industrial Facilities 455 Grounding for Information Technology Equipment 457 Grounding in Telecommunication and C4I (Command, Control, Communications, Computer, Intelligence, Surveillance, and Reconnaissance) Facilities 460 Grounding in HA-EMP-Protected and Secure C4ISR Facilities 463 Grounding for Facility HA-EMP Survivability 463 Grounding for Facility Emanation Security (EMSEC) 466 EMSEC vs. HA-EMP Grounding in Secure C4ISR Facilities 469 Grounding and Bonding Principles for C4ISR Facilities 469 Grounding Practices in Mass Rapid Transit Systems 477 Earthing in Stations 478 Stray Currents 478 Passenger Station and Platform 479 Protection Against Electrical Faults and Lightning Surges 480 Grounding Design Practices for Underground Facilities (in Rock Cavern) 482 Earthing and Bonding Requirements 482 Equipotential Bonding 482 Lightning Considerations 483 Earthing and Bonding Methodology 483 Guarding the Point of Entry 486 Grounding for Preclusion of Electrostatic Discharge (ESD) Effects in Facilities 487 Nature and Sources of Static Electricity 487 Susceptibility to ESD 491 ESD Protected Areas (EPAs) in Facilities 492 ESD Protective Tools, Materials, and Equipment 493 ESD Protective Workbenches and Work Surfaces 493 Personnel Wrist Straps 494 Protective Floors, Floor Mats, and Floor Finishes 494 Essentials of Grounding for ESD Control 495 Safety Considerations in ESD Grounding 496 Grounding Practices in Mobile Platforms and Vehicles 497 Grounding Practices in Transportable Tactical Shelters 497 Stand-Alone Equipment 499

9.2.5 9.2.5.1 9.2.5.2 9.2.5.3 9.2.5.4 9.2.6 9.2.6.1 9.2.6.2 9.2.6.3 9.2.6.4 9.2.7 9.2.7.1 9.2.7.2 9.2.7.3 9.2.7.4 9.2.7.5 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.4.1 9.3.4.2 9.3.4.3 9.3.5 9.3.6 9.4 9.4.1 9.4.1.1

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9.4.1.2 9.4.1.3 9.4.1.4 9.4.2 9.4.2.1 9.4.2.2 9.4.3 9.4.3.1 9.4.3.2 9.4.4 9.4.4.1 9.4.4.2 9.4.4.3 9.4.4.4 9.4.4.5 9.4.4.6

Stand-Alone Shelters or Trailers 499 Collocated Transportable Equipment 502 Collocated Shelters 502 Grounding Practices in Aircraft 505 Earthing of Aircraft and Ground Services 505 Internal Aircraft Grounding 507 Grounding Practices in Spacecraft 509 Earthing and External Grounding Connections between the Spacecrafts to the Launch Facility 509 Spacecraft Internal Grounding Considerations [46–50] 509 Grounding Practices in Ships 513 Ground Reference Structure 514 Hull-Generated EMI 514 Grounding at Ship Hull Penetrations 515 Hull (Structure) Power Current Return Scheme 515 Shipboard Signal Return Grounding Scheme [56] 516 Grounding Architecture in Nonmetallic Hull Ships [56] 518 References 519

10 10.1 10.2 10.3 10.3.1 10.3.2 10.4 10.5 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.6.6 10.7 10.8 10.9 10.10 10.10.1 10.10.2 10.11 10.11.1 10.11.2 10.11.2.1 10.11.2.2 10.11.2.3 10.11.2.4 10.11.2.5 10.11.3 10.12 10.13 10.14

The Earth Connection 523 Introduction 523 Typical Features of an Earthing System for a Low-Voltage Installation 523 Typical Features of an Earthing System for a High-Voltage Installation 525 General Design Considerations 525 Particular Design Considerations 527 Resistance to Earth 530 Soil Resistivity 531 Types of Earth Electrodes 532 The Earth Rods 532 Earth Plates 535 Horizontal Strip or Round Conductor Electrode 536 The Mesh or Grid Earth Electrode 538 The Ring Earth Electrode 540 Foundation Earth Electrode 541 Design of Earth Electrodes and Their Layout 543 Selection of Material 543 Grounding Requirements of Power Distribution Systems 544 Earth Potential Rise and Surface Potential Gradients 546 Vertical Earth Rod 546 Horizontal Electrodes 548 Measurement of Soil Resistivity and Earth Electrode Resistance 549 Measurement of Soil Resistivity 549 Measurement of Earth Resistance 550 Fall-of-Potential Method 550 Two-Point Method 551 Clamp-On Earth Tester 552 Three-Point Method 553 Staged Fault Method 554 Characteristics of Earth Electrode Resistance Testers 554 Measurements of Earthing System Impedance, Touch and Step Voltages 554 Safety in Measurement and Testing Earthing System 555 Reducing Earth Resistance 555 References 556

11 11.1 11.2 11.3

Grounding in Wiring Circuits and Cable Shields 559 Introduction: System Interface Problems 559 To Ground or not to Ground (Cable Shields) 559 Fundamentals of Cable Shielding 562

Contents

11.3.1 11.3.2 11.3.3 11.3.3.1 11.3.3.2 11.4 11.4.1 11.4.2 11.4.2.1 11.4.2.2 11.4.2.3 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 11.4.3.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.4.1 11.5.4.2 11.5.4.3 11.5.4.4 11.5.4.5 11.5.4.6 11.5.5 11.5.6 11.5.6.1 11.5.6.2 11.5.6.3 11.5.6.4 11.6 11.6.1 11.6.2 11.6.3 11.6.4 11.6.5 11.6.5.1 11.6.5.2 11.6.5.3 11.6.6 11.7 11.7.1 11.7.1.1 11.7.1.2 11.7.1.3 11.7.2 11.7.3 11.7.3.1 11.7.3.2 11.7.3.3

Why Shield Cables? 562 Fundamental of Shielding Mechanisms 562 Configuration of Shielded Cables 567 Balanced and Unbalanced Shielded Signal-Interface Cables 567 Transmission-Line Model of Shielded Cables 568 Cable Shield Termination 571 Termination of Cable Shields – A Qualitative Discussion 572 Termination of Cable Shields – A Quantitative Discussion 574 Shielding Against Electric Fields Interactions 574 Shielding for Control of Magnetic Fields Coupling onto Wiring 576 Shielding for Control of Magnetic Field Emissions 578 Frequency Considerations in Cable Shield Termination 579 Shielding and Ground Loops 580 Shield Termination at High Frequencies 581 Frequency-Selective Shield Termination 585 An R-L-C Lumped-Element Analysis of Shield and Its Termination 586 Shield Surface Transfer Impedance 601 Methods for Cable Shielding 603 Shield Surface Transfer Impedance in Coaxial Lines 604 Where Should a Shield of a Balanced Line be Terminated? 608 Shield Termination – The Key to Optimal Cable Shielding Performance 611 Effect of Pigtail Shield Termination 612 High-Performance Shield-Termination Techniques 615 Maintaining Cable Shield Continuity 620 Termination of Multiple Shields 623 Resistive Termination in Multiple Shields 625 Frequency-Selective Cable-Shield Termination 627 Twisted Cables and the Effect of Grounding 629 Strategies for Shield Termination in Common Types of Shielded Cables 632 Coaxial Cables 632 Triaxial Cables 633 Twinaxial Cables 634 Ribbon Cables 636 Grounding Considerations in Signal Interfaces 638 Interfacing Low-Frequency Unbalanced Signal Circuits 638 Interfacing High-Frequency Unbalanced Signal Circuits 640 Interfacing Equipment Containing both Low- and High-Frequency Signals 641 Interfacing of Broadband (Video) Signal Circuits 641 Interfacing of Balanced Signal Circuits 642 Differential vs Balanced Signaling – A Déjà vu 644 RS-422 and RS-485 646 Ethernet (Twisted-Pair Interface) 648 Effect of Interface Grounding Scheme on Magnetic Interference Susceptibility 650 Grounding of Transducers and Measurement Instrumentation Systems 651 Measurement Accuracy Concerns 652 Floating Measurements 652 Floating Measurement Apparatus 654 Guarded Measurement Apparatus 655 Guard Shields and Instrumentation Wiring Shield Interconnection 655 Grounding of Wiring Shields in Analog Data Acquisition Systems 656 Grounded Transducers 658 Ungrounded (“Floated”) Transducers 659 Transducer Amplifiers 661 References 661

12 12.1 12.2

Grounding of Terminal Protection Devices 663 Filtering and Transient-Voltage Suppression – Complementary Techniques to Shielding 663 Types of Conducted EMI 663

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12.3 12.3.1 12.3.2 12.3.2.1 12.3.2.2 12.3.3 12.3.3.1 12.3.3.2 12.3.3.3 12.3.3.4 12.4 12.4.1 12.4.2 12.4.2.1 12.4.2.2 12.4.3 12.4.3.1 12.4.3.2 12.4.4 12.4.5 12.4.5.1 12.4.5.2 12.4.5.3 12.4.5.4

Overview of Filtering and Transient-Voltage Suppression 663 Fundamental EMI Filter Devices and Circuits 663 Special EMI Filter Applications 670 Common-Mode Chokes 670 Power-Line Filters 671 Transient-Voltage Surge Suppression (TVSS) Devices and Circuits 672 A Transient-Effects, Grounding-Related Case Study 672 Fundamentals of Transient-Voltage Surge Protection 673 Commonly Used Transient-Voltage Surge Suppression Devices (TVSS) 673 Hybrid Transient-Protection Circuits 676 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices 677 Modes of Protection 677 Modes of EMI and Transients 678 Common-Mode Surges 679 Linear and Nonlinear Conversion Loss 679 Effect of Circuit Grounding Scheme on Terminal Protection 681 Transient Protection in a Completely “Floating Circuit” 682 Transient Protection in a “Single-Point Grounded Circuit” 683 When Is Ground Not Equal to Ground? 685 Practices for Mounting and Grounding/Bonding of Terminal Protection Devices (TPDs) 689 Optimizing Filter Grounding – Feed-Through Capacitors and Filters 689 Filter Connectors 691 Optimizing Filter Grounding – PCB Layout Issues for Transient-Voltage Protection 692 Mounting Practices – “Doghouse Mounting” 693 References 695

13 13.1 13.2 13.3 13.4

Grounding on Printed Circuit Boards 697 A Bird’s Eye View on Signal Integrity (SI), Power Integrity (PI), and EMC 697 Interference Sources on the PCB 699 “Grounding” on PCBs 704 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields 704 Circuit Representation of Transmission Lines on PCBs 705 Electromagnetic field representation of transmission lines on PCBs 706 Equivalence of Power and Ground Planes as Return Paths for High-Speed Signal Propagation 708 Common Transmission Line Configurations on PCBs 710 Single-Ended Transmission Line Configurations 711 Differential Transmission Line Configurations 713 Nature of Transmission Lines at Ultrahigh Frequencies 714 Losses and Absorption 715 Conductor and Plane Losses 715 Dispersion 718 Effect of Conductor Surface Roughness 721 The Dark Side – Return of the Signal: Return Current Path on PCBs 724 Return Current Distribution 732 Crosstalk on PCBs – The Conversation We Wish Would Stop! 735 Common Impedance Coupling on PCBs 741 Consequences of Transmission Line Topology on EMI and Crosstalk Control 745 Return Path Discontinuities: “Mind the Gap” 750 Dreadful or Tolerable – It Depends? A Case Study 751 Undesired Effects of Traces Crossing Gaps in the Reference Planes: “Seeing is Believing” 754 Creation of Common-Mode Currents and Emissions 754 Susceptibility to Impulsive-Radiated Electromagnetic Fields 756 Crossing Reference Plane Breaks as a Source of Crosstalk 757 Crossing Reference Plane Breaks, Rise Time Effects on Signals 759 Radiated Emissions from a Split Plane, Verification by Simulation 759 Reference Plane Discontinuities and Mitigation Strategies 762

13.4.1 13.4.2 13.4.3 13.4.4 13.4.4.1 13.4.4.2 13.4.5 13.4.5.1 13.4.5.2 13.4.5.3 13.4.5.4 13.4.6 13.4.7 13.4.8 13.4.9 13.4.10 13.5 13.5.1 13.5.2 13.5.2.1 13.5.2.2 13.5.2.3 13.5.2.4 13.5.2.5 13.5.3

Contents

13.5.3.1 13.5.3.2 13.5.3.3 13.5.3.4 13.5.4 13.5.4.1 13.5.4.2 13.5.4.3 13.5.4.4 13.5.4.5 13.5.5 13.5.5.1 13.5.5.2 13.5.5.3 13.5.5.4 13.5.6 13.5.7 13.6 13.6.1 13.6.1.1 13.6.1.2 13.6.1.3 13.6.2 13.6.2.1 13.6.2.2 13.6.3 13.6.3.1 13.6.3.2 13.6.3.3 13.6.3.4 13.6.3.5 13.6.4 13.6.4.1 13.6.4.2 13.6.4.3 13.6.4.4 13.6.4.5 13.6.5 13.6.6 13.6.6.1 13.6.6.2 13.6.6.3 13.6.6.4 13.7 13.7.1 13.7.2 13.7.3 13.7.4 13.7.5 13.7.5.1 13.7.5.2 13.7.6 13.7.7 13.7.7.1 13.7.7.2

Traces Crossing Slots and Splits in Reference Planes 763 Mitigating the Adverse Effects of Traces Crossing Slots in Reference Planes – “Bypass (Stitching) Capacitors” 768 Mitigating the Adverse Effects of Traces Crossing Slots in Reference Planes – “Interdigital Slot in Reference Planes” 772 Excessive Pin/Hole Clearance 780 (Almost) Never Jump Layers! – Cavity Excitations by Signals 788 Signal Trace Traversing a Single Reference Layer 788 Signal Trace Traversing Multiple but Identical Reference Layers 790 Signal Trace Traversing Multiple and Dissimilar Reference Layers 795 The Layer-Jumping Dilemma – Seeing is Believing! 807 Improper Motherboard to Daughter Board Connections 810 Differential Lines Crossing Gaps in Reference Planes 813 Return Current Distribution of a Differential Pair 814 Differential Return Current Concerns: Return Current “U-Turn” 815 Differential Lines Jumping Layers are No Different 817 Differential Lines Crossing Defected Ground Structure (DGS): Putting Slots to Work 818 Edge Connector Discontinuities and Mitigation Strategies 823 Reference Plane Edge Effects 825 DELTA-I (ΔI ) and Simultaneous Switching Noise (SSN) in PCBs 829 General ΔI-Noise Generation Mechanism 829 Drive Current Discharge into Loads’ Input Capacitances 829 Drive Current Discharge into Loads’ Input Capacitances 832 Core (Processing) Noise 833 Consequences of ΔI-Noise 833 Amplitude Type Interference (Ripple) 834 Temporal Type Interference (Jitter) 836 Effective Management and Control of ΔI-Noise Consequences 837 Reducing Load Capacitance 840 Increasing Transition Times of the Switching Signals 840 Reducing Common Impedance in Connectors and Device Packages 841 Reducing Circuit Overall Net Inductance (“It’s Really All About Inductance”) 842 Reducing the Impedance of the Power Distribution Network (“It’s ALSO All About Inductance”) 846 Decoupling Strategies 847 The “Brigade of Capacitors” 847 Decoupling Design – Selection of Capacitors 850 Placement and Mounting of Decoupling Capacitors (Avoid the “No-Fly Zone”) 857 Controlling Spreading (or Interconnection) Inductance 864 Embedded Capacitance – The Ultimate Solution? 868 And then There Were those Pesky Rogue Waves… 870 “Before You Add Capacitors… Hold Your Horses” – Decoupling and Inrush Current 876 What is Inrush Current? 876 Effects of Load Capacitance on Inrush Current 877 Problems Caused by Inrush Current – Why the Concern? 878 Methods of Reducing Inrush Current 879 Parallel-Plate Waveguide (PPW) Noise Mitigation 881 PDN Parallel-Plate Waveguide (PPW) Excitation 881 PDN Parallel-Plate Waveguide (PPW) Cavity Resonance 883 Parallel-Plate Waveguide (PPW) Edge Radiation 885 Parallel-Plate Waveguide (PPW) Noise Mitigation using Recessed PCB Power Planes (20-H Rule) 887 Parallel-Plate Waveguide (PPW) Noise Mitigation using PCB Edge Termination 889 Via Stitching 890 Dissipative Edge Termination 893 Parallel-Plate Waveguide (PPW) Noise Mitigation using Virtual Islands and Shorting Via Arrays 894 Parallel-Plate Waveguide (PPW) Noise Mitigation using Electromagnetic Band Gap (EBG) High-Impedance Structures (HIS) 901 Electromagnetic Band-Gap (EBG) Structures as Surface Wave Filters 901 EMI Suppression Using Embedded EBG (E-EBG) Structures 903

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13.7.7.3 13.7.7.4 13.7.7.5 13.7.7.6 13.7.7.7 13.8 13.8.1 13.8.2 13.8.3 13.9 13.9.1 13.9.2 13.9.3 13.9.4 13.10 13.10.1 13.10.2 13.10.3 13.11 13.11.1 13.11.2 13.11.3 13.11.4 13.12 13.12.1 13.12.2 13.12.3 13.12.4 13.12.5 13.12.6 13.12.7 13.12.8 13.13 13.13.1 13.13.2 13.13.3 13.13.4 13.13.5 13.13.6 13.13.7 13.14 13.14.1 13.14.2 13.14.3

14 14.1 14.1.1 14.1.2 14.1.3 14.1.4 14.2 14.2.1 14.2.2 14.2.2.1

Ultra-Wideband (UWB) EMI Suppression using EBG/HIS Structures 906 Low-Period Coplanar EBG (LPC-EBG) Structures 906 Planar Meander-Line EBG (ML-EBG) Structures 910 Partial EBG (P-EBG) PDN Structures using Remnants of Signal Layer 913 Impact of EBG Structures on SI and Radiated EMI Emissions 917 Return Planes and PCB Layer Stackup 921 Image Planes 922 Shielding Provided by Ground Planes – or a “Trojan Horse Effect?” 923 Frequently Used PCB Layer Stackup Configurations 924 Local Ground Structures 928 Micro-Islands 928 Copper Fills 930 Local Ground Structure Resonances 931 Other Local Ground Structure Concerns 935 Guard Traces – Love Them or Leave Them? 936 Guard and Shunt Traces 936 “Boxed Stripline” 939 Guard Rings 940 Intentional Cuts and Slits in Return Planes 942 Circuit Partitioning, or Why Castles Don’t Have EMI Issues? 942 Circuit Isolation 944 Circuit Partitioning and Isolation – A Case Study: Ethernet Circuit Ethernet Layout and the Function of Ground Planes 945 (Draw)Bridging the Gap 951 Grounding in Mixed (Analog-Digital) Signal Systems 954 Origins of Noise in Mixed Digital-Analog Circuits 955 Grounding Analog Circuits 958 Grounding Digital Circuits 959 Grounding in Mixed Signal PCBs: “To Split or not to Split (the Ground Plane)?” 959 The Mystery of A/D and D/A Converters Resolved 962 Grounding Scheme for a Single ADC/DAC on a Single PCB 964 Grounding Scheme for Multiple ADCs/DACs on a Single PCB 966 Grounding Scheme for ADCs/DACs on Multiple PCBs 970 Chassis Connections (“Chassis Stitching”) 973 Purpose of Stitching PCB Return Planes to Chassis 973 Direct Stitching of Return Planes to Chassis 978 Hybrid Techniques for Stitching of Return Planes to Chassis 979 Capacitive Stitching of Return Planes to Chassis 981 Controlling PCB-Chassis Cavity Resonances 983 Benefits of Reduced Spacing between PCB and Chassis 986 Daughter and Mezzanine Boards Ground Stitching 986 Grounding Considerations for PCB Heatsinks 987 The Role of Heatsinks in Generation of EMI 987 Heatsink Resonances 989 The Effect of Heatsink Grounding on EMI Control 990 References 995 Testing and Troubleshooting Grounding Problems 1001 Ground Plane Interference (GPI) Susceptibility Testing 1001 Conducted Susceptibility, Ground Plane Injection, Spike/Transient 1002 Conducted Susceptibility, Ground Plane Injection, Audio Frequency (AF) 1003 Conducted Susceptibility, Ground Plane Injection, Radio Frequency (RF) 1004 MIL-STD-461G Method CS109, Conducted Susceptibility, Structure Current 1005 Grounding Diagnostics and Troubleshooting 1006 Approaches to EMI Diagnostics 1006 Troubleshooting Grounding “Situations” 1008 A Reminder of Ground Loops Problems 1008

Contents

14.2.2.2 14.2.2.3 14.3 14.3.1 14.3.1.1 14.3.1.2 14.3.1.3 14.3.1.4 14.3.2 14.3.2.1 14.3.2.2 14.3.2.3 14.3.3 14.3.3.1 14.3.3.2 14.3.3.3 14.3.4 14.3.4.1 14.3.4.2 14.3.4.3 14.3.5 14.3.5.1 14.3.5.2 14.3.5.3 14.3.6 14.3.6.1 14.3.6.2 14.3.6.3

Diagnosing and Identifying Ground Loops 1010 Ground Loop Solutions 1011 Grounding, Bonding, and Earthing Case Studies 1012 Case #1: “The Grounds for Electrostatic Discharge (ESD)” 1012 Case Description 1012 Case Investigation 1012 Case Resolution 1013 Misconceptions, Fallacies, and Facts Demonstrated 1013 Case #2: “The Grounds for Lightning Protection” 1013 Case Description 1013 Case Resolution 1014 Misconceptions, Fallacies, and Facts Demonstrated 1016 Case #3: “The Grounds for Ground Radar Grounding” 1016 Case Description 1016 Case Resolution 1017 Misconceptions, Fallacies, and Facts Demonstrated 1018 Case #4: “The Grounds for Differential Signaling Grounding” 1018 Case Description 1018 Case Resolution 1019 Misconceptions, Fallacies, and Facts Demonstrated 1020 Case #5: “The Fallacy of Lightning Protection” 1020 Case Description 1020 Case Resolution 1021 Misconceptions, Fallacies, and Facts Demonstrated 1021 Case #6: “The Grounds for Electrical Safety” 1022 Case Description 1022 Case Resolution 1022 Misconceptions, Fallacies, and Facts Demonstrated 1022 References 1024 Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Index

A B C D E F G H I J K L M

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Glossary of Grounding, Earthing, and Bonding-Related Terms and Definitions 1025 Acronyms 1041 Symbols 1045 Values of Fundamental Properties 1047 Grounding, Earthing, and Bonding-Related Standards, Specifications, and Handbooks 1049 Practical Experiments for Demonstration of Grounding and Bonding-Related Principles 1071 Grounding Verification Checklist and Procedures 1081 Grounding Documentation Content 1119 On the Equivalence Between Ohm’s Law and Fermat’s Least Time Principle 1121 Thoughts on the Low-Frequency Return Current Distribution 1125 Overview of S Parameters 1145 Sample Practical Analysis of “Common-Impedance Coupling” 1157 Grounding, Bonding, and Earthing Check Yourself Quiz 1167

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Author Biographies Elya B. Joffe is the founder and President of “Elya Joffe – Electromagnetic Solutions”, Ltd., an engineering consulting firm in Israel, since 2014. He holds a B.ScEE in Electrical Engineering from the Ben Gurion University in Israel and is a Registered Professional Engineer. Mr. Joffe is also an iNARTE (International Association for Radio, Telecommunications and Electromagnetics Engineers) certified EMC Engineer, EMC MIL-STD Specialist, ESD Control Engineer and EMC Master Design Engineer. Elya has over 40 years of experience in government and industry, in EMC/E3. Mr. Joffe is also well known in Israel and abroad for his activities in EMC training and education, and has authored, developed and presents many courses on Electromagnetic Compatibility and related topics. He has authored and co-authored over 30 papers in EMC and EMC-related topics. Mr. Joffe is Senior Life Member of IEEE, and a Past President of the IEEE EMC Society and Past President of the IEEE Product Safety Engineering Society. He is also a Past Chairman of the Israel IEEE EMC Chapter. Mr. Joffe is a past member of the IEEE Education Activities Board (EAB) and Chaired the IEEE Continuing Education Committee (CEC). Mr. Joffe also served as a “Distinguished Lecturer” of the IEEE EMC Society, for the years (1999 to 2000) and of the Consumer Electronics Society (2013 to 2014). Mr. Joffe received several awards from the IEEE and EMC Society for his activities. In particular - he is a recipient of the IEEE EMC Society “Laurence G. Cumming Award for Outstanding Service” for “outstanding Service and leadership as the Israeli IEEE EMC Chapter Chairman, contributing to the EMC standardization of commercial products in Israel, promotion of the IEEE International EMC Symposium as Chairman and Contributing to the overall success of the IEEE EMC Society” (Ca. 2002), the “Honorary Life Member Award” of the IEEE EMC Society for “outstanding service to the EMC Society in globalization, regional and international standardization, and for on-going EMC chapters and membership initiatives” (Ca. 2004), the IEEE EMC Society “Technical; Achievement Award” for “over two decades of significant professional achievements in airborne and avionics EMC and printed circuit design/analysis for fast digital/analog signals and for significant contributions to the understanding of interference coupling to avionics, and RFI emissions from avionics and cost effective EMC measures for increasing systems’ immunity to EMI” (Ca. 2004) and the IEEE “Third Millennium Medal” “…in recognition and appreciation of valued services and outstanding contributions”. Mr. Joffe was the recipient of the very prestigious “2006 IEEE RAB Larry K. Wilson Transnational Award” “For outstanding contribution to enhancement of the transnational character of IEEE through promotion of conferences, membership and chapter development on a regional and global basis”. Mr. Joffe is a member of the very prestigious honor societies: IEEE Eta-Kappa-Nu (IEEE-HKN) and the “dB Society”. Kai-Sang Lock, PhD, is a professor (engineering) at the Singapore Institute of Technology. He has been a practicing Professional Engineer for over 20 years. He is a Fellow of the Academy of Engineering Singapore, a Fellow of the Institution of Engineering and Technology, UK, an Honorary Fellow of the Institution of Engineers, Singapore as well as a Life Senior Member of IEEE. He is an Emeritus President of the Institution of Engineers, Singapore, a past Board Member of the Professional Engineers Board, and a past Chairman of the Singapore Standards Council. He is the 2021 Co-Laureate of the WFEO Medal for Excellence in Engineering Education awarded by the World Federation of Engineering Organizations.

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Foreword Introduction to the Second Edition The fact that a second edition is in print speaks for itself. There is a need for information and guidance on the very controversial topic of grounding (single or multipoint, which is best …?), and Elya managed to compile the relevant theory and practice of grounding into the voluminous comprehensive first edition of the book. The second edition contains enhancement of some topics as well as new chapters, as a result of the advancement of electronics into high-speed systems and also as a result of cumulated feedback from readers, which show that Elya is keeping in touch with the evolving technology, all to the benefit of the users of the second edition. Good show, Elya, Keep it up. Oren Hartal Qiryat Tivon, Israel

Introduction to the First Edition The topic of grounding in EMC is one of the most controversial in this engineering discipline. A solution implemented in one system may not work in another, and “rules of thumb” and “good engineering practices” serve well mostly in presentations. Elya B. Joffe and Dr. Kai-Sang Lock have undertaken a monumental task and complied into this book, Grounds for Grounding, most of the data and information required by the designer. The treatment covers the electromagnetic basics, explanation of the reasoning behind the grounding solutions and up to their practical implementation. This book is perhaps the most comprehensive publication to date on the subject of grounding. It deals with every aspect of grounding, from component to system to facility. Because of its vast coverage and detailed discourse, it may take some time and effort to read through. However, each chapter can be approached for specific grounding solutions. I applaud Elya B. Joffe, president of the IEEE EMC Society and a full-time EMC Engineer, and Dr. Kai-Sang Lock, the president of PQR Technologies Pte Ltd. in Singapore, for addressing the topic and spending the time and effort, despite their duties, to get this well-written, important book completed. This book will not replace experience and experiment, but it will shorten the path to a successful design. Oren Hartal Qiryat Tivon, Israel Israel procured several groups of F-16 aircraft from my company, General Dynamics (now Lockheed Martin). Electromagnetic compatibility (EMC) engineering for these programs was accomplished by my group of thirty EMC engineers in Fort Worth, Texas. As the models of Israeli F-16 aircraft became more complex, direct interaction with Israeli engineers became appropriate. The first such meeting occurred in 1983 in Tel Aviv, and my attendance triggered the Israeli Air Force to find a suitable engineer to represent them. They found Israeli Air Force Lieutenant Elya B. Joffe, who had a BSEE Degree from Ben Gurion University and majored in wave propagation and electromagnetic theory. They told him he was now an EMC engineer and sent him to my meeting! (Engineers usually wind up in EMC by accident, and Elya was no exception!) Practical applications in engineering do not always follow the theory. In Israel, engineers were very knowledgeable of electromagnetic theory, but in the Israeli Air Force (IAF) in 1983, the practice of the technology was limited. This limitation did not stop Elya. He readily grasped the differences between his technical background and the practical aspects of EMC, and

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progressed well. After 1983, he and I had many technical meetings both in Israel and in Fort Worth, and became good friends. One time, he and his wife, Anat, stayed at my home in Fort Worth while my wife and I were in San Francisco! After completing his military service as a Major, he joined Israeli Aircraft Industries as an EMC engineer. He became very active in the Israeli Chapter of the IEEE EMC Society and was elected its chairman. Elya was nominated and elected to the EMC Society Board of Directors. In 2007, he was elected president-elect of the IEEE EMC Society and served as president in the years 2008–2009; the first and only non-American ever to hold this office to-date! Years ago, Elya recognized the need for a treatise on electrical grounding, the foundation for achieving system electromagnetic compatibility. He has spent many years researching the subject and preparing his manuscript. Now, he has provided the world with this valuable and long-needed reference. Thank you, Elya!

Jack L. Moe Fort Worth, Texas, USA

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Preface to the Second Edition It’s a dangerous business, Frodo, going out your door. You step onto the road, and if you don’t keep your feet, there’s no knowing where you might be swept off to. – J.R.R. Tolkien “The Lord of the Rings, The Fellowship of the Ring” Commencing work on this second edition of the book, indeed reminded me of Frodo, the protagonist of The Lord of the Rings, taking his first steps on his travel from Hobbiton, in the comfortable Shire, to Mordor. Undeniably, the challenge in the second edition is, in a way, greater than the first. Similar to a paratrooper who is typically more scared of the second jump than the first – he has already experienced the fear and knows the challenge, so much so writing the second edition of this book. First, because the amount of effort put into this book is already known, and more so, because it is evident that expectations from the second edition are higher and the challenge is intimidating. We hope and believe that this second edition meets (and hopefully exceeds) your expectations. Blessed are You, Lord, our God, King of the Universe, who has granted us life, sustained us, and allowed/let us [to] arrive at this Time. – The Hebrew “She’hecheyanu” (“Who has given us life”) Blessing, a common Jewish prayer said to celebrate special occasions.

A Tribute to Michael Faraday and James Clerk Maxwell The understanding of grounding as described in this book could not have been made possible without the achievements of Michael Faraday and the great philosopher who followed him, James Clerk Maxwell. The following excerpt was written by Maxwell after Faraday’s death in 1867. It is from the introduction by T.F. Torrance to Maxwell’s A Dynamical Theory of the Electromagnetic Field (Wipf and Stock Publishers, Eugene, OR, 1996). The high place which we assign to Faraday in electromagnetic science may appear to some inconsistent with the fact that electromagnetic science is an exact science, and that in some of its branches it had already assumed a mathematical form before the time of Faraday, whereas Faraday was not a professed mathematician, and in his writings we find none of these integrations of differential equations which are supposed to be the very essence of exact science. Open Poisson and Ampere, who went before him, and you will find their pages full of symbols, not one of which Faraday would have understood. It is admitted that Faraday made some great discoveries, but if we put these aside, how can we rank his scientific method so high without disparaging the mathematics of these eminent men? It is true that no man can essentially cultivate any exact science without understanding the mathematics of that science. But we are not to suppose that the calculations and equations which mathematicians find so useful constitute the whole of mathematics. The calculus is but a part of mathematics. The geometry of position is an example of mathematical science established without the aid of a single calculation. Now Faraday’s lines of force occupy the same position in electromagnetic science that pencils of lines do in the geometry of position. They furnish a method of building up an exact mental image of the thing we are reasoning about. The way in which Faraday made use of his idea of lines of force in coordinating the phenomena of the magnetoelectric induction shows him to have been in reality a mathematician of a very high order—one from whom the mathematicians of the future may derive valuable and fertile methods …. [W]e are probably ignorant even of the name of science which will be developed out of the materials we are now collecting, when the great philosopher after Faraday makes his appearance.

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Acknowledgments To the many great People who have imparted wisdom to me on my journey. In particular, this book would have never come to be a reality had it not been for two special persons in my professional career. Without their guidance and mentorship, I would have never been able to attain the knowledge and experience in my profession. Both are not only good friends of mine but also of each other. First, John (Jack) Moe, who initially introduced me to this magical discipline of EMC and with limitless patience, through “on-job training,” revealed to me the very basics of EMC. The very first book I owned on EMC was presented to me by Jack. I have retained and value his handwritten sketches and notes explaining cable shield grounding. Second, I would like to recognize Oren Hartal, under whose guidance (similar to most EMC engineers in Israel) I discovered the hidden mysteries of the science and art of EMC. The very first course on EMC I had taken was taught by Oren, and through his guidance I truly gained a deep understanding of this discipline. Many years of work with and encouragement by Oren in IEEE and URSI have, additionally, brought me to the international recognition I benefit from today. I am especially grateful to my dear friend Mark M. Montrose, who from the advent of work on the first edition encouraged me to undertake the tremendous challenge of writing this book and now publishing it in this – the second edition. Through his support during the writing of the book, Mark redefined the term “friend.” Mark’s advice helped shape the outline of the book and made significant contributions in many ways to the final manuscript. His technical review, professional scrutiny, and criticism of the material, made with a fine-tooth comb, helped ensure that concepts were clear, correct, and easy to follow and that the language and style were appropriate. Without his guidance and support, the technical quality and clarity of this book would not have been as they are. I thank Mark wholeheartedly for his friendship, collegiality, and support. A particular acknowledgment is given to Kai-Sang Lock, the coauthor of this book. Kai-Sang was the perfect choice for the task, with his expertise on high-power electrical systems. Without his contribution, a major aspect of grounding could not have been included in this book. A large part of the revision to this book in this second edition has been undertaken by Kai-Sang, and his contribution has undoubtfully enhanced the value of this book for even larger audience than the first. The authors are indebted and wish to gratefully acknowledge the contributions made by many individuals who helped to develop the material for this book, provided material, spent time, and exerted efforts in order to make this book of the high quality I believe it is. Acknowledgments of their contributions are included in the context of this book. Special gratitude is expressed to Bruce Archambeault, Douglas C. Smith, Keith Armstrong (Cherry Clough Consultants), Todd Hubing (LearnEMC), Alexander Perez (Agilent), Edoardo Genovese, and David Johns (CST), as well as to Glenair, Inc., and MAJR Products, Inc., for their outstanding support and contribution of material used throughout this book. Gratitude is extended to the editorial and technical reviewers of this book for their dedicated toil and for spending long and frustrating hours of their personal time in tedious study and literal dissection of this book. Their professionalism and experience have greatly enhanced the quality and value of this book. My appreciation is also expressed to the many engineers and students whom I have educated and trained in EMC throughout the years, for their challenging and thought-provoking questions. I have learnt much from my teachers, but from my students I have learnt even more. — Shimon Ben Zoma, a second century Jewish Scholar, based on Psalms, 119:99 I am most grateful to the many readers who have written in to point out misprints and errors in the first edition and have given me the benefit of their comments regarding the level of depth in certain topics. We have attempted to remedy those shortcomings by expanding on certain topics (which explains the new structure of several of the chapters). This book would not have been possible without the wholehearted cooperation of the staff of IEEE Press and Wiley, and I take this opportunity to express my gratitude to each and every one of them. Above all, in a personal note, my most special gratitude is due to my parents: my late mother, Faiga, who gave me the inspiration and taught me the power of words but did not live to observe this achievement; my late father, Harry, who did and was so proud to receive a copy of the first edition of the book.

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Acknowledgments

In the recent two years, my late father-in-law, Professor Emeritus Naftali Shafrir, passed away, at the age of 100 (minus 19 days), and my late mother-in-law, Hanna Shafrir (nee Bauman), passed away at the age of almost 92. As a scientist and engineer (as past head of Nuclear Engineering Department at the Technion in his past), Naftali was a source of professional inspiration to me, a true “scientist and gentleman,” and expressed much interest in this book and could appreciate the achievement from a scientific perspective. I am also indebted to my wonderful, supporting, and understanding immediate family, my wife, Anat, who helped me appreciate the power of persistence and endured my endless frustrations and foibles without (or with little) protest while this book was being created, and finally, to my daughter, Tami Lee, now married to our wonderful son-in-law, Roni, whose beaming smiles and words of encouragement gave me the strength to proceed with this effort. Now that Tami Lee is out of our home, Anat, my wife, has undoubtfully often felt she had taken the back seat in this project and put up with the long hours during the months I spent at my computer keyboard. In these days of trials and tribulations, enhanced by her severe injury and then the loss of her beloved parents, and with the anxiety associated with the Covid-19 pandemic, this effort has no doubt taken its toll on her life. I shall forever treasure her sympathy to my passion and her faith in my ability to create this book.

Elya B. Joffe Hod-Hasharon, Israel March 2022

1

1 Overview The term “ground” too often seems to be associated with a sort of cure-all concept, like snake oil, money or motherhood. Remember that, while you can always trust your mother, you should never trust your “ground.” Examine and think about it.[1] For those unfamiliar with the theory and practice of grounding, it can seem very confusing and complicated. Indeed, grounding is probably the most important aspect of electrical or electronic system design, yet it is probably the least understood by most engineers. Often blended with misconceptions, myriad rules about grounding sometimes seem a bit too much to handle and grounding implementation problems often leave you dazed and confused, with the correct solution seemingly a bit over your head. Despite the long history of electromagnetic compatibility (EMC) and signal integrity/power integrity (SI/PI) engineering, both significantly reliant on proper grounding at the circuit and system levels, some of its important concepts seem to be misinterpreted or even completely missing from the electrical industry’s oral tradition and regular practice. At the end of the day, it is typically necessary, in grounding implementation, to strike a balance between electromagnetic interference (EMI) control, safety, and good engineering practices, often setting the scene for the erroneous (and occasionally disastrous) concept that “one size fits all.” Grounding theory is not intuitive. Achieving a functional grounding philosophy often results from battles of wits, perseverance, and the resolution of conflicts between instinct, intuition, and engineering experience and judgment. The good news is, though, that there are basic fundamental principles that drive grounding design and key metrics for adequate grounding system performance. Electromagnetic interference and noise are generally pervasive in all electrical and electronic systems. Because this is true, it would be fair to say that every electrical and electronics design engineer will ultimately encounter grounding problems during the span of his career. In fact, in our humble opinion, all electrical and electronics design engineer belong to one of two groups: Those who have encountered grounding issues and… those who will! Ask two engineers for “their” solution to EMI or electrical noise problems and, if you are lucky, you will end up with only two different recommended approaches. It is for this reason that many design engineers are wont to say, “For every grounding problem there are many solutions, most of which are wrong.” One of the key challenges in EMC, and particularly in grounding, is that they are integrative and interdisciplinary, requiring familiarity and application of electrical and mechanical engineering, thermodynamics, chemistry and materials, lock, stock and barrel, with potential impact on system reliability, maintainability, and safety (Figure 1.1). Even software issues may sneak in occasionally. On the other hand, it is common that grounding requirements from the perspective of EMI control conflict with requirements emerging from those, seemingly unrelated, fields. When such casually provided approaches are attempted, it will often be revealed that what worked in one situation may not necessarily work well in another. Experience does play a prime role in the details of the grounding design of a specific system. Unfortunately, that experience is generally not transferable to another system, even if they both utilize the same technology. Grounding design is so system specific, which is rarely there is a “generic” solution that is fit for all cases. In other words, “one size fits none.” Many proposed solutions appear to conflict with fundamental physical principal requirements imposed on the system. They may be based on myths and misconceptions regarding the very concept of grounding, such as1:

•• •

“Current Goes to Ground” “Electrons (only) Take the Path of Least Resistance” “Common, Ground and Neutral are the Same”

1 Source: https://www.hvacrschool.com/grounding-bonding-myths/. Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

2

1 Overview

EMC

Thermo dynamics

Reliability Software

Maintainability Safety Figure 1.1

•• •

Materials and chemistry

Mechanics/ dynamics

EMC, and particularly grounding, is integrative and interdisciplinary.

“Ground Electrodes (Rods) Keep Us from Getting Shocked” “To be Safe, Add More Ground Rods” “Connecting Neutral and Ground Together in Multiple Places is a Good Idea”

just to mention a few. But you can steer clear of the confusion if you understand the concepts behind the rules. With a better understanding, you can have more confidence that your grounding system will function as you intended. Indeed, design of any grounding system, contrary to common belief, is founded on solid science. The watchful engineer may be generally aware of the correct principles but be guilty of their misapplication, either through inexperience, negligence, or even an intentional effort to avoid Maxwell’s equations and their consequences. Electrical and electronic design is usually taken to be “well founded.” By that it is meant it can be modeled, analyzed, and simulated using commonly known circuit analysis tools such as pSpice.2 Electrical and electronic circuit design seems repeatable, the solution appears to be straightforward, and the parameters are typically simply outlined and implemented in a wellunderstood model. For a successful analysis to be carried out, the engineer must be able to clearly state the issues of concern or the problem to be addressed down to the component level, including any related variables. This data is provided via measurement or simulation or both. However, when grounding problems are encountered, it is not so simple to identify the components involved, or even the path or paths of interest. This can be a challenging problem at DC or low frequencies. At higher frequencies in radio frequency (RF) circuitry as well as in the now commonly used high-speed digital switching circuits, components stubbornly obey the laws of physics, with capacitors acting like inductors, inductors exhibiting capacitive responses, and printed circuit boards introducing parasitic reactive circuit elements that cannot be found in the drawing. As Don R. Bush, (1942–2001) said, “Anyone can construct a mathematical model and generate data. But if the predictions of your mathematical model do not match experimental data, either your model is worthless or your measurements are not done properly.”3 Analysis of grounding systems, particularly in large installations, but even in small-scale circuits, may be a very complex issue and typically defies straightforward definition. The challenge further increases when considering the risk of safety code violation, caused by misinterpretation and wrong implementation of grounding requirements, which may result in significant negative consequences. The novice may be surprised to observe that electrical and electronics experts find the issue of grounding so complex. “After all,” they may say, “what could ever be so difficult in connecting the ‘zeros’ all together?” The truth is that grounding problems, if not properly addressed in the early phases of design, are bound to surface at the end of the project, at which time a solution is likely to be both costly and complex. With budget and schedule virtually depleted in the panic of finding a solution, attempts may be made to modify the grounding system layout and design by disconnecting, reconnecting, removing, or adding grounding connections randomly in a trial-and-error approach. It is at this time that critical conflicts may be overlooked and safety-compromising situations may not be acknowledged. When the attempts seem to yield good results, the solution is called “successful,” leading all to believe that grounding system design is indeed founded in “black magic.” 2 Cadence® PSpice® technology combines industry-leading, native analog, mixed-signal, and analysis engines to deliver a complete circuit simulation and verification solution. URL: https://www.pspice.com/. 3 Source: Paul, C. (2002). IEEE EMC Society Newsletter (192), Winter 2002.

1 Overview

The typical electrical or electronics engineer will often avoid highly mathematical electromagnetic field theory. After all, “Physics is for the physicists,” right? Wrong! All answers to electrical and electronic design questions, particularly those related to grounding questions, are well founded in electromagnetic field theory, more specifically, Maxwell’s equations. In any discipline, lack of knowledge and comprehension of the science behind the rules may bring about the use of “rules of thumb,” resulting in either inadequate design, faulty or lacking (and possibly hazardous) results, or, worse still, overdesign, and, thus, a costly solution. It Turns Out That EMC is Not Black Magic — Kristin Pollock “Rules of thumb,” by their very essence, divest the engineer of his common sense and true engineering judgment. Such rules, which may have been appropriate years or decades before, are likely not applicable to new technologies. More importantly, they may not be compatible with current safety codes, which may have evolved independently through the years. Applying those rules of thumb may be inappropriate for the intended application (e.g. EMI control) or may introduce serious violation of current safety requirements. Many of these rules of thumb are like urban myths, evolved from misconceptions regarding grounding, and their use should be discouraged. Most misconceptions and rules of thumb related to grounding theory were established in previous generations and were directly applicable to technology available at the time. For example, how often do design engineers still recommend singlepoint grounding topologies in their high-speed digital circuits? Or still think that cable shields should be grounded (or terminated) at one end only? Or still use the 0.1 μF capacitors for decoupling of high-speed digital devices having rise/fall times in the order of tens of picoseconds? A digital signal is actually an analog signal with an (almost) infinitely high slew-rate — Mark Montrose Consider, for instance, the evolution of computing speeds and edge rates coupled with the increased density on printed circuit boards. Today’s digital circuits have gradually evolved into RF circuits, with their edge rates well in the 10s of picosecond range (Figure 1.2) and the subsequent frequency spectral content exceeding 10 GHz. The increase of switching speeds implies an increase in high-frequency spectral content, virtually from DC to daylight, leading to greater significance of parasitic reactive effects and heightened emissions and interference. In fact, cable conductors and PCB traces literally “resist evolution”: traditional PCB materials such as FR-4 and common twisted wire pairs become overly lossy and are no longer appropriate for high-speed signal propagation, requiring that new, more expensive technologies be applied. Rules of thumb developed decades ago will not suffice for contemporary technology. Traditional analog or digital design rules of thumb will not provide functional grounding system design or help control EMI either, and many, in fact that employ transmission line theory, for instance, are necessary today for explaining high-frequency effects encountered in modern circuits. Use of such techniques will yield appropriate grounding schemes, providing both performance and EMI control while not compromising safety. 4.0 V 3.5 V 3.0 V

2ns

6 ns

Vinput

2.5 V

ALVC 244

LV244

2.0 V 1.5 V

AFC 244

1.0 V

LVC 244

0.5 V LVT 244

0.0 V

VCC = 3.3 V Load = 500 Ω/50 pF

–0.5 V –1.0 V 0 ns

2 ns

4 ns

6 ns

8 ns

Figure 1.2 Trends in edge rate increase.

10 ns 12 ns 14 ns 16 ns 18 ns 20 ns

3

4

1 Overview

Grounding design for modern systems must cover many disciplines, including mixed digital and analog circuit design, power engineering, lightning protection, and many others, not to mention system safety concerns. Rather than an intuitive approach, the design of the grounding system must be founded on electromagnetic field theory, in particular Maxwell’s equations.4 A practical approach must be maintained, in consideration of safety and other codes and regulations, and conflicting situations, which may arise due to contradicting requirements in practical systems. A key objective of this book is to dispel the mystery associated with grounding and bringing grounding and bonding “down to earth.” This shall be accomplished by providing a methodical approach for the design of grounding systems, from circuits through systems and up to platforms and facilities. The book attempts to meet the above challenge by putting grounding into the proper perspective. It outlines a physical foundation for explaining the concept of grounding, founded on electromagnetic field theory, while providing insight into practical aspects of grounding system implementation, particularly as related to its interdisciplinary nature, extending from circuits to facilities. It will be clearly demonstrated that grounding systems in facilities, systems, or circuits do, in fact, follow a consistent scheme. From the topological perspective, there is no fundamental difference between a circuit, a rack, a platform, and a facility. The laws of electromagnetics revealed in Maxwell’s equations remain unchanged regardless of the system dimensions. Only the manner and complexity of their application differ from one to the other. In practice, though, circuit and equipment designers are electronic engineers, whereas the facility and platform designers are electrical engineers. The crossroad between the two, electronics and electrical engineering, also constitutes the borderline between power levels (millivolts and kilovolts, microamps and kiloamps) and, of greater significance, between frequency contents, particularly power frequency to signal frequencies ranging from DC to daylight. Integrating equipment and systems in a large facility does require not only a new way of thinking and different comprehension of terms but also a distinctive appreciation of numbers; the difference in units of measurement affects their actions because “they work on the opposite side of the decimal point” [1]. Can an electronic circuit designer truly internalize a 200 kA lightning return stroke current? And what concern are milliamperes to the electrical power engineer? This book is thus also targeted at developing a universal approach to the understanding of grounding at whichever tier is considered, delineating the distinctiveness of each while emphasizing the resemblance between them, hoping to remove the present fuzziness. No doubt, the concepts presented herein may put several designers at unease. These concepts will conflict with the widespread notion that there is no scientific foundation for grounding, which is well known to amount to “black magic.” The theories and practices discussed herein will diverge from the body of “common knowledge” related to the way grounding should really be accomplished. Without a doubt, many may choose to carry on utilizing former practices, finding that easier than attempting to understand these concepts. It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness. — Charles Dickens in “A Tale of Two Cities” We have certainly made some foolish mistakes, been partners with others’ mistakes, but hopefully learned from them. Hopefully, this book will help you learn from ours.5 We are confident that, eventually, this book will help to do away with old, outdated, and erroneous practices, which may have been acceptable where low frequencies were concerned but constitute poor design practices for the high-frequency circuits and systems so widespread today. Application of theory, observing physics principles working in practice, and proving Maxwell’s equations’ validity for grounding and EMC design practices have provided particular satisfaction and made this book, in the authors’ opinion, of even greater consequence. The goal of this second edition of the book is to provide both the novice and the experienced, whether beginners, students, researches or the practicing engineers, an understanding of grounding theory and implementation. It provides the understanding of why grounding is critical to circuit and system design, what are the primary aspects of grounding design, key driving parameters that govern grounding performance, and various commonly implemented schemes of grounding. I have made this letter longer than usual because I lacked the time to make it short. — Blaise Pascal

4 A detailed discussion of Maxwell’s Equations as they apply to grounding theory and practices is presented in Chapter 2. 5 Based on a quotation from Andre, P. (2020). Doing Things That Usually Do Not Work. Interference Technology. https://interferencetechnology.com/ doing-things-that-usually-do-not-work/ (accessed 9 November 2020).

1 Overview

Completely revised and updated, this second edition highlights recent scientific data, changes in terminology, important developments, and provides a superb grounding for new insights in the discipline (of grounding…). Similar to the first edition, the authors, in this engaging second edition, open with a discussion of the fundamental science and concepts required to comprehend the fundamentals of grounding. Fully revised chapters with new and additional examples and source material provide a lively, easily accessible overview of the full range of applications and techniques of grounding in circuits, systems, and facilities. Among the topics expanded is discussion of grounding and earthing in facilities and in power distribution networks. Filled with case studies, supporting examples, and ideas, drawn from practical engineering experience, this second edition brings industrial applications into perspective with the material being discussed. As in the first edition, the text also includes a pictorial illustrative approach to better demonstrate the principles discussed and implementation practices. Consolidating relevant topics into a logical sequence, this second edition provides a concise source of useful information that can be easily translated to the “real-world” and prepares the reader to make educated decisions in future industrial applications. With this in mind, the book begins by taking the reader back to the grassroots, introducing him to the fundamental concepts pertaining to grounding, commencing with a discussion of Maxwell’s equations, particularly as they apply to the topic of grounding. The surprisingly misconceived concept of “electrical current,” “flow of electrons” vs. propagation of “current” in transmission line structures is discussed. Finally, essential terms and understanding of the nonideal nature of passive (R-L-C) electrical circuit components are extended to time-domain, providing new insight to behavior of such components and are also laid out in Chapter 2. Chapter 3 presents the basics of grounding, beginning with a discussion of the term “ground” and the different objectives of grounding. This chapter remains virtually unchanged (with small additions and updates) from the first edition. Chapter 4 provides an in-depth review of the fundamentals of grounding design. It discusses in detail the fundamental topologies of grounding systems and provides a novel yet practical systematic approach for planning grounding systems. The concept of “ground loops” is developed in Chapter 4 and solutions are presented. The implementation of the fundamental grounding architectures in large-scale systems and installation are further examined. In the second edition, the groundingrelated case studies have been moved from Chapter 4 to the (new) Chapter 14 (“Testing and Troubleshooting Grounding Problems”). Chapter 4 is supplemented with the “Grounding Verification Checklist and Procedures” to be found in (the new) Appendix G. Chapter 5 explains the principles of electrical bonding. The approaches for achieving low-impedance connections between metallic surfaces and structures as a fundamental objective for meeting the desired grounding objectives are portrayed. To better understand and explain the mechanism of corrosion, this chapter is expanded to include the basic electrochemical kinetics of corrosion, describes the adverse effects of corrosion on EMC performance of electronic systems and presents the design measures for corrosion control. The content of Chapter 6 (in the first edition of the book), which addressed safety-related grounding concerns, including grounding in power distribution networks and in lightning protection systems, has now been extensively expanded in this second edition and broken down into five chapters namely, Chapters 6 through 10. Chapter 6 describes in detail predominantly safety-related grounding concerns in power distribution networks, in particular, the national electric grid. Rationale for electrical safety grounding requirements is provided and safety grounding (also known as “earthing”) design principles in various power distribution network schemes are presented. Unlike Chapter 6, which addresses grounding in the widely distributed national electrical power grid, the (new) Chapter 7 focuses on the unique aspects of “local” power distribution networks, such as generators and uninterruptible power supplies (UPSs). On the other hand, Chapter 7 addresses grounding concerns in sensitive electronic equipment and instrumentation, often associated with the power network monitoring and control systems. The (new) Chapter 8 focuses on the particular aspects and requirements of grounding in lightning protection systems. The specialty of this topic justified the breakout of this topic from the old Chapter 6 and dedicating it to a separate chapter. Lightning protection systems must handle high-energy, short duration current surges and as such, their design largely diverges from the nature of electrical power system grounding. In fact, one of the reasons for this disengagement was to dispel the misconception that the two may be equivalent. Wrong! Whereas the grounding (or “protective earthing”) system continuously performs its “fault protection” function during operation of the power system, but under normal conditions carries no current (excluding minimal leakage), the lightning protection and associated grounding systems should be dimensioned for the lightning impulse conditions, hence denoted “impulse grounding.” This impulse grounding system functions only for the duration of the discharge surge. Chapter 9 replaces the old Chapter 10 (which was relocated) and leads the reader to the facility and platform levels. The design of integrated grounding systems in facilities (incorporating all functions, “technical” (functional), electrical fault protection, and lightning protection is described. The complexity of and approaches to the integration of multiple subsystems into a larger system as pertaining to grounding system design are explained. Chapter 9 also expands the concept of grounding architecture design to the unique cases of fixed and mobile C4ISR (Command, Control, Communications, Computers, Intelligence, Surveillance, and Reconnaissance) facilities and platforms such as tactical shelters, aircraft, launch vehicles, and ships.

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6

1 Overview

Exclusive aspects of grounding in secure facilities, where separation of “red” and “black” circuits6 (and their associated grounding systems) is reviewed. The (new) Chapter 10 addresses the earth connection. This chapter particularly addresses the nature of the earth, and its impact on the earthing design, such as the scheme the earth electrode subsystem (EESS) and number of necessary electrodes, the design criteria and methods of verification, and measurement of earth resistance. This chapter combines the needs of the various earthing and grounding systems discussed in the preceding chapters, 6 through 9. Chapter 11 covers grounding in wiring and cable systems. One of the most controversial and misunderstood aspects of system grounding design stems from the question of cable shield termination (“grounding”). This chapter will clearly make a distinction between signal grounding and shield termination, putting this question at rest. Essentially, this chapter differs very little from Chapter 7 of the first edition but incorporates a new section on grounding in common balanced signal circuits such as RS-422/RS-485, LVDS, USB, and Ethernet. In particular, the difference between “balanced” and “differential” is clarified, dispelling the (incorrect) notion that RS-422/485… are independent of ground noise. Chapter 12 provides the foundation for understanding the essential necessity of adequate grounding of EMI terminal protection devices (e.g. EMI filters and transient suppressing devices) performance. The effect of acceptable versus objectionable grounding of such protective devices is clearly demonstrated. This chapter remains essentially unchanged but does address, from the grounding perspective, the common (and efficient) technique of terminal protection implementation, i.e. in the connectors. Benefits and drawbacks of this technique will be covered. In Chapter 13, the application of grounding in printed circuit boards (PCBs) is discussed in depth, particularly as related to signal propagation and signal integrity (SI), power distribution and power integrity (PI), and a three-dimensional (3D) consideration of signal current return paths. The question and dilemmas associated with grounding in mixed analog/digital circuits is also addressed. This chapter has been broadly revised from Chapter 9 of the first edition. Chapter 14 is new and addresses testing and troubleshooting of ground-coupled interference and the subsequent grounding problems. In this chapter, the general approach for systematic EMI diagnostics will be presented and, particularly, will focus on troubleshooting grounding and bonding “situations.” “Real-life” grounding, bonding, and earthing case studies are included to supplement the “theoretical” introduction of this chapter. The appendices in the book provide extensive supporting information and supplemental data, which will be of great use for the reader. Appendix A provides an extended glossary of grounding-related terms and definitions, with references to their sources, particularly when derived from official international standards and codes. When several definitions exist for a term, they are all included, with reference to the context of their applicability. Appendix B lists commonly used acronyms employed throughout the book for easy reference by the reader. In this second edition, new, useful terms, definitions, and acronyms have been added in the above appendices. Appendix C presents commonly used symbols associated with variables referred throughout the book. Appendix D provides tables of values of fundamental properties used across the Book. Appendix E (previously Appendix D) presents a broad list of many grounding and earthing-related standards, specifications, and codes and their scope. This list has been updated and expanded in this second edition. The (new) Appendix F presents practical experiments for demonstration of grounding and bonding-related principles, which can be applied for demonstration of the physical principles associated with grounding and bringing theory “down to earth.” The (new) Appendix G and Appendix H provide a grounding design and verification checklist and procedures and a list of the necessary content of grounding engineering documentation, respectively. Both these appendices are intended to be useful particularly for the practicing engineer for validation of the system grounding design and the documentation of such design. Appendix I (previously Appendix E) demonstrates the equivalence between Ohm’s Law and Fermat’s “Least Time” Principle, which is useful for understanding the reason why return (or “ground”) current selects a particular return path, while multiple paths appear to be available. The (new) Appendix J provides some thoughts and results of discussions regarding low-frequency return current distribution. This discussion emerged from the (well-known and documented) pattern of high-frequency current return paths (a.k.a. the “Path of Least Inductance” principle). It turns out that at the lower frequencies, no closed-form expression exists to describe this current return pattern. This appendix tries to shed some light on the question and to provide some insight into the (initially unperceived) complexity of this question. Appendix K (formerly Appendix F) provides an (updated) overview of S-parameters and their application for the evaluation of grounding performance, particularly on printed circuit boards, extensively used in Chapter 13. The (new) Appendix L provides a sample practical assessment of “common-impedance coupling,” which may form a basis for tailoring ground-coupled interference requirements and test levels for equipment-level verification. Finally, the (new) Appendix M includes a multiple-choice “Grounding and Bonding Test Yourself Quiz.” Check and see how many questions did you get right… With the emergence of new technologies – nanotechnology and composite materials in particular – the importance of proper grounding and bonding design is greater than ever. We are certain that this book, founded on fundamental physical principles 6 The “red/black” concept, sometimes called the red/black engineering, refers to the careful segregation in cryptographic systems of signals that contain sensitive or classified plaintext information (“red” signals) from those that carry encrypted information, or ciphertext (“black” signals).

References

on the one hand and on real-world, practical experience on the other, provides an excellent resource for achieving successful, cost-effective, and timely state-of-the-art designs of electronic and electrical equipment, systems, and networks. The authors of this book have been working, for many decades, in the design of grounding systems from circuits to systems, and from installations and facilities to platforms and vehicles. We have found that regardless of application, the fundamentals remain “the fundamentals.” We hope and trust that this book from the fundamentals to the advanced topics is brought to light and made tangible to the readers uninitiated to grounding design and that the experienced will likewise find utility in this book for explaining and clarifying topics that during their typical, busy work day they have had no time to research and investigate. We much enjoyed writing this second edition of our book and it is our sincere hope that the reader will enjoy reading it too. To conclude, we should like to articulate a vision – which coincides with ours – of the craft of explaining science to a large audience: Do not talk down. Try to inspire everybody with the poetry of science and make your explanations as easy as honesty allows, but at the same time do not neglect the difficult. Put extra effort into explaining to those readers prepared to put matching effort into understanding. [2]

References 1 Brokaw, P., “An I.C. Amplifier Users’ Guide to Decoupling, Grounding, and Making Things Right for a Change,” Application Note,

Analog Devices, 1982. 2 Dawkins, R. (1996). Climbing Mount Improbable. New York, USA: W. W. Norton & Company, Inc.

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9

2 Fundamental Concepts

Success is neither magical nor mysterious. Success is the natural consequence of consistently applying the basic fundamentals. — Jim Rohn Most of the fundamental ideas of science are essentially simple, and may, as a rule, be expressed in a language comprehensible to everyone. — Albert Einstein Understanding grounding and, particularly, application of grounding design principles is close to impossible without a basic understanding of the fundamental concepts of electromagnetism. Dr. Howard Johnson, in his article “Why Digital Engineers Don’t Believe in EMC,” [1] points out some of the most fundamental errors of digital design engineers. Two of those deserve special attention: 1. Digital engineers do not believe current flows in loops. 2. Digital engineers do not believe in H-fields. In this chapter, the concepts of the path of current flow and magnetic (H) fields constitute examples of such basic fundamentals, without which the concept of grounding literally can neither be rationalized nor properly applied.

2.1

Maxwell’s Equations Demystified From a long view of the history of mankind – seen from, say, ten thousand years from now - there can be little doubt that the most significant event of the 19th century will be judged as Maxwell’s discovery of the laws of electrodynamics. — Richard P. Feynman

Electromagnetic (EM) phenomena are characterized by Maxwell’s equations, a set of four fundamental equations governing electromagnetism (i.e. the behavior of electric and magnetic fields). James Clerk Maxwell is generally regarded as the greatest theoretical physicist of the nineteenth century and is recognized as the “Father of Electromagnetic Theory.” His field theorybased framework for the laws governing EM phenomena at large (or macroscopic) scales, unified into a single body, a set of mathematical equations deduced earlier (through experimental observations) by Coulomb, Gauss, Oersted, Faraday, Ampere, and others. In Part III of his 1864 paper, “A Dynamical Theory of the Electromagnetic Field,” entitled “General Equations of the Electromagnetic Field,” Maxwell formulated eight equations, labeled (A) to (H). In this paper, Maxwell utilized the correction to Ampere’s original Circuital Law equation, introducing, in Part III of his 1861 paper, “On Physical Lines of Force,” a new displacement current quantity. In Part IV of the 1864 paper, Maxwell modified Ampere’s Circuital Law to include displacement current with some of the other equations of electromagnetism. This displacement current term played a key role in Maxwell’s theoretical prediction of the existence of EM waves and obtained a wave equation with a speed equal to the speed of light, well before they were produced and detected experimentally, commenting: The agreement of the results seems to show that light and magnetism are affections of the same substance, and that light is an electromagnetic disturbance propagated through the field according to electromagnetic laws. Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

10

2 Fundamental Concepts

This displacement current term also facilitated Maxwell’s unification of the different mathematical laws of electromagnetism into a single, consistent framework. Furthermore, Maxwell showed not only the existence of EM waves, but also demonstrated that EM waves travel with a finite velocity, the speed of light. The latter finite velocity therefore directly requires a finite propagation time for the wave to travel from its origin to a distant point, clearly in stark contrast to the Newtonian instantaneous action-at-a-distance concept. Maxwell’s original derivation of the eight EM wave equations were to become known as “Maxwell’s equations,” until, in its modern physics form, this mathematical framework was transformed into a much less cumbersome set of four compact vector equations, in either differential or integral form, known today as the “Heaviside form of Maxwell’s equations.” This compact form of Maxwell’s equations in vector notation was given in 1884 by Oliver Heaviside. Heaviside’s versions of Maxwell’s equations are distinct by virtue of the fact that they are written in modern vector notation. They actually only contain one of the original eight, equation (G), “Gauss’s Law.” Another of Heaviside’s four equations is an amalgamation of Maxwell’s Law of Total Currents [equation (A)] with Ampere’s Circuital Law [equation (C)], actually originally made by Maxwell himself in equation (112) in his 1861 paper, “On Physical Lines of Force.” Although not developed by him, his successful interpretation of Faraday’s concept of the EM field resulted in four field equations bearing his name.1 Formidable mathematical ability combined with great insight enabled Maxwell to lead the way in the study of the two most important areas of physics of his time [2]. When I start describing the magnetic field moving through space, I speak of the E- and B-fields and wave my arms and you may imagine that I can see them. I’ll tell you what I see. I see some kind of vague shadowy, wiggling lines—here and there is an E and B written on them somehow, and perhaps some of the lines have arrows on them—an arrow here or there which disappears when I look to closely at it. I cannot really make a picture that is even nearly like the true waves. — Richard P. Feynman (The Feynman Lectures on Physics; Vol. II; California Institute of Technology, 1989) Considering also Maxwell’s earlier mechanistic interpretations of the nature of a field, it becomes evident that even the best scientific minds are still unclear about many basic ontological questions regarding the nature of an EM field. That is, no clear mental picture can be drawn in which the field appears limpidly and uniquely. “Faraday’s Lines of Force” were, as Maxwell puts it, “the key to the science of electricity.” However, when firmly scrutinized, the exact nature of a field shifts and squirms like Proteus under Menelaus’ grasp. In fact, in 1905, Einstein’s special theory of relativity, which was developed to describe particle dynamics at high velocities (i.e. a substantial fraction of the speed of light), required the speed of light to be invariant; i.e. independent of any inertial frame of reference in which it is measured. It is noteworthy, in this regard, that the laws of Newtonian mechanics are invariant only with respect to the Galilean velocity transformation between different inertial reference frames in relative motion. The speed of light, however, is not invariant with respect to the Galilean transformation since the latter assumes a “universal” time. Time, therefore, not the speed of light, is considered invariant in the Galilean transformation. Maxwell’s equations, which predict that EM waves propagate with the speed of light, turn out to be not invariant with respect to the Galilean transformation. It was Lorentz, however, who had already demonstrated earlier that Maxwell’s equations remained invariant with respect to a different transformation, which, following Einstein’s theory of relativity came to be known as the Lorentz transformation. At sufficiently low velocities (compared to the speed of light), the Lorentz transformation reduces, of course, to the Galilean transformation; thus, Newtonian mechanics, although not relativistically accurate, becomes valid at sufficiently low velocities. For completion of the discussion, it would be suitable to mention that Einstein later developed a field theory for gravitation (general theory of relativity) in 1916; in this sense, Einstein did to gravitation what Maxwell did to electromagnetism. Concurrently, and following Einstein’s theory of relativity, the notions of quantum mechanics began to develop. It was noted that, at very short wavelengths, light exhibits quantum effects, whereby light energy propagates in discrete bundles or light quanta called photons. Nevertheless, it is now well known that at sufficiently low frequencies, EM fields (e.g. visible light) exhibit a wave character since the energy of each photon which is directly proportional to the wave frequency, is thus relatively small. Hence, the macroscopic EM wave phenomena are seen to result from a statistical average over a large number of photons required to produce the energy generated by conventional EM sources. On the other hand, at microscopic scales and sufficiently high frequencies, the existence of a single photon becomes distinguishable. It follows that EM phenomena exhibit a dual nature, simultaneously exhibiting the nature of particles (or photons) and of waves. This scope of this book is restricted to the classical EM field theory. Even with this limited scope, Maxwell’s equations appear to be quite challenging from the mathematical point of view and their solution is not simple. But this is not to diminish their practical implication, especially with respect to the theory of grounding, particularly since the intuitive understanding of their concepts is quite simple. In reality, electromagnetics is not difficult, unless you want to do the “messy math.” These equations describe the distributed parameter nature of EM fields and sources, that is, how fields and their sources are distributed in space. However, quite often we may utilize approximations of these equations, such as applying quasi-static approximation, where 1 Physics World Magazine ranked Maxwell’s equations as the most important set of equations of all time.

2.1 Maxwell’s Equations Demystified

lumped-circuit models are utilized in order to simplify analysis in certain cases, when dimensions of the problem are electrically small. Engineering is the art of approximation. — Dr. Eric Bogatin Maxwell’s equations form a set of partial differential equations, the variables of which are functions of the spatial parameters (e.g. x, y, z) in three-dimensional Cartesian space coordinates, as well as time (t). Accordingly, the E and H fields are time (t) and position dependent, but for the purpose of simplicity, the notation E rather than E(x, t) will be used. In this section, only a brief overview of Maxwell’s equations is presented, with practical implications of these equations to the understanding and design of grounding theory. If you prefer not to be challenged by the concepts outlined in this section and, particularly, Maxwell’s equations, you may skip the remainder of Section 2.1. However, though the knowledge of Maxwell’s equations is not required for the actual design of grounding systems, the understanding of the elementary concepts expressed by them, two in particular to be precise, is important. It is difficult to consider a scientific approach for grounding without their knowledge. The reader is therefore encouraged to pursue the discussion delineated in this section.

2.1.1 Fundamental Terms Maxwell’s equations are described in terms of vector and scalar values. The following are vector values: E = Electric field strength (V/m) D = Electric flux density (C/m2) H = Magnetic field strength (A/m) B = Magnetic flux density (Tesla) J = Conduction current density (A/m2) The following are scalar values: Q = Charge (C) ρV = Volume charge density (C/m3) Vector fields are italicized, with the vector notation above (for instance, if A is a vector field, it will be presented as A). Other vectors (e.g. position and velocity) are italicized, such as v for velocity.

2.1.1.1

Electric Charge

It would be most appropriate to begin by recognizing the basic source of EM fields to be the electric charge Q. Assuming that an amount of charge Q (in Coulombs) is distributed in a given volume, V, we may define a corresponding macroscopic volume charge density, ρV, in Coulombs per cubic meter (C/m3), within V using: Q = ρV dv

21

V

where Q is the total charge within the volume, V. Note that ρV is a function, varying with position and time.

2.1.1.2

Conservation of Charge and the Continuity Equation

A fundamental postulate in EM field theory is that charge is always conserved; i.e. charge cannot be created or destroyed.2 However, equal amounts of positive and negative charge can be made to appear by separation or made to disappear by recombination. Also, charge is assumed to have the same value whether it is in motion or at rest. Any net motion of charges along a specific path constitutes a current, I (in Amperes, A). In particular, the current, I, which flows across any surface, S, is defined equal the rate at which charge crosses that surface. Hence, the rate of decrease of charge within a volume, V, enclosed by a closed surface SV, constitutes an outward flow of current I, across that surface via conservation of charge. I therefore represents a transfer of incremental charge, ΔQ, from the region internal to the volume, V, to the region external to it in an incremental time step, Δt (as Δt 0); i.e. 2 A continuity equation, or transport equation, is an equation that describes the transport of some quantity. It is particularly simple and powerful when applied to a conserved quantity. Since mass, energy, momentum, electric charge, and other natural quantities are conserved under their respective appropriate conditions, a variety of physical phenomena may be described using continuity equations.

11

2 Fundamental Concepts

V

V

q S1 j1

q

V Q

S2 j2

n^ SV

(a)

(b)

Figure 2.1 The flow of current, I, flowing through surface, SV, vis equal to the rate of decrease of charge, Q, in the volume, V. (a) Illustration of a generalized continuity equation: flux, j, of a quantity, q, flows through an open surface, S. Source: Maschen (2011)/Wikipedia/public domain. (b) Illustration of the continuity equation applied to electrical charge transport, or current.

I = lim − Λt

0

ΔQ dQ d = − ρ dv = − Δt dt dt V

22

V

where Q can be either positive or negative. The volume current density, JV (in A/m2), is similarly defined at any point to be equal in magnitude to the charge crossing per unit area of a surface in unit time at that point; the direction, JV, is along the path of the charge motion across the surface at that point. The current, I, flowing across the surface, SV, due to decrease of charge within, V, bounded by SV, can thus be expressed as (Figure 2.1): ↻

I=

SV J V

23

nds

where n is the outward unit vector normal to the surface, SV. By equating the definitions of current in Equations (2.2) and (2.3) above, we obtain: ↻

12

SV J V

nds = −

d ρ dv = I dt V

24

V

Applying the divergence theorem to the left-hand side of Equation (2.4), and assuming that SV is stationary (thus the order of the time derivative operator in Equation (2.4) and the volume integral operation on the right-hand side of Equation (2.4) can be interchanged), leads to: ∇ JV +

dρV dv = 0 dt

25

V

Equation (2.5) is true for any volume, V, therefore: ∇ JV = −

dρV dt

26

The above relation expresses the principle of Conservation of Charge, or the Continuity Equation. Equation (2.6) clearly demonstrates that any sudden appearance or disappearance of charge must always be accompanied by a corresponding and simultaneous flow of electric current and thus constitutes one of the most fundamental equations in EM theory.

2.1.1.3 Electric and Magnetic Forces and Fields

Electric and magnetic fields are defined through the forces they exert on charged particles. An electric field, E, represents the force, F, applied on a discrete charge, q: E=

F q

27

2.1 Maxwell’s Equations Demystified

In the absence of an electric field, no force will be exerted on a charge when it is at rest. However, if a charge moves with velocity v, force is introduced, attributed to a magnetic field. The direction of this force is rather interesting as the force is perpendicular to the velocity and vanishes if the velocity is in some particular direction. For forces of this nature, the magnetic field is defined such that v×B=

F q

N S

N

28 S

If isolated magnetic charges (or “magnetic monopoles”) were to exist, stationary magnetic charges, qm, would have experienced forces due to the magnetic field, B, and if in motion, would have experienced a force v × E. However, magnetic charges, so painstakingly sought by physicists, have not been identified yet.3 For instance, it is impossible to create magnetic monopoles from a bar magnet. If a bar magnet were to be cut in half, it is not the case that one half has the north pole and the other has the south pole. Instead, each piece has its own north and south poles. Hence, a magnetic monopole cannot be created from normal matter such as atoms and electrons, but would instead be a new elementary particle (Figure 2.2). Both electric and magnetic fields are combined into the Lorentz Law of Force: F =q E+v×B

N

S

Figure 2.2 It is impossible to make magnetic monopoles from a bar magnet. Source: Sbyrnes321 (2011)/Wikipedia/ public domain.

29

F

The electric force is straightforward, being in the direction of the electric field if charge q is positive; however, the “×” product in Equations (2.8) and (2.9) denotes the “cross product” by which the unique directional properties of the magnetic field on the moving charge are demonstrated in Figure 2.3. q (V × B) 2.1.1.4

Biot–Savart Law

qE

The Biot–Savart Law relates magnetic fields to current, which constitute their sources. From [3], taken as an arbitrary source, it can be observed that the magnetic field resulting from a current distribution along a conductor can be derived using the Biot–Savart law. Figure 2.4 illustrates the manner in which magnetic fields surround a wire carrying a current I. Each infinitesimal current element Idℓ contributes an infinitesimal magnetic field dB, which is perpendicular to the current element and to the radius vector, r, from the current element to the field point P. The relationship between the magnetic field contribution and its source current element is called the Biot–Savart Law, dB =

μ0 Idℓ × r 4πr 2

E +q

B

θ V

Figure 2.3 Lorentz Law of Force. Source: Maschen (2012)/ Wikipedia/public domain.

2 10

The direction of the magnetic field contribution follows the right-hand rule illustrated for a straight wire. This direction arises from the vector product nature of the dependence upon electric current.

2.1.2 Maxwell’s Equations As aforementioned, Maxwell’s equations combine into a single framework, the separate laws of electromagnetism derived experimentally by Gauss, Faraday, and Ampere (amended by Maxwell’s inclusion of the displacement current), together with an equivalent of Gauss’s Law for magnetic fields. This system of laws clearly demonstrates their inter-relationships and is expressed in a form of four fundamental equations, in either differential or integral form, summarized as follows (Figure 2.5):

3 Experimental searches for magnetic monopoles can be placed in one of two categories: those that try to detect pre-existing magnetic monopoles and those that try to create and detect new magnetic monopoles. Since 2003, approximately, various condensed-matter physics groups have used the term “magnetic monopole” to describe a different and largely unrelated phenomenon. A true magnetic monopole would be a new elementary particle, and would violate Gauss’s Law of magnetism ∇ B = 0. Such a monopole has never been observed in experiments.The monopoles studied by condensedmatter groups have none of these properties. They are not a new elementary particle but rather an emergent phenomenon in systems of common particles (protons, neutrons, electrons, and photons); i.e. they are quasi-particles. They are not sources for the B-field (i.e. they do not violate ∇ B = 0) but of various other quantum fields (Source: https://en.wikipedia.org/wiki/Magnetic_monopole).

13

2 Fundamental Concepts

The differential form of Maxwell’s equations is: Gauss’s Law for Electric Field ∇ D = ρV

2 11

Gauss’s Law for Magnetic Field ∇ B = 0

2 12

P

Faraday’s Law of Induction ∇ × E = −

dB r

Ampere’s Law ∇ × H = J V +

rˆ

∂B ∂t

2 13

∂D ∂t

2 14

In the above equations, the intrinsic vector ∇ (del) operator, for instance, in a Cartesian coordinates system (x,y,z), denotes: Figure 2.4 Biot–Savart Law, magnetic fields surrounding a current-carrying wire.

∇

∂ ∂ ∂ + + ∂x x ∂y y ∂z z

2 15

The integral form of Maxwell’s equations is: D nd s = Q = ρV dv

Gauss’s Law for Electric Field

V

SV

2 16 Gauss’s Law for Magnetic Field

B ds = 0

2 17

S

E dl = −

Faraday’s Law of Induction C

H dl =

Ampere’s Law C

S

J + S

∂D ∂t

ds

∂B ds ∂t

2 18

2 19

The two equation sets, Equations (2.11) through (2.14), and Equations (2.16) through (2.19), are sometimes referred to as the dynamic Maxwell’s equations, since they have an explicit time dependence Figure 2.5 Maxwell’s “Field Equations.” Source: Cartoon Courtesy of Tayfun Akgul. built into them. The interactions described in the dynamic equations form the basis for understanding EM compatibility and in particular, grounding theory. As shown earlier, the fundamental sources depicted in Maxwell’s equations are charge and current density, defined through the relations,4 -Let 's call them "The Field Equations"

ρV = lim V

0

Q I and J = lim SV 0 SV V

2 20

where Q is the total charge in the volume V in coulombs (C) and I is the total current flowing through the cross-section area SV. With relation to these sources, the last relationship portrays the principle (discussed earlier) of Conservation of Charge, or the Continuity Equation: ∇ JV = −

dρV dt

2 21

Equation (2.21), depicted earlier in differential form, can also be depicted in integral form: ↻

14

SV J V

nds = −

d ρ dv = I dt V V

Figure 2.6 depicts the inter-relationship between the equations and the key values. The following is a short discussion of Maxwell’s equations, unfolding their physical significance.

4 Observe that currents and charges, not voltages and potentials, appear as sources in Maxwell’s equations.

2 22

2.1 Maxwell’s Equations Demystified

Figure 2.6 Maxwell’s equations and their interrelationships.

→

→ →

→

→

×q

→

–∇V( r )

– F∙ds

Electric potential

Scalars

Electric force

→ →

–∇V( r )

– E∙ds

2.1.2.1

×q

Electric field

Vectors

Potential energy

Gauss’s Law for Electric Field

Maxwell’s first equation, also known as Gauss’s Law for Electric Fields or the Divergence Theorem, in its differential and integral forms (Equations (2.11) and (2.16)), is expressed as: D nd s = Q = ρV dv 2 23

V

SV

∇ D=ρ Gauss’s Law in integral form (top expression in Equation (2.23)) states that the total electric flux leaving a closed surface, SV, must equal the total charge, Q, enclosed within the volume, V, bounded by the surface, SV. The electric flux is defined in terms of an electric flux density vector, D (in C/m2). It simply states that the net electric displacement emerging from a closed surface is equivalent to the net positive charge enclosed by the surface. Electric flux that begins at a positive charge must terminate at an equal negative charge (Figure 2.7). An implication of Gauss’s Law for Electric Fields is that any net electric flux emerging from an enclosed volume indicates the amount of net charge enclosed within that volume (Figure 2.7a). When the total emerging flux from the volume is zero, it suggests that either there is no charge in the volume, or that the enclosed positive and negative charges are equal (Figure 2.7b). It follows, therefore, that D ds =

0, Q outside S Q, Q inside S

2 24

S

A unique inference of this law, related to a charged piece of metal, is that, regardless of its shape and if current is zero, the electric field inside the piece of metal must be zero. Free charges in metal go to the surfaces of the metal and arrange themselves so that the electric field is zero everywhere inside the metal. Electrostatics is a linear theory, so equilibrium charge distribution is unique, that is, there is only one arrangement of charges on the surface, which produces zero electric field everywhere inside

→

dA

–

+

(a)

–

+

(b)

Figure 2.7 Gauss’s Law for E-fields. (a) Electric flux through an arbitrary surface is proportional to the total charge enclosed by the surface. (b) No charge is enclosed by the sphere and thus the net electric flux through its surface is zero. Source: MikeRun (2020)/Wikipedia/public domain.

15

16

2 Fundamental Concepts

the metal. At equilibrium, there is no current in electrostatics so the electric field at the surface of a conductor is perpendicular to the surface of the metal everywhere. Furthermore, a closed metal surface, regardless of its shape, screens out external sources of electric field. Stated in general terms, if there are no charges inside a volume totally enclosed by a metal surface, the electric field is zero everywhere inside that volume. Subsequent to Gauss’s Law, in the case of AC circuits enclosed within a given volume, Gauss’s Law still holds and, keeping in mind that an AC circuit is balanced (i.e. no net charge, positive or negative) with respect to the total charge the DC electric flux emerging from the volume is zero. Charges are in motion, however, create time-variant magnetic fields which subsequently result in EM waves and radiation as observed in the wave equations: ∇2 E −

1 ∂2 E =0 ν2 ∂t 2

2 25

1 ∂2 H ∇2 H − 2 2 = 0 ν ∂t

where ν represents the velocity of the EM wave (“speed of light”). Such EM radiation is, in no way, in violation of Gauss’s Law, since charges are scalar values, producing static electric fields while the EM waves are a result of charges in motion (i.e. current and a vector value), and not the charges themselves. It is the motion that produces that radiation, not the charges alone. A shielded enclosure, which is an application of this phenomenon, is often called a “Faraday Cage,” after the physicist Michael Faraday, who built the first one in 1836. 2.1.2.2 Gauss’s Law for Magnetic Field

Applying a similar progression of ideas as those above to magnetic fields and based on experimental evidence that isolated magnetic charges (“magnetic monopoles”) do not exist or that the magnetic flux, B, is always solenoidal, no Gaussian surfaces can enclose any net magnetic charge, implying that all magnetic flux lines form closed paths (Figure 2.8). We thus arrive at Maxwell’s second equation, also known as Gauss’s Law for Magnetic Field, in its differential and integral forms (Equations (2.12) and (2.17)): B nd s = 0 2 26

SV

∇ B=0 In other words, the net outflow of the total magnetic flux from any closed surface, SV, containing magnetic poles is zero because they occur only in opposite pairs so that the total magnetic charge within the volume, V, bounded by SV vanishes. It follows that as much magnetic flux leaving SV (due to positive magnetic poles or magnetic charges in V ) also enters SV (due to negative magnetic poles in V whose value is exactly equal and opposite to the positive ones in V ), thus leaving a net outflow of magnetic flux from SV to be zero. From application of the divergence theorem to the integral-form equation (upper expression in Equation (2.26)), we obtain the differential-form equation (bottom expression in Equation (2.26)). 2.1.2.3 Faraday’s Law of Induction

Going to the south and circling to the north the wind goes round and round; and the wind returns on its circuit. — Ecclesiastes 1:6

→

B

Maxwell’s third equation (Maxwell’s Electrical Voltage Law), also known as Faraday’s Law of Induction or simply Faraday’s Law, in its differential and integral forms (Equations (2.13) and (2.18)) is N →

S

V

E dl = −

∇·B = 0 C

→

B SV

Figure 2.8 Gauss’s Law for H-fields. The net magnetic flux B through the surface of any closed volume is zero.

SC

∇×E= −

∂B ds ∂t

2 27

∂B ∂t

This equation reveals that the electromotive force (emf ) induced around a closed contour, C, is related to negative of the total time rate of change of the magnetic flux passing through a surface, SC, bounded by that contour. The notation ∇ × E is referred to as the curl of E, and can be thought of, loosely speaking, as quantifying the amount of “swirl” or

2.1 Maxwell’s Equations Demystified

Figure 2.9 Faraday’s Law of Induction: emf induced around a closed contour C due to timevarying magnetic flux through the surface, SC (the surface, SC, is subdivided into smaller incremental areas, ds. With dC representing the contour which bounds ds, the arrows show the counter-clockwise sense in which the path, dC, encloses the surface area, ds).

→

→ → → E•dl = – ∂B •ds ∂ t sc c

nˆ →

B (t)

C

→

ds

→

dC bounds ds SC

“circulation” of the vector field E. The curl itself is a vector. It points in the direction of the axis of the local swirl (Figure 2.9). The name Faraday’s Law of Induction is attributed to Faraday’s Law by extension from Equation (2.18), whereby it can be expressed as emf = E d l = − C

S

∂B ∂Φ ds = − ∂t ∂t

2 28

Equation (2.28) shows that in lumped circuits, emf induced into a loop (closed contour) is a result of the change of the total magnetic flux through that loop. The induced emf can be considered as a voltage source, Uin, induced into the circuit. Note, however, that emf is a distributed parameter, whereas the lumped model of a voltage source is valid in electrically small circuits only, using quasi-static approximation. When emf is generated by a change in magnetic flux according to Faraday’s Law, the polarity of the induced emf is such that it produces a current whose magnetic field opposes the change of the magnetic field B producing it (see Figure 2.10). This is manifested in the negative sign in Faraday’s Law, indicating that emf induced in a contour has a polarity that tends to generate an induced current, resulting in a magnetic flux opposing any change in the original magnetic flux that produced it.

→

ΔBincrease →

→

→

ΔBinduced

→

→

Binitial

Binitial

–

+ – emf + (a) Figure 2.10

ΔBdecrease

ΔBinduced

+

emf

–

emf

+ emf – (b)

Lentz’s Law: the emf induced in a contour will have a polarity that tends to produce an induced current resulting in magnetic flux

opposing any change in the original magnetic flux that produced it. (a) Increasing B. (b) Decreasing B .

17

18

2 Fundamental Concepts

This principle can easily be understood from the standpoint of conservation of energy. The energy volume density, η B , associated with a magnetic field of flux density, B, is expressed as

UZ1

2

Contour –C

Uin

→ →

E•dl = c

Σi UZi –Uin = 0

UZ2

Energy 1 B ηB = = Volume 2 μ

2 29

If, contrary to the above principle, induced emf were not to produce current opposing the original magnetic flux, the magnetic flux through the contour due to the induced current would increase the induced emf, Figure 2.11 Equivalence between Faraday’s Law and further aiding the increase in the magnetic field, eventually driving Kirchhoff’s Voltage Law in the absence of magnetic flux. energy buildup, η B , to infinity. This is obviously in contradiction to the principle of conservation of energy. From the standpoint of this principle, current must flow in the path such that energy stored in the consequent magnetic field is minimized. The negative sign in Faraday’s Law similarly demonstrates that time-varying currents will always seek to flow in the path constituting the smallest possible contour, C. This important principle is recognized for its own merit and is known as “Lenz’s Law,” expressed as: emf = − L

dI dt

2 30

where L is the inductance5 of the contour, C, defined as: B ds L≜

S

=

I

Φ I

2 31

A special case of Faraday’s Law occurs when no magnetic flux penetrates a surface bounded by a contour, i.e. Φ = 0. In this case, induced emf and consequently the sum of all voltages in the closed contour must be zero: E dl =

Ui = 0

2 32

i

C

Related to lumped-circuit theory, this is the formulation of Kirchhoff’s Voltage Law (KVL),6 illustrated in Figure 2.11. Faraday’s Law is by far one of the two most important aspects of Maxwell’s equations associated with grounding theory (the other being Ampere’s Law), forming the basis for the definition of inductance, discussed in Section 2.3. 2.1.2.4 Ampere’s Law

All the rivers flow to the sea, but the sea is not full. — Ecclesiastes 1:7 Faraday’s Law, discussed earlier, demonstrated that a time-varying magnetic field can produce an electric field. Similarly, Maxwell’s fourth equation, also known as Maxwell’s Electrical Current Law or Ampere’s Law (Equations (2.14) and (2.19)) acknowledges that, in addition to net movement of electric charge, currents as well as time-varying electric flux crossing through an area, SC, enclosed by a contour, C, can produce a magnetic field: H•d l = C

JV + SC

∇×H= J +

∂D •d s ∂t

2 33

∂D ∂t

In other words, Ampere’s Law states that the line integral of the magnetic field intensity, H, (A/m), around any closed contour, C, equals the total current crossing the surface area, SC, enclosed by C; thus, where JV is related to motion of charges and ∂D/∂t represents the displacement current density. 5 Inducrance is discussed later in this chapter. 6 Note that Kirchhoff’s voltage and current laws (KVL and KCL, respectively) apply in lumped-circuit models only. Voltages and currents obtained from them are valid only so long as the largest physical dimension of the circuit is electrically small; that is, much less than a wavelength at the frequency of excitation, f, of that circuit.

2.1 Maxwell’s Equations Demystified

Ampere’s Law reveals, therefore, that magnetic fields emerge from two sources. The first source is the electric field associated with the current flowing

Current, I

in the form of transported charge (conduction current), J = σE, and the second is the time-varying electric fields crossing a surface of a closed-loop circuit (displacement current), ∂D ∂t = ε∂E ∂t. Similar to Faraday’s Law, the notation V × H indicates that time-varying current, JV, or time-varying electric displacement D introduce a “swirl” or “circulation” to the vector magnetic field, H (or B). Therefore, for a current flowing in an upward direction, the magnetic flux flows as illustrated in Figure 2.12. The line integral of H along a closed contour C is referred to the magnetomotive force or mmf around the contour: mmf = H d l

2 34

C

The first term on the right-hand side of Ampere’s Law is the total conduction current, Ic, that penetrates the surface S enclosed by a contour C: Ic =

Magnetic flux density, B

JV ds

Figure 2.12 The right-hand rule: time-varying current introduces a “swirl” to the magnetic field.

→ →

2 35

•

c

SC

The second term on the right-hand side of Ampere’s Law is the total displacement current, Id, that penetrates a surface, SC, enclosed by a contour, C (Figure 2.13): Id =

→ →

OBt dl = OB • dl =

∂ D ds ∂t

c → →

Here: OB • dl = Amperian loop

C

Q t =C V t =C E t

d

2 38

θ ds

C

Direction of integration

Figure 2.13 Ampere’s Law: the mmf, generated along a closed contour C due to conduction currents penetrating a surface, S, bounded by a contour C (current i3 has no effect as it is outside the contour; only conduction current is illustrated).

→ →

Ic= J•ds s

Contour C

The contour is “shifted” →

B

→

But since, by definition, I ≜ dQ/dt, Equation (2.38) reduces to: I dE dD = =ε dt dt A

→

B

2 37

where C is the capacitance, V(t) is the increasing voltage across the capacitor plates due to the increase in charge, and E(t) is the increasing electric field developing along the path, d, the separation between the capacitor plates. If the area of the plates is A, in a medium with permittivity, ε, the capacitance is expressed as C = ε A/d, yielding: Qt =ε E t A

sc

i2

H d l is equal

to the current I penetrating any surface enclosed by a contour, C. If that surface were just a flat circle enclosed by a contour, however, the current is I = 0. On the other hand, the surface could be extended upward until it enclosed the capacitor created by the two plates, thus enclosing I. Maxwell settled this inconsistency by noting that current entering the capacitor plate results in charging the capacitor, thus increasing the electric field, E, within the capacitor:

→

ds

→

The extension of Ampere’s Law to include the displacement current can be justified using Figure 2.14, showing a current-carrying wire interrupted by a parallel plate capacitor. According to the (original) Ampere’s Law, the line integral

•

S

i3

S

•

𝜕t sc → → Jv • ds = μ0Ic= μ0 (i1–i1)

i1

2 36

→ 𝜕D

•

•

c

→

Jv +

→ Id = ∂D • ds ∂t s

2 39

Therefore, time-varying electric fields (or electric displacement) act in a manner similar to that of current density, the displacement current, Id.

Figure 2.14 Ampere’s Law extended by Maxwell to include displacement current.

19

20

2 Fundamental Concepts

I1

I2

Contour C→0 Contour C→0

I3

I2

I1

3

I1 = I 2

C

H • dl = ∑Ii = 0 i=1

(b)

(a)

Figure 2.15 Equivalence between Ampere’s Law and Kirchhoff’s Current Law. Current does not accumulate anywhere in the circuit. (a) Current always flows in closed loops. (b) Total net current entering any junction in the circuit is zero.

Interestingly, the concept of displacement current was the only original contribution by Maxwell to the four equations that bear his name. Maxwell established the foundation for comprehension of the concept of common-mode (CM) currents,7 essential for the awareness of grounding-related issues, for example, ground loops and balanced circuits. A special case occurs when, in Ampere’s Law, the length of the contour, C, on which integration of the magnetic field occurs, approaches zero. In that case, Ampere’s Law states that the sum of all currents entering and leaving the volume must be zero. In this case, Ampere’s Law transforms into Kirchhoff’s Current Law (KCL), stating that the sum of all currents entering a lumped circuit node must be zero (Figure 2.15): H dl = C

Ii = 0

2 40

i

Ampere’s Law is the second of the two more important parts of Maxwell’s equations associated with grounding theory, demonstrating that current always flows in closed loops. A direct outcome of Ampere’s Law is the postulation that current always flows in closed loops (which is another way of stating the Continuity Equation, discussed earlier). This is easily demonstrated now. Commencing from Ampere’s Law: ∇ × H = JV +

∂D ∂t

2 41

Taking the divergence of both sides of the equation, we obtain ∇ ∇×H=∇

JV +

∂D ∂t

= ∇ JV + ∇

∂D ∂t

However, from vector algebra, we know that ∇ ∇ × H ∇ JV + ∇

∂D ∂t

2 42

0; therefore,

0

2 43

which can now be rewritten as: ∇ JV = −∇

∂D ∂t

= −

∂ρV ∂t

which expresses the Continuity equation. Specifically, this results in the following practical conclusions:

7 Common-mode currents are discussed later in this chapter.

2 44

2.1 Maxwell’s Equations Demystified

• •

DC currents must always flow in closed galvanic loops, since for electrostatics, ∂D ∂t = 0, which mandates that ∇ J = 0. AC and transient currents flow in closed circuits but the circuit may be comprised of conductive as well as displacement paths (which in circuits are known as capacitive paths), since for electrodynamics as a whole: ∇ J = −∇

∂ D ∂t

2 45

Faraday’s law V(t)

→

Terminal Characteristics

I(t)

→

B(t),Φ(t)

Core Characteristics

→

Ampere’s law

→

H(t),F(t)

This outcome is of utmost importance for the understanding of electri- Figure 2.16 Simplified analogies and the relations cal and physical phenomena. For instance, lightning and electrostatic dis- between Maxwell’s equations and terminal charge (ESD) currents appear, at first glance, to violate the assertion that characteristics (i.e. Kirchhoff’s equations). current always flows in closed loops, as they do not, seemingly, close any observable loops. However, the above derivation from Ampere’s Law resolves this apparent paradox (Equation (2.45)): when electrostatic and lightning discharges occur, a change (collapse) of the electrical field (change in flux or displacement), − ∂D ∂t, accompanies the conductive discharge current path, J V , completing the loop, and maintaining continuity; thus, no contradiction exists. Now that all four Maxwell’s equations and the two Kirchhoff’s equations were addressed, Figure 2.16 is provided to illustrate a simplified analogy of the relations between Maxwell’s equations (i.e. EM fields) and Kirchhoff’s equations (i.e. terminal characteristics). Note that only Faraday’s Law and Ampere’s Law are represented in Figure 2.16. Interestingly, these two independent Maxwell’s curl equations are independent, while the other two equations (Gauss’s Laws for electric and magnetic fields) are derived from these two, when coupled with the Continuity Equation. 2.1.2.5

Impressed and Conduction Currents

The discussion of Ampere’s Law revealed that conduction as well as displacement currents must be considered. In fact, the current density term, JV, may be decomposed as follows: J V = J Vi + J V c

2 46

where JVi represents the impressed source current density, constituting the primary source of the EM fields, while JVc is produced by the motion of charges induced by EM fields that were originally produced by JVi. JVc therefore could represent the conduction current due to the presence of an EM field within a conducting medium. Also, JVc could represent convection or diffusion currents that result from EM field impressed upon charges in empty space, or upon a semiconductor, respectively. Convection currents can also be produced by a moving charged medium, or by the motion of an object with static charge. The diffusion current in a semiconductor is a transient effect due to charge (electron and hole) migration away from the region of same initial charge concentration. 2.1.2.6

Constitutive Relations

The solution to Maxwell’s equations for conducting media requires the solution solve for the five unknowns E, D, B, H, and JVc, which cannot be derived from the only two independent Maxwell’s curl equations. To obtain the solution and determine all the unknowns, three additional independent equations are therefore required. For that purpose, the following expressions, relating the response of matter to the applied field, are used, and referred to as constitutive relations: a) Permittivity (or dielectric constant), ε, relates the electric displacement to electric field strength, D ≜ εE

2 47

where: ε = ε0 εr

2 48 −9

−12

where ε0 is the permittivity of free space, ε0 (1/36π) × 10 ≈ 8.85π) × 10 F/m, and εr is the relative permittivity of the material containing the charge. The permittivity of free space, ε0, determines the intensity of the electric field occurring in free space resulting from electrical charges. When an electric field is present in an environment other than free space, it has the effect of polarizing matter, causing charges to rearrange themselves in the direction of the field in a manner that tends to oppose the original applied field. This results in a reduction of the total net electric field in polarized material. This is taken into account by saying that the permittivity of the material, ε = ε0 εr, is higher than ε0 (or εr > 1).

21

22

2 Fundamental Concepts

Because permittivity changes discontinuously as the boundary enclosing the charges, the electric field strength will likewise be discontinuous. It is, therefore, advantageous to introduce the electric displacement, D ≜ εE. Unlike the E-field E, electric displacement is continuous across the material boundary. b) Permeability, μ, relates the magnetic flux density to the magnetic field strength: B ≜ μH

2 49

where: μ = μ0 μr

2 50

where μ0 is the permeability of free space, μ0 = 4π × 10−7 H/m, and μr is the relative permeability of the material of the medium. The permeability of free space, μ0, determines how easily magnetic fields are established in free space. When a magnetic field is present in matter, the characteristics of the material will augment the strength of the magnetic field. This effect is taken into account by saying that the permeability of the material, μ = μ0 μr, is different from μ0 (or μr 1). Because permeability changes discontinuously as the boundary enclosing the charge in the material, the magnetic field strength will, likewise, be discontinuous. It is therefore advantageous to introduce the concept of flux density, B ≜ μH. Unlike the magnetic field strength, H, magnetic flux density, B, is continuous across the material boundary. c) The conductivity σ relates current density to electric field (for an isotropic conductor): J ≜ σE

2 51

Often, this relation is called Ohm’s Law in materials and: σ = σ0 σr

2 52

where σ r is the relative conductivity, and σ 0 is the conductivity of copper (Cu), σ 0 ≈ 5.82 × 107 S/m. There are contexts in which the use of resistivity, ρ, (Ω m) is more convenient than conductivity. The above extremely simple linear constitutive relations apply to time-variant as well as static fields. It may be mentioned that the velocity of light in free space, commonly denoted here by c, happens to be related to (ε0, μ0) by: c=

1 ε0 μ0

2 53

EM waves propagate, therefore, in free space at the same velocity, c. Furthermore, EM waves require no medium for propagation. In medium other than free space, the velocity of EM propagation is modified by the relative permittivity and permeability (εr, μr), resulting a somewhat reduced velocity of propagation. 2.1.2.7 Divergence-Free (Solenoidal Vector) Fields

Two of Maxwell’s equations (i.e. Gauss’s Law of electric and magnetic fields) consist of a divergence of a vector field: ∇ D = ρV ∇ B=0

2 54

Figure 2.17 depicts a radial vector field, characterized by Non-Zero Divergence: ∇ g

0

2 55

The divergence and curl of a vector field are two vector operators whose basic properties can be understood geometrically by viewing a vector field, for instance, as the flow of a fluid or gas. The divergence of a vector field simply measures how much the flow is expanding at a given point from a source. It does not indicate in which direction the expansion is occurring. Hence (in contrast to the curl of a vector field), the divergence is a scalar. This field could represent the electric flux emerging from a Gaussian surface enclosing electric charges (Gauss’s Law for Electric Field): ∇ D = ρV

2 56

2.1 Maxwell’s Equations Demystified

Figure 2.17 Illustration of a radial (Non-Zero Divergence) field. Source: Kcooley [4].

The radial unit vector field, er 4 3 2

y

1 0 –1 –2 –3 –4 –6

–4

–2

0 x

2

4

6

If, in general, everywhere in space, for a vector function, f, the following surface integral holds: ∇× f

0

da

2 57

closed surface, A

it follows from Gauss’s theorem that: ∇ g dv = g da V

2 58

A

where the vector function, g, can be expressed as the curl of the vector function, f: g =∇× f

2 59

For Equation (2.57) to be valid unconditionally, it is necessary that: ∇ g =∇

∇× f

0

2 60

In other words, a vector field that has circulation about a point cannot be written as the gradient of a function. In contrary, Figure 2.18 depicts a circumferential vector field, characterized by Zero Divergence (i.e. a “divergence-free field”): ∇ g

0

g =∇× f

2 61

The curl of a vector field indicates, for instance, how a fluid may rotate, circulating around a central axis. It is evident, from observation, that in the case of circumferential field (obviously, a “curl” of a different vector function) the divergence vanishes everywhere outside a hypothetical, very large, Gaussian surface, enclosing the entire space containing the field. A common way of expressing this property is to say that the field has no sources or sinks. The flux lines of a solenoidal field are either closed loops or end at infinity. More formally, the condition of “zero divergence” is satisfied whenever a vector field, say, B, has only a vector potential component, because the definition of the vector potential, A, as: ∇ B=0 B=∇×A

2 62

23

2 Fundamental Concepts

Figure 2.18 Illustration of a circumferential (zero divergence) field. Source: Kcooley [4].

The circumferential unit vector field, eθ 4 3 2 1 y

24

0 –1 –2 –3 –4 –5

–4

–3

–2

–1

0 x

1

2

3

4

5

This vector field, B, could represent the magnetic flux emerging from a Gaussian surface enclosing magnetic source within that surface (Gauss’s Law for Magnetic Field). The upper equation is, in fact, Gauss’s Law of magnetic fields, and the bottom equation is, of course, the definition the magnetic vector potential. An example of a “Zero Divergence” vector fields is the current density, JV, where the charge density is invariant in time: ∇ JV = −

∂ρV ∂t

2 63

Note that this expression is identical to Equation (2.4), representing the “Continuity equation.” 2.1.2.8 Curl-Free (Conservative) Fields

The other two of Maxwell’s equations (i.e. Faraday’s Law and Ampere’s Law) consist of a curl of a vector field: ∇×E= −

∂B ∂t

∇ × H = JV

B

A

Figure 2.19 Illustration of two possible integration paths. The straight line represents the trivial path; the curved line depicts a convoluted curve. Source: DominicPrice (2014)/ Wikipedia/public domain.

∂D + ∂t

2 64

In a two- and three-dimensional space, where (in addition to the (trivial) straight line) an infinitely large number of integration paths, having a greater length, may be available between any two points (a) and (b) (Figure 2.19). In general, the value of the line integral depends on the integration path taken. However, in the special case of a conservative vector field, the value of the integral is independent of the path taken. It is easy to illustrate this concept from mechanics: a) Non-Conservative field visualization: When pushing a box from one end of a room to another (against friction). Pushing the box in a straight line across the room requires noticeably less work against friction than along a curved path covering a greater distance. b) Conservative field visualization: Consider two hikers climbing a cliff; one scaling the cliff by going vertically up it, and the second decides to walk along a winding path that is longer in length than the height of the cliff, but at only a small angle to the horizontal. Although the two hikers have taken different routes to the top of the cliff, once at the top, they will have both gained the same amount of gravitational potential energy, i.e. the gravitational field is conservative.

2.1 Maxwell’s Equations Demystified

A more intuitive understanding can be gained from M. C. Escher’s “Ascending and Descending” famous painting (Figure 2.20), which illustrates a non-conservative vector field, impossibly made to appear to be the gradient of the varying height above ground as one moves along the staircase. It is rotational in that one can keep getting higher or keep getting lower while going around in circles. It is non-conservative in that one can return to one’s starting point while ascending more than one descends or vice versa. On a real staircase, the height above the ground is a scalar potential field: If one returns to the same place, one goes upward exactly as much as one goes downward. Its gradient would be a conservative vector field and is irrotational. The situation depicted in the painting is impossible. A Curl-Free (Conservative) vector field, f, can always be expressed as the gradient of some scalar function, v. If, in general, everywhere in space, for a vector function, f, ∇× f

0

2 65

it follows from Stokes’ theorem that the circulation (curl) of the function, f, must also be zero. ∇ × f dv = f S

ds

0

2 66

C

Therefore, regardless of the path of integration: b

a

f ds = − a

f ds

2 67

b

Figure 2.20 Illustration of conservative and non-conservative fields in M. C. Escher’s painting “Ascending and Descending”. Source: M. C. Escher/Wikipedia Commons/public domain.

where (a) and (b) represent endpoints of the integration path. The value of the line integral depends on the position of points (a) and (b) only. In other words, in curl-free or conservative vector fields the line integral from point (a) to (b) is path independent. Path independence of the line integral is equivalent to the vector field being conservative. A conservative vector field is also irrotational; i.e. it has a vanishing curl. For Equation (2.66) to be valid unconditionally, it is necessary that: f = ∇V x, y, z ;

V = scalar

2 68

which then results in: ∇ × f = ∇ × ∇V

0

2 69

Such vector fields are sometimes referred to as “curl-free” or “curl-less” vector fields and are also referred to as “longitudinal vector fields.” If V represents the (scalar) electrical potential, it follows that E represents the electric field vector field: E = ∇V x, y, z

2 70

The concept of electric potential is born! To better understand the implication of “curl-free” (conservative) vector fields and the principle of “path of least impedance” (see Section 2.5) to be discussed later, the following illustration is brought forth (Figure 2.21). Assume a large uniformly and positively charged sphere and assume its surrounding is symmetrical about the sphere. The monkey attempts to approach the large charged sphere holding a small positively charged sphere. In order to bring two like charges near each other work must be done, and hence, energy changes form. As the monkey brings the charge closer, he does work on the positive charge, subsequently increasing its potential energy. If he is to release the charge, its potential energy is converted to kinetic energy and the charge is repelled. V electrical potential =

W or Δ of potential energy q unit of charge moved

2 71

25

26

2 Fundamental Concepts

Does the particular path the charge is carried along make a difference? The work done against an electric force in carrying a charge along a path from point (a) to point (b) is thus: b

W= −

b

F dl = − q E dl a

(a)

2 72

a

The electric potential between the points (a) and (b) may be expressed as: b

ΔV

a

b

= −

E dl =

W q

2 73

a

If the path the charge is taken makes no difference, then the work done (or exchange of energy) along a closed loop taken by the charge from (a) to (b) and back to (a), would be:

(b)

b

ΔV

a

b

= −

E dl = V b − V a

ΔV

a b

0

a

a

2 74

(c) Figure 2.21 As charge is brought closer, work is done on the charge, increasing its potential energy. When the charge is released, it is repelled from the large charge and its potential energy is converted to kinetic energy. (a) Monkey brings a small charge against the field (he does work, increasing potential energy). (b) Monkey lets go of the charge. (c) The charge is repelled from the large charge (potential energy converted to kinetic energy).

This conclusion would hold, however, only when the charges are immersed in a conservative (i.e. curl free) field. However, when time-varying magnetic fields are present, the electric field can no longer be described simply in terms of a scalar potential V because, from Faraday’s Law of Induction, the electric field is no longer conservative because: ∇ × E 0 and the integral E dl is C

path-dependent. In such cases, the magnetic (vector) potential must also be considered as well, and: b

ΔV

a

b

= −

E dl

ΔV

b

a

2 75

a

But with the “correction,” →

E = − ∇V −

FE → dl

b

q

a q → dl

Figure 2.22 Effect of a rotational, non-conservative field on the total work done by a charge, q, traveling between points (a) to (b) to (a).

2 76

which remains conservative. The effect of a rotational non-conservative field on the total work done, with a charge, q, travels between points (a)–(b) and back to (a) is depicted in Figure 2.22.

Wa t → b = –Wb → a → FM

∂A ∂t

• • • •

The Least You Need to Know Maxwell’s equations describe the basic interactions between EM sources and phenomena. Faraday’s Law and Ampere’s Law are fundamental for understanding grounding theory. All notions about inductance and its derivation stem from Faraday’s Law of Induction, demonstrating that currents always flow in a loop area having the smallest possible contours. Ampere’s Law demonstrates that current always flows in closed loops. Current must return to its source, whether in conductive paths or through displacement.

2.2 Boundary Conditions

• • •

Kirchhoff’s equations are low-frequency approximations of Maxwell’s equations, and are valid only when no time-varying fields are present (i.e. ∂D/∂t = 0, ∂B/∂t = 0), and for electrically small circuits only, when “quasi-static” approximations apply. Divergence-free and curl-free fields are two important principles for the correct application of Maxwell’s equations to the understanding of grounding. Current, not voltage, constitutes the source of EM fields.

2.2

Boundary Conditions

Similar to all differential equations, Maxwell’s equations have an infinite number of solutions. The uniqueness of a particular solution to Maxwell’s equations that are partial differential equations is determined by specific boundary conditions. Boundary conditions are determined by characteristics of the medium and interfaces between different media with respect to their EM properties. Assume a boundary between two physical media, a, b, characterized by their permittivity, permeability, and conductivity, εa, μa, σ a, and εb, μb, σ b, respectively. The tangential components of the electric field vector E and the magnetic field vector H must be continuous across the boundary between the two media: E ta = E tb

2 77

H ta = H tb

2 78

In addition, from the Law of Continuity, the normal component of the electric flux density vector, D, and the magnetic flux density vector, B, must be continuous across the boundary between the two media: D na = D nb

2 79

B na = B nb

2 80

Equation (2.79) for the electric flux density vector D holds a condition that no charges exist on the boundary between the two media. Figure 2.23 illustrates the boundary conditions and the field continuity across the boundary. The effect of boundary conditions for electric and magnetic fields is fundamental to the concepts of image theory and “flux cancellation” provided by signal reference and current return planes, essential for electromagnetic interference (EMI) control in circuits and systems. In those cases, we are primarily concerned with boundary conditions, which apply when one of the media is a conductive surface, as would be the case with the use of reference (or return) planes in printed circuit boards (PCBs).

Eta

⇀

Etb

Eta = 0 Etb = 0

⇀

Ea

Eb ⇀

Ea

⇀

⇀

Ba

Bnb

Bna H ta H tb

⇀

Ha

⇀

Bb

Ba

Bna = 0

Bnb = 0

KS Ht = 0 b

⇀

Hb

H ta

⇀

Da

⇀

Dna

ρS

Dnb Db

Dna

ε a , μ a ,σ a

ε b , μ b ,σ b

ε a , μ a ,σ a

Medium a

Medium b

Medium a

(a)

Dnb = 0

σb = ∞ Medium b (Perfect electrical conductor) (b)

Figure 2.23 Electric and magnetic field vector continuity across a boundary between two media. (a) Arbitrary media. (b) Medium b is perfectly electrical conductor.

27

28

2 Fundamental Concepts

For simplicity, it can be assumed that medium b, for instance, can be approximated as a perfect electrical conductor, that is σ b ∞. As a result, all fields within the perfectly conductive medium must vanish, that is, Eb = 0, Db = 0, as well as Hb = 0 and Bb = 0. Equations (2.77) and (2.78) demonstrate that since all fields vanish in a perfectly conductive medium, the tangential electric field vector and normal magnetic flux density field vector components in medium a at the boundary must vanish too, resulting in: E ta = 0;

σb

∞

2 81

B na = 0;

σb

∞

2 82

The tangential magnetic field vector and normal electric flux density vector components in medium a, do not vanish, however: σb

∞

2 83

Dna = ρS C m2 ; σ b

∞

2 84

H ta = K S A m ;

To satisfy the discontinuity, the tangential magnetic field component creates a surface current distribution, KS, along the surface of the boundary that is orthogonal to the tangential H-field, Ht. The units of KS are A/m, representing a surface current distribution along the surface of the intermedia interface. In a similar manner, the normal electric field flux density component deposits a surface charge distribution, ρS, along the surface of the intermedia interface. The units of ρS are C/m2.

• •

The Least You Need to Know Boundary conditions across metallic surfaces preclude the existence of tangential electric field and normal magnetic flux density vectors. The effects of boundary conditions form the basis for image theory and “flux cancellation” concepts, essential for grounding and EMI control.

2.3

Intrinsic Inductance of Conductors and Interconnects

The concepts of resistance, capacitance, and inductance are fundamental to the understanding of real-world grounding concepts. The meaning and calculation of resistance is clearly understood by all. When current, I, flows through a block of material and the resultant voltage drop, V, across it is measured, the resistance of the block of material is the ratio R = V/I. The units of resistance are in Ohms (Ω). Likewise, the concept and calculation of capacitance is easily understood. A potential difference V exists between any two bodies (which may be conductive or non-conductive), carrying equal and opposite charges, +Q and −Q. The capacitance of this structure is defined as the ratio C = Q/V. The units of capacitance are in farads (F), named for Michael Faraday. Interestingly, Faraday had more to do with inductance than capacitance. Electric field E is usually visualized as lines of flux directed from the positively charged to the negatively charged body. The magnitude of the electric field and, hence, the magnitude of the potential difference is directly proportional to the magnitude of the charge, Q. Capacitance of this structure is thus dependent only on the shape and relative physical orientation of the two bodies, and the properties of the material they are immersed in. Alternatively, suppose we connect a voltage source, V, across the two bodies, resulting in a potential difference between them. Charge Q = C V will subsequently be deposited from the source onto these bodies with the amount of charge, Q, that the bodies can hold, depending on the capacitance of the structure and the potential difference between them. Hence, capacitance represents the ability of a structure to maintain charge. The concept of inductance appears to be less well comprehended, thereby bringing about misconceptions regarding its essence and mistakes in its calculation. Proper consideration of grounding design without a clear understanding of the concept of inductance is simply impossible. For instance, ever too often the performance of a grounding system is stated in terms of grounding resistance, totally neglecting the contribution of inductance to impedance. This section is dedicated to the explanation of the concept of inductance. The concepts of self-, mutual-, internal-, and external-inductance are addressed. In particular, the concept of partial inductance, which allows the calculation of ground bounce and power rail collapse that are critically important in the design of electronic circuits for signal integrity, is presented in detail.

2.3.1

Concept of Inductance

Whereas capacitance is associated with the separation of charge, inductance results from charges in motion, that is, electric current, which subsequently results in the creation of magnetic fields.

2.3 Intrinsic Inductance of Conductors and Interconnects

Inductance is a phenomenon related to the storage of energy contained in the magnetic field surrounding current-carrying conductors and in its most fundamental form, inductance is the relationship of the stored energy in the magnetic field and the current that produces the field as given by [5]: L=

2U m I2

2 85

where I is current and Um is the stored magnetic energy, defined as Um =

1 B Hdv 2

2 86

V

where H is the magnetic field strength, B is the magnetic flux density, and V is the volume of space occupied by H and B. The H and B fields are related by the standard constitutive relationship: B = μ0 μr H

2 87

where μ0 is the permeability of free space and μr is the relative permeability of the medium. The concept of inductance may also be directly derived from Faraday’s Law of Induction: E dl = − C

S

∂B ds ∂t

2 88

The fields in Equations (2.86) and (2.88) correspond to fields present both internally and externally to the conductor (or conductors) carrying the current. The total inductance can therefore be approximately expressed as: L = Lint + Lext

2 89

where Lint is denoted “internal inductance” (associated with the energy of the magnetic fields internal to the conductors) and Lext stands for the “external inductance” (associated with the magnetic fields external to the conductors). This expression for inductance is valid only for a closed system, in that a return path for the current is required in order for Equation (2.85) to have physical meaning. For example, the external inductance of a single infinitely long straight wire is infinite (i.e. has no physical meaning). Since inductance is conventionally defined for closed loops, how should the term “inductance of an isolated conductor” or “inductance of a segment of a conductor or portion of a loop” be understood? A resolution to this confusing situation of determining self-inductance or, simply, the inductance of a current-carrying circuit is achievable by means of the concept of “partial inductance.” In a similar manner, mutual inductance between parallel conductors of a loop can be exclusively determined using the concept of partial mutual inductance.

2.3.2 Self-Inductance For the definition of the concept of self-inductance, we start from the Biot–Savart Law: dB =

μ0 Idℓ × r 4πr 2

2 90

From the circuit depicted in Figure 2.24, we observe that a closed loop bounded by a contour C carrying a current I, produces a magnetic flux density, B, emerging from the surface, S, of the circuit at a distance r from the current carrying element dℓ [6]. The contour, C, of the loop can be thought of as either a conducting material (as in the case of a wire) or an imaginary contour of nonconducting material. Integrating Equation (2.90) with respect to the path length, ℓ, over the conB B tour, C, we obtain the total flux density due to the loop’s entire circumference:

ds ↺

μI B= 0 4π

dℓ' × r r2

2 91

C

The total magnetic flux, Φ, penetrating a surface, S, bounded by the currentcarrying loop is therefore found by integrating the flux density, B, over the entire cross-section of the loop:

S

r

dI V1 = L11 1 dt

C

r Idl ′

Φ≜

B ds S

2 92

Figure 2.24 Model for formulation of the self-inductance concept.

29

30

2 Fundamental Concepts

Substituting B1, dℓ1 in Equation (2.91) and C1 in Equation (2.92), and integrating over the surface the surface, S1, for a particular “loop 1,” we end up with the self-inductance of the loop, Φ11: B1 d s =

μ0 I 1 4π

S1

↺

Φ11 =

S1

dℓ1 ' × r r2

ds

2 93

C1

The self-inductance of a current-carrying loop is conventionally defined as the total magnetic flux penetrating the surface of the loop per unit current that produced it: Φ11 I1

L11 ≜

2 94

Therefore:

↺

μ0 4π

L11 =

S1

dℓ1 ' × r r2

ds

2 95

C1

The subscripts “1” and “11” signify the self-inductance of a loop that is due to the flux produced by the current bounding it. The unit of inductance is in Henry (H) honoring Joseph Henry of Albany, New York, who essentially discovered Faraday’s Law at about the same time as Faraday. Differentiating the left-hand part of Equation (2.93) with respect to time and combining the result with Equation (2.88) while considering total loop inductance results in one of the most commonly used expressions for the effect of magnetic induction, that of induced electromotive force or emf: E dl = −

EL =

dΦ Φ = LI dI = −L dt dt

2 96

C

According to Faraday’s Law, therefore, the effect of the magnetic flux penetrating the surface of the contour, C, may be substituted by inserting an equivalent emf or voltage source, V, into the contour of the loop that encompasses the surface.8 Equation (2.96) depicts Lenz’s Law, demonstrating that a change in the current flow in the circuit will introduce an emf, EL, that opposes the rate of change of the magnetic flux through the loop (note the minus sign). Equation (2.96) also reveals that when the current, I, through a conductor with inductance, L, increases, a voltage, v(t) = EL, develops across the conductor with a polarity that opposes the current (in addition to any IR voltage drop caused by the conductor’s resistance.) The charges flowing through the circuit lose potential energy, which is subsequently stored in the increased magnetic field around the conductor. At any given time, t, the momentary power P(t) flowing into the magnetic field, which is equal to the rate of change of the stored energy U, is the product of the current i(t) and voltage v(t) across the conductor P t =

dU =v t i t dt

2 97

From Equation (2.96): dU di =L i i dt dt

dU = L i idi

2 98

When no current flows through the circuit, no magnetic field exists and the stored energy is zero. Neglecting resistive losses, the energy U (measured in Joules, in SI) stored by inductance with a current, I, through it is equal to the amount of work required to establish the current through the inductance from zero and, therefore, the magnetic field. This is given by: I

U=

L i idi

2 99

0

8 For the “inductance of this loop” to be of physical significance, the physical dimensions of this loop must be assumed to be electrically small. Furthermore, if the loop contour is assumed to be constructed of a conducting material (such as a metallic wire), these effects of the time-varying magnetic field can be represented as a single lumped voltage source placed anywhere in the loop contour.

2.3 Intrinsic Inductance of Conductors and Interconnects

If the value of inductance, L(i), is invariant with respect to the current, i.e. L(i) = L for any I, the energy stored reduces to:

M

+ I1

+ I2

I

U = L idi =

1 2 LI 2

2 100

0

Self-inductance is therefore also proportional to the energy stored in the magnetic field for any current flowing through the current loop. This energy is stored as long as the current through the loop remains constant. Diminution of this current would result in a subsequent decrease of the magnetic field, inducing an opposing emf (i.e. voltage).

2.3.3 Mutual Inductance

–

n:m

–

Figure 2.25 Circuit diagram of two mutually coupled inductances. It also depicts The “Dot Convention”. Source: Fresheneesz (2006)/Wikipedia/public domain.

Mutual inductance refers to magnetic flux penetrating a conducting loop, C2, produced by current, I1, flowing through another conducting loop, C1, causing induction of an emf in the second circuit (Figure 2.25). Observe that the voltage source representing the induced emf in loop 2 has a polarity, according to Faraday’s Law, such that it tends to induce a current in the second loop, which produces a magnetic flux that opposes the original magnetic flux passing through its surface, which is due to the current in loop 1. Mutual inductance is an important mechanism by which transformers function, but it can also result in unwanted coupling between conductors in a circuit. For the common and important case of electrical circuits consisting of thin wires (or traces), the derivation of mutual inductance is straightforward. In a system consisting of K wire loops, each with one or more wire turns, the flux linkage of loop m, λm, is given by: K

λm = N m Φm =

2 101

Lm,n in n=1

where Nm denotes the number of turns in loop m, Φm represents the magnetic flux through loop m and the constants Lm,n are described below. This equation follows from Ampere’s Law. Applying Faraday’s Law of Induction to Equation (2.101) results in Em =

dλm dΦm = Nm = dt dt

K

Lm,n n=1

din dt

2 102

where Em denotes the emf induced in circuit m, which is consistent with the common above definition of inductance if the constant coefficients Lm,n are identified with the coefficients of inductance. Since the total currents Nn in contribute to the flux Φm, it also follows that Lm,n is proportional to the product of turns Nm Nn. Multiplying Equation (2.102) for Em above with imdt and summing over m results in the total energy transferred to the system in the time interval, dt: K

K

im vm dt = m

K

im Lm,n din = m,n = 1

∂W i ∂in n=1

2 103

which should be consistent with the change of the magnetic field energy, W, caused by the n-th currents, in. The integrability condition: ∂2 W ∂2 W = ∂im ∂in ∂in ∂im

2 104

holds when Lm,n = Ln,m, and subsequently the inductance matrix, Lm,n, is symmetrical and the integral of the energy transfer represents the magnetic field energy as a function of the currents: W i =

1 K im Lm,n in 2 m,n = 1

2 105

Similar to Equation (2.94) above for the definition of self-inductance, mutual inductance can be conventionally defined as total magnetic flux penetrating one loop due to a unit current flowing in the contour of a second loop (Figure 2.26): L21 ≜

Φ21 I1

2 106

31

32

2 Fundamental Concepts

B11

L21 is often replaced by the sign M to represent the mutual inductance. Therefore:

I1

L21 =

μ0 4π

↺

Φ11

C1

S2

B21

Φ21

ds

C2

S2 dI V2 = L12 1 dt

dℓ1 ' × r r2

ds

2 107

C1

The subscripts “1” and “12” signify the mutual inductance between loops 1 and 2 by virtue of the flux penetrating loop 2 produced by current flowing in a closed current loop 1. Once the mutual inductance, M, is determined, it can be applied to predict the behavior of a circuit (see Figure 2.25): E1 ≜ L11

di1 di2 di1 di2 − L12 = L11 −M dt dt dt dt

2 108

where E1 represents the emf developed across the inductance of interest, L11 is the self-inductance of this inductor, L12 is the mutual inductance, and di1/dt, di2/ dt represent the rate of change of currents through loop 1 and 2, respectively. Figure 2.26 Self- and mutual inductance The minus sign in Equation (2.108) arises from the manner the current i2 is between adjacent circuits/loops. defined in Figure 2.25. If both currents were to be defined going “into” the dots, the sign of the mutual inductance M will be positive and the equation would include a plus sign instead. The coupling coefficient, k, is the ratio of the open-circuit (o.c.) actual voltage ratio to the ratio that would be obtained if all the flux coupled from one circuit into the other. The coupling coefficient is related to mutual inductance and self-inductances as follows: From the two simultaneous equations expressed in the two-port matrix, the o.c. voltage ratio is: V2 M oc = V1 L11

2 109

If all the flux is coupled between inductors is the ratio of their respective turns, the ratio in Equation (2.109) reduces to: V2 L22 max = V1 L11

2 110

where L22 represents the self-inductance of loop 2. Hence, we may define the coupling factor, k: M = k L11 L22

2 111

If the two circuits are identical, L11 = L22, M = L21 = k L11

2 112

and k≜

L21 L11

2 113

It follows, therefore, that when all (or, in practice, most) of the flux generated by loop 1 couples into loop 2, the mutual inductance approaches the self-inductance of the circuit (L12 L11). The loops are referred to as “tightly coupled” or “closely coupled”.9 Note that k is upper bound by unity and will approach this value for tightly coupled loops.

2.3.4

Partial Inductance

It may be argued that in common expressions provided in the literature for conductors and traces, no indication of current return path and its association to inductance exists. It has been shown above that there is simply no such thing as a standalone conductor carrying current in a given direction; current must return to its source; thus, current loops must subsequently

9 A circuit (such as a transformer) in which the magnetic field due to time-varying currents in one circuit induces voltage in another is said to be “Tightly coupled,” when almost all the flux produced by one circuit links the other, or “Loosely coupled” when only a portion of the flux produced by one circuit links the other.

2.3 Intrinsic Inductance of Conductors and Interconnects V CC

V CC

LVcc(PS)

LVcc(PS)

Gate 1

Gate 1

VS

VS On

Off

Off

On

Gate 2

IC

GND 1

VC C

VN LGND(PS)

Off

On

On

Off

GND 1

VOut

Gate 2 IC

VC C VN

GND 2 LGND(PS)

LGND

VOut

GND 2

LGND

GND

GND

(a)

(b)

Figure 2.27 Illustration of ground bounce and “power rail collapse” generation across the return plane as a basis for illustrating the concept of partial inductance. (a) Gate switching from “Hi” (“1”) to “Lo” (“0”), producing “ground bounce”. (b) Gate switching from “Lo” (“0”) to “Hi” (“1”), producing “power rail collapse.”

exist. Consider, for instance, the case of digital circuits, where ample experimental evidence shows that when digital current passes through the return or “ground” conductor, a voltage drop will, in fact, develop across two points on that return conductor when a change of logical state occurs at the digital driver, the current source (Figure 2.27) [7]. That voltage commonly known as “ground bounce” appears to be proportional to the rate of change (derivative) of the current waveform.10 Clearly, this cannot be due to the resistance of that return conductor. A similar phenomenon occurs on the VCC or power rail, when switching digital currents are drawn through the power supply conductor, referred to as “power rail collapse.” It must, therefore, be concluded that segments of such conductors in the power distribution circuit do exhibit inductances that are uniquely attributable to them. The question addressed in this section is, “can inductances be uniquely attributed to segments of a closed current loop?” The answer to this question is yes! The key to doing so is the concept of partial inductance. In order to quantitatively define partial inductance, we must use two important vector calculus identities [3]: ∇ ∇×A

0

2 114

and Stokes’ theorem, stipulating that the surface integral of the curl of a vector field through a surface S is equivalent to the line integral of that vector field around the closed contour C that encompasses this surface. ∇ × A ds = A dl S

2 115

C

Gauss’s Law for magnetic fields imply that all magnetic flux lines must form closed loops, implying that the magnetic flux density vector, B, can be expressed in terms of the vector magnetic potential [3]: B=∇×A

2 116

The vector magnetic potential, A, at all points around a current-carrying wire can be shown to be parallel to the wire going to zero at infinity [7]. In addition, the vector magnetic potential is directly proportional to the current that produced it. Substituting Equation (2.102) into Stokes’ theorem yields the important result [8]:

B ds = A dl S

C

10 This phenomenon is known as “Delta-I Noise” and is discussed in detail in Chapter 13.

2 117

33

34

2 Fundamental Concepts

B

Contour C

Segment C2 I2

I3

I1

B

Segment C1

Segment C3

I4 B

Segment C4 Figure 2.28

B

Area S

Model for formulation of the partial inductance concept.

The magnetic flux through a surface, S, can thus be alternatively obtained as the line integral of the vector magnetic potential, A, around the closed loop contour, C, that encloses the surface. Substituting the result obtained in Equation (2.117) in the fundamental definition of inductance of a closed loop (Equation (2.94)), results in [6]: B ds A dl ϕ = S 2 118 = C I I I Therefore, the magnetic flux through the surface of a closed loop, S, and subsequently the inductance of that closed loop, can be obtained by integrating the products of the components of the vector magnetic potential, A, tangent to the contour and the differential lengths of the contour around that closed contour, dℓ. It therefore follows that inductance may be uniquely attributed to each segment of the loop contour, C, which is represented as (Figure 2.28): L=

A dl

n Ci

L=

I

i=1

n

=

Li

2 119

i=1

Therefore, the closed loop contour, C, was divided into n segments, such that: n

C=

ci

2 120

i=1

This demonstrates that segments of a closed loop contour can indeed be uniquely attributed inductances, denoted self-partial inductances. As the vector magnetic potential, A, is produced by and proportional to the current I11 flowing through the i-th segment of the loop contour, ci, it follows that the self-partial inductance of the segment that is associated with this segment is unique to that segment, regardless of the loop or loops that it forms a part of [9]. In a similar manner, the concept of mutual partial inductance between a segment of the contour of a closed loop, ci, carrying current, Ii, and a second segment, cj, of the same contour of the loop can be defined as: A dl Lij =

Cj

2 121 Ii Figure 2.29 demonstrates the connection between the previously defined concept of the total closed loop, C, inductance with that of the sum of self- and mutual partial inductances associated with the loop’s segments. Individual inductances Lpii are 11 This point is clearly demonstrated by Ampere’s Law.

2.3 Intrinsic Inductance of Conductors and Interconnects

referred to as the self-partial inductances of the i-th segment, while the inductances Lpij (where i j) are referred to the mutual partial inductance between the circuit’s i-th and j-th segments [9]. Using this definition, the voltage developed across i-th segment of a current-carrying loop can be exclusively and meaningfully obtained: Ei =

K ij Lpij j

dI j dt

;

K ij = ± 1

2 122

The Kij factor is determined by the relative orientation of the currents assigned to segments i and j, becoming negative (Kij = −1) if the currents in segments i and j flow in opposite directions. Subsequently for segment 2, we obtain: E2 =

Lp2j j

dI j dI 2 dI 1 dI 3 dI 4 = Lp22 + Lp21 + Lp23 − Lp24 dt dt dt dt dt

2 123

As depicted in Figure 2.29, we identify different currents associated with the individual segments of the rectangular loop, Ii, where i = 1, …,4. However, I1 = I2 = I3 = I4 = I. Obviously, the total inductance of a segment of a loop constitutes the sum of the self- and mutual partial inductances associated to that segment. Li =

K ij Lpij ;

K ij = ± 1

2 124

j

Consequently, the total inductance of the entire loop is obtained by: LLoop =

K ij Lpij ; i

K ij = ± 1

2 125

j

For a circuit with orthogonally arranged line segments as depicted in Figure 2.29, the mutual partial inductances vanish when segments are mutually perpendicular, thus, Lp23 = LP21 = 0 and Lp34 = LP14 = 0. The total loop inductance (Equation (2.124)) reduces to: n

LLoop =

2 126

Li i=1

where n is the total number of segments in the circuit. Expressions for inductance can be derived analytically for none but the simplest geometries. In most practical cases, though, some approximation is required: The partial inductances of a pair of parallel conductors depicted in Figure 2.30 from Equation (2.124) is (assuming I1 = I2 = I): Lp1 = Lp11 − Lp12 Lp2 = Lp22 − Lp21

2 127

Equation (2.127) points to an interesting and extremely important conclusion: because the partial mutual inductance between two conductors increases as the distance between the conductors shrinks, whereas the partial self-inductance remains

Figure 2.29 Equivalent circuit apportioning the loop inductance into individual inductances associated with segments of the loop.

+ E2 − Lp22

I2

I1 Lp21

Lp23

Lp11

Lp24

Lp33

I3

I4

Lp44

35

36

2 Fundamental Concepts

+

E1 Lp11

unchanged, the total partial inductance decreases as the conductors are brought closer together, resulting in a reduction of inductive voltage drop developed across the conductors when brought closer together. The low-frequency partial self-inductance of a round wire with a length l and radius r (l r) is given by [6]:

− I1

Lp12 I2

−

Lp11 ○ = Lp22

Lp22 E2 +

Figure 2.30 Total partial inductance of two parallel conductors in free space.

○

= Lo-F

μl μl 2l + ln − 1 8π 2π r

2 128

In this expression, the first term is denoted as the internal partial self-inductance and the last term the external partial self-inductance. At high frequency (HF), the internal inductance vanishes, since the current is forced to flow on the surface only due to the skin effect,12 leaving: Lp11 ○ = Lp22

○

= Hi-F

μl 2l ln − 1 2π r

2 129

The low-frequency inductance of a pair of conductors with a rectangular cross-section (such as traces on PCBs) with a length l, thickness t, and width w (l w t) is similarly given by [5, 6]: Lp11 ▭ = Lp22

▭

= Lo-F

μl 8l 1 ln − 2π w+t 2

2 130

The HF inductance cannot be straightforwardly extracted from Equation (2.120), but was derived separately [5, 6, 10]: Lp11 ▭ = Lp22

▭

= Hi-F

μl 8l ln − 1 2π w

2 131

If the separation between the pair of conductors is d, l d cross-sectioned conductors can be approximated as [6, 10]: Lp12 ▭, ○ = Lp21

▭, ○

= Hi-F

w, r, the mutual inductance between round or rectangular

μl 2l d ln + 2π d l

2 132

Using Equations (2.127) and (2.128) through Equation (2.132), the HF total partial inductance for thin traces on PCBs is therefore derived: Lp1 ▭ = Lp2 ▭ =

μl 4d d ln − 2π w l

d

l

μl 4d ln 2π w

2 133

The above expressions will be found to be useful in discussions found in later chapters of this book.

2.3.5

External and Internal Inductance

No current can flow within the cross-section of perfect conductors and all current and charges exist on their surface only. Subsequently, magnetic flux occurs only outside the conductors; hence, inductance, as defined above, is termed external inductance. The concept of loop inductance derived above implicitly is considered external inductance only. Real-world conductors, however, exhibit high but finite conductivity, and some nonzero current distribution can be observed within such conductors. Consequently, some magnetic flux exists within a conductor, associated with the portion of current flowing internal to it, resulting in inductance internal to the conductor, called internal inductance. The frequency dependence of the internal inductance is observed to start at some DC value and begins to decrease as frequency increases, approaching zero at a rate proportional to 1/f 1/2. This decrease of internal inductance is due to the diminishing field penetration into the conductors (a.k.a. “skin effect” discussed in the next section). At very low frequencies, the fields are uniformly distributed throughout the cross-section conductor, and the total inductance approaches its value at DC (the combined external inductance and DC internal inductance, as shown above). At very high frequencies, only a small fraction of the field penetrates the conductor and the inductance approaches its HF limit (external inductance only). In the intermediate frequency range, the inductance has contributions due to both the external and internal inductances. In the high frequencies, where skin effect is small compared to the thickness of the metal, the internal inductance diminishes as frequency increases as 1/f 1/2. This behavior is illustrated in Figure 2.31, where a decrease in inductance (and subsequent increase in resistance) as frequency increases is observed for the intermediate frequencies. At the high frequencies, inductance approaches a constant (i.e. the external inductance). 12 Skin effect is discussed later in this chapter.

2.3 Intrinsic Inductance of Conductors and Interconnects

The internal inductance of a wire of circular cross-section with radius r, conductivity σ, permeability μ, and permittivity ε is given by [6] Lint,DC = Lint = Lint,HF =

μ ≈ 50nH m = 1 27nH in , 8π 2δ 1 Lint,DC = r 4π r

μ 1 , πσ f

δ

for r for r

R

√f

δ 2 134

where δ is the skin depth, defined in equation (2.134). Equation (2.134) demonstrates that the value of the internal inductance of wires with circular crosssection is upper-bound by 50 nH/m. When external inductance exceeds the internal inductance, total inductance is dominated by external inductance and hence the approximation in Equation (2.134). At very high frequencies or in the very small skin depth limit, the internal inductance could be approximated using the Wheeler incremental inductance rule, which related the internal inductance per unit length to resistance per unit length as follows [5]: Lint ≈

RDC

w, t >> δ

w, t 0.1λ, where wavelength, structure λ, corresponds to the highest frequency of concern) prevent the realization of a satisfactory reference at higher frequencies Figure 4.30 Common impedance coupling is not eliminated in the because of large reactive self-impedance of the ground bus. “daisy chain” (series connection) single-point grounding scheme. This is due to the voltage drop developed along the ground bus due to return currents. For instance, at point “C” which serves as the reference point for the most remote circuit, the voltage drop from this point to the GRP can, by observation, be expressed as V C = I1 + I2 + I3

Z1 + I 2 + I 3

Z2 + I 3 Z3

4 26

191

192

4 Fundamentals of Grounding Design

At point “A,” closest to the GRP, the voltage drop is equal to (ignoring the impedance of the connection to the reference structure): V A = I1 + I2 + I3

4 27

Z1

This configuration forces return signals from assemblies 2 and 3 to be impressed on assembly 1 if the distributed impedances along the line are not limited to very low values, undermining the objectives of SPG. “Daisy chain” SPG is often used in equipment racks. It should not be used, however, in systems comprising very diverse assemblies (with respect to their ground-noise emissions or susceptibility) such as high-gain amplifiers as this may introduce intra-system interference. Since high-power systems produce large return currents that share a common ground bus, sensitive components may be affected due to common-impedance coupling. If this approach must be used, the most sensitive component must be located at the point closest to the ground-reference (point “A” in Figure 4.30) and as far away as possible from highlevel components and circuits (which, in turn, should be placed at the far end of the ground bus, at point “C” in Figure 4.30). A superior approach could be employed, whereby separate branches are employed for systems of different emission levels and sensitivity thresholds. In practice, this results in the “nested grounding” architecture discussed later in this chapter. Another concern associated with this scheme is related to the high-frequency performance of this configuration. Owing to distributed stray capacitance along the ground bus to the SRS CS, “series” SPG scheme essentially ceases to function optimally as frequency is increased beyond several hundred kilohertz. Up to this point, the “electrical length” of the ground conductors was not considered. The conductors were assumed to be electrically short. As long as this condition prevails, the “daisy chain” scheme can be used to an advantage. At higher frequencies, when this assumption does not hold, and the length of the ground bus, ℓ, exceeds 0.1λ, grounding conductors running along the SRS exhibit transmission-line (T-line) behavior.20 Consequently, the RF impedance of the ground bus is dominated by (assuming a lossless conductor) a distributed (per-unit-length) inductance LX and capacitance CX (The distributed (per-unit-length) resistance and conductance of the ground bus, RX and GX, respectively, are not presented, since the line is assumed to be lossless) (Figure 4.31b). The point on the conductor connected to the GRP will be at zero-volt potential (“0 V”); however, other points along the line will exhibit a distance-dependent voltage and current distribution (VX and IX, respectively). Due to the varying distribution of

Assembly 1

Assembly 2

Assembly 3

Grounding bus GRP = ‶0 V ″ Signal reference S structure (a)

Assembly 1

Assembly 2 IX +

‶0 V ″

VX VX – Signal Sreference structure

CX

Assembly 3

LX

x

X

(b) Figure 4.31 A grounding conductor as a transmission line with the signal reference structure. (a) Actual circuit. (b) Equivalent transmissionline model of the ground bus (LX = distributed (per unit length) inductance, CX = distributed capacitance).

20 Transmission-line basics and phenomena are discussed in Chapter 2.

4.2 Fundamental Grounding Schemes

Figure 4.32 A 0 V ground potential is converted to “open circuit” (∞ V) at the point x = λ/4.

Zin →∞ x = l/4 Signal reference S structure

GRP = ‶0 V ″

Zin →∞

Vx, Ix

Vx Ix 0

x x = l/4

Vx = 0 = 0 V

Vx = l/4 = Vmax

Ix = 0 = Imax

Ix = l/4 = 0 A

the voltage and current along the transmission line, the impedance at any point along the line also varies. In particular, for a lossless T-line shorted at one end (to the “0 V” point) the input impedance at any point x along the line, at a frequency of concern, f, exhibits a periodic variation expressed as [9] Z in ≜

V in = jZ 0 tan β x = jZ 0 tan 2πf x I in

4 28

Lx C x

For lossless transmission lines, the phase velocity of the line, β, in rad/m, is equal to: β≈ω

Lx C x = 2πf

4 29

Lx Cx

and its characteristic impedance is: Z0 ≜

Vx = Ix

Lx Cx

4 30

In the special case where x = λ/4 at a particular frequency, the phase difference between the voltage and current distribution is π/2 radians (or 90 ). The short circuit at the load is transformed to the input as an effective “open circuit” resulting in infinitely large input impedance at the frequency associated with this wavelength, λ: Z in = jZ 0 tan

π 2

x = 4λ

∞

4 31

This situation finds its equivalence, in circuit theory, in a tuned parallel resonant circuit, which exhibits infinitely high input impedance when at resonance (Figure 4.32). Moving away from the “0 V” GRP along the grounding conductor, the input impedance will alternate between Zi ∞ and Zi = 0 for parallel and series resonance of the T-line at odd and even multiples of λ/4, respectively, occurring at (Figure 4.33): a) x = 2k + 1 b) x = 2k

λ , 4

k = 0,1,2…, parallel resonances, where |Zin|

∞

λ , k = 1,2…, series resonances, where |Zin| = 0 4

In practice, transmission line resonant effects are superimposed on the AC resistance of the line; therefore, at series resonance frequencies, occurring in case (b), |Zin| RAC. The line input impedance is therefore superimposed on the curve of the line AC resistance, RAC (Figure 4.33). In practice, this results in the equipment located at all points x = (2k + 1) λ/4 along the grounding conductor, being practically isolated from the signal reference at the resonance frequency. In general, for any given frequency, the input impedance, Zin, will vary at different points, x, along the ground bus; conversely, at a given point, x, along the ground bus the input impedance, Zin, will exhibit a frequency dependence, appearing inductive, capacitive, open circuit, or pure resistance, providing, therefore, an extremely poor and unreliable ground reference. Furthermore, in the presence of broadband signals such as high-speed digital, tuned circuits will ring at specific frequencies at which they are resonant. This situation is not an EMC problem per sé but may evolve into one if a large RF voltage drop develops along the ground bus, resulting in enhanced emission or EMI pickup. This situation, however, could definitely result in functionality concerns.

193

4 Fundamentals of Grounding Design

Figure 4.33 Parallel and series resonances along a ground bus, |Zin| (Ω) vs. frequency, for the dimensions in (a). (a) Circuit configuration. (b) Input impedance of structure, |Zin| (Ω).

r = 1cm Ground bus Z0 = 100 Ω l = 1m

Zin(x)

Z=0

X=1m

GRP

Signal reference structure (a)

1000

Δ

Zin =

100 Input impedance, Ω

194

VIn IIn

= Z0 ·tan(β·x)

10 1 0.1 0.01 0.001 RAC ≈

0.0001 0.00001 0.01

0.1

1

ρL ρL ≈ Ω π (D – δ) δ πDδ

10

100

1000

10000

Frequency, MHz (b)

4.2.2.2.2 “Star” (Parallel Connection) Single-Point Grounding Scheme

The ideal single-point signal ground network is the “star” or parallel connection. In this scheme (Figure 4.34), a single physical location in the system is defined as the GRP. From this point, separate and dedicated ground conductors extend to the return side of each circuit. This configuration requires a considerable number of conductors, which is generally not practical in large, distributed systems.

Power supply

Z

Z

Electronic assembly with internal circuit/s

Z

Z

Z

Z Z

Z

Z Z

Electrical safety SPG Power source

Signal/logic SPG

Interconnection between grounding points Reference structure

Z

Reference structure

Figure 4.34 “Star” (parallel connection) single-point grounding scheme.

4.2 Fundamental Grounding Schemes

Figure 4.35 “Star” (parallel connection) singlepoint grounding topology minimized the effects of common impedance coupling.

Power supply

Z

Z

Z

Z

Z Z

Electrical safety SPG Power source connected to reference structure

Z

Z

Signal/logic SPG connected to reference structure

Reference structure

The SPG scheme accomplishes the functions of signal return, while helping control common-impedance-coupled interference between systems. As illustrated in Figure 4.35 for three assemblies, closed-loop paths for noise currents, which otherwise could exist, in the signal grounding network are avoided. The interference voltage in the signal reference is not coupled into the signal circuit paths. Hence, potential differences produced by lower frequency noise currents have little or no effect on system performance. Since each of the systems has a dedicated and independent signal-return path, common-impedance coupling between different branches is also precluded. Similar to the “daisy chain” topology, the “star” configuration when used in large systems suffers from the same major problem associated with unavoidably long return conductors interconnecting circuits or systems and a GRP, in particular, the T-line resonant effects along the long return conductors, discussed in detail in the previous section. Furthermore, return conductors of different lengths may result in the circuits connected to them sensing different impedance to the GRP for a given frequency. This may result in functionality and EMI concerns. The length of return conductors in a “star” topology may increase emissions from or EMI pickup by the return conductors. The electrically long grounding conductors constitute efficient radiators, resulting in increased radiated emissions and crosstalk, or enhanced EMI pickup, depending on their respective physical spacing and layout. The extent of the radiation and crosstalk that may take place will also be a function of the spectral content of the return signal: higher frequency components will radiate and couple more efficiently than lower frequency components. Figure 4.36 illustrates how crosstalk can be generated between ground conductors in a “star” grounding scheme. Similar to the “daisy chain” scheme, distributed stray capacitance to the signal reference, CS, is present across the system (Figure 4.34); therefore, effective SPG essentially ceases to exist as the signal frequency is increased. SPG scheme cannot be easily implemented and is particularly violated in real-world systems where a multiplicity of connections to the SRS exists. An example of a potential violation is to have a single-point ground area where one additional grounding connection occurs at a remote point within the electronic load equipment that is normally designed to be grounded only at a single point. Such a connection may be intentional or unintentional. This configuration would provide a well-defined and concentrated current path through the electronic load equipment, which could cause performance problems or component damage. Consider, for instance, coaxial cables (where the shield actually serves as the signal-return path), used to interface between different assemblies, with the shield of the cable interconnecting the circuits’ return and their cabinets or enclosures, in order to ensure functionality (Figure 4.37a). In the presence of low-frequency magnetic fields, for instance, induced electromotive force (emf ) due to the magnetic fields in the large loop shown in Figure 4.37a will occur. As the performance of cable shields is limited at lower frequencies,21 significant coupling of such interference into the circuits may occur. If, however, the shield of the coaxial cable is floated from the enclosure (i.e. not terminated or bonded to the enclosure), violation of the shielding integrity could result (Figure 4.37b). 21 Performance of cable shields is discussed in Chapter 11.

195

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4 Fundamentals of Grounding Design

Mutual coupling Return conductor #1 Impedance of return conductor #1

Return conductor #1 Return conductor #2

(a)

M M C

Return conductor #2 Impedance of return conductor #2

(b)

Figure 4.36 Mutual coupling (crosstalk) between grounding conductors in a “star” single-point grounding scheme. (a) Physical application of the ground lug connection at the GRP. (b) Equivalent circuit.

System #1

ES1

System #2

System #3

Coaxial cable

ESGC (safety ground) Safety Signal Power

“Ground loop” GRP Signal reference structure

(a) Shield integrity violation

ES1

Coaxial cable EMI on coax outer conductor

System #1

System #2

System #3

ESGC (safety ground) Safety

GRP

Signal Power

Signal reference structure

(b) Figure 4.37 Problems associated with coaxial interconnects in a “star” SPG configuration. (a) Outer conductor of coaxial cable grounded to System #1 and System #2 enclosures, compromising the single-point grounding. (b) Coax’s outer conductor not grounded to enclosure, violating the enclosure’s shielding integrity.

It is concluded that use of the “star” grounding topology is limited to the lower frequencies, that is, DC up to 300 kHz, approximately. Typical applications of the “star” topology include audio circuits, analog instrumentation, DC and AC (50/60 Hz) power systems, and similar circuit applications. Nevertheless, even when used in lower frequencies, attention must be paid to the implementation of this scheme, particularly where large loops are produced and high levels of low-frequency ambient magnetic fields are present. In certain cases, “star” grounding configurations may also be found in higher frequency applications, where attention must be paid to proper implementation and functional use.

4.2 Fundamental Grounding Schemes

• • • •

The Least You Need to Know The two SPG schemes – “daisy chain” and “star” – are limited in their practical applications to lower frequency currents, primarily due to the electrical length of the grounding conductors at higher frequencies. Due to distributed stray capacitance to the SRS along each circuit, SPG essentially ceases to exist at higher frequencies, generally 300 kHz and above. T-line resonant effects along the long return conductors used in both SPG schemes could result in high impedance to the ground reference, observed by the equipment counteracting a desired low-impedance ground-reference connection. Because of the aforementioned reasons, use of all variants of the SPG schemes is not practical at high frequencies, where length of the return conductor exceeds 0.1λ.

4.2.2.3

Multipoint Grounding (MPG) Scheme

As discussed with respect to floating systems and SPG schemes, distributed stray (parasitic) capacitance is present from each circuit and along the return conductors to the signal reference. At high frequencies where the length of the return conductor exceeds 0.1λ, SPG essentially ceases to function in an optimal manner. This reason subsequently leads to the logical postulate that “if you can’t fight them, join them.” In other words, if circuits were grounded at multiple points, it would be best to implement those connections to a massive, solid conducting plane in a controlled manner. This grounding method forms a homogenous low-impedance path between circuits. The plane also serves as a high-quality (alas, nonideal) equipotential reference. The MPG scheme is illustrated in Figure 4.38. MPG benefits from the simplicity of system or circuit construction owing to the fact that physically long conductors are no longer required for connection to the reference structure, ensuring they are effectively bonded to it (Figure 4.39). In addition, and no less important, the quality of the SRS must be carefully implemented and maintained. Furthermore, MPG precludes standing-wave and resonance effects at higher frequencies22 on the grounding conductors (however, it does not eliminate resonances of the reference structure or ground planes, as discussed in Section 4.1.3). MPG is frequently the favored technique in higher frequency circuits, (e.g. digital, video, and RF circuits), permitting easy use of coaxial cables. This is because the shield of the coaxial cable does not have to be floated relative to the equipment cabinet or enclosure and can be grounded without violating the system’s chosen grounding methodology. MPG of circuits and equipment minimizes the likelihood for all types of return currents flowing in the SRS to concentrate in a narrow common return path (thus minimizing near-field interactions and ground-coupled interference). One of the most common objections to MPG, however, is that different signal types will, in fact, mutually interact, as they share a common reference structure. There is both truth and fiction in this view of MPG scheme. The truth is that all evils ascribed to this design are quite possible and could happen when objectionable design measures are implemented, and also when all return connections are left Figure 4.38

Multipoint grounding scheme.

Electronic assembly with internal circuit/s

Power supply

Z Z Z

Z Z

Power source not connected to reference structure

22 Techniques for preclusion of such standing waves are discussed in Chapter 13.

Electrical system grounding point

197

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4 Fundamentals of Grounding Design

ES1

I1 + I2 + I3

A I1

System #1 Z1

ZG1

B I2 ZG2

I2 + I3

System #2

System #3 I3

Z2

ZG3

C Z3

I3

ESGC (safety ground) Safety Signal Power

Signal reference structure Figure 4.39

Common impedance coupling is inherently generated in the multipoint grounding scheme.

undefined by the designer. The fiction lies in the fact that MPG is not optimal and must be avoided at any cost in favor of one of the previously described grounding schemes. Where does the difference lie? It is simply a matter of how MPG is implemented. Making low-impedance connections to a properly designed signal reference is what produces all the benefits associated with MPG. To prevent adverse effects resulting from the naturally resultant ground loops, the layout of the system and particularly its respective interconnects become extremely important. MPG, in particular, finds application in systems and circuits operating at or above frequencies at which length of the return conductors would otherwise exceed 0.1λ, such as RF circuits, high-speed digital circuits and systems, printed circuit boards (PCBs), and data networks. In high-frequency PCBs, for instance, MPG is implemented between the return planes in a PCB and the return plane in a backplane or motherboard to the equipment chassis. The implementation of such a configuration is schematically depicted in Figure 4.40.23 Of course, in poor designs, not taking into consideration the nature of the signals, mutual interaction between different return currents is likely to occur, particularly at the lower frequencies, where return currents tend to “spread” and generally follow the shortest path (in most cases) (Figure 4.41a). At the higher frequencies, however, the physical principle “Current, if Not Obstructed, will Always Follow the Path of Least Impedance24” guarantees that return currents will follow the path of the least inductance, i.e. the path of the signal conductor (Figure 4.41b). This principle is valid both at system or board level and simply guarantees that appropriate layout of the interconnected equipment or circuits can provide a well-controlled path of return currents and preclude undesired interactions between the various return currents, as long as the designer is mindful of the manner of current return.

Signal return plane within each PCB

ES1

Circuit #1

Circuit #2 Signal return plane

Circuit #3

Within the backplane

Return/ground Signal Power

Signal reference structure Figure 4.40

Multipoint grounding topology in a backplane.

23 Grounding design and implementation in PCBs are discussed in Chapter 13. 24 The “Path of Least Impedance” principle is discussed in detail in Chapter 2.

4.2 Fundamental Grounding Schemes

Figure 4.41 Low- and highfrequency current-return paths in the signal reference structure. (a) Current return path at low frequencies. (b) Current return path at high frequencies.

(a)

(b)

In using MPG, it is presumed that the signal reference serving as the signal-current-return path exhibits extremely low impedance between any two points. As such, it approximates an equipotential structure at any frequency of concern. If this were not the case, common impedance coupling could occur between the circuits owing to the fact that the return currents from all circuits flow through the same path, introducing common impedance and offering no significant advantage for this topology over the “daisy chain” configuration depicted of Figure 4.30, as illustrated in Figure 4.39. It is important to keep in mind, however, that when applied to high-frequency signals (as would typically be the case), there is no need to construct massive planes as SRSs for the purpose of reducing the impedance of the return path. Keeping in mind that at higher frequencies, the effective cross section of the current flow path is dominated by skin effect,25 diminishing proportionally to square root of frequency. Therefore, regardless of thickness of the reference structure, current will remain on its skin, closest to the signal conductors. For instance, in copper, skin depth vs frequency is provided in Table 4.1. As the copper in a PCB is rated in ounces, and represents the thickness of 1 ounce (oz.) of copper rolled out to an area of 1 ft2, clearly a PCB ground plane using 1 oz. copper has a thickness of 1.4 mils which, by far, exceeds skin depth at 100 MHz and beyond (Table 4.2). Below that frequency, thickness of the plane needs to be considered. Therefore, in high-frequency/high-speed PCBs, the primary consideration for setting the ground plane thickness will be the DC supply current rather than the AC signals. Contrary to common belief, unlike snake oil, multipoint grounding systems are not the cure for all. Table 4.1

Skin depth in copper vs frequency. Skin depth

Frequency

μm

mils

50 Hz

9220

362.99

100 kHz

206

8.11

1 MHz

65.2

2.57

10 MHz

20.6

0.81

100 MHz

6.52

0.26

1 GHz

2.06

0.081

Table 4.2

Copper weight and thickness in a PCB.

Weight (oz.)

Thickness (mils)

1/2

0.7

1

1.4

2

2.8

25 Skin effect is discussed in detail in Chapter 2.

199

200

4 Fundamentals of Grounding Design

ESM (28 V)

Motor PWM current, IM

PWM motor driver

ES1 (3.3 V) Signal current, IS System #2 System #1

VNG ZG1–2S

Figure 4.42

M System #3

PWM motor

Motor current, IM Signal reference structure

ZG2–3

Poor design can produce interference coupling in multipoint ground configurations.

The (contrary) belief that the signal reference exhibits a close-to-perfect equipotential behavior often leads to inferior designs when due consideration is not paid to practical limitations. Current from other sources may be sharing the same return path through the signal reference, whether intentionally or unintentionally. Observe, for instance, the situation from Figure 4.38, illustrated in Figure 4.42 with modification. In this circuit, a PWM motor drive is collocated on the same PCB used for the 3.3 V-powered logic circuitry, pumping current (e.g. 12 A) to the motor. The design was such that the motor drive’s return current from the motor, developing potentially large high-frequency noise across the ground plane impedance, shared with the digital circuitry. This interference voltage will couple into the digital circuits and may disrupt or degrade their performance. This situation constitutes a very poor system design! Good judgment comes from experience, and experience comes from bad judgment. — Rita Mae Brown, Alma Mater Since a large conductive mass can easily be employed for the signal reference, it is often assumed that extremely low impedance between any ground-connection points will guarantee little voltage potential difference between the systems, thus ensuring proper performance. However, reality often dictates otherwise, mainly due to misinterpretation of the MPG concept and objectives. Returning to Figure 4.39, the source of this misapprehension is clearly revealed. When considering the ground impedance, merely taking into account the impedance of the ground structure itself (represented as ZG1, ZG2, and ZG3 in Figure 4.39), the impedances from the systems to the connection points on the ground reference structure (Z1, Z2, and Z3 in Figure 4.39) are neglected. Actually, low impedance should exist between the reference points in the systems (marked A, B, and C in Figure 4.39). Failing to consider the length of grounding leads from systems to grounding points on the signal reference will lead to increased (inductive) impedance between those points, contradicting the objectives of MPG. Merely connecting subsystems to different points on the signal reference, even if it exhibits absolutely zero impedance, does not constitute effective MPG, unless the spirit of this scheme can be observed, that of maintaining low impedance between all reference points throughout the system at the frequencies of concern. In addition, care must be taken when implementing MPG, since numerous ground loops26 are inherently created in this scheme between each ground connection physically distant from other ground connections. These ground loops, in addition to the potential conductive coupling discussed earlier, are prone to magnetic field coupling of RF energy, or may produce EMI emissions, compromising the performance of the system.

• ••

The Least You Need to Know MPG is a preferred grounding topology for signal circuits and systems operating at higher frequencies (where the length of the return conductors exceeds 0.1λ), overcoming the shortcomings of floating systems and SPG topologies. MPG is the only way to avoid standing-wave and resonance effects in ground conductors at higher frequencies. MPG is appropriate for high-frequency applications, where current follows the path of least inductance. Appropriate layout of the interconnected equipment or circuits will provide a well-controlled path of return currents and preclude undesired interactions between the various return currents.

26 Ground loops are discussed later in this chapter.

4.2 Fundamental Grounding Schemes

• •

Effectiveness of MPG requires that the spirit of this scheme be observed, namely, maintaining a low-impedance connection between all reference points throughout the system. Care must be taken to ensure that power frequency and other higher amplitude lower frequency return currents flowing through the common-SRS do not conductively couple into sensitive signal circuits sharing the same plane, for preclusion of intolerable interference to susceptible circuits.

4.2.2.4

Composite (Hybrid) Grounding Scheme

Typically, SPG is used in lower frequency analog systems in which low-level signal amplitudes are involved. In such systems, voltage drops in the signal reference on the order of millivolts and even microvolts can have significant effects on the system performance due to common-impedance coupling interactions. SPG may also be required to be utilized for high-level “noisy” subsystems such as motor drives and solenoids, where the single-point ground is intended to preclude return currents of those systems from flowing through the signal-reference structure, producing high-voltage drops across the reference common to other sensitive circuits. Digital circuits, on the other hand, exhibit an intrinsic immunity to externally introduced interference at reasonable levels. On the other hand, they may adversely respond to noise generated within the circuit.27 In that respect, digital devices, particularly low-level, high-speed devices, are self-defeating, due both to internal noise and common-impedance coupling within the digital devices themselves. MPG is best suited for this situation. They make use of large and “solid” ground planes, thereby effectively reducing the impedance of the return path. Mathematical modeling and predictions of EMI problems arising from grounding are exceptionally difficult to undertake for any but very simple and generic situations, or for SPG configurations. Stray reactance, capacitance, and inductance radically affect the high-frequency performance of the grounding system. Adding uncertainty associated with their value, which cannot, in practice, be appropriately estimated, interactions within the grounding system become exceedingly complex. With the absence of mathematical tools to analyze this situation, a general selection criterion for determining whether singlepoint or MPG should be considered is, therefore, is suggested. In most cases, the choice of the appropriate grounding scheme was shown to abide by the following ground rules [8, 10]: a ℓ < 0 1λ or 30 f b ℓ ≥ 0 1λ or 30 f

Single point grounding Multipoint grounding

4 32

where: ℓ = distance from the unit ground to the GRP (m) f = highest operational frequency in the system (MHz) λ = wavelength associated with the frequency f (m) In practice, SPG, in either series or parallel connection, is best for frequencies below 1 MHz, approximately (use of series connection may be somewhat more limited to the lower frequencies), while MPG is preferred at frequencies exceeding 1 MHz (Figure 4.43). Practical systems and often, even single PCBs (considering that contemporary PCBs may, by their own merit, be “systems on board”) may consist of both low-frequency (e.g. audio circuits) and high-frequency circuits (e.g. RF and high-speed digital circuits) (Figure 4.43). Such situations entail the application of appropriate, system-wide grounding schemes. The best approach for grounding of such systems is the application of a composite (hybrid) scheme, offering the benefit of both SPG and MPG. Higher frequency components will benefit from MPG. From the standpoint of low-frequency components, they possess only a single common reference, whereas from the perspective of the higher frequency components, a system-wide MPG is implemented (Figure 4.44).

Single-point (series) Single-point (star) Multi point 0.01

0.1

1

10

100

Figure 4.43 Frequency limitations of grounding schemes.

27 Chapter 13 discusses grounding considerations in printed circuits boards.

1000

10 000

Frequency, MHz

201

202

4 Fundamentals of Grounding Design

Figure 4.44 Practical systems consisting of both low- and highfrequency circuits, entail application of composite system-wide grounding schemes.

Single-point grounding Serial Star

Z

Z

Z Z

Z

Z

Z

Z Z Z

Z

Z

Signal/logic SPG

Electrical safety SPG

Signal/logic SPG

Electrical safety SPG Z

Z

Z

Multi point grounding

Multi point grounding

Z

Reference structure

System #1

System #2

System #3

System #4 Digital, HF power source

Analog, LF power source

ESD

ESA

GRP Common system-wide signal reference structure

Figure 4.45 Composite (hybrid) grounding scheme.

As observed in Figure 4.45, illustrating a simplified situation, Systems #1 and #2 utilize SPG, whereas Systems #3 and #4 are multipoint grounded. However, the configuration depicted in Figure 4.45, which at first glance seems to be an ideal solution for such situations, may be deceptive. Implementation of composite grounding schemes require due consideration to be paid to such items as:

•• •

Power supply distribution Relative routing of signal and return path Type of signaling between the circuits (analog or digital)

Attention must be paid to ascertain that grounding performance is not compromised when such arrangements are applied.28 Figure 4.46a presents a circuit similar to that of Figure 4.45; however, the same power source is shared by the two system groups. Moreover, due to lack of foresight and poor design, the power source was placed adjacent to the digital circuits, whereby the sensitive, low-level analog circuits experienced the ground noise generated by the digital signal-return current in the signal reference structure. If both power and return conductors exhibit high impedance, common-impedance coupling will be developed across the signal reference and along the high-level digital return path. At first glance, this would not seem to constitute a problem since a voltage drop VNG occurs in the digital current-return path only (high-speed signals return in the path of least inductance); however, a second glance reveals that the same path is shared by the low-level analog circuits. This situation, in fact, is equivalent to that depicted in Figure 4.30 for the “series” SPG configuration, along with its disadvantages. A solution to the undesired situation is provided in Figure 4.46b. The circuit, essentially, did not change; however, the return conductor of the common power supply is now connected at a point common to the low-power analog return. In this case, little or no voltage drop occurs across the analog return current path but, rather, along the digital return path only. 28 On PCBs, this dilemma is realized in mixed analog and digital circuits, comprising ADCs and DACs. This is discussed in Chapter 13.

4.2 Fundamental Grounding Schemes Low-level sensitive analog circuits System #1

High-level noisy digital circuits System #2

System #3

System #4 Common power source ES Common-impedance coupling affecting low level analog return path

GRP

ING

VNG

Common system-wide signal reference structure

(a) Low-level sensitive analog circuits System #1 System #2

High-level noisy digital circuits System #3

System #4

Common power source ES ZGC GRP

IDR

IDR

Common-impedance coupling eliminated VNG ZG

IDR Common system-wide signal reference structure

(b) Figure 4.46 Compromise of grounding performance due to system arrangement with composite grounding scheme: common power supply and return path. (a) Objectionable implementation: common-impedance coupling. (b) Better implementation: common-impedance coupling eliminated.

Low-level sensitive analog circuits System #1 System #2

High-level noisy digital circuits System #3

System #4 Analog, LF power source

Common power source

ESD

ESA Common-impedance coupling eliminated GRP

ING Common system-wide signal reference structure

Figure 4.47 Composite grounding with power source separation.

In an attempt to eliminate the interference coupling mechanism due to the common-current-return path, an alternative approach is proposed, whereby dedicated power supplies for each of the circuits, analog and digital, are provided. This is illustrated in Figure 4.47. Normally this configuration should function properly since the two circuits utilize a common low-impedance signal reference. However, other concerns may result, not necessarily related to EMC but, rather, to functionality concerns, including: a) Voltage difference between separate power supplies. For the circuits to function properly, the voltage difference should be controlled. For instance, interfacing between 5 and 3.3 V circuits may require buffering for level adjustment between circuits. b) Start-up order of the power sources: Often, different power sources are generated from a multioutput switch-mode power supply (SMPS) or from separate independent power supplies. The order in which the power sources are turned on may be

203

204

4 Fundamentals of Grounding Design

critical, since damage or improper functionality may result if different power sources do not start up in a predetermined order, either because of circuit start-up issues, or simply due to voltage differences present between two power sources. For instance, when interfacing 5 and 3.3 V circuits, it is often required that the difference between the power sources not exceed 1.9 V. This requires that the order of and delay between the 5 and 3.3 V power sources upon start-up be well controlled.

•

The Least You Need to Know Composite grounding schemes are very common in mixed analog–digital circuits and systems, and, when properly designed, maintain the necessary grounding design for each application.

4.2.2.5 Frequency-Selective Grounding

In addition to the aforementioned fundamental grounding schemes, namely, SPG and MPG, situations occur in which a special case of the hybrid grounding scheme may be utilized, constituting a combination of SPG and MPG simultaneously, depending on the functionality of the circuit and frequencies of concern. Hybrid grounding is used in those special circumstances where: 1) SPG may be required at lower frequencies and MPG at higher frequencies. 2) MPG may be required at lower frequencies and SPG at higher frequencies. Observe, for instance, Figure 4.48, depicting two systems that have a low-level, low-frequency (e.g. audio-frequency), singleended I/O interface. In this circuit, both the source (System #1) and the load (System #2) appear to be internally grounded to their respective enclosures, which, in turn, are both bonded to a common SRS. The shield of the interconnecting cable (also intended to act as the return path for the single-ended interface) is grounding to the chassis of each of the enclosures. As this system must rely on MPG for its functionality, conflicting concerns due to common-impedance coupling may introduce unacceptable interference. Due to the lower impedance of the signal reference structure, most of the low-frequency return current will probably follow this path rather than through the intended return path, the shield (thus contributing to the flux cancellation and the higher noise immunity of the system). In fact, a system, if better designed, for instance, by using a differential rather than a singleended interface, would probably utilize a single- point signal grounding topology. The situation may be worse if a high-level, low-frequency noise-source (e.g. a PWM motor) current shares the same return-current path through the signal reference structure. One possible solution is to “float” one of the enclosures29 (Figure 4.49). In this case, a SPG configuration has actually been reestablished. This will do for low-frequency environments (say, up to 300 kHz or so), but in a high-frequency radiated environment, RF currents will be induced on the cable shield. Thus, MPG may be desired for RF interference control purposes. Figure 4.50 offers an excellent solution: capacitively grounding the circuit will provide a controlled high-frequency multipoint ground connection while maintaining low-frequency SPG. Motor PWM current, IM

PWM motor driver

System #1

Interference current, II

Motor current, IM

System #2

PWM motor

VNG Signal reference structure

Figure 4.48

M

ZG

Common-impedance coupling in a low-frequency system using multipoint grounding.

29 Note that when safety codes mandate grounding of the enclosure for electrical safety purposes, safety requirements must take precedence and should be followed. This comment applies to any of the examples discussed in this section associated with “floating” circuits and equipment at lower frequencies.

4.2 Fundamental Grounding Schemes Motor PWM current, IM

PWM motor driver

M System #1

System #2

Motor current, IM

Figure 4.49

“Floatation” of System #2

VNG

Signal reference structure

PWM motor

ZG

Floatation of System #2 for elimination of common-impedance coupling.

Motor PWM current, IM

PWM motor driver

M System #1

System #2 High frequency ground

Motor current, IM

PWM motor

C

VNG Signal reference structure

ZG

Figure 4.50 Capacitive selective grounding exhibits low frequency single-point grounding and high-frequency multipoint grounding.

Dielectric compound System #2 C = ε⋅

d

System #1

Signal reference structure Figure 4.51

ZG

A d

A

Dielectric spacer used to implement distributed capacitive selective grounding for an enclosure.

Typical values of this high-frequency capacitance range from 1 to 10 nF depending on the frequency of concern. This capacitance may be implemented using discrete capacitors (in PCB-related applications),30 or, for enclosure grounding, by implementing a capacitance by placing a dielectric compound between the enclosure and the SRS (Figure 4.51). Another approach to a solution is shown in Figure 4.52. In this case, the enclosure of both circuits is grounded. Lowfrequency SPG is implemented by capacitively grounding the cable rather than the enclosure.31 A practical implementation of this approach is depicted in Figure 4.53, where a multiple-shield triaxial32 cable configuration is used [11]. In this configuration, the inner shield is connected to the signal reference at one end only. The outer shield is

30 Selective grounding implementation on PCBs is discussed in Chapter 13. 31 Grounding of cable shields is discussed in Chapter 11. 32 A triaxial cable consists of an inner conductor, an internal shield (often serving as the signal return), and an outer shield.

205

206

4 Fundamentals of Grounding Design Motor PWM current, IM

PWM motor driver

M

C System #1 Low frequency ground VNG

Motor current, IM Signal reference structure

Figure 4.52

System #2 Low frequency ground

PWM motor

ZG

Capacitive selective grounding implemented in the grounding of the cable shield.

Figure 4.53 Using frequency-selective shield termination in high-impedance low-frequency circuits. (a) Physical configuration. (b) Circuit representation.

Inner shield Center conductor

Inter-shield capacitance

ZS Low-F signal current

Outer shield

Ground noise – VG +

Signal reference structure

ZL Low-F ground noise current

(a) Inner shield ZS

Center conductor

Lo-F signal Hi-F shield noise current current flow Inter-shield capacitance

ZL

Lo-F ground noise current

Signal reference structure

(b)

connected to the signal reference at the other end. Low-frequency isolation is maintained between the two shields along their entire length. Assume the inner shield is used as the signal return path. Thanks to this isolation, the low-frequency signal current returns to the source on the inner shield, also acting as the return conductor, keeping off the SRS. As a result, excellent flux cancellation is achieved, and little radiated emissions will result. High-frequency noise on the other hand which may couple to the shield is effectively shunted to the SRS, thanks to highfrequency coupling between the inner and outer shield afforded by the inter-shield capacitance. It follows that from knowledge of the interference frequency, the geometry of the triaxial cable can be determined so as to provide necessary low-impedance coupling. The per-unit-length inter-shield capacitance is approximated as [11]: CM =

2πε0 εr F m ln r os r is

4 33

4.2 Fundamental Grounding Schemes

where rsh and ris signify the radii of the outer shield and the inner shield, respectively, while ε0 and εr represent the permittivity of free space and the relative permittivity of the dielectric between the outer and inner shields. Thanks to the capacitive coupling between the shields, in effect between the return conductor and the SRS, low-frequency interference cannot couple efficiently into the circuit and degrade its performance while effective high-frequency shielding is maintained. A third example of capacitive frequency-selective grounding implementation on PCBs is depicted in Figure 4.54. In this case, a section of a mixed analog–digital circuit33 is depicted, with a “bridge” existing between the analog ground (AGND) and digital ground (DGND), required for adequate performance of the circuit. DGND, with its high-frequency content is assumed to be “stitched” to chassis while AGND, when processing lower frequency content,34 is connected to chassis through discrete capacitors, providing frequencyselective chassis connection of AGND. This technique is especially beneficial in some low-frequency, high-load-impedance circuits, where terminating the shield at both ends may cause low-frequency noise currents on the shield to couple into the circuit. Figure 4.54 Using frequencyIn summary, capacitive selective grounding eliminates low-frequency EMI ground loops selective shield termination in highimpedance low-frequency circuits. while maintaining high-frequency grounding performance. An opposite situation may occur when several systems are interconnected via a singleended slow digital interface (e.g. RS-232); however, each of the systems must be grounded at one location (hence implying a MPG topology) at low frequencies for meeting electrical safety codes. However, the ESGC (the “green wire”) often carries high-frequency RF current, which may penetrate the equipment through the single-ended RS-232 signal link (Figure 4.55). In this case, “floating” is impractical, as this would compromise the electrical safety of the system. Hence, adequate grounding at lower frequencies must be maintained. High impedance to RF noise is desired, however, in order to “block” interference current from propagating through the system. This high impedance is achieved by inserting an “AC block” RF choke (inductor) in series with the ESGC (Figure 4.56). At higher frequencies, the system now exhibits SPG, while at lower frequencies, it exhibits MPG. High-frequency noise propagation is precluded while electrical safety is maintained. Typical values of inductance appropriate for this application range up to 100 nH, which at 50 Hz power frequency has an impedance of 30 mΩ, which is less than the maximum allowable resistance to ground for safety purposes, which is typically 100 mΩ; hence, electrical safety is not compromised. In summary, inductive selective grounding isolates the signal return from the ESGC, thus eliminating high-frequency EMI ground loops while maintaining low-frequency safety grounding at the power frequency. Incorporating capacitors or inductors in a grounding scheme allows us to steer RF currents in a manner that is optimal for the system design. One can take control of the system’s performance at low and high frequencies by defining the path that RF return currents will take. Failure to locate the RF current-return path may result in either emissions or susceptibility problems.

Power supply

Computer CPU

AC power

Peripheral

Slow RS-232 link Interference current, II System #1 ESGC

System #2

ESGC

ESGC VNG Signal reference structure

Figure 4.55

ZG

Interference coupling via the ESGC in a low-frequency RS-232 link using multipoint grounding.

33 Grounding in mixed analog–digital circuits and chassis stitching are discussed in detail in Chapter 13. 34 In cases that the analog portion of the circuit also processes high-frequency signals, multipoint grounding of AGND may be more appropriate.

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4 Fundamentals of Grounding Design

Computer CPU

Power supply

Peripheral

AC power Slow RS-232 link

System #1 ESGC

ESGC

System #2

L

ESGC

L

VNG S Signal reference structure Figure 4.56

• •• •

ZG

Inductive selective grounding provides high-frequency single-point grounding and low-frequency multi point grounding.

The Least You Need to Know Frequency-selective grounding combines the characteristics of single-point and MPG by incorporating reactive elements (capacitors and inductors). Capacitive-selective grounding eliminates low-frequency EMI ground loops while maintaining high-frequency grounding. Inductive-selective grounding eliminates high-frequency EMI ground loops while maintaining low-frequency grounding. Hybrid grounding finds applications in circuit and cable grounding.

4.2.3

Grounding Schemes in Complex Systems

The previous section addressed the more common, or standard grounding schemes. In the following sections, some special schemes are presented, which apply to more specific applications.

4.2.3.1 Distributed Single-Point Grounding

The distributed SPG scheme constitutes a special case of composite/hybrid grounding, and could be considered as a combination of MPG and SPG. Distributed SPG consists of multiple, isolated system grounding points common to an isolated set of equipment (i.e. single-point ground) referenced to a large common-conductive structure, such as “equipotential islands” on a nonconductive vehicle structure (Figure 4.57). Distributed SPG finds its most common application in primary power distribution networks of large vehicles, such as multistage launch vehicles (Figure 4.58) [12, 13] and facilities in which different primary power sources (e.g. 115/230 VAC, 24/28 VDC) are used to feed separate clusters of equipment and subsystems. In such vehicles and facilities, the performance of certain systems (such as mission- or safety-critical equipment) should not be dependent on the presence or absence of other systems, subsystems, equipment, or assemblies comprising the vehicles or facility. In space systems, in particular, no current should intentionally flow through the spacecraft structure. This entails that very special care be paid to interconnects between circuits and assemblies in the different stages, such as between telemetry systems and avionics systems, each being grounded to a different node.

System #1

System cluster #1 System #2

System #3

Common power source E#1

Common power source E#2

GRP #1

ING Common system-wide signal reference structure

Figure 4.57

System cluster #2 System #4

Distributed single-point grounding separation.

GRP #2

4.2 Fundamental Grounding Schemes

4.2.3.2

“Soft” Grounding

Z

Z

Stage #3 satellite segment

Z Electrical power SPG

Signal/ logic SPG Z Z

Z

Upper stage #2 segment

Z Z Z

Z Z

Z

Electrical power SPG

If the missile internal power distribution network is grounded to the missile chassis, it follows that during the “captive flight” mode, it is multipoint grounded, both to the host aircraft chassis as well as to the missile chassis, resulting in ground loops. If the missile power system is “floating” internally, while during the “captive flight” it is (single-point) grounded to the host aircraft chassis, it follows that during “free flight” the missile power system is completely “floating,” with its own drawbacks.

Z

Signal/ logic SPG

•

Z

Z

•

Launch vehicle

Electrical power SPG

In certain applications, “hard grounding” (i.e. low-impedance connection between the equipment and chassis) is not desired, particularly when the grounding scheme of the primary power distribution network is concerned. Consider, for instance, a situation of an air-launched missile. Missile primary power system typically utilizes a SPG scheme. When not terminated to missile chassis, the primary power return is typically DC-isolated from chassis, equipment conditioned power return, and signal returns by 1MΩ minimum. In the “pre-launch” mode, when attached to the host aircraft (i.e. during a “captive flight,” Figure 4.59a), the missile is powered from the aircraft DC power distribution network and grounded to the aircraft chassis,35 while in the “post-launch” mode (“free flight” Figure 4.59b), the missile is powered from its own power sources (e.g. batteries). However, this introduces a dilemma regarding the best approach for system grounding (Figure 4.60):

Z Z

Z

Z

Z Z Z

Signal/ logic SPG

Booster, right

Z Z Z

Z

Z

Z Z

Upper stage #1 segment

Electrical power SPG

Z

Z

Z Z

Z

Z

Signal/ logic SPG

Z

Signal/ logic SPG

Booster, left

Lower stage #2 segment Electrical power SPG

A second issue, often even of even greater significance, associated with systems such as missiles, launch vehicles, etc., is that the power return connection to the chassis (“grounded scheme”) permits a single unfused fault from the positive wire to chassis to occur. Such a fault could lead to termination of the mission. In fact, this has been the cause of several mission failures [12]. In such situations, it is strongly recommended that the power return be isolated from the chassis by some modest impedance (a technique known as “soft ground” or “ground fault isolation,” Figure 4.61), high enough to limit current in case of a fault but sufficiently low to provide a stable reference. Naturally, if the power system is isolated from the chassis, all items attached to the power bus must also be isolated from the chassis.36 It is noteworthy, however, that if “soft grounding” is implemented, higher common-mode noise could be present on the power bus, and power user loads should have greater common-mode noise immunity. An alternate approach would be to bypass the isolation impedance with a capacitor, which reduces common mode noise at the user interfaces and the magnitude of radiated emissions from the power system wiring (Figure 4.61). Such extra requirements are considered to be a tolerable side effect when balanced against the greater advantage of tolerance to high-side shorts to the chassis. Isolation of the power return from the chassis only needs to be a moderate resistance. For instance, isolation of 2 kΩ limits chassis currents to milliamps for a 28 VDC power system (28 V/2 kΩ = 14 mA, resulting in worst-case power loss of 0.39 W). This maintains the power return close to chassis potential but prevents loss of mission (Figure 4.62).

Lower stage #1 segment

Figure 4.58 Illustration of distributed singlepoint grounding application in a launch vehicle.

35 It is common practice, in aircraft, to use the chassis of the aircraft structure as path for DC and AC current return. Therefore, when powered from the aircraft, the missile DC power return is naturally grounded to the aircraft chassis [14]. 36 The Cassini spacecraft (an example of a large/complex spacecraft grounding implementation) uses a balanced floating ground system for primary (30 V) power. Both high (+) and return (−) wires are “soft grounded” chassis through 2 kΩ resistors.

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4 Fundamentals of Grounding Design

(a)

(b)

Figure 4.59 Air-launched missile in “captive” and “free” flight. (a) Rafael Python 3 air-to-air missile captive to IAF F-15D “Buzzard” “957” aircraft. Source: KGyST/Wikimedia/CC BY-SA 3.0. (b) F-15E “Thunder” fires AIM-7M missile. Source: U.S. Air Force/Wikimedia/public domain.

Aircraft chassis bonded to missile chassis via missile mounting hooks

Aircraft 28 VDC power source, grounded to chassis

Grou nd “capt loop in ive fli ght”

Missile battery, grounded to chassis

Missile umbilical connector

(a) Missile power distribution system

Power utilizing equipment load Isolated DC/DC converter

Missile primary DC power source (e.g. battery)

. . . Power utilizing equipment load A/C primary DC power source (e.g. battery)

Connection via Mounting Hooks

Ground loop between A/C and missile in “captive flight” (b)

Figure 4.60 Ground loop formed when missile is in captive flight (A/C = aircraft). (a) Physical representation. Source: David Monniaux / Wikipedia / CC BY-SA 4.0. (b) Schematic representation. Source: U.S Government. / Wikipedia/ / Public Domain.

4.2 Fundamental Grounding Schemes

Power utilizing equipment load

Missile power distribution system Isolated DC/DC converter Missile primary DC power source (e.g. battery)

. AC/DC “soft grounding”

. . Power utilizing equipment load

Figure 4.61

Implementation of “soft grounding” with a bypass capacitor in a missile power distribution network.

Figure 4.62 Advantages of “soft ground.” (a) Avoidance of ground loop with “soft ground” present. (b) Avoidance of mission failure due to single unfused fault from the positive power line to chassis.

Missile power distribution system

Power utilizing equipment load Isolated DC/DC converter

Missile primary DC power source (e.g. battery)

. . .

AC/DC “soft grounding”

Power utilizing equipment load A/C primary DC power source (e.g. battery)

Connection via mounting hooks

(a) “Hot” 28 VDC power line Missile power distribution system

Power utilizing equipment load Isolated DC/DC converter

Missile primary DC power source (e.g. battery)

AC/DC “soft grounding” Path of power fault current current limited by “soft ground” resistor

. . . Power utilizing equipment load

Power fault “Hot” 28 VDC power line shorted to chassis

(b)

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4 Fundamentals of Grounding Design

Electronic equipment units

Figure 4.63 “Tree grounding” scheme for electronic equipment in large facilities and platform.

Main trunk Branches GRP Signal reference structure

4.2.3.3 “Tree” Grounding

Another grounding scheme, more commonly found in large facilities and large-scale platforms (such as nonmetallic ships) is commonly known as “tree grounding” (Figure 4.63),37 owing to its tree-like representation, with a main trunk, limbs, and branches, eventually spreading out to the foliage, which, in practice, constitutes the electrical and electronic load equipment [1, 15]. One of the most salient factors requiring due consideration in the application of the “tree grounding” scheme is the need for heavy-gauge conductors for the “trunk,” with a possible gradual decrease in the cross section of conductors branching out from it. This is found on the misconception that resistance, not impedance, of the conductors is of primary importance. However, if one considers only resistance while failing to consider the inductive reactance of conductors, the high-frequency performance of this grounding scheme is severely compromised. Generally, there should be a strongly stated requirement for total electrical galvanic isolation of the “tree” from other collocated conductors in the installation or facility including piping, conduits, or any other metallic structures. Isolation precludes the development of “ground loops” that may be detrimental to the low-frequency performance of this grounding scheme. Maintaining this isolation, avoiding even accidental metallic contact, constitutes a tight constraint in the realization of such schemes. It follows, therefore, that “tree grounding” is no more than a more complex variant of the SPG scheme. Almost all drawbacks of SPG are also possessed by the “tree grounding” scheme. “Tree grounding” also lacks a safety grounding connection that may violate the overall grounding scheme if improperly treated. 4.2.3.4 “Nested” Grounding

Complexity of electronic systems and constraints that often apply in integration of their subsystems and subassemblies can be accommodated if their functional returns and protective earth connections are integrated into a grounding system hierarchy also known as “nested grounding.” “Nested” grounding constitutes a blend of composite hybrid grounding and “tree grounding” schemes as applied to smaller systems such as complex electronic assemblies, racks, cabinets, and consoles (these are discussed in particular in Section 4.8). In practice, this is the most common scheme in real-world electronic assemblies and systems and constitutes a combination of multiple and diverse grounding schemes. Very often, the grounding schemes of electronic assemblies are designed to form a SPG scheme at the assembly level. When zooming into the subassemblies and circuits, however, the grounding scheme applied in those must match the characteristics of their particular circuits. This is similar to “tree grounding” in the sense that, normally, it still has a system-level single common grounding point (CGP) but differs from it in the sense that it normally does not utilize a large and massive “main trunk.” Figure 4.64 illustrates a system consisting of several subassemblies, where different grounding schemes are used in each. In this case, a system-wide, single-point (“star”) grounding scheme is applied, while subassemblies and modules “nested” within the system comprise a variety of grounding schemes, according to their respective applications. Several practical examples of “nested” grounding schemes, as applied to equipment assemblies, equipment racks, and cabinets are presented later in this chapter. 37 “Tree grounding” as defined here should not be confused with the term “grounding tree,” to be discussed next.

4.3 Grounding Trees

Figure 4.64 Grounding system hierarchy or “nested grounding” scheme for electronic equipment in complex systems and assemblies.

Electronic subassemblies

Multi-point grounding locally Single-point “daisychain” grounding locally

GRP

Single-point “star” grounding locally

Signal reference structure

• • • • •

The Least You Need to Know In complex systems, simple, fundamental grounding schemes can rarely be used; common schemes for complex systems typically assume a form of “distributed SPG,” “tree,” or “nested” grounding schemes. Due consideration must be given to how the systems are powered, grounded, and interconnected, in order to ensure that grounding objectives are not compromised or violated. Maintaining a low-impedance signal reference and proper routing of signal conductors between circuits can overcome any problems that would otherwise result from this configuration. Using separate power sources in an attempt to overcome common-impedance coupling between circuits can further reduce the coupling; however, attention should be paid to the voltage build-up sequence and voltage difference between the power sources for preclusion of potential functionality concerns. “Soft grounding” precludes a single unfused fault from the positive (“hot”) power line to chassis to occur, which would otherwise result in mission termination. “Soft grounding” also limits DC loop currents when multiple connections to the reference structure may exist in the system.

4.3

Grounding Trees

4.3.1 Objectives and Basic Design Considerations The discussion and examples presented earlier demonstrate that a proper grounding topology is required for ensuring a design that does not compromise functionality, safety, or EMI concerns. A complex electronic system may consist of a large number of circuit types, each exhibiting different operational characteristics. Separate power and signal-return conductors are, therefore, assigned to each subsystem identifiable as a distinct load according to its noise and signal characteristics. Examples of such dissimilar load categories include:

•• •• •

Primary DC and AC power returns Low-level analog signal returns High-level signal returns (e.g. relay drives) High-speed digital signal returns High-frequency RF returns There are special cases in which additional dedicated return conductors may be required. Examples include:

a) Safety considerations of firing circuits of EIEDs, such as squibs and pyrotechnic devices. This dictates that special isolation measures be engaged for preclusion of chassis currents or pyro ground-fault currents during firing events, which could potentially cause magnetic field noise coupling into nearby sensitive circuits and, occasionally, even more severe outcomes [16]. b) Preserving red/black isolation (“TEMPEST”) between circuits processing “red” (clear, classified) and “black” (encrypted, unclassified) information, for control of compromising emanations [6].

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4 Fundamentals of Grounding Design

The grounding complexity38 of composite electronic systems is commonly acknowledged as a “grounding tree,” demonstrated symbolically in Figure 4.65. This figure portrays examples of a number of circuit types, the characteristics of which should be carefully addressed in the system grounding scheme design, as related to the specific RF circuits approach that should be applied for prevention of undesired coupling. Digital circuits It is likely that some (or all) of these subsystems will have to share a common reference point for ensuring system functionality. However, in order to avoid circulating currents between circuits, it is often required that no more than one such point exist in the system. The fixation that SPG must religiously be applied often leads to inappropriate grounding schemes, particularly when highfrequency circuits are involved. However, in composite systems that consist of both low-frequency and high-frequency circuits, some varSystem signal iant of system-level, SPG, at least as far as the low-frequency circuits reference structure are concerned, should be considered. Figure 4.65 Symbolic representation of the “grounding Consequently, the “grounding tree” constitutes a simple (yet effectree” concept. tive) method of ground scheme design by categories of circuits and signals. The “grounding tree” should depict different circuits and assemblies that constitute the systems and their respective grounding interconnections, particularly their common reference connection. Inasmuch as the principles portrayed here are commonly addressed at the facility, platform, or system level, relatively complex assemblies could also be considered as a system. The grounding scheme considerations discussed here could be applied to them just as well. Power (e.g. PWM drives) circuits

4.3.2

Analog (e.g. audio) circuits

Ground Tree Design Methodology

This section presents an example of a design procedure for a complex electronic assembly consisting of diverse circuits (e.g. analog, digital high-power, and sensitive RF circuits). The primary objective of this example is to present, in a step-by-step manner, particular considerations, conflicts, and compromises that exist, and the manner in which they can be addressed. In practice, the design of the “grounding tree” is carried out in two tiers, namely: 1) Inter-circuit “grounding tree,” in which the grounding of an integrated system as a whole is carried out, considering all circuits and subassemblies as “black boxes.” 2) Intra-circuit “grounding tree,” in which attention is paid to the internal grounding scheme of subassemblies or circuits. The following design example clearly demonstrates the two tiers of a grounding scheme design of a complex system.

4.3.2.1 Step 1: Identify System Architecture

Examine the system portrayed in Figure 4.66. The first constraint in the grounding system is the physical layout. We begin by identifying the subassemblies (e.g. PCBs). In this example, the system consists of six subassemblies, namely: a) A SMPS accomplishes the power conditioning tasks and conversion of the input AC power to multiple DC power outputs. The SMPS is implemented as a module packaged in a metallic enclosure. b) A Main Central Processing Unit (CPU) circuit serves as the system’s controller. This item consists primarily of digital circuits, but could also contain analog circuitry, principally audio. The CPU circuit is implemented as a separate PCB. c) The Input/Output (I/O) circuit serves as the external interface between the system and outside world. This circuit also serves as an interface to the transceiver module (Tx/Rx). The I/O circuit is implemented as a separate PCB. d) A Video Processor, processes video information and consists of high-speed digital circuits and analog video circuits (both low- and high-frequency analog). The video processor is implemented as a separate PCB. e) A Radio Transceiver (Tx/Rx) module provides high-power RF transmission and reception. Transmissions are pulsed, resulting in high current pulses during transmission. The Tx/Rx is implemented as a module packaged in a separate metallic enclosure. f) An Auxiliary Receiver (Aux Rx) module provides the capability of receiving a channel other than that to which the Tx/Rx was tuned. This is an extremely sensitive receiver utilizing an “active antenna” (i.e. an antenna containing an embedded lownoise amplifier, or LNA). DC power for operation of the LNA is superimposed on the RF signal fed into the coaxial transmission line. The Aux Rx is implemented as a module packaged in a dedicated metallic enclosure. 38 Further enhancing complexity of the grounding scheme is the need, particularly in facilities, to address not only the signal-return conductors, but also lightning protection system grounding, power earth connections, and so on. These aspects are discussed in Chapters 6 and 8.

4.3 Grounding Trees

4.3.2.2 Step 2: Define Chassis Connections at the Circuit/Module Level

Active antenna

When subassemblies are packaged in metallic enclosures, it is advisable to DC-ground everything. Floating metallic parts Aux. Rx within a system may increase radiated emissions39 and can Video potentially compromise the ESD immunity of the system, processor and when high voltages are concerned, these may also compromise electrical safety of the product. Grounding of internal metallic parts, such as subassembly Main CPU enclosures, could potentially impact the system grounding architecture and, therefore, should be taken into consideration at the earliest phases of the grounding system design as design constraints. I/O circuit Power supply In the example presented (Figure 4.67), metallic enclosures of modules (Power Supply, Tx/Rx, and Aux Rx) are bonded to Tx/Rx chassis, which also serves as the signal reference for the system. Figure 4.66 Step 1: Identify system architecture. Three other modules (Main CPU, I/O circuit, and video processor) are not packaged in a metallic enclosure; however, their construction includes a heat–sink, which, for heat transfer purposes, had to be connected to the metallic enclosure.

4.3.2.3

Step 3: Define Subassembly Signal Returns’ (Ground) Requirements

Based on the circuit/subassembly design, return conductors are allocated to each circuit (Figure 4.69). The notation appearing in Figure 4.68 should be interpreted as follows: Using this notation, for instance, the return conductor 5VD is interpreted as the return conductor for digital circuit powered from a 5 V power supply, while 15VA/RF can likewise be interpreted as the return of the analog RF circuit powered from a 15 V power supply.40 All return/reference conductors, required for the operation of the different circuits and subassemblies, are added into the diagram. Figure 4.67 Step 2: Define chassis connections at the circuit/module level.

Active antenna

Aux. Rx Video processor

Main CPU

I/O circuit

Power supply Tx/Rx

39 This situation is similar to that of grounding of heat-sinks discussed in Chapter 13. 40 As detailed in Chapter 13, with respect to grounding design on printed circuit boards, often a common ground plane also serves as a common return path for both analog and digital circuits. In that case, a common return path would be drawn rather than separate analog and digital returns.

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4 Fundamentals of Grounding Design

Figure 4.68 categories.

5 V D / RF

The circuit voltage/s to which the return conductor is allocated

Category of signal return: D = Digital A = Analog

5VD/RF

Notation for identification of return

Indication that the return conductor is associated with an RF circuit

Figure 4.69 Step 3: Define subassembly signal returns (ground) requirements.

Active antenna

15VA/RF 5VD Aux. Rx

15VA Video processor 5/3.3VD 15VA Main CPU 5VD 5VA

15VA/RF Power supply

I/O circuit 28VA/RF Tx/Rx

4.3.2.4 Step 4: Identify Chassis Isolation/Connection Requirements in Subassemblies

In Figure 4.69, all return conductors are depicted without indicating their connection point to chassis or SRS. However, it is well known that RF circuits, as well as high-speed digital commonly utilize MPG to chassis41 at the circuit level. The chassis connection, implemented locally at the subassembly level using the MPG scheme, is shown in Figure 4.70. The analog return conductors are not connected to the chassis at the PCB level. This is also applied to the video return, which contains both lowand high-frequency signals. For these types of circuits, “frequency selective” grounding, by means of small capacitors (typically in the 1–10 nF range) could be implemented, providing high-frequency MPG and low-frequency SPG. In this (real-world) example, this was not required nor applied. As discussed in the following paragraphs, due consideration of the subassembly grounding topology will be given in the decision regarding the system-level grounding scheme. 4.3.2.5 Step 5: Define Common Grounding Point (CGP) Location

For signals that communicate between separate parts of the system, the grounding scheme must provide a common reference with minimum ground shift (low common-mode noise). Once the manner of grounding connection is defined for each of the return conductors, a system-level CGP is defined. In Figure 4.71, the notation of different options for allocating the CGP, which serves as the system-level single-point ground, is now shown:

•• •

Option (a): Near the power supply Option (b): Within the power supply Option (c): Near most sensitive subassembly

41 Note that in the figures and illustrations in this section, only a single chassis connection is shown for RF and high-speed digital circuits, for the purpose of clarity of the images; however, in practice, multipoint grounding is implemented. For that purpose, the “MPG ” notation is added, when applicable, to Figure 4.70.

4.3 Grounding Trees

Figure 4.70 Step 4: Identify chassis isolation/connection requirements in subassemblies.

5VD/RF

Active antenna

15VA/RF

MPG 5VD

Aux. Rx 15VA

Optional “frequency-selective” grounding

Video processor 5/3.3VD MPG 15VA Main CPU 5VD 5VA

15VA/RF Power supply

I/O circuit 28VA/RF

MPG

Tx/Rx

Figure 4.71 Step 5: Define system-level common grounding point (CGP).

5VD/RF

Active antenna

15VA/RF 5VD Aux. Rx

CGP (c) 15VA Video processor

CGP (b)

5/3.3VD

CGP (a)

15VA Main CPU 5VD 5VA 15VA/RF Power supply

I/O circuit 28VA/RF Tx/Rx

There may be cases where MPG throughout the system is a better choice, particularly if the system comprises many highfrequency/high-speed circuits. However, when mixed high- and low-frequency systems are concerned, a hybrid grounding scheme is often applied, mandating that a CGP be determined and used. There may be cases where other system-level schemes may be used, such as “series” SPG scheme. The CGP provides the common connection between all return conductors across the circuit or system. The position of the CGP is determined based on several decisive factors, for instance: Electrical length of the grounding conductors a) System layout b) Sensitivity of system components c) Safety grounding requirements

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4 Fundamentals of Grounding Design

•• •

Three principal positions are normally considered for the CGP, namely: Near the power supply Within the power supply Near most sensitive subassembly The following is a discussion of the abovementioned options, depicted accordingly in Figure 4.71.

a) Near the Power Supply. The most common position for the CGP is as close as possible to or even within (see (b) below) the Power Supply. Normally, all power leads branch out from the output of the power supply and the return conductors would normally be connected to the respective return terminals. Therefore, locating the CGP as close as possible to the power supply actually guarantees short conductors, which are of great importance, when considering the application of SPG. b) Within the Power Supply. If confidence is gained regarding the optimal location of the CGP in the vicinity of the Power Supply, and particularly if the power supply is a custom-made multi-output assembly packaged in a metallic enclosure, the position of the CGP within the power supply is an even better choice, as the enclosure of the power supply can be easily bonded to the metallic chassis of the host enclosure, if present. This again will ensure minimum grounding impedance for low- and high-frequency circuits. Common to both above alternatives (a) and (b) is a situation of particular importance where the equipment is not packaged in a metallic enclosure; hence, grounding of the system can be attained only via the ESGC (or “green wire”). In this case, placing the CGP within the power supply minimizes the length of the ground conductors to the system “safety ground” connection. c) Near Most Sensitive Subassembly. Recalling that when applying the series SPG scheme, the actual system connection to the signal reference, serving as the CGP, is normally made as close as possible to the most sensitive subassembly owing to the fact that the lowest EMI voltages will develop on this short connection. It follows that another alternative for locating the CGP is near the most sensitive subassembly or circuit in the system. In this particular example, the receiver appears to be that most sensitive component, and hence the CGP in option (c) is placed in the point nearest to that assembly, and actually shares this chassis connection. In this specific (real-world) system, the CGP is placed within the power supply (and is marked as such), option (b).42 From here, only reference to alternative (b) will be made. 4.3.2.6 Step 6: Determine Return Conductors Connections from the Circuits to the CGP

Once the location of the CGP is determined, all that remains is to connect the different return conductors to the CGP. As observed in Figure 4.72, the return conductors from most subassemblies are indeed connected to that point. If the subassemblies consist of PCBs and modules inserted into a motherboard or backplane, those interconnects would normally be implemented in the form of wide planes.43 If such a connection is not available, this scheme may suffer from unacceptably high ground path impedance at higher frequencies, which may cause a functionality concern. When a motherboard is not present, or if different system components actually comprise equipment assemblies themselves, such connection is often accomplished using a grounding conductor. In this case, care must be taken to ensure that the impedance of the grounding conductors be as low as reasonably achievable. In Figure 4.72, the CGP serves as the reference point for the return terminals of the power modules, demonstrating that it truly serves as the system common reference point. Note that Figure 4.72 depicts only the return conductors of the power system; the “hot” power leads are omitted from the drawing for clarity. Noticeably, several return conductors are not connected to the CGP (as pointed out by the question mark “?”). Why is that? The answer lies in Step 7. 4.3.2.7 Step 7: Identify Potential Ground Loops

The common denominator between these two cases is that both are RF circuits, internally (multipoint) grounded within their metallic enclosure, which, in turn, is bonded to the assembly’s chassis. That, by its own virtue, does not justify the preclusion of their connection to the CGP. Obviously, if they were to be connected to the CGP, that would in practice, be accomplished using an electrically long conductor, considering the very high frequency content used by these modules. Furthermore, by making that connection, these circuits would be grounded in two different locations in the system forming ground loops. As depicted in Figure 4.73, the resultant ground loop could potentially bring about circulating interference current between the circuits. 42 In an earlier prototype, option (c) was actually applied due to system constraints emerging from the use of nondevelopment items (NDIs). However, when moving on to full-scale development, modifications were made to enable the improvement of the grounding scheme resulting in the application of option (b). 43 The exact manner of accomplishing such a connection in practice is discussed in Chapter 13.

4.3 Grounding Trees

Figure 4.72 Step 6: Determine return conductor connections from the circuits to the CGP.

? 5/3.3VD

DC DC

15VA

DC DC

5VA

DC DC

?

5VD/RF

Active antenna

15VA/RF 5VD Aux. Rx 15VA Video processor 5/3.3VD

CGP

15VA Main CPU 5VD 5VA ? Power supply

?

15VA/RF I/O circuit 28VA/RF Tx/Rx

Figure 4.73 Step 7: Identify potential ground loops resulting from multiple chassis connections.

? 5/3.3VD

DC

15VA

DC

5VA

DC

?

5VD/RF

DC DC

DC/DC converter module

Active antenna

15VA/RF

DC

5VD Aux. Rx

DC

15VA

DC

Video processor 5/3.3VD

CGP

15VA Main CPU Potential ground loop

5VD 5VA

? Power supply

?

15VA/RF I/O circuit 28VA/RF DC

Tx/Rx

DC

DC/DC converter module

Generally, RF circuits, such as the Tx/Rx and the Aux Rx, are multipoint grounded, thus, such a connection would not affect them. However, in the particular case addressed in this example, the Tx output (peak pulsed) power was +50 dBm (100 W), while the Aux Receiver had a sensitivity better than −120 dBm. Isolation greater than 170 dB44 is desired in order to preclude unacceptable coupling between the circuits. It was feared that in this case, even though the high-frequency return current would mostly follow the power leads (path of least inductance), a small proportion of the return current may still circulate in the system and couple via the CGP to the chassis and the sensitive receivers causing a functionality concern.

44 It is true that the Tx/Rx and the Aux Rx operated at different frequency bands, S-band and L-band, respectively. However, even if we assume a transmitter spurious suppression of −80 dBc, an isolation of 90 dB would still be required, which would still pose a major challenge.

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4 Fundamentals of Grounding Design

5VD/RF

DC

5VD/RF

DC

15VA/RF

DC DC

5/3.3VD

DC DC

15VA

DC DC

Active antenna

15VA/RF 5VD Aux. Rx 15VA

5VA DCDC

Video processor

5/3.3VD

CGP

15VA Main CPU 15VA/RF

DC DC

28VA/RF

DC DC

5VD 5VA 15VA/RF

Power supply

I/O circuit 28VA/RF DC DC

Tx/Rx

Figure 4.74

DC/DC converter module

Dedicated DC/DC power modules are required for the RF circuits, for preclusion of ground loops.

It follows, therefore, that the Tx/Rx and the Aux Rx cannot be connected to the CGP and must be left to “float” at their input. That results in the need to allocate dedicated and isolated DC/DC power conversion modules for this purpose (Figure 4.74). Observe that the outputs, which have provided dedicated terminals, are also attributed with a special designation (“/RF”). It is important that the DC/DC power modules exhibit DC isolation from input to output as well as mutually. That is easily accomplished when the DC/DC modules are implemented as “switch mode power modules.”45 Inasmuch as they do not provide absolute isolation at RF, due to parasitics, good ground loop control can be achieved by adequate filtering to support lower frequency isolation. Actually, another outcome of the grounding architecture design process discussed is the high-level characterization of the system power supply. 4.3.2.8 Step 8: Consider “Special Cases” Potentially Leading to Violation of the Grounding Scheme

In some cases, system-specific isolation requirements may require particular attention. In our ongoing example, the I/O circuit is required to control the Tx/Rx module, while the Main CPU controls the Aux Rx. If single-ended signaling is used for this purpose (the dashed lines in Figure 4.75), resulting ground loops are unmistakably apparent. Furthermore, any system isolation requirement precludes any galvanic connection between the external circuits (i.e. circuits external to the system which interface with the I/O module) and internal circuits. This requirement would be violated by the manner in which the I/O circuit is connected to the Tx/Rx module. A similar concern lies in the connection between the Main CPU and the Aux Rx, due to the potential ground loop, particularly in light of the very high sensitivity of the Aux Rx. 4.3.2.9 Step 9: Incorporate “Isolation Measures” for Preclusion of Undesired Ground Loops

In an attempt to overcome the situation identified in Step 8, measures for “breaking” the ground loops are to be incorporated. Such measures, discussed herein, include, for instance, isolation transformers, optical isolators/optocouplers, balanced drivers, etc. In Figure 4.76, observe the Tx/Rx module and its connection to the I/O circuit while recalling that only return conductors are presented. Signaling between the I/O circuit and the Tx/Rx module is carried out through optocouplers, which facilitates the transmission of an electrical signal in the form of an optical (light) signal, therefore, eliminating the need for any common galvanic reference between the circuits. In the case of the link between the Main CPU and the Aux Rx (Figure 4.76), a differential, balanced and isolated high-speed RS-422 digital interface is used,46 exhibiting high common-mode rejection and thus, high immunity to ground loops. Other approaches and techniques may be applied in other cases, as further elaborated in Section 4.5. 45 The role of switch-mode power supplies in grounding system design is discussed below. 46 In this particular case, optocouplers could not be used due to the high speed of the serial digital signal, which exceeded the useful bandwidth of the optocouplers.

4.3 Grounding Trees

Figure 4.75 Step 8: “Special cases” potentially leading to violations of the grounding scheme.

5VD/RF

DC DC

15VA/RF

DC DC

5/3.3VD

DC DC

15VA

DC DC

5VA

DC DC

5VD/RF

Active antenna

15VA/RF 5VD Aux. Rx 15VA Video processor 5/3.3VD

CGP

15VA Main CPU 15VA/RF

DC DC

28VA/RF

DC DC

5VD 5VA 15VA/RF I/O circuit

Power supply

28VA/RF DC

Tx/Rx

Figure 4.76 Step 9: Incorporate “isolation measures” to preclude undesired ground loops.

5VD/RF

DC DC

15VA/RF

DC DC

5/3.3VD

DC DC

15VA

DC DC

5VA

DC DC

RS-422 receiver

5VD/RF

DC

DC/DC converter module

Active antenna

15VA/RF 5VD Aux. Rx RS-422 driver

15VA Video processor 5/3.3VD

CGP

15V A Main CPU 15VA/RF

DC DC

28VA/RF

DC DC

5VD 5VA 15VA/RF

Power supply

I/O circuit

28VA/RF DC

Tx/Rx

4.3.2.10

Step 10: Sketch the “Grounding Tree”

DC

DC/DC converter module

Once all previous steps have been completed, sketch the system “grounding tree.” This is normally performed by identifying the ground/return conductor connections beyond the CGP, located (in this case) within the power supply which by design, consists of isolated outputs. Applying this to our example, Figure 4.76 can be transformed into the schematic of Figure 4.77. It is now easy to view all ground connections, and identify potential ground loops or other abnormal ground connections. Even if loops were not identified in the previous steps, they will certainly be noticed in this schematic diagram, allowing timely implementation of corrective actions.

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4 Fundamentals of Grounding Design

Main CPU RS-422 Link

3.3V/5VD 15VA

Figure 4.77 Step 10: Sketch the “grounding tree.”

Video processor

15VA 5VD

5VD LOOP???

5VA

I/O circuit 5VD

5VD/RF

Aux. Rx 15VA/RF

LOOP???

222

15VA/RF

Tx/Rx

28VA/RF

Enclosure chassis CGP (within power supply)

The resultant grounding scheme illustrated in Figure 4.77 clearly does not form a classic SPG topology. This grounding scheme is better known as “distributed single point grounding,” comprising of a system of multiple, isolated system ground points common to an isolated set of circuits or equipment (i.e. single-point ground), referenced to a common, large, conductive structure, e.g. equipment equipotential structure.

4.3.2.11 Step 11: Consider Intra-Circuit Grounding Scheme

Now examine the Tx/Rx module. Up to this moment, all circuits in this module are depicted such that they are directly connected to the chassis, using a MPG topology. In practice, however, it turned out that the digital circuits return could not be connected directly to chassis simultaneously with the analog circuits return, due to internal circuit constraints. Therefore, we have two alternatives for accomplishing module-level ground connection (Figure 4.78), where a partial schematic of the Tx/Rx grounding scheme is depicted. Due to a limitation in the pin-out of the Tx/Rx module, it is not possible to provide both digital and analog power and return conductors. Only one return conductor could be connected, either digital or analog. Which would it be? Figure 4.78a depicts the first option, actually the one used up to now. In this case, the analog return conductor (AGND) is connected to the chassis of Tx/Rx directly (using the lowest impedance connection possible) whereas the digital return conductor (DGND) is also referenced to the chassis of the Tx/Rx via the AGND. The AGND chassis connection now forms a common impedance link (common-Z) between both the AGND plane and chassis. The risk in this configuration is, of course, that any digital noise developed across the common impedance of the chassis connection will also appear across the analog circuit

Digital ckts.

Analog ckts. AGND

DGND Analog ckts.

Digital ckts.

AGND Common-Z of chassis connection

DGND Common-Z of chassis connection Tx/Rx

Tx/Rx (a)

(b)

Figure 4.78 Step 11: The Tx/Rx grounding dilemma. (a) Digital return referenced to analog return (acceptable). (b) Analog return referenced to digital return (objectionable).

4.4 Role of Isolated Switch-Mode Power Supplies in Grounding System Design

as “ground-coupled interference” and may disrupt the analog circuit performance. However, if the impedance (inductance, in particular) of this common conductor is kept to an absolute minimum, the outcome of such coupling will be minimized. If, on the other hand, the connection portrayed in Figure 4.78b is used, the analog circuits will “ride” over the noisy digital ground plane and chassis connection. Even if the chassis connection is low impedance, a high probability exists for interference coupling due to the very noisy common impedance of the digital return.47 In conclusion, it follows that in such cases where a dilemma exists as to the interconnection between the analog and digital return conductors, the return conductor of the sensitive circuits (e.g. AGND) should always be the one directly connected to the signal reference. The interconnection between AGND and DGND within the Tx/Rx module (intra-circuit architecture) should be included accordingly in the inter-circuit grounding scheme. 4.3.2.12

Step 12: Define the Power Supply Outputs’ Specification

The definition of the power supply’s outputs’ specification is directly derived from the grounding constraints of the system. In our example, it follows that the power supply will have to provide the following isolated converter outputs:

•• • ••

However, Tx/Rx requires:

••

A 5 V isolated output for the Aux Rx digital circuits. A 5 V isolated output for the Aux Rx analog circuits.

A 3.3 V/5 V isolated output with a common digital return for all digital circuits. A 5 V isolated output for the I/O circuit. A ±15 V isolated output with a common analog return for analog circuits.

A ±15 V isolated output with a common analog return for analog RF circuits. A 28 V isolated output for analog RF (pulsed) circuits. Finally, Aux Rx requires two more dedicated converter outputs:

In summary, an optimal power distribution system (PDS) scheme would be derived from use of a “grounding tree” and results in a 7-output SMPS.

• • • •

The Least You Need to Know In any system design, care must be taken to ensure that undesired high-level signals do not conductively couple into sensitive signal circuits sharing the same reference plane, for preclusion of intolerable interference to susceptible circuits. Constructing the grounding architecture of a complex system must be performed in a systematic manner, considering system layout, circuit requirements, and special concerns in the system (e.g. isolation). The “grounding tree” should be expanded to include intra-circuit interactions in addition to the inter-circuit interactions depicted earlier. Such an extension may reveal yet other interactions not identified at this discussion level. You do not need to be “Wonder Woman” or “Super Man” to design your “grounding tree.” Good system awareness, experience, and common-sense are helpful implements to complete this task successfully.

4.4

Role of Isolated Switch-Mode Power Supplies in Grounding System Design

The grounding tree design example in the previous section clearly demonstrated that isolated power supplies play an important role in the design of overall system grounding scheme. In particular, it was shown that the power supply architecture may be directly derived from the system grounding scheme. This section will now discuss in brief the unique features of SMPSs, particularly those associated with grounding.48 SMPSs have been used for many years in industrial, telecommunications, and defense applications in which high efficiency, light weight, and small size are of prime concern. Today, SMPSs are used extensively in almost all DC- or AC-powered electronic devices. A SMPS offers four main advantages over a conventional linear power supply: a) High efficiency (60–95%) compared to that of linear power supplies (40–50%), hence, less heat dissipation. b) Tighter and continuous regulation while producing a wide range of output voltages (often higher than the input voltage). c) Smaller size and lower weight thanks to its higher frequency of operation. 47 Observe that this constitutes a special case of “series” single-point grounding. 48 It is not the intention of this section to dwell on the actual topologies of switch-mode power supplies. Many excellent books have been written on this topic. The reader is encouraged to refer to literature for a more detailed discussion of power supply design.

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4 Fundamentals of Grounding Design

d) Possible input-to-output and output-to-output (in multiple-output SMPSs) isolation thanks to the incorporation of switching transformers in many power supply topologies. The main drawback of SMPSs is that of increased EMI, both common-mode and differential-mode emissions, due to the switching function fundamental to their performance.

4.4.1

Principle of Switch-Mode Power Supply Operation

A linear power supply uses a linear regulator to provide the desired output voltage by dissipating excess power in ohmic losses (e.g. in a resistor or in the source–drain region of a pass FET in its active mode). A linear regulator regulates either output voltage or current by dissipating the excess electric power in the form of heat, and hence its maximum power efficiency is voltage-out/voltage-in since the volt difference is wasted. In contrast, SMPS varied its output voltage and current by switching ideally lossless storage elements, such as inductors and capacitors, between different electrical configurations. Ideal switching elements (approximated by transistors operated outside of their active mode) have negligible (in the order of mΩs) resistance when “on” (RDS) (Figure 4.79) and carry no current when “off,” and so converters with ideal components would operate with close to 100% efficiency.49 The basic operation of a SMPS can easily be understood for the Buck topology (Figure 4.80). In the Buck converter, the current through an inductor is controlled by two switches (usually a transistor and a diode). Commencing with the switch open (“off-state”), no current flows into the circuit. When the switch is first closed (“on-state”), the current increases, and opposing voltage builds across its terminals the inductor in response to the changing current, counteracting the source voltage, hence reducing the net voltage across the load. As the rate of change of current decreases, the voltage across the inductor diminishes, increasing the voltage across the load. During this time, energy is stored in the inductor in the form of a magnetic field. When the switch is opened again (“off-state”), the voltage source is disconnected from the circuit, and the current through the circuit will decrease, producing a voltage drop across the inductor (opposite to the drop at the “on-state”), and the inductor becomes a current source, whereby the energy stored in its magnetic field supports the current flow through the load. This current, when appended to the current flowing during on-state, results in current greater than the average input current, ideally preserving the power delivered to the load (Figure 4.81). A generalized scheme of a SMPS is depicted in Figure 4.82. The main roles of the various stages are briefly explained. a) The input rectifier stage (included when the SMPS is supplied from an AC power source) rectifies the AC waveform and produces an unregulated DC voltage which is then sent to a large filter capacitor. The current drawn from the mains supply by this rectifier circuit occurs in short pulses around the AC voltage waveform peaks, producing high-level harmonics of the power frequency, emitted as EMI to the power source. Figure 4.79 The RDSon of the MOSFETs increase with voltage rating. Source: Power MOFSET/ Wikipedia/ Public Domain.

10.0

Specific resistance (Ω/cm2)

224

1.0

100.0 m

10.0 m

1.0 m Ideal MOSFET Commercially available MOSFETs (estimated specific resistance)

100.0 u 10 v

100 v Breakdown voltage (V)

49 Practical efficiencies in the range 90–98% are achievable at full-load.

1 kv

4.4 Role of Isolated Switch-Mode Power Supplies in Grounding System Design

On-state

Off-state

VL

IL S

L D

Vi

VD

(a)

R

C

Vo

(b)

Figure 4.81 Temporal voltage and current waveforms in an ideal Buck converter operating in continuous mode (refers to Figure 4.80). Source: Efadae/Wikimedia/Public Domain.

Switch state

Figure 4.80 Principle of operation of the Buck converter. (a) Circuit configurations of a Buck converter. (i) Upper: “on-state” switch is closed. (ii) Lower: “off-state” switch is open. (b) Naming conventions of components, voltages, and current of the Buck converter. Source: CyrilB/Wikipedia/Public Domain.

0

TOn

TOff

On

Off

On

Current

Voltage

Vi

VD

0

VO t

–Vo

VL

Vo

Imax Iav

IL

Imin

t

0

Mains input

Input rectifier and filter

Inverter “chopper”

Output transformer

Output rectifier and filter

D.T

T

DC output

Chopper controller

Figure 4.82

t

Block diagram of a mains-operated (“off-line”) AC/DC SMPS. Source: Dcirovic/Wikipedia/Public Domain.

225

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4 Fundamentals of Grounding Design

b) The inverter stage (or “chopper” in Figure 4.82) converts the DC, whether directly from the input or from the rectifier stage described earlier, to pulsed waveforms by running it through a power switch, typically a power-MOSFET. Switching frequencies in contemporary SMPSs are in the range of 250 kHz up to 3 MHz, approximately.50 c) The voltage converter and output rectifier. If the output is required to be isolated from the input, as is usually the case (unlike the Buck converter which provides no such isolation), the switched waveform from the FET drives the primary winding of a high-frequency pulse transformer. This converts the voltage up (“step-up”) or down (“step-down”) to the required output level on its secondary winding. The output transformer in Figure 4.82 serves this purpose. The rectifier element, essentially a diode (Schottky or silicon, depending on voltage) converts the switched waveform to a quasi-DC waveform (with ripple superimposed on the DC). This quasi-DC output is then smoothed by a filter consisting of inductors and capacitors, appropriate for the switching frequency.51 d) Regulation is achieved by means of a feedback control loop in order to regulate the output voltage by varying the duty cycle to compensate for variations in input voltage. A feedback circuit monitors the output voltage and compares it with a reference voltage. Depending on design and safety requirements, the controller may contain an isolation mechanism (such as an optocoupler) to isolate it from the DC output. Varying the momentary switching frequency (i.e. pulse-rate modulated52 or PRM regulator) or duration (i.e. pulse-width modulated53 or PWM regulator), the switch remains closed per unit of time, resulting in duty cycle variation of the unregulated input voltage and a corresponding regulation of the level of the output voltage(s) (Figure 4.83). The output current flow (into the load) depends, therefore, on the input power signal, the storage elements and circuit topologies used, and also on the pattern used (e.g. PWM with an adjustable duty cycle) to drive the switching elements. The spectral density of these switching waveforms has energy concentrated at relatively high frequencies, requiring effective input EMI filtering to comply with EMC standards and regulations and output filtering to achieve the necessary reduction in ripple to guarantee acceptable functionality. One of the more common configurations for providing galvanic isolation in the power supply circuit is the “Flyback” converter54 (Figure 4.84). The “Flyback” converter is used in both AC/DC and DC/DC conversion with galvanic isolation between the input and outputs and incorporates a transformer between the input and the output stages. In addition to providing the galvanic isolation, the transformer enables “step up” or “step down” of the input voltage across the load thanks to the or primary to secondary turns’ ratio of the transformer. The switching transistor (similar to the Buck converter, this is typically a power MOSFET) and pulse transformer form the heart of all isolated SMPSs. Unregulated power is supplied to the switching transistor through the primary winding of the transformer. The switching transistor acts as a switch. When the switch is closed (“on state”), a path is provided for current to flow through the primary winding of the pulse transformer to the power return lead, producing an expanding magnetic field that couples and stores energy in the magnetizing inductance of the secondary winding of the transformer through the core. The voltage induced in the secondary winding of the transformer is negative, so the diode is reverse-biased. The output capacitor supplies energy to the output load. When the switching transistor is opened (“off state”), the transistor is in cutoff and does not conduct and the primary current and magnetic flux collapse. The voltage in the secondary winding of the transformer is positive, forward-biasing the diode, allowing current to flow from the transformer. The energy from the transformer recharges the capacitor and supplies the load. Consequently, current does not flow simultaneously in the primary and secondary windings of the transformer in this topology. The operation of storing energy in the transformer before transferring to the output of the converter allows the topology to easily generate multiple outputs with little additional circuitry, although the output voltages have to be able to match each other through the turns’ ratio. The isolated Flyback converter requires that the feedback from the voltage or current sensing circuit at the output, necessary for obtaining tight voltage or current regulation at the converter output, must not violate the isolation.

50 Previous generation SMPSs used switching frequencies of 20 kHz and above. The increase of switching frequencies in contemporary SMPS is beneficial, mainly thanks to reduction in dimensions of the EMI filters, required for suppression higher frequency spectral components. Higher frequency switching was made possible thanks to evolution of switching MOSFETS technology, on the one hand and the increased efficiency of transformers at higher frequencies. 51 In the Buck converter, the input voltage is reduced in direct proportion to the duty cycle of the switching operation. “Step-up” is not possible in a Buck converter. 52 PWM regulators vary the duration in which the switching transistor is “on” (in conduction). The switching frequency is constant but the duty cycle varies. As the duration of the “on” pulse is increased, the switching transistor conducts for a longer duration and more energy is delivered to the transformer per unit of time, increasing the output DC voltage and vice versa. 53 PRM regulators vary the rate (frequency) at which the switching transistor is turned “off” and “on,” but pulse width remains unchanged. As the pulse rate increases, the “on time” decreases, again changing the duty cycle. As the rate of the “on” pulses is increased, more energy is delivered to the transformer per unit of time, increasing the output DC voltage and vice versa. 54 The Flyback converter is a Buck-Boost converter with the inductor split to form a transformer.

4.4 Role of Isolated Switch-Mode Power Supplies in Grounding System Design

DC output

DC input

Higher duty cycle Constant frequency/cycle time

DC input DC output Lower duty cycle

Variable pulse width and duty cycle (a)

DC output

DC input

Variable frequency and duty cycle

Higher duty cycle

DC input DC output Lower duty cycle Constant pulse width (b) Figure 4.83

The PWM and PRM regulation. (a) Pulse width modulation (PWM). (b) Pulse rate modulation (PRM).

An isolation device (e.g. optical isolator or optocoupler) is required to maintain isolation between the “cold ground” (secondary side of the pulse transformer) and the “hot ground” (primary side), while coupling the DC feedback voltage. Signals or power delivered from one ground reference to another are often referred to as “crossing the isolation boundary” (Figure 4.85). Grounding and isolation in SMPSs are now discussed.

VD ID L D V1

V2

Vi

C

R

Vo

IS S

Vs

4.4.2 The Need for Isolation in Switch-Mode Power Supplies SMPSs are often categorized into two basic types with respect to Figure 4.84 Principle of operation of the Flyback converter. their grounding schemes: isolated and non-isolated. In short, an iso- Source: CyrilB/Wikipedia/Public Domain. lated power supply isolates the input from the output by electrically and physically separating the circuit into two sections, preventing direct current flow between input and output. A SMPS that generates a low-voltage isolated output from a primary (mains) source is often referred to as an “offline SMPS.” In isolated power supplies, input and output circuits of the power supply are electrically isolated from each other, typically achieved by using a

227

228

4 Fundamentals of Grounding Design Unregulated input power supply

Step-up/down Rectifier pulse transformer (“flyback”)

Regulated DC output to load

Figure 4.85 Basic configuration of a single output “Flyback” off-line switch mode power supply.

Rectifier bridge (in AC/DC supplies)

Switching transistor Optical isolator

“Hot ground”

PWM/PRM switching control

“Cold ground”

Feedback to switch control Aux controls (on/off, power fail, etc.)

transformer, precluding electrically continuous current or current-return paths from existing between them. A non-isolated power supply has a single circuit in which current can flow between input and output.55 Galvanic isolation (usually simplified to just “isolation”) is thus the physical and electrical separation between one section of a circuit and another. A result of isolation is that each of the isolated circuits has its own return or ground reference. Although current is not permitted to flow between input and output in isolated power supplies, power and signals must still be transferred from one side to the other. This goal may be accomplished in several manners, but isolated power supplies generally rely on two; power is coupled in the form of electromagnetic (particularly magnetic) fields by means of transformers or coupled inductors and signals cross the isolation gap using signal transformers or optically by means of optical-isolators. When designing a power supply, complying with safety standards is essential to protect operators and other personnel from electric shock and hazardous voltages.56 Isolation is an important method to meet safety standards. For power supplies operating from high, potentially hazardous voltages (such as off-line AC/DC converters powered from AC mains), isolation provide a clear barrier across which dangerous voltages will not pass. No direct conductive path exists between the source of input power to the power supply and its output terminals or load. When safety is of concern, the insulation grade must also be considered. Safety standards should be reviewed to determine what level of insulation is required for a given application. The insulation grade is divided into several categories including functional, basic, supplementary, and reinforced, to be discussed in detail. Additional (very important) advantages to isolation are: a) Ground Loop Prevention: Since the input and output of isolated power supplies do not share a common return path, common-mode interference rejection is enhanced and potentially harmful ground loops are prevented. When ground loops occur, there is high likelihood that the signal voltage developed by current from one of the circuits on the return path will disrupt the operation of the other circuit. Circuits that are sensitive to noise can benefit from this isolation by having their ground broken up and separated from noisy circuits that could cause problems. b) Interference Elimination: Isolation means the net DC and AC extraneous or interference current is substantially reduced in the isolated interface. Isolated products restrict the ground current (return path) of an electrical circuit to only one side of the barrier, enabling a noise-free environment for sensitive measurements on the other side. The isolation protects the equipment from the linelevel events such as common mode57 surges, etc. The remainder of this section focuses on this point. c) Floating Outputs and Level Shifting: Isolated power supplies provide isolated, floating output. While having a fixed voltage between output terminals, isolated outputs do not have a defined or fixed voltage relative to voltage nodes (or the reference structure) in circuits from which they have been isolated, and are said to be floating. However, a floating output may have one of its terminals connected to another circuit node to fix it to that voltage. This fact can be used to shift or invert the

55 This is not to say that non-isolated power supplies have no benefit whatsoever. While there are many benefits to isolation, there are also reasons to use a non-isolated converter including cost, size, and performance, efficiency in particular. Those should be balanced with the benefits of isolation, and particularly ensuring that safety is not compromised. 56 Hazardous voltages are voltage greater than 30 VRMS, 42.4 VPeak, or 60 VDC. 57 Isolation will only support protection against common-mode interference and surges. Differential-mode interference will, in most cases, couple through the barrier, by virtue of the transformer’s nature.

4.4 Role of Isolated Switch-Mode Power Supplies in Grounding System Design

output relative to another point in a circuit. Isolated power supplies can be used, for instance, to produce negative output voltages from positive voltage sources, for example, −5 V from +5 V. d) Obtaining Multiple, Isolated Outputs: The isolating characteristics of a transformer allow the design of power supplies with multiple outputs by adding windings to the transformer along with rectifier and filter components. A common example of this type of power supply is the desktop computer supply with +12, +5, and +3.3 V outputs. Power supplies with floating outputs may also be connected in series to increase the output voltage or create +/− rails. Care should be taken, however, to ensure that the outputs are truly floating. For instance, if the output ground terminals of two isolated converters were to be connected to chassis, they may no longer be considered floating relative to one another, and if the outputs were connected in series, this would create a short across one of the power supplies as both terminals would be connected to chassis. In AC/DC power supplies, the output ground terminal is sometimes connected to earth, which means that it is no longer floating, although isolation is not compromised. If signal, control, or power returns are not isolated at an assembly’s interface, ground currents in the reference structure (chassis) may exist. Figure 4.86 illustrates both isolation of grounds between two subsystems and also lack of isolation (permitting a ground loop to exist). Return current can flow both in the return wire as well as through the chassis ground connections. When isolation is to be maintained, some form of AC coupling, power transformers in particular (in power supply systems), must be used to transmit AC power; no DC path exists between the interconnected assemblies. Note that isolation really means limiting of the flow of current. For instance, a typically recommended isolation impedance of 1 MΩ to chassis in a 28 VDC power system implies that DC current lower than 28 μA to chassis is permitted. A particularly challenging situation may occur when several assemblies, which are powered from a single primary power source and share a common reference (and primary power return path) interface with other assemblies, when no isolation exists in the input power supply of the assemblies.58 This situation is illustrated in Figure 4.87. In Figure 4.87a, the electronic assemblies are powered by an isolated DC/DC SMPS. Although single-ended signaling is used in the circuits, the only available signal return path is through the controlled secondary power59 return circuits; no path exists for the signal return current through the primary power60 return circuits thanks to the isolation of the DC/DC SMPS (as long as the layout of the assemblies is such that there is no physical common path between the assemblies that overlaps the primary power return. In a non-isolated power supply, the input and output share a common ground and current can flow between them. However, in an isolated converter, the input and output return to their own independent paths and there is no path for direct current from one to the other. In Figure 4.87b, the electronic assemblies are powered by a non-isolated power source, whether via a non-isolated DC/DC SMPS or through direct power feed to the assembly. The primary and secondary power return circuits are now directly connected at multiple locations (producing potential “ground loops”). The single-ended signal current may now return through the uncontrolled primary power return circuits resulting in potential degradation of performance, increased EMI, and possible violation of safety objectives.

Figure 4.86 Illustration of isolation of grounds and lack of isolation (permitting a ground loop to exist).

No isolation exists between “commons” of assemblies

No DC isolation; “ground loop” exists VG

ZG

DC return conductors

DC isolation (via isolation transformer) between “commons” of assemblies; no “ground loop”

S reference structure Signal

58 An elaborate and extensive discussion of grounding schemes in power distribution networks of integrated systems is provided later in this chapter. 59 Secondary Electrical Power: Electrical power is a system that has been isolated from the primary electrical power before it is distributed to subsystems. 60 Primary Electrical Power: Electrical power taken from power generation units without conditioning or isolation.

229

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4 Fundamentals of Grounding Design

Isolated DC/DC SMPS Signal current EVDC X

Signal return current path

Figure 4.87 Effect of lack of isolation in the power supply interface on system functionality. (a) Isolated secondary power circuit: signal return current flows only through controlled secondary power return circuit. (b) Non-isolated secondary power circuit: signal return current may flow through uncontrolled primary power return circuit.

X

No signal return current path through primary return (a) Non-isolated DC/DC SMPS Signal current EVDC

Signal return current

Signal return current path through primary return Direct power feed (b)

When a grounding scheme that is totally isolated across all interfaces is used (and for that purpose an isolated DC/DC power supply was utilized), isolation throughout all circuits of the system (including power, control, signal, data, etc.) must be maintained. Note that for any interface to be considered isolated, only one end of the interface (sending or receiving) needs to be isolated.

4.4.3

Isolation and Grounding in Switch-Mode Power Supplies

Within all SMPSs, there are four major current loops. Two of the loops, the “switching transistor current loop” and “output rectified current loop,” are rich with harmonics and noise due to the highly nonlinear switching operation (Figure 4.88). The current waveforms are typical trapezoidal pulses with high peak currents and rapid waveform di/dt transitions, thus comprising higher frequency spectral components. The two remaining current loops are the “input current loop” and “output current loop,” which carry current of lower frequency content, and should remain interference-free. Uncontrolled flow of current through high interference to sensitive paths may adversely affect equipment performance and produce excessive EMI. Figure 4.88 illustrates the above-described current loops in non-isolated (Figure 4.88a) and transformer-isolated (Figure 4.88b) SMPS configurations. The main drawback of non-isolated power supplies (Figure 4.88a) from the standpoint of EMI is self-evident. Any voltage potential difference present between the GRPs of the source and loads results in differential-mode interference current propagating between source and load or vice versa unless the power supply and its loads are floated (which may conflict with safety regulations). This could result in performance degradation and failure to comply with EMC requirements. A transformer-isolated power supply overcomes this difficulty. Interference appearing across the ground reference now appears as common-mode interference across the windings of the transformer, minimizing the adverse effects of this interference. Furthermore, isolation in the power supply permits the application of an equipment internal grounding scheme independent of the host system, platform, or facility grounding architecture. Notice in Figure 4.88b) that a feedback signal must be isolated and brought over the isolation boundary from the secondary (“cold”) ground to the primary (“hot”) ground in order to maintain isolation. Figure 4.89 illustrates the effect of violation of this

Input current loop

Switching transistor current loop

Power switching transistor

L

Output rectified current loop

Regulated DC output load voltage VOut Output/load Current loop

CIn

COut

VFeedback

PWM/PRM switch control

VSource

C

A Source ground reference

Input current return path

B Output rectifier current return path

Power switch current return path

Output current return path

Load ground reference

(a) Switching transistor current loop

Input current loop

Step-up/down pulse transformer (“flyback”)

Output rectified current loop

Regulated DC output load voltage VOut

Output/load current loop

Power switching transistor

VFeedback VSource

PWM/PRM switch control

CIn

COut

Analog ground A Source ground reference

C

B

Power switch current return path

Input current return path

“Hor ground”

Output rectifier current return path

Output current return path

Load ground reference

“Cold ground”

Optical isolator

(b) Figure 4.88 Current loops and return paths in major switch-mode power supply topologies. (a) Non-isolated (“Buck”) switch mode power supply. (b) Transformer-isolated (“Flyback”) switch mode power supply.

VFeedback VSource

PWM/PRM switch control

CIn

A Source (“hot”) ground reference

COut

C

B Interference ground current loop, IGL

Potential difference, VG, between source and load ground references, connected to a common reference structure

Figure 4.89

Effect of non-isolated feedback circuit on system grounding architecture.

Load (“cold”) ground reference

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4 Fundamentals of Grounding Design

isolation on system grounding architecture. A conductive path exists, allowing current, IGL, resulting from an interference potential difference between the “cold” and “hot” reference points, VG, to flow through the feedback circuit between the primary and secondary circuits, intended to be isolated by the isolation transformer, making the transformer useless. The voltage drop across ground, VG, will produce interference in the feedback circuit and, consequently, across the load. The controller, the core of the converter, can be referenced to either the primary or the secondary side ground. Several methods can be used for deriving a feedback signal from the secondary side and bringing it across the isolation boundary. The best design approach for “crossing the isolation boundary” varies with application. Many factors such as performance, complexity, and cost need to be considered. Evaluation of the isolation circuit against the system objectives is necessary throughout each stage of the design. Yet, non-isolated power supplies are often used in some applications such as in digital circuits, where multiple non-isolated DC voltages (such as 5, 3.3, 2.5, and 1.8 V) are required. Circuits powered from such diverse voltage sources are commonly designed to share a common ground reference and thus isolation is neither required nor desired. SMPSs are used in such applications simply for achieving higher efficiency of power conversion, particularly when high currents are drawn.

4.4.4

Isolation Requirements and Testing

Isolation, as discussed earlier, prevents unwanted current from flowing between two or more parts of a system. This current may flow due to a potential difference between the supply rail grounds (for example, high voltage mains to a low-voltage boardlevel power supply), because the grounds are not at the same potential across the system (power ground and signal ground may be at different potentials) or because external voltage may be applied to the system (noise interference, faults, or misuse). The unwanted current can be hazardous to life (shock hazard), may cause equipment damage (faults), or it can simply be a nuisance (erratic data measurements). Isolation is not absolute. At sufficiently high voltages, the insulation will break down and current will flow. The isolation rating should not be confused with the working voltage. Whereas the isolation voltage is the voltage which may be applied across the isolation for a short duration without current flowing, the working voltage is the maximum voltage that may be applied continuously across the isolation without isolation breakdown. As there are different levels of prevention required, particularly when electrical safety is of concern (i.e. hazardous voltages are present), the different levels of prevention, known as “insulation grades,” must also be considered. The isolation grade requirements for a given application are determined through industry standards, government regulations, and safety directives; therefore, the requirements are both application and safety standard-specific. The power supply unit, whether off-board or on-board, typically forms the main component for ensuring compliance with the safety regulations. Five types of insulation grades are defined, namely, functional, basic, double, supplementary, and reinforced insulation.61 a) Functional Isolation. Functional insulation is the simplest grade, and while providing isolation, it provides no any protection against electric shock. When functional isolation is applied, the two (or more) parts of the system are galvanically isolated from each other. Ground loop currents and cross-interference from one supply rail to another are blocked and protection against certain fault conditions (for example, output short circuits) can be implemented. In a power supply, functional isolation is commonly achieved using a transformer. The input and output windings can be wound directly over each other with just the wire coating providing electrical isolation. There are no minimum creepage or clearance separation distances required as the isolation provides no protection against electric shock. Typical applications of functional isolation are avoiding ground loops, signal interference isolation (separating quiet and noisy power rails), board-level power supplies (isolating the load from the supply), and ability to generate positive or negative voltages by choice of grounding point and multichannel or bus-systems (a short circuit on one output does not pull down the entire system). b) Basic Isolation. Basic isolation constitutes, in addition to functional isolation, an isolation layer to protect against electric shock in conjunction with another measure of protection. In a DC/DC power supply, basic isolation between input and output is commonly achieved using a transformer with the input and output windings separated with a layer of solid insulation. Basic isolation to ground is typically achieved by insulation or physical separation. There are minimum creepage or clearance separation distances required, depending on the voltage differences in the system, over-voltage category of the supply, pollution degree of the environment and for clearance, altitude, etc. Typical applications of basic isolation are DC voltage systems which are considered to be potentially hazardous (above 60 VDC) or functional isolation applications requiring an additional single-fault protection for reliability. Basic isolation between AC input and ungrounded outputs is not applicable for mains-powered applications because two means of 61 Although both terms, isolation and insulation, are often used interchangeably, isolation refers to the separation between two systems or voltage levels, while insulation refers to the actual medium being used to do the separation.

4.4 Role of Isolated Switch-Mode Power Supplies in Grounding System Design

protection are required by the safety regulations. However, basic isolation between AC input and a grounded housing is required. c) Double Isolation. Double isolation constitutes, in addition to functional isolation, two independent isolation layers, each capable of protecting against electric shock (two means of protection). In a power supply, double isolation is commonly achieved from input to output using a transformer with the input and output windings separated with two separate layers of solid insulation of a minimum thickness. There are also minimum creepage or clearance separation distances required, depending on the voltage differences in the system, over-voltage category of the supply, pollution degree of the environment and for clearance, altitude, etc. Typical applications of double isolation are AC/DC mains-powered systems in a nonconductive (e.g. plastic) housings with no earth wire and high reliability DC/DC isolation applications requiring double-fault protection. d) Reinforced Isolation. Reinforced isolation constitutes, in addition to functional isolation, a single insulation layer that is equivalent to two independent protections against electric shock. In a power supply, reinforced isolation is commonly achieved using a transformer with the input and output windings separated by set creepage and clearance and a single thick insulator or with a single thinner layer of solid insulation and one winding using triple insulated wire. The advantage of the latter approach is a much more compact transformer compared to a double-insulated design. There are minimum creepage or clearance separation distances required, depending on the potential differences in the system, over-voltage category of the supply, pollution degree of the environment and for clearance, altitude, etc. Typical applications of reinforced isolation are AC/DC mains powered systems, high reliability and medical-grade DC/ DC isolation applications requiring double-fault protection. e) Supplementary insulation. Supplementary isolation constitutes a second layer of insulation that is independent of the basic insulation. The purpose of this layer of insulation is to provide protection from hazardous voltages if there is a failure of the basic insulation. Supplementary insulation is included in addition to basic insulation when protective earth is not present in a power supply. An example of supplementary insulation is the plastic case of an external power supply. While functional isolation simply requires that the isolation barrier withstands the high-voltage test voltage placed across it, the other grades of isolation require, in addition, minimum separations across the isolation barrier, namely, creepage and clearances (Figure 4.90). f) Creepage. Creepage is the minimum distance across the isolation barrier measured along the connecting surface. For example, on a PCB, the creepage distance would be the closest distance the traces on the primary and secondary side approach each other, measured across the PCB. g) Clearance. Clearance is the minimum distance across the isolation barrier measured “as-the-crow-flies” between two conductors. For example, on a PCB, the clearance distance would be the closest two exposed metal components, one on the primary and the other on secondary side, approach each other, measured through air. Minimum creepage and clearance separation distances are specified in various industry standards depending on application-specific classifications such as the operating voltage, maximum surge voltage, type of environment the power supply will be used in, and the maximum altitude. All of these factors influence the ability for current to track along the surface of a part or to arc across between two points, so the minimum separations are the worst-case distances depending on all of these factors.

Figure 4.90 Illustration of creepage and clearance on a printed circuit board (PCB).

Insulating barrier

Creepage

Clearence

Air gap

Conductors

Insulating PCB substrate

233

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4 Fundamentals of Grounding Design

The two commonly used methods in determining the quality of isolation are:

Input to output isolation test voltage

Input voltage Input to ground isolation test voltage

Output voltage

Power supply under test

Output to ground isolation test voltage

• •

Resistance (and/or capacitance when AC coupling is of concern) measurement between the two isolated circuits. Hi-pot test which measures the leakage current between the isolated circuits.

In both cases, the test involves applying a high voltage across the device or equipment terminals and observing if there is any leakage current across the insulation or barrier. The test duration is typically a short time of about 60 seconds, while the test voltage level is governed by Ground reference structure/earth UL62 standards, for instance, and set to VT = 2 VISO(cont) safety ground + 1000, where VT is the test voltage and VISO(cont) is the Figure 4.91 Illustration of input to chassis, input to output, and output continuous voltage rating of the component under test. to chassis isolation voltages. The voltage is typically applied between the power supply’s input to chassis, input to output and output to chassis63 (Figure 4.91). Most insulators exhibit extremely high impedance (extremely low current flow) until the applied voltage (and thus the resultant voltage field strength) is great enough to “break down” the insulation. Once the insulation breaks down, it stops behaving as a good insulator and subsequently serves as a poor conductor. Hazardous levels of current can flow across an isolation barrier after the insulation has broken down. The breaking down of insulation is dependent upon both magnitude and duration of the applied voltage stress. For this reason, the specifications of isolation voltage include the magnitude of the test voltage, duration of the test voltage, and a maximum allowed current flow during the test voltage stress. The voltage waveform used for isolation voltage testing may be either a sinusoidal AC voltage or a DC voltage. Common values of insulation resistance are in the range of 1–10 MΩ at DC, and capacitances lower than 100 nF at AC.

• • • • ••

The Least You Need to Know SMPSs offer many benefits including higher efficiency, tighter regulation, wide range of output voltages, smaller size, less weight, and input-to-output and output-to-output isolation. Input-to-output isolation is often required for ensuring safety and can also eliminate undesired ground loops. SMPSs thus constitute essential elements in grounding systems and architectures. Five types of insulation (and isolation) grades are defined, namely, functional, basic, double, supplementary, and reinforced insulation. The grade requirements for a given application are determined through industry standards, government regulations and safety directives, and are application and safety standard-specific. Additional isolation requirements may be required, based on functional and EMI control requirements. Those may include AC (capacitance) and DC (resistance) isolation. Isolation must be carefully maintained and “crossing the isolation boundary” should be carefully controlled. EMI is intrinsically produced in SMPSs and must be carefully controlled.

4.5

Ground Loops

One of the most problematic types of EMI to understand, diagnose, and resolve is the ground loop. Ground loops are a mystery to many, often thrown into design literature as a placeholder for any circuit that causes ground-coupled interference.64 Most electronic engineers often fail to comprehend the concept of ground loops and typically ignore this aspect of system design. In truth, a ground loop is one of many electrical design issues that may induce or reinforce existing ground noise. In both PCBs and wired systems, a ground loop is, by definition, any complete circuit of low impedance grounding, such as a ground plane on a PCB with as with an air gap inside. 62 UL is an acronym for “Underwriters Laboratories.” UL, LLC is a global safety certification company established in 1894 as the Underwriters’ Electrical Bureau. 63 In certain cases, isolation may be (functionally) specified also between isolated outputs. In such cases, the test levels will be derived as functional specifications and may include minimum isolation resistance (for demonstrating DC isolation) and maximum capacitance (for demonstrating AC isolation). 64 Methods for investigating the susceptibility/immunity of equipment to ground-coupled interference are discussed in Chapter 14.

4.5 Ground Loops

All types of equipment are susceptible to ground loops: multimedia, medical, industrial, and data processing. Ground loops can cause data errors, component failure, lock-ups, and even safety hazards.

4.5.1 Definition of a “Ground Loop” Isolation of ground/return paths constitutes a central concept in a grounding systems’ design. Isolation implies that the net DC and AC extraneous or noise current is substantially reduced. Frequently, however, it is necessary to transport signals between two or more physically separated subsystems associated with different grounding systems, resulting in multiple paths to ground, so a closed conductive loop is formed. In such cases, where more than one ground path exists between assemblies, for instance, a signal return is connected between circuits each with a separate grounding connection to the signal reference their signal interfaces will no longer be isolated from each other and a “ground loop” is formed. These “magical creatures” appear to crop up out of nowhere and “fry” electronics or annoy one’s ear holes. Understanding them will doubtlessly save much money and hassle. It is well known that ground loops in analog AV (audio-visual) systems may result is audio hum or visible bars in a picture and sometimes may even be the cause of unexplained equipment failures. In order to overcome this situation, AV designers preach to apply a single-point “star” grounding scheme, in the form of a tree,65 with one main trunk and many branches. As each of the branches breaks out from the main trunk serving as a single common connection point, only one ground path exists between any two units. In such a scheme, when unit #1 sends a signal to unit #2, any return signal flowing back from unit #2 to unit #1 will interact with that path, No common path affecting everything that is connected to, or branches out from that path. However, that return current will between 1 → 2 → 1 2 and 3 not affect other units connected to other, remote parts of the tree structure (Figure 4.92). That property provides 1 a measure of isolation between units on the tree. When unit #1 sends a signal to unit #3, however, the 3 signal return current must traverse a section of the main trunk, which is common to the interface between unit #2 and #3, affecting unit #2 along this path. Single-point Path between ground schemes provide isolation only when signal 1 → 2 → 1 is partially propagation remains localized to isolated sections of common to 2 → 3 the system. Two or more points in an electrical system that are nominally at ground potential and are interconnected by a conducting path such that either or all designated ground points are not maintained at an equal ground potential are commonly prone to the creation of ground loops [5, 15]. Figure 4.92 A signal delivered from unit 1 to unit 2 interferes with all In the simple example in Figure 4.93, two circuits circuits along the marked path or branch from it, while unit 3 remains share a common path to ground, having a (common) unaffected. resistance RG. Ideally, the ground conductor would have zero resistance, i.e. RG = 0, yielding no voltage drop across it, VG = 0, thus maintaining the connection point between the circuits at a constant ground potential. In that case, the output of circuit 2 is simply Vout = V2. V1 R1 Vout V2 However, if RG is nonzero, RG 0, RG and R1 form a voltage divider. As a result, if a current, I1, flows through RG from circuit 1 and a voltage drop, VG = I1×RG, develops across RG, thus the ground connection of both circuits is no longer at the actual ground potential. This voltage across the ground conductor is applied to circuit 2 and added VG RG to the output: V out = V 2 − V G = V 2 −

RG V1 RG + R1

4 34

The two circuits are therefore no longer isolated from each other and current may start flowing in unanticipated ways. Circuit 1 can now introduce interference into the output of circuit 2. If circuit 2

I1 Figure 4.93 A simplified circuit illustrating a ground loop. Source: Chetvorno/Wikipedia/public domain.

65 Source: Howard Johnson (2012). Ground Loops. EDN (18 December 2012). https://www.edn.com/ground-loops/.

235

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4 Fundamentals of Grounding Design

System #1

Non-isolated interface

System #2

DC-isolated interface

System #3

Figure 4.94 DC isolated ground and non-isolated ground connections.

Ground loop ESGC (safety ground) Signal reference structure

is an audio system and circuit 1 has large AC currents flowing in it, the interference may be heard as a power frequency (50 or 60 Hz) hum in the speakers. Also, both circuits have voltage, VG, on their grounded parts that may be exposed to contact, possibly presenting a shock hazard. This is true even if circuit 2 is not energized. Although they occur most often in the ground conductors of electrical equipment, ground loops can occur wherever two or more circuits share a common current path, if enough current is flowing to cause a significant voltage drop along the conductor. Physically, the grounding system may be implemented as a wire, a trace on a PCB, a metal chassis structure, virtually anything that conducts electricity. Ideally, it should be a perfect conductor but in any practical system, it is not. As the complexity and size of the system are increased, the nonzero impedance of the ground system causes problems. Figure 4.94 illustrates an example of a system comprising both isolation of grounds between two subsystems and the lack of isolation forming a ground loop. Signal return current flows both in the return wire and through the chassis ground connections, in effect, an unbalanced system. An example of a DC isolated interface is a transformer used to transmit AC signals or power, evading the need for a conductive DC path between the assemblies. Whenever a ground loop is present, a potential for damage from intersystem ground noise may occur; the voltage-potential difference in the ground network causes interference loop currents to flow into interconnects. These loop currents are transformed by the impedance of the ground interconnects into voltage fluctuations and, consequently, system ground can no longer serve as a stable system reference. The resultant ground noise is superimposed on the intended signals at the input of sensitive circuits and becomes part of the signal processed by the component. Figure 4.95 depicts a situation that could result in ground loops. The AC-powered computer and peripherals are interconnected through their respective electrical safety ground wires within the building’s power distribution network. A voltage drop across any impedance of the grounding system within the facility may result in a possible ground potential difference between equipment. Computers may also be connected to peripherals via unbalanced RS-232 data communications cables. Multiple ground paths frequently exist. Ground loops caused by RS-232 links between devices may cause computer lockups due to power line transients and electrical noise coupling onto the interface through the ground reference line. Similar results commonly occur within multimedia systems (audio and video) with TV screens and a DVD player interconnected via an HDMI cable, for instance. Unbalanced interfaces, as in the previous example, are a common source of ground loops, often produced in shielded single-ended cable interconnects. Taking into account that some equipment assemblies are linked using shielded single-ended conductors, it is quite likely that some interference problems may arise. Return currents will almost certainly circulate from one assembly through the earth conductor into another grounded assembly and back to the first assembly via a shielded cable. This wire loop may also pickup interference from stray AC magnetic fields (B in Figure 4.96 and radio transmitters. Unfortunately, such interconnections are often overlooked when designers fail to realize that the shield actually serves as the signal’s intended return path. Figure 4.97 illustrates a typical ground loop situation. Two interconnected elements, Assembly #1 and #2, are plugged into grounded AC outlets at different locations, denoted as A (serving as the system’s “0 V” reference) and B, respectively. The signal ground is also internally connected to the enclosure (safety ground) in each. The electrical safety ground path and the duplicate signal return path formed by the interface shield form a loop that can pick up and conduct EMI currents throughout the system. VG represents the common-mode ground noise voltage drop within the SRS due to ground current flowing through the ground conductors and reference structure. Two separate reference points, A and B, are provided for Assembly #1 and Assembly #2, respectively.66 Due to finite impedance of the signal reference, a reference potential difference, VG = |VG#1 − VG#2|, exists between the two subsystems’ reference points.

66 In this example, the notations of ground, marked as “Safety Grounds” are not intended to represent the formal meaning “Earth (Ground)” (#5017) and “Frame or Chassis” (#5020) as defined in IEC 60417 Grounding Symbols (IEC 60417 symbol numbers follow the “#” sign) but rather as an indication that the two grounding points are not at the same voltage potential.

4.5 Ground Loops

Figure 4.95 Examples of ground loop situations. (a) Computer and peripherals. (b) TV and peripherals. Source: Courtesy of Max Pixel.

Printer RS-232 data cable

Computer

Computer’s power cable

Printer Printer’s power cable

Ground loop

Power distribution panel Ground loop

Ground loop

(a) DVD player

Breaker panel

TV

Audio and video cables or HDMI cable

(b)

Unwanted noise from one subsystem may be injected into C1 C2 B the other through a common return path. The magnitude of S the ground-noise voltage, compared to the signal level in each + subsystem circuit, is of prime importance. Low-level interfer– ence, below the circuit’s sensitivity threshold, will probably I have no effect on the circuit’s performance; however, when P that threshold is exceeded, the received signals will become B progressively corrupted and unusable, eventually leading to failure of the receiving circuit. Figure 4.98 depicts a general situation of signal transmission from Assembly #1 to Assembly #2. The path A–B in Figure 4.98 G G corresponds to the return path through the SRS (“ground”). B Common-impedance coupling across the impedance ZG converts the ground currents, IGI, producing a common-mode interfering voltage, VNG = VCM. The ground currents could Figure 4.96 Ground loop current induced by stray ac magnetic fields (B). Source: Chetvorno/Wikipedia/public domain. be generated by such sources as highly inductive circuits, such as a high-power PWM motor for hydraulic pumps, sharing the same return path, subsequently resulting in possible hum and noise within sensitive loads such as low-level, high-gain analog amplifiers. ZG normally comprises a series combination of resistance and inductance. The external ground interference current, IGE, is almost equal to the internal ground current IGI (i.e. IGE IGI). The interfering current, II, flowing toward the interconnecting wiring, is, therefore, much smaller than the current flowing through the reference structure. In spite of its low level, the current II is not negligible and may produce interference across sensitive loads. Once the current II arrives in Assembly #1, it splits into

237

4 Fundamentals of Grounding Design

Assembly#1

Interconnecting interface

VS

Figure 4.97

Assembly#2

Ground loop between two circuits.

VS + V G

VG#1

VG#2 Ground loop via ground and signal return (the cable shield)

A

B

0V

ESGC (safety ground)

ZG = 0.1 W

Ground noise voltage–VG

ESGC (safety ground)

Current in SRS: IG = 1 A

Signal reference structure

Assembly #2: receiver

Assembly #1: transmitter IS ZSS Unbalanced signal source

Signal transport pair “send” conductor ZGR

IR ES

VO

238

IS IR

ZL

“Return” conductor ZLS

Internal signal ground plane ZSG

Signal grounding impedance

ZSE IGE

A

ZG

II

IGI

VNG = VCM

ZLG

Signal grounding impedance

ZLE

Enclosure grounding impedance IGE B

II

Signal reference structure

Figure 4.98

Conductive ground loop interference coupling mechanism in an unbalanced single-ended system.

IS flowing through the signal line, and IR flowing through the signal-return wire (i.e. II = IS + IR). Note that the (common-mode) currents II, IS, and IR shown in Figure 4.96 are those produced by the external disturbance source and are independent of the signal source, ES. The noise voltage across the receiver terminals in Assembly #2 is proportional to the voltage drop VNG = ZG × IGI that generates the noise current II. In single-ended unbalanced interfaces, the lower line depicted in Figure 4.98 serves as the intentional return conductor for the signal current. Therefore, a noise IR, produced by the voltage drop VNG, flows predominantly on the return conductor between Assembly #1 and Assembly #2 since its impedance is typically significantly lower than that of the signal line impedance to the reference structure. The intrinsic impedance associated with the return conductor, ZGR, however, could be sufficiently large at higher frequencies so as to degrade the receiver performance due to the voltage drop, VGR = ZGR × IR. In fact, at all but very low frequencies, ZGR can generally be assumed to be primarily inductive with partial inductance, LGR; hence, ZGR can be represented as ZGR jωLGR. In fact, for this single-ended connection, the noise voltage appearing across the input of the receiver can be expressed as: V O = V GR

Z LS Z SR + Z LS + Z G

V GR

Z LS V Z SR + Z LS

4 35

Since typically ZLS ZSS, VO VGR, thus almost all the noise is superimposed on the signal voltage produced by ES and appears across the load, ZLS. If, for instance, a current of, IGI, of 1 A flows through the impedance of the ground conductor, ZG, of 0.1 Ω, results in a voltage difference between the two reference points, A and B, VNG, of 100 mV. This voltage drop will thus appear across the load as interference, superimposed on the signal voltage, ES.

4.5 Ground Loops

Assume that the input to the receiver is in the form of a “Darlington” stage [17], as illustrated in Figure 4.99a. Considering the 600 mV base-emitter voltage of both transistors and a 500 mV noise margin of the TTL gate, overall system noise immunity is 2 × 600 mV − 500 mV = 700 mV, which provides sufficient noise immunity for achieving optimal performance. If, however, a Darlington stage is not used, and a single transistor only is used at the receiver’s interface, the noise immunity diminishes to 600 mV − 500 mV = 100 mV. This margin may be too small to guarantee sufficiently reliable performance, if the diode were not present in series with the emitter. Inserting the diode increases the noise immunity margin back to 700 mV.

Assembly#1

Assembly#2 VS Noise immunity:

0.6 V + 0.6 V – 0.5 V = 0.7 V VG#1

VG#2 VG

A

(a)

4.5.2 “Who’s Afraid of the Big Bad Loop?,” or – Ground Loop Consequences Do ground loops invariably constitute a problem? They are often demonized and relentless efforts are exerted to have them eliminated at any cost. Why? The following demonstrates why (and when) ground loops constitute a problem, and when they do not. 4.5.2.1

B

Assembly#1

Assembly#2 VS Noise immunity: 0.6 V – 0.5 V = 0.1 V without diode

Why Are Ground Loops a Problem?

When ground loops exist, the current that flows in the system VG#1 0.6 V + 0.6 V – 0.5 V = 0.7 V reference structure becomes unpredictable. VG#2 with diode The return paths formed by multiple connections are the VG equivalent of a loop, which not only conductively couple noise A B between different assemblies, but also act as a loop antenna that may very efficiently pick-up interference noise. Loop currents (b) are produced by voltage differences, induction from other cables or devices, wiring connection errors, ground faults, and Figure 4.99 Effect of the input stage of subsystem #2 on the normal equipment leakage current. These currents can be at common impedance interference coupling as a result of the ground DC, 50/60 Hz power frequency, or, in reality, at any frequency. loop. (a) Darlington stage input circuit. (b) Single transistor stage Line-to-structure current leakage via capacitors in power input circuit. line filters, for instance, could introduce RF current in the return path. This leakage current is typically on the order of milliamperes per unit (typically less than 1 mA in computer equipment). However, with many such sources, each contributing small leakage currents, several amperes can easily be observed and measured. The line-to-ground capacitance of large machines such as motors can exceed safety levels internal to power line filters. Currents from such sources are usually of the order of 1 A. Even a small induced voltage can cause a large amount of current in a ground-conductor loop, as the resistance and inductance are generally low. These loop currents can be as high as tens of amperes. Cables carrying such high currents can create high-level interference current induction. As a result of the above, specific equipment problems can be of three distinct types (Figure 4.100): a) Low-level currents in the ground system generate interference voltages that cause signal and data errors. These can be low frequency (such as power frequency hum on analog systems) or high frequency (electrical noise). Figure 4.100 Common interference problems associated with ground loops.

3. Common-mode noise on power supply lines

1. Noise and hum in control and data lines

Printer data cable Ground noise current (from external noise sources)

2. Transient currents due to lightning and electrical faults on data ground

239

240

4 Fundamentals of Grounding Design

Ground loops are the most common cause of AC-power frequency interference to audio and video signals when multiple multimedia system elements are interconnected. A typical indication of a ground loop problem is the annoying audible “hum” and “buzz” noise (50 Hz/60 Hz power frequency and their harmonics) superimposed on the signals. In video or television systems, this hum may be perceived as stationary or moving bars across the screen (Figure 4.93b). Audio-frequency ground loop problems are typically in the low-millivolt range. It does not take much interference in a grounding system to introduce problems. b) High-energy transients can cause serious problems as transient currents flow to earth through return conductors rather than through the electrical safety ground. Transients can be generated internally (switching or inrush currents) or externally (lightning transients). Transients may cause equipment damage such as flash-over in connectors, heating, and burned wiring, as well as damages to driver and receiver communication ports as well as to the digital signal-processing circuits themselves. c) Ground loops constitute one source of common-mode noise in power and signal circuits. This noise is subsequently injected into circuits and can cause equipment disruption. Industrial and process-control applications, for instance, which are concerned with sensitive and accurate measurements of voltage, current, temperature, pressure, strain, and flow, often involve environments with hazardous voltages, transient signals, common-mode voltages, and fluctuating ground potentials. Such phenomena are capable of damaging measurement systems and significantly degrading measurement accuracy.

4.5.2.2 When Are Ground Loops Not a Problem?

Ground loops do not cause problems when both the following provisions hold: a) None of the wires in the loop carries any current. This, however, is impractical in real systems in which nonzero impedances of conductors are virtually nonexistent. b) The loop is not exposed to external time-variant electromagnetic fields, which implies a zero-ambient electromagnetic field environment. However, there is practically no situation in which such a condition can be satisfied.

4.5.3

Ground Loop Interference Coupling Mechanisms

Most ground loop interactions, particularly where higher frequencies are concerned, result in common-mode currents flowing within the system. Elimination of ground loop problems (the cause) has often become, therefore, synonymous with commonmode interference (the outcome) suppression. As will be shown in the next section, ground loop interference is typically associated with common impedance coupling, and to that effect, also to common-mode interference. Interference currents flow through common impedance introduced by the SRS shared by the victim and culprit circuits. Interference currents may also be produced through radiated electromagnetic field to cable interaction, whereby interference currents are induced into loops formed by the circuit wiring and the common reference structure. In this section, the manner common-mode currents are produced in electrical and electronic systems due to electromagnetic fields into ground loops is presented. The effect of such ground loops in differential circuits due to load imbalance is shown. The discussion is concluded with an introduction of the concept of circuit transfer impedance, serving as a figure of merit for common-mode to differential-mode interference conversion. 4.5.3.1 Coupled Ground Loop Interactions

Electromagnetic fields can efficiently couple undesired signals into interconnected circuits grounded to a common signal reference, particularly if little or no attention has been paid to minimizing field-to-cable interaction. Even in situations in which a high-quality grounding system is present, large loop areas bounded by signal conductors and the signal reference will exacerbate interference coupling [1, 18]. a) Magnetic Field Interactions. Magnetic (inductive) coupling involving near-field magnetic flux often constitutes the most severe offender in certain situations. The magnetic field produced by an adjacent current-carrying circuit induces emf sources into the signal transport conductors producing common-mode current flow between both conductors and the signal reference (Figure 4.101). The level of induced current is directly proportional to the coupling efficiency, which, in turn, depends on the circuit’s layout and the interference field characteristics (field intensity and frequency). Figure 4.102 illustrates that H-field coupling can introduce common-mode interference into a circuit by coupling into a transmission line grounded both at the source and load ends. Coupling is enhanced with an increase in the loop area between each of the circuits to the signal reference plane.

4.5 Ground Loops

Adjacent current-carrying circuit generating an interfering magnetic induction field

Circuit #1: transmitter

Magnetic induction

ICM#1 ZL

ES + ES–

ICM#2

VDM

Differential signal source

Circuit #2: receiver

Loop area–S ZSG-E

Signal grounding impedance

ZE-SR

Enclosure grounding impedance

ZG

VNG = VCM

ZSG-E

Signal grounding impedance

ZE-SR

Enclosure grounding impedance

Signal reference structure

Figure 4.101

Magnetic (inductive) interference coupling producing ground loop interference.

Figure 4.102 H-field common-mode interaction in a victim signal transmission circuit.

IS

ES

ICM

ZL2

VN2

Stray inductive (magnetic) coupling

VN1

ICM +IDM

ZGND

ZL1

loop round

”

“G

ZGND

–IDM e lo “Larg “Small

loop”

op”

V GND

The key to minimizing the effects of inductive coupling into ground loops is to minimize the enclosed loop area around which current flows (“Faraday’s law of induction”) (Equation (4.36)): E dl = −

V NG = CLoop

∂ ∂t

B ds ≈ − SLoop

∂B SLoop ∂t

4 36

In practice, minimizing inductive coupling can be accomplished by reducing spacing between the conductors in the victim circuit, increasing the spacing between the source and victim circuits as well as by keeping both conductors adjacent to a signal reference as much is possible. As a result, the area of the loops formed between both conductors in the victim circuits (the “small loop”), as well as between the victim circuit conductors and the signal reference (the “large loop”) are reduced. b) Electric Field Interactions. Interactions of E-fields with conductor loops are similar in nature to the H-field interaction. Both may introduce common-mode currents and voltages onto victim circuits. E-field interaction is shown in Figure 4.103. Often disregarded by system designers is the fact that E-field interactions are associated with stray reactance paths that normally exist within a product design. E-field interaction is barely affected by minimizing or maximizing the quality of “ground connections,” “ground conductors,” and the like. On the other hand, source-to-victim separation, mutually exposed circuit

241

4 Fundamentals of Grounding Design Stray capacitance provides “return” current path via “displacement”

Adjacent current-carrying circuit generating an interfering electric coupling field

Circuit #1: transmitter

Capacitive induction

Circuit #2: receiver

ICM#1 ZL

ES + ES–

ICM#2

VDM

Differential signal source

Loop area–S Signal grounding impedance

ZSG-E

ZSG-E

Enclosure grounding impedance

ZE-SR

ZE-SR ZG

VNG = VCM

Signal grounding impedance Enclosure grounding impedance

Signal reference structure

Figure 4.103

Electric (capacitive) interference coupling producing ground loop interference.

Figure 4.104 E-field common-mode interaction in a victim signal transmission circuit.

Stray electric (capacitive) coupling ES

ICM

ZL2

VN2

IS

ICM

+IDM VN1

242

ZGND

ZL1 – IDM

ZGND –ICM –ICM

areas, relative orientation between circuits, and so on, are of utmost significance. The fundamental mechanisms of E-field interaction between circuits are shown in Figure 4.104. It is important to realize that a common reference between the circuits may be a chassis of the enclosure, the facility ground, a SRS, a return plane in a PCB, or any combination thereof. The level of the coupled current is directly proportional to coupling efficiency, which, in turn, depends on the mutual circuits’ layout and on the interference field characteristics (field intensity and frequency). The key to minimizing the effects of capacitive coupling into ground loops is to minimize displacement current ∂D ∂t between circuits, which, in turn, depends on the stray capacitance between the circuits (“Ampere’s Law”) (Equation (4.37)):

H dl = C

J + S

∂D ∂t

ds

4 37

4.5 Ground Loops

Electric coupling is enhanced with increased conductor length and proximity between source and victim circuits. Hence, minimizing interaction can be accomplished by increased separation and minimizing the parallel common length between adjacent conductors. Reducing loop area in the circuits will yield little improvement, since unlike magnetic coupling interaction is not dominated by loop area. Electric (capacitive) interactions are commonly dominant in high-frequency circuits as they are limited by the value of the stray capacitance between the circuits. It is also evident from Figure 4.102 that even in cases where grounding impedance, ZGND, in the victim circuit is nonconductive, such as when it is “floated” at one or both ends, there will be little reduction in coupling at higher frequencies. Stray capacitance will “complete the loop” for induced common-mode currents on the victim circuits’ conductors. 4.5.3.2

Ground Loop Interference Due to Load Imbalance

Differential and balanced circuits67 are erroneously considered a “magic solution” to ground loop-coupled interference problems. Perfectly balanced circuits would be indifferent to externally introduced common-mode interference, since the effect of common-mode currents present on both the “send” and “return” conductors would cancel across the receiver’s balanced load. No differential-mode interference signal subsequently develops across its load. If the two lines are not identical (“unbalanced lines”), however, “common-mode to differential-mode conversion” occurs, resulting in differential-mode noise across the differential receiver input. Figure 4.105 depicts undesired common-impedance (conductive) coupling between two interconnected assemblies [18]. Assembly #1 is a differential transmitter represented as the signal source, ES,68 with source impedance, ZS, while Assembly #2 is a differential receiver, represented by the differential load impedance, ZL. Both circuits are grounded to the SRS. In this arrangement, a potential difference between two grounding reference points (VNG = VCM) is assumed, creating an interference voltage. This common-mode voltage source drives common-mode currents ICM#1 and ICM#2 through both “send” and “return” conductors through the loops formed between the two systems’ ground connection points. As a result, some noise voltage develops across the “common-mode impedances” ZC1 and ZC2. ZC1 and ZC2 may not necessarily constitute physical components: they could be conductors, physical impedances, or could result from stray capacitance. In a perfectly balanced system, where ZC1 = ZC2, no differential noise voltage would develop across ZL due to the commonmode currents flowing though ZC1 and ZC2. The signal developed on the load will result from the differential voltage source only: VL ≈

ES Z L + 2Z S

4 38

ZL

In realistic circuits, this is seldom the case. It would be reasonable to assume that ZC1 ZC2. Any difference, ±ΔZ (ΔZ = |ZC1 − ZC2|), represents a degree of the “load imbalance” that exists between them to a “differential load,” ZL, such that: Z C1 =

Z + ΔZ Z − ΔZ and Z C2 = 2 2

4 39

Assembly #2: receiver

Assembly #1: transmitter ZS

ICM#1 ZL

Common mode interference current loop ZS

ZSG-E

Signal grounding impedance

ZE-SR

Enclosure grounding impedance

“Return” conductor Internal signal ground plane

ZG

VNG = VCM

ICM#2

VDM

Differential signal ES+ ES– source

Signal transport pair “send” conductor

ZC2

Output signal disrupted by CM to DM conversion

ZC1

ZSG-E

Signal grounding impedance

ZE-SR

Enclosure grounding impedance

Signal reference structure

Figure 4.105 Conductive ground loop interference coupling in a differential system introduces common-mode ground to differential-mode noise due to circuit imbalance. 67 Refer to Chapter 2 for a description of differential and balanced circuits. 68 In a differential and balanced circuit, in practice, the source voltage ES is a differential source, appearing between the two lines. For illustrating the balance of the source, ES is shown as a split source between the signal and return lines.

243

244

4 Fundamentals of Grounding Design

Consequently, some differential voltage, VDM = VL, develops across the differential load, ZL, introducing interference into the load circuit. Ignoring transmission line impedance (assuming electrically short conductors), the resultant total differential voltage across the load is: V L ≈ I CM#1

Z + ΔZ − I CM#2 2

Z − ΔZ 2

+

ES Z L + 2Z S

ZL

4 40

It is assumed that ZL ZC1 + ZC2. By definition, in a perfectly balanced circuit (ΔZ = 0), common-mode currents are equal (ICM#1 = ICM#2 = ICM) resulting in the desired response, expressed in Equation (4.40). It follows that in “real-world” (nonideal) balanced systems, common-mode noise voltage present across the SRS will result in undesired differential-mode interference introduced across the receiver’s load. This differential-mode voltage appears as a “legitimate” input across the load and may cause an undesired response in the receiver. In wired signal transmission, conversion between the differential- and common-modes deteriorates the quality of the transmitted signal and also causes electromagnetic compatibility problems in the environment. Therefore, the T-line components are requested to be tested on their conversion loss characteristics, such as the longitudinal conversion loss (LCL), transverse conversion loss (TCL), and mixed-mode S-parameters [19]. The degree of unwanted differential mode interference signal, V DM , produced at the terminals of the network, due to the presence of a common-mode (or longitudinal) signal on the connecting leads is defined as longitudinal conversion loss factor, or LCL.69 LCL represents the extent of common-mode to differential-mode conversion in the system [20]. LCL is expressed, in dB, as: V CM V DM

LCLdB = 20 Log

4 41 V o = constant

where: VCM = Common-mode voltage applied to the two balanced input ports of the system, required to generate the standard output voltage, VO V DM = Differential-mode voltage applied between the two balanced input ports of the system, required to generate the standard output voltage, VO Note that the differential-mode voltage, V DM , is NOT the intentional, or desired differential signal voltage but rather the portion of the CM noise that is converted to DM interference. Clearly, a high level of LCL indicates a lower common-mode to differential-mode conversion. The LCL factor, characterizing a circuit, should not be confused with common-mode rejection ratio (CMRR), a devicespecific parameter, independent of installation and parasitics, characterizing the circuit’s response to common-mode signals, and particularly its ability to reject (that is, to exhibit a weaker response to) common-mode signals present at its input terminals. CMRR is defined as the ratio of the common-mode voltage, VCM, required to produce a standard output voltage, Vo, across the differential load, to the nominal differential voltage, VDM, which would produce the same differential output voltage, Vo. CMRRdB = 20 log

V CM V DM

4 42 V o = constant

A CMRR figure is typically provided by manufacturers in the devices’ data sheets. Keep in mind, that the CMRR is frequencydependent: It can reach very high values (as high as 80 dB) at lower frequencies, falling rapidly as the frequency increases beyond the operational frequency of the component. At higher frequencies, achieving a large CMRR value may be difficult to accomplish. Combining Equations (4.40) and (4.41) while assuming ΔZ Z, we obtain: LCLdB = 20 log

V CM Z + 2Z S ≈ 20 log V DM 2ΔZ

4 43

The extent of circuit imbalance will determine the extent of mode conversion and hence, ground induced interference across the differential load. Unfortunately, a system designer has little, if any, control on the amount of common-mode current flowing through the system. It is often determined by factors external to the system itself, such as fault current surges or lightning impulses. Therefore, for precluding the common-mode to differential-mode conversion, the best design practice is that of minimizing the 69 The “longitudinal conversion loss” or LCL is a parameter originally used for telecommunication equipment; see Chapter 2 for a discussion on common-mode to differential conversion and vice versa.

4.5 Ground Loops

common impedance across the broadest frequency band achievable. The second factor under the designer’s control is circuit balance.70 Would “floating” of the circuits offer an adequate solution, and eliminate ground loops? In all but very low frequency applications, “floating” of either circuit, whether between the internal signal ground plane to the enclosure chassis (ZSG-E) or from the enclosure chassis to the SRS (ZE-SR), will be of little benefit in eliminating the problem. Higher frequency displacement current can still flow through these loops owing to the large parasitic capacitance present between the surfaces, effectively completing the loop circuits. Floating will therefore significantly suppress only low-frequency ground loop currents while having little, if any effect on the high-frequency currents, a fact regretfully commonly overlooked by system designers. Common-mode currents flow through potentially large loops: between either of the signal transmission line pair or the signal reference (note the arrows in Figure 4.103). Each of these common-mode currents acts as two differential-mode currents from the stand point of producing radiated fields, the level of which are proportional the loops’ dimensions.

4.5.3.3

Application of the Transfer Impedance Concept to Ground Loop Interference Coupling

Assembly#1: transmitter

IO

ZSS

Differential IR signal ES + ES – source ZSR

Signal transport pair “Send” conductor

ICM#1

ZL

“Return” conductor

ICM#2

Signal grounding impedance

ZSE IGE

A

II

Assembly#2: receiver

ZGR

Internal signal ground plane ZSG

V DM

In previous discussions, it was demonstrated that common-impedance is the immediate cause for ground loops interference coupling, but no insight was provided as to the nature of this impedance. It was evident that in single-ended unbalanced systems, the interference voltage present across the impedance of the reference structure between the interconnected assemblies appears in its entirety as noise superimposed on the intended received signal across the load. From the examples presented earlier, it may be deduced that as long as a low impedance of the ground reference structure is maintained, no interference coupling problems will occur. Unfortunately, the situation is not that simple, particularly if differential and real-world balanced interfaces are used. In this section, a quantitative approach for computation of ground loop interference coupling (GLIC) mechanism is presented, making use of the concepts of transfer impedance and partial inductance. This technique sheds light on the principal factors associated with the GLIC and practical approaches for effectively addressing such challenges. Figure 4.106 depicts a general situation of balanced signal transmission interface from Assembly #1 to Assembly #2. The path A–B in Figure 4.106 corresponds to the return path through the SRS (“ground”). As previously shown, it is anticipated that common-impedance coupling across the impedance ZG converts the ground currents IGI to a common-mode interfering voltage, VNG = VCM. Here again, ground currents flowing through ZG may result in interference to sensitive loads such as low-level, sensitive, high-gain analog amplifiers. As will be shown herein, common noise produced across the reference structure will still produce some interference across the differential load. In case of balanced, differential-mode signaling, the Thevenin equivalent circuit of the source driver typically has low values of ZSS = ZSR and the source voltage is represented as a split and complementary pair of sources ESS = −ESR in series with ZS and ZR, respectively, in order to excite a differential-mode signal (Figure 4.106).71 At the end of the transmission line, the differential load consists of a differential load, ZL, in addition to two impedances to the local reference, ZLS = ZLR, which may be

ZG

IGI

VNG = VCM

ZLR

Output signal disrupted by CM to DM conversion

ZLS

ZLG

Signal grounding impedance

ZLE

Enclosure grounding impedance IGE B

II

Signal reference structure

Figure 4.106 Conductive ground loop interference current introduces common-mode to differential-mode noise due to circuit imbalance in a differential system.

70 Common-mode to differential-mode conversion and the effect of circuit balance on system performance are further discussed in the next section 71 For simplicity of the image, this split source is not illustrated. As it can be assumed as an ideal source (with the source impedances considered in the circuit) it has no effect on the discussion herein.

245

4 Fundamentals of Grounding Design

Signal wire

ZS

ZL IR

VO

IO

Return wire

ZGS

ZGL VNG

II

Signal reference (“ground”) conductor (a)

RSW

ZS

LSW

IO

Signal wire

MS–R RRW

ZL LRW

IR

ZGS

VO

246

Return wire

ZGL II

VNG Signal reference conductor (“ground”) (b)

Figure 4.107 Model of single-ended interface for analysis. (a) Simplified model structure. (b) Equivalent circuit for analysis. Source: Courtesy of Spartaco Caniggia and Francescaromana Maradei.

present and are ideally maintained equal for the purpose of circuit balancing. Also, in high-speed transmission circuits, it is desirable to ensure that ZLS = ZLR = Z0, where Z0 is the differential-mode characteristic impedance of the transmission line between the two circuits. The interfering current, II, produced by the voltage drop, VNG, subsequently appears as common-mode current for the system comprising the two conductors between the driver and the receiver. The concept of transfer impedance is now applied to quantitively characterize the common-impedance coupling between a loop carrying high current that produces unwanted current in a second loop. The two loops share a segment of conductor with a low effective impedance [21]. Consider a simplified case of the circuit in Figure 4.106 with the two circuits directly interconnected to the SRS (“ground”). This case is depicted in Figure 4.107a [21]. The interference voltage, VNG, could be produced by an external noise current flowing through the reference structure shared with some noisy circuit (e.g. PWM-operated motor), as described earlier, or by an external electromagnetic field coupling into the loop formed by the return conductor and the reference structure. That loop area is depicted as the gray area in Figure 4.106. Since IO IR, then IR II, where II is the current produced by the EMI voltage source, VNG, acting as a forcing current around the path formed by the reference structure (A–B) and the return conductor in the transmission line, as shown in Figure 4.104. The combined impedances [ZGS = ZSG + ZSE] and [ZGL = ZLG + ZLE] are associated with the paths between the source Assembly #1 (subscript “S”) and load Assembly #2 (subscript “L”) to the reference structure, respectively. The induced noise voltage at the interconnect output is the voltage VO occurring at the input of the receiver. To quantify the interference, the GLIC parameter is introduced, defined as72: GLIC = 20 log

VO dB V NG

4 44

When the conductors between source and load assemblies are electrically short, the equivalent circuit of Figure 4.107b can be used to compute the GLIC across the frequency range of interest. In this circuit, capacitive effects are neglected because the impedances of the circuit ZGS and ZGL are normally of low value for digital signaling and so inductive effects prevail. In the circuit of Figure 4.107b the inductances, LSW and LRW of the signal and return wires, respectively, represent the self-partial inductances73 while MS–R symbolizes the mutual-partial inductance between the signal and return conductors. RSW and RRW stand for the resistances of the signal and return conductors, respectively. The impedances ZSG and ZLG are associated with the connections to the reference structure (ground) and therefore are of very low value. The parameters ZS and ZL correspond to the circuits’ source and load impedances, respectively. To facilitate the calculation of the GLIC, the concept of partial inductance is now introduced. A closed current loop (of contour C) is correspondingly divided into a number of segments, Ci (where the index, i, represents the number of segments), each of which is attributed an unequivocal value of self-partial inductance regardless of the character of the overall loop. In addition, mutual partial inductance between any two segments of the loop is introduced (Figure 4.108).

72 The GLIC, as defined, is a special case of the LCL (longitudinal conversion loss) defined earlier. 73 The concept of partial inductance is discussed in detail in Chapter 2, and is only partially repeated here for clarity.

4.5 Ground Loops

LP22 (C2)

Recalling that the magnetic flux density, B, can be expressed as a function of a vector potential, A, such that B = ∇ × A, and applying Stokes theorem, the inductance of the entire loop of contour C can be expressed as:

A

LP12

A dl = C

4 45

Li

LP13

LP11 (C1)

LP33 (C3)

LP14

i=1

Note that I1 = I2 = I3 = I4 = I. As the entire contour, C, forming the loop, comprises the sum of all segments, Ci, of the loop, the effective inductance, Li, of each i-th segment of the loop is thus defined as a sum of all partial inductances associated with this segment. Accordingly, the total inductance of the loop is the sum of all self- and mutual-partial inductances associated with each segment (Figure 4.108): 4

Li =

I1

4

ϕ 1 1 LC = A = B da = I I I

I2

± Lpij

4 46

I3 I4

LP44 (C4) I1 = I2 = I3 = I4 = I

Figure 4.108 Conceptual illustration of partial inductance associated with the i-th segment of a contour, Ci.

j=1

The partial inductance associated with the i-th segment of the contour, Ci, is thus: Lpij =

1 Ij

Aij dC i =

1 Ij

B ij da i

4 47

Ai

Ci

The self-partial inductance, Lpii, and partial mutual inductance, Lpij, for circular wire conductor(s) of length, ℓ, and radius, rw, separated by distance, d, are expressed, respectively, as [21]: μ0 ℓ 2π μl ℓ Lpij ≈ 2π

Lpii ≈

2ℓ −1 H rw 2ℓ ln −1 H d

ln

4 48 4 49

These expressions are valid as long as d ℓ and rw ℓ. This concept can now be applied to the circuit in Figure 4.107b which is expanded to Figure 4.109, where each of the circuit conductors, the signal (S), return (R), and reference (G) is replaced by the corresponding partial inductance, LPSW, LPRW, and LPG, respectively. The effect of the current flowing on each of the conductors introduces an emf or voltage source across the neighboring conductors, due to the mutual partial inductance. In general, the current in the i-th conductor, Ii, produces a voltage drop across the j-th conductor, due to the partial mutual inductance between them, equal to: V ij = − jωLPi − j I i V

IO

−jωLPS–R ⋅IR

LPSW

Signal wire

−jωLPS–G ⋅II ZL

ZS IR

−jωLPR–S ⋅IO

LPRW

Return wire

−jωLPR–G ⋅II ZGS II

ZGL LPG

Signal reference conductor (“ground”)

−jωLPS–G ⋅IO

VNG

−jωLPR–G ⋅IR

VO

Figure 4.109 Partial inductance equivalent circuit of a single-ended interface for GLIC analysis. Source: Courtesy of Spartaco Caniggia and Francescaromana Maradei.

4 50

247

4 Fundamentals of Grounding Design

The current in the return conductor, IR, for instance, introduces an emf source, VS–R, across the signal conductor, equal to −jωLPS–R IR (note the negative sign from Faraday’s law of induction). In a similar manner, partial mutual inductances with the reference (ground) conductor are depicted. The impedances ZSG and ZLG, associated with the connections to the reference structure, are assumed to be very small and are therefore neglected. Capacitive effects are likewise neglected as well as the partial mutual inductances between the ground reference conductor and any of the other wires, signal and return (observe the X notation), both due to the relatively large separation between the conductors and the reference conductor. It can also be assumed that II IR IO based on reasoning presented earlier; therefore, the source ground interference voltage, VNG, can be approximated as: jωLPG I I V

V NG

4 51

Through the application of Kirchhoff’s loop equations to the circuit of Figure 4.107, a simplified equivalent circuit shown in Figure 4.110 is derived. Each of the dependent current sources (i.e. current sources which are coupled and resulting from current in the other circuit) illustrated in Figure 4.110 represents the corresponding currents II and IO flowing through the transfer impedance, ZT. The “transfer” feature of this impedance is revealed from observation of its definition for our application: ZT ≜

VO II

Ω

4 52

IO = 0

The transfer impedance, ZT, comprises a series combination of transfer resistance, RT, and transfer inductance, LT. RT represents the frequency-dependent74 resistance of the return conductor whereas LT symbolizes the equivalent inductance which corresponds to the difference between the self-partial inductance, LPSW, and the mutual-partial inductance, MS–R, in the signal and return loop. The dependent voltage sources ZT II and ZT IO determine the current induced in each of the respective loops. The transfer impedance, ZT, signifies, therefore, the extent of coupling between the circuits through the common impedance in the reference structure. From an EMC perspective, the transfer impedance, ZT, should thus be minimized. Typically, II IO, thus the contribution of the dependent voltage source ZT IO in Figure 4.110 is negligible with respect to the voltage developing across the load impedance, ZL. The shape of the signal and return conductors strongly influence ZT, and closed-form expressions are available for few specific configurations only. It can be measured indirectly, however, when

Figure 4.110 Equivalent circuit with the transfer impedance, ZT, concept applied. Source: Courtesy of Spartaco Caniggia and Francescaromana Maradei.

LLoop = LPSW + LPRW–2MPS–R Signal wire

RSW

ZL

ZS RRW

VO

248

Return wire IO −ZT ⋅ II RT

LT

RT LT −ZT ⋅ I0

II

LPRW RRW

ZGL

ZGS II

II VNG

Signal reference (“ground”) conductor

74 The value of RT is frequency dependent, beyond frequencies where skin and proximity effects can no longer be neglected.

4.5 Ground Loops

Figure 4.111 Equivalent circuit used to calculate transfer inductance LT. Source: Courtesy of Spartaco Caniggia and Francescaromana Maradei.

LSW

IS

Signal conductor ZL

IS

Vin

ZS MS–R

ES LRW

Return conductor

VRW = –jωLRW ⋅ IS V

low-frequency approximation (line electrically short) is valid as shown in the circuit in Figure 4.111, derived from Figure 4.109 when the bottom loop of the circuit is open, and can be used to calculate the transfer inductance LT = LRW: V RW ZT = Ω IS

V RW Ω IS V RW = Im H ωI S

RT = RRW = Re LT = LRW

4 53

Clearly, the interference coupling in the second circuit is directly determined by the transfer impedance, ZT, which can be expressed as [21]: Z T ω = RT + jωLT = RRW + jω LRW − M S − R Ω

4 54

Figure 4.112 illustrates the effect of transmission line configuration on its transfer inductance, LT (and subsequently, the GLIC), with particular attention to the configuration of the return (“ground”) structures. The structures depicted in Figure 4.112 are characterized by signal trace (t) and a corresponding return conductor(s), which likewise may be in a form of a trace (t) or a plane (p), as follows75 [21]: a) Broadside-coupled traces, i.e. a trace having another trace of equal size as return conductor, denoted trace–trace structure (tt). b) A trace embedded between two return traces of equal size: trace-trace-trace structure (ttt).

wr

ws

ws

t

d

d

d

d

ws

wr wr (a)

(b)

wr (c)

wr

ws

d

d

h

d

ws

wr (d)

wr (e)

(f)

Figure 4.112 Transfer inductance, LT, of various signal and return conductor structures (t = 0.1 mm, ws = 0.25 mm, wr = 10 ws, d = 0.5 mm, h = 6 × ws). (a) tt structure, LT = 408 nH/m. (b) ttt structure, LT = 134 nH/m. (c) tp structure, LT = 81 nH/m. (d) tc structure, LT = 11 nH/m. (e) ptp structure, LT = 2.3 nH/m. (f ) coax structure (RG-214), LT = 0.13 nH/m. Source: Courtesy of Spartaco Caniggia and Francescaromana Maradei.

75 The transfer inductance, LT, of the various configurations was computed numerically, using Method of Moments (MoM) and Nodal Method [21].

249

4 Fundamentals of Grounding Design

Figure 4.113 Computed GLIC (dB) for the various signal and return conductor structures. Source: Courtesy of Spartaco Caniggia and Francescaromana Maradei.

20 0 GLIC (dB)

250

tt ttt

–20

tp tc

–40

ptp –60 coax –80 10 Hz

100 Hz

1 kHz

10 kHz 100 kHz Frequency

1 MHz

10 MHz

c) A trace above a finite return plane: microstrip-type structure (tp). d) A trace within a finite U-shaped return structure: conduit-type structure (tc). e) A trace embedded between two finite return planes: stripline-type structure (ptp). f) A round wire enclosed within a tubular conductor: coaxial-type structure (coax), used as reference. Using the values of the transfer inductance, LT (which dominates the transfer impedance, ZT), from Figure 4.112, the GLIC was computed vs. frequency (Figure 4.113) using the equivalent circuit shown in Figure 4.110 up to a maximum frequency of 10 MHz (in order to maintain an electrically small structure) [21]. From observation in Figure 4.113, it is evident that the best performance is obtained with the stripline-type (ptp) and coaxial cable (coax) structures. Furthermore, the higher the frequency, the lower the transfer inductance LT (or LRW, inductance of the return path) and correspondingly, the lower is the GLIC. This frequency-dependence is further discussed in the following section. In conclusion, the transfer impedance, ZT, and particularly the transfer inductance, LT, which dominates the GLIC, depends interestingly, not only on the quality of the reference structure, as it is often assumed, but rather and in fact much more on the layout and configuration of the structure comprising the signal, return conductor, and the reference structure.

• • • •• •

The Least You Need to Know Ground loop-related interference such as “hum” and “buzz” can be either conductively, magnetically, or capacitively induced. Magnetic (inductive) coupling commonly occurs at both low and high frequencies, resulting in common-mode and differential-mode currents’ induction into victim circuits. Electric (capacitive) coupling will usually be significant at higher frequencies, resulting in common-mode currents’ induction into victim circuits. CM to DM conversion may be observed on the victim loads. GLIC represents the translation of ground-induced interference voltage to circuit interference voltage. GLIC is dominated by inductance associated with the signal return path; this inductance is primarily geometry-dependent. GLIC is frequency-dependent and typically falls with increase of frequency.

4.5.4

Ground Loop Interactions: Frequency Considerations in CM to DM Interference Conversion

The previous section demonstrated the importance of circuit balance for enhanced circuit performance. For instance, perfectly balanced circuits exhibit high immunity to externally introduced common-mode interference, since the effect of commonmode currents induced on both conductors cancels out at the receiver’s input, leaving a net zero differential-mode interference signal at the circuit input. Consider again the wire pair interconnecting two circuits. It was shown that a poorly balanced, loosely coupled pair has more of a propensity to cause interference than a well-balanced, tightly coupled one. This should be of no surprise, since the capture area of a poorly balanced, loosely coupled wire pair will allow greater amplitudes of energy to be converted to and dissipated as common-mode energy into the environment or accepted into the poorly balanced pair as differential-mode energy from external stimuli.

4.5 Ground Loops

Figure 4.114 Typical ground loop path generating common-mode to differentialmode conversion.

S

Circuit #1 ZS/2

Circuit #2 ICM#1

R1

ZL

Transmission line A

ZS/2

ICM#2

R2

Z2

VL

VS

Z1

A

h CG

d

ZCM

d

CG

VSRS = VCM

There is no magic associated with common-mode to differential-mode conversion in coupled (e.g. differential) transmission lines. Differential transmission lines are simply a pair of individual electromagnetically coupled lines.76 Typically, designers try to make both lines identical. One can excite these lines in the odd-mode (equal and opposite voltages on each line, or differential signaling) or in the even-mode (equal voltages on each line, or common-mode signaling). A not-perfectly balanced excitation results in a combination of odd and even electromagnetic field propagation modes. Similarly, if the two lines are not identical, often called “unbalanced lines,” both modes are produced in order to satisfy boundary conditions.77 Hence, when common-mode interference is introduced into an unbalanced or asymmetrical pair of lines, some differential-mode voltage will be produced by the asymmetry of the transmission line or loads. This is usually what is meant by the term “CM to DM interference conversion.” All discussion presented up to now concentrated on the effect of circuit configuration on CM to DM interference conversion. However, no detailed discussion was held regarding the effect of frequency-dependence of circuit balancing. This is now illustrated (Figure 4.114). Assume two circuits, Circuit #1 and #2. The circuits are interconnected by a two-conductor transmission line. Circuit #1 contains a differential line transmitter (source) represented as an ideal signal voltage source, VS, and source impedance ZS (illustrated as a split impedance at the source, as would be the case for a truly balanced source), while Circuit #2 consists of a differential line receiver (load) represented as ZL. Both circuits are mounted in metallic enclosures, grounded to the SRS. Both circuits are initially floated from their respective enclosure structures. The circuit area, A, with separation distance d from the SRS forms capacitance, CG (C ≈ ε A/d, where ε = ε εr, the permittivity of the medium between surface A and the SRS). For simplicity of discussion, it is assumed that CG is identical for both Circuit #1 and #2. The conductors (transmission line) are placed at height h above the SRS, and have length, S. At low frequencies, these conductors can be treated as a low-pass filter with an equivalent series inductance, LC, and inter-conductor capacitance, CC. For sake of clarity, common-mode capacitance existing between the conductors and input ports to the SRS are omitted. It is noted that the “CM impedances,” Z1 and Z2, may not be physical components, they could be conductors, physical impedances, or stray capacitance. It is also reasonable to assume that Z1 and Z2 are rarely identical, thus some small difference, ±ΔZ representing the degree of the “load imbalance” yielding: H dl = C

J + S

∂D ∂t

ds

4 55

Z + ΔZ Z − ΔZ Z1 = and Z 2 = 2 2

4 56

An arbitrary CM voltage source VSRS = VCM is now assumed present in the SRS due to one of the mechanisms described in the previous section, namely, electric, magnetic, or conductive coupling. This interference voltage source will cause current to flow in the circuit loop, limited by the loop impedance, developing some noise voltages on the unequal impedances Z1 and Z2. Due to this load imbalance, some differential voltage, VL (or VDM), will develop across the differential load, ZL, introducing potential interference into the load circuit. Ignoring the reactive impedance of the transmission line, the total differential voltage developed across the load is equal to: V L = I CM#1

Z + ΔZ − I CM#2 2

Z − ΔZ 2

+ I S ZL

where IS stands for the differential current circulating in the circuit due to the differential voltage source, VS. 76 Differential transmission lines are discussed in detail in Chapter 2. 77 Boundary conditions are defined and discussed in Chapter 2.

4 57

251

252

4 Fundamentals of Grounding Design

Circuit #1 ICM#1

ZS/2

Figure 4.115 Equivalent circuit for analysis: “floated” circuit (initial situation).

Circuit #2 LC VDM = VL

CC

ZS/2 CG = ε

ICM#2

Transmission line

LC

A d

CC

Z2 =

ZL

Z − ∆Z 2

CG = ε

Z1 =

Z + ∆Z 2

A d

VSRS = VCM

By definition, common-mode currents ICM#1 and ICM#2 are equal, hence it follows that when ΔZ = 0, representing a perfectly balanced load, Equation (4.57) simply reduces to: V L = I S ZL

4 58

If the circuit is perfectly balanced, implying Z1 = Z2, no voltage will develop across ZL due to the common-mode currents flowing though Z1 and Z2 and the signal developed on the load will result from the differential voltage source. However, this is seldom the case, thus Z1 Z2. An interference voltage difference will be present proportional to the difference in impedance, ΔZ. For the purpose of the following discussion, an equivalent circuit for this problem corresponding to Figure 4.114 is depicted in Figure 4.115. The differential input, VS, is not included. It is assumed to be an ideal voltage source; the internal source impedance, ZS, is depicted as being equally split between both lines, representing a balanced circuit. From here, the frequency-dependent characteristics of the system can now be investigated. The essential factor to consider is the loop impedance limiting the current flow through the circuit. Clearly, the lower the common-mode current flow in the circuit, the lower will the differential-mode voltage across the load. With the exception of the (split) source impedance, the dominant component of the impedance in the loop is the stray capacitances, CG, between the PCBs to the SRS, typically in the several to tens of nano-Farads. The impedance of this capacitance is inversely proportional to frequency. As a result, common-mode current circulating between the circuit conductors and the SRS will exhibit frequency-dependency and subsequently, so will the resulting differential-mode voltage across the load. At very low frequencies, the impedance of the capacitors is extremely high, considerably limiting RF current flow through the circuit, thus maintaining a low differential-mode noise voltage across the load. As the frequency increases, the impedance of the capacitances CG decreases, allowing higher current flow through the circuit resulting in higher differential-mode noise voltage across the load. However, as frequency further increases, the impedance of the capacitors becomes negligible as the low-pass characteristics of the conductors become gradually influential in dominating the loop impedance. Consequently, significant high-frequency current limiting occurs after peaking, followed by a drop in the load voltage curve at high frequencies. Three distinct cases are now investigated, originating from the circuit depicted in Figure 4.115.

4.5.4.1 Case A: Totally Floating Circuit

Figure 4.114 depicts a circuit that is totally floated with respect to the SRS, creating a true differential and balanced system. The circuit is balanced at lower frequencies. Due to the high impedance of the capacitance to the SRS, CG, the impedance of the loop formed by the SRS and the conductors is dominated by this capacitance. Only a negligible fraction of the CM current may therefore flow in this loop. As frequency increases, however, the capacitive impedance drops progressively, allowing more current to flow in the loop. This is displacement current flowing through the stray capacitance, resulting in an increase in the CM voltages developed across the common-mode load impedances Z1 and Z2, VCM#1 and VCM#2, respectively. As these voltages are not equal due to the imbalance in the circuit, they result in a differential-mode voltage, VDM = VL across load impedance, ZL, corresponding with the system CMRR. The thick curve in Figure 4.116 depicts the frequency-dependence of the voltage across the load.

4.5 Ground Loops

Relative load DM voltage (log scale)

Figure 4.116 Relative DM interference from CM noise coupling in a floating circuit (thick line).

Floated both ends

Frequency (log scale)

Figure 4.117 Equivalent circuit for analysis: grounded one end (at load end).

Circuit #1 ZS/2

Circuit #2 ICM#1

LC VDM = VL

CC

ZS/2 CG = ε

ICM#2

Transmission line

LC

A d

CC

Z2 =

Z − ∆Z 2

ZL Z1 =

Z + ∆Z 2

This side grounded VSRS = VCM

4.5.4.2

Case B: Circuit Connected to SRS (“Grounded”) at One End

Figure 4.117 depicts a situation where the circuit is connected to the SRS at one end, with the other end remaining floated. For this analysis, it is immaterial whether the source or the load side of the circuit is grounded. In this situation, the circuit may still be considered balanced, since the signal current can return only through the return conductor. In this case, the low-frequency loop impedance, dominated by the impedance of the capacitance to the SRS, CG, has been significantly reduced (when the capacitances dominate the circuit loop impedance, the loop impedance would be approximately halved). From the two capacitances existing between the circuits to the SRS, only one effectively remains due to the grounding at one end, shorting out the capacitance between the PCB and the SRS. As the loop impedance is reduced, the common-mode current flowing through the loop formed by the conductors and the SRS accordingly increases, resulting in an increase of the low-frequency differential-mode voltage across the load. No significant change is observed in the highfrequency curve since it is dominated by factors other than the capacitance to the SRS, primarily, the transmission line low-pass characteristics. The thick curve in Figure 4.118 depicts the frequency-dependence of the voltage across the load in this situation. It is noteworthy that when the loop impedance is dominated by the capacitances at both ends, the transition from a floated circuit (Case A) to the single-point grounded system (Case B) will result in an increase of coupled interference at the lower frequencies. Note that when the capacitive reactance between the circuits’ ground and the reference structure dominates the impedance of the circuit’s CM loops, elimination of the one capacitance due to grounding at one end will result in about 6 dB increase of coupled noise level at lower frequencies due to the approximately 50% (or 6 dB) reduction in loop impedance.

253

4 Fundamentals of Grounding Design

Figure 4.118 Relative DM interference from CM noise coupling in a circuit grounded at one end (thick line).

Relative load DM voltage (log scale)

254

Grounded one end

Frequency (log scale)

4.5.4.3 Case C: Circuit Connected to SRS (“Grounded”) at Both Ends

Figure 4.119 illustrates the circuit when it is connected to the SRS at both ends. With both sides grounded, an unbalanced system is produced. The capacitance to the SRS, CG, is bypassed at both ends of the circuit to the SRS. As a result, the loop impedance is dominated at lower frequencies only by the termination impedances and by transmission line reactance (which is influential at higher frequencies only). Consequently, the circuit introduces little loop current limiting at lower frequencies, resulting in high differential-mode voltage across the load even at lower frequencies. At higher frequencies, however, no difference is observed as the high-frequency performance is dominated by other factors, no different from than in both previous cases (Figure 4.120).

•• •• • •

The Least You Need to Know Imbalance in differential circuit will yield CM to DM conversion, introducing DM interference across the load. The effects of circuit imbalance are primarily a concern at lower frequencies: lower frequency performance of circuits and systems is strongly dependent on the circuit grounding scheme. Ground loops are primarily a low-frequency problem and are difficult to eliminate at high frequencies. Higher Frequency circuits are generally well behaved: circuit performance is very predictable, considering that higher frequency current-return paths are foreseeable. The preferred method for interconnecting low-frequency circuits is by balanced interfaces: SPG scheme should be favored for lower frequency circuits. Higher frequency circuit performance is independent of grounding scheme: MPG is favored in higher frequency circuits. Circuit #1 ZS/2

Figure 4.119 both ends.

Circuit #2 ICM#1

LC VDM = VL

CC

ZS/2

Transmission line

ICM#2

LC

This side grounded...

CC Z2 =

Z − ∆Z 2

... and this side grounded too VSRS = VCM

ZL Z1 =

Z +∆Z 2

Equivalent circuit for analysis: grounded

4.5 Ground Loops

Figure 4.120 Relative DM interference from CM noise coupling in a circuit grounded both ends (thick line).

Relative load DM voltage (log scale)

Grounded both ends

Frequency (log scale)

4.5.5 Resolving Ground Loop Problems The previous discussion clearly demonstrated that “ground loops” arise when multiple connections to the same signal reference occur, and are a direct result of:

••

potential differences across the SRS, and external interference sources introducing conductively, inductively, or capacitively undesired currents into the circuit formed between circuit conductors and the signal reference.

Avoiding (or controlling) ground-related interference resultant of ground loops or “living with them” is the essence of optimal grounding design for the purpose of EMI control. There are many ways to address ground loop problems. So far, two primary methods were proposed for addressing the challenge of common impedance, or GLIC via the return conductors (ground system), namely: a) Improving the Quality of the Grounding Return System. b) Avoiding Common Return Connections by reverting to a SPG architecture. In practice, many electronic systems have specific sensitivities and configurations that prohibit or make floated or SPG topologies difficult to implement. Fortunately, a third approach is available to reduce or eliminate ground loops, and their effects of these on systems, which lies in the elimination of interference current circulating between the circuit conductors and the SRS. This approach is commonly known as “breaking ground loops.” The key to resolving ground loop problems lies in the opening, or “breaking” the loops. In an effort to eliminate ground loops, driving a load with a differential driver78 is recommended [1], as illustrated in Figure 4.121. In logic state “1,” transistor T1 and T4 are “on” while T2 and T3 are “off.” The capacitance C is assumed to exhibit a short circuit at high frequencies. The transistors are assumed to represent very low forward saturation impedance, typically less than 5 Ω. Care should be taken to avoid the (common) mistake of confusing “differential” with “balanced” or “floated” circuit. From observation, the impedance to “GND” from each of the transistors, T1 and T4, is NOT identical. This “totem pole” configuration does not exhibit a balanced source! The difference between the impedance to “GND” from each of the transistors, T1 and T4, is denoted ΔZS. Figure 4.122 depicts a simplified schematic of the RS-485 driver (agreeably, a differential interface), comprising of two complementary (single-ended) “totem pole” outputs (transistors Q1, Q3 on the one, and Q2, Q4 on the second). The Q2–Q4 drive output A, while Q1–Q3 drive output B. Note that both outputs are still referenced to a common ground. Ideally, the output, 78 Note, however, that so-called differential networks are not truly differential, and the term “pseudo-differential” is more appropriate. A differential driver comprises two complementary single-ended drivers, referenced to a common return (or “ground”), compromising the network’s differential nature. The receiver, however, is truly differential, as it senses the difference between the two nets, independent of the common “ground,” thus providing high common-mode rejection and noise immunity.

255

256

4 Fundamentals of Grounding Design

Figure 4.121 A presumed differential “totem pole” source driving a balanced load.

VCC R

C T1

GND Noise current path

T2

ZL1

B R

C

GND

ZL2

T3 T4 GND

Differential driver

A

Balanced load

VCC

VCC VF DE (H)

Q1

Q2

VR-ON

R2

A D (H)

Drive logic

RD VF

VR-ON

R1

B

R1

Q1

+VD

B Q3

A

R3

Q4

Q2

R3

(a) Figure 4.122

Output stage

R2

(b)

RS-485 driver and receiver. (a) RS-485 driver. (b) RS-485 receiver.

VD = VA − VB are independent of the ground potential, however, with a small difference between the two outputs to ground, ground-coupled interference can also affect this differential interface.79 Figure 4.123 depicts a noise equivalent circuit. As the GND return connection points A and B are remotely spaced, a “ground noise” source, VN, is assumed to be present across some noise impedance, ZN. This difference will introduce a differential noise across the differential load, ZL, comprising of ZL1 and ZL2. The noise voltage across the differential load, VL, due to the ground noise source, VN, is expressed as: VL =

Z L1 Z L2 − Z L1 + ΔZ S + Z N Z L2 + Z N

VN

ΔZ S Z L1 + ΔZ S

VN

4 59

Which is valid for ZL1 = ZL2 and ZN ZL1, ZL2, i.e. a balanced load is assumed, and that the impedance between the driver and load return connections (A and B) is small compared to the high load impedance.

79 For superior isolation and enhanced common-mode rejection, an enhanced differential driver, e.g. IL-422, is used.

4.5 Ground Loops

ZL1 VN

ZN

B ZB Z L2

VL2

ES

VL

ZS

VL1

Figure 4.123 A noise equivalent circuit of the differential “totem pole” source driving a balanced load.

A

From Equation (4.42), combined with Equation (4.59), we can now determine the LCL expected from this “balanced” circuit [20]80: LCLdB = 20Log

V CM V DM

= 20Log V 0 = constant

VN VL

V 0 = constant

Z L1 + ΔZ S ΔZ S

4 60

Obviously, matched transmission lines where ZL1 is represented by characteristic impedance, Z0, results in high LCL, i.e. high common-mode to differential-mode conversion or little common-mode rejection implying significant ground loop interference! We may conclude, therefore, that a differential driver does not necessarily guarantee high common-mode (and ground loop interference) suppression. A hint to a possible solution appears from an interesting observation emerging from Equation (4.60): the differential interference voltage, VL, developed across load ZL1 (and ZL2) by the common-mode source VN is a function of the circuit balance as well as the circuit load impedance. The better the source balance and/or the higher the load impedance, the lower will be the interference voltage across the load. One possible approach for reducing source impedance imbalance, ΔZS, is to replace the current limiting resistor R in the collectors of T2 and T4 by Schottky diodes. This results in a close to perfect matching of the differential driver output. High impedance inserted in series between point B and the load ground, instead of a short circuit (Figure 4.123), will have no effect on the differential signal path between the driver and the load. It will, however, have a substantial effect on the suppression of ground loop current flowing between points A and B. Equation (4.60) is now converted into: VL = VN

Z L1

Z L1 Z L2 − + ΔZ S + Z N + Z B Z L2 + Z N + Z B

ΔZ S Z L1 + Z B

0

4 61

which holds for ZB ZN, ΔZS. Hence, if ZB is large compared to the ground noise impedance, ZN, and the source imbalance resistance, ΔZS, the voltages across ZL1 and ZL2 will approach an equal value. The two fractions in the left-hand part of Equation (4.61) become equal and the entire expression vanishes. A practical value of such resistors would be in the tens of kΩ. Often, this resistor is bypassed with a 10 nF capacitor in order to decouple high-frequency interference that may develop at point B due to unrelated sources. Four elementary approaches can therefore be employed for breaking ground loops, easily remembered as B2–I–D.

•• ••

Blocking Balancing Isolation Diversion/Decoupling

Each of the techniques presented below will, therefore, have the designation of B, B, I, or D to indicate the manner or manners the particular technique provided resolution to the ground loop problem. All of the above, with the exception of the last, have to do with the utilization of electrical isolation techniques. The different techniques for implementing each of the above approaches are now discussed.

80 “V0 = constant” should be read as “constant V0.”

257

4 Fundamentals of Grounding Design

4.5.5.1 Isolation Transformers

An isolation transformer (see Figure 4.124) is an effective device for blocking (B) common-mode interference coupling through isolation (I) between the primary and secondary sides of the circuit, resulting in balancing of the lines (B), eliminating undesired effects of ground loops. The ground loop interference currents and voltages are still present, but will be observed only at the input terminals of the transformer. The transformer accomplishes this function by magnetically coupling the desired signal from its primary to secondary. This does not require any galvanic connection or common reference between source and load. In an ideal transformer, which has no parasitics, leakage, or losses and exhibits an infinitely large inductance in the primary and secondary windings, the voltage transfer ratio is directly related to the windings ratio, n, resulting in a secondary to primary impedance ratio of n2. A practical transformer, however, exhibits a leakage inductance factor, (1 − k), thus, the inductance of each winding (1 − k) L1 and (1 − k) L2 results in an effective coupling coefficient, k. Using M for the mutual inductance between the two windings: k=

M ≤1 L1 L2

4 62

When an ideal transformer (k = 1), exhibiting no parasitics is inserted in the transmission line (Figure 4.125), ground (common-mode) noise appears only across the windings of the transformer and not across the load. The desired signal current, on the other hand, couples perfectly from source to load through the transformer to loads ZL1 and ZL2. Any noise coupling that occurs is a result of parasitic capacitance, CP, between the primary and secondary windings of the transformer (Figure 4.126). Noise developed across the load ZL (ZA + ZB) is described by: VL =

ZL jωCP Z L = Z L + 1 jωC P 1 + jωCP Z L

4 63

The degree of common-mode isolation achieved by transformers is limited by the inter-winding capacitive parasitics. Capacitance is frequency dependent, which limits the high-frequency performance of the transformer. Improvement of high-frequency performance can be achieved by introducing a shield between the windings (Figure 4.126). In this case, the shield should be connected to the signal reference (the chassis). If shielded transformers are used, both the inter-winding shield as well as the shielded enclosure of the transformer is required to be grounded for electrical safety. This shield is commonly called a “Faraday shield.”

ES

ZS

ZGS

L1

L2

EG

ZG

ZLA

ZLB

VN, VL

CP

Figure 4.124 Isolation transformers block the common-mode current path, balance the transmission line and galvanically isolate the source and load circuits.

ZGL

Signal reference structure

ZS

IS

ES

L1 VN

L2

Figure 4.125 Effect of the isolation transformer in the circuit of Figure 4.124.

IS ZL1 VL

258

ZN

B ZL2

A

4.5 Ground Loops Inter-winding shield Grounding of the shield is not arbitrary, and should be connected to the output of the transformer at point (2). If the shield were grounded at point (1), the potential across CP1 would be CP1 CP2 zero and the ground noise potential EG would have been coupled directly to capacitance CP2 facilitating noise coupling to the transformer’s output. In certain cases, (Figure 4.127), particularly where isolation transformers are used at both ends of the line, such as in certain data bus applications, further improvement of the transformer’s RF isolation can be achieved. This is accomplished by introducing an RF short from the line-side ZGL center-tap of the transformer T2 primary winding (if transformers are placed at both ends, such ZGS 1 2 shorts can be implemented at both ends). If load ZL is isolated from source grounding, the centerEG ZG tap should be grounded to the source ground and also interconnected to the load grounding point (indicated with a dashed line in Figure 4.127), else, the center-tap should be connected to the enclosure chassis. Figure 4.126 An interIsolation transformers exhibit excellent performance at lower frequency AC applications and, winding electrostatic shield in in particular, find use in audio and AC power circuits, where common-mode rejection in the an isolation transformer range of 100–140 dB can be achieved at f = 1 kHz. Isolation transformers can also be found reduces common coupling. in data bus and local area network (LAN) applications such as the MIL-STD-1553 multiplex bus and 10/100/1000BaseT Source T1 Line Line T2 Load Ethernet. CM RF noise The primary disadvantages of isolation transformers are E ZL S their relatively larger physical size, requiring costly real estate RF noise RF noise on PCBs, and additional wiring to transport both the signal shunt E Z and return between source and load, as well as relatively high G G cost. In addition, when isolation of multiple circuits is required, a dedicated transformer is required for each circuit. From the EMC point of view, isolation transformers may be intrinsically susceptible to interference from stray external Figure 4.127 An RF short from the transformer’s primary winding center-tap to the local ground further improves RF isolation. magnetic fields because inductive coupling involves the use of magnetic fields for signal transmission. Frequency limitation is yet another drawback of an isolation transformer: their high-frequency limitation is due to parasitics, ZL1 which restrict their usage to several hundred MHz. They cannot DC current be used to transport DC power. The last drawback, however, can be overcome by using a “phantom” circuit that is frequently DC power DC load used in balanced telephone and data networks, illustrated in source Figure 4.128. The DC current flowing through the circuit (and DC return the transformers’ windings) will have no effect on the signal itself, nor will it saturate the transformers’ cores. The DC curZL2 rent is fed symmetrically into the line-side windings, producing equal but opposite magnetic flux resulting in zero total magnetic Figure 4.128 “Phantom” circuits can be used to transport DC flux in the cores. power through an isolation transformer system. The term “phantom” stems, therefore, from the obvious fact that due to symmetry, the DC power cannot be observed in the individual transformers.

4.5.5.2

Common-Mode Chokes (Baluns, Bifilar Chokes)

One of the most effective techniques for blocking (B) common-mode current flow in the circuit, and hence balancing (B) the lines, is the common-mode choke, also known as “BaLun” (BALanced-UNbalanced Transformer) or “bifilar choke.” One advantage of the common-mode choke is that the device exhibits high series impedance to common-mode interference current propagating in the circuit, without affecting propagation of the functional differential-mode signal. Figure 4.129 illustrates the application of the common-mode choke. The common-mode currents applied into the circuit, ICM1 and ICM2, will develop a voltage across the inductors of the common-mode choke (ignoring the wiring resistance and all parasitics): V L1 = jωL1 I CM1 + jωMI CM2 V L2 = jωL1 I CM2 + jωMI CM1

4 64

259

4 Fundamentals of Grounding Design

CP ICM1 ES

ZS

L1 IS

ZLA

M

ZLB

L2

ICM2

VN, VL

260

Alternative symbols

ZGS

EG

ZGL

ZG

Signal reference structure Figure 4.129 Common-mode chokes block common-mode interference current but maintains the metallic path for uninterrupted differential-mode current.

With tightly coupled inductors, that is: k = 1, M = L1 = L2 = L, and assuming a perfectly balanced system, implying: ICM1 = ICM2 = ICM: Z L1 = Z L2 = 2jωL

4 65

It follows, therefore, that the equivalent circuit of a common-mode choke with respect to common-mode currents is equal to the choke’s winding inductance for each branch. For k = 0 or M = 0 (uncoupled inductors), each branch will represent a separate inductor of value L. The key to this behavior of common-mode chokes lies in their unique construction, depicted in Figure 4.130: two wires of the transmission line are wound together on the choke’s core in the same direction with an equal number of turns, symbolized in Figure 4.129 by the position of the dot present at the same side of the two windings. Figure 4.131 depicts an alternate (and more commonly applied) wiring scheme of the common-mode choke, also illustrating the currents flowing on the wiring wound upon the core and the resultant flux in the core.

• •

The differential (DM) signal current (of equal magnitude but opposite direction) creates equal but opposing magnetic flux in the core resulting in near to perfect flux cancellation. This results in the choke presenting (close to) zero impedance to the differential mode signal, which passes through the choke virtually unattenuated and the common-mode choke thus has no effect on the differential functional signal. Common-mode currents on the other hand flow in the same direction in the core’s windings by virtue of their common source, EG, introducing equal and additive (in-phase) magnetic flux in the choke’s core, which, with the high permeability of the core will introduce a very high series inductance. This effectively inhibits the CM currents, suppressing its effect on the circuit’s differential load, ZL.

A simple mathematical derivation [22] can be very helpful in understanding how common-mode chokes work. Examine Figure 4.132, where the equivalent circuits for differential-mode and common-mode currents are identified. DM-generated flux

CM current Signal DM current

CM-generated flux

Core Hi-μ

(a)

(b)

Figure 4.130 The unique construction of the common-mode choke makes it seem “transparent” to differential-mode signals and highly inductive to common-mode currents. (a) Two forms of practical construction. Source: Würth Electronics. (b) Current flow in the choke.

4.5 Ground Loops

1

4

2

Flux from CM currents is additive, to become highly inductive

3

1

4

2

3

1

4

2

3

(a)

1

4

2

Flux from DM currents oppose each other, so (almost) no inductance observed

3

(b) Figure 4.131 Common-mode (CM) and differential-mode (DM) current produce additive and opposing magnetic flux in the core, respectively (equal number of turns is used on each wire). (a) Common-mode current excitation. (b) Differential-mode current excitation.

L1

ZS

ES

ZS

RC1

IS M

ZL L2 EG

ES

ICM1

RC2

RC1

M

ZL L2

ICM2

ZG

L1

Signal reference structure

RC2 ZG

EG

Signal reference structure (b)

(a)

Figure 4.132 A simple CM and DM circuit analysis of common-mode choke-embedded circuits. (a) Differential-mode current case. (b) Common-mode current case.

Applying Kirchhoff’s voltage rule for the differential-mode current case (a), we obtain, neglecting ZG. Assuming k = 1, M = L1 = L2 = L, and neglecting the wiring resistances, RC1 and RC2 (i.e. ZS+ZL RC1 + RC2), it is clear that a common-mode choke has no effect whatsoever on the differential signal. I S − 2jωM I S + Z S + Z L + RC1 + RC2 ES ES IS = ≈ Z S + Z L + RC1 + RC2 Z S + Z L

E S = jω L1 + L2

IS 4 66

As for the common-mode current in case (b), we find: Upper Loop

EG = jωL1 ICM1 + jωM ICM2 + ZS + ZL ICM1 EG RC2 ICM1 = jωL ZS + ZL + RC2 + ZS + ZL RC2

Lower Loop EG = jωL2 ICM2 + jωM ICM1 + RC2 ICM2 ICM2 =

4 67

EG −jωM ICM1 jωL2 + RC2

In this case, only RC1 is neglected, as it is in series with (ZS + ZL) RC1, whereas RC2 is in series with inductor L2 only. Since load noise voltage, VN, is a result of ICM1 flowing through it and since (ZS + ZL) RC2, we arrive at: V N = I CM1 Z L ≈

EG RC2 L jω + RC2 L

4 68

261

4 Fundamentals of Grounding Design

VN EG

Figure 4.133 Conditions for common-mode chokes’ effectiveness.

(dB) Asymptotic

Common mode rejection

262

–3 dB Actual

ωC =

RC2 L

ω = 5·

RC2

L

Frequency (ω)

Rearranging this equation, we obtain: VN RC2 L ≈ E G jω + RC2 L

4 69

This indicates that VN/EG is minimized when L choke is derived: ω≥5

RC2/ω. From here the condition for the effectiveness of the common-mode

RC2 L

4 70

Figure 4.133 illustrates graphically the situation described mathematically in Equation (4.69) above and the conditions of Equation (4.70). For achieving high effectiveness of the common-mode choke, high-permeability (μ) cores are required. Typical values of relative permeability are μr ≈ 2000 for low-frequency applications and 100–200 for high-frequency applications, resulting in high inductance. In terms of suppression, common-mode rejection exceeding 80–100 dB can be achieved beyond the cutoff frequency of the functional portion of the choke. The primary advantage of the common-mode chokes is its capability to reject higher frequency common-mode signals propagating along a transmission line with little effect on the functional differential signals. With care, multiple common-mode chokes can also be wound on the same core structure, increasing the density or number of signal lines that the choke can handle. Also, common-mode chokes can be used on circuits employing more than 2 wire transmission lines, such as 3-phase AC0 power circuits. In this situation, the phase lines and neutral must all be wound on the same core to ensure optimal performance while precluding saturation of the core. Another advantage in using common-mode chokes is their capability, unlike isolation transformers, to pass DC power without running the risk of saturation of a high-μ core, thanks to DM current-induced flux cancellation. Practical common-mode chokes will exhibit some leakage inductance due to imperfections in the symmetry of the windings, or k < 1; thus L1 = (1 − k)L1 and L2 = (1 − k)L2. With L1 = L2, the total leakage inductance affecting the differential signal path is: LT = L1 + L2 = 2L1

1−k

4 71

Using Equation (4.66), while neglecting RC1, RC2 but inserting LT in series with the source and load impedance, reduces to: E S = jωLT I S + Z S + Z L + RC1 + RC2 ES ≈ Z S + Z L + jωLT

IS

IS 4 72

Even with low winding losses (RC1, RC2), small suppression of differential functional signal occurs. For k ≤ 0.9, for instance, suppression can be significant. Typical common-mode chokes exhibit k = 0.98, while for high-quality chokes, k may be as high as 0.999. Similar to the isolation transformer, parasitic capacitance limits the high-frequency performance of common-mode chokes, particularly due to parasitic capacitance which, at higher frequencies, shorts out the windings of the choke. In particular, “real-world” common-mode chokes will exhibit, in addition to wiring resistance, RWIRE and interwinding capacitance, CP (between turns of the same wire) and CWIRES, between the two wires, some leakage flux between windings and hence will exhibit some “leakage inductance,” LDM (Figure 4.134), hence cancellation will be incomplete. In fact, some common-mode chokes are intentionally designed to have significant leakage inductance, acting in series with the load and hence the leakage inductance also provides differential noise filtering.

4.5 Ground Loops

Also, like isolation transformers, physical size and cost are the main disadvantages of using common-mode chokes. Unlike the isolation transformer, on the other hand, a common-mode choke provides no physical isolation (which actually permits it to be used on DC lines as well). 4.5.5.3

CP LDM

LCM

RWIRE

K

Optocouplers and Optical Isolators

CWIRES

Another technique to prevent ground loops and minimize commonLCM LDM mode current flow is optical isolation. Optocoupler, also called RWIRE opto-isolators, photocouplers, or optical isolators are components that transfer electrical signals between two isolated circuits (I) by using light. Among the oldest and most commonly used isolation techniques are digCP ital isolators based on optical coupling principles. Light emitting diodes (LEDs) produce light signals when a voltage is Figure 4.134 Leakage inductance (LDM) in commonapplied across them. Optical isolation uses a LED along with a photo- mode chokes degrades the flux cancellation and detector device to transmit signals across an isolation barrier using light introduces some differential-mode suppression. as the method of data translation. A photo-detector receives the light transmitted by the LED and converts it back to the original signal. As observed in Figure 4.135, the optical isolator interrupts the direct metallic transmission path between two circuits completely. Ground noise voltage appears between the input LED and the output phototransistor terminals rather than across two input terminals.81 Optical isolators are best suited for cases where a large voltage potential exists between circuits. In particular, optical isolators are best suited for digital designs owing to their nonlinearity. Nonlinearity may introduce distortions in analog circuits, but in certain cases could be used in small-signal analog circuits. For low-level analog ( |Vt1| + VOD1

(a)

(b)

Figure 11.128 Differential signaling (vis-à-vis, TIA/EIA-644 LVDS). Source: Dave at ti / Wikipedia/ Public Domain.

driver (D) and receiver (R) devices, further adding to the misconception that the two are “floated” with respect to each other. As a result, the effects of the multiple connections to the reference structure are often overlooked. In most practical designs, however, these “signal ground” connections are also “stitched” to the signal reference structure (as mentioned with respect to Figure 11.128) and, voilà, the neglected multiple ground connection is very much present, which may result in “imbalance” between the two differential signal currents. Under such conditions, potential differences will most likely exist between the transmitter and receiver ground connections, which may result in interference when exceeding a level specified for the given interface. For instance, RS-485-compliant drivers and receivers are specified for operation with a common-mode range of −7 V to +12 V, while RS-422-compliant drivers are specified for operation with a common-mode range of over the common-mode range of −7 V to +7 V, but are specified regarding bus pin leakage over the common-mode range −10 V to +10 V [24]. Ethernet (IEEE 802.3), such as 10/100/1000BaseT communications (Figure 11.129), is not only differential but also a “balanced” data communications channel. An isolation-magnetics module is required by the IEEE standard at the link ends, which isolates the signal voltage. In this case, the driver and receiver are effectively isolated from each other (through the isolation transformer) and from the signal reference structure (through a center-tap R-C circuit), thus providing immunity from GPDs. Such a circuit is said to be “balanced” in the sense that the two wires are guaranteed to carry equal and opposite currents, exhibiting high CMR.

11.6.5.2 RS-422 and RS-485

Unlike common belief, laws of physics (i.e. the necessity for current return path) dictate that a solid physical return connection be present to ensure error-free communication between RS-422 and RS-485 drivers and receivers [24, 25]. When designing a remote data link channel such as RS-422 or RS-485, it would be reasonable to assume that large GPDs exist between the ends of the link, subsequently resulting in common-mode noise voltage, Vn, being superimposed on the transmitter output. The GPD

3

6

3

Data pair

6

CT RD–

P1 P4 P2 P3 P5 P6

GND

P8

TD+ CT TD– RD+

4

5

J1

TX+

J2

TX–

J3

RX+

J6

RX–

4

Data pair

5

J4,5 J7,8 1000pF/2KV

4×

75 Ω

Figure 11.129 Balanced Ethernet signaling over a twisted wire pair: (a) balanced Ethernet link and (b) schematic of the Ethernet magnetics module.

11.6 Grounding Considerations in Signal Interfaces

may be quite large to the extent that the receiver’s input common-mode range is exceeded, but even if the total superimposed signal is within the receiver’s input common-mode range, relying on the local earth ground as a reliable path for the return current may be questionable (Figure 11.130a). In many cases, the local signal round and the Protective Earth (PE) are directly connected by wire, chassis, or leakage for various reasons, such as lowest cost or simplest power supply design. Such direct connection is not recommended (Figure 11.130b). If a high-voltage GPD exists between remote grounds, during transients in particular, large ground loop currents may thus couple into the data lines in the form of common-mode noise. To allow for a direct connection of remote grounds, the RS-485 standard recommends the insertion of some (typically 100 Ω, 1/2W) resistance between logic and chassis ground to avoid excess ground-loop currents (Figure 11.130c). Although this approach reduces loop current, the mere existence of a large ground loop keeps the data link sensitive to noise generated somewhere else along the loop. Thus, a robust data link has not been established yet. A better approach for ensuring a robust RS-422/RS-485 data link channel over long distance, which also offers tolerance to GPDs up to several kilovolts, is attained through galvanic isolation of the signal and supply lines of a line transceiver from its

VCC1

Line NonNeutral isolated power supply 1 PE

VCC2

Rx

Tx ZT

ZT

Rx GND1

Tx GND2 Large ground potential difference (GPD)

No isolation Protective earth (PE) 1

Line Nonisolated Neutral power supply 2 PE

No isolation

No connection

Circuit GND 1

Circuit GND 2

Protective earth (PE) 2

Facility earthing infrastructure

(a) VCC1

Line NonNeutral isolated power supply 1 PE

VCC2

Rx

Tx ZT

ZT

Rx GND1

Tx GND2

No isolation

Protective earth (PE) 1

Circuit GND 1

Line Nonisolated Neutral power supply 2 PE

No isolation

Large ground loop current

Circuit GND 2

Protective earth (PE) 2

Facility earthing infrastructure

(b) Figure 11.130 Grounding pitfalls and their resolution in the design and implementation of RS-422 or RS-485 data link channels: (a) large ground potential difference (GPD) between transmitter and receiver, (b) loop current due to ground potential difference (GPD), (c) reduced loop current thanks to series 100 Ω resistances, yet still highly sensitive to induced noise due to ground potential difference (GPD), and (d) grounding configuration with local ground isolated from PE.

647

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11 Grounding in Wiring Circuits and Cable Shields

VCC1

VCC2

Line

Line

NonNeutral isolated power supply 1 PE

Nonisolated Neutral power supply 2 PE

Rx

Tx ZT

ZT

Rx GND1

Tx GND2

100 Ω

100 Ω

Protective earth (PE) 1

No isolation

Circuit GND 1

Circuit GND 2

Small ground loop current

No isolation

Protective earth (PE) 2

Facility earthing infrastructure

(c) Isolated supply

Isolated DC/ DC converter DC

VCC1

VCC2

Line Neutral Isolated power supply 1 PE

DC

Line

Isolated Neutral power supply 2 PE

Rx

Tx ZT

ZT

Rx GND1

Tx GND2

Isolation barrier

Isolated Circuit GND 2 GND 2 Protective earth (PE) 1

Circuit GND 1 and PE may be connected by Wire, chassis or through leakage

Circuit GND 1

Protective earth (PE) 2

Circuit GND 2 and PE may be connected by wire, chassis or through leakage

Facility earthing infrastructure

(d) Figure 11.130 (Continued)

local signal and supply sources. Supply isolators, such as isolated DC/DC (e.g. “Flyback”) converters combined with signal line isolators, such as digital capacitive isolators, prevent current flow between remote system grounds and preclude current loops. The non-isolated transceiver at the one end (left side in the image) provides the single-ground reference for the entire channel (Figure 11.130d). The same scheme may be applied to a “multidrop” configuration, where all transceivers but one connect to the bus via power and signal isolation.

11.6.5.3 Ethernet (Twisted-Pair Interface)

Unlike the galvanic interface provided by the RS-422/RS-485 channel, the Ethernet twisted-pair network interface consists of magnetics (with a 1 : 1 turns ratio for both the receive and the transmit transformers) [26]. Unlike the above, the Ethernet (e.g. 10/100/1000BaseT) interfaces are truly differential and are transformer-coupled on both ends. In this manner, no common ground reference connection is generally necessary as long as the common mode voltage remains below 1500 V, the isolation specification of the transformers, schematically illustrated in Figure 11.131.

11.6 Grounding Considerations in Signal Interfaces

10/100/1000 Mbps over twisted wire pair MAC

PHY

PHY Magnetics isolation

MAC

Magnetics isolation

Figure 11.131 Schematic twisted wire pair Ethernet interface.

Figure 11.132 Ethernet transmit and receive interface circuitry: (a) transmit interface circuitry and (b) receive interface circuitry.

Magnetics module Isolation transformer

Common-mode choke

10/100/1000 Mbps Over twisted wire pair

Tx(P) 50 Ω

PHY Tx(N)

10 nF

50 Ω

RJ-45 connector

Rx(Ref) Circuit ground

0.1 μF

Chassis ground

(a) Magnetics module Isolation transformer

Common-mode choke

10/100/1000 Mbps Over twisted wire pair

Rx(P) 50 Ω 10 nF

PHY Rx(N)

50 Ω

RJ-45 connector

Rx(Ref) 0.1 μF Circuit ground

100 Ω

Chassis ground

An alternate termination, if the split 50 Ω termination produces CM noise due to imbalance

(b)

The magnetics modules used on both transmit and receive ends of the Ethernet twisted pair interface provide the high level of isolation and true differential signaling. Figure 11.132 depicts a typical transmit (a) and receive (b) stage, both very similar in construction, differing only by the line termination (not forming part of the magnetics module). The magnetics module consists of the main (transformer) winding, a common-mode choke, and in some cases, a third winding known as an “auto-transformer” (not shown in Figure 11.132) on the output. The common-mode choke blocks common-mode interference current/voltage from reaching the line. Along with capacitor, C, between the center-tap of the transformer and chassis, it shunts common-mode energy away from the line. A “quiet ground” should be used for this purpose. In the receive magnetics, the common-mode choke may be placed on either the primary or secondary side of the main winding. Some vendors place the receive common-mode choke on the line-side (primary) of the main winding while others place it on the device side (secondary). Either location is acceptable. However, when using a magnetics module with the commonmode choke placed on the device side, the bypass capacitor should note be connected between the device-side center tap to ground as noise from the ground can couple through the capacitor into the center tap, bypassing the common-mode choke, resulting in EMI problems and counteracting the isolation of the transformer and common-mode choke. The auto-transformer (when present) provides a line-side center tap for further sinking of common mode energy. This center tap should be referenced to chassis ground.

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11 Grounding in Wiring Circuits and Cable Shields

The Least You Need to Know

• • ••

Distinction should be made between “differential” and “balanced” signaling. These terms are often erroneously considered interchangeable. Inasmuch as a data channel may be considered “differential,” thanks to data transmission across two complementary lines, such interfaces as RS-422, RS-485, LVDS (RS-644), etc., are not truly “floating” and are not isolated from the ground reference structure. Careful grounding design and consideration should be paid to such non-isolated interconnects. Transformer-coupled interconnects, such as Ethernet, on the other hand, are truly isolated and balanced, and exhibit high immunity to common-mode interference.

11.6.6

Effect of Interface Grounding Scheme on Magnetic Interference Susceptibility

An interesting comparison of magnetic interference susceptibility of cable-connected circuitry for various interfacing circuits is shown in Figure 11.133. The evaluation was performed at a frequency of 100 kHz, considered as the boundary between LF and HF, with measurement parameters based on the type of cable configuration used, the grounding arrangement of the load, and manner of grounding of the cable shield. All circuits were placed 1 in. (2.54 cm) above the signal reference structure [5, 18]. The frequency of 100 kHz was well beyond the intrinsic shield cutoff frequency. The arrangement in Figure 11.133a offers virtually no magnetic shielding and is used as reference, hence assigned 0 dB of rejection. The circuit in Figure 11.133b is not significantly better. As in the previous case and for the same reasons, the shield provides no attenuation of the incident magnetic fields. As the signal circuit is grounded at both ends, it appears to be unbalanced at 100 kHz, resulting in poor rejection of magnetic field pickup. Although twisting is broadly considered advantageous for reducing magnetic field coupling,87 that is true only for balanced circuits. Magnetic fields are coupled into the large loop formed by the twisted pair and the signal reference resulting in the development of noise voltage across the unbalanced load. The circuit in Figure 11.133c offers some magnetic field suppression, since the field is above the intrinsic cutoff frequency of the shield.88 If the circuit were grounded at one end only rather than at both ends, converting it into a balanced circuit, the suppression of magnetic fields would have been even higher (see Figure 11.133f ).

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

Figure 11.133 Relative susceptibility of circuits to magnetic interference at F = 100 kHz (Note relative suppression for each arrangement): (a) 0 dB (reference), (b) 2 dB, (c) 5 dB, (d) 49 dB (twisted 6 turns/foot), (e) 57 dB, (f ) 64 dB (preferred for HF), (g) 64 dB, (h) 71 dB, and (i) 79 dB (twisted 18 turns/foot). 87 The effect produced by twisting of cables and the effect of grounding on twisted cables is discussed earlier in this chapter. 88 Description of the shield cutoff phenomenon is discussed earlier in this chapter.

11.7 Grounding of Transducers and Measurement Instrumentation Systems

The circuit in Figure 11.133d is an UTP. As a balanced circuit, it could be anticipated that interference rejection would be higher than 49 dB. That would be correct as far as only magnetic fields are concerned. However, at 100 kHz, the frequency of this example, some common-mode (CM) interference current as a result of the electric field associated with the magnetic field now shows up, flowing through parasitic capacitance to the signal reference structure. This capacitance somewhat degrades the circuit, which is assumed to be “floated” at its right-hand side and thus balanced. If a properly terminated shield were present such as in case (f ), E-field coupling would be alleviated by the shield with greater RF suppression. A significant improvement in magnetic field suppression is achieved in the circuit shown in Figure 11.133e, representing a balanced coaxial arrangement. The pick-up loop created by the inner conductor and the shield acting as a return conductor is reduced and the ground loop that could potentially defeat the shield performance is nonexistent. In an ideal coaxial cable, this arrangement could yield a very high magnetic rejection, but, in practice, coaxial cables exhibit some eccentricity, resulting in a small, but nonzero effective pick-up loop compared to a standard (6 twists per foot UTP cable). Similar to case (d), the performance of this scheme is still limited by E-field (CM) interaction with the cable. The best performance is achieved using the circuit in Figure 11.133f. The twisted, balanced circuit offers high magnetic field rejection. The shield offers high electric field suppression, due to grounding at both ends. As the shield constitutes a separate circuit from the inner signal wiring, they share one common grounding point only. The “ground loop” formed by the shield has negligible effect on the inner circuit. This circuit is therefore preferred for higher frequencies. Figure 11.133g further emphasizes the similarity between the STP cable (case (g)) and the balanced coaxial (case (e)) arrangements. The fact that the performance of case (g) is superior to that of case (e) indicates that the specific coaxial cable used presented a larger pick-up area compared to the STP cable. This may not necessarily be valid in certain applications. Figure 11.133h offers a slight enhancement compared to the previous case (g). That constitutes an amalgamation of cases (e) and (g). The circuit in Figure 11.133i represents an improvement over case (d), due to the higher twisting rate per unit length, resulting in higher rejection of magnetic fields. Among other results, the comparison of these arrangements illustrates the disadvantage of returning any load current through the signal reference structure89 and the advantages gained using tightly twisted leads. For low-level signals and low-impedance circuits where the distance between the interfacing input connector and the actual circuit input is small, i.e. up to 5 cm (2 in.), the use of a twisted pair cable alone may prove adequate. For long runs, the use of STP cables becomes mandatory, both in unbalanced and balanced interfaces. Care should be given to ensure the preservation of circuit balancing utilizing a proper grounding scheme of the circuit and shield, or both. Single-point shield grounding is applied for short runs and multipoint grounding for long runs. Particular attention is required when a STP is part of a cable routed through a connector if isolation of the twisted conductors and the cable shield from the connector’s (grounded) shell is required. High-level signals will, in general, not be bothered by a circuits’ susceptibility to external incident fields. Rather, they may be a source of emissions and interference coupling to sensitive, lower-level signal lines. For this reason, and dependent on other characteristics of the signal, either a twisted-pair or a shielded lead should be used. Multiple shielding may be required if the signal contains sufficiently high level of induced RF current. Grounding of the shield should be applied at both ends to prevent electric field radiation from the cable.

The Least You Need to Know

•• • • •

Balanced lines, e.g. TSP are preferred for LF or broadband signals containing a major LF spectral content signal interfacing. Unbalanced (single-ended) shielded lines should be avoided in LF circuits: The shield forms part of the circuit path of singleended lines leading to noise coupling into the circuit. At higher frequencies grounding, both ends of the shield and circuit is required for acceptable EMC performance. The shield represents “isolated” current paths for the signal return current (inner surface) and EMI current (outer surface). A double-shield arrangement can be used in sensitive LF high impedance circuits with each shield being single-point grounded at an opposing end, taking advantage of the inter-shield capacitance for effective HF shielding. Coaxial and similar single-ended interfaces are effective at high frequencies but should be avoided at low frequencies.

11.7

Grounding of Transducers and Measurement Instrumentation Systems

An especially challenging situation related to grounding in signal interfaces and wiring is concerned with high-resolution measurement and data acquisition systems. Such systems consist of transducers, measurement instrumentation, and the associated wiring and interconnect. 89 Note, however, that at higher frequencies depending on the intrinsic shield and cable cutoff frequency, the circuit wiring may also utilize multipoint grounding, as the high-frequency return current tends to flow through the return wire and not the reference structure, in an attempt to minimize the loop inductance. See Chapter 2 on the “Path of Least Inductance” principle.

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11 Grounding in Wiring Circuits and Cable Shields

Many, if not most, transducers and measurement instrumentation systems are concerned with detection and quantification of physical phenomena (or changes in them), requiring periods of observation ranging from a few milliseconds to several minutes or longer. Owing to the relatively slow nature of such events, the fundamental frequency of the (typically analog) transducer’s outputs may range from DC to a few hundred Hertz. Often, extremely low signals may be expected and should be detected, while high measurement accuracy is desirable. Sensitive, high-resolution measurement apparatus is often assumed to adequately address this need. However, extraneous interference voltages resulting from such sources as power distribution systems, electromechanical circuits, and atmospheric noise may compromise measurement accuracy. The spectral content of interference from such sources is typically concentrated within the lower frequency region, typically overlapping the spectrum of the measured physical phenomena themselves. Improper grounding connection between a device under test (DUT) and the measurement apparatus often increases interference coupling into the instrumentation, producing measurement errors. Particular techniques are generally required in order to keep the interference voltages or currents from obscuring transducer outputs and producing measurement errors. This section addresses grounding considerations in measurements transducers and instrumentation systems.

11.7.1

Measurement Accuracy Concerns

Consider the circuit shown in Figure 11.134, where measurement using grounded apparatus is illustrated. ET represents the measured signal at the output of the measurement transducer, ZH and ZL represent the impedance of the “high” and “low” leads of the wiring, and ZM symbolizes the input impedance of the measurement apparatus itself. The transducer and measurement apparatus are referenced to their respective local grounding points, GNDT and GNDM, respectively. As long as no voltage potential difference exists between the signal reference points GNDT and GNDM, no current flows through the impedance of the return lead, ZL. However, if a potential difference does exist between GNDT and GNDM, interference common-mode (CM) current splits between ZL and ZH in series with ZM. Typically, the input impedance of most measurement apparatus is high (ZH ZM) and ZH and ZM appear in parallel with ZL; therefore, most of the ground common-mode voltage, ECM, also appears across the measurement apparatus terminals input impedance ZM (Figure 11.135), resulting in measurement errors. 11.7.1.1 Floating Measurements

A common solution to the problem shown earlier is to “float” the measurement with respect to the reference ground. An ideal floating measurement would be insensitive to the ground-generated common-mode interference and would only measure the differential mode signal appearing between the output terminals of the transducer. Three situations of common practical floating measurements are now illustrated in Figure 11.136. In the first case (Figure 11.136a), a measurement apparatus is shown to be connected to the same reference ground as the device being measured. However, the measured voltage is not directly referenced to that ground. Rather, the measurement takes place across the upper resistor, RU, using the voltage across the bottom resistor, RB, as reference. The voltage across RB thus constitutes the difference between the two reference potentials, the common-mode voltage. If the measurement apparatus exhibits sufficient CMR, accurate measurements across RU will be achieved. But if its input circuitry is similar to that shown in Figure 11.135, RB will be effectively shorted out (observe the equivalence between RB to ZL in Figure 11.135). Large currents will, consequently, flow through the ground circuits and the entire transducer output voltage, ET, will appear across RU. The measured voltage will be higher than the intended value. The situation in Figure 11.136b may occur when several instruments are connected to the same grounding system. Due to the flow of stray currents through the finite impedance of the ground structure, a voltage potential difference exists between Grounded measurement apparatus ZH High ET

ZM ZL

Transducer output

Ground

GNDT Source ground

GNDM Measurement apparatus ground

Figure 11.134 Measurements using a grounded apparatus.

11.7 Grounding of Transducers and Measurement Instrumentation Systems

Figure 11.135 Ground-generated interference in measurements using a grounded apparatus.

Grounded measurement apparatus ZH

High

ET

ZM ZL

Transducer output

Ground

ECM

GNDT

Source ground

Figure 11.136 Examples of floated measurements: (a) measurement of voltage reference above common ground potential, (b) measurement in the presence of common ground interference currents, and (c) bridge measurements.

~ECM

GNDM

Ground generated CM noise

Measurement apparatus ground

Grounded measurement apparatus

EDM

RU

ET Transducer output

+–

ECM

RB

GNDT Source ground

GNDM Measurement apparatus ground

(a) Other equipment connected to the same ground

EDM RU

Grounded measurement apparatus

ET Transducer output

+–

ECM

RB

Source ECM ground GNDM

GNDT

Measurement apparatus ground

(b)

RU2

RU1

Source ground

EDM RB2

Grounded measurement apparatus

+– RB1

ECM

GNDT

(c)

GNDM Measurement apparatus ground

653

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11 Grounding in Wiring Circuits and Cable Shields

different points along the line. Somewhere in the system, the measurement apparatus is grounded to the common grounding system, resulting in common-mode interference across its input terminals. The bridge circuit shown in Figure 11.136c is commonly used in transducer measurements when high resolution is required. Since both sides of the bridge are above ground potential, common-mode noise will be present. If the measurement apparatus does not exhibit high CMR, severe measurement errors will result. In conclusion, none of the techniques illustrated in Figure 11.136 can be carried out using a grounded measurement apparatus, since all require high CMR in order to provide floated measurements. Floated instrumentation is necessary for that purpose.

11.7.1.2 Floating Measurement Apparatus

Floating measurement apparatus can be made by including a shield between the inner circuits and the apparatus enclosure or chassis (Figure 11.137). The input circuit now consists of three terminals, namely “high,” “low,” and “ground,” representing the “high” terminal in Figure 11.135, the internal (floated) shield, and the apparatus instrument ground connection, respectively. Also shown are the isolation impedances, ZHG and ZLG from the high and low terminals to the instrument ground, respectively. In a perfectly balanced circuit (i.e. ZH = ZL and ZHG = ZLG) where ZHG and ZLG are also much larger than ZH and ZL, high CMR is achieved and no measurement errors are observed, i.e. no differential voltage offset exists across the input impedance, ZM. In practice, however, ZHG ZLG thus ZHG actually amounts to an open circuit and the circuit in Figure 11.139 transforms to that shown in Figure 11.138. Common-mode currents now flow through the two parallel paths developing a voltage across Floated measurement apparatus ZH

High

ET Transducer output

Figure 11.137 Measurement using an ideal floating apparatus.

ZM ZL

Low

Ground

ZLG

ZHG

ECM Ground generated CM noise Measurement apparatus ground

Source ground

Figure 11.138 apparatus.

Floated measurement apparatus ZH

High

ET Transducer output

ZM ZL

Low

Ground

ZLG

ZHG

ECM Ground generated CM noise Source ground

Measurement apparatus ground

Measurement using a practical floating

11.7 Grounding of Transducers and Measurement Instrumentation Systems

ZL, which results in an offset voltage across ZH and ZM, Therefore, CMR of the apparatus depends entirely on the relationship between ZL and ZLG. When ZL ZLG errors are small and ZLG represents the extent of isolation between the inner shield and the chassis of the measurement apparatus. ZLG is typically largest at DC, but due to capacitance, it drops gradually with frequency. CMR anywhere between 60 and 120 dB can typically be achieved at lower frequencies using this setup. However, when higher resolution or sensitivity is required, guarded measurement apparatus are essential. 11.7.1.3

Guarded measurement apparatus ZH

ET

ZL

Transducer output

ICM

High ZM Low Guard

ZLG1 ZHG1 ZLG2

ZHG2

Guarded Measurement Apparatus

ECM Guarded measurement apparatus includes an additional Ground generated shield between its low and ground terminals, effectively CM noise increasing the leakage impedance between them. The addiMeasurement apparatus Source ground tional shield is denoted guard and it may be connected to a ground circuit or device under test through a dedicated “guard” ter(a) minal. This additional shield effectively divides the low-toGuarded measurement ground impedance into two series impedances, ZLG1 and apparatus ZLG2 (Figure 11.139), increasing resistance and reducing overall capacitance. Consequently, a somewhat higher ZH High CMR is obtained, but the greatest advantage of this scheme is attained when a proper connection is made to the measured device or circuit. ET ZM ZL Figure 11.139 illustrates how the guard works. In Transducer Low output Figure 11.139a, the guard terminal is left disconnected, resulting in a situation similar to that of a floating measureZLG1 ZHG1 Guard ment apparatus, except that larger low-to-ground isolation ICM impedance is present. Ground-generated common-mode ZHG2 ZLG2 current, ICM, now flows through the two parallel paths, again resulting in interference voltage across ZL, subsequently proECM ducing interference across ZM, the measurement apparatus Ground generated input impedance. Similar to the floated case, measurement CM noise error will be small as long as ZLG1 + ZG2 ZL. At DC, the Measurement apparatus Source ground guard significantly increases the leakage impedance but at ground AC, only a small increase is observed. As a result, CMR is (b) considerably improved at DC but only slightly at higher frequencies. Figure 11.139 Measurement using a guarded apparatus: When properly connected, however (Figure 11.139b), the (a) improper guard connection: common-mode interference guard provides considerable improvement. It shunts the produced and (b) proper guard connection: common-mode common-mode current away from the two current paths interference shunted from source impedance. consisting of ZH and ZL, practically eliminating them from the common-mode circuit. As virtually no common-mode current flows now through ZL, almost no error can be produced. Furthermore, since the low and guard terminals are almost at the same potential, the voltages on the top and bottom of ZLG1 are also almost equal, hence the voltage difference across ZLG1 is maintained very small, yielding higher CMR across a wider frequency band.

11.7.2

Guard Shields and Instrumentation Wiring Shield Interconnection

One of the most common applications of guard shields is associated with instrumentation wiring circuits. Starting from Figure 11.140b and representing the measurement apparatus by an instrumentation amplifier, yield the situation shown in Figure 11.140. Now the transducer is connected to the instrumentation amplifier through a shielded cable, which, in turn, is connected to the guard shield of the amplifier, following the reasoning in the previous section and Figure 11.140b. Note that the amplifier common is connected to the guard shield which remains ungrounded (or “floated”) to the reference structure, that is, ZLG2 ∞, represented as capacitance, CG [3]. This scheme suffers from the drawback that at higher frequencies, capacitance between the guard shield to the local reference structure (ground) contradicts the effect of the guard and cable shields. Current can now flow through the cable shield as

655

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11 Grounding in Wiring Circuits and Cable Shields

Instrumentation amplifier VAA

ZH

ET

ZM

ZL

Transducer output

Figure 11.140 Guard shield grounded through the cable shield.

ZLG1 ZHG1 CG

GND

Guard shield

ECM Ground generated CM noise Instrumentation aplifier local ground

Source ground

Instrumentation amplifier VAA

ZH

ET

ZM

ZL

Transducer output

Figure 11.141 Maintaining guard shield integrity with a grounded case shield.

ZLG1 ZHG1 GND Guard shield Case shield ECM Ground generated CM noise

Source ground

Instrumentation aplifier local ground

well as through the “low” wire to the reference ground through the guard shield, making the guard shield useless at all but the very low frequencies. A second shield, totally enclosing the guard shield and amplifier, however, rectifies this problem (Figure 11.141). The cable shield is connected to the guard shield but does not have any electrical connection with the case shield. The case shield, in turn, is now grounded to the ground reference structure satisfying functional and safety requirements with no violation of the guard integrity. Note that in this case too, the cable shield remains floated from the ground reference at the amplifier end. This one-end shield termination may result in compromised performance of the shield at higher frequencies. In this case, frequency-selective shield grounding, or better still, a second cable shield grounded both ends enclosing the inner guarded shield, may be required (Figure 11.142).

11.7.3

Grounding of Wiring Shields in Analog Data Acquisition Systems

Analog signals such as those detected and processed in measurement data acquisition systems are primarily lower frequency in nature, thus single-point grounding architecture should be implemented. The signal circuit must be balanced with the signal

11.7 Grounding of Transducers and Measurement Instrumentation Systems

Figure 11.142 Solutions for maintaining guard shield integrity at higher frequencies: (a) frequency-selective cable shield grounding and (b) independently grounded dual cable shields.

ZH

Inner (guard) shield

ET Transducer output

Outer shield

ZL

Instrumentation amplifier VAA

ZM ZLG1 ZHG1 GND Guard shield Case shield

ECM Ground generated CM noise Instrumentation aplifier local ground

Source ground

(a)

ZH

ET Transducer output

Outer shield Inner (guard) shield

ZL

Instrumentation amplifier VAA

ZM ZLG1 ZHG1 GND Guard shield Case shield

ECM Ground generated CM noise Source ground

(b)

Instrumentation aplifier local ground

return conductor grounded at one end only or totally floated. Similarly, individual cable shields used over signal lines should normally be grounded at one end only, at the signal grounding reference connection point [7]. This grounding scheme is particularly effective when high-impedance lower frequency interference coupling dominates.90 When high-accuracy measurements are required, unique cable shield termination or grounding schemes are commonly applied with a distinction made between measurement equipment guard and enclosure shields. The discussion is now further extended to consider several particular cases related to transducer types [7, 17]. Note that regardless of the type of transducer used, whether grounded or floated, the grounding schemes of the wiring and its associated shield are adequate for lower frequencies only, but ineffective against higher frequency EMI interactions. Following the same reasoning in the previous section, protection against higher frequency interference coupling (without violation of the guard shield performance) can be achieved by using multiple shields with the outer shield utilizing both-end shield grounding and the inner shield grounded as described herein. Alternatively, frequency-selective cable shield grounding may be utilized (Figure 11.142). 90 When higher frequency interference is present, single-ended shield grounding architecture may be ineffective, when length of the cable, ℓ > λ/10, where λ is wavelength of the interference signal. Multiple, isolated shields or selective shield grounding should be considered in this case.

657

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11 Grounding in Wiring Circuits and Cable Shields

11.7.3.1 Grounded Transducers

A bonded (grounded) transducer, such as a thermocouple, is a single-ended data amplifier, the output of which drives data acquisition systems or recording devices. Figure 11.14391 illustrates implementation of several key aspects in single-ended transducer circuits. In particular, the shield surrounding the transducer signal leads is grounded at the same point as the transducer to ensure that the shield and signal return wire are at virtually the same (LF) voltage potential. When the bonded transducer (e.g. thermocouple) is connected to the input of an isolated differential amplifier (Figure 11.144), the shield of the input cable should be connected to the amplifier internal guard shield in order to maintain continuity of the signal cable shield within the amplifier. The grounding reference bus interconnects the data acquisition system signal reference and structural chassis ground of the test facility or platform. This ground reference bus is required in any instrumentation system including isolated differential amplifiers in order to provide reference for the signal circuitry within the data acquisition system. This common reference precludes high-voltage electrical safety hazards, and minimizes high common-mode voltage potentials that may otherwise exist between the amplifier input and output, if the data acquisition system were to be referenced to a separate earth or facility

Figure 11.143 Grounding scheme for a grounded transducer and single-ended amplifier.

Transducer’s reference Shield connected to transducer ground only

VAA

Grounded transducer

Single-ended amplifier Output to data acquisition system Shield floating (ungrounded) at amplifier input

Signal reference structure

Signal circuit common

Transducer’s reference Shield connected to transducer ground only

Differential amplifier

VAA

Guard shields Output to data acquisition system

Data acquisition system

Grounded transducer

Cable shield grounded to amplifier guard shield at amplifier input Signal reference structure

Amplifier common

System ground structure

Ground (reference) bus

Signal reference structure

Figure 11.144 Grounding scheme for a grounded transducer with an isolated differential amplifier.

91 Note that in all the cases discussed below, the wire pair should be twisted rather than being routed simply as a wire pair, for better control of magnetic EMI coupling. This twisting is omitted from the figures below for the purpose of clarity.

11.7 Grounding of Transducers and Measurement Instrumentation Systems

Large (100 kΩ to 1 MΩ) resistors

Balanced DC excitation bridge transducer

VAA

Single-ended amplifier Output to data acquisition system Shield floating (ungrounded) at amplifier input

Signal reference structure

Signal circuit common

Figure 11.145 Grounding scheme for a bridge transducer with a single-ended amplifier.

structural ground. Such high-voltage potential difference could result in damage to the data acquisition system if it exceeds the amplifier’s input to output voltage difference rating. The enclosure of the amplifier and its output shield are connected to the data acquisition system (or load end) ground. Grounded bridge transducers (Figure 11.145) introduce additional complexity, as they required a DC excitation voltage source. Such transducers should be excited with a balanced DC source as shown in Figure 11.145, thus the entire bridge is balanced with respect to ground and the unbalanced impedance presented to single-ended amplifier input will be due only to the leg resistances in the bridge. Although a ground loop does still exist, its consequences are greatly reduced when a balanced excitation supply is utilized [7]. Whenever possible, it is best to use isolated differential amplifiers with grounded bridge transducers in the manner illustrated in Figure 11.146, rather than single-ended amplifiers with grounded bridge transducers. In this configuration, both the transducer and the amplifier can be grounded without degrading system performance. 11.7.3.2

Ungrounded (“Floated”) Transducers

Ungrounded (“floated”) transducers remove the difficulty of detrimental ground loops, which may severely degrade highaccuracy measurements. Grounding techniques recommended for ungrounded transducers are presented in Figure 11.147. The metallic enclosure of the transducer is now connected to the cable shield; yet, both enclosure and shield are floated at the transducer end with respect to the reference structure. The shield of the input cable to the single-ended amplifier should Large (100 kΩ to 1 MΩ) resistors

Balanced DC excitation bridge transducer Differential amplifier

Signal reference structure

Cable shield grounded to amplifier guard shield at amplifier input

VAA

Guard shields Output to data acquisition system

Amplifier common

Data acquisition system

System ground structure

Ground (reference) bus Signal reference structure

Figure 11.146 Grounding scheme for a bridge transducer with an isolated differential amplifier.

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11 Grounding in Wiring Circuits and Cable Shields

Transducer’s reference Data acquisition system

Transducer enclosure

VAA

Floated transducer Single-ended amplifier Output to data acquisition system

Cable shield terminated to ungrounded transducer enclosure

Signal circuit common

Signal reference structure

Single system-wide ground Signal reference structure

(a) Transducer’s reference Guard shields

Transducer enclosure

VAA

Data acquisition system

Floated transducer

Output to data acquisition system

Cable shield terminated to ungrounded transducer enclosure Signal reference structure

Signal circuit common Ground (reference) bus

(b) Figure 11.147

Single system-wide ground

Signal reference structure

Grounding scheme for an ungrounded (“floated”) transducer: (a) single-ended amplifier and (b) isolated differential amplifier.

be grounded at the load which typically exhibits high input impedance as shown in Figure 11.147a.92 The amplifier circuit common should also be grounded at the load [7, 18]. Here too, isolated differential amplifiers exhibit superior performance compared to single-ended ones. When used, the grounding scheme of such circuits and their respective cable shields shown in Figure 11.147b should be considered. Similar to the single-ended circuit, a single common system-wide ground reference connection point is provided for all cable shields. The shield of the transducer-to-amplifier cable should be grounded at the transducer end, while at the input to the amplifier, the shield of the input cable should be connected to the isolated amplifier guard shield. Note that when certain non-isolated differential amplifiers are used, a transducer ground bus connection may be required for ensuring proper amplifier performance. In such cases, the instructions provided by the amplifier manufacturer should be consulted.

92 Note that the circuit grounding to the reference structure is accomplished at the typically high-input impedance load, providing higher immunity to stray electrostatic and lower frequency predominantly high-impedance EM fields.

References

11.7.3.3

Transducer Amplifiers

The transducer amplifier and its grounding scheme in particular can have considerable effect on overall measurement results, especially in cases where grounded transducers are used. Single-ended amplifiers should not be used, therefore, with grounded transducers in order to preclude detrimental channel-to-channel ground loops. Single-ended amplifiers should not be used with grounded bridge transducers, in particular. Typically, bridge transducers are used for achieving high-accuracy measurements. Single-ended amplifiers will short circuit one leg of the bridge, severely corrupting the measurements’ quality thus defeating the benefits of the bridge. Transducer amplifiers with guard shields provide enhanced performance with respect to simple single-ended amplifiers. When used, connect the amplifier’s output guard shield to data system ground bus, in order to minimize the DC voltage potential difference across the input and output guard terminals, which could otherwise inflict severe damage the amplifier. Finally, if a permanent unavoidable instrumentation ground exists at test area as well as at the data acquisition system, isolated differential amplifiers should be used to break resultant ground loops.

The Least You Need to Know

• • •• • •

Measurements’ accuracy can be significantly compromised by improper grounding of the measurement instrumentation (i.e. transducers, amplifiers, and data acquisition systems) and its associated wiring and wire shields. Guarded measurement apparatus exhibit superior CMR compared to simple floated measurements apparatus, thus providing higher measurement accuracy. When properly connected, the guard shield shunts common-mode interference from the source impedance. The guard and the “low” input signal terminal should be connected such that they are at the same voltage potential; no common-mode current should flow through the low source impedance or, in general, through any impedance affecting the input signal voltage. Single-ended instrumentation amplifiers and grounded (particularly grounded bridge) transducers should never be used jointly. When grounded transducers and data acquisition systems are used, isolated differential amplifiers, preferably with guard shields, should be utilized. Grounding of interconnecting cable shields should be accomplished so that lower frequency ground loops are precluded. Measurement circuits comprising of ungrounded transducers and isolated differential amplifiers exhibit superior performance; yet, the level of isolation and voltage withstand exhibited by the guarded amplifier and the grounding scheme of the amplifier’s input and output wiring and its associated shields must still be carefully considered.

References 1 Tsaliovich, A. (2001). Electromagnetic Shielding Handbook for Wired and Wireless EMC Applications. Boston: Kluwer Academic 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Publishers. Tsaliovich, A. (1995). Cable Shielding for Electromagnetic Compatibility. New York: Van Nostrand Reinhold. Ott, H.W. (2009). Electromagnetic Compatibility Engineering. New York: John Wiley & Sons Inc. Hartal, O. (1994). Electromagnetic Compatibility by Design. West Conshohocken, PA: R&B Enterprises. NAVSEA OD 30393 (2001). Design Principles and Practices for Controlling Hazards of Electromagnetic Radiation to Ordnance (HERO Design Guide), Second Revision. US Naval Sea Systems Command. White, D. and Mardiguian, M. (1988). A Handbook Series on Electromagnetic Interference and Compatibility, Volume 3, Electromagnetic Shielding. Gainesville, VA: Interference Control Technologies, Inc. Mardiguian, M. (1988). A Handbook Series on Electromagnetic Interference and Compatibility, Volume 2, Grounding and Bonding. Gainesville, VA: Interference Control Technologies, Inc. Feynman, R.P., Leighton, R.B., and Sands, M. (1975). The Feynman Lectures on Physics, Volume II. Reading, MA: Addison-Wesley. Paul, C.R. (1992). Introduction to Electromagnetic Compatibility. New York: Wiley. Vance, E.F. (1978). Coupling to Shielded Cables. New York: Wiley-Interscience. Paul, C.R. (2010). Inductance: Loop and Partial. New York: Wiley-IEEE Press. Weston, D. (2001). Electromagnetic Compatibility, Principles and Applications, 2e. Boca Raton, USA: CRC Press. Martin, A.R. and Emert, S.E. (1979). Shielding effectiveness of long cables. Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (EMC), San Diego, USA. Casey, K.F. and Vance, E.F. (1978). EMP coupling through cable shields. IEEE Transactions on Antennas and Propagation AP-26 (1): 100–106. Johns, D. and DeRoy, P. (2013). Simulating crosstalk and EMI in cables. Signal Integrity Journal, https://www. signalintegrityjournal.com/articles/53-simulating-crosstalk-and-emi-in-cables. MIL-HDBK-1857 (1998). Department of Defense Handbook, Grounding, Bonding and Shielding Design Practices. Washington, DC: U.S. Government Printing Office.

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17 MIL-HDBK-419A (1987). Military Handbook, Grounding, Bonding, and Shielding for Electronic Equipments and Facilities.

Washington, DC: U.S. Government Printing Office. 18 Department of the Navy, Naval Air Systems Command, NAVAIR AD 1115 (1988). Electromagnetic Compatibility Design Guide for

Avionics and Related Ground Support Equipment, 3e. US Department of the Navy, Naval Air Systems Command. 19 Recht, E. and Bar-Natan, V. (2003). Methodology for EMC cable design. Proceedings of the 2003 IEEE International Symposium on

Electromagnetic Compatibility. EMC ’03, Istanbul, Turkey (11–16 May 2003). 20 MIL-STD-464D (2020). Department of Defense Interface Standard, Electromagnetic Environmental Effects Requirements for Systems.

Washington, DC: U.S. Government Printing Office. 21 Department of the Air Force, Air Force System Command (1991). Design Handbook 1-4, Electromagnetic Compatibility, 4e,

Revision 1. US Department of the Air Force, Air Force System Command. 22 Campione, S., Basilio, L.I., Warne, L.K. et al. (2016). Shielding effectiveness of multiple-shield cables with arbitrary terminations

via transmission line analysis. Progress in Electromagnetics Research C 65: 93–102. 23 White, D. (1988). EMC Methodology and Procedures. Gainesville, VA: Interference Control Technologies, Inc. 24 Texas Instruments Application Report SLLA070D (2002). RS-422 and RS-485 standards overview and system configurations.

Revised May 2010. 25 Texas Instruments Application Report SLLA272B (2008). The RS-485 design guide. Revised May 2008. 26 Intel (2001). LXT970 Fast Ethernet Transceiver Layout and Design Guide. Application Note. 27 Shelkunoff, S.A. (1934). The electromagnetic theory of coaxial transmission lines and cylindrical shields. The Bell System Technical

Journal 13: 532–579. 28 Martin, A. (2014). In Compliance Magazine, In Compliance, 29–35. 29 Hartal, O. (1991). Electromagnetic Compatibility by Design. R&B Enterprises Publications.

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12 Grounding of Terminal Protection Devices 12.1

Filtering and Transient-Voltage Suppression – Complementary Techniques to Shielding

Electrical and electronic equipment cannot always be protected from the electromagnetic environment (EME) by shielding alone. Although shielding prevents both entry and exit of radiated EMI, undesired conducted energy can still couple into the system through power, signal, control, and other wires penetrating the shielded enclosure of the equipment and compromising its electromagnetic shielding integrity. This coupled energy can, thus, degrade equipment performance or even result in malfunction. Filtering and transient-suppression devices installed at the point of entry of cables into the shielded enclosure minimize EMI. Terminal protection devices (TPDs) such as a variety of EMI filters and transient-voltage surge suppression devices (TVSS) are commonly used to suppress undesired conducted electrical energy to tolerable levels by shunting, bypassing, absorbing, or reflecting the interference energy. The effectiveness of filtering and transient suppression is dependent on proper implementation of grounding and bonding, particularly for counteracting common-mode interference phenomena. Since many references are available on the design of filter and suppression circuits [1–4], this chapter will provide only a brief overview of filters and transient suppressors but will focus on the role of proper grounding for accomplishing their desired performance.

12.2

Types of Conducted EMI

In order to properly design filters, it is important to understand the different types of conducted noise. The first type, known as differential-mode (DM) noise, propagates out on the one conductor (e.g. wire or PCB trace) and returns on another. EMI generated by switching-current waveforms in power supplies is typically DM and its amplitudes are usually minimal above a few megahertz. This is because the line-to-line and line-to-ground capacitance inherent in the system, as well as wiring inductance, tend to filter out this type of noise. The other type of conducted noise, known as common-mode (CM), travels in the same direction on both (or all, in the case of multiple-phase power lines, for instance) wires and returns through the chassis or reference structure. In power and signal systems that have a single reference to ground or single-point ground, CM noise is capacitively coupled to the reference structure. Because of this capacitive coupling, CM noise is generally dominant at higher frequencies [2].1 Figure 12.1 illustrates examples of DM and CM noise. Understanding and distinguishing between these modes of conducted interference is important as it results in different design approaches for mitigating each of these two types of noise.

12.3

Overview of Filtering and Transient-Voltage Suppression

12.3.1

Fundamental EMI Filter Devices and Circuits

The purpose of an EMI filter is to prevent the propagation of undesired conducted electromagnetic energy. A filter absorbs noise energy through the use of lossy elements such as resistors and ferrite components, or reflects the noise energy back to the source through the use of reactive elements.

1 Fundamentals of common-mode (CM) and differential-mode (DM) signals were discussed in Chapter 2. Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

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12 Grounding of Terminal Protection Devices

Noise current

Noise current

Load

Power source

Load

Power source

Parasitic capacitance

DM noise source in load

CM noise source in load

(a)

(b)

Figure 12.1 Differential-mode (DM) and common-mode (CM) noise propagation (example for power lines’ conducted noise). (a) Differentialmode (DM). (b) Common-mode (CM).

ZS ES

EI

EL1 ZL

Filter

(a) ZS ES

EI

EL2 ZL

Filter

(b) Figure 12.2

Definition of a filter insertion loss. (a) Filter inserted in circuit. (b) Filter absent from circuit.

An electrical filter can be defined as a two-port network of lumped or distributed passive elements consisting of capacitors, inductors, and, occasionally, resisters or their equivalent, or any combination thereof. Filter networks are designed to attenuate signals at certain frequencies while permitting energy at other frequencies to pass through unchanged. The attenuation (or, more accurately, rejection) may vary in the stop band and is usually least near the cutoff frequency, the frequency at which a 3 dB insertion loss is obtained, increasing to higher values at frequencies considerably removed from the cutoff frequency. The characteristic of a filter to pass or suppress signals is called insertion loss, IL, defined as (see Figure 12.2) IL f = 20 log

E L2 f E L1 f

= 20 log

EL f filter omitted dB EL f filter inserted

12 1

EMI filters are generally “low-pass” in nature (Figure 12.3), which pass signals (or power) with a frequency lower than a designed cutoff frequency and attenuate signals with frequencies higher than the cutoff frequency. The exact frequency response of the filter depends on the filter design. The insertion loss of low-pass filters is expressed in general form as N

IL f = 10 log 1 +

ki i=1

f f0

2 i

dB

12 2

The index “i” in Equation (12.2) is the “order of the filter” and represents the number of reactive stages in the filter and, subsequently, the number of poles provided by it. The constant ki is associated with a particular filter topology. f is the frequency of interest and f0 is the cutoff frequency, or 3 dB knee frequency of the filter. By observation, the higher the order of the filter, the higher the suppression above the cutoff frequency, f0 (Figure 12.4). EMI filters may be categorized as “reflective” and “dissipative” filters. Reflective filters accomplish this by using combinations of reactive elements, capacitance and inductance, in particular, to create a high series or low-shunt impedance for interfering (EMI) currents, reflecting them back to their source (Figure 12.5).

12.3 Overview of Filtering and Transient-Voltage Suppression

10 Cuttoff frequency 0 –3.01 dB –10 Slope: –20 dB/decade

Gain (dB)

–20

–30

–40

–50 Passband –60 0.001

0.01

Stopband

0.1

1 10 Angular frequency (rad/s)

100

1000

Figure 12.3 Theoretical gain-magnitude vs angular frequency response of a first-order (single-pole) low-pass filter (in dB). The curve is “theoretical” as it represents a parasitics-free response. In practice, the insertion loss curve can significantly deviate from the theoretical curve, due to parasitics. Source: Omegatron/Wikipedia/ Public Domain.

0

–20

A (ω) / dB

1 –40 2 –60 3 4

–80 5 –100

0.01

0.1

1 ω/rad/s

10

100

Figure 12.4 Theoretical gain of Butterworth low-pass filters of orders 1 through 5 (in dB), with equal cutoff frequency. The slope is 20 n dB/ Decade, where N is the filter order. Source: Inductiveload/Wikipedia/ Public Domain.

100 V

Signal

100 μs

0V 0 μs 50 μs100 μs

200 μs

0 μs50 μs100 μs 100 V

Highfrequency distortion 300 μs

200 μs

300 μs

400 μs

Signal

400 μs

0V

Filter Incident EMI Reflected EMI

Figure 12.5 Effect of an EMI filter on incident EMI.

Transmitted EMI

665

12 Grounding of Terminal Protection Devices

The effectiveness of an EMI filter is greatly influenced by the impedance of both source and load termination impedances.2 For a filter to effectively suppress EMI by reflecting noise, the filter should provide a maximum impedance mismatch to the interference signal while exhibiting little effect on the desired signal. If the load impedance is low, the impedance of the filter from the load viewpoint, ZLF, should be high. Conversely, if the load impedance is high, the filter should exhibit a low impedance from the load viewpoint. Consider, for instance, the most fundamental filter configuration is the first-order low-pass filters, consisting of a single reactive element, a shunt capacitor or a series inductor, depicted in Figure 12.6. Rejection of a capacitive filter (Figure 12.6a) is maximized when placed in circuits with high source (ZS) and load (ZL) impedances. At lower frequencies, the filter has little effect on circuit performance, but at higher frequencies, where ZC ZS, ZL, the filter-capacitor will introduce rejection into the circuit. Conversely, the inductive filter (Figure 12.6b) is most effective in low-impedance circuits, i.e. ZL ZS, ZL. The approximate (theoretical) insertion loss of discrete capacitive and inductive filters is expressed in Equations (12.3) and (12.4), respectively [3, 4]. a) Capacitive filter IL f

20 log ωC

1 ωC

ZS, ZL

ZS ZL dB ZS + ZL

12 3

b) Inductive filter 20 log

IL f ωL

ωL dB ZS + ZL

12 4

ZS , ZL

where ω = 2πf is the angular frequency associated with f, expressed in radians/second. ZS

ES

ZS

C

ZSF

Z LF

ZL

ES

L Z LF

Z SF

50

ZL

Low-ZL

Low-ZS

High-ZL

High-ZS

40

40

Insertion loss (dB)

30

Insertion loss (dB)

666

30

20

20

10 10

0 0.0001

0.001

0.1

0.01

Frequency (MHz)

Figure 12.6

1

10

0 0.0001

0.001

0.1

0.01

1

10

Frequency (MHz)

Insertion loss curve ZS = ZL = 50 Ω, C = 0.1μF

Insertion loss curve ZS = ZL = 50 Ω, L = 100 μH

(a)

(b)

Low-pass EMI filters consisting of a single reactive element. (a) Shunt capacitive low-pass filter. (b) Series inductive low-pass filter.

2 Manufacturers of EMI filters normally specify the filter characteristics with fixed source and load impedances (typically 50 Ω). As the actual circuit characteristics may be very different this aspect must be taken into consideration when designing, specifying or using EMI filters.

12.3 Overview of Filtering and Transient-Voltage Suppression

The above expressions clearly illustrate the improved rejection of the filter as frequency increases, conditional upon the values of C and L in the capacitive and inductive filter schemes, respectively. From the perspective of circuit theory (i.e. Kirchhoff approach), the capacitor in Figure 12.6a acts as a current divider for high-frequency interference, effectively shunting EMI currents when the parallel combination of source and load impedance are significantly higher than the capacitor’s impedance. Conversely, the inductor in Figure 12.6b exhibits a high series impedance at high frequencies, serving as an interference voltage divider, developing across itself the major part of the EMI voltage, thus again, protecting the load from the interference. This will occur as long as the series combination of source and load impedance is significantly lower than that of the inductor at the EMI frequencies.3 ZSF and ZLF in Figure 12.6 represent the filter impedance as seen by the source and load, respectively. From the perspective of electromagnetic theory (i.e. Maxwellian approach), when the filter is placed near the load, for instance, it introduces the impedance mismatch, which results in reflection of the interference signal back to its source, hence “reflective filters.” Dissipative filters (e.g. ferrite compounds) provide rejection by absorbing and dissipating the interference energy. Ferritebased filters, for instance, constitute a substitute to inductors and thus appear as series elements in low-pass filters; however, rather than producing reflection of the interference, they dissipate it. Whether reflective or dissipative, the filter’s passband is the frequency range in which it exhibits little or no rejection, whereas the stop band is the frequency range in which high rejection is desired. A primary disadvantage of single-element/pole filters is that their out-of-band theoretical roll off rate or slope is limited to 20 dB per frequency decade, or 6 dB per octave. When a discrete filter does not provide the required suppression, several singlesection filters can be cascaded to obtain more attenuation (see Figure 12.4 above). In symmetrically loaded circuits similar to those in Figure 12.7, symmetrical filter sections are used, the most fundamental of which are the “π-section” filter and “T-section” filter. These filter schemes consist of three reactive elements resulting in a typical insertion loss curve with a theoretical slope of 60 dB per decade or 18 dB per octave. In high-impedance circuits, “π-section” filters provide the best results, owing to the intrinsic mismatch between the filter elements and the source and load impedances. In fact, “π-section” filters are the most commonly used types of EMI suppression networks, whereas in low-impedance

ZS

ZS

L C

ES

C

ZL

High-ZS

ES

Low-ZS

High-ZL 80

60

70

Insertion loss (dB)

Insertion loss (dB)

Low-ZL

60

50 40 30 20

50 40 30 20

10

10

1

10

100

0 0.01

0.1

1

Frequency (MHz)

Frequency (MHz)

Insertion loss curve: ZS = ZL = 50 Ω, C = 0.5 nF, L = 2 μH

Insertion loss curve: ZS = ZL = 50 Ω, C = 100 nF, L = 2 μH

(a) Figure 12.7

ZL

Z LF

Z SF

70

0 0.1

L C

Z LF

Z SF

L

10

(b)

Low-pass “π” and “T” EMI filters. (a) Low-pass “π filter.” (b) Low-pass “T filter.”

3 The effect of the filters can easily by understood based on Kirchhoff’s current and voltage laws for capacitive and inductive filters, respectively.

667

12 Grounding of Terminal Protection Devices

circuits, “T-section” filters are the most commonly used. Both, however, have a tendency to develop oscillatory ringing when excited by impulsive transients. The approximate insertion loss of “π” and “T” filters is expressed in Equations (12.5) and (12.6), respectively [3, 4]. a) “π-section” filter ZS ZL dB ZS + ZL 1 ωC < Z S and 1 ωC < Z L and ωL > 1 ωC 20 log ω2 LC + LC 2 ω3 + 2ωC

IL f

12 5

b) “T-section” filter 20 log ω2 LC +

IL f

LC 2 ω3 + 2ωL ZS + ZL

dB

12 6

1 ωL > Z S and ωL > Z L and ωL > 1 ωC In these filter schemes, the capacitors act as low-impedance current dividers and the inductors act as high-impedance voltage dividers. “π” and “T” filters should be used for the same applications where capacitive and inductive filters would be used, respectively, offering enhanced performance. The insertion loss of a lossless “π” and “T” filter networks operating with equal source and load impedances, RS = RL = R, is defined in Equations (12.7) and (12.8), respectively [5]. a) “π-section” filter 10 log 1 + f 2 D2 − 2f 4 D + f 6 dB

IL f D=

1−ζ L ; ζ= = damping ratio; f 0 3 ζ 2CR2

1 2 2π RLC 2

1 3

12 7 Hz

b) “T-section” filter IL f D=

10 log 1 + f 2 D2 − 2f 4 D + f 6 dB 1−ζ CR2 = damping ratio; f 0 ; ζ= 3 2L ζ

1 2R 2π L2 C

1 3

12 8 Hz

These equations are of the same form, but differ with respect to the definition of the equation parameters, particularly the damping ratio (or factor), ζ, a dimensionless measure which describing how oscillations in a system decay after an impulsive excitation. Losses (e.g. resistance) damp the system and can cause the oscillations to gradually decay in amplitude towards zero or attenuate. The damping ratio, denoted by ζ (zeta), can vary from undamped (ζ = 0), through underdamped (ζ < 1) and critically damped (ζ = 1) to overdamped (ζ > 1) (Figure 12.8). In asymmetrically loaded circuits (Figure 12.9), asymmetrical filter schemes must be used, the most fundamental of which is the “L-section” filter. Two fundamental representations of low-pass “L-section” filters consist of two reactive elements with a typical insertion loss curve and theoretical slope of 40 dB per decade (12 dB per octave). 2.0

ζ=0 ζ = 0.1 ζ = 0.2

1.5

ζ = 0.4 y(t)

668

ζ = 0.7

1.0

ζ=1 ζ=2

0.5

0.0 0

π

2π ωnt / rad

3π

4π

Figure 12.8 Effect of varying damping factor on the impulse response of a second-order system. Source: Inductiveload/public domain CC BY Share A Like 3.0.

12.3 Overview of Filtering and Transient-Voltage Suppression

(a)

(b)

ZS

ZS

L C

ES ZSF

ZL

ZL

ZSF

ZLF

Low-ZS

L C

ES

High-ZL

Z LF

High-ZS

Low-ZL

50

Insertion loss (dB)

40

30

20

10

0 0.01

10

1

0.1

Frequency (MHz)

Insertion loss curve: ZS = 5 Ω, ZL= 50 Ω C = 3 nF, L = 10 μH

Insertion loss curve: ZS = 50 Ω, ZL= 5 Ω C = 3 nF, L = 10 μH

Figure 12.9 Low-pass “L-section” EMI filters in asymmetrically loaded circuits (insertion loss curve identical for cases (a, b)).

The insertion loss for the “L-section” filter is independent of the direction of inserting the “L-section” into the line, if source and load impedances are equal. When source and load impedances are unequal, the greatest insertion loss will usually be achieved when the capacitor shunts the higher impedance. The approximate insertion loss of the two “L-section” filters are expressed in Equations (12.9) and (12.10), for the high ZL (Figure 12.9a) and high-ZS (Figure 12.9b), respectively [3, 4]. a) “L-section” filter, ZS IL f ZS

20 log

ZL

ωL + LCω2 dB ZL

12 9

ZL

b) “L-section” filter, ZL IL f

ZL

20 log

ZS ωL + LCω2 dB ZS

12 10

ZS

The insertion loss of an “L-section” filter is not changed when it is “turned around” so that the source and load terminals are transposed and with equal source and load impedances, RS = RL = R, expressed by Equation (12.11) [5]. The effect of the damping ratio, ζ, is similar to that for the “π-section” and “T-section” filter networks. IL f

10 log 1 +

f 2 D2 + f 4 dB 2

1−ζ L D= ; ζ= = damping ratio; f 0 ζ CR2

1 2 2π LC

12 11

1 2

Hz

All of the above filter schemes can be used for suppressing both common-mode (CM) and differential-mode (DM) interference signals.4 When used for suppression of CM EMI, the shunt capacitors are referenced to the signal reference structure, or chassis, as shown in Figure 12.10. For DM interference suppression, the capacitors are connected in a line-to-return configuration. No connection to the signal reference structure is required. Most EMI filters are of common-mode type, with few exceptions, primarily in low-frequency sources within equipment, switch-mode power supplies in particular. Common-mode 4 Common-mode and differential-mode signals and their generation/propagation are discussed in Chapter 2.

669

670

12 Grounding of Terminal Protection Devices

L

L C

C L

Figure 12.10 Common-mode and differential-mode filter networks. (a) Common-mode (line to chassis) filters. (b) Differential-mode (line to line) filters.

(1) "L-section" filter

L

L C

C

C

C L

(2) "π-section" filter

L

L

L C

C

L C L

L (3) "T-section" filter

(a)

(b)

interference is the most frequently encountered interference mode, both from sources internal to equipment and coupled from the external environment, and is most prevalent at frequencies above 100 kHz [3, 4].

12.3.2

Special EMI Filter Applications

Several types of special filter components are commonly used for EMI control, often forming part of the filter topologies discussed above, namely common-mode chokes and feed-through capacitors. These devices are of special interest with respect to grounding considerations in circuit and system design. 12.3.2.1 Common-Mode Chokes

Suppression of common-mode (CM) interference signals can be achieved by either line-to-ground (reference structure) capacitors (CM capacitors) or series inductors. For achieving a high-insertion loss, large CM capacitors may be required in powerline filters. A large value of capacitance on the high-voltage input terminals of power supplies is prohibited by electrical safety codes, due to concerns relating to power-frequency leakage currents and the hazard of electrical shock should someone physically touch the pins of the receptacle by accident.5 Signal circuits, on the other hand, cannot tolerate large capacitance due to the detrimental effect it may have on the signal waveforms themselves. Unfortunately, large series inductors cannot typically be used in filters as well. High-permeability cores are easily saturated by excessive magnetic flux induced by large power-supply currents, whereas in signal lines large inductors will be just as harmful to the signal waveforms as large value capacitors. Consequently, the CM filter schemes depicted in Figure 12.10 are rarely used with ordinary high-permeability inductors. This is where common-mode chokes become useful.6 Figure 12.11 illustrates the alternate physical representation of a multiturn CM choke. The wires (signal/power and return) are wound several turns around a high-permeability ferrite core. The function of the CM choke is explained in Figure 12.12. Magnetic flux (BDM) induced by the differential-mode (DM) current (IDM) in the core is canceled out by an equal but opposite magnetic flux induced by the return (DM) current that encircles the core. The DM current is, therefore, not attenuated if perfectly balanced. In reality, common-mode chokes exhibit some undesired “leakage (DM) inductance” due to imperfections in its construction, as well as losses due to winding resistance. This leakage inductance will introduce some DM suppression, which in power line filters is normally not a major concern. A general equivalent circuit of a practical common-mode choke is depicted in Figure 12.13, representing the coupling factor K, the common5 See Chapters 3 and 6 for a discussion of safety concerns associated with leakage of power-frequency current through CM capacitors to the equipment chassis. 6 CM chokes were described in Chapter 4 with respect to their ability to “open” ground loops. The same attributes are used here for suppressing CM interference.

12.3 Overview of Filtering and Transient-Voltage Suppression

DM-generated flux

CM current Signal DM current

CM-generated flux

Core Hi − µ

(a)

(b)

Figure 12.11 Alternate schemes of CM chokes and its effect on CM and DM currents. (a) Two forms of practical construction. (b) Current flow in the choke. Source: The Würth Elektronik Group, https://www.we-online.com/web/en/electronic_components/. 1

4

1

4

2

3

1

4

2

3

Flux from CM currents is additive, to become highly inductive 2

3

(a)

1

4

2

3

Flux from DM currents oppose each other, so (almost) no inductance observed

(b) Figure 12.12 Function and operation of a common mode choke and its effect on CM and DM interference current. (a) Common-mode current excitation. (b) Differential-mode current excitation.

mode inductance (LCM), the (“leakage”) differential-mode inductance (LDM), as well as the inter-winding and intra-winding capacitances (CP and CW, respectively) and the wiring resistance (Rwire) [6]. Magnetic flux (BCM) due to any CM current (ICM) that may be present, however, will cancel itself out with flux from one wire traveling clockwise and the return current traveling counterclockwise, intermingling with each other. Attenuation of the CM noise is, thus, achieved by the series combination of inductive reactance and resistive losses of the core.

CP

LCM

LDM RWire

K LCM

CWire S

LDM RWire

12.3.2.2

Power-Line Filters

Power-line filters are commonly used for compliance with emissions CP and immunity requirements limits of international EMC standards. Owing to the nature of their application, they warrant particular interest with respect to grounding and bonding considerations. There Figure 12.13 Equivalent circuit of a “real-world” commonmode choke. are two conflicting requirements to conform to strict electrical safety codes and shunting RF noise into a ground reference structure. Figure 12.14 presents the configuration of a typical single-phase power-line filter. For three-phase power circuits, the same configuration is duplicated for each phase7). Single-series chokes L1 and L2 provide suppression of DM interference and are typically on the order of tens to hundreds of μH. Inductors L3 and L4, wound on a single toroidal core, constitute a CM choke (discussed in the previous section) and normally exhibit high CM impedance due to relatively high inductance (up to tens of mH). The inherent stray or leakage (DM) inductance of CM choke inductors (L3 and L4) often provides sufficient DM 7 In three-phase power line filters, CY(CM) capacitors are placed between each (phase and neutral) line to the electrical safety ground conductor (ESGC) and CX capacitors are included between all phases and between them to the neutral. Also, three phase lines and the neutral (in “star” power networks) are all wound on a common CM choke core, while DM chokes are placed on separate cores.

671

672

12 Grounding of Terminal Protection Devices

DM stage

Phase

L3 L1 R1

CX

CY CY

L2

CX

Differential (functional) load

L4

Neutral ESGC (P.E.)

Figure 12.14 Configuration of a typical single-phase power line filter (single phase).

CM stage

L5

Equipment chassis

suppression, eliminating the need for additional DM chokes. The resistor R1 is required in order to discharge the line-to-line capacitor, CX, for product safety reasons, in addition to eliminating stray voltage present, thus minimizing oscillations of the filter due to its low-frequency high Q-factor. The chassis of the equipment itself may be RF noisy with internally generated EMI. The protective earth (PE) or electrical safety ground conductor (ESGC) lines can thus carry internally generated interference current, resulting in conducted and, subsequently, radiated emissions. The series inductor L5, sometimes included in power-line filters, is intended to control these emissions from the ESGC wire. In compliance with electrical safety codes, the impedance of the ESGC must not exceed an approved value, which is typically 100 mΩ (equivalent to approximately 300 μH in a 50 Hz power frequency system). This inductor must be able to handle any and all fault current without damage until the fuse on the power line is activated [3]. A category of capacitor known as “Y” capacitors (CY)8 are used between phases (or neutral) lines and chassis or ESGC/PE to shunt CM currents to ground. These capacitors are most effective at higher frequencies. The Y capacitors are limited to very low values owing to electrical safety limits set by regulatory bodies with regard to equipment leakage current. Typical capacitive values of Y capacitors are on the order of tens of pF to tens of nF. The X capacitors (CX) are connected between phase and neutral or phase to phase, producing attenuation of DM interference. Typical values of X capacitors are in the range of tens to hundreds of nF. Clearly, the key to high-frequency performance of any power-line filter is the effectiveness of the Y (CM) capacitors. With ideal capacitors, which in reality do not exist, higher frequency performance is guaranteed. Unfortunately, use of capacitors is limited by parasitics.

12.3.3

Transient-Voltage Surge Suppression (TVSS) Devices and Circuits

Physically long interconnects, such as power lines and cables between equipment, may be subjected to very large voltages and current transients due to a wide variety of phenomena. Conducted phenomena include inductive switching transients and lightning or high-altitude electromagnetic pulses (HA-EMP)-induced surges [5, 7]. Unlike ordinary EMI phenomena, the levels of which cannot normally cause permanent damage to equipment, transients are fast events of high magnitude and may be destructive, significantly harming electrical and electronic apparatus. 12.3.3.1 A Transient-Effects, Grounding-Related Case Study

The case study described in this section illustrates the adverse effect of improper grounding in enhancing vulnerability of a system to lightning-induced surges. Two computer systems, installed in sites separated by several hundreds of meters, were interconnected using a RS-422 data communication link (Figure 12.15).9 The chassis of each of unit contained a local signal reference to earth ground. Due to lightning surge current, resulting from a near lightning stroke, the earth potential increased abruptly between the central and the remote sites, causing a voltage potential, ΔVE, to develop between the earthing points of the two facilities. Since each computer was grounded locally to the facility’s signal reference network, the same potential difference, ΔVE, also appeared as common-mode voltage between both input terminals of the RS-422 receiver, far exceeding its damage threshold, resulting in damage to the line receiver. Ideally, preclusion of damage could have been achieved if an equipotential structure were to be provided between the two interconnected computers. This was impractical, however, since regardless of the quality of the equipotential structure construction, inductance of the grounding network conductors would counteract the objective of attaining a true equipotential structure between the two sites. A voltage potential difference of thousands or more volts would ultimately be present between 8 Breakdown due to an electrical stress across power lines may result in a hazardous electric shock or fire (failure of line-to-line Capacitors could result in fire while failure of line-to-ground capacitors could result in electric shock). Whenever a “fail-to-short-circuit” could put humans in danger, X and Y-capacitors, meeting the IEC 60384-14 standard must thus be used. Typical characteristics of Class X capacitors and Class Y capacitors are rated voltage, capacity and a surge voltage withstand. 9 The Reader may note that this situation is an example of a “distributed system” discussed in Chapter 4.

12.3 Overview of Filtering and Transient-Voltage Suppression

Lightning strikes building at site #1 Site #2 (remote site)

Site #1 (central site)

A portion of the lightning discharge current flows through the wiring

Sig. ref. plane Signal reference network

Sig. ref. plane Signal reference network

Most of the lightning discharge current ZE flows to earth

Earth

ΔVE Lightning current returning through the earth impedance

Figure 12.15

A case study: inadequate grounding as a source of lightning-produced transient effects.

the grounding points of the two computers during a lightning event. To the system designer, this indicates that although a differential interface such as RS-422 uses a low-voltage differential signaling, a remote node may observe the signal voltage superimposed on a transient of hundreds or thousands of volts with respect to that node’s local signal reference structure. How can system nodes be interconnected knowing that these large voltage potential differences between the signal references may be present? The first step toward successful protection is to assure that each device in the system is referenced to only one reference structure, eliminating the path through the device for surge currents searching for a return path. Isolation of the signal return (reference) plane within one or both of the interfacing computers may constitute a satisfactory solution under certain circumstances. In most cases, however, this approach is impractical or ineffective. The other approach is to tie the circuit signal reference terminal through a low-impedance connection to the signal reference structure. This goal, however, cannot always be achieved at DC due to functional constraints (e.g. balancing of the interface) but can be met by means of transient-voltage surge suppression devices (TVSSs) that provide a transitory path for shunting harmful surge currents while limiting the residual voltage transients to tolerable levels. 12.3.3.2

Fundamentals of Transient-Voltage Surge Protection

current

12.3.3.3 Commonly Used Transient-Voltage Surge Suppression Devices (TVSS)

A large variety of shunting TVSS is available to choose from. With the exception of linear EMI filters, all designated TVSS are nonlinear in nature. The most commonly used devices are described below.

Signal reference structure (chassis)

Figure 12.16 circuit.

ZL

TVSS

Creating one common ground connection at the host device provides a safe place to divert surge energy as well as a voltage reference to attach transient-suppression devices to. Shunting harmful surge current to the signal reference structure before it reaches the protected circuit is the function of transient-voltage surge suppression devices (TVSSs). Similar to EMI filters, protection against transients is achieved by diverting the surge current by using low-impedance crowbar devices such as gas discharge tubes (GDTs) and thyristors, limiting the surge voltage by using nonlinear shunting devices such as metal-oxide varistors (MOVs) and avalanche diodes, and blocking the current surge by using series high-impedance components such as resistors and inductors. Occasionally, transient-protection devices are also incorporated within standard linear EMI filters. Figure 12.16 demonstrates the effect of a transient-suppression device (TVSS) on an incident surge with the series resistor and an avalanche diode, serving as blocking and limiting devices, respectively. Similar to other conducted EMI phenomena, transients may appear both in common mode Clamped transient and in differential mode. Figure 12.16 illustrates a tranvoltage Series blocking sient-protection scheme of a single-ended circuit in which device the return signal is connected to the signal reference structure or chassis. In differential and balanced circuits, TVSSs would be required between each line to the reference as Diverted well as line to line if protection against both CM and Incident Protected transient transient DM transients is necessary. load Load's signal return

A typical transient protection scheme for a single-ended

673

674

12 Grounding of Terminal Protection Devices

(a)

(b)

Figure 12.17 Gas tubes and their circuit representations. (a) 2-Electrode gas tube and its circuit representation. (b) 3-Electrode (CM and DM) gas tube and its circuit representation.

a) Spark Gaps and Gas Discharge Tubes (GDTs) (Figure 12.17) A spark gap is a pair of electrodes, insulated by air or the dielectric material of a printed circuit board, and spaced so that the gap sparks over when the voltage across its contacts exceeds a specified level. The spark-gap firing voltage increases with the rate of rise of the applied surge and ranges from hundreds of volts to hundreds of kilovolts. In their nonconducting state, spark gaps behave as open circuits with extremely low capacitances. Gas discharge tubes are spark gaps encapsulated in glass or ceramic tubes filled with a low-pressure inert gas and terminated on each end with an electrode providing a lower spark overvoltage. Gas discharge tubes are used primarily for secondary protection of wire pairs entering a facility from a long external shielded cable or for exposed intra-facility wiring. Being a shunt device, the GDT is connected in parallel with the circuit being protected, exhibiting a very high off-state impedance. Once an incoming transient exceeds the breakdown voltage of the tube, it fires, causing an arc in the tube. This arc ionizes the inert gas that provides a low-impedance path for discharge of the transient. When the transient voltage drops below the hold voltage, the gas discharge tube returns to its high off-state impedance. GDTs may operate in the “glow” or “arc” states. The glow state occurs in circuits whose impedance limits the discharge current to less than about 100 mA. The voltage across the device’s terminals in this state is about 100 V. The arc state occurs when large currents flow through the device, resulting in voltages across its terminals of usually 10–20 V. Gas tubes should not be used on energized lines that can sustain an arc or glow discharge, as they may not extinguish after a period of time, resulting in their damage (a phenomenon known as “follow-current”). One advantage of the gas discharge tube is that it can provide protection against high surge currents. For transients on the order of 10 μs in duration, a GDT can withstand up to 20 kA. For longer but lower current pulses, the gas discharge tube can handle many hundreds of transients before the device enters a failure mode. The greatest disadvantage of spark gaps and gas discharge tubes is their relatively slow response, resulting in large overvoltage transient overshoots across their terminals while the inert gas is ionizing. This overvoltage can be on the order of four times the rating of the tube. Spark gaps are rarely used in high-technology products without successive complementary protection devices. b) Metal-Oxide Varistors (Figure 12.18) Metal-oxide varistors (MOVs) are passive, nonlinear solid-state devices made from sintered metal oxides, primarily zinc, acting as nonlinear resistances, that is, V =I×R V

12 12

or, alternatively: I = K × Vα

12 13

where typically 25 < α < 60, V represents the voltage across the MOV terminals, I represents the surge current through the device, and R(V) is the nonlinear, voltage-dependent resistance of the MOV. When exposed to a voltage greater than the rating of the device, its MOV’s resistance drops to a very low value shunting the surge current and dissipating the transient energy as heat. MOVs are capable of diverting currents up to tens of kiloamperes and are effective for large rateof-rise transients. A MOV stops conducting and returns to its state of high resistance when the applied voltage decreases below the “knee” of the I–V curve and is ideal for protecting energized lines, since it has no current-extinguishing problems. The MOV typically introduces a shunt parasitic capacitance in the order of nano-Farads and shunt resistance of mega-Ohms to the protected circuit, limiting its usefulness in high-frequency and high-impedance circuits. The maximum energy dissipation capability for large MOVs is tens of kilojoules. c) Avalanche Diodes (Figure 12.19) Avalanche diodes are passive, nonlinear solid-state devices with a high doping content that limit Figure 12.18 Circuit representation the voltage across a component or signal line by clamping the incoming transient voltage after the of MOVs. stand-off voltage is exceeded.

12.3 Overview of Filtering and Transient-Voltage Suppression

Avalanche diodes are capable of operating at much lower voltage levels than MOVs and GDTs (1–100 V), but are less tolerant to large peak currents than the other devices and may be damaged by full-threat transients. Peak current ratings up to about 100 A are available. The advantages of using an avalanche diode are its speed and repeatability. Since it is made of silicon, the diode is much faster than an MOV or a gas discharge tube, and its capability will virtually not degrade with time, unless it is stressed beyond its power rating. The design restriction for avalanche diodes is that they are both voltage- and current-dependent. Therefore, as the voltage requirement increases, (a) the current capability will decrease. These devices introduce a shunt parasitic capac(b) itance on the order of nano-Farads to the protected circuit and may aggravate highfrequency signals. Figure 12.19 Circuit Of all the TVSSs presented here, diodes are unique in that they are unipolar in representation of avalanche diodes. (a) Circuit representation of a nature. When forward biased, they exhibit the p–n junction voltage drop across their unidirectional avalanche diodes. terminals, whereas, when reverse biased, the voltage across them is limited by their (b) Circuit representation of a reverse breakdown voltage capabilities. This feature allows the combination of two bi-directional avalanche diodes. “back-to-back” avalanche diodes into a “bidirectional” scheme, which, regardless of the surge polarity, will introduce an equal (but reverse) voltage drop across its terminals. The bidirectional devices are typically used in balanced, differential lines. d) Linear Filters (Figure 12.20) Transients, when analyzed for their spectral energy content, are found to distribute a portion of its energy in medium and high frequencies. It would seem, therefore, that linear low-pass filters, suppressing that portion of energy spectrum, should suppress the overall amplitude. Regretfully, there are certain practical drawbacks to this approach:

• • • •

Components of linear filters cannot typically tolerate the excessive momentary energy associated with the surges and transients; capacitors may breakdown due to peak voltages while chokes’ inductance may decrease during large surge currents due to partial or complete saturation Achieving suppression at low frequencies is difficult; insertion-loss of typical commercial-grade power-line filters is mostly specified across the frequency range 150 kHz–30 MHz, while the lion’s share of the energy spectral content of most surge (e.g. IEC-61000-4-5 8/20 and 1.2/50 μs) waveforms falls well below 100 kHz, resulting in minimal suppression of the surge waveform [8] Spectrum of the surge may overlap that of the desired signal, thus the low-pass filter used may degrade the signal (this is typically of lesser concern on DC and AC power line filters) Low-pass filter insertion-loss is typically obtained from data taken in a 50 Ω (source and load impedances) test setups, specified in such standards as CISPR 1710 and MIL-STD-220A,11 which is of extremely limited value in practical circuits. Furthermore, these tests are carried out with sinusoidal input waveforms while impulsive transient excitations may result in “ringing” response in underdamped filters (see Figure 12.8 above). In fact, the filter termination is usually an unknown

Figure 12.20 Normalized spectral content (Fourier transform) of various nominal transient waveforms. Source: Standler [8].

0

10/1000 µs, VP = 0.6 kV 1.2/50 µs, VP = 6 kV

dB

–20

8/20 µs, IP = 3 kA

–40

100 kHz Ring wave, VP = 0.6 kV

–60 EFT, VP = 4 kV –80 1

10

100

1k 10k Frequency, Hz

10 CISPR 17, “Methods of Measurement of The Suppression Characteristics of Passive EMC Filtering Devices.” 11 MIL-STD-220A, “Department of Defense Test Method Standard Method of Insertion Loss Measurement.”

100k

1M

10M

675

676

12 Grounding of Terminal Protection Devices

value that often varies with frequency. As the filter performance is largely dependent upon termination impedance, the insertion-loss curves given for 50 Ω systems can rarely represent real-world situation. Several alternatives to 50 Ω insertion loss measurement curves are provided in CISPR 17, aimed at showing the filter effectiveness in real situations rather than in an artificial situation. In this approach, the filter insertion loss is measured with 0.1 and 100 Ω terminations on the line and load ends, respectively, and vice versa. For all of the above reasons, linear filters are often used alone for protection against transients but rather in combination with nonlinear transient-suppression devices (discussed above). For this reason, a supplemental gas discharge tube is used to limit the voltage, while the linear filter isolates the internal circuits from the voltage overshoot resulting from the GDT discharge. The shunt input capacitance of the filter may also be used to reduce the rate of rise of the voltage. This allows the surge suppressor to spark over at a lower voltage (Figure 12.21).

12.3.3.4 Hybrid Transient-Protection Circuits

Often, discrete TVSS cannot provide acceptable protection for the circuits. Devices capable of handling high- energy surges (such as gas discharge tubes, GDTs) exhibit a relatively slow response, whereas fast devices (e.g. avalanche diodes) cannot handle a high surge current. For this type of application, three-stage hybrid transient-suppression circuits are used (Figure 12.22). The first stage is typically a GDT, which can handle high surge currents and diverts most of the surge current once it fires. However, it has a high spark-over voltage and is too slow to protect sensitive solid-state circuits on its own. An avalanche diode usually serves as the “fast” TVSS and constitutes the third stage of the circuit. It is fast enough to respond “instantly” to the fast front time of the transients, clamping the voltage across the protected circuit to a safe level. However, its energy handling capabilities are low and it cannot operate without damage for a long period of time. A small series impedance12 serves as an isolation element in the second stage of the circuit and is intended to fulfill two primary objectives, namely, limiting the incident surge current flowing into the third, lower energy stage of protection,

Figure 12.21 Typical EMI filters combined with TVSSs. (a) Power line EMI filter combined with TVSSs. (b) Balanced signal line filter combined with TVSSs.

EMI filter stage

TVSS stage

Load output

Line input

(a) TVSS stage #1

EMI filter stage

TVSS stage #2

Load output

Line input

(b)

12 Typically, a resistor is used as an isolation element on signal lines whereas small inductors are used on power lines. Often, the isolation element is implemented as a common-mode filter.

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

Figure 12.22

Hybrid transient-suppression circuit.

Frequency, Hz Stage #1 Slow, high-energy current shunting TVSS

Stage #2 Series isolation element

Stage #3 Fast, low-energy voltage clamping TVSS

Load output

Line input Incident surge

Gas tube voltage

Current through isolation element

Avalanche diode voltage

and creating a sufficiently high voltage drop between the third and the first stage to ensure the firing of the GDT in a timely manner. For optimal protection, coordination between the different TVSS stages and between them and the protected circuit is required [3].

• •

The Least You Need to Know High-energy transients such as those generated by lightning, HA-EMP and inductive load switching, could potentially damage electronic circuits and components. Transient suppression is accomplished by transient-suppression devices and circuits, typically comprised of nonlinear devices such as gas discharge tubes (GDTs), metal oxide varistors (MOVs), and avalanche diodes, as well as linear components such as resistors, inductors, and low-pass filters.

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices 12.4.1

Modes of Protection

Prior to designing and installation of EMI filters and surge protection devices, some knowledge is necessary with regards to the required “modes of protection.”13 The term “mode of protection” may be interpreted as “an intended current path, between terminals that contains protective components, e.g. line-to-line, line-to-earth, line-to-neutral, neutral-to-earth.”14 For a single-phase AC power TVSS, for instance, connecting to line (L), neutral (N), and ground/protective earth (G) conductors, the modes of protection may be line-to-neutral (L–N), line-to-ground (L–G), and neutral-to-ground (N–G), while for three-phase AC power TVSSs connecting to line, neutral, and ground conductors, the modes of protection may be line-toneutral (L–N), line-to-ground (L–G), line-to-line (L–L), and neutral-to-ground (N–G). A somewhat more accurate and better definition for “modes of protection (of a voltage limiting TVSS or equipment port)” is “list of terminal-pairs” where the diverted surge or EMI current is directly between that terminal pair without flowing via other terminals, emphasizing that the protective function is directly between the pairs and does not involve other terminals. Figure 12.23 illustrates this principle with an MOV. a) In (a), the protective device connects nodes A and B. The scheme provides a single direct mode of protection, A–B. b) In (b), three protective devices are used, each connecting to a node pair. This scheme provides three direct modes of protection A–B, B–C, and A–C.

13 The material in this section is adapted from https://pes-spdc.org/content/modes-protection-and-surge, of the IEEE Power and Energy Society, Surge Protection Devices Committee. 14 This definition is adapted from IEC 61643-11, ed. 1.0 (2011-03), “Low-voltage surge protective devices – Part 11: Surge Protective Devices Connected to Low-Voltage Power Systems – Requirements and Test Methods,” extending the application from surges only to “EMI and surges.”

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12 Grounding of Terminal Protection Devices

A

A

A

B

B

B

C

C

C

(a) Figure 12.23

(b)

A

B

D

C

(c)

(d)

(a–d) Modes of protection (of a voltage limiting TPD or equipment port).

A

A′

B

B′

C

C′

Figure 12.24 Modes of protection in a transformer-coupled circuit.

c) In (c), two protective devices are used each connecting to a node pair. This scheme provides two direct modes of protection B–C and A–C. In addition, one indirect mode of protection is available, namely A–C–B. Note that no protective devices exist in the direct A–B mode of protection.In AC applications, for instance, the protective devices are likely to be symmetrical and of the same voltage, making the A–B voltage twice the A–C or B–C voltage. In signal applications, on the other hand, the protective devices may be highly asymmetrical, making the A–B voltage nearly the same as the A–C or B–C voltages. d) Finally, in (d), three protective functions are used each connecting to a node and a common node D. This is a Y configuration. The arrangement provides three indirect modes of protection, namely A–D–B, B–D–C, and A– D–C.

Observing the example in Figure 12.24 raise some confusion with regards to the modes of protection provided by the circuit. The example in Figure 12.24 is often considered as common-mode surge protection A + B − C due to the isolation transformer insulation barrier voltage withstand and differential mode surge protection A − B due to the (green) output voltage limiter. However, this situation is inconsistent with the standard modes of protection definition because

••

modes of protection are written only for differential (two terminal or node) mode surge conditions surge mitigation is typically based on voltage limiting, providing a high-shunt current path

The term “modes of protection” would therefore more accurately be defined as “differential surge modes of protection using voltage-limiting technology.” It is implicitly assumed that two differential pairs (A–C, B–C, in example (c) in Figure 12.23)) is equivalent to common-mode protection (A + B − C). This could well be true in many cases, but a shared path element in the case of a common-mode surge would need to handle twice the current of the single differential surge condition.

12.4.2

Modes of EMI and Transients

For the purpose of ensuring adequate protection, the propagation modes of the EMI must similarly be considered and matched by the modes of protection.15 Common-mode (CM) and differential-mode (DM) propagation were discussed in detail in Chapter 2. For the purpose of the discussion in this section, it will suffice, therefore, to recall that common-mode EMI appears equally on all conductors of a group at a given location, while differential-mode EMI occurs between any two conductors or two groups of conductors at a given location. Mode conversion is the mechanism by which a signal in the one mode is converted into the other, i.e.

• •

common-mode conversion is the process by which a differential-mode electrical signal is produced in response to a commonmode electrical signal, and differential-mode conversion is the process by which a common-mode electrical signal is produced in response to a differential-mode electrical signal.

15 For the purpose of this chapter and simplicity of the text, unless otherwise stated herein, the term EMI will be assumed to include transients and surges as well. For the purpose of EMI filters, capacitors, rather than SPDs, would be considered.

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

Figure 12.25

Common-mode surge protection. A

B

D

Impulse

E

C

12.4.2.1

RA

Equipment port

RB

RD

RE

GDTE

GDTD

GDTB

GDTA

Common-Mode Surges

A classic approach for protection against common-mode surges is to limit the level of the surge and equalize the level of the residual surge on all conductors as depicted in Figure 12.25.16 An impulse voltage surge is applied in common-mode to cable conductor paths A, B, D, and E. The path currents are limited by series wiring resistors RA, RB, RD, and RE. The current path is completed by the conduction of port shunt GDTs, GDTA, GDTB, GDTD, and GDTE. As there is no interaction between the different current paths, when all GDTs conduct, they will (ideally) carry individually a quarter of the total surge current. If all GDTs were to sparkover simultaneously and the conduction currents would be equally shared, indeed, the residual surge voltage drop between the different paths would be equal, resulting in virtually no differential-mode surges between the lines. In practice, however, simultaneous sparkover is unlikely to occur and cable capacitance is likely to inhibit the initial sparkover of the port GDTs. If one series GDT conducts first, say for example GDTA, then its low-voltage conduction will inhibit sparkover of the GDTs in the three other current paths. Subsequently, in this example, the impulse source total current will flow in current path A, meaning GDTA and the other path A current carrying components will need to be rated for the total surge current. This example demonstrates that common-mode to differential-mode conversion may occur due to imbalance in the circuit response.

12.4.2.2

Linear and Nonlinear Conversion Loss

A classic approach for protection against common-mode surges is to limit the level of the surge and equalize the level of the residual surge on all conductors as depicted in Figure 12.25 above. The linear signal world uses the term longitudinal conversion loss (LCL)17 of a one- or two-port network as a measure (a ratio expressed in dB) of the degree of unwanted transverse (or differential-mode) signal produced at the terminals of the network due to the presence of a longitudinal (or common-mode) signal on the connecting leads. Conversely, differential-mode to common-mode conversion, known as differential conversion loss, is entitled transverse conversion loss (TCL) of a one- or two-port network is a measure (a ratio expressed in dB) of the degree of unwanted longitudinal signal produced at the input (or output) of a network due to the presence of a transverse signal at the same port. In the situation depicted in Figure 12.25, a differential-mode surge results from common-mode surge by the asynchronous operation of a GDTs connected between the common-mode surge conductors to a system common point. An unbalanced differential surge develops as one of the conductors is grounded and the surge only appears on the second conductor of the pair. Figure 12.26 depicts the surge protection circuit comprising of two independent GDTs. Similar to the above, the series resistor feeds, RA and RB, from the impulse source to the equipment port exhibiting a differential load, RAB. The surge protection circuit consists of two electrode GDTs, GDTA and GDTB. GDTB is assumed to spark over first on the rising surge front and conducts the surge current, IB (Figure 12.27). The value of the surge current, IA, conducted by GDTB depends on the value of the load, RAB, compared to RA. If, for instance, the peak surge voltage was 2.5 kV, the GDTB arc voltage would be 10 V, approximately, the series resistance 10 Ω and the equipment Ethernet port was would exhibit a 2 Ω resistance then the peak surge current, IA, would be (2500—10 V)/(10 Ω + 2 Ω) = 208 A, producing a peak surge voltage across GDTA of 415 V. Assuming the protection device complies with the IEEE 16 The examples below illustrate surge protection circuits, but apply, just as well, to EMI filters. 17 LCL is discussed in Chapter 2.

679

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12 Grounding of Terminal Protection Devices

RA

RB

Equipment port

A

Figure 12.26 Common-mode surge protection in a two-line circuit.

RAB B

Impulse

C GDTB

RA

A

RB

B

GDTA

Equipment port

Figure 12.27 Common-mode surge protection in a two-line circuit with GTDB sparking over first.

RAB

IA

IB

Impulse

C GDTB

RA

A

RB

B

GDTA

Equipment port

Figure 12.28 Common-mode surge protection in a two-line circuit with GTDB sparking over first.

RAB

IA

IB

Impulse

C

GDTAB

802.3 500 V insulation strength requirement, the GDT sparkover voltage would be at least 600 V, i.e. GDTA would not sparkover during the surge and the full differential surge of 208 A would flow through the equipment port. For ensuring simultaneous conduction, a commonly proposed solution is based on replacing the two separate GDTs with a single chamber three-electrode GDT as depicted in Figure 12.28. It is assumed that initially one side would sparkover and the plasma from the conducting side would cause conduction of the other side. However, with the low impedance of the load circuit, connecting the outer electrodes, a very different situation occurs. As the voltage of the non-conducting GDT section is pulled down by the conducting section, it has a lower electric field to attract the plasma. As a result, over ten microseconds may pass before both GDT sections conduct. During this time, the whole front edge of the surge is likely to appear differentially across the equipment port.

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

Figure 12.29 Common-mode surge protection in a three-phase power line using a three-phase diode bridge and a GTD.

RA

Equipment port

A

RAB

RB D1

D3

D5

Impulse GDTAB D2 C

Figure 12.30 Common-mode surge protection using a differential overvoltage protection feeding the GDT.

RA

D4

D6

Equipment port

A

RAB

RB

B P1

P2

Impulse

C

GDTAB

A standard solution to achieve simultaneous conduction is to use a three-phase diode bridge, D1, D2, D3, D4, D5, and D6, connected to the A, B, and C conductors with a single-voltage limiter, GDTAB, on the bridge output (Figure 12.29). The diodes, however, need to be rated for approximately 1 kV rated and should exhibit a low forward recovery voltage. An alternative approach is to use the differential overvoltage protection to feed the GDT (Figure 12.30). In this case, the differential voltage limiting is done by the series connection of the MOVs P1 and P2, which are exactly of the same type.18 The common mode voltage at which sparkover occurs will be the threshold voltage of the P1 or P2 protectors and the GDTAB sparkover voltage.

12.4.3

Effect of Circuit Grounding Scheme on Terminal Protection

The circuit grounding scheme has significant effect on the terminal protection scheme, particularly with respect to transient protection. Consider two cases, associated with transient protection of a DC power line, as an example19: 1) A completely “floating” circuit, where both the source and load are “floated” (i.e. ungrounded) both at the power source and at the load 2) A “single-point” grounded circuit, where the source is grounded but the load is “floated” (i.e. ungrounded) The different circuit grounding schemes may significantly impact the transient protection scheme and will be elaborated in the next sections.

18 Nevertheless, this approach may not provide adequate protection, as the two MOVs will not, normally, be perfectly identical. For instance, assuming two MOVs, MOV#1 of VC = 230V, α = 48 and RON = 0.04Ω while MOV#2 of VC = 250 V, α = 42 and RON = 0.04 Ω, both meeting the criterion of VC = 240 V ± 5%. When the voltage over the paralleled varistors is V = 300 V, MOV#1 would carry I = 345 A (99.4%) while MOV#2 would carry I = 2.1 A (0.6%), whereas when the voltage over the paralleled varistors is V = 500 V, MOV#1 would carry I = 3.7 kA (57%) while MOV#2 would carry I = 2.9 kA (43%). It follows that parallel installation of “tightly matched” (5% tolerance) MOVs may be advantageous only for very high surge currents. 19 “Multi-point” grounded circuits, although theoretically conceivable, and in fact, may often be used in digital data communication channels, for instance, is rarely used in power distribution networks, since, in such situations, return currents would mostly flow through the reference structure, owing to its lower resistance (see Chapter 4 for detailed discussion of grounding schemes). Hence, the two schemes discussed above, are considered to representative of common practice.

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12 Grounding of Terminal Protection Devices

Figure 12.31 Response of transient voltage surge protection devices on a fully “floating” circuit (illustrated for a positivelypolarized voltage surge). (a) Unidirectional avalanche diodes. (b) Bidirectional avalanche diodes. Source

VC + T% Load 2VC × T% VC – T%

×

×

(a)

Source

VC ± T% Load ~2 VC ± T%

VC ≈ 0 V

×

×

(b) 12.4.3.1 Transient Protection in a Completely “Floating Circuit”

With source and load circuits fully “floated,” any line-to-ground TVSS devices “see” approximately equal impedance to the ground reference (essentially “open circuit”) (Figure 12.31). It follows that with common-mode induced surges on both lines, both TVSSs, if selected to be equal, are expected to experience breakdown and clamp to equal levels, and theoretically, no differential-mode surge will appear across the load terminals. In reality, TVSS devices exhibit some tolerance, ±10% for typical devices, while matched devices may exhibit better matching (±1–5%) [9], which may result in some residual differential surge voltage across the lines. Assuming a nominal clamping voltage,20 VC, with a tolerance of T%, it follows that at the worst case, the residual line-to-line voltage, VL–L, appearing across the terminals of the load, is therefore, VL−L ≤ 2 × VC × T

12 14

When unidirectional avalanche diodes TVSSs (see Figure 12.19a above) are used (Figure 12.32), the level of VL–L will be as described above, when the incident voltage surge drives the diodes into their reverse breakdown mode. If, however, the incident surge is negatively polarized, the diodes will be driven into forward bias, resulting in a nominal clamping voltage of 0.7 V, approximately. In this case, the potential difference between the lines during breakdown will be VL–L 1 V. The lines are virtually short-circuited in this case.21 If bidirectional avalanche diodes are used on both lines (see Figure 12.19b above), on the other hand, clamping to either positively or negatively polarized surges will result in a much larger differential voltage, and the circuit will not be driven into almost short circuit (line-to-line).22 Consider, for instance, a “Littlefuse®” bidirectional avalanche diode SMCJ36CA installed on the power lines of a nominal 28 VDC circuit, exhibiting a minimum breakdown voltage of 40 V and a maximum breakdown voltage of 44.2 V (representing a tolerance of approximately ±5%). The maximum clamping voltage is 58.1 V for the same device, and if assuming the same tolerance, 5%, the clamping voltage may actually vary between 53 and 58.1 V, approximately, which yields approximately an average clamping voltage of 55.5 V, approximately.

20 Note that tolerances also exist in the breakdown voltage of the TVSS, which means that the device on the one line may breakdown before the one on the other line, resulting in a larger momentary differential voltage. 21 Care must be paid, particularly in power distribution circuits, to ensure that this close to short circuit between the lines will not result in undesired responses of the power distribution system due to the momentary line-to-line (almost) short circuit. 22 Ironically, this is due to the non-zero tolerance between the TVSSs on the two lines.

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

If placed in line-to-ground configuration on the power and return leads, as depicted in Figure 12.31b, the residual differential surge voltage across the two lines will not exceed VL–L ≤ × 55.5 V × 5% = 5.55 V. In either of the two cases, when the residual line-to-line surge voltage developing across the load exceeds a tolerable voltage level (e.g. the absolute maximum rating (AMR)) of the load, an additional differential (line-to-line) TVSS would be necessary (see Figure 12.31a, b) for complementary protection of the load.

I

I = 1 mA

U U = 0. 65 V

=

Transient Protection in a “Single-Point Grounded Circuit”

U

12.4.3.2

7.

–1

In the case that the circuit is “single-point grounded” (in DC power circuits, the source is typically grounded while the load remains “floated”), the situation is very different from the previous one. Generally speaking, the two TVSSs “see” different impedances to the Figure 12.32 V–A characteristics of an avalanche diode ground reference, as the TVSS on the (−) or return line may be virtu- with a reverse and forward breakdown voltages of 17 and ally short-out circuited, owing to the grounding of the return line to the 0.65 V, respectively. Source: Filip Dominec/Wikipedia/ reference structure at the source (Figure 12.33). Public Domain. It follows that with common-mode induced surges on both lines, both TVSSs, even if equal, the return (−) line and the ground reference, are approximately at equal potential, thus the TVSS on this line is virtually short-circuited by the ground connection and is expected to draw virtually no surge current. The TVSS on the (+) line, on the other hand, experiences the full surge voltage, which, in practice, appears fully across the terminals of the load, as well as between the line to the ground reference structure, with the tolerance taken into consideration, 1

V

VL−L ≈ VL−G ≤ VC × T

12 15

Two cases should be considered in this case, depending on the separation (and length of leads) between the source and the protected load, due to the fact that at fast transients, wiring inductance cannot be ignored and a surge voltage drop will develop across long wiring.23 For computation of the common-mode surge voltage drop across the individual wires of the pair, the even-mode24 inductance of the pair should be considered. Assuming the power leads are implemented as an unshielded twisted wire pair (UTP or TWP) (Figure 12.34), the distributed even-mode inductance of such a wire pair must be considered, equal to: L0e ≈ L11 + L12 H m

12 16

where L0e is the even-mode inductance of the wire pair, L11 is the self-inductance of the individual wire in the pair and L12 is the mutual inductance between the wires in the pair. From the relationship, Z 0e ≈

L0e Ω C0e

12 17

and recalling that C 0e ≈ C 11 F m

12 18

we deduce that L0e ≈ Z 0e 2 C 11 H m or 1 L0e ≈ 2 H m νp C 0e

12 19

where νp is the phase velocity (or the speed of light, c, with no dielectric present) and the second expression is derived from its definition, and when ZCM observed by the individual line is (for coupled lines, which would apply to twisted wire pairs): Z CM ≈

Z 0e Ω 2

12 20

23 In certain installations (e.g., land mobile vehicles or aircraft) power return wires are typically grounded to the chassis of the vehicle immediately near the load equipment. In such cases, and TVSS installed on the (−) or return line inside the equipment is fully short-circuited by the chassis connection. 24 Even- and odd-mode propagation are discussed in Chapter 2.

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12 Grounding of Terminal Protection Devices

Figure 12.33 Response of transient voltage surge protection devices on a “single-point grounded circuit” (illustrated for a positively-polarized voltage surge). (a) Unidirectional avalanche diodes. (b) Bidirectional avalanche diodes VC ± T%

Source

Load ~VC ± T% VC ≈ 0 V

×

(a)

VC ± T%

Source

Load ~VC ± T% VC ≈ 0 V ×

(b)

Assuming typical values of C0e ≈ 4 pF/m and νp ≈ c, we obtain L0e ≈ 2.77 μH/m.

D S

Figure 12.34 Model of twisted wire pair (TWP) for inductance estimation. Source: EETech Media/EETech Media, LLC.

a) Very small separation between source and load: When separation between source and load (and hence, length of the wiring) is very small, inductance of the wiring can be assumed to be negligible and the return line at the input to the load is practically “grounded,” effectively short-circuiting the TVSS as described above. b) Large separation between source and load: When separation between source and load (and hence, length of the wiring) is large, inductance of the wiring cannot be ignored and the return line at the input to the load is “grounded” through the high inductance, i.e. a large surge voltage drop will occur across the line, V L − G ≈ − L0e

di V dt

12 21

where i is the peak surge current, t is the surge front time. For a 2 kA peak 8/20 μs25 surge waveform, di/dt ≈ 2 kA/8 μs = 250 A/μs. Using the above typical inductance, and assuming wiring between source to load only 2 m in length, this voltage drop can be as high as 690 V/m, approximately, or 1.38 kV, total. As long as this surge voltage exceeds the breakdown voltage of the TVSS, both TVSSs on both lines will, in fact, be activated, and hence the residual line-to-line voltage will be as in the case for the “floating” circuit, as shown in Equation (12.14) above (repeated here for convenience. VL−L ≤ 2 × VC × T

•

12 22

The Least You Need to Know Performance of terminal protection devices, particularly transient voltage surge suppressors (TVSS) strongly depend on differential circuit grounding schemes, particularly in power distribution networks.

25 See, for instance, IEC-61000-4-5, “Electromagnetic Compatibility (EMC) – Part 4–5: Testing and Measurement Techniques – Surge Immunity Test.”

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

• • • •

In completely (source and load) “floated” circuits, when both lines are equally exposed to a common-mode surge, and protected by identical line-to-ground TVSSs, the residual line-to-line surge voltage appearing across the load is directly dependent on the tolerance of the devices; the smaller the tolerance, the lower the residual voltage. In “single-point” grounded circuits (e.g. source is grounded but load is left “floating”), with a similar protection scheme, the residual line-to-line voltage surge depends on length of the leads between source and load. When separation is small (i.e. short wiring), the TVSS on the grounded return line is virtually short circuited and is not activated. The TVSS on the (+) line develops the full clamped surge voltage across the load terminals. When separation is large (i.e. long wiring), high surge voltage develops across the inductance of the wiring between source and load and the TVSSs on both lines will be activated, with resultant small residual voltage across the load terminals (as in fully “floated” circuits).

12.4.4

When Is Ground Not Equal to Ground?

The above discussion has shown the importance of identifying the scheme or protection, matching the mode of interference and surges. For the purpose of common-mode protection, well-grounded terminal protection circuits should be implemented. The design and installation of terminal protection devices (TPDs), such as filters and transient-suppression devices (TVSSs) and circuits are an art as well as a science. Much depends on parasitics characterizing the components and their installation practices, for which bonding and grounding of the terminal protection circuit elements are of particular importance. As shown above, terminal protection devices such as TVSSs and EMI filters operate primarily by shunting the interference energy to a return path (i.e. the return conductor or the signal reference structure for DM and CM protection, respectively) or reflecting it back to the source. For effectively accomplishing these objectives, the return path must introduce minimal series impedance to the shunted current at all frequencies of interest. Unfortunately, parasitics, particularly inductance, often counteract the opportunity for establishing low-impedance grounding, thus impairing performance. Common-mode (CM) filters, in particular, are intended to shunt undesired high-frequency energy to a signal reference structure or chassis by means of CM capacitors. Figure 12.35 depicts the CM section of the power-line filter from Figure 12.14 above, containing an ideal CM capacitor, CY. Capacitors have intrinsic parasitic attributes: ESR (equivalent series resistance) and ESL (equivalent series inductance).26 As a result of predominantly inductive effects, every capacitor will exhibit capacitive reactance up to its self-resonant frequency. Above this frequency point, the capacitor behaves as an inductive element. Figure 12.36 illustrates the intrinsic impedance and the insertion loss (in a 50 Ω/50 Ω source/load resistance circuit) of an ideal and “real-world” 10 nF capacitor. In addition to intrinsic parasitic attributes, installation of a capacitor cannot be ignored, as the length of its leads adds to the capacitor’s total equivalent inductance. The longer the device leads, the higher the parasitic inductance, which will degrade higher-frequency performance. The significance of bonding terminal protection devices to a reference structure (for common-mode protection) cannot be overemphasized. In particular, when a filter is used at a point of entry for a wire traveling through an enclosure shield, the desired effect is accomplished by directly bonding the filter return, usually the chassis, to the shielding barrier. A poor bond will compromise the filter’s insertion loss beyond the effect of the parasitic attributes of the filter itself. The consequences of poor bonding of a common-mode, π-section filter are depicted in Figure 12.37 [3, 7, 10]. If the return side of the filter, usually the housing, is inadequately bonded to the signal reference structure (the equipment case or rack), bond impedance, ZB, may be sufficiently high to impair the filter’s performance. As shown, the filter constitutes a low-pass filter intended to remove high-frequency interference signals from the line. The filter achieves its goal in part due to the low reactance of the shunt capacitor, XC, at a frequency of the interference current. Interfering signals present on input lines should normally ESR/2 be blocked by the inductive reactance, ωL, and shunted to the signal reference structure along the intended Path 1, thereby staying away from the load impedance, ZL. InterferESL/2 ence currents will still follow undesired Path 2 to the load if, on the other hand, the bonding impedance of the filter, RLeakage Cy Cy ZB is highly relative to the capacitive reactance in series with LCM the load impedance: ESL/2 1 + ZL jωC

Cy

< RB + jωLB

12 23

The effectiveness of the filter at high frequencies could thus be severely compromised, even before the condition spelt out

ESR/2

Figure 12.35

Nonideal properties of Y capacitors.

26 The non-ideal nature of passive circuit elements and interconnects was discussed in detail in Chapter 2.

685

12 Grounding of Terminal Protection Devices 100.00

Ideal capacitor

Impedance (Ω)

10.00

1.00

Real world capacitor 0.10

0.01 1

0.1

10

100

Frequency (MHz)

(a) 90 80

Ideal capacitor 70

Insertion loss (dB)

686

60

Real world capacitor

50 40 30 20 10

in Equation (12.23) has been reached (see also Figure 12.39). The circuit schematics depicted in Figure 12.38a, b were analyzed using PSpice27 for both well-bonded and poorly bonded π-section low-pass filter (LPF), respectively, for illustrating the effect of poor bonding on filter performance. The simulation results (Figure 12.39) clearly reveal dramatic transformation in the performance of the filter circuit as frequency increases. At lower frequencies, well below the filter resonant frequency (50 MHz, approximately), the LPF functions as intended. The bonding impedance is too low to have any significant unfavorable consequence and the interference current flows through Path 1 (see Figure 12.38). At higher frequencies, the impedance of a poor bond connection, ZB, dominates the filter’s performance. The interference current can now take either of two alternate paths, constituting the least of two evils; Path 1 which produces the smallest loop area (the path of least intrinsic inductance), or Path 2, bypassing the blocking inductor through the filter’s capacitors, returning through the load impedance, ZL. The loop impedance of this path may be higher, however, if Equation (12.23) prevails, the poor bond impedance value will be added to the loop impedance, exceeding that of Path 2, which now constitutes the path of least impedance. Consequently, the filter cannot fulfill its role, and the load is not protected. In effect, the filter undergoes a “metamorphosis” from a low-pass to a high-pass filter. A similar situation, with greater potential for harmful impact on a circuit or system’s integrity, occurs when transient currents discharge through the above circuit. Fast transients constitute high-frequency, high-energy phenomena. The incident current transient, IT(t), produces a high-amplitude transient voltage, VB(t), across an (inadequate) bond impedance, ZB (Figure 12.40) [7]:

0

1

0.1

10

100

1000

V B t = RB I T t + L B

dI T t dt

12 24

Frequency (MHz)

where RB and LB represent the bond resistance and inductance, respectively. Not only will the filter not protect the differential load connected between its terminals but may also physically damage it Figure 12.36 Frequency response of and ideal (C = 10 nF) and “real-world” (C = 10 nF, LS = 5 nH, RS = 2 mΩ) capacitor. due to breakdown resulting from high voltages developing across the bond impedance, which may subsequently appear across the load. (a) Intrinsic impedance of capacitor. (b) Insertion loss of the capacitor in a 50 Ω/50 Ω circuit. Actually, the filter itself could also be severely damaged from the transient event. Transient suppression devices would probably be used before the filter to eliminate this threat. However, similar concerns apply to the installation of these devices. The following example illustrates adverse effects of lead inductance on grounding of an MOV (Figure 12.41). (b)

ZS C

ES

Figure 12.37 Effect of poor bonding on the performance of a π-section low-pass filter.

L

Intended path

p-section LPF

LB

C

Unintended path

}Z

1

B

ZL

2

RB Signal reference structure

27 “PSPICE” is a trademark of Cadence Design Systems; Evaluation Version 9.1. Web Update 1, Level 000, Build 101 was used for the purpose of the above simulations.

Figure 12.38 PSpiceTM simulation models for evaluation of the effect of poor bonding on the performance of a π-section low pass filter. (a) Model of a basic filter circuit with zero impedance bonding. (b) Model of a poorly bonded filter circuit.

ZS = 50 Ω

RL = 1 mΩ

L = 2 μH

RC = 3 mΩ ES

1V C = 0.5 nF

ZL = 50 Ω

VL

ZL = 50 Ω

VL

(a) π-section low pass filter

ZS = 50 Ω

RL = 1 mΩ

L = 2 μH

RC = 3 mΩ C = 0.5 nF ES

1V LB = 0.5 nH

Intended path

RB = 1 mΩ

1

}

ZB

Unintended path 2

Poor bond impedance, ZB

(b)

Figure 12.39 PSpiceTM simulation results for good and poor bonding of a π-section low-pass filter.

90 80

Insertion loss (dB)

70 60 50 40 30 20 10 0 0.01

0.1

1

10

100

Frequency (MHz)

Figure 12.40 Effect of poor bonding on the transient operation of π-section low-pass filter. Incident transient

Transient voltage appears across load impedance, ZL

LB RB

}

Transient voltage develops across bond impedance, ZB

1000

688

12 Grounding of Terminal Protection Devices

Penetrating surge current

From transient source

Protected line to equipment load

Lh

Line connection lead model

Ch Rh

Shunted surge current

Lm ROff

Rg

Cm

Actual voltage surge Ideal clamped voltage surge

MOV model

Lg

Ground connection lead model

Cg Rg

Internal ESGC lead

Grounding conductors

Figure 12.41

Adverse effect of lead inductance on protection level provided by an MOV TVSS. Lead inductance further worsens the situation

Input/ line

Output/ load

TPD

“Virtual ground”

LB

}

RB

ΔV Transient/EMI voltage across the bond impedance, ZB

Assume that a vulnerable circuit is installed with a lineto-chassis MOV to provide a common-mode protection voltage level of 30 V. The physical leads of the MOV are 4 cm long and are assumed to exhibit a typical inductance of 10 nH/cm (and negligible resistance), resulting in a total inductance of 40 nH. For a 50 A peak common-mode transient with a front time of 10 ns,28 the maximum voltage across the terminals of the vulnerable device is, approximately, V L = LLeads

dI Surge 50 A ≈ 40 nH = 200 V dt 10 nS

30 V “Actual ground”

12 25

Obviously, the circuit can hardly be considered “protected” and could be severely damaged. Figure 12.42 When is a ground not a ground? We finally arrive at the reply to the question “when is a ground not a ground?” Whenever there is nonzero impedance between two circuit elements. The terminal protection device in Figure 12.42 is intended to protect a sensitive load from incident EMI and transients appearing between the line and the “ground” (signal reference structure). However, due to poor bonding of the transient-voltage surge suppression device (TVSS) circuit, the “ground” terminal of the TVSS denoted the “virtual ground” in Figure 12.42 is not at the same voltage potential as the “actual ground,” or signal reference structure. The two can be many volts apart in case of a transient. It is noteworthy that in cases of differential (line-to-line) protection devices, the same concerns apply to the leads connecting the devices to the lines. Signal reference structure

28 A typical “early time” Nuclear EMP waveform based on IEC (International Electrotechnical Commission), International Standard 61000-2-10, Electromagnetic compatibility (EMC), Part 2–10: Environment – Description of HEMP Environment – Conducted Disturbance, Geneva, Switzerland, First Edition, November 1998.

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

12.4.5 Practices for Mounting and Grounding/Bonding of Terminal Protection Devices (TPDs) The principal cause of failure of terminal protection devices is improper mounting and grounding of the devices. EMI filters are intended to effectively suppress conducted interference at frequencies ranging from hundreds of kHz to frequencies well beyond 1 GHz, while transient suppression devices (TVSSs) are intended to suppress fast electrical voltage or current transients. If good performance of the filter or TVSS is to be achieved, particularly at higher frequencies and transient slew rates, it is absolutely necessary to follow certain installation and grounding/bonding guidelines. Two mounting faults are often commonly observed:

Equipment enclosure

Power line input to equipment

Power line Filter

Input

Good metal-to-metal contact

Figure 12.43

Bulkhead mounted power line filters for

1) High-impedance connection to the ground reference/chas- optimal filter performance. sis. The RF impedance between the device terminals and the ground reference or chassis must be kept as low as possible. Inductive chassis connections will result in serious degradation to the filter insertion loss or transient suppressor clamping voltage. 2) Capacitive bypass of the TPD. Separation of input and output wiring is mandatory in order to minimize capacitive coupling between the protected lines and the nonprotected leads carrying the interference. This is achieved by placing filters at equipment boundaries. This precludes coupling from input wires carrying interference signals directly to the output wires, thus circumventing and nullifying the effects of shielding and filtering. Both of the above mounting flaws can be readily mitigated by the use of bulkhead-mounted filters such as the one shown in Figure 12.43. The TPD (a power-line filter in this case) is directly mounted on and bonded to the enclosure’s boundary. While certain best mounting and grounding/bonding practices apply to almost all TVSS installations, the installation process for each device may slightly differ. Due to this variation, consulting the product literature for the particular device installation and application would be beneficial. With that in mind, the following are some of the most important recommended installation practices for terminal protection devices in the following sections. 12.4.5.1

Optimizing Filter Grounding – Feed-Through Capacitors and Filters

Feed-through capacitors and filters29 are three-terminal devices designed to reduce lead inductances. Feed-through filters are shown in Figure 12.44. In (a), a standard capacitor is shown. One electrode is connected to a metal chassis, while the other terminal is attached to the protected line. The lead bond wires to the electrode plates contain undesired inductance that limits high-frequency performance. In (b), the inductance of the lead between the protected line and one electrode is eliminated;

Protected line

Signal reference structure

(a)

Protected line

Signal reference structure

(b)

Enclosure structure

Protected line

(c)

Figure 12.44 “Transformation” from a standard two-terminal capacitor to a three-terminal feed-through capacitor. (a) Standard line to chassis (CM) capacitor. (b) Three-terminal line to chassis (CM) capacitor. (c) Feed-through (CM) capacitor.

29 Even though the discussion covers mainly capacitors, it could easily be extended to composite filter circuits, considering the fact that in L–C filter networks grounding considerations apply to the capacitors and in that context, the discussion in this Section applies just as much to the capacitors incorporated in such filter circuits.

689

690

12 Grounding of Terminal Protection Devices

Line to be bypassed/filtered

Lead

Metal housing/ case

Enclosure

Feedthrough bus

Epoxy

Ground foils

Solder “Hot” foils

Capacitor Epoxy

Figure 12.45

Construction of a three-terminal feed-through capacitor. Source: VertMarkets, Inc.

however, the grounded electrode still has one long connection lead to chassis. In (c), the two electrodes are scrolled around each other. One electrode of the capacitor is now connected to and actually forms the feed-through housing (“ground”), while the protected line is directly attached to the other electrode, literally “fed through” the device. Feedthrough filter Figure 12.45 shows the actual construction of a feed-through capacitor. A wound foil is made with an extended foil-type construction so that each plate of the capacitor can be soldered to a washer-shaped terminal. One washer is then soldered to the center lead, while the other washer is soldered to the case that is identified as the ground terminal. The theoretical insertion loss of three-terminal capacitors is the same as for an Metallic equipment ideal two-terminal capacitor. However, the insertion loss of a practical threeenclosure terminal capacitor follows the ideal curve much more closely than does a twoterminal capacitor. The useful frequency range of a feed-through capacitor is Figure 12.46 Mounting of feed-through filters/ capacitors. improved further by its case construction, enabling a bulkhead or chassis enclosure to isolate the input and output terminals from each other. The lead inductance in a feed-through capacitor is not part of the shunt circuit. Compared with leaded devices, an insertion loss feed-through filter is not degraded as rapidly with an increase in frequency. Consequently, whereas the short-lead construction capacitor is ideally suited for EMI suppression in the frequency range of up to and even exceeding 1 GHz, feed-through capacitors generally exhibit close to ideal performance up to 1 GHz with a self-resonance frequency well above that frequency. The practical mounting of feed-through capacitors (or filters) is illustrated in Figure 12.46. As illustrated schematically in Figure 12.47a, feed-through filters provide a solid, direct metal-to-metal bond to the mounting surface. Poor mounting of the feed-through filter, for instance by mounting them on a bracket and using jumpers (i.e. indirect bonding) to the surface (Figure 12.47b) as it will preclude the device for providing its necessary performance due to inductance of the bond. Feed-through capacitors may also be combined with lossy (ferrite-based) filter elements, expanding them into common feedthrough filter configurations – “T,” “π,” and “L” sections (Figure 12.48), where ferrite beads or inductive elements are threaded Filter circuit Feedthrough pin Metallic equipment case

Mounting nut

(a)

(b)

Figure 12.47 Proper and poor mounting of feed-through filters/ capacitors. (a) Proper mounting. (b) Poor mounting.

Integral ferrite bead

Threaded part of enclosure

Figure 12.48 Feed-through L–C filter configuration (“L”-section filter illustrated).

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

(a)

(b)

(c)

Figure 12.49 Electrical schematic symbols of a feed-through capacitor. (a) Electrical symbol of a short-lead two-terminal capacitor. (b) Electrical symbol of a feed-through capacitor. (c) Practical equivalent circuit of a feed-through capacitor.

on the feed-through bus inside the package of the filter. In addition, certain feed-through devices incorporate transient suppressor devices, such as avalanche diodes or MOVs between the line and the case. The commonly used circuit schematic symbol of the three-terminal and feed-through capacitors are provided in Figure 12.49a, b, respectively. A practical three-terminal feed-through capacitor schematic is illustrated in Figure 12.49c. As mentioned above, the lead inductance in a feed-through capacitor is not part of the shunt circuit; however, the parasitic lead inductance of the capacitor allows the three-terminal capacitor to act as a “T”-section filter, further enhancing its intended performance. 12.4.5.2

Filter Connectors

Another form of filter that provides excellent bonding is the filter connector. Filter connectors are an extension of the concept of feed-through filters while offering reduced size and improved performance compared to discrete passive elements, and serve as an efficient, compact, and cost-effective solution when multiple lines must be filtered. Capacitors as well as lossy (ferrite-based) filter elements are built directly into a connector assembly, offering low-pass filter performance. Due to their effective feedthrough filtering characteristic, connectors with integral capacitors with values as low as 100 pF provide effective bidirectional suppression of unwanted interference traveling into and out of equipment enclosures at frequencies ranging from several up to hundreds of MHz. Similar to feed-through filters, filtered connectors incorporate the popular “T,” “π,” and “L” section filter circuits and are available in D-Type, Micro-D subminiature, cylindrical connectors, and RJ-45, as well as other less common types (e.g. ARINC), both in plug (“male”) and receptacle (“female”) configurations. One of the most commonly used filter connector technologies is the filter-pin connector, in which the filter elements are incorporated within the connector contacts themselves (Figure 12.50). Grounding of the feed-through capacitive elements incorporated in the contacts is achieved by means of the grounding plate included in the connector assembly. Another filter connector technology utilizes planar array filter devices [11]. Planar array filter connectors, widely used, contain ceramic capacitor arrays and ferrites that externally surround each contact (Figure 12.51). A planar array can be designed with different capacitive values on individual and pin groupings and can also be selectively equipped with transient suppression devices (e.g. avalanche diodes or MOVs), providing protection against voltage fast transients surges from such sources as HA-EMP, lightning, or electrostatic discharge (ESD). The incorporation of filter assemblies into a standard cylindrical or rectangular connector will often increase the overall length of the shell, typically at the non-mating side of the connector receptacle (inside the enclosure). Grounding plate

Hard insert

Contact filter assembly

Ferrite

Pin contact

Interface seal Encapsulation Capacitor Gasket

Connector shell

(b)

(a) Figure 12.50

Filter-pin connector. (a) Filter-pin connector assembly. (b) Contact filter assembly

691

692

12 Grounding of Terminal Protection Devices

(a)

(b)

(c)

Figure 12.51 Multiway planar array filter connector. (a) Integrated cylindrical connector incorporating a planar array filter assembly. (b) Planar array filter assembly, assembled including its ferrite elements and connector contacts, ready for insertion into the connector shell. (c) Cross-sectional view of a planar array filter connector. Note the ferrite elements sandwiched between the ceramic capacitors. Source: Courtesy of Glenair, Inc.

Another drawback of filter connectors is their relatively high cost. In particular, failure of a single pin element often entails the replacement of the entire filter connector, as individual pins or planar components cannot typically be replaced due to the manner of construcFilter tion of the connectors. The decision whether to use filter connector connectors in lieu of standard feed-through or other filtering techniques should be based on considerations regarding cost of filter connector assemblies versus discrete filters, available space, labor involved in construction, and flexibility of design. Filter connectors provide high-density, multiple-line filtering and generally require less space for mounting Figure 12.52 Bulkhead mounted filter connector. than a connector/filter/doghouse assembly (described herein). Also, bonding of the filter connector to the enclosure provides the necessary effective low-impedance grounding of the filter elements (Figure 12.52).

12.4.5.3 Optimizing Filter Grounding – PCB Layout Issues for Transient-Voltage Protection

When use of either of the above-described feed-through techniques is not desired, either because of cost or long lead time concerns, effective terminal protection can be accomplished by discrete filter elements installed on the printed circuit board (PCB). PCB-mount connectors may be connected directly to the PCB, and terminal protection devices are then mounted directly on the PCB, at proximity to the connector pins. A chassis/ground reference plane, if provided in the PCB, enables low-impedance grounding/bonding of the filter capacitors or TVSSs and must be connected to the equipment enclosure immediately behind the connector for minimizing the length of the wiring leads that could receive or transmit radiated EMI (Figure 12.53). The placement and manner of connection of the components on a PCB, and routing of their traces, Grounding stud of PCB is vital if the required filtering or transient protection Ground plane to equipment Daughter boards is to be attained. Figure 12.54 sketches the details for enclosure a filter or TVSS. As most sources of EMI, including transients PCB including chassis (emitted or coupled into the equipment) are mostly ground plane common-mode in nature, filtering or transientprotection are implemented in the line-to-ground Discrete filter (chassis) scheme. Differential-mode filtering or tranelements Motherboard sient suppression is implemented as line-to-line Flex print (however, the principles outlined herein shall apply appropriately to that application as well). Two key considerations are essential for successful Figure 12.53 Filters mounted on a printed circuit board behind the design (Figure 12.54): connector.

12.4 Grounding and Bonding of Filters and Transient-Voltage Surge Suppression (TVSS) Devices

Figure 12.54 Correct (upper) and incorrect (bottom) PCB layout issues for common-mode suppression by filters or TVSSs. (a) Acceptable. (b) Objectionable. Source: Courtesy of Keith Armstrong, Cherry Clough.

The trace to be suppressed must pass through the TVSS terminal pad Point of entry, e.g. connector pad Minimum length “breakout” trace for connection to ground plane (Via-in-pad is best)

(a) Point of entry, e.g. connector pad Never use “stub” connections from trace for TVSS connection to ground plane

(b)

• •

The terminal protection circuit should be placed as close as possible to the point of entry/exit (POE) of the protected line (i.e. “within the connector zone,” near the connector pins) in order to minimize externally induced EMI/transients from being drawn into the circuit and to preclude coupling to internal circuits (through “crosstalk mechanism,” before the interference is suppressed by the TPDs. Conversely, if emissions are of concern, placing the devices in proximity to the POE will preclude pickup of EMI from adjacent circuit after the protection devices. The leads of the devices should be kept as short as possible. Preferably, the line trace should pass through the TPD terminal’s pad. This is essential for minimizing the series lead inductance of the device. Consider, for instance, an IEC/EN 61000-4-2 ESD test introduced at a level of 8 kV, which could generate a di/dt current transient in excess of 43 A/ns. A short (1 mm long) wide 1 mm (40 mil) trace, routed over a ground reference plane, will exhibit a self-inductance in the range of 0.3–0.6 nH (depending on its height above the plane). With an ESD transient current slew rate of 43 A/ns, the resultant peak voltage drop along the 1mm trace will be between 13 and 26 V. Furthermore, the via hole to the reference plane illustrated in Figure 12.50 also exhibits self-inductance. Assuming a twolayer 1.6 mm thick PCB, the length of the via hole carrying the transient ESD current is 1.6 mm, resulting in a self-inductance of 1.6 nH. The voltage-drop across such a via hole due to the 43 A/ns current transient would amount to 70 V peak, approximately. The TVSS device itself will also introduce internal series resistance and self-inductance, which further increases the transient voltage. It follows that even a short trace connecting the transient voltage surge suppressor (TVSS) to the via hole in Figure 12.54 would dramatically degrade the effectiveness of the transient suppression [12].

The very best PCB-mount terminal protection devices are three-terminal types like the three-terminal filter device illustrated in Figure 12.55. To obtain the best performance from such devices, they should be used with at least two parallel vias to their ground reference plane, arranged symmetrically around the device and very close to it. Also, the PCB dielectric between the reference plane layer and the layer on which the suppression device is mounted should be as thin as is practical [12].

12.4.5.4

Mounting Practices – “Doghouse Mounting”

The preferred method of installing feed-through filters in equipment used in a highlevel electromagnetic environment is to mount the TPDs in a metal enclosure behind the front panel (known as a “doghouse”). This enclosure can be constructed with an access panel on one of the sides. However, the panel should be attached to the doghouse using a conductive gasket for obtaining an effective seal (Figure 12.56). This configuration is commonly used for power-line filtering. Signal-line terminal protection is commonly applied using tubular feed-through devices described above. The TPD is installed on a bulkhead or enclosure case, threaded through a properly machined hole that provides perfect bonding of the TPD to the bulkhead. This method is of particular use in RF and microwave assemblies. For many signal lines, brackets containing multiple feed-through devices can be used (Figure 12.57).

Figure 12.55 Three-terminal terminal protection device (illustrated is a TDK feedthrough capacitor surface mount capacitor). Source: TDK Corporation.

693

694

12 Grounding of Terminal Protection Devices

Equipment enclosure

Figure 12.56 mounting.

“Doghouse” configuration of power line filter

Figure 12.57

Bulkhead mounted feed-through filters.

Power line input to equipment Good metal-to-metal contact

Filter

Power line input

“RF tight” bulkhead

Feed-through filters

The doghouse concept can similarly be implemented with feed-through TPDs, offering similar advantages as those described for power-line entry. Alternate configurations of this technique are depicted in Figure 12.58. When using feed-through filters, a bulkhead method of installation must be implemented. Mounting of feed-through TPDs in the flawed manner shown in Figure 12.59 does not provide the full benefits of the feed-through TPDs and can even enhance interference and coupling. The installation of the feed-through TPDs on a mounting bracket does not provide a solid barrier between the filtered and nonfiltered zones, and, worse still, grounding of the filters is achieved through a bracket that ultimately introduces nonzero impedance between the filter housing and the enclosure of the equipment.

Figure 12.58 Doghouse mounting of feedthrough filters.

Feed-through filters Feed-through filters

Doghouse entry

Doghouse entry

References

Figure 12.59

A flawed application of feed-through filters. Mounting bracket

Feed-through filters

EMI coupling

• • •• •

The Least You Need to Know Effectiveness of terminal protection devices is strongly dependent on the grounding scheme of the system, particularly when transient-voltage surge suppression devices are concerned (due to the incident high voltages). Special care must be taken in the installation of terminal protection devices (TPDs), such as filters and transient suppression devices, ensuring sufficiently low ground impedance. Parasitics are detrimental to the performance of TPDs, requiring careful control of their installation. Inadequate grounding of a suppression device may significantly degrade the devices effectiveness. Bulkhead-installed filters, in which the TPD is directly mounted on the enclosure’s boundary, provide optimal grounding and preclude EMI bypass of the device.

References 1 Clark, T.L., McCollum, M.B., Trout, D.H., and Javor, K. (1995). NASA Reference Publication 1368, Marshall Space Flight Center

2 3 4 5 6 7 8 9 10 11 12

Electromagnetic Compatibility Design and Interference Control (MEDIC) Handbook, CDDF Final Report, Project No. 93-15, Alabama (June 1995). Ott, H.W. (2009). Electromagnetic Compatibility Engineering. New York: Wiley. Hartal, O. (1994). Electromagnetic Compatibility by Design. W. Conshohocken, PA: R&B Enterprises. Nave, M. (2003). Power Line Filter Design for Switched-Mode Power Supplies. New York: Van Nostrand Reinhold. MIL-HDBK-419A (1987). Military Handbook, Grounding, Bonding, and Shielding for Electronic Equipments and Facilities. Washington, DC: U.S. Government Printing Office. Kut, T., Lücken, A., Dickmann, S., and Schulz, D. (2014). Common mode chokes and optimisation aspects. Advances in Radio Science 12: 143–148. MIL-HDBK-232A (1987). Military Handbook, Red/Black Engineering – Installation Guidelines. Washington, DC: U.S. Government Printing Office (March 1987). Standler, R.B. (1989). Protection of Electronic Circuits from Overvoltages. New York: Wiley Interscience. Clark, M. and Walters, K. (2008). Parallel Stacking of TVSs For Higher Surge Currents. Microsemi MicroNoteTM 113, Rev. A (July 2008). Department of the Navy, Naval Air Systems Command (1988). NAVAIR AD 1115, Electromagnetic Compatibility Design Guide for Avionics and Related Ground Support Equipment, 3e. US Department of the Navy (June 1988). (2005). EMI/EMP Filter Connector Designer’s Guide Plus Series 801 “Mighty Mouse” Filter Connectors. Glendale, CA: Glenair, Inc. Armstrong, K. (2008). Design techniques for EMC part 6 – ESD, electromechanical devices, power factor correction, voltage fluctuations, supply dips and dropouts. The EMC Journal 2–13.

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13 Grounding on Printed Circuit Boards 13.1

A Bird’s Eye View on Signal Integrity (SI), Power Integrity (PI), and EMC

All EMI problems begin and end in the PCB!!! A design and layout engineer, having been working on PCB designs most of his career, with particular experience in layout and routing of high-speed digital circuits, or mixed analog/digital circuit, probably holds the following truth to be self-evident: That grounding and layout recommendations in component application notes should be taken with a grain of salt. It’s not that these notes are always wrong, but the recommendations can be easily taken out of context. It turns out that for successful design of PCBs, particularly as it pertains to grounding, a deep understanding of the function(s) of grounding on PCBs is an absolute necessity. “What is the primary use of a ground plane and when should it be used?” This question, commonly asked by novices, refers to a key issue in the design of printed circuit boards (PCBs) for achieving EMC, power, and signal integrity (EMC + SI/PI). The instinctive (and facetious) reply by experts may be: “A ground plane is where the airplane lands” or “a ground plane is used if there isn’t enough room for an airplane.” However, the question is a valid one, as it relates to one of the most (if not the most) important measures applied in modern high-speed digital design circuits, that of grounding implementation on printed circuit boards. From a bird’s eye view of a printed circuit board, three aspects, different, yet inter-related, must be considered, namely (Figure 13.1): a) Signal Integrity, i.e. a set of measures to ensure the desired quality of an electrical signal transmission. Some of the key issues of concern for signal integrity are ringing, crosstalk, ground bounce, distortion, reflection, dispersion, signal loss and power supply noise (Figure 13.1b). b) Power Integrity, i.e. a set of measures to ensure the desired quality of power, voltage and current delivery. There are several coupled aspects of PI: on the chip, in the chip package, on the circuit board, and in the system. Some of the key issues must be resolved to ensure power integrity at the printed circuit board level are DC and AC voltage drop and control the DC voltage level at the load at high currents, switching noise1 (a.k.a., synchronous switching noise, simultaneous switching noise, or simultaneous switching output (SSN or SSO)) and voltage ripple (Figure 13.1c). c) EMC, i.e. the ability of electrical equipment and systems to function acceptably in their electromagnetic environment, by limiting the unintentional generation, propagation and reception of electromagnetic energy, which may cause unwanted effects such as electromagnetic interference (EMI) or even physical damage in operational equipment. Some of the key issues of concern for EMC on the PCB are near-field coupling and radiated emissions (Figure 13.1d). When conjoined, these three aspects of PCB design may be termed “Electrical Integrity (EI),” i.e.: SI + PI + EMC = “ Electrical Integrity”

1 Switching noise is erroneously called also “ground bounce.” However, this phenomenon is not restricted to the ground circuit only, but rather to the power distribution network as a whole. Recall, that with respect to AC, VCC (power) and GND (return) are at equal AC potential although they differ in their DC potentials. Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

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(a)

+ DC –

+ DC –

(b)

(c)

+ DC –

(d) Figure 13.1 A bird’s eye view on SI, PI and EMC. (a) The “Bird’s Eye View” (b) Signal integrity (SI): signal transmission issues: attenuation, reflection, dispersion, interference, crosstalk. (c) Power integrity (PI): power delivery issues: voltage drop, switching noise, crosstalk. (d) Electromagnetic compatibility (EMC) issues: near field coupling, radiated emissions. Source: Axonite / Pixabay.

The interactions between these three aspects are strongly associated with grounding on the PCB (Figure 13.2). As will be demonstrated in this chapter:

• • •

SI PI Interaction: Signal I/O output switching produce switching noise in the power distribution network (PDN). Conversely, noise in the PDN may couple onto signal transmission lines and introduce distortion and disruption of signal integrity. SI EMC Interaction: Signal transmission lines, when incorrectly routed (for instance when signal return paths are disrupted) may produce “ground bounce” and couple to I/O ports of the equipment, eventually ending up as conducted band subsequently radiated EMI emissions from the I/O cables. Conversely, EMI coupled onto I/O cables (susceptibility issues) may penetrate the equipment, and, if improperly filtered, eventually end up at the PCBs and result in distortion and interference to the signal circuits. And finally, PI EMC Interaction: Similar to the abovementioned SI EMC interaction, interference, such as ripple and switching noise (“ground bounce”) on the PDN, when incorrectly designed (for instance improper power decoupling or improper pairing of power and ground planes) may couple to power and I/O ports of the equipment, eventually ending up as conducted band subsequently radiated EMI emissions from the power and I/O cables. Conversely, EMI coupled onto power and I/O cables (susceptibility issues) may penetrate the equipment, and, if improperly filtered, eventually end up at the PCBs and result in distortion and interference being introduced into the power distribution network.

13.2 Interference Sources on the PCB

Signal Integrity (SI) SI/PI

Power Integrity (PI)

Bandini Mountain Mode Conversion Power Rail Noise On-Die Interference Reflection Noise Induced Core Logic Voltage Noise Transmission Line Routing Jitter Power Loop Inductance Skin Effect Power Supply Induced On-Package Capacitance Attenuation and Loss Coupling Controlled-ESR Capacitor Dispersion Signal-Cavity Coupling Decoupling Capacitors Selection Current Return Path Interplane Capacitance Impedance Matching SI/PI/EMC Electromagnetic Bandgap Noise Margin Embedded Capacitance Return Path Discontinuities Microstrip/Stripline Bulk Capacitors Cavity Resonances Eye Pattern X2YTM Capacitor Common-Impedance Reflection Delta-I Noise Signal Routing near PCB Crosstalk PI/EMC Edge SI/EMC Timing Power Inrush Current Return Vias and Bypass Jitter Delivery Mode Conversion and Cavity Resonances Capacitors Path Common Currents PCB Edge Radiation Signal Ground Bounce Path Common-Mode Large Current Transients Rejection Power Supply Design Board to Board Coupling Power Line Filters I/O Coupling Common Currents

Electromagnetic Compatibility (EMC) Conducted EMI Radiated EMI Near Field Effects Accidental Antenna

Far Field Effects Common-Mode Chokes Ground Loops Shielding, Filtering

Radiated Path

Figure 13.2

Interfacing aspects of SI, PI and EMC.

As stated above, all EMI problems begin and end on the printed circuit board. Interference reduction forms, therefore, a significant design issue in most electronic systems. Along with other performance considerations, interference is an omnipotent factor that must be dealt with for a successful design. Much has been written in previous chapters about system-wide grounding considerations for EMI control. In this chapter, attention will be paid to the design and implementation of grounding on PCBs, particularly as it pertains to the three aspects of SI, PI, and EMC.

13.2

Interference Sources on the PCB

PCBs constitute a compact electronic system encompassing a large number of components, often mounted in high density on a single board, making efficient power distribution and controlled signal propagation possible. An insulating substrate material (usually FR4, an epoxy/glass composite) with copper plating on both sides has portions of copper etched away to form conductive paths. A number of layers of plated and etched substrates are glued together in a stack with additional insulating substrates in between the etched substrates. Holes are drilled through the stack. Conductive plating is applied to these holes, selectively forming conductive connections between the etched copper of different layers. In recent years, PCBs have become smaller, lighter, much higher layer counts and more complex. Multilayered and flexible circuit PCB designs allow for vastly more operational functionality in electronic devices, with increasingly smaller and lower cost PCBs. Indeed, recent progress such as in the transition to ultrahigh-speed signal propagation (typically considered at frequencies exceeding 10 GHz), where special substrate materials and higher tolerances are typically required, yet it would not be wrong to say that PCB technology has not dramatically changed in recent decades.

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In spite of the necessary advances in the areas of material properties, number of stacked layers, geometries, and drilling techniques (allowing holes that penetrate only a portion of the stack), the basic structures of PCBs have not changed. These structures, formed through the processes outlined above, are abstracted to a set of physical/electrical structures: traces, planes (or planelets), vias, and pads. The evolution of printed circuit board technology has contributed to the increase in circuit performance, speed in particular. As printed circuit boards continue to evolve, they can be expected to grow ever smaller and more complex. The latest innovation in PCB technology, the rigid flex PCB, combines the complexity and reliability of a hardboard circuit with flexible layers that are incorporated into the rigid structure. With these combined layers, rigid-flex PCBs are smaller, thinner and can fit into unusually shaped or especially small products. However, the ever-growing density and complexity of PCBs also constitutes an increasing concern with respect to EMI and SI/PI: The expectation that the evolution of the microelectronics industry will not deviate from Moore’s law2 [1] is driving microprocessors to power levels in the tens of watts and clock frequencies well into the microwave region. The increasing integration of modern high-speed, very large-scale integrated circuits (VLSIs) at higher density on PCBs, coupled with the continuing growth in devices’ switching speed and operating frequency, have resulted in increased noise generation. When coupled with the reduction of signal levels, an exponential increase in the potential for interference and susceptibility is to be expected and observed in practice (Figure 13.3).

Figure 13.3 Graph of Moore’s law depicting on a semi-log plot transistor counts for microprocessors against dates of introduction, nearly doubling every two years. Source: Max Roser, Hannah Ritchie / Public Domain.

2 Moore’s Law describes a long-term trend in the history of computing hardware. Since the invention of the integrated circuit in 1958, the number of transistors that can be placed inexpensively on an integrated circuit has increased exponentially, doubling approximately every two years. Gordon Moore’s original statement that transistor counts had doubled every year can be found in his publication “Cramming more components onto integrated circuits,” Electronics Magazine 19 April 1965: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year … Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years…” Almost every measure of the capabilities of digital electronic devices is linked to Moore’s law: processing speed, memory capacity, even the number and size of pixels in digital cameras.

13.2 Interference Sources on the PCB

Studies on the radiation mechanisms for semiconductor devices and packages [2], the effects of very large-scale integrated circuits (VLSI) on radiated EMI from circuits, revealed that inasmuch as most VLSI devices are too small to act as direct sources of radiated EMI, noise coupled from these devices constitute a severe concern. Coupling was found to occur through three principal mechanisms, namely (i) coupling to heatsinks, (ii) coupling to traces, and (iii) driving reference planes in printed circuit boards. Figure 13.4 presents plots of near-field H-field surface scans of a Rambus DRAM (RDRAM) memory module clocked at 400 MHz and at 200 MHz in “Write” Mode. The major concerns with respect to interference mechanisms associated with modern PCBs are EMI (interference to and from the PCB) and crosstalk (interference on the PCB). With respect to EMI, particularly emissions, PCBs produce radiated emissions: due to both differential-mode and commonmode currents.

55 50 45 40 35 30 25 20

(a) 55 50 45 40 35 30 25 20

(b) Figure 13.4 Near- H-field surface scan of a RDRAM memory module. (a) F = 400 MHz. (b) F = 200 MHz (“Write” Mode). Source: Courtesy of Prof. Todd Hubing, LearnEMC.

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Differential-mode or loop emissions are the result of currents flowing on a signal trace between integrated circuits (ICs) and return via a trace, grid, or plane. Fortunately, the signal-trace current produces fields that tend to cancel the fields from the return current [3]. Hence, typical signal currents must flow through relatively large PCB loops to produce emissions that exceed the regulatory limits. In these cases, emissions can be reduced by simply routing the signal traces closer to the return plane and/ or by reducing the distance between the source and load ICs. Emissions due to common-mode currents, on the other hand, are predominantly due to unbalanced interconnections between digital circuits. Even a slight difference in the geometry of the signal and return conductors on a PCB or even within an IC package can produce common-mode currents. Although they may be several orders of magnitude lower than differentialmode currents, common-mode currents produce equivalent or higher levels of radiated emissions.3 Cables attached to the PCB increase the effective length of the emitting antenna and the resonant frequency at which maximum radiated emissions occur is hence reduced. An unbalanced circuit on a PCB formed by signal and return trace pairs will radiate as an asymmetric folded dipole. As the rectangular geometry of IC packages is inherently unbalanced, it is virtually impossible to construct balanced circuits on a PCB using return traces. One of the best solutions to this situation is to place a relatively large conducting plane beneath the PCB. The currents induced on this “image plane” will produce fields that tend to cancel the fields produced by the common-mode currents on the PCB, resulting in dramatic reduction in the total radiated emissions. Image currents can also lower emissions from PCBs constructed with an embedded return plane. Indeed, common-mode currents cannot exist on a PCB with an infinite return plane because the signal conductor and its return plane image are perfectly balanced. However, the finite return plane on an actual PCB produces an imperfect image, causing the plane itself to become part of the radiating antenna. In this case, the ground-noise voltage produced when signal currents encounter the finite impedance of the return plane constitutes the source driving the dipole antenna. Once again, attaching cables to the PCB simply increases the dipole effective length [3]. Crosstalk is also often a major indirect contributor to EMI interactions. Poor PCB layout may increase coupling from internal, noisy circuits and outgoing input/output (I/O) lines that will, consequently, “export” EMI (emission). Conversely, interference “imported” into the PCB through I/O lines will couple onto internal, sensitive circuits resulting in their undesired response (susceptibility). Signal and power integrity (SI/PI) were shown above to be associated with both EMI and crosstalk, since distortions in signals on the PCB (poor signal integrity) and noise on the power distribution network (poor power integrity) will couple to adjacent signal traces (i.e. crosstalk) and may subsequently contribute to emissions from the PCB due to the increased level of higher frequency harmonics (i.e. EMI) (Figure 13.5). Crosstalk, therefore, is a key mechanism in completing the interactions in the SI/PI/EMC Trio (Figure 13.6, derived from Figure 13.2 above). As a result, the following common interference mechanisms are observed on PCBs (Figure 13.7): 1) Common-impedance coupling through power supplies and their associated conductors, shared by multiple circuits 2) Common-impedance coupling through return conductors, shared by multiple circuits 3) Mismatch on high-speed transmission lines, resulting in reflections

I/O-Line (victim)

Culprit

Crosstalknoise Ref. Plane

Cableradiation Culprit Connector

I/O-Line (victim) Crosstalknoise

Bundle of cables

Figure 13.5 Interference interactions on PCBs. Source: Courtesy of Prof. Todd Hubing, LearnEMC.

3 Emissions due to common-mode and differential mode currents were discussed in detail in Chapter 2.

13.2 Interference Sources on the PCB

Figure 13.6

Crosstalk – completing the SI/PI/EMC trio.

Signal Integrity

Power Integrity

Signal propagation

Switching Noise (Bounce)

Eye Pattern

Power delivery

Reflection, Mismatch...

Power system impedance

Current return path

Decoupling Crosstalk

EMC Emission and Immunity Radiated and Conducted EMI

Inductive power leads

Ripple current on DC Power

Pulsed DC power Switch-Mode power supply

Delta-I noise Reflections on transmission lines

Inadequate decoupling

Stub ringing

Figure 13.7

4) 5) 6) 7)

Delta-I noise

Noise sources on PCBs.

Crosstalk coupling between adjacent conductors of different circuits Crosstalk coupling between high-gain, low-level analog amplifiers, resulting in feedback Transients resulting from inductive load switching within the circuit, coupling into adjacent circuits Power-supply-generated noise entering sensitive circuits

Designing PCBs for ensuring low-EMI and achieving signal integrity in high-speed systems seems easy (at first sight). The one common driving factor behind the above undesired interactions is time varying or transient current, which exists within power distribution networks and signal transmission lines on PCBs. The intensity of EMI interactions within PCBs is determined by the amount of current flowing in the circuit and the efficiency of coupling between circuits, particularly associated with their frequency content and geometry.

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VCC Power leads

GND Reference plane

DC power return Signal return Signal current image

Figure 13.8

Functions of “Ground” on a printed circuit board.

Where currents are concerned, the existence of a round-trip path is implied. Currents follow closed-loop paths, from the power source, through the circuits and components, and back to the source again. This is true for both signal and powerdelivery circuits. It follows, therefore, that for both power and signal circuits a low-impedance return path should be provided. The objective of this chapter is to discuss the design and implementation of signal- and power-return paths (grounding) on PCBs and their interactions, and the role of planes in accomplishing the EMC and signal integrity design goals.

13.3

“Grounding” on PCBs

Ever too often, the overused term “ground” is applied with respect to the function of the “second conductor” associated with signal traces and transmission lines on printed circuit boards. In actual fact, “grounding” on printed circuit boards is associated, first and foremost, with the function of the path for current return. Furthermore, the AC signal return current is not affected by the absolute DC voltage potential of the return conductor. As such, the actual AC current return path may in fact be the plane designated VCC or VAA, namely the digital or analog supply voltage conductors, respectively. At other times, the GND, or low-voltage conductor, may serve for this purpose (see Section 13.4). Note: For that purpose, the term “reference plane” or “return plane,” rather than “ground plane,” is often used throughout this chapter, iterating the fact that either the ground or the power planes may serve as the AC current return path. From the standpoint of AC, they are totally equivalent. Throughout this chapter, these terms should be considered interchangeable. In practice, “grounding” on PCBs is related for the following distinct functions (Figure 13.8): a) Signal Current Return Path. Most electronic devices, digital devices with high-speed CMOS logic in particular, utilize single-ended signaling, where the “ground” serves as a return path for the signal currents. b) DC Current Power Return Path. Electronic devices, whether digital, analog, or mixed, draw current from some DC power source (often denoted “VCC” or “VDD” and “VAA” for digital and analog circuits’ supplies, respectively). The “ground” conductors serve as the return path for the DC supply current to the DC power source. c) Image Plane. The presence of a solid metal plane immediately beneath and close to a printed circuit board has the effect of reducing radiated emissions as a result of the equivalent “image” currents produced in the plane [4]. As will be shown further in this chapter, the image plane will have similar effects on single-ended and balanced signals. Different conductors may perform the above different functions concurrently. For instance, certain AC return signals may flow through a VCC conductor, while the DC current return associated with the same circuits occurs through the DGND (digital ground conductor). The manner in which these objectives are met on printed circuit boards is discussed in detail throughout this chapter. It will be shown that the three are inseparable and are tightly interrelated.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields Signals on high-speed multilayer PCBs4 typically propagate in transmission line structures that are typically formed by the combination of a signal trace and (one or two) reference planes.5The return planes serve as a path for the signal return current, particularly for single-ended circuits (e.g. CMOS logic). Yet, even in differential circuits (e.g. LVDS, RS-422/RS-485), the planes provide a path for the greater part of the high-frequency return currents. As transition (rise and fall) times of digital devices continually decrease6 [5], usage of power and return planes has become increasingly indispensable. Digital devices such as the 74HC series that have been around for nearly 30 years and exhibited 4 Discussion of single and two-layer PCBs is beyond the scope of this book. In two-layer boards, use of planes may not be possible and traces may be used for signal current return. 5 Coplanar traces placed above the dielectric laminate without a return plane (single- or two-sided PCBs) also constitute transmission lines, but are rarely used in high-speed signal propagation due to their relative inferior performance. 6 Effect of signal transition (rise/fall) times on signal spectra is discussed in detail in Chapter 2.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

significant emission only up to 200 MHz approximately are now found to significantly emit undesired energy up to frequencies as high as 1 GHz, due, among other reasons, to progress made in fabrication techniques of the integrated circuits (ICs), e.g. die shrinking. In high-speed circuits, return planes are essential for accomplishing numerous EMC and Signal/Power Integrity (SI/PI) functions, including: a) Providing for optimal return signal propagation through a solid plane adjacent to the signal traces, serving as the path of least impedance. b) Guaranteeing a low-impedance power distribution network, offering fast transition time decoupling, thus also serving as a stable reference at high frequencies (due to the impulsive power transients), consequently reducing emissions and increasing immunity of the circuit. c) Serving as part of a controlled-impedance transmission line, providing for control of reflections due to impedance mismatch. d) Reducing ground and power bounce (also known as simultaneous switching noise (SSN)) effects resulting from high-level impulsive currents through the inductance of the power distribution systems by providing a path of minimum inductance for those currents. e) Controlling crosstalk between traces and circuits by terminating electric fields as well as providing magnetic field flux cancellation. f) Offering some degree of shielding for signal traces routed in adjacent and embedded signal planes in the PCB by virtue of their function as image planes. g) Reducing emissions on cables attached to the PCB due to common-mode EMI present on the circuits. In this section, the role of the return (a.k.a. “reference”) planes in signal propagation is presented, with respect to highfrequency (and high-speed) interconnects in particular.

13.4.1

Circuit Representation of Transmission Lines on PCBs

At low frequencies, where circuit dimensions are electrically small, PCB traces may be considered as a close-to-ideal (lossless or low-loss) lumped circuit (Figure 13.9).7 At higher frequencies, on the other hand, interactions along and between interconnects are best understood by treating them as transmission lines.8 Transmission lines constitute interconnects with their respective return conductors capable of guiding a signal between a signal source (denoted, the “transmitter”) and a load (or “receiver”) through a medium with controlled electrical characteristics. Alternating (AC) circuit characteristics dominate the performance of interconnects causing distributed (per-unit-length) resistance (RX), conductance (GX), inductance (LX), and capacitance (CX) to become prevalent in the conductor (Figure 13.10). Traditionally, transmission lines were considered in telecommunications

Figure 13.9 Low-frequency (lumped circuit) representation of a trace in a printed circuit board.

RT

Tx

Rx CL

RR

Figure 13.10 High-frequency (transmission line) representation of a trace in a printed circuit board.

RX

LX

Tx

Rx

GX

CX dX

7 Transmission line effects and their control are beyond the scope of this book. EMC and signal integrity issues (including crosstalk) pertaining to the design of transmission lines and the control of transmission line effects (e.g. reflections, propagation delay and ringing) are not discussed in any detail here, as they are very adequately covered in a number of excellent sources [5, 6]. This Section focuses only on the role of reference planes in signal propagation along the transmission lines. 8 An overview of transmission line fundamentals is provided in detail in Chapter 2.

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Propagating voltage wave front

Rx

Tx Signal current

Figure 13.11

...

Signal voltage and current propagation along a transmission line in a printed circuit board.

cables operating over long distances. Yet, as transmission rates increased and furthermore, transition times reduced, even the shortest PCB traces, and transmission lines may exhibit undesired transmission line effects such as ringing, crosstalk, reflections, and may introduce ground bounce effects, seriously hampering the integrity of the signal. These issues can be overcome primarily by maintaining controlled characteristic impedance along the line and by following adequate design techniques and simple layout guidelines. For attaining the best comprehension of the role of reference planes in signal propagation on PCBs, it is important to realize that the high-frequency signal constitutes a propagating voltage difference and a propagating current loop between the signal and the return path, i.e. between the trace and the reference plane(s) [7]. This voltage difference, developing across the distributed inductance along the line, propagates as the distributed capacitance along the line charges, generating a current flow forward into the transmission line. This current provides the charge for the capacitance of the next section of the line, between the signal and return conductor (see Figure 13.11). As a result, significant current flows on the solid reference plane(s) beneath or above single-ended and differential signal traces9 alike. When a high-frequency (such as high-speed digital) signal propagates down a single-ended transmission line displacement currents follow the electric flux and flow through the distributed capacitance of the trace to adjacent metallic objects, and to the large, solid plane adjacent to the trace in particular. This capacitive effect provides the means for a returning current flow to the solid reference plane. The return current flows underneath the signal trace along the reference plane back to the source.

13.4.2

Electromagnetic field representation of transmission lines on PCBs

Circuit representation of transmission lines does not provide a full account of the behavior of return current paths in reference planes, particularly when the plane adjacent to the signal trace is not the “ground” or “0 V” plane. A more generalized approach for explaining the nature of signal propagation along a transmission line employs electromagnetic theory. Signal propagation can thus be viewed as an electromagnetic wave conveyed between the trace and the reference plane, considering the boundary conditions imposed by a metal plane. While DC is conducted in the conductors, the signal RF energy propagates throughout the PCB in the form of guided quasi10-TEM (transverse electromagnetic) waves where the E-field and H-field are transverse to the propagation direction (or Poynting) vector [8]. Quasi-TEM waves propagating in multiconductor lines have electric and magnetic field components predominantly tangential to the line cross-section and the signal is transmitted along the line by these fields outside of the conductors. The fields may have components along the line if there is inhomogeneous or multilayered dielectrics and also in the case of lossy or nonideal conductors (discussed below). Consider a trace carrying a signal above a metallic plane. Electric field exists between the trace and the metallic plane while magnetic field surrounds the trace (Figure 13.12). A boundary exists between the dielectric substrate of the PCB and the metallic plane. The tangential components of the electric field vector, E, and the magnetic field vector, H, must be continuous across the boundary between the two media, that is E td = E tm and H td = H tm , where the subscripts “td” and “tm” represent the tangential component of the fields in the dielectric substrate and the metal surface, respectively.11 In addition, from the Law of

9 The distribution assumed by the current in the return plane is presented later in this Chapter. 10 Ideally, propagation would occur in TEM mode. However, due to the non-homogenous discontinuous interface between the dielectric substrate and the surrounding air in a microstrip transmission line (discussed in the following Section), quasi-TEM rather than perfect TEM pattern arises. 11 A detailed discussion of boundary conditions is presented in Chapter 2.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Magnetic field

Electric field

(a) Electric field flux

Magnetic field flux

Trace

Dielectric substrate

Return plane (VCC/GND)

(b) Figure 13.12 Contours of constant H-field (solid lines) encircle a signal conductor microstrip; electric field force lines (broken lines) connect the signal conductor to the reference plane. (a) 3-D illustration. Source: The Sierra Circuits Team [9]. (b) 2-D cross-section.

Continuity, the normal component of the electric flux density vector, D, and the magnetic flux density vector, B, must be continuous across the boundary between the two media, that is Dnd = Dnm (assuming that no surface charges exist on the boundary between the two media) and B nd = B nm , where the subscripts “nd” and “nm” represent the normal component of the fields in the dielectric substrate and the metal surface, respectively. For simplicity of discussion, the metal plane is assumed to be a perfect electrical conductor (PEC), so that σ m ∞. Consequently, all fields within the metal plane must vanish, i.e. E m = 0, Dm = 0, as well as H m = 0 and B m = 0. As a result, the tangential electric field vector and normal magnetic flux density field vector components in the dielectric at the boundary must vanish too, i.e. E td = 0 and B nd = 0. The tangential magnetic field vector and normal electric flux density vector components in the dielectric substrate do not vanish, however. To satisfy this discontinuity, the tangential magnetic field component creates a surface current distribution, KS [A/m], along the surface of the boundary that is orthogonal to H t so that H td = K S. In a similar manner, the normal electric field flux density component deposits a surface charge distribution, ρS [C/m2], along the surface of the boundary so that Dnd = ρS (refer to Figure 13.13). Note that all fields and charge/current distributions are time-varying values, that is H = H(t), D = D(t), KS = KS(t), and ρS = ρS(t).

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13 Grounding on Printed Circuit Boards

Tangent H-field flux

Normal E-field flux

Trace

Dnd (t)

Htd (t) Htd (t)

KS (t) Return plane (VCC/GND)

Ht ≡ 0 m

En (t) d

Dn ≡ 0 m

ρS (t) σm = ∞

Dielectric substrate

Figure 13.13

13.4.3

Surface current KS and charge ρS distributions on the surface of the reference plane due to signal propagation in structure.

Equivalence of Power and Ground Planes as Return Paths for High-Speed Signal Propagation

It follows from the previous section that meeting the boundary conditions requires that time-varying return current and charge12 distributions, corresponding to the signal propagating on the trace, must be present on the surface of the metallic boundary (or surface) of the plane, whether the adjoining mass of metal is a 230 VAC mains, a 5 VDC (VCC), a ground “0 V” plane (GND or VEE), or an isolated metallic surface [7]. These current and charge distributions are also known as the “AC return currents.” Planes on printed circuit boards ideally constitute an uninterrupted solid (or, occasionally, high-density meshed) area of metal covering the entirety of a PCB layer. In certain cases, planelets13 are used, in lieu of complete planes, for instance, in cases of split power (5, 3.3 V, etc.) power planes or split reference planes (AGND, DGND, for analog and digital ground planelets, respectively). The plane is generally designated as “ground” (or 0 V) plane if it serves as the DC current return conductor and a “power” plane if it is connected to a power supply voltage. Although distinction is often made between power (e.g. VCC) and ground (GND, VEE) planes, this distinction should be considered for DC signals and power distribution only. AC signals can and do travel on either the power or ground plane (Figure 13.14). This concept should not be disturbing in any way and can be explained as follows: The E and H field flux distributions in a transmission line structure (discussed in the previous section) and the corresponding charge and current distributions are shown by Maxwell’s equations to be dependent on permittivity, permeability, and conductivity of the dielectric substrate and the metallic surface, ε, μ, and σ, respectively, only. The spatial distributions of the E (=D/ε) and H (=B/μ) fields are linked in the dielectric substrate between the trace and the metal plane through Ampere’s law, ∇ × H = J + ∂D ∂t

13 1

and Faraday’s law, ∇ × E = − ∂B ∂t

13 2

while the E-field to surface charge distribution are linked through Gauss’s law of electric fields, ∇ D=ρ

13 3

Nowhere in these equations is the DC potential or bias of the metallic plane to be found. The boundary conditions discussed above hold, therefore, from the stand point of time-varying propagating fields, regardless of the DC potential of the metallic surface. Furthermore, differentiating equation (13.3), Gauss’s law of electric fields, with respect to time, t, we obtain: ∇ D=ρ

∂ ∂ρ ∇ D = ∂t ∂t

13 4

12 Note that time-varying charge distribution is actually current: ∂Q/∂t I. 13 A planelet, a variation of a plane, is an uninterrupted area of metal covering only a portion of a PCB layer. Typically, a number of planelets exist in one PCB layer. Applications of split power and return planes are discussed in detail later in this Chapter.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

VCC

VCC AC Signal Return Current Path through the Power (VCC) Rail

AC Signal Return Current Path through the GND Rail GND

GND

(a)

(b)

AC Signal Return Current Path through the AC GND AC GND

(c)

AC GND

Figure 13.14 Equivalence of ground and power planes as AC current ground planes. (a) Return RF current flow through VCC . (b) Return RF current flow through GND. (c) Return RF current flow through AC GND.

Note that the time-derivative of the volumetric charge density, ρ, can be said to be conceptually proportional to the surface charge density, J. The surface charge density, J, is defined as the infinitesimal charge, ∂Q, distributed along an infinitesimal surface area element, ∂S, yielding, J=

∂Q ∂S

13 5

while the volumetric charge density, ρ, is defined as the infinitesimal charge, ∂Q, distributed in an infinitesimal volumetric element, ∂V, yielding, ρ=

∂Q ∂V

13 6

Alternatively, through integration, the total charge, Q, of a region according to surface charge density, J(r), over a surface, S, yields, Q = JdS

13 7

σ

d

n

S

and a volume integral of the volume charge density ρ over a volume, V, yields (Figure 13.15), Q = ρdV

13 8 r – r′

V

The total charge divided by the surface area or volume provides the average charge densities: J=

Q Q and ρ = S V

13 9

Considering that signal traces, or the reference metallic planes are fairly thin and have uniform thickness, τ, it would be reasonable to approximate: V =S τ

13 10

where τ represents the thickness of the trace or plane. Due to skin effect, the volumetric current distribution may not be uniform along the thickness of the plane or trace, we will retain the averaging assumption, hence,

ρ r′

r

Figure 13.15 Universal charge density diagram of a continuous charge distribution depicting the volume charge density, ρ, unit volume in the cube, surface charge density, J, and unit surface denoted by the ellipse at the surface. Source: Wikimedia / Public Domain.

709

710

13 Grounding on Printed Circuit Boards

J=

Q Q and ρ = S S τ

13 11

Returning now to equation (13.4), we can see that indeed, ∂ ∂ρ ∇•D = ∂t ∂t

13 12

J

But, as the time derivative, ∂( )/∂t, and the spatial derivative (represented by the divergence), ∇•( ), are independent, the order of differentiation may be changed, thus, ∂ ∂D ∇•D = ∇• ∂t ∂t

=

∂ρ ∂t

J

13 13

If there were a DC potential difference between the signal trace and the plane (i.e. due to the trace being routed above a VCC plane rather than the GND plane), resulting in a DC E-field (E = D/ε), this DC component of the E-field diminishes through temporal differentiation. Subsequently, surface current, J, flows on the plane due to the AC components of the field between the trace and the plane, independent of its DC potential. Q.E.D.14 As yet another example, consider a coaxial cable (a transmission line), which guides RF signals between its inner conductor and its outer conductor (a.k.a., shield), concurrently delivering DC power along the same conductors15 (Figure 13.16). Transmission lines on printed circuit boards are no different. The actual DC voltage potential (represented as an ideal voltage source in Figure 13.16) with respect to some other reference plane has no effect on either the DC or RF signal propagation. In fact, note that TEM propagation will occur in the coaxial transmission line even if no connection exists to any reference plane, as long as the transmission path is complete and forms a closed circuit. So why should it be any different in signal transmission lines on printed circuit boards (e.g. microstrip or stripline)? From this point on, the terms “ground” or “return” will therefore apply to either the “power” (VCC or VAA) or “return” (GND) planes, with respect to AC energy propagation on PCB transmission lines unless explicitly stated otherwise.

The Least You Need to Know

• • • •

Use of solid metallic (typically copper) planes for power distribution and return is essential for high-frequency (short transition time) circuits. Planes minimize noise produced by switching currents through stray inductance, help to mitigate the effects of crosstalk and to control impedance of transmission lines, suppressing reflections and ringing and decreasing emissions and susceptibility, in their function as “image planes.” Distinction between “power” and “ground” (or “0 V”) planes is valid for DC only; AC signals can and do travel on either type of plane; the term “AC current return” applies to both the “power” and “ground” planes. Planes constitute a cost-effective measure for ensuring EMC and signal integrity at the PCB level; without the use of planes, EMI control would have been very difficult if not impossible.

13.4.4

Common Transmission Line Configurations on PCBs

Transmission lines are characterized by two main parameters, namely the characteristic impedance, Z0, and the signal velocity of propagation, ν. Both the characteristic impedance and the signal velocity of propagation are associated with the particular transmission line geometry and depend on the conductor’s shape and its geometry with respect to the conductor(s) carrying its return current. They also depend on the relative permeability, μr and permittivity, εr of the PCB’s dielectric substrate (or laminate) material associated with the transmission line (e.g. FR4, Alumina or Rogers) and on its proximity of other conductors and insulators. The characteristic impedance, Z0, in particular, forms the one most important feature associated with transmission lines, which must be controlled for ensuring signal integrity and subsequently functionality of the circuit. Traces used as transmission lines must maintain a fixed value of Z0 along their route. Discontinuities in Z0 produce reflections of high-frequency components of the propagating signal waveform, introducing distortions and consequently emissions and crosstalk along the transmission line. Such discontinuities may arise, among other reasons, from flawed implementation of the reference planes on the PCB.

14 Q.E.D. or QED is an initialism of the Latin phrase “quod erat demonstrandum,” meaning “which was to be demonstrated.” Literally it states “what was to be shown.” 15 Consider the DC voltage source as an equivalent short circuit.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

H-field

H-field

E-field

E-field

ZL

ZL

Shield

Shield

turn

y re uenc th q e r f pa hHig current

ZS

rn retu ency h u q e pat h-fr Hig current

“0V” ZS

Signal reference structure

“0V”

“0V”

Signal reference structure DC Bias in either location

“0V”

(a)

(b) H-field E-field

ZL Shield

ZS

n etur cy r n e u eq path h-fr Hig current

Signal reference structure

(c) Figure 13.16 DC bias has no effect of high-frequency wave propagation in a coaxial transmission line. (a) No DC bias; shield at potential of “0 V”; wave propagates in TEM mode in transmission line structure. (b) DC bias introduced; TEM wave propagation in transmission line structure prevails. (c) No reference structure connection; TEM wave propagation in transmission line structure prevails.

Several schemes of transmission line structures are implemented in multilayer printed circuit boards. In those schemes, transmission lines can be formed by a single-ended signal conductor and by differential signal conductors. 13.4.4.1

Single-Ended Transmission Line Configurations

In single-ended interconnects, both the signal trace and one or more reference planes are essential for guiding a signal across the PCB. Two fundamental topologies are commonly used, namely microstrip (surface and embedded) and stripline (single and dual) [5]. In the single-ended transmission line, a single conductor interconnects the source to the load. The reference plane provides the signal return path. a) Microstrip Microstrip constitutes a common configuration of transmission lines to implement impedance-controlled interconnects on external layers on a printed circuit board. The two most common configurations of microstrip transmission lines are:

••

Surface Microstrip Embedded Microstrip

The geometry of the two microstrip transmission line topologies is illustrated in Figure 13.17. A surface microstrip transmission line consists of a trace routed in parallel to a solid and continuous reference plane, separated by a dielectric substrate, while air constitutes the dielectric material above the conductor (in practice, a thin

711

13 Grounding on Printed Circuit Boards

w

w

(a)

h

h

εr

εr

t

b

t

712

(b)

Figure 13.17 Geometry of microstrip transmission lines. (a) Geometry of a surface microstrip transmission line. (b) Geometry of an embedded microstrip transmission line.

surface of solder mask is typically present above the trace). The approximate expression for the characteristic impedance, Z0, of a surface microstrip is [5] (refer to Figure 13.17a for description of the dimension parameters):16 Z0 ≈ Z0 ≈

87 5 98h Ω 15 < w < 25 mil ln 0 8w + t εr + 1 414 79 5 98h ln Ω 5 < w < 15 mil 0 8w + t εr + 1 414

13 14

An embedded (or buried) microstrip transmission line is similar to the surface microstrip; however, the signal line is embedded in a dielectric and located a known distance, h, from the reference plane (note that h < b). The approximate expression for the characteristic impedance, Z0, of an embedded microstrip is [5] (refer to Figure 13.17b for description of the dimension parameters): Z0 ≈

87 εr εr 1 − e

ln − 1 55b h

5 98h Ω 0 8w + t

13 15

b) Stripline Stripline refers to a trace located between two solid and continuous reference planes. The volume between the two reference planes contains a dielectric substrate, which totally surrounds the trace. The stripline offers some advantages over the microstrip topology, namely reduced dispersion of electric fields and enhanced magnetic flux cancellation, thus minimizing emissions from and crosstalk within the PCB. The two most common configurations of stripline transmission lines are:

••

Centered Stripline Dual Stripline

The geometry of the two stripline transmission line topologies is illustrated in Figure 13.18. A centered stripline transmission line consists of a single trace centered in between two parallel solid and continuous reference planes. The approximate expression for the characteristic impedance, Z0, of a surface microstrip is [5] (refer to Figure 13.18a for description of the dimension parameters): Z0 ≈

60 4h ln εr 0 67π 0 8w + t

Ω

13 16

A dual stripline transmission line is a variation to the centered stripline and consists of a pair of traces asymmetrically placed in between two parallel solid and continuous reference planes. Each of the traces serves as a single-ended 16 The commonly used expressions provided in this Section (and in the signal integrity literature, in general, are approximations, resulting from the fact that the it is not possible to satisfy the boundary condition of equal phase velocities parallel to the air-dielectric interface with pure TEM waves. Thus, the situation for the microstrip line does not correspond exactly to TEM wave propagation (hence denoted “Quasi-TEM”(, as is the case with any other line involving multiple dielectrics.In addition, the approximation is based on the (i) finite dimensions of the PCB about the transmission line, (ii) the frequency-dependent relative permittivity of the dielectric substrate and (iii) on the actual geometry of the transmission line (e.g. straight vs. bent line, proximity of (and subsequent loading by) adjacent transmission lines, etc.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

w

w

t

h

w

b

d

εr h

t

h

t

εr

(b)

(a)

Figure 13.18 Geometry of stripline transmission lines. (a) Geometry of a centered stripline transmission line. (b) Geometry of a dual stripline transmission line.

interconnect (this configuration is typically found in a stackup where two signal traces are placed in between two reference planes).17 This configuration should not be confused with a differential transmission line scheme discussed herein. The approximate expression for the characteristic impedance, Z0, of a dual stripline is [5] (refer to Figure 13.18b for description of the dimension parameters): Z0 ≈

13.4.4.2

80 4h 2h + t ln εr 0 67π 0 8w + t

1−

2 h−t 4 h+d+t

Ω

13 17

Differential Transmission Line Configurations

For differential interconnects (e.g. LVDS, Ethernet, USB), the transmission line is formed by the combination of two traces and one or more reference planes. In a differential transmission line, two conductors interconnect the source to the load. The reference plane provides the signal return path for the larger part of the returning current from each trace, not the adjacent trace. While the presence of a reference plane is therefore not strictly necessary in the case of differential signaling, it is vital for practical implementation of high-speed differential traces in PCBs. Two fundamental schemes are commonly used, namely edge-coupled microstrip and edge-coupled stripline [5]. The geometry of the two differential transmission line topologies is illustrated in Figure 13.19. a) Differential Edge Coupled Microstrip In a differential edge coupled microstrip scheme, the two conductors are routed in a manner similar to that of a surface microstrip transmission line. However, by virtue of their implementation, the lines are coupled, serving as a paired transmission line. For improving their performance, the separation between both traces of each differential pair should be maintained as small as practical (i.e. tightly coupled) and remain constant to avoid discontinuities in differential characteristic impedance and maintain the balance along the line. The approximate expression for the characteristic impedance, Z0, of a differential edge coupled microstrip is [5] (refer to Figure 13.19a for description of the dimension parameters): 1 − 0 48 e − 0 96h Ω s

13 18

w s

(a)

t

εr

h

εr

w

w

t

w

s

h

Z DIFF = 2 × Z 0

(b)

Figure 13.19 Geometry of differential transmission lines. (a) Geometry of a differential edge coupled microstrip transmission line. (b) Geometry of a differential edge coupled stripline transmission line.

17 A special subcategory of the dual stripline is the “offset stripline” where only one signal layer, embedded between the reference planes is present, but is intentionally off-center.

713

13 Grounding on Printed Circuit Boards

where the expression for Z0 of a single-ended microstrip is: Z0 ≈

60 4h ln 0 67 0 8w + t 0 457εr + 0 67

Ω

13 19

a) Differential Edge Coupled Stripline In a differential edge coupled stripline scheme, the two conductors of the differential pair are each routed in a manner similar to that of a single-ended embedded stripline transmission line. However, by virtue of their implementation, the lines are coupled, serving as a paired differential transmission line. Similar to the edge coupled microstrip, the separation between both traces of each differential pair should be maintained as small as practical and remain constant to avoid discontinuities in differential characteristic impedance and maintain the balance along the line. The approximate expression for the characteristic impedance, Z0, of a differential edge coupled stripline is [5] (refer to Figure 13.19b for description of the dimension parameters): Z DIFF = 2 × Z 0

1 − 0 347 e − 2 9h Ω s

13 20

where the expression for Z0 of a single-ended stripline is: Z0 ≈

60 4b ln εr 0 67π 0 8w + t

Ω

13 21

b) Broadside Coupled Stripline Contrary to the previous coplanar structures, in broadside coupled stripline transmission lines the two conductors are routed in a stacked-up manner in two adjacent layers, embedded between two return planes (Figure 13.20). Broadside coupled stripline structures are particularly useful in backplane design as these utilize only one routing channel and may be easier to route through high-density connector pin fields. The approximate expression for the characteristic impedance, Z0, of a differential broadside-coupled stripline is (refer to Figure 13.20 for description of the dimension parameters): Z DIFF ≈

80 1 9 2h + t ln εr 0 8w + t

1−

h 4 h+s+t

Ω

13 22

Nature of Transmission Lines at Ultrahigh Frequencies Although this may seem a paradox, all exact science is based on the idea of approximation. If a man tells you he knows a thing exactly, then you can be safe in inferring that you are speaking to an inexact man. — Bertrand Russell Everything should be made as simple as possible, but not simpler. — Albert Einstein

t

h

Interconnects are the major bottleneck in communication between electronic devices. Channels exceeding 2 GHz, reaching bit rates as high as of 25–30 Gbps, are common. As signal frequencies and data rates continue to increase, certain assumptions applied up to, say, 2 GHz, are no longer valid. In particular, aspects associated with materials and construcw tion of the PCB need to be considered, with the two key considerations being the lossy and dispersive nature of the transmission line materials, as well as the effect of rough conductor surfaces, all potentially having dramatic consequences on signal degradation, increasing conductor-related εr losses substantially. This section addresses several aspects associated with the nature of transmission line at ultrahigh frequencies as it pertains to the design of the reference planes. In particular, issues to be considered are losses, absorption and dispersion, and Figure 13.20 Geometry of broadside coupled differential effect of roughness of the planes’ surfaces. stripline. h

t

b

S

714

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Three key factors determine distribution of currents in π · f · μ (1 + j) Z( f ) = Kr ( f ) Z ( f ) Z( f ) = R + j2π fL σ the transmission line conductors and return planes, and the corresponding signal loss and dispersion. Those are conductor bulk resistivity, geometry of the conductors, and proximity of the conductors (e.g. strip and plane). In (a) (b) (c) addition, surface roughness and dielectrics surrounding the conductors alter the current density in the intercon- Figure 13.21 Current density variation with increase of frequency. nects. The frequency-dependent conductor effects can be (a) Current concentration below traces. (b) Skin effect. (c) Skin effect qualitatively separated into three frequency regions, low, on rough surfaces. medium, and high, based on the state of current density distribution in conductors or on the base of properties of the conductor impedance per-unit-length (Figure 13.21) [10]. At DC and very low frequencies, current is uniformly distributed across the trace and plane conductors. At slightly higher frequencies, currents concentrate below the strip due to the proximity effect. As frequency further increases, current density becomes larger near the surface of the conductors, and at the trace edges due to skin effect, and finally, at high frequencies, the skin effect is well-developed and roughness and dispersion plus edge effect may further contribute to the resistance growth and change the conductor interior per-unit-length inductance. 13.4.4.1

Losses and Absorption

Transmission line structures exhibit different loss mechanisms. The total transmission line loss in printed circuit boards is named insertion loss (αt), which comprises of four loss mechanisms, namely:

•• ••

Conductor loss (αc), Dielectric loss (αd), Radiation loss (αr), and Leakage loss (αl) αt = αc + αd + αr + αl

13 23

The effect of leakage loss, αl, can be ignored because PCBs have very high-volume resistance. Radiation loss, αr, represents the energy lost from the circuit due to RF radiation, dependent on frequency, dielectric constant (εr), and thickness. For a particular transmission line, the loss increases with increase of frequencies. For the same circuit when using a thinner substrate with a higher permittivity, εr, the radiation loss diminishes. In this section, transmission line losses related to the conductor loss (αc) and dielectric loss (αd) are considered, i.e. αt ≈ αc + αd 13.4.4.2

13 24

Conductor and Plane Losses

Transmission line structures exhibit different loss mechanisms.18 The total transmission line loss in printed circuit boards is named insertion loss (αt), which comprises of four loss mechanisms namely: Chapter 2 included a general discussion of transmission lines, and a model of a segment of length dx was shown and is depicted for convenience in Figure 13.22, where: R = Resistance of the line conductors per-unit-length L = Inductance of the line conductors’ loop G = Conductance (due to dielectric) between signal and return paths C = Capacitance between signal and return paths (increases with dielectric εr) In this section, the behavior and parameters associated with lossy transmission lines is presented. For a sinusoidal signal of frequency f (ω = 2 πf ) traveling along the transmission, the spatial and temporal expression for the voltage is given by: V x, t = V 0 e − αx e j ωt − βx

13 25

Rdx

Ldx

Gdx

Cdx

Figure 13.22 High-frequency distributed circuit representation (of Segment dx). Source: Omegatron / Wikipedia/ Public Domain.

18 Much of the material in this Chapter is derived from the paper by Shlepnev, Y., Nwachukwu, C., “Roughness Characterization for Interconnect Analysis.” [11]

715

716

13 Grounding on Printed Circuit Boards

and the current is simply expressed as: I x, t =

V x, t V 0 − ax = e Z0 Z0

13 26

where α and β represent the real and imaginary components of the propagation constant, γ = α + jβ is separated into two components that have very different effects on signals and is given by: γ=

R + jωL G + jωC = 1−j

= jω LC

1 2

R ωL

1−j

G ωC

1 2

At higher frequencies, we may consider simply, R R + jωL = G + jωC

Z 0 = lim ω

∞

13 27 ωL and G

ωC, or,

L C

13 28

and thus, the commonly known expression for characteristic impedance, Z0, was derived. The propagation constant γ is therefore, γ = jω LC =

1 2

1−

j 2

R G + ωL ωC

R + GZ 0 Z0

= 13 29

+ jω LC

The real part of the propagation constant, γ, is the attenuation constant and is denoted by the letter α. It represents the decrease of the signal amplitude as it propagates along the transmission line. The natural units of the attenuation constant are Nepers/meter or Np/m but is often converted to dB/meter by multiplying Np/m by 8.686:19 1Np m = 20 log 10 e ≈ 8 685889638 dB m 1 1dB m = ln 10 ≈ 0 115129255 Np m 20

13 30

The dB loss is directly proportional, therefore, to the line length, l. The above is also called total insertion loss, αt, of the transmission line and may be written as: αt ≈ 8 68

1 2

R + GZ 0 ≈ 4 34 Z0

R + GZ 0 dB l Z0

13 31

The imaginary part of the complex propagation constant, γ, defines the phase for the transmitted signal and is known as the phase constant, β. It determines the sinusoidal amplitude/phase of the signal along a transmission line, at a constant time. The phase constant’s “natural” units are radians/meter, but we often convert to degrees/meter. A transmission line of length “l” will have an electrical phase of βl in radians or degrees. To convert from radians to degrees, simply multiply by 180/π. No dispersion20 occurs if the phase constant is a linear function of frequency; however, any deviation of phase from linearity distorts the signal (i.e. different signal harmonics will experience different delay). Thus, α, the attenuation constant and β, the phase constant, may be expressed as: α = Re γ =

1 2

R + GZ0 Z0

13 32

β = Im γ = ω LC hence, V x, t = V 0 e

− 12

R Z0

+ GZ0 x jω t − LCx

e

13 33

Equation (13.33) represents a wave traveling with a propagation delay per-unit-length: T PD =

LC

13 34

and is attenuating as it travels along the line. 19 Note that attenuation constant, α, is always a positive number, or the first law of thermodynamics would be violated (as you never get something for nothing!) 20 Dispersion is discussed below.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

The two parts of the propagation constant have radically different effects on a wave. The amplitude of a wave (frozen in time) has a nature of cosine(βl), and in fact, in a lossless transmission line, the wave would propagate as a perfect sinusoidal wave. In a practical, lossy transmission line; however, the attenuation constant must be considered. The amplitude of the signal decays as e−αl. The composite behavior of the propagation constant is observed when the effects of both the attenuation and phase constants, α and β, are multiplied (Figure 13.23). The factor, R/Z0, component of the attenuation constant is proportional to R, the resistance per-unit-length of the transmission line, and is denoted the conductor loss. The conductor loss is due to the I2R losses in the resistance of the conductors forming the transmission line. It is represented by αc. The G Z0 part of the loss is proportional to G, the conductance perunit-length of the dielectric material forming part of the transmission line, and is called the dielectric, or absorption loss, denoted by αd. Therefore, combining the two factors: αt ≈ αc + αd R αc ≈ 4 34 ; and αd ≈ 4 34 GZ 0 Z0

13 35

Applying the above to transmission line structures on PCBs, as frequency increases, due to skin effect, current flow in the trace and in the ground plane is confined to the surface of the conducting material, typically copper. Consequently, conductorresistive losses in the copper conductors, αc, increases (proportional to f 0.5, where f represents frequency). Increasing surface area, i.e. by increasing the width of the trace can slightly mitigate this effect, however, as shall be shown in the next section, increasing the width of the return plane will provide minor to no additional benefit, due to the high-frequency current distribution pattern under the trace (Figure 13.24). The dielectric loss, αd, is characterized by its loss tangent, tan(δ). In applications up to 1 GHz, approximately, dielectric loss forms a small fraction of the loss due to the skin effect; however, as dielectric losses increase faster with frequency than conductor losses, they become dominant at higher frequencies. Figure 13.25 illustrates a comparison for two different dielectric substrates and depicts the dielectric losses in Rogers 4003 (δ = 0.027) and FR4 (δ = 0.002) substrate materials compared to metal (conductor)

Figure 13.23 Amplitude of a propagating electromagnetic wave along a transmission line (“Time is Frozen”) assuming α = 0.05 and β = 1. Source: Adapted from Microwaves101.

150%

Ampolitude (% of original)

100% 50%

0% 0

5

10

15

20

25

30

35

40

–50%

–100%

–150% Distance from source, l

(a)

(b)

Figure 13.24 High-frequency current distribution in trace and return plane(s). (a) Microstrip structure. (b) Stripline structure. Source: Courtesy of Dr. Eric Bogatin.

717

13 Grounding on Printed Circuit Boards

Metal Loss– 8 mil Trace

Loss Tan = 0.02

losses. The “crossover” points between the dielectric and conductor losses for FR4 and Rogers 4003 occur at 700 MHz, approximately, and well above 10 GHz, respectively. It is evident that the commonly used FR4 dielectric loss becomes significant above 1 GHz thus for lower losses, dielectrics such as Rogers 4003 or Arlon 25 should be used. Furthermore, As the value of permittivity is frequency-dependent, changes in frequency may result in errors of approximately 5–6% between calculated and measured characteristic impedance. Most suppliers of “traditional” dielectrics such as FR4 or Polyimide provide the value of εr at 1 MHz, while for Rogers 4003 or Arlon 25, for instance, data is provided at 10 GHz.

Loss Tan = 0.002

1 Attenuation (dB / in.)

718

0.1

0.001

0.001

0.0001 106

13.4.4.3 Dispersion

Transmission line dispersion is a critical aspect of signal behavior, which is intimately related to dielectric and conductive losses in a transmission line (discussed above). The understanding of Figure 13.25 Conductive and dielectric attenuation for various dispersion and losses is crucial for minimizing signal distortion tan(δ) (δ = 0.02 and δ = 0.002 represent Rogers 4003 and FR4, on an interconnect, particularly at ultrahigh frequencies and at respectively). Source: Courtesy of Mark Montrose. fast edge rates. Dispersion can result in degraded system-level performance, cause loss of signal integrity (poor eye performance), reduced bandwidth, and degraded pulse performance. Simply put, dispersion causes different wavelengths to travel at different velocities in the propagation medium (i.e. the dielectric substrate of the transmission line) and is thus of utmost importance in ultrahigh-speed and broadband signals. The short wavelength (higher frequency) spectral components travel faster than the longer wavelength (lower frequency) components, thereby broadening the (time domain) signal pulses, which subsequently start overlapping21 with each other (Figure 13.26). Consequently, after some distance, the signal pulses barely remain distinguishable and the data is lost. This section addresses the role dispersion plays in determining the characteristic impedance spectrum, its relationship to losses in a transmission line. Dispersion is a fundamental property of the interaction between real materials and the electromagnetic field and alludes to the fact that the real part of a material’s dielectric constant, and thus the velocity of propagation of an electromagnetic wave, frequency-dependent. In addition, the imaginary part of the dielectric constant is also a function of frequency. Once the frequency dependence of permittivity is considered, the equivalent parameters in the RLCG( f ) model as functions of frequency can be computed and losses can be calculated as function of frequency. In the previous section, the common RLCG model for calculating transmission line impedance was presented and the characteristic impedance was calculated in terms of the equivalent circuit parameters. Most designers that use this model do not include dispersion in their calculations. In other words, they simply assume that, at higher frequencies, the dielectric constant is invariable and the transmission line’s characteristic impedance converges to a purely resistive value, as shown in equation (13.28) above. This equation is simply incorrect! The characteristic impedance of transmission lines at high frequencies is not purely resistive and this approximation is incorrect for the following reasons:

• •

107

108 Frequency (Hz)

109

1010

C (capacitance) and G (conductance) are frequency-dependent. Both of these terms are functions of frequency as they depend on the dielectric constant (real and imaginary parts, respectively), ε. Skin effect is ignored. Line resistance is frequency-dependent and increases due to skin effect (i.e. R = R( f )). Skin effect also somewhat increases the reactive impedance to the line as it creates eddy currents and hence magnetic fields, thus adding a frequency-dependent contribution to inductance, L.

In reality, the characteristic impedance of a transmission line does include a reactive component. While this reactive component is small, it is nonzero at higher frequencies and contributes to signal deformation. Moreover, skin effect and conductive losses are also dependent on the geometry of the transmission line, and particularly the signal trace. Calculating this behavior throughout the bandwidth of the signal requires the causal nature of the electromagnetic field and its manifestation as signal behavior on a transmission line to be considered. For this purpose, the real and imaginary parts of the dielectric function must be determined using Kramers–Kronig relations [12]. The frequency-dependent parameters in the

21 This phenomenon is thus also known as “inter-symbol interference.”

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Pulse broadening due to dispersion Input pulses Pulse shapes and amplitudes

(a) Separate pulses at time t1 (b) Distinguishable pulses at time t2 > t1 (c) Barely Distinguishable pulses at time t3 > t2 Intersymbol interference

Output pattern

(d) Indistinguishable pulses at time t4 > t3

Distance along line

(a)

Waveform at output of transmitter 0

1

1

0

0

1

1

?

1

0

1

1

0

1

?

1

1

0

Waveform at input of receiver

(b) Figure 13.26 Dispersion broadens the signal pulses, eventually resulting in overlap and loss of data. (a) General dispersion mechanism. (b) Dispersion in digital bit-streams.

RLCG( f ) model describing causal transmission lines, including transmission line dispersion, DC losses, dielectric losses, and skin effect, are: R f = R0 +

f RS

L f = L ∞ + RS C f =

2π

f

K g εrRe ε0

13 36

G f = G0 + 2πfK g εrIm ε0 where the Kramers–Kronig relations between the real and imaginary parts of the dielectric function are εRe ω =

1 P π

εIm ω = −

∞

−∞

1 P π

εIm x dx + 1 x−ω ∞

−∞

13 37 ε Re x − 1 dx x−ω

Effects of dispersion and losses on characteristic impedance and insertion loss can now be considered. Clearly, the common practice of applying the simple, resistive expression for characteristic impedance is erroneous and is an approximation only, generally valid up to 10 GHz, approximately. In practice, the actual impedance is a complex function of frequency, as depicted

719

13 Grounding on Printed Circuit Boards

in Figure 13.27 below,22 which illustrate computed values of characteristic impedance and insertion loss in a stripline structure on an FR4-based PCB, including skin effect losses and dispersion in the dielectric. It is evident that this optimized transmission line geometry provides low loss up to 20 GHz, approximately and that the characteristic impedance is not purely resistive. Similarly, the traditional resistive formula underestimates insertion loss. It is evident that this optimized transmission line geometry provides low loss up to 20 GHz, approximately, and that the characteristic impedance is not purely resistive. Similarly, the traditional resistive formula underestimates insertion loss. The effects of dispersion can also be demonstrated by considering signal integrity, which is important in the design of most any high-speed system. This is especially true for telecom and datacom systems, which may be operating at data rates of many Gbps. Figure 13.28 below demonstrates the effects of dispersion on eye quality of a 10 Gbps signal by comparing a 12.7 mm (0.500 in.) length of coaxial line and microstrip line. It is evident that the coaxial line has essentially no effect on eye quality, while the microstrip line has overshoot and the eye closes early. In addition, the rise and fall times have increased.

0.0

0.08

–0.1

–0.5

0.07

50

–0.2

–1.0

49.9

–0.3

Imaginary

Real

50.2

–0.4

49.7 49.6

IL (dB)

49.8

Im(Z) (Ω)

50.1

0.06 0.05

–1.5

0.04 –2.0

–0.5

–2.5

–0.6

–3.0

–0.7

–3.5

0.03

49.3

0.1

1

10

0.02

IL εI

49.5 49.4

εI

0

50.3

Re(Z ) (Ω)

720

0.01 0.00

0

5

Frequency (GHz)

10 15 Frequency (GHz)

(a)

20

(b)

Figure 13.27 Characteristic impedance and insertion loss and imaginary part of the dielectric function in a stripline structure of 1 oz./sq. ft., 0.196 mm layer thickness, and 0.54 mm width (21.3 mi). (a) Characteristic Impedance. (b) Insertion Loss and Imaginary Part of the Dielectric Function. Source: Courtesy of Dr. Zachariah Peterson, Northwest Engineering Solutions.

2

2

1

1

0

0

–1

–1

–2

–2 0

10

20

30

40

50

60

70

80

90

100 110 120

0

10

20

30

40

50

60

70

Frequency, GHz

Time, psec

(a)

(b)

80

90

100 110 120

Figure 13.28 Effects of dispersion on eye quality in coaxial and microstrip lines. (a) Eye diagram using a 12.7 mm length coaxial transmission line. (b) Eye diagram using a microstrip with 0.75 mm thick alumina. Source: http://www.ricksturdivant.com/2016/06/04/dispersioneffects/; Courtesy of Rick Sturdivant.

22 Source: Peterson Z., “Transmission Line Dispersion and Losses in Your High-Speed PCB,” URL: https://www.nwengineeringllc.com/article/ transmission-line-dispersion-and-losses-in-your-high-speed-pcb.php.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Figure 13.29 Effect of dispersion on eye quality for a 10 Gb/S signal on a 0.25 mm thick alumina substrate. Source: http://www.ricksturdivant.com/2016/06/04/ dispersioneffects/;Courtesy of Rick Sturdivant.

2

1

0

–1

–2 0

10

20

30

40

50

60 70 Time, psec

80

90

100

110

120

In comparison, consider a microstrip line with a 0.25 mm thick alumina substrate exhibits significantly less dispersion, and as can be seen in Figure 13.29, the eye performance is commensurately improved. The improvement is due to use of a thinner substrate. A thinner substrate has less dispersion, which is the same as saying that its phase is more linear (flatter group delay). Reduction of dispersion in microstrip lines can be achieved by: a) Reducing Substrate Thickness: The substrate thickness, h, effects dispersion. A thicker substrate causes more dispersion. As the ratio of substrate thickness to wavelength in the material diminishes, dispersion is also reduced. Therefore, as frequency is increased, the substrate thickness should be decreased to maintain a required level of linear phase (flat group delay response). b) Reducing Substrate Dielectric Constant: The substrate dielectric constant also effects dispersion and eye quality. For a given substrate thickness, a lower dielectric constant has less effect on eye performance. The lower the dielectric constant, the closer it is to air, which represents the homogeneous (non-dispersive) case. In addition, a lower dielectric constant reduces the ratio of substrate thickness to wavelength. c) Reducing Length of the Transmission Line: The effect of a dispersive transmission line can be reduced if the length of dispersive line is minimized. Obvious as this may seem, the effect of a long, dispersive transmission line is often missed by circuit and board designers. A fairly conservative design goal is to have the substrate thickness less than 5% of a wavelength in the material as in Equation (13.38):23 h f εr h = ≤ 0 05 λ ν0

13 38

where h is the thickness of substrate (i.e. separation between trace and return plane), f is frequency, ν0 is the velocity of light in free space, and εr is the relative permittivity. It is thus not data rate (or frequency), but the data rate × distance product, which is governed by dispersion. When rearranged, equation (13.38) becomes: h≤

0 05ν0 f εr

13 39

which can be used to select the desired thickness of the substrate. For example, consider a 10 Gbps signal. As a general rule, the transmission lines should perform well to a frequency that is at least twice the frequency for a RZ (Return to Zero) signal. For 10 Gbps, this implies a transmission line bandwidth of no less than 20 GHz. For high-purity alumina (εr = 9.9), the resultant substrate thickness using equation (13.39) is 0.25 mm. 13.4.4.4

Effect of Conductor Surface Roughness

Conductor surface roughness (Figure 13.30) at high frequencies is yet another major contributor to signal attenuation or degradation.24 The roughness can increase the total interconnect loss as much as 50% and higher as shown in [11]. 23 Source: http://www.ricksturdivant.com/2016/06/04/dispersioneffects/. 24 Much of the material in this Chapter is derived from [10]

721

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13 Grounding on Printed Circuit Boards

At first thought, the increased loss may be attributed to the longer path current must travel along all peaks and valleys (Figure 13.31); however, if this assumption were true, the current flowing along a rough surface would be expected δ at 1 GHz to be delayed more than the current traveling along the smooth path. This however appears to be incorrect. Measurements have demonstrated that the difference in phase delay between both case is relatively small. δ at 10 GHz In practice, the source of the error is the (again) erroneous assumption that it is current that flows along the transmisδ at 100 GHz sion line structure. In practice, the signal propagates as a quasi-TEM wave (i.e. E- and H-fields), which produce charge density on the trace and plane(s) that guide the electromagnetic wave. As the fields’ intensity decreases due to absorpFigure 13.30 Scanning electron microscope (SEM) photograph of a tion and scattering, the level of current density diminishes too (Figure 13.32). high-profile surface relative to skin depth at 1, 10 and 100 GHz. The roughness effect is simply the increase of absorption Source: Courtesy of Dr. Eric Bogatin. by the non-flat conductor surface due to the increase of the conductor area, at the conductor surface bumps, exposed to the electromagnetic field (assuming the bumps are much smaller than wavelength of the propagating wave). This increase of area on rough conductor surfaces can be substantial, twice or more, implying that the conductor losses may increase manyfold. This effect can be denoted skin effect on the rough surface. At lower frequencies, the surface roughness effects (increases) only the effective resistivity of the conductor. As frequency increases and skin depth becomes comparable and even smaller than the bumps on the conductor surface skin-effect on the rough conductor surface is observed. In order to account for this phenomenon, roughness correction coefficients may be used in transmission line or electromagnetic models [11]. This approach is based on the estimation of increase in attenuation with frequency due to conductor surface roughness. Probably, the first and the simplest roughness correction coefficient (RCC) is so-called Hammerstad-Jensen model, derived for conductor surface with 60-degree triangular bumps and extensively used in microwave applications to evaluate the increase in attenuation of strip and microstrip lines. The main disadvantage of the model is that the maximal value of the expected increase in attenuation was two. This approximation, however, may not be sufficiently accurate in PCB applications, where surface bumps may be comparable and often larger than the skin depth. This limitation is overcome by the Modified Hammerstad RCC (MHRCC) model [11] and is illustrated in Figure 13.33. The roughness correction coefficient, Ksr, includes two parameters, namely, Δ, the Surface Roughness (sr) parameter, which is approximately root mean square peak-to-valley measurement of roughness bumps, and RF, the roughness factor that defines the maximal expected growth of losses due to roughness (increase of the surface area or effective absorption area or length on the rough surface). 22 000×

K sr = 1 +

2 Λ arctan 1 4 π δs

Current

Figure 13.31

RF − 1

13 40

Current

Skin Depth, δ

Current flow along a smooth and rough surface. Source: Courtesy of Dr. Eric Bogatin.

Figure 13.32 The propagating signal is expressed by propagating E- and H-fields. Source: Courtesy of Dr. Eric Bogatin.

Signal trace

ˆy H = Hy (0, t)a ˆ Vp = ax

c εr

Snowball stack-up

ˆy H = Hy (1, t)a

ˆx E = Ex (1, t)a

ˆx E = Ex (0, t)a Dielectric medium Ground plane

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Ksr = 1 +

2 π

·arctan 1.4

Δ

δs

Conductor skin-depth δs =

Δ ∼ root mean square peak-to -valley distance ·(RF – 1) 1

2

π·f·μ·σ

2.8

E Π

RF - roughness factor, defines maximal growth of losses due to metal roughness (increase of surface)

2.6 2.4 Kr2j 2.2 Kr1p5j 2

Plane wave outside

H ∆

Δ = 1 µm

RF = 3

RF = 2 - original

Kr3j 1.8 RF = 1.5

1.6 1.4

“Absorption” by the surface Bumps are much smaller than wavelength!

1.2 1 1 × 107

1 × 108

1 × 109 fj

1 × 1010 1 × 1011 Frequency, Hz

Figure 13.33 Modified hammerstad roughness correction coefficient (The power flow vector is directed along the surface, but the power flows into the conductor on the bumps. Source: Courtesy of Dr. Yuriy Shlepnev, President, Simberian Inc.

where: δs =

1 π f μ σ

13 41

is the conductor skin depth. This expression describes increase in attenuation of plane wave propagating along the conductor surface with triangular bumps. Ksr is of unity value at lower frequency (i.e. no increase in attenuation) and grows with the frequency as illustrated on the curve in Figure 13.33 for Δ = 1 micron. RF = 2 corresponds to the original Hammerstad-Jensen model with 60 triangular bumps and predicts increase in the attenuation by factor of 2. Application of roughness correction coefficients to the analysis of interconnects and their effect on signal propagation could be used simply as an additional factor for transmission line attenuation, for evaluating the increase in losses. In the context of interconnect analysis, this approach can be used only for crude evaluation of the attenuation increase in the channel as such a model is not causal [11]. In a more advanced approach, roughness correction coefficients can be used to correct the internal impedance part of the total per-unit-length impedance of the transmission line [11]: Z r f = K sr Z r + jωL ∞ Ω m

13 42

where Ksr is the impedance roughness correction coefficient and Zint represents the conductor per-unit-length impedance matrix. This approach is causal because it modifies both real and imaginary parts of the conductor impedance. However, correction of the per-unit-length impedance does not account for the actual distribution of the current in the conductors; current flows in an extremely thin layer and higher current density is observed in the conductor corners. Currents on the conductor edges can thus be much larger (Figure 13.34). Also, currents on top and bottom side of a microstrip line can substantially different. Current distribution is also different for different transmission line modes. As a result, differences in the observed attenuation growth with frequency is observed [11].

The Least You Need to Know

• • • •

Interconnects are the major bottleneck in communication between electronic devices, particularly at ultrahigh frequencies, with bit rates as high as of 25–30 Gbps. Certain assumptions applied at lower frequencies are no longer valid, particularly, aspects associated with materials and construction of the PCB. The top-two key obstacles at ultrahigh frequencies are the lossy and dispersive nature of the transmission line materials as well as the effect of rough conductor surfaces. Unlike traditional circuit analysis that models skin depth currents as following the surface contour, which yields incorrect (and illogical) outcomes, in reality, the signal is expressed as propagating E- and H-fields, inducing surface charge on the trace, the density of which diminishes as field intensity decreases due to absorption and scattering.

723

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13 Grounding on Printed Circuit Boards

#5 CurrnetDensity(CutPlane) at 10 GHz; T = 100 ps; Peak; Min = 0, Max = 1.44e + 008 [A/m^2]; 0 [dB] –20 –40 –60 f = 10 GHz –80 sd = 0.026 mil t/sd = 46.15

#6 CurrnetDensity(CutPlane) at 30 GHz; T = 33.3333 ps; Peak; Min = 0, Max = 2.776e + 008 [A/m^2]; 0 [dB] –20 –40 –60 –80 f = 30 GHz sd = 0.015 mil t/sd = 80

Figure 13.34 Current density distribution in trace and planes of symmetric stripline at high frequencies. Courtesy of Dr. Yuriy Shlepnev, President, Simberian Inc.

• ••

From the macroscopic electromagnetics point of view, the conductors are simple materials, described by Ohm’s law with constant bulk conductivity up to the THz frequency range. The scale of the skin depth changes with frequency increase and roughness of the surfaces may increase complexity. Effects of dispersion and losses at ultrahigh frequencies are strongly associated with transmission line design on PCBs

13.4.5

The Dark Side – Return of the Signal: Return Current Path on PCBs

Yes, a Jedi’s strength flows from the Force. But beware the dark side. Anger, fear, aggression; the dark side of The Force are they. Easily they flow, quick to join in a fight. If once you start down the dark path, forever will it dominate your destiny, consume you it will. — Yoda, in Star Wars: Episode V – The Empire Strikes Back [25] The fact that electrical current flows in a closed loop constitutes an absolutely fundamental physical principle.25,26,27 It follows that each signal has an equal and opposite complimentary return current associated with it.28 A key to ensuring that optimum PCB design is achieved lies in the understanding of how and where signal return currents actually flow. Signal integrity (functionality concerns) and EMC (radiated emissions and immunity concerns) performance of the circuit are directly associated with the inductance of the signal and return current paths, which in turn is directly related to the area occupied by them. Careful attention is normally paid to the signal current path while little or no consideration

25 This title is courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD). 26 In the previous section, dispersion and losses at ultra-high frequency signals were discussed in detail. In this (and subsequent) Section these effects are not addressed any further. However, it should be kept in mind that as signal frequencies or data rates increase, phenomena discussed in the previous section will affect the waveform of the propagating (and returning) signal due to losses and dispersion. 27 This a direct consequence of Ampere’s law, or Kirchhoff’s Current law, discussed in detail in Chapter 2. 28 A detailed generalized discussion regarding return current propagation in electrical systems is included in Chapter 2. This Section focuses on the unique application of those principles to current propagation on printed circuit boards.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Figure 13.35

See you on the dark side of the moon. Source: Courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD).

is often given to the path utilized by the return current. It is simply taken for granted that the return signal will sort of take care of itself. Moreover, Figure 13.6 above clearly illustrated that crosstalk completes the “SI/PI/EMC Trio.” All PCB designers should therefore be aware of the impact of crosstalk on signal integrity. As signal traces come into proximity to an aggressor signal, part of that signal is unintentionally electromagnetically coupled into the victim trace as noise. It is well known and understood (as illustrated in a detailed discussion in Chapter 2) that electrical current flow forms a round trip, as the current must return to its source to complete the loop. The path followed by the current will always follow the path exhibiting the lowest impedance possible (if not obstructed). Rather than repeating that discussion here, a practical example related to signal propagation on PCBs will be reviewed (Figure 13.35). PCB planes are often, mistakably, assumed to function as a thick, solid plate of copper, capable of handling virtually any amount of current sunk into it (within the bounds of reason, of course). This may be true at DC and very low frequencies, where indeed current flowing in planes utilizes (almost) the entire cross section of the plane. However, as shown in Chapter 2, and illustrated next, it is apparent that without a priori knowledge of the frequency of the signal current, coming up with an unambiguous response regarding the return path of the current (hence, “the dark side”) is not possible. Fundamental physical laws maintain that current always flows in the path of the least impedance, and subsequently, at lower frequencies, the path of least impedance is, typically, the path of least resistance, while at higher frequencies, it is the path of least inductance. As will be demonstrated, at higher frequencies, returning signal currents tend to stay in proximity to the signal conductor, falling off with square of increasing distance. However, with the increase of frequency, current flowing in the plane is actually forced to flow on the outer surface (or skin) of the plane, due to skin effect,29 resulting in a massive portion of the copper plane unused by the signal return current (DC return current will still occupy the entire cross section of the plane). As a result, the per-unit-length resistance increases, while, on the other hand, total current loop inductance diminishes. As frequencies increase beyond 1 GHz, resistance due to skin effect continues to increase, while the loop inductance reaches a practical lower limiting value. What may not be well understood is “when are frequencies considered ‘high frequencies!’” The change-over frequency can be surprisingly low and may be quite easily approximated to the first-order of engineering accuracy [13]. A simple illustration of the manner the change-over frequency may be approximated is realized using a simple microstrip trace over a ground plane on a PCB. Figure 13.36 portrays a U-shaped microstrip trace routed over a ground plane, and its respective dimensions. The line is driven at the one end, and the load is located at the opposite end. At very low frequencies, the return current is expected to flow straight across from the load to the source, this path being the path of least resistance. At very high frequencies, the large loop area formed by points A B C D A would exhibit a very high inductance (and impedance) and the return current will flow under the trace, following the signal path. Although the return current is now taking a longer path than that at low frequency, the area of the loop formed between the trace and the return current is smaller, hence the path A B C D C B A exhibits lower inductance (and impedance). The lower frequency

29 Skin effect is discussed in detail in Chapter 2.

725

726

13 Grounding on Printed Circuit Boards

Signal trace A

B

per-unit-length inductance of these two paths, L, can be computed using a rough approximation from the rectangular following expression30 [14]: A = h ln

h+

h2 + w2 w

w+

h2 + w2 h

4″

B = w ln C

D Total length of trace: 22″ Trace is: 10 mil wide 1 mil thick 10 mil above ground plane

C = h ln

Ground plane

L=

μ0 2 π

2h a

+ w ln

13 43 2w a

h2 + w2 − 2 w + h − A − B + C μH

where: Figure 13.36 Physical geometry for the U-shaped microstrip example.

w = width of the rectangle (wide dimension) h = height of the e rectangle (short dimension) a = radius of the conductor31

Applying this expression, the obtained inductance of the shorter path (low frequency path) is 733 nH (a more accurate value, of 845 nH, was derived using PEEC [15]), based on a rectangle of 9 (w) × 4 (h) (22.86 cm × 10.08 cm), where the width of the trace is 10 mil. As to the longer (high frequency) path, inductance was estimated as 10.7 nH. The DC resistance of the trace is calculated as 1.45 Ω, and of the long path, it is roughly twice the resistance of the trace, 3 Ω, approximately [13]. The higher frequency inductance is derived based on the assumption that current flows in the plane beneath the microstrip. Using the expression for characteristic impedance of the microstrip structure, Z0 ≈

87 5 98h ln Ω 0 8w + t εr + 1 414

13 44

where: w = width of the microstrip conductor (trace) h = height of the trace above the plane (or thickness of the dielectric) t = thickness of the microstrip conductor (trace) above the plane This expression holds for 0.1 < w/h < 3.0. The characteristic impedance for this microstrip structure is, approximately, 126.1 Ω (assuming height of trace above the plane of 10 mil) and using air dielectric, (εr = 1). From the per-unit-length capacitance of the line, C0 ≈

0 67 εr + 1 414 pF in 5 98h ln 0 8w + t

13 45

and by rearranging the general expression for Z0, L0 =

Z0 C0

13 46

the per-unit-length inductance of the line may be derived. Following this line (while neglecting the thickness of the trace, t), the per-unit-length capacitance derived is of 0.804 pF/in., and hence, the per-unit-length inductance is 10.07 nH/in. It follows that applying this approach for the 22 -long trace results in a total loop inductance of 221.52 nH [15]. Figure 13.37 depicts results of calculation of the magnitude of the impedance for the inductances as well as the combined impedance (i.e. resistance and inductance). As the return current always follows the path of least impedance, the cross-over frequency in this example appears to be 800 kHz, approximately. Below 800 kHz, the return current will take the shortest path, 30 This expression is based on the Biot-Savart law, discussed in Chapter 2. 31 This expression provides a crude estimate, as it considers a conductor with circular cross-section (unlike the rectangular cross-section trace).

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Figure 13.37 Impedance of return current paths for long and short current paths.

100

Impedance (Ω)

Z for shortest path (L = 491 nH) Z for longer path (L = 10.7 nH) Inductance only, longer path (L = 10.7 nH) Inductance only, shortest path (L = 491 nH)

10

1

0.1 0.1

10

1

100

Frequency (MHz)

Termination the path of least resistance, while above 800 kHz, the majority of the (load end) return current will follow the longer path, the path of lower Signal tra inductance.32 ce in top layer Full wave electromagnetic simulations using the Keysight (formerly Via #2 Agilent Technologies) “Momentum,” a 3-Dimensional Planar electromagnetic (EM) Simulator33 can illustrate where currents will travel on e an pl er a PCB at different frequencies. rn y tu la Consider a two-layer printed circuit board comprising of a trace re om d li ott above a solid reference (ground) plane, illustrated in Figure 13.38. Signal So n b source i (drive The circuit includes a signal current source on the top layer, driving n end) Via # a single copper trace winding along its path in a signal layer, and ter1 minated (through a resistive load) at its end through via #2 to the reference plane. The return lead of the signal source is also connected Figure 13.38 A model for evaluation of the current return through via #1 to the reference plane. Naturally, the drive currents will path in reference plane interconnects. be constrained to travel on the trace itself (since the current is driven onto the trace), but the return current path will change as frequency increases. Ideally, impedance between via #1 and via #2 is zero and the voltage appearing across the current source should likewise be zero. The simple schematic hardly begins to demonstrate the actual subtleties, but an understanding of how the return current flows back from Via #2 to Via #1 makes the realities apparent and illustrates how interference can be avoided at high frequencies. The signal propagation path from the source to the reference plane is well-defined, as the trace can be considered as a onedimensional structure. However, the reference plane, being a two-dimensional structure, offers an infinitely large number of alternative paths for the current to flow back to the source. The question is “what is the actual return path utilized by the signal current in the plane?” The answer is revealed in the simulation results presented in Figure 13.39 (for legend see Figure 13.40). Having observed the simulation results and addressed the lower- and higher-frequencies behavior (and the transition between the two ranges), the following paragraphs present a slightly more detailed analysis. From the derivation in Chapter 2, it follows that the fraction (ΔI in [%]) of the return current following the path other than that of the shortest electrical distance can be expressed as:

ΔI =

jω × 100 jω + RC LC

13 47

Based on an intuitive application of Ohm’s law (V = I × R) considering the DC resistance of the current contour formed by the signal and return current paths, one might surmise that the return current follows the shortest electrical distance (having the lowest resistance), i.e. a straight line from the end of the trace back to the source (assuming uniform conductivity of the surface). It would be reasonable to expect, under these assumptions, that the bulk of the return current would indeed take this 32 The actual value of loop inductance in the transition region is very complex, and cannot be calculated without using partial inductances and numerical methods since there are multiple return current paths. 33 For more information on “Momentum” see https://www.keysight.com/il/en/lib/resources/training-materials/momentum-key-features1936424.html.

727

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13 Grounding on Printed Circuit Boards

(a)

(b)

(c)

(d)

Figure 13.39 Simulation results visualizing the return current pattern in a solid reference plane under a signal trace at various frequencies. (a) Frequency of 1 kHz. (b) Frequency of 1 MHz. (c) Frequency of 1 GHz. (d) Frequency of 10 GHz. Source: Simulation run on Keysight (Formerly Agilent Technologies) “Momentum” 3D Planar EM Simulator; Courtesy of Alexander Perez, Agilent Technologies.

Return current pattern in ground plane

Signal trace

Figure 13.40 Legend for the plots depicted in Figure 13.39. Source: Simulation run on Keysight (Formerly Agilent Technologies) “Momentum” 3D Planar EM Simulator; Courtesy of Alexander Perez, Agilent Technologies.

Ground plane

shortest path. Obviously, some (insignificant) current spreading from this main path would be expected to an extent inversely proportional to the increased length (and consequently, the resistance) of the alternative spreading current paths.34 This is clearly supported from equation (13.47) when applied for DC (and very low frequencies) currents, where ω 0 and ΔI 0, thus: lim ΔI = lim

ω

0

ω

0

jω × 100 jω + Ri Li

=0

13 48

This result well supports the outcome of the simulation at 1 kHz presented in Figure 13.38a. Practically all the current follows the shortest electrical distance, therefore only a negligible fraction of the current spreads away from the main return path. The majority of the return current follows the shortest electrical distance, the path of least resistance. Since DC and very low-frequency (typically below a few kHz) current is uniformly distributed across the ground plane spreading out to occupy the entire cross-section of the plane.

34 The question of the actual distribution on the spreading return current is seemingly simple but, in effect, is quite complex. A discussion of the return current distribution at low-frequencies is provided in Appendix J.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

For a microstrip structure, the return current path resistance at low frequencies can be computed as [13]: R0 =

l Ω σ cu wp t cu

13 49

where: R0 = Resistance of the ground plane, Ω σ cu = Conductivity of copper ground plane, Si/m l = Length of the microstrip trace, m wp = Width of the ground plane, m tcu = Thickness of the copper plane, m As frequency increases, additional frequency-dependent perturbation of the current distribution in the planes occurs due to the skin and proximity effects.35 Figure 13.41 illustrates an example of the current distribution in a microstrip and stripline for high-frequency AC currents. The current in the trace and in the plane(s) are drawn toward their corresponding nearby surfaces. At frequencies where the skin depth, δ, is less than tcu, equation (13.50) should be used in place of equation (13.49): R0 =

σ cu

l wp δ

13 50

where the skin depth, δ, is defined as: δ=

1

13 51

π f μ σ cu

where: f = Frequency of interest, Hz μ = Permeability of the plane material (cu), H/m Two important features stand out: (i) The signal current flows only on the outer surface of the conductors, owing to skin effect, and (ii) the current distribution in the reference plane(s) is concentrated underneath (or above) the signal trace, due to the proximity effect. Above the frequency where the proximity effect begins to dominate the current in the conductors attains a minimum-inductance distribution and is invariant with frequency [6]. Quite a different situation occurs at higher frequencies as depicted in Figure 13.39b through d (illustrated for the frequencies 1 MHz, 1 GHz and 10 GHz respectively). Now the voltage-drop across the current path, V = I × ZAC, results from the AC (RF) impedance of the current contour, ZAC, which is more accurately described by resistive and reactive terms: Z AC = RC + jX L C ≈ RC + jωLC Ω

13 52

RC and XL(C) represent the resistance and inductive reactance of the current contour, respectively, while XC = ωLC, where ω is the angular frequency of the signal and LC the net inductance of the current contour. When the resistance of the ground plane is significantly lower than the branch inductive reactance of the ground plane (typically at frequencies exceeding a few MHz), the return current is no longer distributed uniformly over the surface of the plane and does not follow the shortest path.

(a)

(b)

Figure 13.41 Illustration of high-frequency AC current distribution in the trace and reference planes for a microstrip and stripline due to skin and proximity effects (The lighter the shading, the higher the current density). (a) Current distribution in a surface microstrip transmission line. (b) Current distribution in a centered stripline transmission line.

35 Skin and proximity effects were discussed in detail in Chapter 2.

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13 Grounding on Printed Circuit Boards

From equation (13.47) when applied at high frequencies, where ω lim ΔI = lim

ω

∞

ω

∞

jω × 100 jω + Ri Li

∞ and ΔI 1 (100%), we arrive at equation (13.53):

= 100

13 53

Figure 13.39b through d clearly support this outcome at higher frequencies.36 The inductive reactance, XC = ωLC, is proportional to frequency and the area of the loop enclosed by the current contour. As frequency, ω, rises, the inductance LC goes somewhat down, but in a rate lower than the increase in frequency. The influence of the inductive reactance becomes increasingly dominant. For the current to follow the path of least impedance, it must flow through the contour exhibiting a lower inductance. The total inductance of the current contour is associated with the net flux per unit of current flowing through the signalreturn contour. By definition, the self-partial inductance of the i-th leg of the loop, Lpii, is37 (refer to Figure 13.42), Lpii ≜

ϕii ϕ = ii Ii I

13 54

where the index i relates to the legs i = 1, 2, 3, 4 of the loop. Note that in an electrically small circuit or loop I1 = I2 = I3 = I4 = I. Similarly, the mutual partial inductance, Lpij, between i-th and the j-th legs of the circuit is defined as, Lpij ≜

ϕij I

13 55

The total inductance of the current contour (neglecting the effect of legs 2 and 4 of the circuit38) is associated with the sum of the magnetic flux, ϕ11 and ϕ33, generated by and surrounding the conductors represented by Leg 1 and 3, respectively, and the

Flux opposing outside loop Leg 4

Flux from Leg 1 (top conductor) ϕ11

Leg 1

X

I1 = I

X

X X

X

X

X

Flux from Leg 3 (bottom conductor) ϕ33

I3 = I

ϕ13 X

X X

Flux opposing outside loop

X X

Flux reinforcing inside loop

Z

730

Leg 2

Leg 3

(a) Lp11

I3

I1

Lp13

Lp33

(b) Figure 13.42 Self and mutual inductance of the signal-return contour (Flux from Legs 2 and 4 Neglected) (a) Electromagnetic representation. (b) Circuit representation.

36 At the frequencies 1 GHz Figure 13.39c and d, respectively, the current distribution both in the trace and the return plane, is not uniform, as a result of resonance at the high frequencies on the electrically large structures. 37 The concepts of partial, self and mutual inductance were discussed in detail in Chapter 2. 38 This approximation is valid thanks to the very short length of the vias interconnecting the signal trace and the return plane.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

magnetic flux ϕ31 and ϕ13, generated by the one leg, but surrounding the other, relative to the loop current, I. The magnetic flux fields, ϕ11 and ϕ31 as well as ϕ33 and ϕ13, are opposite in polarity due to the equal but opposite currents producing them. The resultant total magnetic flux confined by the contour of the current path, is thus the difference between the flux produced by the signal and return conductors: ϕNet ≈ ϕ33 − ϕ13 + ϕ11 − ϕ31

13 56

Combining equations (13.54) through (13.56) results in: LTotal ≈ =

ϕ33 − ϕ13 + ϕ11 − ϕ31 ≜ Lp33 − Lp13 + Lp11 − Lp31 I

=

13 57

Lp33 + Lp11 − Lp31 + Lp13

The diminishing inductance (occurring when Lp11 Lp31 and Lp33 Lp13) forces the return current even more to concentrate beneath the signal trace, further reducing the contour area confined by the signal and return current paths (i.e. decreasing the spacing between the signal and return paths). Equation (13.57) thus reduces to: LTotal ≈ 2 Lp33 − Lp13

13 58

The simple illustration presented in Figure 13.39 visibly demonstrates that the loop with the least area is quite evidently formed by the top trace and the portion of the reference plane directly underneath it. While Figure 13.39a illustrates the return current path at frequencies DC (or at very low frequencies), Figure 13.39b through d reveal that the path that most of the highfrequency current takes in the reference plane resulting in the smallest loop area is directly under the top conductor. Even at frequencies as low as 1 MHz, the return current path is nearly all under the top trace. In practice, the resistance in the reference plane causes the current distribution at low and mid frequencies to spread and attain a pattern somewhere between a straight back and directly under the top conductor (equation (13.47)) demonstrated the dependence on RC/LC, the contour resistance and inductance, respectively). Figure 13.43 illustrates the application of the above effect in a practical high-speed printed circuit board. Finally, consider a digital waveform switching between two logic states (Figure 13.44), the initial transition wave front comprises of high-frequency spectral content, while the steady portion of the waveform is of a DC nature. As a direct consequence of the above discussion, it is now obvious that the DC and AC components of the signal return currents may follow totally different routes on the PCB. The return current during the waveform transition time follows a path of least inductance; after the waveform settling time (e.g. a few nanoseconds), the return current may take a different route, that of least resistance. As a consequence, some distortion of the waveform particularly during the transition time could occur.

6VDC input

+5Volt

GND

Voltage regulator

+5Volt

GND Reference plane

Figure 13.43

+5Volt 56 MHz oscillator

GND

Signal trace Return path in plane

56 MHz clock signal currents follows the path of least inductance. Source: Courtesy of Dr. Todd Hubing, LearnEMC.

731

732

13 Grounding on Printed Circuit Boards

Settling time

With the increase of switching frequency, going up to ultrahigh speeds (in the 10 Gbps and beyond), and the reduction of transition time of the digital signal waveform, signal bandwidth broadens (virtually “from DC to daylight”) and subsequent dispersion of the pulsed signal take further toll, as different, spread out, spectral components in the waveform take different paths, traveling at varied velocities (and hence experience dissimilar delays), resulting in further waveform distortion.

“DC”

DC ?

“DC”

Transition time

13.4.6

Return Current Distribution

Figure 13.44 Digital waveforms represent a transition (high-frequency spectral content) between two “DC” states.

The reasoning in the previous section may lead to the conclusion that all the return current tends to flow directly and only underneath the signal trace. Observation in the plots in Figure 13.39 illustrates that although the highest current density is underneath the signal trace, the RF current also tends to spread out in the plane to either side of the trace’s route. The distribution of high-frequency return current in a reference plane adjacent to a signal trace routed in the form of microstrip is more accurately described by equation (13.59) [16–18]:39

J GP

I0 d = − πw

tan

−1

d+ h

w 2

− tan

−1

d− h

w 2

+

4h wp π

1 wp 2 − d2 2

A m

13 59

where: JGP(d) = Current density at a distance, d, from the trace centerline, A/m I0 = Magnitude of the total current flowing on the source trace, A d = Distance from source trace centerline, m h = Height of trace above the reference plane, m wp = Width of the ground plane, m w = Width of Trace, m An approximate expression for the return current distribution at a distance, d, from the centerline of the signal trace (assuming a narrow trace close to an infinitely wide reference plane) is [19]: J GP d ≈

I0 1 πh 1 + d h

2

A m

13 60

Using this current distribution, the effective resistance, R0, of the path occupied by the actual return current can now be computed as [16]: R0 d =

J GP d l Ω I 0 δ σ cu

13 61

Note how R0 decreases the farther the coupled trace is from the source trace. Figure 13.45 illustrates the return current distribution in a reference plane beneath a Signal Trace in a typical printed circuit board. The peak current density lies directly under the trace while falling off sharply away from the trace. From Figure 13.45, it is evident that approximately 95% of the return current flowing in the reference plane travels in a strip as wide as 3 times the trace-to-plane spacing (h) or three times as wide as the trace width (w), whichever is smaller, centered along the trace’s path [20]. This current distribution in the reference plane results from the balance of two opposing forces. a) If all the return current were to be concentrated immediately underneath the trace, it would have exhibited a higher partial self-inductance, as it would have in effect acted as a narrow trace, disregarding the entire breadth of the plane. The impedance resulting from this inductance is proportional to frequency (ZL≈ωLS, where LS represents the partial self-inductance of the return path). b) Conversely, if the return current were to spread farther apart from the trace, taking full advantage of the entire plane, the inductance resulting from the large loop area created by the widely spread return current will increase. The impedance 39 tan−1( ) is also denoted arctan( ) or atan( ).

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

120 100 Return current density %

Figure 13.45 Current distribution across the reference plane for a microstrip trace as a function of the distance from the centerline of a microstrip trace centered 1 mm above a 20 mm wide plane. Source: Courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD).

80 60 40 20 0 –30

–10

–20

0

20

10

30

Proximity to center of trace (mil/μm)

resulting from this inductance is also proportional to frequency (ZL≈ωLL, where LL represents the loop inductance between the signal trace and the return path). Equilibrium is reached therefore when optimum current distribution is attained, balancing the two opposing inductances, resulting in some spreading of the return current in the reference plane.

Conductor

y

h2

l There is, therefore, a sweet spot where the total energy stored in the electromagnetic field surrounding the trace is optimized, x also clearly observed in the lack of frequency-dependence in w h1 both equation (13.59) and (13.60). This frequency-independence demonstrates that once the cross-over frequency is exceeded for the particular transmission line structure, the current density distribution remains frequency-invariant. Conductor In addition to the special case of microstrip line discussed above, closed-form expressions have been developed for several stripline Figure 13.46 General asymmetric stripline geometry. Source: Adapted from Zhang et al. [21]. configurations [21] (all dimensions are in Figure 13.46) [22]: In a general, asymmetric stripline configuration, the current density on the upper and lower ground planes will differ. The current density on the upper plane (at height h2 above the trace) is found to be:

J upper

I tan − 1 = πw

e

π x−w 2 l

− cos

πh2 l

πh2 sin l

e − tan

−1

π x+w 2 l

− cos

πh2 l

πh2 sin l

13 62

and on the lower plane at height h1 below the trace):

J lower

I tan − 1 = πw

e

π x−w 2 l

− cos

πh1 l

πh1 sin l

e − tan − 1

π x+w 2 l

− cos

sin

πh1 l

πh1 l

13 63

Two additional special cases can now be derived: a) Special Case #1: Symmetric Stripline For a symmetric stripline geometry (h1 = h2), equations (13.62) and (13.63) reduce to the same expression. By substituting h1 = h2 into these expressions, the current density on both ground planes reduces to: J x =

π x−w 2 I tan − 1 e 2h1 πw

− tan − 1 e

π x+w 2 2h1

13 64

b) Special Case #2: Asymmetric Stripline with h2 = 2h1 This particular configuration occurs for some common stackups in multilayer PCBs when a “dual stripline” configuration is implemented (this structure is cost-effective and preferred as it enables two signal traces to be placed between two

733

734

13 Grounding on Printed Circuit Boards

reference planes). Setting h2 = 2h1 in equations (13.62) and (13.63), the following expressions are obtained for the currents on the upper and lower ground planes, respectively: π x−w 2 π x+w 2 I tan − 1 1 1547e 3h1 + 0 57735 − tan − 1 1 1547e 3h1 + 0 57735 J upper = 13 65 πw and on the lower plane at height h1 below the trace): J lower =

π x−w 2 π x+w 2 I tan − 1 1 1547e 3h1 − 0 57735 − tan − 1 1 1547e 3h1 − 0 57735 πw

13 66

c) Special Case #3: Microstrip Line with h2 ∞ For the case of a microstrip line, the upper ground plane is not present. This case can be obtained by taking the limit of the expressions given in equations (13.63), with h2 ∞. When taking the limits of the arguments with h2 ∞ (or l ∞) [21]: b a eu − cos a u 13 67 lim = u ∞ b b sin u Thus, the argument in the first term of equations (13.63) reduces to: e

π x−w 2 l

lim

l

− cos

πh1 l

πh1 sin l

∞

=

2x − w 2h1

13 68

with a similar result for the argument in the second term. Therefore, as h2 ∞, the current density on the lower ground plane reduces to: I 2x − w 2x + w J lower x h2 ∞ = tan − 1 − tan − 1 A m 13 69 πw 2h1 2h1 which is actually equivalent to the expression derived for the microstrip comprising of a single trace over a ground plane. When it is necessary to compute the fraction of the total current flowing on the two ground planes, i.e. the fractional total current normalized to the total current on the signal trace on one of the ground planes (say, the lower plane) is: I lower

1 = − I

∞

J lower dx

13 70

−∞

And in a similar manner, for the upper plane (in an asymmetrical stripline structure):40 I upper

1 = − I

∞

J upper dx

13 71

−∞

In [21], it was shown that the percentage of the total current on the ground planes (relative to the total current on the signal trace) can be expressed as: I lower

=

I upper

=

1−

h1 l

× 100

13 72

and h1 × 100 l

13 73

Two more points are worthy of discussion in this context. The first is that the expressions presented above are for current density in the ground plane(s), rather than the total current in a certain distance, x, from the trace centerline. This question becomes of great interest in the case of common-impedance interference coupling between an aggressor and victim trace routed in proximity to each other, where the “common-impedance” is the ground plane itself 41 (Figure 13.47). It is obvious that the effect of the aggressor trace on the victim trace will be limited to some range x1–x2 from the centerline of the aggressor trace (we may name that range “the zone of influence ” on the victim trace, {−dV, +dV}. 40 Note that the minus sign in the expression is due to the opposite direction of the trace current, I, and the current density in the plane, J. 41 This coupling mechanism is discussed in detail in the next section. The information in this section serves as foundation for that discussion.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Aggressor trace

Victim trace JGP(d)V h

JGP(d)A

d

“Influence zone”

Figure 13.47

Common impedance interference coupling between adjacent, parallel traces.

Commencing from equation (13.60) above and integrating from some x1–x2 integrating x = x2

I x1

x2

x = x2

J GP x dx ≈

= x = x1

I0 =h π

x = x1 x = x2

x = x1

I0 1 πh 1 + x h

2

dx = 13 74

1 dx h2 + x 2

noting that the integral has the form, which is easily solvable, 1 1 x +C dx = tan − 1 a2 + x 2 a a

13 75

We derive: I x1

x2

=h =

I0 π

x = x2

x = x1

I0 x tan − 1 π h

1 I0 1 x tan − 1 dx = h π h h h2 + x 2 x = x2 x = x1

=

I0 π

x = x2 x = x1

tan − 1 x 2 − tan − 1 x 1

= 13 76 A

The fraction of the current enclosed between x = x1 and x = x2 is, thus: I x1 x2 I0 = I0 πI 0

tan − 1 x 2 − tan − 1 x 1

=

tan − 1 x 2 − tan − 1 x 1 π

13 77

This expression can be of great use in assessing the necessary separation between an aggressor and victim trace, given the maximum allowed interference coupling to the trace (i.e. “crosstalk”),42,43 addressed in the following section. The second point relates to “edge effects.” The initial analysis in [21] were obtained by assuming that the ground planes extended to infinity. In reality, however, the ground planes are typically much larger than the width of the traces, but not infinitely large. Results obtained through numerical computations for ground planes of width 10 w provide insight into the effects of a truncated ground plane. The slight increase in current density at the edges of the ground planes is presented in Figure 13.48. As the analytical results assume an infinite ground plane, edge effects are not captured by them, while the numerical results do demonstrate the slight increase in current density at a small region at the edges of the ground plane. Obviously, the larger the ground planes are as compared to w and h1, the smaller will be the edge effects [21].

13.4.7

Crosstalk on PCBs – The Conversation We Wish Would Stop!

Consider a case where two traces are routed adjacent to each other (Figure 13.49). When a signal propagates along an active transmission line (called “aggressor” or “driven” line), electric flux emerges from the line while magnetic flux encircles the line. These flux fields are not confined to the immediate space between the signal and its associated return path. Rather, some of the flux extends into the surrounding area. These fields are entitled “fringe fields” (Figure 13.50). 42 Mechanisms of interference coupling between traces, also known as “crosstalk” are discussed in following section in further detail. 43 The permissible level of allowable interference coupling would normally be set, for instance, in terms of signal-to-noise ratio (SNR), in the case of analog lines, and the noise immunity level (NIL) or level of permissible common-mode interference allowed to preclude excessive radiated emissions from an I/O victim line.

735

13 Grounding on Printed Circuit Boards

Figure 13.48 Comparison of analytical and numerical results for the current on the lower ground plane for h2 = 2h1. Source: Adapted from Zhang et al. [21].

1

w/h1 = 1.0

0.1

–Jlower*(w/l)

0.01 w/h1 = 0.5

0.001

Numerical results Analytical results

0.0001 0

1

2

3

4

5

x/w

Electric field flux emanating from the driven trace terminates on any adjacent metallic structure (Gauss’s law of electric fields), while magnetic fields surrounding the transmission line partially also encircle nearby metallic d structures (Gauss’s law of magnetic fields). Consequently, if the adjacent metallic structure happens to be a signal trace stray current and voltage (actually, electromotive force, or emf ) sources are deposited into that trace (Figure 13.51). Clearly, as separation increases between the two traces, the fields (and hence the coupling) drop off quickly. However, if sufficiently Figure 13.49 Fundamental configuration for close, noticeable interference may be picked up by the victim trace. The crosstalk between aggressor and victim lines. resultant current flowing on the receptor or “victim” trace is now subject to the same behavior as the intended signal flowing on the victim line and may experience reflections and distortions, as well as re-radiate fields or couple to other closely spaced traces. Likely outcomes of crosstalk are degradation of signal integrity and increase of EMI from the PCB. Many failures in EMC-radiated emission tests are due to emissions from “quiet” I/O lines carrying residual interference current induced onto that line by “noisy” signals internal to the PCB, due to poor PCB layout. The electric and magnetic field coupling between conductors is also commonly known (using equivalent circuit models) as “capacitive” and “inductive” coupling, respectively. This equivalence between the circuit (“capacitive,” “inductive”) and Aggressor (Driven) line

Victim line

h

736

Signal trace

Signal trace

Return (Reference) plane

Return (Reference) plane

(a)

(b)

Figure 13.50 Fringe electric (a) and magnetic (b) field flux due to current flowing in an “Active” transmission line. (a) Electric field flux emerging from an active (current conducting) trace. (b) Magnetic field flux surrounding an active (current conducting) trace.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Aggressor trace

Victim trace

Victim trace

Aggressor trace

Return (Reference) plane

Return (Reference) plane

(a)

(b)

Layer2_GND

(c) Figure 13.51 Electromagnetic crosstalk mechanisms between adjacent traces. (a) Electric (or capacitive) coupling: electric flux terminating on an adjacent victim trace. (b) Magnetic (or inductive) coupling: magnetic field flux encircling an adjacent victim trace. (c) Inductive and capacitive coupling between two adjacent microstrip trace.

electromagnetic (“electric,” “magnetic”) jargons allude to the fact that mutual capacitance is representative of the electric coupling between the lines, while mutual inductance represents the magnetic coupling between the lines. Though both capacitive and inductive coupling play a role in crosstalk, their respective effect significantly depends on the circuit layout and topology. Figure 13.51 depicts a simplified model for crosstalk, consisting of capacitive and inductive coupling between short sections of traces on a printed circuit board. Capacitance, CG, exists between the traces to the return plane, playing a role in the characteristic impedance of the traces and the signal propagation delay along the line. Also, the inter-trace capacitance, CM, forms the path for undesired signal coupling (capacitive crosstalk) between the traces. In addition, both the aggressor and victim traces exhibit self-partial inductances, LA and LV, respectively, also relevant for determining the characteristic impedance and signal propagation delay (similar to the capacitance to the return plane). Due to the asymmetry of this configuration, i.e. a narrow trace above a broad return plane, the flux contribution due to the current flowing on the trace and through the return plane are unequal, yielding partial flux cancellation only, hence resulting in radiated emissions from the circuit. The mutual inductance, LM, between the two trace circuits gives rise to the inductive coupling (or crosstalk) between the two circuits. In electrically short lines, capacitive coupling appears as a current source in parallel to the victim line, where the induced current is proportional to the mutual capacitance, CM, and the rate of change of the source line voltage. Conversely, inductive coupling appears as a voltage (emf ) source in series with the victim line, where the induced emf is proportional to the mutual inductance, LM, and the rate of change of the source line current. dV S , A dt dI S , V V L = − LM dt I C = CM

13 78

where IC and VL are the capacitively induced current and inductively induced voltage in the victim line, respectively, due to a time-variant source voltage, VS, and current, IS, in the aggressor circuit. In electrically long lines, this expression is correct for electrically short fractions of the traces only. Coupling in such lines occurs at the position of the aggressor signal wave front (position of transition of the voltage or current waveform), as it

737

738

13 Grounding on Printed Circuit Boards Driven propagating signal

Driven propagating signal k

k+1 Lm Cm

Lm

Lm

Cm

Backward

k

k+2...

k+1 Lm

Cm

Lm

Cm

Cm

(a)

Lm Cm

Forward

Backward

Forward

k+2...

(b) Driven propagating signal k

k+1 Lm Cm

Lm Cm

k+2... Lm Cm

Capacitive

Capacitive

Inductive

Inductive Combined Forward

Combined Backward

(c) Figure 13.52 Capacitive and inductive crosstalk mechanisms in electrically long lines. (a) Capacitive crosstalk. (b) Inductive crosstalk. (c) Combined crosstalk.

LA

Figure 13.53 Fundamental model of capacitive and inductive coupling between trace sections.

ILF ICF

LM LV CM CG Aggressor trace

ILN ICF CG Victim trace

propagates along the line. The local properties of the transmission line determine the coupling, while the termination impedance comes into play only as soon as the wave front arrives there (Figure 13.52). In practical situations, both capacitive and inductive crosstalk mechanisms are present simultaneously. The capacitively induced currents in the victim line emerging from the capacitance between the traces (represented as a current source in parallel to the line), propagate both forward, towards the far-end as well as backwards, towards the near-end (ICF and ICN, respectively, in Figure 13.53) of the victim trace. The inductively coupled voltage source (represented as an induced emf in series with the line), on the other hand, drives current in the victim line (ILF and ILN in Figure 13.53) in a direction opposite to the current flowing in the aggressor line (note the negative sign in equation (13.77)). Consequently, the capacitive and inductive coupled signals reinforce themselves in the backward direction, whereas they tend to cancel in the forward direction, in particular in stripline configurations. The total coupled signals flowing backwards are known as “backward crosstalk,” or “near-end crosstalk” (NEXT), whereas the total coupled signals flowing forward (and practically cancel out), as “forward crosstalk” or “far-end

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

crosstalk” (FEXT). The features of the NEXT and FEXT differ dramatically: The NEXT constitutes a constant-magnitude pulse, with a width extending to twice the propagation time down the coupled region between the traces, whereas the FEXT is characterized as by a narrow pulse, having a width equal to the transition time of the aggressor signal, but an amplitude growing as the coupled region between the traces increases [7]. NEXT reaches its peak magnitude and then remains constant at the so-called “critical length,” LC, that is, the length at which the round-trip propagation time equals the transition (rise or fall) time of the signal, tt: 2 T PD m tt

LC =

13 79

where L is the physical length of the transmission line [m] and TPD is the propagation delay [sec/m]. TPD is estimated using T PD ≈ 1 017

a εr + b; sec m

13 80

where: εr = the relative permittivity of the dielectric substrate on the PCB, and: a = 1, b = 0, for stripline a = 0.475, b = 0.67, for microstrip Defining the maximum crosstalk coefficient as kx, we thus obtain: kx NEXT =

L L ; if 1

b) For the stripline:

1

XTSL dB = 20 log 1+

Seff 2 h1eff h2eff 1

XTSL dB = 20 log 1+

Seff 2 h1eff h2eff

C RT ,C RT ≤ 1 13 88 ,C RT > 1

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

In our case, CRT is found to be 3.58 × 102 1, hence the trace can be assumed to be electrically long and thus the crosstalk (XT) is computed using equations (13.87) and (13.88) for the case CRT > 1 and the subsequent values obtained are:

•• •• •• ••

XTMS = −13.97 dB XTSL = −24.61 dB With the separation to the planes doubled, i.e. HMS = 12 mil (total substrate thickness) HSL = 24 mil (total substrate thickness) h1 = 12 mil (distance of trace from bottom plane, from center of trace) h2 = 12 mil (distance of trace from bottom plane, from center of trace)

while maintaining all other parameters unchanged, the values of crosstalk change dramatically: XTMS = −6.02 dB XTSL = −13.98 dB

Note that the more negative XT is, the better the isolation between the traces. In digital circuits, inductive coupling is more predominant than capacitive coupling, owing to the low-impedance nature of digital drivers, whereas capacitive coupling is more predominant in high-impedance (often analog) circuits.

13.4.8

Common Impedance Coupling on PCBs

“Coupling is frenzy; decoupling is farce.” — David Mitchell, The Bone Clocks A third and very meaningful coupling mechanism on PCBs is common impedance coupling. As shown in Chapter 4, common impedance coupling is associated with the interaction between the return current of the aggressor circuit flowing in the return path of the reference plane, as it weaves its way back to its source through the expansive wasteland of copper in the unseen “dark side” of the signal (Figure 13.35 above) in a path common to the victim circuit. This could be of particular concern when noisy, high-current (e.g. digital) circuits, share a common return path with sensitive (e.g. analog) circuits. Figure 13.56 illustrates a mechanism by which coupling occurs between an aggressor trace and a victim trace, due to the fraction of the aggressor trace return current, JGP(d)A, flowing under the victim trace. The path of the victim return current distribution is also shown, symbolized as JGP(d)V. The “influence zone” is the area where an overlap occurs between the two current distributions, and it determines the extent of interaction between the two traces. The fraction of the return aggressor current flowing in the victim return current path efficiently couples into it, as it adds to the victim’s return current flowing through that common path, appearing as noise in the victim circuit.45 The crosstalk mechanism can therefore be considered as a signal-to-noise transformation effect, defined as the ratio of the noise voltage appearing over the return path of a transmission line common to that of the victim line and the signal voltage transferred over the line. This ratio is displayed in Figure 13.57 [26]: This “ground lift” voltage may subsequently be used as driving voltage to an unintentional antenna formed by cables connected to the reference plane, resulting in excessive radiated emissions (i.e. EMI). The interesting aspect is the asymptotic Figure 13.56 Common impedance crosstalk through a shared return plane.

Victim trace

Aggressor trace

JGP(d)V h

JGP(d)A

“Influence zone”

d

45 The manner of computation of this fraction of the trace driven current in the “influence zone” was demonstrated in the previous section, in association with Figure 13.46 which is repeated here for convenience within context.

741

13 Grounding on Printed Circuit Boards

Figure 13.57 Signal-to-noise transformation for a PCB transmission line. Source: Adapted from Brooks [26].

0 Ref. noise voltage/signal voltage [dB]

742

–20

–40

–60

–80 1 × 105

1 × 106

1 × 107

1 × 108

1 × 109

1 × 1010

Frequency [Hz]

leveling of the “ground lift” voltage at the higher frequencies. The level of this asymptote can be calculated from the transmission line geometry. Analyses and experiments have shown that this same model can be applied in order to assess the crosstalk between two adjacent PCB traces over a common ground reference plane. Here, too, the crosstalk asymptotically approaches a fixed level, commencing at the frequency at which the driven transmission line length corresponds to quarter wavelength. Above this frequency, known as the “cross-over frequency,” crosstalk asymptotically arrives at its maximum level for a given transmission line geometry. This level is also determined by the length of the common run of the two transmission lines and velocity of propagation). The maximum level of crosstalk can be determined using per-unit-length parameters for the two adjacent lines. Assuming two identical lines, running in parallel at a fixed separation, the ratio of the per-unit-length line inductance, LPUL, and mutual inductance, MPUL, is required and is expressed as [26]: Sd ≈

M PUL Jd 1 = = LPUL J0 1+ d h

13 89

2

where d is the horizontal distance from the trace centerline in the return plane and h represents the height of the aggressor trace above the return plane. As shown above, high-frequency return currents tend to flow in the return planes immediately adjacent to the signal trace. The current slightly spreads out in the plane, but otherwise (if not obstructed) follows the signal trace. Equation (13.89) (derived from equation (13.60) above) expresses the approximate extent of spreading of the current distribution under the trace, S(d). Figure 13.58 illustrates the line geometry and the current density distribution in the reference plane. The premise in [26] was to replace the current density J0 in the ground reference plane adjacent to the driven (“aggressor”) trace its per-unit-length inductance, LPUL, as the two are directly proportional. The remaining current density, Jd, under the victim trace, is then replaced by the per-unit-length mutual inductance, MPUL, between the driven and the victim trace. The asymptotic crosstalk level (referenced to the signal level in the driven trace as 0 dB) can be interpreted as attenuation, ATT, depending on the PCB trace configuration, i.e. [27] ATT dB = 20 log

d

h

J0

Figure 13.58 Geometry of two traces of common-run over a reference plane, and current density distribution in the plane. Source: Adapted from Brooks [26].

Jd

LPUL + M PUL M PUL

13 90

which is illustrated in Figure 13.59. Using this approach to crosstalk, its envelope in the frequency domain can be easily drawn using the maximum value of equation (13.90) for frequencies above FCO and values decreasing proportional to frequency below it.46 From equations (13.89) and (13.90), the benefit of diminishing the proximity of the trace to the return planes, both in the microstrip and stripline configurations, is self-evident! The

46 Although the analysis is valid only for properly terminated lines, which is almost never the case in digital boards, at least there much insight to be gained from this analysis [26].

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

“Critical frequency” (Trace length = λ/2)

0 dB = Signal level on aggressor (active) trace 0

Transmission line approach

Attenuation

Crosstalk (dB)

–20 –40 –60 Resistive coupling

l to na i.e. o i , rt po ve e) ro acti ctiv p e u r g lin y ( ind up enc ive, o C equ cit fr apa c

FCO Fcritical 2π

–80 Low frequency approximation –100 0.001

0.01

0.1

1

10

100

1000

10 000

Frequency (MHz)

Figure 13.59

Crosstalk between two identical terminated PCB traces. Source: Adapted from Brooks [26].

Figure 13.60 Coupling levels off above 12 mil separation (simulated by the iCD stackup planner). Source: Courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD).

120

Impedance [Ω]

100 80 60 40 20 0 0

2

4 6 8 10 12 14 16 Trace clearance ( ) vs dielectric thickness ( ), mil

18

20

smaller the separation, the better are the effects of capacitive coupling reduced, owing to the increase of trace to return capacitance. On the other hand, when keeping the signal traces closer to the return plane than the mutual separation, the plane becomes the preferred return path, and inductive crosstalk also decreases considerably. As can be clearly observed from Figure 13.60, the differential impedance, or coupling, of two parallel traces levels off at 100 Ω beyond a trace clearance of 12 mil (◆ curve). All other factors remaining equal, the differential impedance will always be 100 Ω regardless of increased spacing, which also represents the point at which crosstalk (coupling) begins to occur. This curve in Figure 13.60 also defines, therefore, a roadmap for the necessary spacing for single-ended and coupled pairs. In this case, once the separation is less than 12 mil, the two traces begin to efficiently couple [25]. The easiest way to reduce crosstalk from an adjacent aggressor trace is, naturally, to increase the spacing between the aggressor and victim traces. Crosstalk is diminished approximately by a factor of four as spacing is doubled. The return current distribution of two parallel traces (Figure 13.61) demonstrates the overlap of the aggression and victim return signal currents on the surface of the microstrip reference plane. As a matter of fact, the overlap will be greater at lower frequencies when the return currents tend to spread out, thus following the path of least resistance, while at higher frequencies the return currents follow the path of least inductance and are tightly distributed beneath (and slightly about) the traces.47 Figure 13.62 qualitatively illustrates the effect of trace separation on current distribution beneath two identical parallel traces and hence, on “common impedance” crosstalk between the traces. Even this qualitative illustration reveals two key points: (i) The pattern of coupling is practically frequency-independent (beyond the “cross-over” frequency (which is clearly valid for both 100 MHz and 1 GHz). This well supports the independence 47 Recall, though, that above the “cross-over” frequency (between “lower” and “higher” frequencies), the high-frequency current distribution in the reference plane, beneath and about the trace, is frequency-independent.

743

13 Grounding on Printed Circuit Boards

Figure 13.61 Parallel races and return path (common impedance) crosstalk (simulated by the iCD stackup planner). Source: Courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD).

120 100 Return current density %

744

80 60 40 20 0 –30

–20

–10

0

10

20

30

40

50

Proximity to center of trace (mil/μm)

(a)

(b)

(c)

(d)

(e) Figure 13.62 Qualitatively demonstration of trace separation on current distribution beneath adjacent identical and parallel traces (w = 0.173 mm (6.8 mil), h = 0.105 mm (3.9 mil)) (a) F = 100 MHz, separation 10 μm (0.4 mil). (b) F = 100 MHz, separation 200 μm (7.9 mil). (c) F = 1 GHz, separation 10 μm (0.4 mil). (d) F = 1 GHz, separation 200 μm (7.9 mil). (e) F = 100 MHz, separation 600 μm (23.6 mil). Source: Created with CST Studio SuiteTM 2021.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Table 13.1 Fraction (in percent) of the return current density within a normalized distance of ±d/h from the signal trace centerline. Fraction of cumulative current density at distance, d from aggressor trace centerline (%)

d/h

2

70

5

87

10

94

20

97

of the return current distribution of frequency; and (ii) the greater the separation, d, for a given height above the ground plane, h, the dramatically lower the resultant (common impedance) coupling is (this can be observed from the comparison of Figure 13.62a, b, and e. In addition to reducing crosstalk through separation between adjacent traces, crosstalk can also be lessened by decreasing the separation between the traces to the adjacent return plane. This approach may be more cost-effective when real-estate on the PCB is limited. Tight coupling (i.e. reduced separation) between the trace and the return plane ultimately results in diminished crosstalk [25]. The significance of common impedance crosstalk and the combined effect of separation between the traces, d, and the height above the return plane, h, can now be easily demonstrated. Consider a digital processor, drawing a current surge of 10 A through the return plane common to an analog circuit. The analog circuit contains a 24-bit analog-to-digital (A/D) converter, with a least significant bit equivalent to 5.9 nV per 1 V of supply voltage. Assuming a practical plane impedance of 40 μΩ, this voltage is equivalent to 0.15 mA, approximately, constituting 0.15% of the digital switching current. The necessary separation, d, between the digital and the analog traces in order to preclude any interference must be increased so that 99.97% of the digital return current is contained within the distance from the signal trace centerline, d. Table 13.1 presents the fraction (in percent) of the cumulative return current density within a distance, d (normalized to height of the trace above the return plane), from the centerline of the aggressor signal trace, ±d/h, where d is the horizontal distance and h the height of the trace above the ground plane. The fraction of the cumulative current density shown in Table 13.1 provides little insight into the actual total current enclosed within the “influence zone” under the victim trace (in a microstrip structure). In the previous section, the fraction of the current enclosed between x = x1 and x = x2 was shown to be I x1 x2 tan − 1 x 2 − tan − 1 x 1 = I0 π

13 91

where the range {x1, x2} relates to the “influence zone” of the victim trace (effectively, from −dV to +dV), see Figure 13.56. From Table 13.1 it follows that with typical heights, h, of 10 mil, a separation, d, greater than 200 mil (or 5 mm) would be required. Such separations are almost always unattainable in contemporary PCB designs, with practical real-estate constraints. One of the solutions for eliminating common impedance crosstalk, by means of split return planes, is addressed later in this chapter.

13.4.9

Consequences of Transmission Line Topology on EMI and Crosstalk Control

Crosstalk is three dimensional and has been shown to be dependent on the trace-to-trace separation, d, the trace to plane(s) separation, h, parallel segment length, the transmission line load, and the technology employed. However, crosstalk also varies depending on the physical stackup configuration. Figure 13.63 illustrates the effect of transmission line topology on EMI and crosstalk performance of the circuit. In a co-planar transmission line (Figure 13.63a), the traces are exposed and no reference plane is present. The electric flux terminates on adjacent metallic structures. If those happen to be adjacent signal traces, significant crosstalk may be the result. Effective magnetic flux cancellation will be limited by the separation between the signal and the corresponding return traces. Placing a solid metallic reference plane beneath the signal traces (i.e. forming co-planar microstrips) provides a considerable improvement (Figure 13.63b). The greater part of the electric flux now terminates primarily on the large mass of the reference plane, while the equal and opposite return current flowing in the plane provides for substantial magnetic flux cancellation. Embedding the trace between two solid metallic reference planes (i.e. co-planar striplines) further enhances the performance of the circuit (Figure 13.63c). Electric flux now terminates on both reference planes while the equal and opposite return current flowing in the planes provides for even superior magnetic flux cancellation. Consequently, stripline constitutes the ultimate topology from the stand point of EMI and crosstalk control. Figure 13.64 illustrates four stackup configurations, which have varying effects on crosstalk:

745

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13 Grounding on Printed Circuit Boards

H-field Signal traces Dielectric substrate E-field

(a) E-field Signal traces Dielectric substrate Return (Reference) plane H-field

Current return paths

(b)

H-field Signal traces E-field Dielectric substrate Return (Reference) plane Current return paths

(c) Figure 13.63 Effect of reference planes on H- and E-field distribution. (a) Exposed traces on a PCB with no reference plane. (b) Traces routed as surface microstrip on a PCB with an adjacent reference plane. (c) Traces routed as centered stripline on a PCB with adjacent reference planes.

1. Microstrip edge coupled GND

GND POUR 2. Stripline edge coupled

3. Broadside coupled

4. Broadside-edge coupled

PWR

Figure 13.64

a) b) c) d)

Crosstalk stackup configurations. Source: Courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD).

Edge-coupled microstrip Edge-coupled stripline Broadside-coupled dual stripline Broadside-edge-coupled dual stripline

The first two, edge-coupled, transmission line configurations are well known and commonly used for differential pairs, while the other two, broadside coupled configurations, exhibit several drawbacks, particularly associated with fabrication issues and compliance with IPC 601248 Class 3 specifications. In addition, it is very difficult to predict the impedance of broadside-edgecoupling due to alignment issues [17].

48 IPC-6012E, Qualification and Performance Specification for Rigid Printed Boards, March 2020.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Aggressor

Aggressor Ch1

Ch1

Ch2

Ch2 Victim

Victim

VNEXT = VChCH3 – VCh4

VNEXT = VChCH3 – VCh4

(a)

(b)

Figure 13.65 Near-end (NEXT) and far-end (FEXT) crosstalk (illustrated for differential pairs). (a) Near-end (NEXT) crosstalk. (b) Far-end (FEXT) crosstalk. Source: https://www.protoexpress.com/blog/crosstalk-high-speed-pcb-design/.

Two types of crosstalk, forward and backward (a.k.a. far-end (FEXT) and-near end (NEXT)), which refer to where the crosstalk is observed, at the near end or at the far end of the victim, respectively, (Figure 13.65), expressed as: FEXT K F =

1 2

1 NEXT K B = 4

Cm Lm − C total Ltotal

13 92

Cm Lm + C total Ltotal

where: Cm = Mutual Capacitance Lm = Mutual Inductance Ctotal = Total Capacitance Ltotal = Total Inductance The FEXT factor, KF, scales with length of the line, l, and aggressor signal risetime, tr, while for the NEXT factor, KB, the induced pulse amplitude reaches its maximum at risetime and the area under the curve increases with length of the line, l. The dual (electromagnetic and circuit) representation of crosstalk mechanisms is depicted in Figure 13.66. The E-field coupling between the traces and between the traces to the adjacent GND plane (EM notation) (Figure 13.66a) is equivalent to the mutual- and self-capacitances, Cm and CG (circuit notation), respectively, while the H-field coupling between the traces and surrounding the traces (EM notation) (Figure 13.66b) is equivalent to the mutual- and self-inductance, Lm and LS

H-field coupling E-field coupling

H-field surrounding trace

Ls VS1

E-field termination to GND Layer2_GND

(a)

Near-end

Rs

Aggressor line Lm

Rs

Victim line

(b)

VL1 Cm

CL VL2 CL

CG Far-end

Figure 13.66 Dual (electromagnetic and circuit) representations of crosstalk mechanisms. (a) Magnetic and electric coupling between two adjacent microstrip trace (electromagnetic notation). (b) Inductive and capacitive coupling between two adjacent microstrip trace (circuit notation). Source: Adapted from he Sierra Circuits Team 2022.

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13 Grounding on Printed Circuit Boards

(circuit notation), respectively. Total capacitance and inductance, Ctotal and Ltotal, include, therefore, in addition to the mutual capacitance and inductance, the capacitance to the planes, CG, and self-inductance, LS, respectively. From Figure 13.66, the benefit of small spacing between the traces is self-evident. Smaller spacing reduces stray E-field (or mutual capacitance) and increases flux cancellation (or reduces total mutual inductance49). In mode-balanced transmission lines (i.e. stripline), the ratio of Cm/Ctotal and Lm/Ltotal is equal, canceling all forward crosstalk, thus the forward crosstalk factor vanishes (KF in equation (13.92)), while the backward crosstalk factor (KB in equation (13.92)) results from the sum of the two mechanisms and hence is always present (Figure 13.67). For microstrip, inductance and capacitance are not balanced, due to mode separation, and as a result, forward crosstalk can be significant.

114.00 94.00

Microstrip

74.00 Voltage –mV–

NEXT 54.00 GND

34.00 14.00 –6.00 –26.00 FEXT –46.00 –66.00 0.00

500.0

1000.0

1500.0

2000.0

2500.0

3000.0

3500.0

4000.0

4500.0

Time (ps)

(a)

114.00

Stripline

94.00 GND

74.00 Voltage –mV–

748

54.00

VCC

NEXT

34.00 14.00 –6.00 –26.00 –46.00 –66.00 0.00

500.0

1000.0

1500.0

2000.0

2500.0

3000.0

3500.0

4000.0

4500.0

Time (ps)

(b) Figure 13.67 Near- and far-end crosstalk in microstrip and stripline (w = 4 mil/d = 4 mil trace width/separation, respectively). (a) Near-end (NEXT) crosstalk for microstrip. (b) Near-end (NEXT) crosstalk for stripline. Source: Courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD).

49 Recall that for a small current loop, Ltotal = LS − Lm, and as spacing between the trace and the plane (and the corresponding loop size) diminishes, Lm LS and, Ltotal 0.

13.4 Signal Propagation on PCBs – The Dual World View of Currents, Voltages, Circuit Elements, and Electromagnetic Fields

Figure 13.67a illustrates the near- and far-end crosstalk for a microstrip configuration where the victim traces are adjacent to the aggressor trace (1.5 V @ 1 GHz). In this case, the traces are 4 mil wide (w), with a characteristic impedance, Z0, of 40 Ω and a spacing, d, of 4 mil. It is evident that crosstalk falls off rapidly with d2 and the degree of impact is related to the aggressor signal voltage, the proximity of trace segments, and proximity to the plane(s). In an outer layer microstrip, capacitive coupling between the traces is generally weaker than inductive coupling, driving the FEXT co-efficient negative as can be seen in Figure 13.67a. Forward crosstalk does not exist, however, in the stripline configuration. The fine balance between inductive- and capacitivecoupled crosstalk produces almost no observable forward crosstalk (Figure 13.67b) with a geometry (i.e. w, d and Z0) similar to the microstrip. The FEXT component has now virtually vanished and the peak amplitude of the crosstalk has been considerably diminished. The advantage of edge-coupled stripline over edge-coupled microstrip is therefore evident. Furthermore, for equal performance, edge-coupled striplines can be placed closer to each other compared to the microstrip equivalent leaving more space for routing.50 As mentioned earlier, the easiest way to reduce crosstalk is by increasing separation between the traces as crosstalk falls off roughly quadratically with increased separation. Figure 13.68 demonstrates the effect of the edge-coupling on crosstalk for microstrip and stripline. Note that the stripline has about one quarter the crosstalk of the microstrip.

The Least You Need to Know

• •• •• • • • •

Return current does not all flow directly under signal traces; although the highest current density is underneath the traces, the RF current also spreads out in the plane to either side of the trace’s route. Return current spread in the planes can affect collocated circuits routed across the board. Crosstalk constitutes an “on-board” EMI problem, associated with coupling between aggressor and victim traces. Capacitive, inductive, and common impedance mechanism all contribute to crosstalk. In digital circuits, inductive crosstalk mechanism is predominant; in mixed digital-analog circuits, common impedance coupling through the return plane plays an important role. Crosstalk is three dimensional and is dependent on trace-to-trace separation, trace-to-plane(s) separation, parallel segment length, the transmission line load, and technology. The easiest way to reduce crosstalk from a nearby aggressor trace is by increasing spacing between the traces in question: Crosstalk falls off roughly quadratically with distance. The presence of a return plane and the proximity of both aggressor and victim traces to it (in edge-coupled microstrip or stripline configurations) constitute powerful means of controlling crosstalk and EMI. On the other hand, the return plane also creates “common-impedance coupling” crosstalk mechanism, notably dominant when the traces are run in parallel, at proximity (d) and at larger spacing (h) from the return plane. 2.5

2 Crosstalk, V

Microstrip 1.5

1 Stripline 0.5 0.25 0 0

5

15 10 Separation, mil

20

25

Figure 13.68 Crosstalk Vs trace spacing in (edge coupled) microstrip and stripline (tr = 1 sec, VDD = 3.3 V, l = 3000 mil, h1 = h2=3 mil and εr = 4.3). Source: Courtesy of Dr. Barry Olney, In-Circuit Design Pty Ltd (iCD).

50 Note, however, that for equal geometries, i.e. w, d, unless the spacing between the traces to the adjacent reference planes, h, is not increased, the edge-coupled stripline will exhibit a lower characteristic impedance, Z0, which may require stronger drivers than in the edge-coupled microstrips. For maintaining the impedance, reduction in trace width, w, is necessary.

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13 Grounding on Printed Circuit Boards

• •

Stripline constitutes the ultimate topology from the stand point of crosstalk and EMI control and results in lower (one quarter, approximately) coupling between traces than microstrips of equivalent dimensions and spacing (and of course, much lower than between co-planar traces with no return plane present). Edge-coupled stripline traces can also be placed closer to each other compared to the equivalent microstrip.

13.5

Return Path Discontinuities: “Mind the Gap” To be creative means to connect. It’s to abolish the gap between the body, the mind and the soul, between science and art, between fiction and nonfiction. — Nawal El Saadawi

Reports that say that something hasn’t happened are always interesting to me, because as we know, there are known knowns; there are things we know we know. We also know there are known unknowns; that is to say we know there are some things we do not know. But there are also unknown unknowns—the ones we don’t know we don’t know. And if one looks throughout the history of our country and other free countries, it is the latter category that tends to be the difficult ones. — Donald Rumsfeld, former US Secretary of Defense, 2002

There are two kinds of designers: those are trying to design antennas on purpose and those that aren’t doing it on purpose — Eric Bogatin and Charles Grasso If constrained to traces, the high-frequency signal and its return currents will flow through the path to which they are confined, ultimately compromising EMC and possibly circuit functional performance. When the return signal is allowed to flow through a plane, on the other hand, it tends, by nature, to assume a distribution that minimizes the overall impedance of the contour formed by the signal and its associated return path. This is achieved when the return current converges to a path as close to the trace as possible, namely directly next to it. It is what you don’t know you don’t know that can ruin your day. In order to facilitate optimized return current flow paths, high-level of integration in modern electronics typically demands use of multilayer printed circuit boards (PCBs). Up to this point, solid, continuous reference planes, serving as return paths, were assumed. However, in reality, complexity-dependent multiple DC supplies (e.g. VCC, VAA, VDD…) and ground references (e.g. DGND, AGND…) may be available on a single board, commonly implemented in the form of partial power and ground planes (a.k.a. planelets or islands) on the reference layers. When routing signal traces, PCB designers tend not to cross over gaps between reference planelet boundaries, but in densely populated PCBs this good practice may be compromised, and reference planes of different circuits are often physically separated by a slot, for instance, in the case of PCBs incorporating high-resolution mixed (A/D, analog/digital) signals.51 It is well known that if the PCB is correctly partitioned into digital and analog sections and if the analog signals are routed only in the analog section of the board and the digital signals are routed only in the digital section, common impedance coupling may be minimal on the PCB even if a single, common, and solid ground plane is utilized for all circuits. However, common impedance coupling dominates over near-field inductive/capacitive coupling at lower frequencies ( h t H h ;g ≤ h t

nts

curre

A

B

1 nH/cm A Equivalent circuit for a slot in a metal plane

Figure 13.91

C ≃ 0.1pF/cm

R B

of metal sheet

Illustration of Babinet’s Slot-Dipole theorem.

13 96 10

Transmitted microstrip mode

Ex_field|

Displacement across the gap (also known as the 5 Reflected microstrip mode “capacitance across the gap”) allows some current to Slotline mode flow across the gap. This mechanism, however, will be effective only when a relatively large cross-over area 0 exists, again requiring current spread and subsequently increased inductance, across the gap (Figure 13.94). Some similarity exists between slots and splits in ref–5 60 erence planes, but then again, they differ appreciably. Slo 300 t A “slot” refers to a partial gap in an otherwise solid 40 Trace 200 and continuous reference plane (Figure 13.95), whereas 20 100 ction split reference planes result in unrelated planelets n dire 0 0 gatio o p o (Figure 13.96). Both equally constitute EMI and signal r P integrity horrors. A similar yet somewhat different case is depicted in Figure 13.92 E-Field radiated emissions Gaussian pulse scattering on a Figure 13.97, where a trace crosses a slot totally enclosed reference plane. Source: Courtesy of Prof. Jiseong Kim, S. Korea. in a return plane. The effective increase in inductance associated with the slot may be considered as being in series with the trace (and current loop) and can be estimated by using the expression of a loop formed by two flat parallel conductors with a center-to-center spacing d, having width W and length ℓ. Assuming that the return current around the gap flows onto two parSignal trace allel conductors of width W = 3WT, length ℓ = D, thickness of trace, g tT, and spacing d = WC + 3W, the inductance associated with this Slot in plane configuration can be expressed as [37]: d LSlot = =

1 2

μo 2D ln 2π

μo D ln 2π

3W T + W C 3W T + t T

3W T + W C 3W T + t T

+

+

3 2

=

l t

3 H 2 13 97

The factor of “1/2” is added in equation (13.97) in order to account for the fact that the slot results in two loop inductances in parallel

h Solid reference plane

Figure 13.93 Geometry of a slot in the reference plane crossed by a signal trace.

763

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13 Grounding on Printed Circuit Boards

Figure 13.94 Return current in the plane is forced to flow around the gap and through displacement across the gap.

Gap Planelet #1 Displacement (capacitance) across the gap Added inductance due to larger current loop

Planelet #3

Planelet #2

Split return plane

Complete gap (split plane)

VCC1 Planelet

VCC3 Planelet

Split power plane

VCC2 Planelet

Solid return plane

DGND

Figure 13.95 A split in a power plane creating co-planar power planelets in a multi-supply voltage circuit.

Slot in power plane only

Digital Zone on plane

Analog zone on plane

Slot in both power and return plane

Common return plane

and the factor “2” is included since the objective of the calculation is the inductance of one of the loops that is twice the effective inductance associated with one branch of the loop. In this calculation, edge effects were neglected for simplicity. Equation (13.97) was validated by numerical modeling carried out at a frequency of 1 GHz, using CST Microwave StudioTM. The test PCB depicted in Figure 13.98 has the dimensions of 20 mm × 100 mm ×0.77 mm, dielectric substrate thickness of 0.7 mm with relative permittivity εr = 4.4, WT = 0.35 mm, tT = 0.035 mm, length ℓ = 100 mm, gap created in the middle of the PCB of size D = 7.5 mm, and WC = 5 mm [37]. The source was an ideal voltage source with trapezoidal waveform of amplitude 1 V, tr = tf = 1 ns, thold = 5 ns, ttot = 10 ns. The trace was loaded with its characteristic impedance, Z0 = 90.36 Ω. The resulting contribution of the slot to the loop inductance, LSlot, is 4.82 nH. Such high inductance may result in considerable distortion to the signal waveform and degradation of the rise time of the signal in particular. In addition, common-mode emissions are increased, particularly when a cable is attached to the PCB. Observe in Figure 13.98b the distribution of the surface current around the slot. Note that the assumption that the largest part of the return current concentrates in a space equal to 3WT is valid. Equation (13.98) expresses the increase in rise time of the propagating signal waveform due to the increased inductance caused by the gap [36]: t out =

t 2S + t 2in ≈

22

LSlot 2Z 0

2

+ t 2in

13 98

where tin and tout represent the rise time of the input (source) and output (load) current waveforms, respectively. The rise time degradation term, tS, is also explicitly shown in equation (13.98). Figure 13.99 illustrates a trace crossing a slot in an adjacent reference plane. A common application where such a situation is purposely introduced is illustrated in Figure 13.100. A slot (often even a total split, discussed below) is introduced by the designer in the reference planes of a mixed analog/digital59 board in the intention of reducing crosstalk from the digital to the analog zones of the PCB. To reduce crosstalk between analog and digital circuitry, EMC literature often recommends gapping the ground plane between analog and digital areas on PCBs. This technique reduces common-impedance but not inductive or capacitive coupling interactions [6]. In the case presented here, the opposite is achieved: As the designer failed to notice that several digital signal traces cross the slot, the digital return current from the driver cannot flow immediately beneath the trace and is diverted around the slot. Only a little portion of the return signal current may flow through the capacitance of the Figure 13.96 Slots in power and ground planes in a mixed analog/ digital circuit sharing a common ground plane.

59 Grounding considerations in mixed analog/digital circuits are discussed in detail later in this Chapter.

13.5 Return Path Discontinuities: “Mind the Gap” Rise time, tout

Figure 13.97 A trace routed over a slot in an adjacent reference plane.

Rise time, tin

WT

D

Slot in reference plane IC1

Signal trace Solid reference plane

WC

Load (= Z0)

Trace above return plane

Signal return path

x z

Gap in return plane

IC2

y

5 mm Gap

Return plane

Source

(a)

(b)

Figure 13.98 Simulation model of a trace crossing a gap in a return plane on a PCB. (a) Model of the PCB structure. (b) Return current distribution in proximity to the gap at F = 1 GHz. Source: Images from CST “Microwave StudioTM” 3D EM Simulator; Courtesy of Spartaco Caniggia.

Figure 13.99 A trace routed over a slot in an adjacent reference plane.

Slot in reference plane Signal return path

Signal trace

IC1

IC2

Solid reference plane

gap. The diverted return current forms a large loop with respect to the signal trace and strongly increases the current loop inductance, radiated emissions, and crosstalk that the designer was attempting to eliminate at the first place. In many well-designed high-speed digital circuits, the power planes are split into several “planelets” (i.e. unrelated partial planes or islands) allowing co-planar distribution of multiple supply voltages from the main power source or by monolithic voltage regulators/converters, to reside on the same PCB “VCC” layer make efficient use of the power plane area (Figure 13.101). Figure 13.102 depicts this situation in an actual PCB layout [38]. If the digital return (DGND) plane is solid and continuous, it may still provide an unobstructed signal current return path. Such a situation is commonly found in CPLDs (e.g. FPGAs, ASICs) where multiple power supplies for the I/O and the “core” of the device are required. Multiple supplies are often likewise required on “mixed supply logic” PCBs, where voltages such as 5, 3.3, 2.5, and 1.8 V are utilized or in high-resolution (>10 bits) mixed analog/digital circuit.

765

16 MHz clock

Digital

Digital

Digital

USB connector

13 Grounding on Printed Circuit Boards

Figure 13.100 Clock trace crossing a purposely introduced slot in the reference plane. Source: Courtesy of Dr. Todd Hubing, LearnEMC.

Slot Analog/ digital

Data checker Phone line

766

Reference plane Signal trace Return path in plane Return path around slot

Assume a trace is routed between digital devices IC1 and IC2 across a split in the adjacent power plane (Figure 13.101). The How can the return current return current must ultimately find an alternative path to get 1.8 V (Core) cross the split? across the split. In this case, illustrated for a four-layer board (Figure 13.103b), the current is diverted through the closest decoupling capacitor across to the solid DGND plane (common IC1 to all power planelets). Beyond the split, the current returns to 5V Split power the power plane through another decoupling capacitor. The CPLD plane equivalent inductance of the capacitors now dominates the PS loop impedance in addition to the effect of the larger loop 3.3 V (I/O) formed by the path of the current between the planes. IC2 Solid return Take notice that the inter-plane capacitance between two plane planes separated 10 mil (0.01 in. or 0.25 mm) apart with FR4 2.5 V 3.3 V (εr = 4.7) as a dielectric medium is 100 pF/in.2, approximately, DGND much too small to be effective for bypassing the return current across the gap except for frequencies considerably higher than Figure 13.101 Trace crossing a split between co-planar power 500 MHz.60 planelets in a multi-supply voltage circuit. A slightly different situation may occur in mixed analog/digital circuits whereby separate analog and digital power supplies and return paths are commonly utilized for eliminating undesired crosstalk through the common return path impedance to sensitive analog circuits (Figure 13.104). Consider now again a trace routed between digital devices IC1 and IC2. Ideally, the trace should be routed exclusively over the digital power plane, but if the trace were to be routed over the analog plane (due to some design flaw), where would the return signal current flow? There are two, equally unfavorable, answers to this question, a true “damned if you do and damned if you don’t” situation: If the return signal current remains on the digital plane and encircles the analog plane, a large loop is formed, resulting in increased EMI. Conversely, if the return signal current somehow finds a path onto the analog plane following the signal trace, the digital signal will probably couple onto analog traces in the area through crosstalk or ground-coupled interference mechanisms. Some similarity does exist between the cases of slots in planes vs. that of split planes into unrelated planelets. Then again, they differ appreciably: Unlike the case of a slot in a plane (case (a)), no path is available for the return current (not even by surrounding the split) when a trace crosses a split between unrelated co-planar planelets (case (b)) as the gap cuts through the entire board. Furthermore, the situations presented in Figures 13.101 and 13.104 are not equivalent. In the former (Figure 13.101), the power plane is split but an adjacent continuous ground plane is present. By rearranging the layers, this situation may be overcome. In the latter (Figure 13.104) on the other hand, both the power and ground planes are split in a similar manner (normally with no overlap between planelets), efficiently obstructing all possible return current paths.61 2.5/1.8 V power supply (PS) for VLSI 1.8 V core voltage

60 The limitations of interplane capacitance are discussed later in this Chapter. 61 In a severe case the only available current return path may be through the power source, feeding both the digital and analog circuits.

13.5 Return Path Discontinuities: “Mind the Gap”

Figure 13.102 Traces crossing a gap in a reference plane. (Note: Traces crossing the gap in circled areas) Source: Courtesy of Dr. Todd Hubing, LearnEMC.

Trace crossing gap in the plane

Isolated metal planelet Gap in the plane

Decoupling capacitors C1 Signal current path

C2

L1

Signals Gap

L2 Gapped power plane L3

Digital power (VCC1/VCC2)

Signal return current path

Digital return (DGND)

Solid return plane L4

Signals

(a)

Signal current path L1 L2

Signals Signal return current path ? Gap Gapped power plane

L3 Gapped return plane L4

Digital/analog power Digital/analog return (DGND/AGND) Signals

Analog region

Digital region

(b) Figure 13.103 Trace crossing a split reference plane in a four-layer board. (a) Split power plane but a solid ground plane (Figure 13.101). (b) Split power and ground planes (Figure 13.104).

Common to both situations is the fact that when a trace crosses a slot in the adjacent reference (power or ground) plane, a sizeable loop is formed, composed of the signal conductor and the return path in the reference plane when the return current is diverted from underneath the trace and forced to find its way around the edge of the slot. The longer the slot the bigger the loop area becomes. Since emission of and immunity to EMI as well as numerous signal integrity concerns are both related to loop area, a potential EMI and signal integrity situation was now created, where none was present beforehand.

767

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13 Grounding on Printed Circuit Boards

Coupled noise to analog circuit

How can the return current cross the split?

Trace crossing from digital to analog zones

13.5.3.2 Mitigating the Adverse Effects of Traces Crossing Slots in Reference Planes – “Bypass (Stitching) Capacitors”

In actual PCBs, it is not rare that traces cross a gap in the reference (power or return) plane. Slots and splits in reference planes are among the most commonly observed discontinuSplit power IC1 ities in high-speed PCBs, yet generally (with few exceptions) plane Analog power constitute a severely flawed design, often implemented due to planelet misapprehension of fundamental high-speed design princiIC2 ples or worst yet, intentionally. In many cases, splits and slots are used simply “because we always used to do it.” Figure 13.93 above illustrates a trace crossing a slot in a refSplit return Digital power erence plane, such as a partitioned power plane. It was shown plane planelet that the signal line traversing the slot in the partitioned power AGND DGND plane can be modeled as series inductor (equation (13.96)) Figure 13.104 Trace crossing a split between co-planar power and and decoupling or stitching capacitors are added near the slot to compensate signal noise due to this series inductance effect ground planelets in a mixed analog/digital circuit. (Figure 13.105). As the return current cannot flow directly under the trace, it diverts around the ends of the power plane slot, forming a large loop, subsequently increasing the inductance of the current path. Various approaches have been utilized to suppress electromagnetic interference (EMI) arising from the presence of slots and split reference planes. Obviously, the best approach is to avoid routing traces across slots or splits at the first place, at least with critical high-speed/high-frequency signal traces. While recognizing the significance of this recommendation, it must be acknowledged that some design constraint may require this to occur. For instance, in the four-layer stackup depicted in Figure 13.103a above, the ground plane (DGND) is continuous, while the power plane is partitioned. Unfortunately, not all traces can be routed in the bottom layer L4, adjacent to the DGND plane so some traces will ultimately have to be routed in layer L1, above the (split) power plane. When crossing slots in the reference plane is inevitable, the second-best strategy (and indeed, most common approach) is to count on capacitors providing a continuous AC current return path across the gap. In effect, two optional approaches are available, namely (i) decoupling capacitors and (ii) stitching capacitors. The decoupling capacitors’ method provides a return path across the slot by changing reference planes, i.e. power plane to ground plane and vice versa, whereas the stitching capacitors method provides a direct return path across the gap in the partitioned plane (Figure 13.106) [39].

150 μm Decoupling capacitors εR = 4.4 Bypass/stitching capacitor

900 μm

1200 μm 125 μm

(a) L1: Signal layer Gap

L2: Power layer

Gap

L3: Ground layer L4: Signal layer (1) Stitching/Bypassing Method

(1) Decoupling Method

(b) Figure 13.105 PCB structure with a trace crossing a gap and decoupling and bypass capacitors. (a) Model dimensions. (b) Physical implementation. Source: Shim et al. [39].

13.5 Return Path Discontinuities: “Mind the Gap”

Trace crossing gap

a) Decoupling Capacitors.62 When a solid ground plane is used, adjacent to the partitioned power plane (see Figure 13.103a and Figure 13.106 above), a large number of decoupling capacitors may be present between the two planes63

Decoupling capacitors

The relative position of these capacitors with respect to the position of the gap is of utmost importance. However, relying on decoupling capacitors, even when present on the board, may appear to be Return current unacceptable as the position of these capacitors may not be optimal paths for this purpose. The criteria for placement of decoupling capacitors are not associated with the gap in the plane, but rather with the prox- Figure 13.106 Alternative return current paths in a imity to the electronic device served by those capacitors. As a result, partitioned reference plane. Source: Shim et al. [39]. the return current may still be forced to travel a long distance, producing a large signal-return current loop (Figure 13.107). Capacitors C1 and C2 could provide for the smallest loop area, if C2 were present, but if it is not, and the closest decoupling capacitor available on the right-hand side of the gap is C3, a significantly larger loop is formed. Incidentally, the capacitors providing the “crossover” between the power and ground planes need not necessarily be those associated with the driving and receiving gates, but rather those which minimized the loop impedance. This solution scheme, based on the decoupling capacitors, can be effective only as long as at least one of the reference planes is continuous under both sides of the gap (Figure 13.103a). If both reference planes are split in the same manner (Figure 13.103b), the scheme using decoupling capacitors is of little avail, as each decouples to its own reference planelet, while the return current must still overcome the gap between both sides of the split in both planes (Figure 13.108). C1

C2

C3 Signal trace Signals

L1 Increased loop

Gap L2

Power Gapped power plane

L3

Return Solid return plane

L3

Signals Preferred return current path (Through non-existing C2)

Actual return current path (Through C3)

Figure 13.107 You can’t always rely on decoupling capacitors for bypassing return current across a split plane (they may be too far away).

C2

C1

Signal trace L1

Signals Both planes

L2

Power Gapped power plane

L3

Gapped ?

Return

Gapped return plane L4

Signals

Figure 13.108 You can’t rely on decoupling capacitors when both reference planes are split (how can the return current flow, even with C1 and C2 in place?).

62 Decoupling capacitors are used to decouple one part of an electrical network (circuit) from another. In other words, decoupling AC signals from DC signals or vice versa. The term “decoupling capacitors” is most commonly associated with removing the power distortion and noise and protect the system/IC by providing pure DC supply. For optimal performance, decoupling capacitors should be placed in the vicinity of and in parallel to the connections of the device to the power and return planes. Decoupling is briefly discussed later in this Chapter. 63 Decoupling capacitors may not be present on “passive backplanes/motherboards” containing no active devices. In such cases, this approach is non-existent.

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13 Grounding on Printed Circuit Boards

C1 Signal trace L1

Signals

L2

Power Gapped power plane

Both planes

Gapped return plane

Gapped

L3

Return Return current path

L4

Signals Gap crossover through stitching capacitor C1

Figure 13.109 Stitching capacitors provide a direct bypass for the return current across a split plane.

Z (Ω) 1000 1 nF, X7R

100 10

100 nF X7R

1 1 nF, NP0

b) Bypass (Stitching) Capacitors.64 Unlike the decoupling method, whereby the capacitor is always placed between the power and ground planes, in the bypass method, bypass or stitching (a.k.a. bypass) capacitors are placed across the gap, either in a partitioned ground planes (e.g. analog/digital), power planes (e.g. between two different power potentials planelets, such as 3.3, 5 V), or a combination thereof, in order to provide a “detour” or “bypass,” i.e. an alternate path for the return current (Figure 13.109). This scheme will work effectively even with both planes split (see Figures 13.103b and 13.106 above).

0.1

Whether the decoupling or stitching methods are applied, the capacitors should exhibit low impedance at the signal frequencies 1000 10000 1 10 100 for providing an acceptable return current path.65 For higher freFrequency, MHz quency components, the capacitor’s impedance is not driven by the capacitance; rather, it is dominated by inductance, particularly Figure 13.110 Typical impedance curves of X7R and NP0 the capacitor’s intrinsic equivalent series inductance, ESL, as well MLCC chip capacitors of two different capacitance values. as by mounting inductance resulting from its installation (vias, Source: Elcap / Wikipedia/ Public Domain. pads). Figure 13.110 illustrates the impedance of two capacitors of equal package size (equal ESL) but differing in their capacitance. Values of 1–10 nF are typically recommended, depending on the frequency content of the signal, while the package sizes of the capacitors should be maintained as small as possible (0402 or smaller yet, when possible). When decoupling capacitors are placed between the power and ground planes, enhanced return loss performance (S11) is observed (compared to a partitioned plane with no capacitors), notably in the lower frequency region, as observed in Figure 13.111, primarily due to the return current path established by the capacitors. Even further improvement is clearly seen with bypass capacitors, thanks to the more diminished return current path compared to the latter approach (see Figure 13.106 above) [39]. The electromagnetic radiated emissions caused by nonideal return path is proportional to the forward loss factor (FLF),66 0.01

FLF dB = 1 − S11 2 − S21

2

13 99

Figure 13.112 demonstrates that adapting either the decoupling or bypass capacitors approach can lessen the forward loss factor.

64 Stitching (or bypass) capacitors simply allow a path for return currents to return to the source when crossing multiple planes with differing potentials, e.g. power and signal return planes. They need to be located as closely as possible to the location the high frequency trace penetrates the planes. 65 In addition to exhibiting low RF impedance, decoupling capacitors (unlike bypass capacitors) should also be selected on the basis of their charge delivery capability, which may require capacitance values larger than for the mere bypass (low impedance) function. 66 The forward loss factor is equal to the difference between a normalized input power and the power that is reflected and transmitted to the input port (Power loss can occur due to conductor, dielectric and radiation loss mechanisms). See Appendix K for more information on S-parameters. The reciprocal of this concept may be termed “Forward Efficiency Factor (FEF),” expressed as 1-FLF or, simply FEF = |S11|2 + |S21|2, which, when converted to decibels (dB) serves as a measure of how “lossless” a circuit would be if it were perfectly matched (A “perfect” circuit has an efficiency factor of 0 dB.)

13.5 Return Path Discontinuities: “Mind the Gap”

Forward loss factor (FLF)

S11, dB

–10 A third aspect, associated with signal and power integrity (SI/ Split power plane PI), is switching noise or ΔI-noise. As the return current in forced –15 to circumvent the slot in the reference plane, current is forced to Decoupling flow along the slot line in the power plane and traverse to a second –20 capacitor added reference plane, which causes ground bounce or ΔI-noise,67 which –25 can also be effectively alleviated by bypass or decoupling capacitor as depicted in Figure 13.113 [39]. –30 Placement and mounting of the bypass capacitors play a paraStitching capacitor added mount role in their overall performance and should next be care–35 fully considered. SMT (surface mounted technology) stitching –40 capacitors should be used and mounted across the gap, preferably one on either side of the signal trace. The capacitors should be –45 placed at proximity to the trace crossing the gap (preferably within 0.1 in., or 2.5 mm). For best performance, capacitors –50 0 0.5 1 1.5 2 should also be placed at regular intervals along the perimeters Frequency, GHz of all of the plane splits, so that they may be used to interconnect the planelets on either side of the gap. The spacing between the Figure 13.111 Return loss of a partitioned power plane vs capacitors along a gap should not exceed λ/10 at the highest fre- scheme. Source: Shim et al. [39]/ with permission of IEEE. quency of concern, where λ represents the wavelength associated with the highest signal frequency of concern in the dielectric 0.5 medium of the PCB. Figure 13.114 illustrates the implementation 0.45 of this scheme with a slot in a reference plane (a) and in a split plane (b) [23]. 0.4 Bearing in mind that the return current must now flow from one 0.35 planelet, through a series of “obstacles” namely a via, a trace, a 0.3 mounting pad, a capacitor, a mounting pad, a trace, and finally Split power plane 0.25 through a via to the other planelet of the split plane, the solution 0.2 is far from being ideal and considerable inductance is present in series with the return current path (typically no less than 5–10 0.15 Decoupling nH minimum). Proper design of the mounting pads is of utmost 0.1 capacitor added importance. Figures 13.115 and 13.116 present in order of 0.05 Stitching capacitor added improved performance, the manner of installation of the capaci0 tors, shape of the mounting pad, and location of the vias68 [23]. 0 1 0.5 2 1.5 A comparison of inductance of equally sized capacitors when Frequency, GHz applied in regular and reverse aspects revealed, expectedly, that Figure 13.112 Forward loss factor (FLF) of a partitioned reverse aspect capacitors exhibit significant ESL reduction. power plane vs scheme. Source: Shim et al. [39]/ with Figure 13.117 depicts a comparison of measured ESL associated permission of IEEE.. with several SMT capacitor packages, illustrated for 0805/0508 and 1206/0612 footprints [38]. While the stitching capacitors do provide an optimal path for the return current (if placed in proximity to the signal trace at the crossover point), their performance is appreciably limited by their high-frequency impedance,69 as well as the added inductance associated with their mounting (which was not explicitly considered in the previous discussion) [40, 41]. Figure 13.118 depicts a plot of the simulated maximum E-field-radiated emission from a simple PCB with an exposed microstrip trace. The level of emissions in the frequency band 20 MHz–1 GHz are illustrated for the trace routed over a solid metal plane and crossing over a split plane. Noticeably, emissions are 10- to 100-fold (20–40 dB) higher for the latter, in comparison to the former. When stitching capacitors are added (Figure 13.119), a significant improvement is observed, as anticipated, at lower frequencies (up to 100 MHz, approximately) but degrading with further increase in frequency. With one stitching capacitor used, a rise of emissions above 100 MHz is visibly observed. When two parallel capacitors are used, emissions drop (almost) to the level observed over a solid reference plane. Up to this point, real-world intrinsic characteristics (ESR, ESL) of capacitors were considered while the reactance associated with the mounting of the capacitors (e.g. the vias, the mounting pads, and connecting traces) were ignored. If those were to be

67 “Ground Bounce,” a.k.a. ΔI-noise or SSN (simultaneous switching noise) are discussed later in this Chapter. 68 Other capacitor installation schemes, which are less appropriate for plane stitching due to width of the gap and the corresponding installation constraints but are useful for decoupling purposes, are discussed later in this Chapter. 69 The non-ideal behavior of capacitors is extensively discussed in Chapter 2.

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13 Grounding on Printed Circuit Boards

considered, an additional inductance of approximately 1.5 nH must be added. The adverse effects of this situation are depicted in Figure 13.120. Although far from ideal, definitely inferior to the preceding case, without a doubt, stitching capacitors still contribute a significant, yet frequency-band-limited, improvement compared to when not present.

1 0.5 0 –0.5 –1

13.5.3.3 Mitigating the Adverse Effects of Traces Crossing Slots in Reference Planes – “Interdigital Slot in Reference Planes”

–1.5 –2

Split power plane Decoupling capacitor added

–2.5

Stitching capacitor added

–3 0

500

1000 Time Step [0.04 psec]

1500

2000

Plane stitching capacitors

1 MHz)?

• •

Each circuit common is grounded directly to the GRS and also grounded indirectly to the GRS via the connections to the other assemblies Most typical for radio frequency (RF) subsystems but should not be used for video or other signals containing low frequencies (less than roughly 1 MHz) ★ “Ground loops” are inherent to this scheme, but can be controlled by appropriate system layout Ground Loop Control Circuit Interface Control

Distributed (Multiple) Single Point Grounding

Isolated DC/DC converter Missile primary DC power source (e.g. battery)

. . . Power utilizing equipment load

Does the System consist of multiple isolated subsystems, with dedicated power sources?

• • • • •

In large platforms/vehicles, subsystems may have separate power sources and common grounding point to the GRS Each assembly has one and only one path to the GRS, and there are no deliberate structure currents (i.e. no single-ended interfaces) Compared to the “Star SPG,” each ground conductor is short, providing minimum AC impedance between each circuit common and chassis All subsystems have a common DC voltage reference potential (the interconnected lowimpedance GRS) This grounding architecture is typical for modern large vehicles/platforms that pays special attention to grounding architecture, including isolation of interfaces and minimized structure currents Ground Loop Control Circuit Interface Control Ground Reference Structure

Power utilizing equipment load

Missile power distribution system

Missile power distribution system

Isolated DC/DC converter

Power utilizing equipment load

Missile primary DC power source #1 (e.g. battery)

. . . Power utilizing equipment load

Missile primary DC power source #2 (e.g. battery)

Good Practices: [a] Works best at high frequencies (e.g. RF or highspeed digital circuit) and large system dimensions [b] Avoid in low-frequency circuits [c] Control path of signal cables (e.g. coax) and transmission lines on PCBs [d] Provide low-impedance GRS connection [e] Use isolation to lower frequency circuits

Good Practices: [a] Use distributed (multiple) single point grounding when: Multiple, isolated power sources are used (e.g. avionics and telemetry supplies) Interfaces between assemblies well controlled [b] Grounding point for each power source typically near individual source [c] Avoid conductive interconnects between distributed assemblies to avoid ground loops – implement isolation [d] Common in large vehicles/platforms with multiple power sources

• •

(Continued)

Requirement

Review criteria and rational

FrequencySelective Grounding

Does the circuit require low-frequency single point grounding and high-frequency multipoint grounding?

• •

Low-frequency (and video) circuits are typically single-point grounded For shunting high-frequency common-mode noise, multipoint grounding is required ★ However, multipoint grounding in low-frequency circuits could result in detrimental ground loops

• Hybrid Grounding

•

Comments/good practices Missile power distribution system

Power utilizing equipment load Isolated DC/DC converter

Missile primary DC power source (e.g. battery)

AC/DC “Soft” Grounding

. . . Power utilizing equipment load

Good Practices: [a] Capacitors should be small to ensure low impedance only at high frequencies [b] Minimize inductance of capacitors’ connections [c] On PCBs, requires connection from ground plane to chassis plane

Grounding via capacitance ensures that both are met Ground Loop Control

Does the system consist of dissimilar types of circuits, e.g. low-frequency circuits (requiring single point grounding) and high-frequency circuits (requiring multipoint grounding)?

•

Schematics

Most systems combine low-frequency, analog circuits, requiring single-point grounding and high-frequency or digital circuits requiring multipoint grounding A hybrid system combines both according to circuit characteristics Ground Loop Control Single-Point Grounding Multipoint Grounding Power Source and Return Switching Circuit Interface Control Isolated Converters Producing Internal Secondary Power Terminal Protection

Power utilizing equipment load

Power distribution system Isolated DC/DC converter Primary DC power source (e.g. battery)

. . .

Single primary power ground

Power utilizing equipment load

Single-point grounding

Power utilizing equipment load

Missile power distribution system Isolated DC/DC converter

Multi-point grounding

. . . Power utilizing equipment load

Good Practices: [a] Apply single point grounding, for low-frequency circuits (d ≤ λ/20 MHz) [b] Apply multipoint grounding for high-frequency circuits (d > λ/20 MHz) [c] For transitional situations, one or the other may perform better [d] For this crossover region, hybrid grounds perform best: Low-frequency portions use single-point grounding High-frequency portions use multipoint grounding [e] Carefully control the interfaces between different circuits

• •

Soft Grounding

Are there circuits which require low-frequency single point grounding and high-frequency multipoint grounding??

• • •

Simultaneous power sources for same subsystems (e.g. aircraft/launcher power source and missile battery could result in ground loops) A return wire grounded to chassis permits a single unfused fault from the positive wire to chassis that could destroy the mission If the power return is isolated from chassis by some modest impedance, both concerns are addressed ★ Example: Isolation of 2kΩ limits chassis currents to mAs for a 28V system (28 V/2 kΩ = 14 mA, and worst-case power loss of 0.39 W). This keeps the power return close to chassis potential but prevents loss of mission. Ground Loop Control Single-Point Grounding Circuit Interface Control Isolated Converters Producing Internal Secondary Power

Power Source and Return Switching

Missile power distribution system

Missile primary DC power source (e.g. battery)

AC/DC “soft” grounding

• • • •

. . . Power utilizing equipment load

A/C primary DC power source (e.g. battery)

Connection via mounting hooks

Good Practices: [a] Isolation impedance should be high enough to limit fault current but low enough to provide a stable reference [b] If the power system is isolated from the chassis, all items attached to the power bus must also be isolated from chassis [c] Soft grounding may result in greater power bus common mode noise, so: power user loads should have greater common mode noise immunity, or bypass the isolation impedance with a capacitor

• •

Are there two power sources operating at distinctively different times? Power sources operating at distinctively different times (i.e. exclusive of each other, not summed) for same subsystems (e.g. aircraft/launcher power source and missile battery, or multi-launch rockets) may be switched to preclude ground loops Switching should be on both power and return leads ★ In the image, only the return leads are illustrated

Power utilizing equipment load Isolated DC/DC converter

Power and Return DPDT switch

Missile power distribution system

Isolated DC /DC converter

Power utilizing equipment load

Missile primary DC power source (e.g. Battery)

“Hard” grounding

. . . Power utilizing equipment load

A/C primary DC power source (e.g. battery)

Connection via mounting hooks

Good Practices: [a] Switching power sources is a great solution when the two power sources are exclusive to each other [b] Cannot be used if “make-before-break” is required, unless (in missiles) batteries are burst before switching and momentary dual supply is allowed [c] Note that power switching relays must match the dynamics of the platform

This however creates a “break-before-make” situation Provides higher isolation, but electromechanical switches must be fit for the application Ground Loop Control Single-Point Grounding (Continued)

Requirement

Review criteria and rational

EquipmentInternal Grounding Scheme

Has the system’s internal grounding scheme been established (using one or more of the above schemes)?

Schematics

Good Practices:

Assembly #1

• •

The grounding within electrical or electronic enclosures should follow system characteristics Interconnection between assemblies requires attention to preclude (i) radiated emissions; (ii) zoning violation; and (large ground loops) Zoned Grounding Grounding Scheme Design Ground Loop Control Circuit Interface Control Isolated Converters Producing Internal Secondary Power

Comments/good practices

Circuit #1 Assembly #2 Circuit #2 Circuit #2

Chassis ground

Chassis ground

Signal ground

Circuit #1

Radiated EMI coupling Chassis ground

System common ground

Radiated EMI coupling

Signal ground

Poor Design:

••

Ground conductors routed externally Multiple, large ground loops Assembly #1

ESD/EMI

Circuit #1 EMI Assembly #2 Circuit #2 Circuit #2

Signal/chassis ground

Power fault

Circuit #1

Signal current path Signal/chassis ground System common ground (Reference structure)

Improved Design:

•• •

Ground conductors terminated internally Grounding scheme according to circuit characteristics Multiple loops may be produced with signal interconnects between assemblies

[a] Allocate dedicated power returns [b] All signal and power returns should be electrically isolated from each other (except at a single common point); separately derived electrical systems should be connected to structure at one point only [c] The system single-point ground should be connected DIRECTLY and INTERNALLY to chassis for termination and NOT externally to equipment (zoning violation) [d] Use a dedicated power return except where necessary to support system requirements [e] The signal/control power return should be isolated from the primary electrical power return [f] Equipment should not depend on other equipment for grounding, unless it is also dependent upon the other equipment for its power [g] Signal circuits with frequencies 2 MHz) analog interfaces?

• •

Pyrotechnic (Pyro) Firing Interfaces

•

Pyro interfaces perform: – Direct energy transfer – Broadband, highly impulsive current – Little or no signal parameter control – High Signal Levels (tens of Volts/Amps) – Could be safety-critical Preclusion of stray current flow through pyro circuits due to pyro ground fault is critical Single-Point Grounding Soft Grounding Cable Selection and Grounding

Does your system special interfaces, other than the above?

•

Such cases are so unique that it is hard to generalize what to do; such cases must be handled on an individual basis

Comments/good practices

Coaxial cable, grounded both end, serving as RF current return RF circuit

Antenna

Good Practices: [a] Use coaxial interfaces between subsystems [b] Always use multipoint grounding: terminate circuits (and cable shields) at both ends (on enclosures). Never float coaxial shields [c] Remember: current at high-frequencies will follow the path of least inductance (typically the smallest loop area path) [d] Do not use the cable shield as a return current path except in RF circuits (F > 2 MHz) [e] Beware of interfaces between coaxial to tri-axial interfaces Good Practices:

Does your system include Pyrotechnic (Electrically Initiated Explosive Devices (EIEDs)) interfaces?

• Other Special Interfaces

RF interfaces are: – Narrow Band – No Signal Regeneration – Gain Devices – Low or High Signal Levels (μV to 100s of Volts) They could therefore be very noisy or sensitive to EMI Multipoint Grounding Cable Selection and Grounding

Schematics

Shielded cable, grounded both ends

EIED

Z Isolation impedance

[a] Route firing circuit return leads to the firing power source and isolate it elsewhere from chassis by 20 kΩ min [b] Use balanced, twisted, and shielded cables [c] For ESD and pyro ground fault protection, balance the EIEDs firing circuit and use “soft grounding” to chassis via resistance Most guides recommend resistance of 100 kΩ Experience revealed that 100 Ω–1 kΩ are much more effective ★ Consult with Pyro expert to determine value of resistors and “soft grounding” configuration

• •

Interface type 1

Interface type 2

???

Good Practices: [a] Consult with the experts [b] Use common sense [c] “Be the signal”

Isolated Converters Producing Internal Secondary Power

Is isolation between power circuits (e.g. between primary to secondary) required?

•

Isolated switch-mode power supplies provide: – Safety – Ground Loop Control – Multiple outputs from single input Ground Loop Control Single-Point Grounding System-Wide Power Distribution Schemes

Good Practices:

Isolated DC/DC SMPS

Signal current

EVDC

[a] Maintain isolation in control loop [b] Beware of violation of isolation in signal circuits interconnecting between power circuits [c] Isolated converters may not be necessary between secondary and tertiary circuits; consider the power distribution scheme

Signal return current path

X X

No signal return current path through primary return

Isolation for ground loop control D IP

IS

+ VS –

L

IL C

+ VOut –

Q V1

VQ

Flyback converter (example) Cable Shielding and Shield Termination/ Grounding

How to treat and shield cables interconnecting electrical assemblies and subsystems?

• • • •

Cabling extending outside grounded enclosures is vulnerable to radiated emissions if cable lengths are electrically long The proper interfacing cable should be used for the particular interface Adequate shielding and grounding are required to ensure proper system operation Cable shielding may be supplemented by terminal protection on the cable interfaces for complete interface protection Zoned Grounding Cable Selection Cable Shield Continuity and Termination Terminal Protection (Continued)

Requirement

Review criteria and rational

Cable Selection

What types of cables should be used?

• • • ••

Cables should be selected to ensure controlled current return path and avoiding ground loops Other considerations may include e.g. controlled impedance Use twisted and shielded pairs for balanced signal interfaces, particularly at low frequencies Coaxial cables for high-frequency RF circuits Twisted unshielded cables for primary power circuits Grounding Scheme Design Ground Loop Control Cable Shield Continuity and Termination

Schematics

Comments/good practices

Good Practices: Source

Unbalanced single-ended shielded wire) coax(

Load

C B Desired path for high-F return current with Multipoint grounding

A

Undesired path for high-F return current with single-point grounding

Single-ended (coaxial) cable. Low and high frequencies

[a] Use the proper cable type for the application and signal characteristics [b] Think of return current paths. Remember: Low-F signals return through path of least resistance (may be chassis!) High-F signals return through path of least inductance (smallest loop) [c] Treat power as balanced signals, but do NOT shield primary power ★ Most primary power cables are unshielded on the platform, and high-quality power line filters may be used

• •

[d] Never use the cable shield as signal return (except in high-frequency coaxial cables) Source

Balanced twisted shielded wire pair

Load

Balanced signal circuit carried only signal current Even if grounded here, The circuit is still balanced Grounded Shield carries only EMI source current

Grounded load

Twisted-shielded cable. Balanced interfaces

Have you considered cables’ shield termination?

• • •

Good Practices:

Center conductor

Outer sheath

Adequate shielding and grounding are required to ensure proper system operation Low-impedance, 360 shield termination connection is mandatory for high-quality shielding at penetrations and bulkheads By doing so, shielded cables maintain systemwide “zoning” principle Zoned Grounding Ground Loop Control

[a] Use cables with low surface transfer impedance, ZT [b] Ensure low-impedance shield termination at both ends of the cable [c] Never use the cable shield as signal return (except in high-frequency coaxial cables) [d] If interfaces and cables are selected properly, do not be concerned of ground loops across cable shields [e] Maintain 360 shield continuity across all bulkheads and connections

Braided shield Terminal strip

Cable Shield Continuity and Termination

Pigtail shield termination

Bulkhead wall Bulkhead connector

End #1 connector

Bond to chassis

End # 2 connector

EMI backshell Internal wiring

EMI backshell

360º shield termination Shield termination through EMI backshells

360º shield termination

Bond to chassis

(a) Metal shell

Cable shield

See note

Connector Adapter

Backshell

Strain relief

Ground ring

Cable shield

(b)

(Continued)

Do physical interfaces penetrate boundaries of equipment zones (e.g. shielded enclosures and ground zones)?

• • • • • • EMI Filters

Incident transient

• •

Common-mode filters include line-to-ground capacitors and series inductors/ferrites or common-mode chokes ★ X2Y capacitors are most effective in accomplishing common-mode suppression in power and signal circuits Bonding

[a] Use terminal protection devices to suppress EMI on conductors penetrating enclosures and zones [b] Common-mode TPDs are necessary for this role [c] When combining filters and transient suppression devices (TSDs), typically place filters in the interior [d] Beware of excessive capacitance that can violate safety

Protected load Load's signal return

Ground reference plane (GRP)/chassis

Are the interconnects subject to high EMI?

• •

Diverted transient current

Good Practices:

Clamped transient voltage

Series blocking device

Physically long interconnects, such as power lines and cables between equipment, may be subject to large EMI and transient voltages and currents EMI energy coupled onto conductors penetrating zone boundaries could degrade equipment performance Filtering and transient suppression devices installed at the point of entry between zones (e.g. into shielded enclosures) minimizes EMI Terminal protection devices (TPDs) may include: – EMI filters and – Transient suppression devices (TSDs) Both commonly used to suppress undesired conducted electrical energy to tolerable levels by shunting, bypassing, absorbing, or reflecting the interference energy The effectiveness of TPDs depends on proper bonding, particularly for counteracting commonmode interference phenomena Bonding Safety Grounding

EMI filters prevent the propagation of undesired conducted electromagnetic energy Filters comprise of capacitance and inductance to create a high series or low shunt impedance for interfering (EMI) currents, reflecting them back to their source Common-mode filters are most useful for EMI suppression ★ High-quality power line filters also require and include differential-mode suppression

Comments/good practices

ZL

Terminal Protection

Schematics

Filter

Review criteria and rational

TSD

Requirement

Good Practices:

ZS

C

ES

ZL

ZSF

ZLF

High-ZS

High-ZL

Capacitive-filter

ZS

L C

ES

C

ZSF

ZL

ZLF

High-ZS

High-ZL π-Filter

[a] Ensure low bond impedance between capacitors to ground reference plane/chassis [b] Beware of excessive capacitance that can degrade the signal and violate safety (on power lines) [c] Filters may be combined with Transient suppression devices (TSDs)

Transient Suppression Devices (TSDs)

Good Practices:

Are the interconnects subject to EMI transients/ bursts?

• • • •

Transients currents and voltages results from inductive switching transients and induced surges from lightning or nuclear electromagnetic pulse (NEMP) Unlike ordinary EMI, transients are fast events of high magnitude and could significantly harm electrical and electronic apparatus Transient suppression devices (TSDs) shunt harmful transient surge current to the ground reference structure before it reaches the protected circuit by diverting the surge current through low-impedance shunting devices Occasionally, transient protection devices are combined with standard linear EMI filters Bonding

[a] Ensure low bond impedance between TSDs to ground reference plane/chassis [b] Beware of excessive capacitance in MOVs and Avalanche Diodes that can degrade the signal and violate safety (on power lines) [c] Consider circuit coordination in hybrid circuits [d] Transient suppression devices (TSDs) may be combined with filters

Gas discharge tubes

Metal oxide varistors (MOVs)

Avalanche diodes (TranzorbsTM)

Hybrid circuit (example) Bonding

Is the impedance at interfaces between bonded metals been minimized?

• • • •

Development of electric potentials between metallic parts should be controlled to preclude interference and hazardous voltages Bonding is the process in which parts are electrically mated to provide a low-impedance interconnect Bonding requires use of clamps, standard parts, bolt and screw attachments, washers, and materials to ensure performance in the applicable environmental conditions Direct current (DC) bonding goals: – ≤10 mΩ from equipment enclosure to system structure★ – ≤15 mΩ from cable shields to equipment enclosure★ – ≤2.5 mΩ across individual faying interfaces within equipment – ≤100 mΩ up to 1 MHz for preclusion of electrical shock hazards – ≤1000 mΩ for preclusion of static charge buildup ★ including the cumulative effect of all faying surface interfaces Safety Grounding

Tab welded to tubing

Clean tab to Basic metal and seal after installation

Good Practices: [a] The best bond is obtained by metal to metal contact between mating surfaces (“direct bond”) [b] Bonding through intermediate electrical conductors (a “jumpers”) to interconnect otherwise isolated parts (“indirect bond”) is discouraged

(Continued)

Requirement

Review criteria and rational

Direct Bonds

Can the mating parts be directly bonded?

•

Development of electric potentials between metallic parts should be minimized to preclude interference and avoid compromise of safety Surface Treatment Corrosion Control

Schematics

Comments/good practices

Good Practices:

Clean metal to base metal 6 35 mm ( in.) larger than connector unless mounting material is finished as in note 1 or 2

[a] Always prefer a direct bond to an indirect bond [b] Do not rely on screws or rivets alone to provide an acceptable bond [c] The mating surfaces must be treated in order to ensure minimum contact resistance [d] The compatibility of the mating metals must be considered for corrosion control

Refinish after installation 1- dia area cleaned

Connector

Mounting surface

Notes. 1 Clean and refinish aluminum surface mating with connector 2 Magnesium surface mating with connector may be finished with chrome pickle conforming to specification MIL-M-3171, type 1

Indirect Bond

What if mating members CANNOT be directly bonded?

• • •

Indirect bonding is discouraged except across movable vibration or thermal isolation joints A good metal to metal bond must be maintained at the jumper contact surfaces Performance limited to 10 MHz, maximum, due to inductive effects Surface Treatment Corrosion Control

Mounting base Bonding strip (Ref)

Good Practices:

Lock washep Shock mount Mounting structure

Lock washer

[a] Treat the mating areas between the jumper to the equipment surfaces in order to ensure minimum contact resistance. Source: Wiring Depot. [b] Consider the compatibility of the mating metals at the mating surfaces for corrosion control [c] Keep bonding straps direct and short, with a length-to-width ratio not exceeding 5–1 [d] CRES and titanium are preferred materials for metal-to-metal bonding [e] Solid bonding straps are superior to braided straps

Surface Treatment

How do mating surfaces be treated to ensure low contact resistance?

• •

Surfaces must be maintained as clean and smooth as possible Remove dirt, paints and nonconductive protective coatings from the bond area Corrosion Control

Good Practices:

Bonding or current return jumper

Screw or bolt steel lockwasher steel washer

Plated steel, or CR steel

Steel locknut or plate

Refinish after instl 1-1/2 Dia of cleaned area

Corrosion Control

Have you considered the materials being bonded?

• • •

Bonds are typically formed between dissimilar metals (e.g. copper and aluminum) When operating in an atmosphere with some degree of humidity, a voltaic cell is formed: current will flow from the anode to the cathode, resulting in a bond corrosion Corrosion results in EMI and failure

0.2

0

–0.2

–0.4

Clean to base metal area 1-1/2 Dia of term

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

Magnesium Zinc Beryllium Aluminium alloys Cadmium Mild steel and Cast iron Low alloy steel Austenitic cast iron Aluminium bronze Naval brass, yellow brass and red brass Tin Copper 50/50 lead tin solder Admiralty brass, aluminium brass Manganese bronze Silicon bronze Stainless steel – grades 410, 416 Nickel silver 90/10 copper nickel 80/20 copper nickel Stainless steel – grade 430 Lead 70/30 copper nickel Nickel aluminium bronze Nickel chromium alloy 600 Nickel 200 Silver Stainless steel – grades 302, 304, 321 and 347 Nickel copper alloys – 400, K500 Stainless steel – grades 316 and 317 Alloy 20 stainless steel Nickel iron chromium alloy 825 Titanium Gold, platinum Graphite Most noble – cathodic

[a] Begin by removing all anodic film, grease, paint, or other high-resistance properties from the faying surfaces [b] Avoid using abrasives which cause corrosion if embedded in the metal [c] Select the mating metals according to the electrochemical chart (“dissimilar metals” considerations) [d] Apply protective conductive coatings

Good Practices: [a] Avoid contact between dissimilar metals: consider the electrochemical table [b] Use protective coating when dissimilar metals cannot be avoided [c] Avoid sharp corners [d] Ensure no water retention [e] Make vulnerable parts easy to replace [f] Consult with material engineers when in doubt

Least noble – anodic

(Continued)

Requirement

Review criteria and rational

Safety Grounding

Does the System contain hazardous voltages?

• •

Electrical shock occurs when electrical current flows through a person’s body and he becomes part of the current’s path A person can receive a hazardous shocks by being in contact with: ○ Both wires of an electric circuit ○ One wire of an energized circuit and ground ○ A metal part that accidentally becomes energized, for example, a break in its insulation Electric shock occurs when a person touches a hazardous, or “live,” voltage, i.e.: ○ >30 Vrms and 42.4 Vpeak or ○ >60 VDC Protective devices (e.g. circuit breakers) may not provide sufficient protection as a person can be electrocuted below the point at which protective device operate Proper bonding and earthing help reducing this type of hazard protects personnel from electrical shocks due to system faults by limiting case voltage rise to prevent hazardous currents: Summary Effects of Alternating and Direct Currents Electrical Shock

• • •

Alternating Current (50/60 Hz) (mA)

Direct Current (DC) (mA)

0.5–1 1–3 3–21 21–40 40–100 >100

0–4 4–15 15–80 80–160 160–300 >300

Verification Methods Source: Adapted from NASA MSFC-SPEC-521 [1].

Reaction Perception Surprise Reflex action Muscular inhibition Respiratory block Usually fatal

Schematics

Comments/good practices

Neutral

Good Practices: Safety first! Find the balance between safety and proper EMC design

Neutral Phase

Phase

Flashover

No protective earth

Flashover

Protective earth present

Electric shock with faulty and good earth connection

Appendix G Grounding Verification Checklist and Procedures

Purpose This section of the appendix identifies activities required to verify that the grounding and bonding requirements are satisfied.

Verification Methods Equipment and subsystems shall be verified by analysis, demonstration, inspection, test, validation of records, or similarity (or a combination thereof ) as specified herein to assure compliance with grounding and bonding requirements which apply to the particular system. [a] Analysis Analysis (A) involves the use of engineering analysis, qualitative assessment, computer modeling, and/or simulations to ensure compliance to the requirement(s). Analysis is a method used in lieu of, or in addition to, testing. [b] Inspection Inspection (I) is the physical evaluation to ensure that the requirement(s) has been incorporated or met. Inspection shall be used as the method on the product to satisfy such requirements as construction features, workmanship, dimensions, and physical conditions identified on the engineering documentation (e.g. drawings and Engineering Parts List). [c] Demonstration Demonstration (D) is the “acting out” to ensure the requirement(s) has been incorporated or met. Demonstration shall be used as the method on the product to satisfy such requirements as accessibility, replaceability, and human factors. [d] Test Test (T) (e.g. functional and environmental) is the actual operation to ensure that the performance is in accordance with the requirement(s). [e] Validation of Records Validation of records (R) is the use of vendor-furnished/supplied manufacturing or processing records to ensure the requirement(s) has been incorporated or met. Validation of records shall be used as the method to satisfy incorporation of requirements for such items as commercial off-the-shelf products and products purchased to standards. [f] Similarity Similarity (S) is the process of assessing prior data, configuration, processes, or applications and concluding that the item under assessment is similar or identical to another item that has previously been verified to equivalent or more stringent specifications or validated to an equivalent use or function.

Verification method Topic

Primary Power Typically, primary power is facility/ vehicle/platform-generated power that is distributed to the various loads. Secondary power may be distributed to other loads, but secondary power distribution is usually, but not always limited in scope. Equipment/LRU Power Grounding: Interface (1) Equipment that provides a voltage source should reference the source to ground to allow for electrical fault clearing and enhance operability and safety. Equipment ground references should not be brought outside the equipment chassis, but should be connected as close to the source as possible to prevent noise currents and voltages from creating common-mode voltages in the power circuit.

•

A

I

✓

D

T

R

✓

S

Verification method comments

Success criteria

Inspection of grounding schemes of the primary power system

Verification is successful when inspection shows the power grounding scheme consistent with platform/facility requirements and national electrical codes, as applicable

Inspection of engineering documentation

Verification is successful when inspection shows the voltage source is referenced to ground and the grounding circuit is fully enclosed within the equipment chassis

See the following items: ✓

(Continued)

1111

1112

Appendix G Grounding Verification Checklist and Procedures

Verification method Topic

I

•

✓

✓

✓

Inspection of engineering documentation Inspection of engineering test results Analysis may be required to show isolation in all operational modes

Verification is successful when inspection and measurements show equipment maintains a prescribed (typically 1 MΩ) isolation between primary power lines and chassis and between primary and secondary power lines

•

✓

✓

✓

Inspection of engineering documentation. Inspection of engineering test results.

Verification is successful when inspection and measurements show equipment maintains a prescribed (typically 1 MΩ) isolation between primary and secondary power lines

Interface (2) DC Power consumers, converters, conditioners, distributors, etc., connected to primary power must maintain at least 1 MΩ DC isolation between both high and return lines and chassis to prevent SPG1 violation and the isolation should be maintained during all operational modes to prevent sneak circuits. Isolation between primary and secondary lines is required to prevent violation of SPG in circuitry utilizing secondary power. Secondary Power Isolation between primary and secondary is best achieved through the use of transformers. If secondary power is not further referenced to structure (i.e. floating output), then no SPG violation occurs and the intent of the requirement is met. Circuitry receiving secondary power should be analyzed to ensure that no intentional or unintentional (sneak circuit) ground reference is present. Equipment/LRU Signals Grounding Considerations: Signal Grounding Signal circuitry routed external to equipment shall be isolated from chassis/structure by at least 1 MΩ except at a single reference to structure on the transmit or source end (the reference is not necessary). Signal (Single-Ended) Returns Each signal, command, control, and power circuit routed externally to the equipment shall employ a separate return and shall be isolated2 from cable shields and destination chassis by a minimum resistance of 1 MΩ. Signal returns for circuits using separate derived power sources shall be isolated by a minimum resistance of 1 MΩ. Some databus protocols such as Electronics Industries Association (EIA) Standards permit utilization of a single return for multiple signals. The intent of this requirement is considered to be met when equipment meets such data bus protocols and complies with the functional requirements of the equipment. Such practice should be avoided on low-level, sensitive signal lines. Balanced/Differential Circuit Isolation Balanced differential circuits external to equipment shall be isolated from chassis by (typically) 6 kΩ or greater.

D

T

R

S

Verification method comments

A

Success criteria

See the following items:

•

✓

✓

Inspection of engineering documentation Inspection of engineering test results

Verification is successful when inspection and measurements show equipment signal returns maintains a prescribed (typically 1 MΩ) isolation except at the source end

•

✓

✓

Inspection of engineering documentation Inspection of engineering test results

Verification is successful when inspection shows equipment signal, command, control, and power circuits routed externally employ separate returns and returns maintains a prescribed (typically 1 MΩ) isolation from cable shields

•

✓

✓

Inspection of engineering documentation Inspection of engineering test results

Verification is successful when inspection shows balanced differential circuits routed external to equipment has prescribed (typically 6 kΩ) or greater isolation to chassis

Appendix G Grounding Verification Checklist and Procedures

Verification method Topic

Line drivers and receivers having balanced receivers and low impedance drivers are considered balanced circuits even though the source is referenced to ground. Coaxial Shields Coax cabling shall be permitted only when all frequency components of the signal are greater than or equal to 1 MHz. Coaxial interfaces shall not be used as interconnects between equipment utilizing different power sources unless electrical isolation is provided (opto-isolators, transformers, etc.) to prevent violation of SPG architecture. Coaxial cables should be terminated by coaxial connectors. Electrical Bonding: Bonding Provisions The equipment shall have provisions to allow its enclosure to be bonded to structure. Bonding provisions shall be for metalto-metal contact of bare surfaces or surfaces with a qualified conductive finish or for a ground-strap-tostructure bond. The bonding surface area shall be at least 4 times the crosssectional area of a cable conductor that could safely carry the expected current in the bond path. Bonding surface areas shall be prepared such that it is clean and free of paint or any type of nonconductive conversion coating. Bare, clean, metal-to-metal contact will ensure a low-impedance connection between mating surfaces. If a bonding strap is used, it should have a length-to-width ratio less than 5 : 1. The preferred method of bonding is through the mounting surface to structure. Corrosion Control Bonding between dissimilar metals should be avoided to preclude corrosion. Surface treatments should be applied, preferably on both mating materials. When dissimilar metals are to be bonded, consideration of proper design measures should be applied (e.g. coating and sacrificial metals) to minimize corrosion.

A

I

D

T

R

S

Verification method comments

Success criteria

•

✓

✓

Inspection of engineering documentation Inspection of engineering test results

Verification is successful when inspection shows all frequency components of signals carried on coax is greater than 1 MHz and coax interconnecting equipment using different power sources does not violated SPG

•

✓

✓

Inspection of engineering documentation Inspection of engineering bonding resistance measurement results

Verification is successful when inspection shows the equipment has the necessary provisions for electrical bonding and the provisions, including the bond straps comply with the requirements for cleanliness, surface finish, and dimensions

✓

✓

Analysis of mating metals’ compatibility using proper galvanic/ electrochemical series. Inspection of the interfaces of mating surfaces for the presence of corrosion.

Verification is successful when analysis demonstrates that compatible metals are used or that appropriate protection measures were applied. Verification is also successful when inspection shows no traces of corrosion at the bonding areas after salt-spray tests. Note that corrosion may not be observed on newly produced equipment but could appear during long-term use, hence the value of the salt-spray tests.

•

✓

(Continued)

1113

1114

Appendix G Grounding Verification Checklist and Procedures

Verification method Topic

A

I

•

✓

•

✓

Wiring Circuits Wire Twisting Circuits that interconnect equipment shall provide for minimum loop coupling and maximum flux cancellation by twisting of return with high side. Twisting should only take place between signal and their associated return lines, or between wires in a differential pair. Both signal and power circuits shall be twisted with their respective returns. Multiple circuits sharing a common return shall be twisted as a group. Wire Shielding Wire shields shall cover the twisted pair or twisted group rather than individual wires. No shield shall intentionally carry current except for coaxial cables used at radio frequencies only (1 MHz and above). Circuit shields should normally be terminated to the equipment enclosure at both ends, preferably through a low-impedance, circumferential (360 ) termination, such as a conductive EMI backshell that makes good electrical contact to the equipment case. The DC resistance between the cable shield and case shall not exceed 15 mΩ. Overall shields may be used over a cable bundle for additional protection and shall also be grounded to equipment case at each end. Electrical connectors that may be used to terminate cable shields shall be installed to provide a low impedance path to the equipment case. Mounting surfaces shall be clean and free of nonconductive material. The DC resistance between the connector and case shall not exceed 2.5 mΩ.

D

T

✓

1

R

S

Verification method comments

Success criteria

Inspection of engineering documentation and of actual cables after production.

Verification is successful when inspection shows returns are twisted with the high side, signal and power circuits twisted with their respective return, and multiple circuits using a common return are twisted as a group

Inspection of engineering documentation Inspection of engineering test results

Verification is successful when inspection shows cable shields cover the twisted pair or group and shields do not intentionally carry current (except coax). Verification is successful when inspection also shows cable connectors used to terminate cable shields are installed to provide a low impedance path to case with the DC resistance not to exceed a prescribed value (typically 2.5 mΩ between connector and enclosure, and 15 mΩ between the cable shield to the enclosure)

SPG: Single-Point Ground. Commentary: Testing isolation of signal returns must be performed prior to connecting cables and equipment. Connector pins, connected to signal returns in the equipment containing the power source, should measure continuity to chassis ground. Signal returns in cables or equipment not containing or connected to the power source should measure at least 1MΩ when measured from return to equipment chassis or cable shield. At least 1MΩ should also be measured between signal returns for circuits using separate derived power sources. On-Site Inspection

2

Source: MIL-HDBK-419A [2]/U.S. Department of Defense.

Appendix G Grounding Verification Checklist and Procedures

Purpose This section of the appendix provides some guidance pertaining to grounding and bonding inspection on site:

Before Equipment is Installed a) Before installing, or accepting for installation, any piece or item of electronic equipment in a facility or platform designed or modified to meet the grounding and bonding requirements, the equipment should be evaluated for conformance with the practices set forth in the installation documentation (Figure G.1). Results of this evaluation should be recorded in the Inspection Form. b) Prior to evaluation, determine whether the equipment is designed to operate at frequencies (a) from DC up to 300 kHz or (b) above 300 kHz. Pulsed signals are always considered to be higher frequencies. In making this determination, the primary signals to consider are those which interface or communicate with other equipment or systems. For example, the frequencies of control and monitor signals, communication signals, data links, and input and output RF signals should be noted. Signals arising from internal sources and utilized only internally to the equipment are primarily the designer’s responsibility. The frequencies should be listed in the Inspection Form. c) After establishing the frequency classification of the equipment, inspect the lower and higher frequency types for conformance with their respective frequency bands. Some equipment will necessarily utilize both lower and higher frequency signals for interfacing purposes. For example, wideband data links frequently extend from low audio frequencies to frequencies well above 1 GHz. Specific inspection steps and procedures for all three types of equipment are contained in the following sections. Individual unit or piece or equipment

Signal ground terminal

Disconnect all signal data and control cables

Unplug power cord Selector switch Alternate probe position for measuring resistance of green safety connections

Measure resistance between signal ground terminal and a clean, unpainted point on the equipment case

Ohm meter

Figure G.1 Signal ground terminal isolation resistance test for an individual equipment. Source: MIL-HDBK-419A [2]/U.S. Department of Defense.

1115

1116

Appendix G Grounding Verification Checklist and Procedures

(1) Lower Frequency Equipment. [a] Examine the drawings and schematics and visually inspect to see if an isolated single-point signal ground is provided. Provide a brief description of the signal ground network in the Inspection Form or attach copies of the schematics or drawings. Verify that the internal signal ground network is terminated to an insulated signal ground terminal or as otherwise specified. If a wire is used, verify that the size conforms to the specified value. Enter the information requested in the Inspection Form. [b] Verify that the signal ground is correctly identified with a yellow label or color code. [c] With all cables (signal cables, control lines, power cables, etc.) disconnected, measure the resistance between the signal ground terminal and the equipment case. The resistance should be greater than one megohm. Also, measure the resistance between each AC input terminal (ground wire excluded) and enclosure. A resistance of 1 MΩ or greater should be measured. Note: Prior to Performing Resistance Testing, Disconnector Unplug All Cables (Signal, Power, Data, Control, etc.) [d] Record both readings in the Inspection Form. If the measured resistance is less than 1 MΩ, proceed as follows: I. First check to see that all cables, lines, cords, etc., are disconnected from the equipment or that the far ends of any such cables are insulated from other equipment and the structure. Disconnect all cables found still connected. II. If no connected cables are found or the low resistance reading still exists after disconnecting all cables, visually inspect the mounting of the signal ground terminal to see that it is properly insulated from tile case or cabinet (disassemble, if necessary). Alternately, disconnect the signal ground connection inside the equipment and then measure the resistance between just the terminal and the case. If the terminal is not insulated from the case or cabinet, it must be redone. III. If the preceding two steps fail to identify the reason for the lack of isolation, the equipment schematics and mechanical layout should be analyzed and inspected to locate the compromise in the signal ground isolation. Be particularly alert for sneak paths through components (transformers, switches, relays, etc.), readout devices (meters, lights), physical contact between the case or cabinet and the signal ground, and wiring errors. [e] Measure the resistance between the green protective earth (PE) wire and the case; the resistance reading should be 0.1 Ω or less. If higher reading is obtained, inspect the equipment to see if the PE wire in the power cord has been connected to the case or cabinet. If the connection is there physically, was the paint removed from the area of attachment? Are screws or nuts fastened securely? If any of these deficiencies exist, they must be corrected before installing or energizing the equipment. [f] Inspect all cabling and connectors to see that balanced signal lines are used for lower frequency interfacing: lines and that cable shields Doubled-balanced are terminated at both ends. The shields of individual cable pairs bridge must be isolated from each other except at the common ground points, unless analysis has shown that no such isolation is necessary. Check overall shields for proper termination. Record any specifically noted deficiencies in the Inspection Form. [g] If the equipment is already installed, verify that the signal ground terminal is connected to the nearest feeder ground plate of the lower frequency signal ground network for the facility. Check the size of Current Potential leads the cable to see that it conforms to the specified value. leads (2) Higher Frequency Equipment [a] Verify that higher frequency reference points and planes are directly grounded to the chassis and the equipment case to the extent permitted by circuit design requirements (and unless specified otherwise). [b] Check to see that properly matched constant impedance cables are used for interfacing purposes. Verify that all connectors are of a type and design that provides a low impedance path from the signal line shield to the equipment case. Do not permit the use of pigtails for the termination of higher frequency cable shields outside the equipment enclosure. [c] Check connectors for tightness, cleanliness, and for proper mounting. Measure the DC resistance between the connector shell or body and its mounting with a milliohm meter. The resistance should not exceed 1 mΩ. If the resistance exceeds 1 mΩ, the mounting surfaces should be recleaned to remove all paint, nonconductive coatings, or dirt and all screws or fasteners should be retightened to achieve a close mechanical fit (Figure G.2). [d] Measure the point-to-point resistance between selected points on the case or cabinet with a milliohm meter. The maximum DC resistance

Connector

Mounting surface

Figure G.2 Measurement of connector bonding resistance. Source: MIL-HDBK-419A [2]/U.S. Department of Defense.

Appendix G Grounding Verification Checklist and Procedures

between any two points on the case or cabinet should be 1 mΩ or as specified. If the resistance is greater than 1 mΩ, check to see that all bonding surfaces are properly cleaned and that all connections are securely fastened. (Larger sized bonding conductors may have to be added to reduce the resistance to 1 mΩ or less.) [e] Record the results of the inspection in the Inspection Form. (3) Hybrid (equipment utilizing both lower and higher frequency interfacing signals) Equipment If the lower and higher frequency signal networks are separate, inspect each in accordance with the preceding respective instructions. If the networks involve both lower and higher frequency signals, inspect for conformance with the higher frequency requirements. Record the results of the inspection in the Inspection Form.

Installed Equipment a) Check to see that installed equipment have their cases or cabinets bonded to the facility or platform ground system as specified.

Fault Protection Subsystem a) Verify that all exposed metal parts of the equipment are properly bonded to the protective earth conductor as prescribed by the applicable codes. Record all information obtained in the Inspection Form.

Bonding a) Inspect all joints, seams, and connections to see that the mating surfaces were cleaned of corrosion, nonconductive finishes, and dirt prior to. Check fasteners for tightness. Have combinations of dissimilar metals been avoided or, where unavoidable, have appropriate protective measures been applied? b) Do not permit sheet metal screws or Tinnerman nuts1 to be used for electrical bonding. c) Where used, do bonding jumpers generally conform to the design recommendations? d) Check all bonds between subassemblies, equipment, and racks for conformance to the design recommendations? e) Inspect shield terminations for tight peripheral bonding to the connector shell. Such connections should be firm, offer maximized contact between the shield and the shell, and should be formed in a way that restricts the entrance of moisture and foreign matter into the bond area. Preferably bonds should be protected with an adequate weather seal. f) Pigtail terminations should be inspected for tightness and for excessive length. The pigtail should only be long enough to permit the connection to be made. Record the findings in the Inspection Form. g) Determine the proper mounting and bonding of terminal protection devices (e.g. EMI filters and surge protection devices) installed on signal, control, or power lines associated with the equipment. h) The maximum DC resistance between the devices and the mounting surface (e.g. entry-point bulkhead panel) should be 1 mΩ or less. If the resistance is greater than 1 mΩ, check to see that all bonding surfaces are properly cleaned and that all connections are securely fastened. i) Record all observations in the Inspection Form.

Other Observations a) As appropriate, note the existence of any personnel hazards due to deficiencies of grounding and bonding in the Inspection Form. 1 A speed nut, a.k.a sheet metal nut or Tinnerman nut, is a type of locknut with two sheet metal prongs that act as one thread. They are made from spring steel. The fastener serves the functions of both a lock washer and a nut. As the fastener is tightened in the nut, the prongs are drawn inward until they exert pressure on the root of the thread on the fastener. When the fastener is tightened, the base of the nut, which is arched, elastically deforms and applies a force to the fastener, which locks it from loosening under vibrations.

1117

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Appendix G Grounding Verification Checklist and Procedures

References 1 NASA MSFC-SPEC-521 (2013). Revision C, MSFC Technical Standard, Electromagnetic Compatibility Requirements for Equipment

and Subsystems. NASA, the National Aeronautics and Space Administration (1 July 2013). 2 MIL-HDBK-419A (1987). Military Handbook, Grounding, Bonding, and Shielding for Electronic Equipments and Facilities.

Washington, DC: U.S. Government Printing Office.

1119

Appendix H Grounding Documentation Content The complexity of grounding systems and schemes requires that careful documentation be done, particularly in complex platforms and systems (grounding and earthing of facilities is normally included in the facility electrical schematics). Often, electrical system designers consider only the primary power grounding schemes while overlooking the secondary power and signal return paths. Those, however, if overlooked may significantly impact system performance, and give way to system-wide ground loops and ground-coupled interference.1 This appendix provides a (probably) nonconclusive checklist of items that should be included in equipment and system grounding documentation and schematics, as follows:

H.1

Approach for Grounding/Power Distribution Schemes

In complex systems, it is recommended to describe the architecture of power and grounding distribution in two separate drawings. a) A power distribution scheme, which illustrates the paths of the power current from the power sources to the final loads. b) A “grounding tree,” which illustrates the return current paths from the loads back to the signal and power sources. The “grounding tree” shall also include signal and control return paths, as well as the grounding schemes for cable shields. The following are a few ground rules and recommendations for the design of the grounding tree: a) When sensing/monitoring (e.g. telemetry) systems consists of a large number of components, it may be preferable to prepare a separate set of power distribution/grounding schemes for the sensing/monitoring system. Interconnections and interfaces between the platform/facility operational and the sensing/monitoring grounding systems shall be clearly marked in both drawings and grounding schemes. b) If a distributed single-point grounding scheme is used (i.e. when different sections of the system/platform are powered and referenced to separate power sources), each section may be described in separate drawings. c) The grounding scheme of the operational environment shall also be incorporated in system integration and development facilities, including, but not limited to simulators/emulators, test and support equipment, monitoring and sensing equipment, etc.

H.2

Content of Power and Grounding Schemes

The power distribution and grounding schemes shall include, as a minimum, the following data: a) All primary AC and DC power sources and secondary (all voltage derived from switch-mode DC/DC or AC/DC power supplies or voltage regulators) power circuits. When possible, tertiary power circuits (all voltages derived from the secondary power circuits) shall also be included. b) The exact physical location of grounding nodes or system-wide common-impedance points, where the location of grounding nodes is changed during operation (for instance through ground-switching relays). The switching device shall be included in the schematics and both (or more) states shall be addressed. 1 Chapter 14 provides several case studies where ground-loop coupling interference between primary and secondary power circuits and between them to the signal circuits resulted in system failure and even damage. Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

1120

Appendix H Grounding Documentation Content

c) If the power distribution and grounding schemes are dependent on the operation mode of the system, which should be noted in the drawing, by using a proper graphical notation. Alternatively, a separate drawing shall be prepared for each operation mode, which affects the power distribution and/or grounding schemes. d) All power line filters at the input and output of the power sources and loads. e) Devices powered from more than one power source, primary and/or secondary. For instance, an operational amplifier, powered from a 28 V power source, while one of its inputs is 5 V and the reference voltage is derived from 15 V. f) Power switching devices (e.g. transistors, FETs, relays, SCRs). g) Protective devices or circuits: All protective measures against EMI (e.g. EMI filters), transient voltage surge suppressors (e.g. TVSSs, surge suppressors, surge stopper), overvoltage protective devices (e.g. surge stoppers and shutdown circuits), fault current, and short circuits (e.g. fuses, circuit breakers, residual-current device, or RCDs) shall be shown to allow the analysis of their behavior. h) All cable shields and shield termination techniques, and location of chassis connections. The actual manner of shield termination should be noted in the drawing. i) Types of circuit signal interfaces (discretes, single-ended or differential serial data busses, RF, analog, video, etc.) j) Indication of types of conductors used for grounding and bonding purposes. k) All passages through separation and bulkhead panels and connectors shall be noted. l) Special loads antennae be described using a specific graphical symbol (e.g. moors, transmitters, antennae, disconnect and junction boxes) m) Loads should be described in terms of equivalent circuit elements (resistance, inductance, capacitance). For instance, “An electronic assembly has an input capacitance of 50 μF and the load on the 5 V power supply in its secondary terminals is 1 A; a 5 Ω load resistance should be used.” Motors should be described using their inductive parameters for transient effects (e.g. “back EMF”) analysis. These definitions should be obtained from the system engineer. n) Paths of wires carrying currents exceeding 1 A shall be illustrated showing the entire current and return paths/loops, from source to end-load (motor, actuator, transmitter, etc.) and back to facilitate analysis of the full functional performance. o) Current sensing devices (e.g. shunt resistors, Hall-Effect devices) shall be described and their actual location shall be noted. p) Specific serial number (S/N) of assemblies/circuits incorporated in the equipment/system, as replacing those with substitute unites, OEM (original equipment manufacturer) or COTS/NDI (commercial off-the-shelf/nondevelopment items), in particular, is concerned, could modify the grounding scheme. For this purpose, also, the grounding description document should be configuration controlled.

1121

Appendix I On the Equivalence Between Ohm’s Law and Fermat’s Least Time Principle In Chapter 2, the principle of path of least impedance with respect to return current propagation path was discussed. It was concluded that “current, if not altered by significant amount of impedance, always assumes a distribution that minimizes the impedance of the loop formed by the signal and return path.” At lower frequencies, the “path of least impedance” was shown to correspond to the “path of least resistance,” whereas, at higher frequencies, it corresponds to the “path of least reactance” or “path of least inductance.” It was shown that this principle is traceable to the principle of conservation of energy, whereby it was stated that “current will flow in the path such that the energy stored in the consequent magnetic field is minimized.” It was further shown that conservation of energy is yet but a special case of the greatest generalization in all physical science, that of “least action,” which, simply stated, asserts that nature always finds the most efficient course from one point to another. Fermat’s premise of “least time” is one of the manifestations of the “least action” principle. The objective of this appendix is to demonstrate the equivalence between Ohm’s law, E=

1 J σ

I1

(Equation F of Maxwell’s eight original equations) to Fermat’s premise of “least time.” With this demonstration established, the notion that “current follows the path of least impedance because it constitutes the path of least time and, thus, the ‘path of least action’ is proven.” This appendix begins with a fundamental scientific formulation and proceeds to introduce the least time/maximum probability (LT/MP) principle. The LT/MP principle is Fermat’s principle of least time and classical probability theory combined [1].

I.1

Origin of the LT/MP Principle

The origin of the least time/maximum probability (LT/MP) principle can be traced back to a fundamental scientific hypothesis. This hypothesis is phrased as follows: In any frame of reference where the total number of possible outcomes of an observation is N, the number of similar outcomes n is inversely proportional to the average time, τ, required to complete the process that generates the observed outcome. The scientific hypothesis is founded on the basis of two classical and elementary concepts:

• •

The proportionate number of similar outcomes (n/N) represents the classical definition of probability of an observed outcome. The average time, τ, required to complete the process that generates the observed outcome. In a process involving a group of outcomes, the inverse of the mean time (τ–1) measures the frequency of occurrence of the observed outcome.

Thus, the scientific hypothesis is a simple statement of a commonly known fact: The probability of the outcome of an observation, P, is directly proportional to the frequency of occurrence of the observed outcome.

I.2

Statement of the LT/MP Principle

The parametric equation for the LT/MP scientific premise can be written as follows: P p =

1 N

1 τ p

=

1 τ p all τ 1 τ p

Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

I2

1122

Appendix I On the Equivalence Between Ohm’s Law and Fermat’s Least Time Principle

In Equation (I.2), N represents the total number of possible outcomes and, thus, it clearly demonstrates that the maximum probability is inversely proportional to the least time. This is the least time/maximum probability (LT/MP) principle, given by P max p =

1 N

1 τ min p

I3

Electrical current constitutes the transport of an ensemble of charged particles between two points in a circuit. Given that a number of alternative paths (or channels) are available, the total current for which the total number of charged particles is N will be distributed over all available paths. The manner in which the current is distributed over the different paths or channels is in direct proportion to the probability that charged particles fall into a specific channel. The channel that carries that larger current is, by definition, the channel of greater probability, since for that one channel: n1 n2 = P n1 > = P n2 N N

I4

where n1 and n2 represent the number of charged particles in (the alternate) channels 1 and 2, respectively. Therefore, the channel with the largest current is the channel corresponding to the largest probability, also denoted the “main channel.” The LT/MP principle is, therefore, a selection rule for determining the primary current propagation channel and states that: Current follows the path of least time because it is the path of maximum probability.

I.3 Derivation of the Equivalence Between Ohm’s Law and Fermat’s Least Time Principle The derivation shall commence from Ohm’s Law of Materials: J ≜ σE

I5

where σ is the conductivity of the medium is σ = ρ

−1

and the current density, J, is expressed as,

J = ne < u >

I6

In Equation (I.6), ne represents the electron volume (Vol) charge density and is given by: ne =

dQ dQ = dVol A dℓ

I7

where: A = cross section of the current channel passing an average charge particles velocity < u > dℓ = distance traveled along the electric field, E dt (refer to Figure I.1). The electric field E is responsible for driving the charges from a source region to a drain region through a voltage drop, V, and is given by: E = − ∇V = − E = −ΔV = −

e

J =

e e

e

I8

where ∇ in Equation (I.8) represents the “del” or “grad” operator. Ohm’s Law can therefore be rearranged and is rewritten in the form:

dQ ne = 1 ⋅ A d

dV d

dV dℓ

e

dQ = A dℓ

dQ A

dℓ

=

1 1 dV E= − ρ ρ dℓ I9

This equation can again be rearranged to obtain the equation for the incremental time to transport the charges through the path dℓ: d

dℓ

E

=

ρ

1 A

dQ E

= −

dQ dV

ρ

1 dℓ A

I 10

Equation (I.10) can now be integrated to obtain the equation for

Figure I.1 Geometry for demonstrating the parameters of the the incremental time required to transport the charges through charge propagation channel. the distance dℓ. Note that since the electron charge is negative,

Appendix I On the Equivalence Between Ohm’s Law and Fermat’s Least Time Principle

the incremental time in Equation (I.10) is positive. Integrating both sides of Equation (I.10) with respect to distance, ℓ, we obtain: ℓ =

τ=

ρ

1 A

Q E

= −

dQ dV

ρ

ℓ A

I 11

Also, observe that the right-hand term in Equation (I.11) is the classical expression for the electrical resistance, R, of the current path: ℓ A

R=ρ

I 12

Hence, Equation (I.11) reduces to: ℓ =

τ=

− dQ dV

I 13

R

In any given medium, the time to transport a charged particle is the distance traveled divided by its velocity in that medium. Any ensemble of particles is characterized by a velocity stochastic distribution of its constituents and in a given medium the majority of the particles travel at an average velocity, < u > . Therefore, for the majority of charged particles in an ensemble, the average transport time τ(p) is: τ p =

ℓ

I 14

Note that Equation (I.14) is equivalent to the left-hand term of Equation (I.11) while considering the transport time τ(p) as a stochastic process. Equation (I.14) thus corresponds to the key equation in the LT/MP Theory.

I.4

Equivalence of Ohm’s Law and the LT/MP Theory

In a typical circuit, the factor Q/E appearing in Equation (I.11) is constant. Equation (I.11) can be minimized from the equivalence of Ohm’s Law (minimum resistance), and Fermat’s Principle, also known as the principle of least time, is the link between ray optics and wave optics. In its original “strong” form, Fermat’s principle states that the path taken by a ray between two given points is the path that can be traveled in the least time. Fermat’s principle is illustrated in Figure I.2 where, given an object-point A in the air, and an observation point B in the water, the refraction point P is that which minimizes the time taken by the light to travel the path APB. If we seek the required value of x, we find that the angles α and β satisfy Snell’s law, Recalling that capacitance, C is defined as: dQ dV

C≜

I 15

It follows therefore that: min τ = min

ℓ

= min

− dQ dV

ρ

ℓ A

= min C R

I 16

Consequently, τ (Fermat’s Minimum Time) = C × R (Ohm’s Minimum Resistance) Equation (I.16) illustrates an unequivocal correspondence between minimum time and minimum resistance. The derivation to present a direct correspondence with the least impedance is practically the same and follows the following reasoning, casting the transmission line equation into the framework of statistics can easily demonstrate this equivalence: V =

dV =IZ dx

V Z

a

l1 α

x

P B

b

l2

I 17

d

I 18

Figure I.2 Fermat’s principle in the case of refraction of light at a flat surface between air and water, for instance. Source: Klaus-Dieter Keller/Wikipedia/ CC0 1.0.

Solving for the current – I, yields: I=

A

B

1123

1124

Appendix I On the Equivalence Between Ohm’s Law and Fermat’s Least Time Principle

In a given electric field, E = − ∇V = −

dV dx

I 19

the path of maximum probability where current, I, is at its maximum, the impedance of the channel, Z, must therefore be at its minimum. Therefore, in conclusion: 1) Least Time Maximum Probability (Derived from the theory of Fourier Transform, noting that probability frequency of occurrence) 2) Maximum Probability Maximum Current (Fourier Transform Maxwell’s Equations through Ohms Law in Materials) 3) Maximum Current Least Impedance (Maxwell’s Equations Transmission Line Theory)

Reference 1 Briët, R. (1997). Application of the LT-MP principle to the theory of lightning propagation. Interference Technology Engineering

Master (ITEM), USA (1997). Interference Technology.

1125

Appendix J Thoughts on the Low-Frequency Return Current Distribution If I had an hour to solve a problem, I’d spend 55 minutes thinking about the problem and 5 minutes thinking about solutions. — Albert Einstein

J.1

Introduction

Disclaimer This appendix does not provide conclusive information and should not be treated as such. Rather, this Appendix provides some thoughts, based on formal resources (when quoted), simulations, and also on thoughts and stipulations by the Author, which might still need confirmation (and proof ) or contradiction. It is primarily brought here as “food for thought” and to serve as a basis for analysis of common-impedance coupling at lower frequencies (see Appendix L). It is a well-established fact that current, if not obstructed, always follows the path of least impedance. At higher frequencies (approximately above 100 kHz), current, always follows the path of least inductance, whereas at lower frequencies, the path of least resistance.1 In a PCB, higher frequency return current flows in the return plane immediately under the signal trace (Figure J.1a), whereas at lower frequencies, it tends to spread in the PCB, in the path presumably being the path of least resistance (Figure J.1b). An approximate expression for the return current distribution at a distance, d, from the centerline of the signal trace (assuming a narrow trace close to an infinitely wide reference plane) is [1]: J GP d ≈

I0 1 πh 1 + d h

2

A m

J1

where JGP(d) = current density at a distance, d, from the trace centerline, A/m I0 = magnitude of the total current flowing on the source trace, A d = distance from source trace centerline, m h = height of trace above the reference plane, m. A similar effect was observed in coaxial cables (Figure J.2). At lower frequencies (e.g. in the kHz range and below) (Figure J.2a), return current flows through the entire cross section of the cable shield (minimizing path resistance); at intermediate frequencies (e.g. around the 100 kHz range) (Figure J.2b), it flows through a fraction of the shield cross section (higher resistance, but lower inductance); while finally, at high frequencies (e.g. around the 1 MHz range and above), it flows through a tiny cross section and all current is confined to the inner surface of the shield (highest resistance, but minimal inductance).

1 This principle was discussed in detail in Chapter 2 (general discussion) and Chapter 13 (as this principle applies to printed circuit boards (PCBs). Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

1126

Appendix J Thoughts on the Low-Frequency Return Current Distribution

Return current pattern in ground plane

Signal trace

Ground plane

(a)

(b)

Figure J.1 Path of signal return current distribution in a PCB. Simulation run on Keysight (Formerly Agilent Technologies) “Momentum” 3D Planar EM Simulator. (a) F = 100 kHz. (b) =1 kHz. Source: Courtesy of Alexander Perez, Agilent Technologies.

(a)

B=0

B=0

B=0

B=0

(b)

(c)

Figure J.2 A cross section of a coaxial. (a) Low frequencies. (b) Middle frequencies. (c) High frequencies. Source: Constant314/Wikipedia/CC0 1.0.

Skin depth, δ, is defined as: δ=

1

J2

π f μ σ cu

where f = frequency of interest, Hz μ = permeability of the plane material (cu), H/m. Presumably, the current distribution at lower frequencies is a simple question. “The return current follows the shortest path, which exhibits the lowest resistance,” right? Surprisingly – not so. To demonstrate the difficulty (consider Figure J.1b), the resistance, R, of a uniform conductive path of length, L, cross section, A, and resistivity, ρ, is: R=ρ

L L =ρ A WH

J3

where W and H are the width and length of the current path, respectively, at a given point along the path. A dilemma that follows is, therefore:

•

If all current returns through the shortest path (i.e. min{L}) between source and load, it will ultimately flow through a very narrow path, W 0, or A 0, thus: R=ρ

L A

L min 0

R

∞

J4

Appendix J Thoughts on the Low-Frequency Return Current Distribution

•

If the current returns spread out across the entire PCB, flowing through the largest cross section available (i.e. max{A}), the length of the path between source and load increases significantly, thus: R=ρ

L↗ A↗

J5

Via 2

Signal current source

Via 1

Quasi-static return

current path And this approach too would not minimize R. (path of least R?) The question is, therefore, where is the balance, or the point of equilibrium? Research of literature, revealed that High-F return Signal Ground no closed-form expression, even for the very simple case of current path trace plane return current flowing between aligned source and load, is (path of least L) available. This question actually has some practical applications, as may be observed in Appendix L. Observe, for instance, an illustration of the classical experiment (provided in full in Chapter 2) whereby current flows in a “U”-shaped trace closely spaced above a ground plane.2 Whereas at high frequencies (typically in the 100 kHz range Figure J.3 Illustration of high- and low-Frequency current and above), the return current is known to follow the path of return paths. the signal trace (if not obstructed …),3 with some spreading about the trace, as shown in Equation (J.1) (Figure J.3); at lower frequencies (typically in the kHz range and below, where quasi-static assumptions may apply), the return current follows the shortest path, but with some spreading, pretty much like the flux lines between two opposite charges (Figure J.4). Might there be some non-coincidental relationship between the two cases? This appendix provides some insight into the question of lowfrequency (quasi-static) return current distribution in the ground plane.4

J.2

Current Flow and Ohm’s Law

Many current flow problems cannot be solved analytically [2].5 Therefore, a discussion of flux-plotting techniques is included in this appendix. In the quasi-static case, in the region external to the current source, the field producing a current flow is the (quasi) electrostatic field. Since current density is linearly related to the electric field, an interesting duality between the current flow field and the displacement flux exists. This duality may often be made use of in the solution of current flow problems. In the conducting medium, it is found experimentally that the current is related to the electric field by: J = σE

Figure J.4 Electrical field (flux) between positive and negative charges in free space.

J6

where E represents the E-field in the medium, σ is the conductivity of the medium in Siemens, and J is the current density in Amperes per square meter. 2 This “close spacing” assumption is necessary for ensuring “tight-coupling” between the trace and the return plane, as described in detail in Chapter 2. 3 This phenomenon is strongly dependent on the tight coupling between the trace and the return path in the ground plane, as mentioned in the previous footnote. 4 Much of the discussion in this appendix is based on exchange of ideas with, and contributions of Prof. Antonio Orlandi, from the University of L’Aquila, Italy. 5 Most of the derivation in this section is derived from [2].

1127

1128

Appendix J Thoughts on the Low-Frequency Return Current Distribution

Equation (J.6) is valid when σ < ∞ (i.e. finite conductivity).6 In that case, the vector relationship in Equation (J.6) implies that the lines of flux, J, coincide with those of the field, E (see Figure J.3). For conceptual reasons, the E-field is conveniently interpreted in terms of flow (flux) field. The current flow field, J, however, truly involves flow, and J represents the quantity of coulombs flowing across a unit cross-sectional area per second. As usual, to calculate total current flow across a surface, the following surface integral must be evaluated:

Φ2

E

H

L

J

I=

J ds

J7

S

Φ1

W

Equation (J.7) implies that conduction is both linear and isotropic, which is not always true (for instance, in composites). However, for metals, under a wide range Figure J.5 Uniform current flow in a of current densities, it does apply. For the purpose of this discussion, it will be rectangular bar. Source: [2]/McGraw-Hill. assumed that Equation (J.6) correctly relates current density and electric field in conductors. Equation (J.6) is a point relationship and is true even if it is a function of coordinates. For a homogeneous body with uniform current, it is relatively easy to obtain a relationship between it and the applied field. Such a formulation would be desirable in a circuit analysis. A simple case is illustrated in Figure J.5, where a uniform axial applied field exists in a conductor of rectangular cross section [2]. From Equation (J.7), the total current that flows through this bar is (assuming uniform current distribution): I = J WH = σE WH = σEA

J8

where A is the cross section of the bar, A = WH. Assuming that over the extent of the conductor, E is conservative, then: E = − ∇ϕ

J9

and the potential difference between the ends of the conductor is: V = ϕ1 − ϕ2 = EL

J 10

Combining Equations (J.8) and (J.10) results in: I=

σ

WH V = GV L

G=σ

WH L

J 11

where G is the total conductance of the parallelepiped.7 As it is more common to specify the resistance of the conductor which is the reciprocal of the conductance and so may be written as: R = G−1 =

1 L L =ρ σ WH WH

J 12

where ρ (not to be confused with charge density) is the resistivity in ohm meters, is the reciprocal of the conductivity. Equation (J.12) represents the resistance of any homogeneous conductor in the presence of a uniform field. A particular case are the wire-like conductors. From Equation (J.12), the well-known statement of Ohm’s law as applied to the macroscopic circuit is derived: V =I R

J 13

If current density is uniform over a constant cross section A, then:

L

1 dl = σA

↺

↺

R=

ρ dl A

J 14

L

6 Clearly, a perfect electrical conductor, or PEC, cannot be assumed, because based on Ohm law in materials, Equation (J.6), if σ ∞, E in the material must vanish to maintain a finite (zero) current, J. However, with finite σ, some E-flux can exist in the plane, which would drive the current between the two points (drive and load). 7 In geometry, a parallelepiped is a three-dimensional figure formed by six parallelograms. By analogy, it relates to a parallelogram just as a cube relates to a square. In Euclidean geometry, the four concepts – parallelepiped and cube in three dimensions, parallelogram and square in two dimensions – are defined, but in the context of a more general affine geometry, in which angles are not differentiated, only parallelograms and parallelepipeds exist.

Appendix J Thoughts on the Low-Frequency Return Current Distribution

Equation (J.14) provides the total resistance of a uniform cylindrical conductor. For a homogeneous body of conductivity σ, but of an arbitrary shape (Figure J.6), a more general expression can be derived: When no sources exist in the structure under consideration, the field external to the source is conservative and can be derived from a scalar potential: E d l = ϕ1 − ϕ2

A2 Φ2

A′ A E, J σ Φ1

J 15

A1

L

where C is any path starting at surface Al and terminating at surface A2 and ϕ1 − ϕ2 is the potential difference between the Figure J.6 An arbitrary-shaped conductor. surfaces Al and A2. Source: [2]/McGraw-Hill. Consider any cross-sectional surface in the conductor such as A or A in Figure J.6. From the law of conservation of charge, the same total current crosses surfaces A1, A, A , and A2, thus the current over any surface may be evaluated over any surface, A, from Equation (J.7) as: I=

J da

J 16

A

Substituting J = σE into Equation (J.16) yields: I = σ E da

J 17

A

By definition, the resistance between the two surfaces A1 and A2 is:

R=

ϕ1 − ϕ2 = I

E dl L

σ

J 18 E da

A

Although Equation (J.18) is rather simple in concept and form, the integrals cannot be evaluated before a detailed solution for the field, E (or current flow density, J), has been obtained. For a general-shaped conductor, this is usually not feasible and one is forced to resort to approximate methods of analysis or experimental methods in order to determine the resistance, R. Another expression for R can be formulated that better demonstrates the geometrical properties of the resistance. Again, it is necessary to know the field and current distribution everywhere within the conductor. Figure J.7 illustrates a general conductor with two equipotential cross-sectional surfaces Si and Si+l. The potential difference between these surfaces is denoted Δϕi. The volume between Si and Si+l may be decomposed into a number of elementary flow tubes of length Δli and cross-sectional area ΔSj. Figure J.7 Two equipotential surfaces within an arbitrary current-carrying conductor. Source: [2]/McGraw-Hill.

Δln

Δli

ΔSj J Si S1

Si+1

Sn

Sn+1

1129

1130

Appendix J Thoughts on the Low-Frequency Return Current Distribution

For each elementary tube the resistance, rj, is given by: rj =

Δϕi EΔli Δli = = ΔI j σΔS j σEΔSj

J 19

The conductance of this flow tube is: σΔSj Δli

gj = r j− 1 =

J 20

As conductances in parallel add directly, the total conductance between surfaces Si and Si+l is: ΔGj =

gj = j

j

σΔSj Δli

J 21

which corresponds to a resistance: 1

ΔRi =

J 22

σΔSj Δli

j

In general, the length, Δli, will vary over the cross section since the spacing between the equipotential surfaces, Si and Si+l, may not necessarily be uniform. By dividing the entire conductor into n such sections, Equation (J.22), the resistance of the i-th section can be used to derive the total resistance of the entire length of the conductor as a series combination of all ΔRi − s given by: 1

R= i

j

J 23

σΔSj Δli

From Equation (J.23), it is evident that the resistance formula may be obtained by allowing ΔSj and Δli to approach zero. In order to obtain a meaningful expression, a suitable set of curvilinear coordinates must be introduced. Since σE = J = − σ∇ϕ

J 24

is normal to the constant potential surfaces, a curvilinear coordinate, u1, is introduced. This coordinate increases in the direction parallel to the current flow lines and is normal to the constant potential surfaces. The distance, dl, along the flow lines is then given by h1du1, where h1 is a scale factor and, in general, will vary over the cross section of the conductor. Over the constant potential surface, we assume that two additional orthogonal curvilinear coordinates, u2, u3, can be introduced in order to measure the cross-sectional area of an elementary flow tube. The cross-sectional area ΔSj is now given by ΔSj = h2h3Δu2Δu3, as depicted in Figure J.8. The factors h2 and h3 are scale factors introduced so that h2du2 and h3du3 are differential lengths in the direction of increasing u2 and u3, respectively. Equation (J.23) may now be expressed as 1

R= i

σh2 h3 Δu2 Δu3

j

i

h1 Δu1

Δu1

= i

i

j

i

σh2 h3 h1 Δu2 Δu3

J 25 i

L u3 dS = h2h3du2du3

J

h3du3

u1

dl = h1du1

h2du2

u2

Cross section Figure J.8

Orthogonal curvilinear coordinates used to describe current flow in an arbitrary conductor. Source: [2]/McGraw-Hill.

Appendix J Thoughts on the Low-Frequency Return Current Distribution

since u1, u2, and u3 are independent variables owing to their mutual orthogonality. In the limit, we arrive at: L

du1

R=

J 26

σh2 h3 h1 du2 du3

0 S

This equation is clearly a function of the geometry of the conductor only. Equation (J.26) can be directly applied on symmetrical structures, such as a spherical section; however, at more complex geometries, a flux-mapping technique, which is essentially a graphical procedure for evaluating the above expression for resistance, can be applied [2]. For that purpose, it is beneficial to review the duality between J and D.

J.3

Duality Between J and D

The current density, J, and displacement flux density, D, are both linearly related to the electric field E in many materials.8 A consequence of this property is the existence of dual relationships between J and D. In a region where nonconservative fields are absent, the following equations apply for linear, isotropic materials: Conducting Media Dielectric Media ∇×E=0

∇×E=0

J = σE ∇ J =0

D = εE

J 27

∇ D=0

In a homogeneous material where ε and σ are constant, the following also applies: Conducting Media

Dielectric Media

∇× J =0

∇×D=0

J 28

which demonstrates that both J and D may be derived from a scalar potential; hence: Conducting Media

Dielectric Media

J = − ∇ϕ

D = − ∇ϕ

J 29

and in both cases, owing to the divergence relations, ∇2 ϕ = 0

J 30

The solution for J and D is uniquely determined by finding a scalar potential function, ϕ, that satisfies Laplace’s equation and any imposed boundary conditions. It is evident from Equations (J.27) through (J.29) that any solution for J can be transformed into a solution for D, and vice versa, by applying the following interchange of quantities (Figure J.9): J

D

σ

ε

J 31

L

Figure J.9 Duality between conductance and E-field for two arbitrary bodies. Source: [2]/McGraw-Hill.

Φ=0

Φ=V J or D 1 2 S

8 Most of the derivation in this section is derived from [2].

σ or є

1131

1132

Appendix J Thoughts on the Low-Frequency Return Current Distribution

This means that if a solution to a boundary-value problem in electrostatics is known, it is also the solution to a corresponding problem in steady current flow. This procedure is valid only if the boundary conditions are equivalent in both cases.

J.4

Application to Return Current Flow in a Ground Plane on a PCB

The discussion in the previous section,(particularly Equation (J.29), has demonstrated that the model for flux distribution between two opposite charges (in free space, for instance) is just as valid for the case of drive and load points on a PCB. At the contact (feed and load) points (or nodes) between the plane and the voltage source, the ideal condition no longer holds (see below) and the spatial distribution of J (and E) will be different from the ideal pattern. It would be reasonable to assume that a “transition region” on the plane, around the node/contact where the flux lines of J (or E) will move to the ideal shape/ path (Figure J.10a), as expected from an isolated charge (Figure J.10b). Note, in Figure J.10a the flux distribution immediately around the charge (or feed node). However, as we move far away from the feed node (or the two charges), the flux lines of the quasi-static current tend very quickly to approach a uniform distribution on the plane. They will not follow the “shortest path” but rather the path of least resistance, balancing length of the path, L and cross section, A (or width of the path, W). Applying Equation (J.18) to the case of return current from node α to node β on a PCB, the resistance offered by the conductor between nodes α and β is: E dl Rα

β

=

L

J 32 J da

A

where L is any line connecting nodes α and β, and A is any surface that divides the conductor in two parts laying nodes α and β in two opposite parts with respect to the surface, A (Figure J.11). Figure J.10 Electrical field (flux) between positive and negative charges (a) and of an isolated charge (b). (a) Two opposite charges (or feed and load nodes in near proximity). (b) Isolated point charge (or feed node). By saying “isolated feed node,” we understand that the feed and load nodes are sufficiently separated so as to have minimum local mutual interaction.

(a)

(b)

Partitioning surface A

Ground plane Node β

Zone of parallel current/ flux distribution

Node α

Signal feed node

Signal feed node Quasi-static return current path

Figure J.11 Illustration of current/flux distribution in a PCB ground plane (the zone of parallel, uniform current flux distribution is illustrated).

Appendix J Thoughts on the Low-Frequency Return Current Distribution

If the conductor is homogeneous and the E-field is uniform, then Equation (J.32) reduces to:

E 1y Y

E dl Rα

β

L

=

J 33

α2

(ε0 , μ0)

da

J

R2

A

α2

The assumption of a uniform field strictly implies that the nodes α and β cannot be point-like (see Figure J.10a vs b) but must be two equipotential surfaces, planes and parallel. Under these circumstances, the integral at the numerator in Equation (J.33) represents the distance, L, between nodes α and β and the integral at the denominator of Equation (J.33) the cross section of the conductor. Considering that E = ρJ

P

–Q2 (x 2, 0)

E1

α1

E 1x

R1

α1 +Q1 (x 1, 0)

X

Figure J.12 A total E-field computed from two charges +Q1 and −Q2 in the X–Y plane.

J 34

where ρ = 1/σ, and subsequently, similar to Equation (J.12): Rα

β

=ρ

L A

J 35

Equation (J.35) is, as well known, represents the resistance of any conductor homogeneous in the presence of a uniform field. Now, building upon the duality between J and D, as discussed in the previous section, an expression for the electric flux, D (recall that D = εE), between two isolated charges in a plane may provide a basis for approximating the current flux, J, since the flux of J is simply J = σE. The electrical flux distribution between two opposite charges in free space (or any linear homogeneous medium) is the cumulative effect of the flux distribution due to each single charge. In the following derivation, a general expression for the flux lines of E is computed on the same plane (say X–Y) in which the two charges lie.9 Assume two charges, +Q1 and −Q2, where +Q1 is at the point (x1,0) and −Q2 at (x2,0) on the X–Y plane. The total E-field (note this is a vector addition), ET = E1 + E2

J 36

is computed on the X–Y plane at an arbitrary point P(xP,yP) (Figure J.12). Assume a medium of ε0, μ0. The E-field at point P from the charge +Q1 and −Q2 is computed at the distances R1 and R2, respectively: R1 =

xP − x1

2

+ yP − 0

2

R2 =

xP − x2

2

+ yP − 0

2

J 37

and the angles α1 and α2 (see Figure J.12) are: yP − 0 xP − x1 yP − 0 α2 = arctan xP − x2 α1 = arctan

J 38

From which we derive: Q1

E1 = 4πε0

xP − x1

2

+ yP

2

Q2

E2 = 4πε0

xP − x2

2

+ yP

2

Q1

cos α1 x + 4πε0

xP − x1

2

+ yP

2

J 39

Q2

cos α2 x + 4πε0

xP − x2

2

+ yP

sin α1 y

2

sin α2 y

9 This derivation was carried out and provided courtesy of Prof. Antonio Orlandi, University of L’Aquila, Italy.

1133

1134

Appendix J Thoughts on the Low-Frequency Return Current Distribution

For any point (xP, yP), such that R1, R2 Q1

ETX = 4πε0

xP − x1

2

+ yP

2

+ yP

2

Q1

ETY = 4πε0

xP − x1

2

0, we therefore derive: Q2

cos α1 4πε0

xP − x2

2

+ yP

2

cos α2 x J 40

Q2

sin α1 + 4πε0

xP − x2

2

+ yP

2

sin α2 y

Arriving at: ET =

E 2T X + E 2T Y

J 41

And based on the relationship J = σE, we can now conclude that at any point, P in the X–Y plane, the surface current flux is10: J T = σ ET = σ

E 2T X + E2T Y

J 42

So, the equivalence between the flux of electrical field, E, and of the current density, J, has been demonstrated. However, what about the equivalence between the charges in free space (or any homogenous material) and the source-load case in the plane? Such an equivalence indeed exists, as can be observed from Equation (J.29), relating flux or current and potential, brought here again for convenience, Conducting Media

Dielectric Media

J = − ∇ϕ

D = − ∇ϕ

J 43

where, ϕ represents the electrical potential (also known as the Coulomb potential) arising from a point charge, Q, at a distance, R,11 from the charge is observed to be, ϕ=

Q 4πε0 R

J 44

Recall that the electric potential (also called the electric field potential, potential difference, and the electrostatic potential) is defined as the amount of work energy needed to move a unit of electric charge from a reference point to the specific point in an electric field. More precisely, it is the energy per unit charge for a test charge that is so small that the disturbance of the field under consideration is negligible. × 1012 This definition can also be extended to a circuit, rather than isolated charges in free space, whereby, the electric 1 potential difference is the measure of potential energy between two points in a circuit and is commonly referred 0.5 to as its “voltage drop.” Thus, when a voltage source is connected to a closed loop circuit, the voltage will pro0 duce a current (the equivalent of the “test charge”) flowing around the circuit. –0.5 The equivalence is self-evident, and can be illustrated graphically. For the two charges in free-space on the –1 2D plane X–Y, the electrical potential computed from 0.2 two charges +Q1 and −Q2 in the X–Y plane is depicted 0.1 0.2 in Figure J.13. 0.1 0 Now, the total electric field, E, and electric potential, ϕ, 0 –0.1 were computed in two different manners (Figure J.14): –0.1 –0.2 –0.2

Figure J.13 A graphic illustration of the electrical potential computed from two charges +Q1 and −Q2 in the X–Y plane. Source: Courtesy of Prof. Antonio Orlandi, University of L’Aquila, Italy.

• •

From the cumulative potential, ϕ, produced from both charges, based on E = −∇ϕ. From the cumulative fields, computed directly as E1 + E2.

10 This relationship holds, of course, in a homogenous medium, where σ is uniform across the plane. 11 Not to be confused with resistance, R.

Appendix J Thoughts on the Low-Frequency Return Current Distribution

Figure J.14 A graphic illustration of the total electric field, E, and electric potential, ϕ, from two charges +Q1 and −Q2 in the X–Y plane, computed in two different manners. (a) Computation from the electrical potentials, ϕ1 and ϕ2, arising from both charges. (b) Computation directly from the cumulative field arising from both charges. Source: Courtesy of Prof. Antonio Orlandi, University of L’Aquila, Italy.

0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 –0.2

–0.15

–0.1

–0.05

0

0.05

0.1

0.15

0.2

0.05

0.1

0.15

0.2

(a) 0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 –0.2

–0.15

–0.1

–0.05

0 (b)

If the conductor has a bidimensional symmetry (like a plane with a given thickness), then the cross section (that is equipotential for the previous assumptions) can be divided in multiple elementary “tubes” or filaments, the cross section of which is Atube < A and hence: Atube = A

J 45

containing the field flux lines12 (Figure J.15). All “filaments” exhibit a resistance larger than Rα β but, at the same time, being all filaments in parallel, the final resistance is always Rα β. As concluded from the above, it follows that under the assumption of homogeneous conductor and uniform field, the path of least resistance is the one expected: homogeneous distribution through the cross section. In conclusion, far from the nodes (that is to say in the part of the plane where the E-field is spatially uniform), an equivalence between isolated charges and a DC (or quasi-static-drive circuit nodes) is apparent. Closer to the nodes/contact points, it would 12 Compare this to the discussion earlier in this chapter.

1135

1136

Appendix J Thoughts on the Low-Frequency Return Current Distribution

be reasonable to conclude that the “charges in free-space” would serve as a valid quantitative approximation of the behavior of the E-field and subsequently, of the current, J.

Y

Z

β

J.5

Conclusions

a) At DC or very low frequencies, skin effect is not (well) developed; therefore, the current is uniform “far” from the discontinuities (such as the nodes/contact points) on the cross section (plane X–Z in Figure J.15) of the plane. On the plane itself (surface X–Y in Figure J.15), the spread of the current depends on the distance between the contact points/nodes. If the two points are very remotely spaced, the return current will virtually spread all across the plane; however, the closer the contact points are, the less will be the spread in the X–Y plane (Figure J.14). X Under this condition, close to the contact points, only numerical solution is possible because the solution (the spatial distribution) is a function of the form and placement Figure J.15 Elementary “tubes” of the contacts points/nodes; however, far from the contact points/nodes, the E-field or filaments of E or J. (and subsequently, the current J = σE) is uniform on the cross section (whether circular or rectangular). b) At higher frequencies, skin effect is well developed. A closed-form expression for conductors of circular cross section is known. However, for conductors of rectangular cross section, the return current follows the path of the “forward” current trace and approximate expressions exist and are presented in Chapter 2 and earlier in this appendix.

α

J.6

Simulation and Results

In order to illustrate the spreading of return current between two (feed and load) nodes on a PCB, a simulation was carried out by CST Microwave Studio.13 The model for the simulation is presented in Figure J.16. The width and length of the model were 1000 mils (1 in. or 25.4 mm, approximately) and 3000 mils (3 in. or 76.2 mm, approximately). The trace, 33.84 mils in width, was routed 20 mils above the ground plane to ensure loose coupling between the trace and the ground plane, i.e. that the presence of the plane has no effect on the return current distribution. As the model was carried out at very low frequencies, but not in DC, the main point was to ensure that the spacing was significantly greater than skin depth. The dielectric between the trace and the ground plane was set as FR4, which have a relative permittivity of εr = 4.3. The simulation was run in four frequencies:

•• ••

100 Hz 1 kHz 10 kHz 100 kHz Trace Feed node

84

33.

mil

20 mil il

0m

300

Dielectric (FR4), εr = 4.3 Load node 1000 mil

Ground plane

2D plot calculation point

Z 0 = 50Ω

13 All simulations and results are courtesy of Avraham (Avi) Cohen, Israel.

Figure J.16 Model for CST simulation of quasi-static return current on a PCB.

Appendix J Thoughts on the Low-Frequency Return Current Distribution

and with two materials used for the ground plane:

••

Aluminum (Al) Carbon fiber composite (CFC) material, assumed to have a resistivity of ρCFC ≈ 1000ρAl, e.g. 17 μΩ m, depending on layup of the composite plies14,15 [3, 4]

and for setting a basis for comparison only and observing the return current behavioral trend, an arbitrary intermediate (midvalue) resistivity between the above two. Results of the simulation are presented in both 3D (spatial distribution of the current density, J) for the two materials (Al and CFC) and 2D (current density at the structure’s midpoint) plots for the same two materials plus the mid-value material. The 3D results are presented in Figure J.17 for aluminum, and Figure J.18 for CFC.

A/m2 5500 4000 3000 2000 1000 0

Current-density (f = 100) [1] Orientation Component Frequency Phase Cross section Cutplane at X Maximum on plane (plot) Maximum (plot)

Outside Abs 100 Hz 0º A 0.000 mil 2234.87 A/m2 2411.96 A/m2

(a) A/m2 5500 4000 3000 2000 1000 0

Current-density (f = 1000) [1] Orientation Outside Component Abs Frequency 1000 Hz Phase 0º Cross section A Cutplane at X 0.000 mil Maximum on plane (plot) 14 469.1 A/m2 Maximum (plot) 15 981.9 A/m2

(b)

Figure J.17 3D (current density (J) distribution) CST simulation results for an aluminum ground plane. (a) F = 100 Hz. (b) F = 1 kHz. (c) F = 10 kHz. (d) F = 100 kHz.

14 Graphite exhibits directionality in its electrical properties, which accounts for the inhomogeneity and anisotropic nature of the carbon fibers in carbon fiber composites. This anisotropy makes the physical properties of these materials vary as a function of the number of fiber layups and their orientation, as well as with their fiber to epoxy resin ratio. Differences in fiber layups affect the resistivity of the overall material in particular directions. 15 The resistivity of carbon fiber reinforced polymer (CFRP) T300-class materials is 1000 times higher than that of aluminum.

1137

1138

Appendix J Thoughts on the Low-Frequency Return Current Distribution A/m2 5500 4000 3000 2000 1000 0

Current-density (f = 10000) [1] Orientation Outside Component Abs Frequency 10 000 Hz Phase 0º Cross section A Cutplane at X 0.000 mil Maximum on plane (plot) 72888 A/m2 Maximum (plot) 82 937.7 A/m2

(c) A/m2 5500 4000 3000 2000 1000 0

Current-density (f = 1e+5) [1] Orientation Outside Component Abs Frequency 1 00 000 Hz Phase 0º Cross section A Cutplane at X 0.000 mil Maximum on plane (plot) 300823 A/m2 Maximum (plot) 361499 A/m2

Figure J.17

(d)

(Continued)

The simulations present clearly the current distribution along the line, but the local distribution at near proximity to the nodes cannot be demonstrated due to the excessively high meshing required for obtaining significant result. This is of no significant consequence on the simulation, as the question at the basis of this appendix was the return current distribution along the line. The impact of skin effect is clearly evident for aluminum (Figure J.17). For F = 100 Hz, the current occupies pretty much the entire volume of the structure (careful observation can show some slightly higher distribution along the path, this will be much clearer in the 2D plots), while the effect of diminishing skin depth is quite evident as expected, with the increase of frequency from 1 to 100 kHz. Unlike for the case of aluminum, the impact of skin effect is virtually unobservable for CFC (Figure J.18). In the 3D plots, only in the case of F = 100 kHz, significant current distribution is observed. Note, however, that in both cases where current density distribution is observed, the striking fact is that the return current does not spread to occupy the entire return plane, but rather flows in a width, W, which is resistivity-dependent. The latter interesting observation is better illustrated in the 2D plots in Figure J.19. In these images, the upper curve is for aluminum, the middle, for the (arbitrary) intermediate resistivity, and the bottom, for CFC. Some qualitative conclusions may be drawn from the plots in Figure J.19: a) As expected, with the increase of frequency, return current density primarily converges beneath and about the trace (as expressed in Equation (J.1), brought here again for convenience):

Appendix J Thoughts on the Low-Frequency Return Current Distribution

J GP d ≈

I0 1 πh 1 + d h

2

A m

J 46

b) The lower the resistivity (ρAl < ρMid < ρCFC), the higher the “convergence” of the return current beneath the trace. This can be due to the fact that the “break frequency” between “low” and “high” depends on the ratio between resistance and inductive reactance of the circuit, occurring at16: Fc =

Ri Ri or ωc = 2πLi Li

J 47

Clearly, as resistivity drops, the knee frequency, FC (or ωC = 2πfC), drops as well, as observed by comparing the images in Figure J.19 (but also from Figures J.17 and J.18 to a lesser extent). A/m2 680 600 500 400 300 200 100 0

Current-density (f = 100) [1] Orientation Outside Component Abs Frequency 100 Hz Phase 0º Maximum (plot) 547.974 A/m2

(a)

A/m2 680 600 500 400 300 200 100 0

Current-density (f = 1000) [1] Orientation Outside Component Abs Frequency 1000 Hz Phase 0º 548.49 A/m2 Maximum (plot)

(b)

Figure J.18 3D (current density (J) distribution) CST simulation results for a carbon fiber composite (CFC). (a) F = 100 Hz. (b) F = 1 kHz. (c) F = 10 kHz. (d) F = 100 kHz.

16 See Chapter 2 for a detailed discussion of the “path of least impedance” principle for current return.

1139

1140

Appendix J Thoughts on the Low-Frequency Return Current Distribution A/m2 680 600 500 400 300 200 100 0

Current-density (f = 10 000) [1] Orientation Outside Component Abs Frequency 10 000 Hz Phase 0º Maximum (plot) 598.221 A/m2

(c)

A/m2 680 600 500 400 300 200 100 0

Current-density (f = 1e+5) [1] Orientation Outside Component Abs Frequency 1 00 000 Hz Phase 0º 2407.92 A/m2 Maximum (plot)

Figure J.18

(d)

(Continued)

c) Next, and maybe the most interesting of all (particularly at the very low frequencies, 100 Hz and below), the higher the resistivity (ρCFC > ρMid > ρAl), the wider the current distribution at any given frequency (see Figure J.19a). The implication is that at highly conductive current return paths, the return current tends to assume a sort of “bell-shaped” current distribution (see the top curve for aluminum), while higher resistivities still spread out significantly (actually, they too assume this “bell shape”) as the little “kink” in the plot for the intermediate value material (see the middle curve) shows. The “kink” is virtually not observed at all for the CFC simply due to scaling, but can be clearly seen in Figure J.19d. In conclusion, consistent with (b) above, the return current density, J, significantly diminishes with the increase of resistivity, owing to this “spreading.” In fact, in linear and homogenous materials, the relationship in Equation (J.34), brought here for convenience again, E = ρJ

J 48

holds. Since, in the macro scale, E = − ∇V

J 49

Appendix J Thoughts on the Low-Frequency Return Current Distribution

where the ∇ operator implies for a long and narrow path, where the return current is concentrated, say in the x direction (neglecting the y and z coordinates), ρ J = − ∇V ≈ −

∂V ∂x

J 50

As long as the structure is electrically small (which would be the case for all practical quasi-static cases), it can be assumed that the excitation potential difference, V, across the source and load nodes produces a fixed voltage gradient (in linear and homogenous materials), hence: ρJ ≈ −

Vi ℓ

J 51

10 000

Current-density...(Y) [alu] Current-density...(Y) [carbon] Current-density...(Y) [middle]

6000 4000 3000 2000 1000 600 400 300 200 100 –600

–400

–200

0 Y/mil

200

400

600

(a) 50 000

Current-density...(Y) [alu] Current-density...(Y) [carbon] Current-density...(Y) [middle]

30 000 20 000 10 000 7000 5000 3000 2000 1000 700 500 300 200 100 –600

–400

–200

0 Y/mil

200

400

600

(b) Figure J.19 2D (current density (J) distribution) CST simulation results for aluminum, carbon fiber composite (CFC), and an intermediateresistivity material. (a) F = 100 Hz. (b) F = 1 kHz. (c) F = 10 kHz. (d) F = 100 kHz.

1141

1142

Appendix J Thoughts on the Low-Frequency Return Current Distribution

1e+05

Current-density...(Y) [alu] Current-density...(Y) [carbon] Current-density...(Y) [middle]

50 000 30 000 20 000 10 000 5000 3000 2000 1000 500 300 200 100 –600

–400

–200

0 Y/mil

200

400

600

(c) 1e+06 4e+05 2e+05 1e+05 40 000 20 000 10 000 4000 2000 1000 400 200 100 –600

–400

–200

0 Y/mil

200

400

600

(d) Figure J.19

(Continued)

where Vi is the impressed voltage across the feed and load nodes and ℓ represents the total length of the path from feed to load nodes, resulting in: J≈−

Vi ρℓ

J 52

Note from the curves in Figure J.17a and Figure J.18b that the maximum current density in the plots were JAl = 82.94 kA/m2 and JCFC = 0.55 kA/m2, both at F = 100 Hz, respectively. Coupled with the qualitative and quantitative data from Figure J.19a, it is evident that the difference in current density is not only due to resistivity (JAl/JCFC ≈ 150) whereas the resistivity of CFC was assumed to be ρCFC = 1000 ρAl. The ratio, therefore, is predominantly due to the increased spreading in CFC compared to aluminum. d) Finally, in all the frequencies, even in the lowest used in the simulation (100 Hz), it is evident that the current does not assume the full extent of the return path width (y-axis) available in the plane (1000 mils total, in the model, see Figure J.16) and tends to converge into a smaller width. This width should not be significantly dependent on the height of the trace above the plane (for very low frequencies, DC and just slightly above), as it assumes loose coupling between the trace and the plane.

Appendix J Thoughts on the Low-Frequency Return Current Distribution

References 1 Johnson, H. and Graham, M. (1993). High Speed Digital Design, A Handbook of Black Magic. Upper Saddle River, NJ: Prentice-

Hall PTR. 2 Plonsey, R. and Collin, R.E. (1961). Principles and Applications of Electromagnetic Fields. McGraw-Hill Book Company, Inc. 3 Abid, R. (2015). Electrical characterisation of aerospace grade carbon-fibre-reinforced polymers. PhD thesis. Cardiff School of

Engineering (December 2015). 4 Zhao, Q., Zhang, K., Zhu, S. et al. (2019). Review on the electrical resistance/conductivity of carbon fiber reinforced polymer.

Applied Sciences 9 (11): 2390. https://doi.org/10.3390/app9112390. (11 June 2019).

1143

1145

Appendix K Overview of S Parameters In many places throughout this book, particularly in Chapter 13, Scattering parameters or, in short, S parameters are used to describe the performance of circuits and systems. This appendix provides a short overview of S parameters and their applications to the extent necessary for the understanding of the material included in this book. For a more detailed understanding of S parameters and the theoretical background of their derivation, the reader is encouraged to refer to the many resources available on the topic.

K.1

Background

Historically, an electrical network would have comprised a “black box” containing various interconnected basic electrical circuit components or lumped elements such as resistors, capacitors, inductors, and transistors. Elementary circuit theory provides many methods for describing complex electronic networks. Those methods, however, best describe DC and lowfrequency circuits. They fall short when wavelengths of the signals of interest shrink to become comparable to the physical dimensions of the circuit of interest. To better characterize high-frequency circuits, scattering parameters or S parameters are commonly used. S parameters constitute properties of electrical, electronic and communication systems engineering for describing the electrical behavior of typically high-frequency (electrically large) linear electrical networks when undergoing various steady-state stimuli by small signals. Many electrical properties of networks or components may be expressed using S parameters such as gain, return loss, voltage standing wave ratio (VSWR), network stability, and reflection coefficient. The term “scattering,” as related to electromagnetic wave propagation, commonly refers to the effect observed when a plane electromagnetic wave is incident on an obstruction or passes across dissimilar dielectric media. In the context of S parameters, scattering refers to the way in which traveling current and voltage waveforms in a transmission line are affected as they interact with discontinuities along the transmission line, for instance due to the presence of a lumped electrical network. Such networks may include many typical communication system components or “blocks” such as amplifiers, attenuators, filters, and couplers provided they operate under linear and defined conditions. S parameters change with the frequency, thus frequency dependence must be included for any S-parameter characterization of a network, in addition to its characteristic impedance or system impedance. S parameters are readily represented in matrix form and obey the rules of matrix algebra [1, 2].

K.2

Ports and Interaction Matrices

The external behavior of any “black box” can be predicted without regard for its contents. The black box could contain anything, ranging from a resistor, a transmission line, or an integrated circuit (Figure K.1). Network analysis can be significantly simplified when circuit nodes are grouped into appropriate pairs, yielding the concept of ports. In fact, knowledge of the internal circuit topology is not required for utilizing the port concept. An electrical network or “black box” to be characterized using S parameters may have any number, N, of ports. Ports are the points at which electrical currents either enter or exit the network. Sometimes these are referred to as pairs of “terminals,” thus a two-port network is equivalent to a four-terminal network. Figure K.1 depicts a simple network with just two ports. Any linear two-port (and multi-port) network (“black box”) can thus be characterized by a number of equivalent circuit parameters associated with interactions occurring at each of its ports so as to produce a simple matrix representation of the internal circuitry, such as their transfer matrix, impedance matrix, admittance matrix, and scattering matrix. Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

1146

Appendix K Overview of S Parameters

Port 1

“Black box”

Port 2

Figure K.1 Concept of a “black box” representation and its associated ports.

I1

I2

+ V1

+ Port 1

Port 2

Two-port network

V2

–

–

A network may have any number of ports. A two-port network can be represented by a 2 × 2 matrix. In general, an N-port network having N pairs of nodes can similarly be represented by an N × N matrix. Figure K.2 depicts a typical two-port network. All interaction matrices relate the signal incident upon a port of a network or “black box” to that leaving from each port. With an RF signal incident on one port, a fraction of the signal bounces back out of that port whereas another portion of it scatters and exits other ports (possibly even amplified) while some of it is dissipated as heat or is emitted as electromagnetic radiation. Power, voltage, and current can be considered to be in the form of waves travelling in both directions (Figure K.3). The transfer matrix, also known as the ABCD matrix, relates the voltage and current at port 1 to those at port 2, whereas the impedance matrix relates the two voltages V1, V2 to the two currents I1, I21: a) Transfer matrix V1 I1

Figure K.2 Representation of a two-port network.

V1 V2 Port 2

“Black box”

Dissipated energy (e.g. heat) Figure K.3 A fraction of the signal incident at port 1 reflects back out of this port and another portion of the signal exits through other ports (e.g. port 2).

V2 I2

K1

=

Z 11 Z 21

Z 12 Z 22

I1 − I2

K2

Thus, the transfer (T) and impedance (Z) matrices for two-port networks are the 2 × 2 matrices:

Transmitted wave

Reflected wave

A B C D

b) Impedance matrix

Incident wave

Port 1

=

T=

A

B

C

D

Z=

Z 11

Z 12

Z 21

Z 22

K3

The admittance matrix is simply the inverse of the impedance matrix, Y = Z−1.

K.3

The Scattering Matrix and S Parameters

S parameters are members of a family of similar impedance or admittance two-port parameters used in two-port theory, such as ABCD, Z, and Y parameters. Analogous to the Y or Z parameter, they describe the performance of a two-port completely. They differ from these, however, in the sense that S parameters do not make use open circuit (O.C.) or short circuit (S.C.) conditions to characterize a linear electrical network but rather relate to the traveling waves that are incident, scattered or reflected when a two-port network is imbedded into a transmission line of a certain characteristic impedance, Z0. Furthermore, the waves’ quantities are expressed in terms of power and can be interpreted in terms of normalized voltage or current amplitudes. S parameters are conceptually simple, analytically convenient, and capable of providing detailed insight into a measurement and modeling problem. Still, it must be kept in mind that similar to all other two-port parameters, S parameters are linear by default, i.e. they represent the linear behavior of the two-port.

K.3.1

The Scattering (S) Matrix

The scattering (S) matrix describing an N-port network contains N2 elements or S parameter coefficients, each representing a possible input–output interaction. The number of rows and columns in an S-matrix is equal to the number of ports. For the Sparameter subscripts “ij,” “j” stands for the excited port (the input port) and “i” denotes the output port. 1 In the figure, I2 flows out of port 2, and hence −I2 flows into it. In the usual convention, both currents I1, I2 are taken to flow into their respective ports.

Appendix K Overview of S Parameters

Figure K.4 Representation of an incident and reflected wave in a two port network.

I2

I1 a1 b1

+ V1

+ Port 1

–

Two-port network

Port 2

V2 –

b2 a2

At each frequency, each element or S parameter is expressed as a unitless complex number, representing magnitude and angle, or amplitude and phase, commonly presented in polar form. When stated in logarithmic fashion, the magnitude of the S parameter is typically expressed in decibels (dB). The scattering (S) matrix relates the scattered waves b1, b2 to the incident waves a1, a2 (Figure K.4): b1 b2

=

S11

S12

a1

S21

S22

a2

K4

Thus, the scattering (S) matrix for a two-port network is the 2 × 2 matrix: S=

S11 S21

S12 S22

K5

The S-parameter matrix for the two-port network is probably the most common and it serves as the basic building block for generating the higher order matrices for larger networks. Parameters along the leading diagonal of the S-matrix, S11 and S22, are referred to as “reflection coefficients” because they refer to the reflection occurring at one port only. Off-diagonal S parameters, S12 and S21, are referred to as “transmission coefficients” because they refer to what happens from one port to another. The normalized traveling incident (applied) power waves for each port are designated by the letter an, while the normalized reflected power wave is designed by bn where n is the port number of the network. These can be expressed in general form as: 1 V n + Z0 I n 2 Z0 1 bn = V n − Z0I n 2 Z0 an =

K6

In a two-port system, the traveling wave variables a1, b1 at port 1 and a2, b2 at port 2 are defined in terms of the port voltages and currents, V1, I1 and V2, I2 and a real-valued positive reference impedance Z0 as follows: V 1 + Z0 I 1 2 Z0 V 1 − Z0 I 1 b1 = 2 Z0

a1 =

V 2 + Z0I 2 2 Z0 V 2 + Z0I 2 b2 = 2 Z0

a2 =

K7

The definitions at port 2 appear different from those at port 1, but they are actually the same if expressed in terms of the incoming current −I2: V 2 − Z0 I 2 V 2 + Z0 − I 2 = 2 Z0 2 Z0 V 2 + Z0 I 2 V 2 − Z0 − I 2 = b2 = 2 Z0 2 Z0

a2 =

K8

Similar to the T and Z parameters, S parameters are frequency-dependent, so when looking at the formulae for S parameters, it is important to note that frequency dependence is implied (even if not explicitly written). For this reason, S parameters are often called complex scattering parameters.

K.3.2

S21 or “Forward Transmission Gain/Loss”

S21 refers to the signal exiting at port 2 for the signal incident at port 1 expressed as the ratio of the two waves, b2 and a1 (Figure K.5): S21 =

b2 a1

= a2 = 0

Transmitted power and port 2 Incident power and port 1

K9

1147

1148

Appendix K Overview of S Parameters

Port 1

Port 2

“Black box”

Incident wave, a1

Transmitted wave, b2

Figure K.5 Illustration of S21 or “forward transmission gain/loss.”

The greatest value of S21 to a circuit or system designer is to indicate how much frequency-dependent forward transmission gain or loss may be expected at a given frequency. The plot of the magnitude of S21 versus frequency allows a straightforward comparison of lossy structures. For a two-port network, S21 represents the complex linear gain, G, i.e.: G = S21

K 10

S21 therefore corresponds to linear ratio of the output voltage divided by the input voltage, all values expressed as complex quantities. The magnitude is given in linear form by: G = S21

K 11

The scalar logarithmic (decibel or dB) expression for gain (g) is more commonly used than the scalar linear gain, and is expressed as: g = 20 log 10 S21 dB

K 12

where g > 0 is normally understood to represent “gain,” while g < 0 is interpreted as “negative gain” or more commonly as “loss” equivalent to its magnitude in dB.

S11 or “Input Return Loss”

K.3.3

S11 refers to the signal reflected at port 1 for the signal incident at port 1 expressed as the ratio of the two waves, b1 and a1 (Figure K.6): S11 =

b1 a1

= a2 = 0

Reflected power and port 1 Incident power and port 1

K 13

Engineers most often use S11 to compare the quality of electrically short structures that constitute impedance discontinuities, such as connectors, vias, etc. When designing a transmission path, a lower return loss is preferable, because it indicates that less energy is reflected due to impedance mismatches and their resultant discontinuities to the energy flow. Incident wave, Input return loss (RLin) is a scalar measure of how close the a1 actual input impedance of the network is to the nominal system impedance value and, when expressed in logarithmic magnitude, is given by: Port 1

“Black box”

Port 2

RLin = 20 log 10 S11 dB

By definition, return loss is a positive scalar quantity implying the two pairs of magnitude (|) symbols.

Reflected wave, b1 Figure K.6 Illustration of S11 or “input return loss.”

Incident wave, a2

Port 1

K 14

“Black box”

K.3.4

S22 or “Output Return Loss”

The output return loss (RLout) has a similar definition to the input return loss but applies to the output port (port 2) instead of the input port and is expressed as the ratio of the two waves, b2 and a2 (Figure K.7):

Port 2

S22 = Reflected wave, b2 Figure K.7 Illustration of S22 or “output return loss.”

b2 a2

= a1 = 0

Reflected power and port 2 Incident power and port 2

K 15

When expressed in logarithmic magnitude, the output return loss is given by: RLout = 20 log 10 S22 dB

K 16

Appendix K Overview of S Parameters

K.3.5

S12 or “Reverse Gain and Reverse Isolation”

S12 refers to the signal exiting at port 1 for the signal incident at port 2 expressed as the ratio of the two waves, b1 and a2 (Figure K.8): S12 =

b1 a2

= a1 = 0

Transmitted power and port 1 Incident power and port 2

Port 1

“Black box”

Port 2

K 17 Transmitted wave,

Incident wave,

a2 The greatest value of S21 to a circuit or system designer is to indicate b1 how much frequency-dependent forward transmission gain or loss may be expected at a given frequency. The plot of the magnitude of Figure K.8 Illustration of S12 or “reverse gain/isolation.” S21 versus frequency allows a straightforward comparison of lossy structures. When expressed in logarithmic magnitude, the reverse gain is given by:

grev = 20 log 10 S12 dB

K 18

Often this expression will be used to represent reverse isolation (Irev) in which case it becomes a positive quantity equal to the magnitude of grev and the expression becomes: I rev = grev = 20 log 10 S12 dB

K.3.6

K 19

Effect of Reference Impedance

Reference impedance is an important concept for understanding and using S parameters. In contrast to equations involving port voltages and currents, scattering equations are defined by a set of (in principle) arbitrary reference loads, which is very useful in many applications. Usually, S21, in particular, is simply stated arbitrarily in dB terms. However, to be more precise, it should be stated that “S21 is stated in dB when impedance, Z (Ω), is used as reference impedance.” Since the reference impedance is typically 50 Ω, the abbreviated expression can be used. Still, it is important to keep in mind that the S parameter is a relative value depending on a certain reference value. In other words, the reference impedance is always necessary for acquiring S parameters (by measurements or by extraction though simulation). The following clarifies the meaning of “reference” taking only the 1-port S parameter (i.e. reflection coefficient, Γ) as an example. In general, reference loads defined by finite impedances are termination conditions milder than the shorts and open circuits defining impedance, admittance, hybrid, and chain equations. As a result, the conditions for the existence of the scattering equations (i.e. for the existence of the solution of the network of Figure K.9) are weaker than the conditions for the existence of the equations involving port voltages and currents. The port voltages of the network in Figure K.9 lead to the B port voltages and hence to the scattering equations for the reference impedances Zr1 and Zr2. In particular, S defined by a set of strictly positive reference resistances exists for any passive n-port [3]. Scattering equations, therefore, can handle a larger class of n-port elements. Of course, the reference impedance of Equation (K.6) can be also complex and frequency dependent; however, this general case greatly complicates the analysis and is out of the scope of this Appendix, and the discussion herein is restricted to real positive constant reference impedances (i.e. to reference resistors). The reference impedance values can be exploited to obtain scattering functions defined by reference loads closer to the operating load of the n-port element. This can be beneficial in measurement and modeling applications. In fact, even if any characteristic matrix can be used to predict the responses of the nport to its actual loads, there are practical limitations for matrices affected by errors. If the responses of interest are defined by loads significantly deviating from those defining Zr2 Zr1 the characteristic matrix available, large errors may occur. Two-port network V1 V2 This problem can be best visualized by considering the poles + 2A2 +– of the characteristic matrix and those of the sought responses. 2A1 – If the two sets of poles are very different, the limited accuracy of the characteristic matrix will lead to large inaccuracies in B1 = V1 – A1 the prediction of the new set of poles. B2 = V2 – A2 In order to cope with different sets of reference impedances, it is useful to compute the scattering matrix S of a reference impedance matrix Z r from the matrix S that Figure K.9 Network defining the scattering responses for a twoport element network. Source: Adapted from Maio [3]. holds for Zr.

1149

1150

Appendix K Overview of S Parameters

Consider the equation set [3], V =A +B

K 20

I = Yr A − B to express the port voltages and currents for the port voltages defined by: Z = Yr

−1

K 21

It follows that the port voltages defined by Zr are given by 2A = V + Z r I = A + B + Z r Y r A − B 2B = V − Z r I = A + B − Z r Y r A − B

K 22

which may also be expressed as, 2A = 1 + ζ A + 1 − ζ B

K 23

2B = 1 − ζ A + 1 + ζ B where ζ represents the diagonal matrix ZrY . When these expressions are substituted into the known scattering relation,

K 24

B = SA S may be obtained: S = 1 + ζ −S 1−ζ

−1

S 1 + ζ − 1−ζ

K 25

Assuming Zrk = Zr and Z rk for any k, then S reduces to: S = 1 − ΓS

−1

S − Γ1

K 26

where Γ=

Z − Zr Z + Zr

K 27

represents the reflection coefficient of Z r with respect to Zr. For example, assume there are two resistors, 50 Ω and 200 Ω. When Z = 50 Ω is substituted into the reflection coefficient using the reference impedance, Zr = 50 Ω, we derive Γ = 0. Similarly, with Z = 200 Ω, Γ = 0.6. If the reference impedance of Zr = 200 Ω is used, we obtain Γ = −0.6 for Zr = 50 Ω and Γ = 0 for Zr = 200 Ω. In summary, no reflection occurs from the 50 Ω resistor when the reference impedance is 50 Ω (i.e. matched load and Γ = 0), and no reflection occurs from the 200 Ω resistor when the reference impedance is 200 Ω. It follows that the reflection coefficient is a relative value that varies depending on conditions. The reference impedance is the reference value used for calculating this relative value. Devices other than one-port can be similarly considered, but require more complex computations. The reference value can be modified. For instance, assume that you have the S parameter already determined for Zr = 50 Ω, thus it is possible to transform it to a different S parameter using a reference impedance other than 50 Ω.2 Computation is difficult, but those can be extracted by means of 3D high-frequency field simulations.

K.4

Characteristic Values of S Parameters

The magnitude of S11 and S22 is always less than 1. Otherwise, it would represent a negative Ohmic value. On the other hand, the magnitude of S21 and S12 can exceed the value of 1 in the case of active amplification. Also, S21 and S12 can be positive or negative. If they are negative, this implies the existence of a phase shift. Table K.1 summarizes the interpretation of the different values of the S parameters:

2 Knowledge of all original S parameters (i.e. S11, S21, S12, and S22) is necessary even when computation of S21 only is desired.

Appendix K Overview of S Parameters

Table K.1 Characteristic values of S parameters. S11 and S22

Interpretation

−1

Incident voltage wave is reflected and inverted (Load=Short circuit, ZL = 0 Ω)

0

Impedance matching; No reflections (matched load, ZL = Z0) Incident voltage wave is reflected (Load = Open circuit, ZL = ∞ Ω)

+1 S21 and S12

Interpretation

0

No signal transmission

0 … +1

Input signal is damped in the Z0 environment

+1

Unity gain signal transmission in the Z0 environment

>+1

Input signal is amplified in the Z0 environment

K.5

S Parameters in Loss-Free and Lossy Networks

K.5.1

The Loss-Free Network

A loss-free network is one which does not dissipate any power; therefore, the sum of the incident power at all ports is equal to the sum of the reflected power at all ports, i.e.: an 2 = n

bn

2

K 28

n

This implies that the S-matrix is unitary, or: S

H

S = I

K 29

where (S)H is the conjugate transpose of (S) and (I) is the identity matrix.

K.5.2

Lossy Networks

A lossy passive network is one in which the sum of the incident power at all ports is greater than the sum of the reflected power at all ports. It therefore dissipates power, thus: an

2

n

bn

2

bn

2

K 30

n

In this case an 2 > n

n

K31

and S

K.5.3

H

S ≤ I

Insertion Loss

Insertion Loss (IL), usually also represented in dB, is given by: IL = − 10 log 10

S21 2 1 − S11

2

dB

K 32

Since insertion loss is, by definition, a loss (or, negative gain), the leading negative sign is often neglected. Insertion loss is commonly confused with g (above). The difference between the two is that g penalizes the network for mismatch at the input, while insertion loss, IL, is not a function of the input or source impedance. This point can be further made clear using the following expressions: g = 20 log 10 Pout Pav IL = 20 log 10 Pout Pin

K 33

where Pav represents the power available from the source, whereas Pin stands for the power incident into port 1 of the network.

1151

1152

Appendix K Overview of S Parameters

K.5.4

Radi/Figure/ciation Loss

In networks where power is “lost” in the form of radiated emissions, the radiation loss, LR, can be expressed using S11 and S12, respectively (note that S11 and S12 are expressed in their linear, non-dB, values): LR = 1 − S11 2 − S21

2

K 34

This expression implies that the RF energy “lost” to the environment is the fraction of the incident that is not transmitted forward into the network (S12) or reflected at the input port (S11). This represents a situation which differs from a closed lossless system, in which the total combination of reflection coefficient.

K.5.5

Mismatch Loss

Mismatch loss, ML, is the ratio of power delivered to power available, and is a simple function of reflection coefficient. The formula for mismatch loss is simply: ML = 1 − Γ 2

K 35

The absolute value of Γ is typically assigned to Greek letter rho (ρ), thus yielding a simpler, alternative expression: ML = 1 − ρ2

K.5.6

K 36

Loss Factor

The concept of “loss factor,” or LF, in short, is useful in determining if an S-parameter measurement of a passive device is good. The forward (FLF) and reverse (RLF) loss factors are calculated from passive component S parameters as [4]: a) Forward loss factor: FLF = 1 − S11 2 − S21

2

K 37

2

K 38

b) Reverse loss factor: RLF = 1 − S22 2 − S12

Through these definitions, the loss factors are seen to equal the difference between a normalized input power and the power that is reflected and transmitted to the input and output ports, respectively (power loss may result from conductor, dielectric, and radiation loss mechanisms). For reciprocal devices S21 = S12, the differences between the forward and reverse loss factor occur due to differences in |S11| and |S22|. As shown above, for ideal lossless components, the magnitudes of S11 and S22 are equal, but may deviate from each other when loss is present. For passive components such as capacitors, inductors, and resistors (and diodes), the electrical behavior is most often symmetrical (i.e. S11 = S22), hence the difference in the forward and reverse loss should be negligible. Significant deviations in the forward and reverse loss can be observed when radiation occurs from a component, particularly observed in inductors. The loss factor is, hence, an indication of the amount of power “disappearing” in a network, through resistive loss or radiation.

K.5.7

Efficiency Factor

The efficiency factor seems to be a more useful quantity for evaluating passive parts, compared to the “loss factor” [5] defined as: a) Forward efficiency factor: FEF = S11 2 + S21

2

K 39

b) Reverse efficiency factor: REF = S22 2 + S12

2

K 40

When converted to decibels, a “perfect” circuit has an efficiency factor of 0 dB, while a circuit that loses 20% of its power has an efficiency factor of −1 dB, etc. This parameter is indicative, therefore, of how “lossless” a circuit would be if it were perfectly impedance-matched.

Appendix K Overview of S Parameters

K.6

Mixed Mode S Parameters

K.6.1

Mode Conversion on a Differential Pair

Differential signaling (differential circuit topology) is widely and commonly used in contemporary high-speed digital applications3 (Figure K.10). However, with even a small amount of asymmetry in differential transmission lines (due to the nonideal nature of practical lines), will produce a common signal that propagates through the circuit. This asymmetry (Figure K.11) can be caused by any physical feature that is on one line of the differential pair and not the other line, including solder pads, jags, bends, and digs. This mode conversion is a source of EMI emission and susceptibility. Mode conversion analysis provides the designer with that insight so that EM problems can be resolved early in the design stage. A differential transmission system is a system that supports primarily two propagation modes such as the differential mode (related to the odd mode) and common mode (related to the even mode).4 Typical single-ended devices have a single input port and a single output port. Signals on the input and output ports are referenced to ground. On the other hand, balanced devices have two leads on either the input, the output, or both. The signal of interest is the difference and average of the two input or output lines, not referenced to ground (see Figure K.11). The S-parameter matrix for this system needs to be handled according to the modes, which is referred to as a mixed-mode Sparameter matrix (or modal S-parameter matrix). The normal S parameter (referred to as a single-ended S parameter or nodal S parameter) indicates the response for each port. On the other hand, a mixed-mode S parameter indicates the response for the sum of two signals (common mode) or the response for the difference of two signals (differential mode). A mixed-mode S parameter can be obtained from a single-ended S parameter (Figure K.12) [6]. The expressions for computation of the mixed-mode S parameter are quite complex; however, those can be extracted by means of 3D high-frequency field simulations. Mixed mode responses are represented by differential S parameters. The format of the parameter notation “Scdij,” where “S” stands for S parameter, “i” represents the response mode (differential or common), “j” represents the stimulus mode (differential or common), while “i” and “j” stand for the response port number and the stimulus port number, respectively. In particular, the mixed-mode S parameters have the following notations (see Figure K.12): Sccij: Common mode response Sddij: Differential mode response Sdcij, Scdij: Mode conversion between differential mode and common mode The mode conversion (Sdcij or Scdij) can be used as indication of the extent of system imbalance. If the device is well balanced, the mode conversion should be zero, which means that each mode is independent. The longitudinal conversion loss, or LCL,5 can be calculated using the S parameter as follows [3]: a) In a two-port circuit: LCL1 = − 20 log 2Sdc = − 20 log S11 − S21 + S12 − S22

K 41

b) In a four-port circuit: LCL2 = − 20 log 2Sdc11 = − 20 log S11 − S31 + S13 − S33

Figure K.10

K 42

Illustration of transmitting information with two complementary signals sent on a differential pair.

3 The benefits of differential signaling were discussed in detail in Chapter 2. 4 Refer to Chapter 2 for discussion of even and odd propagation modes and their association with differential and common mode signaling. 5 In ITU-T Recommendation G.117-1996, “Transmission Aspects of Unbalance about Earth,” LCL is defined for two-port and four-port circuits. (In the Standard, two-port and four-port circuits are referred to as one-port and two-port, respectively.) To avoid confusion, LCLs for two-port and four-port circuits are referred to as LCL1 and LCL2, respectively. LCL2 is equal to LCL1 at the nontarget port terminated with reference impedance. Since LCL uses the signal source voltage as its reference, the difference between LCL and S parameter is 6 dB.

1153

1154

Appendix K Overview of S Parameters

Gain = 1

Gain = 1 CM

DM

Fully balanced

Fully balanced CM

CM + DM

Gain = 1

Gain = 1

DM

CM

Balanced to single ended

CM

(a) Figure K.11

(b)

Illustration of mode conversion in a differential (input) circuit. (a) Ideal balanced circuits. (b) Practical balanced circuit.

1 S= 3

C1 S′ = D1

Balanced to single ended

CM + DM

S11 S21

S12 S22

S13 S23

S14 S24

S31

S32

S33

S34

S41

S42

S43

S44

Scc11

Scc12

Scd13 Scd14

Scc21

Scc22

Scd23 Scd24

Sdc31 Sdc32

Sdd33 Sdd34

Sdc41 Sdc42

Sdd43 Sdd44

2

4

C2

D2

Figure K.12 Mixed-mode S parameter can be derived from single-ended S parameter.

The 16 S parameters that are obtained by fully characterizing a differential network (or interconnect) can be categorized into four stimulus/response quadrants. In order to interpret the large amount of data in the differential parameter matrix, it is helpful to analyze one quadrant at a time (Figure K.13). a) The first quadrant is defined as the upper left four parameters describing the differential stimulus and differential response characteristics of the device under test (Sddij, Sdcij), representative of the actual mode of operation in most high-speed differential networks. This quadrant is thus the most useful quadrant. It includes input differential return loss (Sdd11), input differential insertion loss (Sdd21), output differential return loss (Sdd22), and output differential insertion loss (Sdd12). b) The second and third quadrants are the upper right and lower left four parameters, respectively (Scdij, Sdcij), also referred to as the differential quadrants as they fully characterize any mode conversion occurring in the device under test, whether it is common-to-differential conversion (EMI susceptibility) or differential-to-common conversion (EMI emission).

Appendix K Overview of S Parameters Diff → Diff

Comm → Diff Differential- Common-mode stimulus mode stimulus Logical Logical Port 1 Port 2

Differential-mode response

Differential-mode response Common-mode response

Logical Port 1 Logical Port 2 Logical Port 1 Logical Port 2

Diff → Comm

Mode-conversion EMI interference/emissions

Figure K.13

Logical Logical Port 1 Port 2

Scc11 Scc21

Scc12 Scc22

Scd13 Scd23

Scd14 Scd24

Sdc31 Sdc41

Sdc32 Sdc42

Sdd33 Sdd43

Sdd34 Sdd44

Mode-conversion EMI susceptibility/immunity

Comm → Comm

Common-mode response

The 16 S parameters of a differential interconnect can be categorized into four stimulus/response quadrants.

c) The fourth quadrant is the lower right four parameters and describes the performance characteristics of the common signal propagating through the device under test (Sccij, Sccij). If the device is properly balanced, minimal mode conversion should be observed and the fourth quadrant data is of little concern. However, if any mode conversion occurs due to network imbalance, the fourth quadrant will describe the nature of this common signal.

References 1 Paul, C.R. (2006). Introduction to Electromagnetic Compatibility, 2e. Wiley-Interscience: New York. 2 Wikipedia, the Free Encyclopedia. https://en.wikipedia.org/wiki/Scattering_parameters. 3 Maio, I.A. (2008). A primer on scattering parameters, part I: definitions and properties. The Electromagnetic Society Newsletter,

Spring. 4 Capwell, J., Weller, T., Markell, D., and Dunleavy, L. (2004). Automation and real-time verification of passive component S-

parameter measurements using loss factor calculations. Microwave Journal 47 (3): 82. (27 March 2004). 5 Microwave101 Encyclopedia. https://www.microwaves101.com/encyclopedias/mismatch-loss-etc. (accessed 8 October 2022). 6 Fujishiro, Y. (2011). Taking Advantage of S-Parameter, TDK EMC Technology, Basic Section. TDK Corporation Application Center.

1155

1157

Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Dogmatism and skepticism are both, in a sense, absolute philosophies; one is certain of knowing, the other of not knowing. What philosophy should dissipate is certainty, whether of knowledge or ignorance. — Bertrand Russell Chapter 14 provided several methods for ground plane interference noise susceptibility/immunity testing. A skeptic might ask, “whence were those requirements derived, and so they actually have a practical basis?”

Disclaimer This appendix should be considered as an example analysis, portraying the process and considerations to be taken in such an analysis. It does not claim to be accurate, and is definitely not suggested to be equivalent to numerical/computational techniques, but intends to provide a “quick look” insight into potential problems that may be further investigated later on. As quoted from Dr. Eric Bogatin: Sometimes an okay answer NOW! is more important than a good answer late. There are occasions when an estimate that you can do quickly can indicate how close to a problem you may be. If you are far from a problem area, move on to a more important problem. If the estimate says you are close, then it can justify spending the extra time and expense to get a better answer. You may never have all the information you need to make a good decision. Use what you know, use your judgment, and consider a later, follow-on investigation to get the additional important information for a better decision. This appendix provides a sample (and rough) analysis of one of the requirements, namely, “Conducted Susceptibility, Ground Plane Injection, Spike /Transient.”

L.1

Scenario

As the “Conducted Susceptibility, Ground Plane Injection, Spike/Transient” is derived from spacecraft EMC standards (e.g. AIAA-S-121A [1]), a hypothetical example will be presented for a spacecraft. Figure L.1, for instance, provides an illustration of the grounding scheme of a large and complex spacecraft (Cassini1). It is quite evident that the grounding scheme includes such systems as command, control, communication and Navigation (C3N) systems are present, in addition to sensitive instrumentation and pyrotechnic systems. Pyrotechnic systems are typically activated in a “line-to-line” mode (the EIED, or electrically initiated explosive device, is commonly “floating”) such as illustrated in Figure L.22 [3]. However, during the process of firing, often a short-circuit to chassis occurs, which result in high firing currents, in the order of 10–20 A, flowing through the vehicle chassis back to the power source (e.g. batteries), which are often grounded to the vehicle chassis also, elsewhere in the platform. 1 Cassini was the fourth space probe to visit Saturn and the first to enter its orbit, where it stayed from 2004 to 2017. 2 This is a typical circuit for purpose of illustration of the various parts of the electroexplosive subsystem and does not reflect an actual design. Contemporary firing circuits may differ from the scheme presented here; however, the principles pertaining to the discussion in this appendix still apply, in particular, the “line-to-line” firing scheme. Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

1158

Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Bay 7 RSP REU A/B

Bay 6

Bay 5

RFS-Elec.

RRS

Antenna ass embly

RFSTWTA

HFR 73.4 MSC PA ME-2 AN

MS C 6.1

ME-1 DIG.

2.1 73.1 PPS

RTG 1

LP

IN MS

LP PA

30 VDC 2k

50 K 4.1

2 k 0.1μF

RTG 2

BUS TLM IMBAL SENS

73.3

73.2

RPWS 74.0 LEMMS

INCA

MI MI ELEC

S/C LOADS

30 VDC RTN

76.0 CHEMS

UN SW LOADS

50 K

UVIS

CAPS

84.0

82.0

RTG 3 Note: Awitching simplified

50 K

PMS REU A/B

SW LOADS

CDA

79.0

10.0 PWR control and distrib.

Separation plane PROBE

SED PPS REU A/B

PSA-A

PSA-B

80.1

80.2

RUSO

RFE 80.5

80.4

RADAR (RFES)

RADAR (DSS)

80.3

PYRO PSU-A

Mult. internal chassis connections

PYRO PSU-B

CIRS (elec)

CIRS (elec)

5K 81.1 EU A/B

81.1

81.2

4.2 Mult. internal chassis connections

CDS

SSR

MAG

35.0

Subsystem chassis Circuit common ground tree

Subsystem

WAC (elec)

WAG (camera)

6.0 KE Y:

89.0 NAC (camera)

NAC (elec)

36.1

36.2

VIMS-I R (Sig Proc. Elec)

VIMS (Main. Elec)

VIMS-V (Vischanl/Elec)

Circuit common to subchassis (external single point ground) Subchassis to S/C electrical bond

XXX S/C chassis

37.1

37.2

Note: Except for power, pyro, and REU signal returns, this drawing indicates in which assemblies each ground tree exixts.

Ground tree no.

Figure L.1

Grounding scheme (partial) of a large and complex spacecraft (Cassini). Source: NASA-HDBK-4001 [2]/NASA/public domain.

Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Firing source (Distribution point for electro explosive subsystem) Firing circuit Firing source circuit

Firing output circuit Current limiting short circuit protection resistor

System bus Prearm

Isolation filters

Arm

Fire

Static bleed resistors

Structure ground System ground point

Monitor circuits

Firing control circuits

Safe and arm connector Isolation (plugs) filter connectors

EED

(a) Safing/arming device

Connector

100 000 Ω EED

100 000 Ω

Input

Shielded cable (b)

Figure L.2 Typical firing circuit scheme [3, 4]. The bleeding resistors may be too large; Experience has shown that resistors of 100 kΩ are ineffective against fast ESD impulses coupled onto the firing lines, and experience has shown that values in the range of 100–1000 Ω are more effective against such threats [4]. (a) Example of a typical EIED firing circuit. Source: Netzer [4]/M Netzer. (b) Example of a typical EIED firing circuit. Source: Adapted from MIL-STD-1576 (USAF) [3].

Under such a situation, the high currents might flow in a path common to other electronic systems, which may incorporate digital communication links (e.g. RS-422), analog links (e.g. video), etc. Any voltage drop between the two ends of such a link might result in “common-impedance interference coupling” (Figure L.3).

L.2

Conducted Susceptibility, Ground Plane Injection, Spike/Transient Requirement

According to the “Conducted Susceptibility, Ground Plane Injection, Spike/Transient Requirement” [1], the equipment under test (EUT) is required to withstand a transient waveform between equipment chassis and ground plane, while exhibiting no malfunction, degradation of performance, or deviation from specified indications, beyond the tolerances indicated in the individual equipment or subsystem specification.

1159

1160

Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Firing current pulse

EIED Firing circuit

Victim circuit RSL Firing circuit currentlimiting resistor

REIED EIED Resistance

Firing return current

VSD Signal source

VSF Firing pulse source

Inadvertent EIED Short to vehicle chassis during Firing Victim load circuit GND bonded to chassis

Victim driver circuit GND bonded to chassis

Vehicle chassis

Potential drop between assemblies Figure L.3

Common-impedance coupling mechanism between EIED and other equipment.

8 Vpeak

Time (μs) 10

20

30

40

50

t

Figure L.4 Ground plane injection (GPI) spike potential waveform.

The test waveform with an amplitude of ±8 V peak and duration of 10 μs is depicted in Figure L.4 but the requirement is also considered to be met if a spike of 8 V (positive and/or negative) cannot be established, but peak current as high as, but not exceeding, 16 A can be injected without EUT malfunction, degradation of performance, or deviation from specified indications. At first glance, skeptics might ask how such ground plane spikes/ transient might occur (after all, they claim, the chassis is “equipotential” and of sufficiently low-impedance, right? Well, not necessarily …).

L.3

Analysis

The following sections provide a rough, approximate, worst-case estimation of the actual expected transients they might occur under such situations.

L.3.1

Potential Interference Mechanism

As mentioned earlier, firing of EIEDs can produce high impulsive currents, typically in the order of 10–20 A, with rise time in the order of 1–2 μs, the switching time of the FETs in contemporary firing circuits. This switching current must return to its source, and that may occur through one of the following three potential paths (Figure L.2):

•• •

Through the designated return current wire. Through the shield of the EIED firing wire. Through chassis due to inadvertent shorting of the EIED bridgewire to chassis.

•

Through the DC power circuits, which are supplied from a primary DC power source (such as 28 VDC batteries), which are typically grounded to chassis.

The question in concern is whether, and to what extent, this current may find its way through an impedance common to other sensitive equipment, introducing voltages which may be hazardous to the function of that equipment. Also, three coupling mechanisms into victim equipment are examined:

Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

• •

By leakage through line-to-ground (common-mode) capacitors (or through parasitic capacitance) present between the DC supply input to victim equipment. Through the ground/reference circuits of the secondary voltages (e.g. DGND and AGND), which are often grounded to equipment enclosure, and subsequently, to the vehicle chassis, due to impulsive voltage drop between the source and load assemblies.

The feasibility of these mechanisms is now evaluated, all addressing the interaction due to unintentional chassis current flow. L.3.1.1

Coupling Through the DC Power Circuits, Supplied Directly from a Primary, Grounded DC Power Source

It would be reasonable to assume that the vast majority of electronic assemblies incorporate “floated input” DC/DC converters,3 with respect to the primary DC power distribution network. Hence, with a single chassis connection, no chassis current can directly flow into the DC primary power circuits, as a second connection for current exit is not available. This mechanism is, therefore, not feasible. L.3.1.2 Coupling by Leakage Through Line-to-Ground Capacitors (or Other Parasitic Capacitance), into the DC Supply Input to Victim Equipment

This mechanism is also assumed to be of low probability. Assuming that the line-to-chassis capacitors incorporated in the power-line filter at the equipment power entry port are quite small (as a very worst-case assumption, consider 10 μF, where typically these capacitors are each in the order of tens to hundreds of nFs, and in total, maybe 1 μF). Assuming a firing voltage impulse waveform, with a rise time of 2 μs and assuming a voltage swing of 28 V, the equivalent circuit in Figure L.5. A current-limiting resistance of 2 Ω at the firing circuit will be assumed. Now, we assume that in the path between the EIED being fired (and assumed to be shorted to chassis at the moment of firing) and the DC power source is an avionic assembly powered from the same DC power source. It will also be assumed that the firing power lines and the DC supply lines to the avionic assembly do not share a common path (which would otherwise serve as “common impedance”). Under worst case, we may assume current flowing from the DC power source (say, 28 V) through the 1 Ω current limiting resistor, is thus 14 A. Also, we assume that the avionics assembly present on the path of chassis current flow, has, as mentioned above, a “DC-floating” primary power input, thus coupling occurs only through the line-to-chassis capacitors. Actually, several return current paths are available back to the (−) terminal of the battery, and the current may split between them (see Figure L.5): a) Through the return current wiring of the EIED, back through the (−) terminal of the battery. b) Through the chassis of the vehicle, directly back to the (−) terminal of the battery.

Firing circuit

Firing impulse current

2 Ω Current limiting resistor

Avionic assy DC power source 28VDC RTN

DC/DC PS

Current divider between chassis and DC RTN Figure L.5

Equivalent circuit for assessing coupling through line-to-ground capacitors.

3 See Chapter 9 for discussion of grounding practices in spacecraft and launch vehicles.

EIED

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Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

c) Through the line-to-ground capacitors to the (−) terminal at the equipment power entry point, and thereafter to the (−) terminal of the battery. Using a rough assessment, the AC impedance of the capacitors (neglecting its ESL) is determined, primarily, by its capacitance. As the rise time of the impulse voltage across the capacitor (due to the firing FET switching) is 1μsec, the corresponding frequency is: F tr =

1 1 ≈ 320 kHz ≈ πt r π 1 μs

L1

The corresponding capacitive reactance of the capacitor is thus (recall that the mounting impedance of the capacitors and the ESL were neglected, as worst-case assumption). XC =

1 1 ≈ ≈ 50 mΩ 2πFC 2π 320 kHz 10 μF

L2

It follows the EIED return current flowing through the capacitance is limited by an impedance of 50 mΩ, approximately. Note that larger capacitors will have lower capacitive reactance, but may also possibly have greater ESL and ESR. Therefore, the impulsive current flowing through the capacitors depends on the current divider between the direct current path and the path through the capacitors. This can be easily evaluated by negation. For an impulsive current of 8 V (as per Figure L.4) across the capacitor, a current of approximately 80 A should flow through it: IC = C

dV C 8V ≈ 10 μF ≈ 80 A dt 1 μs

L3

However, it was assumed upfront that thanks to the current limiting resistor of 1 Ω and the firing voltage being 28 V, would limit the current to no more than 14 A, that is, the current which could develop the voltage specified in Figure L.4 is much larger than the available current (not even considering the current divider (Figure L.5) between the current path through the capacitor and directly through the chassis, where it is assumed that a large fraction of the current will flow). Note that (from Equation L.3) a larger capacitor will require even a larger current impulse to develop the “target” voltage. It follows, therefore, by negation, that this mechanism is not feasible either.

L.3.1.3 Coupling Through the Ground/Reference Circuits of the Secondary Voltages (e.g. DGND and AGND), When (as Often) Grounded to Equipment Enclosure and Chassis

This mechanism is based on the assumption that the EIED firing return current flows through the vehicle chassis between avionic assemblies mounted along the firing return current path. In this mechanism, it is assumed that a voltage drop occurs between the “local grounds” of the avionic assemblies (e.g. DGND), serving as path for signal return as well as secondary DC voltages within the assemblies, both assumed to be grounded to the vehicle chassis. When discrete or communication signals interface between the two assemblies, a momentary potential difference may exist between the two assemblies across the chassis of the vehicle, resulting in potential interference to the functionality of the secondary circuits. This mechanism in fact, is the “common-impedance coupling” or “ground-loop interference coupling” (see Figure L.3). The circuit in Figure L.6 illustrates the power source (e.g. battery4). In the current return path between the EIED and the power source, two avionic assemblies are illustrated, both powered from the same primary power source.5 For the purpose of this analysis, it is assumed that the signal interfaces between the circuits are non-isolated “copper interfaces” (i.e. wired, in contrast to optical links), such as RS-422, Can-Bus, discretes, etc. Absolute maximum ratings for the common-mode potential difference between the two end terminals are estimated to be:

• •

Can-Bus: – 7 V, for continued performance – 40 V, for no-damage RS-422: – 12 V, for continued performance – 20 V, for no-damage

4 The circuit does not illustrate the switching FETs, but does include the 2 Ω current-limiting resistor. 5 In this mechanism, which involves the secondary power grounds, this assumption is of minor significance, as long as the primary and secondary power circuits are isolated from each other, as assumed.

Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Firing circuit

Firing impulse current

2 Ω Current limiting resistor

Avionic assy #1

DC power source

28VDC RTN

DC/DC PS GND secondary

Avionic assy #2 Signal interface Ground impedance, ZG

DC/DC PS

GND secondary

EIED Inadvertent EIED short to vehicle chassis during firing

Potential drop between assemblies Figure L.6

Equivalent circuit for assessing coupling through vehicle chassis.

It follows that disruption of communication between two end-units, due to a potential difference across the chassis of the vehicle, will occur when the EIED firing return current flowing through the vehicle will exceed the permissible levels. For the purpose of this assessment, a 7 V permissible potential difference is assumed, where: 14A Z G = 7 V

L4

where ZG represents the total impedance of the vehicle chassis between the two assemblies. It follows from Equation (L.4) that for disrupting the communication between the assemblies, the current should flow through an impedance of ZG > 500 mΩ. Two key assumptions are taken for the purpose of the following analysis:

• •

The firing FET functions as an ideal current source; therefore, the current flowing through the vehicle chassis is independent on the path impedance (except the current limiting resistor). The two assemblies are assumed to be in the direct path of the firing return current (between the EIED and the power source). If the two assemblies, the EIED and the power source, are not aligned (for instance, if they are mounted on the perimeter of the vehicle segment at a displacement angle of 90 ), most of the return current path will not flow in the vehicle structure in the path between the two assemblies and the potential difference between them will be lower.

In TTL interfaces such as discrete lines, the criterion may be stricter. In 3.3 V TTL interfaces, the disruption level will, most likely, be determined by the noise margin or noise immunity level of the interface. It would be reasonable to assume an acceptable interference level of approximately 5% of the nominal supply voltage, i.e. 5% of 3.3 V, yielding, approximately, 150 mV. This implies that if between the two assemblies exist discrete TTL interfaces, impulsive interference in the order of 150 mV may result in disruption of the signal. With an impulse current of 14 A, as assumed, a potential difference of 150 mV will occur if the impedance of the vehicle chassis is ZG =

5

3 3V = 10 mΩ 14 A

L5

What is the expected impedance of the chassis? The impedance of the structure depends on the material used. Aluminum (AL 6061), for instance, has a resistivity of ρ = 28.2 nΩ m. The resistivity of carbon fiber reinforced polymer (CFRP) T300-class materials is 1000 times higher than that of aluminum, e.g. 17 μΩ m, depending on layup of the composite plies6 [5, 6]. For the purpose of this analysis, a comparison of aluminum and composite structures will be considered. As in most cases, the main structure of the stages of a typical launch vehicle is constructed of composite materials. The typical missile-derived expendable launch vehicle (LV) may be thought of as a stack of tanks with an engine at one end and a payload at the other. In more detail, the engines are mounted to the aft end of the tanks and exert thrust through a reinforced structure. The tanks are connected with thin-walled cylinders called skirts or intertanks. Complete stages are connected to one another through cylindrical shells called interstages or adapters, which often include the avionic systems at the top and/or bottom of each stage. It is assumed that the engines are constructed of composite materials, while the interstage modules are assumed to be metallic (e.g. aluminum) (see Figure L.7 for an image of the Indian SLV-3 low earth orbit (LEO) vehicle, brought for illustration only.)

6 Graphite exhibits directionality in its electrical properties, which accounts for the inhomogeneity and anisotropic nature of the carbon fibers in carbon fiber composites. This anisotropy makes the physical properties of these materials vary as a function of the number of fiber layups and their orientation, as well as with their fiber to epoxy resin ratio. Differences in fiber layups affect the resistivity of the overall material in particular directions.

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Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Stage 1 L = 10.0 m D = 1.0 m

Stage 2 L = 6.4 m; D = 0.8 m

Stage 3 L =1.5 m; D = 0.65 m

Stage 4 L = 2.2 m; D = 0.8 m

Figure L.7 Example of construction of a launch vehicle (example is of the SLV-3 Indian launch vehicle [height 24 m]). Source: Courtesy of GW_Simulations/public domain.

• •

Two cases should now be investigated: Assemblies mounted on the same interstage segment, where a solid metallic chassis (i.e. aluminum) is assumed to be present, or Assemblies mounted on the adjacent interstage segments (e.g. top stage 1 and bottom stage 2), where it may be assumed that continuous metal-to-metal bonding exists between the segments. Assemblies mounted on two remote interstage segments on the same stage (e.g. bottom and bottom of stage 1), where it may be assumed that electrical contact between the assemblies is achieved through the composite materials forming the cylinders containing the engines.

The first two cases are assumed to be identical, in principle, thanks to the continuous metal-to-metal contact between the structures. Next, a discussion of the two distinct cases is provided, using the following process: 1) Most of the firing impulse current spectral density is contained in the frequency range from DC to the firing pulse-widthequivalent frequency. Assuming a firing pulse width, d, of 5 ms, the corresponding frequency is: Fd =

1 1 = 63 kHz = πd π 5 ms

L6

This frequency is sufficiently high to assume that skin depth is smaller than thickness of the skin, hence, the current may be assumed to concentrate (mostly) in a depth of 3δ, where δ is the skin depth: δ=

1 πFμσ

L7

where F is the frequency of concern, μ is permeability of the material (assumed to be 1 4π × 10−7 H/m), and σ is the conductivity of the material. It would be reasonable to assume that owing to the low-frequency content of the current impulse, the current flows between source to load with some elliptic spreading. It will be assumed that the maximum width of the elliptic path is approximately one third (1/3) of the total length of the path between source and load. The resistance of the path is, therefore7: R=ρ

L L L ρ = ≈ρ ≈ρ A 3δ w 3δ L 3 δ

L8

where A is the cross section of the current path, L is the length of the path, and w, the maximum width of the spreading current path. This will now be applied to the two cases above: a) Assemblies mounted on a common metallic (aluminum) structure. Aluminum (AL 6061), for instance, has a resistivity of ρ = 28.2 nΩ m, thus, substituting in Equation (L.7) yields an approximate skin depth (at F = 63 kHz) of δ ≈ 0.337 μm. Since the metallic structure is assumed to be significantly thicker than 3δ ( 1 μm), the current does not occupy the full thickness of the skin. Consequently, the resistance of the path is, approximately (based on Equation (L.8)), is 83 mΩ. With this resistance, and a peak current impulse of 14 A, yields a potential difference of 1.15 V. b) Assemblies mounted on a common composite structure. A composite (CFRP of T300-class material), for instance, has a resistivity of ρ = 17 μΩ m, thus, substituting in Equation (L.7) yields an approximate skin depth (at F = 63 kHz) of δ ≈ 8.27 mm. Since the composite structure is assumed to significantly thicker than 3δ ( 1 mm), the current, again, does not occupy the full thickness of the skin. 7 With higher resistivity, ρ, of the current return path (through the vehicle chassis), the return current density is expected to be lower (as observed from J = σE, or J = E/ρ, Ohms law in materials), thus the current spreading will be greater. In this case, an increase in the width current return path is anticipated. See Appendix J for analysis.

Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Consequently, the resistance of the path is, approximately (based on Equation (L.8)), is 2.06 Ω. With this resistance, and a peak current impulse of 14 A, yields a potential difference of 28.8 V. If the cables are routed in metalized (e.g. with copper plating) cable conduits along the stage 1 engine, from the top to bottom segment, say 0.5 m wide, the current spread will essentially be as wide as the metalized conduit, w = 0.5 m. The resistivity of copper is ρ = 17.2 nΩ m and skin depth is 0.263 μm at F = 63 kHz. Again, using Equation (L.8) but substituting w = 0.5 m, we arrive at: L L ≈ρ A 3δ w 10 m = 0 44 Ω = 17 2 nΩ m 3 0 263 × 10 − 6 m 0 5 m R=ρ

L9

With this resistance, and a peak current impulse of 14 A, yields a potential difference of 6.1 V.

L.3.2

Summary and Conclusions

The rough assessment presented in this appendix was intended for illustration of the practicality of one of the “Conducted Susceptibility, Ground Plane Injection, Spike/Transient,” derived from spacecraft EMC standards (e.g. AIAA-S-121A [1], see Figure L.4), as an example. This example is fictional and not based on any true system, but could be relevant to such airborne platforms as launch vehicles. As it is not realistic, assumptions were made, such as:

•• • •• •

Construction and materials of the vehicle chassis. Characteristics of the EIEDs, etc. Some assumptions were made for simplicity of the assessment, such as: The pulse-width equivalent “corner frequency” used for determining the frequency at which the skin depth, δ, is computed (this may be too conservative, as it is well known that the current spectrum is concentrated from DC to this frequency, and in fact, lower frequency spectral components will flow through greater skin depths that that assumed, resulting in lower resistance of the path). That most return current concentrates in a depth of 3δ (this may be too liberal, and might result in lower resistance of the path). Assessment based on resistance, rather than inductance, due to the lower frequency content of the firing impulse (this may be too conservative, as inductance will further increase the loop impedance resulting in lower current). The assumption that the firing current source acts as an ideal current-source, hence the firing current flowing through the path is independent on the path resistance (this, in fact has been validated in practice).

The conclusion from this rough assessment is that among the three interference mechanisms, resulting from a short of the EIED during its firing to the chassis vehicle, the one most likely to cause significant interference is that of common-impedance coupling, when the return current between the EIED and its firing circuit occur in a path common to electronic assemblies interconnected through digital or analog circuitry, where their secondary power return (e.g. DGND and AGND) circuits (isolated from the primary power inputs of those assemblies) are connected to the chassis of the vehicle. It is evident that there are several factors affecting the coupling in this mechanism, namely:

• • •

Material of the Firing Current Return Path Aluminum (e.g. for assemblies mounted on the same interstage segment), exhibiting high conductivity precludes high (destructive, and possibly even disruptive) potential differences from developing ( 1 V, in this example); CFC composites, the conductivity of which is approximately 1/1000th of aluminum and hence orders of magnitude higher potential differences across the structural chassis will occur ( 29 V, approximately, in this example); finally, when the cables are routed along the engines along metalized (copper) conduits, medium potential differences develop ( 6 V, in this example). Layout of Equipment Obviously, common impedance coupling through the vehicle chassis can occur when the return current flows in a path common to routing of signal cables interconnecting avionic assemblies. Grounding scheme Coupling into the electronic circuits was facilitated through the conductive path formed by the low-impedance bond between the electronic assemblies. “Floating” secondary “grounds” (DGND and AGND) in the electronic assemblies precludes efficient coupling into the circuits (equivalent to the case illustrated in Figure L.5), but on the other hand may result in other EMI concerns.

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Appendix L Sample Practical Analysis of “Common-Impedance Coupling”

Isolated signal interfaces (e.g. Ethernet, galvanically isolated RS-485/RS-422 transceivers, and optically isolated discrete interfaces) would reduce the risk of disruption (or even damage) from the impulsive interference discussed here. The analysis has demonstrated that the “Conducted Susceptibility, Ground Plane Injection, Spike/Transient,” derived from spacecraft EMC standards (e.g. AIAA-S-121A [1], see Figure L.4), is well-founded, and depending on case, may even be too liberal, while in other cases, too conservative. Application of this requirement to practical cases (the example here is brought for illustration only, and inasmuch as it may be practical, it is not founded on a true, particular case), should be considered based on analysis and due consideration. As quoted from Thomas A. Edison: The three great essentials to achieve anything worthwhile are, first, hard work; second, stick-to-itiveness; third, common sense. Common-sense should be applied in applying EMC requirements derived from standard, particularly those associated with “ground-coupled interference.” Good understanding of the system architecture, sources of interference, potential coupling mechanisms, and the modes of interference (including unintentional, such as the EIED short to chassis during firing), are all essential for such assessment. Such an assessment may not be accurate (accuracy may be improved by rigorous 3-D simulations), but, as Dr. Eric Bogatin states8: 6. Sometimes an okay answer NOW! is more important than a good answer late. There are occasions when an estimate that you can do quickly can indicate how close to a problem you may be. If you are far from a problem area, move on to a more important problem. If the estimate says you are close, then it can justify spending the extra time and expense to get a better answer. You may never have all the information you need to make a good decision. Use what you know, use your judgment, and consider a later, follow-on investigation to get the additional important information for a better decision.

References 1 AIAA S-121A (2017). Electromagnetic Compatibility Requirements for Space Equipment and Systems (January 2017). AIAA,

American Institute of Aeronautics and Astronautics. 2 NASA-HDBK-4001 (1998). NASA Technical Handbook Electrical Grounding Architecture for Unmanned Spacecraft. National

Aeronautics and Space Administration (17 February 1998). 3 MIL-STD-1576 (USAF) (1984). Military Standard, Electroexplosive Subsystem Safety Requirements and Test Methods for Space

Systems (July 1984). US Department of Defence (DoD). 4 Netzer, M. (2019). A Design Guide for Hardening Firing Circuits Against the Threats of EMI and ESD (Hebrew). Rafael

(December 2019). 5 Abid, R. (2015). Electrical characterisation of aerospace grade carbon-fibre-reinforced polymers. PhD thesis. Cardiff School of

Engineering (December 2015). 6 Zhao, Q., Zhang, K., Zhu, S. et al. (2019). Review on the electrical resistance/conductivity of carbon fiber reinforced polymer.

Applied Sciences 9 (11): 2390. https://doi.org/10.3390/app9112390.

8 Bogatin, E. (2020). Bogatin’s 20 rules for engineers. Signal Integrity Journal (14 January 2020).

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Appendix M Grounding, Bonding, and Earthing Check Yourself Quiz

Checkup each week on the progress you are making. Ask yourself what mistakes you have made, what improvements, what lessons you have learned for the future. — Dale Carnegie

Confidence applied properly is the path of genius. You must always be in a state of confidence. And the way you sustain a state of confidence is by testing yourself. Difficult quagmires that may occur; there’s always a test. You have to seek them out. You constantly have to test yourself to prepare for these quagmires. That’s why I always put myself to the test. — Mike Tyson

M.1

Introduction

This appendix is designed to test your understanding of the concepts covered in this book and to give you an opportunity to reflect on what you have learnt. It is presented in a form of a multiple-choice quiz. Note that the “most correct” answer should be selected. Inasmuch as several answers may be correct, there will always be one that is the most correct and conclusive. An answer key and rational are provided at the end of this appendix.

M.2

Grounding

M.2.1

Which of the following statements best defines Grounding?

a) b) c) d)

M.2.2 a) b) c) d)

M.2.3 a) b) c) d)

A A A A

connection of an equipment unit to earth path of fault current flow connection between two metallic parts path for return current flow

Common-mode current flows on all power conductors to the power return conductors in equal amplitude and equal polarity signal conductors to the signal return conductors in equal amplitude and opposite polarity

For controlling high-frequency radiated emissions earthing of equipment is undesired as it may increase radiated emissions is necessary only for high-frequency circuits is of no significant effect on radiated emissions will effectively reduce radiated emissions

Grounds for Grounding: A Handbook from Circuits to Systems, Second Edition. Elya B. Joffe and Kai-Sang Lock. © 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.

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Appendix M Grounding, Bonding, and Earthing Check Yourself Quiz

M.2.4

Multipoint grounding is particularly useful in order to

a) b) c) d)

provide a low impedance to ground at higher frequencies separate paths of signal and power return currents ensure that the impedance to ground is as low as possible AC power circuits, for ensuring safety of personnel

M.2.5 a) b) c) d)

Current, if not obstructed, will always follow the path of least least least least

distance resistance inductance impedance

M.2.6 If resistance of the grounding conductor in the figure shown below is negligible, the grounding path’s characteristic impedance (Z0) is approximately …

Equipment Ground conductor Zin→

a) b) c) d)

Ground loops are seldom a problem at high frequency almost always a problem seldom a problem at low frequency mostly a problem at high frequency

M.2.8 a) b) c) d)

An equipotential ground structure should have low resistance low inductance low impedance carry no current

M.2.9 a) b) c) d)

What grounding scheme is best for high frequencies? Single point Floating system Multipoint Composite/hybrid

M.2.10 a) b) c) d)

ZL = 0

L0.5/C L/C L/C0.5 (L/C)0.5

M.2.7 a) b) c) d)

Zo =

Multipoint grounding is not the cure for all grounding problems because its greatest drawback is …

uncontrolled current return paths its electrically long grounding conductors resonances that develop across the grounding leads ground-coupled interference between grounded circuits

Appendix M Grounding, Bonding, and Earthing Check Yourself Quiz

M.2.11 a) b) c) d)

electrical safety purposes providing different grounding schemes at different frequencies preclusion of high-frequency ground-loops in mixed analog/digital circuits in lower frequency analog circuits

M.2.12 a) b) c) d)

In distributed systems, the most important method to ensure EMI-free performance is …

grounding both ends of differential interfaces grounding source circuits only and filtering floating source and load and shielding of cables use terminal protection devices and balanced interfaces

M.2.16 a) b) c) d)

Ground loops can be “broken” by …

balancing, blocking, isolation attenuation, blocking, isolation isolation, suppression, balancing filtering, isolation, blocking

M.2.15 a) b) c) d)

Optical isolators (opto-couplers) are …

excellent for high-frequency common-mode rejection best suited for digital interfaces simple, passive isolation devices effective for isolation up to 1GHz, approximately

M.2.14 a) b) c) d)

The “grounding tree” concept is …

useful for mixed analog/digital circuits a simple graphical grounding scheme of value for grounding on PCBs only ensures isolation between analog and digital circuits

M.2.13 a) b) c) d)

Frequency-selective grounding is necessary for …

The greatest benefit of differential signaling is that it …

requires no ground connection exhibits high immunity to ground-coupled EMI eliminates the need for terminal protection eliminates the need for shielding the cables

M.2.17 In order to preclude magnetic field emissions from a high-frequency coaxial cable connected to a grounded circuit, the cable shield should be … a) b) c) d)

grounded at both ends grounded at one end only left floating at both ends grounded every quarter wavelength

M.2.18 a) b) c) d)

The term “AC Ground” implies …

a path of AC return current (“neutral”) an AC power protective earth connection a path that may carry either AC or DC current the protective earth serving as signal return

M.2.19

Inductance in high-frequency circuits …

a) limits high-frequency noise voltage b) increases rail bounce noise

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Appendix M Grounding, Bonding, and Earthing Check Yourself Quiz

c) suppresses ground plane resonances d) ensures a controlled DC current path

M.2.20 a) b) c) d)

effective high-frequency decoupling broadband low-impedance decoupling suppression of series resonances multiple parallel resonances

M.2.21 a) b) c) d)

Corrosion reactions primarily result from …

the small contact areas between surfaces of mating metals electrochemical potential difference between mating metals high ambient temperature presence of paint on mating surfaces

M.2.27 a) b) c) d)

Indirect bonds …

provide low-impedance connection at high frequencies are mandatory for electrical safety exhibit highly inductive bonds the most reliable chassis connection

M.2.26 a) b) c) d)

Chassis stitching is useful to …

ensure a low-frequency equipotential reference provide multipoint electrical safety connection suppress high-frequency natural PCB resonances provide high isolation between returns

M.2.25 a) b) c) d)

The grounding scheme in circuits with an embedded A/D converter depends primarily on …

complexity of the digital circuits resolution of the A/D converter voltage level of the analog power source number of the power planes present

M.2.24 a) b) c) d)

High-speed transmission lines jumping across the VCC (power) and GND (return) planes is OK …

at high frequencies only when an adjacent signal trace is provided when an adjacent stitching capacitor is present for differential signals only

M.2.23 a) b) c) d)

Interplane capacitance on multilayer PCBs …

exhibits low effective capacitance eliminates the need for decoupling produces an effective current return path creates low-frequency resonances

M.2.22 a) b) c) d)

Multiple, unequal parallel decoupling capacitors produce …

Ground-coupled interference in a differential system occurs primarily due to …

imbalance in the load losses in the wiring sensitivity of the load losses in the ground plane

Appendix M Grounding, Bonding, and Earthing Check Yourself Quiz

M.2.28 a) b) c) d)

equipotential lossy interference-tolerant does not exist

M.2.29 a) b) c) d)

Cable shield should not serve as a signal return path except in …

differential digital circuits AC or DC power circuits higher frequency coaxial cables single-ended analog circuits

M.2.31 a) b) c) d)

Single-point grounding is …

optimal across all frequencies, from DC to daylight best at lower frequencies necessary for electrical safety purposes best in mixed analog/digital circuits

M.2.30 a) b) c) d)

A practical ground is …

A ground fault circuit interrupter (GFCI) monitors the …

neutral current ground current voltage difference between the neutral and ground current imbalance between the phase and neutral

M.2.32 Flat straps are preferred over round wires with equal cross section for high-frequency conductors because they … a) b) c) d)

provide more flexibility have lower resistance at higher frequencies have a larger skin depth provide lower resistance and inductance

M.2.33 a) b) c) d)

resistance inductance capacitance reluctance

M.2.34 a) b) c) d)

The preferred ratio for a flat bonding strap’s length to width is …