Digitally Assisted Pipeline ADCs : Theory and Implementation [1 ed.] 1402078390, 9781402078392, 9781402078408

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DIGITALLY ASSISTED PIPELINE ADCs

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Digitally Assisted Pipeline ADCs Theory and Implementation by

Boris Murmann Standford University and

Bernhard E. Boser University of California, Berkeley

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: Print ISBN:

1-4020-7840-4 1-4020-7839-0

©2004 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2004 Kluwer Academic Publishers Dordrecht All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Kluwer Online at: and Kluwer's eBookstore at:

http://kluweronline.com http://ebooks.kluweronline.com

Dedication

To our families.

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Contents

List of Figures List of Tables Acknowledgments Preface

xi xv xvii xix

1. INTRODUCTION 1. Motivation 2. Overview 3. Chapter Organization

1 1 2 4

2. PERFORMANCE TRENDS 1. Introduction 2. Digital Performance Trends 3. ADC Performance Trends

5 5 6 7

3. SCALING ANALYSIS 1. Introduction 2. Basic Device Scaling from a Digital Perspective 3. Technology Metrics for Analog Circuits 4. Scaling Impact on Matching-Limited Circuits 5. Scaling Impact on Noise-Limited Circuits

15 15 16 17 25 33

4. IMPROVING ANALOG CIRCUIT EFFICIENCY 1. Introduction 2. Analog Circuit Challenges 3. The Cost of Feedback

43 43 43 45

viii

Digitally Assisted Pipeline ADCs 4. 5.

Two-Stage Feedback Amplifier vs. Open-Loop Gain Stage Discussion

46 52

5. OPEN-LOOP PIPELINED ADCS 1. A Brief Review of Pipelined ADCs 2. Conventional Stage Implementation 3. Open-Loop Pipeline Stages 4. Alternative Transconductor Implementations

53 53 54 55 60

6. DIGITAL NONLINEARITY CORRECTION 1. Overview 2. Error Model and Digital Correction 3. Alternative Error Models

63 63 65 74

7. STATISTICS-BASED PARAMETER ESTIMATION 1. Introduction 2. Modulation Approach 3. Required Sub-ADC and Sub-DAC Redundancy 4. Parameter Estimation Based on Residue Differences 5. Statistics Based Difference Estimation 6. Complete Estimation Block 7. Simulation Example 8. Discussion

75 75 76 77 79 84 87 90 97

8. PROTOTYPE IMPLEMENTATION 1. ADC Architecture 2. Stage 1 3. Stage 2 4. Post-Processor

101 101 102 106 107

9. EXPERIMENTAL RESULTS 1. Layout and Packaging 2. Test Setup 3. Measured Results 4. Post-Processor Complexity

109 109 111 112 121

10. CONCLUSION 1. Summary 2. Suggestions for Future Work

123 123 124

Appendices A- Open-Loop Charge Redistribution B- Estimator Variance

127 131

Contents

ix

C- LMS Loop Analysis 1. Time Constant 2. Output Variance 3. Maximum Gain Parameters

137 137 138 139

References Index

143 153

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List of Figures

1-1. 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7. 3-8. 3-9. 3-10. 3-11. 3-12.

System overview. ADC performance trend. ADC energy efficiency trend. Comparison of speed trends: ADCs versus digital. Comparison of energy efficiency trends: ADCs versus digital. Modern ADC application: 802.11 base band processor for wireless networks [21]. ADC applications in the speed/resolution space. The equipower contours assume FOM2=3pJ/conversion. Supply voltage scaling. NMOS transit frequency. Transconductor efficiency versus gate overdrive. The dotted line shows the case for perfect square law devices. Product gm/ID·fT. NMOS intrinsic device gain at VOV=200mV. NMOS intrinsic device gain at VOV=200mV (Zoom into typical operating region). Technology scaling trends of AVTH and Aｅ. Flash ADC block diagram. Preamp/latch model. Flash ADC energy as a function of sampling rate (assuming constant mismatch factors AVTH, and Aｅ). Flash ADC energy as a function of sampling rate (assuming improving mismatch factors AVT, and Aｅ with technology). Estimated flash ADC energy versus feature size (from speed trajectory in Figure 3-11).

3 10 11 12 12 13 14 18 19 20 21 22 22 24 26 27 29 30 31

xii 3-13. 3-14. 3-15. 3-16. 3-17. 3-18. 3-19. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6.

5-1. 5-2. 5-3. 5-4. 5-5. 5-6. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 7-1. 7-2. I

7-3. 7-4. 7-5. 7-6.

Digitally Assisted Pipeline ADCs Published flash ADC performance vs. technology. Basic amplifier model. Noise limited circuit energy versus speed and technology. Ratio slewing/linear settling time vs. sampling speed. Noise limited circuit energy with slewing included. Published 10-bit pipelined ADC performance vs. technology. Typical 10-bit pipelined ADC power distribution. Analog circuit challenges and power dissipation. Comparison: (a) Precision feedback amplifier. (b) Open-loop amplifier. (a) Two-stage feedback amplifier. (b) Open-loop gain stage. Two-stage amplifier penalty factor. Percent power savings with open-loop amplification as a function of gain (assuming ｋa=ｋb). Percent power savings with open-loop amplification as a function of gain (assuming Vref=1V, ｋa=10V-1 and ｋb given by (4-13)). Pipelined ADC block diagram. Conventional pipeline stage. Open-loop pipeline stage. Open-loop stage model. Differential pair V-I characteristic. Differential pair nonlinearity as a function of ｄ=Vxmax/VOV. (a) ADC block diagram. (b) Reduced model for analysis. Reduced model with stage sub-circuits. Model for error compensation. Additive nonlinearity compensation. (a) Model with shifted variables. (b) Equivalent/compensated model. Modification for hardware efficient linear digital weighting. Complete digital correction hardware. System model with digital code modulation. ntroducing Sub-ADC redundancy: (a) Quantization error of a 2-bit sub-ADC. (b) Error of a (2+1)-bit sub-ADC. (c) Superimposed modulation. Sub-ADC/DAC interface: (a) Bipolar modulation. (b) Equivalent unipolar modulation with DAC offset. System model for transfer function analysis. Residue plot for both RNG states. Single transfer function segment without correction and b3