Design of CMOS Operational Amplifiers [illustrated, reprint] 1608071537, 9781608071531

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Design of CMOS Operational Amplifiers

For a complete listing of titles in the Artech House Microwave Library, turn to the back of this book.

Design of CMOS Operational Amplifiers Rasoul Dehghani

Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library. Cover design by Adam Renvoize

ISBN 13: 978-1-60807-153-1

© 2013 ARTECH HOUSE 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark.

10 9 8 7 6 5 4 3 2 1

Contents Chapter 1 Basic Specifications of Op Amps 1.1 Op Amp Parameters 1.2 Conclusion

1 1 13

Chapter 2 CMOS Technology and Physics 2.1 Basic Processes in MOS Transistor Fabrication 2.2 Principles of MOS Transistor Functioning 2.2.1 MOS Transistor Operating in Saturation Region 2.2.2 MOS Transistor Operating in Subthreshold Regime 2.3 Small-Signal Model of MOS Device 2.3.1 Gate to Substrate Capacitance 2.3.2 Gate to Source/Drain Capacitance 2.3.3 Source/Drain to Bulk Capacitance 2.4 Conclusion

15 15 17 17 21 21 24 26 27 31

Chapter 3 CMOS Differential Amplifiers 3.1 Source-Coupled Differential Pair Characteristic 3.2 CMOS Differential Amplifier with Active Load 3.2.1 Large-Signal Characteristic of CMOS Differential Amplifier 3.2.2 Offset Voltage of CMOS Differential Amplifier 3.3 Common-Mode Behavior of CMOS Differential Amplifier 3.4 CMOS Differential Amplifier Frequency Response 3.5 Noise Calculations in CMOS Differential Amplifier 3.6 Conclusion

33 33 36

Chapter 4 CMOS Single-Ended Output Op Amps 4.1 CMOS Two-Stage Op Amp 4.1.1 Offset Voltage 4.1.2 Two-Stage Op Amp Frequency Response 4.1.3 CMOS Two-Stage Op Amp Design Procedure Design Example 4.1.4 PSRR of CMOS Two-Stage Op Amp 4.2 Telescopic Cascode Op Amp 4.3 Folded-Cascode Op Amp Design Example 4.4 Current Mirror Op Amp Design Example 4.5 Rail-to-Rail Input Op Amp 4.6 Conclusion

36 38 42 43 47 53 55 55 56 59 65 69 72 83 86 87 90 94 96 105

v

vi

Contents

Chapter 5 CMOS Fully Differential Op Amps 5.1 Advantages of Fully Differential Op Amps 5.2 Common-Mode Feedback Concept 5.3 Common-Mode Feedback Circuits 5.3.1 Common-Mode Feedback Circuit with Resistive Sensing 5.3.2 Differential Difference Common-Mode Feedback Circuit 5.3.3 Common-Mode Feedback Circuit Using MOS Devices Operating in the Triode Region 5.3.4 Switched-Capacitor Common-Mode Feedback Circuit 5.4 Fully Differential CMOS Op Amp Architectures 5.4.1 Fully Differential Two-Stage Op Amp 5.4.2 Fully Differential Current Mirror Op Amp 5.4.3 Fully Differential Folded-Cascode Op Amp Design Example 5.5 Conclusion

107 107 109 111

118 119 123 123 127 129 130 134

Chapter 6 CMOS Output Stages 6.1 Class A and Class B Output Stages 6.1.1 Source-Follower as an Output Stage 6.1.2 Class B Power Amplifier 6.2 Drain-Coupled Complementary Transistors as Output Stage 6.3 Low-Voltage Class AB Buffer 6.4 Class AB Output Stage Using a Translinear Loop 6.5 Case Study Design Example 6.6 Conclusion

135 135 135 139 142 149 153 159 163 166

Chapter 7 CMOS Reference Generators 7.1 CMOS Voltage Reference Generators 7.1.1 Bandgap Voltage Reference Generator Design Example 7.1.2 Low-Voltage Bandgap Reference Generator Design Example 7.1.3 CMOS Voltage Reference Generator without Resistors 7.2 CMOS Current Reference Generators 7.2.1 Gm-Constant Circuit 7.2.2 Fully Integrated Precision CMOS Current Reference 7.2.3 CMOS Current Reference without Resistors Design Example 7.3 Conclusion Index

167 167 168 170 173 174 176 180 182 186 188 191 193 195

112 114

Chapter 1 Basic Specifications of Op Amps An operational amplifier is one of the most important building blocks in many analog systems. For instance, in an integrated analog filter such as a switchedcapacitor or a Gm-C filter, the op amp is an integral part of the circuit. Data converters including both analog-to-digital and digital-to-analog converters are other categories in which the op amp plays a fundamental role to achieve the desirable performance. In voltage and current reference generators an op amp has remarkable influence on the operation of these circuits. In the enumerated instances many parameters of the system are extensively dependent on the specifications of the op amps used in that system. It should be noted that the criteria applied to the design of an op amp employed in such systems are usually different from those used for designing a general-purpose op amp that is to be available as a stand-alone component in discrete circuitries. In general, the behavior of an op amp is described by many different parameters in which some of them might be more important than others in a particular analog system. In this chapter we introduce the main op amp parameters that have significant impact on the behavior of an analog system where an op amp has been exploited.

1.1

Op Amp Parameters

DC gain: Ideally the value of this parameter is considered infinity but in reality, due to the limited intrinsic voltage gain of each device used in the op amp circuit, the entire gain of an op amp has a finite value in the typical range of to (40 dB-100 dB). Exploiting an op amp in a linear amplifier involves putting the op amp in a negative-feedback loop. In this situation a high dc gain of the op amp could be essential. In the following we demonstrate the reason for such an assertion. Supposing that the open-loop gain of the feedback is quite high, we can calculate the closed-loop gain of the circuit based on the values of the feedback network components independent of the op amp parameters. As an example consider the inverting feedback amplifier shown in Figure 1.1. Denoting the low-frequency voltage gain of the op amp as , we can calculate the exact

1

2

Basic Specifications of Op Amps

C2

vi

C1

−

vo

+ Figure 1.1 Inverting feedback amplifier.

closed-loop voltage gain as (1.1) Where is the feedback factor. If it is assumed that , (1.1) can be approximated as . In an ideal case, for , the amplifier gain is completely independent of the op amp gain and equals . In practice, for a particular feedback gain error, we need to increase the op amp gain above a certain level. For example, ideal feedback gain of 2 with an error less than 0.1% is achievable provided that or if we have . Thus, in order to achieve more accurate feedback gain the dc gain of the op amp needs to be quite high. Limited linearity range. For a certain level of the input and output signal variations, the internal devices of op amp operate in the linear part of their characteristics. At input, the devices remain in their active operation region when the variation range of the input common-mode voltage is limited to a particular range known as input common-mode range (ICMR) [1]. This parameter depends on the op amp structure and the type and biasing conditions of the input devices. The linear operation range for a differential input signal in an open-loop state is much more limited. Of course when an op amp is used in a negative-feedback loop, the linearity behavior is significantly improved by the feedback mechanism. An amplified signal at the output of an op amp can also swing in the limited range at the most between two supply rails, although its precise level depends on the particular structure utilized as the output stage. Common-mode rejection ratio. One of the most outstanding advantages of an op amp is its capability to amplify the difference of two input signals without output being affected significantly by the changes in the input common-mode level. This property results in immunity against any common-mode undesirable signal that

1.1 Op Amp Parameters

3

might appear at the inputs of the op amp. The parameter of common-mode rejection ratio (CMRR) is used to quantify this performance [2]. The definition of this parameter is a little bit different for the two types of op amp. In a fully differential op amp in which both input and output signals are differential, the differential-mode and common-mode components of the output voltage are expressed as a linear combination of the corresponding input voltages as follows !"#

$# !%$

!"$

## !%#

$$ !%$

(1.2a)

#$ !%#

(1.2b)

where ## and $$ are differential-mode and common-mode voltage gains, respectively. $# and #$ exhibit the contribution of the common-mode and differential-mode of the input; that is, !%$ and !%# in their corresponding components in the output voltage, respectively. In an ideal differential op amp with a fully symmetrical structure, we have $# but in reality, due to #$ the device mismatches in the path of each input to two other outputs, this is not the case. In this situation, CMRR is defined as the ratio of the differential voltage gain ## to the common-mode to differential-mode voltage gain $# as &''()

*

++ ,+

*

(1.3)

where &''() denotes the fully differential CMRR. To measure the &''() , we might exploit the circuit illustrated in Figure 1.2. The fully differential op amp is configured as a unity voltage gain amplifier in a negative-feedback loop. The internal common-feedback circuit and the external negative-feedback cause the output common-mode voltage and also the dc level of each output to be kept on the common-mode reference voltage denoted by -$. . Representing the voltages at the inverting and noninverting inputs of the op amp as ! / and ! , respectively, we can easily find these voltages as follows !"

!/

!

!"/

-$. -$.

-$0

(1.4a)

-$0

(1.4b)

From the above relations, the input differential-mode and common-mode voltages are obtained

!%$

!%# !

!

!/

!/

!"$

!"# -$.

(1.5a) -$0

(1.5b)

4

Basic Specifications of Op Amps

R

R

-

+

+ vod

R

vo-

+ -

Vcm

R

+ Vcr

vo+

-

Figure 1.2 Test circuit used to measure the CMRR for a fully differential op amp.

By substituting (1.5a) and (1.5b) into (1.2a) and simplifying the result, we get !"#

1,+ 2 1++ 2

!"$

-$.

-$0

(1.6)

Now when the input voltage of -$0 is changed by 3-$0 , the terms of !"$ and -$. have no variation and thus we have 3!"$ 3-$. . That gives 3!"#

Since

##

1,+ 2 1++ 2

3-$0

(1.7)

, we have 34 +

34,5

,+

++

67889:

(1.8)

It should be emphasized that the gain of $# is not zero only when the mismatches in the op amp circuit are considered. As a result, we have to perform an ac analysis for several Monte Carlo simulation runs and obtain the corresponding voltage gain of 3!"# 3-$0 for each run. Since the amount of the mismatch changes in each run, we get various voltage gains whose mean value can be used to calculate the typical &''() . As an example, in a fully differential op ;< = >? as the mean amp, 100 runs of Monte Carlo analysis give 3!"# 3-$0 value of the data with a standard deviation of @ A = >? and thus for this op amp

1.1 Op Amp Parameters

5

the typical value of the CMRR becomes ;< = >?. The worst-case value could reach B >? in the range of C@. In an op amp with single-ended output the output voltage is represented by !"

#0 !%#

$0 !%$

(1.9)

where #0 and $0 are differential-mode and common-mode voltage gains, respectively. Here CMRR is defined as &''DE

*

+5 ,5

*

(1.10)

where &''DE indicates the CMRR of a single-ended output op amp. As it will be shown in the next chapters, in a fully differential op amp a high CMRR is achievable by implementing a fully symmetrical circuit to minimize $# . In a single-ended one, even when the op amp has a perfect symmetry in an ideal condition, the CMRR would be limited by the output resistance of the tail current source used in the differential pair. One method to measure the CMRR for a single-ended output op amp is shown in Figure 1.3 [3]. In this circuit we have ! -$0 and ! / !" -$0 . Since !%# ! ! / and !%$ ! !/ , by substituting these relationships into (1.9), we can write the output voltage as !"

#0 !"

$0

F-$0

G

(1.11)

Rearranging (1.11), we obtain the transfer function as ,5 1,5 +5 / 2

4,5

(1.12)

Noting that #0 H $0 , we see that the inverse of the obtained gain in (1.12) approximately gives the &''DE . Offset voltage. The device mismatches in the input stage have the most

Vcm

+ −

−

vo

+ + V − cm

Figure 1.3 Measurement of the CMRR parameter for a single-ended output op amp.

6

Basic Specifications of Op Amps

contribution in this parameter. It is interesting that the nonzero common-mode voltage gain of an op amp also contributes to the input offset voltage [4]. To see that, from (1.9) for !%# , we have !" $0 !%$ . This means the op amp output voltage varies in response to the input common-mode voltage variation in spite of the fact that the differential mode of the input voltage has no variation. In this situation, the op amp can be thought of as an ideal op amp in a sense that it just reacts to the differential mode of the input voltage and the effect of the input common-mode changes is attributed to an equivalent differential input voltage with the value of -%HIJ !" #0 or -%HIJ $0 !%$ #0 . Therefore in an op amp with nonzero common-mode voltage gain, the voltage of -%HIJ -%$ &'' is added to the input-referred offset voltage. The main parameters of an op amp that affect the offset voltage will be discussed in more detail in the next chapters. Figure 1.4 represents two circuits to measure the offset voltage of single-ended and fully differential op amps. Both op amps are configured as a voltage follower without any external input. The left-side circuits depict the real op amps including mismatches with finite CMRR. All nonideal effects that create the offset voltage such as mismatches and nonzero common-mode voltage gains of $0 and $# have been modeled by a dc voltage source denoted by -"K that is placed in series with the input of an ideal op amp. Hence, the output voltage relationships for two types in an ideal case are !" #0 !%# and !"# ## !%# . Summing voltages around the loop from the output to the input yields !%# -"K !" for the single-ended op amp and !%# -"K !"# for the other one. Substituting these relationships into the corresponding equations of the output voltages gives us the offset voltages as Real includes mismatches Ideal

−

−

vid +

vo

+ Vos

vo

+

+ −

(a) Real includes mismatches Ideal +

+

-

+ vod -

vid + Vos

+ −

−

−

+

+

-

+ vod -

(b)

Figure 1.4 Test circuits for (a) single-ended (b) fully differential op amp offset voltage.

1.1 Op Amp Parameters

7

-"K ## !"HDE -"K #0 ## for single-ended and #0 and !"H() fully differential types, respectively. Since #0 H ## , the output voltages of both circuits nearly represent the offset voltage. It should be pointed out that similar to the method used for measuring CMRR of a fully differential op amp, the op amp offset voltage can be obtained by running several Monte Carlo analyses on the circuits of Figure 1.4 and taking the standard value of the data as the op amp offset voltage. In the absence of systematic errors the mean value of the offset voltage is almost zero. Frequency bandwidth. The open-loop voltage gain of an op amp begins to drop as frequency increases. This happens because of internal parasitic capacitances in the op amp circuit. The bandwidth parameter is important because by dropping the op amp voltage gain, the closed-loop gain would not be independent of the op amp parameter anymore. In fact, the frequency bandwidth expresses how fast an op amp can follow the time variations in the input signal. It is obvious that to amplify fast signals we need to employ an op amp with adequate large bandwidth in such a way that it can provide enough loop gain at maximum operating frequency. The speed performance of an op amp is usually measured by the unity gain bandwidth parameter denoted by LM , as illustrated in Figure 1.5. As its name suggests, LM is a frequency at which the magnitude of the gain reaches unity. When an op amp is used as a voltage follower in a negative-feedback loop, it might suffer from the instability problem at frequencies near LM . Thus the op amp should be properly designed to have an acceptable amount of stability in the frequency domain [5]. Slew rate. This parameter is used to express the time speed limitation of an op Av(jω) Av0

ωp2 0

ωp1

Figure 1.5 Op amp voltage gain versus frequency.

ωu

ω

8

Basic Specifications of Op Amps vi(t)

Input step voltage

V

vo(t) vi(t)

t

0

− +

vo(t)

Output response

V (a)

tsettle

tslew

t

0 (b)

Figure 1.6 (a) Voltage follower, and (b) time response of voltage follower to input step voltage.

amp output. When an op amp is placed in a negative-feedback loop and a rather large-signal is applied to its input, the output cannot follow the rapid changes in the input signal. This is another speed limitation in op amps that is raised in conjunction with the large-signal behavior of op amps. Indeed, unity gain bandwidth indicates the limitation of an op amp to follow the fast input signals with very small amplitude while slew rate is considered an index of op amp largesignal time response [6]. In some applications such as pipeline analog-to-digital converters, both parameters play a key role in determining the maximum achievable speed for the converter [7]. The response of a voltage follower to a step voltage applied as input is plotted in Figure 1.6(b). As it can be seen, the output time response consists of two parts. The first part is the time duration that the output voltage changes from its initial value to approach its final level. This part is associated with the limited op amp slew rate. The second part starts when the difference between input and output voltages is small. Now the small-signal frequency response of the op amp determines how long it takes to reach its steady state. This time, known as settling time, is illustrated in Figure 1.6(b). Noise. A complementary metal oxide semiconductor (CMOS) op amp is made of several numbers of n-type MOS (NMOS) and p-type MOS (PMOS) transistors. Channel thermal noise and flicker noise are two main noise sources in each MOS device [8]. The total noise generated by each device is represented by two generally correlated noise voltage and noise current generators at the input of an op amp. Flicker noise has a higher level of energy at low frequencies while thermal noise has a flat spectrum in the frequency domain. The variation of the spectral density of the input-referred noise voltage including both flicker and thermal noises is plotted in Figure 1.7. In this plot the thermal noise and flicker

1.1 Op Amp Parameters

9

Vn 2

f Kf

f

4kTReq

0

f

fc

Figure 1.7 Spectral of input-referred noise voltage.

noise asymptotes intersect each other at a frequency called the flicker noise corner frequency that is denoted by $ . In submicron CMOS technology, due to some physical effects such as the hot electron effect, the level of the thermal noise in the MOS device increases. According to Figure 1.7, the part of the frequency band that is less than $ is mostly influenced by the flicker noise. At the frequencies near zero there is no noticeable difference between the input offset voltage and the flicker noise at the input. Power supply rejection ratio. The amount of supply noise or any other disturbances on the supply rail that can find its way to the op amp output depends on this parameter [9]. Mathematically the power supply rejection ratio (PSRR) in an op amp is defined as NO''

P +P Q

(1.13)

where # is the differential voltage gain of the op amp and R is the voltage gain from each supply to the op amp output. Supposing the op amp as a linear circuit, we express its output voltage as a linear combination of the differential input voltage and the noise voltage on the supply !"

# !%#

R !R

(1.14)

In (1.14) the first term is the desirable signal component and the second one indicates the amount of supply noise at the output. Indeed, PSRR represents the ratio of the desired signal to the supply noise at the op amp output. Since op amps have two supply rails, two parameters of NO'' and NO''/ are usually defined

10

Basic Specifications of Op Amps

in which the corresponding voltage gain from positive and negative supply is denoted by R and /R , respectively. In an integrated analog mixed-mode circuit where different analog and digital blocks are fabricated on the same chip, special attention should be paid to the PSRR parameter of op amps used in the circuit [10]. For example, if the PSRR of an op amp is not good enough, any existent noise on the supply rail such as digital noise created by the system clock can reach the op amp output and amplified by the next stages can easily corrupt the quality of the ultimate output signal. In addition, the behavior of PSRR at higher frequencies is also important. In fact, the magnitude of this parameter at high frequencies determines the amount of high-frequency supply noise that impacts on the op amp output signal. In practice, PSRR can be measured by employing the circuit shown in Figure 1.8. Assuming a finite differential voltage gain of # for op amp and denoting the voltage gain from supply to the output by R , we can write !"

R !R

# !"

(1.15)

Rearranging (1.15), we have

Since

#

!"

+

Q

!R

(1.16)

, we can obtain the PSRR as NO''

Q

(1.17)

The circuit in the path from positive supply to the output is generally different from the other path from negative supply to the output; thus, two different PSRR parameters are usually defined for two op amp supply rails.

+ vo -

−

vo

Ad

+ + vp -

Figure 1.8 Circuit used to measure PSRR.

1.1 Op Amp Parameters

11

PSRR in a fully differential op amp has a similar relationship given in (1.13) in which # is replaced with ## . It should be pointed out that if the circuit of the fully differential op amp has perfect symmetry in an ideal case, the noise of supply appears equally on both outputs and as a result there is no differential output voltage. In reality, device mismatches in the op amp circuit reveal their contributions as nonzero differential output voltage. Thus the mismatch is responsible for nonzero PSRR in fully differential op amps. This means that to measure PSRR we have to follow the procedure that was given to measure &''() . We can use the circuit of Figure 1.2 in which an ac voltage source is placed in series with the supply while just common-mode voltage reference -$. is applied to the input. Repeating the given method for CMRR calculation, we obtain 3!"#

Q 1++ 2

3!R

(1.18)

Equation (1.18) represents the change in the differential output owing to the variation in the supply voltage. The parameter R denotes the voltage gain from supply to the output. Since ## , from (1.18), PSRR is given by NO''

++ Q

3S + 3SQ

(1.19)

By performing Monte Carlo analysis we can obtain the voltage gain from supply to the differential output in different runs. Such simulation on the previous example given for CMRR calculation produces the result of 3!"# 3!R A T >? as the mean value of data that based on (1.19) gives NO'' A< T >? while its standard deviation is @ ; >?. This result reveals that in the op amp of our example, the supply noise compared to the input common-mode voltage variation is more effectively passed to the op amp output in the presence of mismatches.

12

Basic Specifications of Op Amps

Table 1.1 Some Main Parameters of a Typical CMOS Op Amp Parameter Name DC voltage gain

Input commonmode range

Parameter Symbol 4

ICMR

Relationship

Value in Ideal Case

Typical Value in a Real Op Amp

Unit

Depends on structure

Infinity

40-120

dB

-%$H0UV

-%$H0UV

CMRR

Fully differential * ++ *

Offset voltage

-"K

Depends on mismatches in threshold voltage and sizing

Unity gain bandwidth

LM

Commonmode rejection ratio

,+

Single-ended output op amp * +5*

V

Infinity

> 80

dB

Zero

80

,5

In most single-stage op amps X0H%Y Z

Slew rate

SR

Usually as W

Power supply rejection ratio

PSRR

P

Inputreferred noise voltage

-))

= W &' -)) (e.g., in a simple NMOS input op amp)

-Y

+5 Q

Z

P

Channel thermal noise and flicker noise referred to the input

Zero

^

`ab ^ _`ab ;

[ \] dB

c[ d`a

1.2 Conclusion

1.2

13

Conclusion

In this chapter, several important dc and ac parameters of op amps were introduced and some methods were presented that can be used to measure these parameters. The discussed parameters are associated with both single-ended output and fully differential op amps. We have summarized some main parameters of a typical CMOS op amp that were briefly discussed in this chapter as illustrated in Table 1.1. It is worth keeping in mind that the exact relationship for each parameter in this table depends extensively on the particular structure used in the op amp circuit that will be the subject of the next chapters. The given numerical data for some parameters indicate typical values that are usually observed in currently designed CMOS op amps.

References [1]

Huijsing, J., Operational Amplifiers: Theory and Design, Second Ed, Springer, 2011.

[2]

Baker, R. J., CMOS: Circuit Design, Layout, and Simulation, Third Ed, John Wiley & Sons, 2010.

[3]

Allen, P. E., Holberg, D. R., CMOS Analog Circuit Design, Second Ed, Oxford University Press, 2002.

[4]

Mancini, R., Carter, B., Op Amps for Everyone, Third Ed, Elsevier Inc., 2009.

[5]

Ivanov, V., Filanovsky, M., Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology, Kluwer, 2004.

[6]

Baher, H., Signal Processing and Integrated Circuits, John Wiley & Sons, 2012.

[7]

Plassche, R., V., D., CMOS Integrated Analog-to-Digital and Digital-to-Analog, Second Ed, Boston, Kluwer Academic Publisher, 2003.

[8]

Bhattacharyya, A. B., Compact MOSFET Models for VLSI Design, John Wiley & Sons, 2009.

[9]

Shepherd, P. R., Integrated Circuit Design, Fabrication and Test, McGraw-Hill, 1996.

[10] Gejji, V. P., Analog and Mixed Mode VLSI Design, PHI Learning Private Limited, New Delhi, 2011.

Chapter 2 CMOS Technology and Physics A part of the limitation in the performance of a CMOS circuit is related to how it is implemented. Therefore a comprehensive perception of the CMOS circuit fabrication and the required steps to get the final desirable circuit can significantly aid in achieving a successful design. Furthermore, the advanced semiconductor industry necessitates a close and tight collaboration between circuit designers and process engineers, who need to understand their languages in order to exchange information about possible technological capabilities and also existent constraints in the fabrication process. In this chapter, we briefly describe the main sequence of steps that are followed in the fabrication of an MOS transistor. Next, we introduce the electric current equation for this kind of transistor and based on the physical operation we present a complete small-signal model of the device. In the given analysis we will refer to some physical effects such as short-channel behavior, and subthreshold operation region and their impact on the circuit design. Interested readers are referred to the references at the end of the chapter for deeper discussions.

2.1

Basic Processes in MOS Transistor Fabrication

In an n-well process in which all PMOS transistors are to be put inside the n-wells, the first step is to create an n-well inside the substrate of a p-type. The ion implantation technique is usually used to create an n-well region. The next step is to create isolation areas between adjacent transistors by growing a thick oxide layer under which an extra ion implantation called channel-stop is done to increase the effective threshold voltage of this area. After applying some trimming on the threshold voltage of the active area, the gate pattern is defined and then the source/drain junctions and also p-substrate and n-well contacts are formed by two individual ion implantations for two NMOS and PMOS devices. After source/drain ion implantation, a thermal process needs to be done and thereby the damaged lattice structure is fixed. This process is known as annealing. Because of the thermal process in the annealing, the impurity atoms in these areas penetrate

15

16

CMOS Technology and Physics

underneath the gate electrode due to lateral diffusion. The overlapped part of the gate with the extended part of the source/drain regions creates an overlap parasitic capacitance between the source/drain and gate terminals. These capacitances, especially one that is formed between the gate and drain, can affect significantly the frequency response of the circuits particularly in analog designs. Figure 2.1 summarizes the main steps mentioned above to fabricate two types of MOS devices. The subject of CMOS technology and the fabrication process can be found in [1-5] in much more detail.

Gate Oxide sio2

Creation of n-well in p-substrate

(1)

n-well p-substrate

Gate Oxide

Channel-stop and threshold adjust implant and growth of field oxide

Field Oxide sio2 Channel-Stop

(2)

n-well p-substrate

Gate Oxide

Deposition of polysilicon gate of NMOS and PMOS devices

Field Oxide sio2 Channel-Stop

(3)

n-well p-substrate

Gate Oxide

Implantation of source, drain, and n-well contacts using two individual masks in two steps for NMOS and PMOS devices

n+

(4)

Figure 2.1 Main steps of MOS device fabrication.

n+

p+

p+

S/D of PMOS S/D of NMOS

p-substrate

n-well

n+

Field Oxide sio2 Channel-Stop n-well ohmic contact

2.2 Principles of MOS Transistor Functioning

2.2

17

Principles of MOS Transistor Functioning

Shown in Figure 2.2 is the cross-section view of an NMOS transistor. When a positive voltage is applied to the gate, since the majority carries of the substrate are the holes, they are repelled toward the bulk and as a result, a charge space of the negative ions leaves behind at the surface. In device physics this operating area of the device is known as the depletion mode. By increasing the gate voltage in the positive direction the proper condition is provided for the majority carriers in the source region to be injected into the substrate. More positive gate voltage causes growth of electrons and at the same time reduction of the number of holes. This ultimately leads to inverting the type of the semiconductor from p-type to n-type at the surface. For a certain level of the gate-source voltage, the density of electrons in the created inversion layer would be that of the substrate holes. In this situation the transistor operates at the edge of a state called strong inversion. The corresponding gate-source voltage that puts the device at the edge of the strong inversion condition is known as the threshold voltage and is denoted by -e . For -fD -e , the electrons concentration of the inversion layer is less than that of the substrate holes and the transistor is in a state called weak inversion. This operating area is known as the subthreshold region. In the following sections we deal with the MOS functioning in these two operating areas. 2.2.1 MOS Transistor Operating in Saturation Region In the presence of the conductive layer in a strong inversion state, an applied voltage between the drain and source creates an electric field along the channel and makes the current flow from the source to the drain. By utilizing Ohm’s law and writing the channel conductivity in terms of inversion charge g%Y , it is shown that [6] for a long-channel device the drain current equation in the triode region can be approximated by a quadratic relationship that is a function of the gateG

S

D

n+ FOX

FOX n+ inversion layer p_substrate Figure 2.2 Cross section of an NMOS device.

18

CMOS Technology and Physics

source and drain-source voltages. W)

hY

i "V Z j

-fD

-e -)D

2 4:k

l

(2.1)

where hY is the electron mobility in the inversion layer, "V m"V n"V is the gate oxide capacitance per unit area with m"V as the oxide permittivity and n"V as the gate oxide thickness, and o and p are the transistor channel width and length, respectively. At a given -fD -e , increasing the drain-source voltage causes the density of the free electrons of the inversion layer at the drain side to decrease, and ultimately for -f) -e the electron charges at drain almost disappear such that the device is put at the edge of the saturation region. The certain value of the drain-source voltage at which the device is at the edge of saturation will be -)D HKUq

-fD

-e

(2.2)

For -)D -)D HKUq , the depletion region of the drain-bulk junction extends toward the source. The excess voltage of -)D -)D HKUq extends across the depletion region of the drain to the bulk junction and the voltage drop across the inversion layer is kept on -)D HKUq . This situation is very similar to the behavior of a bipolar junction transistor (BJT) operating in an active forward region in which the major part of the collector to emitter voltage drops across the reverse-biased collector-base junction and a small part of the total voltage drops across the forward-biased baseemitter junction. To make clear the operation of the MOS device in saturation, the drain-bulk junction and the inversion layer can be modeled by the series connection of a reverse-biased diode indicating the drain-bulk junction and a resistor representing the inversion layer resistance, as illustrated in Figure 2.3. For a given constant -fD , -)D HKUq -fD -e is constant and thus the drain current is fixed. In practice, by increasing the drain-source voltage, the voltage of

VGS=cte

VDS

+

D

+ S

G

VDS-VDS,sat

D

+

VDS n+ FOX

FOX n+

Rch

VDS,sat

-

L p_substrate

Leff

∆L

Figure 2.3 MOS operation in a saturation region.

ID

S

2.2 Principles of MOS Transistor Functioning

19

-)D -)D HKUq across the drain to bulk junction increases, which results in extending the depletion area toward the source region. This causes the effective length of the inversion layer to decrease, and as a result, the inversion layer resistance slightly reduces. This effect leads to gradually increase the drain current, which is known as channel length modulation. This phenomenon shows itself as a small positive slope on the MOS output characteristic, as depicted in Figure 2.4. The drain current equation including the channel length modulation effect is a quadratic equation in which channel length is replaced by an effective length as

where pI junction [7]

p

W)

hY

3p

tJw

-fD

i "V Z rss

-e

(2.3)

-)D HKUq

(2.4)

3p with 3p as the depletion region width of the one-sided drain uv

vxy

-)D

The slope of the curve shown in Figure 2.4 in saturation is denoted by X#K and can be calculated by taking the derivation of (2.3) in terms of implicit variable -)D X#K

z{:

z4:k

z{: zZrss

zZrss z4:k

(2.5)

Using (2.3) and (2.4) and after some simple manipulations on (2.5), we have X#K |W) where the parameter | defined as ID

VGS=cte

slope=gds

0

VDS,sat

Figure 2.4 MOS characteristic in saturation with channel length modulation effect.

VDS

20

where }#K

CMOS Technology and Physics

| }#K €~ pI t-)D

-)D HKUq •

(2.6)

F

(2.7)

• mK ‚ƒKM„ . Supposing 3p … p, (2.6) can be approximated as |†

‡+v

Zt4:k /4:k Hvˆ‰

‡+v Z

G

The parameter X#K is the dynamic conductance between drain and source terminals of an MOS device and plays an important role in all MOS amplifiers. In fact, for a given MOS transconductance, the maximum achievable voltage gain is determined by this parameter. In a CMOS current source, high output resistance is achievable if the exploited MOS devices have minimum possible |. For a particular drain current, a practical way to minimize | is to use the maximum possible channel length for MOS devices and also to increase the drain-source biasing voltage based on (2.7). It is interesting that PMOS transistors at the same channel length and drain biasing conditions have usually less X#K in comparison to their NMOS counterparts. This is because PMOS devices are fabricated inside the n-well and doping concentration of the n-well is usually greater than the impurity density in the p_substrate of NMOS devices. Consequently at the same condition in terms of channel length and biasing condition, }#K is smaller for the PMOS device. As an example, in a 0.25-\Š CMOS technology the impurity concentration in the Œ p_substrate is ƒKM„ ?) Unity gain bandwidth: M ÷ = _`a Phase margin: N& ÷ < ° Slew rate: O' ÷ [ \] Load capacitance: Z = µ.

The design procedure begins by choosing $ T Z µ. Assuming the ° zero has been moved to infinity, for N& ÷ < , we have LR X0ê Z ÷ dCLM . With the given data, we need to have X0ê ÷ B Š¶ [. From LM ÷ X0 $ , we obtain X0 ÷ < A \¶ [. Based on the given slew rate, from O' ÷ W $ , the tail current should be greater than \¶. The minimum required aspect ratio of the input transistors is determined from X0 ¾•hY "V o p H W ÷ < A \¶ [. Supposing that ¾ ;, we obtain the aspect ratio of the input transistors as o p H ÷ A. Such large sizing with low level of drain current for these transistors causes these devices to work in subthreshold. As discussed in Chapter 2, the transconductance in such an operating area is independent of the device < A \¶ [, W) should be sizing and given by X0 W) --q¦ . For X0 greater than C \¶. In order to make sure that input transistors work in saturation, their drain currents should be larger than C \¶. By choosing W) C \¶,

70

CMOS Single-Ended Output Op Amp

recalculation of transconductance gives o p H ÷ C? Now we choose the compensation resistance '$ such that the zero 4 and the second pole, LR , cancel each other out. To this end, we calculate the A œ . Repeating simulation resistance from '$ X0ê Z $ while adding '$ , we obtain N& B