Design of Analog CMOS Integrated Circuits 9780071188159, 0-07-118815-0

Table of contents :
Preface......Page 10
Acknowledgments......Page 12
Contents......Page 16
1.1 Why Analog?......Page 22
1.3 Why CMOS?......Page 27
1.5.2 Robust Analog Design......Page 28
2 Basic MOS Device Physics......Page 30
2.1.2 MOSFET Structure......Page 31
2.1.3 MOS Symbols......Page 33
2.2.1 Threshold Voltage......Page 34
2.2.2 Derivation of I/V Characteristics......Page 36
2.3 Second-Order Effects......Page 44
2.4.1 MOS Device Layout......Page 49
2.4.2 MOS Device Capacitances......Page 50
2.4.3 MOS Small Signal Model......Page 54
2.4.4 MOS Spice models......Page 57
2.4.5 NMOS versus PMOS Devices......Page 58
2.4.6 Long-Channel versus Short-Channel Devices......Page 59
Problems......Page 60
3.1 Basic Concepts......Page 68
3.2.1 Common-Source Stage with Resistive Load......Page 69
3.2.2 CS Stage with Diode-Connected Load......Page 74
3.2.3 CS Stage with Current-Source Load......Page 79
3.2.4 CS Stage with Triode Load......Page 80
3.2.5 CS Stage with Source Degeneration......Page 81
3.3 Source Follower......Page 88
3.4 Common-Gate Stage......Page 97
3.5 Cascode Stage......Page 104
3.5.1 Folded Cascode......Page 111
3.6 Choice of Device Models......Page 113
4.1 Single-Ended and Differential Operation......Page 121
4.2 Basic Differential Pair......Page 124
4.2.1 Qualitative Analysis......Page 125
4.2.2 Quantitative Analysis......Page 128
4.3 Common-Mode Response......Page 139
4.4 Differential Pair with MOS Loads......Page 145
4.5 Gilbert Cell......Page 147
5.1 Basic Current Mirrors......Page 156
5.2 Cascode Current Mirrors......Page 160
5.3 Active Current Mirrors......Page 166
5.3.1 Large-Signal Analysis......Page 170
5.3.2 Small-Signal Analysis......Page 172
5.3.3 Common-Mode Properties......Page 175
6.1.1 Miller Effect......Page 187
6.1.2 Association of Poles with Nodes......Page 190
6.2 Common-Source Stage......Page 193
6.3 Source-Follower......Page 199
6.4 Common-Gate Stage......Page 204
6.5 Cascode Stage......Page 206
6.6 Differential Pair......Page 208
Appendix A: Dual of Miller's Theorem......Page 214
7.1 Statistical Characteristics of Noise......Page 222
7.1.1 Noise Spectrum......Page 224
7.1.2 Amplitude Distribution......Page 227
7.1.3 Correlated and Uncorrelated Sources......Page 228
7.2.1 Thermal Noise......Page 230
7.2.2 Flicker Noise......Page 236
7.3 Representation of Noise in Circuits......Page 239
7.4 Noise in Single-Stage Amplifiers......Page 245
7.4.1 Common-Source Stage......Page 246
7.4.2 Common-Gate Stage......Page 249
7.4.3 Source Followers......Page 252
7.4.4 Cascode Stage......Page 253
7.5 Noise in Differential Pairs......Page 254
7.6 Noise Bandwidth......Page 260
8.1 General Considerations......Page 267
8.1.1 Properties of Feedback Circuits......Page 268
8.1.2 Types of Amplifiers......Page 275
8.1.3 Sense and Return Mechanisms......Page 277
8.2.1 Voltage-Voltage Feedback......Page 279
8.2.2 Current-Voltage Feedback......Page 284
8.2.3 Voltage-Current Feedback......Page 287
8.2.4 Current-Current Feedback......Page 290
8.3.1 Two-Part Network Models......Page 291
8.3.2 Loading in Voltage-Voltage Feedback......Page 293
8.3.3 Loading in Current-Voltage Feedback......Page 296
8.3.4 Loading in Voltage-Current Feeback......Page 299
8.3.5 Loading in Current-Current Feeback......Page 302
8.3.6 Summary of Loading Effects......Page 304
8.4 Effect of Feedback on Noise......Page 305
9.1.1 Performance Parameters......Page 312
9.2 One-Stage Op Amps......Page 317
9.3 Two-Stage Op Amps......Page 328
9.4 Gain Boosting......Page 330
9.5 Comparison......Page 334
9.6 Common-Mode Feedback......Page 335
9.7 Input Range Limitations......Page 346
9.8 Slew Rate......Page 347
9.9 Power Supply Rejection......Page 355
9.10 Noise in Op Amps......Page 357
10.1 General Considerations......Page 366
10.2 Multipole Systems......Page 370
10.3 Phase Margin......Page 372
10.4 Frequency Compensation......Page 376
10.5 Compensation of Two-Stage Op Amps......Page 382
10.5.1 Slewing in Two-Stage Op Amps......Page 389
10.6 Other Compensation Techniques......Page 390
11.2 Supply-Independent Biasing......Page 398
11.3.1 Negative-TC Voltage......Page 402
11.3.2 Positive-TC Voltage......Page 403
11.3.3 Bandgap Reference......Page 405
11.4 PTAT Current Generation......Page 411
11.5 Constant-Gm Biasing......Page 413
11.6 Speed and Noise Issues......Page 414
11.7 Case Study......Page 418
12.1 General Considerations......Page 426
12.2.1 MOSFETS as Switches......Page 431
12.2.2 Speed Considerations......Page 435
12.2.3 Precision Considerations......Page 438
12.2.4 Charge Injection Cancellation......Page 442
12.3 Switched-Capacitor Amplifiers......Page 444
12.3.1 Unity-Gain Sampler/Buffer......Page 445
12.3.2 Noninverting Amplifier......Page 453
12.3.3 Precision Multipl-by-Two Circuit......Page 459
12.4 Switched-Capacitor Integrator......Page 460
12.5 Switched-Capacitor Common-Mode Feedback......Page 463
13.1.1 General Considerations......Page 469
13.1.2 Nonlinearity of Differential Circuits......Page 473
13.1.3 Effect of Negative Feedback on Nonlinearity......Page 475
13.1.4 Capacitor Nonlinearity......Page 478
13.1.5 Linearization Techniques......Page 479
13.2 Mismatch......Page 484
13.2.1 Offset Cancellation Techniques......Page 492
13.2.2 Reduction of Noise by Offset Cancellation......Page 497
13.2.3 Alternative Definition of CMRR......Page 499
14.1 General Considerations......Page 503
14.2 Ring Oscillators......Page 505
14.3 LC Oscillators......Page 516
14.3.1 Crossed-Coupled Oscillator......Page 520
14.3.2 Colpitts Oscillator......Page 523
14.3.3 One-Port Oscillators......Page 526
14.4 Voltage-Controlled Oscillators......Page 531
14.4.1 Tuning in Ring Oscillators......Page 533
14.4.2 Tuning in LC Oscillators......Page 542
14.5 Mathematical Model of VCOs......Page 546
15.1.1 Phase Detector......Page 553
15.1.2 Basic PLL Topology......Page 554
15.1.3 Dynamics of Simple PLL......Page 563
15.2.1 Problem of Lock Acquisition......Page 570
15.2.2 Phase/Frequency Detector and Charge Pump......Page 571
15.2.3 Basic Charge-Pump PLL......Page 577
15.3.1 PFD/CP Nonidealities......Page 583
15.3.2 Jitter in PLLs......Page 588
15.4 Delay-Locked Loops......Page 590
15.5.1 Frequency Multiplication and Synthesis......Page 593
15.5.2 Skew Reduction......Page 595
15.5.3 Jitter Reduction......Page 597
16.1 Scaling Theory......Page 600
16.2.1 Threshold Voltage Variation......Page 604
16.2.2 Mobility Degradation with Vertical Field......Page 606
16.2.3 Velocity Saturation......Page 608
16.2.5 Output Impedance Varoation with Drain-Source Voltage......Page 610
16.3 MOS Device Models......Page 612
16.3.1 Level 1 Model......Page 613
16.3.2 Level 2 Model......Page 614
16.3.3 Level 3 Model......Page 616
16.3.4 BSIM Series......Page 617
16.3.5 Other Models......Page 618
16.3.6 Charge and Capacitance Modeling......Page 619
16.4 Process Corners......Page 620
16.5 Analog Design in a Digital World......Page 621
17.1 General Considerations......Page 625
17.2 Wafer Processing......Page 626
17.3 Photolithography......Page 627
17.5 Ion Implantation......Page 629
17.7.1 Active Devices......Page 632
17.7.2 Passive Devices......Page 637
17.7.3 Interconnects......Page 645
17.8 Latch-Up......Page 648
18.1 General Layout Considerations......Page 652
18.1.1 Design Rules......Page 653
18.1.2 Antenna Effect......Page 655
18.2.1 Multifinger Transistors......Page 656
18.2.2 Symmetry......Page 658
18.2.3 Reference Distibution......Page 663
18.2.4 Passive Devices......Page 665
18.2.5 Interconnects......Page 674
18.2.6 Pads and ESD Protection......Page 678
18.3 Substrate Coupling......Page 681
18.4 Packaging......Page 687
References......Page 697
Index......Page 698