Circuit Design with VHDL (The MIT Press) [3 ed.] 0262042649, 9780262042642

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Circuit Design with VHDl Third Edition

Circuit Design with VHDl Third Edition

Volnei A. Pedroni

The M IT Press Cambridge, Massachusetts London, England

©

2020 Massachusetts Institute of Technology

All rights reserved. No part of this book may be reproduced in any form by any electronic or mechanical means (including photocopying, recording, or information storage and retrieval) without permission in writing from the publisher. This book was set in Stone Serif and Stone Sans by Westchester Publishing Services. Library of Congress Cataloging-in-Publication Data Names: Pectroni, Volnei A" author. Title: Circuit design with VHDL / Volnei A. Pedroni. Description: Third edition.1 Cambridge, MA : The MIT Press, [2019]1 Includes bibliographical references and index. Identifiers: LCCN 20180509411 ISBN 9780262042642 (hardcover ; alk. paper) Subjects: LCSH: VHDL (Computer hardware description language) 1 Electronic circuit design. System design. Classification: LCC TK7885.7 .1'43 20191 DDC 621.39/5--dc23 LC record available at https://lccn.loc.gov/2018050941

Contents

Preface

xv

Acknowledgments

xvii

Review of Combinational Circuits 1

1.1

Combinational Circuits

1.2

Fundamental Logic Gates

1.3

Chain-Type versus Tree-Type Structures

1.4

Examples of Combinational Logic Circuits

1.5

1.6

2

1.4.1

Multiplexer

1.4.2

Address Decoder

1.4.3

Parity Detector

1.4.4

Priority Encoder

1.4.5

Binary-to-BCD Converters

3 4

4 6 6 6

Examples of Combinational Arithmetic Circuits 1.5.1

Full-Adder Unit

10

10

1.5.2

Carry-Ripple Adder

1.5.3

Faster Adders (Manchester, Carry-Lookahead, and Kogge-Stone Tree)

11

1.5.4

Adder Arrays

1.5.5

Subtracters

1.5.6

lncrementer, Decrementer, and Two's Compiementer

1 .5.7

Parallel Multiplier

12 13

1.5.8

Comparators (Equality and Greater-than/Equal-to)

1.5.9

Arithmetic Logic Unit

Binary Arithmetic

14

14 14

IS

16

1.6.1

Carry B i t and Overflow Flag

1 .6.2

Unsigned Integer Arithmetic

1 .6.3

Signed Integer Arithmetic

1.6.4

Extension, Truncation, Rounding, and Saturation

1.6.5

Floating-Point Arithmetic

16 17 19 24

21

11

vi

2

Contents

Review of Sequential Circuits 2.1 2.2 2.3

Sequential Circuits Latches 29 Flip-Flops

29

29

31

2.4

Glitch Analysis and Prevention

2.5

Register Transfer Level of Abstraction

2.6

Initial Examples of Sequential Circuits 2.6. 1

2.7

Shift Registers

34 35 36

36

2.6.2

Synchronous Modulo-2N Counters

37

2.6.3

Synchronous Modulo-M Counters

38

2.6.4

Asynchronous Counters

2.6.5

Gray, Johnson, and One-Hot Counters

2.6.6

Signal Generators

38 39

41 41

2.6.7

Clock Dividers

2.6.8

Timers and Sequential Binary-to-BCD Converters

2.6.9

Tapped Delay Line

Clock Division

42

2.7.1

Common Clock Division Cases

2.7.2

Clock Division by Any Integer with Symmetric Phase

42

2.7.3

The Cost of Clock Division by an Even Integer

2.7.4

Breaking a Large Clock Divider into Smaller Serial Clock Dividers

2.8

Clock Multiplication and Phase-Locked Loops (PLLs)

2.9

Asynchronous Data and Synchronizers Clock-Domain Crossing

2.9.2

A Practical Example: Frequency Meters

2.9.3

Dealing with Reset

46

49 49

52

2.10

Clock Gating

2.11

Additional Examples of Sequential Circuits

53

2.1 1.2 Switch Debouncers

54 54

55

2.1 1.3 Reference-Value Generators 2.1 1.4 Pulse Width Modulator

58

59

2.1 1.5 Pseudo-Random Sequence Generators

60

2.1 1.6 Digital Finite Impulse Response (FIR) Filters 2.1 1.7 Digital Infinite Impulse Response (IIR) Filters 2.1 1.8 Serializer and Deserializer Circuits

Review of Finite State Machines

65

67

3.1

Finite State Machines

3.2

State Transition Diagram and Machine Types

67

3.3

Representing versus Implementing

70

68

43

44

48

2.9.1

2 . 1 1 . 1 One-Shot and Pulse-Capturer Circuits

3

41

41

61 64

46

vii

Contents

3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Moore-to-Mealy and Mealy-to-Moore Conversion Time Behavior of Moore versus Mealy Machines Choosing between Moore and Mealy Machines Transition Types

70 71 73

74

Incorrect State Transition Diagrams Safe State Machines

7S

78

Fundamental Hardware Architectures for FSMs Encoding Styles 79 Fundamental Design Technique for FSMs State Machine Categories Dealing with Time

78

79

82

83

Dealing with Repetitive States

85

Pointer-Based FSM Implementation Dealing with Recursivity

86

86

Number of Flip-Flops in FSMs

88

Examples of Category 1 (Regular) State Machines

88 3.19.1 Arbiter 89 3.19.2 Garage Door Controller 89 3.19.3 Datapath Control for a Greatest Common Divisor 90 3.20 Examples of Category 2 (Timed) State Machines 93 3.20.1 Car Alarm 93 3.20.2 Password Decoder 94 3.20.3 Serial Peripheral Interface for an AID Converter 95 3.21 Examples of Category 3 (Recursive) State Machines 96 3.21.1 SRAM Memory Interface 97 3.21.2 Datapath Controller for a Serial Multiplier 97 3.21.3 Reference-Value Definer with Embedded Debouncers 99

4

Review of Field Programmable Gate Arrays (FPGAs) 4.1 4.2 4.3 4.4 4.5 4.6

5

Programmable Logic Devices PLD Configuration Memories PAL and PLA Devices

104

GAL Devices

104 CPLD Devices 105 FPGA Devices 107

Introduction to VHDL 5.1 5.2 5.3 5.4

101 103

About VHDL

115

115

Translation of VHDL Code into a Circuit Design Flow

117

Commercial VHDL Tools

119

115

101

viii

Contents

5.5 5.6 5.7

5.8

RTL Design Approach

120 5.7.1 Assignment Symbols 120 5.7.2 Comments 120 5.7.3 Bit and Bit String 121 5.7.4 Integers 121 5.7.5 Character and Character String 5.7.6 Identifiers 122 5.7.7 Delimiters 122 5.7.8 Reserved VHDL Words 123

6.7 6.8 6.9

7

123

Naming an Entity Declaration ("The Design") Naming an Architecture Body Naming Constants

124

124

Naming Signals and Variables

125

Naming Functions and Procedures

126 127

Naming Types Naming Files

129

Design Units and Code Structure

129 130 Packages List in the Code 134 Entity Declaration 135 Architecture Body 138 Object Classes 138 6.6.1 Constant 139 6.6.2 Signal 140 6.6.3 Variable 141 6.6.4 File 142 Generics 143 Entity-Architecture Binding 145 Introductory VHDL Examples 145

Libraries and Packages

Predefined Data Types 7.1 7.2 7.3 7.4 7.5

122

Choosing Good Names for Your Design

Code Structure and Composition 6.1 6.2 6.3 6.4 6.5 6.6

119

Lexical Elements of VHDL

5.8.1 5.8.2 5.8.3 5.8.4 5.8.5 5.8.6 5.8.7 6

119

Concurrent versus Sequential Statements

153

Predefined VHDL Types Type Classes

153

154

Type Declarations

156

Subtypes 158 A Note on Operators and Attributes

159

125

124

ix

Contents

7.6

Study of Predefined Data Types

7.7 7.8 7.9

Access Types, File Types, and Protected Types

1S9 7.6.1 Standard Types 160 7.6.2 Standard-Logic Types 162 7.6.3 Unsigned and Signed Types 165 7.6.4 Fixed-Point Types 166 7.6.5 Floating-Point Types 168 7.6.6 Type real 170 Record Types 172 Aggregation, Concatenation, and Resizing

7.9.1 7.9.2 7.9.3

7.10

7.11 7.12 7.13

8

Data Aggregation

173 175 Resizing Data Arrays 175 Type Conversion 178 7.10.1 Automatic Conversion 178 7.10.2 Type Cast 179 7.10.3 Type-Conversion Functions 179 7.10.4 Strength-Stripping Functions 182 Type-Qualification Expressions 183 Additional Examples 183 Exercises 185 Data Concatenation

User-Defined Data Types 8.1 8.2

8.4

8.5 8.6 8.7

193

Review of Synthesizable Predefined Types

193

User-Defined Types

8.2.1 8.2.2 8.2.3 8.3

173 173

193 Integer Types 193 Enumeration Types Array Types

195

195

196 Building and Addressing Complex Array Types 8.3.1 Array Dimensionality 196 8.3.2 Predefined 10 Arrays 197 8.3.3 Building lOx 10 Arrays 197 8.3.4 Building 20 Arrays 198 8.3.5 Building 1Dx1Dx1D Arrays 199 8.3.6 Building 3D Arrays 199 Checking and Resetting Data Arrays 199 8.4.1 Zeroing Entire Data Arrays 200 8.4.2 Checking Whether Data Arrays Contain Only Zeros Classical Mistakes in Assignments 201 Additional Examples 204 Exercises 208

200

x

Contents

9

Operators and Attributes 9.1

9.2 9.3

9.4 9.5

9.6 9.7 9.8 10

213

Predefined Operators

213 9.1.1 Logical Operators 214 9.1.2 Arithmetic Operators 218 9.1.3 Comparison (Relational) Operators 223 9.1.4 Shift Operators 226 9.1.5 Concatenation Operator 227 9.1.6 Condition Operator 227 User-Defined Overloaded Operators 228 Predefined Attributes 229 9.3.1 Attributes of Scalar Types 229 9.3.2 Attributes of Array Types and Objects 230 9.3.3 Attributes of Signals 231 9.3.4 Attributes of Named Entities 231 User-Defined Attributes 232 Synthesis Attributes 234 9.5.1 State Machine Encoding Attributes 234 9.5.2 Safe State Machine Attributes 235 9.S.3 Keep-Logic Attribute 236 9.5.4 ROM and RAM Implementation Attributes 237 Group 237 Alias 238 239 Exercises

Concurrent Code

243

10.1 Concurrent Statements 243 10.2 The when Statement 246 10.3 The select Statement 248 10.4 The generate Statement 249 10.5 Component Instantiation Statements 252 10.5.1 Component Instantiation 252 10.5.2 Design Entity Instantiation 253 10.6 Avoiding Multiple Assignments to the Same Signal 256 10.7 Suggested Approaches for Arithmetic Circuits 259 10.8 Additional Examples and Exercises 264 11

Concurrent Code: Practice 11.1

265

Additional Design Examples Using Concurrent Code Example 11.1. Vectors Absolute Difference Calculator

265 265

Example 11.2. Programmable Combinational Delay Line (Structural) Example 11.3. Sine Calculator with Integers and ROM-Type Memory

268 270

xi

Contents

11.2

Exercises

273

Part 1: Combinational Logic Circuits

274

Part 2: Combinational Arithmetic Circuits

277

Part 3: With Component Instantiation (Structural Code)

12

Sequential Code 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13

13

283

Concurrent Code versus Sequential Code

283

Detecting Clock Transitions: e1k'event or rising_edge(e1k)? The process Statement The if Statement

288 291 The wait Statement 294 The loop Statement 295 The case Statement

The Sequential when and select Statements Signal versus Variable

297

298

More about the Updating Rule of Signals and Variables More about the Inference of Registers Rule The Problem of Combinational Loops

312 313

Additional Examples and Exercises

315

Additional Design Examples Using Sequential Code Example 13.2. Single-Switch Debouncer

318

Example 13.4. Sequential Square-Root Calculator Exercises

315

315

Example 13.3. FIR Filter with Fixed Coefficients

320 322

326

Part 1: Signal versus Variable Part 2: Combinational Circuits

326 330

Part 3: Counters and Clock Dividers Part 4: Timers and Associated Circuits Part 5: Synchronism Part 6: Shifters

Part 7: Controllers Part 9: Filters

330 332

337

339 340

Part 8: Serial Arithmetic Circuits

343

347

Part 10: With Component Instantiation (Structural Code)

14

Packages and Subprograms 14.1 14.2

301

307

Example 13.1. Generic Tree-Type Adder Array

13.2

284

285

Sequential Code: Practice 13.1

281

Package

349

349

Package with Generics

351

347

xii

Contents

14.3 14.4 14.5 14.6 14.7 14.8 14.9 15

Function Procedure

353 359

Function versus Procedure Summary

363

Subprogram with Generics and Generic Subprograms Overloaded Subprograms

Assert and Report Statements Exercises

364

366 367

369

The Case of State Machines

373

15.1 The Finite State Machine Approach 373 15.2 State Encoding Styles 375 15.3 VHDL for Regular (Category 1) State Machines 375 15.3.1 Hardware Architecture of Regular State Machines 376 15.3.2 Simple Moore-to-Mealy Conversion 376 15.3.3 VHDL Templates for Regular State Machines 378 15.4 VHDL for Timed (Category 2) State Machines 387 15.4.1 Hardware Architecture of Timed State Machines 387 15.4.2 VHDL Templates for Timed State Machines 388 15.5 VHDL for Recursive (Category 3) State Machines 395 15.5.1 Hardware Architecture of Recursive State Machines 395 15.5.2 VHDL Templates for Recursive State Machines 395 15.6 Summarizing (and Simplifying) Things 402 15.7 Exercises 402 16

The Case of State Machines: Practice 16.1 16.2 16.3 16.4

407

Design Examples of Regular (Category 1) State Machines

407 412 Design Examples of Recursive (Category 3) State Machines 416 Exercises 421 Part 1: Exercises with Regular FSMs 421 Part 2: Exercises with Timed FSMs 422 Part 3: Exercises with Recursive FSMs 425 16.5 Exercises with SPI, J'C, and LCD Jnterfaces 426 17

Design Examples of Timed (Category 2) State Machines

Additional Design Examples

427

17.1 Additional Design Examples 427 ExampJe 17.1. SPI Interface for an EEPROM Device (with FSM) 428 Example 17.2. SPI Interface for an EEPROM Device (with Pointer) 434 Example 17.3. J'C Interface for an AID Converter (with Pointer) 440 Example 17.4. J'C Interface for an AID Converter (with Pointer Built with FSM)

444

xiii

Contents

Example 1 7.5 Digital Watch with Liquid Crystal Display (LCD)

447

Example 1 7.6 VGA Video Interface for a Hardware-Generated Image Example 1 7.7 DVI Video Interface for a Hardware-Generated Image Example 1 7.8 TMDS 8B/lOB Encoder 1 7.2

Exercises

464

468

Part 1: Exercises with SPI Protocol

468

Part 2: Exercises with I'C Protocol

469

Part 3: Exercises with Alphanumeric LCD Part 4: Exercises with VGA Video Driver Part 5: Exercises with DVI Video Driver

18

471 472 473

Introduction to Simulation with Testbenches 18.1

Testbenches

18.2

Dealing with Time in VHDL

18.3

Stimuli Generation

475

475 476

478

18.4

Complete Testbenches

18.5

Practical Considerations on Functional and Timing Simulations

18.6

Dealing with Data Files

482 490

18.7

Running Simulation with Tel Scripts

18.8

Exercises

495

495

Appendix A: Vivado Tutorial

497

Appendix B: Quartus Prime Tutorial Appendix C: ModelSim Tutorial

511

521

Appendix D: Simulation Analysis and Recommendations Appendix E: Using Seven-Segment Displays with VHDL Appendix F: Serial Peripheral Interface Appendix H: Alphanumeric LCD Appendix I: VGA Video Interface Appendix J: DVI Video Interface

Appendix K: TMDS Link

541

545 551 555

559

Appendix L: Using Phase-Locked Loops with VHDL

563

Appendix M: List of Enumerated Examples and Exercises Bibliography 583

581

531 533

537

Appendix G: I'C (Inter Integrated Circuits) Interface

Index

454 458

571

489

Preface

This text offers a comprehensive coverage of VHDL and its applications to the design of digi­ tal circuits. It is a completely updated and expanded version of its highly successful first and second editions, now including all VHDL-200S constructs and several new features, such as an extensive review of digital circuits, RTL analysis, and a superior collection of VHDL design examples and exercises. It is suitable for undergraduate and graduate courses on VHDL and digital circuits design in the areas of electrical/computer engineering and computer science, in-house courses on VHDL and digital circuits design, and engineers and other VHDL prac­ titioners in the industry. The only background knowledge needed to follow the book is familiarity with basic digital logic concepts and circuits. Because of the tight combination of digital circuits analysis, detailed VHDL code, and industry-standard examples and exercises, this text is also recommended for digital VLSI courses and digital VLSI designers in general. Before entering VHDL (chapters 5-1S), a review of digital circuits is presented (chap­ ters 1-4), resulting in a self-contained text that allows the teaching of digital circuits design with VHDL using a single reference. To complete this self-containment, all tutorials needed for synthesis and simulation (with Xilinx and Intel FPGAs) are included in the appendixes. The review chapters cover all classes of digital circuits, which consist of combinational logic circuits, combinational arithmetic circuits, sequential circuits, and sequential circuits mod­ eled as finite state machines. A review of FPGAs is also included. Full VHDL-200S cover­ age is presented, while still keeping the text as concise as possible. The same acclaimed sequence of topics in the previous two editions was maintained, with updated descriptions and modern examples carefully planned to make the understanding of the language simple and enjoyable. Additionally, a clear separation (unusual elsewhere) between code that is for synthesis versus code that is for simulation is made. In summary, everything in chapters 5-1 7 is syn­ thesizable, while the topics that are specific for simulation are concentrated in chapter IS. The VHDL codes in the examples are always complete (also unusual elsewhere), and not just partial sketches. Moreover, simulation results and comments are also offered. The collections of examples and exercises were hugely expanded and include many not seen before in the literature. That was possible because of the review chapters, which present

xvi

Preface

the necessary background and, at the same time, keep it separated from the VHDL chapters, so that a neater and more profound coverage results. Further, an enormous effort was devoted to making the examples and exercises interesting to students, with very illustrative physical demonstrations, which are crucial for their motivation. Finally, RTL analysis and discussions on hardware optimization are also included in many of the examples and exercises in this edition of the book. For that, too, the review chapters were fundamental.

©

2020 Massachusetts Institute of Technology

All rights reserved. No part of this book may be reproduced in any form by any electronic or mechanical means (including photocopying, recording, or information storage and retrieval) without permission in writing from the publisher. This book was set in Stone Serif and Stone Sans by Westchester Publishing Services. Library of Congress Cataloging-in-Publication Data Names: Pectroni, Volnei A" author. Title: Circuit design with VHDL / Volnei A. Pedroni. Description: Third edition.1 Cambridge, MA : The MIT Press, [2019]1 Includes bibliographical references and index. Identifiers: LCCN 20180509411 ISBN 9780262042642 (hardcover ; alk. paper) Subjects: LCSH: VHDL (Computer hardware description language) 1 Electronic circuit design. System design. Classification: LCC TK7885.7 .1'43 20191 DDC 621.39/5--dc23 LC record available at https://lccn.loc.gov/2018050941

Acknowledgments

I am grateful to the many people, in so many countries, who helped to make the previous editions of the book so successful. Their comments (along the years) were carefully consid­ ered and incorporated into this new edition when appropriate. In particular, I am most grateful to the reviewers of this third edition for their professional comments and suggestions. Finally, my dearest thank you to my two electrical engineering sons, Bruno and Ricardo Pedroni, for the countless fun and productive technical discussions on the many aspects of this material.

©

2020 Massachusetts Institute of Technology

All rights reserved. No part of this book may be reproduced in any form by any electronic or mechanical means (including photocopying, recording, or information storage and retrieval) without permission in writing from the publisher. This book was set in Stone Serif and Stone Sans by Westchester Publishing Services. Library of Congress Cataloging-in-Publication Data Names: Pectroni, Volnei A" author. Title: Circuit design with VHDL / Volnei A. Pedroni. Description: Third edition.1 Cambridge, MA : The MIT Press, [2019]1 Includes bibliographical references and index. Identifiers: LCCN 20180509411 ISBN 9780262042642 (hardcover ; alk. paper) Subjects: LCSH: VHDL (Computer hardware description language) 1 Electronic circuit design. System design. Classification: LCC TK7885.7 .1'43 20191 DDC 621.39/5--dc23 LC record available at https://lccn.loc.gov/2018050941

1

Review of Combinational Ci rcuits

1 .1

Combinational Circuits

This chapter presents a review of combinational circuits and binary arithmetic. By definition, combinational circuits are those whose outputs depend solely on the pre­ sent inputs; in other words, the outputs do not depend on previous circuit states. A regular adder, for example, is combinational because the result of the present computation does not depend on previous computations. By contrast, sequential circuits (reviewed in chapter 2) are those for which previous circuit states matter. For example, a counter is sequential because the next state depends on the state at which the counter is now. Sequential circuits, except for rare cases (asynchronous-logic based systems, for example), are characterized by the presence of a clock signal, which does not occur in combinational circuits. Combinational circuits can be divided into logic and arithmetic combinational circuits. If sign matters, it is arithmetic; otherwise, it is logic. For example, AND gates and multiplexers are logic, while adders and most comparators are arithmetic. Notes:

1) About numeric values: In VHDL, a single bit is written in single quotes (examples: ' 0 ' , ' 1 ' ) , bit vectors are written in double quotes (examples: " 110", "00000"), and integers are written without quotes (examples: 110, 9,-255). For simplicity, quotes were omitted in the review chapters (1 to 4), but the reader will be able to easily determine the proper values from the context. 2) A bout signal and constant names: In the review chapters (1 to 4), short names were employed, which is particularly important for the figures. In the VHDL chapters (5 to 18), longer, more meaningful names are also employed, following the suggestions of section 5.8.

2

1 .2

Chapter 1

Fundamental Logic Gates

We start by briefly reviewing the ten fundamental logic gates, all included in figure 1 . 1 . For each gate, the figure shows the symbol, the boolean equation, and the construction using CMOS logic. CMOS stands for Complementary MOS because for each nMOS transistor (Le., an n-channel MOSFET) there is a pMOS transistor (a p-channel MOSFET). The former appears in the lower part of each circuit, while the latter is in the upper part. The former conducts (Le., is turned on) when a 1 (Le., a positive VOltage, like 1 .8V) is applied to its gate, while the latter conducts when a 0 (zero volts) is applied to it. Taking the inverter, for example, which is the simplest gate, Y= 0 occurs when a = 1 because then the nMOS transistor connects the output node to ground, while Y= 1 occurs when a= 0 because then the pMOS transistor connects the output node to the upper power supply rail, VDD• The next circuit is the NAND gate, here with two inputs, therefore with two nMOS tran­ sistors in series and two pMOS transistors in parallel; consequently, only when all inputs are high the output will be low, and that is the reason for its name. Its noninverting version, the AND gate, is shown next; it requires a full NAND plus an inverter, being therefore more space and power consuming, and also slower (the inverter adds extra propagation delay), than the NAND gate. An analogous behavior occurs in the NOR and OR gates, which are the mirrored versions of the NAND and AND gates, respectively. The next pair is formed by the XOR and XNOR gates. The former produces Y= 1 when the number of inputs that are high is odd, while the latter outputs Y= 1 when that number is even. For the particular case of two inputs, the XOR gate is used to detect whether the inputs are different, while the XNOR detects whether they are equal. The next gate is the regular buffer, used, for example, at the inputs and outputs of digital integrated circuits (in the connections between the chip's internal circuitry and the chip pins). At the input, it reconditions the incoming signal and is also responsible for voltage scaling; for example, many chips operate internally with IV logic, but the incoming pulses might employ other logic VOltages, like 1 .8Y, 2.SV, or 3.3V, leaving to the buffer the down conversion. At the output, the buffer must do the opposite; additionally, a stronger output (with higher current or fan-out capability) might be reqUired, which is usually achieved by means of cascaded stages of growing size, as illustrated in the figure. The next gate is the tri-state buffer. Note that when ena = 0 both transistors connected to the Y node are turned off, leaving that node literally in a "floating" condition. This allows that node to be connected to a wire shared by several circuits, as far as only one tri-state buffer is turned on at a time. An application example is in computer buses, which can then be shared by several peripherals. The final gate is a pass switch, which is somehow analogous to the tri-state buffer, but it is not buffered and can transfer even analog VOltages. Its construction consists simply of two transistors (nMOS and pMOS) in parallel. An alternative construction is to use just one

Review of Combinational Circuits

Inverter

y=a

�f'

0 1 0 1

0 0 o 1 1 0 1 1

1 1 1 0

y

0 1 1 0

'-j

8

-1

b'-j b-1

:D-y

y=(a+b)' 8 b Y o o 1 1

0 0 0 1

0 1 0 1

y=a+b b Y

8

1 0 0 0

0 o 1 1

0 1 0 1

0 1 1 1

' ' : � , � � � : : :j[):>-

y

Regular buffer

Tri-state buffer

8-{>-y

8V-Y

y

a'·b' y=8b+ · 8 b Y 0 o 1 1

0 1 0 1

8

8

1 b1

'-j

8

-1

y;;ena·a+ena'·Z

,

8

Transmission gate

a----