Assembly language programming for the 68000 9780130498274, 0130498270

Citation preview

fOR REfERENCE aNt y

ASSEMBLY

NGUAGE

P G FOR THE-Arillwlf' GiOO IEdw((JJlf'd COIl'WOIlD AVilfotrneffe u..og((JJU'

(IfIIJ

Prentice-Hall International, Inc.

OL 5018173 4 .

111111111111111111111111111111111111111111

Library of Congress Cataloging-in-Publication Data

Gill, Arthur (date) Assembly language programming for the 68000. Includes index. 1. Motorola 68000 (Microprocessor)-Programming. 2. Assembler language (Computer program language) I. Corwin, Edward (date) . II. Logar, Antonette (date) . III. Title. QA 76.8.M6895G55 1987 005.265 ISBN 0-13-{)49827-{)

86-15118

This edition may be sold only in those countries to which it is consigned by Prentice-Hall International. It is not to be re-exported and it is not for sale in the U.S.A., Mexico or Canada.

To our parents Editorial/production supervision: Linda Zuk Manufacturing buyer: Ed O'Dougherty

© 1987 by Prentice-Hall, Inc. A division of Simon & Schuster Englewood Cliffs, New Jersey 07632

All rights reserved. No part of this book may be reproduced, in any form or by any means, without permission in writing from the publisher. Printed in the United States of America 10

ISBN

9

8

7

6

5

0-13-049827-0

4

3

025

Prentice-Hall International (UK) Limited, London Prentice-Hall of Australia Pty. Limited, Sydney Prentice-Hall Canada Inc., Toronto Prentice-Hall Hispanoamericana, S.A., Mexico Prentice-Hall of India Private Limited, New Delhi Prentice-Hall of Japan, Inc., Tokyo Prentice-Hall of Southeast Asia Pte. Ltd., Singapore Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro Prentice-Hall, Inc., Englewood Cliffs, New Jersey

CONTENTS

PREFACE 1

vii

NUMBER SYSTEMS 1 1.1 Decimal-to-Binary Conversion, 1 1.2 Decimal-.to-Hexadecimal Conversion, 3 1.3 Binary-to-Decimal Conversion, 4 1.4 Hexadecimal-to-Decimal Conversion, 5 1.5 Hexadecimal-to-Binary Conversion, 6 1.6 Binary-to-Hexadecimal Conversion, 6 1.7 Binary and Hexadecimal Addition, 7 Exercises, 8

2

THE ORGANIZATION OF THE 68000 9 2.1 The Central Memory, 9 2.2 The Central Processor, 10 2.3 The Terminal and the Communication Chip, 12 2.4 The Line Clock, 14 Exercises, 14

3

REPRESENTA TlON OF NUMBERS AND CHARACTERS 3.1 2's Complement Representation, 15 3.2 Addition and Subtraction, 19 3.3 Character Representation, 20 3.4 Floating-Point Representation (Optional), 22 Exercises, 23

15

iii

CONTENTS

iv

4

INSTRUCTIONS AND ADDRESSING MODES

25

4.1 The Execution Cycle, 25 4.2 Addressing Modes, 26 4.3 Single-Operand and Double-Operand Instructions, 32 4.4 No-Operand Instructions, 42 4.5 Machine Language, 42 4.6 On the Contents of a Computer Word, 45 Exercises, 46

5

ASSEMBL Y LANGUAGE PROGRAMMING

48

5.1 Assembly Language versus Machine Language, 48 5.2 Assembly Language Directives, 49 5.3 Assembly Language Program Format, 52 5.4 Example 1: Echo Keyboard Input to Screen, 53 5.5 Example 2: Multiple Echo, 56 5.6 Coding Hints, 58 Exercises, 61

6

64

STACKS AND SUBROUTINES 6.1 Stacks, 64 6.2 Example: Backward Echo, 66 6.3 Subroutines, 66 6.4 Subroutine Call and Return, 69 6.5 Argument Transmission, 70 6.6 Nested Subroutines, 75 6.7 Recursive Subroutines, 79 6.8 Example-Tower of Hanoi, 81 6.9 Coroutines, 86 Exercises, 87

7

ARITHMETIC OPERA TlONS

92

7.1 Carry and Overflow Under Addition, 92 7.2 Carry and Overflow Under Subtraction, 94 7.3 Double-Precision Arithmetic, 95 7.4 The TST and CMP Instructions, 97 7.5 More on Branch Instructions, 98 7.6 Shift Instructions, 103 7.7 Example: ASCII-to-Binary Conversion, 105 Exercises, 111

CONTENTS

8

v

TRAPS AND INTERRUPTS

116

8.1 Traps, 116 8.2 Some Examples of Traps, 117 8.3 Program Traps, 119 8.4 Interrupts, 120 8.5 Why Use Interrupts?, 121 8.6 Priority Interrupts, 123 8.7 Timer Interrupts Using an MC68230 Parallel Interface and Timer (PI/T), 125 8.8 Example: Time Request, 126 Exercises, 130

9

ASSEMBLERS AND LINKAGE EDITORS

135

9.1 The Two-Pass Assembly Process, 135 9.2 Example of Assembler Listing, 138 9.3 Absolute and Relocatable Addresses, 138 9.4 The Linkage Editor, 140 9.5 Address Modification, 141 9.6 Global Symbols, 143 9.7 The Two-Pass Linkage Process, 143 9.8 Position-Independent Code, 145 Exercises, 146

10

ADVANCED ASSEMBL Y LANGUAGE TECHNIQUES 10.1 Macros, 150 10.2 Macro Definitions and Macro Calls, 152 10.3 Local Symbols, 158 10.4 Repeat Directives, 160 10.5 Conditional Assembly, 163 Exercises, 168

Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G INDEX

68000 Organization 172 ASCII Character Set 174 178 68000 Addressing Modes 68000 Instructions 180 68000 Machine Language 215 Notes on Programming Style 235 238 Answers to Selected Exercises 245

150

PREfACE

The objective of this book is to familiarize the reader with the basic organization and operational features of the Motorola 68000 and to present assembly language techniques for this computer. It is not, per se, a general text on machine structures, and the authors do not attempt to provide a comprehensive treatment of available computer organizations and assemblers. However, to the extent that the concepts and methods governing the operation and programming of the 68000 are used in many other computers, the material in this book should provide the reader with good preparation for the operation and programming of other machines. Chapter 1 provides an outline of algorithms for converting numbers from one system (binary, hex, decimal) to another. The algorithms are not provided with proofs, and are intended to serve only as reference. Chapter 2 describes the organizational structure of the 68000 (the central memory, central processor, and peripheral devices). Chapter 3 explains how numbers (integer and floating-point), characters, and strings are represented in the 68000. Chapter 4 describes the 68000's instruction formats and addressing modes. And Chapter 5 introduces the reader to assembly language programming. The first five chapters should provide the reader with sufficient background to write simple programs for the 68000. The remaining chapters delve deeper into operational details and describe additional techniques. Chapter 6 introduces stacks and subroutines (including recursion). Chapter 7 looks more closely at the 68000's arithmetic (including double-precision) and other operations, such as the test, comparison, branch, and shift operations. Chapter 8 explains the trap and interrupt mechanisms. Chapter 9 describes the workings of assemblers and linkage editors and the notion of relocation. (No particular assembler or linkage editor is used, and the concepts discussed are quite general.) Chapter 10 introduces some advanced assembler facilities, such as macros, repeated assembly, and conditional assembly. The book ends with a number of appendixes, which consist of reference lists and tables (character codes, summary of addressing modes, lists of instructions, and so forth). An appendix on programming style is also included, which should be carefully read by the beginner. Each chapter concludes with a set of exercises that serve to illustrate and sometimes complement the material in the text. The reader is encouraged to solve the problems and vii

viii

PREFACE

run the programs included in these exercises. True assimilation of the material in this book can come about only through practice-by the actual writing and execution of programs. The only prerequisite to this book is some experience with high-level language programming. No particular language is assumed, but it is taken for granted that the reader is familiar with the notions of an algorithm, a flowchart, and a stored program. It is not our intent that this book stand alone as a course text. Since it does not describe all the fine details of the 68000 instructions and assembler directives, students should have access to a 68000 microprocessor handbook and the assembler manual appropriate to their particular installation, where these details can be found when needed. Little is said in the book regarding peripheral equipment (only the terminal and clock device are treated in detail), and students doing I/O programming may wish to refer to peripherals handbooks and local manuals for assistance. The assembler used in this text contains features common to most 68000 assemblers. It is named TASTE, and was written by two South Dakota Tech graduate students, John Kjellevold and Jon Sundfjord. The authors are indebted to Dr. Karen Whitehead for reviewing the manuscript and offering much useful advice. Thanks are also due Dr. David Ballew and Professors Harold Cards, Julie Dahl, and Roger Opp for helpful comments and suggestions. And, finally, thanks to Tara and Rob Powles for their help with the manuscript.

1 NUMBER SYSTEMS

As we work with the 68000, we shall make extensive use of the binary and hexadecimal (hex) number systems, as well as the decimal system. It is important that the student acquire, as soon as possible, the facility to convert from one system to another. In this chapter we shall outline, without proof, some algorithms for carrying out these conversions. Students familiar with these algorithms may proceed directly to Chapter2. In this chapter, a "number" will mean a non-negative integer (0, 1, 2, ... ). The number N will be denoted by Nl0' N16 , or N2 if it is in the decimal, hexadecimal, or binary system, respectively. However, the subscript may be dropped if it is understood from the context. An m-digit number will be written symbolically as Dm_ 1 ••• DIDo [Dj being the (i+l)st digit from the right]. In all flowcharts, an oval-shaped box will represent an entry or an exit point, and a diamond-shaped box will represent a branching point.

1.1 DECIMAL-TO-BINARY CONVERSION The flowcharts in Figures 1.1 and 1.2 describe algorithms for converting a decimal number N into its binary equivalent M. Example (Subtraction-of-powers method) N=217 1O 217 - 27=217 -128 =89 89 - 2 6 = 89 - 64 = 25

(D6 = 1)

25 - 24 = 25 - 16 = 9

(D4 = 1)

9 -2 3 =9 - 8 = 1

(D3 = 1)

1 - 2°= 1 -1 = 0

(Do = 1)

M = 11011001 2 1

2

NUMBER SYSTEMS

Yes

M-D m _ 1 ···D 1 Do Find greatest power of 2, say 2k,

(with all Dk not previously assigned set to 0)

not exceeding X. *

Dk -1 X-X - 2k

*Use Table 1.1

Figure 1.1

Decimal-to-binary conversion by subtraction of powers.

Example (Division method) N= 217 1O 217 is odd

(Do = 1)

217/2 = 108 is even

(Dl = 0)

108/2 = 54 is even

(D2 = 0)

54/2 = 27 is odd

(D3 = 1)

27/2 = 13 is odd

(D 4 = 1)

13/2 = 6 is even

(Ds = 0)

6/2

= 3 is odd

(D6 = 1)

3/2

= 1 is odd

(D7 =1)

1/2

=0 M = 11011001 2

CHAP. 1

SEC. 1.2

DECIMAL-TO-HEXADECIMAL CONVERSION

3

Yes

X-N m-O

No Halt

*qt (a/Ill

Figure 1.2

= integer quotient a/Il

Decimal-to-binary conversion by division.

1.2 DECIMAL-TO-HEXADECIMAL CONVERSION The flowcharts in Figures 1.3 and 1.4 describe algorithms for converting a decimal number N into its hexadecimal equivalent M. Powers of 16 are listed in Table 1.1, hexadecimal digits are listed in Table 1.2. Example (Subtraction-of-powers method)

N = 2591 10 2591 -10*16 2 = 2591 - 2560 = 31 31- 1*16 1 =

31-

16= 15

15 - 15*16° =

15 -

15 = 0

M=AIF 16

(D2 = 10 = A 16 ) (D t

= 1)

4

NUMBER SYSTEMS

CHAP. 1

Yes

M-D m _ 1 ···D 1 Do (with all Dk not previously assigned

Find greatest number of form

set to 0)

a'16 k (1';;; a';;; 15) not exceeding X. * Dk-a X-X - (a'16 k )

*Use Table 1.1

Figure 1.3

JExample

Decimal-to-hex conversion by subtraction of powers.

(Division method)

N=2591 10 2591/16 = 161 (remainder 15)

(Do =F)

161/16 = 10 (remainder 1)

(Dl = 1)

10/16 =

0 (remainder 10)

(D2=A) M=AIF 16

An alternative method consists of ftrst converting N into binary as shown in Section

1.1, and then converting the result into hexadecimal as shown in Section 1.6.

1.3 BINARY-TO-DECIMAL CONVERSION IfN = Dm _ 1 .•. D1Dois a binary number, then its decimal equivalent is: m-l

M=

1:

i=O

(powers of 2 are listed in Table 1.1)

SEC. 1.4

HEXADECIMAL-TO-DECIMAL CONVERSION

5

Yes

Yes

Dm- rm(X/16t* X-qt(X/16)* m-m + 1 *qt(a/f3) = integer quotient a/f3 rm(a/f3) = remainder of a/f3

Figure 1.4

Decirnal-to-hex conversion by division.

JExample N = 1011100

M =22 + 23 + 24 + 26 =4 + 8 + 16 + 64

=92 10

1.4 HEXADECIMAL-TO-DECIMAL CONVERSION IfN = Dm _ 1 ... DIDOis a hexadecimal number, then its decimal equivalent is: m-l

M=

E i=O

(powers of 16 are listed in Table 1.1.) Alternatively, the decimal equivalent can be written as M = ( ... ((D m _ 1*16 + Dm _ 2)*16 + Dm _ 3)*16 + ... + D 1)*16 + Do The following examples illustrate how these two forms can be used to compute the decimal equivalent of a hexadecimal number.

NUMBER SYSTEMS

6

CHAP. 1

Example (Sum-of-powers method) N = 3107 16 M = 7*16° + 0*16 1 + 1 *16 2 + 3*16 3 = 7*1 7

+ 0*16 + 1*256 + 3*4096 +

0 + 256

+ 12288

=12551 10 Example (Multiply-and-add method)

N = 3107 16 + 1=

48 + 1 =

49

49*16 +0=

784+0=

784

3*16

784*16 + 7 = 12544 + 7 = 12551 M=12551 1O

1.5 HEXADECIMAL-TO-BINARY CONVERSION The binary equivalent M of the hexadecimal number N is obtained by replacing each digit in N with a group of four binary digits as shown in Table 1.1. (Leading Os in the leftmost group can be deleted.) Example

N = 3D6C 16 M = 11 1101 0110 1100 2 TABLE 1.1

16° = 2° = 21 = 22= 23 = 16 1 =2 4 = 25 = 26 = 27 =

POWERS OF 2 AND 16

1 2 4 8 16 32 64 128

16 2 =2 8 256 29 512 210 = 1024 211 = 2048 16 3 = 212= 4096 2 13 = 8192 214 = 16384 2 15 = 32768

1.6 BINARY-TO-HEXADECIMAL CONVERSION The hex equivalent M of the binary number N is obtained by partitioning N into fourdigit groups from right to left and then replacing each group by a hex di~t as shown in Table 1.2. (If the length of N is not divisible by 4, add enough leading Os to make it so.)

SEC. 1.7

BINARY AND HEXADECIMAL ADDITION

TABLE 1.2

7

DECIMAL-HEXADECIMAL-BINARY CONVERSION

Decimal

Hex

Binary

0

0

2 3 4 5 6 7 8 9 10 11 12 13 14 15

2 3 4 5 6 7 8 9 A

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

B

C D E

F

Example N = 1101011010001111

= 1101

0110 1000 1111

M = D68F 16

1.1 BINARY AND HEXADECIMAL ADDITION Binary numbers are added as if they were decimal, except for the following rules:

1 + 1 = 0 (carry 1) 1 + 1 + 1 = 1 (carry 1) Example 101101 2

+ 100111 2 10101002 The most straightforward method for adding two hex numbers is to add as if they were decimal, except for the following rules: 1.

If a digit is a letter (A to F), convert it to decimal.

NUMBER SYSTEMS

8

2. 3.

CHAP. 1

If the sum, S, of two digits (added as if they were decimal) is 16 or more, then replace S with S-16 and carry 1 (e.g., 9 + 9 = 2 carry 1). If the sum of two digits (added as if they were decimal) is 10 to 15, then replace it with the appropriate letter, A through F (e.g., 5 + 7 =1210 =C I6 ).

Example 7A34D 16

+ B2C36 16 12CF83 16

EXERCISES

1.1. Using both the subtraction-of-powers and the division method, convert the following decimal numbers into their binary and hex equivalents. a. 2337 10 b. 1000010 c. 16383 10 1.2. Convert the following binary numbers into their decimal and hex equivalents. a. 11111112 b. 10000001 2 c. 1010011100101110 2 1.3. Convert the following hex numbers into their decimal and binary equivalents. a.8FF 16 b. 9A8 16 c. CAFE 16 1.4. Perform the following binary additions and check the results by converting the numbers into decimal. a. 1011010 2 + 11010 2 b. 1111101 2 + 1110 2 1.5. Perform the following hex additions and check the results by converting the numbers into decimal. a. 16A 16 + FFF 16 b. 18F 16 + 2EC 16 1.6. Compute the following binary product and check the result by converting the numbers into decimal. 11010111 2

*

100101 2

1.7. Show that the binary equivalent of 2k_1 is 111 ... 1 (k times).

2 THE ORGANIZATION Of THE 68000 A Motorola 68000-based computer system consists of a Motorola 68000 central processor (CP), where all computations take place, the central memory (CM), where the data and program are stored; and peripheral devices, such as the terminal, clock, and the devices needed to communicate between the 68000 and the terminal. In this text we shall assume a very rudimentary 68000 configuration with only a terminal, a clock, and a communication device as peripheral devices. Details on these and other devices can be found in the manuals for the particular devices. Strictly speaking, "68000" refers to the microprocessor chip itself (consisting of the CP only). However, for the sake of brevity, in the remainder of this text the designation 68000 will refer to the entire system-CP, CM, and peripherals-and not just the chip. Figure 2.1 outlines the general structure of the 68000 CP along with central memory and peripheral devices. In this chapter we shall describe the main features of the various components shown in this figure with the exception of the clock control and status registers. These registers, together with the interrupt feature of the communication device, will be discussed in Chapter 8. A symbol by itself, for example X, will represent a CM address or a register name. The notation (X) will stand for ''the contents of X". Similarly, ((X)) will stand for the "contents of (X)" (Le., the contents of the memory location whose address is found in X). For the sake of readability, the name of a register will sometimes be used to indicate its contents when no other meaning is possible. Thus, D5 and (D5) will both be used to indicate the contents of register D5. For example, "add D5 to D3" and "add (D5) to (03)" will both be used and will mean the same thing. The latter is perhaps more technically accurate, but the former is easier to read.

2.1 THE CENTRAL MEMORY The central memory of a computer is also called "main memory", "primary memory", "RAM" (random access memory), and "core" (a term left over from the days when most central memories were constructed from magnetic core elements). The basic memory element of a computer is the bit, which is capable of holding 9

THE ORGANIZATION OF THE 68000

10

CHAP. 2

a single binary digit, either a 0 or a 1. The multitude of bits of which the central memory consists are grouped into bytes, which, in tum, are grouped into words (which can be grouped into long words by the programmer). In the 68000 each word consists of 16 bits, numbered (right to left) from 0 through 15; bits 0 through 7 constitute the low byte and bits 8 through 15 the high byte ofthe word: Low byte

High byte

15

14

13

12

11

10

9

8

7

6

5

4

3

2

o

A long word consists of two words whose bits are numbered (right to left) 0 through 31. Figure 2.1 shows a 68000 memory consisting of 214 = 16384 10 = 16K words or 2 15 =32768 10 =32K bytes (where K stands for 2 10 = 1024). Larger memories are possible, the exact size varying from one machine to another. Each byte in the CM is identified by a unique number called the address (or the location) of the byte. If the CM has b bytes, the sequence of byte addresses is 0, 1,2, ... , b-l. The address of a word is, by convention, the address of its high byte. Thus, the sequence of word addresses is 0, 2, 4,6, ... , b-2. Note that a word address is always even. For example, in the 16K-word machine shown in Figure 2.1, the byte addresses are 0,1,2,3, ... , 7FFF 16 (7FFF16 = 32767 10) and the word addresses are 0,2,4,6, ...,7FFE 16 We shall always write CM addresses in hexadecimal. The contents of a word (or byte) can naturally be represented by a sequence of 16 (or 8) binary digits. When the sequence, viewed as a binary number, is converted into its four-digit (or two-digit) hex equivalent, the result is the hex contents of the word (or byte)-a concise and convenient representation which will be used frequently in this text. For example, the word whose actual (binary) contents is 1010011100101110 has the hex contents A72E; its low byte has the hex contents 2E, and its high byte, A7.

2.2 THE CENTRAL PROCESSOR The CP consists of the arithmetic and logic unit (ALU), where all numerical and logical operations take place, and a number of 32-bit (long word-size) registers which constitute the CP's "private memory".

SEC. 2.2

THE CENTRAL PROCESSOR

11

Central Processor (CP) Program counter (PC) (32 bits, 24 used)

I

~

2423 0 Status register (SR) (16 bits) System byte User byte

31

I15

Central memory (CM) Word

I

T.S .. ppp

... XNZVC

8 7

General purpose registers

~

16 bits

o

) 32K Bytes 16K Words

j

DO D1 D2 D3 D4 D5 D6 D7

r----"-l 1 3 5

2 4 6 8

7 9 B D

A

C E 10 ~

7FFE~7FFF 15 87

0

~L......-.J

High byte

Low byte

Arithmetic and logic unit (ALU)

AO A1 A2 A3 A4 A5 A6 A7*

F 11 L-:\

I

0

31

16 15

8 7

0

*A7 is stack pointer (SP) Terminal status and data registers (ACIA)

r----I . ."'I---_ _~. ~

110040 10042

1--_ _ _ _ _- '

Terminal

7

-coJ1-------i1>1lo-

0

Clock control and status registers These will be discussed in Chapter 8.

Figure 2.1

68000 organization.

There are 16 general-purpose registers called DO, DI, ... D7, and AO, AI, ... A7. A7 is also called the stack pointer (SP) , for reasons to be discussed later. There is another register called the program counter (PC) which always contains the address of the next program instruction to be executed. The CP's access to the general-purpose registers is much quicker than its access to the CM. It is thus advisable to keep frequently needed data (e.g., loop control variables) in these registers rather than in the CM. The status register (SR) contains several I-bit condition codes whose values depend on the result of the instruction last executed. For example, the Z ("zero") and N ("negative") codes:

THE ORGANIZATION OF THE 68000

12

Z code (bit 2) =

{ 1 if result was 0 oif result was not 0

N code (bit 3) =

{ 1 if result was < 0 oif result was > = 0

CHAP. 2

Other condition codes will be discussed in later chapters. It should be noted that different instructions affect codes differently (and some do not affect them at all). The precise effect of each instruction on the condition codes is specified in MC68000 User's Manual or in Appendix D of this book. A number of registers associated with peripheral devices will be introduced in subsequent sections.

2.3 THE TERMINAL AND THE COMMUNICATION CHIP The terminal is representative of various character-oriented peripheral devices. By means of the terminal, information can be entered into the 68000 (by a human operator) via a keyboard and printed by the 68000 via a display screen. It is important to note that, unlike an ordinary typewriter, the terminal consists of two devices, the keyboard and the screen, which are completely independent (Le., pressing a character on the keyboard will not automatically result in the display of this character on the screen). The terminal is associated with four interface registers, each of which has a nominal address and can be regarded as if it were part of the CM. This means that the registers are not actually part of the memory but can be accessed by using fake addresses called "nominal addresses". The processor translates, or "memory maps", these address references into references to the appropriate registers. This address structure results from the use of a communication chip called a 6850 Asynchronous Communications Interface Adapter or ACIA. Other communication chips may have different address structures, so you may need to consult the manual for your system if you have a different chip. Also, the particular addresses mentioned here are for the 32K Motorola Educational System MEX68KCB and may be different on your system. The interface registers are: 1. The terminal status register (addressed 10040) 7

I@ •

0

• @•

@

I

0

•

Input ready bit

Bit 0 (the "input ready" bit) is 1 when the character typed in is available in the keyboard data register. It becomes 0 only after an instruction is executed which fetches the contents of the keyboard data register.

SEC. 2.3

THE TERMINAL AND THE COMMUNICATION CHIP

13

o

7 10

0

®

0

®

01

•

10

Output ready bit

Bit 1 (the "output ready" bit) is 1 when the screen is available for printing. It becomes 0 as soon as a character is loaded into the terminal output data register and remains so until printing is completed. Note that the terminal is much slower than the CPU, so the time taken to display a character after it has been sent to the screen cannot be ignored. We shall see later that there is an instruction that will allow us to easily test the value of each bit in a byte. Using this instruction, we will be able to test whether input is available by testing bit 0 in byte 10040 and test whether the screen is ready for output by testing bit 1 in byte 10040. This register is "read only" and cannot be written into by the program. 2. The keyboard data register (addressed 10042)

o

7

Character

This byte holds the encoded form of the typed-in character. This register is "read only" and cannot be written into by the program. 3. The terminal output data register (addressed 10042)

o

7

Character

This byte holds the encoded form of the character to be printed. If the terminal output status register's "ready" bit is 1, printing will take place immediately upon loading the data register. This register is "write only" (Le., its contents cannot be moved elsewhere by a program). 4. The terminal control register (addressed 10040) This register will be discussed in Chapter 8. It, like the terminal output data register, is write only. Note that the keyboard data register and terminal output data register have the same nominal address (as do the terminal status register and the terminal control register).

THE ORGANIZATION OF THE 68000

14

CHAP. 2

This does not cause a conflict because the fIrst is read only and the second is write only. Thus, an instruction that reads from byte 10042 will read the keyboard data register, while one that writes to byte 10042 will write to the terminal output data register. These are physically different registers within the ACIA hardware.

2.4 THE LINE CLOCK The 68000 does not have a built-in clock, but it can be connected to a device containing a clock. We will discuss the use of a clock device, the MC68230 Parallel Interface and Timer (PI/T) in Chapter 8.

EXERCISES

2.1. Write (in hex) the highest byte and word addresses in a w-word computer, where w (in decimal) is a.28K h. 2 18 2.2. How many words are there in a CM whose highest byte address is FFFF 16? 2.3. Determine the hex contents of the words that contain a. 0110110110110110 h. 1001011111010101 What are the hex contents of the low byte and high bytes of each of these words?

3 REPRESENTATION Of

NUMBERS AND CHARACTERS

In this chapter we shall see how numbers (integer and "real", positive and negative), characters, and character strings are stored within the 68000. Unless otherwise specified, a "number" will mean an integer. A "positive number" will mean a non-negative integer (0,1,2, ... ).

3.1 2'S-COMPLEMENT REPRESENTATION Numbers are represented in the 68000 in the n-bit 2's complement form, where n is 32 (for long word representation), 16 (for word representation), or 8 (for byte representation). This form is constructed by the following rules. To store a positive number N: 1. Express N in binary form. 2. Store the (binary) N right:iustified in the word (or byte or long word), supplying it with as many leading Os as needed to make the total number of digits n. Examples 1. N = 1607 10 = 647 16 16-bit 2's-complement representation: 0000 0110 0100 0111

(0647 16 )

2. N = 10 10 =A 16 8-bit 2's-complement representation: 0000 1010 The largest positive number recognized in the n-bit 2's-complement form is

n-l

15

REPRESENTATION OF NUMBERS AND CHARACTERS

16

CHAP. 3

When n = 16, then N d", ... , dr d1,d", ... , dr

cause the assembler to store the data (numbers or characters) dl>d", ... , d r in consecutive bytes, words, or long words, respectively. (DC stands for "define constant".) For example, DC.B DC.W DC.L

l2,-5,'ABCD' $ABCD,50 $12345678,7

ASSEMBLY LANGUAGE PROGRAMMING

50

CHAP. 5

will result in storing, in nine consecutive words, the hex numbers (12,-5) ('A','B') ('C','D') ($ABCD) (50) ($12345678)

OCFB 4142 4344 ABCD

0032 1234 5678

0000 0007 2. DS.B DS.W DS.L

(7)

n n n

cause the assembler to reserve a storage block of n bytes, words, or long words, respectively. (DS stands for "define storage".) Note that the DS directive reserves storage but does not initialize the storage. Thus, DS.W 100 reserves 100 words whereas DC.W 100 reserves one word initially containing the number 100. 3. The "assignment directive" sym

EQU

exp

causes the assembler to assign the symbol "sym" the value of expression "exp". (EQU stands for "equate".) For example, TRMSTAT CR

EQU EQU

$10040 $OD

assign the values $10040 and $OD to the symbols TRMSTAT and CR, respectively. Henceforth, every time the assembler encounters the symbol TRMSTAT, it reo places it with $10040, and every time the assembler encounters the symbol CR, it replaces it with $OD. A subsequent directive, TRMDATA

EQU

TRSMTAT+2

assigns to the symbol TRMDAT A the value $10042. Assignment directives permit the programmer to use meaningful names, rather than obscure numbers, in the body of the program-which considerably enhances readability. They also make the program less sensitive to changes in hardware, character code, etc. If, for example, the keyboard status register is

SEC. 5.2

ASSEMBLY LANGUAGE DIRECTIVES

51

moved to a new address, or the code for a carriage return is replaced by another, all one needs to do is change the assignment directives for TRMSTAT and CR; this will automatically enforce the new values upon all the TRMSTAT and CR symbols appearing in the body of the program. Thus, if the ACIA registers in your 68000 system have different addresses than those used in this text, you only need to change the appropriate assignment directives appearing at the beginning of our programs. The expression in the assignment directive may contain the operators '" and / as well as + and -. Brackets are also allowed. The usual rules pf algebraic precedence apply. For example, in

A B C

EQU EQU EQU

3

1+2 "'A [1+2] "'A

B is assigned the value 7, and C the value 9.

4. The symbols DO,DI, ... ,D7,AO,Al, ... ,A7,SP,SR, and PC are predefined in the assembler. The symbol'" ("star", or "asterisk" if you prefer giving your tongue a challenge), which is also predefined, refers to an assembler variable (called location counter) which, at any time during assembly, holds the address of the word into which the current instruction is being assembled. 1 Its initial value is defined by the ORG directive (see below).

5.

ORG

n

assigns the value n to the location counter. This must be done at the beginning of every program. (ORG stands for "origin".) The ORG directive can also be used to define starting locations for different parts of the program (data blocks, code, etc.). For example,

ABC START

ORG DS.W ORG

$5000

EQU

'"

100 $6000

could be used to reserve 100 words of storage starting at location $5000 for an array called ABC to be used in a program that starts at location $6000. (The purpose of the directive START EQU '" is simply to assign to the symbol START the current value of the location counter, namely $6000.)

IWith some assemblers, "star" can also be used to specify addresses. For example, "jump 3 words ahead" can be written as IMP *+6; "move current address to AD" can be written as MOVE #*,AD.

ASSEMBLY LANGUAGE PROGRAMMING

52

n

LOAD

6.

CHAP. 5

causes the machine language version of the program to be stored in memory start· ing at address n. This is usually the same value as on the ORG directive. The LOAD directive can be omitted if the program is not going to be executed for the purpose of error checking. Many assemblers create a me of the program's object code which is later loaded into memory and, thus, do not need the LOAD directive.

7.

EVEN forces "star" to become the next even address. If the location counter is already even, this directive does nothing. This is required if a directive reserving an odd number of bytes comes before one which reserves words. Without this directive, the word addresses would be odd, which is not allowed in the 68000.

8. The last statement of every program must be:

END 5.3 ASSEMBL Y LANGUAGE PROGRAM FORMAT A source program is composed of a sequence of lines, each containing a single statement. A statement may be composed of as many as four fields, named and formatted as follows: Label

Operator

Operand

;Comment

The label field terminates with a space; the comment field starts with a semicolon; items within the operand field are separated by commas; the operator and operand fields are separated by at least one space. For example: LOOP

MOVE.B

DO,$10042

;PRINT CHARACTER

The label, which assigns a symbolic address to the statement, needs to appear only when the statement is referred to symbolically. A symbol may be of any length. Labels should consist of letters and digits and start with a letter. Different assemblers may have different rules on allowable labels, but most will allow a reasonable number of letters and digits. A label cannot be anything that could be confused with a pre· defmed symbol such as DO, AS, or PC. Note that there is no confusion between the label ABC and the hex number ABC, since the hex number ABC must be written as $ABC. The operator field contains the mnemonic op code of a 68000 instruction, or the code of an assembler directive. The operand field contains the remainder of the instruction or directive.

SEC. 5.4

EXAMPLE 1: ECHO KEYBOARD INPUT TO SCREEN

53

The comment field is optional, but should be used generously if a well-documented program is to result. (A line consisting entirely of commentary may start with ; in any column.) Comments are ignored by the assembler and are used only for documentation purposes. As a matter of convention, all source programs in this text will be organized as follows: ORG LOAD

$7000 $7000

(Description of program) EQU MOVE

START

*

#START,SP

(program) END With this format, the program starts at $7000 with the instruction MOVE #START,SP which stores the address $7000 in SP (the stack pointer). The reason for this will be explained in the next chapter.

5.4 EXAMPLE 1: ECHO KEYBOARD INPUT TO SCREEN We wish to write a program which "echoes" (types back) every typed-in character. Striking a key sends a signal to the 68000, but it does not automatically send a return signal to the screen. This program will allow the programmer to see what is typed and will probably be incorporated into most 68000 programs. Figure 5.1 shows the flowchart and Figure 5.2 the assembler listing of the source and object codes. The listing shows (left to right) the CM addresses into which the source instructions are assembled, the object code, the ordinal numbers of the source lines, and the source code of the program. The instruction: BTST

#O,TRMSTAT

checks the input ready bit of the ACIA. If it is 0, no character is available in the keyboard data register. Thus, this instruction coupled with: BEQ

INPOLL

ASSEMBLY LANGUAGE PROGRAMMING

54

CHAP. 5

~------~------~

Figure S.l

Flowchart for program to echo input.

has the effect of looping until the input ready bit is 1. This process is known as polling and will be used again to output the character to the screen. The instruction: MOVE.B

TRMDATA,D3

moves the contents of the input data register (namely the ASCII code for the character typed) into the low byte of D3. The instruction: CMP.B

#$D,D3

compares the character in D3 to a carriage return (see Table 3.2). If they are equal, the next instruction causes the program to branch to the label DONE. If not, the character must be echoed to the screen. The instruction: BTST

#l,TRMSTAT

has a polling function similar to the one mentioned above, except that bit 1, the output

SEC. 5.4

EXAMPLE 1: ECHO KEYBOARD INPUT TO SCREEN

55

1 ; •• o ••••••••••• oeooo ••••• oeoe •••• a •••••••••••••• o ••••••••••••••••

2 ,

3 ; THIS PROGRAM ECHOES CHARACTERS ENTERED FROM THE KEYBOARD 4 ,

007000 007ODO 007000 007000 007000 007000 007000 007000 007004 007004 007004 007004 007004 007008 00700C 00700E 007012 007014 007018 0070lC 0070lC 0070lC 0070lC 0070lC 007020 007024 007026 00702A 00702C 00702E 00702E 00702E 007032 007034

5 ; •••••••••••••••••••••••••••••••••• oo ••••••• e •••••• o •• e •••••••••• 6 ORG $7000 7 LOAD $7000

3E7C7000

08390000 00010040 67F6 16390001 0042 OC03000D 67000014

8 9 10 II 12 13 14 IS 16 17 18

; TRMSTAT EQU TRHDATA EQU ; START EQU HOVE

, INPOLL

4EF9EEEE EEEE

G

#START,SP

INPUT CHARACTER EQU BTST

"

1I0,TRMSTAT

19 20

BEQ INPOLL HOVE.B TRHDATA,D3

;WAIT UNTIL CHARACTER AVAILABLE ; INPUT CHARACTER INTO 03

21 22

CI1P.B BEQ

;DONE IF RETURN ENTERED

23 24

OUTPUT CHARACTER

25 ;

08390001 00010040 67F6 13C30001 0042 6006

;TERHINAL STATUS REGISTER ;TERMINAL DATA REGISTERS

$10040 $10042

26 OUTPOLL EQU 27 BTST

#$0,03 DONE

.. #I,TRHSTAT

28 29

BEQ OUTPOLL HOVE.B D3,TRHDATA

30 31 ; 32 DONE 33

BRA

INPOLL

;GET NEXT CHARACTER

EQU JI1P

"$EEEEEEEE

;ILLEGAL BRANCH FOR STOP

34

END Figure S.2

; WA IT FOR OUTPUT READY ;OUTPUT CHARACTER IN 03

Program to echo input.

ready bit, is being tested. The BEQ instruction on the next line again checks if the bit is 0, indicating not ready. If it is 0, the program must again poll until the bit becomes 1, indicating that the output device is ready to receive a character. The instruction: MOVE.B

D3,TRMDATA

moves the character in D3 into the terminal output data register. This causes the character to be printed. The instruction: BRA

INPOLL

56

ASSEMBLY LANGUAGE PROGRAMMING

CHAP. 5

transfers control to the statement labeled INPOLL, allowing the process to be repeated for the next character. Notice that the instruction:

]MP

$EEEEEEEE

requires a jump to an invalid address. This has the effect of ending the program, although it will produce error messages. A more elegant method for ending a program is a jump to the system monitor which will be discussed later. There is also a STOP instruction that will cause the processor to stop processing instructions, but this is not advisable since it is essentially an infinite do-nothing loop.

5.5 EXAMPLE 2: MUL TlPLE ECHO We are now ready to try a more complicated example. This program will echo the typedin character n times. Since echoes of a character may not be completed before the next one is typed in, the program should set up a "buffer" (Le., a temporary storage block) for storing characters awaiting printout. We shall assume that the backlog can never exceed 6410 characters. The program employs a "buffer input pointer", which, at any time, points to the next free buffer byte (Le., the byte in which the next typed-in character is to be stored), and a "buffer output pointer", which, at any time, points to the next buffer byte to be echoed. Typically, the output pointer lags behind the input pointer; when the former finally catches up with the latter, the buffer is "empty" (no character awaits printout). For efficient operation, it is proposed to use a "circular buffer", where the byte with the highest address is followed by the byte with the lowest address. In this manner, only 6410 bytes are required for storage, regardless of the number of characters typed in. An implementation of such a buffer required that when a buffer pointer reaches 6310 ($3F), its next value be reverted to O. One way of accomplishing this is to mask out (clear) all but the rightmost 6 bits of the pointer (see below) after every incrementation. This operation is known as masking. Figure 5.3 shows the flowchart and Figure 5.4 the assembler listing of the source and object codes of the program (where n was selected to have the value 5). The masking operation is done in the program by means of the AND instruction (see lines 28 and 38 in Figure 5.4). AND s,d does a logical (bit-by-bit) AND of (s) and (d) and stores the result in d. Thus, AND #$3F,DO will clear all but the rightmost 6 bits in DO. Notice the destination (AO,DO) on line 26 [or the source (AO,DI) in line 34]. This is an example of address register indirect with index and displacement, N(An,Dm); here N = 0 and need not be written.

SEC. 5.5

EXAMPLE 2: MULTIPLE ECHO

(~O)

(01) (02) -

57

0 0 0

Buffer Buffer + 1 Buffer + 2 No

Store input character in buffer

01

r

(Buffer + (OO))-character (OOHOO) + 1 (00)-(00) A $3F

~:;:-;:------r:;:========-.J

Echo output character

r

DO Buffer + 3 F '---_ _ _----'

= buffer input pointer (01) = buffer output pointer (02) = repetition count n (~O)

~-------,--------~

Prepare for next output character

r '--_ _ _ _...,_ _ _ _.....

Yes

Pick up repetition cou nt

Figure S.3

Flowchart for multiple-echo program.

ASSEMBLY LANGUAGE PROGRAMMING

58

1

.OOGOOOG9000000oooftooaoeaeOOGOOaODOGGQOOoo.oueeo&o&oee.0.90.e • • eo

2

ECHO EACH TYPED-IN CHARACTER N TIMES. USE CIRCULAR BUFFER OF 64 (DECIMAL) BYTES FOR STORING AWAITING CHARACTERS.

3 4

007000 007000 007000 007000 007000 007000 007000 007000 007004 007004 007006 007008 o0700A o07ooE o0700E 00700E o0700E 00700E 007012 007016 o07olA o07olE 007022 007024 007028 007028 o0702A o0702E 007032 007036 007038 00703C 007040 007042 007044 007046 o0704A o0704A 00704C o0704E 007052 007054 007056 007056 007098 007098

3E7C7ooo 4240 4241 4242 307C7058

08390000 00010040 67000010 IIB9000i 00420000 5240 o24ooo3F 4A42 670000iE 08390001 00010040 6706 13FoIooo 00010042 5342 66CA 5241 o241oo3F B240 67CO 34390000 7056 6oB8 0005

~ 7 8 9 10 II 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

CHAP. 5

;00000000000000000000000000000&000008000000.0.0000060&Raaae*o • • a&

ORG $7000 LOAD $7000 $10040 :TERMINAL STATUS REGISTER TRMSTAT EgU TRMDATA E U $10042 :TERMINAL DATA REGISTER START EQU " MOVE #START,SP CLR :INITIALIZE BUFFER INPUT POINTER (BIP) DO CLR 01 :INITIALIZE BUFFER OUTPUT POINTER (BOP) CLR 02 :INITIALIZE REPETITION COUNT MOVE #BUFFER,AO ;Ao=START OF BUFFER FOR INDEXING INPUT CHARACTER : G EQU LOOP BrST #o,TRHSTAT BEQ ECHO ;IF NO CHARACTER, KEEP ECHOING MOVE.B TRMDATA,(AO,Do) ;STORE CHARACTER IN BUFFER ADDQ ; INCREMENT BIP f.I,Do AND ;ZERO IF BIP = $40 f$3F,Do EQU ECHO TST ;IF MULTIPLE ECHO TERMINATES~ 02 BEQ NEXT ; PREPARE FOR NEXT OUTPUT LHAR. BTST #I,TRMSTAT ;OTHERWISE, IS PRINTER READY? LOOP ;IF NOT, ACCEPT NEXT CHARACTER 33 BEQ 34 MOVE.B (AO,DI),TRHDATA ;IF SO, ECHO OUTPUT CHARACTER DECREMENT COUNT 35 SUBQ f60~2 BNE IF COUNT NOT 0, ACCEPT NEXT CHAR. 36 37 ADDQ Q.I ,0 I ELSE, INCREMENT BOP 38 AND ZERO IF BOP = $40 f$3F,DI EQU 39 NEXT CHP ;IF BIP=BOP (BUFFER EMPTY), 40 DQ~DI LwP ; ACCEPT NEXT CHARACTER 41 BEQ 42 N,D2 ;SET COUNT TO N MOVE ;ACCEPT NEXT CHARACTER BRA LOOP 43 44 : ;REPETITION COUNT 45 N DC.W 5 ;BUFFER SPACE: 64 DECIMAL BYTES 46 BUFFER DS.B 64 47 END :

Figure 5.4

Multiple-echo program.

5.6 CODING HINTS It is useful to mention some common mistakes made by beginners while learning assembly language. The novice is often tempted to use addressing modes which do not exist. For example:

CLR

1000(AO)+

whose intention (presumably) is to use AO in address register indirect with displacement mode and then increment it. This hybrid displacement-autoincrement mode,

59

CODING HINTS

SEC. 5.6

although occasionally useful, is nonexistent in the 68000. One should issue, instead: CLR ADDQ

IOOO(AO) #2,AO

As another example, consider the statement: MOVE

D1+4,D2

whose intention is (presumably) to add 4 to the contents of DI and store the result in D2. This is impossible to do in a single 68000 instruction; one should issue, instead, MOVE ADDQ

DI,D2 #4,D2

[Note that the LEA instruction will allow us to do a similar operation on address registers by issuing LEA 4(AI),A2 which adds 4 to the contents of Al and stores the result in A2.] Another common problem is using an addressing mode which is not valid in a particular context. For example: CLR

AO

whose (clear) intention is to set AO to zero. However, the CLR instruction does not permit the use of the address register direct mode. One way of performing the desired operation is with SUBA AO,AO. (The problem of having to check the validity of every instruction/mode combination in the 68000 is rather annoying.) There is a tendency to forget the # sign when using immediate addressing. Note that there is a world of difference between MOVE

#SOO,DO

and MOVE

SOO,DO

The first instruction stores the constant 500 in DO, while the second stores the contents of address 500 in DO. As another example, suppose we wish to clear locations 1000, 1002, and 1004. The following sequence of instructions will do it: MOVE CLR CLR CLR

#1000,AO (AO)+ (AO)+ (AO)

60

ASSEMB L Y LANGUAGE PROGRAMMING

CHAP. 5

The first instruction puts the address 1000 into AO. The second instruction then clears location 1000 and adds 2 to AO. The third and fourth instructions clear locations 1002 and 1004, respectively. (Note that it would be more efficient to use a CLR.L for the first instruction, but this has no bearing on the point of the example.) Suppose now that the contents of 1000 is 500, and instead of the previous sequence we issue MOVE CLR CLR CLR

1000,AO (AO)+ (AO)+ (AO)

The first instruction moves the contents of location 1000 to AO. AO now contains the value 500. The next three instructions would clear locations 500, 502, 504. This is certainly not what we intended to do. All symbolic addresses other than DO, ... ,D7,A0, ... ,A 7 ,PC,SP,SR and perhaps a few others defined by your assembler must be defined within the program. For example, BTST #O,TRMSTAT is wrong unless the program contains the assignment directive TRMST AT EQU $10040. Beginners often issue instructions such as: MOVE ADD

#O,SAM #1 ,JUDY

While these are legal, they are wasteful in both time and space. Write instead:

SAM

CLR ADDQ

#l,JUDY

Beware of executing word instructions on operands which reside in odd addresses. For example, do not issue the instruction CLR (AO) unless you are sure that AO will always contain an even address. Beginners tend to confuse assembly directives with machine instructions. Notice that

J

EQU

results in the assignment, during assembly time, of the value 1 to the symbol J. It is totally different from: MOVE

#l,J

which stores, during run time, the value 1 in the word whose symbolic address (in the source program) is J. As another example, the statement:

CHAP. 5

61

EXERCISES

x

DC.W

172

results in 172 being stored, during assembly time, in the word whose symbolic address is X; when the program is ready for executions, 172 already resides in X. On the other hand, MOVE

#172;X

inserts 172 in X during run time. While the DC.W directive is obeyed only once (by the assembler), the MOVE instruction can be included in a loop which inserts 172 in X every time the loop is executed by the CPo A note on stopping a program is in order here. We have been using a jump to an invalid address for a stop. This has the advantage of being easy to do and causes all registers to be displayed at the end of the program, which may be useful. In order to end in a more elegant way, a program can mimic a hardware reset. To do this, you will need to know that the first two long words in the 68000's memory (bytes 0-7) are read-only memory that contain values to be loaded into the stack pointer (SP) and program counter when a hardware reset is requested. Thus, to do what amounts to a hardware reset the following instructions can be used: MOVE.L MOVE.L JMP

O,SP 4,AO (AO)

;RESET VALUE OF STACK POINTER ;START OF RESET CODE ; JUMP TO RESET CODE

Finally, let us remind the reader that it is not enough to write a program that merely runs correctly. A program should be well organized and adequately documented. The reader is referred to Appendix F, "Notes on Programming Style", for further details.

EXERCISES

5.1. Modify the keyboard echo program of Figure 5.2 to echo a backspace (ASCII $08) by printing the sequence backspace, space, backspace (ASCII $08 $20 $08) so that characters backed over will no longer appear on the terminal screen. 5.2. Modify the multiple-echo program of Figure 5.4 to accommodate a buffer size of 128 10 bytes. 5.3. What does the following program do? What are the hex contents of AO, DI, and D2 when it halts? How could this program be modified to be more efficient?

START

ORG LOAD EQU MOVE

$6000 $6000

*

#L4,AO

62

ASSEMBLY LANGUAGE PROGRAMMING

u:

L2

13 lA

CLR.L EQU MOVE.B AND CMP BLT CMP BGT SUB CMP BLE ADD SUB ADD EQU ROL ADD BRA EQU JMP DC.B END

CHAP. 5

D2

*

(AO)+,Dl #$FF,Dl #'O'DI 13 #'F',Dl 13 #'O',Dl #9,Dl L2 #'O',Dl #'A',Dl #$A,Dl

*

#4,D2 DI,D2 U

*

$EEEEEEEE '2BC7',$D,$A

5.4. Without using the DIVS or DIVU instructions, write an assembly language program that divides an integer stored in X by an integer stored in Y (with the fractional part truncated). The quotient is to be left in DO and the remainder in Dl. 5.5. Write an assembly language program that regards the word K as consisting of eight 2-bit "quarter-bytes" and counts the number of such quarter-bytes which have the value 3 (Le., 112)' The count is to be left in DO. 5.6. Write an assembly language program that prints out the hex contents of a word whose address is found in ADDR. (For example, if ADDR contains $124 and $124 contains $456, then the program should print out 0456.) 5.7. One hundred (decimal) 16-bit 2's complement numbers (not necessarily different from each other) are stored in order of ascending value in an array starting at address TABLE. Place in DO the number of occurrences of the array number that occurs most often. 5.8. Fifty (decimal) numbers, each between 0 and 100 10 , are stored in a 50-word array starting at address GRADE. The contents of GRADE + i represent the grade of student number i + I. Write an assembly language program that sets up a 50-word array starting at address RANK, where the contents of RANK + i is the rank of student number i + 1 in the class of 50. (The rank of a student equals one plus the num ber of students whose grades exceed that student's grade.) 5.9. Consider a chessboard whose rows and columns are numbered 0 through 7.

CHAP. 5

EXERCISES

63

Write an assembly language program that accepts an input of the form ij (0 0 (N mod M is the remainder when N is divided by M.)

6.8. Write a recursive subroutine that finds DO to the Dl power and puts the result in D2 using the following algorithm. Assume Dl is positive. 1 if Dl = 0 POWER(DO,Dl) = ( POWER(DO,Dl/2?ifDl > 0 and even DO*POWER(DO,Dl-l) ifDl odd

[A related problem is to develop a general formula for Nmult(N) = the number of multiplies required to compute POWER(DO,N).] 6.9.

Write a recursive subroutine that finds an integer N >= 1 in DO and leaves FIB(N) in D 1. Use the definition of FIB(N) given in Section 6.7.

This subroutine is often called the "Fibonacci disaster". Explain why. [Check how it computes FIB(10), for example.] Develop a better recursive algorithm and implement it. 6.10. A binary tree T with root N is a graph that can be defined recursively as follows: Basis: If T is a single node N, then T is a binary tree with root N.

CHAP. 6

STACKS AND SUBROUTINES

90

Induction step: (See the figure below.) If T consists of a node N connected to nodes LS (left successor) and RS (right successor), and if LS and RS are the roots of binary trees (denoted LT and RT, respectively), then T is a binary tree with root n. N

As an example, Figure 6.l8(a) shows a binary tree whose root is labeled 0 and whose nodes are labeled (in hex) 0,1,2, ... C. In the 68000, a k-node tree can be represented by a k-word array with base address TREE. Node number N is represented in location TREE + 2N. The high byte of TREE + 2N contains the number LS of the left successor of N, and the low byte the number RS of the right successor of N. Figure 6.l8(b) shows the representation of the tree of Figure 6.18(a). (a) The in order traversal of a binary tree T is defined recursively as follows:

Basis: If T is a single node N, visit N. Induction step: If T consists of a node N connected to binary trees LT and RT, then: (a) traverse LT in inorder; (b) visit N; (c) traverse RT in inorder. Write a recursive subroutine which prints out the node numbers of a given N

LS

RS

o

1

2 3

3 5 0

2 4 6 0

4

0

0

5 6 7 8

7

0 9

8 0 0

9

B

A

0 0 0

B

C

Figure 6.18

0

Binary tree and its representation.

A

C 0 0 0

Tree

CHAP. 6

91

EXERCISES

binary tree as they appear in inorder traversal. (For example, for the tree of Figure 6.18 the printout should be 3,1 ,4,O,7,5,B,9,C,8,A,2,6.) (b) The height of a binary tree T, denoted H(T), can be defined recursively as follows: Basis: If T is a single node N then H(T) = 0. Induction step: If T consists of a node N connected to binary trees LT and RT, then:

H(T) = 1 + maximum(H(LT),H(RT)) Write a recursive subroutine that prints out the height of a given binary tree. (For example, for the tree of Figure 6.18, the printout should be 5.)

7 ARITHMETIC OPERATIONS

As we already know, the condition codes in the status register provide infonnation on the result (which, as a rule, means the final value of the destination operand) obtained by the last operation. In this chapter we will describe in detail how these condition codes are influenced by various arithmetic operations. In particular, we will examine how the C, V, and X codes behave and how they can be used for overflow indication and in double-precision arithmetic. We will also take a closer look at the TST and the CMP instructions, at branch instructions, and at shift instructions. An ASCII-to-binary conversion program is included which illustrates some of the points made previously.

7.1 CARRY AND OVERFLOW UNDER ADDITION As already mentioned in Section 3.2, The C(Cany) and V (oVerflow) condition codes in the SR are influenced by the result of an ADD instruction in the following manner: 1 if addition resulted in carry from MSB 1

C=

V=

1o

otherwise

fol

if operands are of same sign and their sum is of opposite sign

\

otherwise

Examples For simplicity, let us assume that the 68000 has 4-bit words, capable of accommodating integers from -8 to +7.

I

92

Recall that MSB stands for "most significant bit".

SEC. 7.1

CARRY AND OVERFLOW UNDER ADDITION

Example (Decimal)

4-bit 2'sComplement Addition

1 +(+2) 3

93

Find Value of C

V

Binary Result is

0001 +0010 -0011

0

0

OK

5 +(+6) II

0101 +0110 -1011

0

-6 +(+7) I

1010 +0111

--

wrong

0

OK

0

OK

0

OK

t OO01

1 -6 +(+3) -3

1010 +0011 -1101 -

-5 +(-2) -7

1011 +1110 .{ 1001

0

I

-6 +(-6) -12

1010 +1010 -,,0100 1

wrong

Generally, the following can be readily deduced: 1. If both numbers are positive, e is always 0 (since both MSBs are 0). The sum is incorrect only if it is negative 01 = 1). 2. If both numbers are negative, e is always 1 (since both MSBs are 1). The sum is incorrect only if it is positive 01 = 1). 3. If numbers have opposite signs, V is always 0 and the sum if always correct. e can be either 0 or 1. In conclusion, the result of adding two numbers is incorrect only if V = 1. The branching instructions BVe and BVS can be conveniently used to check whether or not an overflow (and hence an arithmetic error) has occurred. For example, after ADD X,Y one can issue BVS ERRMSG to initiate an error message which announces the overflow.

94

ARITHMETIC OPERATIONS

CHAP. 7

7.2 CARRY AND OVERFLOW UNDER SUBTRACTION The way in which the C and V condition codes are influenced by the result of a subtraction operation (Le., by SUB or CMP instruction) is the following:

c = (I

if subtraction did not result in carry from MSB

o otherwise l if operands are of opposite signs and the result is of

V=

{o

the same sign as the number subtracted (source) otherwise

Examples Again, we shall use 4-bit words.

Example (Decimal)

4-bit 2'sComplement Subtraction

6 -(+3) 3

0110 +1101 ,0011 1

4 -(-2) 6

0100 +0010 -0110

4 -(-5)

9 -5

-(+7) -2 -3 -(+2) -5

-2 -(-5)

3

Final Value of V

o

o

OK

o

OK

0100 +0101 -1001

wrong

0101 +1001 1110 1101 +1110 ,1011 1 1110 +0101 .(0011 1

Binary Result is

C

o

OK

o

o

OK

o

o

OK

SEC. 7.3

95

DOUBLE-PRECISION ARITHMETIC

Example (Decimal)

4-bit 2'sComplement Subtraction

-4

1100 +1010 £0110 1

-(+6)

-10

Final Value of C

V

Binary Result is

wrong

°

Inspecting these examples we can conclude (as we did with addition) that the result of subtraction is incorrect only if V = 1. The negation operation (NEG), when applied to a nonzero number, results in C = 1; when it is applied to 0, it results in C = O. Notice that the negation of a number (which consists of 1's-complementing it and adding 1) produces a carry only when the number is O. Thus, a negation operation results in C = 1 if there is no carry, and in C =0 if there is carry.

7.3 DOUBLE-PRECISION ARITHMETIC In some applications the range of numbers accommodated by a single long word is not sufficient, and two consecutive long words are employed to store a number. In the 68000 a two long word, or double-precision, number is stored in a 64-bit 2's-complement form. The low order long word holds the least Significant bits of the number, while the high-order long word holds the most significant bits of the number. The MSB of the high-order long word is the sign bit of the entire number:

o 31

31

Sign~~__

H __ ig_h-_O_rd_e_r__________L -_ _ _ _ _ _ _L_O_w_-o_r_de_r______

- L_ _ _ _ _ _ _ _ _ _

o

~

2's-complement number

While a long word can handle numbers on the order of 2*10 9 , with double precision the 68000 can handle numbers on the order of 8*10 18 (more than the square, since we have 63 bits instead of31). How do we add two double-precision numbers, say a and b? Suppose that a is stored in AL and AH, b in BL and BH, and a + b is to be stored in BL and BH (where the suffix L denotes low-order long word and H high-order long word). To compute a + b it is not sufficient to issue ADD.LAL,BL followed by ADD.LAH,BH, since this will ignore a possible carry from the low-order long word. This carry, which is the value of C after the low-order addition is executed, must be added to BH (or to AH) just before the high-order addition is performed. This operation is facilitated by the instruction

96

ARITHMETIC OPERATIONS

CHAP. 7

ADDX source,destination which performs (destination) = (destination) + (source) + X, where X is the X condition code and is set to the same value as C whenever C is affected by an instruction. Thus, to compute a + b we issue

MOVE MOVE ADD.L ADDX.L

#AL,AO #BL,Al (AO),(Al) -(AO),-(Al)

!Examples For the remainder of this section, all examples will assume 4-bit long words. Example 1

Initially

Example 2

{AH AL BH BL

0001 1001 0011 0101

After ADD.L (AO),(A1)

{AH AL BH BL

0001 1001 0011 1110 (C = 0)

0001 1001 0011 0000 (C= 1)

After ADDX.L -(AO),-(Al)

{AH AL BH BL

0001 1001 0100 1110

0001 1001 0101 0000

+-a~

+-b~

+-a+b~

0001 1001 0011 0111

To negate a double precision-number a stored in AL and AH, we 1's-complement AH, 1's-complement AL, add 1 to AL, and add the resulting carry to AH. This can be accomplished by first negating AL (which performs the complement and the add 1) and then using the NEGX.L AH instruction which finishes the negation of the double precision number by setting AH to 0 - AH - X. This works because the NEG instruction sets the C (and hence the X) bit to 0 if there is a carry and 1 if not. Thus, if there is no need to carry, X = 1, and AH is set to 0 - AH - 1 which amounts to complement, add 1, subtract 1, and thus is equivalent to complementing. If there is a need to carry, X = 0, and AH is set to 0 - AH which is equivalent to a complement and add 1. Thus, to compute -a, we issue: NEG.L NEGX.L

AL AH

Examples Example 1

Initially After NEG.L AL After NEGX.L AH

AH AL AH AL AH AL

0101 1011 +-+a~ 0101 0101 (C = 1) 1010 0101 +- -a ~

Example 2

0101 0000 0101 0000 (C = 0) 1011 0000

SEC. 7.4

THE TST AND CMP INSTRUCTIONS

97

Suppose that a and b are stored as before and we wish to compute b - a and store it in BL and BH. We start by subtracting AL from BL. We now notice that the MSB resulting from this operation generates a carry only if no "borrow" is required in subtracting the leftmost digit of AL from the leftmost digit of BL. Hence, the C bit resulting from the subtraction of AL from BL is 1 only if a "borrow" is required from BH. When this is the case, the "borrowing" can be done with SUBX.L. [The SUBX instruction sets the destination to (destination) - (source) - X.] Thus, to compute b - a we issue:

MOVE MOVE

#AL,AO #BL,A1 (AO),(A1) -(AO),-(A1)

SUB.L SUBX.L

Examples Example 1

Initially

Example 2

{BH BL AH AL

0101 1001 0011 0101

After SUB.L (AO),(Al)

{BH BL AH AL

0101 0100 (C = 0) 0011 0101

0101 1101 (C= 1) 0011 1010

After SUBX.L -(AO),-(Al)

{BH BL AH AL

0010 0100 0011 0101

0001 1101 0011 1010

~b-+ ~a-+

~

b-a-+

0101 0111 0011 1010

From Sections 7.1 and 7.2 we know that the result of addition or subtraction is incorrect only if it produces overflow (Le., V = 1). In the double-precision case this means that the overall result is incorrect only if the high-order addition or subtraction produces V = 1; overflow produced by the low-order operation is irrelevant.

7.4 THE TST AND CMP INSTRUCTIONS The instruction CMP s,d (also CMPA, CMPI, and CMPM) forms the difference (d) - (s) inside the ALU in some inaccessible internal register (not in d!). Thus, CMP has no effect on either s or d. It is most often used to set the X, Z, N, C, and V condition codes to facilitate the comparison of (s) and (d). It is important to note that the X, C, and V codes resulting from CMP are set according to the rules of subtraction (stated in Section 7.2). We shall elaborate on the applications of CMP in Section 7.5. The instruction TST d is equivalent to (d) ~ (d). Its most common purpose is to set the Z and N condition codes to facilitate determining whether (d) is zero or nonzero, positive or negative.

ARITHMETIC OPERATIONS

98

CHAP. 7

Examples Results of Instruction Contents of CM Word Addressed 1000

0000 0100 0045 6275 8400 OOFA 0186 48BO FFD4 8516

TST 1000 N

Z

1 0 0 0 0 0 0 0 0 0

0 0 0 0 0 1 1 1 1 0

TST.B 1000 Z N

TST.B 1001 Z N

1 0 1 0 0 1 0 0 0 0

1 1 0 0 1 0 0 0 0 0

0 0 0 0 1 0 0 0 1 1

0 0 0 0 0 1 1

1 1 0

While TST is intended for testing entire bytes, words, or long words, the AND instruction can be used to test selected portions of words (or bytes or long words). For example, to branch to L if either bit 7 or bit 15 of DO (or both) are 1, we can issue: MOVE AND BNE

DO,D7 #$8080,D7 L

Note that the AND instruction changes the destination so that a copy usually needs to be made.

7.5 MORE ON BRANCH INSTRUCTIONS In Section 4.8 we listed 14 conditional branch instructions. Eight of them, BEQ, BNE, BPL, BMI, BVC, BVS, BCC, BCS are best suited to test whether the result of an arithmetic operation is zero or nonzero, positive or negative, did or did not cause overflow, and did or did not produce a carry. To compare two numbers, say a in A and b in B, it is most convenient to issue (since CMP A,B is not a valid instruction): MOVE B,DO CMP A,DO

SEC. 7.5

99

MORE ON BRANCH INSTRUCTIONS

(which foons b - a) and then any of the following instructions:

Signed conditional branches

Mnemonic

Branch to d if*

rE d

NVV=O NVV= I Zv(NVV)=O Z v (N V V) = I

(b>=a) (ba) (ba) (b b if (AH) > (BH), or if: (1 ) (AH) = (BH), and (2) (AL) > (BL), where (AL) and (BL) are unsigned! Thus, to jump to X if a > b and to Y otherwise, we write: MOVE.L CMP.L BGT BLT MOVE.L CMP.L

AH,DO BH,DO X

Y BL,DO AL,DO

SEC 7.5

MORE ON BRANCH INSTRUCTIONS

101

y

x

BLS EQU

y

EQU

*

*

Another use of the unsigned branch instructions is in testing for two conditions simultaneously. Suppose that we want to know if (DO) is less than 0 or greater than 7 and if so, to branch to location X. We can write:

CMP BGT TST BLT

#7,00 X DO X

An alternative solution is:

CMP BHI

#7,DO X

This works because a negative number, when treated as an unsigned number, is always "higher" than any positive number. It is worth mentioning that another solution would be AND BNE

#$FFF8,DO X

For a loop that involves testing a condition a given number of times (for example, looking through an array for a specified value), the DBcc (decrement and branch conditionally) instruction can be used. The form of the DBcc instruction is DBce

Dn,label

where ee is one of the allowed conditions for Bee, or T (true), or F (false). (Most assemblers allow DBRA as another way of saying DB F.) The effect of this instruction is as follows 1. If the condition specified by ec is true, go on to next instruction (no branch); 2. If the condition is false, decrement Dn and 2a. If (Dn) is -1 then go on to the next instruction; 2b. If (Dn) is not -1, branch to label. Note that the decrement and test is done until the condition is true, not if it is true. This makes the effect of the DBee condition essentially the opposite of that of

N

0

...

0011 - 0110 1101

1110 - 0010 ,r1100 1

3 - (+6) -3

-2 - (+2) -4

1010 -1010 ,r0000 1

1110 - 1011 ,r0011 1

-6 - (-6)

-2 - (-5) 3

0

-1

1101 -1110 1111

-3 -(-2)

-9

- (+5)

-4

0

1100 - 0101 ,r0111 1

0101 - 0101 ..,-0000 1

5 - (+5)

4

0111 - 0011 ,r0100 1

0

0

0

0

0

0

Z

Binary

7 - (+3)

"

,.

0

0

0

1

1

0

0

N

BRANCH EXAMPLES

....

Example

Decimal

,.

TABLE 7.1

0

0

0

0

1

0

0

C

0

0

0

0

0

0

0

V

0

0

0

0

'"NVV

...

0

1

1

0

0

0

0

1

0

ZV(NVV) CVZ

Resultant Condition Codes

./

./

./

./

BGE

,.

./

./

./

./

BLT

"

./

./

BGT

Signed Conditionals

./

./

./

./

./

./

BLE

...

./

./

./

./

./

./

./

./

BLOS

./

./

./

./

./

./

'" BHIS

...

./

./

BLO

Unsigned Conditionals

BHI

,

SEC. 7.6

SHIFT INSTRUCTIONS

103

the Bee condition. Also, the number of times through a loop that ends with a DBee instruction is one more than the starting value of Dn. Thus, Dn must be set to one less than the number of times needed to process the loop. (An alternative method is to branch to the DBee instruction to start the loop.) The value in Dn is viewed as being a word-sized value. As an example of the use of DBee, the following program segment searches an array starting at ARRAY for the value stored in X. The length of the array is stored in N.

LOOP

MOVE #ARRAY,AO MOVE N,DO SUBQ #I,DO MOVE X,DI EQU * CMP (AO)+,Dl DBEQ DO,LOOP TST DO BPL FOUND NUMBER NOT FOUND

;START OF ARRAY ;NUMBER OF ELEMENTS ;DBEQ CHECKS FOR-I ;NUMBER TO LOOK FOR ;CHECK FOR DESIRED VALUE ;LOOP BACK IF NOT FOUND ;-1 IF NOT FOUND ;NUMBER WAS FOUND

An instruction that can be used to save the result of a comparison for future testing and to aid in the computation of a compound logical expression (one with logical operations such as AND and OR) is the Sec (set according to condition) instruction. The form of the Sec instruction is:

See

destination

where ee is any of the conditions allowable on the DBee instruction, and the addressing mode of the destination is any mode except address register direct, the PC relative modes, or immediate. The effect of See is to set the destination byte to all 1s ($FF) if the condition is true, and all Os ($00) if the condition is false. Almost every instruction influences the Z and N condition codes. This means that a test instruction which one may be tempted to insert after an operation and before a branch instruction is actually redundant. For example, in: SUB TST BEQ

A,DO DO NEXT

the TST instruction is superfluous.

7.6 SHIFT INSTRUCTIONS The 68000 has a number of instructions that shift the contents of a word (or byte or long word) some number of bits to the left or right (see Figure 7.1):

ARITHMETIC OPERATIONS

104

ROL ROR ASL ASR LSL LSR ROXL ROXR

CHAP. 7

rotate left rotate right arithmetic shift left arithmetic shift right logical shift left logical shift right rotate left with extend rotate right with extend

Addressing modes allowed for the ROL, ROR, ASL, ASR, LSL, and LSR instructions are discussed in Section 4.3.5. Addressing modes allowed for ROXL and ROXR are the same as those for ROL and ROR. The above operations are word size. Byte and long word operations are defined analogously. To understand the operation of ROL and ROR, we take the destination word (or byte or long word) and form a "ring" by joining its ends. Assuming that the sequence of bits 0,1,2,3, ... in this ring is arranged in the counterclockwise direction, the effect of ROL is to rotate the contents of the ring counterclockwise, and the effect of ROR is to rotate the contents clockwise. (The C bit is set to the last bit that was shifted off the end, leftmost for ROL, rightmost for ROR.) The effect of ASL is to shift the contents of the destination word (or byte or long word) 1 bit left, with the rightmost bit replaced by O. The last bit shifted out of the leftmost bit is put into the C (and X) bit. This operation is equivalent to multiplying the contents of the destination (regarded as a 2's-complement signed number) by a power of 2. The V code is set to 1 if the result of this multiplication is out of bounds. The effect of ASR is to shift the contents of the destination word (or byte or long word) 1 bit right, with the leftmost bit remaining unchanged and the last rightmost bit shifted out replacing the old value of C (and X). This operation is equivalent to dividing the contents of the destination by a power of 2 (and truncating any fractional part). Examples (A)

After ASL A

After ASR A

0032 FFCE (=-32)

0064 (=32*2) FF9C (=-64)

0019 (=32/2) FFE7 (=-19)

LSL and LSR set the C (and X) bit to the last bit shifted out of the destination, and fill with zeros on the other end. ROXL and ROXR are similar to ROL and ROR except that the X bit is inserted in the "ring". For example, ROXR #1 ,DO rotates the ring formed by appending the X bit to DO to the right 1 bit. Thus, the rightmost bit of DO is moved into X, and the old X value is moved into the leftmost bit of DO. Like ADDX, SUBX, and NEGX, these are handy in dealing with double-precision values.

SEC. 7.7

105

EXAMPLE: ASCII-TO-BINARY CONVERSION

ROL

0

q

ROR

ASL

Operand

4

LSR

~

Operand

tEJ

Operand

~

0

I

~

r-G

Q5

Operand

Operand

I~

Operand

Figure 7.1

r-G

cgj

Operand

ROXL~ ROXR

~~

Operand

~

ASR

LSL

I=-:J

~

I

Shift instructions.

7.7 EXAMPLE: ASCI/-TO-BINARY CONVERSION

To illustrate the use of some of the instructions and features introduced in the preceding sections, we shall present a program which accepts a decimal number N from the terminal and converts it into a 16-bit 2's-complement form. N may be prefixed with + or - and is always followed by a carriage return. It should not exceed 32767 10 in magnitude.

ARITHMETIC OPERATIONS

106

String

CR

(05)-(05) - #'0' (A3) +-(05)

Figure 7.2

Flowcharts for ASCII-to-binary program.

CHAP. 7

SEC. 7.7

107

EXAMPLE: ASCII-TO-BINARY CONVERSION

Initialize sign flag, pointer and result.

(05)-0 (02)-0 (04)-((A3)) (A3)-(A3) + 1

(A3) = pointer to next character of N (04) = currently scanned character of N (05) = N'ssign flag (0 if N >= 0; 1 if N I
I) onto the system stack, using the macro PUSH of Example 5.

Definition

SAVE COUNT

COUNT

Call Expansion

(a)

COUNT COUNT

MACRO SET REPT PUSH SET ENDR ENDM

I,J I [J-I+l] /2 \ COUNT COUNT+2

SAVE

12,23

SET PUSH SET PUSH

12 \12 14 \14 [23-12+1]/2=6 macro calls

COUNT

(b)

COUNT COUNT

COUNT

SET PUSH SET MOVE SET MOVE

22 \22 12 TAB+12,-(SP) 14 TAB+14,-(SP)

SET MOVE

22 TAB-t22.-(SP)

Another useful directive is the IRP ("indefinite repeat") directive: ~heading

IRP

repeat block

} ENDR

~

terminator

SEC. 10.5

CONDITIONAL ASSEMBLY

163

where d is a dummy argument and al> a2, ... , ar are actual arguments. The assembler (during pass I) duplicates the repeat block r times, first with d replaced with at. next with d replaced with a2, and so forth. For example, to restore DO, D3, D4, and DS from the system stack without using MOVEM, we can write IRP MOVE ENDR

REG, (SP)+,REG

A similar directive is d,str

IRPC

+-

}

d

ENDR

heading repeat block

+-

terminator

where d is a dummy argument and "str" is a string of characters. The assembler duplicates the repeat block, first with d replaced by the first character of "str", next with d replaced by the second character of "str", and so on. For example, to restore DO, D3, D4, and DS from the system stack, we can write N,034S (SP)+,D 'N

IRPC MOVE ENDR

(As in macros, , serves to separate adjacent symbols but is deleted during duplication.)

10.5 CONDITIONAL ASSEMBL Y Conditional assembly directives enable the programmer to either include or exclude a segment of source code, depending on certain conditions. This facility is frequently used inside macro definitions, where parameter values (as defined during pass I of the assembly process) determine which version of the macro should be expanded. The general form of the conditional directive is: IF

cond,s

+}

ENDC

heading conditional block

+-

terminator

where "cond" specifies a condition that s mayor may not satisfy. If s does satisfy the

ADVANCED ASSEMBLY LANGUAGE TECHNIQUES

164

CHAP. 10

condition, the conditional block is assembled; otherwise it is ignored. Table 10.1 lists some of the allowable IF directives. If the directive IFF appears inside the conditional block, then the part of the block lying below the IFF is assembled only if the preceding IF condition is not satisfied (like an ELSE if Fortran or Pascal). Thus, the IFF directive partitions the block into two subblocks, only one of which is actually assembled. TABLE 10.1

CONDITIONAL DIRECTIVES

Directive

IF IF IF IF IF IF IF IF IF IF IF IF

Assemble Block If

EQ,s NE,s LT,s GT,s LE,s GE,s

DF,s NDF,s B, NB, IDN, DIF,

s= 0 s*O sO s= 0 s is defined s is not defined macro argument s is null (absent) macro argument s is not null (present) macro arguments sand t are identical macro arguments sand t are different

Examples

1. The macro BRANCH generates the instruction BRA X if the relative distance to X is less than $7FFF, and the instruction JMP X otherwise. Definition

BRANCH

MACRO IF BRA IFF JMP ENDC ENDM

X LT,*-X-$7FFF X

X

X must be defined when this macro is called (that is, the branch must be a backward branch). This restriction can be removed if your assembler allows the expression ABS(*-X)-$7FFF. 2.

BET A is a subroutine which may be nested either within a subprogram called

SEC. 10.5

CONDITIONAL ASSEMBLY

165

SUB1 (Le., whose first instruction is labeled SUB1) or within a subroutine called SUB2. If the nesting subprogram is SUB1, BETA is expected to start with +1 in DO; otherwise, BETA is expected to start with -1 in DO. (The rest of BETA is invariant.) This can be accomplished by opening BETA in the following manner: EQU IF MOVEQ IFF MOVE ENDC

BETA

* DF,SUBI #1 ,DO #-1 ,DO

For example, if the nesting program is SUB2, the program will look as follows: SUB2

EQU

BETA

EQU MOVE

* *

#-1 ,DO

3.

The intent of the macro IFP is to introduce a Pascal-like statement into an assembly language program. A call has the form: IFP

X,REL,Y ,THEN ,S 1,ELSE,S2

where REL is any of the relations EQ, NE, LT, GT, LE, and GE; where SI and S2 are single-line 68000 instructions (or, perhaps, macro calls); and where" ,ELSE,S2" is optional. Note that calling this macro is made tricky by the restrictions on addressing modes allowed by the CMP instruction.

Definition

IFP

MACRO LOCAL CMP B'REL IF S2 ENDC

X,REL,Y,THEN,S1,ELSE,S2 L,M Y,X L NB,

ADVANCED ASSEMBLY LANGUAGE TECHNIQUES

166

L M

Call

Expansion

??OOOO ??OOOI

??0002 ??0003

CHAP. 10

BRA EQU SI EQU ENDM

M

IFP

DO,GT,Dl,THEN,,ELSE,

IFP

SAM,LE,#JOE,THEN,

CMP BGT CLR BRA EQU SUB EQU CMP BLE BRA EQU MOVE EQU

* *

Dl,DO noooo

DO nOOOl

*

Dl,DO

* #JOE,SAM ??0002 nOO03

*

SAM,JOE

*

4. The macro MAX puts in DO the maximum of one to three arguments. The code generated depends on the number of arguments, which is determined by the NARG directive (see Section 10.2).

Definition

MAX

NEXT

OUT

MACRO LOCAL NARG MOVE IF IF CMP BGT MOVE ENDC EQU CMP BGT MOVE ENDC EQU ENDM

A,B,C NEXT,OUT K A,DO NE,K-l NE,K-2 C,DO NEXT C,DO

*

B,DO OUT B,DO

*

SEC. 10.5

CONDITIONAL ASSEMBLY

167

Call

Expansion

MAX

P

MAX

P,Q

MAX

P,Q,R

MOVE EQU

P,DO

MOVE CMP BGT MOVE EQU

P,DO Q,DO ??OOOI Q,DO

MOVE CMP BGT MOVE EQU CMP BGT MOVE EQU

P,DO R,DO ??0002 R,DO

(K=l)

??OOOO

*

(K=2)

??OOOI

*

(K=3)

??0002

??0003

*

Q,DO ??0003 Q,DO

*

S. Conditional assembly can be used to implement "macro recursion." The following macro is functionally equivalent to the previous example. The macro actually calls itself recursively, with the recursion terminating by virtue of the IF which checks to see if there is a second argument. Definition

MAX

NEXT

MACRO LOCAL IF MAX CMP BGT MOVE IFF MOVE ENDC EQU ENDM

A,B,C NEXT NB, B,C A,DO NEXT A,DO A,DO

*

ADVANCED ASSEMBLY LANGUAGE TECHNIQUES

168

Call

Expansion ??OOOO

nOO01

??0002

??0003

??0004

nOO05

MAX

P

MAX

P,Q

MAX

P,Q,R

MOVE EQU

P,DO

*

Q MAX MOVE Q,DO EQU * ENDM OF MAX Q CMP P,DO BGT ??0002 MOVE P,DO EQU * Q,R MAX MAX R MOVE R,DO EQU * ENDM OF MAX R Q,DO CMP BGT ??0004 Q,DO MOVE EQU * ENDM OF MAX Q,R CMP P,DO BGT ??0005 MOVE P,DO EQU *

EXERCISES

10.1. The macros MAC1 and MAC2 are defined as follows: MAC1

MACRO MOVE.B ENDM

K,X D'K,X+K

MAC2 I

MACRO SET

N,Z 0

CHAP. 10

CHAP. 10

EXERCISES

169

REPT MAC 1 SET ENDR ENDM

N \I,Z 1+1

Explain what MAC2 accomplishes and expand the call: MAC2

5,TEMP

10.2. (a) The macro STORE is defined by STORE

X,N

MACRO MOVE.B SET IF STORE ENDC ENDM

#I,X+I 1+1 NE,I-N

X,N

Expand the call

I

SET STORE

°

TAB,7

(b) Write a nonrecursive macro that takes the same action as STORE.

10.3. The macro FOO is defined as follows: FOO

MACRO CMP'BETA R5 DC.W IF DS.W IFF DS.B ENDC ENDM

R5,ITEMS,LENGTH,BETA DO,D1 ITEMS B, LENGTH LENGTH

Expand the calls L5

FOO FOO

,,IOO, ,,52

ADVANCED ASSEMBLY LANGUAGE TECHN IQUES

170

CHAP. 10

10.4. Write a subroutine POWSUB and a macro POWMAC each of which computes XN (where X is found in DO and N in Dl). Compare the subroutine with the macro, indicating their relative advantages and disadvantages. Would it be better to implement either recursively?

10.5. Write a macro XOR which, when called with XOR A,B, puts in DO the exclusive or of A and B. That is, DO will contain 1's only in those bits where A and B differ.

10.6. Write a macro JMPSR, headed JMPSR

MACRO

SUB ,REGS ,ARRAY

which stores the registers listed in REGS into a block of words starting at ARRAY, performs JSR SUB, and then restores the contents of all these registers. For example, the call: JMPSR

DPADD ,024 ,TEMP

stores DO, D2, and D4 in TEMP, TEMP+4, and TEMP+8; performs JSR DPADD; and then restores DO, D2, and D4.

10.7.

A fictitious computer called SIMCOM (SIMple COMputer) has one generalpurpose register called an accumulator (ACC). Its central memory and number representation are identical to those of the 68000. The following is its instruction set, written in SIMCOM assembly language (where d is a CM address): Instruction

LDA STO ADD SUB TRA TRZ TRN HALT

d d d

d d d d

Action

Load: (ACC) +- (d) Store: (d) +- (ACC) Add: (ACC) +- (ACC) + (d) Subtract: (ACC) +- (ACC) - (d) Transfer: Branch to d (unconditionally) Transfer on zero: Branch to d if (ACC) = 0 Transfer on negative: Branch to d if (ACC) Halt

? @

A B

C D

176

APPENDIX B

7-bit Hex Code 45 46 47 48 49 4A 4B 4C 40 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 50 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 60 6E 6F

Character

ASCII CHARACTER SET

Remarks

E F G H I J K L M N 0 P Q R S T U V W X Y Z [

\ ]

. a b c d e f g

h j

k 1 m n 0

Up arrow on some terminals. Underline, back arrow (~) on some terminals . Accent grave.

APPENDIX B

ASCII CHARACTER SET

177

7-bit

Hex Code 70 71

72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F

Character

Remarks

p q r

s t

u v w x

y

z

{ I I

} DEL

Tilde Delete, rub out

APPENDIX C 68000 ADDRESSING MODES

TABLE 1

Mode

ADDRESSING MODES

Register

Name of Mode

Effective Address

Explanation

Dn

Dn

Operand is in Dn

An

An

Operand is in An

(An)

(An)

(An)+

(An)

Autodecrement

-(An)

(An)

N(An)

(N+(An))

Address of operand is in An Address of operand is in An; (An)+-(An)+i after operand is fetched* (An)+-(An)-i before operand is fetched*; address of operand is in An. Address of operand is N + (An)

N(An,Am) or N(An,Dm)

(N+(An)+(Am))

N

(N)

N

(N)

000

m

001

m

010

m

011

m

Data Register Direct Address Reg. Direct Address Reg. Indirect Autoincrement

100

ITr

101

m

110

m

111

000

Address Reg. Indirect with Displacement Address Reg. Indirect with Index and Displacement Absolute Short

111

001

Absolute Long

178

Assembly Language

(N+(An)+(Dm) )

Address of operand is N+(An)+(Am) or N+(An)+(Dm) Address of operand is N (16-bit number) Address of operand is N (32-bit number)

APPENDIX C

TABLE 1

68000 ADDRESSING MODES

179

ADDRESSING MODES

Mode

Register

Name of Mode

111

010

111

011

111

100

PC Relative with Displacement PC Relative with Index and Displacement Immediate

Assembly Language

Effective Address

Explanation

N(PC)

(N+(PC))

Address of operand is N plus (PC)

N(PC,An) or N(PC,Dn)

(N+(PC)+(An))

#N

N

Address of operand is N+(PC)+(An) or N+(PC)+(Dn) Operand is the numberN**

(N+(PC)+(Dn))

*i = 1 for byte operation; i = 2 for word operation; i = 4 for long word operation. An exception: if A7 (SP, the stack pointer) is used for byte operation, then i = 2. **In some instructions, Mode 111 and Register 100 are used to indicate that another operand is in the status register (S R).

APPENDIX D 68000 INSTRUCTIONS

The following is a description of instructions available on the 68000. For further details on all instructions, see the M68000 16/32-BIT MICROPROCESSOR Programmer's Reference Manual. For convenience, below is an alphabetical list of the instructions described in this appendix: ABCD ADD ADD A ADD! ADDQ ADDX AND AND! AND! to CCR AND! to SR ASL ASR Bcc BCRG BCLR BRA BSET BSR BTST CRK CLR

180

CMP CMPA CMPI CMPM DBcc DNS DIVU EOR EORI EORI to CCR EORI to SR EXG EXT ILLEGAL

lMP JSR LEA LINK LSL LSR MOVE

MOVE from SR MOVE to CCR MOVE to SR MOVEUSP MOVEA MOVEM MOVEP MOVEQ MULS MULU NBCD NEG NEG X NOP NOT OR ORI ORI to CCR ORI to SR PEA RESET

ROL ROR ROXL ROXR RTE RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPV TST UNLK

APPENDIX D

68000 INSTRUCTIONS

181

In the tables that follow, abbreviations will be used for addressing modes. These abbreviations are:

DDIR ADIR INDR AINC ADCRDISP INDX ABSH ABLO PCDS PCIN -

data register direct address register direct address register indirect autoincrement autodecrement address register indirect with displacement address register indirect with index and displacement absolute short absolute long program counter relative with displacement program counter relative with index and displacement IMMD - immediate

An X in a table will indicate that the addressing mode is valid, a dash (-) will indicate invalid. Thus, in the following table, data register direct is a valid mode for source and destination, while absolute long is valid for destination but not valid for source.

Source Destination

DDlR ADlR lNDR AlNC ADCR DlSP lNDX ABSH ABLO PCDS PClN lHHD X X X X X X X X X X

ABOD - add binary coded decimal Adds the source operand and the X bit to the dest I nat Ion operand and stores the result In the destination. Both source and destination are viewed as binary coded decimal number$. The operation size must be byte. The Z bit Is cleared If the result Is not zero and unchanged If the result Is zero. The C and X bits are set If the operation produced a carry and c I eared I f not. The N and V bits are undefined (no way to know what the result Is). Source and destination operands must be either both data reg I ster direct or both autodecrement. No mI x I ng of modes Is allowed. DDIR ADIR INDR AINe ADCR DISP INDX ABSH ABLO PeDS PeIN I"MD

Source

X

DestInation

X

or DDIR ADIR INDR AINC ADCR DISP INDX ABSH ASlO PCOS PCIH IPUm

Source Destination

X X

~

APPENDIX D

182

ADD - add bInary

68000 INSTRUCTIONS

(see also ADDA. ADDI. ADDQ. and ADDX)

Adds the source operand to the destInatIon operand and stores the result In the destInatIon. The operatIon sIze may be byte. word. or long word. The N bIt Is set IF the result Is negatIve. cleared IF posItIve. The Z bIt Is set IF the result Is zero. cleared IF not. The V bIt Is set IF an overFlow Is generated. cleared IF not. The C bit fs set IF a carry Is generated. cleared IF not. The X bit Is set the same as the C bit. Address mode combinations FollowIng two tables:

can

be

taken

From

one

of

the

OOIR AOIR INOR AINC AOCR DISP INDX ABSH ABLO PCOS PCIN II1HO Source

X

x

Dest I nat Ion

x

x

x

x

x

OOIR AOIR INDR AINe ADCR OISP INDX ABSH ABLO PCDS PCIN 111110 X X X X X X X X X X X X

Source Cest I MIt Ion

)(

ADDA - add address (see also ADD. ADDI. ADDQ. and ADDX) Adds the source operand to the destination operand and stores the result in the destination. The operat Ion size may be word or long word. destination register Is set regardless or the size.

The

ent ire

Condition codes are not aFFected. Address table: Source Destination

mode

combinations

can

be

taken

rrom

the

rol lowing

ODIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN I"HD X X X X X X X X X X X X X

ADDI - add Immediate (see also ADD, ADDA, ADDQ. and ADDX) Adds the source operand to the destination operand and stores the result In the destination. The operation size may be byte, word, or long word.

APPENDIX D

68000 INSTRUCTIONS

183

The N bit is set IF the result is negative, cleared iF positive. The Z bit is set iF the result is zero, cleared iF not. The V bit is set iF an overFlow is generated, cleared iF not. The C bit is set iF a carry is generated. cleared iF not. The X bit is set the same as the C bit. Address table: Source Destination

mode

combinations

can

be

taken

From

the

Fol lowing

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD 'X X

X

X

X

X

X

X

X

ADDQ - add quick (see also ADD. ADDA. ADDI. and ADDX) Adds the source operand to the destinatIon operand and stores the result In the destination. IF the destinatIon is an address regIster. condlblon codes are not aFFected. Otherwise. the bits are aFFected as Follows. The N bit Is set IF the result Is negative. cleared IF posItive. The Z bit Is set IF the result Is zero. cleared IF not. The V bit Is set IF an overFlow Is generated, cleared IF not. The C bit Is set IF a carry Is generated. cleared IF not. The X bit Is set the same as the C bit. The source operand must be an Immediate number From 1 to 8. Address table: SoYrce Destination

mode

combinations

can

be

taken

From

the

Following

DO I R AD I R I NOR AINC AOCR DI SP I tIlX ABSH ABLO PCDS PC I N I l'iI'iD X

x

)(

)(

)(

x

x

ADOX - add with extend (see also ADD, ADDA, ADDI. and ADDQ) Adds the source operand and the X condition code to destination operand and stores the result In the destination.

the

The operation size may be byte. word. or long word. The N bit Is set IF the result Is negative, cleared IF pes It I vee The Z bit I s set I F the resu I t fs zero, unchanged IF not. (This Is to allow For a test For zero or a multiple-precisIon number.) The V bit Is set IF an overFlow Is generated. cleared IF not. The C bit Is set IF a carry Is generated. cleared IF not. The X bit Is set the same as the C bit.

68000 INSTRUCTIONS

APPENDIX D

184

Source and destination operands must be either both data reg I ster dIrect or both autodecrement. No mI x I ng or modes Is allowed.

OOIR ADIR INOR AINC ADCR OISP IHOX ABSH ABlO PCOS PCIN 1""0 Source Destination Source Destination

AND -

X

X

or DOIR ADIR INOR AINC ADCR OISP INOX ABSH ABlO PCOS PCIN II'lI'lD X X

logical and (see also ANOI) Forms the logical AND or the source operand to the destination operand and stores the result In the destInation. The operation size may be byte. word. or long word. The N bit Is set Ir the result Is negative. cleared Ir positive. The Z bit Is set IF the result Is zero. cleared IF not. The V and C Flags are always cleared. The X bit Is not arFected. Address mode combinations Following two tables:

can

be

taken

From

one

of

the

DOIR ADIR INOR AliIIC AOCR OISP INOX ABSH ABlO PCOS PCIN II1KO Source Destination

X

X

x

X

x

x

X

ODIR PlDIR fNOR AfiIIC AOCR OISP INOX flBSH ABLO PeDS PCIN 111110 Source DestinatIon

ANOK -

X X

X

X

X

X

X

X

X

X

X

X

logical and Immediate (see also ANO)

Forms the logical AND or the source operand to the destination operand and stores the result In the destinatIon. The operatIon size may be byte. word. or long word. The N bit Is set IF the result Is negative. cleared IF positive. The Z bit Is set IF the result Is zero. cleared IF not. The V and C Flags are always cleared. The X bit Is not aFFected. Address table:

mode

combinations

can

be

taken

From

the

Following

APPENDIX D

68000 INSTRUCTIONS

Source Dest Inat Ion

185

DDIR ADIR INOR AINe ADCR OISP INOX ABSH ABLO PCDS PCIN l"ltO X

x

x

x

X

x

AMDI to COR - and Immediate to condition code register Perrorms logical AND or source operand with the condition code register (the lower byte or the SR) and stores the result In the conditIon code register. The operation size must be byte. Cond It' on codes are operation.

set

to the

resu I t

or

the

log' ca I

AND

The source addressing mode must be Immediate. and the destInation must be "CCR" (IndicatIng the condItion code register).

AMOK to SR - and Immediate to status register Perrorms logical AND the result In the SR.

or

source operand with the SR and stores

The operation size must be word. Cond I t Ion operation.

codes are

set

The source addressing destination must be "SR".

to the mode

resu I t

must

be

or

the

log I ca I

Immediate.

and

AND

the

ASL - arithmetic shirt lert Sh I rts the dest I nat Ion operand 1ert. The number of bit s to shift is given by the source operand. The bits shifted out of the leftmost bit are put in the C and X flags. Bit 0 Is rilled with 0 after every bit shift. The operation size may be byte. word. or long word. A11 condit ion codes are affected by thi s Instruction. The N bit is set if the result is negative. cleared If positive. The Z bit I s set I f the resu 1t i s zero. cleared I f not. C and X are described above. The V bit Is set if the most significant bit Is changed at any time dur I ng the sh I ft I ng operat i on and cleared otherwise.

APPENDIX D

186

There are three forms of the ASL Instruction. 1)

They are:

both operands data registers

Source Destination 2)

68000 INSTRUCTIONS

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X

source Immediate, destination data register

Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X

3) source implied to be 1 (single bit shift) and destination taken from the following table Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X X X X X X

ASR - arithmetic shift right

Sh I fts the dest I nat Ion operand right. The number of bit s to shift Is given by the source operand. The bits shifted out of the rightmost bit are put In the C and X flags. The most significant bit Is unchanged, effectively extending the sign bit to the right. The operation size may be byte, word, or long word. AI I cond i t Ion codes are affected by th is I nstruct I on. The N bit Is set If the result Is negative, cleared If positive. The Z bit Is set If the result Is zero, cleared If not. C and X are descrIbed above. The V bit Is cleared. There are three forms of the ASR InstructIon. 1)

both operands data regIsters

Source DestInation 2)

They are:

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PeIN IHHD X X

source Immediate, destination data register

Source DestInation

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PeIN IHHD X X

3) source Implied to be 1 (single bit shift) and destination taken from the following table Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PCIN IHHD X X X X X X X

APPENDIX D

68000 INSTRUCTIONS

187

Bee - branch conditionally Branch to address given by destination if condition is true. Address given In machine language offset. No addressing modes apply.

as

either

byte

or

word

Condition codes are not affected. Possible values for cc and their meanings are Code EQ

NE GT LT

GE LE HI LS PL

MI CC CS VC VS

Meaning equal not equal greater than less than greater or equal less or equal high low or same plus minus carry clear carry set overflow clear overflow set

Test (I=true, O=false)

z

-Z N~VQ-Z

+

-N~-VQ-Z

N"-V + -NQV N"V + -N"-V Z + N"-V + -N"V

N

-C C

-v V

means complement + means or " means and

BCHG - test a bit and change Tests bit In the destination and then changes it. The number of the bit to test is given by the source operand. The test result is reflected in the Z code. The tested bit is changed - set to 1 if it is initially 0, cleared if Initially I. The operation size is byte if the destination Is a memory location and long word If the destination is a data register. The Z code is set to 1 if the bit tested is zero and cleared if It is one. The other codes are not affected.

Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X X X X X X X X X

APPENDIX D

188

68000 INSTRUCTIONS

BCLR - test a bit and clear Tests bit In the destination and then clears It. The number of the bit to test Is given by the source operand. The test result Is reflected in the Z code. The tested bit is cleared - set to O.

",

The ope rat I on size I s byte I f the dest I nat I on I s a memory location and long word If the destination Is a data register. The Z code Is set to 1 If the bit tested Is zero and cleared if It is one. The other codes are not affected.

Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X X X

BRA - branch always Branch to address given by destination. Address given In machine language offset. No addressing modes apply.

as

either

byte

or

word

Condition codes are not affected.

BSET - test a bit and set Tests bit In the destination and then sets It. The number of the bit to test Is given by the source operand. The test result is reflected In the Z code. The tested bit Is set to 1. The operat I on size I s byte I f the dest I nat I on I s a memory location. and long word If the destination Is a data register. The Z code Is set to 1 If the bit tested Is zero and cleared if It Is one. The other codes are not affected.

Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X X X

BSR - branch to subroutine Branch to subroutine at address given by destination. The long word address of the word Immediately following the BSR instruction is pushed onto the system stack before the branch. Address given In machine language offset. No addressing modes apply. Condition codes are not affected.

as

either

byte

or

word

APPENDIX D

68000 INSTRUCTIONS

189

BTST - bit test Tests bit in the destination. The number of the bit to test Is given by the source operand. The test result Is reflected In the Z code. The operat Ion size I s byte I f the dest I nat I on I s a memory location and long word If the destination Is a data register. The Z code Is set to 1 If the bit tested Is zero and cleared If It Is one. The other codes are not affected. Address mode combinations following two tables:

can

be

taken

from

one

of

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 111110 Source Destination

X X

X

X

X

X

X

X

X

X

X

X

or Source Destination

CHK -

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 111110 X )( X X X X X X X X X

check data register against bounds Tests a data register given by the destination against an upper bound given by the source operand. 1f" the dest I nat Ion va I ue I s positive and less than or equal to the source value, then the only eff"ect of" the I nstruct I on I s on the cond I t Ion codes. 1f the dest I nat Ion va I ue Is negat I ve or greater than the source va I ue, then a trap through address $18 takes place. The operation size must be word. The N code Is set to 1 If" the data register tested is negative and cleared If" It Is positive. The X code Is not af"f"ected. The Z, V, and C codes are lef"t undefined - they could be 0 or I with no real way of" knowing which. DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 111110

Source Destination

X

)()()(

X

)(

)(

)(

)(

)(

)(

X

CLR - clear C I ears (sets to zero) the dest.1 nat I on I ocat Ion. The operation size may be byte. word, or long word. set.

The N. C. and V bits are always cleared. The X bit Is not af"fected.

The Z'bit Is always

APPENDIX D

190

68000 INSTRUCTIONS

Address mode can be taken from the following table: Destination

C"P - compare

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X

{see also CMPA. CMPI. CMPM}

Subtracts the source operand from the destination but does not change the destination. Only condition codes are affected by this instruction. The operation size may be byte. word. or long word. The N bit is set if the result is negative. cleared if positive. The Z bit is set if the re"sult is zero. cleared if not. The V bit is set if an overflow is generated. cleared if not. The C bit is set if a borrow is generated. cleared If not. The X bit is not affected. Address table: Source Destination

mode

combinations

can

be

taken

from

the

following

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PeIN IHMD X X X X X X X X X X X X X

C"PA - compare address

{see also CMP. CMPI. CMPM}

Subtracts the source operand from the destination but does not change the destination. Only condition codes are affected by this instruction. The operation size may be word or long word. but word length source operands are sign extended to 32 bits before the operation is done. The N bit is set if the result is negative. cleared if positive. The Z bit Is set If the result Is zero. cleared if not. The V bit Is set If an overflow is generated. cleared If not. The C bit is set if a borrow is generated. cleared if not. The X bit is not affected. Address table: Source Destination

mode

combinations

can

be

taken

from

the

following

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PCIN IMMD X X X X X X X X X X X X X

APPENDIX D

68000 INSTRUCTIONS

CMPI - compare Immediate

191

{see also CMP, CMPA, CMPM}

Subtracts the source operand from the destination but does not change the destination. Only condition codes are affected by this instruction. The operation size may be byte, word. or long word. The N bit is set If the result Is negative, cleared If positive. The Z bit Is set If the result Is zero, cleared if not. The V bit Is set If an overflow Is generated, cleared If not. The C bit is set If a borrow is generated. cleared If not. The X bit Is not affected. Address table:

mode

combinations

can

be

taken

from

the

fol lowing

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN I""D Source Destination

X X

C"P" - compare memory

X

X

X

X

X

X

X

{see also CMP, CMPA. CMPI}

Subtracts the source operand from the destination but does not change the destination. Only condition codes are affected by this instruction. The operation size may be byte, word, or long word. The N bit is set if the result is negative, cleared if positive. The Z bit is set if the result Is zero, cleared if not. The V bit Is set If an overflow is generated, cleared if not. The C bit Is set If a borrow Is generated, cleared If not. The X bit Is not affected. Both source and destination operands must be autoincrement:

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PCIN 1""0 Source Destination

X X

DBcc - decrement and branch conditionally Branch to address gIven by destInatIon and decrement source data regIster If condItIon Is false and the source data regIster Is posItIve. Source operand must be a data reg I ster • Oest I nat I on address that Is gIven In machIne language as an offset.

I s an

APPENDIX D

192

68000 INSTRUCTIONS

Source operation size must be word. Condition codes are not Possible values Code T F

~or

a~~ected.

cc and their meanings are Test (I=true. O=~alse) I (always true) o (always ~else)

Meaning true ~alse

egual not equal greater than less than greater or equal less or equal high low or same plus minus carry clear carry set over~low clear over~low· set

EQ

NE GT LT

GE LE HI

LS PL MI CC CS VC VS

Z

-Z

N*V·-Z + -N"-V·-Z N*-V + -N"V N*V + -N*-V Z + N"-V + -N"V -C*-Z

-C C

-V V

means complement

+ means or * means and Note: Many programmers ~ I nd that the most use~u I vers I on o~ this Instruction Is OBF (some assemblers accept OBRA). This can be used to program a counting loop very e~~Iclently as ~ollows:

LOOP

MOVE EQU

#n-I,OO

OBRA

OO,LooP

OIVS - divide signed

;LooP n TIMES

"

(see also DIVU)

Divides the destination operand by the source operand and stores the resu I t I n the dest I nat i on. The dest i nat Ion I s a long word operand and the source I s a word operand. The d f vis i on Is done using Signed arithmetic (MSBs are viewed as sign bits). The lower word o~ the destinatIon Is set to the integer quotient, and the upper word to the remainder. Division by zero causes a trap. If overflow Is detected before the completion of the operation, the destination is not changed. The N bit is set if the quotient Is negative, cleared if positIve, undefIned if overflow. The Z bit Is set if the quotient Is zero. cleared if not, undefined if overflow. The V bit is set if an overflow Is generated, cleared If not. The C bIt is always cleared. The X bit is not affected. The destination operand must be a data register, the source may be any mode except address regIster dIrect.

APPENDIX D

68000 INSTRUCTIONS

Source Destination

193

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X X X X X

DIVU - divide unsigned

(see also DIVS)

o I v I des the dest I nat Ion operand by the source operand and stores the resu I t i n the dest I nat I on. The dest I nat I on I s a long word operand and the source I s a word operand. The d I v I s I on Is done using unsigned arithmetic (MSBs are not viewed as sign bits. the numbers are assumed positive). The lower word of the destination Is set to the Integer quotient. and the upper word to the rema I nder. 0 I v I s Ion by zero causes a trap. If overf I ow Is detected before the completion of the operation, the destination Is not changed. The N bit I s set to the MSB of the quot I ent I f no overf I ow. undefined If overflow. The Z bit Is set If the quotient Is zero. cleared If not. undefined If overflow. The V bit Is set If an overf low I s generated, c I eared I f not. The C bit I s a I ways cleared. The X bit Is not affected. The destination operand must be a data register. the source may be any mode except address register direct. Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X X X X X

EOR - logical EXCLUSIVE OR

(see also EORI)

Forms the logical EXCLUSIVE OR of the source operand and the destination operand and stores the result In the destination. The operation size may be byte, word, or long word. The N bit Is set If the result Is negative, cleared If positive. The Z bit Is set If the result Is zero, cleared If not. The V and C bits are always cleared. The X bit Is not affected. Address table: Source Destination

mode

combinations

can

be

taken

from

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X X

following

194

68000 INSTRUCTIONS

APPENDIX D

EORI -

logical EXCLUSIVE OR Immediate

(see also EOR)

Forms the logical EXCLUSIVE OR of the source operand and the destination operand and stores the result In the destination. The operation size may be byte, word, or long word. The N bit Is set IF the result Is negative, cleared iF positive. The Z bit is set iF the result is zero, cleared IF not. The V and C bits are always cleared. The X bit is not aFFected. Addres s table: Source Destination

EORI to CCR -

mode

como I nat Ions

can

be

taken

From

the

Fo I low I ng

DDIR ADIR INOR AINC ADCR DISP INDX ABSH ABLO PeDS PeIN 1""0 X X X X X X X X X X

logical EXCLUSIVE OR immediate to condition code register

Forms the logical EXCLUSIVE OR of the source operand and the CCR (condition code register, the low byte of the SR) and stores the result In the CCR. The operation size must be byte. The condition codes are set based on the result of the logical operation. The source operand must be Immediate.

EORI to SR -

logical EXCLUSIVE OR immediate to status register

Forms the logical EXCLUSIVE OR of the source operand and the SR and stores the result In the SR. The operation size must be word. The condition codes are set based on the result of the logical operation. The source operand must be immediate.

EXG - exchange two registers Exchanges the contents of the source and destination registers. The operation size must be long word (Full register exchange). Condition codes are not aFFected.

APPENDIX D

195

68000 INSTRUCTIONS

Both operands must be reg i ster direct but may be either data registers or address registers (or one of each). DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD

X X

Source Destination

X X

EXT - sign bit extend Extends the sign bit of the specified data register. sized operations it copies bit 7 Into bits 8 through 15. word operations It copies bit 15 Into bits 16 through 32.

For word For long

The operation size can be either word or long word. The N bit is set If the result Is negative, cleared if positive. The Z bit Is set If the result Is zero, cleared if not. The V and C bits are always cleared. The X bit Is not affected. There is no source operand. data register. Destination

The destination operand must be a

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMHD X

ILLEGAL - Illegal Instruction This Is an assembly language instruct Ion that generates the It same machine language as the DC.W $4AFC pseudo-instruction. causes an Illegal Instruction trap. Condition codes are not affected. There are no operands for this Instruction.

J"P - jump

(see also BRA)

Causes an unconditional branch to the address specified by the destination operand. This operation is unslzed. Condition codes are not affected. There I s no source operand. The mode of the operand can be taken from the following table. Destination

dest I nat Ion

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X X X X X X

68000 INSTRUCTIONS

APPENDIX D

196

JSR - jump to subroutine

(see also BSR)

Jump to the subroutine at the address given by the destination. The long word addres s of' the word I mmed I ate I y f'o I low I ng the JSR instruction Is pushed onto the system stack bef'ore the branch. This operation Is unslzed. Condition codes are not af'f'ected. There I s no source operand. The mode operand can be taken f'rom the f'ollowing table. Destination

of'

the

dest I nat Ion

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X

LEA - load ef'f'ectlve address Set the dest I nat i on address source operand.

reg I ster to the

address of' the

The operation size must be long word. Condition codes are not af'f'ected. The destination must be an address register. The mode of' the source operand can be taken f'rom the f'ollowlng table. Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X )()()( X X X X

LINK - link and allocate

(see also UNLK)

The long word contents of the source address register Is pushed onto the stack. Next, the updated SP I s moved I nto the source address register. Finally, the Immediate destination operand value I s added to the SP. A negat I ve dest I nat Ion operand I s used to a I locate stack area since the system stack grows toward lower addresses. Thus, the LINK and UNLK I nstruct Ions can be used to allocate and deal locate space for local variables In subroutines. Condition codes are not aff'ected. The source operand must be an destination must be Immediate data.

address

register,

DDIR ADIR INDR AINC ADCR DISP IMDX ABSH ABLO PCDS PCIM IMHD Source Destination

X X

and

the

APPENDIX D

LSL -

68000 INSTRUCTIONS

197

logical shift left Sh i fts the dest i nat i on operand I eft. The number of bits to shift is given by the source operand. The bits shifted out of the leftmost bit are put In the C and X flags. Bit 0 is filled with a after every bit shift. The operation size may be byte. word. or long word. AI I cond i t i on codes are affected by th I s I nstruct I on. bit Is set If the result is negative. cleared If positive. bit Is set If the result is zero. cleared if not. C and described above If the shift count is not zero. If the shift Is zero, the C bit Is cleared and the X bit Is unaffected. bit is always cleared (compare to ASL). There are three forms of the LSL Instruction. 1)

They are:

both operands data registers

Source Destination 2)

The N The Z X are count The V

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PCIN IMMD X X

source Immediate, destination data register DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMHD

Source Destination 3)

X

source Implied to be 1 (single bit shift) and destination taken from the following table

Destination

LSR -

x

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMHD X X X X X X X

logical -shift right Sh I fts the dest I nat Ion operand right. The number of bit s to shift Is given by the source operand. The bits shifted out of the rightmost bit are put in the C and X flags. The most significant bit Is filled with a after every bit shift (compare to ASR). The operation size may be byte. word. or long word. AI I cond i t i on codes are affected by th I s I nstruct Ion. bit Is set If the result Is negative, cleared If positive. bit Is set If the result Is zero, cleared If not. C and described above if the shift count is not zero. If the shift is zero, the C bit Is cleared and the X bit is unaffected. bit Is always cleared.

The N The Z X are count The V

APPENDIX D

198

There are three rorms or the LSR Instruction. I)

68000 INSTRUCTIONS

They are:

both operands data registers

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 Source Destination 2)

source Immediate, destination data register

Source Destination 3)

X X

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X

source Implied to be 1 (single bit shift) and destination taken from the following table

Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X X X X X X

ttOVE - move data rrom instructions)

source

to

dest i nat i on

(see

other

MOVE

Sets destination operand to value or source operand. The operation size may be byte, word, or long word. The N bit is set Ir the value moved Is negative, cleared ir positive. The Z bit is set ir the value moved is zero, cleared ir not. The V and C bits are always cleared. The X bit is not arrected. Addressing mode combinations can be taken rrom the rollowing table.

Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X X X X X X X X X X X X X X X X X X X

ttOVE From SR - move data rrom status register to destination MOVE instructions)

(see other

Set destination operand to value In status register. The operation size must be word. Condition codes are not arrected. The source operand must be the status reg i ster (SR). The destination operand's mode can be taken rrom the rollowing table. Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X X X X X X X

APPENDIX D

199

68000 INSTRUCTIONS

HOVE to CCR - move data rrom source to other MOVE Instructions)

cond I t I on

code

reg I ster

(see

Move value or source operand Into low byte or status register. Operation size must be word, but only the low byte Is actually moved. Th I s means that an even address must be spec I r I ed ror source operands that are In memory. Condition codes are set based on the source value. The destination must be "CCR", the source operand's mode can be taken rrom the rollowlng table.

Source

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN X X X X X X X X X X

ttOVE to SR - move data rrom source to status register Instructions)

I~HD

X

(see other MOVE

Move value or source operand Into the status register. The operation size must be word. Condition codes are set based on the source value. The destination must be "SR", the source operand's mode can be taken rrom the rol lowing table.

Source

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN X X X X X X X X X X

HOVE USP - move user stack pointer

IH~D

X

(see other MOVE Instructions)

Move the contents or the user stack pointer (USP) to an address register, or move the contents rrom an address register to the USP. The operation size must be long word (entire register moved). Condition codes are not arrected. Either the source or destination must be "USP", and the other must be an address register. [MOVE USP,An or MOVE An.USPJ

HOVEA - move address Move source destination.

(see other MOVE Instructions) operand

va 1 ue

to

addres s

reg i ster

spec I r i ed

by

Operation size may be word or long word. but word size operands are sign extended to ril 1 the entire destination register.

200

APPENDIX D

68000 INSTRUCTIONS

Condition codes are not affected. The destInation must be an address regIster. The addressing mode for the source operand may be taken from the fol lowing table. Source DestInatIon

OOIR AOIR INOR AINC AOCR OISP INOX ABSH ABLO PCOS PCIN IHHO X X X X X X X X X X X X X

OOOVE" - move multiple registers

A specified list of registers Is moved to or from consecutive memory locations. To specify the list of registers to move, a dash (-) Is used to Indicate a range of registers. and a slash (/> Is used to separate registers and ranges. For example. In order to specify that 00. 03. 04. 05. 06. AI. A2. A3. and A6 are to be moved. the register list DO/03-D6/AI-A3/A6 could be used. . The order of movement depends on the addressIng mode used. below for further explanation.

See

The operation size can be word or long word. ConditIon codes are not affected. If the source operand Is a register list. the destInation can be taken from the following table. DDIR ADIR INOR AINC ADCR OISP INDX ABSH ABLO PODS PCIN 1""0 DestInation

X

X

)(

X

X

If the destination operand Is a register list, the source can be taken from the following table. OOIR AOIR INDR AINC ADCR OISP INOX ABSH ABLO PCDS Pelt-! 114"0 Source

X

X

X

X

X

)(

X

X

1f the addres sIng mode Is anyth I ng except auotodecrement. the order of movement Is A7 ••••• AO. 07 ••••• 00. If the autodecrement mode I s used. the order of movement Is 00. •••• 07. AO. •••• A7. ThIs Insures that the r.eglsters moved to memory wIll be restored In the proper order.

~VEP

- move peripheral data

Move data from data reg i ster to alternate bytes I n memory or from alternate bytes in memory to data register. Thus a MOVEP of the value $1234 to the address $7001 will set byte $7001 to $12 and byte $7003 to $34. The operation sIze can be word or long word.

APPENDIX D

68000 INSTRUCTIONS

201

Condition codes are not aFFected The operand that is not a data register must be speciFied using address register indirect with displacement.

Source Destination Source Destination

~VEQ

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PC OS PCIN IHHD X X or DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X

- move quick Move immediate byte size number to data is automatically sign bit extended to Fi 11 The number is stored I n such a way as to Instruction than the other MOVE instructions

register. The number the entire register. make MOVEQ a Faster (see Appendix E).

The operation size must be long word. The N bit Is set IF the result Is negative, cleared IF positive. The Z bit is set IF the result is zero, cleared iF not. The V and C bits are always cleared. The X bit is not aFFected. The below. Source Destination

only

possible

addressing

mode

combination

is

indicated

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X

MULS - multiply signed

(see also MULU)

Multiply two signed word size operands and store the product as a long word value. The operand sizes must be word. word.

The product size must be long

The N bit Is set IF the result is negative. cleared IF positive. The Z bit is set IF the result Is zero. cleared IF not. The V and C bits are always cleared. The X bit is not aFFected. Address i ng mode comb I nat Ions can be taken From the Fo 1 low I ng table. Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X X X X X

202

APPENDIX D

"ULU - multiply unsigned

68000 INSTRUCTIONS

(see also MULS)

Multiply two unsigned word size operands and store the product as a long word value. The operand sizes must be word. word.

The product size must be long

The N bit Is set Ir the MSB or the result Is one. cleared Ir It Is zero. The Z bit Is set Ir the result Is zero. cleared Ir not. The V and C bits are always cleared. The X bit Is not arrected. Address I ng mode comb I nat ions can be taken rrom the ro II ow i ng table.

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X X X X X X X X X X

Source

DestinatIon

X

NBCD - negate binary coded decimal Negate (subtract rrom zero) the binary coded decImal value In the destination operand. Store the result in the destination. The operation size must be byte. The N and V bits are under I ned (no way to know what the I r values are). The Z bit is unchanged ir the result Is zero. cleared If not. The C bit Is set If a borrow Is generated. cleared if not. The X bit Is set the same as the C bit. There I s no source operand. The address I ng mode destination operand can be taken from the following table.

Destination

for

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X X X X X X X

NEG - negate Negate (subtract from zero) the value operand. Store the result In the destination.

In

the

destination

The operation size may be byte. word. or long word. The N bit Is set If the result is negative. cleared if positive. The Z bit is set if the result is zero. cleared if not. The V bit Is set If an overflow Is generated. cleared if not. The C bit Is cleared if the result Is zero. set Ir not. The X bit is set the same as the C bit.

APPENDIX D

68000 INSTRUCTIONS

203

There Is no source operand. Addressing mode for destination operand can be taken from the following table. Destination

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X X X X X X X

NEGX - negate with extend Adds the destination operand and the X bit, and then the sum is negated (subtracted from zero). The result Is stored in the destination. The operation size may be byte, word, or long word. The N bit Is set If the result Is negative, cleared If positive. The Z bit is unchanged If the result Is zero, cleared If not. The V bit is set If an overflow is generated, cleared if not. The C bit is set If a borrow is generated, cleared If not. The X bit Is set the same as the C bit. There Is no source operand. Addressing mode for destination operand can be taken from the following table. Destination

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMHD X X X X X X X X

NaP - no operation Performs no operat Ion. Execut I on cont I nues with the next instruction. Used for putting space in programs for debugging and for self-modifying code. This operation Is

~nslzed.

There are no source or destination operands.

NOT -

logical not (complement) Forms logical complement of the value In operand. Stores the result In the destination.

the

destination

The operation size may be byte. word. or long word. The N bit Is set If the result Is negative, cleared if positive. The Z bit Is set If the result Is zero, cleared if not. The V and C bits are always cleared. The X bit Is not affected.

204

68000 INSTRUCTIONS

APPENDIX D

There Is no source operand. Addressing mode for destination operand can be taken from the following table. Destination

the

DOIR ADIR INOR AINC ADCR OISP INOX ABSH ABLO PCOS PeIN 1""0 X X X X X X X X

OR - logical or

(see also ORI)

Forms the logical OR of the source operand and the destination operand and stores the result In the destination. The operation size may be byte. word. or long

wor~.

The N bit Is set If the result Is negative. cleared If positive. The Z bit Is set If the result Is zero. cleared If not. The V and C bits are always cleared. The X bit Is not affected. Address mode combinations following two tables:

Source Destination

Source Destination

can

be

taken

from

one

of

the

DDIR ADIR INOR AINe ADCR DISP INDX ABSH ABlO PeDS PCIN 1""0 X

X

x

x

x

x

x

x

DDIR ADIR INDR AINe ADCR DISP INDX ABSH ABlO PCOS PCIN 1""0 X

X

X

X

X

X

X

X

X

X

X

X

ORr - logical or Immediate

(see also OR)

Forms the logical OR of the source operand and the destination operand and stores the result In the destinatIon. The operation size may be byte. word. or long word. The N bit Is set If the result Is negative. cleared If positive. The Z bit Is set If the result Is zero. cleared If not. The V and C bits are always cleared. The X bit Is not affected. Address table.

Source Destination

mode

combinations

can

be

taken

from

the

DDIR ADIR INOR AINC ADCR DISP INDX ABSH ABlO PCOS PCIN 1""0

x

x

X

x

x

X

X

following

APPENDIX D

68000 INSTRUCTIONS

ORI to CCR -

205

logical or Immediate to condition code register

Perrorms logical OR or source operand with the condition code register (the lower byte or the SR) and stores the result in the condition code register. The operation size must be byte. Condition operation.

codes

are

set

to

the

result

or

the

logical

OR

The source addressing mode must be Immediate. and the destination must be "CCR" (Indicating the condition code register).

ORI to SR -

logical or Immediate to status register

Perrorms logical OR or source operand with the SR and stores the result In the SR. The operation size must be word. Condition operation.

codes

are

set

The source addressing destination must be "SR".

to

the

mode

result

must

be

or

the

logical

Immediate.

OR

and

the

onto

the

PEA - push errectlve address Push the system stack.

errect i ve

address

or the

source

operand

The operation size must be long word. Condition codes are not arrected. The destination is Implied to be the system stack and is not speciried on the Instruction. The addressing mode ror the source operand can be taken rrom the rollowing table.

Source

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PeIN 1""0 X X X X X X X

RESET - reset external devices Sends a reset signal to all external devices. This operation Is unslzed.

206

APPENDIX D

68000 INSTRUCTIONS

Condition codes are not aFFected. There are no operands For this Instruction.

ROL -

rotate left Sh i fts the dest I nat Ion operand 1eft. The number of bits to shiFt is given by the source operand. The bits shifted out of the leFtmost bit are put In the C bit and bit 0 of the destination. Thus, the shift is circular. The operation size may be byte, word, or long word. The N bit is set if the result Is negative: cleared if positive. The Z bit is set If the result is zero, cleared if not. The C bit Is described above. The V bit Is always cleared. The X bit Is not affected. There are three forms of the ROL Instruction. I)

both operands data registers

Source Destination 2)

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X

source Immediate, destination data register

Source Destination 3)

They are:

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X

source Implied to be 1 (sIngle bit shift) and destination taken from the following table

Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMHD X X X X X X X

ROR - rotate right Shifts the destination operand right. The number of bits to shift Is given by the source operand. The bits shifted out of the rightmost bit are put in the C bit and the leftmost bit of the destination. Thus, the shift is circular. The operation size may be byte, word, or long word. The N bit Is set If the result is negative, cleared If positive. The Z bit Is set If the result Is zero, cleared If not. The C bit Is described above. The V bit is always cleared. The X bit is not affected.

APPENDIX D

68000 INSTRUCTIONS There are three Forms of the ROR Instruction. I)

207

They are:

both operands data registers

Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PeIN IMMD X X

source Immediate, destination data register

Z)

Source Destination 3)

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PeDS PeIN IMMO X X

source Implied to be 1 (single bit shift) and destination taken from the following table

Destination

DOIR ADIR INOR AINC ADCR DISP INOX ABSH ABLO PeDS PeIN IMMO X X X X X X X

ROXL - rotate leFt with extend Sh I Fts the dest i nat i on operand I eFt. The number of bit s to shiFt is given by the source operand. The bits shiFted out of the leFtmost bit are put In the C and X bits. Bit 0 of the destination Is set to the previous contents of the X bit. Thus.' the shiFt Is circular iF the X bit is viewed as being to the leFt of the leFtmost bit of the destination. The operation size may be byte, word. or long word. The N bit is set iF the result is negative. cleared iF positive. The Z bit Is set IF the result Is zero. cleared IF not. The C and X bits are described above. The V bit Is always cleared. There are three Forms of the ROXL Instruction. 1)

both operands data registers

Source Destination 2)

DOIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PeIN IMMO X X

source Immediate. destination data register

Source Oest I nat-Ion 3)

They are:

OOIR ADIR INOR AINC ADCR DISP INOX ABSH ABLO PCOS PCIN I"MO X X

source Implied to be I (single bit shift) and destination taken from the following table

Destination

DDIR ADIR INOR AINC ADCR DISP INDX ABSH ABLO PeOS PeIN IMMO X X X X X X X

208

APPENDIX D

68000 INSTRUCTIONS

ROXR - rotate right with extend ShiFts the destination operand right. The number 01' bits to shiFt Is given by the source operand. The bits shiFted out 01' the rightmost bit are put In the C and X bits. The leFtmost bit 01' the destInation Is set to the prevIous contents 01' the X bit. Thus, the shiFt Is circular IF the X bit Is viewed as being to the right 01' the rightmost bIt 01' the destinatIon. The operation size may be byte. word, or long word. The N bIt Is set IF the result Is negative. cleared IF posItIve. The Z bit Is set IF the result Is zero. cleared IF not. The C and X bIts are descrIbed above. The V bit Is always cleared. There are three Forms 01' the ROXR fnstructton. 1)

They are:

both operands data registers DDIR ADIR INDR AINe ADCR DISP KNOX ABSH ABlO PCDS PCIN 11lIII0

Source DestinatIon 2)

X X

source ImmedIate. destInatIon date regIster DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABlO PCOS PCIN nlro

Source DestInatIon 3)

X X

source IIJf)I fed to be I (sIngle bit shlf't) and destination taken from the followIng table DDIR ADIR INDR AINe ADCR DISP INDX A8SH ABlO PCOS PCIN IttII)

Destination

X

RTE - return f'rom exception

X

X

X

X

X

X

(see also RTR)

Pops the top word oFf' the system stack I nto the SR and then pops the new top long word of'F the stack Into the PC. This operation Is unslzed. ConditIon codes are set according to the SR value popped oFf' the stack. There are no operands.

RTR - return and restore condition codes

(see also RTE)

Pops the top word 01'1' the system stack and puts Its low byte Into the condition code register (the low byte 01' the SR) and then pops the new top long word oFf' the stack Into the PC.

APPENDIX D

209

68000 INSTRUCTIONS

This operation Is unslzed. Condition codes are set according to the CCR value popped 01"1" the stack. There are no operands.

RTS - return From subroutine Pops the top long word 01"1" the stack Into the PC. This operation Is unslzed. Condition codes are not aFFected. There are no operands.

S8CD - subtract binary coded decimal Subtracts the source operand and the X bit From the destination operand and stores the result In the destination. Both source and destination are viewed as binary coded decimal numbers. The operation size must be byte. The Z bit Is cleared IF the result Is not zero and unchanged IF the resu 1t f s zero. The C and X b f ts are set IF the operat Ion produced a borrow and cleared If' not. The N and V bits are undeFined (no way to know what the result Is). Source and destination operands must be either both data reg I ster direct or both autodecrement. No mI x I ng 01" modes I s allowed. OOIR ADIR INDR AINC ADCR OISP INOX ABSH ABlO PCDS PCIN IMMO

Source Destination

X X

or DDIR AOIR INOR AINe ADCR OISP INDX ABSH ABlO PCDS PCIM IMHO

Source Destination

X X

See - set according to condition

Set destinatIon to alII's ($FF) IF the conditIon speciFIed by cc Is true and to all O's ($00) IF it is False.

The operation size must by byte. Condition codes are not aFFected.

210

APPENDIX D

68000 INSTRUCTIONS

Possible values for cc and their meanings are Meaning equal not equal greater than less than greater or equal less or equal high low or same plus minus carry clear carry set overflow clear overflow set true false

Code

EO NE

GT LT

GE LE HI LS PL

MI CC CS VC VS

T F

Test (l=true. O=false) Z

-Z

N*V*-Z + -N"-V*-Z N*-V + -N"V N*V + -N*-V Z + N"-V + -N*V

N

-C C

-v V 1

o

means complement

+ means or " means and There I s no source operand. The addres sing destination can be taken from the following table.

Destination

mode

for

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD X X X X X X X X

STOP - stop CPU

The source operand (which must be Immediate) Is moved Into the SR, the PC Is incremented to point to the next Instruction, and the CPU stops fetching Instructions. Execution resumes when an Interrupt or reset occurs or If the trace bit Is set., An Interrupt must have higher priority than the CPU in order to restart execution. This operation Is unslzed. The condition codes are set according to the value moved Into the SR. There is no destination operand. source operand must be Immediate.

The addressIng mode for the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IHHD Source

SUB -

X

subtract binary

(see also SUBA, SUBI. SUBQ, SUBX)

Subtracts the source operand from the destInatIon operand and stores the result In the destInation. The operatIon sIze may be byte, word, or long word.

APPENDIX D

68000 INSTRUCTIONS

211

The N bit Is set Ir the result is negative. cleared Ir positive. The Z bit Is set Ir the result Is zero, cleared Ir not. The V bit Is set Ir an overrlow Is generated, cleared Ir not. The C bit Is set Ir a borrow Is generated, cleared Ir not. The X bit Is set the same as the C bit. Address mode combinations rollowlng two tables:

can

be

taken

rrom

one

or

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PeIN 1""0 Source Destination

X A

Source Destination

x X X X X X X Data register direct allowed In the following form.)

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X X X X X X X X X X X X

SUBA - subtract address (see also SUB, SUBI. SUBQ. and SUBX) Subtracts the source operand rrom the destination operand and stores the result In the destination. The

The ope rat Ion size may be word or long word. destination register Is set regardless or the size.

ent I re

Condition codes are not arrected. Address table: Source Destination

mode

combinations

can

be

taken

rrom

the

rol lowing

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X X X X X X X X X X X X X

SUBI - subtract immediate (see also SUB, SUBA, SUBQ. and SUBX) Subtracts the source operand rrom the destination operand ar.d stores the result in the destination. The operation size may be byte, word. or long word. The N bit is set ir the result is negative. cleared ir positive. The Z bit is set if the result is zero, cleared if not. The V bit is set if an overflow Is generated, cleared Ir not. The C bit Is set If a borrow is generated, cleared if not. The X bit Is set the same as the C bit. Address table:

mode

combinations

can

be

taken

from

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN 1""0 Source Destination

X X

X

X

X

X

X

X

X

fol lowing

APPENDIX D

212

68000 INSTRUCTIONS

SUBQ - subtract quick (see also SUB, SUBA, SUBI, and SUBX)

Subtracts the source operand from the destination operand and stores the result in the destination. The operation size maybe byte. word, or long word. If the destination is an address register, the condition codes are not affected. Otherw I se, the bits are affected as fo I lows. The N bit Is set if the result Is negative, cleared If positive. The Z bit Is set if the result Is zero, cleared if not. The V bit is set iT an overflow is generated. cleared if not. The C bit is set If a borrow Is generated, cleared If not. The X bit is set the same as the C bit. The source operand must be an immediate number Trom 1 to 8. Address table.

Source Destination

mode

combinations

can

be

taken

from

the

following

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X

X

X

X

X

X

X

X

X

SUBX - subtract with extend (see also SUB, SUBA. SUBI. and SUBQ) Subtracts the source operand and the X condition code from the destination operand and stores the result In the destination. The operation size may be byte, word, or long word. The N bit Is set If the result Is negative. cleared IT posit ive. The Z bit is set if the resul t i s zero, unchanged iT not. (This Is to allow for a test for zero of a multiple-precision number.) The V bit Is set If an overflow Is generated, cleared If not. The C bit Is set If a carry Is generated, cleared If not. The X bit is set the same as the C bit. Source and destination operands must be either both data register direct or both autodecrement. No mI x I ng of modes Is allowed.

Source Destination Source Destination

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X

or DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD X X

213

68000 INSTRUCTIONS

APPENDIX D

SWAP - swap halves or register Swap halves or a data register. The upper word Is set to the previous contents or the lower word. and the lower word Is set to the previous contents or the upper word. The operation size must be word. The N bit is set ir bit 31 or the destination Is one. cleared ir it Is zero. The Z bit is set Ir the entire 32-blt result is zero, cleared Ir not. The V and C bits are always cleared. The X bit Is not arrected. There is no source operand. data register. Destination

The destination operand must be a

DDIR ADIR IHOR AINC AOCR DISP INDX ABSH ABLO PCDS PCIN 1""0 X

TAS - test and set Test the current value or the destination and set the Nand Z bits accordingly (see below). Arter the test. the MSB or the destination Is set. The operation IS Indivisible (using a readmod i ry-wr I te memory cyc Ie) to a I low ror the synchron I zat Ion or several processors. The operation size must be byte. The N bit Is set Ir the original destination value is negative. cleared Ir positive. The Z bit is set ir the original destination value Is zero. cleared Ir not. The V and C bits are always cleared. The X bit Is not arrected. There I s no source operand. The address I ng destination can be taken rrom the rollowlng table. Destination

mode

DOIR ADIR INOR AINC ADCR OISP INOX ABSH ABLO PCOS PCIN IMMO X X X X X X X X

TRAP - trap Trap through trap vector speciFied by source operand. This operation Is unslzed. Condition codes are not arrected.

ror

the

APPENDIX D

214

There Is no destination operand. valid trap vector number ($O-$F).

68000 INSTRUCTIONS

The source operand must be a

DDIR ADIR INOR AINC AOCR OISP INDX ABSH ABlO PCOS PeIM 1""0

Source

X

TRAPV - trap on overrlow Trap through vector at $IC Ir the V bit Is set. otherwise no operation Is perrormed. This operation Is unslzed. CondItIon codes are not arrected. There are no operands.

TST - test Compares the source operand with zero. The condition codes are set according to the result or the test (see below). The operatIon sIze may be byte. word. or long word. The N b f t f s set I r the operand f s negat I ve. c I eared I r positive. The Z bit Is set Ir the operand Is zero. cleared Ir not. The V and C bits are always cleared. The X bIt Is not arrected. There I s no dest I nat I on operand. Address I ng modes source operand can be taken rrom the followIng table.

ror the

DOIR ADIR INDR AINC AOCR DISP INDX ABSH ABLO PeDS PeIM l"ltD X X X X X X X X

Source

UNLK - unlink and deallocate

(see also LINK)

The stack pOinter is set to the destination address register. Then, the new long word on the top or the stack Is popped into the destination. The operation size must be long word. Condition codes are not affected. There is no source operand. The addressing destination must be address register direct.

mode

of

the

DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IltltD Destination

X

o

APPENDIX E 68000 MACHINE LANGUAGE

The following is a description of the machine language of the 68000. For further details, see the M68000 16/32-BIT MICROPROCESSOR Programmer's Reference Manual. For convenience, below is an alphabetical list of the instructions described in this appendix:

ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ANDI to CCR ANDI to SR ASL ASR Bee BCHG BCLR BRA BSET BSR BTST CHK CLR

CMP CMPA CMPI CMPM DBee DIVS DIVU EOR EORI EORI to CCR EORI to SR EXG EXT ILLEGAL JMP JSR LEA LINK LSL LSR MOVE

MOVE from SR MOVE to CCR MOVE to SR MOVE USP MOVEA MOVEM MOVEP MOVEQ MULS MULU NBCD NEG NEGX NOP NOT OR ORI ORI to CCR ORI to SR PEA RESET

ROL ROR ROXL ROXR RTE RTR RTS SBCD Sec STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPV TST UNLK

215

APPENDIX E

216

68000 MACHINE LANGUAGE

In the tables that follow, abbreviations will be used for addressing modes. These abbreviations are: DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD

-

data register direct address register direct address register Indirect autoincrement autodecrement address register Indirect with displacement address register Indirect with Index and displacement absolute short absolute long program counter relative with displacement program counter relative with index and displacement immediate

The addressing modes are coded in the machine language of most instructions as six-bit numbers. Three bits are referred to as the mode field, and the other three are called the register field. The codes for the addressing modes are the same for most instructions. The usual codes are:

Addressing mode DDIR ADIR INDR AINC ADCR DISP INDX ABSH ABLO PCDS PCIN IMMD

Mode Tleld 000

RegIster Tleld regIster number regIster number regIster number regIster number regIster number register number regIster number 000 001 010 011 100

DOl

010 Oil

100 101 110 1 11 11 1 III III III

For DISP and INDX, the "register number" listed above is the number of the address register that has the displacement or index added to it. For INDX and PCIN, an extra word is needed for index and displacement information. The format of this word is:

15 14 13 12 11 10 D/ A Reg.Num. W/L 0

9

8

o o

7

6

543 2 Displacement

o

APPENDIX E

68000 MACHINE LANGUAGE

217

where D/A is 0 for a data register, 1 for an address register. Reg. Num. is the number of the index register. W/L is 0 for a word size index and 1 for long word size index. And the low byte is the displacement as a signed 2's-complement number. An absolute short or absolute long address is stored in the word or words following the instruction. An immediate value is stored in the word or words following the instruction. Byte size immediate data is stored in the low byte of the word with the high byte set to zero ($00). If extra words are needed for both source and destination, the extra words for the source precede the extra words for the destination. Abbreviations to be used in describing the machine language are:

D/A

data register If 0, address register If I a-bit displacement destination mode field destination register field destination register number (If mode must be register direct) source mode field source register field source regIster number (If mode must be register dIrect) standard two bIt size fIeld, OO=byte, 0l a word, 10=long o for word size operatIon, I for long word

dlspB dst.md.fld dst.rg.fld dst.rg.num src.md.fld src.rg.fld src.rg.num std.slz !rilL

ABeD - add binary coded decimal 15 1

14 I

12

13

o

ADD - add binary

o

11 10 9 dst.rg.num

7

8

o

1

14 1

o

5

o

4

320

o D/A

src.rg.num

(see also ADDA, ADDI, ADDQ, and ADDX)

For data register direct source: are data regIster dIrect] 15 1

6

13

o

12 1

11

10

9

src.rg.num

8 1

[do not use if both operands

76543 std.siz dst.md.fld

2 0 dst.rg.fld

For data register direct destInatIon: [use If both operands are data register direct] 15 1

14 1

13

o

12 1

11

10

9

dst.rg.num

8

76543

o std.slz src.md.fld

210

src.rg.fld

APPENDIX E

218

68000 MACHINE LANGUAGE

ADDA - add address (see also ADD, ADD!. ADDQ, and ADDX) 15

14

1

1

13

o

12 1

11 10 9 dst.rg.num

8

W/L

7 1

6 1

5 4 3 src.md.fld

2 0 src.rg.fld

ADDI - add immediate (see also ADD, ADDA. ADDQ, and ADDX) 15 14 13 12 11 00000

10 1

9 I

8

o

7

6

5

4

3

std.slz dst.md.fld

2

1

0

dst.rg.fld

ADDQ - add quick (see also ADD. ADDA. ADDl, and ADDX) 15

o

14 1

13

o

12 1

11 10 9 qulck.num.

8

76543

o std.slz dst.md.fld

2 I 0 dst.rg.fld

A val ue

Where quick.num. Is the source operand. Indicates that the number 8 Is to be added.

of

zero

ADDX - add with extend (see also ADD, ADDA. ADD!. and ADDQ)

AND -

IS

14

I

I

13

o

12 I

II 10 9 dst.rg.num

8 I

7

6

std.slz

5

o

4

o

320 D/A src.rg.num

logical and (see also ANDI) For data register direct source: are data register direct]

IS

14

I

I

13

o

12

II

9

8

o src.rg.num

I

10

[do not use If both operands

7 6 4 3 5 std.slz dst.md.fld

For data register direct destination: are data register direct]

AND! -

IS

14

I

I

13

o

12

II

10

9

o dst.rg.num

8

o

[use

2

0

dst.rg.fld

if both operands

7 6 5 4 3 std.slz src.md.fld

2 0 src.rg.fld

logical and Immediate (see also AND)

IS

o

14

o

13

o

12

o

II

o

10

o

9 1

8

o

4 7 6 5 3 std.siz dst.md.fld

2 0 dst.rg.fld

The Immediate source operand fol lows the word described above.

APPENDIX E

68000 MACHINE LANGUAGE

219

ANDI to CCR - add immediate to condition code register

15 14 13 000

12 11 10 000

9 1

8

o

7

o

6

5

o

1

4 1

3 1

2 1

1

o

o

o

The immediate source operand Follows the word described above.

ANDI to SR - and immediate to status register

15 14 13 000

12 11 10 000

9 1

8

o

7

o

6

5 1

1

4

3

2

1

1

1

1

a

a o

The immediate source operand Follows the word described above.

ASL -

arithmetic shiFt leFt IF both operands are data registers:

15 1

15 1

14 1

13 1

12 0

1 1 10 9 src.rg.num

8

IF source is immediate: 14 13 12 11 10 9 I 1 0 shFt.count

8

1

1

6 7 std.siz

5 1

4 0

0 3 2 1 0 " dst. rg. num

7 6 std.siz

5 0

4 0

3 0

0 2 dst.rg.num

4 5 3 dst.md.num

2 0 dst.rg.num

Where shFt.count is the source operand. IF source is impl fed 1 :

15 1

14 1

13 1

12 0

11 0

10 0

9

8

0

1

7 1

6

1

ASR - arithmetic shiFt right IF both operands are data registers:

15 1 15 1

14 1

13 1

12 0

1 1 10 9 src.rg.num

IF source is immediate: 14 13 12 11 10 9 1 1 0 shFt.count

8

0 8

0

7 6 std.siz

5 1

4 0

3 0

0 2 dst.rg.num

7 6 std.siz

5 0

4 0

3 0

2 0 dst.rg.num

5 4 3 dst.md.num

0 2 dst.rg.num

Where shFt.count is the source operand. IF source is impl ied 1 :

15 1

14 1

13 1

12 0

11 0

10 0

9

8

0

0

7 1

6

1

220

APPENDIX E

68000 MACHINE LANGUAGE

Bee - branch conditionally 15 0

14 1

Where rollows:

13 1

12 0

9 a 1 1 10 condition type

condition

type

ce

Is

a

7

rour

6

5

bit

4 3 dlspa code

2

spec:. I ry i ng

0

ee as

rour bit code 0111 0110 1110 1101 1100 1111 0010 0011 1010 1011 0100 0101 1000 1001

EO NE GT LT GE LE HI LS PL MI CC CS VC VS

lr the a-bit displacement Is zero, the next word holds a 16-bit displacement. The displacement is the value to add to the program counter to get to the target or the branch. Don' t rorget that the PC Is always 2 more than the starting address or the Instruction being processed.

BCHG - test a bit and change For data register direct source: 15 0

14 0

13 0

12 0

1 1 10 9 src.rg.num

a 1

7 0

6 1

5 4 3 dst.md.rld

0 2 1 dst.rg.rld

a 0

7 0

6 1

4 5 3 dst.md.rld

0 2 1 dst.rg.rld

For Immediate source: 15 0

14 0

13 0

12 0

11 1

10 0

9 0

The Immediate source operand rollows the word described above.

BCLR - test a bit and clear For data register direct source: 15

o

14

o

13

o

12

o

11 10 9 src.rg.num

a

7

1

1

6

5

432 1 0 dst.rg.rld

o dst.md.rld

221

68000 MACHINE LANGUAGE

APPENDIX E

For Immediate source: 15

o

14

o

13

o

12

o

11 1

10

o

7 1

8

9

o

o

6

5

4

3

210

o dst.md.fld

dst.rg.fld

The Immediate source operand follows the word described above.

BRA - branch always 15

o

14 1

13 1

12 0

11 0

10 0

8

9

o

o

7

6

5

4 3 dlsp8

2

o

If the 8-blt displacement Is zero. the next word holds a 16-bit displacement. The displacement Is the value to add to the program counter to get to the target of the branch. Don' t forget that the PC I s always 2 more than the starting address of the instruction being processed.

IBSET - test a bit and set For data register direct source: 15 0

14 0

13 0

12 0

9 1 1 10 src.rg.num

8 1

7 1

6 1

4 3 5 dst.md.fld

0 2 1 dst.rg.fld

8 0

7 1

6

4 3 5 dst.md.fld

0 2 1 dst.rg.fld

For Immediate source: 15 0

14 0

13 0

12 0

1I I

10 0

9 0

1

The Immediate source operand follows the word described above.

IBSR - branch to subroutine 15

o

14 I

13 1

12 0

11 0

10 0

9

o

8 1

7

6

5

4 3 dlsp8

If the 8-bit displacement is zero. the next word displacement.

2 ~olds

o a J6-bit

The displacement Is the value to add to the program counter to get to the target of the branch. Don't forget that the PC is always 2 more than the starting address of the Instruction being processed.

APPENDIX E

222

68000 MACHINE LANGUAGE

BTST - bit test For data register direct source: 14

IS

a

13

a

12

II

o

o

10

9

src.rg.num

6

o

o

5 432 I 0 dst.md.fld dst.rg.fld

7

6

5 432 I a dst.md.fld dst.rg.fld

7

8 I

For Immediate source: 14

IS

o

13

a

a

12

II

10

0

I

0

9

o

8

a

o

o

The immediate source operand follows the word described above.

CHK - check data register against bounds 14

IS

a

13

1

a

14

13

12

11

10

9

o dst.rg.num

7

8 1

1

6

a

543 src.md.flg

2 0 src.rg.fld

ClR - clear 15

a

14

o

1

II

a

a

13

12

I

I

14

a

a

14

a

9 1

8

o

7 6 5 432 0 std.slz dst.md.fld dst.rg.fld

13 I

12 I

13

a

12

a

8

o

7 654 3 std.slz src.md.fld

2 0 src.rg.fld

{see also CMP. CMPI. CMPM} 11 10 9 8 dst.reg.num W/L

7

6

1

1

4 3 5 src.md.fld

2 0 src.rg.fld

{see also CMP. CMPA. CMPM}

C"PI - compare Immediate 15

0

II 10 9 dst.rg.num

C"PA - compare address IS 1

10

{see also CMPA. CMPI. CMPM}

C"P - compare 15

12

a

1

11

10

1

1

9

o

8

o

7 6 5 432 1 0 std.siz dst.md.fld dst.rg.fld

The immediate source operand follows the word described above.

68000 MACHINE LANGUAGE

APPENDIX E

CHPK - compare memory 15 1

14

o

13 1

12 1

223

{see also CMP. CMPA. CMPI} 11 10 9 dst.rg.num

8

7

1

6

4

0

o

3 1

2 0 src.rg.num

5

4

3

2 0 src.rg.num

5

std.slz

OSee - decrement and branch conditionally 15

o

14

1

Where rollows:

13

o

12 1

11 10 9 8 condition type

cond i t Ion

type

ee

a

1

rour

6 1

o

bit

o

code

1

spec I ry I ng

ee as

rour bit code 0111 0110 1110 1101 1100 1111 0010 0011 1010 1011 0100 0101 1000 1001 0001 0000

EQ NE GT LT GE LE HI LS PL HI CC CS VC VS F T

A 16-blt Instruction.

is

7

displacement

is

stored

in

the

word

rollowing

the

The displacement is the value to add to the program counter to get to the target or the branch. Don' t rorget ·that the PC is always 2 more than the starting address or the Instruction being processed.

DIVS - divide signed 15

1

14

o

13

o

(see also DIVU)

12

DIVU - divide unsigned 15 1

14

o

13

o

11

10

9

o dst.rg.num

12

8 1

7 1

6 1

543 src.md.rld

2 0 src.rd.rld

7

6 1

543 src.md.rld

210 src.rg.rld

(see also DIVS) 11

10

9

o dst.rg.num

8

o

1

APPENDIX E

224

EOR - logical EXCLUSIVE OR 15 1

14

o

13 1

12 1

(see also EORI)

9

8

src.rg.num

1

11

10

EORI - logical EXCLUSIVE OR Immediate 15 14 13 000

12 0

11 1

68000 MACHINE LANGUAGE

10 0

9 1

8

o

765

4

3

std.siz dst.md.fld

2

1

0

dst.rg.fld

(see also EOR) 7

6

5

432

std.siz dst.md.fld

1

0

dst.rg.fld

The Immediate source operand follows the word described above.

EORI to

CCR 15 0

14 0

logical EXCLUSIVE OR Immediate to condition code register 13 0

12 0

11 1

10 0

9 1

8 0

7 0

6 0

5 1

4

I

3 1

2 1

1 0

0 0

The Immediate source operand follows the word described above.

EORI to

SR 15 0

14 0

logical EXCLUSIVE OR Immediate to status register 13 0

12 0

11 1

10 0

9 1

8 0

7 0

6 1

5 1

4 1

The Immediate source operand follows the word

3 1

2 1

descrl~ed

1 0

0 0

above.

EXG - exchange two registers Two data registers: 15 1

14 1

13 0

12 0

1 1 10 9 src.rg.num

8 1

2

0

7 0

6 1

5 0

4 0

3 0

dst.rg.num

7 0

6 1

5 0

4 0

3 1

dst.rg.num

5 0

4 0

3 1

add.rg.num

Two address registers: 15 1

14 1

13 0

12 0

9

8

src.rg.num

1

11

10

2

0

One data register and one address register: 15 1

14 1

13 0

12 0

10 9 11 dat.rg.num

8 1

7 1

6 0

Where dat.rg.num Is the number of the data add.rg.num Is the number of the address register

2

register

0

and

225

68000 MACHINE LANGUAGE

APPENDIX E

EXT - sign bit extend 15

14

o

13

12

o

o

I1

10

9

8

o

o

o

10 0

9 I

8

10 1

9 1

8

7

6

5

4

3

W/L

o

o

o dst.rg.num

7 1

6 1

5 1

4 1

3

7 1

6

5

4

3

2

0

ILLEGAL - Illegal instruction 15

o

J"P - jump 15

o

14 I

13 12 11 001

o

1

2 1

o

1

o o

2

I

0

(see also BRA) 14 I

13 0

12 0

11 1

JSR - jump to subroutine 15

o

14 1

13 12 11 001

o

I

dst.md.fld

dst.rg.fld

(see also BSR) 9 1

8

o

7 I

6

I

10

9

8

7

6

543

1

1

1

src.md.fld

10

o

5

4

3

dst.md.fld

2

I

0

dst.rg.fld

lEA - load effective address 15

o

14 1

13

o

12

11

o dst.rg.num

lHMK - link and allocate 15

o

14 1

13

o

12

o

11 1

2

I

0

src.rg.fld

(see also UNLK) 10 1

9 1

8

o

7

o

6

1

5

o

4 1

3

2

0

o src.rg.num

The immediate data occupying the destination field assembly language instruction Is put in the following word.

in

lSL - logical shift left If both operands are data registers: 15 I

14 1

13 I

12

11

10

9

o src.rg.num

876 1 std.siz

5 1

4

o

3 I

2 0 dst.rg.num

the

226

APPENDIX E

68000 MACHINE LANGUAGE

IF source Is Immediate: 15

13 1

14 1

I

12 0

11

9

10

7

B 1

shFt.count

6

std.slz

5 0

4 0

3 1

5

4

3

2

0

dst.rg.num

Where shFt.count Is the source operand. IF source Is Implied 1 : 15

14 1

I

LSR -

13 1

12 0

11 0

10 0

B 1

9 1

7

6

1

1

2

dst.md.num

0

dst.rg.num

logical shiFt right IF both operands are data registers: 9

B

src.rg.num

0

IF source Is Immediate: 14 13 12 I 1 10 9 1 1 0 shFt.count

B

14 1

15 1

15 1

12

13 1

11

0

10

7

6

std.slz 7

6

std.slz

0

2

0

5 1

4 0

3 1

dst.rg.num

5

4

0

0

3 1

dst.rg.num

5

4

3

2

0

Where shFt.count Is the source operand. IF source Is Implied 1 : 15 1

14

13 1

1

12

11

o

o

ttOVE - move data From Instructions) 15

o

14

13

12

o .size.

10

o

source

11

10

9

dst.rg.Fld

7

6

1

1

9 1

B

to

dest I nat ion

o

B

7

6

dst.md.Fld

2

5

(see 4

other 2

3

src.md.Fld

0

dst.rg.num

dst.md.num

MOVE 0

src.rg.Fld

Where .slze. Is 01 For byte operation. 11 For word. and 10 For long. Not I ce that the reg I ster and mode Fie 1ds For the dest i nat Ion operand are not In their usual order.

ttOVE

~rom

15

o

SR - move data from status register to destination MOVE Instructions) 14 1

13 0

12 11 10 000

9

o

B

o

7

6

1

1

5

4

3

dst.md.fld

(see other 2

ttOVE t:o CCR - move data From source to cond I t I on code reg I ster other MOVE Instructions) 15

o

14 1

13

o

12

o

11

o

10 1

9

o

B

o

7 1

6 1

5

4

3

src.md.Fld

0

dst.rg.fld

2

( see 0

src.rg.fld

APPENDIX E

227

68000 MACHINE LANGUAGE

noVE to SR - move data from source to status register

(see other MOVE

Instructions) IS

o

14 I

13

12

o

o

II

o

10 I

9 I

noVE UlSP - move user stack pointer

8

o

7 I

6 I

4 5 3 src.md.fld

2 0 src.rg.fld

(see other MOVE Instructions)

Move to U5P: IS 0

14 I

13 0

12 0

1I I

10 I

9 I

8 0

7

0

6 I

5 I

4 0

3 0

0 2 src.rg.num

12 0

II I

10 I

9 I

8 0

7 0

6 I

5 I

4 0

3 I

0 2 dst.rg.num

5 4 3 src.md.fld

2 0 src.rg.fld

Move from U5P: IS 0

~VEA

14 I

13 0

- move address IS

o

14

o

13 I

(see other MOVE Instructions)

12 II 10 9 L/W dst.rg.num

8

o

7

o

6 I

Where L/W Is 0 for long word operations. I for wor.d operations.

MOVE" - move multiple registers For moves to memory: IS 0

14 I

13 0

12 0

II I

10 0

9 0

8 0

7 I

6 5 4 3 W/L src.md.fld

2 0 src.rg.fld

10 I

9 0

8 0

7 I

6 5 4 3 W/L dst.md.fld

I 2 0 dst.rg.f"ld

For moves from memory: IS 0

14 I

13 0

12 0

II I

The register list Is coded as a word whose bits each stand for In this word, which f"ollows the word described above. a I Indicates the register Is to be moved and a 0 indicates the register is not to be moved. The registers are moved in order based on the bit positions. The register correspond i ng to I east sign I f" I cant bit that I s l i s the f" i rst moved; the one corresponding to the most signlf"icant bit that Is I is the last moved.

one of" the 16 possible registers.

For a II

but autodecrement address I ng,

the reg i ster

list word

Is: 15 A7

14 A6

13 AS

12 A4

II A3

10 A2

9 AI

8 AD

7 07

6 06

5 05

4 04

3 03

2 02

I 01

0 DO

68000 MACHINE LANGUAGE

APPENDIX E

228

For autodecrement, the register list word Is: 15

14 Dl

DO

13 02

12 03

11 04

10 05

9 06

a 07

7 AD

6 Al

5 A2

4 A3

3 A4

2 AS

1 A6

0 A7

The difference I n these two formats I nsures that reg I sters stored and retrieved using autodecrement and autolncrement are processed correctly.

- move peripheral data

~VEP

For move from memory: 15 0

14 0

13 0

12 0

1 1 10 9 dst.rg.num

a 1

7 0

6 W/L

5 0

4 0

3 1

2 0 src.rg.num

a 1

7 1

6 W/L

5 0

4 0

3 1

2 0 dst.rg.num

For move to memory: 14 0

15 0

13 0

12 0

1 1 10 9 src.rg.num

displacement The for the address register displacement mode follows the word described above.

~VEQ

indirect

with

- move quick 15

14

13

12

o

1

1

1

11 10 9 dst.rg.num

a o

7

6

5

4 quick

3 2 data

o

Where quick data Is an a-bit field holding the source operand.

HULS - multiply signed

~ULU

15

14

I

1

13

o

12

o

(see also MULU) 11 10 9 dst.rg.num

- multiply unsigned 15 1

14 1

13

o

12

o

8 1

6 1

543 src.md.fld

2 I 0 src.rg.fld

1

6 1

543 src.md.fld

210 src.rg.fld

7

6

7 1

(see also MULS)

11 10 9 dst.rg.num

a o

7

NBCO - negate binary coded decimal 15

o

14 13 12 100

11 1

10 0

9

o

a o

o

5

4

3

o dst.md.fld

2 I 0 dst.rg.fld

APPENDIX E

NEG -

68000 MACHINE LANGUAGE

229

negate

IS

o

14 I

13 12 II 000

10

9

I

o

876 5 432 I 0 o std.slz dst.md.fld dst.rg.fld

10 0

9

876 5 4 3 o std.siz dst.md.fld

10

9 I

8

o

o

10

9

8

7

I

I

NEGX - negate with extend

IS

o

14 I

13 0

12 0

II

II I

0

o

2 I 0 dst.rg.fld

HOP - no operation

IS

o

14

13

12

I

0

0

I

7

6

5 I

4 I

3

I

6

5

4

3

o

2

o

I

o

o I

NoT - logical not (complement) IS

o

OR -

14 I

13 12 II 000

logical or

o std.siz dst.md.fld

(see also DRI)

For data register direct source: are data reister direct]

IS I

14

o

2 I 0 dst.rg.fld

13

o

12

o

II 10 9 src.rg.num

8 I

[do not use If both operands

7654321 0 std.slz dst.md.fld dst.rg.fld

For data register direct destination: [use If both operands are data register direct]

IS I

ORI -

14

o

13

o

12

o

II 10 9 dst.rg.num

logical or Immediate

IS

14 13 000

8

o

7 6 4 5 3 std.slz src.md.fld

2

0

src.rg.fld

(see also DR)

12 II 10 000

9

o

8

7

6

5

4

3

o std.slz dst.md.fld

2 1 0 dst.rg.fld

The immediate source operand follows the word described above.

230

68000 MACHINE LANGUAGE

APPENDIX E

ORI to CCR - logical or immediate to condition code register 15 14 13 000

12 II 10 000

9

o

8

o

7

o

6

5 I

o

4 1

3 I

2 1

I

o

o o

The immediate source operand follows the word described above.

ORI

to SR - logical or Immediate to status register 15 0

14 0

13 0

12 0

I I 0

10 0

9

8

7

6

0

0

0

I

5 1

4 I

3 I

2 1

I 0

0 0

The immediate source operand follows the word described above.

PEA -

push effective address 14 I

15 0

13 0

12 0

11 1

10 0

9

8

7

6

0

0

0

1

9 1

B

7

6 1

5

4

3

src.md.fld

2

0

src.rg.fld

RESET - reset external devices 15

o

ROL -

14

13

12

11

10

1

0

0

1

I

o

o

5 1

4

3

1

d

2

o

I

o

o o

rotate left If both operands are data registers: 15 I

14 I

13 1

12 0

9

8

src.rg.num

1

11

10

7

5

6

std.siz

4 1

3 I

dst.rg.num

0

4 1

3 1

dst.rg.num

5

4

3

I

2

0

If source Is Immediate: 15 I

14 1

13 I

12 0

11

10

9

shft.count

B I

7

5

6

std.siz

2

0

Where shf"t.count Is the source operand. If" source is impl ied I : 15 1

14 1

13 1

12 0

11

0

10 I

9

B

1

1

7 1

6 1

dst.md.num

2

0

dst.rg.num

ROR - rotate right If both operands are data registers: 15 I

14 1

13 1

12

o

11

10

9

src.rg.num

8

o

7

6

std.siz

5

4

1

1

3 1

2

0

dst.rg.num

68000 MACHINE LANGUAGE

APPENDIX E

231

l'f source Is Immediate: 15 1

14 1

13 1

12 0

9

8

sh'ft.count

0

11

10

7

6

std.slz

5 0

4 1

3 1

5

4

3

0

2

dst.rg.num

Where shft.count Is the source operand. If source Is Implied 1 : 15 1

14 1

13 1

12 0

11 0

10 1

9

8

7

6

1

0

1

1

dst.md.num

2

0

dst.rg.num

ROXL - rotate left with extend

If both operands are data registers: 15 1

14 1

13 1

12 0

11

10

9

8

src.rg.num

1

7

6

std.siz

5 1

4 1

3 0

_, dst.rg.num

5 0

4 1

3 0

dst.rg.num

5

4

3

2

0

If source Is Immediate: 15 1

14 1

13 1

12 0

11

10

9

8

shft.count

1

7

6

std.slz

2

0

Where shft.count Is the source operand. If source Is Impl led 1 : 14 1

15 1

13 1

12 0

11 0

10 1

9

8

7

6

0

1

1

1

dst.md.num

2

0

dst.rg.num

ROXR - rotate right with extend

l'f both operands are data registers: 15 1

14 1

13 1

12 0

9

8

src.rg.num

0

11

10

7

6

std.siz

5 1

4 1

3 0

dst.rg.num

5 0

4 1

3 0

dst.rg.num

5

4

3

2

0

I'f source Is Immediate: 15 1

14 1

13 1

12 0

9

8

shft.count

0

11

10

7

6

std.siz

2

-I

0

Where shft.count Is the source operand. If source Is Implied 1 : 15 1

14 1

13 1

12 0

11 0

10 1

RTE - return from exception 15

o

14

1

13 12 11 001

9

8

7

6

0

0

1

1

dst.md.num

2

0

dst.rg . .num

(see also RTR) 10

1

9 1

8

o

7

o

6 1

5 1

4

1

3

o

2

o

o 1

232

68000 MACHINE LANGUAGE

APPENDIX E

RTR - return and restore condition codes 15 0

14 1

13 0

12 0

11 1

10 1

(see also RTE)

9

8

7

6

1

0

0

1

9

8

7

6

1

0

0

1

5 1

4 1

3 0

2 1

5 1

4 1

3 0

2 1

0 1

RTS - return f'rom subroutine 15 0

14 1

13 0

12 0

11 1

10 1

0 1

1 0

SeeD - subtract binary coded decimal 15 I

14 0

13 0

12 0

9

8

7

6

dst.rg.num

1

0

0

11

10

5 0

4 0

3 D/A

2

0

src.rg.num

See - set according to condition 15 0

14 1

Where f'ollows:

13 0

12 1

8

7

6

condition type

1

1

11

10

9

condition type

Is

a

f'our

cc

f'our bit code

EQ NE GT LT GE LE

0111 0110 1110 1101 1100 1111 0010 0011 1010 1011 0100 0101 1000 1001 0000 0001

HI

LS PL MI

CC CS VC VS T F

5

4

3

dst.md.f'ld

bit

code

2

I

0

dst.rg.f'ld

speclf'ylng

cc

as

STOP - stop CPU 15 0

14 I

13 0

12 0

11 I

10 1

9

8

7

6

5

I

0

0

1

1

4 1

3 0

2 0

0 0

The Immediate source operand f'ollows the word described above.

233

68000 MACHINE LANGUAGE

APPENDIX E

SUB - subtract binary

(see also SUBA. SUBI. SUBQ. SUBX)

For data register direct source: are data register direct] 15

14

o

1

13

o

12 1

11

10

8 1

9

src.rg.num

[do not use iF both operands

76543 std.slz dst.md.Fld

210

dst.rg.Fld

For data register direct destination: [use IF both operands are data register direct] 15 1

14

o

13

o

12 1

11

10

8

9

o

dst.rg.num

2 0 src.rg.Fld

7 6 5 4 3 std.slz src.md.Fld

SUBA - subtract address (see also SUB. SUBI. SUBQ. and SUBX) 15 1

14

o

13

o

12

1

11

10

9

dst.rg.num

8

7

W/L

1

6 1

543 src.md.Fld

2 0 src.rg.fld

SUBI - subtract Immediate (see also SUB. SUBA. SUBQ. and SUBX) 15

14

13

12

o

o

o

o

11

o

10 1

9

o

8

o

76543 std.slz dst.md.Fld

210

dst.rg.Fld

The Immediate source operand Follows the word desclbed above.

SUBQ - subtract quick (see also SUB. SUBA. SUB!. and SUBX) 15

o

14 1

13

o

12 1

9

8

quick.data

1

11

10

5 4 3 7 6 std.siz dst.md.fld

Where qulck.data specifies the source operand. (OOO) Indicates that 8 Is to be subtracted.

2 0 dst.rg.fld A value of zero

SUBX - subtract with extend (see also SUB. SUBA, SUBI, and SUBQ) 15

14

13

12

1

0

0

1

11

10

9

dst.rg.num

8 1

7 6 std.slz

5 0

4

o

3

2

0

D/A src.rg.num

234

68000 MACHINE LANGUAGE

APPENDIX E

SWAP - swap halves of register

15

o

14 1

13

o

12

o

11

10

9

1

o

o

8

7

6

o

o

8

7

6

1

1

7

6

1

5

4

3

5

4

3

o

o

2

0

o dst.rg.num

TAS - test and set

15

o

14 1

13 0

12 0

11 1

10 0

9 1

o

14

13

12

11

10 1

9 1

8

1

dst.md.fld

2

1

0

dst.rg.fld

TRAP - trap

15

o

1

o

o

o

o

1

5

o

4

3

2

o vector number

o

Where vector number 15 the Immediate operand (O-$F).

TRAPV - trap on overflow

15

o

14 1

13 0

12 0

11 1

10 1

9 1

8

14

13

12

11

10

9

8

o

7

o

6 1

5 1

4 1

3

o

2 1

o

o

TST - test

15

o

1

o

o

o

1

UNLK - unlink and deallocate

15

o

14 1

13

o

12

o

1

o

4 7 6 5 3 std.slz src.md.fld

2 0 src.rg.fld

(see also LINK)

11

10

9

1

1

1

8

o

7

o

6

1

5

o

4 1

3 1

2 0 dst. rg. n'Jm

o

APPENDIX F NOTES ON PROGRAMMING STYLE A good assembly language program must be correct, well structured, and properly documented. It is taken for granted that a fmal version of a program must provide correct answers. The remaining criteria can be classified as "programming style". Good programming style includes careful annotation and commentary, clear organization, and lucid coding. In writing your program, bear in mind that the reader knows relatively little about the problem you are trying to solve, and next to nothing about your programming habits. Here are some specific pieces of advice:

1. Programs should be modular. Well-defined portions of an algorithm should be coded as subroutines. 2. Each program or subroutine should have a concise introductory comment describing the purpose of the program or subroutine, the algorithm used, the significance of important internal variables, and thP. meaning and formats of required inputs and generated outputs. For subroutines, describe the meaning and format of arguments; also list the registers used by the subroutine. 3. Standardize your jnstruction format. For example: Label field - column 1 Operation field - column 9 Operand field - column 17 Comment field - column 33 If the operand field extends beyond column 32, simply leave a space and start the comment. 4. A comment should appear with almost every instruction. Such a "marginal" comment should not be simply a literal translation of the instruction, but an explanation of its effect on the program. For example, a comment for BRA LOOP should not be "branch to LOOP", but "return for processing next character". 5. If marginal comments do not make the operations clear enough, do not hesitate to insert full-line commentary between instructions.

235

APPENDIX F

236

NOTES ON PROGRAMMING STYLE

6. A marginal comment extending over several lines should be successively indented. For example: CMP BLT

#'O',DO NONDIG

;IF DO < '0' PROCESS NON-DIGIT CASE

7. Separate distinct parts of the code with blank lines (or lines containing only ; in column 1). 8. Avoid "tricky" or "clever" instruction sequences. If you must include such sequences, provide them with full explanations. 9. Pay attention to all possibilities. For example, in writing a division routine, include a check for zero divisor. If a divisor is found to be zero, some specific action must be taken (an error message is to be printed out, a certain condition code is to be set, etc.). 10. Avoid writing self-modifying programs (where instructions or assembler-inserted constants are altered during execution). Such "nonreentrant" programs are extremely difficult to debug. 11. Subroutines that stand a good chance of being useful in other programs should be as "transparent" as possible to the calling program. All registers used by such subroutines should be saved on entry (a convenient place is the system stack) and restored before exit. 12. Storage areas should be grouped together in a single place in the program, not mixed with executable code. 13. To the extent possible, symbols should be mnemonic. For example, points in the program should be named LOOP, NEXTCH ("next character"), EXIT, etc., rather than Xl, X2, X3. Similarly, storage locations should be named TEMP, TABLE, CONST, etc., rather than P, Q, R. 14. For better readability and easier maintainability, predefine symbols for absolute addresses and constants used in your program: for example, BELL == 7, MASK = $F, TRMDATA =$10042. Write SP for A7. 15. Avoid wasteful instructions if efficient ones are just as lucid. For example, write CLR DO MOVEQ #1,DO

not not

MOVE #O,DO MOVE #I,DO

16. Do not insert a test instruction where it is not needed. For example, in SUB TST BEQ

#A,B B NEXT

the TST instruction is redundant. 17. Avoid using instructions as data. For example, do not use

APPENDIX F

NOTES ON PROGRAMMING STYLE

MOVE

237

LOOP,DO

if LOOP is a label on an instruction. 18. To reserve a word of storage, write DS.W 1, not DC.W O. (Both directives reserve a word of storage, but the latter directive indicates that the initial contents of the word is significant.)

APPENDIX G ANSWERS TO

SELECTED EXERCISES Chapter 1 1.1

1.2.

1.3.

1.4.

1.5. 1.6. 1.7.

(a) 100100100001 2,921 16 (b) 10011100010000 2,2710 16 (C) 11111111111111 2, 3 FFF 16 (a) 127,7F 16 (b) 129,81 16 (c) 42798, A72E 16 (a) 2303,100011111111 2 (b) 2472,100110101000 2 (c) 51966, 11001010111111102 (a) 11101002 (b) 10001011 2 (a) 1169 (b) 47B 1111100010011 2 Add 1 to 111 ... 12

Chapter 2 2.1.

(a) (b) 2.2. 2 15 2.3. (a) (b)

Byte DFFF DFFE , Word Byte 7FFFF , Word 7FFFE = 32K = 32768 Word6DB6,highbyte6D,lowbyteB6 Word 97D5, high byte 97, low byte D5

Chapter 3 3.1.

238

(a) FFFF (b) FC18

APPENDIX G

3.2. 3.3.

3.4.

3.5. 3.6. 3.7.

ANSWERS TO SELECTED EXERCISES

239

(C) FOOO (d) 85B4 (a) 04C4 (b) 5F (a) 01 EF (b) E3FD (c) FBC8 1000: 7B1F 1002: E536 1004: 5A9C 1006: OAOD 17 IS PRIME! (a) BEOO 0000 (b) 41A4 0000 (a) 31.875 (b) -0.03125

Chapter 4 4.1.

In the condition code values, -- will mean "unchanged". Actual values of affected codes are given even though not required by question. (A2) unchanged XNZVC - - - - (a) (A3) =00007002 (b) (D1) = 6F4A0021 (A2) unchanged XNZVC -0000 (c) (D2) = 12348000 XNZVC -1000 (d) (D2) = 00008000 XNZVC -0000 (e) (D1) = 6F4A2300 (A2) =00007003 XNZVC -0100 (f) (D2) = 12340152 (A2) = 00007000 XNZVC -0000

4.2.

In the condition code values, - will mean "unchanged". Actual values of affected codes are given even though not rcquired by qucstion. XNZVC 01000 (a) (D2) = A4BlEF3C (b) (D2) = A4B1983C XNZVC 10001 (c) (D2) = 98C4A4B1 XNZVC -1000 (d) (D2) = A4B19981 (AI) unchanged XNZVC 11001 (e) (D2) = FFF3FACE (A2) = 0000600A XNZVC -1000 (f) (Dl) = 00000078 XNZVC -0000 DA44 DClD 67FA DOA8 0014 DE7C 0032

4.3.

APPENDIX G

240

4.4.

6DOO 04FO ADD.B ADD.B BEQ.L ADD BGT.S ADD.L

ANSWERS TO SELECTED EXERCISES

#5,D5 D5,(Al) $6000 (A7)+,D4 $705A D3,D7

Chapter 5 5.3. The program converts an ASCII string of hex digits into binary. (AO) = $6045, (D!) = $D, (D2) = $2BC7

Chapter 6 6.1. 6.2.

6.3.

(DO) +- (Dl) * (D2) SP = 00006FEA Contents of system stack: 006FEA 00 00 70 28 00 05 00 00 70 28 00 06 00 00 70 28 006FF A 00 07 00 00 70 OE (a) (DO) = $A (b) SP = 00006FE8 Contents of system stack: 006FE8 00 00 70 3E 00 00 70 3E 00 00 70 3E 00 00 70 3E 006FF8 00 00 70 3E 00 00 70 16 (c) (DO) +- smallest number in ARRAY

Chapter 7 7.1. CLR SUBQ ADD ADD NOT SUB ADD SUBQ AND ASL ASR NEG ROR

DO #1,DO #$7FFF,DO #2,DO DO #$FFFF,DO #$8000,DO #1,DO #$ABCD,DO #l,DO #l,DO DO #l,DO

SR=2704 SR=2719 SR=2711 SR=270A SR=2700 SR=271B SR=2717 SR=2719 SR=2718 SR=2713 SR=2700 SR=2719 SR=2719

DO=OOOO DO=FFFF DO=7FFE DO=8000 DO=7FFF DO=8000 DO=OOOO DO=FFFF DO=ABCD DO=579A DO=2BCD DO=D433 DO=EA19

APPENDIX G

ANSWERS TO SELECTED EXERCISES

7.2.

(a) L1

7.3. 7.4.

ZNCV: 01xx, (a) BGE, BLE, (b) BGE, BLE, (c) BLE, BLT, (d) BGE, BGT, (e) BGE, BGT, (f) BLE, BLT, (g) BLE, BLT, (h) BLE, BLT,

(b) L1

(c) L2 (d) L4 (e) 13 01xx, OOxx, OOxx, 10xx, 01xx, 0000, 1010 BLS BLS BBI BBI BBI BLS BLS BBI

7.5. The instruction should be BLS LOOP 7.6. If 2p>q then (DO) ~ 1; else (DO) ~ 2 7.7. (a) $FF (b) If (X) has n I-bits, then (Y) ~ 11 ... 1 (n times). Chapter 8 8.1.

(PC) = $7016

($6FFC) = $00007012

8.2. 8.3. 8.4. 8.5.

MOVE.L #NOW,2(SP) or ADD.L #2,2(SP) (PC) = $7018 ($6FFC) = $000070lE (PC) = $7034 ($6FFC) = $00007030 (a) 5 (b) 4 (c) 6 (d) impossible

Can be interrupted by Routine INT2, INT3, INT4 ENTER 1 INT4 ENTER2 none INTI none INT2 all INT3 none INT4 8.7. Change the MOVE #$2nOO,SR instruction in each routine as follows: Number on MOVE to SR Routine 2200 ENTER 1 2100 ENTER2 2200 INTI 2000 INT2 2400,2500,2600, or 2700 INT3 2000 INT4

8.6.

Chapter 9 9.1.

NEG MOV

Run time error (odd address with word instruction) Assembly error (wrong op code)

241

APPENDIX G

242

RTE JMP MOVE CLR

ANSWERS TO SELECTED EXERCISES

OK (comment) Run time error (illegal address) OK (contents of SP is always even) Assembly time error (invalid address field)

9.2. (a) Object module ofPROG2 (starting at $1000) 33FCI000 00000016 33FCFFEA 00001016 3B780FFB 0016 4AFC 1000FFED (b) Load module ofPROGl and PROG2 (starting at $1000) 4AFC 33FCI002 00000016 33FCFFEA 00001018 3B780FFD 0016 4AFC 1002FFED 9.3. Object module: 33F8000C 00001056' 317CFFFA 1008' 337CI062' 0004 4AFC 1010' FFCO Load module: 33F8000C 00002256 317CFFFA 2208 337C2262 0004 4AFC 2210 FFCO

Symbol table: A OOOOOOOC B 00001056' C FFFFFFFA D 00000004 E 00001008' F 0000100E' G 00001016'

APPENDIX G

9.4.

ANSWERS TO SELECTED EXERCISES

(a) MAIN: SUB1: SUB2:

GLOBAL GLOBAL GLOBAL

243

A,B,K,L,SUB1,X B,K,L,SUB1,SUB2,X A,L,SUB2,X

(b) Object module for MAIN: (l000)337C04000100 317A0022102C' 31FC,L,OlSO 31FA,X,0060 33F9,K,0000102C' 4EB9,SUB1 4AFC 100C' Symbol table: A 0000 102ARG K ********* G START 00001000R Global symbol table: 0000102AR A

B L SUB1

B

0000102CRG ********G ********G

C X

0000100CR ********G

L SUB2

0000002CRG ********G

0000102CR

Object module for SUB1: (0)33E9002D0000002C' 377C0012,B 31FC,B,0076 33FA,X,000000SO 4EB9,SUB2 31FAOFCC',B 4E7S ,X,(SO)FFF2 Symbol table: B ********G M OOOOOOSOR X ********G Global symbol table: K 00000012

K SUB1

L

00000012G OOOOOOOORG

0000002CR

SUB1

OOOOOOOOR

Object module for SUB2: (0)31FC0012,L 3B7A001C,A 33FA02F2'00000036' 6A000006 4EE9,L 31E900441234 4E7S 0036' Symbol table: ********G A 00000024RG X Global symbol table: SUB2 OOOOOOOOR

********G 00000036R

L Y X

SUB2 Z

OOOOOOOORG 0000001CR

00000024R

(c) Load map: MAIN 1000-1066, SUB1 1068-10B8, SUB2 lOBA-10FE Merged global symbol table: A 0000102AR B 0000102CR K 00000012 L 00001094R SUB1 00001068R SUB2 000010BAR X 000010DER (d) Load module for MAIN, SUB1, SUB2: (1000) 337C04000100 317A0022102C 31FC109401S0

APPENDIX G

244

ANSWERS TO SELECTED EXERCISES

3lFAOOCA0060 33F9000000l20000l02C 4EB900001068 4AFC 100C (1068) 33E9002DOOOO1094 377C0012l02C 3lFCl02C0076 33FA00600000l0B8 4EB90000l0BA 3lFAFF64l02C 4E75 lODE (10B8) FFF2 3lFC0012l094 3B7AOOlCl02A 33FAF2380000l0FO 6A000006 4EE9l094 3lE90044l234 4E75 10FO 9.5.

CLR LEA LEA MOVE

$100 K(PC),A3 L(PC),A4 0(A3,A4),A4

Chapter 10 10.1.

10.2

10.3.

MAC2 stores the low bytes of DO, Dl, ... , D(N-l) in Z, Z+l, ... , Z+N-l. Expansion: DO,TEMP+O MOVE.B MOVE.B Dl,TEMP+l MOVE.B D2,TEMP+2 MOVE.B D3,TEMP+3 MOVE.B D4,TEMP+4 (a) MOVE.B #O,TAB+O MOVE.B #l,TAB+l MOVE.B #6,TAB+6 L5 CMP.B DO,Dl BPL L5 DC.W 5,25,3 DS.B 100 CMP BNE DC.W DS.W

DO,Dl L5 52

INDEX

ABCD, 181,217 Absolute addresses, 138 Absolute long, 30 Absolute short, 29 ACIA,12 Actual argument, 153 ADD instructions ADD, 36,182,217 ADD A, 36, 182,218 ADDI, 36,182,218 ADDQ, 36,183,218 ADDX, 96,183,218 machine language, 43 Addition, 92 binary, 7 hex, 7 2's-complement, 19 Address, 11 absolute, 139 effective, 26 nominal, 12 relocatable, 138 Address expression, 139 Address modification, 141 Address register direct, 27 Address register indirect, 28 with displacement, 29 with index and displacement,29 Address trap error, 117 Addressing modes, 26 absolute long, 30 absolute short, 29

Addressing modes (Contd.) address register direct, 27 address register indirect, 28 with displacement, 29 with index and displacement,29 autodecrement, 28 autoincrement, 28 data register direct, 26 immediate, 31 PC relative with displacement, 30 with index and displacement, 30 ALU, 11 AND,40, 184,218 ANDI, 184, 185,218,219 Argument, 66 transmission, 68 Arithmetic logic unit (ALU), 11 Arithmetic operations, 92 ASCII,20 ASCII-to-binary example, 105-110 ASL,4l,185,2l9 ASR, 41,186,219 Assembler, 48 two pass, 136 Assembler directive, 49 Assembly, 48 conditional, 163

Assembly language instructions, 180. (See individual instruction) Assembly language program, 48 format, 52 Assembly time, 49 Assignment directive, 50 Asynchronous communication interface adaptor (ACIA),12 Autodecrement, 28 Autoincrement, 28 Backward echo example, 66 Basis (of recursion), 79 Bee, 187,220 BCRG,187 BCLR, 116, 188,220 Binary equivalent, 1 Binary number system, 1 Binary point, 22 Binary-to-decimal conversion, 4 Binary-to-hexadecimal conversion, 6 Bit, 9 input ready, 12 output ready, 13 parity, 20 sign, 17 supervisor, 116 trace, 116 Branch instructions, 38 BCC, 39,187,220

245

246

INDEX

Branch instructions (Contd.) BCS,39,187,220 BEQ, 39,187,220 BGE, 39,187,220 BGT, 39,187,220 BHI,39,187,220 BLE, 39,187,220 BLS, 39, 187,220 BLT, 39,187,220 BMI, 39, 187,220 BNE, 39,187,220 BPL,39,187,220 BRA, 38, 188,221 BSR, 69,188,221 BVC, 39,187,220 BVS, 39,187,220 IMP, 38, 195,225 BSET, 188,221 BSR, 69, 188,221 BTST, 35, 189,222 Buffer, 56 Buffer input pointer, 56 Buffer output pointer, 56 Bus trap error, 117 Byte, 10 high byte, 11 low byte, 11

Compare instructions (Contd.) CMPI, 35,191,222 CMPM, 97,191,223 Concatenation, 157 Condition codes, 11 carry (C), 19 extend (X), 20 negative (N), 11 overflow (V), 20 zero (Z), 11 Conditional assembly, 163 Conditional block, 163 Conditional branch instructions, 39 Conversions binary-to-decimal, 4 binary-to-hexadecimal, 6 decimal-to-binary, 1 decimal-to-hexadecimal, 3 hexadecimal-to-binary, 6 hexadecimal-to-decimal, 5 Coroutine, 84 CP,9 CP priority, 124 DBcc, 101, 191,223

C bit, 19 C condition code values, 102 Call,66 Calling program, 66 Carry, 19 Central memory (CM), 9 Central processor (CP), 9 Characters ASCII,174 digits, 20 letters, 20 nonprinting, 20 null,22 special,20 strings, 22 CHK, 119, 189,222 Circular buffer, 56 Clock,125 Clock status register, 125 CLR, 34,189,222 Coding hints, 58 Comment field, 52 Compare instructions CMP, 35,190,222 CMPA, 35, 190,222

Decimal number, 1 Decimal-to-binary conversion, 1 Decimal-to-hexadecimal conversion, 3 Destination field, 26 Destination operand, 26 Digit, 1 Directives DC.B, DC.L, DC.W, 49 DS.B, DS.L, DS.W, 50 END,52 ENDC, 163 ENDM, 152 ENDR,160 EQU, 50 EVEN,52 IF,163 IFF,164 IRP, 162 LOAD, 52 MACRO, 152 ORG,51 REPT,160 Displacement, 38 Displacement addressing, 29

Divide instructions DlVS, 37, 192,223 DlVU, 37, 193,223 Double-operand instructions, 32 Double-precision, 95 Double-precision arithmetic, 95 Double-precision number, 95 Dummy argument, 152 Effective address, 26 END, 52 ENDC, 163 ENDM,152 ENDR,160 EOR, 193,224 EORI, 194,224 EQU,50 EVEN,52 Execution cycle, 25 EXG, 34, 194,224 Exponent, 22 Exponentiation algorithm, 71 EXT, 34,195,225

Data register, 11 Factorial function, 80 Fibonacci numbers, 79 Fields, 52 Floating point representation IEEE standard fonnat, 23 of real numbers, 22 Fraction, 22 General purpose register, 11 Global symbol, 143 Global symbol table, 144 Hand assembly, 42 Hand disassembly, 42 Hexadecimal digits, 7 Hexadecimal equivalents, 3 Hexadecimal number systern, 1 Hexadecimal-to-binary conversion, 6 Hexadecimal-to-decimal conversion, 5 High byte, 10 High level language, 135 High-order addition, 95 High-order long word, 95 Higher priority device, 124

INDEX

IF, 163 IFF,164 ILLEGAL, 195,225 Illegal address trap (See address trap error) Illegal instruction trap, 116 Immediate source, 43 Index, 29 Induction, 79 Initialization, stack, 65 Input interrupt enable, 120 Input ready bit, 12 Interface registers, 12 Interrupts, 120 Interrupt-driven device, 121 Interrupt handler, 120 Interrupt routine, 120 Interrupt vector, 120 IRP, 162

IMP, 33,195,225 ISR, 69, 196,225 K,ll Keyboard data register, 13 Keyboard input interrupts, 120 Labe1,52 LEA, 59,196,225 LINK, 75,196,225 Linkage, 69 Linkage editor, 140 LOAD,52 Load map, 144 Load module, 140 Loading origin, 139 Local symbols, 159 Location, 11 Location counter, 135 Logical instructions AND, 40,184,218 NOT, 40, 203, 229 OR, 40, 204, 229 Long word, 10 Low byte, 10 Low-order long word, 95 LSL,41, 197,225 LSR, 41,197,225 Machine language, 25 MACRO, 151, 152-158 Macros, 150 Macro body, 152

247

Macro call, 152 Macro definition, 152 Macro heading, 152 Macro recursion, 167 Mantissa, 22 Masking, 56 Merged global symbol table, 144 Microprocessor chip, 9 Mnemonic op code, 32 Modular programs, 67 Motorola 68000-based computer system, 9 MOVE, 32, 198, 226 MOVEA, 32, 199,227 MOVEM, 76, 200, 228 MOVEP, 125,201,228 MOVEQ, 32, 201, 228 MSB (most significant bit), 16 MULS, 37,201,228 Multiple echo example, 56 MULU, 37, 202, 228 NBCD, 202, 228 N bit, 11 N condition code values, 102 NEG, 37, 202, 229 NEGX, 96,203,229 Nested subroutines, 76 Nominal address, 12 N onprinting characters, 20 No-operand instructions NOP, 42, 203, 229 RESET,42,205,230 NOT, 40, 203, 229 Null character, 22 Number, 1 floating point representation,22 one's complement representation, 16 storing negatives, 16 two's complement representation, 15 Number systems, 1 Object module, 140 Object program, 48 Odd parity, 20 One's complement, 16 Op code, 32 Op code table, 135 Op mode field, 43

Open subroutine, 152 Operand field, 52 Operating modes, 117 Operation code, 32 Operator field, 52 OPR,32 OR, 40, 204, 229 ORG,51 ORI, 204, 205, 229 Output interrupt enable, 120 Output ready bit, 13 Overflow indication, 92 Parameter, 70 Parameter passing, 70 Parity bit, 20 PC,11 PC relative modes, 30 PEA, 206, 230 Peripheral devices, 9 Permutation example, 79 PIC, 145 PIIT, 14, 125 Polling, 54 Pop,65 Position independent code, 30, 145 Powers of 2,6 Powers of 16, 6 Preload counter, 125 Priority, 124 Priority field, 123 Priority of an interrupt, 124 Priority of a peripheral device, 124 Processor traps, 116 Program counter, 11 Program traps, 119 Programming style, 235 Pseudo-instructions, 49 Pure procedure, 67 Push,65 Quarter-byte, 62 Recursion, 79 Recursive function, 79 Recursive subroutine, 80 Reentrant code, 67 Register, 11 keyboard data, 13 terminal control, 13 terminal output data, 13

INDEX

248

Register (Contd.) terminal status, 12 timer control, 125 timer status, 125 Relocatable address, 139 Repeat block, 160 REPT,160 RESET,42,205,230 ROL, 40, 206, 230 ROR, 40, 206, 230 ROXL, 104,207,231 ROXR, 104,208,231 RTE, 118,208,231 RTR, 208, 232 RTS, 69, 209, 232 Run time, 49 SBCD, 209, 232 Sec, 209, 232

Scientific notation, 22 SET,161 Shift instructions, 40 Sign bit, 17 Signed conditional branch, 99 Single-operand instructions,32 Single precision, 22 Source field, 26 Source program, 48 Special characters, 20 Stack,64 Stack overflow, 66 Stack pointer (SP), 11

Stack underflow, 66 Statement, 52 Status register, 11 STOP, 210, 232 Subprograms (See subroutines) Subroutines, 66 Subtraction instructions, 36 SUB, 36, 210, 233 SUBA, 36, 211, 233 SUBI, 36, 211,233 SUBQ, 36, 212, 233 SUBX, 97, 212, 233 Subtraction of powers method,1 Supervisor mode, 117 SWAP, 34,213,234 Symbol table, 135 Symbolic address, 52 Symbols global, 143 loca1,159 System stack, 69 TAS, 213, 234 Terminal; 12 Terminal control register, 13 Terminal output data register, 13 Terminal status register, 12 Timer control register (TCR),125 Timer status register (TSR), 125 Top-down programming, 67

Tower of Hanoi example, 81 Trace bit, 116 Trace mode, 116 TRAP, 119,213,234 Trap errors address trap error, 117 bus trap error, 117 Trap handler, 116 Trap routine, 116 TRAPV, 119,214,234 Trap vector, 116 TST,97,214,234 Two-pass assembly, 136 Two's complement addition and subtraction, 19 representation, 15 UNLK, 75, 214, 234 Unsigned conditional branch, 99 Unsigned numbers, 99 User mode, 117 V bit, 20 V condition code values, 102 Word,10 high-order long word, 95 low-order long word, 95 X bit, 20 X condition code values, 102 Z bit, 12 Z condition code values, 102