Analog Circuit Design Volume 2: Immersion in the Black Art of Analog Design 9780123978882, 1865843830, 0123978882

Citation preview

Analog Circuit Design Volume 2 Immersion in the Black Art of Analog Design

This page is intentionally left blank

Analog Circuit Design Volume 2 Immersion in the Black Art of Analog Design

Edited

by

Bob Dobkin Jim Williams

AMSTERDAM • BOSTON • HEIDELBERG • LONDON • NEW YORK • OXFORD PARIS • SAN DIEGO • SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO

Newnes is an imprint of Elsevier

Newnes

Newnes is an imprint of Elsevier The Boulevard, Langford Lane, Kidlington, Oxford OX5 1GB, UK 225 Wyman Street, Waltham, MA 02451, USA First edition 2013 Copyright �© 2013, Linear Technology Corporation. Published by Elsevier Inc. All rights reserved. See separate Publisher’s Note for copyright details of Trade Marks used in this book. The right of Linear Technology Corporation to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means electronic, mechanical, photocopying, recording or otherwise without the prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone (+44) (0) 1865 843830; fax (+44) (0) 1865 853333; email: [email protected]. Alternatively you can submit your request online by visiting the Elsevier web site at http://elsevier.com/locate/permissions, and selecting Obtaining permission to use Elsevier material. Notice No responsibility is assumed by the publisher or authors/contributors for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions or ideas contained in the material herein. Because of rapid advances in the medical sciences, in particular, independent verification of diagnoses and drug dosages should be made. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library Library of Congress Cataloging-in-Publication Data A catalog record for this book is availabe from the Library of Congress ISBN: 978-0-12-397888-2

For information on all Syngress publications visit our website at http://store.elsevier.com Printed and bound in the United States of America 13 14 15  10 9 8 7 6 5 4 3 2 1

For Jerrold R. Zacharias, who gave me the sun, the moon and the stars. For Siu, who is the sun, the moon and the stars.

This page is intentionally left blank

In memory of Jim Williams, a poet who wrote in electronics.

This page is intentionally left blank

Contents Publisher’s Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii



PART 1 Power Management �������������������������������������������������������������������� 1

Section

1 Power Management Tutorials . . . . . . . . . . . . . . . . . . 3



1 Performance enhancement techniques for three-terminal regulators . . . . . . . . . . . .5 2 Load transient response testing for voltage regulators . . . . . . . . . . . . . . . . . . . 13 3 A closed-loop, wideband, 100A active load . . . . . . . . . . . . . . . . . . . . . . . . . 29

Section

2 Switching Regulator Design . . . . . . . . . . . . . . . . . . . 41

4 Some thoughts on DC/DC converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 Theoretical considerations for buck mode switching regulators . . . . . . . . . . . . . . 89

Section 3 Linear Regulator Design . . . . . . . . . . . . . . . . . . . . . . . . .135

6 High efficiency linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Section 4 High Voltage and High Current Applications . . . . . . . . . . . . 149 7 High voltage, low noise, DC/DC converters . . . . . . . . . . . . . . . . . . . . . . .

151

Section 5 Powering Illumination Devices . . . . . . . . . . . . . . . . . . . . .199 8 A fourth generation of LCD backlight technology . . . . . . . . . . . . . . . . . . . . . 201 9 Simple circuitry for cellular telephone/camera flash illumination . . . . . . . . . . . . . 323

Section 6 Automotive and Industrial Power Design . . . . . . . . . . . 333



10  Extending the input voltage range of PowerPath circuits for automotive and industrial applications . . . . . . . . . . . . . . . . . . . . . . . .

335

PART 2 Data Conversion, Signal Conditioning and High Frequency/RF 337

Section

1 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . 339

11 Circuitry for single cell operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

341 ix

Contents



12 Component and measurement advances ensure 16-bit DAC settling time . . . . . . . . 349 13 Fidelity testing for A→D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Section 2 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . 405 14 Applications for a new power buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal techniques in measurement and control circuitry . . . . . . . . . . . . . . . . 16 Methods of measuring op amp settling time . . . . . . . . . . . . . . . . . . . . . . . . 17 High speed comparator techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Designs for high performance voltage-to-frequency converters . . . . . . . . . . . . . 19 Unique IC buffer enhances op amp designs, tames fast amplifiers . . . . . . . . . . . . 20 Power gain stages for monolithic amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 21 Composite amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 A simple method of designing multiple order all pole bandpass filters by cascading 2nd order sections . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FilterCAD user’s manual, version 1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 30 nanosecond settling time measurement for a precision wideband amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Application and optimization of a 2GHz differential amplifier/ADC driver . . . . . . . . 26 2 nanosecond, 0.1% resolution settling time measurement for wideband amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 An introduction to acoustic thermometry . . . . . . . . . . . . . . . . . . . . . . . . .

407 415 423 431 463 483 507 523 535 551 577 607 639 665

Section 3 High Frequency/RF Design . . . . . . . . . . . . . . . . . . . 681 28 Low noise varactor biasing with switching regulators . . . . . . . . . . . . . . . . . . . 683 29 Low cost coupling methods for RF power detectors replace directional couplers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 30 Improving the output accuracy over temperature for RMS power detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715



PART 3 Circuit Collections . . . . . . . . . . . . . . . . . . . . . . . 719

31 Circuit techniques for clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 32 Measurement and control circuit collection . . . . . . . . . . . . . . . . . . . . . . . . 729 33 Circuit collection, volume I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 34 Video circuit collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 35 Practical circuitry for measurement and control problems . . . . . . . . . . . . . . . . 801 36 Circuit collection, volume III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 37 Circuitry for signal conditioning and power conversion . . . . . . . . . . . . . . . . . . 929 38 Circuit collection, volume V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961 39 Signal sources, conditioners and power circuitry . . . . . . . . . . . . . . . . . . . . .1083 40 Current sense circuit collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 41 Power conversion, measurement and pulse circuits . . . . . . . . . . . . . . . . . . .1217

x

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235

Publisher’s Note

This book was compiled from Linear Technology Corporation’s original Application Notes. These Application Notes have been re-named as chapters for the purpose of this book. However, throughout the text there is a lot of cross referencing to different

Application Notes, not all of which have made it into the book. For reference, this conversion table has been included; it shows the book chapter numbers and the original Application Note numbers.

CHAPTER NUMBER

APPLICATION NOTE

CHAPTER NUMBER

APPLICATION NOTE

1

2

22

27A

2

104

23

38

3

133

24

79

4

29

25

123

5

44

26

128

6

32

27

131

7

118

28

85

8

65

29

91

9

95

30

129

10

107

31

12

11

15

32

45

12

74

33

52

13

132

34

57

14

4

35

61

15

5

36

67

16

10

37

75

17

13

38

87

18

14

39

98

19

16

40

105

20

18

41

113

21

21

xi

SECTION ONE

Publisher’s Note

Trademarks These trademarks all belong to Linear Technology Corporation. They have been listed here to avoid endless repetition within the text. Trademark acknowledgment and protection applies regardless. Please forgive us if we have missed any. Linear Express, Linear Technology, LT, LTC, LTM, Burst Mode, Dust Networks, FilterCAD, LTspice, OPTILOOP, Over-The-Top, PolyPhase, SwitcherCAD, TimerBlox, µModule and the Linear logo are registered trademarks of Linear Technology Corporation. Adaptive Power, Bat-Track, BodeCAD, C-Load, Direct Flux Limit,

xii

DirectSense, Dust, Easy Drive, Eterna EZSync, FilterView, Hot Swap, isoSPI, LDO+, LinearView, LTBiCMOS, LTCMOS, LTPoE++, LTpowerCAD, LTpowerPlanner, LTpowerPlay, MicropowerSwitcherCAD, Mote-onChip, Multimode Dimming, No Latency ∆∑, No Latency Delta-Sigma, No RSENSE, Operational Filter, PanelProtect, PLLWizard, PowerPath, PowerSOT, PScope, QuikEval, RH DICE Inside, RH MILDICE Inside, SafeSlot, SmartMesh, SmartMesh IP, SmartStart, SNEAK-A-BIT, SoftSpan, Stage Shedding, Super Burst, SWITCHER+, ThinSOT, Triple Mode, True Color PWM, UltraFast, Virtual Remote Sense, Virtual Remote Sensing, VLDO and VRS are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Acknowledgments

Analog Circuit Design, Volume 2 emerges a year after the first volume through the efforts of a dedicated team. For many of us, this is a labor of love, giving further legs to the timeless application notes of the late Jim Williams and many colleagues at Linear Technology. Thanks first to the authors, who do the heavy lifting—in the lab and through their insightful writing. Also to the dedicated graphics and

editorial team that ensured that the application notes are clear and consistent—Gary Alexander and Susan Dale. We are indebted to the efforts of the professionals at Elsevier/Newnes, including publisher Jonathan Simpson and the production efforts of Pauline Wilkinson and Fiona Geraghty. Finally, to Bob Dobkin for his insight, time and belief in this project.

John Hamburger Linear Technology Corporation

xiii

This page is intentionally left blank

Introduction

Why I Write In the early 1980s we wanted prospective customers to know our name and what we were up to. The real issue was finding a way to productively use the seeming dead time before product availability. What readers wanted was a series of credible, full length technical articles in the language of relevant, working circuits. I moped for weeks over this problem before a possible solution became apparent. Instead of waiting for products, I’d simply go into the lab, develop the applications, and then write the articles. The key to this approach was to synthesize the expected products using available ICs and discretes to build rough equivalents on small plugin boards. We could develop functional applications and write most of the text. We’d then shelve the manuscript and breadboards. Later, when products became available, we could put them into the breadboards and implement the attendant final changes. Once we had done these tasks, we could drop scope photos and specifications into the waiting text, tweak the manuscript, and ship it off. This approach would speed publication by perhaps a year and synchronize the article’s appearance with product introduction. Initially, the whole scheme appeared absurd and eminently unworkable, with uncountable technical and editorial sinkholes. Getting started was much more difficult than I had imagined. Synthesizing the hardware for our unborn ICs proved tricky; my methods, clumsy and stumbling. Breadboarding the applications was laborious and slow, primarily because I wasn’t sure how accurately I was mimicking the forthcoming IC’s performance.

Writing was equally painful. Text flow was staccato and disjointed because of the gaps that occurred while I waited for results with actual products. I had to keep separate notes directing me to unfinished text when we finally dropped the products into the breadboards. The first article took almost two months, but things slowly became easier. Tricks to move along the lab work evolved, and I found ways to write more efficiently, making the manuscripts inherently adaptable to the planned additions and changes. Soon, I was producing an almost-finished article every two weeks or so, roaring along, powered by adrenaline, solder, pencils, paper, and pizza. During the next year, life was a dizzy seven-day-a-week blur of breadboards and manuscripts shuttling between work and my home lab. My diet was a cardiologist’s nightmare. I don’t recall having a meal at home. The refrigerator was devoid of food but well-provisioned with Polaroid film to feed the oscilloscope camera. All this frenetic bustle boiled off any semblance of a normal social life. At dinner in San Francisco, while nominally listening to my date describe her job intricacies, I silently calculated the optimum chapper-channel crossover frequency in a composite amplifier. The regimen of madness continued for about a year, resulting in 35 full-length feature articles between June 1983 and November 1987. I still write, although at a significantly less frenetic pace. Now, when the kids in our lab complain to me about writing technical material, I try not to sound like the curmudgeon I am not so slowly becoming. I think that mad tear almost 25 years ago contributes to my current lack of empathy. These kids today, with a catalog full of products, they don’t know what they’ve got.

Jim Williams Staff Scientist Linear Technology Corporation Note: This essay originally appeared in EDN magazine.

xv

This page is intentionally left blank

Foreword

We appreciate the enthusiastic response to the original book, Analog Circuit Design: A Tutorial Guide to Applications and Solutions. The acceptance of this book emphasizes the need for making good circuit design applications accessible. These writings on applications fill a vacuum, since the majority of application notes and magazine articles do not have sufficient depth to teach analog design. At the time I learned analog design, there were not yet any analog ICs. Circuits were all transistorized (maybe some tubes) and the circuit explanations in magazines and books were more complete than many are today. In those days equipment manuals included schematics for repair. I was fortunate to work at a large company with a huge calibration lab for their equipment. I spent many lunch hours perusing the calibration and repair manuals for analog systems. I thank HP, Tektronix and many other companies for their tutorials on analog circuit design that I discovered in the calibration lab. It is interesting to note that Jim Williams in his early years at MIT spent much time repairing electronic test equipment that was nonfunctional. Today’s manuals are more sparse. It is relatively hard to find completed analog designs to study. Books may include analog designs, but they are not necessarily complete circuits with test results. Likewise most application notes are very specific to the device they are showing and don’t provide a general breadth of information that is useful in the analog world. I am pleased that this book series is becoming a teaching handbook of applications. An application should be useful, have multiyear life and be easy to duplicate. Any good application note should have a description of the application and discussion of where it will be used. It should include ancillary information, such as temperature range, power systems, lifetime and other key data usually excluded in textbooks that just focus on principles. The application block diagram needs to be explained so that the approach to the solution is understandable. Unless you know where you are going, it is difficult to understand how you got there. The circuits for the applications need to be fully developed, have part types and construction information. The solutions may include specialized components that require the reader to have knowledge of the function and special properties. The circuit should be shown and the properties and function of each item in the circuit explained with sufficient detail that readers can extract that information and use it again. The origin of “breadboard” dates back to a time when actual bread cutting boards were used to assemble

electronic circuits for testing. Components were screwed to the board and wired with Fahnestock clips, such as the one in this diagram.

Many analog circuits are layout-sensitive and if not properly laid out, the circuits may not work. I have seen many circuits constrained by this problem. Finally, designers need a detailed set of test results for the circuit. These show how the circuit works when it’s working properly and provides a comparison guide for anyone trying to duplicate the circuit. Without all of these, the applications fail as part of a teaching system. Analog design is challenging. There are many ways to get from input to output, and the circuitry in the middle can lead to divergent results. Analog design is like learning a language. When you first learn a language, you begin with a vocabulary book and then analyze writings in that language by looking up words one by one as you encounter them. Likewise, in analog design you learn the basics of the circuit, as well as the function of different devices. You can write node equations and determine what the circuit is doing by studying each of the individual circuits. With analog circuit design, you end up using the basic circuit configurations you have learned—differential amplifiers, transistors, FETs, resistors, and previously studied circuits—to achieve the final circuit. As with a new language, it takes many years to learn to write poetry, and the same is true of analog circuit design. Today’s system manuals rarely have any circuit design. They contain block diagrams and hookup schematics with thousands of leads to different blocks. So where do people go for analog circuit design? If you’re just starting, or if you encounter a problem that’s outside your experience, appropriate references are difficult to find. xvii

Foreword

Hopefully, these books provide some answers, as well as circuit design and test and lab techniques for design and duplication of the circuits. Today, analog design is in greater demand than ever before. Analog design is now a combination of transistors and ICs that provide high functionality in analog signal processing. This volume focuses on fundamental aspects of

xviii

circuit design, layout, and testing. It is our hope that the talented writers of these application notes shed some light on the “black art” of analog design.

Bob Dobkin Co-Founder, Vice President, Engineering, and Chief Technical Officer Linear Technology Corporation

PART 1 Power Management

This page is intentionally left blank

Section 1 Power Management Tutorials Performance enhancement techniques for three-terminal regulators (1) This application note describes a number of enhancement circuit techniques used with existing 3-terminal regulators which extend current capability, limit power dissipation, provide high voltage output, operate from 110VAC or 220VAC without the need to switch transformer windings, and many other useful application ideas.

Load transient response testing for voltage regulators (2) Semiconductor memory, card readers, microprocessors, disc drives, piezoelectric devices and digitally based systems furnish transient loads that a voltage regulator must service. Ideally, regulator output is invariant during a load transient. In practice, some variation is encountered and becomes problematic if allowable operating voltage tolerances are exceeded. This mandates testing the regulator and its associated support components to verify desired performance under transient loading conditions. Various methods are employable to generate transient loads, allowing observation of regulator response. This application note presents open and closed loop transient load testing

circuitry with measured performance taken under various conditions. Practical considerations for a memory supply voltage regulator are reviewed. Four appended sections cover capacitor parasitics and their effects on load transient response, output capacitor selection, probing techniques and a stabilized transient load tester.

A closed-loop, wideband, 100A active load (3) Digital systems, particularly microprocessors, furnish transient loads in the 100A range that a voltage regulator must service. Ideally, regulator output is invariant during a load transient. In practice, some variation is encountered and becomes problematic if allowable operating voltage tolerances are exceeded. 100A load steps, characteristic of microprocessors, exacerbate this issue, necessitating testing the regulator and associated components under such transient loading conditions. To meet this need, a closed-loop, 500kHz bandwidth, linearly responding, 100A capacity active load is described. Study of this approach is prefixed by a brief review of conventional test load types and noting their shortcomings.

This page is intentionally left blank

Performance enhancement techniques for three-terminal regulators

1

Jim Williams

Three terminal regulators provide a simple, effective solution to voltage regulation requirements. In many situations the regulator can be used with no special considerations. Some applications, however, require special techniques to enhance the performance of the device. Probably the most common modification involves extending the output current of regulators. Conceptually, the simplest way to do this is by paralleling devices. In practice, the voltage output tolerance of the regulators can cause problems. Figure 1.1 shows a way to use two regulators to achieve an output current equal to their sum. This circuit capitalizes on the 1% output tolerance of the specified regulators to achieve a simple paralleled configuration. Both regulators sense from the same divider string and the small value resistors provide ballast to account for the slightly differing output voltages. This added impedance degrades total circuit regulation to about 1%.

Figure 1.2 shows another way to extend current capability in a regulator. Although this circuit is more complex than Figure 1.1, it eliminates the ballasting resistor’s effects and has a fast-acting logic-controlled shutdown feature. Additionally, the current limit may be set to any desired value. This circuit extends the 1A capacity of the LT®1005 multifunction regulator to 12A, while retaining the LT1005’s enable feature and auxiliary 5V output. Q1, a booster transistor, is servo-controlled by the LT1005, while Q2 senses the current dependent voltage across the 0.05Ω shunt. When the shunt voltage is large enough, Q2 comes on, biasing Q3 and shutting down the regulator via the LT1005’s enable pin. The shunt’s value can be selected for the desired current limit. The 100°C thermo-switch limits dissipation in Q1 during prolonged short circuits by disabling the LT1005. It should be mounted on Q1’s heat sink.

Figure 1.1 • Paralleling Regulators with Small Ballast Resistors Analog Circuit and System Design: Immersion in the Black Art of Analog Design. http://dx.doi.org/10.1016/B978-0-12-397888-2.00001-8 © 2013, Linear Technology Corporation. Published by Elsevier Inc. All rights reserved.

SECTION ONE

Power Management Tutorials

Boosted regulator schemes of this type are often poorly dynamically damped. Such improper loop compensation results in large output transients for shifts in the load. In particular, because Q1’s common emitter configuration has voltage gain, transients approaching the input voltage are possible when the load drops out. Here, the 100μF capacitor damps Q1’s tendency to overshoot, while the 20Ω value provides turn-off bias. The 250μF unit maintains Q1’s emitter at DC. Figure 1.3 shows that this “brute force” compensation works quite well. Normally the regulator sees no load. When Trace A goes high, a 12A load (regulator output current is Trace C) is placed across the

output terminals. The regulator output voltage recovers quickly, with minimal aberration. While the 100μF output capacitor aids stability, it prevents the regulator output from dropping quickly when the enable command is given. Because Q1 cannot sink current, the 100μF unit’s discharge time is load limited. Q4 corrects this problem, even when there is no load. When the enable command is given (Trace A, Figure 1.4) Q3 comes on, cutting off the LT1005 and forcing Q1 off. Simultaneously, Q4 comes on, pulling down the regulator output (Trace B), and sinks the 100μF capacitor’s discharge current (Trace C). If fast turn-off is not needed, Q4 may be omitted.

Figure 1.2 • Switched High Current Regulator with Fast Turn-off

Figure 1.3 •

6

Figure 1.4 •

Performance enhancement techniques for three-terminal regulators

Power dissipation control is another area where regulators can be helped by additional circuitry. Increasing heat sink area can be used to offset dissipation problems, but is a wasteful and inefficient approach. Instead, the regulator can be placed within a switched-mode loop that servo-controls the voltage across the regulator. In this arrangement the regulator functions normally while the switched-mode control loop maintains the voltage across it at a minimal value, regardless of line or load changes. Although this approach is not quite as efficient as a classical switching regulator, it offers lower noise and the

CHAPTER 1

fast transient response of the linear regulator. Figure 1.5 details a DC driven version of the circuit. The LT350A functions in the conventional fashion, supplying a regulated output at 3A capacity. The remaining components form the switched-mode dissipation limiting control. This loop forces the potential across the LT350A to equal the 3.7V value of VZ. When the input of the regulator (Trace A, Figure 1.6) decays far enough, the LT1018 output (Trace B) switches low, turning on Q1 (Q1 collector is Trace D). This allows current flow (Trace C) from the circuit input into the 4500μF capacitor, raising the regulator’s

Figure 1.5 • Switching Preregulator

Figure 1.6 • Switching Waveforms

7

SECTION ONE

Power Management Tutorials

input voltage. When the regulator input rises far enough, the comparator goes high, Q1 cuts off and the capacitor ceases charging. The 1N4003 damps the flyback spike of the current-limiting inductor. The 4.7kΩ unit ensures circuit start-up and the 68pF-1MΩ combination sets loop hysteresis at about 80mVP-P. This free-running oscillation control mode substantially reduces dissipation in the regulator, while preserv-

ing its performance. Despite changes in the input voltage, different regulated outputs or load shifts, the loop always ensures the minimum possible dissipation in the regulator. Figure 1.7 shows the dissipation limiting technique applied in a more sophisticated circuit. The AC-powered version provides 0V-35V, 10A regulation under high line-low line (90VAC-140VAC) conditions with good efficiency. In this version, two SCRs and a center-tapped

Figure 1.7 • Phase Controller Preregulator for 50 or 60 Hz Power Input

8

Performance enhancement techniques for three-terminal regulators

transformer source power to the inductor-capacitor combination. The transformer output is also diode rectified (Trace A, Figure 1.8), divided down, and used to reset the 0.1μF unit (Trace B) via C1. The resulting AC line synchronous ramp at C1’s output is compared to A1’s offset output by C2. A1’s output represents the deviation from the VZ value that the loop is trying to force across the LT1038. When the ramp output exceeds C2’s “+” input value, C2 pulls low, dumping current through T1’s primary (Trace C). This fires the appropriate SCR and a path from the main transformer to the LC pair occurs (Trace D). The resultant current flow (Trace E) is limited by the inductor and charges the capacitor. When the

CHAPTER 1

AC line cycle drops low enough, the SCR commutates and charging ceases. On the next half cycle the process repeats, except that the alternate SCR does the work. In this fashion, the loop controls the phase angle at which the SCRs fire to keep the voltage across the LT1038 at VZ (3.7V). As a result, the circuit functions over all line, load and output voltage conditions with good efficiency. The 1.2V LT1004 at the LT1038 allows the output voltage to be set down to 0.00 and the 2N3904 clamp at A1 prevents loop “hang-up”. Figure 1.7A shows a way to trigger the SCRs without using a transformer. Although A1’s output is an analog voltage, the ACdriven nature of the circuit makes it approximate a

Figure 1.7A • Triggering SCR without a Transformer

Figure 1.8 • Trigger Waveforms

9

SECTION ONE

Power Management Tutorials

smoothed, sample loop response. Conversely, the regulator constitutes a true linear system. Because these two feedback systems are interlocked, frequency compensation can be difficult. In practice, A1’s 1μF capacitor keeps dissipation loop gain at a low enough frequency for stable characteristics, without influencing the LT1038’s transient response characteristic. Trace A, Figure 1.9 shows the output noise while the circuit is operating at 35V into a 10A load (350W). Note the absence of fast switching transients and harmonics. The output noise is made up of residual 120Hz ripple and regulator noise. Reflected noise into the AC power line is also negligible (Trace B) because the inductor limits current rise time to about 1ms, much slower than the normal switching supplies. Figure 1.10 shows a plot of efficiency versus output voltage for a 10A load. At low output voltages, where the static losses across the regulator and SCRs

Figure 1.9 •

are significant, efficiency suffers, but 85% is attained at the upper extreme. High voltage output is another area for regulator enhancement. In theory, because the regulator does not have a ground pin, it can regulate high voltages. In normal operation the regulator floats at the supply’s upper level, and as long as the VIN–VOUT maximum differential is not exceeded there are no problems. However, if the output is shorted, the VIN–VOUT maximum is exceeded and device destruction will occur. The circuit of Figure 1.11 shows a complete high voltage regulator that delivers 100V at 100mA and withstands shorts to ground. Even at 100V output the LT317A functions in the normal mode, maintaining 1.2V between its output and adjustment pin. Under these conditions the 30V Zener is off and Q1 conducts. When an output short occurs, the Zener

Figure 1.10 •

Figure 1.11 • Preregulating and Buffering the Voltage to the IC Allows Operation with High Voltage

10

Performance enhancement techniques for three-terminal regulators

conducts, forcing Q1’s base to 30V. This causes Q1’s emitter to clamp 2 VBEs below VZ, well within the VIN–VOUT rating of the regulator. Under these conditions, Q1, a high voltage device, sustains 90V VCE at whatever current the transformer and the regulator’s current limit will support. The transformer specified saturates at 130mA, keeping Q1 well within its safe area as it dissipates 12W. If Q1 and the LT317A are thermally coupled, the regulator will soon go into thermal shutdown and oscillation will commence. This action will continue, protecting the load and the regulator as long as the output remains shorted. The 500pF capacitor and the 10Ω-0.02μF damper aid transient response and the diodes provide safe discharge paths for the capacitors. This approach to high voltage regulation is primarily limited by the power dissipation capability of the device in series with the regulator. Figure 1.11A uses a vacuum tube (remember them?) to achieve very high short-circuit dissipation capability. The tube allows high voltage operation and is extremely tolerant of overloads. This circuit allows the LT317A to control 600W at 2000V (V1’s plate limit is 300mA) with full short-circuit protection. Power is not the only area in which regulator performance can be augmented. Figure 1.12 shows a way to increase the stability of a regulator’s output over time and temperature. This is particularly useful in powering strain

Figure 1.11A • Very High Voltage Regulator

CHAPTER 1

gauge-based transducers. In this circuit the output voltage is divided down and compared to the 2.5V reference by A1, a precision amplifier. A1’s output is used to force the LT317A’s adjustment pin to whatever voltage is required to maintain the 10V output. A1 contributes negligible error. The resistors specified will track within 5ppm/°C and the reference contributes about 20ppm/°C. The regulator’s internal circuitry protects against short circuits and thermal overload. Figure 1.13’s circuit allows a regulator to remotely sense the feedback voltage, eliminating the effects of voltage drop in the supply lines. This is a concern where high currents must be transmitted over relatively long supply rails or PC traces. Figure 1.13’s circuit uses A1 to sense the voltage at the point of load. A1’s output, summed with the regulator’s output, modifies the adjustment pin voltage to compensate for the voltage lost across RDROP. The feedback divider is returned through a separate lead from the load, completing the remote sensing scheme. The 5μF capacitor filters noise and the 1k value limits bypass capacitor discharge when power is turned off. A final circuit allows voltage regulator-powered circuity to run from 110VAC or 220VAC without having to switch transformer windings. Regulator dissipation does not increase for 220VAC inputs. In Figure 1.14, when T1 is

Figure 1.12 • Using a Regulator as a Protected Power Stage for a Reference

11

SECTION ONE

Power Management Tutorials

driven from 110VAC, the LT1011 output goes high, allowing the SCR to receive gate bias through the 1.2k resistor. The 1N4002 is off. T1’s output is rectified by the SCR and the regulator sees about 8.5V at its input. If T1 is plugged into a 220VAC source, the negative input at the LT1011 is driven beyond 2.5V and the device’s output clamps low. This steers the SCR’s gate bias to ground through the LT1011’s output transistor. The diodes in the LT1011 output line prevent reverse voltages from reaching the SCR

or the LT1011 output. Now, the SCR goes off and the 1N4002 sources current to the regulator from T1’s center tap. Although T1’s input voltage has doubled, its output potential has halved and the regulator power dissipation remains the same. Figure 1.15 shows the AC line input versus regulator input voltage transfer function. The switch to center tap drive occurs midway between 110VAC and 220VAC. The hysteresis, a desirable characteristic, occurs because T1’s output voltage shifts with the step change in loading.

Figure 1.13 • Remote Sensing the Load Voltage for Better Regulation

Figure 1.14 • Switched Input Voltage for Operating over a Wide Input Range

12

Figure 1.15 •

Load transient response testing for voltage regulators Practical considerations for testing and evaluating results

2

Jim Williams

Introduction Semiconductor memory, card readers, microprocessors, disc drives, piezoelectric devices and digitally based systems furnish transient loads that a voltage regulator must service. Ideally, regulator output is invariant during a load transient. In practice, some variation is encountered and becomes problematic if allowable operating voltage tolerances are exceeded. This mandates testing the regulator and its associated support components to verify desired performance under transient loading conditions. Various methods are employable to generate transient loads, allowing observation of regulator response.

Basic load transient generator Figure 2.1 diagrams a conceptual load transient generator. The regulator under test drives DC and switched resistive loads, which may be variable. The switched current

Figure 2.1 • Conceptual Regulator Load Tester Includes Switched and DC Loads and Voltage/Current Monitors. Resistor Values Set DC and Switched Load Currents. Switched Current is Either On or Off; There is No Controllable Linear Region

and output voltage are monitored, permitting comparison of the nominally stable output voltage versus load current under static and dynamic conditions. The switched current is either on or off; there is no controllable linear region. Figure 2.2 is a practical implementation of the load transient generator. The voltage regulator under test is augmented by capacitors which provide an energy reservoir, similar to a mechanical flywheel, to aid transient response. The size, composition and location of these capacitors, particularly COUT, has a pronounced effect on transient response and overall regulator stability.1 Circuit operation is straightforward. The input pulse triggers the LTC1693 FET driver to switch Q1, generating a transient load current out of the regulator. An oscilloscope monitors the instantaneous load voltage and, via a “clip-on” wideband probe, current. The circuit’s load transient generating capabilities are evaluated in Figure 2.3 by substituting an extraordinarily low impedance power source for the regulator. The combination of a high capacity power supply, low impedance connections and generous bypassing main-

Figure 2.2 • A Practical Regulator Load Tester. FET Driver and Q1 Switch RLOAD. Oscilloscope Monitors Current Probe Output and Regulator Response Note 1: See Appendix A, “Capacitor Parasitic Effects on Load Transient Response” and Appendix B, “Output Capacitors and Stability” for extended discussion.

Analog Circuit and System Design: Immersion in the Black Art of Analog Design. http://dx.doi.org/10.1016/B978-0-12-397888-2.00002-X © 2013, Linear Technology Corporation. Published by Elsevier Inc. All rights reserved.

SECTION ONE

Power Management Tutorials

tains low impedance across frequency. Figure 2.4 shows Figure 2.3 responding to the LTC1693-1 FET driver (Trace A) by cleanly switching 1A in 15ns (Trace B). Such speed is useful for simulating many loads but has restricted versatility. Although fast, the circuit cannot emulate loads between the minimum and maximum currents.

Figure 2.5 • Conceptual Closed Loop Load Tester. A1 Controls Q1’s Source Voltage, Setting Regulator Output Current. Q1’s Drain Current Waveshape is Identical to A1 Input, Allowing Linear Control of Load Current. Voltage and Current Monitors are as in Figure 2.1

Figure 2.3 • Substituting Well Bypassed, Low Impedance Power Supply for Regulator Allows Determining Load Tester’s Response Time

of nearly any load profile. Feedback from Q1’s source to the A1 control amplifier closes a loop around Q1, stabilizing its operating point. Q1’s current assumes a value dependant on the control input voltage and the current sense resistor over a very wide bandwidth. Note that once A1 biases to Q1’s conductance threshold, small variations in A1’s output result in large current changes in Q1’s channel. As such, large output excursions are not required from A1; its small signal bandwidth is the fundamental speed limitation. Within this restriction, Q1’s current waveform is identically shaped to A1’s control input voltage, allowing linear control of load current. This versatile capability permits a wide variety of simulated loads.

FET based circuit

Figure 2.4 • Figure 2.2’s Circuit Responds to FET Driver Output (Trace A), Switching a 1A Load (Trace B) in 15ns

Closed loop load transient generators Figure 2.5’s conceptual closed loop load transient generator linearly controls Q1’s gate voltage to set instantaneous transient current at any desired point, allowing simulation 14

Figure 2.6, a practical incarnation of a FET based closed loop load transient generator, includes DC bias and waveform inputs. A1 must drive Q1’s high capacitance gate at high frequency, necessitating high peak A1 output currents and attention to feedback loop compensation. A1, a 60MHz current feedback amplifier, has an output current capacity exceeding 1A. Maintaining stability and waveform fidelity at high frequency while driving Q1’s gate capacitance necessitates settable gate drive peaking components, a damper network, feedback trimming and loop peaking adjustments. A DC trim, also required, is made first. With no input applied, trim the “1mV adjust” for 1mV DC at Q1’s source. The AC trims are made utilizing Figure 2.7’s arrangement. Similar to Figure 2.3, this “brick wall” regulated source provides minimal ripple and sag when step loaded by the load transient generator. Apply the inputs shown and trim the gate drive, feedback and loop peaking adjustments for the cleanest, square cornered response on the oscilloscope’s current probe equipped channel.

Load transient response testing for voltage regulators

CHAPTER 2

Figure 2.6 • Detailed Closed Loop Load Tester. DC Level and Pulse Inputs Feed A1 to Q1 Current Sinking Regulator Load. Q1’s Gain Allows Small A1 Output Swing, Permitting Wide Bandwidth. Damper Network, Feedback and Peaking Trims Optimize Edge Response

Figure 2.7 • Closed Loop Load Tester Response Time is Determined as in Figure 2.3. “Brick Wall” Input Provides Low Impedance Source

Bipolar transistor based circuit Figure 2.8 considerably simplifies the previous circuit’s loop dynamics and eliminates all AC trims. The major trade-off is a 2× speed reduction. The circuit is similar to Figure 2.6, except that Q1 is a bipolar transistor. The bipolar’s greatly reduced input capacitance allows A1 to drive a more benign load. This permits a lower output current amplifier and eliminates the dynamic trims required to accommodate Figure 2.6’s FET gate capacitance. The sole trim is the “1mV adjust” which is accomplished as described before2. Aside from the 2× speed reduction the bipolar transistor also introduces a 1% output current error due to its base current. Q2 is added to prevent Note 2: This trim may be eliminated at some sacrifice in circuit complexity. See Appendix D, “A Trimless Closed Loop Transient Load Tester.”

excessive Q1 base current when the regulator supply is not present. The diode prevents reverse base bias under any circumstances.

Closed loop circuit performance Figures 2.9 and 2.10 show the two wideband circuits’ operation. The FET based circuit (Figure 2.9) only requires a 50mV A1 swing (Trace A) to enforce Trace B’s flat-topped current pulse with 50ns edges through Q1. Figure 2.10 details the bipolar transistor based circuit’s performance. Trace A, taken at Q1’s base, rises less than 100mV causing Trace B’s clean 1A current conduction through Q1. This circuit’s 100ns edges, about 2× slower than the more complex FET based version, are still fast enough for most practical transient load testing. 15

SECTION ONE

Power Management Tutorials

Figure 2.8 • Figure 2.6 Implemented with Bipolar Transistor. Q1’s Reduced Input Capacitance Simplifies Loop Dynamics, Eliminating Compensation Components and Trims. Trade Off is 2× Speed Reduction and Base Current Induced 1% Error

Figure 2.9 • Figure 2.6’s Closed Loop Load Tester Step Response (Q1 Current is Trace B) is Quick and Clean, Showing 50ns Edges and Flat Top. A1’s Output (Trace A) Swings Only 50mV, Allowing Wideband Operation. Trace B’s Presentation is Slightly Delayed Due to Voltage and Current Probe Time Skew

Figure 2.10 • Figure 2.8’s Bipolar Output Load Tester Response is 2× Slower than FET Version, but Circuit is Less Complex and Eliminates Compensation Trims. Trace A is A1’s Output, Trace B is Q1’s Collector Current

Load transient testing

resumes control. In Figure 2.13, a 500mA peak-to-peak 500kHz noise load, emulating a multitude of incoherent loads, feeds the regulator in Trace A. This is within regulator bandwidth and only 6mVP-P of disturbance appears in Trace B, the regulator output. Figure 2.14 maintains the same conditions, except that noise bandwidth is increased to 5MHz. Regulator bandwidth is exceeded, resulting in over 50mVP-P error, an 8× increase. Figure 2.15 shows what happens when a 0.2A DC biased, swept DC-5MHz, 0.35A load is presented to the regulator. The regulator’s rising output impedance versus frequency results in ascending error as frequency scales.

The previously discussed circuits permit rapid and thorough voltage regulator load transient testing. Figure 2.11 uses Figure 2.6’s circuit to evaluate an LT1963A linear regulator. Figure 2.12 shows regulator response (Trace B) to Trace A’s asymmetrically edged input pulse. The ramped leading edge, within the LT1963A’s bandwidth, results in Trace B’s smooth 10mVP-P excursion. The fast trailing edge, well outside LT1963A passband, causes Trace B’s abrupt disruption. COUT cannot supply enough current to maintain output level and a 75mVP-P spike results before the regulator 16

Load transient response testing for voltage regulators

CHAPTER 2

Figure 2.11 • Closed Loop Load Tester Shown with LT1963A Regulator. Load Testing for a Variety of Current Load Waveshapes is Possible

Figure 2.12 • Figure 2.11 Responds (Trace B) to Assymetrically Edged Pulse Input (Trace A). Ramped Leading Edge, Within LT1963A Bandwidth, Results in Trace B’s Smooth 10mVP-P Excursion. Fast Trailing Edge, Outside LT1963A Bandwidth, Causes Trace B’s Abrupt 75mVP-P Disruption. Traces Latter Portion Intensified for Photographic Clarity

Figure 2.14 • Same Conditions as Figure 2.13, Except Noise Bandwidth Increased to 5MHz. Regulator Bandwidth is Exceeded, Resulting in 50mVP-P Output Error

Figure 2.13 • 500mAP-P, 500kHz Noise Load (Trace A), Within Regulator Bandpass, Produces Only 6mV Artifacts at Trace B’s Regulator Output

Figure 2.15 • Swept DC −5MHz, 0.35A Load (On 0.2ADC) Results in Above Regulator Response. Regulator Output Impedance Rises with Frequency, Causing Corresponding Ascending Output Error

17

SECTION ONE

Power Management Tutorials

This information allows determination of regulator output impedance versus frequency.

Capacitor’s role in regulator response The regulator employs capacitors at its input (CIN) and output (COUT) to augment its high frequency response. The capacitor’s dielectric, value and location greatly influence regulator characteristics and must be quite carefully considered.3 COUT dominates the regulator’s dynamic response; CIN is much less critical, so long as it does not discharge below the regulator’s dropout point. Figure 2.16 shows a typical regulator circuit and emphasizes COUT and its parasitics. Parasitic inductance and resistance limit capacitor effectiveness at frequency. The capacitor’s dielectric and value significantly influence load step response. A “hidden” parasitic, impedance build-up in regulator output trace runs, also influences regulation characteristics, although its effects can be minimized by remote sensing (shown) and distributed capacitive bypassing.

Figure 2.16 • COUT Dominates Regulator’s Dynamic Response; CIN is Much Less Critical. Parasitic Inductance and Resistance Limit Capacitor Effectiveness at Frequency. Capacitor Value and Dielectric Significantly Influence Load Step Response. Excessive Trace Impedance is Also a Factor

Figure 2.17 • Stepped 0.5A Load to Figure 2.16’s Circuit (Trace A) with CIN = COUT = 10μF Results in Trace B’s Regulator Output. Low Loss Capacitors Promote Controlled Output Excursions Note 3: See Appendices A and B for extended discussion of these concerns.

18

Figure 2.17 shows Figure 2.16’s circuit responding (Trace B) to a 0.5A load step biased on 0.1A DC (Trace A) with CIN = COUT=10μF. The low loss capacitors employed result in Trace B’s well controlled output. Figure 2.18 greatly expands the horizontal time scale to investigate high frequency behavior. Regulator output deviation (Trace B) is smooth, with no abrupt discontinuities. Figure 2.19 runs the same test as Figure 2.17 using an output capacitor

Figure 2.18 • Expanding Horizontal Scale Shows Trace B’s Smooth Regulator Output Response. Mismatched Current and Voltage Probe Delays Account for Slight Time Skewing

Figure 2.19 • “Equivalent” 10μF COUT Capacitor’s Performance Appears Similar to Figure 2.17’s Type at 10μs/DIV

Figure 2.20 • Horizontal Scale Expansion Reveals “Equivalent” Capacitor Produces 2× Amplitude Error vs Figure 2.18. Mismatched Probe Delays Cause Time Skewing Between Traces

Load transient response testing for voltage regulators

claimed as “equivalent” to the one employed in Figure 2.17. At 10μs/division things seem very similar, but Figure 2.20 indicates problems. This photo, taken at the same higher sweep speed as Figure 2.18, reveals the “equivalent” capacitor to have a 2× amplitude error versus Figure 2.18, higher frequency content and resonances.4 Figure 2.21 substitutes a very lossy 10μF unit for COUT. This capacitor allows a 400mV excursion (note Trace B’s vertical scale change), >4× Figure 2.18’s amount. Conversely, Figure 2.22 increases COUT to a low loss 33μF type, decreasing Trace B’s output response transient by 40% versus Figure 2.18. Figure 2.23’s further increase, to a low loss 330μF capacitor, keeps transients inside 20mV; 4× lower than Figure 2.18’s 10μF value.

CHAPTER 2

The lesson from the preceding study is clear. Capacitor value and dielectric quality have a pronounced effect on transient load response. Try before specifying!

Load transient risetime versus regulator response The closed loop load transient generator also allows investigating load transient risetime on regulation at high speed. ­Figure 2.24 shows Figure 2.16’s circuit (CIN = COUT = 10μF) responding to a 0.5A, 100ns risetime step on a 0.1A DC load (Trace A). Response decay (Trace B) peaks at 75mV with some following aberrations. Decreasing Trace A’s load step risetime (Figure 2.25) almost doubles Trace B’s response error, with attendant enlarged following aberrations. This indicates increased regulator error at higher frequency. All regulators present increasing error with frequency, some more so than others. A slow load transient can unfairly make a poor regulator look good. Transient load testing that does not indicate some response outside regulator bandwidth is suspect.

Figure 2.21 • Excessively Lossy 10μF COUT Allows 400mV Excursion −4× Figure 2.18’s Amount. Time Skewing Between Traces Derives from Probe Mismatch

Figure 2.22 • Increasing COUT with Low Loss 33μF Unit Reduces Output Response Transient by 40% Over Figure 2.17

Figure 2.23 • Low Loss 330μF Capacitor Keeps Output Response Transients Inside 20mV −4× Lower than Figure 2.17’s 10μF Note 4: Always specifiy components according to observed performance, never to salesman’s claims.

Figure 2.24 • Regulator Output Response (Trace B) to 100ns. Risetime Current Step (Trace A) for COUT = 10μF. Response Decay Peaks at 75mV

Figure 2.25 • Faster Risetime Current Step (Trace A) Increases Response Decay Peak (Trace B) to 140mV, Indicating Increased Regulation Loss vs Frequency

19

SECTION ONE

Power Management Tutorials

A practical example – Intel P30 embedded memory voltage regulator A good example of the importance of voltage regulator load step performance is furnished by the Intel P30 embedded memory. This memory requires a 1.8V supply, typically regulated down from +3V. Although current requirements are relatively modest, supply tolerances are tight. Figure 2.26’s error budget shows only 0.1V allowable excursion from 1.8V, including all DC and dynamic errors. The LTC1844-1.8 regulator has a 1.75% initial tolerance (31.5mV), leaving only a 68.5mV dynamic error allowance. Figure 2.27 is the test circuit. Memory control line movement causes 50mA load transients, necessitating attention to capacitor selection.5 If the regulator is close to the power source CIN is optional. If not, use a good grade 1μF capacitor for CIN. COUT is a low loss 1μF type. In all other respects the circuit appears deceptively routine. A load transient generator provides Figure 2.28’s output load test step (Trace A).6 Trace B’s regulator response shows just 30mV peaks, >2× better than required. Increasing COUT to 10μF, in Figure 2.29, reduces

peak output error to 12mV, almost 6× better than specification. However, a poor grade 10μF (or 1μF, for that matter) capacitor produces Figure 2.30’s unwelcome surprise. Severe peaking error on both edges occurs (Trace B’s latter portion has been intensified to aid photograph clarity) with 100mV observable on the negative going edge. This is well outside the error budget and would cause unreliable memory operation.

Figure 2.28 • 50mA Load Step (Trace A) Results in 30mV Regulator Response Peaks, 2× Better than Error Budget Requirements. COUT = Low Loss 1μF

Figure 2.26 • Error Budget for Intel P30 Embedded Memory Voltage Regulator. 1.8V Supply Must Remain Within ±0.1V Tolerance, Including All Static and Dynamic Errors Figure 2.29 • Increasing COUT to 10μF Decreases Regulator Output Peaks to 12mV, Almost 6× Better than Required

Figure 2.27 • P30 Embedded Memory VCC Regulator Must Maintain ±0.1V Error Band. Control Line Movement Causes 50mA Load Steps, Necessitating Attention to COUT Selection

Note 5: The LTC1844-1.8’s noise bypass pin (“BYP”) is used with an optional external capacitor to achieve extremely low output noise. It is not required for this application and is left unconnected. Note 6: Figure 2.8’s circuit was used for this test, with Q1’s emitter current shunt changed to 1Ω. Note. This application note was derived from a manuscript originally prepared for publication in EDN magazine.

20

Figure 2.30 • Poor Grade 10μF COUT Causes 100mV Regulator Output Peaks (Trace B), Violating P30 Memory Limits. Traces Latter Portion Intensified for Photographic Clarity

Load transient response testing for voltage regulators

CHAPTER 2

References 1. LT1584/LT1585/LT1587 Fast Response Regulators Datasheet. Linear Technology Corporation 2. LT1963A Regulator Datasheet. Linear Technology Corporation

3. Williams, Jim, “Minimizing Switching Residue in Linear Regulator Outputs”. Linear Technology Corporation, Application Note 101, July 2005

Appendix A Capacitor parasitic effects on load transient response Tony Bonte Large load current changes are typical of digital systems. The load current step contains higher order frequency components that the output decoupling network must handle until the regulator throttles to the load current level. Capacitors are not ideal elements and contain parasitic resistance and inductance. These parasitic elements dominate the change in output voltage at the beginning of a transient load step change. The ESR (equivalent series resistance) of the output capacitors produces an instantaneous step in output voltage.(ΔV = ΔI • ESR). The ESL (equivalent series inductance) of the output capacitors produces a droop proportional to the rate of change of output current (V = L • ΔI/Δt). The output capacitance produces a change in output voltage

4. Shakespeare, William, “The Taming of the Shrew,” 1593-94

proportional to the time until the regulator can respond (ΔV=Δt • ΔI/C). These transient effects are illustrated in Figure A1. The use of capacitors with low ESR, low ESL, and good high frequency characteristics is critical in meeting the output load voltage tolerances. These requirements dictate high quality, surface mount tantalum, ceramic or organic electrolyte capacitors. The capacitor’s location is critical to transient response performance. Place the capacitor as close as possible to the regulator pins and keep supply line traces and planes at low impedance, bypassing individual loads as necessary. if the regulator has remote sensing capability, consider sensing at the heaviest load point. Strictly speaking, the above are not the only time related terms that can influence regulator settling. Figure A2 lists 7 different terms, occurring over 9 decades of time, that can potentially influence regulation. The regulator IC must be carefully designed to minimize regulator loop and thermal error contributions.

Figure A1 • Parasitic Resistance, Inductance and Finite Capacitance Combine with Regulator Gain-Bandwidth Limitations to Form Load Step Response. Capacitors Equivalent Series Resistance (ESR) and Inductance (ESL) Dominate Initial Response; Capacitor Value and Regulator Gain-Bandwidth Determine Responses Latter Profile

Figure A2 • Time Constants Potentially Influencing Regulator Settling Time After a Load Step are Electrical and Thermal. Effects Span Over 9 Decades

21

SECTION ONE

Power Management Tutorials

Appendix B Output capacitors and loop stability Dennis O’Neill Editorial Note: The following text, excerpted from the LT1963A datasheet, concerns the output capacitor’s relationship to transient response. Although originally prepared for LT1963A application, it is generalizable to most regulators and is presented here for reader convenience. A voltage regulator is a feedback circuit. Like any feedback circuit, frequency compensation is needed to make it stable. For the LT1963A, the frequency compensation is both internal and external – the output capacitor. The size of the output capacitor, the type of the output capacitor, and the ESR of the particular output capacitor all affect the stability. In addition to stability, the output capacitor also affects the high frequency transient response. The regulator loop has finite bandwidth. For high frequency transient loads recovery from a transient is a combination of the output capacitor and the bandwidth of the regulator. The LT1963A was designed to be easy to use and accept a wide variety of output capacitors. However, the frequency compensation is affected by the output capacitor and optimum frequency stability may require some ESR, especially with ceramic capacitors. For ease of use, low ESR polytantalum capacitors (POSCAP) are a good choice for both the transient response and stability of the regulator. These capacitors have intrinsic ESR that improves the stability. Ceramic capacitors have extremely low ESR, and while they are a good choice in many cases, placing a small series resistance element will sometimes achieve optimum stability and minimize ringing. In all cases, a minimum of 10μF is required while the maximum ESR allowable is 3Ω. The place where ESR is most helpful with ceramics is low output voltage. At low output voltages, below 2.5V, some ESR helps the stability when ceramic output capacitors are used. Also, some ESR allows a smaller capacitor value to be used. When small signal ringing occurs with ceramics due to insufficient ESR, adding ESR or increasing the capacitor value improves the stability and reduces the ringing. Figure B1 gives some recommended values of ESR to minimize ringing caused by fast, hard current transitions.

22

Figure B1 • Capacitor Minimum ESR

Figures B2 through B7 show the effect of ESR on the transient response of the regulator. These scope photos show the transient response for the LT1963A at three different output voltages with various capacitors and various values of ESR. The output load conditions are the same for all traces. In all cases there is a DC load of 500mA. The load steps up to 1A at the first transition and steps back to 500mA at the second transition. At the worst case point of 1.2VOUT with 10μF COUT (Figure B2), a minimum amount of ESR is required. While 20mΩ is enough to eliminate most of the ringing, a value closer to 50mΩ provides a more optimum response. At 2.5V output with 10μF COUT (Figure B3) the output rings at the transitions with 0Ω ESR but still settles to within 10mV in 20μs after the 0.5A load step. Once again a small value of ESR will provide a more optimum response. At 5VOUT with 10μF COUT (Figure B4) the response is well damped with 0Ω ESR. With a COUT of 100μF at 0Ω ESR and an output of 1.2V (Figure B5), the output rings although the amplitude is only 20mVP-P. With COUT of 100μF it takes only 5mΩ to 20mΩ of ESR to provide good damping at 1.2V output. Performance at 2.5V and 5V output with 100μF COUT shows similar characteristics to the 10μF case (see Figures B6 and B7). At 2.5VOUT 5mΩ to 20mΩ can improve transient response. At 5VOUT the response is well damped with 0Ω ESR. Capacitor types with inherently higher ESR can be combined with 0mΩ ESR ceramic capacitors to achieve both good high frequency bypassing and fast settling time. Figure B8 illustrates the improvement in transient response that can be seen when a parallel combination of ceramic and POSCAP capacitors are used. The

Load transient response testing for voltage regulators

CHAPTER 2

Figure B3

Figure B2

Figure B4

Figure B5

Figure B6

Figure B7

Figure B8

23

SECTION ONE

Power Management Tutorials

output voltage is at the worst case value of 1.2V. Trace A with a 10μF ceramic output capacitor, shows significant ringing with a peak amplitude of 25mV. For Trace B, a 22μF/45mΩ POSCAP is added in parallel with the 10μF ceramic. The output is well damped and settles to within 10mV in less than 20μs. For Trace C, a 100μF/35mΩ POSCAP is connected in parallel with the 10μF ceramic capacitor. In this case the peak output deviation is less than 20mV and the output settles in about 10μs. For improved transient response the value of the bulk capacitor (tantalum or aluminum electrolytic) should be greater than twice the value of the ceramic capacitor.

When used with a 5V regulator, a 10μF Y5V capacitor can exhibit an effective value as low as 1μF to 2μF over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress,

Tantalum and polytantalum capacitors There is a variety of tantalum capacitor types available, with a wide range of ESR specifications. Older types have ESR specifications in the hundreds of mΩ to several Ohms. Some newer types of polytantalum with multi-electrodes have maximum ESR specifications as low as 5mΩ. In general the lower the ESR specification, the larger the size and the higher the price. Polytantalum capacitors have better surge capability than older types and generally lower ESR. Some types such as the Sanyo TPE and TPB series have ESR specifications in the 20mΩ to 50mΩ range, which provide near optimum transient response.

Aluminum electrolytic capacitors Aluminum electrolytic capacitors can also be used with the LT1963A. These capacitors can also be used in conjunction with ceramic capacitors. These tend to be the cheapest and lowest performance type of capacitors. Care must be used in selecting these capacitors as some types can have ESR which can easily exceed the 3Ω maximum value.

Figure B9 • Ceramic Capacitor DC Bias Characteristics

Ceramic capacitors Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. The most common dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and temperature coefficients as shown in Figures B9 and B10.

Figure B10 • Ceramic Capacitor Temperature Characteristics

24

Load transient response testing for voltage regulators

similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients.

“Free” resistance with PC traces The resistance values shown in Figure B11 can easily be made using a small section of PC trace in series with the output capacitor. The wide range of non-critical ESR makes it easy to use PC trace. The trace width should be sized to handle the RMS ripple current associated with the load. The output capacitor only sources or sinks current for a few microseconds during fast output current transitions. There is no DC current in the output

CHAPTER 2

capacitor. Worst case ripple current will occur if the output load is a high frequency (>100kHz) square wave with a high peak value and fast edges (125°C

•

85

125

kHz

Switching Frequency Line Regulation

8V ≤ VIN ≤ VMAX (Note 7)

Error Amplifier Voltage Gain (Note 6)

1V ≤ VC ≤ 4V

20

•

0.03

kHz 0.1

2000

Error Amplifier Transconductance

%/V V/V

3700

5000

8000

µmho

Source (VFB = 2V)

100

140

225

µA

Sink (VFB = 2.5V)

0.7

1

1.6

mA

0.5

2

µA

2.21

2.265

V

±0.5

±1.5

%

Feedback Pin Bias Current

VFB = VREF

•

Reference Voltage

VC = 2V

•

Reference Voltage Tolerance

VREF (Nominal) = 2.21V

2.155

All Conditions of Input Voltage, Output Voltage,Temperature and Load Current

•

±1

±2.5

%

8V ≤ VIN ≤ VMAX (Note 7)

•

0.005

0.02

%/V

VC Voltage at 0% Duty Cycle Over Temperature

•

Multiplier Reference Voltage

Shutdown Thresholds

110

TJ ≤ 125°C VFB = 0V Through 2kΩ (Note 4)

Shutdown Pin Current

A

  RLIM = 10k (Note 5)

Switching Frequency

Reference Voltage Line Regulation

3.2

   

Maximum Duty Cycle

Error Amplifier Source and Sink Current

2.6

VSH = 5V

•

VSH ≤ VTHRESHOLD (≅2.5V)

•

Switch Duty Cycle = 0

•

2.2

Fully Shut Down

•

Status Window

As a Percent of Feedback Voltage

Status High Level

ISTATUS = 10µA Sourcing

•

Status Low Level

ISTATUS = 1.6mA Sinking

•

5

1.5

V

-4

mV/°C

24

V

10

20

µA

50

µA

2.45

2.7

V

0.1

0.3

0.5

V

4

±5

6

%

3.5

4.5

5.0

V

0.25

0.4

V

Status Delay Time

9

µs

Status Minimum Width

30

µs

Thermal Resistance Junction to Case

LT1074

2.5

°C/W

LT1076

4.0

°C/W

91

SECTION TWO

Switching Regulator Design

The • denotes the specifications which apply over the full operating temperature range. Note 1: To calculate maximum switch on voltage at currents between low and high conditions, a linear interpolation may be used. Note 2: A feedback pin voltage (VFB) of 2.5V forces the VC pin to its low clamp level and the switch duty cycle to zero. This approximates the zero load condition where duty cycle approaches zero. Note 3: Total voltage from VIN pin to ground pin must be ≥8V after startup for proper regulation. Note 4: Switch frequency is internally scaled down when the feedback pin voltage is less than 1.3V to avoid extremely short switch on times. During testing, VFB is adjusted to give a minimum switch on time of 1μs. RLIM −1k R −1k Note 5: ILIM ≈ LIM2k (LT1047), ILIM ≈ 5.5k (LT1076) Note 6: Switch to input voltage limitation must also be observed. Note 7: VMAX = 40V for the LT1074/76 and 60V for the LT1074HV/76HV. Note 8: Does not include switch leakage.

Block Diagram

92

Theoretical considerations for buck mode switching regulators

Block diagram description A switch cycle in the LT1074 is initiated by the oscillator setting the R/S latch. The pulse that sets the latch also locks out the switch via gate G1. The effective width of this pulse is approximately 700ns, which sets the maximum switch duty cycle to approximately 93% at 100kHz switching frequency. The switch is turned off by comparator C1, which resets the latch. C1 has a sawtooth waveform as one input and the output of an analog multiplier as the other input. The multiplier output is the product of an internal reference voltage, and the output of the error amplifier, A1, divided by the regulator input voltage. In standard buck regulators, this means that the output voltage of A1 required to keep a constant regulated output is independent of regulator input voltage. This greatly improves line transient response, and makes loop gain independent of input voltage. The error amplifier is a transconductance type with a GM at null of approximately 5000μmho. Slew current going positive is 140μA, while negative slew current is about 1.1mA. This asymmetry helps prevent overshoot on startup. Overall loop frequency compensation is accomplished with a series RC network from VC to ground. Switch current is continuously monitored by C2, which resets the R/S latch to turn the switch off if an overcurrent condition occurs. The time required for detection and switch turn-off is approximately 600ns. So minimum switch on time in current limit is 600ns. Under dead shorted output conditions, switch duty cycle may have to be as low as 2% to maintain control of output current. This

CHAPTER 5

would require switch on time of 200ns at 100kHz switching frequency, so frequency is reduced at very low output voltages by feeding the FB signal into the oscillator and creating a linear frequency downshift when the FB signal drops below 1.3V. Current trip level is set by the voltage on the ILIM pin which is driven by an internal 320µA current source. When this pin is left open, it selfclamps at about 4.5V and sets current limit at 6.5A for the LT1074 and 2.6A for the LT1076. In the 7-pin package an external resistor can be connected from the ILIM pin to ground to set a lower current limit. A capacitor in parallel with this resistor will soft-start the current limit. A slight offset in C2 guarantees that when the ILIM pin is pulled to within 200mV of ground, C2 output will stay high and force switch duty cycle to zero. The shutdown pin is used to force switch duty cycle to zero by pulling the ILIM pin low, or to completely shut down the regulator. Threshold for the former is approximately 2.35V, and for complete shutdown, approximately 0.3V. Total supply current in shutdown is about 150μA. A 10μA pull-up current forces the shutdown pin high when left open. A capacitor can be used to generate delayed startup. A resistor divider will program “undervoltage lockout” if the divider voltage is set at 2.35V when the input is at the desired trip point. The switch used in the LT1074 is a Darlington NPN (single NPN for LT1076) driven by a saturated PNP. Special patented circuitry is used to drive the PNP on and off very quickly even from the saturation state. This particular switch arrangement has no “isolation tubs” connected to the switch output, which can therefore swing to 40V below ground.

93

SECTION TWO

Switching Regulator Design

Typical performance characteristics

94

Theoretical considerations for buck mode switching regulators

CHAPTER 5

Typical performance characteristics

95

SECTION TWO

Switching Regulator Design

Typical performance characteristics

96

Theoretical considerations for buck mode switching regulators

Pin descriptions VIN pin The VIN pin is both the supply voltage for internal control circuitry and one end of the high current switch. It is important, especially at low input voltages, that this pin be bypassed with a low ESR, and low inductance capacitor to prevent transient steps or spikes from causing erratic operation. At full switch current of 5A, the switching transients at the regulator input can get very large as shown in Figure 5.1. Place the input capacitor very close to the regulator and connect it with wide traces to avoid extra inductance. Use radial lead capacitors.

CHAPTER 5

To ensure good load regulation, the ground pin must be connected directly to the proper output node, so that no high currents flow in this path. The output divider resistor should also be connected to this low current connection line as shown in Figure 5.2.

Figure 5.2 • Proper Ground Pin Connection

Figure 5.1 • Input Capacitor Ripple

LP = Total inductance in input bypass connections and   capacitor. dl “Spike” height is dt • LP approximately 2V per inch of lead length. Step = 0.25V for ESR = 0.05Ω and ISW = 5A is 0.25V. Ramp = 125mV for C = 200μF, tON = 5μs, and ISW = 5A is 125mV. Input current on the VIN Pin in shutdown mode is the sum of actual supply current (≈140μA, with a maximum of 300μA) and switch leakage current. Consult factory for special testing if shutdown mode input current is critical.

Ground pin It might seem unusual to describe a ground pin, but in the case of regulators, the ground pin must be connected properly to ensure good load regulation. The internal reference voltage is referenced to the ground pin; so any error in ground pin voltage will be multiplied at the output; �VOUT =

(�VGND ) (VOUT ) 2. 21

Feedback pin The feedback pin is the inverting input of an error amplifier which controls the regulator output by adjusting duty cycle. The noninverting input is internally connected to a trimmed 2.21V reference. Input bias current is typically 0.5μA when the error amplifier is balanced (IOUT = 0). The error amplifier has asymmetrical GM for large input signals to reduce start-up overshoot. This makes the amplifier more sensitive to large ripple voltages at the feedback pin. 100mVP-P ripple at the feedback pin will create a 14mV offset in the amplifier, equivalent to a 0.7% output voltage shift. To avoid output errors, output ripple (P-P) should be less than 4% of DC output voltage at the point where the output divider is connected. See the Error Amplifier section for more details.

Frequency shifting at the feedback pin The error amplifier feedback pin (FB) is used to downshift the oscillator frequency when the regulator output voltage is low. This is done to guarantee that output short-circuit

97

Switching Regulator Design

SECTION TWO

current is well controlled even when switch duty cycle must be extremely low. Theoretical switch on time for a buck converter in continuous mode is;

tON

will be subjected to the simultaneous conditions of high input voltage and output short circuit.

Shutdown pin

VOUT + VD = VIN • f

VD = Catch diode forward voltage (≈0.5V) f = Switching frequency At f = 100kHz, tON must drop to 0.2μs when VIN = 25V and the output is shorted (VOUT = 0V). In current limit, the LT1074 can reduce tON to a minimum value of ≈0.6μs, much too long to control current correctly for VOUT = 0. To correct this problem, switching frequency is lowered from 100kHz to 20kHz as the FB pin drops from 1.3V to 0.5V. This is accomplished by the circuitry shown in Figure 5.3. Q1 is off when the output is regulating (VFB = 2.21V). As the output is pulled down by an overload, VFB will eventually reach 1.3V, turning on Q1. As the output continues to drop, Q1 current increases proportionately and lowers the frequency of the oscillator. Frequency shifting starts when the output is ≈60% of normal value, and is down to its minimum value of ≅20kHz when the output is ≅20% of normal value. The rate at which frequency is shifted is determined by both the internal 3k resistor R3 and the external divider resistors. For this reason, R2 should not be increased to more than 4k, if the LT1074

The shutdown pin is used for undervoltage lockout, micropower shutdown, soft-start, delayed start, or as a general purpose on/off control of the regulator output. It controls switching action by pulling the ILIM pin low, which forces the switch to a continuous off state. Full micropower shutdown is initiated when the shutdown pin drops below 0.3V. The V/I characteristics of the shutdown pin are shown in Figure 5.4. For voltages between 2.5V and ≈VIN, a current of 10µA flows out of the shutdown pin. This current increases to ≈25μA as the shutdown pin moves through the 2.35V threshold. The current increases further to ≈30μA at the 0.3V threshold, then drops to ≈15μA as the shutdown voltage falls below 0.3V. The 10μA current source is included to pull the shutdown pin to its high or default state when left open. It also provides a convenient pull-up for delayed start applications with a capacitor on the shutdown pin. When activated, the typical collector current of Q1 in Figure 5.5, is ≈2mA. A soft-start capacitor on the ILIM pin will delay regulator shutdown in response to C1, by ≈(5V) (CLIM)/2mA. Soft-start after full micropower shutdown is ensured by coupling C2 to Q1.

Figure 5.3 • Frequency Shifting

98

Theoretical considerations for buck mode switching regulators

CHAPTER 5

Figure 5.4 • Shutdown Pin Characteristics Figure 5.5 • Shutdown Circuitry

Undervoltage lockout Undervoltage lockout point is set by R1 and R2 in Figure 5.6. To avoid errors due to the 10μA shutdown pin current, R2 is usually set at 5k, and R1 is found from: R1 = R2

Figure 5.6 • Undervoltage Lockout

(VTP − VSH ) VSH

VTP = Desired undervoltage lockout voltage. VSH = Threshold for lockout on the shutdown pin=2.45V. If quiescent supply current is critical, R2 may be increased up to 15k, but the denominator in the formula for R2 should replace VSH with VSH – (10μA)(R2). Hysteresis in undervoltage lockout may be accomplished by connecting a resistor (R3) from the ILIM pin to the shutdown pin as shown in Figure 5.7. D1 prevents the shutdown divider from altering current limit.

Figure 5.7 • Adding Hysteresis

99

Switching Regulator Design

SECTION TWO

  R1 Trip Point = VTP = 2. 35V 1 + R2

If R3 is added, the lower trip point (VIN descending) will be the same. The upper trip point (VUTP) will be:     R1 R1 R1 VUTP = VSH 1 + − 0. 8V + R2 R3 R3

If R1 and R2 are chosen, R3 is given by: R3 =

(VSH − 0. 8V)(R1)   VUTP − VSH 1 + R1 R2

saturated NPN with ≈100Ω resistance and a maximum sink current of approximately 5mA. An external pull-up resistor can be added to increase output swing up to a maximum of 20V. When the status pin is used to indicate “output OK,” it becomes important to test for conditions which might create unwanted status states. These include output overshoot, large-signal transient conditions, and excessive output ripple. “False” tripping of the status pin can usually be controlled by a pulse stretcher network as shown in Figure 5.8. A single capacitor (C1) will suffice to delay an output “OK” (status high) signal to avoid false “true” signals during start-up, etc. Delay time for status high will be approximately (2.3 × 104) (C1), or 23ms/µF. Status low delay will be much shorter, ≈600µs/µF.

Example: An undervoltage lockout is required such that the output will not start until VIN = 20V, but will continue to operate until VIN drops to 15V. Let R2 = 2.32k. R1 = (2. 32k)

R3 =

15V − 2. 35V = 12. 5k 2. 35V

(2. 35 − 0. 8)(12. 5)  = 3. 9K  20 − 2. 35 1 + 12.5 2.32

Status pin (available only on LT1176 parts) The status pin is the output of a voltage monitor “looking” at the feedback pin. It is low for a feedback voltage which is more than 5% above or below nominal. “Nominal” in this case means the internal reference voltage, so that the ±5% window tracks the reference voltage. A time delay of ≈10μs prevents short spikes from tripping the status low. Once it does go low, a second timer forces it to stay low for a minimum of ≈30µs. The status pin is modeled in Figure 5.8 with a 130μA pull up to a 4.5V clamp level. The sinking drive is a

100

Figure 5.8 • Adding Time Delays to Status Output

Theoretical considerations for buck mode switching regulators

If false tripping of status low could be a problem, R1 can be added. Delay of status high remains the same if R1 ≤ 10k. Status low delay is extended by R1 to approximately R1 • C2 seconds. Select C2 for high delay and R1 for low delay. Example: Delay status high for 10ms, and status low for 3ms: 10ms C2 = = 0. 47µF(Use 0. 47µF) 23ms/µF R1 =

CHAPTER 5

As an example, a 3A current limit would require 3A (2k) + 1k = 7k for the LT1074. The accuracy of these formulas is ±25% for 2A ≤ ILIM ≤ 5A (LT1074) and 0.7A ≤ ILIM ≤ 1.8A (LT1076), so ILIM should be set at least 25% above the peak switch current required.

3ms 3ms = = 6. 4k C2 0. 47µF

In this example D1 is not needed because R1 is small enough to not limit the charging of C2. If very fast low tripping combined with long high delays is desired, use the D2, R2, R3, C3 configuration. C3 is chosen first to set low delay: C3 ≈

tLOW 2k

R3 is then selected for high delay: R3 ≈

Figure 5.9 • ILIM Pin Current

tHIGH C3

For tLOW = 100μs and tHIGH = 10ms, C3 = 0.05μF and R3 = 200k.

ILIM pin

Foldback current limiting can be easily implemented by adding a resistor from the output to the ILIM pin as shown in Figure 5.10. This allows full desired current limit (with or without RLIM) when the output is regulating, but reduces current limit under short-circuit conditions. A typical value

The ILIM pin is used to reduce current limit below the preset value of 6.5A. The equivalent circuit for this pin is shown in Figure 5.9. When ILIM is left open, the voltage at Q1 base clamps at 5V through D2. Internal current limit is determined by the current through Q1. If an external resistor is connected between ILIM and ground, the voltage at Q1 base can be reduced for lower current limit. The resistor will have a voltage across it equal to (320μA) (R), limited to ≈5V when clamped by D2. Resistance required for a given current limit is: R LIM = I LIM (2k�) + 1k� (LT1074) R LIM = I LIM (5. 5k�) + 1k� (LT1076)

Figure 5.10 • Foldback Current Limit

101

Switching Regulator Design

SECTION TWO

for RFB is 5k, but this may be adjusted up or down to set the amount of foldback. D2 prevents the output voltage from forcing current back into the ILIM pin. To calculate a value for RFB, first calculate RLIM, then RFB:   I SC − 0. 44∗ (R L )   R FB = = R L in k� 0. 5∗ R L − 1k� − I SC *Change

0.44 to 0.16, and 0.5 to 0.18 for LT1076. Example: ILIM = 4A, ISC = 1.5A, RLIM = (4)(2k) + 1k = 9k: R FB =

(1. 5 − 0. 44)(9k�) = 3. 8k� 0. 5(9k − 1k) − 1. 5

Error amplifier The error amplifier in Figure 5.11 is a single stage design with added inverters to allow the output to swing above and below the common mode input voltage. One side of the amplifier is tied to a trimmed internal reference voltage of 2.21V. The other input is brought out as the FB (feedback) pin. This amplifier has a GM (voltage in to current out) transfer function of ≈5000μmho. Voltage gain is determined by multiplying GM times the total equivalent output loading, consisting of the output resistance of Q4 and Q6 in parallel with the series RC external frequency compensation network. At DC, the external RC is ignored, and with a parallel output impedance for Q4 and Q6 of 400kΩ, voltage gain is ≈2000. At frequencies above a few hertz, voltage gain is determined by the external compensation, RC and CC.

is specified much tighter on the data sheet. The higher frequency “zero” is determined solely by RC and CC: fZERO =

1 π 2 •R C • C C

The error amplifier has asymmetrical peak output current. Q3 and Q4 current mirrors are unity gain, but the Q6 mirror has a gain of 1.8 at output null and a gain of 8 when the FB pin is high (Q1 current = 0). This results in a maximum positive output current of 140μA and a maximum negative (sink) output current of ≅1.1mA. The asymmetry is deliberate—it results in much less regulator output overshoot during rapid start-up or following the release of an output overload. Amplifier offset is kept low by area scaling Q1 and Q2 at 1.8:1. Amplifier swing is limited by the internal 5.8V supply for positive outputs and by D1 and D2 when the output goes low. Low clamp voltage is approximately one diode drop (−0.7V – 2mV/°C). Note that both the FB pin and the VC pin have other internal connections. Refer to the frequency shifting and synchronizing discussions.

Gm at midfrequencies 2π • f • C C AV = Gm • R C at high frequencies AV =

Phase shift from the FB pin to the VC pin is 90° at midfrequencies where the external CC is controlling gain, then drops back to 0° (actually 180° since FB is an inverting input) when the reactance of CC is small compared to RC. The low frequency “pole” where the reactance of CC is equal to the output impedance of Q4 and Q6 (r0), is: fPOLE =

1 r0 ≈ 400k 2 π •r0 • C

Although fPOLE varies as much as 3:1 due to r0 variations, mid-frequency gain is dependent only on GM, which

102

Figure 5.11 • Error Amplifier

Theoretical considerations for buck mode switching regulators

Definition of terms VIN: DC input voltage. VIN': DC input voltage minus switch voltage loss. VIN' is 1.5V to 2.3V less than VIN, depending on switch current. VOUT: DC output voltage. VOUT': DC output voltage plus catch diode forward voltage. VOUT' is typically 0.4V to 0.6V more than VOUT. f: Switching frequency. Im: Maximum specified switch current IM = 5.5A for the LT1074 and 2A for the LT1076. ISW: Switch current during switch on time. The current typically jumps to a starting value, then ramps higher. ISW is the average value during this period unless otherwise stated. It is not averaged over the whole switching period, which includes switch off time. IOUT: DC output current. ILIM: DC output current limit. IDP: Catch diode forward current. This is the peak current for discontinuous operation and the average value of the current pulse during switch off time for continuous mode. IDA: Catch diode forward current averaged over one complete switching cycle. Ida is used to calculate diode heating. I: Peak-to-peak ripple current in the inductor, also equal to peak current in the discontinuous mode. I is used to calculate output ripple voltage and inductor core losses. VP-P: Peak-to-peak output voltage ripple. This does not include “spikes” created by fast rising currents and capacitor parasitic inductance.

CHAPTER 5

tSW: This is not really an actual rise or fall time. Instead, it represents the effective overlap time of voltage and current in the switch. tSW is used to calculate switch power ­dissipation. L: Inductance, usually measured with low AC flux density, and zero DC current. Note that large AC flux density can increase L by up to 30%, and large DC currents can decrease L dramatically (core saturation). BAC: Peak AC flux density in the inductor core, equal to one-half peak-to-peak AC flux density. Peak value is used because nearly all core loss curves are plotted with peak flux density. N: Tapped-inductor or transformer turns ratio. Note the exact definition of N for each application. µ: Effective permeability of core material used in the inductor. µ is typically 25-150. Ferrite material is much higher, but is usually gapped to reduce the effective value to this range. Ve: Effective core material volume (cm3). Le: Effective core magnetic path length (cm). Ae: Effective core cross sectional area (cm2). Aw: Effective core or bobbin winding area. Lt: Average length of one turn on winding. PCU: Power dissipation caused by winding resistance. It does not include skin effect. PC: Power loss in the magnetic core. PC depends only on ripple current in the inductor not DC current. E: Overall regulator efficiency. It is simply output power divided by input power.

103

SECTION TWO

Switching Regulator Design

Positive step-down (buck) converter The circuit in Figure 5.12 is used to convert a larger ­positive input voltage to a lower positive output. Typical waveforms are shown in Figure 5.13, with VIN = 20V, VOUT = 5V, L = 50μH, for both continuous mode (inductor current never drops to zero) with IOUT = 3A and discontinuous mode, where inductor current drops to zero during a portion of the switching cycle (IOUT = 0.17A). Continuous mode maximizes output power but requires larger inductors. Maximum output current in true discontinuous mode is only one-half of switch current rating. Note that when load current is reduced in a continuous mode design, eventually the circuit will enter discontinuous mode. The LT1074 operates equally well in either mode and there is no significant change in performance when load current reduction causes a shift to discontinuous mode.

Note that duty cycle does not vary with load current except to the extent that Vf and VSW change slightly. A buck converter will change from continuous to discontinuous mode (and duty cycle will begin to drop) at a load current equal to:

I OUT(CRIT) =

(V′OUT )(V′IN − V′OUT ) 2 • V′IN • f • L

(2)

With the possible exception of load transient response, there is no reason to increase L to ensure continuous mode operation at light load. Using the values from Figure 5.12, with VIN = 25V, Vf = 0.5V, VSW = 2V

DC’ =

5 + 0. 5 = 24% 25 − 2

(3)

(5. 5)(23 − 5. 5) = 0. 42A 2(23)(105 )(50 • 10−6 ) The “ringing” which occurs at some point in the switch off cycle in discontinuous mode is simply the resonance created by the catch diode capacitance plus switch capacitance in parallel with the inductor. This ringing does no harm and any attempt to dampen it simply wastes efficiency. Ringing frequency is given by: I OUT(CRIT) =

fRING =

Figure 5.12 • Basic Positive Buck Converter

Duty cycle of a buck converter in continuous mode is:

DC =

′ V VOUT + Vf = OUT VIN − VSW VIN′

Vf = Forward voltage of catch diode VSW = Voltage loss across on switch

104

(1)

1  π 2 L • (C SW + C DIODE

(4)

CSW ≈ 80pF CDIODE = 200pF to 1000pF No off-state ringing occurs in continuous mode because the diode is always conducting during switch off time and effectively shorts the resonance. A detailed look at the leading edge of the switch waveform may reveal a second “ringing” tendency, usually at frequencies around 20MHz to 50MHz. This is the result of the inductance in the loop which includes the input capacitor, the LT1074 leads, and the diode leads, combined with the capacitance of the catch diode. A total lead length of 4 inches will create ≈0.1μH. This coupled with 500pF of diode capacitance will create a damped 25MHz oscillation superimposed on the fast rising switch voltage waveform. Again, no harm is created by this ringing and no attempt should be made to dampen it other than minimizing lead length. Certain board layouts combined with very

Theoretical considerations for buck mode switching regulators

CHAPTER 5

Figure 5.13 • Buck Converter Waveforms with VIN = 20V, L = 50µH

short interconnects and high diode capacitance may create a tuned circuit which resonates with the switch output to cause a low amplitude oscillation at the switch output during on time. This can be eliminated with a ferrite bead slipped over either diode lead during board assembly. It is interesting to note that standard silicon fast recovery diodes create almost no ringing because of their lower capacitance and because they are effectively damped by their slower turn-off characteristics. This slower turn-off and the larger forward voltage represent additional power loss, so Schottky diodes are normally recommended.

Maximum output current of a buck converter is given by Continuous Mode

I OUT(MAX) = 1M −

VOUT (VIN − VOUT ) 2f • VIN • L

(5)

IM = Maximum switch current (5.5A for LT1074) VIN = DC input voltage (maximum) VOUT = Output voltage f = Switching frequency 105

SECTION TWO

Switching Regulator Design

For the example shown, with L = 50μH, and VIN = 25V,

I OUT(MAX) = 5. 5 −

5(25 − 5) = 5. 1A(6) × 10−6 )

2(105 )(25)(50

Note that increasing inductor size to 100μH would only increase maximum output current by 4%, but decreasing it to 20μH would drop maximum current to 4.5A. Low inductance can be used for lower output currents, but core loss will increase.

Inductor The inductor used in a buck converter acts as both an energy storage element and a smoothing filter. There is a basic trade-off between good filtering versus size and cost. Typical inductor values used with the LT1074 range from 5μH to 200μH, with the small values used for lower power, minimum size applications and the larger values used to maximize output power or minimize output ripple voltage. The inductor must be rated for currents at least equal to output current and there are restrictions on ripple current (expressed as volt • microsecond product at various frequencies) to avoid core heating. For details on selecting an inductor and calculating losses, see the Inductor Selection section.

Output catch diode D1 is used to generate a current path for L1 current when the LT1074 switch turns off. The current through D1 in continuous mode is equal to output current with a duty cycle of (VIN – VOUT)/VIN. For low input voltages, D1 may operate at duty cycles of 50% or less, but one must be very careful of utilizing this fact to minimize diode heat sinking. First, an unexpected high input voltage will cause duty cycle to increase. More important however, is a shorted output condition. When VOUT = 0, diode duty cycle is ≈1 for any input voltage. Also, in current limit, diode current is not load current, but is determined by LT1074 switch current limit. If continuous output shorts must be tolerated, D1 must be adequately rated and heat sunk. 7 and 11-pin versions of

106

the LT1074 allow current limit to be reduced to limit diode dissipation. 5-pin versions can be accurately current limited using the technique shown in Figure 5.20. Under normal conditions, D1 dissipation is given by:

P DI = I OUT

(VIN − VOUT ) • Vf VIN

(7)

Vf is the forward voltage of D1 at IOUT current. Schottky diode forward voltage is typically 0.6V at the diode’s full rated current, so it is normal design practice to use a diode rated at 1.5 to 2 times output current to maintain efficiency and allow margin for short-circuit conditions. This derating allows Vf to drop to approximately 0.5V. Example: VIN(MAX) = 25V, IOUT = 3A, VOUT = 5V, assume Vf = 0.5V: Full Load P DI =

(3)(25 − 5)(0. 5V) = 1. 2W 25

Shorted Output

P DI = (≈ 6A)(DC = 1)(0. 6V) = 3. 6W The high diode dissipation under shorted output conditions may necessitate current limit adjustment if adequate heat sinking cannot be provided. Diode switching losses have been neglected because the reverse recovery time is assumed to be short enough to ignore. If a standard silicon diode is used, switching losses cannot be ignored. They can be approximated by: Ptrr ≈ (VIN )(f)(trr )(I OUT )

(9)

trr = Diode reverse recovery time

Example: Same circuit with trr = 100ns: Ptrr = (25)(105 )(10−7 )(3) = 0. 75W

(10)

Diodes with abrupt turn-off characteristics will transfer most of this power to the LT1074 switch. Soft recovery diodes will dissipate much of the power within the diode itself.

Theoretical considerations for buck mode switching regulators

LT1074 power dissipation The LT1074 draws about 7.5mA quiescent current, independent of input voltage or load. It draws an additional 5mA during switch on time. The switch itself dissipates a power approximately proportional to load current. This power is due to pure conduction losses (switch on voltage times switch current) and dynamic switching losses due to finite switch current rise and fall times. Total LT1074 power dissipation can by calculated from: P = VIN [7mA + 5mA • DC + 21OUT • tSW • f]   (11) + DC I OUT (1. 8V)∗ + 0. 1�∗ (I OUT )2

VOUT + 0. 5V DC = Duty Cycle ≈ VIN − 2V

tSW = Effective overlap time of switch voltage and current ≈50ns + (3ns/A)(IOUT) (LT1074) ≈60ns + (10ns/A)(IOUT) (LT1076) Example: VIN = 25V, VOUT = 5V, f = 100kHz, IOUT = 3A: DC =

5 + 0. 5 = 0. 196 25 − 2

(12)

tSW = 50ns + (3ns/A)(3A) = 59ns P =     7mA + 5mA(0. 196)+ 25 + 0. 196 3(1. 8) + 0. 1(3)2 (2)(3)(59ms)(105 ) =

0. 21W   

Supply Current Loss

*LT1076

+

0. 89W   

+

1. 24W   

=2. 34W

Dynamic Switching Loss Switch Conduction Loss

(13)

= 1V, 0.3Ω

Input capacitor (buck converter) A local input bypass capacitor is normally required for buck converters because the input current is a square wave with fast rise and fall times. This capacitor is chosen by ripple current rating—the capacitor must be large enough

CHAPTER 5

to avoid overheating created by its ESR and the AC RMS value of converter input current. For continuous mode:  VOUT (VIN − VOUT ) (14) I AC,RMS = I OUT (VIN )2 Worst case is at VIN = 2VOUT. Power loss in the input capacitor is not insignificant in high efficiency applications. It is simply RMS capacitor current squared times ESR: P C3 = (I AC,RMS )2 (ESR)

(15)

Example: VIN = 20V to 30V, IOUT = 3A, VOUT = 5V. Worst case is at VIN = 2 • VOUT = 10V, so use the closest VIN value of 20V: I AC,RMS = 3A



5(20 − 5) = 1. 3A RMS (20)2

(16)

The input capacitor must be rated at a working voltage of 30V minimum and 1.3A ripple current. Ripple current ratings vary with maximum ambient temperature, so check data sheets carefully. It is important to locate the input capacitor very close to the LT1074 and to use short leads (radial) when the DC input voltage is less than 12V. Spikes as high as 2V/inch of lead length will appear at the regulator input. If these spikes drop below ≈7V, the regulator will exhibit anomalous behavior. See VIN Pin in the Pin Descriptions section. You may be wondering why no mention has been made of capacitor value. That’s because it doesn’t really matter. Larger electrolytic capacitors are purely resistive (or inductive) at frequencies above 10kHz, so their bypassing impedance is resistive, and ESR is the controlling factor. For input capacitors used with the LT1074, a unit which meets ripple current ratings will provide adequate “bypassing” regardless of its capacitance value. Units with higher voltage rating will have lower capacitance for the same ripple current rating, but as a general rule, the volume required to meet a given ripple current/ESR is fixed over a wide range of capacitance/voltage rating. If the capacitor chosen for this application has 0.1Ω ESR, it will have a power loss of (1.3A)2 (0.1Ω) = 0.17W.

107

SECTION TWO

Switching Regulator Design

Output capacitor In a buck converter, output ripple voltage is determined by both the inductor value and the output capacitor: Continuous Mode   (ESR)(VOUT 1 − VVOUT IN (17) VP P = (L1)(f) Discontinuous Mode  (21OUT (VOUT )(VIN − VOUT ) VP P = ESR L • f • VIN Note that only the ESR of the output capacitor is used in the formula. It is assumed that the capacitor is purely resistive at frequencies above 10kHz. If an inductor value has been chosen, the formula can be rearranged to solve for ESR to aid in selecting a capacitor. Continuous Mode ESR(MAX) =

(VP P )(L1)(f)   VOUT 1 − VVOUT IN

Discontinuous Mode  ESR(MAX) = VP P

(18)

L • f • VIN 21OUT (VOUT )(VIN − VOUT )

108

(0. 025)(50 • 10−6 )(105 )   = 0. 03� 5 (5) 1 − 25

A. Paralleling several capacitors if component height is more critical than board area. B. Increasing inductance. This can be done at no increase in size if a more expensive core (molypermalloy, etc.) is used. C. Adding an output filter. This is often the best solution because the additional components are fairly low cost and their additional space is minimized by being able to “size down” the main L and C. See the Output Filter section. Although ripple current is not usually a problem with buck converter output capacitors because the current is pre-filtered by the inductor, a quick check should be done before a final capacitor is chosen—especially if the capacitor has been “downsized” to take advantage of an additional output filter. RMS ripple current into the output capacitor is: Continuous Mode

I RMS =

 0. 29(VOUT ) 1 − L1 • f

VOUT VIN



(20)

From the previous example:

Worst-case output ripple is at highest input voltage. Ripple is independent of load for continuous mode and proportional to the square root of load current for discontinuous mode. Example: Continuous mode with VIN(MAX) = 25V, VOUT = 5V, IOUT = 3A, L1 = 50μH, f = 100kHz. Required maximum peak-to-peak output ripple is 25mV. ESR =

A 10V capacitor with this ESR would have to be several thousand microfarads, and therefore fairly large. Trade-offs which could be made include:

(19)

I RMS =

5 25 ) • 10−6 )(105 )

0. 29(5)(1 − (50

= 0. 23A RMS

(21)

This ripple current is low enough to not be a problem, but that could change if the inductor was reduced by two or three to one and the output capacitor was minimized by adding an output filter. The calculations for discontinuous mode RMS ripple current were considered too complicated for this discussion, but a conservative value would be 1.5 to 2 times output current.

Theoretical considerations for buck mode switching regulators

CHAPTER 5

To minimize output ripple, the output terminals of the regulator should be connected directly to the capacitor leads so that the diode (D1) and inductor currents do not circulate in output leads.

that the frequency shifting action created by the FB pin voltage is maintained under shorted output conditions.

Efficiency

Switching regulators often exhibit start-up overshoot because the 2-pole LC network requires a fairly low unity-gain frequency for the feedback loop. The LT1074 has asymmetrical error amplifier slew rate to help reduce overshoot, but it can still be a problem with certain combinations of L1C1 and C2R3. Overshoot should be checked on all designs by allowing the output to slew from zero in a no-load condition with maximum input voltage. This can be done by stepping the input or by pulling the VC pin low through a diode connected to a 0V to 10V square wave. Worst-case overshoot can occur on recovery from an output short because the VC pin must slew from its high clamp state down to ≈1.3V. This condition is best checked with the brute force method of shorting and releasing the output. If excessive output overshoot is found, the procedure for reducing it to a tolerable level is to first try increasing the compensation resistor. The error amplifier output must slew negative rapidly to control overshoot and its slew rate is limited by the compensation capacitor. The compensation resistor, however, allows the amplifier output to “step” downward very rapidly before slewing limitations begin. The size of this step is ≈(1.1mA)(RC). If RC can be increased to 3kΩ, the VC pin can respond very quickly to control output overshoot. If loop stability cannot be maintained with RC = 3kΩ, there are several other solutions. Increasing the size of the output capacitor will reduce short-circuit-recovery overshoot by limiting output rise time. Reducing current limit will also help for the same reason. Reducing the compensation capacitor below 0.05μF helps because the VC pin can then slew an appreciable amount during the allowable overshoot time. The “final solution” to output overshoot is to clamp the VC pin so that it does not have to slew as far to shut off the output. The VC pin voltage in normal operation is

All the losses except those created by the inductor and the output filter are covered in this buck regulator section. The example used was a 5V, 3A output with 25V input. Calculated losses were: switch, 1.24W; diode, 1.2W; switching times, 0.89W; supply current, 0.21W; and input capacitor, 0.17W. Output capacitor losses were negligible. The sum of all these losses is 3.71W. Inductor loss is covered in a special section of this Application Note. Assume for this application that inductor copper loss is 0.3W and core loss is 0.15W. Total regulator loss is 4.16W. Efficiency is: E=

(3A)(5V) I OUT • VOUT = = 78% I OUT • VOUT + �P L (3A)(5V) + 4. 16

(22)

When considering improvements or trade-offs of particular loss terms, keep in mind that a change in any one term will be attenuated by efficiency squared. For instance, if switch loss were reduced by 0.3W, this is 2% of the 15W output power, but only a 2(0.8)2 = 1.28% improvement in efficiency.

Output divider R1 and R2 set DC output voltage. R2 is normally set at 2.21kΩ (a standard 1% value) to match the LT1074 reference voltage of 2.21V, giving a divider current of 1mA. R1 is then calculated from: R1 =

R2(VOUT − VREF ) VREF

(23)

If R2 = 2.21kΩ, R1 = (VOUT – VREF) kΩ R2 may be scaled in either direction to suit other needs, but an upper limit of 4kΩ is suggested to ensure

Output overshoot

109

SECTION TWO

Switching Regulator Design

known fairly precisely because it is made independent of everything except output voltage by the internal multiplier: VOUT (24) VC Voltage ≈ 2 φ + 24 φ = VBE of internal transistor = 0.65V – 2mV/°C To allow for transient conditions and circuit tolerances, a slightly different expression is used to calculate clamp level for the VC pin: VC(CLAMP) = 2 φ +

VIN(MAX) VOUT + + 0. 2V 20 50

(25)

Overshoot fixes that don’t work

For a 5V output with VIN(MAX) = 30V: VC(CLAMP) = 2(0. 65) +

5 30 + + 0. 2 = 2. 35V 20 50

It clamps the VC pin to the feedback pin with two diodes, D1 and D2. These are small signal non-gold doped-diodes with a forward voltage that matches φ. The reason for this is start-up. VC is essentially clamped to ground through the output divider when VOUT = 0. It must be allowed to rise sufficiently to ensure start-up. The feedback pin will sit at about 0.5V with VOUT = 0, because of the combined current from the feedback pin and VC pin. The VC voltage will be 2φ + 0.5V + (0.14mA) (RC). With RC = 1kΩ, VC = 1.94. This is plenty to ensure start-up.

(26)

There are several ways to clamp the VC pin as shown in Figure 5.14. The simplest way is to just add a clamp Zener (D3). The problem is finding a low voltage Zener which does not leak badly below the knee. Maximum Zener leakage over temperature should be 40μA at VC = 2φ + VOUT/20V. One solution is to use an LM385-2.5V micropower reference diode where the calculated clamp level does not exceed 2.5V.

I know that these things don’t work because I tried them. The first is soft-start, created by allowing the output current or the VC voltage to ramp up slowly. The first problem is that a slowly rising output allows more time for the VC pin to ramp up well beyond its nominal control point so that it has to slew farther down to stop overshoot. If the VC pin itself is ramped slowly, this can control input startup overshoot, but it becomes very difficult to guarantee reset of the soft-start for all conditions of input sequencing. In any case, these techniques do not address the problem of overshoot following overload of the output, because they do not get “reset” by the output. Another common practice is to parallel the upper resistor in the output divider with a capacitor. This again works fine under limited conditions, but it is easily defeated by overload conditions which pull the output slightly below its regulated point long enough for the VC pin to hit the positive limit (≈6V). The added capacitor remains charged and the VC pin must slew almost 5V to control overshoot when the overload is released. The resulting overshoot is impressive—and often deadly.

Tapped-inductor buck converter

Figure 5.14 • Clamping the VC Pin

A second clamp scheme is to use a voltage divider and diode (D4). VX must be some quasi-regulated source which does not collapse with regulator output voltage. A third technique can be used for outputs up to 20V.

110

Output current of a buck converter is normally limited to maximum switch current, but this restriction can be altered by tapping the inductor as shown in Figure 5.15. The ratio of “input” turns to “output” turns is “N” as shown in the schematic. The effect of the tap is to lengthen switch on time and therefore draw more power from the input without raising switch current. During switch on time, current delivered to the output through L1 is equal to switch current—5.5A maximum for the LT1074. When the switch turns off, inductor current flows only in the output section of L1, labeled “1,” through

Theoretical considerations for buck mode switching regulators

CHAPTER 5

Figure 5.15 • Tapped-Inductor Buck Converter

D1 to the output. Energy conservation in the inductor requires that current increase by the ratio (N + 1):1. If N = 3, then maximum current delivered to the output during switch off time is (3 + 1)(5.5A) = 22A. Average load current is increased to the weighted average of the 5A and 22A currents. Maximum output current is given by:

I OUT(MAX) = 

  (VIN ′ − VOUT ′ )(1 + N) N + 1   � � 0. 95 I SW − N•V V ′ ′ 2Lf N + V IN ′ 1 + V OUT ′ OUT

IN

(27)

L = Total Inductance The last term, (N + 1)/(1 + N • VOUT/VIN) is the basic switch current multiplier term. At high input voltages it approaches N + 1, and theoretical output current approaches 18A for N = 3. For lower input voltages the multiplier term approaches unity and no benefit is gained by tapping the inductor. Therefore, when calculating maximum load current capability, always use the worst-case low input voltage. The 0.95 multiplier is thrown-in to account for second order effects of leakage inductance, etc.

Example: VIN(MIN)=20V, N=3, L=100μH, VOUT=5V, Diode Vf = 0.55V, f =100kHz. Let ISW = Maximum for LT1074 = 5.5A, VOUT' = 5V + 0.55V = 5.55V, VIN' = 20V – 2V = 18V: I OUT(MAX) 

� � 3+1 (18 − 5. 55)(1 + 3)   � � =0. 95 5. 5 − 18 1 + 3(5.55) 2(10−4 )(105 ) 3 + 5.5 18 (28) = 0. 95[5. 5 − 0. 4][2. 08] = 10. 08A

Duty cycle of the tapped-inductor converter is equal to:

DC =

1+N N+

(29)

VIN ′ VOUT ′

Average and peak diode currents are: I OUT (VIN ′ − VOUT ′ ) I D(AVG) = VIN ′

(30)

(Use Maximum VIN ′)

I D(PEAK) =

I OUT (NVOUT ′ + VIN ′ ) VIN ′

(Use Minimum VIN ′)

111

Switching Regulator Design

SECTION TWO

Average switch current during switch on time is:

I SW(AVG) =

I OUT (N • VOUT ′ + VIN ′ ) VIN ′ (1 + N)

P SWITCH = (1SW )(DC)[1. 8V + (0. 1)(I SW )] (31)

+ (VIN ′ + VZ )(I SW )(f)(tSW ) tSW = 50ns + 3ns • I SW = (3. 85)(0. 64)[1. 8 + (0. 1)(3. 85)]

(Use Minimum VIN')

+ (20 + 30)(3. 85)(105 )(62ns)

Diode peak reverse voltage is: VDI(PEAK) =

= 5. 3W + 1. 19W = 6. 5W

VIN + N • VOUT 1+N

(32)

VDI(PEAK)) =

(Use Maximum VIN) Switch reverse voltage is:

VSW = 30 + 30 +

VSW = VIN + VZ + VSPIKE

(33)

(Use Maximum VIN) VZ = Reverse breakdown of D2 (30V) VSPIKE = Narrow (