Analog and Digital Electronics (3130907) Darshan Unit-2 to 6

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Unit-2B

Linear Applications of Op. Amp.

Analog & Digital Electronics (3130907)

3rd Semester Electrical Engineering

Unit-2.B Linear Applications of Op. Amp. 2.1 The 741C Op Amp is connected in Non inverting mode having following parameters R1 = 1 KΏ, Rf = 10 KΏ, A = 2,00,000 , Ri = 2 MΏ , Ro = 75 Ώ , f = 5 Hz , Supply voltage = ± 15 volt , Output voltage swing = ± 13 volt Then compute the value of : Af , Rif , Rof , fF , VooT Solution: Av = ( 1 +

𝑅𝑓 𝑅1

) = (1+

10 1

) = 11 𝑅1

β =

1

=

𝑅1 + 𝑅𝑓

1 + 10

=

1 11

= 0.0909

RinF = Rin (1 + β A) = 2 x 106 x (1 + 0.0909 x 2 x 105) = 36.4 x 109 Ώ

RoF =

𝑅𝑜

=

1+𝛽𝐴.

75 1 + 0.0909 x 2 x 105

= 0.0042 Ώ

fF = f (1 + β A) = 5 x (1 + 0.0909 x 2 x 105) = 90.9 KHz

VooT =

𝑉𝑆𝑎𝑡

=

1+𝛽𝐴.

13 1 + 0.0909 x 2 x 105

= 0.715 mV

2.2 The 741C Op Amp is connected in Non inverting mode having following parameters Given: Vin = 0.6V, RF = 200 KΏ , R1 = 2 KΏ , AOL = 400k , Rin = 8 MΏ , Ro = 60 Ώ Find : Vo , iF , Av , β , RinF and RoF Solution: Vo = ( 1 + IF =

𝑉𝑖𝑛 𝑅1

=

𝑅𝑓 𝑅1

) Vin = ( 1 +

0.6 2000

200

= 0.3 mA

( Also, If = Av = ( 1 +

𝑅𝑓 𝑅1

) x 0.6 = 60.6 Volt

2

) = (1+

200 2

𝑉𝑜 − 𝑉𝑓 𝑅𝑓

=

60.6 − 0.6 200000

=

60 200000

= 0.3 mA )

) = 101

Prof. Manoj N. Popat (E.C. Dept.)

Analog & Digital Electronics (2130907)

1

Unit-2.B Linear Applications of Op. Amp 𝑅1

β =

𝑅1 + 𝑅𝑓

2

=

= 9.9 x 10-3

2 + 200

RinF = Rin (1 + β AOL) = 8 x 106 (1 + 9.9 x 10-3 x 4 x 105) = 3.1688x1010 Ώ

RoF =

𝑅𝑜

=

1+𝛽𝐴𝑜𝐿

60 1 + 9.9 x 10−3 x 4 x 105

= 0.015 Ώ

2.3 The 741C Op Amp is connected in Inverting mode having following parameters Given: Vin = 0.6V, RF = 20 KΏ , R1 = 2 KΏ , AOL = 400k , Rin = 8 MΏ , Ro = 60 Ώ Find : Vo , iF , Av , β , RinF and RoF Solution: Vo = ( -

𝑅𝑓

𝑉𝑖𝑛

=

IF =

𝑅1

𝑅1

) Vin = ( 0.6

20 2

) x 0.6 = - 6 Volt

= 0.3 mA

2000

( Also, If = Av = ( β =

𝑅𝑓 𝑅1

𝑅1 𝑅1 + 𝑅𝑓

) = (=

20 2

2 2 + 20

𝑉𝑜 − 𝑉𝑓 𝑅𝑓

=

6 −0 20000

=

6 20000

= 0.3 mA ) as VF is virtual ground

) = 10 = 0.0909

RinF = R1 = 2000 Ώ

RoF =

𝑅𝑜 1+𝛽𝐴𝑜𝐿

=

60 1 + 0.0909 x 4 x 105

= 0.00167 Ώ

2.4 Draw the circuit of differential amplifier using one Op. Amp. and derive the equation of differential gain (AD). The differential amplifiers amplify the difference between two input voltages making this type of operational amplifier circuit a Subtractor. The basic differential amplifier is shown in figure. Prof. Manoj N. Popat (E.C. Dept.)

Analog & Digital Electronics (2130907)

2

Unit-2.B Linear Applications of Op. Amp.

Since there are two inputs Superposition theorem can be used to find the output voltage. When, Vb = 0, then the circuit becomes inverting amplifier, hence the output is due to Va only. Voa = -

𝑅𝑓

Va ----- (1)

𝑅1

Similarly When, Va = 0, the configuration is a Non-inverting amplifier having a voltage divided network at the non-inverting input. Vob = ( 1 +

𝑅𝑓 𝑅1

) V1 ----- (2)

but in equation (2) V1 = (

𝑅2 𝑅2 + 𝑅3

) Va ----- (3)

Substituting the value of V1, in equation (2) Vob = ( 1 +

𝑅𝑓 𝑅1

) (

𝑅𝑓 𝑅2 + 𝑅3

) Va ----- (4)

In equation (4) if R2 = R1 and R3 = Rf then equation (4) can be written as Vob = (

𝑅1 + 𝑅𝑓 𝑅1

) (

𝑅𝑓 𝑅1 + 𝑅𝑓

) Va ----- (5)

So, Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp Vob = (

𝑅𝑓 𝑅1

) Va ----- (6)

As per Superposition theorem sum of equation (1) and (6) is total output voltage. 𝐕𝐨 = ( −

𝑹𝒇 𝑹𝟏

) ( 𝐕𝐚 − 𝐕𝐛 ) ----- (7)

Now, differential Gain can be written as 𝐀𝑫 =

𝑽𝒐 𝑽𝒂𝒃

=

𝑽𝒐 𝑽𝒂 −𝑽𝒃

=−

𝑹𝒇 𝑹𝟏

----- (8)

Input Impedance : Input Impedance at Inverting terminal is 𝐑 𝒊𝒇𝒂 = 𝑹𝟏 Input Impedance at Non-Inverting terminal is 𝐑 𝒊𝒇𝒃 = 𝑹𝒊 (1 + A𝜷) Thus, it has been observed that input impedances are not matched, 𝐑 𝒊𝒇𝒂 ≠ 𝑹𝒊𝒇𝒃 Which is one of the limitation of Differential amplifier using one Op. Amp. 2.5

Draw the Block diagram of Instrumentation System and explain it.

The measurement and control of physical conditions is very important in many industrial and consumer applications. For example, the operator may make necessary adjustments in the measurement of temperature or humidity inside a dairy or meat plant to maintain the product quality, or to produce a particular type of plastic, precise temperature control of the plastic furnace is needed. A transducer is generally used at the measuring site to obtain the required information easily and safely. Transducer is a device that converts one form of energy into another. For example, when a strain gauge is subjected to pressure or force (physical energy), the resistance of the strain gauge changes (electrical energy), i.e. it converts mechanical energy into electrical energy. Actually, an instrumentation system is used to measure the output signal produced by the transducer and mostly used to control the physical condition producing the output signal. The simplified form of such an instrumentation system is shown in Figure.

Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp.

This instrumentation system consists of a type of transducer as the input stage, depending upon the physical quantity to be measured. The transducers output is fed to the pre-amplifier. The instrumentation amplifier is the intermediate stage. The output of the instrumentation amplifier can be connected to various devices, such as meter, oscilloscope, charts or magnetic recorders. The lines connecting the various stages, as shown in figure are called the transmission lines. On the system requirement and the physical quantity to be monitored, the length of these transmission lines are chosen. These transmission lines permit signal transfer from unit to unit. The output of the transducer is the input signal source of the instrumentation amplifier. A transducer which produces sufficient strength can be used to drive the output device directly. Most do not produce sufficient output. Hence, to amplify these low level output signals of the transducer, instrumentation amplifiers are used which drive the indicator or display unit or output device. 2.6

Explain Instrumentation Amplifier in detail. OR Draw and explain the circuit diagram of Instrumentation Amplifier using transducer bridge which is consisting of Thermistor in one of it’s arm of bridge. OR Explain differential Instrumentation Amplifier with transducer bridge

Simplified circuit of a Differential Instrumentation Amplifier with Transducer Bridge is as shown in figure. In this circuit a resistive transducer/Thermistor (whose resistance changes as a function of some physical energy/Temperature) is connected to one arm of the bridge. Let RT be the resistance of the transducer and ΔR the change in resistance of the resistive transducer. Hence the total resistance of the transducer is (R T ± ΔR).

Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp

The condition for bridge balance is Vb = Va, i.e. the bridge is balanced when Vb = Va, or when,

The bridge is balanced at a desired reference condition, which depends on the specific value of the physical quantity to be measured. Under this condition, resistors R A, RB and RC are so selected that they are equal in value to the transducer resistance RT. (The value of the physical quantity normally depends on the transducers characteristics, the type of physical quantity to be measured, and the desired applications.) Initially the bridge is balanced at a desired reference condition. As the physical quantity to be measured changes, the resistance of the transducer also changes, causing the bridge to be unbalanced (Vb ≠ Va ). Hence, the output voltage of the bridge is a function of the change in the resistance of the transducer. The expression for the output voltage V0, in terms of the change in resistance of the transducer is calculated as follows. Let the change in the resistance of the transducer be ΔR. Since R B and RC are fixed resistors, the voltage Vb is constant, however, the voltage Va changes as a function of the change in the transducers resistance. Therefore, applying the voltage divider rule we have

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Unit-2.B Linear Applications of Op. Amp. The output voltage across the bridge terminal is Vab, given by Vab=Va-Vb Therefore,

The output voltage Vab of the bridge is applied to the Differential Instrumentation Amplifier through the voltage followers to eliminate the loading effect of the bridge circuit. The gain of the basic amplifier is (RF/R1) and therefore the output voltage Vo of the circuit is given by

It can be seen from the above equation that Vo is a function of the change in resistance ΔR of the transducer. Since the change is caused by the change in a physical quantity, a meter connected at the output can be calibrated in terms of the units of the physical quantity. Applications of Instrumentation Amplifier with Transducer Bridge We shall now consider some important applications of instrumentation amplifiers using resistance types transducers. In these transducers, the resistance of the transducer changes as a function of some physical quantity. Commonly used resistance transducers are thermisistors, photoconductor cells, and strain gauges. (i) (ii) (iii) 2.6

Temperature Indicators Using Thermistor Light Intensity Meter Analog Weight Scale Explain Integrator circuit in detail. OR Draw circuit diagram of Integrator using Op. Amp. and derive the equation of output voltage. Also draw the output waveform if input is (i) Sine wave and (ii) Square wave. OR Draw circuit diagram of Integrator using Op. Amp and explain it with necessary frequency response and derivations. Also draw practical Integrator circuit.

Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp An integrator is the circuit in which the output voltage waveform is the integral of the input voltage waveform. It can be obtained by replacing feedback resistor by feedback capacitor in basic inverting amplifier. Input signal, which can be applied at the inverting terminal i.e. pin – 2 of the op-amp through resistor Rin. A feedback capacitor Cf is connected between the output terminal i.e. pin – 6 and the inverting terminal i.e. pin – 2 of the op-amp. The non-inverting terminal i.e. pin – 3 of the op-amp is grounded either directly or through a resistor which is a parallel combination of input resistor Rin and feedback resistor Rf. Figure 1 shows Basic Integrator Circuit.

Basic Integrator circuit The output of the op-amp will then be integrated version of the input. DESIGN EQUATION : Applying KCL at inverting node,

Iin = IB + IF As input impedance of op-amp is very large, bias current IB =0. Therefore,

Iin = IF = I The current through resistor R1 can be given as

---- (1)

The current through capacitor can be given as

-----(2)

Because of virtual ground concept VA=VB=0 in equation (1) and (2). Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp. Now comparing equation (1) and (2)

----(3)

Integrating both sides of equation (3)

---- (4)

---- (5)

Equation (5) indicates that output is integration of input voltage. Hence this circuit will work as an integrator circuit. Where Vo(0) is constant of integration and it indicates initial value of output voltage at time t=0. Frequency Response of Integrator: Frequency response is graph relating Gain and Frequency. Capacitive reactance Xc =

𝟏 𝟐𝛑𝐟𝐂.

As frequency is increases, Xc and gain will decreases. But at low frequency capacitive reactance Xc is high, so gain is very large and circuit becomes unstable at low frequency input signal. To control the gain at low frequency, a Resistor Rf is required to be connected in parallel with Cf in practical integrator circuit. Frequency response of Ideal/Basic integrator and practical integrator circuit is as shown in figure.

Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp

Frequency Response of Basic & Practical Integrator PRACTICAL INTEGRATOR CIRCUIT:

Practical Integrator circuit DESIGN: Frequency at which gain starts decreases is called gain limiting frequency and is given by equation 1 f𝑎 =

2Π R f Cf

The frequency at which the gain is 0 dB (Unity) is given by equation f𝑏 =

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1 2Π R1 Cf Analog & Digital Electronics (2130907)

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Unit-2.B Linear Applications of Op. Amp. Generally fb = 20 fa Now selecting standard value of capacitor Cf we can determine the value of R1 and Rf using equation of fa and fb to design Integrator of particular frequency range. INPUT & OUTPUT WAVE FORMS : -

2.7

Draw the output wave form if unit step input is applied to an integrator as shown in figure.

Let the input waveform is of step type, with a magnitude of A units as shown in the figure. For simplicity of understanding, assume that the time constant R 1Cf = 1 and the initial voltage V0(0) = OV.

Mathematically the step input can be expressed as,

From above equation with RICf = 1 and V0(0) = 0,

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Unit-2.B Linear Applications of Op. Amp

Now the output waveform can be drawn as follow:

Thus output waveform is a straight line (negative going Ramp) with a slope of -A where A is magnitude of the step input. The output waveform is shown in the figure. 2.8

Explain Differentiator circuit in detail. OR Draw circuit diagram of Differentiator using Op. Amp. and derive the equation of output voltage. Also draw the output waveform if input is (i) Sine wave, (ii) Square wave and (iii) Triangular wave. OR Draw circuit diagram of Differentiator using Op. Amp and explain it with necessary frequency response and derivations. Also draw practical Differentiator circuit.

The circuit which produces the differentiation of the input voltage at its output is called Differentiator. The differentiator using an active device like op-amp is called an active Differentiator. Let us discuss first the operation of Ideal/Basic Differentiator circuit.

The active differentiator circuit can be obtained by exchanging the positions of R and C in the basic integrator circuit. The op-amp differentiator circuit is shown in the figure.

Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp. The node B is grounded. The node A is also at the ground potential because of virtual ground, hence VA = 0. DESIGN EQUATION : Applying KCL at inverting node,

Iin = IB + IF As input impedance of op-amp is very large, bias current IB =0. Therefore,

Iin = IF = I1 The current through capacitor C1 can be given as

---- (1)

The current through resistor Rf can be given as

-----(2)

Because of virtual ground concept VA=VB=0 in equation (1) and (2).

Now comparing equation (1) and (2)

----- (3)

Hence,

---- (4)

Equation (4) indicates that output is differentiation of input voltage. Hence this circuit will work as an differentiator circuit. Frequency Response of Differentiator: Frequency response is graph relating Gain and Frequency. Capacitive reactance Xc =

𝟏 𝟐𝛑𝐟𝐂.

As frequency is increases, Xc will decreases and gain will increase. At low frequency capacitive reactance Xc is high, so gain is low and circuit is stable. But as the frequency is increasing, Xc will decrease which cause the gain to increase. Thus at high frequency input signal, circuit becomes unstable. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp So, gain is required to be controlled at high frequency. To control the gain at high frequency, a Resistor R1 is required to be connected in series with input capacitor C 1 in practical Differentiator circuit. Also a feedback resister Rf is to be connected in parallel with Cf. Frequency response of Ideal/Basic differentiator and practical differentiator circuit is as shown in figure.

Frequency Response of Basic & Practical Differentiator PRACTICAL DIFFERENTIATOR CIRCUIT:

Practical Differentiator circuit DESIGN: The frequency at which the gain is 0 dB (Unity) is given by equation f𝑎 =

1 2Π R f C1

Frequency at which gain starts decreases is called gain limiting frequency and is given by equation Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp. f𝑏 =

1 2Π R1 C1

Also gain is controlled by Cf and Rf. Hence gain limiting frequency can be given by equation. f𝑏 =

1 2Π R f Cf

Generally fb = 20 fa Now selecting standard value of capacitor C1 we can determine the value of Cf , R1 and Rf using equation of fa and fb to design differentiator of particular frequency range. INPUT & OUTPUT WAVE FORMS : -

2.9

Explain Summing, Scaling and Averaging amplifier using Op. Amp.

Figure shows an Summing Amplifier Circuit in inverting configuration with three inputs Va, Vb, Vc. Depending on the relation between Ra, Rb, Rc and RF, the circuit can be used as a Summing amplifier, Scaling amplifier or Average amplifier.

Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp Using Kirchoff‘s circuit equation, we have la + lb+ lc= IB + If. But IB ≡ 0 and V1 ≡ V2 ≡ 0 (Virtual ground) Therefore,

Ia + Ib + Ic = I f 𝑉𝑎 −𝑉2 𝑅𝑎

+

𝑉𝑏 −𝑉2 𝑅𝑏

+

---- (1)

𝑉𝑐 −𝑉2

=

𝑅𝑐

𝑉2 −𝑉𝑜

---- (2)

𝑅𝑓

As V2 is virtual ground, V2 = 0. Hence equation (2) is 𝑉𝑎 𝑅𝑎

+

𝑉𝑏 𝑅𝑏

So,

𝐕𝒐 = − [

(i)

+

𝑉𝑐 𝑅𝑐

=

−𝑉𝑜

---- (3)

𝑅𝑓

𝑹𝒇 𝑽𝒂 𝑹 𝒇 𝑽𝒃 𝑹 𝒇 𝑽𝒄 + + ] 𝑹𝒂 𝑹𝒃 𝑹𝒄

---- (4)

Summing Amplifier: In equation (4) if Ra = Rb = Rc = Rf = R then equation (4) is

V𝑜 = − [ V𝑎 + V𝑏 + V𝑐 ]

---- (5)

Thus circuit will behaves as Summing Amplifier which gives output that is sum of all the inputs. It is also called Adder circuit

(ii)

Scaling Amplifier: In equation (4) if Ra ≠ Rb ≠ Rc ≠ Rf then equation (4) is

V𝑜 = − [

𝑅𝑓 𝑉𝑎 𝑅𝑓 𝑉𝑏 𝑅𝑓 𝑉𝑐 + + ] 𝑅𝑎 𝑅𝑏 𝑅𝑐

---- (6)

Thus circuit will behaves as Scaling Amplifier in which every input is amplified by different scale/weight. Gain of every input is different.

(iii)

Averaging Amplifier: In equation (4) if Ra = Rb = Rc = R and R = 3Rf then equation (4) is

V𝑜 = −

𝑅𝑓 [ V𝑎 + V𝑏 + V𝑐 ] 𝑅

---- (7)

and

V𝑜 = − [ Prof. Manoj N. Popat (E.C. Dept.)

V𝑎 + V𝑏 + V𝑐 3

]

---- (8)

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Unit-2.B Linear Applications of Op. Amp. Thus circuit will behaves as Average Amplifier in which output is the average of three inputs..

2.10 Explain Subtractor circuit using Op. Amp. A subtractor circuit using a basic differential amplifier is as shown in figure.

By selecting the appropriate values for the external resistance, the input signal can be scaled to the desired value. As shown in figure, all values of the external resistance are equal, and the gain of the amplifier is unity. Therefore, the output voltage of differential amplifier with unity gain. As we know that output voltage in differential amplifier is

V𝑜 = −

𝑅𝑓 [ V𝑎 − V𝑏 ] 𝑅1

But in above circuit Rf = R1 = R2 = R3 = R Hence,

V𝑜 = − [ V𝑎 − V𝑏 ]

--- (1)

Thus the output is Subtraction of two input signal. So circuit will behaves as Subtractor circuit.

2.11 Explain RC phase shift Oscillator using Op. Amp, RC Phase Shift Oscillator basically consists of an amplifier and a feedback network consisting of resistors and capacitors arranged in ladder fashion. Hence such an oscillator is also called ladder type RC Phase Shift Oscillator. RC network is used in feedback path. In oscillator, feedback network must introduce a phase shift of 180° to obtain total phase shift around a loop as 360°. Thus if one RC network produces phase shift of 60° then to produce phase shift of 180° such three RC networks must be connected in cascade. Hence in RC phase shift oscillator, the feedback network consists of three RC sections each producing a phase shift of 60°, thus total phase shift due to feedback is 180° (3x 60°). Such a feedback network is shown in the figure. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp

The network is also called the ladder network. All the resistance values and all the capacitance values are same, so that for a particular frequency, each section of R and C produces a same phase shift of 60°. In R-C phase shift oscillator op-amp connected in inverting amplifier mode. Thus it introduces the phase shift of 180° between input and output. The feedback network consists of 3 RC sections each producing 60° phase shift. Hence total phase shift around a close loop is 360°. Such a RC phase shift oscillator using op-amp is shown in the figure.

The output of amplifier is given to feedback network. The Output of feedback network drives the amplifier. The total phase shift around a loop is 180° of amplifier and 180° due to 3 RC section, thus 360°. This satisfies the required condition for positive feedback and circuit works as an oscillator. The frequency of sustained oscillations generated depends on the values of R and C and is given by,

The frequency is measured in Hz. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp. At this frequency the gain of the op-amp must be at least 29 to satisfy loop gain Aβ = 1. Now gain of the op-amp inverting amplifier is given by,

Thus circuit will work as an oscillator which will produce a sinusoidal waveform if gain is 29 and total phase shift around a loop is 360°. This satisfies the Barkhausen criterion for the oscillator. These oscillators are used over the audio frequency range i.e. about 20 Hz up to 100 kHz. Advantages (i) The circuit is simple to design. (ii) Can produce output over audio frequency range. (iii) Produces sinusoidal output waveform. (iv) It is a fixed frequency oscillator. Disadvantages (i) phase shift oscillator is fixed frequency oscillator. Frequency cannot be varied. (ii) Frequency stability is poor. 2.12 Explain Wien Bridge Oscillator using Op. Amp, The Wien Bridge is one of the simplest and best known oscillators and is used extensively in circuits for audio applications. This is also RC oscillator which uses RC type of feedback network. Wien bridge oscillator uses a non-inverting amplifier. So in Wien bridge type there is no phase shift necessary through the feedback network. The two arms of the bridge, namely R1, C1 in series and R2, C2 in parallel are called frequency sensitive arms. This is because the components of these two arms decide the frequency of the oscillator. Such a feedback network is called lead–lag network. .

The resistance R and capacitor C are the components of frequency sensitive arms of the bridge. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp

The resistance Rf and R1 form the part of the feedback path. The gain of non inverting op-amp can be adjusted using the resistance Rf and R1. The gain of op-amp is,

To satisfy Barkhausen criterion that AB=1 it is necessary that the gain of the non inverting op-amp amplifier must be minimum 3.

Thus ratio of Rf and R1 must be greater than or equal to 2. The frequency of oscillations is given by,

The feedback is given to the non inverting terminal of op-amp which ensures zero phase shift. If in a Wien bridge feedback network, two resistances are not equal i.e. they are R 1 and R2 while two capacitors are not equal i.e. they are C1 and C2 then the frequency of oscillations is given by,

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Unit-2.B Linear Applications of Op. Amp.

Advantages (i) It is stable. (ii) We can change the frequency very effectively. (iii) The perfect sine wave output is possible. (iv) It is useful audio frequency range i.e. 20 Hz to 100 kHz. Disadvantages (i) The maximum frequency output is limited. 2.13 Explain Active Filters Active Filters is a circuit that is designed to pass a specified band frequencies while attenuating all the signals outside that band. It is a frequency selective circuit. The filters are basically classified as active filters and passive filters. The passive filter networks use only passive elements such as resistors, inductors and capacitors. On the other hand, active filter circuits use the active elements such as op-amps, transistors along with the resistors, inductors and capacitors. Modern active filters do not use inductors as the inductors are bulky, heavy and nonlinear. The inductors generate the stray magnetic fields. The inductors dissipate considerable amount of power. Advantages of Active Filters (i) Flexibility in Gain and Frequency Adjustment : The op-amp gain can be easily controlled in closed loop fashion, hence active filter input signal is not attenuated. The passive filters need the attenuation. The active filters can be easily tuned. (ii)

No Loading Effect : The op-amp has high input impedance and low output impedance. Hence active filter using op-amp does not cause loading of the source or load.

(iii)

Cost : Due to availability of modern ICs, a variety of cheaper op-amps are available. The inductors are absent which makes the modern active filters more economical than passive filters.

The most commonly used filters are: 1) Low Pass (LP) filter 2) High pass (HP) filter 3) Band Pass (BP) filter

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Unit-2.B Linear Applications of Op. Amp 4) Band Reject (BR) filter. This is also called as Band Stop Filter (BS) or Band Elimination (BE) filter. 5) All Pass filter Frequency response of Ideal filter: Each of these filters use op-amp as an active element and resistors and capacitors. Frequency response characteristics of these types of filters are as follow:

Active Filters Types: There are basically four useful Active Filters Types. 1. 2. 3. 4.

Butterworth Chebyschev Bessel Elliptic

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Unit-2.B Linear Applications of Op. Amp. Frequency response of major practical Active Filters Figure shows the frequency response characteristics of the Active Filters Classification. The ideal response is shown by the dashed lines, while solid lines indicate the practical filter response.

2.14 First order Law Pass Butterworth Filters The Butterworth filter has an essentially flat amplitude versus frequency response up to the cutoff frequency. A first order low pass Butterworth filter can be obtained from the Basic Low Pass Filter Circuit using an RC filter network. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp Figure shows a first order low pass Butterworth filter that uses an RC network for filtering. The op.amp. is used in the non-inverting configuration, which does not load the RC network. R1 and RF determine the gain of the filter (in this case unity).

Using the voltage divider rule, the voltage across the capacitor, i.e. at the non-inverting input is

Simplifying, we get

As output voltage

where Vo/Vin = Gain of the filter as a function of frequency AF = 1 + RF/R1= pass band gain of the filter f= frequency of the input signal Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.B Linear Applications of Op. Amp. fH = 1/2 π RC = high cutoff frequency The gain magnitude and phase angle can be obtained by applying modulus to

where Φ is the phase angle in degrees. The operation of the Basic Low Pass Filter Circuit can be verified from the gain magnitude

Hence the Basic Low Pass Filter Circuit has a constant gain, AF, from 0 Hz to the high cutoff frequency fH. At fH, the gain is 0.707 AF and after fH the gain decreases at a constant rate with increase in frequency; when the frequency is increased 10 times (one decade), the voltage gain is divided by 10. In other words, the gain decreases by 20 db (20 log 10) each time the frequency is increased by 10. Hence the rate at which the gain rolls off after fH is 20 db/decade or 6 db/octave, where octave signifies a two fold increase in frequency. The frequency f = fH is called the cutoff frequency.

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Unit-2.B Linear Applications of Op. Amp The procedure of converting a cutoff frequency to a new cutoff frequency is called frequency scaling. To obtain a new cutoff frequency, R or C (but not both) is multiplied by the ratio of the original cutoff frequency to the new cutoff frequency. In filter design, the values required for R and C are often not standard, and a variable capacitor C is not commonly used. Hence, we choose a standard value of the capacitor and then calculate the value of the resistor required for a desired cutoff frequency. This is because for a non-standing value of a resistor, a potentiometer can be used.

2.15 First order High Pass Butterworth Filters The Butterworth filter has an essentially flat amplitude versus frequency response up to the cutoff frequency. A first order high pass Butterworth filter can be obtained from the Basic high Pass Filter Circuit using an RC filter network. Figure shows a first order high pass Butterworth filter that uses an RC network for filtering. The op.amp. is used in the non-inverting configuration, which does not load the RC network. R1 and RF determine the gain of the filter (in this case unity). a high pass filter is a circuit that attenuates all the signals below a specified cut off frequency denoted as fL. Thus, a high pass filter performs the opposite function to that of low pass filter. Hence, the First Order High Pass Butterworth Filter circuit can be obtained by interchanging frequency determining resistances and capacitors in low pass filter circuit.

The first order high pass filter can be obtained by interchanging the elements R and C in a first order low pass filter circuit. The figure shows the first order high pass Butterworth filter.

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Unit-2.B Linear Applications of Op. Amp. It can be observed that as compared to first order low pass filter, the positions of R and C are changed in the high pass circuit shown in figure. The frequency at which the gain is 0.707 times the gain of filter in pass band (maximum) is called as low cut off frequency, and denoted as fL. So, all the frequencies greater than fL are allowed to pass but the maximum frequency which is allowed to pass is determined by the closed loop bandwidth of the op.amp. used. Analysis of the Filter Circuit The impedance of the capacitor is

where f is the input i.e. operating frequency. By the voltage divider rule, the potential of the non inverting terminal of the op.amp. is

Substituting in the above expression of VA,

This can be represented as

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Unit-2.B Linear Applications of Op. Amp

Now, for the op-amp in non-inverting configuration,

Hence,

This is the required expression for the transfer function of the filter. For the frequency response, we require the magnitude of the transfer function which is given by,

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Unit-2.B Linear Applications of Op. Amp.

Thus, the circuit acts as high pass filter with a pass band gain as Af. For the frequencies, f < fL, the gain increases till f = fL at a rate of + 20 dB/decade. Hence, the slope of the frequency response in stop band is + 20 dB/decade for first order high pass filter. The frequency response is shown in the figure.

Note : As high pass filter is basically a low pass filter circuit with positions of R and C interchanged, the design steps and the frequency scaling method discussed earlier for low pass filter is equally applicable to the first order high pass Butterworth filter.

2.16 Second order Low Pass Butterworth Filters The practical response of Second Order Low Pass Butterworth Filter must be very close to an ideal one. In case of low pass filter, it is always desirable that the gain rolls off very fast after the cut off frequency, in the stop band. In case of first order filter, it rolls off at a rate of 20 dB/decade. In case of second order filter, the gain rolls off at a rate of 40 dB/decade. Thus, the slope of the frequency response after f = f H is -40 dB/decade, for a second order low pass filter.

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Unit-2.B Linear Applications of Op. Amp

A first order filter can be converted to second order type by using an additional RC network as shown in the figure. The cut off frequency fH for the filter is now decided by R2, C2, R3 and C3. The gain of the filter is as usual decided by op-amp i.e. the resistance R1 and Rf. The frequency response is shown in figure.

At the cut off frequency fH, the gain is 0,707 Af i,e. 3 dB down from its 0 Hz level. After, fH ( f > fH ) the gain rolls off at a frequency rate of 40 dB/decade,. Hence, the slope of the ‘response after, fH is – 40 dB/decade.

2.17 Second order Low Pass Butterworth Filters The second order high pass Butterworth filter produces a gain roll off at the rate of + 40 dB/decade in the stop band. This filter also can be realized by interchanging the positions of resistors and capacitors in a second order low pass Butterworth filter. The figure shows the second order high pass Butterworth filter. The analysis, design and the scaling procedures for this filter is exactly same as that of second order low pass Butterworth filter.

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Unit-2.B Linear Applications of Op. Amp.

The frequency response of this filter is shown in the figure.

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Unit-2C Linear Applications of Op. Amp.

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Unit-2.C Linear Applications of Op. Amp. 2.1

Compare active filter and passive filter 1 2 3 4 5 6 7

2.2

Active Filter Passive Filter It uses active devices like It uses passive devices like Transistor, Op. Amps. etc. Resistor, Capacitor, Inductor etc. Frequency is response more Frequency is response less sharper sharper. More expansive Less expensive More complex Less complex More sensitive Comparatively less sensitive Higher Gain. Lower Gain Also gain is adjustable. High Q factor Low Q factor

Explain the concept of P, PI and PID controller using Op. Amp. OR Explain Proportional, Proportional Integral and Proportional Integral Derivative controller.

Analog Electronics Process Controllers must be capable of providing one or more of the three main methods of control, namely, Proportional, Integral and Derivative (i)

Proportional Control The simplest form is the proportional control as shown in figure, which has an overall voltage gain of

Here Op. Amp. is connected in inverting mode. Hence, for the given circuit

So output voltage is proportional to the input voltage. The value of the proportional band of the controller is modified by changing the value of R1 and R2. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.C Linear Applications of Op. Amp (ii)

Integral Control Pure integral action/control is obtained from the circuit shown in figure. Integral circuit is often used in conjunction with proportional control (twoterm control or PI control) as a means of reducing the steady state deviation or offset.

(iii)

Proportional Integral Control (PI Controller) Figure shows Proportional Integral control circuit. It is a realistic version of proportional plus integral controller. The magnitude of the proportional gain factor is given by R2/R1 and the integral action time is R1C1.

The integral action time of a proportional plus integral controller can best be explained in terms of the output waveform for a step change in the input signal shown in figure.

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Unit-2.C Linear Applications of Op. Amp. Since the Op. Amp. in figure is connected as inverting amplifier, a negative step change in input voltage is applied to produce a positive output voltage change. As soon as the step change is applied, the Proportional action of the controller causes the output voltage to change suddenly by Y 1 volts. The action of the integrator capacitor then causes the controller output voltage to begin to rise at a steady rate and it takes a time known as the integral action time for the output voltage to rise by a further Y1 volts. (iv)

Proportional Derivative Control (PD Controller) A basic proportional plus derivative controller is shown in figure, the Proportional action being provided by R 1 and R2 , while the derivative action is provided by capacitor C2 together with R3.

The derivative action time of a P plus D action controller can be explained in terms of the output waveform of the controller for a ramp/constant change in input signal, shown in figure.

Since the op-amp is inverting, a negative ramp signal is applied in order to get a positive going output voltage. As soon as the change in the input signal is applied, the derivative action of capacitor C2 causes the output voltage to suddenly change by Y2 volts. The Proportional action to the controller causes the output voltage to rise at a constant rate, and takes a time known as the derivative action time for the output voltage to rise by a further Y 2 volts. In this case, the derivative action time is given by R 1C2 of the controller. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.C Linear Applications of Op. Amp (v)

Proportional Integral Derivative Control (PID Controller) The block diagram of a 3-term controller providing P + I + D (PID) control is shown in figure.

Resistors R 1 and R2 provide the basic Proportional control, while capacitor C1 introduces integral control and capacitor C2 derivative control 2.3

What is the need of frequency compensation network in op. Amp.?

Consider the inverting amplifier circuit and waveforms in figure(a). The signal voltage (vs) is amplified by a factor R2/R1, and phase shifted through -180°. The Operational Amplifier Circuit Stability is redrawn in figure(b) to illustrate the fact that the output voltage (vo) is divided by the feedback network to produce the feedback voltage (v).

For an ac voltage (v) at the op-amp inverting input terminal in figure(b), the amplified output is vo = Avv, is as shown. The output is divided by the feedback factor [B = R1/(R1 + R2)], and fed back to the input. An additional -180° of phase shift can Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.C Linear Applications of Op. Amp. occur within the op-amp at high frequencies, and this causes v to be in-phase with vo, as illustrated. Thus, the feedback voltage can be exactly equal to and in phase with the voltage (v) at the inverting input. In this case, the circuit is supplying its own ac input voltage, and a state of continuous oscillation exists. Because of the feedback network, high-frequency oscillations can occur in many operational amplifier circuits, and when this happens the circuit is termed unstable. Methods/techniques used to stabilize Operational Amplifier Circuit are referred to as frequency compensation techniques. Assuming that the feedback network is purely resistive, it adds nothing to the loop phase shift. The loop phase shift is essentially the amplifier phase shift. The phase shift from the inverting input terminal to the output is normally -180°. But at high frequencies there may be additional phase shift caused by circuit capacitances, and the total can approach -360°. When this occurs, the circuit is virtually certain to oscillate. Most currently-available operational amplifiers have internal compensating components to prevent oscillations. In some cases, compensating components must be connected externally to stabilize a circuit.

Graph shows frequency response of uncompensated and compensated Op. Amp. 2.4

Explain Lead/Lag compensator using Op. Amp. OR Explain frequency compensation network. OR Explain Phase-Lag and Phase-Lead Compensation

Lag compensation and lead compensation are two Frequency Compensation methods often employed to stabilize op-amp circuits. The phase-lag network in figure(a) introduces additional phase lag at some low frequency where the op-amp phase shift is still so small that additional phase lag has no effect. It can be shown that at frequencies where XC1 ≫ R2, the voltage v2 lags v1 by as much as 90°. At higher frequencies where XC1 ≪ R2 no significant phase lag Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.C Linear Applications of Op. Amp occurs, and the lag network merely introduces some attenuation. The effect of this attenuation is that the Av f graph is moved to the left, as illustrated in figure (b). Thus, the frequency (fx1) at which AvB = 1 [for a given closed-loop gain (ACL)] is moved to a lower frequency (fx2), as shown. Because fx2 is less than fx1, the phase shift at fx2 is less than that at fx1, and the circuit is likely to be stable.

The network in figure(c) introduces a phase lead. In this network, when XC1 ≫ R1, the voltage v2 leads v1. This phase lead cancels some of the unwanted phase lag in the operational amplifier θf graph as shown in figure(d), thus rendering the circuit more stable. Phase-lag and phase-lead networks are both used internally to Frequency Compensation methods op-amp circuits. Both types of circuit can also be used externally 2.5

Explain IC Voltage regulators in detail. OR Explain three terminal voltage regulators in detail.

A Voltage Regulator is a device or a circuit that is responsible for providing a steady DC Voltage to an electronic load. IC Voltage Regulator uses integrated circuits for voltage regulation. Block diagram of a power supply which uses IC regulator is as shown in figure.

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Unit-2.C Linear Applications of Op. Amp.

Advantages of IC voltages regulators: (1) (2) (3) (4) (5) (6) (7) (8)

(9)

The IC voltage regulator is conveniently used for local regulation. The IC voltage regulator is easy to use. It is most efficient and reliable. The IC voltage regulator is versatile. It is very cheap due to mass production and easily available. It is compact in size, rugged and light in weight. The power supply design becomes easy and quick. It is easily manufactured with features like built in protection, programmable output, current or voltage boosting, internal protections such as thermal shutdown, floating operation to facilitate higher output voltage etc. It has fast transient response.

IC voltage regulators/Three terminal regulator/3-T regulars: Regulation/regulator circuits in integrated circuit form are most widely used. They are treated as a single device with associated components. These are generally three terminal devices that provide a positive or negative output. IC regulators contain the circuitry for: -

reference source comparator amplifier control device overload protection

The following figure shows the block diagram of three terminal IC regulator. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-2.C Linear Applications of Op. Amp It has three terminals. (1) Input voltage (Vin) (2) Output voltage (Vo) (3) Common terminal (Ground).

Several types of both linear (series and shunt) and switching regulators are available in integrated circuit (IC) form. Generally, the linear regulators are three-terminal devices that provides either positive or negative output voltages that can be either fixed or adjustable Fixed voltage regulator: The fixed voltage regulator has an unregulated dc input voltage V i applied to one input terminal, a regulated output dc voltage V o from a second terminal, and the third terminal connected to ground. Fixed-Positive Voltage Regulator The series 78XX regulators are the three-terminal devices that provide a fixed positive output voltage.

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Unit-2.C Linear Applications of Op. Amp. Some of the fixed positive regulator in 78XX series are given in table. IC Part

Output Voltage (V)

Minimum Vi (V)

7805

+5

+7.3

7806

+6

+8.3

7808

+8

+10.5

7810

+10

+12.5

7812

+12

+14.5

Fixed-Negative Voltage Regulator: The series 79XX regulators are the three-terminal IC regulators that provide a fixed negative output voltage. This series has the same features and characteristics as the series 78XX regulators except the pin numbers are different.

Some of the fixed negative regulator in 79XX series are given in table. IC Part

Output Voltage (V)

Minimum Vi (V)

7905

-5

- 7.3

7906

-6

- 8.3

7908

-8

- 10.5

7910

- 10

- 12.5

7912

- 12

- 14.5

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Unit-2.C Linear Applications of Op. Amp Pin configuration of 78XX and 79XX series regulator

Adjustable-Voltage Regulator: Voltage regulators are also available in circuit configurations that allow to set the output voltage to a desired regulated value. The LM317 is an example of an positive adjustable-voltage regulator, can be operated over the range of voltage from 1.2 to 37 V.

The three terminals are Vin, Vout, and Adjustment(adj). The LM337 series of voltage regulators are a complement of LM317 series. They are negative adjustable voltage regulators. These negative voltage regulators are available in the same voltage and current options as the positive adjustable voltage regulator LM317.

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Unit-2.C Linear Applications of Op. Amp. Pin configuration of LM317 and LM337 adjustable regulators

Switching-Voltage Regulator: The switching regulator is more efficient than the linear series or shunt type. This type regulator is ideal for high current applications since less power is dissipated. Voltage regulation in a switching regulator is achieved by the on and off action, limiting the amount of current flow based on the varying line and load conditions. With switching regulators 90% efficiencies can be achieved In switching regulator, the transistor acts as a switch. When the transistor is off (switch is open), no current flows, therefore no power dissipation takes place. When the transistor is on (switch is closed), high current flows but VCE becomes low and therefore power dissipation is less.

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Unit-3 Non Linear Applications of Op. Amp.

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Unit-3. Non-Linear Applications of Op. Amp. 3.1

What is Comparator? Explain basic comparator circuit. OR What is Comparator? Draw the circuit for Inverting and Non-inverting comparator using Op. Amp. and explain it with necessary waveform.

The Op Amp comparator is a circuit with two inputs and a single output. The two inputs can be compared with each other, i.e. one of them can be considered a reference terminal. When Op. Amp. is used without feedback (open loop configuration), the amplifier output is usually in one of its saturated states. When the non-inverting input is higher or greater than the inverting input voltage, the output of the comparator is high ( +Vsat ) and when the non-inverting voltage is less than the inverting voltage then output of the Comparator is low ( -Vsat ). Non-inverting Comparator: The Op. Amp. Comparator circuit shown in figure, consists of a fixed reference voltage (Vref) applied to the inverting input terminal and a sinusoidal signal Vin applied to the non-inverting terminal.

As discussed earlier, when Vin is greater than Vref the output voltage goes to positive saturation, i.e. Vout = + Vsat = + Vcc. and when Vin is less than Vref, the output goes to negative saturation, i.e. Vout = – Vsat = – VEE. Hence the output changes from one saturation level to another. Since the sinusoidal input is applying to the non-inverting terminal, this circuit is called the non-inverting comparator. Diodes D1 and D2, shown in figure are used to protect the Op. Amp. from damage due to excessive input voltage (Vin). The difference input voltage (V id) of the Op. Amp. is clamped to either + 0.7 V or - 0.7 V because of the diodes D 1 and D2. Hence the diodes are called clamping diodes. Necessary input and output waveforms are also shown in figure, in case of V ref is positive as well as negative.

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Unit-3. Non-Linear Applications of Op. Amp.

When Vref is Positive

When Vref is Negative

Inverting Comparator: Inverting comparator can also be obtained by applying the sinusoidal input to the inverting terminal and reference voltage to non-inverting terminal.

Necessary input and output waveforms are also shown in figure, in case of V ref is positive as well as negative for inverting comparator.

When Vref is Positive Prof. Manoj N. Popat (E.C. Dept.)

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Unit-3. Non-Linear Applications of Op. Amp. Characteristics and Application of Comparator Characteristics: Three important characteristics of comparator are (i) Speed of operation (ii) Accuracy (iii) Compatibility of output Applications (i) (ii) (iii) (iv) (v) (vi) (vii)

3.2

Signal generation & transmission Automatic control & measurement A/D converter Voltage level detector Window detector/comparator V to F converter Switching regulator

Explain Zero Crossing Detector.

The zero crossing detector circuit in figure is seen to be simply an operational amplifier with the inverting input grounded and the signal applied to the non inverting input. When the input is above ground level the output is saturated at its positive maximum, and when the input is below ground the output is at its negative maximum level. This is illustrated by the input and output waveforms which show that the output voltage changes from one extreme to the other each time the input voltage crosses zero. The input waveform could have any shape (sinusoidal, pulse, ramp, etc.), and the output will always be a rectangular-type wave.

Input and output waveform for Zero crossing detector is as shown in figure Prof. Manoj N. Popat (E.C. Dept.)

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Unit-3. Non-Linear Applications of Op. Amp.

If the op-amp non-inverting input is grounded and the signal is applied to the inverting input then output is negative when the input is above ground, and vice versa. Because of the waveform inversion, this circuit is often termed an inverter

Input and output waveform for Zero crossing detector is as shown in figure.

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Unit-3. Non-Linear Applications of Op. Amp. 3.3

Explain Window Detector/Window comparator circuit

A window detector circuit, also called window comparator circuit or dual edge limit detector circuits. It is used to determine whether an unknown input is between two precise reference threshold voltages. It employs two comparators to detect over-voltage or undervoltage. Each single comparator detects the common input voltage against one of two reference voltages, normally upper threshold and lower threshold. Outputs detect whether the input is in the range of the so-called "window" between upper and lower threshold reference voltage.

For any value of input voltage Vin > VLT and Vin < VUT, both comparator’s output is high, hence output voltage is High. But for any value of input voltage Vin < VLT lower comparator generates output low and upper comparator generates output high, so output voltage V out is low. In the same way for any value of Vin > VUT, output of lower comparator is high but output of upper comparator is low, so output voltage V out is low. Hence for any value of Vin < VLT and Vin > VUT, output voltage Vout is Low as shown in graph. Transfer characteristic of window detector is as shown in figure.

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Unit-3. Non-Linear Applications of Op. Amp. 3.3

Explain Schmitt Trigger circuit. OR Draw circuit for Inverting Schmitt Trigger. Explain it with necessary equation and also draw Hysteresis loop,

Schmitt trigger is a comparator circuit implemented by applying positive feedback to the non inverting input of a comparator or differential amplifier. It is an active circuit which converts an analog input signal to a digital output signal. The circuit is named a "trigger" because the output retains its value until the input changes sufficiently to trigger a change. In Inverting configuration, when the input is higher than a certain chosen threshold (Upper Threshold), the output is Low. When the input is lower chosen threshold (Lower Threshold), the output is High, and when the input is between the two levels, the output retains its value. This dual threshold action is called hysteresis. A Schmitt Trigger is a circuit which converts an irregular shaped waveform to a square wave or pulse. This circuit is also called as a squaring circuit. A Schmitt trigger circuit is as shown in figure.

The input voltage Vin triggers (changes the state of) output V out every time it exceeds certain voltage levels called upper threshold V ut and lower threshold voltage Vlt as shown in figure. These threshold voltages can be obtained by using the voltage divider R 1 and R2, where the voltage across R1 is fed back to the (+) input. The voltage across R 1 is a variable reference threshold voltage that depends on the value and the polarity of the output voltage. When Vout = +Vsat, the voltage across R1 is called the upper threshold voltage, Vut.

On the other hand, when Vout = -Vsat, the voltage across R1 is referred to as lower threshold voltage, Vlt. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-3. Non-Linear Applications of Op. Amp.

The hysteresis voltage is, equal to the difference between V ut and Vlt. Therefore,

Input and output waveform for Schmitt trigger circuit is as shown in figure.

A graph of output voltage (V o) versus input voltage (Vi) can be plotted for an inverting Schmitt Trigger Circuit Diagram, as shown in figure. This input/output characteristic is called Hysteresis loop.

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Unit-3. Non-Linear Applications of Op. Amp. 3.5

Explain Square wave generator circuit using Op. Amp.

The Square Wave Generator using Op Amp. means the Astable Multivibrator circuit using op-amp. It generates the square wave of required frequency. The figure shows the square wave generator using Op. Amp. The circuit has a time dependent elements such as resistance and capacitor to set the frequency of oscillation. As shown in the figure resistors R1 and R2 form an positive feedback.

When Vo is at +Vsat, the feedback voltage V 1 is called the upper threshold voltage V UT and is given as

---- (1) When Vo is at -Vsat, the feedback voltage V1 is called the lower threshold voltage VLT and is given as

---- (2) When power is turn ON, output is assumed to be +V sat because of positive feedback. With Vo= +Vsat we have V1 = VUT and capacitor starts charging towards +V sat through the feedback path provided by the resistor R f at the inverting input. This is illustrated in figure. As long as the capacitor voltage V c is less than VUT, the output voltage remains at +Vsat As soon as Vc charges to a value slightly greater than VUT, the inverting (-) input becomes higher than non inverting (+) input. This switches the output voltage from +Vsat to -Vsat and we have V1 = VLT which is negative with respect to ground. As V o switches to -Vsat, capacitor starts discharging via Rf, as shown in the figure. Prof. Manoj N. Popat (E.C. Dept.)

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Unit-3. Non-Linear Applications of Op. Amp.

The current I discharges capacitor to 0 V and recharges capacitor to V LT. When Vc becomes slightly more negative than the feedback voltage V LT, the non inverting (+) input is higher than inverting (-) input. This switches the output voltage from -Vsat to +Vsat and we have V1 = VUT again which is positive with respect to ground.. As a result, capacitor now has a initial charge equal to V LT. The capacitor will discharge from VLT to O Volt and then recharge to VUT, and the process is repeating. Once the, initial cycle is completed, the waveforms become periodic, as shown in the figure. The frequency of oscillation is determined by the time it takes the capacitor to charge from VUT to VLT and vice versa. Time period of output waveform is given by equation

---- (3)

Hence frequency of output waveform is given by equation

--- (4)

in equation (4) if R2 = 1.16R1 then

---- (5)

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Unit-3. Non-Linear Applications of Op. Amp. 3.6

Explain Triangular wave generator circuit using Op. Amp.

As we know that output of integrator is a Triangular Wave, if its input is a square wave. This means that a Triangular Wave Generator Using Op Amp can be formed by simply connecting an integrator to the square wave generator as shown in the figure.

Basically, triangular wave is generated by alternatively charging and discharging a capacitor with a constant current. This is achieved by connecting integrator circuit at the output of square wave generator. Assume that V’ is high at +V sat. This forces a constant current (+Vsat/R3) through C (left to right) to drive V o negative linearly. When V’ is low at —Vsat, it forces a constant current (- Vsat /R3) through C (right to left) to drive

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Unit-3. Non-Linear Applications of Op. Amp. Vo positive, linearly. The frequency of the triangular wave is same as that of square wave. This is illustrated in figure. Although the amplitude of the square wave is constant (± Vsat), the amplitude of the triangular wave decreases with an increase in its frequency, and vice versa. This is because the reactance of capacitor decreases at high frequencies and increases at low frequencies. In practical circuits, resistance R4 is connected across C to avoid the saturation problem at low frequencies as in the case of practical integrator as shown in the figure.

Time period of output waveform is given by equation

---- (1)

Hence frequency of output waveform is given by equation

--- (2)

in equation (4) if R2 = 1.16R1 then ---- (3)

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Unit-3. Non-Linear Applications of Op. Amp. 3.7

Explain precision Half wave rectifier circuit using Op. Amp.

Rectifier circuits can be also implemented with a diode/diodes (half wave rectifier or full wave rectifier). The major limitations of these Rectifiers circuits is that they cannot rectify voltages below VD = 0.7 V, the cut-in voltage of the diode. Hence

Due to this, output of the conventional rectifier is distorted. To achieve Precision Rectifiers we need a circuit that keeps V o equal to Vi for Vi > O V. This can be achieved by using Op. Amp. along with the diodes and these circuits are called Precision Rectifiers. These are used to precisely rectify voltages having amplitudes less than 0.7 V. Precision Half Wave Rectifiers There are two types of precision half wave rectifiers available, (i) Non inverting half wave rectifier (ii) Inverting half wave rectifier Non inverting Half Wave Rectifier: Figure shows precision half wave rectifier. It consists of non inverting amplifier with diode D1 in the feedback loop of an Op. Amp

The analysis of this circuit can be done considering two distinct cases for Vi > 0 V and Vi < 0 V CASE 1 : Vi > O V : For closed loop Op. Amp. Vp = Vn, due to virtual ground.

Prof. Manoj N. Popat (E.C. Dept.)

Analog & Digital Electronics (3130907)

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Unit-3. Non-Linear Applications of Op. Amp. When Vi > 0, Op. Amp. tries to keep Vo = Vn = Vp = Vi (Voltage follower circuit) and it does this because forward biasing diode provides closed loop feedback path. The voltage drop across forward bias diode V D = 0.7 V. To accommodate the voltage drop across diode the Op. Amp. swings about 0.7 V higher than Vo, as shown in the figure. CASE 2 : Vi < O V : When Vi < O V, diode D1 is reverse biased and the Op. Amp. is working in the open loop, as shown in the figure. Therefore, Op. Amp. is no longer capable of keeping Vn = Vp. With no current through resistance R we have V 0 = 0.

The input and output waveforms are shown in figure

Inverting Half Wave Rectifier Figure shows another popular circuit, inverting half-wave rectifier. It consists of two diodes and two resistors and Op. Amp. is connected in the inverting configuration.

Prof. Manoj N. Popat (E.C. Dept.)

Analog & Digital Electronics (3130907)

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Unit-3. Non-Linear Applications of Op. Amp. CASE 1: Vi > 0 : Recalling virtual ground concept we can say that V p = Vn = O V. For Vi > 0, Vi is positive with respect to Vn and hence current through R 1 flows from left to right. Only one path for this current to flow is through diode D 1. Hence diode D1 is forward biased and diode D2 is reverse biased. As current flow through R 2 is zero, Vo = Vn = O V. CASE 2 : Vi < 0 : For Vi < 0, Vi is negative with respect to V n and hence current through R1 flows from right to left. Only one path for this current to flow is through diode D 2 and resistor R2, indicating that V0 > Vn . Hence diode D1 is OFF, and diode D 2 is ON. With these diode states, circuit acts like an inverting amplifier and output voltage is given as

If R1 and R2 are made equal, then we can write Vo = -Vi The input and output waveforms are shown in figure.

Non inverting Half Wave Rectifier which rectifies negative half cycle:

Prof. Manoj N. Popat (E.C. Dept.)

Analog & Digital Electronics (3130907)

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Unit-3. Non-Linear Applications of Op. Amp.

Precision Full Wave Rectifier:

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Analog & Digital Electronics (3130907)

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Unit-3. Non-Linear Applications of Op. Amp. 3.8

Explain Peak Detector circuit using Op. Amp

Square, Triangular, Sawtooth and pulse waves are typical examples of non-sinusoidal waveforms. A conventional ac voltmeter cannot be used to measure these sinusoidal waveforms because it is designed to measure the RMS value of the pure sine wave. One possible solution to this problem is to measure the peak values of the non-sinusoidal waveforms. Peak detector measures the +ve peak value of the square wave input.

During the positive half cycle of Vin: The output of the Op. Amp. drives D1 in Forward bias, Charging capacitor C to the positive peak value V p of the input volt Vin. During the negative half cycle of Vin: D1 is reverse biased and voltage across C is retained. The only discharge path for C is through RL. For proper operation of the circuit, the charging time constant (CR d ) and discharging time constant (CRL) must satisfy the following condition. CRd = 10T Where RL = Load Resistor. Resistor R is used to protect the op-amp against the excessive discharge currents. Diode D2 conducts during the –ve half cycle of Vin and prevents the op-amp from going into negative saturation. Negative peak of the input signal can be detected simply by reversing diode D 1 and D2.

Prof. Manoj N. Popat (E.C. Dept.)

Analog & Digital Electronics (3130907)

16

Unit 4-Part 1 : Boolean Algebra Table of Contents 3.1

Introduction .......................................................................................................................................3

3.1.1 Advantages of Boolean Algebra..................................................................................................................3 3.2

Boolean Algebra Terminology .............................................................................................................3

3.3

Logic Operators...................................................................................................................................4

3.4

Axioms or Postulates ..........................................................................................................................4

3.5

Boolean Algebra’s Laws and Theorems ................................................................................................4

3.5.1

Reduction of Boolean Expression ...................................................................................................... 10

3.5.1.1 De-Morganized the following functions ............................................................................................ 10 3.5.1.2 Reduce the following functions using Boolean Algebra’s Laws and Theorems ................................ 10 3.6

Different forms of Boolean Algebra ................................................................................................... 12

3.6.1

Standard Form ................................................................................................................................... 12

3.6.1.1 Standard Sum of Product (SOP) ......................................................................................................... 12 3.6.1.2 Standard Product of Sum (POS) ......................................................................................................... 12 3.6.2

Canonical Form .................................................................................................................................. 12

3.6.2.1 Sum of Product (SOP) ........................................................................................................................ 12 3.6.2.2 Product of Sum (POS) ........................................................................................................................ 13 3.6.2

MINTERMS & MAXTERMS for 3 Variables ......................................................................................... 14

3.6.3

Conversion between Canonical Forms .............................................................................................. 14

3.6.3.1 Convert to MINTERMS ....................................................................................................................... 14 3.6.3.2 Convert to MAXTERMS ...................................................................................................................... 15 3.7

Karnaugh Map (K-Map) ..................................................................................................................... 17

3.7.1

2 Variable K-Map ............................................................................................................................... 17

3.7.1.1 Mapping of SOP Expression ............................................................................................................... 17 3.7.1.2 Mapping of POS Expression ............................................................................................................... 17 3.7.1.3 Reduce Sum of Product (SOP) Expression using K-Map .................................................................... 18 3.7.1.4 Reduce Product of Sum (POS) Expression using K-Map .................................................................... 18 3.7.2

3 Variable K-Map ............................................................................................................................... 18

3.7.2.1 Mapping of SOP Expression ............................................................................................................... 18 |EE & EC Department

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Unit 4-Part 1 : Boolean Algebra 3.7.2.2 Mapping of POS Expression ............................................................................................................... 18 3.7.2.3 Reduce Sum of Product (SOP) Expression using K-Map .................................................................... 19 3.7.2.4 Reduce Product of Sum (POS) Expression using K-Map .................................................................... 19 3.7.3

4 Variable K-Map ............................................................................................................................... 20

3.7.3.1 Mapping of SOP Expression ............................................................................................................... 20 3.7.3.2 Mapping of POS Expression ............................................................................................................... 20 3.7.3.3 Looping of POS Expression ................................................................................................................ 21 3.7.3.4 Reduce Sum of Product (SOP) Expression using K-Map .................................................................... 23 3.7.3.5 Reduce Product of Sum (POS) Expression using K-Map .................................................................... 24 3.7.3.6 Reduce SOP & POS Expression with Don’t Care Combination using K-Map ..................................... 24 3.7.4

5 Variable K-Map ............................................................................................................................... 25

3.7.4.1 Mapping of SOP Expression ............................................................................................................... 25 3.7.4.2 Reduce Sum of Product (SOP) Expression using K-Map .................................................................... 25 3.7.4.3 Reduce Product of Sum (POS) Expression using K-Map .................................................................... 26 3.8

Converting Boolean Expression to Logic Circuit and Vice-Versa........................................................... 26

3.9

NAND and NOR Realization/Implementation ..................................................................................... 28

3.10

Tabulation / Quine-McCluskey Method ............................................................................................. 29

3.11

GTU Questions .................................................................................................................................. 33

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Unit 4-Part 1 : Boolean Algebra 3.1

Introduction 

Inventor of Boolean algebra was George Boole (1815 - 1864).



Designing of any digital system there are three main objectives; 1) Build a system which operates within given specifications 2) Build a reliable system 3) Minimize resources

   

Boolean algebra is a system of mathematical logic. Any complex logic can be expressed by Boolean function. Boolean algebra is governed by certain rules and laws. Boolean algebra is different from ordinary algebra & binary number system. In ordinary algebra; A + A = 2A and AA = A2, here A is numeric value. In Boolean algebra; A + A = A and AA = A, here A has logical significance, but no numeric significance.



Table: Difference between Binary, Ordinary and Boolean system

Binary number system 1+1=10  

Ordinary no. system 1+1=2 A + A = 2A and AA = A2

Boolean algebra 1+1=1 A + A = A and AA = A

In Boolean algebra, nothing like subtracting or division, no negative or fractional numbers. Boolean algebra represent logical operation only. Logical multiplication is same as AND operation and logical addition is same as OR operation. Boolean algebra has only two values 0 & 1. In Boolean algebra; If A = 0 then A ≠ 1. & If A = 1 then A ≠ 0.

 

3.1.1 Advantages of Boolean Algebra 1. 2. 3. 4. 5. 6. 7.

3.2

Minimize the no. of gates used in circuit. Decrease the cost of circuit. Minimize the resources. Less fabrication area is required to design a circuit. Minimize the designer’s time. Reducing to a simple form. Simpler the expression more simple will be hardware. Reduce the complexity.

Boolean Algebra Terminology 1. Variable

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: The symbol which represent an arbitrary elements of a Boolean algebra is known as variable. e.g. F = A + BC, here A, B and C are variable and it can have value either 1 or 0. | 3130907 – Analog and Digital Electronics

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Unit 4-Part 1 : Boolean Algebra 2. Constant 3. Complement

4. Literal 5. Boolean Function

3.3

: In expression F = A + 1, the first term A is variable and second term 1 is known as constant. Constant may be 1 or 0. : A complement of any variable is represented by a “ ” (BAR) over any variable. e.g. Complement of A is 𝐴. : Each occurrence of a variable in Boolean function either in a noncomplemented or complemented form is called literal. : Boolean expressions are constructed by connecting the Boolean constants and variable with the Boolean operations. This Boolean expressions are also known as Boolean Formula. e.g. F(A, B, C) = (𝐴 + 𝐵) C OR F = (𝐴 + 𝐵) C

Logic Operators 1. AND : Denoted by ∙ (e.g. A AND B = A ∙ B) 2. OR : Denoted by + (e.g. A OR B = A + B) 3. NOT OR Complement : Denoted by “ ” (BAR) or ( )′ (e.g. 𝐴 or (𝐴)′ )

3.4

Axioms or Postulates

Axioms 1 Axioms 2 Axioms 3 Axioms 4

3.5

: : : :

0·0=0 0·1=0 1·0=0 1·1=1

Axioms 5 Axioms 6 Axioms 7 Axioms 8

: 0+0=0 : 0+1=1 : 1+0=1 : 1·1=1

Axioms 9 : Axioms 10 :

1’ = 0 0’ = 1

Boolean Algebra’s Laws and Theorems

1. Complementation Laws:  The term complement simply means to invert, i.e. to change 0’s to 1’s and 1’s to 0’s. Law 1: 0’ = 1 Law 4: If A = 1 then A’ = 0 Law 2: 1’ = 0 Law 5: A’’ = A Law 3: If A = 0 then A’ = 1 2. AND Laws: Law 1: A · 0 = 0 Law 2: A · 1 = A

Law 3: A · A = A Law 4: A · A’ = 0

3. OR Laws: Law 1: A + 0 = A Law 2: A + 1 = 1

Law 3: A + A = A Law 4: A + A’ = 1

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Unit 4-Part 1 : Boolean Algebra 4. Commutative Laws:  Commutative laws allow change in position of AND or OR variables. Law 1: A + B = B + A Proof:



This law can be extended to any numbers of variables for e.g. A+B+C=B+A+C=C+B+A=C+A+B Law 2: A · B = B · A Proof:



This law can be extended to any numbers of variables for e.g. A·B·C=B·A·C=C·B·A=C·A·B 5. Associative Laws:  The associative laws allow grouping of variables. Law 1: (A + B) + C = A + (B + C) Proof:



This law can be extended to any no. of variables for e.g. A + (B + C + D) = (A + B + C) + D = (A + B) + (C + D)

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Unit 4-Part 1 : Boolean Algebra Law 2: (A · B) · C = A · (B · C) Proof:



This law can be extended to any no. of variables for e.g. A · (B · C · D) = (A · B · C) · D = (A · B) · (C · D)

6. Distributive Laws:  The distributive laws allow factoring or multiplying out of expressions. Law 1: A (B + C) = AB + AC Proof:

Law 2: A + BC = (A + B) (A + C) Proof: R.H.S. = (A + B) (A + C) = AA + AC + BA + BC = A + AC + BA + BC = A + BC (∵ A(1 + C + B) = A) = L.H.S.

Law 3: A + A’B = A + B Proof: L.H.S. = A + A’B = (A + A’) (A + B) =A+B = R.H.S.

7. Idempotence Laws:  Idempotence means the same value. Law 1: A · A = A Proof: Case 1: If A = 0  A · A = 0 · 0 = 0 = A Case 2: If A = 1  A · A = 1 · 1 = 1 = A

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Law 2: A + A = A Proof: Case 1: If A = 0  A + A = 0 + 0 = 0 = A Case 2: If A = 1  A + A = 1 + 1 = 1 = A

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Unit 4-Part 1 : Boolean Algebra 8. Complementation Law / Negation Law: Law 1: A · A’ = 0 Proof: Case 1: If A = 0  A · A’ = 0 · 1 = 0 Case 2: If A = 1  A · A’ = 1 · 0 = 0

Law 2: A + A’ = 1 Proof: Case 1: If A = 0  A + A’ = 0 + 1 = 1 Case 2: If A = 1  A + A’ = 1 + 0 = 1

9. Double Negation / Involution Law:  This law states that double negation of a variables is equal to the variable itself. Law: A’’ = A Proof: Case 1: If A = 0  A’’ = 0’’ = 0 = A Case 2: If A = 1  A’’ = 1’’ = 1 = A  

Any odd no. of inversion is equivalent to single inversion. Any even no. of inversion is equivalent to no inversion at all.

10. Identity Law: Law 1: A · 1 = A Proof: Case 1: If A= 1  A · 1 = 1 · 1 = 1 = A Case 2: If A= 0  A · 0 = 0 · 0 = 0 = A

Law 2: A + 1 = 1 Proof: Case 1: If A= 1  A + 1 = 1 + 1 = 1 = A Case 2: If A= 0  A + 0 = 0 + 0 = 0 = A

11. Null Law: Law 1: A · 0 = 0 Proof: Case 1: If A= 1  A · 0 = 1 · 0 = 0 = 0 Case 2: If A= 0  A · 0 = 0 · 0 = 0 = 0

Law 2: A + 0 = A Proof: Case 1: If A= 1  A + 0 = 1 + 0 = 1 = A Case 2: If A= 0  A + 0 = 0 + 0 = 0 = A

12. Absorption Law: Law 1: A + AB = A Proof: L.H.S. = A + AB = A (1 + B) = A (1) =A = R.H.S. |EE & EC Department

Law 2: A (A + B) = A Proof: L.H.S. = A (A + B) = A · A + AB = A + AB = A (1 + B) =A = R.H.S. | 3130907 – Analog and Digital Electronics

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Unit 4-Part 1 : Boolean Algebra 13. Consensus Theorem: Theorem 1: A · B + A’C + BC = AB + A’C

= (0 + AC + A’B + BC) (B + C) = ACB+ACC+A’BB+A’BC+BCB+BCC = ABC + AC + A’B + A’BC + BC + BC = ABC + AC + A’B + A’BC + BC = AC (1 + B) + A’B (1 + C) + BC = AC + A’B + BC = AC + A’B ……..……………………(1)

Proof: L.H.S. = AB + A’C + BC = AB + A’C + BC (A +A’) = AB + A’C + BCA + BCA’ = AB (1 + C) + A’C (1 + B) = AB + A’C = R.H.S. 

R.H.S. = (A + B) (A’ + C) = AA’ + AC + BA’ + BC = 0 + AC + BA’ + BC = AC + A’B + BC = AC +A’B ……………………………(2) Eq. (1) = Eq. (2); So, L.H.S = R.H.S.

This theorem can be extended as, AB + A’C + BCD = AB + A’C

Theorem 2: (A + B) (A’ + C) (B + C) = (A + B) (A’ + C) Proof: L.H.S. = (A + B) (A’ + C) (B + C) = (AA’ + AC + A’B + BC) (B + C) 14. Transposition theorem: Theorem: AB + A’C = (A + C) (A’ +B) Proof: R.H.S. = (A + C) (A’ +B) = AA’ + AB + CA’ + CB = 0 + AB + CA’ + CB = AB + CA’ + CB = AB + A’C =L.H.S. 15. De Morgan’s Theorem: Law 1: (A + B)’ = A’ · B’ Proof:

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OR



This theorem can be extended to any no. of variables. (A + B) (A’ + C) (B + C + D) = (A + B) (A’ + C)

(∵ AB + A’C + BC = AB + A’C)

(A + B + C)’ = A’ · B’ · C’

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Unit 4-Part 1 : Boolean Algebra Law 2: (A· B)’ = A’ + B’ Proof:

OR

(A · B · C)’ = A’ + B’ + C’

LHS AB

A B

(AB)’

A

=

(AB)’

B

NAND Gate RHS A’

A

A

A’ + B’

= B’

B

A 0 0 1 0

B 0 1 0 1

AB 0 0 0 1

(AB)’ 1 1 1 0

A’ + B’

B

Bubbled OR

=

A 0 0 1 0

B 0 1 0 1

A’ 1 1 0 0

B’ 1 0 1 0

A’+B’ 1 1 1 0

16. Duality Theorem:  Duality theorem arises as a result of presence of two logic system i.e. positive & negative logic system.  This theorem helps to convert from one logic system to another.  From changing one logic system to another following steps are taken: 1) 0 becomes 1, 1 becomes 0. 2) AND becomes OR, OR becomes AND. 3) ‘+’ becomes ‘·’, ‘·’ becomes ‘+’. 4) Variables are not complemented in the process.

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Unit 4-Part 1 : Boolean Algebra 3.5.1

Reduction of Boolean Expression

3.5.1.1 De-Morganized the following functions (1)

F

=

[(A + B’) (C + D’)]’

(3)

F F F F

= = = =

[(A + B’) (C + D’)]’ (A + B’)’ + (C + D’)’ A’ B’’ + C’D’’ A’B + C’D

F

=

[(AB)’ + A’ + AB]’

F F F F F

= = = = =

[(AB)’ + A’ + AB]’ (AB)’’ · A’’ · (AB)’ ABA (A’ + B’) AB (A’ + B’) ABA’ + ABB’

F

=

[P (Q + R)]’

Sol:

∴ ∴ ∴ ∴ (5)

F

=

[(AB)’ (CD + E’F) ((AB)’ + (CD)’)]’

∴ ∴ ∴

F F F F

= = = =

[(AB)’ (CD + E’F) ((AB)’ + (CD)’)]’ (AB)’’ + (CD + E’F)’ + ((AB)’ + (CD)’)’ AB + [(CD)’ (E’F)’] + [(AB)’’ (CD)’’] AB + (C’ + D’) (E + F’) + ABCD

(4)

F

=

[(P + Q’) (R’ + S)]’

∴ ∴ ∴

F F F F

= = = =

[(P + Q’) (R’ + S)]’ (P + Q’)’ + (R’ + S)’ P’Q’’ + R’’S’ P’Q + RS’

(6)

F

=

[[(A + B)’ (C + D)’]’ [(E + F)’ (G + H)’]’]’

F F F F

= = = =

[[(A + B)’ (C + D)’]’ [(E + F)’ (G + H)’]’]’ [(A + B)’ (C + D)’]’’ + [(E + F)’ (G + H)’]’’ [(A + B)’ (C + D)’] + [(E + F)’ (G + H)’] A’B’C’D’ + E’F’G’H’

Sol:

Sol: ∴ ∴ ∴

(2)

Sol:

Sol:

Sol:

F F F

= = =

[P (Q + R)]’ P’ + (Q + R)’ P’ + Q’ R’

∴ ∴ ∴

3.5.1.2 Reduce the following functions using Boolean Algebra’s Laws and Theorems (1)

F

=

A + B [ AC + (B + C’)D ]

F

=

A [ B + C’ (AB + AC’)’ ]

F F F F F F F F F

= = = = = = = = =

A [ B + C’ (AB + AC’)’ ] A [ B + C’ (AB)’ (AC’)’ ] A [ B + C’ (A’ + B’) (A’ + C) ] A [ B + (A’ C’ + B’ C’) (A’ + C) ] A [ B + (A’ C’A’ + B’ C’A’) (A’ C’ C + B’ C’ C) ] A [ B + (A’C’ + B’ C’A’) (0 + 0) ] A [ B + A’C’ ( 1 + B’) ] AB + A’AC’ AB

Sol:

Sol: ∴ ∴ ∴ ∴ ∴ ∴

(2)

F F F F F F F

= = = = = = =

A + B [ AC + (B + C’)D ] A + B [ AC + (BD + C’D) ] A + ABC + BBD + BC’D A + ABC + BD + BC’D A (1 + BC) + BD (1 + C’) A (1) + BD (1) A + BD

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∴ ∴ ∴ ∴ ∴ ∴ ∴ ∴

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Unit 4-Part 1 : Boolean Algebra (3) Sol:

F

=

(A + (BC)’)’ (AB’ + ABC)

F F F F F F

= = = = = =

(A + (BC)’)’ (AB’ + ABC) (A’ (BC)’’) (AB’ + ABC) (A’BC) (AB’ + ABC) A’BCAB’ + A’BCABC 0+0 0

F

=

[(A + B’) (A’ + B’)]+ [(A’ + B’) (A’ + B’)]

∴

F F

= =

∴ ∴ ∴ ∴

F F F F

= = = =

[(A + B’) (A’ + B’)] + [(A’ + B’) (A’ + B’)] [AA’ + AB’ + B’A’ + B’B’] + [A’A’ + A’B’ + B’A’ + B’B’] [0 + AB’ + A’B’ + B’] + [A’ + A’B’ + B’] [B’ (A + A’ + 1)] + [A’ + B’(1)] B’ + A’ + B’ A’ + B’

(7) Sol:

F

=

(B + BC) (B + B’C) (B + D)

(8)

F F F F F F

= = = = = =

(B + BC) (B + B’C) (B + D) (BB + BB’C + BBC + BCB’C) (B + D) (B + 0 + BC + 0) (B + D) B (B + D) (∵B + BC = B(1 + C) = B) B + BD (∵B (B + D) = BB + BD) B (∵B + BD = B (1 + D))

Sol:

F

=

AB + AB’C +BC’

F F F F F F

= = = = = =

AB + AB’C +BC’ A (B + B’C) + BC’ A (B + B’) (B + C) + BC’ AB + AC + BC’ { ∵ B + B’ = 1} CA + C’B + AB CA + C’B { ∵ 𝑐𝑜𝑛𝑠𝑒𝑛𝑠𝑢𝑠 𝑡ℎ𝑒𝑜𝑟𝑒𝑚 }

∴ ∴ ∴ ∴ ∴ (5) Sol:

∴ ∴ ∴ ∴ ∴ (9) Sol: ∴ ∴ ∴ ∴ ∴

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(4) Sol:

F

=

[(A + B) (A’ + B)] + [(A + B) (A + B’)]

F F F F F F

= = = = = =

[(A + B) (A’ + B)] + [(A + B) (A + B’)] [AA’ + AB + BA’ + BB] + [AA + AB’ + BA + BB”] [0 + AB + A’B + B] + [A + AB’ + AB + 0] [B (A + A’ + 1)] + [A (1 + B’ + B)] B+A A+B

F

=

(A + B) (A + B’) (A’ + B) (A’ + B’)

∴

F F

= =

∴ ∴ ∴ ∴

F F F F

= = = =

(A + B) (A + B’) (A’ + B) (A’ + B’) (AA + AB’ + BA + BB’) (A’A’ + A’B’ + BA’ + BB’) [A (1+ B’ + B)] [A’ (1 + B’ + B)] [A(1)] [A’(1)] AA’ 0

∴ ∴ ∴ ∴ ∴ (6) Sol:

F = AB’C + B + BD’ + ABD’ + A’C Reduce the function to minimum no. of literals.

F = AB’C + B + BD’ + ABD’ + A’C ∴ F = AB’C + B (1 + D’ + AD’) + A’C ∴ F = AB’C + B + A’C ∴ F = C (A’ + AB’) + B ∴ F = C (A’ + A) (A’ + B’) + B ∴ F = C (1) (A’ + B’) + B ∴ F = C (A’ + B’) + B ∴ F = A’C + CB’ + B ∴ F = A’C + (C + B) (B’ + B) ∴ F = A’C + (B + C) (1) ∴ F = A’C + B + C ∴ F = C (1 + A’) + B ∴ F = B+C Here, 2 literals are present B & C.

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Unit 4-Part 1 : Boolean Algebra 3.6

Different forms of Boolean Algebra 

3.6.1    

There are two types of Boolean form 1) Standard form 2) Canonical form Standard Form Definition: The terms that form the function may contain one, two, or any number of literals. i.e. each term need not to contain all literals. So standard form is simplified form of canonical form. A Boolean expression function may be expressed in a nonstandard form. For example the function: F = (A + C) (AB’ + D’) Above function is neither sum of product nor in product of sums. It can be changed to a standard form by using distributive law as below; F = AB’ + AD’ + AB’C + CD’ There are two types of standard forms: (i) Sum of Product (SOP) (ii) Product of Sum (POS).

3.6.1.1 Standard Sum of Product (SOP) 



3.6.2

SOP is a Boolean expression containing AND terms, called product terms, of one or more literals each. The sum denote the ORing of these terms. An example of a function expressed in sum of product is: F = Y’ + XY + X’YZ’

3.6.1.2 Standard Product of Sum (POS) 



The OPS is a Boolean expression containing OR terms, called sum terms. Each terms may have any no. of literals. The product denotes ANDing of these terms. An example of a function expressed in product of sum is: F = X (Y’ + Z) (X’ + Y + Z’ + W)

Canonical Form  Definition: The terms that form the function contain all literals. i.e. each term need to contain all literals.  There are two types of canonical forms: (i) Sum of Product (SOP) (ii) Product of Sum (POS).

3.6.2.1 Sum of Product (SOP)  A canonical SOP form is one in which a no. of product terms, each one of which contains all the variables of the function either in complemented or non-complemented form, summed together.  Each of the product term is called “MINTERM” and denoted as lower case ‘m’ or ‘Ʃ’.  For minterms, Each non-complemented variable  1 & Each complemented variable  0  For example, 1. XYZ = 111 = m7 3. P’Q’R’ = 000 = m0 2. A’BC = 011 = m3 4. T’S’ = 00 = m0 |EE & EC Department

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Unit 4-Part 1 : Boolean Algebra 3.6.2.1.1 Convert to MINTERM (1)

F

=

P’Q’ + PQ

(2)

F

=

X’Y’Z + XY’Z’ + XYZ

F F F

= = =

001 + 100 + 111 m1 + m4 + m7 Σm(1,4,7)

Sol:

Sol: ∴ ∴ (3)

F F F

= = =

00 + 11 m0 + m3 Σm(0,3)

F

=

XY’ZW + XYZ’W’ + X’Y’Z’W’

F F F

= = =

1011 + 1100 + 0000 m11 + m12 + m0 Σm(0,11,12)

∴ ∴

Sol:

∴ ∴

3.6.2.2 Product of Sum (POS) 

A canonical POS form is one in which a no. of sum terms, each one of which contains all the variables of the function either in complemented or non-complemented form, are multiplied together. Each of the product term is called “MAXTERM” and denoted as upper case ‘M’ or ‘Π’. For maxterms, Each non-complemented variable  0 & Each complemented variable  1 For example, 1. X’+Y’+Z = 110 = M6 2. A’+B+C’+D = 1010 = M10

  

3.6.2.2.1 Convert to MAXTERM (1)

F

=

(P’+Q)(P+Q’)

(3)

F

=

(A’+B+C)(A+B’+C)(A+B+C’)

F F F

= = =

(100) (010) (001) M 4 M2 M1 ΠM(1,2,4)

Sol:

Sol: ∴ ∴

(2)

F F F

= = =

(10)(01) M2·M1 ΠM(1,2)

F

=

(X’+Y’+Z’+W)(X’+Y+Z+W’)(X+Y’+Z+W’)

F F F

= = =

(1110)(1001)(0101) M14·M9·M5 ΠM(5,9,14)

∴ ∴

Sol:

∴ ∴

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Unit 4-Part 1 : Boolean Algebra 3.6.2

MINTERMS & MAXTERMS for 3 Variables Table: Representation of Minterms and Maxterms for 3 variables

3.6.3

Conversion between Canonical Forms

3.6.3.1 Convert to MINTERMS 1. F(A,B,C,D) = ΠM(0,3,7,10,14,15) Solution: Take complement of the given function; ∴ F’(A,B,C,D) = ΠM(1,2,4,5,6,8,9,11,12,13) ∴ F’(A,B,C,D) = (M1 M2 M4 M5 M6 M8 M9 M11 M12 M13)’ Put value of MAXTERM in form of variables; ∴ F’(A,B,C,D) = [(A+B+C+D’)(A+B+C’+D)(A+B’+C+D)(A+B’+C+D’)(A+B’+C’+D) (A’+B+C+D)(A’+B+C+D’)(A’+B+C’+D’)(A’+B’+C+D)(A’+B’+C+D’)]’ ∴ F’(A,B,C,D) = (A’B’C’D) + (A’B’CD’) + (A’BC’D’) + (A’BC’D) + (A’BCD’) + (AB’C’D’) + (AB’C’D) + (AB’CD) + (ABC’D’) + (ABC’D) ∴ F’(A,B,C,D) = m1 + m2 + m4 + m5 + m6 + m8 + m9 + m11 + m12 + m13 ∴ F’(A,B,C,D) = Σm(1,2,4,5,6,8,9,11,12,13) In general, Mj’ = mj

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Unit 4-Part 1 : Boolean Algebra 2. F = A + B’C Solution: A  B & C is missing. So multiply with (B + B’) & (C + C’) B’C  A is missing. So multiply with (A + A’). ∴ A = A (B + B’) (C + C’) ∴ A = (AB + AB’) (C +C’) ∴ A = ABC + AB’C + ABC’ + AB’C’ And, ∴ So, ∴ ∴ ∴ ∴

B’C B’C

= =

B’C (A + A’) AB’C + A’B’C

F F F F F

= = = = =

ABC + AB’C + ABC’ + AB’C’ + AB’C + A’B’C ABC + AB’C + ABC’ + AB’C’ + A’B’C 111 + 101 + 110 + 100 + 001 m7 + m6 + m5 + m4 + m1 Σm(1,4,5,6,7)

3.6.3.2 Convert to MAXTERMS 1. F = Σ(1,4,5,6,7) Solution: Take complement of the given function; ∴ F’(A,B,C) = Σ(0,2,3) ∴ F’(A,B,C) = (m0 + m2 + m3) Put value of MINTERM in form of variables; ∴ F’(A,B,C) = (A’B’C’ + A’BC’ + A’BC)’ ∴ F’(A,B,C) = (A+B+C)(A+B’+C)(A+B’+C’) ∴ F’(A,B,C) = M0·M2·M3 ∴ F’(A,B,C) = ΠM(0,2,3) In general, mj’ = Mj 2. F = A (B + C’) Solution: A  B & C is missing. So add BB’ & CC’ B + C’  A is missing. So add AA’ ∴ A = A + BB’ + CC’ |EE & EC Department

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Unit 4-Part 1 : Boolean Algebra ∴ ∴

A A

= =

(A + B + CC’) (A + B’ + CC’) (A + B + C) (A + B + C’) (A + B’ + C) (A + B’ + C’)

∴

B + C’ B + C’

= =

B + C’ + AA’ (A + B + C’) (A’ + B + C’)

F F F F

= = = =

(A + B + C) (A + B + C’) (A + B’ + C) (A + B’ + C’) (A + B + C’) (A’ + B + C’) (A + B + C) (A + B + C’) (A + B’ + C) (A + B’ + C’) (A’ + B + C’) (000) (001) (010) (011) (101) ΠM(0,1,2,3,5)

3. Solution:

F

=

XY + X’Z

∴

F F F F

= = = =

XY + X’Z (XY + X’) (XY + Z) (X +X’) (Y + X’) (X + Z) (Y + Z) (X’ + Y) (X + Z) (Y + Z)

And,

So, ∴ ∴ ∴

∴ ∴ ∴

X’ + Y  Z is missing. So add ZZ’ X + Z  Y is missing. So add YY’ Y + Z  X is missing. So add XX’ ∴ ∴

X’ + Y X’ + Y

= =

X’ + Y + ZZ’ (X’ + Y + Z) (X’ + Y + Z’)

∴

X+Z X+Z

= =

X’ + Z + YY’ (X + Y + Z) (X + Y’ + Z)

∴

Y+Z Y+Z

= =

Y + Z + XX’ (X + Y + Z) (X’ + Y + Z)

F F F F

= = = =

(X’ + Y + Z) (X’ + Y + Z’) (X + Y + Z) (X + Y’ + Z) (X + Y + Z) (X’ + Y + Z) (100) (101) (000) (010) M4 M5 M0 M 2 ΠM(0,2,4,5)

And,

And,

So, ∴ ∴ ∴

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Unit 4-Part 1 : Boolean Algebra 3.7

Karnaugh Map (K-Map)        

A Boolean expression may have many different forms. With the use of K-map, the complexity of reducing expression becomes easy and Boolean expression obtained is simplified. K-map is a pictorial form of truth table and it is alternative way of simplifying Boolean function. Instead of using Boolean algebra simplification techniques, you can transfer logic values from a Boolean statement or a truth table into a Karnaugh map (k-map) Tool for representing Boolean functions of up to six variables then after it becomes complex. K-maps are tables of rows and columns with entries represent 1’s or 0’s of SOP and POS representations. K-map cells are arranged such that adjacent cells correspond to truth table rows that differ in only one bit position (logical adjacency) K-Map are often used to simplify logic problems with up to 6 variables

No. of Cells = 2 n, where n is a number of variables.  

3.7.1

The Karnaugh map is completed by entering a ‘1’ (or ‘0’) in each of the appropriate cells. Within the map, adjacent cells containing 1's (or 0’s) are grouped together in twos, fours, or eights and so on.

2 Variable K-Map  For 2 variable k-map, there are 22 = 4 cells.  If A & B are two variables then; SOP  Minterms  A’B’ (m0, 00) ; A’B (m1, 01) ; AB’ (m2, 10) ; AB (m3, 11) POS  Maxterms  A + B (M0, 00) ; A + B’ (M1, 01) ; A’ + B (M2, 10) ; A’ + B’ (M3, 11)

3.7.1.1 Mapping of SOP Expression

 

1 in a cell indicates that the minterm is included in Boolean expression. For e.g. if F = ∑m(0,2,3), then 1 is put in cell no. 0,2,3 as shown below. B A

1

A 1

1

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 

0 in a cell indicates that the maxterm is included in Boolean expression. For e.g. if F = ΠM(0,2,3), then 0 is put in cell no. 0,2,3 as shown below. B

B’ 0

A’ 0

3.7.1.2 Mapping of POS Expression

B 1

A

0 0

A’ 0

0

3

A 1

0

B 1

1 0

1

1 2

B’ 0

1

0 2

3

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Unit 4-Part 1 : Boolean Algebra 3.7.1.3 Reduce Sum of Product (SOP) Expression using K-Map (1)

F = m0 + m1

Sol:

B

(2) B’ 0

A A’ 0

1

A 1

0

B 1

B

A’ 0

1

A 1

1

0 2

(5) B’ 0

A A’ 0

0

A 1

1

A’ 0

0

A 1

0

0

B 1

0 0

1

A’ 0

1

A 1

10

1 2

B’ 0

A

3

F=A

1 1

1 2

3

F=B (6)

B

B 1

0

3

∑m(0,1,3)

Sol:

B’ 0

1

F = B’

F = m2 + m3 B

B A

0

2

3

F = Σ(1,3)

Sol:

B 1

0

1

F = A’ (4) Sol:

(3)

B’ 0

A

1 0

F = A’B’ + AB’

Sol:

B 1

1

1 2

B A

1 0

∑m(0,1,2,3)

Sol:

3

B’ 0

A’ 0

1

A 1

1

B 1

1 0

F = A’ + AB

1

1 2

3

F=1

3.7.1.4 Reduce Product of Sum (POS) Expression using K-Map (1)

F = ΠM(0,2,3,1)

(2)

B

Sol:

Sol:

B’ 1

B 0

A

0

1

0

0

A’ 1

2

3

F=0 3.7.2

B

0

0

A’ 1

F=AB

B A A 0 A’ 1

B’ 1

B 0

0

1 0

1

1 2

F = M3·M1·M2

Sol:

0

0

A 0

(3)

B’ 1

B 0

A

0

0

A 0

F = (A+B) (A’+B) (A+B’)

0

0 2

3

1

3

F = A’ B’

3 Variable K-Map  For 3 variable k-map, there are 23 = 8 cells.

3.7.2.1 Mapping of SOP Expression

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3.7.2.2 Mapping of POS Expression

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Unit 4-Part 1 : Boolean Algebra 3.7.2.3 Reduce Sum of Product (SOP) Expression using K-Map (1) Sol:

F = A’B’C + ABC + A’BC’

(2) Sol:

F = Σ(1,6,7)

F = A’B’C + ABC + A’BC’ (3) Sol:

F = A’B’C’ + ABC’ + AB’C’ + A’BC

F = A’B’C + AB (4) Sol:

F = Σm(0,1,2,4,5,6)

F = B’C’ + AC’ + A’BC (5) Sol:

F = m3 + m4 +m6 + m7

F = B’ + C’ (6) Sol:

F = Σm(3,7,1,6,0,2,5,4)

F = BC + AC’

F=1

3.7.2.4 Reduce Product of Sum (POS) Expression using K-Map (1) Sol:

F = (A’+B’+C’) (A’+B+C’)

F = (A’ + C’) |EE & EC Department

(2) Sol:

F = M0·M3·M7

F = (A + B + C) (B’ + C’) | 3130907 – Analog and Digital Electronics

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Unit 4-Part 1 : Boolean Algebra (3) Sol:

F = ΠM(1,2,5)

(4) Sol:

F = (B + C’) (A + B + C) (5) Sol:

F = (A+B+C)(A+B’+C’)(A’+B+C)

F = (B) (C’) (6) Sol:

F = (B + C) (A + B’ + C’)

3.7.3

F = ΠM(0,4,1,5,7,3)

ΠM(5,7,0,3,2,4,6,1)

F=0

4 Variable K-Map  For 4 variable k-map, there are 24 = 16 cells.

3.7.3.1 Mapping of SOP Expression

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3.7.3.2 Mapping of POS Expression

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Unit 4-Part 1 : Boolean Algebra 3.7.3.3 Looping of POS Expression 

Looping Groups of Two:



Looping Groups of Four:

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Unit 4-Part 1 : Boolean Algebra 

Looping Groups of Eight:



Examples

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Unit 4-Part 1 : Boolean Algebra

3.7.3.4 Reduce Sum of Product (SOP) Expression using K-Map (1) Sol:

F = ∑ (0,1,2,4,5,6,8,9,12,13,14)

(2) Sol:

F = C’ + A’D’ + BD’ (3) Sol:

F = ∑ (0,1,2,3,5,7,8,9,12,13)

F = A’B’ + AC’ + A’D |EE & EC Department

F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

F = B’C’ + B’D’ + A’CD’ (4) Sol:

F = ∑ (0,1,3,4,5,6,7,13,15)

F = A’C’ + A’D + BD + A’B | 3130907 – Analog and Digital Electronics

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Unit 4-Part 1 : Boolean Algebra (5) Sol:

F = ∑m (5,6,7,9,10,11,13,14,15)

F = BD + BC + AD + AC 3.7.3.5 Reduce Product of Sum (POS) Expression using K-Map (1) Sol:

F = ΠM (0,1,2,5,7,8,9,10,14,15)

(2) Sol:

F = (B + D) (B + C) (A + B’ + D’) (A’ + B’ + C’)

F = M1 M3 M4 M7 M6 M9 M11 M12 M14 M15

F = (B’ + D) (C’ + B’) (D’ + B)

3.7.3.6 Reduce SOP & POS Expression with Don’t Care Combination using K-Map (1) Sol:

F = ∑m (1,5,6,12,13,14) + d (2,4)

F = BC’ + BD’ + A’C’D |EE & EC Department

(2) Sol:

F = ΠM (4,7,10,11,12,15) · d (6,8)

F = (B’ + C + D) (B’ + C’ + D’) (A’ + B + C’) | 3130907 – Analog and Digital Electronics

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Unit 4-Part 1 : Boolean Algebra 3.7.4

5 Variable K-Map  For 5 variable k-map, there are 25 = 32 cells.

3.7.4.1 Mapping of SOP Expression

3.7.4.2 Reduce Sum of Product (SOP) Expression using K-Map (1) F = ∑m (0,2,3,10,11,12,13,16,17,18,19,20,21,26,27) Sol:

F = C’D + B’C’E’ + AB’D’ + A’BCD’ (2) F = ∑m (0,2,4,6,9,11,13,15,17,21,25,27,29,31) Sol:

F = BE + AD’E + A’B’E’ |EE & EC Department

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Unit 4-Part 1 : Boolean Algebra 3.7.4.3 Reduce Product of Sum (POS) Expression using K-Map (1) F = ΠM (1,4,5,6,7,8,9,14,15,22,23,24,25,28,29,30,31) Sol:

F = (B’ + C + D) (C’ +D’) (A + B + C’) (A’ + B’ + D) (A + C + D + E’)

3.8 (1)

Sol: 

Converting Boolean Expression to Logic Circuit and Vice-Versa For the logic circuit shown fig., find the (2) Boolean expression and the truth table. Identify the gate that given circuit realizes.

Here, Output of OR gate will be (A+B) Output of NAND gate will be (AB)’ So, C will be AND of these two outputs ∴ C = (A+B) · (A·B)’

For the logic circuit shown fig., find the Boolean expression and the truth table. Identify the gate that given circuit realizes.

Sol: 



Truth table for the same can be given below; Input Output A B A+B A·B (A·B)’ (A+B)·(A·B)’ 0 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0





From the truth table it is clear that the circuit realizes Ex-OR gate.



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Here, bubble indicates inversion. Hence input of top OR gate is A’ and B’ and hence its output will be A’+B’ Output of bottom OR gate will be A+B ∴ Y = (A’+B’)(A+B) Truth table for the same can be given below; Input Output A B A’ B’ A’+B’ A+B (A’+B’)(A+B) 0 0 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 0

From the truth table it is clear that the circuit realizes Ex-OR gate.  NOTE: NAND = Bubbled OR | 3130907 – Analog and Digital Electronics

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Unit 4-Part 1 : Boolean Algebra (3)

For the logic circuit shown fig., find the Boolean expression.

(4)

For the given Boolean expression draw the logic circuit. F = X + (Y’ + Z) The expression primarily involves three logic gates i.e NOT, AND and OR. To generate Y’ a NOT gate is required. To generate Y’Z an AND gate is required. To generate final output OR gate is required.

Sol:

Sol: 

(5)

Here, Output of top AND gate will be AB’ Output of bottom AND gate will be A’B So, C will be OR of these two outputs ∴ C = AB’ + A’B

F = ∑ (0,1,2,4,5,6,8,9,12,13,14) Reduce using k-map method. Also realize it with logic circuit or gates with minimum no. of gates.

Sol:

(6)

F = ∑m (1,5,6,12,13,14) + d (2,4) Reduce using k-map method. Also realize it with logic circuit.

Sol:

F = C’ + A’D’ + BD’ 

Realization of function with logic circuit

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F = BC’ + BD’ + A’C’D 

Realization of function with logic circuit

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Unit 4-Part 1 : Boolean Algebra 3.9 NAND and NOR Realization/Implementation 

Steps to implement any function using NAND or NOR gate only as below; 1. Reduce the given function if necessary. 2. For NAND, add Bubbles at the outputs of AND gates and at the inputs of OR gates. 3. For NOR, add Bubbles at the outputs of OR gates and at the inputs of AND gates. 4. Add an inverter symbol wherever you created a Bubble. 5. Ignore cascading connection of two NOT gates, if any are present. 6. Replace all gates with NAND gates or NOR gates depending on the type of implementation.

(1) F = AB + CD + E Implement given function using (i) NAND gates only (ii) NOR gates only Sol:  Function realization using basic logic gates as below;

Using NAND gates

Using NOR gates

Step:1

Step:1

Step:2

Step:2

Step:3

Step:3

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Unit 4-Part 1 : Boolean Algebra Step:4

Step:4

3.10 Tabulation / Quine-McCluskey Method    

As we know that the Karnaugh map method is a very useful and convenient tool for simplification of Boolean functions as long as the number of variables does not exceed four. But for case of large number of variables, the visualization and selection of patterns of adjacent cells in the Karnaugh map becomes complicated and too much difficult. For those cases Quine McCluskey tabulation method takes vital role to simplify the Boolean expression. The Quine McCluskey tabulation method is a specific step-by-step procedure to achieve guaranteed, simplified standard form of expression for a function. Steps to solve function using tabulation method are as follow; Step 1 − Arrange the given min terms in an ascending order and make the groups based on the number of ones present in their binary representations. So, there will be at most ‘n+1’ groups if there are ‘n’ Boolean variables in a Boolean function or ‘n’ bits in the binary equivalent of min terms. Step 2 − Compare the min terms present in successive groups. If there is a change in only one-bit position, then take the pair of those two min terms. Place this symbol ‘_’ in the differed bit position and keep the remaining bits as it is. Step 3 − Repeat step2 with newly formed terms till we get all prime implicants. Step 4 − Formulate the prime implicant table. It consists of set of rows and columns. Prime implicants can be placed in row wise and min terms can be placed in column wise. Place ‘1’ in the cells corresponding to the min terms that are covered in each prime implicant. Step 5 − Find the essential prime implicants by observing each column. If the min term is covered only by one prime implicant, then it is essential prime implicant. Those essential prime implicants will be part of the simplified Boolean function. Step 6 − Reduce the prime implicant table by removing the row of each essential prime implicant and the columns corresponding to the min terms that are covered in that essential prime implicant. Repeat step 5 for reduced prime implicant table. Stop this process when all min terms of given Boolean function are over.

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Unit 4-Part 1 : Boolean Algebra (1)

Simplify the following expression to sum of product using Tabulation Method 𝑭(𝑨, 𝑩, 𝑪, 𝑫) = ∑(𝟎, 𝟏, 𝟐, 𝟑, 𝟒, 𝟔, 𝟕, 𝟏𝟏, 𝟏𝟐, 𝟏𝟓)

Sol:  Determination of Prime Implicants

 Determination of Prime Implicants

𝑭(𝑨, 𝑩, 𝑪, 𝑫) = 𝑩𝑪′ 𝑫′ + 𝑨′ 𝑩′ + 𝑪𝑫 + 𝑨′𝑫′ |EE & EC Department

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Unit 4-Part 1 : Boolean Algebra (2)

Simplify the following expression to sum of product using Tabulation Method 𝑭(𝑨, 𝑩, 𝑪, 𝑫) = 𝒎(𝟎, 𝟒, 𝟖, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑, 𝟏𝟓) + 𝒅(𝟏, 𝟐)

Sol:  Determination of Prime Implicants

 Determination of Essential Prime Implicants

𝑭(𝑨, 𝑩, 𝑪, 𝑫) = 𝑨𝑩𝑫 + 𝑪′𝑫′ + 𝑩′𝑫′ |EE & EC Department

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31

Unit 4-Part 1 : Boolean Algebra (3)

Simplify the following expression to sum of product using Tabulation Method 𝑭(𝑨, 𝑩, 𝑪, 𝑫) = 𝜫(𝟏, 𝟑, 𝟓, 𝟕, 𝟏𝟑, 𝟏𝟓)

Sol:  Determination of Prime Implicants

 Determination of Essential Prime Implicants

𝑭(𝑨, 𝑩, 𝑪, 𝑫) = (𝑨 + 𝑫′)(𝑩′ + 𝑫′) (4)

Simplify the following expression to sum of product using Tabulation Method 𝑭(𝑨, 𝑩, 𝑪, 𝑫) = 𝑴(𝟎, 𝟖, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑, 𝟏𝟓) ∙ 𝒅(𝟏, 𝟐, 𝟑)

Sol:  Determination of Prime Implicants

 Determination of Essential Prime Implicants

𝑭(𝑨, 𝑩, 𝑪, 𝑫) = (𝑨′ + 𝑩′ + 𝑫′)(𝑩 + 𝑫)(𝑨′ + 𝑩′ + 𝑪) |EE & EC Department

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32

Unit 4-Part 1 : Boolean Algebra

A

A

A

A 3 A A B

Summer-18

Winter-17

Summer-17

Winter-16

3.5_8

3.5_8

4

3.5.1.2_10

3

3.5_8

4

3.5.1.2_11

7

3.5_8

3 3

B

|EE & EC Department

7

7

Explain minterm and maxterm

Compare SOP and POS. Give examples of standard and nonstandard SOP and POS forms. Explain how a NON B standard POS expression can be converted in to standard POS expression using example you have given. Express the Boolean function F=A+A'C in a B sum of min-terms. Express A’B + A’C as sum of minterms and B&C also plot K-map. What are SOP and POS forms of Boolean expressions? Minimize the following C expression using K-map Y= Σm(4,5,7,12,14,15) + d( 3,8,10) Write short note on K-map. OR Explain KC map simplification technique.

Summer-16

Winter-15

7

Answer Topic No_ Pg. No.

State and explain De Morgan’s theorems with truth tables. Apply De Morgan’s theorem to solve the following: (1) [A + (BC)']' [AB' + ABC] = 0 (2) A [ B + C' (AB + AC')'] = AB Reduce the expression: (1) A + B (AC + (B+C’) D) (2) (A + (BC)’ )’(AB’ + ABC) Demonstrate by means of truth tables the validity of the De Morgan’s theorems for three variables. Simplify the following Boolean functions to a minimum number of literals. (i) F(x,y,z)=xy+xyz+xyz’+x’yz (ii) F(p, q, r, s) = (p’+q) (p+q+s)s’ State and prove De Morgan’s theorems Reduce the expression F = (B+BC) (B+B'C)(B+D)

Winter-18

A

Questions

Summer-15

Group

Unit

3.11 GTU Questions

3.5.1.2_11 3.6.2.1_12 3.6.2.2_13 3.6.1.1_12

3 3

7

3.6_12

7

3.6.3.1_15 3.6.3.1._15 3.7.2_18

7

3.6.1.1_12 3.7.3.6_24

7

7

7

| 3130907 – Analog and Digital Electronics

3.7_17

33

Unit 4-Part 1 : Boolean Algebra Simplify the following Boolean function using K-map F (w, x, y, z) = Σ m(1, 3, 7, 11, 15) with don’t care, d(w, x, y, z) = Σm(0,2,5) Simplify the Boolean function F = A’B’C’+AB’D+A’B’CD’ using don’t-care conditions d=ABC+AB’D’ in (i) sum of products and (ii) product of sums by means C of Karnaugh map and implement it with no more than two NOR gates. Assume that both the normal and complement inputs are available. Reduce using K-map C (i)Σm(5,6,7,9,10,11,13,14,15) (ii)ΠM(1,5,6,7,11,12,13,15) Minimize using K-map C f(A,B,C,D) = Σ(1,3,4,6,8,11,15) +d(0,5,7) also draw MSI circuit for the output. Simplify equation using K-map : F(a,b,c,d) = Σm(3,7,11,12,13,14,15) C Realize the expression with minimum number of gates. Minimize the following Boolean expression using K- Map and realize it using logic gates. C F(A,B,C,D)=Σm(0,1,5,9,13,14,15)+d(3,4,7,10 ,11) Compare K-map and tabular method of C&D minimization. Simplify following Boolean function using D tabulation method: F(w, x, y, z) = Σ (0, 1, 2, 8, 10, 11, 14, 15) Simplify the Boolean function D F(x1,x2,x3,x4)=Σm(0,5,7,8,9,10,11,14,15) using tabulation method. Simplify Y=A’BCD’ + BCD’ + BC’D’ + BC’D and E implement using NAND gates only. Implement following Boolean function using E only NAND gates. Y=ABC’+ABC+A’BC. C

3

|EE & EC Department

3

3.7.3.6_24

3.7.3.6_24 3.9_28

7

3.7.3.4_23 3.7.3.5_24

4

7

3.7.3.6_24

3.7.3.4_24 3.8_26

4

7

3.7.3.6_24

3

3.7_17 3.10_29

7

3.10_29

7

3.10_29

7

3.9_28

4

| 3130907 – Analog and Digital Electronics

3.9_28

34

Unit 4-Part 2 : Combinational Logic Circuits

Table of Contents 4.1

Introduction .......................................................................................................................................3

4.1.1 Difference between Combinational and Sequential Circuit .......................................................................3 4.2

Binary Adder Logic Circuit ...................................................................................................................3

4.2.1 Half Adder ...................................................................................................................................................4 4.2.2 Full Adder ....................................................................................................................................................4 4.2.3 Comparison between Half & Full Adder .....................................................................................................5 4.3

Binary Subtractor Logic Circuit.............................................................................................................5

4.3.1 Half Subtractor ............................................................................................................................................5 4.3.2 Full Subtractor ............................................................................................................................................5 4.4

Binary Parallel Adder/Ripple Carry Adder ............................................................................................6

4.5

Binary Parallel Subtractor (2’s Complement Adder) .............................................................................6

4.6

Binary Parallel Adder/Subtractor (2’s Complement Adder)...................................................................7

4.6.1 Advantages of Parallel Adder/Subtractor ...................................................................................................7 4.6.2 Disadvantages of Parallel Adder/Subtractor ..............................................................................................8 4.7

BCD Adder/Decimal Adder ..................................................................................................................8

4.8

Carry Look Ahead Adder......................................................................................................................9

4.9

Magnitude Comparator ..................................................................................................................... 11

4.9.1 2 bit Magnitude Comparator ................................................................................................................... 11 4.9.2 4 bit Magnitude Comparator ................................................................................................................... 13 4.10

Encoder ............................................................................................................................................ 14

4.10.1 8 to 3 (Octal to Binary) Encoder ............................................................................................................ 14 4.10.2 Priority Encoder ..................................................................................................................................... 15 4.11

Decoder ............................................................................................................................................ 16

4.11.1 2 to 4 Decoder ....................................................................................................................................... 16 4.11.2 3 to 8 Decoder ....................................................................................................................................... 17 4.11.3 2 to 4 Decoder with Enable ................................................................................................................... 17 4.11.4 Examples of Decoder ............................................................................................................................. 18

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Unit 4-Part 2 : Combinational Logic Circuits 4.12

Multiplexer (MUX) ............................................................................................................................ 18

4.12.1 2 to 1 (2 X 1 or 2:1) Multiplexer ............................................................................................................. 19 4.12.2 4 to 1 Multiplexer .................................................................................................................................. 19 4.12.3 8 to 1 Multiplexer .................................................................................................................................. 20 4.12.4 Examples of Multiplexer ........................................................................................................................ 20 4.13

Demultiplexer (DEMUX) .................................................................................................................... 22

4.13.1 1 X 4 Demultiplexer ............................................................................................................................... 22 4.13.2 1 X 8 Demultiplexer ............................................................................................................................... 23 4.13.3 Applications of Multiplexer and Demultiplexer..................................................................................... 23 4.14

Parity Bit Generator and Checker ...................................................................................................... 24

4.14.1 Examples of Parity Bit Generator / Checker .......................................................................................... 25 4.15

GTU Questions .................................................................................................................................. 26

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Unit 4-Part 2 : Combinational Logic Circuits 4.1

Introduction 

Combinational logic circuit is a circuit in which we combine the different logic gates in the circuit such that the output of combinational circuit at any instant of time, depends only on the logic levels present at input terminals.



Some of the characteristics of combinational circuits are following − 1. The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit. 2. A combinational circuit can have an n number of inputs and m number of outputs.

Fig.: Block Diagram of Combinational Logic Circuit 

Below logic circuit are the examples of combinational logic circuit 1. Adder and Subtractor 2. Magnitude comparator 3. Encoder and Decoder 4. Multiplexer and Demultiplexer 5. Parity Checker and Generator etc.

4.1.1 Difference between Combinational and Sequential Circuit Combinational Circuit Sequential Circuit 1. It does not contain memory elements. 1. It contains memory elements. 2. Output depends on present state of input 2. Output depends not only on the present only. inputs but also on the past history of inputs. 3. Its behaviour is described by the set of 3. Its behaviour is described by the set of nextoutput functions. state (memory) functions and the set of output functions. 4. 5. 6. 7.

Does not use Feedback path. Does not require clock signal. Faster than sequential circuit. E.g.: Adder, Subtractor, MUX, Encoders, etc.

4.2

4. 5. 6. 7.

Use Feedback path. Most of sequential circuit use clock signal. Slower than combinational circuit. E.g. Flip Flops, Registers, Counters, etc.

Binary Adder Logic Circuit  

Adder is used to add binary numbers Binary adders are of two types; 1. Half Adder: Used to add two single bit binary numbers A & B. 2. Full Adder: Used to add two single bit binary number A & B and carry bit Cin.

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Unit 4-Part 2 : Combinational Logic Circuits 4.2.1 Half Adder  A binary adder adds two binary bits. Block diagram of half adder is shown in fig. A

Sum (S)

Half Adder

Inputs B



 

 



Outputs Carry(C)

Fig.: Block diagram of half adder There are two input terminals, which are marked as A and B. Binary numbers, the sum of which has to be made are applied here. There are two output terminals. One terminal is for sum bit S and the other is the carry bit C. Truth table of half adder is shown below. Table: Truth table for half adder Inputs Outputs A B S (Sum) C (Carry) 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 From truth table we can write the expression for sum S and carry C. For sum and carry summing up input combinations for which the output is 1. Sum (S) = A’B + AB’ = A ⨁ B Carry (C) = AB

4.2.2 Full Adder  Full adder is made up of two half adder and OR gate.  It has three inputs and two output.  It can able to add 3 digit at a time.  Fig. shows the full adder logic circuit using half adder and OR gate.

Fig.: Block diagram of full adder Table: Truth table for full adder



For sum and carry summing up input combinations for which the output is 1. S = A ⨁ B ⨁ Cin Cout = (A ⨁ B) Cin + AB

It is seen that the sum S can be realized by EX-OR gate and carry C can be realized by an AND gate. Such circuit is shown in Fig.

Fig.: Circuit of half adder | EE &EC Department

Fig.: Circuit diagram of full adder | 3130907– Analog and Digital Electronics

4

Unit 4-Part 2 : Combinational Logic Circuits 4.2.3 Comparison between Half & Full Adder 1. 2.

Half Adder Used for 2 single bit number. One EX-OR gate and one AND gate are used.

1. 2.

3. 4. 5. 6.

Output is the sum of two signal. Circuit is simple. There are 2 input and output terminals. It cannot be used as full adder.

3. 4. 5. 6.

4.3

Binary Subtractor Logic Circuit

4.3.1 Half Subtractor  The subtraction of 2 binary digits also produces two outputs which are termed as difference and borrow.  The simplest possible subtraction of 2-bit binary digits consists of four possible operations, they are 0-0, 0-1, 1-0 and 1-1.  The operations 0-0, 1-0 and 1-1 produces a subtraction of 1-bit output whereas, the remaining operation 0-1 produces a 2-bit output. They are referred as difference and borrow bit. Table: Truth table for half adder Inputs Outputs A B D (Diff.) B (Borrow) 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 

Full Adder Used for 2 single bit & 1 carry bit number. Two EX-OR gates, two AND gates and 1 OR gate are used. Output is the sum of three signal. Circuit is complicated. There are 3 input and 2 output terminals. It can be used as half adder.

4.3.2 Full Subtractor  Full subtractor as a combinational circuit which takes three inputs and produces two outputs difference and borrow. Table: Truth table for half adder Inputs Outputs A B C D (Diff.) B (Borrow) 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 

Boolean eq. from truth table; Difference (D) = A ⨁ B ⨁ C Borrow (B) = (A ⨁ B)’ C + A’ B

Boolean eq. from truth table; Difference (D) = A’B + AB’ = A ⨁ B Borrow (B) = A’ B

Fig.: Circuit of half subtractor | EE &EC Department

Fig.: Circuit of full subtractor | 3130907– Analog and Digital Electronics

5

Unit 4-Part 2 : Combinational Logic Circuits 4.4

Binary Parallel Adder/Ripple Carry Adder  

A single full adder performs the addition of two one bit numbers and an input carry. But a Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary numbers that is greater than one bit in length by operating on corresponding pairs of bits in parallel. It consists of full adders connected in a chain where the output carry from each full adder is connected to the carry input of the next higher order full adder in the chain. “A n bit parallel adder requires n full adders to perform the operation.”

Fig.: n-bit binary parallel adder 

4.5

Working of n bit parallel adder 1. As shown in the figure, firstly the full adder FA1 adds A1 and B1 along with the carry C1 to generate the sum S1 (the first bit of the output sum) and the carry C2 which is connected to the next adder in chain. 2. Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2 and B2 to generate the sum S2(the second bit of the output sum) and the carry C3 which is again further connected to the next adder in chain and so on. 3. The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and Bn to generate the last bit of the output along last carry bit Cout.

Binary Parallel Subtractor (2’s Complement Adder)  

A Parallel Subtractor is a digital circuit capable of finding the arithmetic difference of two binary numbers that is greater than one bit in length. The parallel subtractor can be designed in several ways including combination of half and full subtractors, all full subtractors or all full adders with subtrahend complement input. “A n bit parallel subtractor requires n full adders & n NOT gates to perform the operation.”

(“1”)

Fig.: n-bit binary parallel subtractor | EE &EC Department

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Unit 4-Part 2 : Combinational Logic Circuits 

4.6

Working of Parallel Subtractor – 1. As shown in the figure, the parallel binary subtractor is formed by combination of all full adders with subtrahend complement input. 2. Firstly the 1’s complement of B is obtained by the NOT gate and 1 can be added through the carry to find out the 2’s complement of B. This is further added to A to carry out the arithmetic subtraction. 3. The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and 2’s complement of Bn to generate the last bit of the output along last carry bit Cout.

Binary Parallel Adder/Subtractor (2’s Complement Adder)

Fig.: n-bit binary parallel adder/subtractor 

Here M-line acts as a control line

 For M = 0 (Adder):  When M=0, then one of the input to each and every XOR gate would be logic 0. This means that the XOR outputs in this case will be unchanged binary bits of the number BnBn-1…B2B1.  In addition, if M = 0, the carry in pin (Ci1) of the first full adder (FA1) would also be 0. Due to these conditions, the circuit shown will be behave as a n-bit adder adding the number AnAn1…A2A1 with BnBn-1…B2B1.  For M = 1 (Subtractor):  When M = 1, one of the inputs to each XOR gate would be logic 1. This means that we get the complement of the bits BnBn-1…B2 and B1 as the outputs of each XOR gate.  In addition, for the same case, even the Ci1 of the first full adder FA1 would be logically high. As a result, the cascaded arrangement of full adders shown in Fig. effectively performs-bit binary subtraction where the binary number BnBn-1…B2B1 is subtracted from AnAn-1…A2A1. 4.6.1 Advantages of Parallel Adder/Subtractor 1. The parallel adder/subtractor performs the addition/subtraction operation faster as compared to serial adder/subtractor. 2. Time required for addition/subtraction does not depend on the number of bits. 3. The output is in parallel form i.e all the bits are added/subtracted at the same time. 4. It is less costly. | EE &EC Department

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Unit 4-Part 2 : Combinational Logic Circuits 4.6.2 Disadvantages of Parallel Adder/Subtractor 1. Each adder/subtractor has to wait for the carry/borrow which is to be generated from the previous adder in chain. 2. The propagation delay (delay associated with the travelling of carry bit) is increase with the increase in the number of bits to be added/subtract.

4.7

BCD Adder/Decimal Adder     

BCD adder is combinational circuit that adds two BCD number and gives output also in BCD. Add two BCD numbers using ordinay binary addition. If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form. If the four-bit sum is > 9 or if a carry is generated from the four-bit sum, the sum is invalid. To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from this addition, add it to the next higher-order BCD digit.



Thus to implement BCD adder we require :  4-bit binary adder for initial addition.  Logic circuit to detect sum greater than 9 and,  One more 4-bit adder to add 01102 in the sum if sum is greater than 9 or carry is 1.



The logic circuit to detect sum > 9 can be determined by simplifying the Boolean expression of given truth table Inputs Output Carry Z3 Z2 Z1 Z0 Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1

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Unit 4-Part 2 : Combinational Logic Circuits 

K-Map representation of truth table:

4.8

Carry Look Ahead Adder   



Design of logic circuit:

In parallel adder, the carry propagation time is the major speed limiting factor. One widely used approach employs the principle of carry look-ahead solves this problem by calculating the carry signals in advance, based on the input signals. This type of adder circuit is called as carry look-ahead adder (CLA adder). It is based on the fact that a carry signal will be generated in two cases: (1) When both bits Ai and Bi are 1, or (2) When one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.



To understand the carry propagation problem, let’s consider the case of adding two n-bit numbers A and B.



The Figure shows the full adder circuit used to add the operand bits in the ith column; namely Ai & Bi and the carry bit coming from the previous column (Ci).

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Unit 4-Part 2 : Combinational Logic Circuits

  

Gi is known as the carry Generate signal since a carry (Ci+1) is generated whenever Gi =1, regardless of the input carry (Ci). Pi is known as the carry propagate signal since whenever Pi =1, the input carry is propagated to the output carry, i.e., Ci+1. = Ci (note that whenever Pi =1, Gi =0). Computing the values of Pi and Gi only depend on the input operand bits (Ai & Bi).

Fig.: Carry look ahead adder 

The Boolean expression of the carry outputs of various stages can be written as follows:



In general, the ith Carry output is expressed in the form Ci = Fi (P’s, G’s, C0).

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Unit 4-Part 2 : Combinational Logic Circuits

Fig.: Combination circuit to generate c1, c2, c3,…

4.9

Magnitude Comparator     

It compares two numbers A & B. In process of comparison, it first compares MSB of input A to MSB of input B. If one of these bits is 1 and the other 0, the process is completed & the number containing 1 as the MSB is identified as the largest number. If MSB of A equals the MSB of B, then the next most significant bits of A and B are compared. This process continues until a bit of one number differs from the corresponding bit of the other.

4.9.1 2 bit Magnitude Comparator  There are two numbers A and B, each of two bits long.  Magnitude comparator compares numerical values of these numbers.  The result of comparison can be Equal (E), Greater than (G) or Less than (L).  If A > B then G should be asserted to 1.  If A = B then E should be asserted to 1.  If A < B then L should be asserted to 1.

Fig.: Block diagram of magnitude comparator

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Unit 4-Part 2 : Combinational Logic Circuits 



Truth Table Inputs



Outputs

A1

A0

B1

B0

G

E

L

0

0

0

0

0

1

0

0

0

0

1

0

0

1

0

0

1

0

0

0

1

0

0

1

1

0

0

1

0

1

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1

0

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0

1

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

0

1

1

0

0

0

1

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0

1

0

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1

1

0

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1

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1

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1

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1

1

0

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1

1

1

0

0

1

0

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1

1

0

1

1

0

0

1

1

1

0

1

0

0

1

1

1

1

0

1

0

Boolean Equation

For E,

For L,

For G,

Circuit Diagram

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Unit 4-Part 2 : Combinational Logic Circuits 4.9.2 4 bit Magnitude Comparator 



Fig.: Circuit diagram of 4 bit magnitude comparator | EE &EC Department

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Unit 4-Part 2 : Combinational Logic Circuits 4.10 Encoder     

It is a combinational circuit. It has ‘n’ input lines & ‘m’ output lines. (2m = n, where n = inputs and m = outputs) An encoder produces an ‘m’ bit binary code corresponding to the digital input number of ‘n’ bits. Many types of Encoders – Octal to Binary (8 to 3), Decimal to BCD (10 to 4) etc. The block diagram is shown as below,

Fig.: Block diagram of encoder 4.10.1 8 to 3 (Octal to Binary) Encoder 



Truth Table: Input

D0 1

D1 0

D2 0

D3

0

1

0

  

Q0 = D1 + D3 + D5 + D7 Q1 = D2 + D3 + D6 + D7 Q2 = D4 + D5 + D6 + D7

Output D5 0

D6 0

D7 0

Q2 0

Q1

Q0

0

D4 0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

1

0

0

0

0

1

0

0

0

1

0

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0

0

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1

0

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1

0

1

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0

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1

0

1

1

0

0

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0

0

0

0

0

1

1

1

1

Boolean Eq.:



Circuit Diagram:

It has 8 input lines & 3 output lines. Corresponding to the eight input octal numbers we get three bit binary output. In encoders only one input will have a one value at any given time.

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Unit 4-Part 2 : Combinational Logic Circuits 4.10.2   

Priority Encoder This is special type of encoder. Priorities are given to the input lines. If two or more input lines are ‘1’ at the same time, then the input line with highest priority will be considered.

Fig.: Block diagram of priority encoder    

The truth table of priority encoder is as given below, There are four inputs, D0 through D3 and outputs Y1 and Y0. Out of the four inputs D3 has the highest priority and D0 has the lowest priority. That means if D3 = 1 then Y1Y0 = 11 irrespective of the other inputs. Similarly if D 3 = 0 and D2 = 1 then Y1Y0 = 10 irrespective of other inputs. Truth Table:

D3 0 0 0 0 1 

Inputs Outputs D2 D1 D0 Y1 Y0 0 0 0 X X 0 0 1 0 0 0 1 X 0 1 1 X X 1 0 X X X 1 1

K-Map representation of truth table:

Y 0 = D 3 + D 2’ D 1 

Circuit diagram:

Y1 = D 3 + D 2 | EE &EC Department

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Unit 4-Part 2 : Combinational Logic Circuits 4.11 Decoder   

Decoder is a device which does the reverse operation of Encoder. It is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of ‘2 n’ unique output lines. Decoder is identical to a demultiplexer without any data input. E.g.: 2 to 4 Decoder, 3 to 8 Decoder, BCD to Seven Segment Decoder.

Fig.: Block diagram of decoder 4.11.1 2 to 4 Decoder  I0 & I1 are two inputs whereas y3, y2, y1 & y0 are four outputs.  The truth table shows that each output is ‘1’ for only a specific combination of inputs. 

Block Diagram:



Boolean Eq.: y0 = I̅1 I̅0 ; y1 = I̅1 I0 ; y2 = I1 I̅0 ; y3 = I1 I0

 

Truth Table: Inputs Output I1 I0 y0 y1 y2 y3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1



Working:  According to the truth table, when I1I0=00, the output Y0 is set to ‘1’, others are ‘0’  When I1I0=01, the output Y1 is set to ‘1’, others are ‘0’  Similarly, for other input combinations, particular output is set to ‘1’ & others are ‘0’

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Circuit Diagram:

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Unit 4-Part 2 : Combinational Logic Circuits 4.11.2 3 to 8 Decoder  Block Diagram:







Boolean Eq.: Y0 = Y1 = Y2 = Y3 = Y4 = Y5 = Y6 = Y7 =

Truth Table: Inputs Output I2 I1 I0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1



I̅2 I̅1 I̅0 I̅2 I̅1 I0 I̅2 I1 I̅0 I̅2 I1 I0 I2 I̅1 I̅0 I2 I̅1 I0 I2 I1 I̅0 I2 I1 I0

Circuit Diagram:

Working:  According to the truth table, when I2I1I0=000, the output Y0 is set to ‘1’, others are ‘0’  When I2I1I0=001, the output Y1 is set to ‘1’, others are ‘0’  Similarly, for other input combinations, particular output is set to ‘1’ & others are ‘0’

4.11.3 2 to 4 Decoder with Enable  Truth Table: Inputs Output E I1 I0 Y0 Y1 Y2 Y3 0 X X 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1  Boolean Eq.: Y0 = E I1’ I0’ ; Y1 = E I1’ I0 ; Y2 = E I1 I0’ ; Y3 = E I1 I0 | EE &EC Department



Circuit Diagram:

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Unit 4-Part 2 : Combinational Logic Circuits 4.11.4 Examples of Decoder (1) Implement following (2) Implement Full adder (3) Design 4 to 16 decoder using 3 function using using decoder. to 8 decoder. decoder: F=Σ(2,4,5,7) Sol: Sol: Sum = Σ(1, 2, 4, 7) Sol: Carry = Σ(3, 5, 6, 7)

4.12 Multiplexer (MUX)         

 

Multiplexer is a special type of combinational circuit. The figure below shows the n x 1 multiplexer and its equivalent circuit representation. There are ‘n’ data inputs, 1 output and ‘m’ select lines, i.e. 2m = n. A multiplexer is a digital circuit which selects one of the n data inputs and routes it to the output. The selection of one of the n inputs is done by the select inputs To select ‘n’ inputs, ‘m’ select lines such that 2m = n. Depending on the digital code applied at the select inputs, one out of ‘n’ data sources is elected and transmitted to the single output. As shown in the figure, the multiplexer acts like a digitally controlled single pole, multiple way switch. The output gets connected to only one of the ‘n’ data inputs at given instant of time. It is also called DATA SELECTOR.

Fig.: Illustration of multiplexer Different types of multiplexers are available i.e. 2 to 1, 4 to 1, 8 to 1, 16 to 1 and onwards. Multiplexers are needed in most of electronics systems. Many logical functions can be implemented using Multiplexer.

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Unit 4-Part 2 : Combinational Logic Circuits 4.12.1 2 to 1 (2 X 1 or 2:1) Multiplexer  Here 2n=2 inputs, i.e. n=1 select lines and m = 1 output. 



Circuit Diagram:



Working:  When S=0, the upper AND gate will turn ON and lower AND gate will turn OFF, and so the input I0 appears in the output.  When S=1, the upper AND gate will turn OFF and lower AND gate will turn ON, and so the input I1 appears in the output.

Block Diagram:



Truth Table: Select Line Output S Y 0 I0 1 I1

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Boolean Eq.: Y = S’I0 + SI1

4.12.2 4 to 1 Multiplexer  Here 2n=4 inputs, i.e. n=2 select lines and m = 1 output. 

 

Block Diagram:

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Truth Table: Select Line Output Y S1 S0 0 0 I0 0 1 I1 1 0 I2 1 1 I3

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Working:  According to the truth table, when S1S0=00, the input I0 is selected and routed to the output.

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When S1S0=01, the input I1 is selected and routed to the output. Similarly, when S1S0=10, then Y=I2 & when S1S0=11, then Y=I3.



Boolean Eq.: Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3



Circuit Diagram:

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Unit 4-Part 2 : Combinational Logic Circuits 4.12.3 8 to 1 Multiplexer  Here 2n=8 inputs, i.e. n=3 select lines and m = 1 output. 



Truth Table: Select Line Output Y S2 S1 S0 0 0 0 I0 0 0 1 I1 0 1 0 I2 0 1 1 I3 1 0 0 I4 1 0 1 I5 1 1 0 I6 1 1 1 I7

 Boolean Eq.: Y = S2’S1’S0’I0 + S2’S1’S0I1 + S2’S1S0’I2 + S2’S1S0I3 + S2S1’S0’I4 + S2S1’S0I5 + S2S1S0’I6 + S2S1S0I7 

Circuit Diagram:

Working:  According to the truth table, when S2S1 S0=000, the input I0 is selected and routed to the output.  When S2S1S0=001, the input I1 is selected and routed to the output.  Similarly, for other combinations of select lines particular input is routed to the output.

4.12.4 Examples of Multiplexer (1) 8 X 1 Multiplexer using 4 X 1 and 2 X 1 Multiplexers. Sol:      

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MUX1 & MUX2 are 4 X 1 Multiplexer & MUX3 is 2 X 1 Multiplexer. Assuming that input I5 is to be routed through the output. So select lines will be S2S1S0=101. Now, for MUX1 & MUX2, S1S0=01, so the inputs I1 & I5 will be routed through each 4 X 1 Multiplexer. I1 & I5 appears as input to 2 X 1 Multiplexer. The value of S2=1, so the second input which I5 will be routed through the output Y.

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Unit 4-Part 2 : Combinational Logic Circuits (2) Implement the function F(x, y, z) = ∑ (1, 2, 6, 7) (3) Design full adder using multiplexer. using multiplexer. Sol: Sol:

(4) Implement the following function F(x,y,z)=∑ (1,2,6,7) using 4 X 1 mux. Sol:

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(5) Implement the following function F (A, B, C, D) = ∑ (1, 3, 4, 11, 12, 13, 14, 15) using 8 X 1 multiplexer. Sol:

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Unit 4-Part 2 : Combinational Logic Circuits 4.13 Demultiplexer (DEMUX)

Fig.: Illustration of demultiplexer

   

It has one input common data, ‘n’ select lines and ‘m’ output lines. A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. Relation between ‘n’ output lines and m select lines is as follows :

n = 2m 4.13.1 1 X 4 Demultiplexer  1 to 4 Demultiplexer has one data input F; select line inputs a, b and four outputs A, B, C & D.  The select lines control the data to be routed. It helps in selecting the output on which the data will be routed. 



Truth Table: Select Line Output Line b a 0 0 A 0 1 B 1 0 C 1 1 D



Working:  When ab=”00”, the input data F is routed to the output A  When ab=”01”, the input data F is routed to the output B  When ab=”10”, the input data F is routed to the output C  When ab=”11”, the input data F is routed to the output D



Circuit Diagram:

Boolean Equation: A = Fb′a′; C = Fba′;

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B = Fb′a; D = Fba;

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Unit 4-Part 2 : Combinational Logic Circuits 4.13.2 1 X 8 Demultiplexer  1 to 8 Demultiplexer has one data input I; select line inputs are S2, S1 & S0 and eight outputs F0, F1, F2, F3, F4, F5, F6, F7 & F8.  The select lines control the data to be routed. It helps in selecting the output on which the data i.e. ‘I’ will be routed. 





   

Truth Table: Select Line Output Line S2 S1 S0 0 0 0 F0 0 0 1 F1 0 1 0 F2 0 1 1 F3 1 0 0 F4 1 0 1 F5 1 1 0 F6 1 1 1 F7 Boolean Equation: F0 = IS̅̅̅2 S̅1 ̅̅̅ S0 ; F2 = IS̅̅̅2 S1 ̅̅̅ S0 ; F4 = IS2 S̅1 ̅̅̅ S0 ; F6 = IS2 S1 ̅̅̅ S0 ;

F1 = F3 = F5 = F7 =

 

When S2S1S0=”011”, the routed to the output F3 When S2S1S0=”100”, the routed to the output F4 When S2S1S0=”101”, the routed to the output F5 When S2S1S0=”110”, the routed to the output F6 When S2S1S0=”111”, the routed to the output F7

input data input data input data input data input data

Circuit Diagram:

IS̅̅̅2 S̅1 S0 ; IS̅̅̅2 S1 S0 ; IS2 S̅1 S0 ; IS2 S1 S0

Working:  When S2S1S0=”000”, the input data routed to the output F0  When S2S1S0=”001”, the input data routed to the output F1  When S2S1S0=”010”, the input data routed to the output F2

4.13.3 Applications of Multiplexer and Demultiplexer 1. Communication system 2. Computer memory 3. Telephone network 4. ALU in computer 5. Transmission from the commuter system of a satellite 6. Shift register etc. | EE &EC Department

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Unit 4-Part 2 : Combinational Logic Circuits 4.14 Parity Bit Generator and Checker              

Ex-OR functions are very useful in systems requiring error detection & correction codes. Binary data, when transmitted and processed, is susceptible to noise that can alter its 1s to 0s and 0s to 1s. To detect such errors, an additional bit called the parity bit is added to the data bits and the word containing the data bits and the parity bit is transmitted. At the receiving end the number of 1s in the word received is counted and the error, if any, is detected. This parity check detects only single bit errors. The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that checks the parity in the receiver is called parity checker. A parity bit, a 0 or a 1 is attached to the data bits such that the total number of 1s in the word is even for even parity and odd for odd parity. The parity bit can be attached to the code group either at the beginning or at the end depending on system design. A given system operates with either even or odd parity but not both. So, a word always contains either an even or an odd number of 1s. At the receiving end, if the word received has an even number of 1s in the odd parity system or an odd number of 1s in the even parity system, it implies that an error has occurred. In order to check or generate the proper parity bit in a given code word, the basic principle used is “the modulo sum of an even number of 1s is always a 1”. Therefore, in order to check for an error, all the bits in the received word are added. If the modulo sum is a o for an odd parity system or a 1 for an even parity system, an error is detected.

Fig.: Circuit diagram of parity bit generator / checker | EE &EC Department

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Unit 4-Part 2 : Combinational Logic Circuits 4.14.1 Examples of Parity Bit Generator / Checker (1) Design 4 bit input even parity bit generator (2)  Let the 4-bit input be A, B, C & D.   For even parity, a parity bit 1 is added such that the total number of 1s in the 4-bit input and the parity bit together is even.

Design 4 bit input odd parity bit generator An odd parity bit generator outputs a 1, when the number of 1s in the data bits is even, so that the total number of 1s in the data bits and parity bit together is odd.

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Truth Table:

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Truth Table

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Boolean Equation

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Boolean Equation

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Circuit Diagram



Circuit Diagram

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Unit 4-Part 2 : Combinational Logic Circuits

4

I I I

Design 3-bit odd parity generator circuit. Explain a parity generator and checker. Design 3-bit even parity generator circuit.

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Answer Topic No._Pg. No.

3

Winter-18

3

Summer-18

Winter-16

Summer-16

Winter-17

Write short note on half adder and full adder. Explain a full adder circuit. Explain half adder circuit. Explain full adder circuit with the help of two half adders. A&B Explain how four bit combined binary adder and subtractor circuit can be constructed using full adders? B Explain full- subtractor in brief. C Explain look-ahead-carry adder. C Construct BCD adder using two 4-bit binary parallel adder and logic gates. D Discuss 4 – bit magnitude comparator. D Explain 2-bit magnitude comparator. E Explain octal to binary encoder. F Explain in brief the working of decoders. F Explain 3-to-8 line decoder. Construct a 4 × 16 decoder with two 3 × 8 decoder. Use block diagram construction only. F Describe a 3-to-8 line decoder. F Draw truth table and logic diagram of 3 to 8 line decoder. F&G Design a full adder circuit using decoder and multiplexer (4:1 MUX). G Explain multiplexer. G Implement the following Boolean function by using 8:1 MUX F(A,B,C,D) = Σm(0,1,3,4,8,9,15). G Explain multiplexer with suitable example. G Explain a 4 input multiplexer. G Implement a full adder using 8:1 multiplexer. G&H Describe multiplexer and de-multiplexer with circuit and application of each.

Summer-17

A A A

Winter-15

Questions

Summer-15

Group

Unit

4.15 GTU Questions

7 4.2.1_4 4.2.2_4

7 7

4.6_7

3

4

7

4.3.2_5 4.8_9

7

4.7_8

7

4.9.2_13

3

4.9.1_11

3

4.10.1_14

7

4.11_16 4.11.2_17 4.11.4_18

7 7

4.11.2_17

4

4.11.4_18 4.12.4_21

4 7

7 3

4.12_18 4.12.4_21

4

3

4.12_18

7

4.12.2_19

7

4.12.4_21 4.12_18 4.13_22 4.13.3_23 4.14.1_25

3

4.14_24

7 4 4 4 | 3130907– Analog and Digital Electronics

4.14.1_25

26

Unit-5. Flip Flops & Sequential Logic Circuits Q:1

What do you mean by Combinational and Sequential circuits?

Ans:

Combinational Circuit: A combinational circuit can be defined as a circuit whose output is dependent only on the inputs at the same instant of time. Half Adder, Full Adder, Half Subtractor, Full Subtractor are examples of combinational circuits. Sequential Circuit A sequential circuit can be defined as a circuit whose output depends not only on the present inputs but also on the past history of inputs. Flip-Flops, Registers, Counters form the sequential circuit. A sequential circuit consists of combinational circuit and memory elements are connected to it to form a feedback path as shown in the block diagram below:

Figure 5.1 sequential circuit block diagram A sequential circuit can further be categorized into Synchronous and Asynchronous. Synchronous Sequential Circuit: Output changes at discrete interval of time. It is a circuit based on an equal state time or a state time defined by external means such as clock. Examples of synchronous sequential circuit are Flip Flops, Synchronous Counter. Asynchronous Sequential Circuit: Output can be changed at any instant of time by changing the input. It is a circuit whose state time depends solely upon the internal logic circuit delays. Example of asynchronous sequential circuit is Asynchronous Counter.

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Unit-5. Flip Flops & Sequential Logic Circuits Q:2

Enlist the difference between Combinational and Sequential circuits. Combinational Circuit

1 2 3 4 5 6 7

Sequential Circuit

It does not contain memory elements. It contains memory elements. Output depends on present state of input Output depends not only on the present only. inputs but also on the past history of inputs. It’s behavior is described by the set of It’s behavior is described by the set of nextoutput functions state (memory) functions and the set of output functions Does not use Feedback path. Does not require clock signal. Faster than sequential circuit. Example: Adder, Subtractor, Multiplexers, Encoders, etc.

Use Feedback path. Most of sequential circuit use clock signal. Slower than combinational circuit. Flip Flops, Registers, Counters, etc.

Q:3

What is Flip Flops?

Ans:

Memory element used in clocked sequential circuit is known as Flip Flop. It is capable of storing binary information. It is a Binary cell capable of storing one bit. A Flip Flop circuit can maintain a Binary state until directed by an input signal to switch into other state. It is also known as Bi-stable Multivibrator, because it has two stable states either ‘Logic 0’ or ‘Logic 1’. It can be also known as Latch. The Flip Flop is made up of an assembly of Logic Gates. Even though, a Logic gate by itself has no storage capability, several gates can be connected in such a way that, permit the information to be stored. There are various types of Flip Flops, like SR Flip Flop, D Flip Flop, JK Flip Flop, T Flip Flop etc. but the major difference between various Flip Flops, are in the number of inputs they possess and the manner in which the input affect the binary states at the output.

Q:4

Draw the circuit of Basic S-R Flip Flop using NOR gate and NAND gate. Also explain it with necessary truth table and characteristic equation.

Ans:

S-R Flip Flop (Set-Reset Flip Flop) Active High S-R Flip Flop: It can be constructed using NOR gate. Which is also known as ( S-R Latch) / (R-S Flip Flop) / (Set – Clear Latch)/ (S-C Latch). Figure 5.3 shows Basic Flip Flop circuit, upon which we can construct other type of Flip Flops. This type of Flip Flop is called direct coupled R-S Flip Flop. Here cross coupled connection constitutes the feedback path. This is an Asynchronous sequential circuit.

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Unit-5. Flip Flops & Sequential Logic Circuits ̅ OR Q and S-R Flip Flop has two inputs SET and RESET as well as two outputs Q and 𝑸 Q’. Both the outputs are complement of each other. For different combination of inputs, outputs are shown in Truth Table.

Figure 5.2 Symbol of S-R Flip Flop

Figure 5.3 Basic Flip-Flop Circuit with NOR Gates& Truth Table Working of Active High SR Flip Flop: - When S=1, R=0 then output is Q=1 (SET condition of Flip Flop) - When S=0, R=1 then output is Q=0 (RESET condition of Flip Flop) - When S=0, R=0 then output is Q=Q0(Previous condition of Flip Flop)/Memory State - When S=1, R=1 then output is Q=0, and Q´=0 (Invalid condition of Flip Flop as Q and ̅ are always complement of each other). 𝑸 Active Low S-R Flip Flop: It can be constructed using NAND gate. Figure 5.4 shows Basic Flip Flop circuit, using NAND Gate.

Figure 5.4 Basic Flip-Flop Circuit with NAND Gates

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Unit-5. Flip Flops & Sequential Logic Circuits

Figure 5.5 Truth Table of Active low SR Flip-Flop using NAND Gates Working of Active Low S-R Flip Flop : -

When S=1, R=0 then output is Q=0 ( SET condition of Flip Flop) When S=0, R=1 then output is Q=1 ( RESET condition of Flip Flop) When S=1, R=1 then output is Q=Q0 ( Previous condition of Flip Flop)/Memory State ̅ =1 ( Invalid condition of Flip Flop as Q and When S=0, R=0 then output is Q=1, and 𝑸 ̅ are always complement of each other) 𝑸

Active low S-R Flip Flop can be converted into Active High by connecting an Inverter at both the inputs OR by applying inverted inputs.

Q:5

What is the Need of clock/Triggering pulse in Sequential circuits? Also explain Types of Triggeringmethods.

Ans:

The output of a flip flop can be changed by bringing a small change in the input signal. This small change can be brought with the help of a clock pulse or commonly known as a trigger pulse. It is difficult to apply all the inputs simultaneously at the input terminal of flip flop, so to synchronize these inputs, a clock or triggering pulse is applied. When such a trigger pulse is applied to the input, the output changes and thus the flip flop is said to be triggered. Flip flops are applicable in designing counters or registers which stores data in theform of multi-bit numbers. But such registers and counters need a group of flip flops connected to each other as sequential circuits and these sequential circuits require trigger pulses. If a clock pulse is given to the input of the flip flop at the same time when the output of the flip flop is changing, it may cause instability to the circuit. The reason for this instability is the feedback that is given from the output combinational circuit to the memory elements. This problem can be solved to a certain level by making the flip flop more sensitive to the pulse transition rather than the pulse duration.There are mainly four types of pulse-triggering methods. They differ in the manner in which the Flip- Flop responds to the pulse.

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Unit-5. Flip Flops & Sequential Logic Circuits (1) High Level Triggering: When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used. It is mainly identified from the straight lead from the clock input. Take a look at the symbolic representation shown below.

Figure 5.6High Level Triggering (2) Low Level Triggering: When a flip flop is required to respond at its LOW state, a LOW level triggering method is used.. It is mainly identified from the clock input lead along with a low state indicator bubble. Take a look at the symbolic representation shown below.

Figure 5.7 Low Level Triggering (3) Positive Edge Triggering: When a flip flop is required to respond at a LOW to HIGH transition state, a POSITIVE Edge triggering method is used. It is mainly identified from the clock input lead along with a triangle. Take a look at the symbolic representation shown below.

Figure 5.8 Positive Edge Triggering (4) Negative Edge Triggering: When a flip flop is required to respond during the HIGH to LOW transition state, a NEGATIVE edge triggering method is used. It is mainly identified from the clock input lead along with a low-state indicator and a triangle. Take a look at the symbolic representation shown below. EE and EC Department

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Unit-5. Flip Flops & Sequential Logic Circuits

Figure 5.9 Negative Edge Triggering Q:6

Draw logic circuit diagram of Clocked S-R Flip Flop using NAND gate and explain it with necessary truth table and characteristic equation. Also draw logic circuit diagram using NOR gate.

Ans:

A Clocked RS Flip Flop requires a clocked pulse for synchronization purpose. It’s S and R input can control the output only when ENABLE (clock) signal is high. It is also known as clocked SR latch or Synchronous SR latch. This type of Flip Flop responds to the changes in input only when clock is HIGH. It is also called LEVEL TRIGGERED Flip Flop. Working of Clocked SR Flip-Flop: -

When S=1, R=0 then output is Q=1 which is SET condition of Flip Flop When S=0, R=1 then output is Q=0 which is RESET condition of Flip Flop When S=0, R=0 then output is Q=Q0 which is Previous condition of Flip Flop. It is also considered as Memory State. ̅ =0 which is Invalid/indeterminate When S=1, R=1 then output is Q=0, and 𝑸 ̅ are always complement of each other. condition of Flip Flop as Q and 𝑸

Figure 5.10 Circuit Diagram and Symbol of Clocked S-R Flip-Flop Figure 5.10 shows the circuit diagram & symbol of clocked SR Flip Flop. Truth table is derived from the above circuit base on previous state. In truth table Q(t + 1) indicates the next state and Q is previous state. Transition as per Truth table occurs only when clock pulse is HIGH i.e. Clock is ENABLE. The timing diagram of Level Triggered SR Flip Flop is shown in Figure 5.13.

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Unit-5. Flip Flops & Sequential Logic Circuits

. Figure 5.11 Truth Table of Clocked S-R Flip-Flop K-Map derived from truth table is as follow with characteristic equation. S=1, R=1 is considered as don’t care condition.

Figure 5.12 Characteristic Equation of S-R Flip-Flop Characteristic equation can be written as Q(next state) = S + R'Q and SR = 0 Timing Diagram:

Figure 5.13 Timing Diagram of S-R Flip-Flop EE and EC Department

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Unit-5. Flip Flops & Sequential Logic Circuits SR Flip Flop can be also derived using only NOR Gate as shown in Figure 5.14.

Figure 5.14 S-R Flip-Flop using NOR Gate Q:7

Draw logic circuit diagram of D-Flip Flop (Gated D Latch) using NAND gate and explain it with necessary truth table and characteristic equation. Also draw logic circuit diagram using NOR gate:

Ans:

D Flip Flop is a modification of Clocked SR Flip Flop. It is also known as gated D latch. The D Flip Flop receives designation ‘D’ from the ability to transfer ‘Data’ into a Flip Flop. It is basically a RS Flip Flop with an inverter at R Input. So number of input is only one in D Flip Flop.

Figure 5.15 D Flip-Flop using NAND Gate

Figure 5.16 Symbol and Truth Table of D Flip-Flop EE and E.C. Dept.

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Unit-5. Flip Flops & Sequential Logic Circuits D flip flop is actually a slight modification of the clocked SR flip-flop. From the figure you can see that the D input is connected to the S input and the complement of the D input is connected to the R input. The D input is passed on to the flip flop when the value of CP is ‘1’. When CP is HIGH, the flip flop moves to the SET state. If it is ’0′, the flip flop switches to the CLEAR state. Characteristic Equation of D Flip Flop:

Figure 5.17 Characteristic Equation of D Flip Flop D Flip Flop : Gated D Latch using NOR Gate:

Figure 5.18 D Flip-Flop using NOR Gate

Q:8

Draw logic circuit diagram of J-K Flip Flopusing NAND gate and explain it with necessary truth table and characteristic equation. Also draw logic circuit diagram using NOR gate.

Ans:

J-K Flip Flop using NAND Gate:

Figure 5.19 Logic diagram of J-K Flip-Flop using NAND Gate EE and EC Department

Analog and Digital Electronics(3130907)

9

Unit-5. Flip Flops & Sequential Logic Circuits The flip-flop is constructed in such a way that the output Q is ANDed with K and CP. This arrangement is made so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly Q’ is ANDed with J and CP, so that the flip-flop is cleared during a clock pulse only if Q’ was previously 1.

Figure 5.20 Symbol and Truth table of J-K Flip-Flop Working of JK Flip Flop using NAND gate: When J=K=0 When both J and K are 0, the output of the flip-flop is the same as its previous value. This is because when both the J and K are 0, the output of their respective NAND gate becomes 1 and it results in Q as well as Q’ same as previous value. When J=0, K=1 When J=0, the output of the NAND gate corresponding to J becomes 1but output of the NAND gate corresponding to K depends on previous value of Q. Therefore Q’ becomes 1 and Q becomes 0. This condition will reset the flip-flop. This represents the RESET state of Flip-flop. When J=1, K=0 In this case, the NAND gate corresponding to K becomes 1 but output of the NAND gate corresponding to J depends on previous value of Q’ Therefore Q becomes 1 and Q’ becomes 0. This condition will set the Flip-flop. This represents the SET state of Flipflop. When J=K=1 Consider the condition of CP=1 and J=K=1. When both the inputs J and K have a HIGH state, the flip-flop switches to the complement state. So, for a previous value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1. This will cause the output to complement again and again. This complement operation continues until the Clock pulse goes back to 0. Since this condition is undesirable, we have to find a way to eliminate this condition. This can be avoided by setting time duration of pulse lesser than the propagation delay through the flip-flop. But it very difficult to generate the pulse with duration less than propagation delay time. So the restriction on the pulse width can be eliminated with a master-slave JK Flip Flop or Edge-triggered JK Flip Flop. EE and E.C. Dept.

Analog and Digital Electronics(3130907)

10

Unit-5. Flip Flops & Sequential Logic Circuits Characteristic Equation for JK Flip Flop: From the truth table, characteristic equation can be derived as follows using K-Map.

Figure 5.21 Characteristic Equation for J-K Flip Flop

Timing Diagram for positive Edge Triggered JK Flip Flop:

Figure 5.22 Timing Diagram of Positive Edge Triggered J-K Flip-Flop Race around condition: If inputs of J-K flip-flop are J=K = 1, and Q= 0 and clock pulse is also HIGH i.eCP=1as shown in figure, then after a time interval Tp equal to propagation delay of NAND gates, the outputwill change to Q=1. Now, we have J=1, K=1 and Q=1. if duration of clock pulse (T)is greater than propagation delay, Tp , after another time interval of Tp theoutput will change back to Q=0, hence the output will oscillate back and forthbetween 0 and 1. The output is uncertain at the end of clock pulse if flip-flop islevel trigger. This situation is called race-around condition. The race-around condition can be avoided if clock pulse duration is reduced than the propagation delay of flip-flop, i.e., t