An Introduction to Contact Resistance 1536185019, 9781536185010

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MATERIALS SCIENCE AND TECHNOLOGIES

AN INTRODUCTION TO CONTACT RESISTANCE

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MATERIALS SCIENCE AND TECHNOLOGIES

AN INTRODUCTION TO CONTACT RESISTANCE

ZUOGUANG LIU EDITOR

Copyright © 2020 by Nova Science Publishers, Inc. All rights reserved. No part of this book may be reproduced, stored in a retrieval system or transmitted in any form or by any means: electronic, electrostatic, magnetic, tape, mechanical photocopying, recording or otherwise without the written permission of the Publisher. We have partnered with Copyright Clearance Center to make it easy for you to obtain permissions to reuse content from this publication. Simply navigate to this publication’s page on Nova’s website and locate the “Get Permission” button below the title description. This button is linked directly to the title’s permission page on copyright.com. Alternatively, you can visit copyright.com and search by title, ISBN, or ISSN. For further questions about using the service on copyright.com, please contact: Copyright Clearance Center Phone: +1-(978) 750-8400 Fax: +1-(978) 750-4470

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NOTICE TO THE READER The Publisher has taken reasonable care in the preparation of this book, but makes no expressed or implied warranty of any kind and assumes no responsibility for any errors or omissions. No liability is assumed for incidental or consequential damages in connection with or arising out of information contained in this book. The Publisher shall not be liable for any special, consequential, or exemplary damages resulting, in whole or in part, from the readers’ use of, or reliance upon, this material. Any parts of this book based on government reports are so indicated and copyright is claimed for those parts to the extent applicable to compilations of such works. Independent verification should be sought for any data, advice or recommendations contained in this book. In addition, no responsibility is assumed by the Publisher for any injury and/or damage to persons or property arising from any methods, products, instructions, ideas or otherwise contained in this publication. This publication is designed to provide accurate and authoritative information with regard to the subject matter covered herein. It is sold with the clear understanding that the Publisher is not engaged in rendering legal or any other professional services. If legal or any other expert assistance is required, the services of a competent person should be sought. FROM A DECLARATION OF PARTICIPANTS JOINTLY ADOPTED BY A COMMITTEE OF THE AMERICAN BAR ASSOCIATION AND A COMMITTEE OF PUBLISHERS. Additional color graphics may be available in the e-book version of this book.

Library of Congress Cataloging-in-Publication Data ISBN: 978-1-53618-501-0 Names: Liu, Zuoguang, editor. Title: An introduction to contact resistance / Zuoguang Liu (editor). Description: New York : Nova Science Publishers, Inc., [2020] | Series: Materials science and technologies | Includes bibliographical references and index. | Identifiers: LCCN 2020038446 (print) | LCCN 2020038447 (ebook) | ISBN 9781536185010 (paperback) | ISBN 9781536185836 (adobe pdf) Subjects: LCSH: Semiconductor-metal boundaries. | Electric contacts. | Electric resistance. Classification: LCC TK7872.C68 I58 2020 (print) | LCC TK7872.C68 (ebook) | DDC 621.3815/2--dc23 LC record available at https://lccn.loc.gov/2020038446 LC ebook record available at https://lccn.loc.gov/2020038447

Published by Nova Science Publishers, Inc. † New York

CONTENTS Preface Chapter 1

Chapter 2

vii Introduction to Semiconductor Transistor Resistances Zuoguang Liu Physics and Materials of Semiconductor-Metal Contacts Zuoguang Liu and Nicolas Breil

1

25

Chapter 3

Electrical Characterization of Contact Resistance Zuoguang Liu

51

Chapter 4

Contact Resistance Reduction Approaches Heng Wu

79

Chapter 5

Meta-Stable Alloys for Ultra-Low Contact Resistance Zuoguang Liu and Heng Wu

101

Low-Resistance Contact Integration in CMOS Technology Heng Wu

123

Chapter 6

vi Chapter 7

Contents Contact Engineering of Two-Dimensional Transition Metal Dichalcogenides Zhihui Cheng and Aaron D. Franklin

137

About the Editor

167

Index

169

PREFACE Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been the fundamental building block in integrated circuits (IC) over the past fifty years. Performance of the MOSFET is increased in each technology node according to the famous Moore’s Law. In the 1970s to 1990s, performance gain was mainly from the reduction of transistor gate length, thus charge carriers could travel a shorter distance for fast switching and high drive current. In the 1990s to 2000s, scaling the thickness of gate oxide SiO2 was the focus in performance step-up as higher gate capacitance with thinner oxide brings more drive current at the same operating voltages. Around end of the 2000s, scaling the SiO2 reached its limit, and high-K oxide replaced SiO2 to continue the Moore’s Law. As the MOSFETs become smaller and smaller, device parasitics start to dominate the performance since 22nm node in the 2010s. The resistance part in the MOSFET RC delay is mainly from external components particularly the source/drain contact. This is quite unexpected by a lot of semiconductor community who was betting on high mobility channels and carbon-based devices for future logic technology because those exotic devices all try to address device internal components rather than the external. In the past decade, 3-D MOSFETs, also named FinFETs, became the leading technology device structure, and it brings a unique opportunity

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Zuoguang Liu

for the contact resistance engineering. Among the device performance elements, contact resistance surpasses gate dielectrics, SiGe channel, and low-k materials in major semiconductor forums and journals in the past five years. MOSFET contact resistance is both an old and new topic. It is old because principles of the MOSFETs are well established since the early 1960s, and even earlier than the MOSFETs are the fundamentals of semiconductor-metal contacts which were established in the 1930s. In Chapter 1, we will go over basic device physics of modern MOSFETs with focus on the resistance components. Chapter 2 introduces Schottky-type and ohmic-type semiconductor-metal contacts. This is to provide background for the contact resistance topics in the following chapters. The new knowledge is on material and integration aspects for contact resistance reduction. Chapter 2 also discusses the contact metal, semiconductor substrate, and silicide materials for a low contact resistivity. Chapter 3 introduces the test structures and measurements of contact resistance, and explains how to calibrate the contact resistivity. Chapter 4 and Chapter 5 discuss the approaches for contact resistance reduction. State-of-the-art process techniques and material engineering are introduced. Integration of the contact resistance reduction into CMOS FinFET flow is presented in Chapter 6. Beside standard Si-based CMOS technology, 2-D devices based on transition metal dichalcogenides (TMDs) have attracted a lot of attention in recent years for energy storage, photonics, and sensors. However, the metal-2D contacts suffer from high resistance, which limits the 2-D devices in product application. As an expansion in this book, we introduce the 2-D TMDs and important aspects of their contact interface engineering in Chapter 7. The authors acknowledge IBM Research where the Si CMOS related content in this book is conducted. We thank Dr. O. Gluschenkov, for his guidance in the CMOS contact resistance work with his deep knowledge in thermal process, SPE, and LPE. I would like to acknowledge my doctoral advisor Professor T.P. Ma for his academic guidance; my colleagues in IBM for research and career support: Drs. H. Bu, T. Yamashita, D.C. Guo,

Preface

ix

and M. Khare. At the end, I would like to thank my family and friends for their encouragement and support along the way. Zuoguang Liu, Ph.D Guilderland, New York June 2020

In: An Introduction to Contact Resistance ISBN: 978-1-53618-501-0 Editor: Zuoguang Liu © 2020 Nova Science Publishers, Inc.

Chapter 1

INTRODUCTION TO SEMICONDUCTOR TRANSISTOR RESISTANCES Zuoguang Liu*, Ph. D. Semiconductor Technology Research, IBM, Albany, NY, US

ABSTRACT Transistors are basic building blocks in integrated circuits (IC), which have been evolving for generations since the 20 th century. Each generation doubles transistor density, increases operating frequency by 30-40%, and reduces 50% power compring to its predecessor. High performance transistors typically refer to their fast operating frequency which directly relates to RC delay. While the C is device capacitance, the R is overall device resistance. In recent 10 years, device scaling is so significant that major resistance is from external components of a transistor, of which source/drain contact contributes the most. Chapter 1 discusses basic device phyiscs of modern transistors, Metal-OxideSemiconductor Field Effect Transistors (MOSFETs), with focus on the resistance. This will give a high level picture of transistor achitecture, and provide background for the contact resistance topics in the following chapters.

Keywords: transistor, MOSFET, scaling, resistance, contact *

Corresponding Author’s Email: [email protected].

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Zuoguang Liu

INTRODUCTION The metal-oxide-semiconductor field-effect transistor (MOSFET) is the most important device for high density integrated circuits (IC) such as microprocessors and memories. The principle of the field-effect transistor was first proposed in the early 1930s by Lilienfeld [1-3] and Heil [4]. In 1960, Ligenza and Spitzer produced the first device-quality Si-SiO2 MOS system using thermal oxidation [5]. The first MOSFET was reported by Kahng and Atalla in 1960 [6]. Early development of the MOSFET can be found in [7-9]. Figure 1 shows the reduction of the gate length in product IC’s since 1970. This dimension has been decreasing at a steady rate and will continue to shrink in future. The reduction of device dimensions is driven by performance and density. The number of devices per chip has grown exponentially. The rate of growth is slowing down because of increasing technological challenge and cost. A number of 1 billion or more devices per chip had been available around 2000 using 0.1 um technology.

Figure 1. Minimum gate length in commercial IC as a function of production year.

Introduction to Semiconductor Transistor Resistances

3

Figure 2. Schematic diagram of a MOSFET.

In this chapter, the basic device characteristics will be introduced using long-channel MOSFETs in which the longitudinal field along the channel is not large enough to cause velocity saturation. In this regime, the carrier velocity is limited by mobility. As the channel length becomes shorter, short-channel effect has to be considered due to two-dimensional potential and high-field transport such as velocity saturation and ballistic transport.

BASIC DEVICE CHARACTERISTICS MOSFETs The basic structure of a MOSFET is illustrated in Figure 2. In this chapter, we assume that the channel carriers are electrons (e.g., n-channel MOSFET). All equations are applicable to the p-channel devices with proper substitution of parameters and reversal of voltage polarity. A common MOSFET is a four-terminal device that has a p-type semiconductor substrate where two n+-regions, source/drain (S/D) are constructed. The gate oxide is on top of the Si channel region. The metal contact on the gate oxide is called the gate. The basic device parameters are the channel length L, which is the distance between the two n+-p junctions; the channel width W; the oxide thickness d; the junction depth rj;

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Zuoguang Liu

and the substrate doping NA. In integrated circuits, a MOSFET is surrounded by thick oxide (e.g., field oxide) or a trench filled with insulator to electrically isolate it from adjacent devices. The source contact is used as the voltage reference. When ground or a low voltage is applied to the gate, the channel is turned off, and the S-to-D path corresponds to two p-n junctions connected back to back. When sufficient positive bias is applied to the gate and a surface inversion layer (e.g., channel) is formed between the two n+-regions, the S and D are connected by the conductive n-channel through which current can flow. The channel conductance can be modulated by the gate voltage.

Inversion Charge in Channel When a voltage is applied across the S-D contacts, the MOS structure is in a non-equilibrium condition; that is, the minority-carrier (e.g., electron) quasi-Fermi level EFn, is lowered from its equilibrium Fermi level. To show clearly the band bending across the device, Figure 3a [9] illustrates the MOSFET turned 90 deg. The two-dimensional, flat-band, and zero-bias (VG = VD = 0) equilibrium condition is shown in Figure 3b. The equilibrium condition under the gate bias which induces surface inversion is shown in Figure 3c. The non-equilibrium condition with both drain and gate biases is shown in Figure 3d in which the quasi-Fermi levels of electron EFn, and hole EFp are seprerated. The EFp remains at the bulk Fermi level while EFn is lowered toward the drain contact. Figure 3d shows that the VG required for inversion at the drain is greater than the equilibrium in which ψs(inv) ≈ 2ψB. The inversion charge at the drain end is lowered by the drain bias VD. This is because the applied VD lowers the EFn, and an inversion layer is formed only as the surface potential meets the requirement [EFn - Ei(0)] > qψB, where Ei(0) is the intrinsic Fermi level at x = 0.

Introduction to Semiconductor Transistor Resistances

5

Figure 3. 2-D band diagram of a n-channel MOSFET: (a) Device structure, (b) Flatband zero-bias equilibrium condition, (c) Equilibrium condition (VD = 0) under a positive gate bias. (d) Non-equilibrium condition under both gate and drain biases [9].

Figure 4 shows comparison of the charge distribution and energy-band variation of an inverted p-region for the equilibrium and non-equilibrium cases at the drain. In the equilibrium, the surface depletion region reaches maximum width WDm, at inversion. In the non-equilibrium case, the depletion-layer width is deeper than the WDm, and is a function of VD.

6

Zuoguang Liu

Figure 4. Comparison of charge distribution and energy-band variation of an inverted p-region in (a) equilibrium and (b) non-equilibrium at the drain end.

The surface potential ψs(y) of the drain at the onset of strong inversion is ψs(inv) ≈ VD + 2ψB.

(1)

The characteristics of the surface charge under the non-equilibrium condition are derived under two assumptions: (1) the majority-carrier quasi-Fermi level EFp is the same as that of the substrate and it does not vary with distance from the bulk to the surface (constant with x); (2) the minority-carrier quasi-Fermi level EFn is lowered by the VD by an amount dependending on the y-position. The first assumption introduces little error when the surface is inverted, because majority carriers can be negligible in the surface space charge. The second assumption is valid under the inversion condition, because minority carriers are an important part of the

Introduction to Semiconductor Transistor Resistances

7

surface charge at inversion. Based on these assumptions, the 1-D Poisson equation for the surface space-charge region at the drain end is 𝑑 2 𝜓𝑝 𝑑𝑥 2

𝑞

= 𝜀 (𝑁𝐴 − 𝑝 + 𝑛),

(2)

𝑛𝑖2 , 𝑛𝑝𝑜

(3)

𝑠

where 𝑝𝑝𝑜 = 𝑁𝐴 =

𝑝 = 𝑁𝐴 exp⁡(−𝛽𝜓𝑝 ),

(4)

𝑛 = 𝑁𝑝𝑜 exp⁡(𝜓𝑝 − 𝛽𝜓𝐷 ),

(5)

and β = q/kT. The charge due to minority carriers within the inversion layer, is given by 𝑥

𝜓 𝑛(𝜓𝑝 )𝑑𝜓𝑝 , 𝑑𝜓𝑝 ⁄𝑑𝑥 𝑠

|𝑄𝑛 | = 𝑞 ∫0 𝑖 𝑛(𝑥)𝑑𝑥 = 𝑞 ∫𝜓 𝐵

(6)

where xi stands for the point at which qψp(x) = EFn - Ei(x) = qψB. Eq. 6 is the exact formula to calculate the inversion charge Qn but can only be evaluated numerically. Alternatively, we can use the charge-sheet model which is simpler and much more useful for deriving the I-V characteristics of MOSFETs.

Charge-Sheet Model In the charge-sheet model, under strong-inversion conditions, the inversion layer is treated as a charge sheet with zero thickness (xi = 0). This assumption implies that the potential drop across this charge sheet is also zero. These conditions introduce some error but within acceptable extent.

8

Zuoguang Liu

From Gauss’ law, the boundary conditions on both sides of the charge sheet are: 𝐸𝑜𝑥 𝜀𝑜𝑥 = 𝐸𝑠 𝜀𝑠 − 𝑄𝑛 .

(7)

In order to calculate Qn(y) throughout the channel, the surface potential is generalized from Eq. 1 to 𝜓𝑠 (𝑦) ≈ ∆𝜓𝑖 (𝑦) + 2𝜓𝐵 , ∆𝜓𝑖 (𝑦) =

𝐸𝑖 (𝑥=0,𝑦=0)−𝐸𝑖 (𝑥=0,𝑦) , 𝑞

(8) (9)

where Δψi(y) is the channel potential with respect to the source end; and is equal to VD at the drain end. The electric fields can be expressed as: 𝐸𝑜𝑥 =

𝑉𝐺 −𝜓𝑠 𝑑

=

𝑉𝐺 −(∆𝜓𝑖 +2𝜓𝐵 ) , 𝑑

2𝑞𝑁𝐴 (∆𝜓𝑖 +2𝜓𝐵 ) , 𝜀𝑠

𝐸𝑠 = √

(10)

(11)

In Eq. 10, an ideal MOS system with zero work-function difference is assumed. Eq. 18 is the maximum field at the edge of the depletion region. Combining Eqs. 7-11 and using Cox = εox/d, we can obtain |𝑄𝑛 (𝑦)| = [𝑉𝐺 − ∆𝜓𝑖 (𝑦) − 2𝜓𝐵 ]𝐶𝑜𝑥 − √2𝜀𝑠 𝑞𝑁𝐴 [𝜓𝑖 (𝑦) + 2𝜓𝐵 ], (12) This Qn form will be used as the channel charge for the conduction current.

Introduction to Semiconductor Transistor Resistances

9

Current-Voltage Characteristics The basic MOSFET characteristics are derived under the following ideal conditions: (1) the gate corresponds to an ideal MOS capacitor, that means, there are no interface traps or mobile charges; (2) only drift current is considered; (3) channel doping is uniform; (4) reverse leakage current is negligible; and (5) the transverse field (Ex in x-direction) in the channel is much greater than the longitudinal field (Ey in y-direction). Note that in (1), the requirements of zero fixed oxide charge and zero work function difference are removed, and their effects are included in a flat-band voltage VFB required by the gate to make the flat-band condition. Consequently, the VG is replaced by (VG - VFB) for the inversion charge, giving |𝑄𝑛 (𝑦)| = [𝑉𝐺 − 𝑉𝐹𝐵 − ∆𝜓𝑖 (𝑦) − 2𝜓𝐵 ]𝐶𝑜𝑥 − √2𝜀𝑠 𝑞𝑁𝐴 [∆𝜓𝑖 (𝑦) + 2𝜓𝐵 ].

(13)

Under the above conditions, the channel current at any y-position is 𝐼𝐷 (𝑦) = 𝑊|𝑄𝑛 (𝑦)|𝑣(𝑦),

(14)

where v(y) is average carrier velocity. Since the current is continuous and constant throughout the channel, the integral of Eq. 14 from 0 to L gives 𝐼𝐷 =

𝑊 𝐿 ∫ |𝑄𝑛 (𝑦)|𝑣(𝑦)𝑑𝑦, 𝐿 0

(15)

The carrier velocity v(y) is a function of the y-position since the longitudinal field Ey(y) is a variable. The relationship between v(y) and Ey(y) is important to evaluate Eq. 15. We first consider the case of low Ey(y) so that the mobility is constant. For a shorter channel length, higher field causes velocity saturation and ballistic transport. These effects can be found in [10] 6.4.

10

Zuoguang Liu

Figure 5. Idealized drain characteristics (ID - VD) of a MOSFET. The dashed lines separate the linear, nonlinear, and saturation regions.

Constant Mobility Under the constant mobility assumption, substitutions of v = Eμ and Eq. 13 into Eq. 16 generates 𝐼𝐷 =

𝑊𝜇𝑛 𝐿 ∫0 |𝑄𝑛 (𝑦)|𝐸(𝑦)𝑑𝑦 𝐿

=

𝑊𝜇𝑛 𝐿 𝑑∆𝜓𝑖 (𝑦) |𝑄𝑛 (𝑦)| 𝑑𝑦 ∫ 0 𝐿 𝑑𝑦

=

𝑊𝜇𝑛 𝑉𝐷 ∫0 |𝑄𝑛 (Δ𝜓𝑖 )|𝑑Δ𝜓𝑖 , 𝐿

=

𝑊 𝜇 𝐶 {(𝑉𝐺 𝐿 𝑛 𝑜𝑥

− 2𝑉𝐹𝐵 − 2𝜓𝐵 −

2𝜓𝐵 )3⁄2 − (2𝜓𝐵 )3⁄2 ]},

𝑉𝐷 ) 𝑉𝐷 2

2 √2𝜀𝑠 𝑞𝑁𝐴 [(𝑉𝐷 𝐶𝑜𝑥

−3

+ (16)

Eq. 16 predicts that for a given VG, the drain current ID first increases linearly with drain voltage VD (linear region), then gradually levels off (nonlinear region), and finally approaching a saturated value (saturation region).

Introduction to Semiconductor Transistor Resistances

11

Figure 6. MOSFET operated (a) in the linear region (low VD), (b) at onset of saturation, and (c) beyond saturation (effective channel length is reduced).

The basic output characteristics of an idealized MOSFET are shown in Figure 5. The dashed line on the right indicates the locus of the drain voltage (VDsat) at which the current reaches a maximum value IDsat. For small VD, the ID is linear with VD. Between the two dashed lines are designated as the nonlinear region. A qualitative picture of the device operation is Figure 6. Considering a positive voltage applied to the gate, the voltage is large enough to cause inversion at the semiconductor surface. If a small VD is applied, a current will flow from the S to D through the conducting channel. The channel acts like a resistor, and the drain current ID is proportional to the VD. This is the

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Zuoguang Liu

linear region shown in Figure 6a. As the VD increases, the current deviates from the linear relationship with the VD as the charge near the drain end is reduced by the channel potential Δψi (Eq. 13). It eventually reaches a point at which the inversion charge at the drain end Qn(L) is reduced to almost zero. This location of Qn = 0 is called the pinch-off point as shown in Figure 6b. In reality, the Qn(L) is not zero for current continuity, but very small because of its high field and high carrier velocity. Beyond this drain bias, the drain current remains essentially the same, because for VD > VDsat, the pinch-off point moves toward the S, but the voltage at this pinch-off point remains the same VDsat. Thus, the number of carriers arriving at the pinch-off point from the S, and hence the current, remains essentially the same, except for a decrease in L to L’ (Figure 6c). This change of effective channel length will increase the drain current only when the shortened amount is a substantial fraction of the channel length, and it is considered part of the short-channel effects. We now derive the current equations for the three cases of linear, nonlinear, and saturation regions. In the linear region, with a small VD, using power series around VD and taking the initial terms 𝜓𝐵 𝑉 , 2 𝐷

(𝑉𝐷 + 2𝜓𝐵 )3⁄2 − (𝑉𝐷 + 2𝜓𝐵 )3⁄2 = 3√

(17)

Eq. 17 of the ID reduces to

𝐼𝐷 = =

𝑊 𝜇 𝐶 {(𝑉𝐺 𝐿 𝑛 𝑜𝑥

𝑊 𝜇 𝐶 (𝑉𝐺 𝐿 𝑛 𝑜𝑥

− 𝑉𝐹𝐵 − 2𝜓𝐵 −

− 𝑉𝑇 −

𝑉𝐷 ) 𝑉𝐷 , 2

𝑉𝐷 ) 𝑉𝐷 2

2 √2𝜀𝑠 𝑞𝑁𝐴 𝜓 (3√ 2𝐵 𝑉𝐷 )}, 𝐶𝑜𝑥

−3

for 𝑉𝐷 ≪ (𝑉𝐺 − 𝑉𝑇 ),

(18)

where VT is the threshold voltage, one of the most-important parameters 𝑉𝑇 = 𝑉𝐹𝐵 + 2𝜓𝐵 +

√4𝜀𝑠 𝑞𝑁𝐴 𝜓𝐵 , 𝐶𝑜𝑥

(19)

Introduction to Semiconductor Transistor Resistances

13

Further evaluation of Eq. 17 indicates that the current ID initially increases, then goes through a peak, and eventually drops with VD. The drop of current is not physical but corresponding to the condition that the charge in the inversion layer at the drain end Qn(L) becomes zero. The pinch-off point happens because the relative voltage between the gate and the semiconductor is reduced. The VD and ID at the pinch-off point are defined as VDsat and IDsat respectively. Beyond the pinch-off point the ID remains independent of VD and that is the saturation region. The value of VDsat is obtained from Eq. 13 under the condition Qn(L) = 0. The solution gives 𝑉𝐷𝑠𝑎𝑡 = ∆𝜓𝑖 (𝐿) = 𝑉𝐺 − 𝑉𝐹𝐵 − 2𝜓𝐵 + 𝐾 2 [1 − √1 +

2(𝑉𝐺 −𝑉𝐹𝐵 ) ], 𝐾2

(20)

where K = (εsqNA)1/2/Cox. The same solution can be obtained by dI/dVD = 0. The saturation current IDsat can be obtained by substituting Eq. 20 into Eq. 17: 𝑊

𝐼𝐷𝑠𝑎𝑡 = 2𝑀𝐿 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝑇 )2 , 𝑀 =1+

𝐾 2√𝜓𝐵

,

(21) (22)

The M is a function of doping concentration and oxide thickness. It has a value slightly greater than 1 and approaches 1 with thinner oxide and lower doping. In the saturation region with constant mobility, the current IDsat is a square-law function in Eq. 21, indicated by the increasing current steps between gate biases as shown in Figure 5. A more convenient form of the VDsat can be the following with mathematics transformation. 𝑉𝐷𝑠𝑎𝑡 =

𝑉𝐺 −𝑉𝑇 , 𝑀

(23)

The transconductance gm in the saturation region where Eq. 21 applies is

14

Zuoguang Liu 𝑑𝐼

𝑔𝑚 = 𝑑𝑉𝐷 | 𝐺

𝑊

𝑉𝐷 >𝑉𝐷𝑠𝑎𝑡

= 𝑀𝐿 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺 − 𝑉𝑇 ),

(24)

Lastly, the nonlinear region between the two extreme cases can be described 𝐼𝐷 =

𝑊 𝜇 𝐶 (𝑉𝐺 𝐿 𝑛 𝑜𝑥

− 𝑉𝑇 −

𝑀𝑉𝐷 ) 𝑉𝐷 . 2

(25)

Series Resistance in MOSFETs The MOSFET series resistance is an important parameter which significantly impact device performance. We will see later that the contact resistance is a big component of the series resistance especially in shortchannel devices. The series resistance between the source and drain consists of source resistance, channel resistance, drain resistance, and contact resistance. The source resistance RS and drain resistance RD are shown in Figure 7. They can be further partitioned into S/D contact resistance, the sheet resistance of the S/D (also called S/D series resistance), the junction extension resistance at the transition from S diffusion to the channel, and wiring resistance. The channel resistance is contained in the MOSFET symbol in Figure 7. In many places, the total resistance of a MOSFET is defined as Rtotal, the resistance of the channel and its proximity is called Rint (int: internal), and the rest is Rext (ext: external) [11, 12]. 𝑅𝑡𝑜𝑡𝑎𝑙 = 𝑅𝑖𝑛𝑡 + 𝑅𝑒𝑥𝑡 ,

(26)

Given the same channel material and doping, the channel-related resistance Rint largely depends on effective channel length (Leff). The Leff differs from the mask-defined gate length and also from the physical device gate length due to S/D junction encroachment under the gate, as shown in Figure 7, where Lm is the mask-defined gate length, L is the physical gate length, Lmet is the metallurgical channel length (distance

Introduction to Semiconductor Transistor Resistances

15

between S and D), and Leff is the effective channel length. To simplify the discussion in previous section, we treat the effective or electrical channel length the same as the physical gate length L and the distance between S and D (i.e., Leff = Lmet = L). But it is not always the case. For highly doped S/D with steep doping density gradient, the Leff is approximately equal to the physical length between S and D. However, for lightly doped drain structures, the Leff can be larger than the S/D spacing, because the channel can extend into the lightly doped S/D, especially for high gate voltages. We will now substitute the physical gate length L in the previous MOSFET current-voltage equations with the correct term Leff. If the effect of the series resistance (RS, RD) is considered according to Figure 7, the MOSFET current-voltage Eq. 18 in the linear region, valid for small VD, need to be changed with several new parameters.

Figure 7. (a) MOSFET with series resistances, (b) device cross section showing the actual gate length L and Leff = L - ΔL with ΔL = 2δL.

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The Eq. 18 is derived based on an intrinsic MOSFET without the series resistance, with the series resistance RD and RS, the VG and VD in Eq. 18 are equivalent to VGS’ and VDS’ in Figure 7 which are the potential inside the RS and RD. The actual applied gate-to-source voltage is VGS in Figure 7. Without body bias, the MOSFET I-V Eq. 18 in the linear region is then changed to, ′ 𝐼𝐷 = 𝑘 (𝑉𝐺𝑆 − 𝑉𝑇 − 𝑊

where 𝑘 = 𝐿

𝑒𝑓𝑓

′ 𝑉𝐷𝑆 ′ ) 𝑉𝐷𝑆 , 2

(27)

𝜇𝑒𝑓𝑓 𝐶𝑜𝑥 , and 𝜇𝑒𝑓𝑓 the effective mobility

′ ′ Ohm’s Law: 𝑉𝐺𝑆 = 𝑉𝐺𝑆 + 𝐼𝐷 𝑅𝑆 and 𝑉𝐷𝑆 = 𝑉𝐷𝑆 + 𝐼𝐷 (𝑅𝑆 + 𝑅𝐷 )

use symmetric S/D: 𝑅𝑆 = 𝑅𝐷 = 𝑅𝑆𝐷 ⁄2 𝑉𝐷𝑆 ) (𝑉𝐷𝑆 2 𝑉 𝑉𝑇 − 2𝐷𝑆 ) (𝑉𝐷𝑆

 𝐼𝐷 = 𝑘 (𝑉𝐺𝑆 − 𝑉𝑇 −

− 𝐼𝐷 (𝑅𝑆 + 𝑅𝐷 ))

 𝐼𝐷 = 𝑘 (𝑉𝐺𝑆 −

− 𝐼𝐷 𝑅𝑆𝐷 )

(28)

For the MOSFET in the linear region, the applied drain voltage VDS is low (50-100 mV), thus (VGS - VT) >> 0.5VDS for the device in strong inversion. With this condition, Eq. 28 becomes 𝐼𝐷 = 𝑘(𝑉𝐺𝑆 − 𝑉𝑇 )(𝑉𝐷𝑆 − 𝐼𝐷 𝑅𝑆𝐷 ) Plug in the k, 𝐼𝐷 = 𝐿

𝑊𝜇𝑒𝑓𝑓 𝐶𝑜𝑥 (𝑉𝐺𝑆 −𝑉𝑇 )𝑉𝐷𝑆 𝑒𝑓𝑓 +𝑊𝜇𝑒𝑓𝑓 𝐶𝑜𝑥 (𝑉𝐺𝑆 −𝑉𝑇 )𝑅𝐷𝑆

(29) (30)

Eq. 30 is the basis to determine RSD, μeff, and Leff. We can calculate the total resistance of the MOSFET using the Ohm’s Law: 𝑅𝑡𝑜𝑡𝑎𝑙 =

𝑉𝐷𝑆 𝐼𝐷

(31)

Introduction to Semiconductor Transistor Resistances

17

A different representation of Eq. 30 using the Rtotal is 𝑅𝑡𝑜𝑡𝑎𝑙 =

𝑉𝐷𝑆 𝐼𝐷

𝐿𝑒𝑓𝑓

= 𝑊𝜇

𝑒𝑓𝑓 𝐶𝑜𝑥

1 (𝑉𝐺𝑆 −𝑉𝑇 )

+ 𝑅𝑆𝐷

(32)

The first part of Eq. 32 on the right-hand side is related to the channel which changes according to the gate voltage VGS, and the second part RSD is independent to the channel and the VGS. With previous definition of the Rint and Rext, 𝑅𝑡𝑜𝑡𝑎𝑙 = 𝑅𝑖𝑛𝑡 + 𝑅𝑒𝑥𝑡 , 𝐿

1 , (𝑉 𝑒𝑓𝑓 𝑜𝑥 𝐺𝑆 −𝑉𝑇 )

𝑅𝑖𝑛𝑡 = 𝑊𝜇 𝑒𝑓𝑓𝐶

(33)

𝑅𝑒𝑥𝑡 = 𝑅𝑆𝐷 .

(34)

There are many types of mobility expressions. Here we use the simplest one that is constant μeff for the first order extraction of the series resistances. This method is based on Eq. 26, allowing the RSD and Rint to be extracted [13]. If the Rint is combined with the μeff from other method such as split C-V [14], the Leff can be obtained. In Figure 8, the Rtotal is plotted against 1/(VGS - VT). The slope of this plot is m = Leff/Wμeff Cox and the intercept on the Rtotal axis is the RSD. The method above for the series resistance extraction is based on the current-voltage relationship established without significant short channel effects. As the Leff and L less than 0.1 um, this method reaches its limit to give good accuracy of the Rint and Rext because the Rint is no longer a perfect linear function of the Leff due to the short channel effects. However, this method continues to be widely used for estimating the series resistances in semiconductor industry even for the technology development of devices with the gate length less than 30 nm because of its simplicity and good first-order approximation.

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Figure 8. Rtotal versus 1/(VGS - VT) for the RSD extraction.

MOSFET Resistance Partition We now look at the detailed resistance partition in a MOSFET in Figure 9. In Eq. 26, there is a gate voltage dependent part Rint, and a gate voltage independent part Rext. Most of the Rint is due to the channel which is controlled by the gate voltage. However, when the gate length is less than 30 nm, the fringing effect of the gate to the junction is not negligible comparing to the Rch. Thus, Rint = Rch + Rextn

(35)

where the Rextn stands for junction extension resistance. The sheet resistance of the S/D (or the S/D series resistance), RSD,srs, does not depend on gate voltage. The external resistance can be partitioned into the contact resistance RC between the silicide and the S/D, metal resistance in the contact trench RCA, VIA resistance RVIA, and wiring resistance RM. Rext = RSD,srs + RC + RCA + RVIA + RM

(36)

Introduction to Semiconductor Transistor Resistances

19

Figure 9. MOSFET resistance partition.

In the Rext partition Eq. 36, the RC stands out as a major component due to a metal-semiconductor contact barrier which will be discussed in the next chapter. The RSD,srs can become a serious issue in very small devices. For the size of the MOSFETs, a useful parameter is CPP, Contacted Gate (Poly) Pitch, which is the distance from one gate to the next gate. In the MOSFETs of 64 nm CPP or less, with a gate length of 20-24 nm, the S/D becomes very small, thus RSD,srs increases significantly [15]. The RCA is directly related to the trench dimension. As the CPP scales, the width of the contact trench reduces while the depth of the trench increases due to gate height growth, thus resulting in a higher RCA. The RVIA is small unless there is VIA contact process issue. The RM can vary depending on how the MOSFETs are wired and the wire width. Using the method of plotting Rtotal vs. 1/(VGS - VT), the intercept is the Rext and in most cases Rext ~ RC. If the transistors of multiple CPP’s and different sizes of the contact trench are available, separating the RSD,srs, RC, and RCA is possible. The RC can also be extracted using other test structures such as the TLM macros (will be discussed in Chapter 3) and compared to the resistance partition of the transistor measurement. The RVIA and RM can be obtained using VIA chain test macros. Along with the Rext, the Rint = (Rch + Rextn) combination can be calculated at fixed ID or (VGS - VT). For long channel devices, the Rch directly indicates the carrier effective

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mobility μeff, thus a critical parameter to study any impact to mobility from the gate stack and scattering effects of interface traps or bulk traps. For short channel devices with an overlapped junction, the Rextn is not negligible compring to the Rch, and partitioning these two is difficult.

MOSFET Device Performance: Resistance Perspective The performance of an IC chip is a big topic beyond the scope of this book. However, the chip performance is fundamentally related to its single building block, the MOSFET. From a simple RC-delay perspective, the MOSFET delay time constant τ is the reciprocal of MOSFET operating frequency f (e.g., τ = 1/f). If we want the MOSFET to switch fast, a small τ (or a high f) is desired. τ = R ∙ C,

(37)

where the R is turn-on resistance and the C is the capacitance in the RC loop. In Eq. 69, the C is the total capacitance of the MOSFET which increases as its dimension scales. A lot of engineering efforts have been put into reducing the parasitic C such as low-k spacer [16]. But in general, reducing the C alone to achieve the performance requirement on the technology roadmap is tough due to aggressive device scaling. Therefore, the resistance reduction is the major focus of performance step-up. The MOSFET turn-on resistance is an important performance parameter, which can be defined in the linear region as RON and the saturation region as Rsat. The Rsat is dominated by the channel resistance due to the pinch-off. The RON is balanced between the Rint and Rext. Also, from a circuit perspective, the transient between ON and OFF are more relevant to the RON than the Rsat. In semiconductor industry, the RON is defined at a given ID and VD from an ID - VG curve in the linear region. For example, if ID = 1 × 10-4 A/um and VD = 0.05V, RON = VD/ID = 500 Ω-um. The RON can be further partitioned into the Rint and RC components for a quantitative analysis of device parametric.

Introduction to Semiconductor Transistor Resistances

21

Figure 10. TCAD modeling for contact resistivity ρC impact on resistance component (a) RON and (b) RC in MOSFET of 14 nm/10 nm/7 nm technology nodes [17].

Impact of MOSFET Scaling to Device Performance Along the MOSFET scaling roadmap, the external resistance Rext, especially the contact resistance RC increasingly impacts the device performance. Figure 10 [17] shows the modeling of the impact to the RON and RC from contact resistivity ρC in 14 nm/10 nm/7 nm technology nodes. The ρC is the RC normalized to the contact area of the conducting current. As shown in Figure 10, both the RC and RON are increased significantly at a fixed ρC when the devices get smaller. For the 10 nm node, the ρC of less than 2 x 10-9 Ω-cm2 is required. Moving to the 7 nm node, an additional performance gain is needed for the ρC in a 10-10 Ω-cm2 range. These requirements are very challenging in material science and device design, which we will try to address later in this book.

CONCLUSION The MOSFETs are introduced in this chapter. We discuss the basic device phyiscs of MOSFETs from the resistance perspective, providing

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background for the contact resistance topics in the following chapters. MOSFET resistance partition method is introduced to understand different components of the series resistance. Transistor scaling puts the contact resistance reduction on the top priority for the performance step-up.

REFERENCES J. E. Lilienfeld, “Method and Apparatus for Controlling Electric Currents,” US Patent 1,745,175. Filed 1926. Granted 1930. [2] J. E. Lilienfeld, “Amplifier for Electric Currents,” US Patent 1,877,140. Filed 1928. Granted 1932. [3] J. E. Lilienfeld, “Device for Controlling Electric Current,” US Patent 1,900,018. Filed 1928. Granted 1933. [4] Heil, “Improvements in or Relating to Electrical Amplifiers and other Control Arrangements and Devices,” British Patent 439,457. Filed and granted 1935. [5] J. R. Ligenza and W. G. Spitzer, “The Mechanisms for Silicon Oxidation in Steam and Oxygen,” J. Phys. Chem. Solids, 14, 131 (1960). [6] D. Kahng and M. M. Atalla, “Silicon-Silicon Dioxide Field Induced Surface Devices,” IRE-AIEE Solid-state Device Res. Conf. (Carnegie Inst. of Tech., Pittsburgh, PA), 1960. [7] D. Kahng, “A Historical Perspective on the Development of MOS Transistors and Related Devices,” IEEE Trans. Electron Dev., ED23,655 (1976). [8] C. T. Sah, “Evolution of the MOS Transistor-From Conception to VLSI,” Proc. IEEE, 76, 1280 (1988). [9] H. C. Pao and C. T. Sah, “Effects of Diffusion Current on Characteristics of Metal-Oxide (Insulator)-Semiconductor Transistors (MOST),” IEEE Trans. Electron Dev., ED-12, 139 (1965). [10] S. M. Sze, Physics of Semiconductor Devices 3rd, John Wiley & Sons Inc., New Jersey, 2007. [1]

Introduction to Semiconductor Transistor Resistances

23

[11] Chen Zhang, Zuoguang Liu, Xin Miao, and Tenko Yamashita, “FinFET External Resistance Analysis by Extended Shift-and-Ratio Method,” IEEE Trans. Electron Dev., 65 (8), 3127-3130 (2108). [12] Y. Taur, “MOSFET channel length: Extraction and interpretation,” IEEE Trans. Electron Dev., vol. 47, no. 1, pp. 160-170 (2000). [13] F. H. De La Moneda, H. N. Kotecha and M. Shatzkes, “Measurement of MOSFET Constants,” IEEE Electron Dev. Lett., EDL-3, 10-12 (1982). [14] C. Sodini, T. Ekstedt, and J. Moll, Solid-State Electron. 25, 833 (1982). [15] Z. Liu, H. Wu, C. Zhang, X. Miao, H. Zhou, R. Southwick, T. Yamashita, D. Guo, “Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures,” 2019 Symposium on VLSI Technology, T146-T147 (2019). [16] T. Yamashita, et al., “A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs,” 2015 Symposium on VLSI Technology, 154-155 (2015). [17] O. Gluschenkov, Z. Liu, H. Niimi, et al., “FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys,” 2016 IEEE International Electron Devices Meeting, 17.2.1-17.2.4, (2016).

In: An Introduction to Contact Resistance ISBN: 978-1-53618-501-0 Editor: Zuoguang Liu © 2020 Nova Science Publishers, Inc.

Chapter 2

PHYSICS AND MATERIALS OF SEMICONDUCTOR-METAL CONTACTS Zuoguang Liu1,* and Nicolas Breil2 1

Semiconductor Technology Research, IBM, Albany, NY 2 Applied Materials, Sunnyvale, CA

ABSTRACT Contact between semiconductor and metal materials can be either Schottky-type or ohmic depending on the Schottky barrier height between the metal and semiconductor, doping concentration, and compounds (silicide) formed at the interface. Device and material phyiscs of the semiconductor-metal (MS) contact will be discussed in this chapter. The MS contact in transistors refers to transisitor source and drain (S/D) contacts which is desired to be ohmic with low resistance. The choice of metal materials for the MS contact in n-type or p-type transistors depends on the S/D materials. As the device scaling continues, yield and reliability issues related to the contact have to be considered. The S/D preparation for low resistance contact and silicidation processes will also be covered.

*

Corresponding Author’s Email: [email protected].

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Zuoguang Liu and Nicolas Breil

Keywords: Schottky barrier, ohmic contact, silicide, doping concentration, Ni, Ti, annealing, diffusion, yield

INTRODUCTION The metal-semiconductor (MS) contact is an important component of semiconductor devices. There are two types of MS contacts: Schottky contact (rectifying) and Ohmic contact (non-rectifying). The ohmic contact of low resistance is usually used in transistors to reduce device external resistance. Traditionally, the ohmic MS contacts use metal silicide MxSiy to achieve low contact resistance. Various metals, Ni, Co, and Ti, have been used. Since 14nm technology node around 2014, a liner silicide process of low thermal budget has been developed to obtain a thin interficial silicide layer. Recently, the MS contacts made by solid or liquid phase epitaxy (SPE or LPE) have demonstrated extremely low contact resistivity, more than one order lower than any other silicide contacts. Such state-of-the-art MS contact requires highly doped S/D materials and special “meta-stable” M:S alloys formed at the interface.

2.1. MS CONTACTS Different types of MS contacts are due to the mismatch of the Fermi levels (EF) of the metal and the semiconductor materials. It can also be viewed from the difference in their work functions (Φ). Figure 1 shows the energy band diagram of the MS contact. The vacuum level E0 is the energy level of a free electron in the vacuum if released from the material. The E0 is used to align the bands of the metal and the semiconductor. The work function Φ is defined as the energy between EF and E0. The electron affinity, χ is defined as the energy required to move an electron from E0 to the conduction band (EC): χ = (E0 – EC)

(1)

Physics and Materials of Semiconductor-Metal Contacts

27

Figure 1. Energy band diagram for ideal MS contacts: (a) ΦM > ΦS and (b) ΦM < ΦS.

When the metal and the semiconductor are brought together, an ideal MS contact is formed. If there is no electron movement during the contact formation, the band diagram for the contact is as Figure 1, where there is a mismatch for the Fermi level (EFM) in the metal and the Fermi energy in the semiconductor (EF). For the ideal MS contact, there are following assumptions:   

No oxide or charge layers at the MS interface No intermixing and diffusion between metal and semiconductor No impurities at the MS interface

The χ and metal work function ΦM are invariant properties which remain unaffected by the contacting process. The semiconductor work fuction ΦS is related to the electron affinity, EC and EF in the following relationship: ΦS = χ + (EC – EF)

(2)

where χ = (E0 – EF) However, the situations in Figure 1 are not equilibrium condition, as the metal EFM is not aligned with the semiconductor EF. Therefore, electrons will transfer between the semiconductor and the metal until their Fermi levels are aligned, which will cause the formation of a depletion region at the MS contact. With different properties of the MS interface,

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Zuoguang Liu and Nicolas Breil

two types of the MS contact are formed: rectifying Schottky contact and non-rectifying Ohmic contact.

2.1.1. Schottky Contact The Schottky contact refers to the MS contact of a large potential barrier height, Scottky Barrier Height (SBH), which is formed as the metal EFM and the semiconductor EF are aligned. The barrier height ΦB is defined as the energy difference between the band edge with majority carriers and the EFM. As the Schottky barriers can result in rectifying characteristics, it is normally used as a diode, which is a rectifying MS junction. Both n-type and p-type semiconductors can form the Schottky contact.

At Equilibrium (Applied Bias V = 0) Consider the case of ΦM > ΦS, electrons will transfer from the semiconductor to the metal due to their greater energy until the equilibrium is established. The net loss of electrons creates negative charge in the metal and positive charge in the semiconductor, which results in a depletion region and a growing barrier at the semiconductor surface. As a result, the equilibrium band structure for the metal and a n-type semiconductor is shown in Figure 2. The surface potential barrier ΦB (e.g., SBH) is a function of the metal and the semiconductor:

Figure 2. Flat band diagram of MS contact at equilibrium.

Physics and Materials of Semiconductor-Metal Contacts

29

ΦB = ΦM – χ, for n-type semiconductor

(3)

ΦB = (Eg/q) + χ – ΦM, for p-type semiconductor

(4)

The barrier results in a high resistance when there is a small applied voltage. Since the SBH can be changed by the bias, the effect of forward bias and reverse bias are different.

Effect of Biasing Consider the case of ΦM > ΦS, the current I is formed if there is an applied bias VA on the metal with the semiconductor grounded. (Figure 3) The I is positive when it flows from the metal to the semiconductor. Under a forward bias (VA > 0), the MS junction is illustrated in Figure 4. The metal EFM becomes lower than the semiconductor EF, resulting in reduction of the ΦB across the semiconductor. Consequently, it will be easier for electrons to pass over the barrier, making electron diffusion easier from the semiconductor to the metal. As the VA increases, the current will increase very fast as more electrons are able to overcome the barrier. There will be more electrons diffusing from the semiconductor to the metal than the electrons coming back to the semiconductor, a positive current will be generated across the MS junction. With reverse bias, a negative voltage is applied on the metal (VA < 0). The MS junction is illustrated in Figure 5. The metal EFM becomes higher than the semiconductor EF, resulting in an increase of the barrier across the MS junction. The large barrier will block the diffusion of electrons from semiconductor to the metal. Under a small reverse bias, only a small amount of electrons in the metal can overcome the barrier. Therefore, the current I is small under a reverse bias, which is the rectifying behavior.

Figure 3. MS contact under an applied DC bias.

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Figure 4. Energy band diagram and carrier movement at forward bias (VA > 0).

Figure 5. Energy band diagram and carrier movement at VA < 0.

In general, the current flowing through the Schottky contact can be defined with the applied voltage, which is like that of a pn-junction diode: 𝐼 = 𝐼0 (𝑒 𝑞𝑉𝐴⁄𝑘𝑇 − 1), where I0 is saturation currrent

(5)

Under forward bias (VA > 0), when the forward bias exceeds a few kT/q volts, the current will be dominated by the exponential term. For reverse bias (VA < 0), when the reverse bias is greater than a few kT/q volts, the exponential term can be neglected, resulting in a small saturated current: I = − I0. The I-V characteristics is shown in Figure 6.

Physics and Materials of Semiconductor-Metal Contacts

31

Figure 6. Schematic I-V characteristics of a Schottky diode.

2.1.2. Ohmic Contact If there is no potential barrier at the MS contact, the contact does not rectify current. With such condition, the current can be conducted in both directions of the MS contact, therefore the contact is ohmic. An ideal ohmic contact is low resistance, and non-rectifying with no potential between the metal-semiconductor interface. Consider the case in Figure 1(b) the MS contact with ΦM < ΦS, electrons will transfer from metal to semiconductor due to their low energy, causing the semiconductor EF to move up until equilibrium is established. The band diagram at the equilibrium is illustrated in Figure 7(a).

Figure 7. Ohmic MS contact: (a) energy band diagram at equilibrium for ΦM < ΦS, (b) schematic I-V characteristics of the ohmic MS contact.

Zuoguang Liu and Nicolas Breil

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Table 1. Electrical category of MS contacts

ΦM > ΦS ΦM < ΦS

n-type semiconductor Schottky Ohmic

p-type semiconductor Ohmic Schottky

Since there is no barrier for the electron flow from semiconductor to metal, a small forward bias (VA > 0) will induce a large forward-bias current. When there is a reverse bias (VA < 0), a small potential barrier is formed for the electron flow from metal to semiconductor. However, the small barrier will vanish when the reverse bias becomes greater. Consequently, there is a large reverse current when VA < 0. The I-V characteristic of the ohmic contact is illustrated in Figure 7(b). Different from the Schottky contact, the ohmic contact has a linear I-V curve that follows the Ohm’s Law in both forward and reverse bias. In summary, for metal on n-type semiconductor a Schottky contact is formed when ΦM > ΦS, and the ohmic contact is formed when ΦM < ΦS. For metal on p-type semiconductor, the MS contact is Schottky when ΦM < ΦS, and ohmic when ΦM > ΦS.

2.2. MATERIAL ENGINEERING FOR OHMIC MS CONTACT 2.2.1. Metals for MS Contact It is discussed in Chapter 1 that the turn-on resistance RON of the MOSFETs with the small CPP is dominated by the external component, especially the S/D contact resistance RC. The ohmic MS contact of low resistance is required for high performance low power devices. Ideally, we need to choose those metals which have zero or small potential barriers when in contact with the S/D (n-type or p-type). However, with the band gap of typical semidoncutors, 0.66eV for Ge and 1.1eV for Si, it is impossible for one single metal to make the ideal ohmic contact with both n- and p-type semiconductors. In addition, Fermi-level pinning due to

Physics and Materials of Semiconductor-Metal Contacts

33

metal-induced gap states at the MS interface can happen [1]. Figure 8 illustrates experimentally obtained SBH ΦB on n-type Si and Ge and reported metal work functions ΦM in a diagram [1]. It is worth noting that these numbers could be obtained on the Si and Ge with their dopant concentration less than 1 × 1019 cm-3. For doping levels higher than 1×1019 cm-3, there can be higher interface states density (Dit) which could induce even stronger Fermi-level pinning effect. For NFETs, S/D is n-type semiconductor of doping ~ 1 × 1019 cm-3 or higher, which gives its EF,n close to EC (C.B. in Figure 8). Based on Figure 8, it looks difficult to find a metal for ΦM < ΦS with the Fermi-level pinning effect. Similarly, for PFETs with its EF,p close to EV (V.B. in Figure 8), the Fermi levels of all metals fall within the semiconductor bandgap, making the ΦM < ΦS difficult. The alternative is to use the metals (Er, Yb, Y, La, Ti) with the EFM close to the EC for NFET S/D contact, and the metals (Ni, Pt) of the EFM close to the EV for PFET contact based on Figure 8 and Table 1. However, single contact metallization is preferred than individual metallizations on NFET and PFET in production. For example, in 32-22nm technology nodes, Ni is selected as the S/D contact metal [2]. In 14-7nm nodes, Ti is used for the contact [3]. The exotic metals, Er, Tb, Y, and La, are rarely used in semiconductor industry. People have explored them as contact metal for some novel 2D semiconductors such as CNT (carbon nanotubes) and MoS2 which will be discussed in Chapter 7.

2.2.2. Silicides A silicide is a compound of silicon and a metallic element. The composition of silicides cannot be easily specified as covalent molecules. The chemical bonds in silicides can be covalent, ionic, or metal-like bonds. Formation of silicides requires thermal energy when the metal is put in contact with Si. Thermal processes such as furnace annealing, and rapid thermal Annealing (RTA), can be used for silicidation reaction. A silicide layer between metal and semiconductor can reduce the MS contact

Zuoguang Liu and Nicolas Breil

34

resistance in two ways: first, the low sheet resistance of the silicide layer shunts the doped diffusion region of the S/D to reduce its in-plane resistance, and second the silicide reaction leads to more intimate and reliable MS contact and improves the conduction in vertical direction. Important properties of commonly used silicide materials are listed in Table 2 [4].

Figure 8. Experimental SBH on n-type Si and Ge and reported metal work functions [1]. Reprinted from [T. Nishimura, K. Kita, and A. Toriumi, Appl. Phys. Lett. 91, 123123, 2007], with the permission of AIP Publishing.

Table 2. Properties of common silicides: electrical resistivities are at 298 K [4]

Silicide

Resistivity (μΩ∙cm)

Annealing T (C)

Stablility on Si (C)

PtSi TiSi2 (C54) TiSi2 (C49) Co2Si CoSi CoSi2 NiSi NiSi2 WSi2 MoSi2 TaSi2

28 - 35 13 - 16 60 - 70 ~ 70 100 - 150 14 - 20 14 - 20 40 - 50 30 - 70 40 - 100 35 - 55

250 - 400 700 - 900 500 - 700 300 - 500 400 - 600 600 - 800 400 - 600 600 - 800 1000 800 - 1000 800 - 1000

~ 750 ~ 900

~ 950 ~ 650 ~ 1000 ~ 1000 ~ 1000

nm Si consumed per nm metal 1.12 2.27 2.27 0.91 1.82 3.64 1.83 3.65 2.53 2.56 2.21

nm silicide per nm metal 1.97 2.51 2.51 1.47 2.02 3.52 2.34 3.63 2.58 2.59 2.41

Barrier height to n-Si (eV) 0.84 0.58

0.65 0.66 0.67 0.64 0.59

Physics and Materials of Semiconductor-Metal Contacts

35

Figure 9. Ternary phase diagrams of (a) Ti on Si, and (b) Ni on SiC. Note that the temperature required for the reaction is not indicated in the diagrams.

Preferred silicides in semiconductor technology include TiSi2, NiSi, CoSi2, and NiPtSi due to their overall excellent properties. It was thought that TiSi2 and CoSi2 consumed excessive Si during formation thus not scalable to ultrashallow junction, while NiSi was suited for the junction. Recently years with new process development for good control on the TiSi2 formation, TiSi2 bcomes more popular than NiSi due to less diffiusivity of Ti than Ni in Si, which reduces yield failure of shorts in scaled devices. For TiSi2, C54 phase is preferred than C49 because of the low resistivity of the C54 phase. Ternary Phase Diagrams are usually used to indicate the stability of silicides of certain composition. Figure 9 shows the Ti-Si-O and Ni-Si-C ternary phase diagrams for the TixSiy and NixSiy stability [5]. Existance of a tie line indicates that the system is stable and a reaction will not happen. X-Ray Diffraction (XRD) is very useful to understand the compositions and phases of the silicides. Figure 10 shows XRD analysis of Ni and Ni0.9Pt0.1 thin films deposited on Si for NiSi and NiPtSi [6]. The silicide films show typical axiotaxy lines at the d-value corresponding to monosilicide Ni1−xPtxSi. Those groups of isolated diffraction spots indicate epitaxial alignment of the silicide grains with Si substrate. In-situ XRD can be performed during annealing process. Figure 11 shows in-situ XRD measurements of NiPt film deposited on Si and SiGe with annealing process followed [7]. Each anneal was done twice with different 2θ

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positions for the linear detector to capture both the Ni and some metal-rich peaks (50-60 deg) during one anneal, and the 020/013 NiSi peak at higher angle (60-75 deg) during the other anneal. The Ni peak disappears a little above 52 deg within about 10 C window slightly above 280 C. Therefore, the transition from Ni-metallic phase to metal-rich phases is not dramatically affected by the Ge addition. The detection of the metal-rich phases is difficult in this near θ-2θ geometry, because the texture of these phases is not necessarily aligned so that the crystalline planes are parallel with the surface of the substrate. The transition from the metal-rich phases to the monosilicide phase by the appearance of the 020/013 NiSi diffraction peak which is slightly above 65 deg, is delayed by the Ge addition. The strong signature of the metal rich phase of the NiPt film on SiGe (100), correlates with a delay in the formation of the monosilicide [7]. Salicide (Self-Aligned Silicide) process has been used in multiple technology nodes from 90nm to 22nm. The salicide process flow is shown in Figure 12: blanket metal deposition  selective silicide formation on Si (e.g., simultaneously silicide polysilicon gate and S/D regions) by thermal heating  wet chemistry removal of remaining metal  leaving selectively silicide regions. The salicide process is very sensitive to interface cleanliness and heavy doping. TiSi2 was extensively used for this process before NiSi salicide that help to reduce Si consumption for ultrashallow junctions.

Figure 10. XRD poles at d = 0.19 nm for silicide films formed with (a) 2 nm Ni, (b) 6 nm Ni, and (c) 2 nm Ni0.9Pt0.1 [6].

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Figure 11. In-situ XRD during annealing 10 nm NiPt10% film on (a) Si (100), (b) SiGe (100) substrates. Measurement has 2 steps, shown on a contour plot separated by a horizontal black line, to capture metal-rich and monosilicide phases [7].

Figure 12. Salicide process flow: simultaneous silicidation of polysilicon gate, S/D.

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2.2.3. Challenges and Evolution of Silicides NiSi Encroachment and “NiSi-Fang” Defects Ni-based silicides (NiSi, NiPtSi) have been widely used from 90nm to 22nm technology nodes due to its low silicide resistivity. However, defectivity concerns due to Ni encroachment or “NiSi-Fang” (Figure 13) [7, 8], more prevalent for scaled 3D devices, lead a transition to Ti-based silicde contacts [3] to preserve functional yield. The defect, Ni-silicide encroachment or “NiSi-Fang”, is not present after the silicide module, and when detected is exceptionally large considering that the source of available Ni is minimal at that point of the process. The silicidation process for Figure 13 includes an in-situ plasma clean followed by PVD Ni or NiPt deposition [7]. The formation of the silicide is achieved with a sequence of two rapid thermal annealing (300 C and 400 C) to complete the phase transformation from metal-rich silicide to monosilicide. Wet etching removes unreacted metal while avoiding attack of the silicide. The “NiSiFang” defect is shown in Figure 13, in which a significant amount of Ni has diffused from S to D, creating electrical shorts. In Figure 13a, the defect appears near the junction between the S/D and the shallow trench isolation (STI).

Figure 13. SEM and TEM images with elemental analysis of “NiSi-Fang” defect causing an electrical short between the S/D. The NiSi fang is located under the gate, at the boundary between the S/D and the STI [8].

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Figure 14. (a) XPS Ni2p spetra post NiSi formation and RIE processes followed by aqua regia cleaning. The peak shifts after the RIE from a Ni-monosilicide (853.8 eV) toward Ni2Si (853.3 eV). (b) Schematic illustration of the RIE impact on NiSi [7].

The phase of the fang defects is monosilicide NiSi without any Pt element. The defect does not develop during the formation of the silicide contacts, thus source of the available metal cannot be metallic Ni because unreacted metal is removed after the silicidation. The Ni in the defects originates from a metal-rich silicide transforming to monosilicide. As a Ni atom leaves a metal-rich area, the monosilicide forms both at that position and on its final destination – the defects. The monosilicide formed on the S/D could be exposed to various environments which may cause modifications at the surface. Reactive Ion Etching (RIE) plasma process which is used to trim nitride spacers could attack the silicide and cause serious depletion of Si. X-ray Photoelectron Spectroscopy (XPS) is used to study the modifications of the silicide surface in Figure 14. The Ni2p spectra is sensitive to various phases of the silicide. A first measurement after the NiSi formation was performed. The Ni2p peak is centered around 853.8 eV, which is expected for the monosilicide phase [9, 10]. Different RIE processes were then applied to the NiSi film. Precursors in the RIE process are based on fluorine-containing chemistries, oxygen, and various carrier gases. To remove surface contamination, the samples post the RIE process were treated with an aqua regia solution. A second XPS

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measurement was taken after the aqua regia, and a significant shift of the Ni2p peak occurs toward lower energy values centered around 853.3 eV (Figure 14), which is typical of a metal-rich phase such as Ni2Si [9, 10]. The RIE process thus could lead to the Ni-enrichment of the monosilicide, and to the re-formation of the metal-rich phases, such as schematically shown in Figure 14b. Mechanism of the NiSi-Fang formation can be described as follows. Once the monosilicide is formed, silicide oxidation or RIE can lead to Ni enrichment and formation of a metal-rich phase at the NiSi surface. In the processes afterwards, typical temperature in 400 C range is sufficient to force Ni diffusion and reform the monosilicide phase. In NFETs, the Ni diffusion can be in all directions. In PFETs, because the formation of the monosilicide on SiGe S/D is slow at the temperature, the vertical reaction path in the S/D is blocked. The free Ni follows a lateral path and reach a faster reaction region through the grain boundaries of the metal-rich or monosilicide phase. For annealing time of one second at 500 C, Ni can diffuse to distances of the order of a micron. Consider the thermal treatments post silicide which include 500 C peak termperature and several hours at 400 C. A diffusion distance of several microns for the Ni is realistic.

Ti Liner Silicide From the above discussion, we see that the Ni from the metal-rich phase can diffuse through the entire width of the S/D areas of the scaled MOSFETs on a standard product chip. This Ni encroachment defect pushes the development of different metal silicide solutions such as Ti liner silicide, and moving the silicide process after the S/D and gate modules to avoid exposure of exessive oxidation, RIE, and thermal processes for preventing the defect formation. In fact, historically Ti silicide was used before Ni silicide for the S/D contact. However, due to the excessive Si consumption during the TiSi formation, Ti was replaced by Ni. In addition, the resistivity of NiSi is generally better than TiSi. With the device-scaling showstopper, Ni encroachment, Ti silicide comes back in a revised process flow called liner

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41

silicide which is illustrated in Figure 15. The liner silicide flow starts after the gate and S/D formation at the end of front-end-of-line (FEOL) process. With increased complexity and importance of contact module, the processes of liner silicide and FEOL interconnect are usually given a separate name, Middle-of-Line (MOL). In the liner silicide flow, the S/D contact trench is first opened with a sequence of oxide/nitride RIE processes. Then, a shallow ion implantation of 5-10nm depth is performed through the nano-scale trenches to form a localized, amorphous mix of elements, Si:P (NFET) and SiGe:B (PFET), with targeted compositions. The amorphous mix is then subjected to rapid annealing (usually by laser) to induce fast solid/liquid phase epitaxy to re-activate the dopants in the amorphous region. Surface cleaning of wet or dry can be used prior to the metallization. The liner Ti and TiN, and W plug are deposited in the contact trench. Another annealing for silicidation with rapid thermal processes (RTA or laser) forms a thin TiSi layer of a few nanometers to complete the contact structure. Figure 15b shows a TEM image of the MS contact made with Ti liner silicide [11]. Key differences of the liner silicide process from traditional silicide include: The process is positioned after the formation of gate and S/D. There is no high temperature treatment or RIE touching the silicide during downstream processes, which prevent the metal encroachment. No metal removal is needed after the silicidation. Metal removal in traditional silicide process is done by very harsh wet chemistry, which increases the size of contact trench. With the CPP scaling, the increased trench size may cause S/D-to-gate shorts. The shallow ion implantation and the thermal activation boost active doping concentration, thus reducing the contact resistance (will be explained in 2.2.4 Transistor S/D Doping for Contact Resistance). All thermal treatments are fast annealing with RTA, spike, flash, or laser, which can provide high peak temperature of 700-1000 C while the total thermal budget equals 400-500 C furnace slow process. The low thermal budget minimizes the impact to the gate stack and junction.

Zuoguang Liu and Nicolas Breil

42

Figure 15. (a) Liner metal silicide process flow. Note: TiN liner is for W nucleation. (b) trench contact with Ti liner silicide [11].

Table 3. MS contact resistivity with different silicide processes on n-/p-type substrates Substrate p-Si0.6Ge0.4 p-Ge p-Si0.3Ge0.7 p-Si p-Si0.3Ge0.7 p-Ge p-Si0.25Ge0.75 n-Si n-Si n-Si

Metal Ni Ni Ti Pt NiPt Ti Ti Ti Ti Ti

Dopant B B B B B B + III B + III P P P

N (cm-3)

Process traditional silicide liner silicide + SPE liner silicide + SPE liner silicide (no SPE) liner silicide (no SPE) liner silicide + laser SPE liner silicide + laser SPE liner silicide + laser SPE liner silicide + laser SPE liner silicide + laser LPE

ρc (Ω-cm2) 2E-8 2.3E-9 2.1E-9 1.9E-9 1.5E-9 1.9E-9 7E-10 1.8E-9 1E-9 9E-10

Ref [13] [14] [15] [16] [17] [12] [18] [19] [19] [12]

N: doping concentration; III: group-III metal elements [12].

The liner silicide is the state-of-art MS contact process and has been used in all semiconductor foundries for advanced technology nodes. The lowest MS contact resistivity numbers are all achieved using the liner silicide process with variations in dopant, thermal treatment, or metallization (Table 3).

2.2.4. Transistor S/D Doping for Contact Resistance The S/D doping concentration and profile in transistors are very critical parameters, which impact device sub-threshold slope (SS), parasitic

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43

capacitance, RON, DIBL (drain induced barrier lowering), S-to-D leakage, and S/D contact resistance. The S/D doping could have different concentrations at the S/D surface and the S/D region near the channel. Here we focus on the S/D surface doping and its impact to the contact resistance. As we can see from 2.2.1, regardless of the Fermi-level pinning effect, it is difficult to find a metal of ΦM < ΦS for NFETs and at the same time ΦM < ΦS for PFETs. The MS contacts in all single-metal solution has some Schottky barrier, rather than ideal ohmic contact. However, with highly doped semiconductor, the I-V characteristics of the MS contact even with the barrier can be non-rectifying (e.g., ohmic). The reason of this ohmic behavior is the decrease of effective barrier thickness as the doping concentration N increases, resulting in significant tunneling current through the barrier at the MS interface. The tunneling current is field driven, thus its conduction is ohmic according to the voltage drop on the contact. The principal of the doping effect to the MS contact is shown in Figure 16 with band diagrams and associated I-V characteristics.

Figure 16. Effect of S/D doping to MS contact: band diagram and I-V characteristics.

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Zuoguang Liu and Nicolas Breil

Figure 17. Dopant solid solubility in (a) Si and (b) Ge. Data from [20].

To achieve the ohmic I-V characteristics of the contact, typically the N needs to be greater than 1019 cm-3. The higher the doping concentration, the lower the MS contact resistivity (ρc). The ρc can be estimated using Eq. 6-9 of the carrier tunneling through a barrier. 𝑗 = 𝑗𝑡ℎ𝑒𝑟𝑚𝑖𝑜𝑛𝑖𝑐 + 𝑗𝑡𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔 ,

(6)

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45

For high doping concentration N: 𝑗~𝑗𝑡𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔 𝑗𝑡𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔 = 𝑁𝑞𝑣𝑅 𝑒 −𝑉𝑏𝑎𝑟𝑟𝑖𝑒𝑟 ⁄𝑘𝑇 (𝑒 𝑉𝑏𝑖𝑎𝑠⁄𝑘𝑇 − 1),

(7)

𝑉𝑏𝑎𝑟𝑟𝑖𝑒𝑟 ≪ 1, 𝑗𝑡𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔 = 𝑁𝑞𝑣𝑅 (𝑒 𝑉𝑏𝑖𝑎𝑠⁄𝑘𝑇 − 1)

(8)

Small 𝑉𝑏𝑖𝑎𝑠 → 𝑒 𝑉𝑏𝑖𝑎𝑠⁄𝑘𝑇 = 1 + 𝑉𝑏𝑖𝑎𝑠 ⁄𝑘𝑇 𝑗𝑡𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔 = 𝑁𝑞𝑣𝑅 (𝑉𝑏𝑖𝑎𝑠 ⁄𝑘𝑇), 𝜌𝑐 ∙ 𝑗 = 𝑉𝑏𝑖𝑎𝑠 → 𝜌𝑐 = 𝑘𝑇⁄𝑁𝑞𝑣𝑅

(9)

We can see the ρc inversely proportional to N, which motivates the doping increase for lower contact resistance. It is important to note that the N here is active dopant concentration. The chemical doping injected by ion implantation and diffusion could have much higher concentration than the active dopants. But most of the chemical dopants may not be activated thus not contributing to the tunneling current to reduce the ρc. There is a limit of active doping concentration, solid solubility, for the dopants in semiconductors, shown in Figure 17. The active doping concentration also depends on the activation temperature [20]. The active doping concentration N can be extracted using transmission line measurement or 4-point measurement of the resistivity (ρ) or conductivity (σ = 1/ρ) of the doped semiconductor. The conductivity σ of a material is defined as the current density divided by the applied electric field E in Eq. 10. The carrier density and velocity can be expressed as a function of the electric field using the mobility. To include the contribution of electrons and holes to the conductivity in a general case, the current density due to electrons and holes are added together. For doped semiconductors, we can simply consider the majority carrier of n-type or ptype. The mobility μ of electrons (μn) and holes (μp) in a bulk semiconductor can be calculated using empiric Eq. 11, where the active doping concentration N contributes to carrier transport (e.g., mobility μ). The μmin, μmax, α, and Nr are fit parameters [21]. These parameters for Arsenic, Phosphorous and Boron doped Si are provided in Table 4. The electron and hole mobility versus the doping density N for Si is plotted in

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Figure 18a. Combining Eq. 11 and 12 where σ is measured and only N is the unknown, we can extract the active doping concentration N. The resistivity of n-type and p-type Si versus N is plotted in Figure 18b. σ = j/E = q(n∙μn + p∙μp)

(10)

μ = μmin + (μmax − μmin)/(1 + (N/Nr)α)

(11)

ρ = 1/σ = 1/q(n∙μn + p∙μp)

(12)

It is interesting to note that some of the reported doping concentration of the Boron in SiGe with high Ge% is 0.7 – 1 × 1021 cm-3 in Table 3, which is significantly higher than the Boron solid solubility 5.5 × 1018 cm-3 in Ge [20]. Similarly, in Table 3 the reported Phosphorus concentration 6 × 1021 cm-3 in Si is also much higher than its solid solubility in Figure 17. The record low contact resistivity numbers are associated with these highly doped substrates. As the solid solubility is for the dopants in their base states, the active doping concentration higher than the solid solubility indicates that some of the active dopants are in meta-stable states. To achieve the meta-stable states, special processes and techniques such as shallow amorphization implantation, fast laser annealing, and SPE/LPE, are needed. Table 4. Carrier mobility fit parameters

min (cm2/Vs) max (cm2/Vs) Nr (cm–3) 

Arsenic 52.2 1417 9.68×1016 0.68

Phosphorus 68.5 1414 9.20×1016 0.711

Boron 44.9 470.5 2.23×1017 0.719

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Figure 18. (a) Electron (red) and hole (blue) mobility versus doping concentration N for Si, (b) Resistivity of n-type (red) and p-type (blue) Si versus N.

CONCLUSION Principals of Schottky-type and ohmic-type MS contacts are explained in this chapter. Metal selections for the ohmic MS contact and associated Fermi-level pinning effect are discussed. Silicide materials and their formation are reviewed. Ni encroachment defects cause significant yield failure. Ti liner silicide requires low thermal budget and mitigates the metal encroachment. High doping of the S/D is a critical knob to reduce the MS contact resistance.

REFERENCES [1]

[2]

[3]

Tomonori Nishimura, Koji Kita, Akira Toriumi. “Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface,” Appl. Phys. Lett., 91, 123123, (2007). Narasimha, S; et al., “22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL,” 2012 IEEE International Electron Devices Meeting, 3.3.1-3.3.4, (2012). Lin, CH; et al., “High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu

48

[4]

[5]

[6]

[7]

[8]

[9]

[10] [11]

[12]

[13]

Zuoguang Liu and Nicolas Breil metallization,” 2014 IEEE International Electron Devices Meeting, 3.8.1-3.8.3, (2014). Krishna Saraswat. Standford University EE311 teaching materials, available to public, link: https://web.stanford.edu/class/ee311/ NOTES/Silicides.pdf. La Via, F; Roccaforte, F; Makhtari, A; Raineri, V; Musumeci, P; Calcagno, L. “Structural and electrical characterisation of titanium and nickel silicide contacts on silicon carbide,” Microelectronic Eng., 60, (2002), 269-282. Zhang, Z; Zhang, SL; Yang, B; Zhu, Y; Rossnagel, SM; Gaudet, S; Kellock, AJ; Jordan-Sweet, J; Lavoie, C. “Morphological stability and specific resistivity of sub-10 nm silicide films of Ni1−xPtx on Si substrate, “ Appl. Phys. Lett., 96, 071915, (2010). Breil, N; Lavoie, C; Ozcan, A; Baumann, F; Klymko, N; Nummy, K; Sun, B; Jordan-Sweet, J; Yu, J; Zhu, F; Narasimha, S; Chudzik, M. “Challenges of nickel silicidation in CMOS technologies,” Microelectronic Eng., 137, (2015), 79-87. Adusumilli, P; et al., “Ti and NiPt/Ti liner silicide contacts for advanced technologies,” 2016 IEEE Symposium on VLSI Technology, DOI : 10.1109/VLSIT.2016.7573382 (2016). Mangelinck, D; et al., “Enhancement of thermal stability of NiSi films on (100)Si and (111)Si by Pt addition,” Appl. Phys. Lett., 75, (1999), 1736. Lam, PL; et al., Surf. Coat. Technol., 203 (19), (2009), 2886-2890. Liu, Z; et al., “Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability,” 2017 Symposium on VLSI Technology, T212-T213, (2017). Gluschenkov, O; et al., “FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys,” 2016 IEEE International Electron Devices Meeting, 17.2.1-17.2.4, (2016). Liu, J; Ozturk, MC. “Nickel Germanosilicide contacts formed on heavily boron doped Si/sub 1-x/Ge/sub x/ source/drain junctions for nanoscale CMOS,” IEEE Trans. Electron Dev., vol. 52, iss. 7, p. 1535-1540, (2005).

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[14] Miyoshi, H; Ueno, T; Akiyama, K; Hirota, Y; Kaitsuka, T. “In-Situ Contact Formation for Ultra-Low Contact Resistance NiGe Using Carrier Activation Enhancement (CAE) Techniques for Ge CMOS,” 2014 Symposium on VLSI Technology, p. 146, (2014). [15] Yu, H; et al., “Ultralow-Resistivity CMOS Contact Scheme with PreContact Amorphization Plus Ti (Germano-) Silicidation,” 2016 Symposium on VLSI Technology, p. 66, (2016). [16] Stavitski, N; van Dal, MJH; Lauwers, A; Vrancken, C; Kovalgin, AY; Wolters, RAM. “Systematic TLM Measurements of NiSi and PtSi Specific Contact Resistance to n- and p-Type Si in a Broad Doping Range,” IEEE Electron Device Lett., vol. 29, iss. 4, p. 378381, (2008). [17] Zhen Zhang; et al., “Ultra Low Contact Resistivities for CMOS Beyond 10-nm Node,” IEEE Electron Dev. Lett., vol. 34, iss. 6, p. 723-725, (2013). [18] Wu, H; et al., “Integrated dual SPE processes with low contact resistivity for future CMOS technologies,” 2017 IEEE International Electron Devices Meeting, 22.3.1-22.3.4, (2017). [19] Niimi, H; et al., “Sub-10-9 Ω-cm2 n-Type Contact Resistivity for FinFET Technology,” IEEE Electron Device Lett., 37 (11), 13711374, (2016). [20] Trumbore, FA. “Solid Solubilities of Impurity Elements in Germanium and Silicon,” The Bell System Technical Journal, vol. 39, no. 1, p. 205 Jan, (1960). [21] Van. Zeghbroeck, B. Principles of Electronic Devices, Online Textbook, EECE Univ of Colorado (2011), resource available to general public, link: https://ecee.colorado.edu/~bart/book/book/ toca.htm.

In: An Introduction to Contact Resistance ISBN: 978-1-53618-501-0 Editor: Zuoguang Liu © 2020 Nova Science Publishers, Inc.

Chapter 3

ELECTRICAL CHARACTERIZATION OF CONTACT RESISTANCE Zuoguang Liu,* PhD Semiconductor Technology Research, IBM, Albany, NY, USA

ABSTRACT Contact resistance can be measured electrically using a voltagecurrent method. Transmission line measurement (TLM) based on large structures works for extracting specific contact resistivity in a certain range. As the contact resistivity reduces, measurement data need correction with current transfer length. Nano-TLM test structure is used in advanced technology development, and capable of calibrating low contact resistivity without the correction. There are a few other test structures for low contact resistance measurement with high precision. Besides the above special test structures for contact resistance, it is desirable to measure and extract the resistance from an integrated transistor. Kelvin transistors are designed for such on-the-fly

measurement, and proved good accuracy. In this chapter, we will discuss *

Corresponding Author’s Email: [email protected].

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Zuoguang Liu the test structures, electrical measurements, and how to calibrate contact resistivity.

Keywords: electrical characterization, TLM, contact resistivity, Kelvin FETs

INTRODUCTION Transmission Line Measurement (TLM) is commonly used to determine the contact resistance between metal and semiconductor. The measurement involves making a series of metal-semiconductor contacts separated by different distances. Current-Voltage (I-V) measurements are applied to the pairs of contacts, and the resistance R between them is calculated by Ohm’s Law. The resistance measured is a sum of the contact resistance RC, and the resistance Rsemi of the semiconductor in-between the contacts. When several such measurements are made between the pairs of contacts which are separated by different distances L, a plot of R versus L can be obtained to extract the RC and the semiconductor sheet resistance RSH. Variations of the TLM technique include NanoTLM [1-2], multi-ring circular TLM (MR-CTLM) [3], and Ladder TLM (LTLM) [4]. They are used to calibrate very low contact resistivity. It is also desired to measure the RC directly on transistors as the TLM requires special design of the test structures (macros) which are different from transistor-based VLSI circuits. There is local layout effect (LLE) which can induce process and structure variance even if both TLM and transistor macros are processed on the same wafer at the same time. Kelvin FET (RcFET) measurement is such a technique that can obtain the RC directly from the transistor [5].

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53

1. TLM FOR CONTACT RESISTANCE 1.1. TLM Consider a simple semiconductor resistor geometry in Figure 1. Two contacts are at the ends of the bar and each has a contact area AC. If a force current I, for example 10 uA, is applied, a corresponding voltage V can be sensed, thus total resistance R is determined by Eq.1. The R consists of several components. 𝑅=

𝑉 𝐼

(1)

𝑅 = 2𝑅𝑚 + 2𝑅𝐶 + 𝑅𝑠𝑒𝑚𝑖 𝑅𝑠𝑒𝑚𝑖 = 𝑅𝑆𝐻

𝐿 𝑊

(2) (3)

where Rm is the resistance due to the contact metal, RC is associated with the metal-semiconductor interface, and Rsemi is due to the semiconductor resistance between the two contacts. The resistance of a single contact is Rm + RC. In the situation of low metal resistivity (Rm ≪RC ) which is true in most cases, Rm can be neglected, thus the resistance of a single contact is RC.

Figure 1. I-V measurement of the contact resistance of a simple resistor.

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Resistors of several semidoncutor lengths (L) can be made, keeping all other components the same, the total resistance R of each resistor can be measured and plotted. In the limit of L = 0, the residual resistance is 2RC which can be extracted from Figure 2 by extrapolating to the intercept of the R-L line to the R axis. In the meantime, the RSH of the semiconductor can be obtained from the slope.

Figure 2. Extrapolation of RC and RSH using TLM measurement.

The contact resistance RC with units ohm depends on the size of the contact. A standard quantity as point of comparison for the contact independent of the contact area AC is contact resistivity ρC. Consider a small region in the vicinity of the contact in Figure 3: 𝑅𝐶 = 𝜌′

∆𝐿 𝐴𝐶

(4)

Electrical Characterization of Contact Resistance 𝜌𝐶 = lim 𝜌′ ∆𝐿 = 𝑅𝐶 ∙ 𝐴𝐶 ∆𝐿→0

55 (5)

The ρC in Eq.5 is independent of the contact area AC and has units ohm-cm2.

Figure 3. Contact resistance (RC) and contact resistivity (ρC).

Typicall TLM structures built on semiconductor wafers do not resemble the contact geometry in Figure 1. Instead, the contacts are located on the top, which is part of the planar TLM geometry shown in Figure 4. The current flow through the semiconductor is uniform, but the flow into the contact is not. With the non-uniform current flow in the contact, the AC can not be determined by the physical length and width of the contact. In Figure 5, the current flowing in and out is large at the edge of the contact. Moving away from that edge, the current drops off until, at the far edge, there is no current. This is known as “current crowding” effect.

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Figure 4. Planar TLM geometry.

Figure 5. Current crowding effect in the planar TLM measurement.

An analysis of the current crowding shows the drop-off in an exponential fashion with a characteristic length LT, which is known as the transfer length [6]. LT can be determined by Eq.6 for the planar TLM geometry. 𝜌

𝐿 𝑇 = √𝑅 𝐶

𝑆𝐻

(6)

The LT can be viewed as the effective length of the contact, and the average distance that a carrier travels in the semiconductor underneath the contact before flowing up into the contact. The effective area of the contact can be treated as LTW to replace the AC in Eq.4. The LT-ρC curve is plotted in Figure 6 using typical RSH values of doped Si materials.

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57

Figure 6. Lt-ρC curve with different RSH of Si substrate. [7]

The R-L plot in Figure 7 can also give the LT, by extrapolating the R-L line to the L axis, where the intercept is 2LT. 𝜌𝐶 𝑇𝑊

𝑅𝐶 = 𝐿

=

𝑅𝑆𝐻 𝐿𝑇 𝑊

𝑅 = 𝑅𝑠𝑒𝑚𝑖 + 2𝑅𝐶 =

(7) 𝑅𝑆𝐻 (𝐿 𝑊

+ 2𝐿 𝑇 )

Figure 7. Transfer length LT extraction using R-L plot from TEM measurement.

(8)

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Zuoguang Liu

A typical arrangement for a TLM test pattern is shown in Figure 8. There is a single rectangular region (blue) that has the same doping (i.e., same RSH) as the contact areas of the device. An array of contacts (grey) with various spacings, is formed over the doped region.

Figure 8. A typical TLM test pattern.

NanoTLM is enssentially a TLM with much scaled contact length LC of about 50 nm or less, which is typically smaller than the LT associated with the ρC and the semicondcutor. The length L of the semiconductor region (e.g., the gap between each pair of contacts) is a few hundred nanometers. The NanoTLM design makes the extraction of ρC straightforward without the need of calibrating LT. Since the physical contact length LC is so small that the current crwoding is negligible, the LT can be replaced by LC in Eq.7 in the NanoTLM: 𝜌𝐶 𝐶𝑊

𝑅𝐶 = 𝐿

(9)

With the NanoTLM design, a back-contact measurement scheme illustrated in Figure 9 can be used to extract the RC. A sensing terminal is placed on the other side of the current direction to measure the voltage VS below the contact. The voltage drop on the contact can be calculated as VF − VS. Using the Ohm’s Law, we get

Electrical Characterization of Contact Resistance 𝑅𝐶 =

𝑉𝐹 −𝑉𝑆 𝐼

59 (10)

Figure 9. NanoTLM back-contact measurement scheme.

This back-contact scheme relies on a uniform potential across the bottom of the contact otherwise the RC is underestimated. The condition of the uniform potential needs negligible current crowding, which is ensured by the NanoTLM. The TLM can give good accuracy of the ρC ~10-8 Ω-cm2 and above. The NanoTLM is effective in calibrating the ρC less than 10-8 (Ω-cm2) to low-10-9 (Ω-cm2) range. Fabrication of the NanoTLM structure requires advanced lithography and patterning tools in order to make sub-50nm features.

1.2. MR-CTLM The multi-ring circular TLM (MR-CTLM) technique [8] is shown in Figure 10. The MR-CTLM has simpler fabrication than the NanoTLM as the feature size of the MR-CTLM is several hundreds of nanometers and above. With the shrink of the contact trench due to device scaling, the resistance of contact metal fill could increase significantly. The metal resistance may not be negligible comparing to the contact inteface resistance in future technology. The RC measured by the TLM and

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Zuoguang Liu

NanoTLM includes the metal resistance, while the MR-CTLM could exclude the metal resistance with additional four-point measurement on the metal and associated modeling.

Figure 10. Schematic (a) top view and (b) section view of MR-CTLM. 10 CTLMs are connected in series. r0-r9 are inner radii of the CTLMs. E0, E1-E9, and Eout are labels of inner electrode, ring electrodes, and outer electrode, respectively. Sm is the spacing of electrodes. Ss is the width of each metal ring. Sm ranges from 0.35-10 um, Ss = 10 um, r0 = 30um, ri = r0 + i(Ss+Sm), (i = 1, 2, ... 9). [8]

In a MR-CTLM measurement, the probe P1 is put at the center of E0. The distance of P1 to P4 is several hundreds of microns (300 um in Figure 9). The probes P2 and P3 are put close to the ring edges.

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Figure 11. (a) Equipotential distribution in MR-CTLM based on lump model simulation. The potential profile along “cut” is (b). P1-P4 indicate probe positions. MRCTLM is the same to Figure 9. ρC = 1×10-8 (Ω-cm2) RSH = 100 (Ω/sq), RM = 0.2(Ω/sq), Sm = 1 um. E0 is the inner electrode; E1-E9 are annular electrodes; horizontal dashed lines are to compare the potential across each metal electrode. [8]

A lump model simulation of the MR-CTLM was performed in Figure 11. A series of rings compose a large effective resistance RE which is the contact resistance plus semiconductor resistance (resistance underneath the dielectric stack in Figure 10). A large ratio of the RE to the metal resistance renders the MR- CTLM insensitive to small probe placement deviations. In the MR-CTLM, equipotential along the rings is valid (Figure 11), because the metal resistance is negligible compared with RE. The total resistance R of the MR-CTLM can be divided into RE and RP (parasitic metal resistance). For a 10-ring MR-CTLM in Figure 10 with RSH ≪RM and ri ≫LT, the R can be calculated by [9]. 𝑅 = 𝑅𝐸 + 𝑅𝑃

(11)

𝑅𝐸 =

𝑅𝑆𝐻 9 𝑟 +𝑆 ∑𝑖=0 [ln ( 𝑖 𝑚) + 2𝜋 𝑟𝑖

𝑅𝑃 =

𝑅𝑀 9 𝑟 −𝐿 ∑ [ln ( 𝑖 𝑇 )], 2𝜋 𝑖=0 𝑟𝑖 −𝑆𝑆 +𝐿𝑇

1

1

𝐿 𝑇 (𝑟 + 𝑟 +𝑆 )] 𝑖

𝑖

𝑚

(12) (13)

where RM is the sheet resistance of the contact metal material which can be derived by four-point probe measurement. RSH and LT are extracted by fitting a set of R-Sm data using Eq.11-13. The contact resistivity ρC is derived from Eq.6.

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Zuoguang Liu

An example in Figure 12 illustrates the curve fitting and parameter extraction with the R-Sm data of MR-CTLM [8]. The small error bars in Figure 12 show the high precision of the measurement. A low ρC of (6.17 ± 0.35)×10-9 Ω-cm2 was extracted for the Ti/n-Si contact.

Figure 12 (a) Measurement and fitting of Ti/n-Si R-Sm data of MR-CTLM of Figure 10. (b) ρC and RSH extracted from MR-CTLM. MR-CTLM fitting are based on measurements of six chips. The solid dots and the error bars in (a) and (b) are averages and standard deviations of data, respectively.

1.3. LTLM The Ladder TLM (LTLM) technique features eliminated parasitic resistance from contact metal and access electrodes, simple fabrication process, and high resolution for accurate extraction of the contact resistivity ρC in 10-9~10-10 Ω-cm2 regime [4].

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Figure 13. (a) Schematic of the proposed ladder TLM (LTLM), (b) the distributive resistor network of LTLM. [4]

The LTLM idea is the placement of additional metal pads in the contact gap forming an additional metal/semiconductor (MS) region. Figure 13a shows LTLM schematic. A cross-sectional view along the line AA’ illustrates the distributive resistor network in the MS region. In a long contact case that the MS length LC is much greater than the transfer length LT, the current distribution in the MS region can be obtained by Kirchhoff's Loop Law. Figure 13b shows the current distribution and resistance partitions. The RC from the LTLM is consistent with that from a conventional TLM when the metal resistance Rshm is zero. The ρC is extracted by measuring the total R under various LC’s with given sheet resistance of the metal (RM) and the semiconductor (RSH). In the LTLM, the impact of access resistance from electrodes on the ρC is eliminated. Kirchhoff’s loop Law in Figure 13b:

64

Zuoguang Liu 𝜕𝐼𝑠 (𝑥) 𝜕𝑥

=−

𝑉(𝑥) 𝜕𝑉(𝑥) , 𝜕𝑥 𝜌𝐶

= 𝐼𝑚 (𝑥)𝑅𝑠ℎ𝑚 − 𝐼𝑠 (𝑥)𝑅𝑠ℎ𝑠 ,

𝐼0 = 𝐼𝑚 (𝑥) + 𝐼𝑠 (𝑥), 𝑥 𝐿𝑇

𝑥 𝐿𝑇

𝐼𝑠 (𝑥) = 𝐴 ∙ 𝑠𝑖𝑛ℎ ( ) + 𝐵 ∙ 𝑐𝑜𝑠ℎ ( ) + 𝜌𝐶

𝐿 𝑇 = √𝑅

𝑠ℎ𝑚 +𝑅𝑠ℎ𝑠

𝑅𝑠ℎ𝑚 𝐼 , 𝑅𝑠ℎ𝑚 +𝑅𝑠ℎ𝑠 0

,

(14)

RMS modeling (Lg >> LT): 𝐿𝑔

𝐼𝑠 (0) = 𝐼0 , 𝐼𝑠 ( 2 ) ≈ 𝐼𝑠 (∞) = 𝑅 𝐼𝑠 (𝑥) = 𝑅

𝑅𝑠ℎ𝑚

𝑠ℎ𝑚 +𝑅𝑠ℎ𝑠 𝐿𝑔

2

𝑅𝑠ℎ𝑚 𝑠ℎ𝑚 +𝑅𝑠ℎ𝑠

𝐼0

𝑥

𝐼0 (𝑒𝑥𝑝 (− 𝐿 ) + 1), 𝑇

𝑅𝑀𝑆 = 𝐼 ∫02 𝐼𝑠 (𝑥) 𝑅𝑠ℎ𝑠 𝑑𝑥, 0

𝑅𝑡𝑜𝑡𝑎𝑙 = 2𝑅𝑝 + 2𝑅𝑠 + 𝑅𝑀𝑆 , 𝑅𝑀𝑆 = 𝑅𝐶 =

2𝜌𝐶 𝐿𝑇

𝜌𝐶 𝐿𝑇

2 𝑅𝑠ℎ𝑚 ) +𝑅 𝑠ℎ𝑚 𝑠ℎ𝑠 2 𝑅

∙ (𝑅

∙ (𝑅

𝑠ℎ𝑚

𝑠ℎ𝑚 +𝑅𝑠ℎ𝑠

) ,

𝑅

𝑅

+ 𝐿𝑔 𝑅 𝑠ℎ𝑚+𝑅𝑠ℎ𝑠 , 𝑠ℎ𝑚

𝑠ℎ𝑠

(15)

Simulation in Figure 14 is used to quantify the resolution of the ρC obtained by the LTLM technique. An assumed value of the ρC in the simulation has to be correctly extracted by LTLM. The current density in the semiconductor decays exponentially from the leading edge of the contact in the MS region (Figure 15). Due to the finite metal resistance in LTLM, the current in the semiconductor does not entirely flow into the metal. For a long contact, the ratio of the total current in metal (IM) and semiconductor (IS) follows the current divider relationship. The total resistance R of the LTLM is extracted from the simulation and plotted as the dots in Figure 16. The fitting line using the LTLM model gives the RMS. The RC and ρC can be extracted using Eq. 14-15.

Electrical Characterization of Contact Resistance

65

Figure 14. Simulated current distribution (a) single-cell and (b) multi-cell LTLM. n+Si is used to verify the LTLM model. [4]

Figure 15. (a) modeled current density (line) along the contact (x-axis) is consistent with the simulation (symbols), (b) current distribution along BB’ line, showing that the modeled current distribution by LTLM matches the simulation. [4]

As the parasitic metal resistance is eliminated in the LTLM, the main factor limiting the accuracy of the LTLM is the current spreading and

66

Zuoguang Liu

crowding effect [10]. A difference of low 10-10 Ω-cm2 for the extracted ρC by the LTLM and the assigned ρC in the simulation is observed (Figure 17) due to the spreading resistance when the current crosses the contact interface and spreads into metal or semiconductor.

Figure 16. Simulated total resistance (symbols) of (a) single cell, (b) multicell structures. LTLM fit lines are shown to extract contact resistivity ρC. [4]

Figure 17. Difference of the ρC extracted by LTLM and simulation (LTSPICE) < 6% for an ultra-low ρC ~5×10-10 Ω-cm2 in the calibration. [4]

Electrical Characterization of Contact Resistance

67

2. KELVIN FET FOR CONTACT RESISTANCE 2.1. Kelvin FET (RcFET) Kelvin FET for RC measurement is also called RcFET [5]. The RcFETs are a series of transistors sharing their source (S) and drain (D) alternatively (Figure 18). Current IDS flows through the left transistor while the transistor source potential below the contact is sensed from the transistor on the right. The sensing transistor is biased at inversion. The inversion charge (QINV) in the channel of the sensing transistor directly senses the potential where it contacts.

Figure 18. Direct RC partition on RcFETs with a Kelvin measurement. [5]

Figure 19 shows simulation of the sensed potential with transistor parameters based on 14nm technology node. At 80nm CPP, the potential across S/D along the vertical direction (x-axis in Figure 19) is relatively constant due to sufficient S/D volume and good S/D resistivity.

68

Zuoguang Liu

Figure 19. Simulated potential map across S/D. [5]

The RC is calculated as the voltage drop (VS/D−Vsense) on the contact divided by IDS. The voltage drop is the difference of the sensed potential at the S/D and the terminal voltage VS/D (Figure 18). 𝑅𝐶 =

𝑉𝑆/𝐷 −𝑉𝑠𝑒𝑛𝑠𝑒 𝐼𝐷𝑆

⁡

(16)

Measurement of the sensed potential Vsense at the S/D (e.g., Vsource and Vdrain in Figure 20) on the RcFET is shown in Figure 20. The asymmetry of the RC at S and D (noted by the “S” “D” in Figure 20) can also be captured by this RcFET method.

Electrical Characterization of Contact Resistance

69

Figure 20. RC partition by RcFET: sense in S/D for potential drop on the contact. [5]

The correlation of the RcFET technique and the TLM technique is shown in Figure 21. Because the potential is sensed on the other side of the S/D where the current flows in, the RcFET method gives a RC value similar to that from a back-contact NanoTLM scheme.

70

Zuoguang Liu

Figure 21. Correlation of direct sensing using RcFET to the TLM: the Kelvin measurement obtains similar RC to back-contact NanoTLM. [5]

Kevin FET Characterization of Lateral Gate-All-Around (LGAA) FET More-Moore logic device roadmap [11] suggests Lateral/Vertical Gate-All-Around (LGAA/VGAA) device architectures beyond FinFETs for further scaling and performance (Figure 22). At extremely scaled gate pitches, parasitic resistance significantly impacts the device performance. Stacked LGAA or NanoSheet (NS) FETs at 50-44nm CPP exhibit high S/D series resistance (Rsrs) due to their high-rise S/D from the stacked channel and small S/D volume. The contact resistance RC also increases with scaling the contact area. The Kelvin FET method can partition Rsrs and RC on the LGAA FETs.

Figure 22. IRDS logic device roadmap and their outstanding components in external resistance. CPP: FinFET 80-56nm, LGAA 50-44nm, VGAA 40-27nm.

Electrical Characterization of Contact Resistance

71

Figure 23. Kevin FET partition RC and Rsrs in stacked LGAA FETs: scaled LGAA FETs with tall and small S/D: sensed potential includes voltage drop on Rsrs. [5]

j(x0) = 0, V(x,y) = constant = V(∞,y) is the measured Vsense No net current passing the vertical interface (Figure 23): 𝐻

𝐻

∫0 𝑗𝑥 𝑑𝑦 = − ∫0 𝜎𝑥

𝜕𝑉(𝑥,𝑦) 𝜕𝑥

𝜎𝑐ℎ =𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝜕

𝐻 ∫ 𝜕𝑉(𝑥, 𝑦)𝑑𝑦 𝜕𝑥 0

𝑑𝑦 = 0 →

+

=0

Averaged potential: 𝑉𝑎𝑣𝑒 = ∫0𝐻 𝜕𝑉(0 𝐻,𝑦)𝑑𝑦 = ∫0𝐻 𝜕𝑉(∞,𝑦)𝑑𝑦 = 𝑉𝑠𝑒𝑛𝑠𝑒 𝐻

(17) (18)

From Eq. 17-18 and Figure 23, we can see that the sensed S/D potential is an average along the vertical direction of the nanosheet’s. The Rsrs of the small S/D and its over-fill is included in the extracted RC with the Kelvin method (Figure 23). The Rsrs significantly impacts the partition accuracy at CPP less than 50nm. However, the effect of Rsrs is much reduced in large LGAA FETs with big S/D.

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Figure 24. Kelvin FET partition RC, Rsrs in stacked NSFETs: different pitches. [5]

Figure 24 shows the Kelvin method performed on NSFETs of 48nm and 250nm CPP’s with similar LC = 17-20nm. The ρC of the two devices on the same wafer is identical. Correlating the two sets of partition, RC and Rsrs of the scaled NSFETs can be obtained as in Figure 24. The ρC extracted on the NSFETs of a large CPP is compared to the ρC measured on the TLM structure, showing the similar value in Figure 24-25, which indicates RC,250cpp >> Rsrs,250cpp in the 250nm pitch case. It is worth noting that the Rsrs is a significant portion in the external resistance of the scaled NSFETs, comparable to the RC of the small contact (LC < 20nm).

Figure 25. Correlation of direct sensing to TLM in stacked LGAA devices. [5]

Electrical Characterization of Contact Resistance

73

Kevin FET Characterization of Vertical Gate-All-Around (VGAA) FET VGAA FETs have a very different structure from FinFETs or LGAA FETs in its vertical channel (Figure 22). Thanks to the relaxed contact area in the VGAA structure, the ρC requirement for a competitive VGAA FET is relaxed even at 40-27nm gate/fin pitch comparing to the LGAA FET. But the spreading resistance (Rsprd) of the bottom S/D can be high for the current flow at the end of fin. The asymmetric S/D of the VGAA FET also results in different contact resistances at the bottom and the top. Kelvin VGAA FETs and measurement methodology can be utilized to partition these resistance components.

Figure 26. Kelvin partition of VGAA FETs: bottom S/D Rb,C and Rsprd. [5]

Figure 26 illustrates partition of the bottom Rb,C and Rsprd using VGAA Kevin FETs. The potential Vsense1 is sensed on the side of the active bottom S/D contact (Force1) for the Rb,C partition. The Vsense2 is measured on the other side of the vertical channel for the voltage drop (Vsense2 – Vsense1) due to the current spreading in the bottom S/D. Note that there is another sense terminal Vm on top of Force1 metal contact to exclude wiring resistance Rm. Linearity of the sensed potentials versus the S/D current Ids indicates the ohmic behavior of the Rb,C, Rsprd, and Rm, Rb,C = (Vsense1 – Vm) / Ids

(19)

Rsprd = (Vsense2 – Vsense1) / Ids

(20)

74

Zuoguang Liu Rm = Vm / Ids

(21)

It is found that the Rsprd strongly depends on the doping and depth of bottom S/D. The Rsprd takes a significant portion in the external resistance of the VGAA FETs even for a lateral fin length less than 50nm [5].

Figure 27. Kelvin partition of top drain contact resistance Rc,t in VGAA FETs: (a) simulation, (b) Rc,t is overestimated due to crowding current jcrwd. [5]

At the top S/D, RC,t is the major parasitic component while the top spreading resistance is small because of the VGAA FET structure (Figure 27). However, sensing the exact potential Vtop in the top D below the contact is difficult due to the current crowding (jcrwd) effect. The sensed potential Vsns2 in Figure 27a has a discrepancy from the Vtop of over 20% due to the jcrwd, resulting in overestimating the RC,t. The current crowding effect also manifests non-linearity in the plot of Vsns2 versus Ids. Impact of

Electrical Characterization of Contact Resistance

75

the current crowding effect could be suppressed by lowering the sheet resistance of the top D.

Figure 28. Improved VGAA Kelvin FET design for Rc,t partition: (a) tri-top contacts with middle sense terminal to reduce drain current crowding, (b) simulated potential. [5]

An improved VGAA Kevin FET design for the RC,t partition is shown in Figure 28: tri-top contacts with the drain voltage sense in the middle and two-side current terminals. Simulation shows that the sensed potential Vsns at the middle has only 5% or less discrepancy from the potential Vtop directly under the drain (Figure 28b). [5]

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SUMMARY In this chapter, we explain test structures and electrical measurements for the contact resistance. Conventional TLM measurement works well for the contact resistivity extraction with the correction of transfer length. The NanoTLM of a small contact length is capable of calibrating the contact resistivity in 10-9 Ω-cm2 range without the correction. Kelvin FETs are designed to measure and extract the contact resistance from integrated transistors. Principals of the Kevlin FET method is explained in detail. Application of the Kelvin FET in partitioning the external resistance components in advanced transistor architectures (FinFET, LGAA and VGAA FETs) demonstrates its great usefullness in analyzing the device parametrics.

REFERENCES [1]

[2]

[3]

[4]

[5]

Zhen Zhang et. al., “Ultra Low Contact Resistivities for CMOS Beyond 10-nm Node,” IEEE Electron Dev. Lett., vol. 34, iss. 6, p.723-725 (2013) Robert Dormaier, and Suzanne E. Mohney, “Factors controlling the resistance of Ohmic contacts to n-InGaAs,” J. Vac. Sci. Technol. B 30, 031209 (2012). Hao Yu, et.al., “Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction,” IEEE Electron Device Lett., vol. 36, no. 6, pp. 600-602 (2015). Y. Wu, et. al., “A Novel Fast-Turn-Around Ladder TLM Methodology with Parasitic Metal Resistance Elimination, and 2× 10-10 Ω-cm2 Resolution: Theoretical Design and Experimental Demonstration,” 2019 Symposium on VLSI Technology, T.150-151 (2019). Z. Liu, H. Wu, C. Zhang, X. Miao, H. Zhou, R. Southwick, T. Yamashita, D. Guo, “Direct Partition Measurement of Parasitic

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Resistance Components in Advanced Transistor Architectures,” 2019 Symposium on VLSI Technology, T146-T147 (2019). [6] Chapter 3, “Semiconductor material and device characterization 2nd Edition,” by Dieter Schroder, John Wiley Inc. (1998). [7] Sidhant Grover, “Effect of Transmission Line Measurement (TLM) Geometry on Specific Contact Resistivity Determination,” (2016). Thesis. Rochester Institute of Technology. [8] H. Yu, et. al., “Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction,” IEEE Electron Device Lett., vol.36, iss.6 (2015). [9] G. S. Marlow and M. B. Das, “The effects of contact size and nonzero metal resistance on the determination of specific contact resistance,” Solid-State Electron., vol. 25, no. 2, pp.91-94 (1982). [10] H. H. Berger, “Models for contacts to planar devices,” Solid-State Electron., vol.15, no.2, pp.145-158 (1972). [11] IRDS 2017, “International Roadmap for Devices and Systems, 2017 Edition, More Moore,” available to general public access, web link: https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf.

In: An Introduction to Contact Resistance ISBN: 978-1-53618-501-0 Editor: Zuoguang Liu © 2020 Nova Science Publishers, Inc.

Chapter 4

CONTACT RESISTANCE REDUCTION APPROACHES Heng Wu*, PhD Semiconductor Technology Research, IBM, Albany, NY, US

ABSTRACT In this chapter, we will discuss key aspects in contact resistance reduction: optimizing contact resistivity (ρc) to be below 2 × 10-9 Ω·cm-2, enlarging contact area by widening the contact. Methods to improve the ρc will be reviewed and investigated including: increasing in-situ dopant concentration of materials of transistor source/drain (S/D), dopants activation via various thermal processes, solid phase epitaxy (SPE) and liquid phase epitaxy (LPE) processes in metal contact formation, Schottky barrier engineering at metal to semiconductor interface with different contact liners, and tuning material contents of the S/D. In following, improvement of the contact area will be explored with regard to: increasing the contact dimension by gauging the S/D epitaxy, and using wrapped around contact (WAC) to enlarge contact area. In the end, a summary of the approaches and their applications in different technologies will be given. *

Corresponding Author’s Email: [email protected].

Heng Wu

80

Keywords: contact resistance reduction, contact resistivity (ρc), SPE, LPE, dopant, interface, Schottky barrier, contact area, WAC

4.1. TECHNIQUES FOR CONTACT RESISTANCE REDUCTION IN ADVANCED TECHNOLOGY The needs for continuous scaling [1-4] in state-of-the-art CMOS technology urge the minimization of geometrical dimensions of transistors. However, the transistor’s performance is highly affected by geometrical sizes.

(a)

(b)

Figure 1. Decoupling of a typical FinFET resistance: a) Schematic of FinFET across the gate direction in the fin region with each resistance component marked b) Schematic of FinFET across the fin direction in the Source/Drain region [5].

Figure 1 shows the partition of transistor resistance in a typical FinFET structure [5], the overall transistor resistance can be separated as internal resistance (RINT) governed by gate bias, and external resistance (REXT) which is independent of the gate bias. Furthermore, the RINT is composed of channel resistance (RCH) and spacer/extension resistance (RSPC). Inherited from smaller dimensions, high external resistance is one of the

Contact Resistance Reduction Approaches

81

key hurdles for progressive performance improvements in recent technology nodes. As for the external resistance, it can be partitioned into source/drain epitaxy series resistance (REPI), metal to S/D semiconductor contact resistance (RC) and contact metal stud resistance (RMETAL). Among these resistive components, the RC contributes to majority of the external resistance, and elevated RC is mainly caused by smaller contact area associated with transistor scaling and high contact resistivity at such small dimensions. In this chapter, we will investigate two key aspects in contact resistance reduction: 1) optimizing contact resistivities (ρC) and 2) enlarging the contact area. With CMOS technology advancing, the requirement for contact resistivity is more and more strict due to contact size scaling. In 7nm node and beyond, the typical requirement for ρC is below 2 × 10-9 Ω·cm-2 [6]. Methods to improve the ρC will be first reviewed and examined, including: increasing the in-situ doping of the Source/Drain epitaxy, dopants activation via various thermal processes, solid phase epitaxy (SPE) and liquid phase epitaxy (LPE) processes at the surface of S/D epitaxy, Schottky Barrier Height (SBH) engineering at metal-semiconductor interface via different contact liners, and tuning S/D epitaxy materials. After that, contact area improvement will be explored with regard to increasing the contact length by gauging the S/D epitaxy and using wrapped around contact to enlarge the contact width. In the end, a summary will be given.

4.2. CONTACT RESISTIVITY REDUCTION METHODS The contact resistivity is directly related to the Schottky Barrier Height (ΦB) of the metal-semiconductor interface and the active doping concentration (N) at the semiconductor surface. It can be described as [7]: 2√𝜀𝑠 𝑚∗ Φ𝐵

ρ𝐶 ∝ 𝐸𝑋𝑃(

ℏ

√𝑁

),

(1)

Heng Wu

82

in which ℏ is the reduced Planck constant, εs is the semiconductor permittivity and m* is the carrier effective mass. Reducing the SBH and increasing the active doping concentration are critical for the ρC reduction.

4.2.1. Contact Area Optimization The contact area should also be carefully examined for the contact resistance reduction. The contact resistance can be determined by the contact area A and the contact resistivity ρC in Eq.2: 𝑅𝐶 =

𝜌𝐶 𝐴

=𝐿

𝜌𝐶 𝐶 ∙𝑊𝐶

,

(2)

Figure 2. (a) Contact length LC equals physical contact length L (b) in TLM measurement LC = LT ≤ L.

where the contact length is LC and the contact width is WC. It is worth noting that the LC is equal to the physical contact length L only if the direction of current flow is perpendicular to the area and the current density over the entire LC is uniform as shown in Figure 2(a). when the current flow makes a turn as it is in a typical Transmission Line Measurement (TLM) shown in Figure 2(b), the LC is not necessarily the physical length L, but determined by the transfer length LT discussed in Chapter 3. Usually LT ≤ L. As is indicated in the Eq.2, to lower the RC, one approach is to increase the LC and/or the WC, the other is to reduce the ρC

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which will be discuss later in this chapter. How to enlarge the contact area while keeping the size of contact opening the same is of great importance.

Figure 3. Process flow of increasing the contact length to enlarge the contact area.

To increase the contact length LC, as shown in Figure 3, after opening the contact trench (2), a gentle etch on the S/D epitaxy is used to gauge the epitaxy (3) and profile of the epitaxy surface is modified, resulting in a larger LC for the contact metal landing (4). This method is widely used in both planar CMOS technology [8, 9-10] and 3D FinFET technology [11, 12-13]. This method has the limitation of the gauging depth which could impact the junction if the S/D is over etched.

Figure 4. Cross-fin contact profiles for typical FinFET without (1) and with (2) wrap around contact (WAC).

The other method is to increase the contact width (WC), unique to FinFET technology. As shown in Figure 4, due to the 3D nature of the S/D epitaxy in FinFET, majority of the exposed epitaxy surface can be utilized

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to make the contact by using wrapped around contact (WAC) scheme [14]. For the WAC technique, a contact metal liner is conformally deposited around the S/D, rather than only on the top portion of the S/D. After that, contact annealing forms the silicide at the metal-semiconductor interface, surrounding the S/D epitaxy. With the WAC scheme, the contact area is improved. A demonstration of the technique is shown in Figure 5 by a CVD Ti process [14].

Figure 5. Fin-shaped (Si/SiGe) with SiGe:B diamond-shape S/D and CVD Ti conformal deposition (left). Merged S/D Si diamonds and CVD Ti deposition. The top and bottom of the facet have similar Ti liner thicknesses (right) [14].

4.2.2. Schottky Barrier Height Engineering for ρC Reduction The SBH of the metal-semiconductor contact is determined by both the metal and semiconductor. By adjusting the work functions of the contact metal, the SBH can be reduced, thus reducing the contact resistivity. Figure 6 shows the band diagrams of the Schottky barriers between the metal and doped semiconductors for electrons (a) and holes (b). Depending on the difference between the metal work function and the semiconductor electron affinity, for the contact resistivity optimization, different metals are needed for n-type and p-type contacts. In order to reduce the SBH, high work-function metals such as Ni, Pt are preferred for the PFET. On the contrary, for the NFET, low work-function metals such as Ti are used. However, integration of the different types of metal contacts on NFET and

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PFET separately is complicated, usually at additional cost of either opening the contact trenches of NFET and PFET individually, or an extra layer of metal deposited on the transistors of which the contact forms later in the flow.

Figure 6. The Schottky Barrier between the contact metal and (a) n-type and (b) p-type semiconductors. The SBH is different for (a) electrons and (b) holes.

Considering the needs of different contact metals for NFET and PFET to reduce the ρC, dual metal contacts scheme has been reported recently, using Ti liner for NFETs and NiSi for PFETs [15]. An integration flow of the different metal contacts is illustrated in Figure 7 [16].

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Figure 7. Integration of different metal contacts on NFET and PFET: (a) open contact trench, (b) deposit Ti/TiN, (c) fill trench with sacrificial aC, (d) mask NFET, remove aC Ti/TiN on PFET, (f) remove mask and deposit NiPtTi/TiN, (g) W fill and CMP to expose aC, (h) Remove aC in NFET trench, another W fill and CMP [16].

Besides different work-function metals, the source/drain epitaxy can also be tuned to adjust the SBH, especially on the PFET side. Different from NFET, PFET source/drain epitaxy growth in FinFETs usually features certain amount of Ge to introduce strain and reduce resistance. Related to the metal-semiconductor interface trap density and the trap distribution, the Fermi level of Ge is pinned close to the valence band edge [17]. Due to the Fermi-level pinning, the barrier height of metal-Ge contact for holes is much smaller than that for electrons, which benefits the p-type contacts.

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Figure 8 shows the relationship of PFET contact resistivity ρC and Ge content in SiGe epitaxy [5]. The ρC first decreases with higher Ge content from 40% to 70%, and then increases at very high Ge content of 70% to 100%, instead of monotonically reduction with higher Ge%. This indicates a trade-off between the Schottky Barrier Height and the active doping concentration. Comparing to Si, Ge has more than one order smaller solid solubility of Boron (~1 × 1018 cm-3 in Ge versus ~8 × 1019 cm-3 in Si) [18]. Therefore, SiGe alloys with higher Ge content have lower active Boron concentration. The trade-off between the SBH and the active doping concentration determines that an optimal ρC can be found by tuning the Ge content and in-situ Boron doping in the SiGe:B epitaxy. In Figure 8, the optimal Ge content for the ρC reduction is around 70% [5].

Contact Resistivity(cm2)

3.0x10-9

PFET

2.5x10-9 2.0x10-9 1.5x10-9 1.0x10-9 5.0x10-10 0.0

40

50

60

70

100

Ge%

Figure 8. Contact resistivity of PFETs with different Ge contents in SiGe epitaxy growth. The ρC first decreases, then increases with higher Ge%. The preferred Ge content is around 70% [5].

4.2.3. Contact Interface Optimization with Trench Epitaxy The techniques of source/drain epitaxy for the SBH and dopant tuning can be applied in Middle-of-the-Line (MOL) module (e.g., trench epitaxy

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[6, 19]) after the S/D junction formation for even more aggressive ρC reduction. Considering dopant diffusion which impacts junction sharpness and dopant deactivation which reduces the active doping concentration for a highly doped pristine S/D in the downstream thermal processes after the S/D formation, trench epitaxy in the MOL module is advantageous [6, 19].

Figure 9. Process flow of trench epitaxy (TE) technique.

Figure 9 shows the process flow of the trench epitaxy technique for contact resistivity reduction. Following (1) Replacement-Metal-Gate (RMG) module, (2) dummy oxide filling the contact trench is removed to open the space for contact landing. (3) After opening the contact trench, a low temperature epitaxy process (600°C) are used in the RMG module for interface passivation and reliability purposes, which could deactivate the active dopants introduced originally during the S/D formation and lead to the dopant diffusion. Considering the dopant diffusion, in-situ S/D doping higher than 2 × 1021 cm-3 with the common dopants (B, P) of small atomic size is not preferred.

Tuning Dopant Elements One strategy of increasing S/D doping concentration is to change the dopant elements. Table 1 lists the solid solubility of dopants in Ge and Si [29-30]. By going from B to Ga in PFET SiGe S/D, particularly the high Ge% top portion, the solubility-limited in-situ active doping density can be increased more than one order of magnitude. Different dopant elements of the same type can be also combined to achieve a desired high doping density. Figure 15 shows the use of a group-III metallic dopant combined with B for p-type doping boost, which yields 7.6 × 1020 cm-3, much higher than the B solubility in Ge [30]. N-type dopants, P and As, have similar solid solubility in Si. However, the activation of P requires lower temperature than As (Chapter 2 Figure 17), which means that the P will

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have a higher active doping concentration than As with the same thermal budget allowed in the process. Table 1. Solid solubility of dopants in Ge and Si [29-30] Doping element B Ga P As

Atomic radius (pm)

Substrate

85 135 110 120

Ge Ge Si Si

Maximum equilibrium solid solubility (at./cm3) 5.5 × 1018 4.9 × 1020 1.2 × 1020 1.7 × 1020

Figure 15. Active hole concentrations for B and group-III-metal in Ge by Hall measurements. The group-III-metal chemical concentration [Me] is ~1 × 1021 cm-3 while [B] is 2 × 1019 cm-3. Hall scattering factor (HSF) is 1.8 [6].

Diffusion of the dopants during thermal treatments largely depend on their atomic sizes with bigger the size slower the diffusion. To control the diffusion of dopants for sharp junction gradient, it seems that Ga and As are more favorable than B and P due to their large sizes. However, the S/D doped with large atoms often has high density of defects such as grain boundaries, dangling bonds, and lattice mismatch, which will impact carrier injection velocity thus the mobility. Therefore, it is desired to engineer the S/D dopant profile differently at different regions: B and P closer to the channel with moderate doping, Ga and As near to the contact with high doping. Design of S/D materials and doping concentrations is a

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complicated task requiring overall consideration of both device and process integration.

Active Doping Concentration Improvement via SPE or LPE Increase of the in-situ S/D doping sometimes cannot effectively reduce the contact resistivity due to the dopant deactivation in the downstream process after the S/D formation. It could also induce severe short channel effects due to the dopant diffusion. How to improve the active doping concentration becomes an emerging topic. Solid Phase Epitaxy (SPE) and Liquid Phase Epitaxy (LPE) in the MS contact formation are recently introduced [5, 6, 8, 19-21, 23-24] showing significant reduction of the contact resistivity without impacting the channel and junction.

Figure 16. Process flow of SPE and LPE techniques for contact resistivity reduction.

Figure 16 illustrates the process flow of the SPE and LPE techniques for the contact formation. After opening the contact trench on the S/D, a shallow ion implantation (I/I) is conducted onto the surface of the S/D, forming a localized and amorphous mix of dopants and semiconductor elements. The amorphous pocket region typically ranges in several nanometers from the surface, depending on the I/I energy. The pocket is then subjected to fast millisecond (mSec) or nanosecond (nSec) laser annealing to introduce the SPE or LPE. The peak temperature can be set below the melting point of the S/D materials for the SPE or above the melting for the LPE. The re-crystallization happens simultaneously within the amorphous pocket, enabling a homogeneous semiconductor-dopant

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alloy with high active doping concentration of several atomic percent above the dopant solubility [6, 24, 20].

Downstream Thermal Process Optimization As discussed earlier, in the FinFET process flow, the dopant deactivation during the thermal processes plays a big role in limiting the contact resistivity reduction. This means, adding more dopants during the S/D formation cannot effectively increase the active doping density. Taking the NFET as an example, Figure 17 shows the sheet resistance of the S/D Si:P under different thermal treatments [5]. It is clear that the furnace annealing at low temperature but for a long time (800°C). With introduction of even higher temperature and faster annealing (>1200°C mSec laser LSA), the sheet resistance can be further improved by 35%, indicating a full reactivation of the deactivated dopants and additional activation of extra dopants.

Epi Sheet Resistance(a.u.)

9

NFET

8 7 6 5

LS A >1

20 0C

LS A >1

00 0C

P RT >8 00 C

rna ce Fu C 700ºC, measuring the SPE rate require laser heating, so the target temperature is reached before a complete transformation. Rapid thermal annealing is also used to reduce diffusion and out-diffusion of implanted dopants while achieving a high dopant activation. 1.1.3. Crystalline and Amorphous Si and Ge For crystalline Si and Ge, the four valence electrons bond covalently with four nearest neighbors in a tetrahedral configuration, resulting in a diamond cubic lattice composed of sixfold rings in a “chair” configuration

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shown in Figure 3. The nearest neighbors are separated by a distance of a(3)1/2/4, where the characteristic lattice constants are aSi = 0.543 nm and aGe = 0.566 nm. The angle between any two adjacent tetrahedral bonds is 109.47 deg.

Figure 3. Crystalline and continuous random network structure.

The structure of the amorphous phase cannot be easily defined. Its properties depend on the method of fabrication and the thermal history of the sample, and its atomic structure is difficult to determine experimentally. In general, the long-range order of the amorphous phase which characterizes the crystal lattice is not available, and only short- and medium-range order is retained. The definition of short-range order includes bond lengths, coordination number, and bond angle ranges. TEM is often used in this range. Medium-range order is characterized by higher order correlations such as dihedral angles and ring statistics, which are associated with 1-3 nm length scale. These structural correlations are subtle and are not apparent in TEM.

1.1.4. Crystal-Amorphous Interface At the interface between the crystalline and amorphous phases, the bonds are believed fully coordinated. In other words, there are no free bonds, so it is in the lowest energy configuration. There may be some small number of defects at the interface. The spatial transition zone from the amorphous phase to the crystalline phase has been determined theoretically, with results in the range of 3-11 Å thick for Si [6-8].

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Therefore, the interface is quite sharp where there are a few layers between the two phases having intermediate properties.

1.1.5. Intrinsic SPE Crystalline (c-) Si has lower Gibbs free energy (G) than the amorphous (a-) phase per atom. The rate at which the a-phase transforms to the cphase is so low at the temperature up to a few 100ºC that a-Si may be used in devices. With the temperature increase beyond TSi = 500ºC or TGe = 350ºC, crystallization occurs with increasing speed, but still slow (10-2 nm/s) for the S/D SPE process that is intended for. With a pre-existing c-a interface, nucleation is unnecessary, in which case the transformation is determined by the SPE rate. The growth rate can be described as a thermally activated process with an energy barrier, in which atoms undergo transition from the amorphous structure to the crystalline structure at the ca interface. This picture is illustrated in Figure 4 where ΔGac is the Gibbs free energy difference per atom between the a- and c-states and ΔG* is the free energy barrier to the crystallization. Both quantities depend on temperature and pressure according to thermodynamics. The number of transitions per site per second at which an amorphous-to-crystal transition occurs is given by k+ = v ∙ exp(−ΔG* / kT)

(2)

where v is the attempt frequency [9]. The number of transitions per site per second in the reverse direction, k−, is given by the same expression, except with a larger barrier height, ΔG* + ΔGac. The SPE rate vac is the product of the areal density of interfacial sites where a transition occur, the volume transformed per transition, and the net transition rate (k+ − k−). The SPE rate, defined as the velocity at which the interface moves, is given by v = v∞ ∙ exp(−ΔH* / kT) (1 – exp(−ΔGac / kT))

(3)

where ΔH* is the activation enthalpy. The pre-exponential factors have been collected into the v∞, including the exponential of the activation

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entropy. Because the thermodynamic factor (1 – exp(−ΔGac / kT)) hardly changes over experimental conditions, it can be gathered into the preexponential factor, resulting in v = v0 ∙ exp(−ΔH* / kT)

(4)

At normal pressures, ΔH* = ΔE* + PΔV* is not distinguishable from the “activation energy” ΔH*, which is the Ea in Eq.1. For Si (001) the activation energy and pre-exponential factor are Ea = 2.7 eV and v0 = 4.64×106 m/s. For Ge (001), Ea = 2.15 eV and v0 = 2.6×107 m/s [10-11]. According to Eq.1, crystallization occurs at SPE rates from 0.1 to 10,000 A/s at temperatures in 500-800ºC for Si and 315-530ºC for Ge, as shown in Figure 5 [5]. The specific atom-level processes by the activation energies have never been identified definitively. The SPE rate and the quality of the resulting substrate depend strongly on the interface orientation. Figure 6 shows the SPE rate versus the misorientation from (111) for both Si and Ge. The growth rate is 25 times faster when growing on a {001} crystal than on a {111} crystal [12]. Although there are large changes in the SPE rate, the activation energies do not vary with orientation; this suggests that the underlying SPE mechanism does not change (Figure 7).

Figure 4. Schematic of the Gibbs free energy versus reaction coordinate representing the energetics of a transformation between the a- and c-phases. The activation energy, ΔG*, is 2.70 eV for Si and 2.15 eV for Ge.

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Figure 5. SPE rate as a function of 1/kT for Si [10] and Ge [11] as obtained from timeresolved reflectivity measurements [5].

Figure 6. Normalized SPE rate vs. the interface misorientation from (111). Si (550ºC) from [12] and Ge from [13]. The solid line is the relative dangling bond density between the crystal and amorphous phases [14].

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Figure 7. Schematic of (100) Si SPE growth where the c-a interface is moving upward. The application of compression is represented by the arrows for (a) hydrostatic, (b) inplane uniaxial, and (c) normal uniaxial cases [15].

SPE in substrates close to the {111} orientation result in an imperfect crystal containing a significant density of defects [16]. The SPE rate on {111} crystals is nonlinear with time, exhibiting a slow initial stage of growth followed by a faster stage [17]. The latter stage is dominated by the formation of twin defects inclined to the surface and associated with the orientation, which is a much faster growth direction than the {111}. This may be the cause of the nonlinear behavior. Such defects in Si are not as prevalent in Ge, and only a linear growth mode has been observed in {111} SPE in Ge [13].

1.1.6. Dopant Dependence of SPE The SPE rate can be enhanced or retarded in the presence of impurity atoms. It is found that group-III and group-V elements tend to enhance the SPE rate for concentrations greater than 1019 cm-3 [18,19]. Non-doping impurities, such as H, generally retard the interface motion. Enhancement of up to 30 times has been observed for B at a impurity concentration of 0.4 at.% [20]. Figure 8 illustrates the effect of dopants to SPE in which a surface a-Si layer is implanted with As or Al, or partially overlapping As and Al profiles, and annealed at 615ºC. During the initial stages of the annealing, the intrinsic SPE rate is observed. When the c-a interface meets the dopant-implanted region, its velocity increases and follows the concentration profile of the implanted dopant. When both n- and p-type dopants are present in equal concentrations, the SPE rate returns to intrinsic. Overlapping two dopants of the same type gives an additive

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effect on the SPE regrowth rate [21]. Figure 9 shows the As SPE rates as a function of inverse anneal temperature and dopant concentration. The normalized SPE rate is approximately linear with clear difference between the dopants [22-23].

Figure 8. SPE rate vs. depth. Dopants As, Al and As+Al implanted at multiple energies create a constant concentration profile. The intrinsic rates are for comparison [5].

Figure 9. SPE rate of As-implanted Si as a function of (a) inverse temperature and as a function of (b) dopant concentration, both normalized by the intrinsic SPE rate. SPE rates for B and P are shown for comparison in (b). The SPE rates from the samples with the highest B concentration were excluded from the fittings (solid lines) [5].

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1.1.7. Dopant Activation in SPE As discussed in Chapter 2, the dopant solid solubility limit is the maximum concentration that can be achieved in equilibrium with its host lattice, and it is determined by the thermodynamic requirement that the free energy of the system is minimized. Active concentrations well above the solubility limit are possible through the SPE, and such SPE material is named metastable alloy. A doping concentration 9×1021 cm-3 of active As has been reported in Si [24], whereas the equilibrium concentration is 1.5×1021 cm-3 [25]. Doping concentrations after SPE comparing to their solid solubilities for both Si and Ge are shown in Figure 10.

Figure 10. Equilibrium solid solubility (solid symbols) [25] and metastable active dopant concentration after SPE (open symbols) of dopants in Si and Ge [1, 26-31].

In CMOS process, the electrical activation of implanted dopants after the SPE annealing is a critical parameter. The activated dopant concentration depends on the parameters of the annealing. For example in [32], the sheet resistance of BF2 implanted samples is reduced for both a higher anneal temperature and a higher anneal ramp rate. The thermal stability of an activated dopant profile is also a critical parameter for which subsequent high-temperature processing may be a necessary component of the process flow after the SPE annealing. Dopant deactivation could happen at the temperature greater than the SPE annealing temperature, or at a lower temperature during long thermal processes. Besides reactivation or deactivation of dopants, long range redistribution of the dopants can also occur. Variations in sheet resistance can be driven by dopant clustering.

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1.1.8. Dopant Diffusion and Segregation in SPE Dopants can diffuse, form defects, and precipitate during the SPE. Dopant clustering leads to deactivation, and it occurs when dopant atoms diffuse during the activation annealing. This deactivation can cause retardation of the SPE rate. For semiconductor devices, dopant deactivation is a serious issue and is typically minimized by limiting thermal budgets. The mechanism of impurity diffusion in amorphous phase is different from that in crystalline phase. For an example, B diffusion in aSi is mediated by defects in the amorphous phase and has complex dependence on B concentration. In c-Si, B diffusion is through B interactions with Si interstitials, but the B diffusivity is much less than that in a-Si at the same temperature. Thus, it is important to limit the time in the amorphous phase during the SPE for B. The interstitial-based mechanism also dominates the diffusion of P. In c-Ge, B diffusion is also mediated by Ge interstitials. But because the vacancy in Ge is highly mobile, B is immobile unless a source of interstitials is present. In Ge, P, As, and Sb diffusion is dominated by a vacancy-mediated process with negligible contribution of self-interstitials. Interstitials can act to suppress diffusion of such impurities.

1.2. Liquid Phase Epitaxy Liquid Phase Epitaxy (LPE) is a method to grow crystalline semiconductor layers from the melt on solid substrates. LPE needs to happen at temperatures well below the melting point of the deposited semiconductor by dissolving the semiconductors in the melt of another material which has much lower melting point of the resulting crystalline product. For the LPE of Si and Ge, the starting materials are usually amorphous Si and amorphous Ge or SiGe, which have much lower melting point than their crystalline counterparts (Figure 11). The melting temperatures of crystalline Si and Ge are too high for the contact process in the CMOS flow. At conditions close to the equilibrium between dissolution and deposition, the deposition of the crystalline materials on

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the substrate is uniform. Fast laser annealing with nano-second duration of the peak temperature to melt the amorphous material is an advanced method in CMOS processes, as the total thermal budget can be very low. Laser has a refractive index which depends on its wavelength and the incident materials, thus the wavelength can be tuned to selectively melt the material of interest [2].

Figure 11. Process window of LPE: Si, Ge, and SiGe [2].

Similar to SPE, active doping concentration above the solid solubility can be achieved by LPE. Recent work [1] shows that an ultra-heavily doped metastable Si:P alloy can have the P concentration exceeding 10 at.% by LPE. Localized epitaxial growth and implantation through nanometer trenches reduce the volume of SPE and LPE, and increase the likelihood of creating the metastable alloy within the trench. The fast laser annealing prevents excessive precipitation and promotes creation of a homogeneous metastable phase. Figure 12 shows epitaxial growth of LPE Si:P in a nano-scale contact trench with P I/I followed by nano-second (nSec) laser annealing. The nSec laser annealing could melt amorphous Si:P at 1200-1250ºC quickly, converting it to crystalline Si:P. Figure 13 illustrates the active doping concentration of the metastable alloy created by SPE and LPE. The reference cell [a] of Figure 13 has a typical Si:P base layer with P content of ~5×1020 cm-3. Through-trench implantation case [b] adds locally ~4-5 at.% of P with the conversion occurring during the silicidation step with mSec laser anneal for SPE. Cases [c] [d] have ~8

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at.% of P through localized trench epitaxy with an additional throughtrench P I/I which adds 4-5 at.% of the P. nSec LPE case [d] increases the active doping concentration to greater than 10 at.% well above the P solid solubility in Si.

Figure 12. TEM images of Si:P epitaxial growth in nano-scale contact trench on S/D, followed by P ion implantation and Laser LPE: peak temperature 1200ºC [33].

Figure 13. Active doping concentration of the meta-stable Si:P alloys created by SPE and LPE and the contact resistivity reduction due to increasing the doping concentration. Case [b] through-trench implantation, [c] trench Si:P epitaxy, throughtrench P implantation, and mSec SPE, [d] Si:P trench epitaxy, through-trench P implantation, and nSec laser LPE. [a] has a base Si:P epitaxial layer with P~5×1020 cm3 , case [b] adds ~2×1021 cm-3 of P, cases [c] and [d] have ~6×1021 cm-3 of P [33].

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In many aspects, a liquid-phase material can be treated similarly as its solid-phase amorphous material. The liquid-to-crystalline interface, LPE growth rate, dopant dependence, and activation in LPE, can be approximated by the SPE in previous discussion. The dopant diffusion and segregation in LPE could be more severe in LPE than SPE as the diffusivity of dopants in liquid is much higher than that in the solid material. However, if the nano-second laser annealing is under consideration, the diffusion or segregation of the dopants can be neglected within such short period of time (Figure 14).

Figure 14. The calculated B diffusion length dependence on time. Parameters in the calculation are taken from [34] for Boron doping mid 10 16 cm-3 in Si.

2. CONTACT RESISTANCE REDUCTION BY METASTABLE ALLOYS IN SPE AND LPE The SPE and LPE techniques for the contact resistivity ρC reduction has been described in Chapter 4 (Figure 16 Chapter 4). The starting amorphous material is formed by a shallow ion implantation (I/I) onto the surface of heavily doped S/D (SiGe:B for PFET, Si:P for NFET). The amorphous pocket is then subjected to the millisecond (mSec) or nanosecond (nSec) laser annealing to introduce SPE or LPE. The peak temperature is set ~1000°C but well below the melting point of the S/D

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materials. The nSec laser annealing applies sub-100ns laser pulses on the surface with peak temperature beyond the melting point, which converts the amorphous pocket into liquid phase. The re-crystallization procedure happens simultaneously within the shallow amorphous pocket, making a homogeneous semiconductor/dopant alloy with an active doping concentration at the super-saturated and meta-stable region of several atomic percent. Due to the super high active doping concentration at the surface, very low contact resistivity is expected [1, 29-30]. The SPE re-crystallization process can be captured by TEM. Figure 15 shows the S/D contact of FinFETs with and without the SPE process, in which the S/D epitaxy, contact and metal stud are shown [35]. The one without SPE shows near single crystalline structure. However, crystal defects such as stack faults can be seen in the one with SPE process due to the non-ideal re-crystallization during the rapid cooling after the laser annealing. Reproduced from [33], Figure 16 shows n-type contact resistivity results with and without SPE process based on TLM measurement. The TLM structure is formed on heavily doped Si:P with a contact length LC about 30 nm. For the sample with the SPE process, neutral Si ions were implanted to amorphize the Si:P surface and 1250 °C mSec laser spike annealing (LSA) was used for the re-crystallization. Without introducing any extra dopants, the SPE process reduces the ρC from 2×10-8 Ω·cm2 to 6×10-9 Ω·cm2, indicating more dopants in the Si:P epitaxy are activated.

Figure 15. High resolution TEM image of S/D epitaxy and contact region of FinFETs (a) without SPE process, (b) with SPE process. Stacking faults are induced during the re-crystallization on the (b) sample with SPE [35].

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Figure 16. Contact resistivity of n-type contacts with and without SPE technique.

Figure 17. (a) NFET contact resistivities with and without SPE process at various insitu doping levels. (b) PFET contact resistivities with and without SPE process at various in-situ doping levels. Ga is used as dopants in the SPE process [35].

Furthermore, by replacing the neutral elements (Si or Ge) with n- or ptype dopants in the ion implantation, more dopants can be introduced and activated during the SPE or LPE. As a result, the overall contact resistivities can be further improved. Figure 17a shows the result of contact resistivities of NFETs with and without SPE process at various in-situ doping levels [35]. P ion implantation is used in this experiment and the ρC is significantly reduced in the case of SPE. By combining the SPE with high in-situ chemical doping from S/D epitaxy growth, the corresponding ρC of 2.1×10-9 Ω∙cm2 is close to the requirement in the CMOS technology roadmap. On the PFET side, as the S/D layer for the contact is SiGe of high Ge%, p-type dopant Ga needs to be used instead of B because the solid solubility of Ga is more than one order higher than that of B (Refer to

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Figure 15 in Chapter 4). By using SPE with Ga I/I, significant ρC reduction can be achieved, shown in Figure 17b [8]. Figure 18 summarizes improvement of ρC by incorporating pocketed Ge: Ga metastable alloy. Case [a] is the SiGe:B reference. Case [b] shows the positive effect of Fermi level pinning by the Ge:B layer. Cases [c] and [d] show the effect of Ge:Ga alloy with two different at.% of Ga, both in excess of its chemical solubility. The amount of ρC reduction and its Ga at.% dependence further confirms creation of a metastable Ge:Ga alloy within the contact trench. The ρC of 1.9×10-9 Ω∙cm2 for the Ge:Ga contact layer includes the resistivity of the unipolar heterojunction and the Ge layer [1, 37] which are together ~ 4×10-10 Ω∙cm2. Case [e] shows an upper bound for the ρC of the Ti-Ge to Ge-Ga contact. Similar to SPE, the nSec laser annealing can trigger LPE and reduce ρC as well. The record-low ρC number, 8×10-10 Ω·cm2 is reported on NFETs [1, 33] and 1.2×10-9 Ω·cm2 is on PFETs [38] by the use of LPE.

Figure 18. ρC reduction with metastable Ge:Ga alloys. [a] SiGe:B reference, [b] Ge:B trench epitaxial layer, [c]-[d] Ge:B:Ga metastable alloys with [Ga] above chemical solubility in Ge and [Ga]d = 2×[Ga]c, [e] upper bound estimate for the metal-tosemiconductor alloy contact resistance of [d] [1].

CONCLUSION In this chapter, we reviewed the crystallization behavior via SPE with a focus on Si and Ge. Both are of great technological importance and serve as models to study SPE. SPE substrate orientation, and impurity

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concentration dependencies are discussed. The inclusion of SPE and LPE in the CMOS process signifies that our understanding of SPE/LPE kinetics will be refined in broader experimental work, and also provides insight into fundamental processes and materials such as contact formation, laser annealing, dopant activation, and metastable alloy. The contact resistivity reduction associated with the SPE/LPE processes and different dopants are reviewed, showing great achievements and promises of the SPE and LPE applications in technology performance step-up.

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[2]

[3]

[4]

[5]

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Gluschenkov, O. et al. “FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys,” 2016 IEEE International Electron Devices Meeting, 17.2.1-17.2.4 (2016). Liu, Z. et al. “Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability,” 2017 Symposium on VLSI Technology, T212-T213 (2017). Biersack, J. P., Haggmark, L. G. “A Monte Carlo computer program for the transport of energetic ions in amorphous targets,” Nucl. Instrum. Methods, vol.174, iss.1-2 p.257 (1980). Posselt, M. “Crystal-trim and its application to investigations on channeling effects during ion implantation,” Radiat. Eff. Defects Solids, iss.1, p.87 (1994). Handbook of Crystal Growth, 2nd edition, Volume III, Part A. Thin Films and Epitaxy: Basic Techniques, Chapter 7 Solid-Phase Epitaxy, chapter authors: B. C. Johnson, J. C. McCallum, M. J. Aziz, book editor: T. F. Kuech, Elsevier North-Holland, Boston (2015). Bernstein, N., M. J. Aziz, E. Kaxiras, “Amorphous-crystal interface in silicon: A tight-binding simulation,” Phys. Rev. B, 58, 4579 (1998). da Silva, C. R. S., A. Fazzio, “Formation and structural properties of the amorphous-crystal interface in a nanocrystalline system,” Phys. Rev. B, 64, 075301 (2001).

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Zuoguang Liu and Heng Wu Tu, Y., J. Tersoff, G. Grinstein, D. Vanderbilt, “Properties of a Continuous-Random-Network Model for Amorphous Systems,” Phys. Rev. Lett., 81, 4899 (1998). Vineyard, G. H., “Frequency factors and isotope effects in solid state rate processes,” J Phys Chem Solids, vol.3, iss.1-2, p.121-127 (1957). Roth, J. A., and G. L. Olson, “Kinetics of solid phase epitaxy in thick amorphous Si layers formed by MeV ion implantation,” Appl. Phys. Lett., 57, 1340 (1990). Johnson, B. C., P. Gortmaker, and J. C. McCallum, “Intrinsic and dopant-enhanced solid-phase epitaxy in amorphous germanium,” Phys. Rev. B, 77, 214109 (2008). Csepregi, L., E. F. Kennedy, J. W. Mayer, and T. W. Sigmon, “Substrate‐orientation dependence of the epitaxial regrowth rate from Si‐implanted amorphous Si,” J. Appl. Phys., 49, 3906 (1978). Darby, B. L., B. R. Yates, I. Martin-Bragado, J. L. Gomez-Selles, R. G. Elliman, and K. S. Jones, “Substrate orientation dependence on the solid phase epitaxial growth rate of Ge,” J. Appl. Phys., 113, 033505 (2013). Custer, J. S., A. Battaglia, M. Saggio, F. Priolo, “Growth-site-limited crystallization of amorphous silicon,” Phys. Rev. Lett., 69, 780 (1992). Rudawski, N. G., K. S. Jones, R. Gwilliam, “Stressed solid-phase epitaxial growth of ion-implanted amorphous silicon,” Mater. Sci. Eng., vol.61, iss.1-6, p.40-58 (2008). Rechtin, M. D., P. P. Pronko, G. Foti, L. Csepregi, E. F. Kennedy, and J. W. Mayer, “An electron microscopy study of defect structures in recrystallized amorphous layers of self-ion-irradiated silicon,” Philos. Mag. A, vol.37, iss.5, pp.605 (1978). Lau, S. S., “Regrowth of amorphous films,” Vac. J. Sci. Technol., 15, 1656 (1978). Csepregi, L., J. W. Mayer, T. W. Sigmon, “Chaneling effect measurements of the recrystallization of amorphous Si layers on crystal Si,” Phys. Lett. A, vol.54, iss.2, p.157 (1975).

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[19] Csepregi, L., E. F. Kennedy, T. J. Gallagher, and J. W. Mayer, “Reordering of amorphous layers of Si implanted with 31P, 75As, and 11 B ions,” J. Appl. Phys., 48, 4234 (1977). [20] Johnson, B. C., and J. C. McCallum, “Dopant-enhanced solid-phase epitaxy in buried amorphous silicon layers,” Phys. Rev. B, 76, 045216 (2007). [21] Suni, I., G. Göltz, M. G. Grimaldi, and M. A. Nicolet, “Compensating impurity effect on epitaxial regrowth rate of amorphized Si,” Appl. Phys. Lett., 40, 269 (1982). [22] Walser, R. M., Y. J Jeon, “Application of Solid Phase Epitaxy for Measuring Dangling Bond Densities and Impurity Ionization in Amorphous Silicon,” Mater. Res. Soc. Symp. Proc., vol. 205, 27 (1990). [23] McCallum, J. C., “The kinetics of dopant-enhanced solid phase epitaxy in H-free amorphous silicon layers,” vol. 148, iss.1-4, pp.350-354, (1999). [24] Williams, J. S., “Solid phase epitaxial regrowth phenomena in silicon,” Nucl. Instrum. Methods Phys. Res. Sect. B, vol. 209-210, Part 1, p.219-228 (1983). [25] Trumbore, F. A., “Solid solubilities of impurity elements in germanium and silicon,” Bell Syst. Tech. J., vol.39, iss.1, p.205 (1960). [26] Johnson, B. C., T. Ohshima, J. C. McCallum, “Dopant effects on solid phase epitaxy in silicon and germanium,” J. Appl. Phys., 111, 034906 (2012). [27] Duffy, R., T. Dao, Y. Tamminga, K. van der Tak, F. Roozeboom, E. Augendre, “Groups III and V impurity solubilities in silicon due to laser, flash, and solid-phase-epitaxial-regrowth anneals,” Appl. Phys. Lett., 89, 071915 (2006). [28] Jain, S. H., P. B. Griffin, J. D. Plummer, S. Mccoy, J. Gelpey, T. Selinger, et al. “Metastable boron active concentrations in Si using flash assisted solid phase epitaxy,” J. Appl. Phys., 96, 7357 (2004).

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[29] Chao, Y. L., S. Prussin, J. C. S. Woo, R. Scholz, “Preamorphization implantation-assisted boron activation in bulk germanium and germanium-on-insulator,” Appl. Phys. Lett., 87, 142102 (2005). [30] Posselt, M., B. Schmidt, W. Anwand, R. Grotzschel, V. Heera, A. Mucklich, et al. “P implantation into preamorphized germanium and subsequent annealing: Solid phase epitaxial regrowth, P diffusion, and activation,” J. Vac. Sci. Technol. B, 26, 430 (2008). [31] Duffy, R., V. C. Venezia, K. van der Tak, M. J. P. Hopstaken, G. C. J. Maas, F. Roozeboom, et al. “ Impurity redistribution due to recrystallization of preamorphized silicon,” J. Vac. Sci. Technol. B, 23, 2021 (2005). [32] Juang, M. H., and H. C. Cheng, “Activation mechanism of implanted boron in a Si substrate,” J. Appl. Phys., 72, 5190 (1992). [33] Niimi, H., et al. “Sub-10-9 Ω-cm2 n-Type Contact Resistivity for FinFET Technology,” IEEE Electron Device Lett., 37 (11), 13711374 (2016). [34] Plummer, J. D., M. D. Deal, P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling, Prentice Hall, NJ (2000). [35] Wu, H., et al. “Integrated dual SPE processes with low contact resistivity for future CMOS technologies,” in Technical Digest International Electron Devices Meeting, IEDM, 2017, pp. 22.3.122.3.4. [36] Yu, H., et al. “Ultralow-Resistivity CMOS Contact Scheme with PreContact Amorphization Plus Ti (Germano-) Silicidation,” 2016 Symposium on VLSI Technology, p.66 (2016). [37] Sze, S. M., et al. “Resistivity, mobility and impurity levels in GaAs, Ge, and Si at 300°K,” Solid-State Electronics, vol.11, iss.6, p.599602 (1968). [38] Wu, Y., et al. “Record low specific contact resistivity (1.2×10-9 Ωcm2) for P-type semiconductors: Incorporation of Sn into Ge and inSitu Ga doping,” in Digest of Technical Papers - Symposium on VLSI Technology, 2017, pp. T218-T219.

In: An Introduction to Contact Resistance ISBN: 978-1-53618-501-0 Editor: Zuoguang Liu © 2020 Nova Science Publishers, Inc.

Chapter 6

LOW-RESISTANCE CONTACT INTEGRATION IN CMOS TECHNOLOGY Heng Wu*, PhD Semiconductor Technology Research, IBM, Albany, NY

ABSTRACT In previous two chapters, we have discussed various approaches for contact resistance reduction. As the gate pitch of transistors keeps shrinking, contact resistance reduction attracts a lot of attention in the last decade for advanced CMOS technology development. By nature, the shrinkage of metal contact dimensions associated with the transistor scaling results in elevated contact resistance given a constant contact resistivity (ρc). Furthermore, in the state-of-the-art CMOS technology beyond 7nm technology node, the contact size of transistor source/drain is less than 20 nm [1], posing a great challenge for the contact resistance reduction and overall circuit performance. Contact optimization is now a key thread in leading-edge CMOS technology. In this chapter, we will review integration of contact resistance reduction techniques in standard CMOS process flow. CMOS compatible processes for the contact

*

Corresponding Author’s Email: wuheng@ us.ibm.com.

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Heng Wu formation is particulary important to optimize both NFETs and PFETs to achieve overall performance gain.

Keywords: scaling, contact size, contact resistivity (ρc), CMOS technology, MOL, CMOS integration

INTEGRATION OF CONTACT RESISTIVITY REDUCTION TECHNIQUE IN FINFET TECHNOLOGY Complementary-Metal-Oxide-Semiconductor (CMOS) technology is the fundation of all integrated circuits, computer chips, and systems built upon them. The CMOS technology has evolved according to the famous Moore’s Law and its successor roadmap for more than half a centry. Since about a decade ago, planar transistors are replaced by 3D transistors namely FinFETs which dominate the device structure from 14nm technology node for more than four generations. A typical FinFET technology process flow in Figure 1 includes front end of line (FEOL) for transistor formation and back end of line (BEOL) for interconnects. The FEOL has multiple modules [8]. In the FinFET technolgy, the FEOL can be divided into: fin module for the fin formation, dummy gate module to form the dummy gate used in the downstream RMG module, epi module for epitaxial S/D, poly open CMP (POC) module for inter-level dielectric formation, replacement metal gate (RMG) module for replacing the dummy gate with high-k/metal gate, contact module for the S/D contact formation, and middle-of-line (MOL) module for local interconnects. For the S/D where the metal-semiconductor contact lands, it is covered by thick dielectrics after the S/D epitaxy growth to protect it from exposure to etching and deposition processes. The contact trenches to the S/D are opened at the contact module. Considering the FinFET process flow, the methods discussed in Chapter 4 for contact resistance reduction are employed either after the S/D epitaxy growth or after the contact trench opening. In this chapter, we will review various contact resistivity

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reduction techniques in the FinFET integration with respect to their impacts to device performance.

Figure 1. Typical FinFET process flow of the front end of line (FEOL) and back end of line (BEOL): FEOL modules are listed.

1. Increase In-Situ Doping for Contact Resistivity Reduction As is discussed in Chapter 4, increasing in-situ doping shows limited contact resistivity reduction due to the low dopant activation efficiency. Meanwhile, this approach should be considered in the aspect of short channel effects. More in-situ dopants in the S/D could introduce more dopants to diffuse into the channel in the downstream processes after the S/D epitaxy growth, which could degrade the gate control and channel carrier mobility. The trade-off between the contact resistivity and the channel property needs to be carefully examined. Figure 2a shows NFET ON resistance (RON) versus Drain Induced Barrier Lowering (DIBL) [2].

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Higher in-situ doping features lower RON from the contact resistance reduction but also significant DIBL degradation, which indicates much worse short channel effects (SCE) due to the dopant diffusion. It is also worth noting that all three in-situ doping conditions fall into the same RONDIBL trend line, which indicates limited performance benefit and weak SCE immunity. This is further verified in Figure 2b for transistor off current (IOFF) versus effective current (IEFF). The off-state leakage current can increase substantially with high in-situ doping while IEFF at constant IOFF remains the same for all three groups, indicating that there is no net transistor performance improvement due to the trade-off between short channel effects and the RON benefit from the ρC reduction by simply increasing the in-situ doping. On the PFET side, because active dopant concentration is limited by low boron activation in the SiGe S/D, no RON benefit is for the high in-situ doping group, as in Figure 3a [2]. Like NFETs, the PFET DIBL degrades with higher boron concentration, which is due to the dopant diffusion into the channel [3]. Overall no PFET performance benefit is seen as shown in Figure 3b.

Figure 2. (a) The RON versus DIBL of NFETs with different in-situ doping levels. Clear trade-off between resistance and gate control can be seen. (b) IOFF-IEFF chart for the same sets of data in (a). No net performance benefit is seen. [2]

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Figure 3. (a) RON vs. DIBL for three groups of PFETs with different in-situ doping. RON remains similar while DIBL degrades with higher in-situ doping. (b) IOFF-IEFF chart for the same sets of data in (a). [2]

2. SPE Method with Neutral Element in Ion Implantation Compared with conventional annealing methods such as RTA or furnace, the laser annealing used in the SPE technique is ultra-fast thus the dopant diffusion during the process can be minimal. Figure 4 shows the RON versus DIBL [2] of FinFETs with and without the SPE process for NFETs and PFETs. Ge, a neutral element for Si-channel MOSFETs, is implanted for amorphization purpose. The RON reduction of 7-8% is achieved without any SCE penalty, which indicates that the thermal budget from the fast SPE has minimal impact on the junction and gate control. Because of the ultra-fast annealing time, the SPE (and LPE) techniques also have minimum impact on transistor’s gate electrostatics. Considering the re-crystallization process only occurs in the amorphous pocket region at the surface as determined by the ion implantation, dopant diffusion into the channel can be minimal. Meanwhile, in this experiment, the neutral element Ge is used in the ion implantation to amorphize the surface of the S/D without introducing any extra dopants. Through the amorphization and re-crystallization process, more dopants inside the S/D are activated.

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Consequently, the contact resistivity is reduced, and the overall RON goes lower. Furthermore, since the implantation ions Germanium in this experiment are neither n-type nor p-type dopants, no extra lithography and patterning process is needed for the RON reduction in both NFETs and PFETs.

Figure 4. FinFET RON versus DIBL relationship for (a) NFET and (b) PFET. The overall RON is reduced by 7% / 8% for NFET / PFET without DIBL degradation. Neutral element Ge is used in the ion implantation.

3. SPE Method with Doping Elements in Ion Implantation Combining n-type or p-type dopants in the SPE technique, more benefit on the contact resistivity can be achieved (refer to Chapter 5.2). However, since extra dopants are introduced, location of the SPE process in the CMOS flow and its downstream thermal budgets need to be carefully examined in terms of dopant deactivation and diffusion. As discussed in Chapter 4, the thermal processes in the RMG module could greatly deactivate the dopants in the S/D epitaxy, causing a lower active doping concentration and worse contact resistivity. Therefore, the benefits of using SPE methods right after the S/D formation cannot be well maintained since the extra dopants activated by the SPE can be deactivated in the downstream. By moving the location of SPE from post-S/D-

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formation to post-contact-trench-opening, the downstream thermal budget is significantly reduced. Thus, the associated dopant deactivation can be minimized, and the SPE result and contact resistance can be optimal. Figure 5 shows the comparison of contact resistivity of NFETs at different in-situ doping levels with SPE, with optimized SPE, and without SPE [2]. With the optimized SPE condition, contact resistivity shows significant reduction with the ρC as low as 2.2×10-9 Ω·cm2 for the lowest in-situ doping level of all splits. In other words, without introducing an extensive amount of in-situ dopants during the S/D epitaxial growth, optimizing the active doping concentration at the contact interface by tuning the SPE process can effectively reduce the contact resistivity to its technology target [5-7]. Most importantly, with a low thermal budget in the SPE downstream and non-excessive in-situ doping, dopant diffusion from S/D to channel is minimized, thus the gate electrostatics are well maintained.

Figure 5. NFET contact resistivities of different ρC reduction strategies: without SPE, with SPE and with optimized SPE processes. [2]

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Figure 6a shows NFET RON-DIBL relationship without SPE, with SPE and with optimized SPE processes [2]. RON reduction of 17% is achieved by using a non-optimal SPE process, but it is accompanied by 10 mV DIBL penalty due to the diffusion of the extra dopants introduced in the ion implantation after the S/D epitaxy. Note that the DIBL degradation from this SPE process is still much less when compared with the method of using high in-situ doping even if the location of this SPE is not optimal. By moving the SPE to optimal location, which is after opening the contact trench, 40% reduction in the RON is achieved without DIBL degradation (compared to the groups without SPE in Figure 6a). With absence of the SCE degradation, more transistor performance is available. In Figure 6b. 25% improvement of IEFF at constant IOFF is achieved thanks to the RON reduction and minimal SCE degradation.

Figure 6. (a) RON vs. DIBL of NFETs with different ρC reduction strategies: without SPE, with SPE, and with optimized SPE. (b) IOFF-IEFF characteristics of the same groups of NFETs in (a). [2]

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Figure 7. PFET contact resistivities of different ρC reduction strategies: without SPE, with SPE, and with optimized SPE processes. [2]

On the PFET side, using the optimized SPE method, the contact resistivity can also be significantly reduced. In Figure 7, a very low p-type ρC of 2.0×10-9 Ω·cm2 is reported in [2], showing that the optimized SPE method can be applied to both NFET and PFET for contact resistivity reduction. In terms of transistor performance, an RON reduction of 23% is achieved without DIBL degradation as shown in Figure 8. Consequently, the IEFF at constant IOFF is improved by 17%. The results from both NFETs and PFETs regarding tuning the SPE process indicate that it is preferred to apply the SPE method post contact trench opening, where the dopant deactivation and diffusion are minimal, thus is the least impact to gate controllability.

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Figure 8. (a) RON vs. DIBL of PFETs with different ρC reduction strategies: without SPE, and with optimized SPE. (b) IOFF-IEFF characteristics of the same groups of PFETs in (a). [2]

4. CMOS Integration of Optimized SPE Methods In order to integrate the SPE technique to the CMOS FinFET flow, multiple patterning processes are needed to block the PFET/NFET region during the ion implantation of n-type/p-type dopants, otherwise the contact resistivity would be severely degraded due to counter-doping. An integrated CMOS dual SPE process flow has been reported recently [2]. Figure 9a shows the AC performance of ring oscillators with the SPE on NFETs and without any SPE [2]. Thanks to the n-type contact resistance reduction, the delay of ring oscillator (RO) is improved by 3% at constant IDDQ. On the other hand, by applying the SPE method on PFETs, 4% gain of the RO delay is shown in Figure 9b. By combining the benefit on NFETs and PFETs together, 7% reduction of the RO delay is achieved as in Figure 10 [2].

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Figure 9. IDDQ vs Delay of ring oscillators (a) without SPE and with optimized SPE on NFET only, 3% gain on delay. (b) without SPE and with optimized SPE on PFET only. 4% gain on delay. [2]

Figure 10. IDDQ vs Delay of ring oscillators with and without dual SPE process. [2]

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Thanks to the improvement on contact resistivity enabled by the dual SPE process, for smaller devices with tighter gate pitches, more contact resistance reduction can be available due to the smaller contact sizes. Figure 11 shows the RON dependence on contact sizes for NFETs and PFETs [2]. With smaller contact dimensions, the contact resistance increases, leading to higher overall transistor resistance. By using the optimized SPE process, the RON is reduced significantly, especially at smaller contact dimensions. Meanwhile, the sensitivity of the RON to the contact size is also reduced, indicating good transistor scalability thanks to the low contact resistivity. For circuit level performance, Figure 12 [2] shows the dependences of RO DC effective resistance (REFF) and delay per stage on the contact size of transistors. We can see 13% reduction of the DC REFF at contact size 24 nm while 28% reduction at the contact size 16 nm. Similarly, for the RO delay, 17% reduction in the delay per stage is achieved by using the optimized SPE on NFETs and PFETs for the contact size 16 nm.

Figure 11. RON dependences on contact size of (a) NFETs and (b) PFETs without SPE and with optimized SPE. [2]

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Figure 12. Ring oscillator performance dependence on contact size of transistors with optimized SPE and without SPE for (a) DC REFF and (b) delay. [2]

SUMMARY In this chapter, we have discussed the device implications of the contact resistance reduction approaches that are introduced in the previous chapter. The scaling of transistors results in a significant portion of device resistance due to contact resistance thus the approaches of contact resistance reduction need to be inserted into the device integration flow. Integrating the approaches into different modules of the CMOS process flow could have great difference in performance along with side effects. The insertion of SPE and LPE approaches after opening the contact trenches could bring net benefits to the overall RON and RO delay while other device electrical parameters like DIBL and IOFF concerning the short channel effects and leakage are not impacted. Considering the CMOS of both NFETs and PFETs, SPE with neutral elements such as Ge is relatively easy to implement. SPE with doping elements brings even more performance but needs separate NFET and PFET processes. An in-situ high doping concentration from the S/D formation is also enssential as it provides the base available dopants to be reactivated during the SPE. After the SPE and contact formation, thermal budget in the downstream needs to

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be as low as possible to prevent dopant deactivation caused contact resistance degradation.

REFERENCES [1] [2]

[3] [4]

[5]

[6]

[7]

Kuhn, K. J. “Considerations for ultimate CMOS scaling,” IEEE Trans. Electron Devices, vol. 59, no.7, pp.1813-1828, (2012). Wu, H. et al., “Integrated dual SPE processes with low contact resistivity for future CMOS technologies,” in Technical Digest – International Electron Devices Meeting, IEDM, 2017, pp.22.3.122.3.4. Uppal, S. et al., “Diffusion of ion-implanted boron in germanium,” J. Appl. Phys., vol.90, no.8, pp.4293-4295 (2001). Gluschenkov, O. et al., “FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys,” in Technical Digest - International Electron Devices Meeting, IEDM, 2017, pp. 17.2.1-17.2.4. Auth, C. et al., “A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects,” in Technical Digest - International Electron Devices Meeting, IEDM, 2018, pp. 29.1.1-29.1.4. Ha, D. et al., “Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications,” in Digest of Technical Papers - Symposium on VLSI Technology, 2017, pp. T68-T69. Wu, S. Y. et al., “A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications,” in Technical Digest International Electron Devices Meeting, IEDM, 2017, pp. 2.6.12.6.4.

In: An Introduction to Contact Resistance ISBN: 978-1-53618-501-0 Editor: Zuoguang Liu © 2020 Nova Science Publishers, Inc.

Chapter 7

CONTACT ENGINEERING OF TWO-DIMENSIONAL TRANSITION METAL DICHALCOGENIDES Zhihui Cheng1, PhD and Aaron D. Franklin1,2, PhD 1

Department of Electrical and Computer Engineering, Duke University, Durham, NC, US 2 Department of Chemistry, Duke University, Durham, NC, US

ABSTRACT Two-dimensional (2D) materials have captured tremendous attention in recent years. One sub-family of such 2D materials are transition metal dichalcogenides (TMDs), which comprise ~40 different materials with a range of electronic properties, including insulators, semiconductors, and conductors. Challenges, however, still cloud the promise of unbounded applications for 2D TMDs. One major difficulty is the formation of metal-2D contacts with low contact resistance, limiting device performance for a range of applications from transistors to photovoltaics. Hundreds of papers have been published on contact engineering to 2D materials, including TMDs. This chapter is by no means a comprehensive overview of those studies. Meanwhile, contact engineering for 2D

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Keywords: 2D materials, TMDs, contact resistance, 2D interface, contact engineering

7.1. INTRODUCTION Over the last decade, atomically thin, two-dimensional (2D) nanomaterials have become an active platform for investigating a wide range of novel physical phenomena and applications [1, 2]. Starting with graphene, new 2D nanomaterials with diverse properties continue to emerge, from insulator to metallic, and from elemental to compound [3]. Applications based on 2D nanomaterials are as expansive as the variety of materials themselves, including electronics, energy storage, photonics, sensors, and so forth. The ultrathin nature of semiconducting 2D crystals offers particular promise for future scaled electronic devices. There have been several review papers comprehensively covering aspects of contact engineering to these various 2D nanomaterials [4–9]. We focus on the core challenges of the 2D nanomaterial contacting interfaces and identify key questions and objectives to guide further research. In the following sections, we introduce basics of 2D materials, contact geometries, and transport models.

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7.1.1. 2D Materials

Figure 1. The family of TMDs. (a) ~40 different layered materials constitute the TMD family. The boxes with orange color are Chalcogen or X and Transition metal are in the shaded box from column 4-10. Partial highlights for Co, Rh, Ir and Ni suggest not all of the elements form layered structures. (b) Top and side view of a typical crystal scheme of TMDs. (c) Example of the layered structure of MoS 2. (d) Table of common TMDs and their bandgaps from [11].

Among the 2D crystal options, semiconducting transition metal dichalcogenides (TMDs) have attracted most of the attention for electronic

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devices. As shown in Figure 1, TMDs have the chemical formula MX2, where M is a transition metal of group 4-10 (typically Mo, Nb, W, Ni, V or Re) and X is a chalcogen (Se, Te or S) [10]. There are ~40 different combinations of TMDs with different chalcogen atoms. Based on the coordination and oxidation state of the metal atoms, TMDs comprise of insulators such as HfS2, semiconductors such as MoS2, semimetals such as TiSe2, and true metals such as NbSe2 which can even exhibit superconductivity at low temperature. While the bonds of TMDs within one sheet are covalent, neighboring sheets are bonded only by van der Waals interactions (see three layers of MoS2 in Figure 1(c) as an example). TMDs also host a range of band gaps depending on the type, phase and thickness (Figure 1(d)). In this chapter, MoS2 is used as the primary representative for TMDs since it has been most widely studied and can guide the research on other TMDs.

7.1.2. Contact Geometries There are primarily two different contact geometries that have been explored for 2D FETs: top contacts and edge contacts. It is essential to distinguish these two contact geometries as lots of papers reporting top contacts use edge contact geometries in their device schematics. The vast majority of studies use the top contacts due to the simplicity of fabrication. As shown in Figure 2(a), 3D metal top contacts rest on top of the 2D nanomaterial. More details on improving contact resistance of top contacts are covered later. The second type of contact geometry is edge contact (Figure 2(b)). One subgroup of this geometry employs 2D nanomaterials, such as graphene, to form an in-plane contact interface. For example, the interaction between MoS2 and graphene has exhibited Ohmic contact behavior [12–16]. Note that an “Ohmic contact” does not guarantee small contact resistance as linear output curves (at small Vds) could have a small slope and thus a large contact resistance. Some 2D crystals, such as MoS2, exhibit both semiconducting and metallic phases, enabling the use of the

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metallic phase to create an in-plane 2D contact [17]. Note that this phase engineering requires high processing temperature of 600°C [18] and thus is not compatible with traditional semiconductor fabrication processing. Electrostatic doping has also been reported to induce structural phase transition in monolayer MoTe2 [19]; however, more work is needed to implement fabrication-friendly phase engineering that yields better contacts.

Figure 2. Two different contact geometries. (a) Metal top contacts where the contact rests on top of the 2D nanomaterial. (b) Metal edge contacts where the contacts only interface with the edge of the 2D crystals.

Another subgroup of edge contacts use metal as the source and drain [20–22]. The most notable example uses a chromium (Cr) edge contact to graphene that yields contact resistance as low as 150 Ω∙µm [22]. While edge contacts to MoS2 have received limited investigation, molecular dynamic simulation for the metal-MoS2 edge contacts suggest they can outperform top contacts due to more intimate orbital overlapping between the metal atoms and edge states of MoS2 [23]. Yet, despite such promise, experimental realizations of edge contacts show small on-currents, possibly due to the sensitive MoS2 edge states and small contact area exposed on the edge [20, 21]. The possibility of a more efficient contact between the MoS2 edge and metal is intriguing and requires more in-depth research.

7.1.3. Carrier Transport The contact interface for 2D field-effect transistors (FETs) typically involves a three-dimensional (3D) contact on top of the 2D nanomaterial,

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as illustrated in Figure 3(a) with molybdenum disulfide (MoS2) as an example. Although the physics of interfacial interactions and carrier injection mechanisms are not fully understood, it is generally believed that electrons first tunnel through the van der Waals gap between the metal contacts and the 2D nanomaterial, depicted as the red arrows in Figure 3(a-b) [5]. Then, the injected electrons from the source contact flow to the drain under an electric field from Vds. Note that different models are needed to paint the actual transport picture as different 2D thickness, contact geometry, and gating scenario can readily change the carrier injection mechanism. Also, this topic is still in the stage of active research, both theoretically and experimentally.

Figure 3. An example transport picture of a top contact interface. (a) Simplified, crosssectional diagram of carrier injection. (b) Band diagram of the interface assuming a weak bonding between the contact and the TMDs. (a-b) are reprinted from [23] (available under the terms of the Creative Commons Attribution 3.0 License which permits unrestricted use, distribution, and reproduction in any medium, provided attribution to the author(s) and the published article’s title, journal citation, and DOI are maintained).

7.2. CONTACT INTERFACE Understanding the contact interface is pivotal for lowering contact resistance. Approaches for improving the 2D FET performance with top contacts include using different contact metals [24–27], annealing [28], [29], adding an interlayer at the contact interface [30–34], engineering surface states [35], and doping chemically [36–39] or physically [40]. Instead of reviewing all of the approaches reported in detail, which has been done by a variety of review papers [4–9], we will cover the most

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critical aspects, including the impact of different metals, interface modification, contact gating and scaling.

7.2.1. Different Contact Metals Metals with different properties lead to significant differences in contact resistance to TMDs. Some metals, such as Ti, have been found to form compounds with S in MoS2 in the top contact geometry [41, 42]. The TixSy compound was formed under UHV conditions, as confirmed by Xray photoelectron spectroscopy (XPS) (Figure 4(a)). The covalent bonds between metal and MoS2 are likely due to S vacancies present on the MoS2 surface. However, the formation of these bonds does not guarantee superior performance, as Ti still forms a worse contact than Cr and other high work function metals such as Au and Ni [43]. Another contact interface challenge is the manifestation of a Fermi level pinning-like behavior, as shown in Figure 4(b) [44]. Density functional theory (DFT) simulations suggest the Fermi level pinning is a result of interfacial interactions, where the metal work function can be modulated by interface dipoles due to charge redistribution [45]. A recent study on transferred metal demonstrates a substantially quenched Fermi level pinning effect, attributed to the pure van der Waals interface produced by the transferred metal approach [46]. The study also suggested that the commonly used metal evaporation approach promotes a metal-2D interfacial interaction (via damage to the 2D crystal), leading to a strong Fermi level pinning effect. On the other hand, according to some theoretical simulations, different bonding strength and orbital overlapping between metals and 2D materials could lead to a small Schottky barrier and thus high carrier injection efficiency [23], [47–49]. Many experimental studies intentionally add defects to the contact region to promote more covalent bonds and interfacial reactions at the metal-2D interface and do observe improvement in the contact performance [50–52]. The proposed mechanism for these experimental observations typically involves: the creation of defects 

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more metal-2D bonds  smaller (or thinner) Schottky barriers  smaller Rc. However, there are many open questions remaining to be answered, such as how high the suitable defect density is and how metal-2D bonds impact the Schottky barrier. Thus, there has yet to be a comprehensive picture that captures exactly how interfacial interactions impact the carrier injection and thus further studies are needed.

Figure 4. Understanding the contact interface. (a) XPS characterization of interface chemistry of Ti on MoS2 showing hybridization and covalent bonds at the interface. Adapted from [44] with permission. Copyright 2016 American Chemical Society. (b) Illustration of Fermi level pinning at the metal-2D interface. Adapted from [44]. Copyright 2017 American Chemical Society. (c) Comparison of evaporated metal and transferred metal showing strong Fermi-pinning effect for the evaporated metal and obedience to the Schottky-Mott law for the transferred metal. Adapted from [44] with permission. Copyright 2018 Springer Nature.

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7.2.2. Contact Interface Modification Since the dangling bond free 2D surface is likely not conducive to the charge injection, it is worthwhile to explore the effect of defects on carrier injection in the contact interface. In graphene, it has been demonstrated that intentionally damaging the crystal lattice in the contact region using O2 plasma can substantially reduce Rc and boost performance [53–56]. The mechanism is likely due to the defect sites created onto the contact region. Since O2 plasma is likely to etch the underlying 2D materials quickly, we introduce a study using a low energy convergent ion beam to selectively modify the contact interface and thereby improve contact resistance [57]. Figure 5(a) depicts the experimental setup where the convergent ion beam source exclusively hits the substrate with negligible interaction with the chamber wall. The ultra-high vacuum (UHV) chamber houses an ebeam evaporator for in situ metal deposition after ion beam bombardment. The energetic ions (Ar+) impinging on the MoS2 surface sputter away Mo and S atoms, with sulfur comprising the majority of the sputtered atoms due to its lighter atomic weight and higher density in the crystal lattice (Figure 5(b)). The main parameters that were controlled in the experiments herein are the beam energy and current (ion flux) using an automated controller module.

Figure 5. Experimental setup of the in situ convergent Ar+ ion beam source. (a) Schematic of the convergent ion beam source incorporated with an e-beam evaporator within an ultra-high vacuum (UHV) chamber. (b) Diagram showing the process of ions knocking out Mo and S atoms from the MoS2 crystal. Adopted from [57].

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Figure 6. Cross-sectional STEM analysis of 600 eV ion beam modified MoS 2 film. (a) Mechanically exfoliated, unaltered 15L MoS2 flake. Scale bar, 4 nm. The same flake after (b) 25 seconds and (c) 50 seconds of 600 eV ion beam exposure. Scale bars in (bc) are 5 nm. (d-e) High magnification image of (a-b) comparing the atomic defects and disorder. Scale bars in (d-e) are 2 nm. Adopted from [57].

In order to analyze the atomic deformations caused by the convergent ion beam, cross-sectional STEM was used. A 10 nm (15L) flake was mechanically exfoliated onto a 300 nm SiO2 /P++ Si substrate, as shown in Figure 6(a). Using poly(methyl methacrylate) (PMMA) as an etching mask, different regions of the same flake were irradiated with a 600 eV ion beam (beam voltage Vb = 600 V, beam current Ib = 36 mA). To make the effect of the ion beam more pronounced across different layers, the beam voltage and current were increased to 600 eV and 36 mA with a prolonged exposure time of 25 s and 50 s. Cross-sectional STEM images after 25 s and 50 s ion beam exposure are presented in Figure 6(b-c). Comparing the unexposed region (Figure 6(a)) to the one exposed for 25s (Figure 6(b)), defects and deformations can be seen across different layers. The thickness decreased from 10 nm (15L) to 4 nm (5L-6L) after ion beam exposure—an

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etch rate of approximately 1L per 2.5 s. However, this etch rate is not consistent with time, as is evident from comparing the results of 25 s and 50 s exposure. After the 50 s exposure, the 2-3L region still partially remains. Surprisingly, some interlayer delamination in the MoS2 crystals is also observed, as shown in Figure 6(c). In addition, small and large gaps appear horizontally between different regions and vertically between different layers. These new effects could have profound implications for metal-2D material interfaces and other applications such as intercalation and sensing devices. In order to atomically compare the unexposed and exposed layers, the higher magnification STEM images in Figure 6(a,b) were studied. An ordered and uniform atomic structure is present across different layers of the unaltered MoS2 (Figure 6(d)), whereas the 25 s exposed region shows apparent disorder and defects, indicated as arrows in Figure 6(e). Examining the remnants of the topmost layers in Figure 6(e) reveals structural disorder, leaving no distinguishable MoS2 crystal lattice. In order to explore the effect of convergent ion beam modification on contact resistance, a 5 nm (7L) MoS2 flake was exfoliated and transferred onto a 10 nm SiO2/p++ Si substrate. Of special note is that only the contact region was exposed, keeping the channel region intact, by using PMMA as a mask. Moreover, in order to avoid variation for the purpose of comparing device performance, the devices were fabricated with and without ion beam modified contacts on the same MoS2 flake. The same ion source is used as in the previous experiments. It is worth stressing that immediately after ion beam modification (Figure 5(a)), the in situ e-beam evaporator was used to deposit the contact metal (Figure 7(a)), protecting the modified region from other reactive species. Figure 7(b,d) are schematics of the two contact interfaces. 40 nm of Ni was used as the contact metal. After characterizing the devices in N2 at room temperature, the devices with 60 eV ion beam modification was found to outperform the unaltered devices, as shown in Figure 7(e). From the output curves in Figure 7(f), the modified devices also show improvement in the low VDS region, where carrier injection at the contact dominates the current output. At VDS < 0.5 V, The I-V curves of the device with ion beam have a larger slope than the unmodified device, indicating a smaller contact resistance. As VDS

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increases, the current output depends more on the channel properties, thus limiting the improvement of ID at VDS = 3 V. The total resistance of these devices at VDS = 0.5 V was calculated and plotted Rtot in Figure 7(g). Using the transfer length method (TLM), RC was improved from 17.5 kΩ μm to 6 kΩ μm at a relatively low carrier density of n2D = 5.4×1012 cm-2. This improvement of contact performance is attributed to the defects facilitating greater carrier injection.

Figure 7. Alteration of metal-MoS2 contact interface using Ar+ ion beam. (a) Diagram of the in-situ Ni evaporation process carried out immediately after ion beam exposure. Schematics of (b) the metal contact region of a non-modified device (prior to lift-off) and (d) a modified device (prior to lift-off). (c) AFM image of a set of devices fabricated on a single MoS2 crystal region. Scale bar, 2 μm. (e-f) Comparison of I-V characteristics for 60 eV altered versus unaltered contact 2D FETs. (g) Extraction of R c using the transfer length method (TLM). (h) Comparison of the effect of different ion beam energies on device performance. The ion beam exposure conditions are as follows (60 eV, 3 mA, 3 s), (200 eV, 3 mA, 3 s) and (600 eV, 36 mA, 3 s). Adopted from [57].

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7.2.3. Contact Gating Contact gating can dramatically impact the carrier injection profile and thus the contact resistance. The back-gate geometry (typically using a doped Si substrate as the gate electrode) is the most commonly used gating approach in 2D FETs due to the ease of fabrication. In a back-gated device, the metal-2D interface will be modulated by the back gate, creating a contact gating scenario. Contact gating has been examined in the past and the transfer length (LT) was extracted to be ~0.63 µm for monolayer devices using LT = (ρc/Rsh)1/2, in which ρc is the metal-2D interfacial resistance and Rsh is the lateral sheet resistance of the 2D material underneath the metal contact [58]. However, two recent experimental studies of contact scaling estimated the LT to be ~35 nm [24] or ~2 nm [59] for devices with 2-3 layers MoS2 in a back-gated geometry. These discrepancies between different experimental results require new theoretical models to depict the carrier injection behavior of scaled contacts along with the influence of contact gating. A two-path carrier injection model has been applied by two separate studies [60, 61], both of which suggest a much smaller LT for back-gated monolayer 2D devices. As depicted in Figure 8, in the two-path model, Path-1 represents carrier injection from the metal to the edge of the 2D channel, and Path-2 accounts for carriers vertically tunneling to the metalcovered 2D crystal and then laterally traveling to the channel region. The back-gate modulation of the metal-2D interface allows for even more carriers in Path-2, which explains why back-gated geometries outperform top-gated geometries with the same monolayer [62] and 7-layer (7L) [60] 2D channels. However, another theoretical study estimated that for monolayer and bilayer 2D devices with back-gate control, LT is close to 1 nm, as most carriers would accumulate at the metal-2D edge (path 1) because the Schottky barrier fully depletes the 2D semiconductor below the metal [61].

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Figure 8. Illustration of the two-path model for back-gated 2D devices where (a) shows the two injection paths and (b) is a typical transfer characteristic of a back-gated WSe2 FET, along with the individual contributions of each of the two paths, calculated as per the new model presented in [60] for a Schottky barrier height of 0.4 eV and a body thickness of 7 nm by assuming a square root scaling length λS for Path-1. Green circles assume continuous band movement for Path-1 even above its threshold (VTP1) whereas green dashed lines assume slowed down band movement for Path-1 above threshold. Adopted from [60] (licensed under Creative Commons Attribution 4.0 Int’l License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, with appropriate credit to the original author(s) and source).

Even when using the same gate geometry, 2D nanomaterial thickness (number of layers) can also impact the transfer length. 2D thickness is a major factor impacting overall device performance [27, 63]. One experimental study found that Ti-6L MoS2 has a larger LT than that of Ti2L MoS2 with the same back-gate overdrive voltage [64]. However, in top gate geometries, how a different number of 2D layers affects transfer length remains unclear. These discrepancies between different experimental and theoretical studies highlight the need for further

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theoretical and experimental investigation of the impact of contact gating and 2D nanomaterial thickness on the transfer length and carrier injection.

7.2.4. Contact Scaling The advantage of 2D crystals as a channel material is most obvious in sub-10 nm dimensions as its ultra-thinness allows for extremely scaled channel lengths (Lch ≤ 10 nm), at which silicon (Si) would not be able to achieve satisfactory performance [65–67]. For a fully scaled device technology, both the channel and contact lengths must be scaled to sub-10 nm. Yet, contact scaling has been largely neglected for 2D FETs. Papers reporting the most promising performance for 2D FETs, even at small channel lengths, have contact lengths of hundreds of nm to several μm [24], [36]. Contact scaling based on top metal contacts (Figure 9(a)) has shown severely degraded performance, especially when the contact length Lc drops below the transfer length, LT (~30-40 nm for top-contacted MoS2 of exfoliated 2-3 layers) [24], as shown in the inset of Figure 9(b)).

Figure 9. Scaling contact length in MoS2 FETs. (a) Cross-sectional TEM image of scaled top contacts. (b) Performance degrades as the contact length decreases. (a-b) are adapted from [24] with permission. Copyright 2016 American Chemical Society.

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Figure 10. Scaling contact length in MoS2 FETs. (a) Cross-sectional TEM image of scaled top contacts. (b) ID performance stays in a close range as the contact length decreases. (a-b) are adapted from [59] with permission.

However, recently, ultra-scaled Ni contacts with Lc = 13 nm were demonstrated [59]. Although devices with ultra-scaled Lc suffer from larger variation in device performance, the on-current stays within the same magnitude regardless of the Lc. Thus, it was claimed that the carrier injection for the back-gated contacts happens at the edge of the top contact metal. Future study is needed to compare the scaled contacts in the saturation field, both vertical (sufficient VGS) and horizontal field (sufficient VDS). An example of the benchmarking and comparison is demonstrated in the next section. These scaled contacts shall also be investigated using asymmetrical contacts to further understand the properties and performance of scaled contacts. Edge contacts (effective Lc = 1 nm) have the potential to yield ultimate scalability, down to sub-5 nm, since the carrier injection area is independent of Lc. Recently, edge contacts to CVD-grown MoS2 films were reported [68], with the device schematics shown in Figure 11(a). Cross-sectional STEM imaging shows the abrupt interface of the metal contact and edge of the MoS2 in Figure 11(b). Several edge-contacted MoS2 FETs (Lc = 20~80 nm) were fabricated on the same 2D film. These edge-contacted devices, with the same Lch but different Lc, exhibited the same on-current (Figure 11(c)). TLM structures were fabricated to confirm the similar contact resistance, as given in Figure 11(c) [68]. The fact that device performance can be independent of the physical Lc using edge contacts is encouraging, and further experimental and theoretical studies investigating the edge interface and improving its performance are needed.

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Figure 11. (a-b) Schematic and cross-sectional STEM image showing edge contacts. (c) Similar device performance despite different Lc demonstrates the better scalability of edge contacts. (d) Extraction of Rc with TLM devices with different Lc. Adapted from [68].

7.3. BENCHMARKING Assessing contact performance is vital to compare different approaches and promote progress. A plethora of different parameters should be considered, including Lc, Lch, Vdd, EOT, Ion, on-off ratio and Rc. Before we dive into details of different reports on Rc of TMD FETs, it is necessary to know the target device performance. According to the final (2015) ITRS roadmap [69], a device for low-power applications around 2030 has to sustain sufficient on-current (Ion = 1500 µA/µm) and operate at a low supply voltage of Vdd ≤ 0.5 V with Ohmic contacts and small contact resistance. Transistors benefit most from output curves (Id- Vds) with features like those in Figure 12(b). Instead of benchmarking every available contact approach based only on one or two isolated metrics (typically contact resistance), which has been done to some degree in other review papers [5, 70, 71], in Table I we list the state-of-the-art contact engineering progress with emphasis on several key metrics. A selection of the best representative contact engineered MoS2 FETs were chosen, as these studies could provide guidelines for other 2D FETs. Most of the devices listed have contact resistance (Rc) close to 1 kΩ∙µm, except devices based on CVD films. We include parameters such as channel length (Lch), flake thickness in the

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channel (Tch) and carrier density (n2D), where n2D =VovCox/q, with overdrive voltage Vov = Vgs - Vth, Cox as the capacitance of the gate dielectric and q as the elementary charge.

Figure 12. (a) Schematic of a typical MoS2 field-effect transistor with contact length and channel length labeled. (b) Example of the desired output curves and parameters for an N-type 2D FET in the 2030 era [69].

Table 1. Benchmarking Representative TMDs FETs Contact approach

n Id Lch Tch µFE Rc ×1012 cm-2 µA/µm µm nm cm2V-1 s-1 kΩ•µm [30] Ni etched Gr 4.9 180 0.5 16 80 0.2 [17] 1T MoS2 6.4 60 0.7 1.4 50 0.2 [36] Cl doping 16.5 335 0.1 4 ~55 0.5 [24] UHV Au 9.6 200 0.1 4.5 35 0.74 [72] Ti 12.5 30 1.5 10 ~47 0.78 3.1 88 0.45 [73] In 8.1 18 ~0.8 [59] Ni 13 294 0.029 2 15 1.7 [74] Ag 18.0 19 4.3 0.7 20~45 ~3 5.0 18 1 [73] In 0.7 170 3.3 [75] Nb doped N/A 232 0.27 7 N/A 0.3 All Ion are extracted at Vds = 1 V. Top metal contacts are used in the reports listed above except in [17], which uses in-plane 1T MoS2 as the contact. *Top gate structure was used, whereas others use back-gate structure. Note we did not include low Rc data from low-temperature measurement. The shaded row is based on WSe2 FETs while others are based on MoS2 FETs.

The need for considering the collection of metrics in Table I when analyzing the performance of a given 2D FET is based on the frequent incongruence of actual device performance (e.g., Id) and favorable metrics (e.g., Rc). For example, phase engineered 1T MoS2 contacts were reported

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to yield the smallest contact resistance of 200 Ω∙µm, yet produced disproportionately low Id, even with a relatively short Lch of 0.7 µm. Cl doping yielded the highest Id, yet it required the highest n2D of 16.5×1012 cm-2 and effective n2D of nearly 29 ×1012 cm-2 because of both chemical and electrostatic doping [36]. The larger carrier density gives rise to a smaller estimated Rc and degraded on-off ratio. Directly comparing the different approaches in Table I with multiple variables is challenging. In order to make a better comparison, we define a metric to represent the contact performance (CP): 𝐼

𝐶𝑃 = 𝑉𝑑𝑠 𝑑

⁄𝐿 𝑐ℎ

1

∗𝑅

𝑐

Benchmarking devices without considering source-to-drain field (Vds/Lch) and gate field (Vov/EOT) can lead to biased comparison. CP takes into account of the source-to-drain field, at which the Rc and Id is extracted. Usually, Rc is extracted at a relatively low source-to-drain field, when the Id-Vds curves are linear; for example, Vds = 0.5 V for devices with Lch = 500 nm. The larger the CP, the better the contacts. We then consider the gate field across the gate oxide (represented by carrier density, n2D) and plot CP vs. n2D, as shown in Figure 13.

Figure 13. Benchmarking MoS2 FETs performance in terms of contact performance CP versus n2D (which is a function of the gate field). MoS2 thickness for multilayer devices is given in orange.

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To gain a full picture of the device performance both in the linear region and the saturation region with high gate field, we must measure devices across a full range of carrier density. Extracting Id and Rc before compensating for Vth shift and considering the Vov is a common mistake that leads to overestimation in performance related to the contacts [38, 39, 76, 77]. Other parameters, such as on-current Ion (Isat), Ion/Ioff ratio, subthreshold swing (SS), should also be benchmarked with both the source-to-drain field and gate field (VOV or n2D) taken into account. This holistic approach of benchmarking can yield more leveled comparisons. From Figure 13, the fact that the Ni etched graphene approach already exceeds the 2030 target is surprising, which highlights the need for validation by other groups. Approaches that might work for thicker 2D crystals should also be investigated for thinner channel materials as thickness plays a key role. Devices built on CVD-grown MoS2 films typically have a higher Rc and more effort is needed to improve the quality of CVD films and subsequent contact interfaces. Further exploration is also needed to improve the Ion for MoS2 FETs based on monolayer TMDs, which is still far from the target performance outlined in Figure 12(b) and many simulation studies [78, 79]. Moving forward, when assessing future advances in contact engineering, a comprehensive view must be taken to evaluate the true potential of reported approaches. Rc should be reported together with its associated carrier density, especially in scenarios with contact gating. The impact of device dimensions and contact gating must be accounted for [60, 61]. Other critical issues, such as reproducibility, variability, and yield, may seem less exciting to study, but constitute the most substantial roadblocks for making 2D electronics a viable technology.

7.4. PROSPECT While considerable progress has been made in scaled highperformance 2D transistors [22, 27, 65, 80, 81], significant challenges remain related to interfaces with the 2D crystals in these devices. Research

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groups have been able to demonstrate low contact resistance and reasonably high on-current, but rarely simultaneously; and even when considered independently, both of these metrics are still far from the desired values. Moreover, there needs to be consideration of the variability and yield for proposed improvements to the metal-2D contact, along with a more comprehensive theoretical picture of transport at this unique interface to account for parameters such as gating configuration and the number of 2D layers. Looking ahead, the following aspects merit further research:    

Reproducible scaled contacts with small Rc and high Ion Better models explaining carrier injection in different contact scheme Contact gating effect on Rc and improving Rc under top gates Integration of top-gated and scaled devices into circuits

While achieving these efforts, maintaining better benchmarking is also pivotal. Together, these endeavors will pave the way for better understanding of 2D-3D material interface and hopeful future generation nanoelectronics.

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ABOUT THE EDITOR Zuoguang Liu Research Staff Member, Scientist IBM Email: [email protected] Dr. Zuoguang Liu is a Research Staff Member of IBM. He has worked on multiple technology nodes (32nm/14nm/10nm/7nm) and future exploratory device architectures for 5nm/3nm nodes. Dr. Liu is a Golden Reviewer for IEEE Electron Device Letters, and IEEE Trans. Electron Devices. He is an IBM Master Inventor with over 200 patents. Dr. Liu received his Ph.D. degree in Electrical Engineering and Applied Physics from Yale University in 2012, and B.S. degree in Physics from Peking University in 2007.

INDEX # 2D interface, 138, 143, 144, 149, 163 2D materials, 137, 138, 139, 143, 145, 157, 158, 161, 163, 164

annealing, 26, 33, 34, 35, 37, 38, 40, 41, 84, 96, 104, 109, 111, 112, 113, 116, 122, 127, 142, 160 Arrhenius equation, 102

B A activation, 41, 45, 49, 79, 81, 89, 93, 96, 97, 99, 102, 106, 107, 111, 112, 115, 122, 126 activation energy, 102, 107 activation enthalpy, 106 active dopant concentration, 45, 102, 111, 126 active doping concentration, 41, 45, 46, 81, 82, 87, 88, 92, 94, 95, 96, 101, 113, 114, 116, 128, 129 amorphization, 46, 49, 99, 104, 122, 127 amorphous Ge, 112 amorphous layer, 102, 103, 104, 120, 121 amorphous phase, 102, 105, 108, 112 amorphous pocket, 95, 115, 127 amorphous Si, 104, 112, 113, 120, 121 amorphous Si P, 113

B diffusion, 112, 115 B solubility, 93 back end of line (BEOL), 47, 124, 125 back-contact measurement, 58, 59 back-gate, 149, 150, 152, 154 back-gated, 149, 150, 152 band gap, 32, 140 benchmarking, 152, 153, 154, 155, 156, 157

C carrier injection, 94, 142, 143, 145, 147, 149, 151, 152, 157, 162, 163 carrier injection area, 152 carrier velocity, 3, 9, 12 channel, viii, 3, 4, 5, 8, 9, 11, 14, 17, 18, 19, 20, 23, 43, 67, 70, 73, 80, 94, 95, 125,

170

Index

126, 127, 129, 147, 149, 151, 153, 154, 156, 163, 164 channel charge, 8 channel current, 9 channel length(s), 3, 9, 12, 14, 23, 151, 153, 154, 164 channel potential, 8, 12 channel resistance, 14, 20, 80 charge-sheet model, 7 chemical, 45, 89, 117 chemical doping, 45, 89, 117 CMOS integration, 124, 132 CMOS technology, v, viii, 47, 80, 81, 83, 98, 117, 123, 124, 136 conduction, 26 conduction band, 26 conductivity, 45 contact, v, vi, vii, viii, 1, 3, 4, 14, 18, 19, 21, 22, 23, 25, 26, 27, 28, 31, 32, 33, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 51, 52, 53, 54, 55, 56, 58, 59, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 72, 73, 74, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86,87, 88, 89, 90, 91, 92, 94, 95, 96, 97, 98, 99, 101, 102, 103, 104, 112, 113, 114, 115, 116, 117, 118, 119, 122, 123, 124, 125, 128, 129, 130, 131, 132, 134, 135, 136, 137, 138, 140, 141, 142, 143, 144, 145, 147, 148, 149, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164 contact area, 21, 53, 54, 55, 58, 70, 73, 79, 80, 81, 82, 83, 84, 97, 141 contact engineering, 89, 137, 138, 153, 156, 158, 164 contact gating, 138, 143, 149, 151, 156, 157, 163 contact geometries, 138, 140, 141 contact interface(s), viii, 66, 90, 129, 138, 140, 141, 142, 143, 144, 145, 147, 148, 156 contact length, 58, 76, 81, 82, 83, 97, 116, 151, 152, 154

contact metals, 85, 142, 143 contact resistance, viii, 1, 14, 18, 21, 22, 26, 32, 41, 43, 45, 47, 48, 51, 52, 53, 54, 55, 61, 70, 73, 74, 76, 77, 79, 80, 81, 82, 89, 97, 101, 118, 119, 123, 124, 126, 129, 132, 134, 135, 137, 138, 140, 141, 142, 143, 145, 147, 149, 152, 153, 155, 157, 162, 163 contact resistance reduction, viii, 22, 48, 79, 80, 81, 82, 119, 123, 124, 126, 132, 134, 135 contact resistivity (ρc), viii, 21, 26, 42, 44, 45, 46, 49, 51, 52, 54, 55, 61, 62, 66, 76, 79, 80, 81, 82, 84, 87, 88, 89, 90, 92, 95, 96, 99, 101, 114, 115, 117, 119, 122, 123, 124, 125, 128, 129, 131, 132, 134, 136, 149 contact scaling, 149, 151, 164 contact size, 77, 81, 123, 124, 134, 135 contact width, 81, 82, 83 CPP, 19, 32, 41, 67, 70, 71, 72 crystalline, 104, 112, 113 crystalline Si P, 113 crystalline Si and Ge, 104, 112 current crowding, 55, 56, 59, 74 current density, 45, 64, 65, 82 current spreading and crowding effect, 66 current-voltage (I-V), 7, 9, 15, 16, 17, 30, 31, 32, 43, 44, 52, 53, 147, 148

D DC effective resistance (REFF), 134, 135 defects, 38, 39, 47, 94, 105, 109, 112, 116, 119, 143, 145, 146, 148 delay time constant, 20 depletion, 5, 8, 27, 28, 39 device performance, viii, 14, 20, 21, 70, 125, 137, 147, 148, 150, 152, 153, 154, 156, 161 DIBL degradation, 126, 128, 130, 131

Index diffusion, 14, 22, 26, 27, 29, 34, 40, 45, 93, 94, 104, 112, 115, 122, 127, 128, 130, 131, 136 dopant, 33, 42, 44, 79, 80, 87, 88, 92, 93, 94, 95, 96, 99, 100, 102, 104, 109, 110, 111, 112, 115, 116, 117, 119, 120, 121, 125, 126, 127, 128, 129, 131, 136 dopant activation, 93, 99, 104, 111, 119, 125 dopant concentration, 33, 79, 110, 111 dopant deactivation, 88, 93, 95, 96, 111, 112, 128, 129, 131, 136 dopant diffusion, 88, 93, 95, 100, 115, 126, 127, 129 dopant diffusion and segregation, 112, 115 doping, 13, 25, 26, 42, 43, 44, 45, 46, 47, 87, 88, 89, 93, 94, 102, 111, 113, 114, 116, 135 doping concentration, 13, 25, 26, 42, 43, 44, 45, 46, 47, 87, 88, 89, 93, 94, 102, 111, 113, 114, 116, 135 drain, 4, 5, 6, 7, 8, 10, 11, 13, 14, 15, 16, 25, 43, 67, 74, 75, 80, 81, 86, 98, 100, 125, 141, 142, 155, 163 drain current, 10, 11, 75, 163 drain induced barrier lowering (DIBL), 43, 125, 126, 127, 128, 130, 131, 132, 135 drain resistance, 14 drain voltage, 10, 11, 16, 75 dual metal contacts, 85 dual SPE, 49, 99, 122, 132, 133, 134, 136

E Edge contact, 152 edge contact(s), 140, 141, 152, 153 effective barrier thickness, 43 effective channel length, 11, 12, 14 effective current (IEFF), 126, 127, 130, 131, 132 effective mobility, 16, 20

171

electrical characterization, 52 electron affinity, 26, 27, 84 energy, 26, 31 energy band diagram, 26, 27, 30, 31 equilibrium, 4, 5, 6, 27, 28, 31, 88, 94, 111, 112 equilibrium band structure, 28 equilibrium concentration, 88, 111 extension resistance, 80 external resistance (REXT), 18, 21, 26, 70, 72, 74, 76, 80

F fast annealing, 41, 127 fast laser annealing, 101, 113 Fermi level(s), 4, 6, 26, 27, 33, 86, 118, 143, 144, 162 Fermi-level pinning, 32, 33, 43, 47, 86, 99, 162 FinFET, viii, 23, 47, 48, 49, 70, 76, 80, 83, 93, 96, 97, 98, 99, 119, 122, 124, 125, 128, 132, 136 FinFET integration, 125 FinFET process flow, 93, 96, 124, 125 FinFET technology, 49, 79, 83, 84, 97, 98, 99, 122, 124, 136 flat-band voltage, 9 forward bias, 29, 30, 32 front-end-of-line (FEOL), 41, 124, 125 furnace annealing, 33, 96

G Ga ion implantation, 90 Gallium (Ga), 90, 92, 93, 94, 99, 102, 117, 118, 122 gate bias, 4, 5, 13, 80 gate voltage, 4, 15, 17, 18 gate-to-source voltage, 16 gauging depth, 83

172

Index

Ge Ga metastable alloy, 118 Gibbs free energy, 106, 107 graphene, 138, 140, 141, 145, 156, 158, 159, 160, 162, 163

H high work-function metals, 84

I ideal, 27 ideal MS contact, 27 impurity, 49, 100, 104, 109, 112, 118, 121, 122 in-situ doping concentration, 92, 97 interface, 9, 20, 25, 26, 27, 31, 33, 36, 43, 47, 53, 71, 79, 80, 81, 84, 86, 87, 89, 93, 97, 101, 102, 104, 105, 106, 107, 108, 109, 115, 119, 138, 141, 142, 143, 144, 145, 152, 157, 160, 161, 162, 163 interface orientation, 107 internal resistance (RINT), 80 intrinsic SPE, 106, 109, 110 inversion, 4, 7, 9, 12, 67 inversion charge, 4, 7, 9, 12, 67 inversion layer, 4, 7, 13 ion implantation, 41, 45, 89, 95, 103, 114, 115, 117, 119, 120, 127, 128, 130, 132

J junction extension resistance, 14, 18

K Kelvin FET, 52, 67, 70, 72, 75, 76

L ladder TLM (LTLM), 19, 49, 51, 52, 53, 54, 55, 56, 58, 59, 62, 63, 69, 70, 72, 76, 82, 116, 148, 152, 153 laser annealing, 46, 48, 89, 90, 95, 102, 113, 115, 116, 119, 127 lateral/vertical gate-all-around, 70, 73 LGAA, 70, 71, 72, 73, 76 linear region, 10, 11, 12, 15, 16, 20, 156 liner silicide, 26, 41, 42 liquid phase, 26, 41, 79, 81, 101 liquid phase epitaxy, 26, 41, 79, 81, 89, 95, 101, 112 low work-function metals, 84 LPE, viii, 26, 42, 46, 79, 80, 81, 89, 95, 97, 101, 102, 112, 113, 114, 115, 117, 119, 127, 135 LSA, 96, 116

M majority, 6 majority-carrier, 6 melt, 102, 112, 113 melting, 95, 112, 115 melting point, 95, 112, 115 metal stud resistance (RMETAL), 81 metal work functions, 33, 34 metal-rich silicide, 38, 39 metal-semiconductor, 19, 26, 31, 52, 53, 81, 84, 86, 97, 124, 162 metal-semiconductor (MS) contact, 19, 25, 26, 27, 28, 29, 31, 32, 33, 41, 42, 43, 44, 47, 52, 84, 89, 92, 95, 124 metastable alloy, 101, 102, 111, 113, 118, 119 metastable Si P alloy, 113 middle-of-line (MOL), 41, 87, 124 minority carrier(s), 4, 6

Index mobility, vii, 3, 9, 10, 13, 17, 20, 45, 46, 47, 94, 122, 125 MOL, 41, 87, 124 molybdenum, 142 molybdenum disulfide (MoS2), 33, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 158, 159, 160, 161, 162, 163, 164, 165 monosilicide, 35, 37, 38, 39, 40 MoS2, 142 MOSFET, vii, viii, 1, 2, 3, 4, 5, 9, 10, 11, 14, 15, 16, 18, 19, 20, 21, 22, 23, 97 MS, 25, 26, 27, 28, 29, 31, 32, 33, 41, 42, 43, 44, 47, 63, 64, 89, 92, 95 mSec laser anneal, 113 multi-ring circular TLM (MR-CTLM), 52, 59

N nano-second (nSec) laser annealing, 95, 113, 114, 115, 118 NanoSheet (NS), 70 NanoTLM, 52, 58, 59, 69, 70, 76 neutral, 117, 135 neutral elements, 117, 135 Ni, 26, 33, 35, 36, 38, 39, 40, 42, 47, 84, 99, 139, 140, 143, 147, 148, 152, 154, 156, 162 Ni encroachment, 38, 40, 47 NiSi-fang, 38, 40 nonlinear region, 10, 11, 14 non-rectifying, 26, 28, 31, 43 nSec laser annealing, 113, 116, 118 nSec LPE, 114 NSFETs, 72 n-type contact resistivity, 116

173 O

off current (IOFF), 126, 127, 130, 131, 132, 135 ohmic contact, 26, 28, 31, 32, 43, 76, 140, 153 ON resistance (RON), 20, 21, 32, 43, 125, 126, 127, 128, 130, 131, 132, 134, 135 on-current, 141, 152, 153, 156, 157

P partition, 18, 19, 23, 67, 69, 70, 71, 72, 73, 74, 75, 76, 80 partition of transistor resistance, 80 peaking/peak temperature, 41, 95, 113, 114, 115 physical contact length, 58, 82 physical gate length, 14 pinch-off, 12, 13, 20

Q quasi-Fermi level, 4, 6

R RcFET, 52, 67, 68, 69, 70 reactivation, 96, 111 reactive ion etching (RIE), 39, 40, 41 re-crystallization, 95, 116, 127 rectifying, 26, 28, 29 replacement-metal-gate (RMG), 88, 93, 124, 128 resistance, v, vii, viii, 1, 14, 16, 18, 19, 20, 21, 22, 23, 25, 26, 29, 31, 32, 34, 41, 42, 43, 49, 51, 52, 53, 54, 59, 61, 62, 63, 64, 65, 67, 70, 73, 76, 77, 79, 80, 82, 86, 92, 96, 97, 101, 111, 115, 123, 125, 126, 127, 128, 130, 131, 132, 134, 135, 138,

174

Index

140, 147, 149, 153, 158, 159, 160, 161, 162, 163, 164, 165 resistance partition, 18, 19, 22, 63 reverse bias, 29, 30, 32 RIE, 39 ring oscillator (RO), 132, 134, 135

S S/D, 3, 14, 16, 18, 19, 25, 26, 32, 33, 34, 36, 37, 38, 39, 40, 41, 42, 43, 47, 67, 68, 69, 70, 71, 73, 74, 79, 81, 83, 84, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 101, 106, 114, 115, 116, 117, 124, 125, 126, 127, 128, 129, 130, 135 S/D doping concentration, 42, 93 S/D series resistance, 14, 18, 70 salicide, 36, 37 saturation, 10, 12, 13, 20, 156 saturation current, 13 saturation region, 10, 12, 13, 20, 156 SBH, 28 scalability, 134, 152, 153 scaling, vii, 1, 20, 21, 22, 25, 40, 41, 59, 70, 80, 81, 97, 123, 124, 135, 136, 138, 143, 150, 151, 152, 164 Schottky barrier, 25, 26, 28, 43, 79, 80, 84, 92, 143, 149, 150, 158, 163 Schottky barrier height (SBH), 25, 28, 29, 33, 34, 81, 82, 84, 85, 86, 87, 150 Schottky barrier height engineering, 84 Schottky contact, 26, 28, 30, 32 sensed potential, 67, 68, 71, 73, 74, 75 series resistance, 14, 15, 16, 17, 22 sheet resistance, 14, 18, 34, 52, 61, 63, 75, 96, 111, 149 short channel effects (SCE), 17, 95, 125, 127, 130, 135 silicide, viii, 18, 25, 26, 33, 34, 35, 36, 38, 39, 40, 41, 42, 47, 48, 84, 89, 98

solid phase epitaxy (SPE), viii, 26, 42, 46, 79, 80, 81, 89, 90, 91, 95, 97, 101, 102, 103, 104, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 120, 121, 127, 128, 129, 130, 131, 132, 133, 134, 135 solid solubility, 44, 45, 46, 87, 88, 90, 93, 94, 99, 101, 102, 111, 113, 117 source resistance, 14 source/drain (S/D), vii, 1, 3, 14, 16, 18, 19, 25, 26, 32, 33, 34, 36, 37, 38, 39, 40, 41, 42, 43, 47, 48, 67, 68, 69, 70, 71, 73, 74, 79, 81, 83, 84, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 101, 106, 114, 115, 116, 117, 123, 124, 125, 126, 127, 128, 129, 130, 135 source/drain epitaxy series resistance (REPI), 81 source-to-drain field, 155, 156 SPE, viii, 26, 42, 46, 79, 80, 81, 89, 90, 91, 95, 97, 101, 102, 103, 104, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 127, 128, 129, 130, 131, 132, 133, 134, 135 SPE rate, 102, 104, 106, 107, 108, 109, 110, 112 spreading resistance, 66, 73, 74 substrate doping, 4 surface potential, 4, 6, 8, 28 surface potential barrier, 28

T technology, 79, 84, 97 ternary phase diagrams, 35 thermal treatment(s), 40, 41, 93, 94, 96, 97 threshold voltage, 12 through-trench implantation, 113, 114 Ti, 26, 33, 35, 38, 40, 42, 47, 48, 49, 62, 84, 85, 86, 98, 99, 118, 122, 143, 144, 150, 154, 160

Index Ti liner silicide, 40, 41, 42, 47, 48, 98 TLM, 19, 49, 51, 52, 53, 54, 55, 56, 58, 59, 63, 69, 70, 72, 76, 82, 116, 148, 152, 153 TMDs, viii, 137, 138, 139, 142, 143, 154, 156 top contacts, 75, 140, 141, 142, 151, 152 top gate, 150, 154, 157 total resistance, 14, 16, 53, 54, 61, 64, 66, 148 transconductance, 13 transfer length, 51, 56, 57, 63, 76, 82, 148, 149, 150, 151 transistor, v, vii, 1, 2, 19, 22, 23, 41, 42, 51, 52, 67, 76, 77, 79, 80, 93, 97, 123, 124, 126, 127, 130, 131, 134, 154, 158, 159, 160, 164 transition metal dichalcogenides (TMDs), viii, 137, 138, 139, 142, 143, 154, 156, 157, 158, 161 transmission line measurement (TLM), 19, 45, 49, 51, 52, 53, 54, 55, 56, 58, 59, 63, 69, 70, 72, 76, 77, 82, 116, 148, 152, 153 trench epitaxy, 87, 88, 89, 90, 91, 97, 114 tunneling, 43, 45 tunneling current, 43, 45 turn-on resistance, 20, 32

175 V

vacuum, 26 vacuum level, 26 van der Waals gap, 142 VGAA, 70, 73, 74, 75, 76 VIA resistance, 18

W wiring resistance, 14, 18, 73 work functions, 26, 84 wrap/wrapped acround contact (WAC), 79, 80, 81, 83, 84, 97

X x-ray diffraction (XRD), 35, 36, 37 x-ray photoelectron spectroscopy (XPS), 39, 143, 144

Y yield, 25, 26, 35, 38, 47, 152, 155, 156, 157