Circuit Analysis [1 ed.] 9781617287039, 9781617281068

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Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved. Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved. Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

ELECTRICAL ENGINEERING DEVELOPMENTS

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CIRCUIT ANALYSIS

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ELECTRICAL ENGINEERING DEVELOPMENTS

CIRCUIT ANALYSIS

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

VIRGINIA E. WRIGHT EDITOR

Nova Science Publishers, Inc. New York

Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

Copyright © 2011 by Nova Science Publishers, Inc. All rights reserved. No part of this book may be reproduced, stored in a retrieval system or transmitted in any form or by any means: electronic, electrostatic, magnetic, tape, mechanical photocopying, recording or otherwise without the written permission of the Publisher. For permission to use material from this book please contact us: Telephone 631-231-7269; Fax 631-231-8175 Web Site: http://www.novapublishers.com

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The Publisher has taken reasonable care in the preparation of this book, but makes no expressed or implied warranty of any kind and assumes no responsibility for any errors or omissions. No liability is assumed for incidental or consequential damages in connection with or arising out of information contained in this book. The Publisher shall not be liable for any special, consequential, or exemplary damages resulting, in whole or in part, from the readers’ use of, or reliance upon, this material. Any parts of this book based on government reports are so indicated and copyright is claimed for those parts to the extent applicable to compilations of such works.

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Independent verification should be sought for any data, advice or recommendations contained in this book. In addition, no responsibility is assumed by the publisher for any injury and/or damage to persons or property arising from any methods, products, instructions, ideas or otherwise contained in this publication. This publication is designed to provide accurate and authoritative information with regard to the subject matter covered herein. It is sold with the clear understanding that the Publisher is not engaged in rendering legal or any other professional services. If legal or any other expert assistance is required, the services of a competent person should be sought. FROM A DECLARATION OF PARTICIPANTS JOINTLY ADOPTED BY A COMMITTEE OF THE AMERICAN BAR ASSOCIATION AND A COMMITTEE OF PUBLISHERS. Additional color graphics may be available in the e-book version of this book.

LIBRARY OF CONGRESS CATALOGING-IN-PUBLICATION DATA Circuit analysis / editor, Virginia E. Wright. p. cm. Includes bibliographical references and index.

ISBN:  (eBook)

1. Electronic circuits. 2. Electric circuit analysis. I. Wright, Virginia E. TK7867.C496 2010 621.3815--dc22 2010025436

Published by Nova Science Publishers, Inc. † New York

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CONTENTS

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Preface

vii

Chapter 1

Element Stamp Algorithm for Matrix Formulation of Symbolic Circuits Fawzi M. Al-Naima and Bessam Z. Al-Jewad

Chapter 2

Microwave and Millimeter-Wave Coaxial-Waveguide Power-Dividing/Combining Circuits Kaijun Song

Chapter 3

Analysis of Feedback Circuits Using Miller's Techniques V.C. Prasad

105

Chapter 4

Tire Pressure -Temperature Tester for Real Driving Conditions Pavel Koštial and Ivan Ružiak

131

Chapter 5

Analyzing Circuit Structures as Language Takushi Tanaka

143

Index

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1

55

181

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved. Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

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PREFACE Understanding a circuit means finding the hierarchical structure of its functional blocks and rediscovering the designer's original intentions. This book presents a new method for analyzing circuit structures as sentences and their elements as words in order increase the level of automatic circuit understanding. Also discussed is a new formulation procedure that not only changes the solution strategy, but it also changes the view of matrix reduction techniques, as well as the use of electromagnetic (EM) stimulation tools for the first-pass design of coaxial-waveguide power-combining circuits. The need to analyze a linear network is a recurring requirement in computer-aided network analysis. Not only a majority of the network problems to be solved is posed as linear problems; nonlinear resistive and dynamic networks are usually solved by the analysis of a sequence of “linearized” networks. The analysis of such networks can commonly be viewed as a two-stage process: 1. equation formulation and 2. linear solution. In Chapter 1, an attractive formulation procedure will be uncovered that will not only change the solution strategy but also the authors’ view to matrix reduction techniques. In the integrated symbolic circuit analysis, one might attempt substituting every component of the circuit by its model. Such an analysis is based on a strictly network-modeling point of view and it appears highly descriptive of the circuit behavior. However, a strictly symbolic network analysis is not

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Virginia E. Wright

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actually of any interest to engineers. This is mainly due to two inherent drawbacks in such an analysis: 1. As this analysis introduces many additional elements and variables to the original circuit, the resultant symbolic expression will be extremely large and beyond any human interpretation or comprehension even for the smallest circuits (not to mention the size limitation imposed on the circuit to be analyzed). Such a result will be completely useless especially for the designer. The reason behind this is simple: To design a circuit, it is easier to have five or six variables to control within some simplified constraints than to have a hundred variables most of which having complicated constraints and do not affect the circuit characteristics by any considerable amount. 2. A strictly symbolic network analysis requires extremely high processing power and storage even for small circuits. Furthermore, the system matrix suffers often from ill-conditioning and singular values, which imposes an additional analysis difficulty against producing a result that can be produced much more efficiently by other methods of circuit analysis. Ill-conditioning of symbolic system matrices is further complicated by the fact that numerical values do not exit to check for such a problem during the formulation process The compacted modified nodal analysis CMNA method (or the elementstamp method) is a very nice and easy way to illustrate the impact of each element on the matrix since it constitutes going through each branch of the circuit and adding its contribution to the system matrix in the appropriate positions. It represents an automatic technique to construct the nodal admittance matrix. This method consists of programming a lookup table for every element type in the network. This table has link-lists that will test which variables of the element are actually needed in the final compacted matrix and introduce the element in a way so as to eliminate the redundant variables. The microwave power-combining technology is one of the most important approaches to obtain high power using semiconductor devices, especially in millimeter-wave band, in which the available power from a single device is low. Conventional hybrid-type power-combining circuits, such as Wilkinson power dividers, Lange couplers, and branch-line couplers suffered from low power-combining efficiency, limit power handling capability, and impedance bandwidth. In this chapter, the authors discuss the novel designs of microwave and millimeter-wave coaxial-waveguide power-dividing/combining circuits.

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Preface

ix

The traditional rectangular waveguide power dividers have limited bandwidth due to the cutoff frequency and transmission dispersion effect. The coaxial waveguide is a good (potential) candidate to overcome these problems due to its TEM waveguide environment. In this chapter, the authors have detailedly discussed the oversized coaxial waveguide power dividers using a probe array to achieve very wide band and low insertion loss. Furthermore, the equivalent-circuit method has been developed to analyze this type of powerdividing circuits. To integrate the 3-D waveguide divider and planar power amplifier circuitry, the planar probe coaxial-waveguide power divider/combiner has been developed and investigated. In addition, a novel ultra-wideband (UWB) multi-way coaxial-waveguide power divider with rotated electric field mode has been discussed, and it will be easy to construct the active power-combining system at microwave and millimeter-wave frequencies. Chapter 2 also provides many design examples using full-wave electromagnetic (EM) simulation. EM simulation tools have become widely available and served as an invaluable tool for the first-pass design of coaxialwaveguide power-combining circuits. Miller's theorem is a popular tool to analyze electronic circuits. It is often used by assuming that closed loop voltage gain is approximately equal to open loop voltage gain. But nothing is known so far about the conditions under which this approximation works. Chapter 3 shows that Miller’s approximation is valid if the circuit without feedback possesses one of the following properties. (i) The forward current gain (h f) is large (ii) The reverse current gain (hr) is small in a certain sense (iii) Trans resistance gain is larger than output impedance and output impedance is small (iv) Trans conductance gain is larger than input admittance and input impedance is large (v) Reverse trans resistance gain is smaller than input impedance and input impedance is large (vi) Input impedance is large and output impedance is small (vii) Reverse trans conductance gain is smaller than output impedance and output impedance is small (viii) Input impedance is small and output impedance is large. Similar results are derived for Miller’s dual. This theorem is normally used for series feedback. It is well known that Miller’s theorem cannot be used to determine all parameters of the circuit. Contrary to this, a method is proposed to get all parameters using one Miller parameter only. An example is given to show that Miller’s dual works in some situations where Miller theorem fails to deliver. As explained in Chapter 4, the heat in tires is created by a tire deformation (accompanied by hysteresis), and its amount is dependent on many factors such as material properties, construction, etc.

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Virginia E. Wright

The heat sources in the tire in the exploitation process could dangerously increase the local temperature and consequently cause destruction of the tire. In this contribution the authors present a complex system for the simultaneous contact less measurement of external and internal tire temperature as well as the internal tire pressure (CTPA). The measurement is fully automatic, controlled by a personal computer and installed “in situ” on the car. The global position system, which is connected to a PC, also allows us to measure the car speed in synchronized regime with other measured parameters. All external temperatures under investigation were independently tested by other contact thermometers. As a step toward automatic circuit understanding, the authors present a new method for analyzing circuit structures. The authors view circuits as sentences, and their elements as words. The electrical behavior and functions are the meaning of the sentences. Circuit structures are defined by a logic grammar called DCSG. A set of grammar rules, when converted into Prolog clauses, forms a logic program which perform top-down parsing. When an unknown circuit is given, this logic program will analyze the circuit and derive a parse tree for the circuit. In Chapter 5, the authors first present the basic concepts of the logic programming using examples of circuits, then introduce the logic grammar DCSG (Definite Clause Set Grammar) which was developed for word-order free languages. Circuits are represented as sentences in the language. Circuit structures are defined as grammar rules for functional blocks composing bipolar analog ICs. A given circuit is parsed as a grammatical sentence, and its hierarchical structure of functional blocks is derived. An extension to DCSG uses additional fields to hold semantic terms. Using the fields, electrical behavior and functions can be defined for the syntactic structures. After a circuit is parsed, not only its syntactic structure, but also its electrical behavior and functions can be derived as the meaning of the circuit structure.

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Chapter 1

ELEMENT STAMP ALGORITHM FOR MATRIX FORMULATION OF SYMBOLIC CIRCUITS Fawzi M. Al-Naimaa and Bessam Z. Al-Jewadb

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Department of Computer Engineering, College of Engineering, Nahrain University, P.O. Box 64040. Jadriya, Baghdad, Iraq *

Abstract The need to analyze a linear network is a recurring requirement in computeraided network analysis. Not only a majority of the network problems to be solved is posed as linear problems; nonlinear resistive and dynamic networks are usually solved by the analysis of a sequence of “linearized” networks. The analysis of such networks can commonly be viewed as a two-stage process: 1. 2.

equation formulation and linear solution.

In this chapter, an attractive formulation procedure will be uncovered that will not only change the solution strategy but also our view to matrix reduction techniques. In the integrated symbolic circuit analysis, one might attempt substituting every component of the circuit by its model. Such an analysis is based on a strictly network-modeling point of view and it appears highly descriptive of the a E-mail address: [email protected], [email protected]. b E-mail address: [email protected]. * Fax: (009641) 7786242

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad circuit behavior. However, a strictly symbolic network analysis is not actually of any interest to engineers. This is mainly due to two inherent drawbacks in such an analysis: 1.

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2.

As this analysis introduces many additional elements and variables to the original circuit, the resultant symbolic expression will be extremely large and beyond any human interpretation or comprehension even for the smallest circuits (not to mention the size limitation imposed on the circuit to be analyzed). Such a result will be completely useless especially for the designer. The reason behind this is simple: To design a circuit, it is easier to have five or six variables to control within some simplified constraints than to have a hundred variables most of which having complicated constraints and do not affect the circuit characteristics by any considerable amount. A strictly symbolic network analysis requires extremely high processing power and storage even for small circuits. Furthermore, the system matrix suffers often from ill-conditioning and singular values, which imposes an additional analysis difficulty against producing a result that can be produced much more efficiently by other methods of circuit analysis. Ill-conditioning of symbolic system matrices is further complicated by the fact that numerical values do not exit to check for such a problem during the formulation process

The compacted modified nodal analysis CMNA method (or the elementstamp method) is a very nice and easy way to illustrate the impact of each element on the matrix since it constitutes going through each branch of the circuit and adding its contribution to the system matrix in the appropriate positions. It represents an automatic technique to construct the nodal admittance matrix. This method consists of programming a lookup table for every element type in the network. This table has link-lists that will test which variables of the element are actually needed in the final compacted matrix and introduce the element in a way so as to eliminate the redundant variables.

1. Computer Representation of Symbolic Matrices Before introducing the CMNA method, a bit of background is needed on how to represent a symbolic system of equations in a computer program. In general, a symbolic variable or expression must be represented as a string data type or a pointer to a string data type that is stored in memory [1]. The first thing to do is to set a list, which will include the names of the symbolic variables that will be used later. The rule is that the instance of any symbolic variable that is not included in the list will cause the addition of the variable name to the list. If an identifier has not been assigned a value, then it stands for itself (or its name). In other words, each variable in our list is a pointer and it will be handled

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Element Stamp Algorithm for Matrix Formulation …

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accordingly. If it has no value to point to then it points to its name. Therefore, it is a symbol. Example: Consider the following assignment operation

Here the identifier p has been assigned the formula x2+4x+4. The identifier x has not been assigned a value; it is just a symbol, an unknown. The identifier p has been assigned a value. It is now like a programming variable. The value of p is x2+4x+4 The value of x on the other hand is x Because a variable can be assigned a value, which contains symbols, the issue of evaluation immediately arises. For example, consider the assignment Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

x=3 it should result in p=25 So the other rule of our list is that if A is pointing to B and B is pointing to C then A should use C in its evaluation. In general, handling the string by itself should be avoided as much as possible. The string should always stay in the memory and only pointers to it should be manipulated. This is very important since we might have many functions in our routine and certainly passing string parameters to such functions is quite a waste of time and memory. Mathematical formulae, e.g. things like sin(x+/2), and x3y2-2/3 are called expressions. They are made up of symbols, numbers, arithmetic operators and functions. Symbols are things like sin, x, y, Pi etc. Numbers include 12, 2/3, 2.1, etc. The arithmetic operators are + (addition),  (subtraction),  (multiplication), / (division), and ^ (exponentiation). Added to these are the brackets, which are used to separate the terms in the expression, to reset the priority of performing the operations, and to pass parameters to functions like in sin(x). Strictly speaking,

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formulae in the routine should be represented as expression trees or DAGs (Directed Acyclic Graphs) in computer jargon [1], [2]. When the routine is programmed to manipulate formulae, it is basically manipulating expression trees. Having all these rules stated, the routine for any of the basic operations is now easier to deal with. The arguments and cases that should be tested before executing any of the operations are The identity element I (e.g. the zero for addition) The negation element a* (e.g. negative arguments for addition) The invalid element O (e.g. the zero divisor for division) The null element (e.g. the zero for multiplication) The association and commutation between the basic operations and bracket handling (6) The separation and evaluation of numerical values as they arise during the operation

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(1) (2) (3) (4) (5)

The above list of if-conditions are not hard to program but they require a considerable amount of time to execute. The result is to make the routine much slower than what is required. The best way to deal with that is to compile the basic routines and use them as object-code functions whenever needed. Furthermore, some of the above tests can be removed (for example, if no division by zero is expected then the invalid element test can be removed). Following the programming of the basic symbolic operations, a data structure for symbolic polynomials needs to be defined. The data structure representing those polynomials would need to support addition, subtraction and multiplication. Finally a symbolic matrix representation needs to be included in the program. A symbolic matrix A can be described by the multiplication of a row operator P and a column operator Q with a diagonal matrix of symbols (1) P and Q are the matrix operators (or topological matrices) that indicate location of the matrix element value in the symbolic matrix A. Thus, if a matrix with n  n dimensions has b symbolic elements, then P and Q matrices are n  b and b  n operator matrices.

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Example: Consider the following fully symbolic matrix

This can be represented by

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One can immediately notice that the Y matrix is a diagonal matrix that can be represented by a simple array while both P and Q are sparse numerical matrices. One benefit of this representation is that linear operations on rows can be simply implemented on P while linear operations on columns can be implements on Q without altering the diagonal matrix. For example if one would like to add the first row of the matrix in the previous example with double the second row and put the result in place of the second row then these operations can be performed as follows

For most circuit analysis applications, system equations are rarely fully dense or fully symbolic. In that respect, some matrix elements may contain not only a single symbolic element value but constant values as well. These constants do not

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

affect the structures of matrices P and Q. In the strict sense the numerical value of the element should be kept in the diagonal matrix. However, it can also be moved to either P or Q and the number 1 can be added to the diagonal matrix. In fact even if the element values are complete polynomials the representation is still not altered. However, semi-symbolic sparse system matrices offer room for reduction in P and Q in non-strict representations. Example: Consider the following semi-symbolic matrix

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This can be represented as

It can also be reduced by reducing the 8 (element in row 1 column 2 on the original matrix). Simply delete column 2 from the P matrix and replace row 1 from the Q matrix by the addition of rows 1 and 2 then delete row 2

Reduction algorithms can be advised to help in reducing the size of P and/or Q and thereby save the memory space considerably [3].

In the same way symbolic matrix equations of the form

(2) Where x is the column vector of unknowns and b is a symbolic column vector, can be represented as (3)

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Where I is initially the identity matrix and q is a column vector. Hence only arrays of symbolic polynomial data structures need to be stored to represent diagonal matrices Y and B while numerical matrices P, Q, I and vector q can be manipulated to solve this system. While this representation of matrix equations manifests itself directly towards the algebraic solution, it does not represent the only approach to solve or represent the system of equations. An alternative topological approach based on graphical representation of the equations exists as will be shown later on. Solving equations similar in form to equation (2) can be done in many ways. Among which, parameter reduction method is one alternative when there is a need to find the transfer characteristics of a system. With this method, there is no need to solve the whole linear system just to find the ratio of two system variables. The system matrix is reduced successively before any attempt of evaluation is made. It should be clear that such a reduction does not reduce the amount of the required operations. But the key point here is that the reduction helps in reducing the matrix size for the purpose of storing and thus reducing the number of memory excess times. It also increases the speed of passing parameters to functions by reducing the sizes of their arguments. In this sense, the reduction can be carried out during the formulation of the system matrix and in this way the memory requirement is highly reduced. This provides a way to handle very large system matrices. Due to its importance in later on discussion, a reduction method will now be demonstrated (namely Kron‟s reduction) of a row (or set of rows) and its associated column (or their associated columns) that are collectively called a matrix axis [4]. Consider the following matrix equation:

(4) In which A1, A2, A3 and A4 can be thought of as matrices or single coefficients and X1, X2, B1, and B2 are vectors or single variables respectively. Equation (4) in expanded form is (5)

(6) Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad Rewriting equation (6) gives

Pre-multiplication by

yields (7)

On substitution of X2 into equation (5) we get

Rearranging and collecting terms gives (8)

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or (9) From which X2 can still be found from equation (7). Hence, the dimension of the matrix that needs to be inverted is reduced by eliminating the unknown X2. Thus, the axes corresponding to A2 and A3 are eliminated. The sub-matrix was modified to reflect the system solution corresponding to the unknown

.

This is valid as long as is not singular. The above reduction is very useful in large network analysis. The Kron‟s reduction is greatly simplified when a single axis is being eliminated (i.e. A4 has a single element). Repeating the elimination of a single axis is superior to the elimination of many axes in a single reduction as is verified in [5]. In the case of a single axis reduction, becomes 1/a44. The modification of the elements not in the axis being eliminated can be carried out element-by-element rather than by application of equation (8) (hence no matrix multiplication is required). All elements are modified in-place and no additional computer memory is required for the storage of the minor . It can be easily verified that the elimination of axis k is simply [4]

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(10) The reduction can be carried out recursively in a very efficient way. Further memory efficiency can be gained if the reduction is done in place without preserving additional space for sub-matrices. The algorithm would go something like that:

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CalcReducedMatrix (input Matrix “e” and requested output matrix size n, output Matrix) { Check for invalid conditions (not square, zero pivotal element etc) If number of rows = 1 then return only element, e[0][0] Initialize a pivotal element Initialize return value to empty matrix Initialize current matrix size m While m is smaller than requested output size { For each row i (i smaller than m) And for each column (j smaller than m) {Replace e[i][j] with e[i][j]-e[i][m]*e[m][j]/e[m][m] } Return CalcReducedMatrix of matrix e[m-1][m-1] } }

Notice this algorithm will work regardless of whether the matrix is composed of numbers or symbolic polynomials. For it to function with polynomials the data structure representing them would need to support the basic mathematical operations as said before. Solving the linear system may incorporate additional steps for the right-hand side vector and for pivoting (in case there is a zero pivot element) for which a separate evaluation function needs to be written. In practice the evaluation does not need to be complicated. Since only a zero pivotal element is forbidden there is no need to build a detailed simplification algorithm. An evaluation of the pivot element can be done by giving random arbitrary values to the symbols so if there are some cancellations in the pivotal element expression resulting in setting its value to zero, it will immediately show up with the random numerical values given to the symbols. In such a case swapping the rows of the matrix can generally solve the problem easily. Luckily if the matrix is in the form

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of equation (3), the row swapping can be implemented easily on the P and I matrices without disturbing the symbolic string vectors. One drawback to the algorithm is the need to successively divide by a matrix element which is not easily implemented in the form of equation (3). To overcome that, scaling of the unknown variables can be used to convert the divisions into multiplications as shown in the example below. Example: In the following matrix equation, we would like to find the ratio (transfer characteristic) of axis 1 to axis 2. That is,

(11)

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Solution: Partitioning and eliminating the pivotal element a33, using equation (10), we get

However, before eliminating row 3 and column 3 of the matrix it is worth noting the high number of divisions and simplifications needed after just one setp of the solution. This can be overcome simply by scaling the unknow variable in equation (11) by the pivotal element a33 (12) Next, the new variable with unity pivotal element

can be eliminated by applying equation (10)

and finally scaling back the unknown variable x3 can be done to get Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

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Now, this form of the reduction does not require any divisions and does not disturb the original storage arrangement of the symbolic matrix (yet the test for a zero pivotal element is still needed as a zero pivot would turn both sides of the equation to zero). Thus the structure of equation (3) is kept as it is without the need to implement sophisticated division/simplification algorithms. Hence equation (10) can now be rewritten as (13) Now it is very easy to shift focus to the 22 sub-matrix generated

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or

Solving this matrix equation gives

The required ratio can be found as

This follows from the well-known butterfly relation [6].

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2. Topological (Graphical) Representation of Matrices Topological methods of solving linear systems of equations relate directly to the study of electronic circuits. Study of these methods was initiated by Kirchhoff [7] at the end of the 19th century and intensified in the sixties and seventies of the 20th century [8]-[15], to a large degree due to the development of computer technology and related devices requiring advanced methods of electronic circuit analysis and design. Concurrently, algebraic methods that represent network topology and can be used for its analysis were developed, most notably by Wang [16]-[19] and Bellert [20]-[24]. The most attractive feature of topological methods that was apparent since the early stage of their development was their ability to obtain transfer functions directly from the circuit netlist or from its graph description simply by inspection. Since then graph based methods were generalized to solve any set of linear equations associated with electrical circuits using signal flow graphs (Coates [25],[26] and Mason‟s [27], [28] graphs), linear graphs (current-voltage [29], [30] and nullator-norator [14] , [31] graphs), and directed graphs (unistor [32], [33] and dispersor [33], [34] graphs) to describe the matrix structure. Specialized analysis methods were developed for each of these graph representations and recently there has been an effort on unifying graphical methods that would handle these various representations and reuse results from one form of graph representation to another [35]. As indicated above, three major types of graph representations are used to describe the system matrix in circuit topology. These three major types and some of their better known subtypes are as follows: 1. Flow graphs a. Coates‟ graph b. Mason‟s graph 2. Directed graphs a. Unistor graph b. Dispersor graph 3. Conjugated graphs a. Current-voltage graph b. Nullator-norator graph These graphs represent both the interconnection structure of an electronic circuit and its element values. Since topological analysis and diagnosis is Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

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Element Stamp Algorithm for Matrix Formulation …

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performed on a linear system, it is assumed that the circuit elements represented by the graph are linearized around their DC operating points. Thus, in general, graphs represent circuit interconnected structures and associated linearized element values. Computer representation of the graph is simple. A directed graph G=(V,E) consists of a finite, nonempty set of vertices V and a set of edges E that are ordered pairs ei=(vi,vi') of vertices; vi is called the tail and vi' is called the head of edge ei. Each edge eiE has a weight wi associated with it. If the order of the pairs is irrelevant then the graph is called undirected. In addition, the following notation will be adopted: if all the associated weights are unity then the graph will be called oriented, while if both the weights and the order are irrelevant then it will be called associated [36]. Each edge of a graph may describe one, two, or four elements of the coefficient matrix depending on whether it is in a signal-flow graph, directed graph or pair of conjugated graphs. Flow graphs represent each element of the coefficient matrix as an independent edge of the graph, resulting in relatively complex graphs that contain as many edges as the number of nonzero entries in the coefficient matrix. Directed graphs may represent two elements of the coefficient matrix, either in a single row (dispersor graph) or a single column (unistor graph) as an independent edge of the graph. Finally, the conjugated graphs represent four elements of the coefficient matrix as an independent edge of the graph, resulting in graphs that contain the minimum number of edges. The level of graph complexity reflects directly onto its simplification through Graph Decomposition. Graph decomposition is used in many applications dealing with large systems like linear programming [37], [38], the shortest path problem [39]-[41], information encoding [37], synthesis of VLSI circuits [42], partition of sparse matrices [6], [43], job shop scheduling [44], gene assembly [45], software synthesis [46], etc. Thus very well developed algorithms and packages exist to handle graph decomposition. The aim of graph decomposition is to improve the algorithmic performance of problems represented by a system graph. Network decomposition is used in analysis of computer and communication networks [47][52]. Decomposition plays an important role in stability analysis of large systems [53]-[55] or layout compaction in very large scale integrated (VLSI) circuits [56]. In circuit analysis one can further distinguish diakoptics [57]-[59], generalized hybrid analysis [60], and topological analysis with nodal decomposition [61], [62]. Detailed discussion of the different graphical representations and their decomposition variations is beyond the scope of this chapter. However, we will

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comment on how to generate such graphs with minimum efforts and relate them easily to the algebraic approach during the formulation of the system matrix equation for any circuit.

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3. Basic Network Elements and Equations (Distributed vs. Lumped) The electrical networks of interest to engineers consist of an interconnection of some components. For a two-terminal component, which is called a branch, two variables are of primary interest: the voltage across the branch and the current through the branch. Due to the physical construction of the components, there is a definite voltage-current relationship characterizing each branch. These relationships are collectively called the constitutive equations (CE) [6]. For example, a resistance is characterized by the conventional Ohm‟s law, while a capacitance and an inductance are characterized by differential equations in the time-domain. The relationship may involve also variables of other branches, leading to what are called “coupled branches”. In such a case, it is convenient to use a two-port representation of each one of the two-coupled branches. Common symbolic analysis literature focuses on such simple networks. Yet, current needs for symbolic analysis have widened to include fault diagnosis, high frequency network analysis and very fast switching VLSI. Many network elements in such networks can be defined depending on the type of the network and the type of analysis. Generally speaking, different parts of those networks can be lumped, distributed, or mixed. When a number of branches are connected together, we have a lumped network. A lumped network is characterized by its small dimensions compared to the wavelengths of the signals of interest. On the other hand, when the element dimensions become comparable to the wavelengths of the electrical signals involved in the network we will have a distributed network. The latter is distinguished by the traveling waves propagating through its components. Any lumped network obeys three basic laws: Kirchhoff‟s current law (KCL), Kirchhoff‟s voltage law (KVL), and a set of constitutive equations (CE) defined for each branch. The constitutive equations are intrinsic physical properties, and are independent of how the branches are connected together. On the other hand, KCL and KVL are linear algebraic constraints on branch voltages and currents, arising from the interconnection of the branches, and are independent of the branch characteristics. Hence they are topological constraints. Even though many of the implementation techniques proposed here are imposed with linear networks

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in mind, it should be pointed out that KCL and KVL are valid for any lumped network, whether the network is linear or nonlinear, time-invariant or time varying. The basic elements in a lumped network are linear, lumped and time-invariant resistors, capacitors as shown in Figure 1. No matter how basic the consecutive equations of these elements may seem, they impose constraints that have to be satisfied by the solution variables. In addition, KCL and KVL impose topological constraints that also have to be satisfied simultaneously by the same solution variables. Fortunately, transforming all the CE into the Laplace domain will yield a set of linear (or linearized) equations that can be solved easily. Speaking strictly, in any electrical network involving time-varying signals (whether lumped or distributed), all the variables must satisfy the famous Maxwell‟s equations (ME). The set of Maxwell‟s equations form the basis of our topological constraints. In addition, the solution variables have to fulfill some boundary conditions (BC) that are specific to each element. The equations constitute a complicated partial differential (or integral) set that has a geometrydependent form. The solution of this set cannot be carried out symbolically for any set of elements and sound numerical techniques seem to be the only possible way in most of the problems. However, it is not possible to solve the electromagnetic integral or differential equations either conveniently or rigorously in regions containing or bounded by geometrically complicated metal or dielectric structures, and the basic analytical discipline of electrical engineering curricula has from the beginning been that of lumped-element circuit analysis. This employs the previously mentioned idealized concepts of two-terminal resistances, inductances and capacitances to represent the localized functions of energy dissipation, magnetic field energy storage, and electric field energy storage, respectively. Voltages and currents, which are related by integral or differential expressions to electric and magnetic fields, are the primary electrical variables. Such an approximation is an adequate substitute for the electromagnetic theory when the occurrences of the three functions mentioned above can be separately identified. This happens when the dimensions of a circuit are sufficiently small that no appreciable change will occur in the voltage or current at any point during the time electromagnetic waves would require propagating through the entire circuit. The size criterion is obviously a function of frequency. At the power line frequency of 50 Hertz, the methods of lumped element circuit analysis are applicable with high accuracy to circuits several kilometers long, while at microwave gigahertz frequencies the same methods may be useless for analyzing a circuit less than a few centimeters across (e.g. monolithic VLSI). In such a case,

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

the set of ME together with the BC have to be solved numerically. The reduction of these equations into simple KCL and KVL relations is not so simple anymore. More importantly, one will not be dealing with currents and voltages any further, but rather with fields. This in general poses a problem against the high frequency symbolic circuit analysis both from the modeling and from the analysis side of views. As an example, the high frequency models of a simple thin-film resistor used in microwave circuit applications are shown in Figure 2 where the complicated frequency-conditioned situations are apparent. Element

Admittance Description

i(t) +

R

i(t)

I=VG

𝐼𝑜 𝑠

i(t) + Vo 

I

+

1 𝑌= 𝑠L

+ 𝑍 = 𝑠L

V

V

– 𝑑𝑖(𝑡) 𝑣 𝑡 =𝐿 𝑑𝑡 1 𝐿

V=IR

I

v(t)

+ V –

R

V –

+

L

𝑖 𝑡 = 𝐼𝑜 +

I +

G

– v(t) i(t)=v(t)G v(t)=i(t)R

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Impedance Description

I

–

𝑡

𝐼=

𝑣 𝑡 𝑑𝑡 0

+

v(t) – 𝑑𝑣(𝑡) 𝑖 𝑡 =𝐶 𝑑𝑡 1 𝑡 𝑣 𝑡 = 𝑉𝑜 + 𝑖 𝑡 𝑑𝑡 𝐶 0

𝐼𝑜 𝑉 + 𝑠 𝑠𝐿

LIo –

𝑉 = 𝑠𝐿𝐼 − 𝐿𝐼𝑜

I CVo

 +

+

Y=sC

V 

𝐼 = 𝑠𝐶𝑉 − 𝐶𝑉𝑜

I

1 𝑍= 𝑠𝐶 + 

 𝑉=

𝑉𝑜 𝐼 + 𝑠 𝑠𝐶

𝐼 𝑠𝐶 

+

𝑉𝑜 𝑠

+

V 

Figure 1. Lumped network elements in time and Laplace domains; Io and Vo represent the initial inductor current and capacitor voltage respectively

In addition to the techniques of electromagnetic theory and of lumped element circuit analysis, electrical engineers make use of a third analytical procedure for electrical problems, which combines features that is separately characteristic of each of the other two methods. It extends the application of the concepts of the lumped-constant theory to circuits which can be indefinitely long

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in one dimension, but which must be restricted and uniform in the other dimensions throughout their length. This analysis discloses propagating waves of the voltage and current variables, analogous to the waves of electric and magnetic fields that are the solutions of Maxwell‟s equations. The method is known as distributed circuit analysis. In this method, each device is considered as being the interconnection of an infinite number of lumped elements. The final answer in this case will be the limiting solution as the number of lumped elements grows indefinitely. This method represents the only reasonable means of analyzing high frequency and microwave circuits symbolically and it can be used at different levels of accuracy [63]. In symbolic circuit analysis (whether distributed or lumped), one might attempt substituting every component of the circuit by its model. In the distributed circuit case, every piece of a wire is considered as a transmission line and every device is represented by a two-port high frequency model. In the lumped circuit case, every active element (transistor, op-amp, etc) is an interconnected circuit of many elements. Such an analysis is based on a strictly network-modeling point of view and it appears highly descriptive of the circuit behavior. However, a fully detailed symbolic network analysis is not actually of any interest to engineers. This is mainly due to two inherent drawbacks in such an analysis: 1. As this analysis introduces many additional elements and variables to the original circuit, the resultant symbolic expression will be extremely large and beyond any human interpretation or comprehension even for the smallest circuits (not to mention the size limitation imposed on the circuit to be analyzed). Such a result will be completely useless especially for the designer. The reason behind this is simple: To design a circuit, it is easier to have five or six variables to control within some simplified constraints than to have a hundred variables most of which having complicated constraints and do not affect the circuit characteristics by any considerable amount. 2 A fully detailed symbolic network analysis requires extremely high processing power and storage even for small circuits. Furthermore, the system matrix suffers often from ill-conditioning and singular values, which imposes an additional analysis difficulty against producing a result that can be produced much more efficiently by other methods of circuit analysis.

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad L

L

R

R

C

R

|v/i| 1/C f < 10 kHz

L

f < 1 GHz

f < 100 GHz R

R

10 kHz

1 GHz

100 GHz

f

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Figure 2. High frequency models of a simple thin-film resistor

The method of mixed-circuit analysis can be considered as the ultimate solution to these difficulties. It is the best available method that describes the characteristics of a circuit (lumped or distributed) in the simplest form. In this technique, the passive lumped element are left as they are, the active lumped elements are replaced by macro-models (or macro-stamps) while those elements that are known to have non-negligible distributed effects are replaced by their two-port equivalents. In this way, the features of the detailed analysis are preserved within a method that overcomes the drawbacks mentioned above.

4. Nodal Analysis Techniques For a computer implementation of the mixed-circuit analysis one needs first an algorithm that deals efficiently with lumped circuit elements. This algorithm can then be modified to incorporate the presence of distributed elements in a proper manner by standard known methods of network analysis (namely the sparameter techniques [64]). The efficiency of the original algorithm will determine the efficiency of all subsequent modifications to it. Therefore, the algorithmic efficiency will be the prime concern during the development of the computer implementation.

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The technique of nodal analysis is discussed in most texts on circuit theory and in many versions, but for the present purposes, another version will yet be described that has substantial benefits over existing ones. Despite its popularity, many concepts of the method shall be derived for the sake of completeness as well as to emphasize the important features of the technique. Nodal analysis is based on the application of Kirchhoff‟s current law to all the nodes in a circuit; each node (or unique junction of components) gives rise to a current balance equation. The set of nodal equations may be assembled to give a matrix description of the network, known as the nodal admittance matrix, where each matrix element has the dimensions of admittance. Solving all the nodal equations simultaneously yields the voltage at each node. The first problem of implementing the nodal approach in circuit analysis is the formulation of the nodal equations through the nodal admittance matrix in the simplest possible way. The subsequent manipulations, which yields the results of the analysis, then corresponds to nothing more than the solution of a set of simultaneous linear equations using standard matrix techniques.

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4.1. Formulation of the Nodal Admittance Matrix The simplest way to approach the formulation of the nodal equations is to consider the derivation of one such equation at just one node of a passive network [65]. To this end, consider Figure 3, which shows a general passive network with node j isolated from the remainder of the n-node network. To maintain generality, it is assumed that node j is connected directly to every one of the remaining n-1 nodes through an admittance Yij. If there is no such connection in a specific circuit, then clearly the corresponding admittance may be set to zero. It is also assumed that incident on node j there is an external current Ij emanating from some external source, which again may be zero in a specific case. Currents ij1, through ijn are also assigned to each admittance respectively. Since all the currents (Ij and ij1 to ijn) are at present defined as algebraic quantities, their assumed directions are quite arbitrary, since they may have either positive or negative signs. Finally, it should be noted that, although not shown explicitly in Figure 3, all the other nodes in the network might be considered connected to each other through further admittances, but for the present purpose the precise nature of the admittances involved is immaterial. Applying Kirchhoff‟s current law to node j yields

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad (14)

i.e.

(15)

Now applying Ohm‟s law to each of the admittances Yjk, (k=1…n, kj) one sees that , and in general (16)

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n Yjn

ijn

Ij

j ij1

ij3 Yj3 3

Yj1 ij2

1

Yj2

2

Figure 3. A typical node in a passive n-node network.

Substituting equation (16) into equation (15),

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which may be rewritten as

(17)

The quantity

is known as the self-admittance of the node j and

may be denoted yjj. If the quantities Yjk are additionally denoted by yjk, equation (17) may be further rewritten as

(18)

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By assembling equations derived for all the nodes, the set of nodal equations of the form given in equation (18) can be expressed as a single matrix equation:

(19a)

i.e. (19b) Where the matrix Yi is known as the indefinite nodal admittance matrix [6], [65]. The above development leads to a very simple method for the formulation of the indefinite nodal admittance matrix of passive networks. The element entries for the matrix are found as follows:  

Diagonal elements: yii=(the sum of all admittances connected to node i), (i = 1… n) Off-diagonal elements: yij=(minus the sum of all admittances connected between node i and node j), (i,j = 1… n, ij)

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

The formulation of the indefinite nodal admittance matrix is thus a trivial task, given some description of the network. Several properties of this matrix can be exploited to provide some efficiency. For example, the symmetric nature of the passive nodal admittance matrix is clearly seen by writing the expressions for yij and yji explicitly. This property may be exploited in both the formulation and possibly the storage of the matrix within the computer. The above development has served to introduce a simple, easily programmed approach to the formulation of the nodal equations for linear passive networks incorporating two-terminal elements. Continuing the simple approach to the formulation problem, one may make the important observation that most practically occurring active devices may be characterized by some two-port description, and where they exist, they can be provided as data in an extended form of branch node listing (see for example [6] for tables of two-port admittance matrices. In some cases, the two-port description of an element may exist as a circuit model rather than a set of numerical parameters. The precise nature of such circuit models for common active devices is left until later in this chapter. However, such models can be analyzed once and their nodal admittance matrix added wherever they appear as part of a big system matrix as will be shown. Such an addition, of course, should be made to the proper elements of the system matrix corresponding to the position of the active element and this offers a big time saving when analyzing very large circuits. Finally, before proceeding with the active formulation, it can be noted that many passive networks are also characterized by two-port short circuit admittance parameters, and the treatment described below is equally applicable to such networks. With these points in mind, the formulation can proceed by considering that an active network may be represented as a passive network into which (active) twoport devices are embedded. Therefore, attention is turned to the general two-port network shown in Figure 4. The two-port admittance relationship is defined as (20) where the upper case (e.g. Y12) is used to avoid confusion with the elements of the nodal admittance matrix. Now equation (20) relates the port variables I1, I2, V1 and V2. If one now considers the two-port to be defined with terminal node variables of voltage and current as shown in Figure 5, then it can be seen, with reference to Figure 4:

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(21) where a, b, c, d represent the node numbers to which the two-port is connected in the network.

I1

I2 Port

V1

1 I1

Port V2

2 I2

Figure 4. A general two-port network.

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I´a

I´c

Va

Vc

Vb

Vd

I´b

I´d

Figure 5. Definition of terminal node variables of a two-port network.

If equation (20) is now combined with equations (21), it is readily shown that

(22)

Equation (22) represents the four-terminal indefinite admittance matrix relationship for the network of Figure 5. Implicit in this equation are the constraints and . These constraints are imposed by the two-port convention for the current flow shown in Figure 4. In some cases (for example the

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

transistor), where two of the terminals are common, the two-port can be represented as shown in Figure 6(a), which has the terminal equivalent shown in Figure 6(b). In this case, the terminal node constraint Vc = Vd reduces equation (22) to

(23) At this point, an indefinite admittance matrix description of the two-port has been obtained, and this must now be incorporated into the nodal equations describing the network. As was remarked earlier, the nodal equations for the part of the network containing passive two-terminal components may be obtained first, and these must now be modified to include the effects of the two-port.

I1

I2 Port 1

V1

Port 2

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I1

I´a V2

I´b Vb

Va

I2

Vc I´c

(a)

(b)

Figure 6. A general three‐terminal network.

Thus, referring to equation (18) the nodal equation pertaining to node a prior to the inclusion of the two-port under consideration may be written (24a) Embedding the two-port within the remainder of the network will upset this current balance, and noting the relevant equation in equation (23), it is seen that a current must be added to the right hand side of equation (24a) to express Kirchhoff‟s current law at this node. Thus (24b)

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Equation (24) shows that the entries yaa, yab, yac and yad in the original indefinite admittance matrix will be modified according to

and consideration of the remainder of the node currents indicates that similar modifications must be made to all the other elements yij (i,j = a, b, c, d). Now, if equation (22) and equation (23) are rewritten as

(25)

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and

(26) then the embedding of the two-port into the formulation for the remainder of the network may be summarized as the element by element addition of the elements of the matrix in equation (25) or (26) to the corresponding elements yij in the indefinite nodal admittance matrix, and this process would be repeated for all twoports within the network. It is possible now to formulate the indefinite nodal admittance matrix for a large range of practically occurring networks. The process starts normally for the passive elements as was done before. Then, the four-terminal nodal admittance matrix for each active device can be incorporated by adding the elements in the corresponding positions in the passive matrix. A word of warning is appropriate here. It was noted earlier that the development of the four-terminal indefinite admittance matrix from the two-port equations carried the implicit constraints and . The simple formulation technique that has been discussed will not work, however, when the circuit being incorporated into the

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

matrix description does not satisfy these constraints, and care should be taken to ensure that this is not the case. Luckily, such cases occur infrequently. Furthermore, a little consideration shows that when two of the two-port terminals are common, as in Figure 6, the case does not occur at all in practical circuits [65]. With this in mind, larger models for bigger elements can be added to the system matrix provided they have two-port (or multi-port) admittance matrices forming macro-models which again need to satisfy some constraints to maintain the equations balance. By trying some practical examples, it will be noted that the symmetry of the nodal admittance matrix, which is exhibited by passive networks, has been destroyed by the inclusion of the active device. Two other important observations may be made with regard to the indefinite nodal admittance matrix of all networks. Firstly, all the elements in any particular row sum to zero. This relates to the practical observation that if all the node voltages in a network were made equal, no currents would flow in the circuit, and this may be confirmed by setting all the voltages equal in each of the equations represented by equation (19). Secondly, all the elements in each column also sum to zero. This result is a direct consequence of Kirchhoff‟s current law, since all the currents entering a network must algebraically sum to zero. Again, reference to Figure 3 shows that if one sums all the currents I1 to In by adding all the equations represented therein, the stated result is obtained. An alternative way to express the influence of Kirchhoff‟s current law on the network is to say that the set of nodal equations based on all nodes in the network will be linearly dependent. This implies that equation (19b) may not be solved for the voltage vector V. since the matrix Yi will be singular. This surprising result may be rectified by noting that in the initial considerations, the elements of the node voltages vector V were not defined with respect to any specific internal reference. Practically, node voltages would be measured between each node and a reference node usually designated „earth‟ or „ground‟. This ground node is usually assigned a potential of zero volts. Thus, if an n-node network is considered, and node n is designated as ground, equation (19a) reduces to

(27)

Equation (27) represents n current equations in n1 unknown voltages. The problem is thus over specified, and one current equation may be discarded. It is Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

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Element Stamp Algorithm for Matrix Formulation …

most convenient to select the equation corresponding to node n, the ground node in this case, and so, finally, equation (27) may be reduced to

(28)

i.e. (29) where Y is known as the definite nodal admittance matrix. It should be noted that the vectors I and V in equation (29) are now reduced from n-vectors to (n1)vectors as a result of the above remarks. R

R

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V

+ 

V

(a)

+ 

R

I

(b)

V R

R

(c)

Figure 7. Application of Norton‟s theorem to a general voltage source

The definite admittance matrix Y of equation (28) may be simply obtained from Yi by deleting the row and column corresponding to the ground node, and, as will be shown, subsequent manipulation through equation (29) will then yield the unknown vector V and complete the analysis. One difficulty of the aforementioned analysis procedure is that of incorporating voltage sources. This is a constraint on unknown vector that has to be satisfied during the formulation. The most straightforward way of dealing with voltage sources is by using Norton‟s theorem to convert the voltage source to a current source. In Figure 7(a), an ideal voltage source is shown. In Figure 7(b), two resistors are introduced in series with the source. These resistors are of opposite signs but equal in magnitude so that they do not alter the operation of the circuit. Finally, in 7(c) Norton‟s theorem has been used to transfer the circuit to a current source with shunt resistance. This equivalent circuit can be incorporated into the network and

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

the difficulty of formulating the equations vanishes. An extra node has also been added but it is a reasonable price to pay for the ease of analysis. The resistance R may be chosen arbitrarily to satisfy any computational requirements so it is common to set its value to 1. Thus voltage sources of all kinds, even though they depend on another branch variable in a nonlinear fashion, may be coped with using the nodal approach.

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4.2. Tableau and Compacted Modified Nodal Analysis (CMNA) Methods The formulation methods introduced in the previous section are quite efficient and have been used successfully in many applications, but they cannot handle all ideal elements (especially those which have no two-port short circuit admittance parameters). In addition nodal analysis will only provide the nodal voltages. Thus if currents or transfer functions are required, back substitution is needed to get the required currents or transfer functions. Finally the generated system matrix may be ill conditioned while there is a trivial solution to the system. Such cases occur when the circuit involves loops of voltage sources and/or ideal current sources in series. Thus a modification to the method is needed to incorporate additional variables in the vector of unknowns that will eliminate the need for back substitution and provide sufficient conditions in the system matrix to avoid having it turn ill-conditioned when there is a trivial solution. To avoid the restrictions, general formulation methods are introduced in this section. The formulations discussed before can all be derived from a general formulation called the tableau. In this formulation, all equations describing the network are collected into one large matrix equation, involving the KVL, KCL, and the constitutive equations, CE. All branch currents, all branch voltages and all nodal voltages are retained as unknown variables of the problem. Thus, the formulation is most general (everything is available after the solution) but leads to large system matrices. We will first comment on the most convenient type of tableau. For initial considerations let the network have b branches; n+1 nodes; R, G, L, C elements; and sources. The topological properties of such a network can be expressed by means of the incidence matrix A. This is a matrix representation of the KCL for the oriented graph of the network. As discussed in section 2 an oriented graph of a network is a directed graph whose weights are all unity. For example, consider the simple network shown in Figure 8 with its oriented graph representation.

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Element Stamp Algorithm for Matrix Formulation …

R6 C4 + 2 1

+ J1

6



L5 3

 

+ R2

+



1

4

2

 C3

+

5

3

2 3

1 0

0

Figure 8. A typicall example of network and its oriented graph representation.

Let us write the KCL equations with the edge orientations as indicated. A current flowing away from a node will be considered as positive. Then

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This can be written in matrix form: (30) where A is the incidence matrix and, for this example,

It has n rows and b columns, n being the number of ungrounded nodes and b the number of edges in the graph. It can be shown that equation (30) is always valid [6]. Furthermore, it can be written in a generalized form as

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(31)

30

Fawzi M. Al-Naima and Bessam Z. Al-Jewad

where Ib represents the branch currents. It can also be shown that the branch voltages Vb and the node voltages Vn are related by (32) This is another form of stating KVL in the circuit. Finally, the general representation describing all possible constitutive equations CE has the following form

where Y1 and Z2 represent admittances and impedances, respectively; K1 and K2 contain dimensionless constants; and Wb1, and Wb2 include the independent current and voltage sources, as well as the influence of initial conditions on capacitors and inductors. For notational compactness, the following form will be used:

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(33) In all subsequent formulations, it is highly advisable to enter capacitors in admittance form and inductors in impedance form to keep the variable s in the numerator. Since the Laplace transform variable s is equivalent to the differentiation operator, a set of algebraic differential equations will be obtained when performing time domain analysis. Table 1 indicates the choices of Yb, Zb, and Wb for various two-terminal elements. Equations (31)-(33) can be collected, for instance, in the following sequence:

and put into one matrix equation

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Element Stamp Algorithm for Matrix Formulation …

31

Or, in general, (35) where T, X and W represent the combined system matrix, unknowns vector and excitation. The arrangement indicated in equation (34) has square sub-matrices on the diagonal. In this tableau formulation, the element numbering can be completely arbitrary. For computer implementation, the SPICE-package input format is usually adopted in numbering the elements. Table 1. The choices of Yb, Zb, and Wb for various two-terminal elements Element

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Resistor Conductor Capacitor Inductor Voltage source Current source

Constitutive Equation (CE) VbRbIb=0 GbVbIb=0 sCbVbIb=CbV0 VbsLbIb=LbI0 Vb=Eb Ib=Jb

Value of Yb 1 Gb sCb 1 1 0

Value of Zb Rb 1 1 sLb 0 1

Value of Wb 0 0 CbV0 LbI0 Eb Jb

Until now, we have been discussing the tableau for two-terminal elements only. In order to generalize the tableau to any element the two-port element representations have to be considered. In such a representation, each port of a two-port network is represented by a constitutive equation and two constitutive equations must therefore be given. A lookup table can thus be programmed to identify each element in the circuit and return its constitutive equation(s). To this end, a summary of the most important ideal elements is given in Table 2. The tableau formulation discussed so far has mainly theoretical importance. Many ideal two-ports introduce redundant variables. For instance, the input currents of the voltage-controlled voltage source (VCVS) and the voltagecontrolled current source (VCCS), or the input branch voltages of the currentcontrolled voltage source (CCVS) and the current-controlled current source (CCCS) are known to be zero. However, they are kept in this formulation as variables. The tableau formulation has yet another problem: the resulting matrices are quite large and sparse matrix solvers are needed. Unfortunately, the structure of the matrix is such that coding these routines is complicated. A re-structuring algorithm must be implemented before the linear solution techniques can be of any use to us.

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Table 2. Constitutive equations of ideal elements for the tableau formulation

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Table 2 Constitutive equations of ideal elements for the tableau formulation

V1

V2

V1

V2

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Table 2. (Continued)

A major development step to the tableau method is to eliminate all redundant variables. These can be eliminated by the use of a pivotal condensation procedure (as is explained later) to produce a compacted nodal admittance matrix that can be inverted easily. However, such elimination would take quite a long time especially for symbolic matrices, not to mention the huge storage requirements for the sparse symbolic matrices. A more practical approach is to program a lookup table for every element in the network. This table has conditioned link-lists that will test which variables of the element are actually needed in the final compacted matrix and introduce the element in a way so as to eliminate the redundant variables during the formulation. This method is called the compacted modified nodal analysis CMNA (or the element-stamp method [66]) and it represents an automatic technique to construct the nodal admittance matrix. The compacted modified nodal analysis method is a very nice and easy way to illustrate the impact of each element on the matrix since it constitutes going through each branch of the circuit and adding its contribution to the system matrix in the appropriate positions. To understand the method, the following elementary examples are introduced. However, programming the method requires a full lookup table with explicit statement of the conditions required to eliminate any of the redundant variables.

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad Example: Consider the general admittance y shown in Figure 9. i y

iy

(ViVj)y= iy

j

Figure 9. A general admittance.

Assuming that the Y matrix is already generated for the other branches, the impact of this admittance (following the tableau formulation) on the system matrix is to add an additional row and column corresponding to the new system variable iy as shown below

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(36)

Now, if iy is not a solution variable then it has to be eliminated from the system matrix to generate a new matrix that is compacted (condensed) with respect to the axis iy. Carrying out Kron‟s reduction described in equation (10) one gets

(37) Equations (36) and (37) are the conditioned stamps for the admittance shown in Figure 9 and they can be programmed in a lookup table easily. However, although equation (37) is the simplest, it is not the only possible elimination that can be carried out on the system matrix of equation (36). Connecting an admittance between node i and node j constrains the current through the branch i-j and thus affecting three system equations at the same time. Thus, if iy is to be eliminated using an equation other than the iy equation (say the jth equation) then

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the elimination can be carried out using Kron‟s reduction on the following permutation of equation (36)

(38)

The resulting system matrix is then

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(39) which is just a linear transformation of equation (37). Obviously, the stamp of equation (37) is much easier to implement than the procedure resulting in equations (39). Yet, this simple example shows how the element stamps and stamping procedures can be derived from Kron‟s reduction depending on the variables one wants to keep as solution variables without actually performing the reduction. Stamping procedures have similar properties and some of them were used in the past (e.g. Nathan‟s method to analyze constrained op-amp networks which is really Kron‟s reduction in disguise [11]). However, their practical advantage occurs only when they can be programmed easily. Therefore, the art of deriving a stamping procedure lies in its programming suitability. Thus, all the subsequent derivations of stamping procedures will be carried out keeping this in mind Example: Consider the independent voltage source E shown in Figure 10 Again, assuming that the Y matrix is already generated for the other branches, the impact of this voltage source (following the tableau formulation) on the system matrix is to add an additional row and column corresponding to the new system variable iE as shown below

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

i E

+ 

iE

ViVj=E

j

Figure 10. A general independent voltage source.

Now, if iE is not a solution variable then it has to be eliminated from the system matrix. However, the axis iE has a zero pivotal element which makes it impossible to eliminate both the iE row and column. Carrying out Kron‟s reduction on the jth equation, the following stamping procedure is obtained:  

Add row j to row i (including the right-hand side element) and put the result in row i, Replace row j by the elements of row iE given in equation (40).

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This results in the following system matrix

(41) Other elimination combinations can also be considered in this respect. Connecting a voltage source between node i and node j constrains the voltage on both nodes so that the voltage of one node will be a linear function of the voltage on the other node. Furthermore, fixing the voltage difference between two nodes constrains the current as well. Therefore, a reduction of one of the node voltages is also possible. Eliminating axis Vj on equation (40) results in the following stamping procedure:   

Add column j to column i and put the result in column i, Add column j multiplied by E to the right-hand side, Replace column j by the elements of column iE given in equation (40).

This results in the following system matrix Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

Element Stamp Algorithm for Matrix Formulation …

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(42) Finally, two axes can be eliminated together resulting in a new stamping procedure. Eliminating both the Vj axis and the iE axis on equation (40) results in the following stamping procedure:    

Add row j to row i and put the result in row i, Add column j to column i and put the result in column i, Add column j multiplied by E to the right-hand side, Remove the jth row and column.

This results in the following system matrix

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(43) It must be emphasized that the system matrix shown in equation (43) is not a 1x1 matrix, but rather a big matrix of which only the (i-i) element is shown. It is evident from the example that the number of the stamps and stamping procedures for one element can grow quite large depending on the possible elimination combinations. Obviously, this results in many if-conditions and thus a long processing time. Yet, the practical implementation shows that the time required to eliminate the redundant variables in a symbolic sparse tableau matrix is greater than the time required to go through all the if-conditions by about an order of magnitude. This verifies the efficiency of this approach in generating the compacted system matrix.

j j´

i + 



k k´

VjVj´=0

Figure 11. An ideal (infinite gain) operational amplifier.

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Example: Consider the ideal operational amplifier (op-amp) shown in Figure 11. Again assuming that the Y matrix is already generated for the other branches, the impact of this device on the system matrix is to add an additional row and column corresponding to the new system variable i as shown below

(44)

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The elimination combinations and stamping procedures for this device can be summarized as follows: 1. If one of the input voltages (say Vj) is not needed but i is a solution variable then the stamping procedure is:  Add column j´ to column j and put the result in column j,  Replace the j´th column by the elements of column i given in equation (44) and delete row i. The resulting system matrix is

(45)

2. If the current i is not a solution variable but both input voltages are, then the stamping procedure is:  Add row k´ to row k and put the result in row k,  Replace the k´th row by the elements of row i given in equation (44). The resulting system matrix is

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(46)

3. If neither the current i nor one of the input voltage (e.g. Vj´) are solution variables then the stamping procedure is:  Add row k´ to row k, put the result in row k and delete row k´,  Add column j´ to column j, put the result in column j and delete column j´, The resulting system matrix in this case is

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(47)

Obviously, the op-amp constrains the input nodes but not the output nodes so that only one of the input node voltages can be eliminated. Therefore, the procedures leading to equations (45)-(47) are the basic three stamping procedures of the op-amp. The forms of equations (45)-(47) might be different depending on which of the input node voltages (Vj or Vj´) is to be eliminated but the general steps are the same.

4.3. Practical Application of the CMNA Method The above three examples served to introduce the concept of stamping in generating a compacted system matrix using three elementary devices. Other elements like the general two-port network and the controlled sources have more complicated stamps with many conditions. A comprehensive list of all the conditions is beyond the scope of this chapter but a summary of the most common stamps is shown in Table 3. In practice the actual linear operation described by the stamping procedure must be postponed until all the elements have been added. However if the system is described using the simplified representation of equations (1) and (3), the linear operations can be carried out on the P matrix as it would not affect the element values. Yet the actual row eliminations must be postponed until all the elements

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are added to avoid eliminating an element whose effect on the system matrix is yet to be added. Table 3. Stamp models of linear circuit elements Table 3 Stamp models of linear circuit elements

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.

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Element Stamp Algorithm for Matrix Formulation … Table 3. (Continued)

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.

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Even when all the conditions set forth are met, consistency must be maintained and verified in choosing the solution variables as an inconsistent set of solution variables may lead to conflicting stamping procedures that could not be carried out. In the following examples, use will be made of the method in analyzing typical circuits. Through these, a try will be made to outline the general steps of the analysis procedure and to verify its efficiency in generating a small dense set of linear equations. Example: Consider the following active network shown in Figure 12. The first thing that has to be done is to decide which variables are to be considered as solution variables. Assuming that only the node voltages V2 and V4 are needed while all the other variables are to be eliminated, a preliminary Y-matrix for the network has to be generated. This matrix has the size of 4x4 since there are 4 ungrounded nodes. It can be generated for the passive elements using the stamp of equation (37) as shown below:

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(48)

The next step is to add the influence of the independent voltage source keeping in mind that one of its nodes is grounded and that neither its node voltages nor its current are solution variables. The following stamping procedure was used:  

Subtract column 1 multiplied by E1 from the right-hand side, Remove row and column 1.

The resulting system matrix and the right-hand side after this will be

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Element Stamp Algorithm for Matrix Formulation …

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C4 1

G2

3 2

E1

+ 

4 +

G3

V6

C5

+ 

V7=V6

 0

Figure 12. An active network with a VCVS.

Finally, the impact of the voltage-controlled voltage source is added keeping in mind that one of its input nodes is grounded and that neither its input node voltages nor its output current are solution variables. To this end, the following stamping procedure was used:  

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

Delete row 4, Add column 3 multiplied by 1/µ to column 4 and put the result in column 4, Delete column 3.

The final system matrix will be

(50) To compare various formulations, it is convenient to introduce the matrix density D and the formulation efficiency F, defined respectively as follows [6], [66]:

(51) For this example, the matrix has the size 22 for two solution variables and there are 4 nonzero entries. Thus the density is D=100% and the efficiency is

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F=100%. It can be verified that the tableau formulation produces a matrix of size 1818 with a density as low as 12% and an efficiency as low as 11% [6]. Example: Consider the following active network shown in Figure 13. Assume the solution variables are only the node voltages V1 and V4, while all the other variables are to be eliminated. The preliminary Y-matrix has the size of 55 since there are 5 ungrounded nodes. It can be generated for the passive elements as given below:

(52)

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Next, the effects of the op-amps are added. The op-amps in this example will be assumed ideal with infinite gains and input impedances. This assumption introduces a virtual ground between the inputs of the op-amps. The stamping procedure used to add the first op-amp is:  

Add column 3 to column 1 and put the result in column 1, Delete row 4 and column 3.

On the other hand, the stamping procedure used to add the second op-amp is:

1

2

Figure 13. A generalized impedance converter.

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Add column 5 to column 1 (since column 1 and column 3 are virtually short-circuited) and put the result in column 1, Delete row 2 and column 5.

The resulting system matrix equation will be

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(53)

For this example, the matrix has the size 3x3 for three solution variables and there are 7 nonzero entries. Thus the density is D=77.78% and the efficiency is F=66.67%. It can be verified that the tableau formulation produces a matrix of size 2525 with a density as low as 9.12% and an efficiency as low as 8% [6]. It is evident from the above example that not all unwanted system variables can be reduced with the stamping procedure. The formulation efficiency is not always 100% unless the proposed method is combined with a matrix reduction technique (like Kron‟s reduction) to reduce the unconstrained node voltages. In such a case, the reduced system matrix will be obtained. Although the later provides the highest formulation efficiency, it is not the best choice always. The problem lies in the reduction itself. It involves the division of each new term by the pivotal element, which complicates the elements in the new matrix and increases the number of symbolic terms. The complexity increases drastically with each application of the reduction. Therefore, the best utilization of the reduction is to apply it whenever there is a pivotal element of unity. Of course, this means sacrificing some of the formulation efficiency. However, the final gain surpasses any inefficiency that might be introduced. The benefits of this technique in matrix formulation can be summarized as follows: 1. Ability to use sparse techniques to overcome the possible inefficiency in the system matrix, 2. Reduction of the overall solution time, 3. Reduction of the overall memory requirement, which provides an ability to solve larger systems, 4. Flexibility of the technique to generate system matrices that might be as big as the tableau matrices or as small as the matrices formulated by

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad hand. This, of course, offers solutions that range from transfer functions to voltage and current solutions for each element in the network, 5. Exceptional control over the generated matrix density and efficiency in such a way so as not to disturb the improved time performance of the method. 6. Macro-models of section 4.2 can be easily converted with proper elimination of non-system variables into Macro-stamps with the required complexity level. This provides element stamps for more complicated elements like transistors and non-ideal op-amps

4.4. Implementation Considerations Practical implementation of the CMNA for symbolic circuit analysis requires further special considerations. Techniques for representing the symbolic matrix need to be applied during the software development. To that end we may assume without loss of generality that, at a given operating point, an electronic circuit is described by the modified nodal equations with the coefficient matrix

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(54) In the same way used to define equation (1). The coefficient matrix A can be directly obtained from the element equations using the “stamp approach” as described in the previous section [6]. These element models are directly inserted and their symbolic values are added to other element values at the corresponding locations of the modified nodal matrix. As before P and Q are the topological matrices that indicate location of the element‟s parameter value (element value) in the modified nodal coefficient matrix A. Except for the reference node (ground), typically all element values are placed at most at 4 locations in A using the stamp approach as can be seen in Table 3. More specifically, for each element its symbolic value Y is placed, e.g. equation (37), on the intersection of rows i and j and columns k and l as in the following stamp matrix Sy (all remaining elements of the stamp matrix are zero):

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(55)

Each circuit element has a single row and column in topological matrices P and Q respectively that represent information about element‟s interconnections. More specifically, for an element described by the stamp of equation (55), matrix P contains 1 and -1 in rows i and j and matrix Q contains 1 and -1 in columns k and l with all other elements equal to 0. Thus, if a circuit model has b elements, and it is described by nn modified nodal matrix T, then P and Q matrices are nb and bn matrices respectively. Some stamps may contain not only the element value represented in equation (54) by Y but constant values as well. These constant values do not affect matrices P and Q. In a circuit model with passive two-terminal circuit components (R, L, and C) only, matrix P is equal to matrix Q, and it is known as the incidence matrix. Having those matrices set up, the method of handling them once the system matrix is obtained depends entirely on the solution algorithm to be adopted. Successive reduction by Kron‟s equation does not provide the most efficient way for the solution. Practical experience shows that direct algebraic methods guided by topological methods are the most efficient. For that reason it is important to know how to generate basic graphical representation of the circuit without the need to go in the details of graphical analysis. The three types of graphs (signal-flow graphs, directed graphs, and conjugated graphs) can be easily obtained from the modified nodal stamps, and their major types are clearly established based on how they appear in the modified nodal matrix. Each edge of a graph may describe one, two, or four elements of the coefficient matrix depending on whether it is in a signal-flow graph, directed graph or pair of conjugated graphs. Table 4 contains various types of example graphs of a passive two-terminal element and a voltage controlled current source. Using the stamp approach based on the modified nodal equations [6] all types of graphs can be directly obtained. A complete set of Coates‟ graph stamps were presented by Starzyk in [67] using the so called transitor models. Chen [33] presented a subset of unistor graph models for elements with admittance

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

description only. In [68] this description was extended to include all elements with modified nodal equations using formal unistor models. In addition, Starzyk introduced dispersor graphs and used them for topological analysis in [69]. Seshu [30] showed how to obtain current–voltage graphs and Davies [70] presented nullator-norator networks of the controlled sources. Finally, the conjugated norator -nullator graphs and rules to use them in topological analysis were presented by Starzyk in [71]. These stamp based models facilitated topological analysis by automating the graph creation process, a critical step in computer based topological analysis. Table 4. Graphs of a two-terminal element and a voltage controlled current source

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Table 4 Graphs of a two-terminal element and a voltage controlled current source

Dispersor graphs were introduced in [69] to use topological methods for analysis of electronic circuits with ideal op -amps. Although unistor models of electronic elements were known in the literature, only the introduction of formal

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unistor models [72] permitted to model ideal op -amps and other active elements for which unistor models did not exist. Other forms of graphical representations based for instance on the tableau equations can be used, however, they lead to larger graphs and, in general, require more effort to analyze. Solutions using topological methods vary in complexity and efficiency depending on the graph selected. Exact symbolic analysis based on hierarchical decomposition and a graphical representation of symbolic determinants called determinant decision diagrams (DDD) can be used in this respect for a very efficient implementation [73]. DDD‟s take advantage of the coefficient matrix sparsity leading to exact and canonical symbolic analysis that share symbolic expressions to improve computing efficiency. Efficiency of this method exceeds efficiency of numerical analysis programs like Spice. It is also faster than other symbolic programs such as ISAAC and Maple-V, and uses less computer memory [74].

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5. Conclusion The CMNA algorithm was presented in this chapter with special considerations adopted to automatically generate the system matrix for symbolic circuit analysis applications. The formulation was presented in a simplified yet generalized form with ability to select solution variables automatically at various levels of complexity. Ultimately a heuristic approach can be adopted in the program instead of a comprehensive list of if-conditions to automatically weigh the complexity of the generated terms versus the reduction gained in the system matrix size. A note was also made on automatic generation of different graphical representations for the same application much in the same way adopted in the CMNA stamping procedure. This is a crucial step for any topological solver algorithm. Although not part of the CMNA formulation, constraints imposed by the element stamps were introduced with emphasis on nodal effects under such constraints. Such a view of constrained nodes becomes particularly important in symbolic circuit design where element values are only represented by ranges and spans. Finally the concept of element model incorporation within the CMNA is briefly introduced through Macro-stamps. Ideally, using this simple description and the derivation methods developed in this chapter, generalized element stamps can be derived to represent even active element models.

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The improved performance of the method was verified by solving a number of examples and comparing the formulation efficiency and the memory requirements with several commercial packages. Indeed, the proposed method can achieve (if applied correctly) significant savings in efficiency and memory resources of the computer not to mention the potential ability to solve larger circuits.

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References [1] Monagan, M. (1997). Programming in maple: the basics. Institute für Wissenschaftliches Rechnen, Zürich, Switzerland. http:// amath. colorado.edu/ computing/mmm/MapleProgr.pdf [2] Hammerton, P. & Stevens, D. (1999). Introduction to MAPLE. Maths Terminal Room, mth1a31. http:// www. uea.ac.uk/~dps/mth1a31/ maple.pdf. [3] Char, (1992). B. et al. First Leaves: A Tutorial Introduction to Maple V; Springer-Verlag Pub: New York. [4] Brown, H. E. (1985). Solution of Large Networks by Matrix Methods, John Wiley and Sons: New York, 1985. [5] Press, W. H., Teukolsky, S. A., Vetterling, W. T. & Flannery, B. P. (1992). Numerical Recipes in C: The Art of Scientific Computing, second edition; Cambridge University Press: New York. [6] Vlach, J. & Singhal, K. (1994). Computer Methods for Circuit Analysis and Design; second edition; Van Nostrand Reinhold: New York. [7] Kirchhoff, G. (1947). On the solution of the equations obtained from the investigation of the linear distribution of galvanic currents. IRE Trans, 1958, Vol. CT-5, (tlum. pracy z 1947). [8] Dunn, W. R., Jr. & Chan, S. P. (1971). Topological formulation of active network functions. IEEE Trans. Circuit Theory, Vol. CT -13, 554-557. [9] Jony, M. T. & Zobrist, G. W. (1968). Topological formulas for general linear networks. IEEE Trans. Circuit Theory, Vol. CT-15, 251-259. [10] Chen, W. K. (1965). Topological analysis for active networks. IEEE Trans. Circuit Theory, Vol. CT-12. [11] Nathan, A. (1965). Topological rules for linear networks. IEEE Trans. Circuit Theory, Vol. CT-12, No 3. [12] Braun, J. (1966). Analytical methods in active network theory. Acta Polytechnica – Prace CVUT v Praze. Vol. IV. I. [13] Braun, J. (1966). Topological analysis of networks containing nullators and norators. Electr. Lett, 1966, 427.

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[14] Davies, A. C. (1966). Topological solutions of networks containing nullators and norators, Electr. Lett, 90. [15] Talbot, A. (1966). Topological analysis for active networks. IEEE Trans. Circuit Theory, Vol. CT-13. [16] Wang, K. T. (1934). On a new method for the analysis of electrical networks. National Resources, Institute for Engineering, Academia Sinica Memoir, No 2. [17] Ting, S. L. (1935). On the general properties of electrical network determinant. Chinese Journal of Physics, No 1. [18] Tsai, C. T. (1939). Shortcut methods for expanding the determinants involved in network problems. Chinese Journal of Physics, No 3. [19] Duffin, R. J. (1959). An analysis of Wang algebra of network. Trans. American Mathematics Society. [20] Bellert, S. & Wojciechowski , J. (1972). Grafy blokowe i liczby strukturalne drugiej kategorii. Prace naukowe P.W., Seria Elektronika, No 1. [21] Bellert, S. & Wozniacki, H. (1968). Analiza i synteza układów elektrycznych metoda. liczb Strukturalnych. WNT: Warszawa. [22] Bellert, S. (1962). Topological analysis and synthesis of linear systems. Journal of the Franklin Inst., Vol. 274. [23] Bellert, S. (1963). Topological considerations and synthesis of linear networks by means of the method of structural numbers, Arch. Elektr. t.XII, z.3. [24] Gandhi, B. R. M., Rao, V. P. & Raju, G. S. (1972). Passive and active circuit analysis by the method of structural numbers. Int. J. Electr, Vol. 32, No 6. [25] Coates, C. L. (1959). Flow graph solutions of linear algebraic equations. IRE Trans. Circuit Theory., 170-187. [26] Coates, C. L. (1958). General topological formulas for linear networks functions. IRE Trans. Circuit Theory, Vol. 5. [27] Mason, S. J. (1956). Feedback theory - further properties of signal flow graphs. Proc. IRE, Vol. 44, 920-926. [28] Mason, S. J. (1953). Feedback theory - some properties of signal flow graphs. Proc. IRE, Vol. 41, 1144-1156. [29] Mayeda, W. (1983). Topological formulas for active networks. Univ. of Illinois. 1958, Int. Tech. Rpt. No 8, U.S. Army Contract No DA-11-022ORO-1983. [30] Seshu , S. & Reed, M. B. (1961). Linear graphs and electrical networks; Addison-Wesley P. C. [31] Davies, A. C. (1966). On matrix analysis of networks containing nullators and norators. Electronic Letters, 48.

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Fawzi M. Al-Naima and Bessam Z. Al-Jewad

[32] Mason, S. J. (1957). Topological analysis of linear nonreciprocal networks. Proc. IRE, Vol. 45, 829-338. [33] Chen, W. K. (1976). Applied graph theory - graphs and electrical networks, North-Holland P. C. [34] Chen, W. K. (1966). On directed trees and directed k -trees of a digraph and their generation. SIAM J. Appl., Math. Vol. 14, No 3. [35] Janusz, A. & Starzyk, (2007). Topological Analysis and Diagnosis of Analog Circuits. Wydawnictwo Politechniki Śląskiej Gliwice. http://www.ent.ohiou.edu/~starzyk/network/Research/Papers/ Topological_analysis_and_diagnosis.pdf. [36] Beineke, L. W., Gross, J. L., Maurer, S. B. & Scheinerman, E. R. (2000). Graph theory- Handbook of Discrete and Combinatorial Mathematics, K. H. Rosen; J. G. Michaels, J. L. Gross; J. W. Grossman; D. R. Shier; CRC Press LLC.: New York. [37] Csiszar, I. & Korner, J. (1981). Graph decomposition: A new key to coding theorems. IEEE Transactions on Information Theory, Vol. 27, No 1. [38] Ho, J. K. & Loute, E. (1981). An advanced implementation of the Dantzig – Wolfe decomposition algorithm for linear programming. J. Mathematical Programming, Vol. 20, 303-326. [39] Hu, T. C. (1969). Integer programming and network flow Reading; Addison – Wesley P. C. MA. [40] Goto, S. & Sangiovanni-Vincentelli, A. (1979). A new decomposition algorithm for the shortest path problem. Proc. IEEE Int. Symp. on CAS, Tokyo. 653 -656. [41] Frederickson, G. N. (1991). Planar graph decomposition and all pairs shortest paths. Journal of the ACM, Vol. 38, No 1, 162 -204. [42] Chu, T. (1987). Synthesis of Self-timed VLSI Circuits from Graph Theoretic Specifications., Massachusetts Institute of Technology, Technical Report TR -393. [43] Pothen, A., Simon, H. D. & Liou, K. P. (1990). Partitioning sparse matrices with eigenvectors of graphs. SIAM Journal on Matrix Analysis and Applications, Vol. 11, No 3, 430-452. [44] Wu, S. D., Byeon, E. S. & Storer, R. H. (1999). A Graph-Theoretic Decomposition of the Job Shop Scheduling Problem to Achieve Scheduling Robustness. J. Operations Research, Vol. 47, No 1, 113-124. [45] Ehrenfeucht, A., Harju, T. & Rozenberg, G. (2002). Gene assembly through cyclic graph decomposition. Theoretical Computer Science, Elsevier, Vol. 281, No 1 -2, 325-349. [46] Ko, M. Y., Murthy, P. K. & Bhattacharyya1, S. S. (2004). Compact

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Element Stamp Algorithm for Matrix Formulation …

[47] [48] [49] [50] [51] [52]

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[53] [54] [55]

[56] [57] [58] [59] [60]

53

Procedural Implementation in DSP Software Synthesis through Recursive Graph Decomposition. Software and Compilers for Embedded Systems; Springer Verlag, Lecture Notes in Computer Science, 3199, 47 -61. Engel, A. B. & Mlynski, D. A. (1979). Maximal partitioning of graphs. Proc. IEEE Int. Symp. on CAS, Tokyo. 84 -87. Ferrari, D. (1974). Improving locality by critical working sets. Comm. of ACM. Vol. 17, No 11, 614-620. Kernighas, B. W. & Lin, S. (1970). An efficient heuristic procedure for partitioning graphs. Bell System Tech. J, Vol. 49, No 2, 291 -307. Luccio, F. & Sami, M. (1969). On the decomposition of networks in minimally interconnected subnetworks. IEEE Trans. Circuit Theory, Vol. CT-16, 184-183. Narayanan, H. (1979). A Theorem on graphs and its application to network analysis. Proc. Int. Symp. Circuits and Systems, Tokyo. 1007 -1011. Ogbuobiri, E. C., Tinney, W. F. & Wal ker, J. W. (1970). Sparsity-directed decomposition for Gaussian elimination on matrices. IEEE Trans. Power, Appr. Syst, Vol. PAS-89, 141-150. Callier, F. M., Chan, W. S. & Desoer, C. A. (1976). Input-output stability theory of interconnected systems using decomposition techniques. IEEE Trans. Circuits and Systems, Vol. CAS-23, 714-729. Guardabassi, G. & Sangiovanni-Vincentelli, A. (1976). A two levels algorithm for tearing. IEEE Trans. Circuits and Systems, Vol. CAS -23, 783791. Desai, M. P., Narayanan, H. & Patkar, S. B. (2003). The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. J. Discrete Applied Mathematics, Vol. 131, No 2, 299310. Starzyk, J. A. (1984). Decomposition Approach to a VLSI Symbolic Layout with Mixed Constraints. Proc. IEEE Int. Symp. Circuits and Systems, Montreal, 457-460. Kron, G. (1963). Diakoptics: the piecewise solution of large scale systems, Mc Donald: London. Nicholson, H. (1978.) Structure of interconnected systems; Peter Peregrines LTD. Stenbakken, G. N. & Starzyk, J. A. (1992). Diakoptic and Large Change Sensitivity Analysis. IEE Proc. Part G, Circuits, Devices and Systems, Vol. 139, No 1, 114-118. Chua, L. O. & Chen, L. K. (1976). Diakoptic and generalized hybrid analysis. IEEE Trans. on CAS, Vol. CAS-23, No 12, 694-705.

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[61] Konczykowska, A. & Starzyk, J. (1975). Wyznaczanie liczby strukturalnej grafu zdekomponowanego. Czesc I i II, Arch. Elektrot, z.2. [62] Konczykowska, A. (1976). Analiza ukladow elek trycznych z zastosowaniem metod dekompozycji, Praca doktorska, Warszawa. [63] Tosic, D. V., Djordjevic, A. R. & Reljin, B. D. (1997). Symbolic Analysis of Microwave Circuits. Journal of Applied Electromagnetism, Vol. 1, No 1, 3745. [64] Tosic, D. V., Djordjevic, A. R. & Reljin, B. D. (1996). Symbolic computation of S-parameters of linear electric networks. ETF Journal of electrical engineering, Vol. 6, No 1, 84-98. [65] Fidler, J. K. & Nightingale, C. (1978). Computer Aided Circuit Design; Thomas Nelson and Sons: Hong Kong. [66] Fernández, F. V., Rodríguez-Vázquez, A., Huertas, J. L. & Gielen, G. E. (1998). Symbolic Analysis Techniques – Applications to Analog Design Automation, IEEE Press: New York. [67] Starzyk, J. A. (1981). Analiza topologiczna duzych ukladow elektronicznych, Prace Naukowe PW, Elektronika, z. 55. [68] Centkowski, G., Starzyk, J. & Śliwa, E. (1980). Computer implementation of topological method in the analysis of large networks, Proc. of the ECCTD Warszawa. [69] Starzyk, J. A. (1978). The dispersor graphs. Proc. of 3rd Czech-Polish Workshop on CT, Prenet. [70] Davies, A. C. (1967). Nullator-norator equivalent networks for controlled sources. Proc. IEEE, 722-723. [71] Starzyk, J. A. (1975). Metody topologiczne analizy akladow skupionych liniowych i stacjonarnych z nulatorami i no ratorami, Prace Naukowe PW, Elektronika, No 20. [72] Centkowski, G., Konczykowska, A., Starzyk, J. & Śliwa, E. (1980). Modernizacja program HADEN zuwzględnieniem analizy hierarchicznej wstę pującej, analizy tolerancjiz możliwością analizy układow z przełączanymi pojemnościami. Problem badań podstawowych, Warszawa. No 1.11.07.02. [73] Tan, X. D. & Shi, C. J. R. (2000). Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams. IEEE Trans. on Computer–Aided Design of Integrated Circuits and Systems, Vol. 19, No 4, 401-412. [74] Shi, C. J. R. & Tan, X. D. (2000). Canonical symbolic analysis of large analog circuits with determinant decision diagrams. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, no 1, 1-18.

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ISBN: 978-1-61728-106-8 © 2011 Nova Science Publishers, Inc.

Chapter 2

MICROWAVE AND MILLIMETER-WAVE COAXIAL-WAVEGUIDE POWERDIVIDING/COMBINING CIRCUITS Kaijun Song* Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

EHF Key Laboratory of Fundamental Science, School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu, 610054, China

Abstract The microwave power-combining technology is one of the most important approaches to obtain high power using semiconductor devices, especially in millimeter-wave band, in which the available power from a single device is low. Conventional hybrid-type power-combining circuits, such as Wilkinson power dividers, Lange couplers, and branch-line couplers suffered from low powercombining efficiency, limit power handling capability, and impedance bandwidth. In this chapter, we discuss the novel designs of microwave and millimeter-wave coaxial-waveguide power-dividing/combining circuits. The traditional rectangular waveguide power dividers have limited bandwidth due to the cutoff frequency and transmission dispersion effect. The coaxial waveguide is a good (potential) candidate to overcome these problems due to its TEM waveguide environment. In this chapter, we have detailedly discussed the oversized coaxial waveguide power dividers using a probe array to achieve very wide band and low insertion loss. Furthermore, the equivalent*

E-mail address: [email protected]; [email protected].

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Kaijun Song circuit method has been developed to analyze this type of power-dividing circuits. To integrate the 3-D waveguide divider and planar power amplifier circuitry, the planar probe coaxial-waveguide power divider/combiner has been developed and investigated. In addition, a novel ultra-wideband (UWB) multiway coaxial-waveguide power divider with rotated electric field mode has been discussed, and it will be easy to construct the active power-combining system at microwave and millimeter-wave frequencies. This chapter also provides many design examples using full-wave electromagnetic (EM) simulation. EM simulation tools have become widely available and served as an invaluable tool for the first-pass design of coaxialwaveguide power-combining circuits.

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1. Introduction With the rapid advancement of military and commercial communications systems in recent years, the demands for high-power solid-state power amplifiers with high efficiency and wide bandwidth have greatly increased. The research for high-power solid-state power amplifier is always an important issue in microwave/millimeter-wave communication systems. The amplifier’s bandwidth, output power, and efficiency drive the communication system’s link performance, power budget, and thermal design. Traveling-wave tube amplifier (TWTA), known for its high power capability and high efficiency, is widely used in microwave systems such as radars, satellite, and wireless communication systems. However, motivated by benefits such as low supply voltage, small size, low development cost, and a wide commercial technology base, there is considerable interest in developing broadband, efficient, solid-state power amplifiers as an alternative to vacuum tube technology. However, at microwave and millimeter-wave frequencies, the individual solid-state device produces less power and operates at lower efficiency when comparing with individual vacuum tube device. To overcome these difficulties, the power combining techniques have been presented, which can integrate a large amount of solid-state amplifiers in order to obtain high output power. Thus, the considerable research activities of developing broadband and efficient powerdividing/combining circuits have been motivated, and a wide variety of powercombining techniques have been demonstrated [1-24]. Conventional hybrid-type power-combining circuits, such as Wilkinson power dividers, Lange couplers, and branch-line couplers, suffer low power-combining efficiency at microwave and millimeter-wave frequencies due to high insertion loss [24]. Furthermore, microstrip-line power-dividing networks are limited by power handling capability [24].

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Therefore, the multi-way, broadband, and low-loss power-dividing/combining circuits are highly desirable. To meet these requirements, various techniques, such as quasi-optical and waveguide-based spatial power-combining approaches, have been proposed at these frequencies [1-13], [19-29]. These techniques are preferred over traditional corporate combiners because of their low insertion loss, and high power-combining efficiency. Generally, waveguide technology is superior in many applications due to its low loss and high power handling capability. Additionally, waveguide combiners have the potential to accommodate a large number of amplifiers within a constrained space. The waveguide-based spatial power-combining technology has been greatly developed in the recent years. Large numbers of spatial power combiners based on rectangular waveguide have been presented [25-29]. The power combiners using finline array in a rectangular waveguide have been investigated and applied as high power-combining amplifiers at X-band [28]. However, the bandwidth of the rectangular waveguide is limited by its cutoff frequency [30-34]. In addition, the dominant TE10 mode inside the rectangular waveguide leads to non-uniform illumination of the loaded finline array inside the waveguide, which can reduce the efficiency and distort the saturation characteristics of the system. What's more, the rectangular waveguide environment is dispersive, which complicates broadband impedance matching over an extended frequency range. Moreover, the number of solid-state amplifiers is limited by the size of the standard rectangular waveguide. Although an oversized rectangular waveguide can be used to include a large number of the solid state amplifiers at microwave and millimeter-wave range, the higher order modes may be generated by the discontinuities in the oversized waveguide, and cannot be suppressed effectively. A slotted-waveguide power-dividing/combining circuit has been presented and used in power amplifier at millimeter-wave range, and has shown a high power-combining efficiency of 80% [26]. However, the slotted-waveguide spatial combiner is a chain-coupled combiner, in which the incorporation of various couplers and phase shifters is quite complicated, and the operation bandwidth is quite limitary with the increasing devices. The difficulties of waveguide power divider mentioned above can be addressed by replacing the rectangular waveguide by a TEM waveguide environment, such as a coaxial waveguide. A spatial power divider using finline array in an oversized coaxial waveguide was first proposed by Alexanian and York [30]. A flared coaxial line is loaded radially with tapered slotlines along the direction of wave propagation. Each input slotline provides a gradual transition from the coaxial TEM field to a planar transmission line, for compatibility with standard microwave integrated circuitry. This coaxial power divider/combiner has

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Kaijun Song

wider frequency response compared with the rectangular waveguide type divider [30-34]. However, this complex design and difficult fabrication structure is not suitable for millimeter-wave applications. It is also difficult to efficiently remove the heat from the microwave amplifiers since the waveguide cannot be directly used as heat sink. In this chapter, several types of coaxial-waveguide power-dividing/combining circuits with probe array are presented, constructed, and designed. Based on the equivalent-circuit method, the circuit model of the coaxial-waveguide power dividers have been developed and used to design the desired multi-way broadband power dividers.

2. Coaxial-Waveguide Power-Dividing/Combining Structure The coaxial waveguide, which is extensively used in microwave circuits, is formed by a pair of concentric circular cylinders, as shown in Figure 1. Let a and b be the radii of the inner and outer cylinders, respectively, and the propagation of the wave be assumed to be in the z-direction. Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

y

r

a

φ

x εr

b

z

Figure 1. Coaxial waveguide.

The TEM wave is the dominant mode of propagation in the coaxial waveguide, and the TEM mode on the coaxial waveguide will be characterized by Ez  H z  0 ; furthermore, due to azimuthal symmetry, the fields will not have variation in  -direction, and so    0 . The fields inside the coaxial line will satisfy Maxwell’s curl equations,

    E   jH

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(1)

Microwave and Millimeter-Wave Coaxial-Waveguide …

    H   jE

59 (2)

where    ' j ' ' may be complex to allow for a lossy dielectric filling. Conductor loss will be ignored here. The electric and magnetic fields of the TEM mode inside the coaxial waveguide can be expressed as

Er 

E0 a  jz e r

H 

E0 a  jz e r

(3)

(4)

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

where β is the propagation constant of the waveguide. As shown in Figure 2, the dominant TEM mode is symmetry with respect to the coaxial line axis and no circumferential variations. The TEM electric field has

an r–directed component only, while the magnetic field has a  -directed component only. If N equispaced identical peripheral probes are inserted into the coaxial waveguide along the radial, it is possible for the coaxial waveguide to divide N-way equal signals into N probes because of the N-fold symmetry with respect to the coaxial waveguide axis. Figure 3 shows the coaxial waveguide power dividers/combiners using probe array that achieved low-loss probe-to-waveguide transitions [35-36]. In order to include a large of solid-state active devices, an oversized coaxial waveguide has been used. The purpose of the coaxial taper is to match the impedance at the flared end of the coaxial waveguide with the 50Ω input coaxial lines. The microwave signals are fed from the left input coaxial connector, then transmitted to the oversized coaxial waveguide through a coaxial taper, and subsequently divided into N ways through probe arrays in the left oversized coaxial waveguide; the divided N-equal signals are then fed to the input ports of N amplifiers; and these N-amplified signals are fed to N-input ports of the right power combiner; finally, the combined microwave signals are output from the right coaxial connector. Therefore, the signal dividing, amplifying, and combining have been implemented.

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Kaijun Song

Figure 2. TEM mode within coaxial waveguide. MMIC Amplifiers Outer Conductor

SMA Connector

Short wall

Inner Conductor

Coaxial probe

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

(a)

(b) Figure 3. Coaxial power dividers/combiners using probe array (a) Cross-sectional view along the axis and (b) along the radial.

The TEM electric field distributions within the oversized coaxial waveguide with probe array are shown in Figure 4. Although the electric fields are greatly changed and are non-uniform after inserting N probes, the electric field pattern within the oversized coaxial waveguide still has N-fold symmetry with respect to the coaxial line axis when the N probes are identical and equispaced in the oversized coaxial waveguide, which results in perfect amplitude and phase balance of the N probes.

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Microwave and Millimeter-Wave Coaxial-Waveguide …

61

Figure 4. The TEM electric field distributions within the oversized coaxial waveguide with probe array.

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

3. Design of the Coaxial Stepped Impedance Transformer When the coaxial-waveguide power-dividing/combining circuits include a large number of active devices to output high power, the radius of the oversized coaxial waveguide will become very large and further larger than the standard coaxial line. Therefore, the transition from the standard coaxial line to oversized coaxial waveguide will become an important issue. To obtain perfect impedance matching from the standard coaxial connector (such as the type-SMA connector or type-N connector) to the oversized coaxial waveguide, the coaxial stepped impedance transformer can be used, as shown in Figure 5. Figure 5(a) shows a multi-section coaxial stepped impedance transformer, which is used when a very good match is required over a broad frequency range. Its reflection characteristics can be studied by using the transmission-line model. As an exemplification, a two-section coaxial stepped impedance transformer is designed [37], as shown in Figure 5(b). The transmission-line equivalent-circuit approach is adopted to design this stepped impedance transformer. The structure has two step discontinuities. The first step discontinuity is due to the transition of

Z

the characteristic impedance from 0 to Z1 . The structure and equivalent circuit are shown in Figure 6. It is a junction of two coaxial guides of equal inner but different outer radii. The parameters of the equivalent circuit at the reference plane T can be expressed as [38]

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Kaijun Song

Y0' ln c a  Y0 ln b a

(5)

Z1

ZL

2R

2 r3

2 r1

2

2

Z0

x =0 x =L

L

L1

L2

Figure 5. Coaxial stepped impedance transformer circuit. (a) multi-stage (b) two stage.

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

Y0

Y0

b0 2a 2b 2c

T (a)

jB

T

T (b)

(c)

Figure 6. Structure of outer step discontinuity and its equivalent circuit. (a) side view; (b) cross sectional view; and (c) equivalent circuit. 2 4 B 2b0 A1  2.718 2 2  b0  A   2 ln   4  1   2  2  Y0   4 3 2  





(6) 2

a ln c a  b a  1  ba  A1      1  b c a  1 ln b a b  c  a   , and ca , 0 where ,

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Microwave and Millimeter-Wave Coaxial-Waveguide … 2c b

A2 

 2b 

 1 1   0    1 

2



63

 J ( x) N 0 ( xb c)  N 0 ( x) J 0 ( xb c)  1 a c  0  2 J ( x) 1 a b   1 2 0 J 0 ( xa c)

2

2

 2b d      0 sin 2  d b0   2b0   1      . 1

x

 1 1 a c



c x01 a is the root of  xa   xa  J 0 ( x) N 0    N 0 ( x) J 0    0  c   c  .

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The second step discontinuity is due to the transition of the characteristic impedance from Z1 to Z L , which is a junction of two coaxial guides of different inner but equal outer radii. Figure 7 shows the structure and the equivalent circuit of the inner step discontinuity. The parameters of the equivalent circuit at the reference plane T are given by

Y0' ln c a  Y0 ln c b

(7)

Y0

Y0

b0 2a 2b 2c

jB

T

T (a)

(b)

(c)

Figure 7. Structure of inner step discontinuity and its equivalent circuit. (a) side view; (b) cross sectional view; and (c) equivalent circuit.

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Kaijun Song

B  Y0 same as Eqs. (6) 2 b ln c a  c b  1  c b  A1     1   a c a  1  ln c b  c  a , b0  c  a , where , and 2 a b

 J ( x) N 0 ( xb a)  N 0 ( x) J 0 ( xb a)  c a 1 A2    0  2 2 J 0 ( x) c b 1    2b0   1  J 2 ( xc a)  1 1   0   1  

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x

 1 c a 1

 x01

2

2

 2b d     0 sin 2  d b0   2b0   1      . 1

is the first nonvanishing root of

 xc   xc  J 0 ( x) N 0    N 0 ( x) J 0    0  a   a  . The parameters of the equivalent circuit of these two step discontinuities can be obtained from equations (5) to (7). Each of the two step discontinuities can also be modeled as a discontinuity capacitance reactance. Thus, the overall equivalentcircuit model of this stepped impedance transformer can be developed as shown in Figure 8. The model consists of two discontinuities in capacitance and sections of coaxial waveguides represented by transmission lines. In the model, the lengths of the coaxial waveguide corresponding to characteristic impedances

Z0

, Z1 ,

L0 L , , and L1 , respectively. Z R is the impedance of the probe array, including the impedance of the back-short wall placed by a distance of L2 from the and Z L are

array. According to the transmission-line theory, we have

Zin3  Z L 

Z R  jZ LtgL1 Z L  jZ RtgL1

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(8)

Microwave and Millimeter-Wave Coaxial-Waveguide …

Zin 2 

Zin1  Z1 

Zin 0 

It is obvious that

Zin 0

65

Zin3 1  jB2 Zin3

(9)

Zin 2  jZ1tgL Z1  jZ in 2tgL

(10)

Zin1 1  jB1Zin1

(11)

can be determined from equations (8) to (11). If

Z  Zin0

chosen to be n·λ/2, then the input impedance is given by in equivalent model, the input reflection coefficient can be derived as

L0

is

. Using this

Z in  Z 0 Z in  Z 0 Z  Z0  in 0 Z in 0  Z 0 Z  Z 0  jB1Z in1Z 0  in1 Z in1  Z 0  jB1Z in1Z 0

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in 

Гin

L0

Z0

Zin

L

jB 1

Zin0 Zin1

(12) L1

jB 2

Z1

ZL

ZR

Zin2 Zin3

Figure 8. Overall equivalent-circuit model of the coaxial stepped impedance transformer.

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66

Kaijun Song 0.08 B1 B2

0.07

Susceptance (S)

0.06 0.05 0.04 0.03 0.02 0.01 0 1.5

2

2.5

3

3.5

4

R (mm)

Figure 9. Calculated susceptances of used in the calculations are:

B1 and B2 for the step discontinuities. The dimensions

r1 = 0.3175 mm, r2 = 0.71 mm, and r3 = 1 mm.

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Using equations (5) to (12), the parameters of the overall equivalent-circuit model of the coaxial stepped impedance transformer are determined. Conversely, when the value of inverted.

in

is specified, the parameters of the model can also be

The susceptances B1 and B2 shown in Figure 8 for the step discontinuities have been calculated using the above equations (5) to (7), as shown in Figure 9. It is obvious that B1 varies quickly with the outer radius R but B2 varies slightly with it.

4. Analysis of the Coaxial Taper Another method of changing impedance levels in a transmission system involves the use of a continuously coaxial taper. The coaxial taper is used when a very smooth impedance match is required over a broad frequency range. Figure 10 shows the coaxial taper transition circuit, which is essentially a piece of a nonuniform transmission line. The coaxial taper of length L is between the planes PP’ and Q-Q’, as shown in Figure 10, which can be viewed as a reciprocal and lossless two-port network. The continuously coaxial taper is synthesized from small reflection theory of TEM lines [39, 40], so the associated reflection coefficient of the gradual coaxial waveguide taper at x is given by

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Microwave and Millimeter-Wave Coaxial-Waveguide …

( x )   where

  2 / g

1 x  j 2 x d ln ZT ( x) e dx  C 2 0 dx

67

(13)

denotes the propagation constant of the coaxial line, which is

assumed to be lossless; ZT (x) denotes the characteristic impedance of the coaxial taper at x; and C is a constant.

 

L When x  L , ( x ) , where L is the reflection coefficient of Port 2. In this case, the associated reflection coefficient at x becomes

( x ) 

1 L  j 2 x d ln ZT ( x) e dx  L 2 x dx

(14)

When Port 2 is well-matched or terminated by a matched load, the element

S11 of the two-port network is equal to the reflection coefficient at Port 1, namely,

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

S11  1 

1 L  j 2 x d ln ZT ( x) e dx 2 0 dx

(15)

Similarly, when Port 1 is match-terminated, the element S 22 of the two-port network is equal to the reflection coefficient at Port 2, namely,

S 22  2 

1 L  j 2 x ' d ln ZT ( L  x' ) e dx' 2 0 dx'

(16)

The phases of S 21 and S12 can be expressed as

 21  12  11   22    / 2

(17)

Then the scattering parameters of the coaxial taper are



S   

S11

2 j  1 | S11 | e 21

1 | S11 |2 e j12   S 22 

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(18)

68

Kaijun Song It can be noted that the analytical integral results of the equations (15) and

(16) can’t be obtained directly except for several special functions of ZT (x) , such as triangular function and exponential function. Hence, the equations (15) and (16) have to be determined using numerical integration.

P

x

x'

Q

Port 2

Port 1

P'

L

Q'

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

Figure 10. The sketch of the coaxial taper.

5. Coaxial-Waveguide Power Dividers/ Combiners Using Coaxial Probe Array The coaxial waveguide power-dividing/combining structure with coaxial probe array is illustrated in Figure 3. The input power is divided by N ways using a coaxial probe array in an oversized coaxial waveguide. A short wall placed at λg/4 beyond the probe array transforms to an open circuit to the coaxial probe array. The operation frequency and bandwidth are determined by the coaxial probe dimensions and the electrical length between the waveguide short wall and the center of coaxial probe array. The power divider/combiner is terminated by commercially available type-SMA connectors. The coaxial tapers are used to match the oversized coaxial waveguide to 50Ω input lines. The reflection from the oversized coaxial waveguide to the type-SMA connector is minimized by the optimized coaxial taper transition. Obviously, this structure can accommodate a large number of amplifiers, provide uniform illumination of the array, and can be designed for ultra-wide-band operation.

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Figure 11 shows the cross section of a coaxial waveguide. Due to the symmetry and a dominant TEM mode excitation, an N-way power divider/combiner can be viewed as a structure composed of N identical sectoral waveguides separated by magnetic side walls, and the structure is reduced to a sectoral waveguide cell for analysis purpose, with PEC (Perfect Electrical Conductor) and PMC (Perfect Magnetic Conductor) boundary conditions applied [35]. When the divider/combiner consists of a large number of coaxial probes, each unit cell can be approximated by a rectangular waveguide cell for the convenience of analysis. So the problem of matching the coaxial probe is confined to matching a coaxial probe in a rectangular waveguide with magnetic side walls and a short at the back.

PEC

PEC

PMC

PMC PEC

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

PMC

PMC PEC

Figure 11. Schematic cross section of a coaxial waveguide with a coaxial probe array structures.

An equivalent-circuit, transmission line approach similar to that in [25] was used to determine optimum values for the coaxial probes admittances. Figure 12 shows an equivalent-circuit model (not including coaxial taper) of an N-way coaxial power divider. The equivalent-circuit model consists of N dividing units with coaxial probe represented by its respective conductance and susceptance, and sections of waveguides represented by transmission lines. The electrical length between the waveguide short wall and the coaxial probe, Ф, is taken to be the distance from the short wall to the center of the coaxial probe. Considering Figure 12, the admittance seen from the center of coaxial probe to short wall and normalized to the waveguide admittance is

Y ()  Yp ()  j cot(())

 G()  jB()  j cot(()) where Yp ( )  G( )  jB ( )

(19)

is the admittance of the coaxial probe

(normalized to the oversized coaxial waveguide admittance). Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

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Kaijun Song Ф G

Short

jB

L

Ф Coaxial waveguide input

G

jB

G

jB

Short

Ф Short

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Figure 12. Equivalent-circuit model of an N-way coaxial waveguide power divider (not including coaxial taper).

Since there are N waveguides separated by magnetic side walls in parallel, the input admittance of the array is simply the sum of all individual coaxialwaveguide transition admittances. The total admittance

Ym

is given by

Ym ( )  n  Y ( )  n[G( )  jB ( )  j cot(( ))]

(20)

Using this equivalent-circuit model, the input reflection coefficient at the center of coaxial probe array is given by

Y1 ( )  Ym ( ) Y1 ( )  Ym ( ) Y ( )  n[G ( )  jB ( )  j cot(( ))]  1 Y1 ( )  n[G( )  jB ( )  j cot(( ))]

L ( ) 

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Microwave and Millimeter-Wave Coaxial-Waveguide …

71

where Y1 ( ) is the characteristic wave admittance of the oversized coaxial waveguide. Using equation (21), the necessary coaxial probe admittance for perfect input match is given by

Yp ( )  Y1 ( ) / n  j cot(( ))

. Conversely,

when values of L ( ) are specified, the coaxial probe admittance can be determined using

Yp ( ) 

1  L ( ) Y1 ( )   j cot(( )) 1  L ( ) n

(22)

0

Por t 2

-5

Shor t wal l

Por t 1

-10 -15

dB

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Using the simplified model, the design of an N-way oversized coaxial waveguide power divider/combiner is reduced to solve a single waveguide to coaxial probe transition. This design approach becomes important when using full-wave analysis techniques to solve electrically large three-dimensional (3-D) problems. Analyzing a full coaxial probe array becomes computationally inefficient due to the stringent requirements placed on the computer resources. Therefore, simplifying the problem allows for a significant reduction in design time.

-20 -25 -30

S21 S11

-35 -40 5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 Freauency, GHz

Figure 13. Simulated results of a single probe-to-waveguide transition.

Using equations (19) to (22), we can determine a suitable value (G, B and Φ) to realize broadband matching as seen from the oversized coaxial waveguide input plane. Once suitable coaxial probe admittances were selected, a full-wave

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Kaijun Song

simulation tool (such as HFSS) was used to realize the desired admittances and determine the final dimensions of the structure. By treating an N-way coaxial waveguide power divider, in terms of the above simplified model, the design is reduced to solve a single probe to waveguide transition. If the divider/combiner consists of a large number of coaxial probes, the rectangular waveguide (with PMC side walls) approximation can be used, otherwise, only sectoral waveguide (with PMC side walls) approximation can be used. For a four-way coaxial power divider/combiner, the sectoral waveguide approximation is valid. A single probe-to-waveguide transition was simulated in Ansoft-HFSS. The sectoral waveguide comprising a coaxial probe (with PMC side walls) is used and the simulation includes the back short. Figure.13 shows the simulated S-parameters of the single probe-to-waveguide transition. The 15-dB return loss bandwidth is approximately 9GHz. Based on the design procedure discussed above, a broad-band four-way coaxial power divider for 6-17GHz operation was designed by expanding the single probe-to-waveguide transition [35]. The power-dividing structure was simulated in Ansoft-HFSS. Dielectric and conductor losses were included in the simulation. An optimized coaxial waveguide taper is applied at end to transform from a standard 50Ω type SMA connector to the flared coaxial waveguide. Reflection caused by the waveguide transition is minimized.

(a)

(b)

Figure 14. Photograph of four-way coaxial waveguide power divider (a) Overview of the coaxial waveguide power divider (b) Inside view (not including the inner conductor).

The fabricated coaxial waveguide power-dividing structure has been shown in Figure 14. The simulated and measured results about insertion and return losses are presented in Figure 15. Measured and simulated results agree well, with the

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insertion loss exhibiting a value of approximately 6 dB as expected for a four-way divider. The measured and simulated 15-dB return loss bandwidths were found to be approximately 8.2GHz and 8.7GHz, respectively, which is close to the simulated 15-dB return loss bandwidth of a single probe-to-waveguide transition. The measured and simulated bandwidth around which the minimum insertion loss increases by 0.5 dB was all found to be approximately 11GHz. 0 -6 -5

S11, dB

-15

-10 -12

-20 -25

-14

-30

-16

-35

-18

-40 5

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-8

6

7

8

S21, dB

Simulated Measured

-10

-20 9 10 11 12 13 14 15 16 17 18 19 Frequency, GHz

Figure 15. Simulated and measured results.

Based on the above coaxial-waveguide power divider, the four-way passive power-combining circuit is built by placing two identical power-dividing structures back-to-back, and efficient heat sinking of the power amplifiers can be achieved by mounting the active devices on the ground plane between two coaxial waveguides. The coaxial-waveguide active combiner is fabricated by copper blocks, and its assembly is shown in Figure 16(a). The four-device power-combining amplifier is built combining four identical MMIC Hittite HMC441LM1 internally matched GaAs PHEMT medium power amplifiers [36]. At 11GHz, the individual MMIC showed a small-signal gain of 17 dB and an output power of 19.8dBm. Measured return loss and small-signal gain of the broadband four-device power-combining amplifier are shown in Figure 16(b) as a function of the frequency. The four-device power-combining amplifier has 13–16.65-dB gain over a wide bandwidth from 7 to 13.5 GHz. The upper end bandwidth of the four-device power amplifier is limited by the individual MMIC.

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Kaijun Song

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(a)

(b) Figure 16. (a) Photograph of the broadband four-device power-combining amplifier (b) measured return loss and small-signal gain.

In addition, the output power properties have also been studied. Figure 17(a) shows that the output power of 25.4dBm is achieved at the 1-dB gain compression at 11GHz, while the power-combining efficiency is 91%. The output power of the four-device power-combining amplifier as a function of frequency is shown in Figure 17(b). These small-signal gain and output power results are uncorrected flange-to-flange results including all the associated losses in the assembly and the fabrication errors.

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Microwave and Millimeter-Wave Coaxial-Waveguide … 30

Output Power (dBm)

25

20

15

10

5 -10

-5

0 5 Input Power (dBm)

10

15

(a) 26

Output power (dBm)

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25 24 23 22 21 20 6

8

10 12 Frequency (GHz)

14

(b) Figure 17. (a) Output power at 11GHz (b) Pout@1dB.

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75

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Kaijun Song

6. Coaxial-Waveguide Power Dividers with Microstrip Probes As illustrated in Figure 18, the coaxial-waveguide power dividers/combiners with microstrip probes are similar to those with coaxial probes [41]. So, this type of coaxial power dividers/combiners can be designed by using the methods above. Obviously, this coaxial power divider/combiner can integrate the microstrip probes with solid state devices well, for compatibility with standard microwave integrated circuitry. In addition, the microstrip probe array has been used to achieve the power-dividing/combining in this type of coaxial power dividers/combiners, which can be fabricated by using the standard printed circuitboard (PCB) process and has the potential to be used in millimeter-wave and submillimeter-wave power-dividing/combining networks. MMIC Amplifiers

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

Outer Conductor

SMA Connector

Short wall

Inner Conductor

Microstrip probe

Figure 18. Topology of coaxial waveguide divider/combiner.

To validate the performance of this type of coaxial power divider, a four-way coaxial-waveguide power divider has been designed and fabricated [41], as shown in Figure 19(a). Figure 19(b) shows the measured insertion and return losses together with the simulated results for the fabricated coaxial-waveguide power divider. The power-dividing structure was simulated in HFSS. The measured results included the influences of the SMA connectors at input and output ports. Measured and simulated results agree well, with the insertion loss exhibiting a value of approximately 6 dB as expected in an ideal four-way divider. The measured and simulated 15-dB return loss bandwidths were found to be

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approximately 28.6% and 45.3%, respectively. The bandwidth around which the minimum insertion loss increases by 0.5 dB was found to be 41.3% experimentally. Simulation predicted this value to be greater than 52%. The higher insertion loss in the measured response may be due to the dielectric loss, the insertion loss of SMA connectors, and imprecision in assembly. The shift in frequency is due to the inaccuracies in the machining of the waveguide and microstrip probe array, particularly the electrical length between the waveguide short wall and the microstrip probe θ, which determine the operating frequency.

0

-4 -6

-5 -8

-15

-10 -12 -14

S21, dB

Measured Simulated

-10

S11, dB

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

(a)

-20 -16 -25 -18 -30

-20 10

12

14

16

Frequency, GHz

(b) Figure 19. (a) Photograph and (b) Simulated and measured results of four-way coaxial waveguide power divider.

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Kaijun Song

7. Millimeter-Wave Coaxial-Waveguide Power-Combining Amplifiers

MMIC Amplifiers Lt

ZL

Wt Wb

Wp

2R

2a

2c

Z1

Lp

Z0

Outer Conductor K Connector

W

Short wall

2b

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

Figure 20 shows a millimeter-wave multi-way coaxial-waveguide powercombining amplifier including the amplifier connections [37, 42]. The combiner is terminated by type-K connectors available commercially. This type of power combiner has the following features: firstly, a microstrip probe array has been used to implement the power dividing/combining function; secondly, a stepped transformer has been used to provide a smooth impedance transition from the 50Ω input coaxial line to the oversized coaxial waveguide, which is easy to fabricate at millimeter-wave frequencies; finally, this topology can provide efficient heat sinking for active devices and be used widely at millimeter-wave frequencies. Figure 21 shows the comparison of a coaxial taper transformer and a coaxial stepped impedance transformer with the same length. It can be noted that the stepped transformer can meet the design expectation (the return loss is greater than 22 dB over the entire Ka band) although the characteristic of the return loss for the taper transformer is better than that of the stepped transformer. So, the stepped transformer has been used in this coaxial-waveguide amplifier because of the easy fabrication.

x =0 x =L L

L1

L2

Inner Conductor

Microstrip probe

Figure 20. Topology of a coaxial-waveguide power-combining amplifier.

The passive coaxial-waveguide power divider/combiner shown in Figure 20 can be analyzed according to the design method in Section 3.2.4. Apparently, the sectoral waveguide approximation is probably valid for this four-way coaxial-

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waveguide power divider/combiner. Thus, this four-way power divider can be viewed as a structure composed of four identical sectoral waveguides separated by PMC side walls, and the design is reduced to solve a single sectoral waveguide to microstrip probe transition. 0 -5 Return loss (dB)

-10 -15

Taper transformer Stepped transformer

-20 -25 -30 -35 -40

26

28

30

32 34 36 Frequency (GHz)

38

40

Microstrip output port

W Microstrip line

Dielectric

Short wall

Lt

Wt

Lp

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Figure 21. Comparison of a coaxial taper transformer and a coaxial stepped impedance transformer with the same length.

waveguide input Wp

PMC Waveguide input port

PMC

L2

Figure 22. Single sectoral waveguide-to-microstrip transition.

A waveguide-to-microstrip transition is shown in Figure 22. The sectoral waveguide comprising a microstrip probe (with PMC side walls and PEC inner and outer walls) is used. There is a transformer between microstrip line and microstrip probe so that the microstrip probe matches to a 50-Ω microstrip line.

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Kaijun Song

The design is then reduced to solve for input match at the waveguide port and output match at the microstrip line port. The transition including the short wall was simulated with Ansoft-HFSS. 0

S11 (dB)

-10

-20

-30

Lp=1.74 Lp=1.69 Lp=1.64 Lp=1.59 Lp=1.54

-40

-50 26

28

30

32

34

36

38

40

Frequency (GHz)

-5 -10 -15

S11 (dB)

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

(a)

0

-20 -25 -30

L2=1.95 L2=1.9 L2=1.85 L2=1.8 L2=1.75

-35 -40 -45 -50 26

28

30

32

34

36

38

Frequency (GHz)

(b) Figure 23. Simulation results of the power divider.

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Microwave and Millimeter-Wave Coaxial-Waveguide … During the design phase, the probe length

.

length

Lt

, transformer width

Wt

Lp

, probe width

Wp

81

, transformer

, and the length between the waveguide short wall

and microstrip probe L2 are adjusted to get the desired operation frequency and

bandwidth. A transformer of 90-Ω impedance is used instead of 50-Ω microstrip lines in order to obtain proper match between the probe and microstrip line. At 35 GHz, the length of the microstrip probe is optimized to be approximately 0.2λg due to the effective air-dielectric constant at the coaxial waveguide. Figure 23(a) shows the frequency response of the simulated input return loss with varying the probe length

Lp

and Figure.23 (b) shows the frequency response

for different lengths L2 between the waveguide short wall and the microstrip probe. Compared Figure 23(a) with Figure 23(b), we can see that the input return

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L

loss is more sensitive to p than to L2 . The fabricated coaxial-waveguide passive power-dividing/combining circuits are shown in Figure 24 [37]. Figure 25 shows the simulated and measured Sparameter of the passive combiner. It can be seen that the 10-dB return loss bandwidth can almost cover the entire Ka-band (from 26.5 to 40 GHz) and the insertion loss of the power-combining circuits is less than 2 dB at the entire Kaband except for several frequencies.

(a)

(b)

Figure 24. Photograph of the passive spatial combiner. (a) Overview and (b) Inside view.

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Kaijun Song 0

-10

-2

-20

-4

-30

-6

-40

-8 Simulated Measured

-50 26

28

30

S21 (dB)

S11 (dB)

0

-10 32 34 Frequency (GHz)

36

38

40

Figure 25. Simulated and measured input return loss and insertion loss of the passive coaxial-waveguide combiner. 30 20 S21_Single MMIC S21_Passive S11_Passive S11_PA S21_PA

10

(dB)

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0 -10 -20 -30 -40 26

28

30

32

34

36

38

40

Frequency (GHz)

Figure 26 (a). Photograph of the coaxial waveguide four-device power amplifier (b) measured S-parameters of the single MMIC, the four-way coaxial passive combiner, and the proposed power-combining amplifier

The millimeter-wave four-device power-combining amplifier using the proposed passive power-combining networks is designed and fabricated [42], as shown in Figure 26(a). The four-device power amplifier is demonstrated by combining four identical MMIC Agilent AMMC5040 internally matched GaAs pHEMT medium power amplifiers. For describing the characteristics of the fourdevice coaxial waveguide power amplifier, the S-parameters of the single MMIC

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have also been measured, as shown in Figure 26(b). The single MMIC showed a small-signal gain of more than 20 dB from 26 GHz to 37 GHz, and its smallsignal gain decreases with the increasing frequency. 100

28

95

Power (dBm)

26

90

24 22

85

20

80

18

75

16

Pout Efficiency

14

70 65

12 10 26

28

30

32 34 36 Frequency (GHz)

38

Power combining efficiency (%)

30

60 40

(a) 40 Pout Gain PAE

MMIC_Pout MMIC_Gain MMIC_PAE

35

25

30 25

20

20 15

15

PAE (%)

Power (dBm) & Gain (dB)

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30

10 5

10 -12

-8

-4 0 4 Input power (dBm)

8

0 12

(b) Figure 27 (a). Output power and power-combining efficiency (b) Output power, gain, and PAE of the proposed amplifier and single MMIC at 30 GHz.

Figure 26(b) and Figure 27 show the measured results of the four-device power-combining amplifier. The 10-dB return loss bandwidth of the fabricated amplifier is from 27.5 GHz to 40 GHz, and the power amplifier has 17–25.9 dB gain over a wide bandwidth from 26 to 38 GHz. The measured output power at 1dB gain compression is about 26.6 dBm at 30 GHz, with a power-combining

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Kaijun Song

efficiency of about 90%. The other measured results are also shown in Figure 26(b) and Figure 27.

Outer Conductor

SMA Connector Inner Conductor

4

5

3

6 Microstrip probe

7

2

1 8

11 9

10

Subtrate

(a)

(b)

(a) Cross-sectional view along the length of the coaxial waveguide. (b) The planar probe array within an oversized coaxial waveguide. (c) Numbering of the ports of a ten-way combiner.

(c)

Figure 28. The sketch of a planar probe coaxial-waveguide power divider/combiner

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8. Planar Probe Coaxial Power Dividers/Combiners A multi-way planar probe coaxial-waveguide power divider/combiner is shown in Figure 28 [43]. The port numbering is shown in Figure 28(c). The planar probe coaxial combiner consists of three sections, i.e.: 1) the N microstrip probes located on the same planar substrate, as shown in Figure 28(b); 2) the oversized coaxial waveguide with a short wall; and 3) the central standard coaxial connector to the oversized coaxial waveguide transition. The microstrip probes are inserted into the oversized coaxial waveguide along the radial direction, and the length of

 /4

the microstrip probe is normally about g . The axis of the oversized coaxial waveguide is perpendicular to the microstrip probe plane. The radii of both inner and outer conductors have been increased greatly to extend the space within the oversized coaxial waveguide, and to accommodate large numbers of microstrip probes that can implement multi-way power dividing/combining. A short wall

 /4

placed g beyond the microstrip probe plane presents an equivalent open circuit to the microstrip probe array. Obviously, in this type of power-combining structure, the microstrip probe array is designed on the same planar substrate and

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the relative locations between microstrip probes can be fixed accurately, which is easier in fabrication and assembly than these structures in the previous studies.

8a. Analysis of Coaxial Taper Transition To provide a smooth impedance match from the standard coaxial connector (type-SMA connector) to the oversized coaxial waveguide, an improved coaxial taper transition has been proposed, as shown in Figure 29(a). The inner conductor

a

(with a radius 0 ) of the SMA connector is inserted into the center of the gradual taper in order to provide a perfect electric connection. It can be noted that the inner and outer conductors of the coaxial taper transition have been tapered at two different planes rather than at the same plane, which can provide good impedance match. Based on the transmission-line theory, the equivalent circuit of the improved

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

coaxial taper transition can be developed, as shown in Figure 29(b), where Z L is the equivalent impedance of the oversized coaxial waveguide including the planar probe array. Apparently, the coaxial taper transition includes a dielectric discontinuity at plane A-A’, a step discontinuity at plane T-T’, and two gradual coaxial tapers with different lengths L1 and L2 . The outer and inner radii of the coaxial taper changes linearly. The coaxial taper of length L1 is between the plane B-B’ and the plane T-T’, and denoted as coaxial taper I, while the coaxial taper of length L2 is located at the right of plane T-T’, and denoted as coaxial taper II. So, the characteristic impedance ZT 2 ( x) of the coaxial taper II can be given by  b L  b  b1 x  ZT 2 ( x)  60 ln  1 2   a1L2  a  a1 x 

(23)

where b1  a0 

L1 b  b0  L1  L2 ,

and x is the position along the taper. According the equation (14) in section 3.2.3, the reflection coefficient of the coaxial taper II at x  0 is

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Kaijun Song

in 2 

1 L2  j 2 x d ln ZT 2 ( x) e dx  L 2 0 dx

(24)

where L is the reflection coefficient of the oversized coaxial waveguide including the planar probe array (with a input impedance Z L ) and will be analyzed later. For this one port network, the input impedance

Z in 2 can be given by

b  1  in 2 1  in 2 Z 02  60 ln  1  1  in 2 1  in 2  a1 

Z in 2 

(25)

So, the input impedance Z B is

ZB 

Zin 2 jB1Zin 2  1

(26)

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

where B1 is an equivalent capacitive reactance of the coaxial step discontinuity at plane T-T’ and can be obtained according to section 3.2.2. The reflection coefficient B can be given by

B 

by

Z B  Z 01 Z B  60 ln b1 a0   Z B  Z 01 Z B  60 ln b1 a0 

(27)

The characteristic impedance ZT 1 ( x) of the coaxial taper I can be calculated

 b L  b1  b0 x  ZT 1 ( x)  60 ln  0 2  a0 L1  

Similarly, the reflection coefficient given by

in1 

in1

(28)

of the coaxial taper I can also be

1 L1  j 2 x d ln ZT 1 ( x) e dx  B 2 0 dx

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(29)

Microwave and Millimeter-Wave Coaxial-Waveguide … Inner Conductor

A BT

A' B'

2a 2b

2b0 2a0

2b1

0

2a1

Outer Conductor

εr

87

T'

L2

L0 L L1 (a)

x

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Г0

Гin

ГB Гin2

Гin1

L0

L

L1

Z0

Z1

ZT1(x)

Zin

Zin1

ГL L2

jB 1

ZB

ZT2(x) ZL

Zin2

(b) Figure 29 (a). Coaxial taper transition circuit (b) Equivalent circuit of the coaxial taper transition.

Then, the input impedance

Zin1 

Z in1

is

b  1  in1 1  in1 Z1  60 ln  0  1  in1 1  in1  a0 

where Z1 is the characteristic impedance of the coaxial line with length L .

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(30)

88

Kaijun Song Then the characteristic impedance

Z in

is given by

Zin1  jZ1 tan  Z1  jZ in1 tan 

Zin  Z1

(31)

where   L . The coaxial line contains two different dielectric materials at the two sides of the plane T-T’, namely the air at the right of the plane T-T’ and the dielectric



materials with a dielectric constant r 0 at the left of the plane T-T’. Thus, there is a dielectric discontinuity at the plane T-T’, and the reflection coefficient at the dielectric interface on the

in 

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where So,

Z0

is

Z0  50

the

Z0

coaxial line is given as [44]

Zin  Z 0 Zin  60 ln b0 a0  /  r 0  Zin  Z 0 Zin  60 ln b0 a0  /  r 0

characteristic

Ω. When

impedance

L0  n  g / 2

of

the

type-SMA

(32) connector.

, then the input reflection coefficient

0  in 

Zin  50 Zin  50

0

is

(33)



It can be seen that the input reflection coefficient 0 of the coaxial taper transition can be determined according to the equations (23)-(33). Conversely, when the value of also be inverted.

0

is specified, the parameters of the coaxial taper model can

8b. Planar Probe Array The oversized coaxial waveguide with a planar probe array is shown in Figure 30(a), which has an air dielectric and inner and outer radii of a and b, respectively. The desired mode within the oversized coaxial waveguide is the dominant TEM mode, which has N-fold symmetry with respect to the coaxial line axis and no

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circumferential variations. The TEM electric field has an r–directed component only, and the magnetic field has a Ф-directed component only. When the N microstrip probes are identical and equispaced in the oversized coaxial waveguide, the electric field pattern within the coaxial combining structure still has N-fold symmetry with respect to the coaxial line axis, which results in perfect amplitude and phase balance of the N microstrip probes. In this design, the inner and outer radii of a and b are chosen so as to

ba  /4

g accommodate N microstrip probes radially. So, . Figure 30 (b) shows the single microstrip probe-to-coaxial waveguide (one N-th of the overall

oversized coaxial waveguide) transition, where   360 N . The one N-th of the overall oversized coaxial waveguide can be approximated by a rectangular waveguide separated by magnetic side walls (as shown in Figure 30 (b)). To keep the structure as compact as possible, the width of the equivalent rectangular waveguide is chosen to half of the width W of the standard rectangular waveguide, while the height of the equivalent rectangular waveguide is equal to the height H of the standard rectangular waveguide. The dimensions of the standard rectangular waveguide can be determined by the operation frequency. Thus, 

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b

NW 4

(34)

a bH

(35)

A short circuit is placed in the oversized coaxial waveguide a distance L4 from the plane of the microstrip probe array. Then, the distance L4 is

L4  g / 4

(36)

W0

To avoid the resonance in the operation frequency range, the width of the rectangular hole on the oversized coaxial waveguide has to be as small as possible. In this case,

W0  g / 4

W

. The height of the rectangular hole is equal to

h W / 2

0 about half of the width 0 , namely . Figure 30(c) shows the equivalent circuit of the single microstrip probe-to-coaxial waveguide transition. The input

impedance

Zm

of the transition is

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Kaijun Song

Z m  NZ 2

jZ p tan 3  tan  4   NZ 2 tan 3 tan  4 Z p 1  tan 3 tan  4   jNZ 2 tan  4

p p 3 ,  4  L4 ,and Z 2  60 ln b a  and p where 3 are the characteristic impedance of the oversized coaxial waveguide and the impedance

Z  R  jX

  L

of single microstrip probe, respectively;. Then the input impedance Z L can be given by

ZL  Z2

jZ p tan3  tan 4   NZ 2 tan3 tan 4 Z p 1  tan3 tan 4   jNZ 2 tan 4 h

ГL

(37)

W0 Ws

Z2

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2a 2b

Lr Lp

Wh

ZL

L3

L4

(a)

Magnetic wall

Wp

φ

Magnetic wall

(b) L3

L4

Z p=Rp+jX p

N Z2

Zm

(c) Figure 30. Oversized coaxial waveguide including the planar probe array. (a) Cross-section along the direction of wave propagation (b) single microstrip probe-to-coaxial waveguide transition (c) Equivalent circuit of the single microstrip probe-to-coaxial waveguide transition.

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For the microstrip probe design, the approach employed in the rectangular waveguide can be used [45]. Once the initial dimensions of the microstrip probe are obtained, the single microstrip probe-to-coaxial waveguide transition can be simulated and optimized with a field solver (such as Ansoft HFSS) to give the

Z

minimum of S11 in the desired frequency range, and the associated impedance p of single microstrip probe can also be obtained. So, the reflection coefficient L can be calculated as

L 

Z L  Z2 Z L  Z2

substituting in (24), the reflection coefficient

in 2

(38) can be obtained.

8c. Summary of the Total Design Procedure

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The total design procedure is as follows: 1) Design the dimensions of the oversized coaxial waveguide including the planar probe array. a) According to equations (34)-(36), the initial dimensions of the oversized coaxial waveguide can be determined. Keep (a+b) as small as possible to reduce higher order modes.

W  /4

h W / 2

g 0 b) The width 0 and the height of the rectangular hole on the oversized coaxial waveguide can be obtained according

W

the desired operation frequency. Keep 0 and h as small as possible to avoid the resonance. c) Design the microstrip probe using the approach employed in the rectangular waveguide [45]. d) Construct a field simulation model of the single microstrip probe-tocoaxial waveguide transition. Optimize the sizes of the structure to achieve a desired bandwidth and reflection coefficient. Obtain the optimized dimensions of the structure and the impedance single microstrip probe.

Zp

of

e) Calculate the reflection coefficient L from equations (37) and (38). Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

92

Kaijun Song 2) Design and optimize the coaxial taper transition in MATLAB to get the minimum of the reflection coefficient in the desired frequency range. a) According to the dimensions of the SMA connector，the initial dimensions and parameters of the standard coaxial connector (

a0 b0 ,

and

 r 0 ) can be obtained.

b) Substitute the reflection coefficient L in (24), and then the reflection



coefficient in 2 can be calculated. c) Using (231)-(33), the coaxial taper transition structure can be analyzed and optimized. Finally, the dimensions of the transition can be determined.

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8d. Simulated and Measured Results of the Ten-Way Planar Probe Coaxial Combiner Based on the design procedure given above, a ten-way planar probe coaxialwaveguide power combiner/divider was designed [43]. The power-dividing structure was simulated and optimized in Ansoft-HFSS. The fabricated structure is terminated by commercially available type-SMA connectors. Figure 31 shows the assembly and overview of the ten-way planar probe coaxial-waveguide power combiner.

(a)

(b)

Figure 31. Photograph of the fabricated ten-way planar probe power combiner/divider (a) Assembly (b) Overview.

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93

0 -5

S21

-10 -15

S11

(dB)

-20 -25 -30 -35 -40

Simulated results Measured results

-45 -50 9

10

11

12

13 14 15 16 Frequency (GHz)

17

18

19

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

Figure 32. Simulated and measured results of the proposed planar probe combiner.

The simulated and measured reflection results of the constructed combiner are shown in Figure 32, which also include the simulated insertion loss results. The measured insertion loss results are presented in Figure 33. Only insertion loss S21 is plotted in Figure 32 and the insertion losses between the port 1 and other ports are the same as S21 because of the N-fold symmetry with respect to the coaxial line axis. The measured and simulated 15-dB return loss bandwidths of the fabricated multiple-port structure are about 4.3 and 4.8 GHz, respectively. The simulated S21 is approximately 10 dB as expected for a ten-way divider. The difference between the simulated and measured results is most likely attributed to the fabrication and assembly errors, such as the coaxial taper transition and the polygonal hole in the substrate. Figure 33 shows the measured transmission coefficients of the planar probe combiner. It can be seen that, on average, the insertion loss is around 10.8 dB. A maximum amplitude imbalance of ±1 dB and a phase imbalance of ±5º are observed in the 11.5–16-GHz band, and an amplitude imbalance of ±1.5 dB and a phase imbalance of ±7º are observed in the 11–17-GHz band. The increased insertion loss is due to the peripheral microstrip line to coaxial type-SMA connector transition. This was not included in the simulation.

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Kaijun Song -5 -6

Transimission Sn1 (dB)

-7 -8 -9 -10 -11 -12 -13 -14 -15 11

12

13

14

15

16

17

Frequency (GHz)

(a) 180 120

Ф n1(deg)

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60 0 -60 -120 -180 11

12

13 14 15 frequency (GHz)

16

17

(b) Figure 33. Measured transmission coefficients of the planar probe combiner (n = 2; 3; . . . ; 11). (a) Amplitude. (b) Phase.

The simulated and measured isolation characteristics of the planar probe combiner are shown in Figure 22 where good agreement between the results is demonstrated. The isolation between the peripheral ports displayed includes S32, S42, S52, S62, and S72. S11,2, S10,2, S92, and S82 are the same as S32, S42, S52, and S62, respectively. It can be seen that, on average, the isolation is better

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than 10 dB, except for S32. It is noted that the worst isolation is between ports 2 and 3 (the adjacent ports), while the best isolation seems to be between the ports 2 and 5 (the ports which are interleaved by two ports), which isn’t consistent with the remarks made in [8, 9, 46] because of the different structures. 0 -5 -10

(dB)

-15 -20 -25 S32 S42 S52 S62 S72

-30 -35 -40 -45 9

10

11

12

13

14

15

16

17

18

19

Frequency (GHz)

0 -5 -10 -15 -20

(dB)

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

(a)

-25 -30

S32 S42 S52 S62 S72

-35 -40 -45 -50 -55 9

10

11

12

13

14

15

16

17

18

19

Frequency (GHz)

(b) Figure 34. Simulated and measured isolations of the planar probe combiner. (a) Simulated. (b) Measured.

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Kaijun Song

Coaxial probe

2rp

2r0 Lp

Ls

post

2R0 2r

2R1

2r1

Outer conductor

R

Inner conductor

Type N connector

L0

96

d Li

Lt

Lc

Lh

Type SMA connector

(a)

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Outer Conductor

Coaxial probe

Short-circuited post

Inner Conductor (b)

Figure 35. Structure of a UWB coaxial-waveguide power divider with rotated electric field mode: (a) Cross-sectional view along the length of the coaxial waveguide and (b) Cross sectional view of the coaxial waveguide.

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9. Ultra-Wideband (UWB) Coaxial Power Divider with Rotated Electric Field Mode According to the above studies, it can be noted that all of the probes have been inserted into the oversized coaxial waveguide along the radial. Then, the direction of the output ports for a power divider are not parallel with each other except for the ports located at the opposite sides of the divider, which makes it inconvenient to be used in active power-combining system. The proposed coaxialwaveguide power divider is illustrated in Figure 35. It can be noted that a stepped inner conductor in the oversized coaxial waveguide has been used, which can rotate the electric field orientation from the radial to axial. In this case, all of the output coaxial probes can be inserted into the oversized coaxial waveguide along the direction of axis (as shown in Figure 35(a)), and good impedance matching between the oversized coaxial waveguide and the coaxial probe array can be obtained. In addition, the direction of the output ports can be parallel and the same as each other. Compared with the above power-dividing structure, the proposed power-dividing structure may be easy to construct the active power-combining system. An active power-combining system (including the amplifiers) using the proposed coaxial-waveguide power dividing/ combining circuits is shown in Figure 36. The input signal is fed to the left input type-N connector, and then divided into N-equal signals (using the proposed coaxial-waveguide power divider), where each is parallelly fed to the input of an amplifier out of the oversized coaxial waveguide. These N-amplified signals are then collected by using a same structure as the coaxial-waveguide power divider to combine power to the right output type-N connector. By this design, it can be seen that the input and output ports are aligned, which can simplify the structure of the active powercombining system. The proposed coaxial power divider is terminated by commercially available type-N connector at the input port and the type-SMA connectors at the output ports. A coaxial taper transformer has been used to provide smooth impedance matching from the type-N connector to the oversized coaxial waveguide. The microwave signals have been coupled to four identical coaxial probes in the oversized coaxial waveguide, and have been equally divided to N-way signals output from type-SMA connectors with same magnitude and phase. For obtaining the UWB passband performance, the strong coupling between the coaxial probe array and the stepped inner conductor has been used. A short-circuited post placed

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Kaijun Song

about λg/4 beyond the coaxial probe presents an open circuit to the coaxial probe array. It is obvious that the input return loss can be mainly determined by the coaxial taper transformer from the type-N connector to the oversized coaxial waveguide when the oversized coaxial waveguide is match-terminated and can be minimized by the optimized coaxial taper transformer. Due to the symmetry of the power divider and a dominant mode excitation, an four-way coaxial-waveguide power divider can be viewed as a structure composed of four identical heteromorphic waveguides (each one includes a coaxial probe) separated by magnetic side walls. So the problem of matching the coaxial probe array in the oversized coaxial waveguide is confined to matching a coaxial probe in a heteromorphic waveguide with magnetic side walls, which is similar to the matching method in [11]. Finally, the dimensions of the proposed coaxialwaveguide power divider can be optimized by full-wave simulation tools (such as HFSS or CST).

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Type N connector

Outer Conductor

Inner Conductor

MMIC Amplifiers

type N Connector

Coaxial probes

Figure 36. Full sketch of the active power-combining system using the proposed coaxial power dividing/combining structure.

A UWB coaxial-waveguide four-way power divider has been designed. The coaxial-waveguide power divider was simulated and optimized in CST MICROWAVE STUDIO. Dielectric and conductor losses were included in the simulation. The photograph of the proposed UWB power divider is shown in Figure 37.

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(a)

99

(b)

Figure 37. Photograph of the fabricated coaxial-waveguide UWB power divider: (a) Assembly (b) Overview. 0

2.0 S21

1.8

-5

1.4

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

(dB)

-10

1.2

Simulated results Measured results

-15

1.0 0.8

S11

-20

0.6

Group delay (ns)

1.6

0.4

-25

0.2 -30 0

2

4 6 8 Frequency (GHz)

10

0.0 12

Figure 38. Simulated and measured scattering parameters and group delay.

Figure 38 shows the simulated and measured results of the fabricated UWB coaxial-waveguide power divider. The measured results included the influences of the SMA connector, N connector, and SMA to N adapter at the input port. The insertion loss S21 is displayed only, and the insertion loss S31，S41 and S51 are the same as S21 because of the symmetry of the structure. Measured and simulated results agree well at the entire UWB band, with the insertion loss exhibiting a value of approximately 6 dB as expected for a four-way power divider. The simulated and measured 10-dB return loss bandwidths and the 0.5-dB insertion loss bandwidths have all covered the entire UWB band, while the

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Kaijun Song

simulated and measured 20-dB return loss bandwidths were found to be approximately 6.7 GHz (from 3.5 to 10.2 GHz) and 7.1 GHz (from 3.5 to 10.8 GHz), respectively. The measured insertion loss of the four-way power divider can be as low as 0.2 dB within the UWB passband. It can also be seen from Figure 38 that the measured and simulated results have little disagreement in the upper passband, which is most likely attributed to the fabrication errors and the inaccuracies in assembly. In addition, the simulated and measured group delays show good linearity within the UWB passband, as shown in Figure 38. The measured group delay is about 0.22 ns at 6.85 GHz within a variation of only about 0.06 ns over the entail UWB band.

References [1]

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[2] [3] [4] [5]

[6] [7]

Song, K., Fan, Y. & Zhang, Y. (2008). Eight-Way Substrate Integrated Waveguide Power Divider with Low Insertion Loss, IEEE Trans. Microw. Theory Tech., vol. 56(6), 1473-1477. Song, K. & Fan, Y. (2009). Broadband travelling-wave power divider based on substrate integrated rectangular waveguide, Electron. Lett., vol. 45, (12), 631-632. Song, K., Fan, Y. & Zhou, X. (2008). X-Band Broadband Substrate Integrated Rectangular Waveguide Power Divider, Electron. Lett., vol. 44, (3), 211-213. Jin, H. & Wen, G. (2008). A Novel Four-Way Ka-Band Spatial Power Combiner Based on HMSIW, IEEE Micro. Wirel. Comp. Lett., vol. 18, (8), 515-517. Song, K., Fan, Y. & Zhang, Y. (2007). Design of Low-profile Millimeterwave Substrate Integrated Waveguide power divider/combiner, International Journal of Infrared and Millimeter Waves, vol. 28, (6), 473478. Song, K., Fan, Y. & Zhang, Y. (2006). Radial cavity power divider based on substrate integrated waveguide technology, Electron. Lett., Vol. 42, (19), 1100-1101. Moldovan, E., Bosisio, R. G. & Wu, K. (2006). W-Band Multiport Substrate-Integrated Waveguide Circuits, IEEE Trans. Microw. Theory Tech., vol. 54, (2), 625-632.

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Microwave and Millimeter-Wave Coaxial-Waveguide … [8] [9] [10] [11] [12] [13]

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

[14] [15] [16] [17] [18] [19] [20] [21]

101

de Villiers, D. I. L., van der Walt, P. W. & Meyer, P. (2008). Design of Conical Transmission Line Power Combiners Using Tapered Line Matching Sections,” IEEE Trans. Microw. Theory Tech., vol. 56, (6), 1478-1484. de Villiers, D. I. L., van der Walt, P. W. & Meyer, P. (2007). Design of a ten-way conical transmission line power combiner, IEEE Trans. Microw. Theory Tech., vol. 55, (2), 302-308. Song, K., Fan, Y. & Zhou, X. (2009). Broadband Radial Waveguide Power Amplifier Using a Spatial Power Combining Technique, IET Microwaves, Antennas & Propagation, vol. 3, (8), 1179-1185. Song, K., Fan, Y. & He, Z. (2008). Broadband radial waveguide spatial combiner, IEEE Micro. Wirel. Comp. Lett., vol. 18, (2), 73-75. Song, K., Fan, Y. & Zhou, X. (2008). Investigation of broadband power amplifier with high power-combining efficiency, Microwave and Optical Technology Letters, vol. 50, (8), 2178-2181. Song, K., Fan, Y. & Zhang, Y. (2007). Broad-band power divider based on radial waveguide, Microwave and Optical Technology Letters, vol. 49, (3), 595-597. Fathy, A. E., Lee, S. W. & Kalokitis, D. (2006). A simplified design approach for radial power combiners, IEEE Trans. Microw. Theory Tech., vol. 54, (1), 247-255. Song, K., Fan, Y. & Zhou, X. (2008). Broadband Multilayer In-Phase Power Divider, Electron. Lett., vol.44, (6), 417-419. Abbosh, A. M. (2008). Design of Ultra-Wideband Three-Way Arbitrary Power Dividers, IEEE Trans. Microw. Theory Tech., vol. 56, (1), 194-201. Wong, S. W. & Zhu, L. (2008). Ultra-Wideband Power Divider With Good In-Band Splitting and Isolation Performances, IEEE Microw. Wireless Compon. Lett., vol. 18, (8), 518-520. Bialkowski, M. E. & Abbosh, A. M. (2007). Design of a Compact UWB Out-of-Phase Power Divider, IEEE Microw. Wireless Compon. Lett., vol. 17, (4), 289-291. Judaschke, R., Hoft, M. & Schunemann, K. (2005). Quasi-Optical 150-GHz Power Combining Oscillator, IEEE Microw. Wireless Compon. Lett., vol. 15, (5), 300-302. Magath, T. (2004). Diffraction synthesis and experimental verification of a quasi-optical power splitter at 150 GHz, IEEE Trans. Mircow. Theory Tech., vol. 52, (10), 2385-2389. Magath, T., Hoft, M. & Judaschke, R. (2004). A two-dimensional quasioptical power combining oscillator array with external injection locking, IEEE Trans. Mircow. Theory Tech., vol. 52, (2), 567-572.

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[22] Ortiz, S., Hubert, J., Mirth, L. & etc. (2002). A high-power Ka-band quasioptical amplifier array, IEEE Trans. Microw. Theory Tech., vol. 50, 487494. [23] DeLisio, M. P. & York, R. A. (2002). Quasi-Optical and Spatial Power Combining, IEEE Trans. Microw. Theory Tech., vol. 50, (3), 929-936. [24] Chang K. & Sun, C. (1983). Millimeter-wave power-combining techniques, IEEE Trans. Microw. Theory Tech., MTT-31, 91-107. [25] Becker, J. P. & Oudghiri, A. M. (2005). A planar probe double ladder waveguide power divider, IEEE Microw. Wireless Compon. Lett., vol. 15, (3), 168-170. [26] Jiang, X., Ortiz, S. C. & Mortazawi, A. (2004). A Ka-band power amplifier based on the traveling-wave power-dividing/combining slotted-waveguide circuit, IEEE Trans. Microw. Theory Tech., vol. 52, (2), 633-639. [27] Jeong, J., Kwon, Y., Lee, S., Cheon, C. & Sovero, E. A. (2000). 1.6- and 3.3-W power-amplifier modules at 24 GHz using waveguide-based powercombining structures, IEEE Trans. Microwave Theory Tech., vol. 48, 27002708. [28] Cheng, N. S., Jia, P., Rensch, D. B. & York, R. A. (1999). A 120-W X-band spatially combined solid-state amplifier, IEEE Trans. Microw. Theory Tech., vol.47, (12), 2557-2561. [29] Sanada, A., Fukui, K. & Nogi, S. (1994). A waveguide type power divider/combiner of double-ladder multi-port structure, IEEE Trans. Microw. Theory Tech., vol. 42, (7), 1154-1161. [30] Alexanian, A. & York, R. A. (1997). Broadband Waveguide-Based Spatial Combiner, IEEE MTT-S Int. Microw. Symp. Dig., vo1.3, 1139-1142 [31] Jia, P. C., Chen, L. Y., Alexanian, A. & York, R. A. (2003). Broad-Band High-Power Amplifier Using Spatial Power-Combining Technique, IEEE Trans. Mircow. Theory Tech., vol. 51, (12), 2469-2475. [32] Jia, P. C., Chen, L. Y., Alexanian, A. & York, R. A. (2002). Multioctave Spatial Power Combining in Oversized Coaxial Waveguide, IEEE Trans. Microw. Theory Tech., vol. 50, (5), 1355-1360. [33] Jia, P. C. & York, R. A. (2001). A compact coaxial waveguide combiner design for broadband power amplifiers. IEEE MTT-S Int. Microw. Symp. Dig., 43-46. [34] Jia, P. C., Liu, Y., Chen, L. Y. & York, R. A. (2000). Analysis of a passive spatial combiner using tapered slotline array in oversized coaxial waveguide, IEEE MTT-S Int. Microw. Symp. Dig., 1933-1936.

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[35] Song, K., Fan, Y. & Zhang Y. (2007). Investigation of a power divider using a coaxial probe array in a coaxial waveguide, IET Microwaves, Antennas & Propagation, vol. 1, (4), 900-903. [36] Song, K., Fan, Y. & He, Z. (2007). Narrowband amplifier with excellent power combining efficiency, Electron. Lett., vol. 43, (13), 717-719. [37] Song, K., Fan, Y. & Zhou, X. (2009). Broadband millimetre-wave passive spatial combiner based on coaxial waveguide, IET Microwaves, Antennas & Propagation, vol. 3, (4), 607-613. [38] Marcuvitz, N. (1951). Waveguide handbook, New York, McGraw-Hill. [39] Pozar, D. M. (1998). Microwave Engineering, 2nd ed, New York, Wiley. [40] Klopfenstein, R. W. (1956). A transmission-line taper of improved design, Proc. IRE, vol. 442, 31-35. [41] Song, K., Fan, Y. & Zhang, Y. (2006). A Microstrip Probe Coaxial Waveguide Power Divider/Combiner, International Journal of Infrared and Millimeter Waves, vol. 27, (9), 1269-1279. [42] Song, K., Fan, Y. & Xue, Q. (2010). Millimeter-wave power amplifier based on coaxial-waveguide power-combining circuits, IEEE Micro. Wirel. Comp. Lett., (will be published in Jan. 2010. [43] Song, K. & Xue, Q. (2009). Planar Probe Coaxial-Waveguide Power Combiner/Divider, IEEE Trans. Microw. Theory Tech., vol. 57, (11), 27612767. [44] Rizzi, P. A. (1988). Microwave engineering passive circuits, Prentice Hall, 271. [45] Xue, Q. & Lin, W. G. (1995). Analysis on waveguide cross-section plane microstrip probe, Microwave and Optical Technology Letters, vol. 9, (4), 214-216. [46] Bialkowski, M. E. & Waris, V. P. (1993). Electromagnetic model of a planar radial-waveguide divider/combiner incorporating probes, IEEE Trans. Microw. Theory Tech., vol. 41, (6), 1126-1134.

Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved. Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

In: Circuit Analysis Editor: Virginia E. Wright, pp. 105-129

ISBN: 978-1-61728-106-8 © 2011 Nova Science Publishers, Inc.

Chapter 3

ANALYSIS OF FEEDBACK CIRCUITS USING MILLER'S TECHNIQUES V.C. Prasad* Faculty of Engineering and Technology , Multimedia University , 75450, Melaka , Malaysia Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

Abstract Miller's theorem is a popular tool to analyze electronic circuits. It is often used by assuming that closed loop voltage gain is approximately equal to open loop voltage gain. But nothing is known so far about the conditions under which this approximation works. This paper shows that Miller’s approximation is valid if the circuit without feedback possesses one of the following properties. (i) The forward current gain (h f) is large (ii) The reverse current gain (hr) is small in a certain sense (iii) Trans resistance gain is larger than output impedance and output impedance is small (iv) Trans conductance gain is larger than input admittance and input impedance is large (v) Reverse trans resistance gain is smaller than input impedance and input impedance is large (vi) Input impedance is large and output impedance is small (vii) Reverse trans conductance gain is smaller than output impedance and output impedance is small (viii) Input impedance is small and output impedance is large. Similar results are derived for Miller’s dual. This theorem is normally used for series feedback. It is well known that Miller’s theorem cannot be used to determine all parameters of the circuit. Contrary to this, a method is proposed to get all parameters using one Miller *

E-mail address: [email protected]. Retired from Indian Institute of Technology . Delhi , India.. [email protected].

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V.C. Prasad parameter only. An example is given to show that Miller’s dual works in some situations where Miller theorem fails to deliver.

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

I. Introduction Consider the network shown in Figure 1.1 (a). N is a black box which can be any linear network, for example, a single stage amplifier, a multistage amplifier or any other network with or without controlled and independent sources. ZF is feedback impedance which may be connected externally or it may be an unwanted impedance present in the circuit like a stray or junction capacitance. For ease of reference we will call it parallel feedback. RL and EL denote the Thevenin equivalent of the network to the right of N. Similarly V s and R s may refer to a voltage source or the Thevenin equivalent of the network to the left of N. ZF is replaced by two impedances Z1 and Z2 as shown in Figure 1.1(b) where Z1 = ZF (1 – h) and Z2 = Z F (1 – h-1) h =V2 / V1. This was originally used to a situation in which Vs is the only source in the entire network and N is a single stage amplifier. This is refered to as Miller's theorem and h is called Miller's parameter. This theorem is extremely popular in Analog Electronics [1 – 12]. It is often used to compute the voltage gain of the amplifier with feedback using the knowledge of the gain without feedback. Figures 1.1 (a) & (b) are equivalent and so Figure 1.1 (b) can be analyzed to determine voltage gain of Figure 1.1 (a). This is because the analysis of Figure 1.1 (b) is usually much simpler than that of Figure 1.1 (a). But the problem is that h is an unknown. One way to overcome this is to use an approximate value of h. Since the gain (h) of the amplifier without Z F is known,it can be used as an approximate value of h even when Z F is present. This is what Miller did on a vacuum tube amplifier [1]. Though this decision is somewhat arbitrary, it is fairly accurate in practice for the circuit considered by him. Now a days it is used to analyze transistor amplifiers also [2 – 7]. But it is well known that feedback changes gain and causes an error in Miller’s approximation. Recently Moura [11] carried out an analysis of this error. Thus it is necessary to know the conditions under which this error is small. It is well known that Miller's theorem can not be used to compute output impedance of such circuits[11]. Consequently Miller's theorem is often used to compute voltage gain only. It is not used to compute all parameters of the network.

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Analysis of Feedback Circuits Using Miller's Techniques

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(a) R

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R Z V

V1

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2

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E

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

L

L

2'

1'

(b) Fig. 1.1 (a) Given circuit with parallel feedback (b) Its Miller equivalent

circuit Figure 1.1. (a) Given circuit with parallel feedback (b) Its Miller equivalent.

In this paper we present conditions under which Miller's theorem works. We also enhance its applicability. In Section II we investigate the conditions under which the Miller impedance Z2 can be approximated by an open circuit (call it open circuit approximation). The well known voltage gain approximation (closed loop gain is approximately equal to the open loop voltage gain) is a special case of this. The problem of approximating Z 1 by an open circuit is also studied in this section. The conditions stipulate restrictions on properties of N (the network without feedback) like current gain, input and output impedances etc. The analysis is carried out for the general situation in which sources can be present any where. In this case h depends on two parameters one of which is decided by the independent sources. Both parameters do not depend on ZF. Therefore they are known from the knowledge of the circuit without feedback. Since the circuit

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properties have nothing to do with the location of the source, open circuit approximation can be used for Z1 or Z2 whether the source Vs is on the input side or load side. Consequently all parameters including output impedance of the network can be determined. The details are presented in Section III. R

S

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Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

L

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(a) R

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1'

(b) Fig. 1.2 (a) Given circuit with series feedback (b) Its equivalent circuit using Miller’s dual

2'

Figure 1.2. (a) Given circuit with series feedback (b) Its equivalent circuit using Miller’s dual.

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Analysis of Feedback Circuits Using Miller's Techniques

109

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Consider the network shown in Figure 1.2 (a) where N, Vs, Rs, R L and E L are same as in Figure 1.1 (a). ZF is a feedback impedance. We will refer to it as series feedback impedance. Z F can be replaced by two impedances Z1 and Z2 as shown in Figure l.2 (b).They are given by Z1 = Z F (1 + k) and Z2 = ZF (1 + k-1) where k = I2/I1. This is called Miller's dual.[2,8]. This was first proposed by Millman and Halkias [2]. Similar to Miller's theorem, the current gain k with feedback is approximated by the current gain without feedback (Replace ZF by a short circuit). We will call this current gain approximation.This is true if Z2 can be approximated by a short circuit and Vs is the only source in the entire network. Conditions are derived in Section IV under which this approximation is valid. Conditions for short circuit approximation for Z1 are also derived in this section.Normally current gain approximation is not valid when the source is on the load side. This is however not a problem for the techniques presented here because our conditions do not depend on the location of the source.Thus it is possible to determine all parameters using the new method. The details are given in Section IV.It is also illustrated that in some situations it may be better to use Miller's dual than Miller's theorem although the use of Miller's theorem is obvious and Miller's dual is not an obvious choice. Section V summarizes the contributions of this paper.

II. Open Circuit Approximation Using Circuit Properties: Parallel Feedback Impedance Consider the black box N of Figure 1.1(a). Assume that it is represented by the hybrid equations given by V1 =h i Il + hrV2 + El

(2.1)

I2 = hfIl + h0 V2 + J2

(2.2)

Where E1 and J2 are required to account for independent sources in N. Replacing N by the equivalent circuit generated from these equations, the network of Figure 2.1 will be obtained. Let yF = 1/ZF. Some equations of Figure 2.1 are IS = I1 + (V1 – V0) yF

(2.3)

IL = hfI1 + h0V0 + J2 + (V0 - V1) yF

(2.4)

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V.C. Prasad IL - hfIs = (V0 - V1)yF (1 + hf) + h0V0 + J2

(2.5)

≈ (V0 - V1) yF. hf + h0V0 + J2if | h f | >>1. Solve for (V 0 - V 1) y F, substitute into equation (2.3) and simplify. This gives IL = hfI1 + h0V0 + J2. Let h = V0/V1 and Z1 = ZF/(1 – h) and Z2 = ZF / (1 - h 1 ).Then V 0 / Z 2 = (V0 - V1) y F, V 1 / Z 1 = (V 1 – V 0) y F. Z 1 and Z 2 are Miller impedances. This proves the following statement. Fact 2.1 : Z 2 can be replaced by an open circuit approximately if | h f | > > 1. V0 = E L – I LRL = EL -RL(hf I1 + J2) -h0 RL V0 if Z2 = 8. Using eqn. (2.1), we get

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

V0 ( l + h 0 R L -

RL hr ) _________ hi

Thus V0 is of the form The Miller parameter R

=

E L - R LJ 2 + R L h f E 1 - R L h f V1 _________ _________ hi hi

V0= k 2 + k1V1. h=k1 + k2 / V1

S

IS

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I F

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_

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L

_ + E _1

h

f

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h0

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Fig.2.1. 2.1 : Network Network withwith parallel feedback impedance Z Figure parallel feedback impedance Z. F

Note that this derivation of h assumes that the source is at port 1 (input port). Fact 2.1 guarantees that Z 2 can be approximated by infinity even when Z F is Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

Analysis of Feedback Circuits Using Miller's Techniques

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present provided |hf| >> 1. It does not guaranty that Z 1 is infinity if feedback is there. Consequently V1 with and without ZF will be different .i.e., voltage gain approximation is not true even if Z 2 is infinity. On the other hand if E 1, J 2 and E L are zero, then k 2 is zero. Then voltage gain approximation is true if Z 2 is infinity. This proves the following. Fact 2.2 : Voltage gain approximation is true with the source V s at port 1 if (i) open circuit approximation is true for Z 2 and (ii) V s is the only independent source in the network

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Remarks : 2.1) In view of this, Miller's argument (i.e., using open loop gain as an approximation of closed loop gain) can not be used if there are multiple sources in the network. But open circuit approximation for the impedance can be used. Further voltage gain approximation depends upon the location of the source V s whereas open circuit approximation is independent of the location of the source. Thus open circuit approximation is more general than voltage gain approximation for analysis of feedback circuits. 2.2) For a common emitter transistor amplifier circuit, h f > > 1 and V s is the only source. Therefore the usual procedure of approximating the Miller parameter h by open loop voltage gain is valid. Now assume that | h f | < < 1. Then from eqn. (2. 5), (V0 –V1)yF = IL - hf Is - h0V0 - J2. Substitute into eqn.(2. 4) and simplify. This gives I s = I we have the following observation.

1.

i.e., Z 1 = 8. Thus

Fact 2.3: Open circuit approximation is true for Z 1 if | h f | 1 . Proceeding as above ( V1 - V

0

)y F = -

IsΔ ______ hr

- I L + h0Vl ______ hr

+

Δ J1 _____ hr

Substitute into eqn.(2. 9) and simplify. This gives I S = I 1. i.e., Z 1 = ∞ Fact 2.5: Open circuit approximation is valid for Z 1 if | h r / Δ | > > 1. Remark 2.5 : | h r / Δ | >> 1 implies h r > hi h0 / (1 +h f). For a CE amplifier h0 is negligible and h r is also small. Therefore Z 1 = ∞ approximation is not possible. On the other hand h r < hi h0 / (1 +h f) is possible. i.e., Z 2 = ∞ is possible. Note that this does not necessarily mean that h f > > 1.

Circuit Analysis, Nova Science Publishers, Incorporated, 2010. ProQuest Ebook Central,

Analysis of Feedback Circuits Using Miller's Techniques Z R

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Fig. 2.2 : Trans resistance network with parallel feedback . Figure 2.2. Trans resistance network with parallel feedback.

Copyright © 2010. Nova Science Publishers, Incorporated. All rights reserved.

The above arguments used I 2 and I 1. This is more suitable when the input and output are current signals. Let us now consider other possibilities. We will derive these along the lines of the proof of Facts 2.1 & 2.3.Results can be derived using the strategies of Facts 2.4 and 2.5 also. Thus consider a trans resistance circuit shown in Figure 2.2. From the figure, V 0 = Rm I1 + R 0 I2 + E2

(2.10)

Using equations (2.3) & (2. 9) R m Is + R0 IL = (V0 - E2) + (V 1 – Vo)yF(Rm – R0).

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Fig. 2.3 : Trans conductance network with parallel feedback impedance Z

_

Figure 2.3. Trans conductance network with parallel feedback impedance ZF.

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Let R m >>R0.Then R m - R 0 ≈ R m. Solve for (V 1 - V 0)yF, substitute into eqn.(2. 3) and simplify using eqn. (2. 10). This gives I L = I 2. If R m < < R0, compute (V 1 - V0) y F, substitute into eqn. (2. 9) and simplify. This gives I s = I 1 Fact 2.6: Open circuit approximation is valid for Z 2 (Z 1)if R m > > R 0 (R m < < R 0) Remark 2.6: Since the output is a voltage, R 0 has to be small. Thus R m > > R 0 is a reasonable condition. Next consider a network in which the input is a voltage and output is a current signal. It is shown in Figure 2.3. From the figure V1= I1 R i + R r I 2 + E l

(2.11)

I2 = g m V1 + V0 / R0 + J2

(2.12)

Substitute for V 1 using eqn. (2. 11) I2(1 - g m Rr) = g m Ri I 1 + V0 / R0 + (J 2 + g m E 1)

(2.13)

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From eqns.(2. 3) & (2.9) -gm Ri Is + (1–gm Rr)IL = V0/ R0 + (J2 +gm El)+ (V0 – V1) yF (1 – gm Rr + gm RL) Assume that g m R i >>| 1 - g m R r |. Solve for (V 0- V 1) y F , substitute into eqn.(2.3) and simplify. This gives Z 2 = ∞. If g m R i < < | 1 - g m R r |, neglect g m R i, compute (V0 - V1) y F , substitute in eqn.(2. 9) and simplify. This gives I S = I 1 i.e., Z 1 = ∞ . This gives the following statement. Fact 2.7: Open circuit approximation is valid for Z2 (Z1) if Ri + Rr >>1/gm. (Ri + Rr < < 1 /g m). Finally consider the network shown in Figure 2.4. Both input and output are voltage signals V 1=R i I l+ A r V0 + E l

(2.14)

V0 = R 0 I 2 + A f V 1 + E 2

(2.15)

I s = gi V1 -gi Ar V0 - g i E 1 + (V 1 - V0)yF

(2.16)

I L= - A f g0 V 1 + g0 V0 - g0 E 2 + (V0 - V 1 ) y F

(2.17)

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gi IL+ Af g0Is = gi g0V0 - Af g0 gi ArV0 + (V0–V1)yF(gi –Af g0) - gi g0 E2 – Af gi g0 E1 Let A f g 0 > > g i. Calculate (V 0 – V 1) y F , substitute into eqn.(2.16) and simplify. This gives Z 2 =∞. If A f g 0 < < g i , we can prove similarly that Z 1 = ∞. This gives the following observation. Fact 2.8: Open circuit approximation is valid for Z2 (Z1) if Af >> R0 / Ri ( A f