Chiplet Design and Heterogeneous Integration Packaging 9811999163, 9789811999161

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John H. Lau

Chiplet Design and Heterogeneous Integration Packaging

Chiplet Design and Heterogeneous Integration Packaging

John H. Lau

Chiplet Design and Heterogeneous Integration Packaging

John H. Lau Research and Development Unimicron Technology Corporation Palo Alto, CA, USA

ISBN 978-981-19-9916-1 ISBN 978-981-19-9917-8 (eBook) https://doi.org/10.1007/978-981-19-9917-8 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Preface

There are at least five different chiplet design and heterogeneous integration packaging, namely (1) chip partition and heterogeneous integration (driven by cost and technology optimization), (2) chip split and heterogeneous integration (driven by cost and semiconductor manufacturing yield), (3) multiple system and heterogeneous integration with thin-film layer directly on top of a build-up package substrate (2.1D IC integration), (4) multiple system and heterogeneous integration with throughsilicon via (TSV)-less interposer (2.3D IC integration), and (5) multiple system and heterogeneous integration with TSV interposers (2.5D and 3D IC integration). In chip partition and heterogeneous integration, the system-on-chips (SoCs), such as the logic and I/Os, are partitioned into functions: logic and I/O. These chiplets can be stacked (integrated) by the front-end chip-on-wafer (CoW) or wafer-on-wafer (WoW) methods and then assembled (integrated) on the same substrate of a single package by using the heterogeneous integration technique. It should be emphasized that the front-end chiplets’ integration can yield a smaller package area and better electrical performance but is optional. In chip split and heterogeneous integration, the SoC, such as logic, is split into smaller chiplets, such as logic1, logic2, and logic3. These chiplets can be stacked (integrated) by the front-end CoW or WoW methods and then assembled on the same substrate of a single package by using the heterogeneous integration technique. Again, the front-end integration of chiplets is optional. In multiple system and heterogeneous integration with thin-film layers directly on top of the build-up package substrate, the SoC such as the central processing unit (CPU), logic, and high-bandwidth memory (HBM) are supported by a buildup package substrate with thin-film layers. This is driven by performance and form factor and for high-density and high-performance applications. In multiple system and heterogeneous integration with TSV-less interposers, the SoC such as the CPU, logic, and HBM are supported by a fine metal line width (L) and spacing (S) redistribution-layer (RDL)-substrate (organic interposer) and then on a build-up package substrate. This is driven by performance and form factor and for high density and performance applications.

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In multiple system and heterogeneous integration with TSV-interposers, the SoC such as the CPU, logic, and HBM are supported by a passive (2.5D) or active (3D) TSV-interposer and then on a build-up package substrate. This is driven by performance and form factor and for extremely high-density and high-performance applications. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for yield, cost, time-to-market, performance, form factor, or power consumption. Unfortunately, for most of the practicing engineers and managers, as well as scientists and researchers, these chiplet design and heterogeneous integration packaging methods are not well understood. Thus, there is an urgent need, both in industry and research institute, to create a comprehensive book on the current state of knowledge of these chiplet design and heterogeneous integration packaging technologies. This book is written so that readers can quickly learn about the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions. There are six chapters in this book, namely (1) State-of-the-Art of Advanced Packaging, (2) Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration, (3) Multiple System and Heterogeneous Integration with TSVInterposers, (4) Multiple System and Heterogeneous Integration with TSV-Less Interposers, (5) Chiplets Lateral Communications, and (6) Cu-Cu Hybrid Bonding. Chapter 1 presents the recent advances and trends in semiconductor advanced packaging. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance and are grouped into 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, which will be presented and discussed. Fan-in packaging, such as the six-sided molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP are presented. Fan-out packaging such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference will be provided. Chapter 2 presents the chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration and (b) chip split and heterogeneous integration. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. System-on-chip (SoC) and Defense Advanced Research Projects Agency’s (DARPA) efforts in chiplet heterogeneous integration will be briefly mentioned first. Chapter 3 details the recent advances in multiple system and heterogeneous integration with passive/active TSV interposers. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and many examples of multiple system and heterogeneous integration with TSV-interposer. Also, some recommendations will be provided. Chapter 4 presents the recent advances in multiple system and heterogeneous integration with TSV-less interposers (2.3D IC integration). Some of the challenges (opportunities) of 2.3D IC integration (organic interposer) will also be presented. Some recommendations of 2.3D IC integration will be provided. Finally, characterization of low-loss dielectric materials for organic interposer will be presented. Some

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fundamentals and recent advances in fan-out technology will be briefly mentioned first. Chapter 5 presents the lateral (horizontal) communications (bridges) between chiplets. Various kinds of bridges such as the ridge bridges embedded in build-up package substrate and those embedded in fan-out epoxy molding compound, and the flexible bridges will be presented. UCIe will also be briefly mentioned. Chapter 6 presents the recent advances and trends in Cu-Cu hybrid bonding. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of Cu-Cu bumpless hybrid bonding. Also, some recommendations will be provided. The direct Cu-Cu thermocompression bonding (TCB) and direct SiO2 -SiO2 TCB will be briefly mentioned first. For whom is this book intended? Undoubtedly it will be of great interest to three groups of specialists: (1) those who are active or intend to become active in research and development of chiplet design and heterogeneous integration packaging, (2) those who have encountered practical chiplet design and heterogeneous integration packaging problems and wish to understand and learn more methods for solving such problems; and (3) those who have to choose a reliable, creative, high performance, high density, low power consumption, and cost-effective technique for their products. This book can also be used as a text for college and graduate students who have the potential to become our future leaders, scientists, and engineers in the electronics and optoelectronics industry. I hope that this book will serve as a valuable reference source for all those faced with the challenging problems created by the ever-increasing interest in chiplet design and heterogeneous integration packaging. I also hope that it will aid in stimulating further research and development on key enabling technologies and more sound applications to chiplet design and heterogeneous integration packaging products. The organizations that learn how to design and manufacture chiplet design and heterogeneous integration packaging in their semiconductor packaging systems have the potential to make major advances in the electronics and optoelectronics industry, and to gain great benefits in cost, performance, functionality, density, power, bandwidth, quality, size, and weight. It is my hope that the information presented in this book may assist in removing roadblocks, avoiding unnecessary false starts, and accelerating design, materials, process, and manufacturing development of chiplet design and heterogeneous integration packaging. Palo Alto, CA, USA

John H. Lau

Acknowledgments

Development and preparation of semiconductor advanced packaging were facilitated by the efforts of a number of dedicated people. I would like to thank them all, with special mention of Kumar Boominathan and Satish Ambikanithi, Springer Nature Scientific Publishing Services (P) Ltd., for their unswerving support and advocacy. My special thanks go to Ms. Jasmine Dou, Springer Singapore, who made my dream of this book come true by effectively sponsoring the project and solving many problems that arose during the book’s preparation. It has been a great pleasure and fruitful experience to work with all of them in transferring my messy manuscripts into a very attractive printed book. The material in this book clearly has been derived from many sources, including individuals, companies, and organizations, and I have attempted to acknowledge by citations in the appropriate parts of the book the assistance that I have been given. It would be quite impossible for me to express my thanks to everyone concerned for their cooperation in producing this book, but I would like to extend due gratitude. Also, I would like to thank several professional societies and publishers for permitting me to reproduce some of their illustrations and information in this book, including the American Society of Mechanical Engineers (ASME) conference proceedings (e.g., International Intersociety Electronic Packaging Conference) and transactions (e.g., Journal of Electronic Packaging), the Institute of Electrical and Electronics Engineers (IEEE) conference proceedings (e.g., Electronic Components and Technology Conference and Electronics Packaging and Technology Conference) and transactions (e.g., Components, Packaging, and Manufacturing Technologies), and the International Microelectronics and Packaging Society (IMAPS) conference proceedings (e.g., International Symposium on Microelectronics), and transactions (e.g., International Journal of Microcircuits and Electronic Packaging). I would like to thank my former employers, ASM (HK), Industrial Technology Research Institute (ITRI), the Hong Kong University of Science and Technology (HKUST), the Institute of Microelectronics (IME), Agilent, and HP, for providing me with excellent working environments that have nurtured me as a human being, fulfilled my need for job satisfaction, and enhanced my professional reputation. Also,

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I would like to thank Dr. Don Rice (HP), Dr. Steve Erasmus (Agilent), Prof. DimLee Kwong (IME), Prof. Ricky Lee (HKUST), Dr. Ian Yi-Jen Chan (ITRI), and Mr. Lee Wai Kwong (ASM) for their kindness and friendship while I was at their organizations. Furthermore, I would like to thank Mr. Tzyy-Jang Tseng (Chairman of Unimicron Technology Corporation) for his trust, respect, and support of my work at Unimicron. Finally, I would like to thank the following colleagues for their stimulating discussions and significant contributions to this book: T. C. Chai, L. Chang, H. Chang, P. Chang, Y. Chang, Y. Chao, E. Charn, C. Chen, G. Chen, J. Chen, S. Chen, R. Cheng, Y. Cheng, C. Chien, H. Chien, R. Chou, J. Cline, Y. Fang, H. Fu, Z. Hsiao, Y. Hsin, Y. Hsu, J. Huang, Y. Huang, M. Kao, N. Khan, C. T. Ko, V. Kripesh, T. Ku, C.-K. Lee, P. Lee, T. Lee, V. Lee, Y. Lee, M. Li, E. Liao, L. Liao, S. Lim, B. Lin, C. Lin, E. Lin, N. Liu, W. Lo, M. Ma, R. Nagarajan, C. Peng, P. Peng, V. Rao, K. Saito, R. Tain, W. Tsai, T. Tseng, P.-J. Tzeng, J. Wang, H. We, C. Wu, S. Wu, T. Xia, C. Yang, K. Yang, C. Zhan, and X. Zhang. Definitely, I would like to thank my eminent colleagues (the enumeration of whom would not be practical here) at Unimicron, ASM, ITRI, HKUST, IME, Agilent, EPS, HP, and throughout the electronics industry for their useful help, strong support, and stimulating discussions. Working and socializing with them has been a privilege and an adventure. I learned a lot about life and chiplet design and heterogeneous integration packaging from them. Lastly, I would like to thank my daughter Judy and my wife Teresa for their love, consideration, and patience by allowing me to work peacefully on this book. Their simple belief that I am making a contribution to the electronics industry was a strong motivation for me. Thinking that Judy and her supportive husband (Bill) have been doing very well in the electronics industry and their two adorable kids (Allison and James) have been raising in a happy and loving environment, and Teresa and I are in good health, I want to thank God for His generous blessings. Palo Alto, CA, USA

John H. Lau

Contents

1 State-Of-The-Art of Advanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Flip-Chip Bumping and Bonding/Assembly . . . . . . . . . . . . . . . . . . . 1.2.1 Flip-Chip Bumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Flip-Chip Bonding/Assembly . . . . . . . . . . . . . . . . . . . . . . . 1.3 Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Some Fundamental on Hybrid Bonding . . . . . . . . . . . . . . 1.3.2 Sony’s CIS with Hybrid Bonding . . . . . . . . . . . . . . . . . . . 1.3.3 TSMC’s Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.4 Intel’s Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.5 SK Hynix’s Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . 1.4 2D IC Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 2.1D IC Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Thin-Film Layers on Package Substrates . . . . . . . . . . . . . 1.5.2 Fine Metal L/S RDL Bridge Embedded in Organic Package Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 Fine Metal L/S RDL Bridge Embedded in Fan-Out EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 Fine Metal L/S RDL Flexible Bridge . . . . . . . . . . . . . . . . 1.6 2.3D IC Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 SAP/PCB Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 Fan-Out with Chip-First Method . . . . . . . . . . . . . . . . . . . . 1.6.3 Fan-Out with Chip-Last Method . . . . . . . . . . . . . . . . . . . . 1.7 2.5D IC Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.1 AMD/UMC’s 2.5D IC Integration . . . . . . . . . . . . . . . . . . . 1.7.2 NVidia/TSMC’s 2.5D IC Integration . . . . . . . . . . . . . . . . . 1.7.3 Some Recent Advances in 2.5D IC Integration . . . . . . . . 1.8 3D IC Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1 3D IC Packaging (Without TSVs) . . . . . . . . . . . . . . . . . . . 1.8.2 3D IC Integration (with TSVs) . . . . . . . . . . . . . . . . . . . . . . 1.9 Chiplet Design and Heterogeneous Integration Packaging . . . . . . .

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1.9.1 1.9.2

System on Chip (SoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.3 Advantages and Disadvantages . . . . . . . . . . . . . . . . . . . . . 1.9.4 Xilinx’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.5 AMD’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.6 CEA Leti’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.7 Intel’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.8 TSMC’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 Fan-In Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.1 Six-Side Molded WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.2 Reliability of WLCSP: Conventional Versus Six-Side Molded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11 Fan-Out Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12 Dielectric Materials for Advanced Packaging . . . . . . . . . . . . . . . . . . 1.12.1 Why Need Low Dk and Df Dielectric Materials? . . . . . . 1.12.2 Why Need Low CTE Dielectric Materials? . . . . . . . . . . . 1.13 Summary and Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 DARPA’s Efforts in Chipet Heterogeneous Integration . . . . . . . . . . 2.3 SoC (System-On-Chip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Chiplet Design and Heterogeneous Integration Packaging . . . . . . . 2.5 Advantages and Disadvantages of Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . 2.6 Xilinx’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 AMD’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Intel’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 TSMC’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Graphcore’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 CEA-LETI’s Chiplet Design and Heterogeneous Integration Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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2.12 UCIe (Universal Chiplet Interconnect Express) . . . . . . . . . . . . . . . . 126 2.13 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3 Multiple System and Heterogeneous Integration with TSV-Interposers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Through-Silicon Via (TSV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Tiny Vias on a Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 TSV (Via-First Process) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 TSV (Via-Middle Process) . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 TSV (Via-Last from the Front-Side Process) . . . . . . . . . . 3.2.5 TSV (Via-Last from the Back-Side Process) . . . . . . . . . . 3.3 Passive TSV-Interposers Versus Active TSV-Interposers . . . . . . . . 3.4 Active TSV-Interposer Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration) . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 UCSB/AMD’s Multiple System and Heterogeneous Integration with Active TSV-Interposer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Intel’s Multiple System and Heterogeneous Integration with Active TSV-Interposers . . . . . . . . . . . . . 3.5.3 AMD’s Multiple System and Heterogeneous Integration with Active TSV-Interposers . . . . . . . . . . . . . 3.5.4 CEA-Leti’s Multiple System and Heterogeneous Integration with Active TSV-Interposers . . . . . . . . . . . . . 3.6 Passive TSV-Interposer Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Fabrication of TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Fabrication of RDLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Fabrication of RDLs: Polymer + Cu-Plating and Etching Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 Fabrication of RDLs: SiO2 + Cu Damascene and CMP Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5 A Note on Contact Aligner for Cu Damascene Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6 Backside Processing and Assembly . . . . . . . . . . . . . . . . . . 3.7 Multiple System and Heterogeneous Integration with Passive TSV-Interposers (2.5D IC Integration) . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 CEA-Leti’s SoW (System-on-Wafer) . . . . . . . . . . . . . . . . 3.7.2 TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) . . . . . . . 3.7.3 Xilinx/TSMC’s Multiple System and Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . 3.7.4 Altera/TSMC’s Multiple System and Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . .

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3.7.5

3.8

AMD/UMC’s Multiple System and Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.6 NVidia/TSMC’s Multiple System and Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . 3.7.7 TSMC’s Multiple System and Heterogeneous Integration with DTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.8 Samsung’s Multiple System and Heterogeneous Integration with Integrated Stack Capacitor (ISC) . . . . . 3.7.9 Graphcore’s Multiple System and Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.10 Fujitsu’s Multiple System and Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.11 Samsung’s Multiple System and Heterogeneous Integration (I-Cube4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.12 Samsung’s Multiple System and Heterogeneous Integration (H-Cube) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.13 Samsung’s Multiple System and Heterogeneous Integration (MIoS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.14 IBM’s Multiple System and Heterogeneous Integration (TCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.15 IBM’s Multiple System and Heterogeneous Integration (Hybrid Bonding) . . . . . . . . . . . . . . . . . . . . . . . 3.7.16 Multiple System and Heterogeneous Integration of EIC and PIC (Side-by-Side) . . . . . . . . . . . . . . . . . . . . . . 3.7.17 Multiple System and Heterogeneous Integration of EIC and PIC (3D Stacked) . . . . . . . . . . . . . . . . . . . . . . . 3.7.18 Fraunhofer’s Multiple System and Heterogeneous Integration with Glass-Interposer . . . . . . . . . . . . . . . . . . . . 3.7.19 Fujitsu’s Multiple System and Heterogeneous Integration with Glass-Interposer . . . . . . . . . . . . . . . . . . . . 3.7.20 Dai Nippon/AGC’s Multiple System and Heterogeneous Integration with Glass-Interposer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.21 GIT’s Multiple System and Heterogeneous Integration with Glass-Interposer . . . . . . . . . . . . . . . . . . . . 3.7.22 Leibniz University Hanover/Ulm University’s Electroless Glass Interposer . . . . . . . . . . . . . . . . . . . . . . . . 3.7.23 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . Heterogeneous Integration with Stacked TSV Interposers . . . . . . . 3.8.1 Module Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 Thermo-Mechanical Design . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 Carrier Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 Thin Wafer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.5 Module Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.6 Module Reliability Assessment . . . . . . . . . . . . . . . . . . . . .

162 163 163 166 167 167 168 168 170 170 171 172 173 174 175

176 176 177 178 181 181 181 182 187 187 190

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3.8.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . Multiple System and Heterogeneous Integration with TSV Interposers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 The Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 TSV Etching and CMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 Thermal Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.4 Thin-Wafer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.5 Microbumping, C2W Assembly, and Reliability Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.6 Failure Mechanism of 20 µm Pitch Micro Solder Joints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.7 Electromigration in Solder Micro Joints . . . . . . . . . . . . . . 3.9.8 Final Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.9 Leakage Current Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.10 Thermal Simulation and Measurement of the Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.11 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 3.10 Multiple System and Heterogeneous Integration with Chips on Both-Side of TSV Interposers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 The Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 Thermal Analysis—Boundary Conditions . . . . . . . . . . . . 3.10.3 Thermal Analysis—TSV Equivalent Model . . . . . . . . . . . 3.10.4 Thermal Analysis—Solder Bump/Underfill Equivalent Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.5 Thermal Analysis—Results . . . . . . . . . . . . . . . . . . . . . . . . 3.10.6 Thermomechanical Analysis—Boundary Conditions . . . 3.10.7 Thermomechanical Analysis—Material Properties . . . . . 3.10.8 Thermomechanical Analysis—Results . . . . . . . . . . . . . . . 3.10.9 Fabrication of the TSV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.10 Fabrication of the Interposer with Topside RDLs . . . . . . 3.10.11 TSV Reveal of the Cu-Filled Interposer with Topside RDLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.12 Fabrication of the Interposer with Bottom-Side RDLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.13 Passive Electrical Characterization of the Interposer . . . 3.10.14 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.15 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 3.11 Multiple System and Heterogeneous Integration with Through-Silicon Hole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.1 Electrical Simulation and Results . . . . . . . . . . . . . . . . . . . 3.11.2 Test Vehicle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.3 Top Chip with UBM/PAD and Cu Pillar . . . . . . . . . . . . . . 3.11.4 Bottom Chip with UBM/Pad/Solder . . . . . . . . . . . . . . . . . 3.11.5 TSH Interposer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.6 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xv

192

3.9

192 192 195 198 199 200 203 204 206 206 208 213 214 215 216 216 217 218 221 223 223 224 227 230 230 233 234 235 240 242 243 244 246 247 248

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3.11.7 Reliability Assessments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 3.11.8 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 253 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 4 Multiple System and Heterogeneous Integration with TSV-Less Interposers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Fan-Out Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Chip-First with Die Face-Down . . . . . . . . . . . . . . . . . . . . . 4.2.2 Chip-First with Die Face-Up . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Die Shift Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Warpage Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Chip-Last (RDL-First) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Heterogeneous Integration of EIC and PIC Devices . . . . 4.2.7 Antenna-In-Package (AiP) . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Patent Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 2.3D IC Integration with Fan-Out (Chip-First) Packaging . . . . . . . 4.4.1 Fan-Out (Chip-First) Packaging . . . . . . . . . . . . . . . . . . . . . 4.4.2 STATSChipPac’s 2.3D eWLB (Chip-First) . . . . . . . . . . . 4.4.3 MediaTek’s Fan-Out (Chip-First) . . . . . . . . . . . . . . . . . . . 4.4.4 ASE’s FOCoS (Chip-First) . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.5 TSMC’s InFO_oS and InFO_MS (Chip-First) . . . . . . . . . 4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging . . . . . . . . 4.5.1 NEC/Renesas’ Fan-Out (Chip-Last or RDL-First) Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Amkor’s SWIFT (Chip-Last) . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 Samsung’s Si-Less RDL Interposer (Chip-Last) . . . . . . . 4.5.4 TSMC’s Multilayer RDL Interposer (Chip-Last) . . . . . . 4.5.5 ASE’s FOCoS (Chip-Last) . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.6 SPIL’s Large Size Fan-Out Chip-Last 2.3D . . . . . . . . . . . 4.5.7 Shinko’s 2.3D Organic Interposer (Chip-Last) . . . . . . . . . 4.5.8 Samsung’s Cost-Effective 2.3D Packaging (Chip-Last) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.9 Unimicron’s 2.3D IC Integration (Chip-Last) . . . . . . . . . 4.6 Other 2.3D IC Integration Structures . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Shinko’s Coreless Organic Interposer . . . . . . . . . . . . . . . . 4.6.2 Intel’s Knights Landing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 Cisco’s Coreless Organic Interposer . . . . . . . . . . . . . . . . . 4.6.4 Amkor’s SLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.5 Xilinx/SPIL’s SLIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.6 SPIL’s NTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.7 Samsung’s TSV-Less Interposer . . . . . . . . . . . . . . . . . . . . 4.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 2.3D IC Heterogeneous Integration with ABF . . . . . . . . . . . . . . . . . 4.8.1 The Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

271 271 274 275 275 278 279 279 284 284 285 286 286 286 286 286 288 289 289 290 291 292 294 295 295 296 297 299 299 301 301 302 303 303 304 305 307 308

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4.8.2 4.8.3 4.8.4

Test Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wafer Bumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fine Metal L/S/H RDL-Substrate (Organic Interposer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.5 Build-Up Package Substrate . . . . . . . . . . . . . . . . . . . . . . . . 4.8.6 Warpage Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.7 Hybrid Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.8 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.9 Finite Element Simulation and Results . . . . . . . . . . . . . . . 4.8.10 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer . . . . . 4.9.1 The Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.2 Test Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.3 Fine Metal L/S RDL-Interposer . . . . . . . . . . . . . . . . . . . . . 4.9.4 Interconnect-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.5 HDI PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.6 Final Assembly of the Hybrid Interposer . . . . . . . . . . . . . 4.9.7 Characterizations of the Hybrid Substrate . . . . . . . . . . . . 4.9.8 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.9 Reliability Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.10 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . 4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.1 Why Low-Loss Dielectric? . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.2 Raw Materials and Their Data Sheets . . . . . . . . . . . . . . . . 4.10.3 Sample Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.4 Fabry–Perot Open Resonator (FPOR) . . . . . . . . . . . . . . . . 4.10.5 Test Vehicle Designed by Polar and ANSYS . . . . . . . . . . 4.10.6 Test Vehicles Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.7 TDR Measurement and Results . . . . . . . . . . . . . . . . . . . . . 4.10.8 Effective Dielectric Constant (1eff) . . . . . . . . . . . . . . . . . . 4.10.9 VNA Measurement and Correlation with Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.10 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

310 310

5 Chiplets Lateral Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Rigid Bridges Versus Flexible Bridges . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Intel’s EMIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Solder Bumps for EMIB . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Fabrication of EMIB Substrate . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Bonding Challenges for EMIB . . . . . . . . . . . . . . . . . . . . . . 5.4 IBM’s DBHi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Solder Bumps for DBHi . . . . . . . . . . . . . . . . . . . . . . . . . . .

381 381 383 384 384 386 387 388 388

310 313 316 316 317 317 326 327 327 327 328 330 330 333 336 336 338 346 348 348 349 350 351 358 361 364 364 366 367 369

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5.4.2 DBHi Bonding Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 DBHi Underfilling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 DBHi Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Université de Sherbrooke/IBM’s Self-aligned Bridge . . . . . . . . . . . 5.5.1 Process Flow of the V-Groove Opening of the Self-aligned Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Challenges of Self-aligned Bridge . . . . . . . . . . . . . . . . . . . 5.6 Patents on Rigid Bridges with Fan-Out Packaging . . . . . . . . . . . . . . 5.7 TSMC’s LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 SLIP’s FO-EB and FO-EB-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 FO-EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 FO-EB-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 ASE’s sFOCoS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 The Structure and Process of sFOCoS . . . . . . . . . . . . . . . 5.9.2 The Structure and Process of FOCoS-CL . . . . . . . . . . . . . 5.9.3 Reliability and Warpage Between sFOCoS and FOCoS-CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Amkor’s S-Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.1 S-Connect with Si-Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.2 S-Connect with Molded RDL-Bridge . . . . . . . . . . . . . . . . 5.11 IME’s EFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.1 Process Flow of EFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.2 Thermal Performance of EFI . . . . . . . . . . . . . . . . . . . . . . . 5.12 imec’s Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.1 The Structure of imec’s Bridge . . . . . . . . . . . . . . . . . . . . . 5.12.2 The Process of imec’s Bridge . . . . . . . . . . . . . . . . . . . . . . . 5.12.3 The Challenges of imec’s Bridge . . . . . . . . . . . . . . . . . . . . 5.13 UCIe Consortium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 Flexible Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Unimicron’s Hybrid Bonding Bridge . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.1 Hybrid Bonding Bridge with C4 Bumps on the Package Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.2 Hybrid Bonding Bridge with C4 Bumps on the Chiplet Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

389 392 397 397

6 Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Direct Cu-Cu TCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Some Fundamental on Direct Cu-Cu TCB . . . . . . . . . . . . 6.2.2 IBM/RPI’s Cu-Cu TCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Direct SiO2 -SiO2 TCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Some Fundamental on SiO2 -SiO2 TCB . . . . . . . . . . . . . .

431 431 431 431 433 433 433

398 399 399 400 403 403 405 406 409 409 410 411 413 413 415 416 416 418 418 419 420 420 421 422 423 423 426 426 427

Contents

6.4 6.5 6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14 6.15

6.16

xix

6.3.2 MIT’s SiO2 -SiO2 TCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Leti/Freescale/STMicroelectronics’ SiO2 -SiO2 TCB . . . A Brief History of Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . Some Fundamental on Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . Sony’s Direct Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Sony’s CIS with Oxide-Oxide TCB . . . . . . . . . . . . . . . . . . 6.6.2 Sony’s CIS with Cu-Cu Hybrid Bonding . . . . . . . . . . . . . 6.6.3 Sony’s Three-Wafer Hybrid Bonding . . . . . . . . . . . . . . . . 6.6.4 Sony’s Bond Strength on W2W Hybrid Bonding . . . . . . SK Hynix’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Hybrid Bonding for DRAM Applications . . . . . . . . . . . . 6.7.2 Bonding Yield Improvement . . . . . . . . . . . . . . . . . . . . . . . Samsung’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Characterization of Hybrid Bonding . . . . . . . . . . . . . . . . . 6.8.2 Effect of Pad Structure and Layout on Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 Voids in Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . 6.8.4 CoW Hybrid Bonding of 12-Momery Stacked . . . . . . . . TEL’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 Simulation of Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . 6.9.2 Wet Atomic Layer Etch of Cu . . . . . . . . . . . . . . . . . . . . . . Tohoku’s Cu-Cu Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 Cu Grain Enlargement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.2 Hybrid Bonding with Cu/PI Systems . . . . . . . . . . . . . . . . Imec’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 Hybrid Bonding with Cu/SiCN Surface Topography . . . 6.11.2 Die-To-Wafer Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . 6.11.3 Thermal and Mechanical Reliability of Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CEA-LETI’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.1 CEA-LETI/ams Cu-Free Hybrid Bonding . . . . . . . . . . . . 6.12.2 CEA-LETI/SET D2W Hybrid Bonding . . . . . . . . . . . . . . 6.12.3 CEA-LETI/Intel D2W Self-assembly for Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IME’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.1 Simulation of SiO2 W2W Hybrid Bonding . . . . . . . . . . . 6.13.2 Simulation of SiO2 C2W Hybrid Bonding . . . . . . . . . . . . 6.13.3 Simulation of Cu/Polymer C2W Hybrid Bonding . . . . . . 6.13.4 Yield Improvement on C2W Hybrid Bonding . . . . . . . . . Intel’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xperi’s Cu-Cu Hybrid Bonding [51–57] . . . . . . . . . . . . . . . . . . . . . . 6.15.1 D2W Hybrid Bonding—Die Size Effect . . . . . . . . . . . . . . 6.15.2 Multi-Die Stacks with Hybrid Bonding . . . . . . . . . . . . . . Applied Material’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . 6.16.1 Dielectric Materials for Hybrid Bonding . . . . . . . . . . . . .

434 437 437 438 439 439 443 445 448 448 448 449 450 452 453 453 455 456 456 458 460 460 462 466 466 467 469 472 474 475 477 478 479 482 484 491 493 493 495 495 498 498

xx

Contents

6.16.2 Development Platform for Hybrid Bonding . . . . . . . . . . . 6.17 Mitsubishi’s Cu-Cu Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 Unimicron’s Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 D2W vs. W2W Hybrid Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20 Summary and Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

499 501 502 507 507 509

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

About the Author

John H. Lau, Ph.D., P.E. was the CTO from July 2019 to July 2021 and has been a Senior Special Project Assistant since August 2021 of Unimicron in Taiwan. Prior to that, he was a Senior Technical Advisor at ASM Pacific Technology in Hong Kong for 5 years; a specialist of the Industrial Technology Research Institute in Taiwan for 5 years; a Visiting Professor at Hong Kong University of Science and Technology for 1 year; the Director of the Microsystems, Modules, and Components Laboratory at the Institute of Microelectronics in Singapore for 2 years; and a Senior Scientist/MTS at Hewlett-Packard Laboratory/Agilent in California for more than 25 years. His professional competences are design, analysis, materials, process, manufacturing, qualification, reliability, testing, and thermal management of electronic, optoelectronic, LED, CIS, and MEMS components and systems, with emphases on solder mechanics and manufacturing, RoHS-compliant products, SMT, flip chip, fan-in and fan-out wafer/panel-level packaging, SiP, chiplet design and heterogeneous integration packaging, and TSV and other enabling technologies for 3D IC integration. With more than 40 years of R&D and manufacturing experience, he has authored or coauthored more than 515 peer-reviewed articles (out of which 370 are the principal investigator), invented more than 40 issued or pending US patents (out of which 25 are the principal inventor), and given more than 320 lectures/workshops/keynotes worldwide. He has authored or coauthored 23 textbooks (all are the first author) on semiconductor advanced packaging, fan-out wafer-level packaging, 3D IC heterogeneous integration and packaging, TSV for 3D integration, advanced MEMS packaging, reliability of 2D and 3D IC interconnects, flip chip, WLP, MCM, areaarray packages, WLCSP, high-density PCB, SMT, DCA, TAB, lead-free materials, soldering, manufacturing, and solder joint reliability. He earned a Ph.D. degree in theoretical and applied mechanics from the University of Illinois at Urbana–Champaign, an M.A.Sc. degree in structural engineering from the University of British Columbia, a second M.S. degree in engineering mechanics from the University of Wisconsin at Madison, and a third M.S. degree in management science from Fairleigh Dickinson University in New Jersey. He also has a B.E. degree in civil engineering from National Taiwan University. xxi

xxii

About the Author

He has received many awards from the American Society of Mechanical Engineers (ASME), the Institute of Electrical and Electronics Engineers (IEEE), the Society of Manufacturing Engineers (SME), and other societies, including for the best IEEE/ECTC proceedings paper (1989), outstanding IEEE/EPTC paper (2009), best ASME transactions paper (Journal of Electronic Packaging, 2000), best IEEE transactions paper (CPMT, 2010), the ASME/EEP Outstanding Technical Achievement Award (1998), IEEE/CPMT Manufacturing Award (1994), IEEE/CPMT Outstanding Contribution Award (2000), IEEE/CPMT Outstanding Sustained Technical Contribution Award (2010), SME Total Excellence in Electronics Manufacturing Award (2001), Pan Wen Yuan Distinguished Research Award (2011), IEEE Meritorious Achievement in Continuing Education Award (2000), IEEE Components, Packaging, and Manufacturing Technology Field Award (2013), and ASME Worcester Reed Warner Medal (2015). He is an elected ASME fellow, IEEE fellow, and IMAPS fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.

Chapter 1

State-Of-The-Art of Advanced Packaging

1.1 Introduction In this chapter, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fanout epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and highfrequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first. Semiconductor industry has identified five major growth engines (applications) [1, 2], namely: (1) mobile (such as smartphones, smartwatches, and wearables) and portable (such as notebooks and cameras); (2) high-performance computing (HPC), also known as supercomputing, which is able to process data and perform complex calculations at high speeds on a supercomputer; (3) autonomous vehicle (or selfdriving cars); (4) Internet of Things (IoT), such as smart factory and smart health; and (5) big data (for cloud computing) and instant data (for edge computing). There are many system-technology drivers, such as artificial intelligence (AI) and fifthgeneration (5G technology standard for broadband cellular networks), which are boosting the growth of these five semiconductor applications. Because of the drive of 5G and AI, the semiconductors’ speed increases, the interconnect density increases,

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging, https://doi.org/10.1007/978-981-19-9917-8_1

1

2

1 State-Of-The-Art of Advanced Packaging

the pad pitch decreases, the chip size increases, and power dissipation increases. All these provide challenges (opportunities) to advanced packaging. There are many advanced packaging technologies (to house the semiconductors), such as the 2D fan-out (chip-first) IC integration, 2D flip-chip IC integration, package on package (PoP), the system-in-package (SiP), 2D fan-out (chip-last) IC integration, 2.1D flip-chip IC integration, 2.1D flip-chip IC integration with bridges, 2.1D fan-out IC integration with bridges, 2.3D fan-out (chip-first) IC integration, 2.3D (organic substrate) IC integration, 2.3D fan-out (chip-last) IC integration, 2.5D (solder bump) IC integration, 2.5D [microbump (μbump)] IC integration, μbump 3D IC integration, μbump chiplets 3D IC integration, bumpless 3D IC integration, and bumpless chiplets 3D IC integration. Depending on applications, their electrical performance and interconnect density ranking are schematically shown in Fig. 1.1. Figure 1.2 shows the groups of packaging. The simplest packaging method is directly attaching the semiconductor chip on a printed circuit board (PCB), such as chip-on-board (COB) or direct chip attach (DCA) [3–5], Fig. 1.3. Lead-frame packages, such as plastic quad flat pack (PQFP) and small outline integrated circuit (SOIC), are ordinary packages [6, 7]. Even plastic ball grid array (PBGA) [8] and flip-chip–chip-scale package (fcCSP) [9] for single chip (Fig. 1.4) are conventional packages [10]. In this book, advanced packaging is defined (see Fig. 1.2) as from the 2D IC integration with multichip on a package substrate or fan-out redistribution-layer (RDL) substrate. If the package substrate

Fig. 1.1 Advanced packaging ranking according to their density and performance

1.1 Introduction

3

Semiconductors (Regular, SoC, Chiplets, etc.) Single chip

Multichip

Thin-Film or Bridge

COB or DCA

Inorganic or Organic TSV-less Interposer

Passive TSVInterposer

Active TSVInterposer

Package Substrate (Carrier) fcCSP

2D

2.1D

2.3D

2.5D

3D

PBGA

PCB

Fig. 1.2 Groups of advanced packaging: 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration

has thin-film layers on top, then it is called the 2.1D IC integration. If the package substrate or the fan-out epoxy molding compound (EMC) has embedded bridges, then it is called the 2.1D IC integration with bridges. If the multichips are supported by an inorganic/organic through-silicon via (TSV)-less interposer (substrate) and then attached on a package substrate, then it is called the 2.3D IC integration. If the multichips are supported by a passive TSV interposer and then attached to a package substrate, then it is called the 2.5D IC integration. If the multichips are supported by an active TSV interposer and then attached on a package substrate, then it is called the 3D IC integration. There is one exception, where one single chip on an active TSV interposer is also called 3D IC integration [11, 12]. In this chapter, the recent advances of 2D, 2.1D, 2.3D, 2.5D, and 3D IC integrations will be briefly discussed. Chiplet design and heterogenous integration packaging [13], fan-in [14] and fan-out [15] packaging, and low-loss dielectric materials for high-speed and high-frequency applications will also be presented. Flip-chip [4, 15] bumping and bonding/assembly will be briefly mentioned first.

4

1 State-Of-The-Art of Advanced Packaging

Solder joint

Underfill

CHIP

PCB X-ray showing solder joints3 Fig. 1.3 Direct chip attached on board

Chip Package Substrate Solder Bumps PCB

Solder Balls

Solder Balls

Ni-plated Cu Lid Underfill

Chip

Package Substrate

Solder Balls

Fig. 1.4 Flip-chip–chip-scale package (fcCSP)

Solder Bumps

1.2 Flip-Chip Bumping and Bonding/Assembly

5

1.2 Flip-Chip Bumping and Bonding/Assembly 1.2.1 Flip-Chip Bumping There are many flip-chip bumps, such as Au bumps, Ni bumps, Cu studs, and solder bumps [5, 16]. Today, the controlled collapse chip connection (C4) bumps are the most used. For very high-density and fine-pitch, chip connection (C2) bumps are used. The C4 and C2 bumping processes have been presented in [17] and are systemically shown in Fig. 1.5a, b, respectively. One of the examples of the application of C4 and C2 bumps has been given by Amkor [see Fig. 1.5c]. In this book, C4 bumps can be any kind of solder, and C2 bumps consist of Cu pillar + any kind of solder caps, which is also called μbump. Because the solder volume is very small compared with the C4 bump, the surface tension of the C2 bump is not enough to perform the self-alignment. On the other hand, besides being able to handle finer pitch, C2 bumps also provide better thermal and electrical performances than C4 bumps, as shown in Table 1.1.

(a) C4 bump Device Wafer

Solder Cu

Passivation pad Si (1) Redef. Passivation Cu Ti

(3) Spin Resist UV

(b) C2 bump

Solder

(4) Patterning

(2) Sputter Ti/Cu

(6) Strip Resist

Passivation pad

Solder Cu

Si (1) Redef. Passivation

Device Wafer

Cu Ti

(7) Etch Cu/Ti

(5) ECD Cu, Solder

Mask

Mask

(3) Spin Resist UV

(5) ECD Cu, Solder

(8) Flux, Reflow Solder

(7) Etch Cu/Ti Cu

(2) Sputter Ti/Cu

(4) Patterning

(6) Strip Resist

(8) Flux, Reflow

Mother Die Daughter Die Daughter Die Daughter Die Grandma Die

(c) Flip chips with C2 and C4 bumps

PCB Solder Ball

(C2 Bumps) Cu Pillar Micro-Bumps with Solder Caps

C4 (solder) Bumps

Package Substrate

Fig. 1.5 Wafer bumping: a C4 process and b C2 process. c Amkor’s Double-POSSUM

6

1 State-Of-The-Art of Advanced Packaging

Table 1.1 C4 bumps versus C2 bumps: bump pitch and self-alignment Structure

Thermal conductivity (W/m·K)

Electrical resistivity (μΩ·m)

Bump pitch

Self-alignment

Cu

400

0.0172

–

–

C4 bump (solder)

55–60

0.12–0.14

≥ 50 μm

Very good

C2 bump (Cu pillar + solder cap)

300 (effective)

0.025 (effective)

< 50 μm

Very poor

1.2.2 Flip-Chip Bonding/Assembly There are many flip-chip bonding/assembly methods, such as: (1) mass reflow of the C4 or C2 bumps with capillary underfill (CUF); (2) thermocompression bonding (TCB) with low force and reflow of C4 or C2 bumps and CUF; (3) TCB with high force and reflow of C2 bumps and nonconductive paste (NCP) ; (4) TCB with high force and reflow of C2 bumps and nonconductive film (NCF); and (5) bumpless low-temperature hybrid bonding, as shown in Fig. 3. Flip-chip bonding/assembly methods (1)–(4) can be applied to chip-to-chip and chip-to-organic, silicon, or ceramic substrates and have been presented in [17, 18]. Herein, only bumpless hybrid bonding, which can only be applied to chip-to-chip and chip-to-silicon substrates, is briefly mentioned (Fig. 1.6).

1.3 Hybrid Bonding Hybrid bonding was invented by Research Triangle Institute (RTI). They started off with the ZiBond (a direct oxide to oxide bonding that involves wafer-to-wafer processing at low temperatures to initiate high bond strengths). Between 2000 and 2001, Fountain, Enguist, Tong, and several other colleagues founded Ziptronic as a spin-out of RTI. Between 2004 and 2005, based on their ZiBond technology, Ziptronic combined the dielectric bond with embedded metal to simultaneously bond wafers and form the interconnects at lowtemperature, so-called DBI (direct bond interconnect) [19, 20]. Ziptronic was acquired by Tessera on August 28, 2015. Tessera changed its name to Xperi on February 23, 2017. In 2022, Xperi was renamed to Adeia Inc. The breakthrough for Ziptronic DBI technology came in the spring of 2015 when Sony, already using its “Zibond” oxide to oxide bonding technology extended its license to include DBI. DBI is now being used for much of the CMOS (Complementary Metal–Oxide–Semiconductor) image sensor market in the world’s smartphones and other image-based devices. Also, for example, YMTC (Yangtze Memory Technologies Co., Ltd.) is using the Ziptronix DBI technology in its 232-layer 3D NAND with a density of 15.2 GB/mm2 products.

1.3 Hybrid Bonding

7

(a) Mass reflow of C4 or C2 Bumps (CUF)

(b) TCB with Low-Force and reflow of C4 or C2 Bumps (CUF)

(c) TCB with High-Force and reflow of C2 Bumps (NCP)

(d) TCB with High-Force and reflow of C2 Bumps (NCF) Bump less Bump less (e) Bumpless Hybrid Bonding Fig. 1.6 Flip-chip assembly and bonding. a Mass reflows of C4 or C2 bumps (CUF). b TCB with low force and reflow of C4 or C2 bumps (CUF). c TCB with high force and reflow of C2 bumps (NCP). d TCB with high force and reflow of C2 bumps (NCF). e Bumpless hybrid bonding

1.3.1 Some Fundamental on Hybrid Bonding Figure 1.7 shows the key process steps for the bumpless low-temperature DBI [19– 43]. First, controlling nanoscale topography is very important for DBI technology. The dielectric surface should be extremely flat and smooth before activation and bonding. Chemical–mechanical polishing (CMP) should achieve a very low dielectric roughness (< 0.5 nm rms) and a certain recess of metal areas below the dielectric surface, as shown in Fig. 1.7a. Upon contact, the dry plasma-activated dielectric surfaces bond together instantaneously, as shown in Fig. 1.7b, at room temperature. (Very high bond energies can be obtained at very low temperatures, as shown in [26]). The dishing gap can be closed by heating, as shown in Fig. 1.7c. (This step is optional because the dishing gap can also be closed by the following subsequent annealing step.) Metal-to-metal bond occurs during batch annealing. The coefficient of thermal

8

1 State-Of-The-Art of Advanced Packaging

expansion (CTE) of metals is typically far larger than dielectrics. The metal expands to fill the gap and then builds up the internal pressure, as shown in Fig. 1.7d. It is under this internal pressure and annealing temperature that metal atoms diffuse across the interface, making a good metal-to-metal bond and, hence, electrical connection [26]. External pressure is optional for this type of bonding. In this case, the copper oxidation during bonding is minimized because the bonded oxide layer surrounding the copper interconnect protects the interconnect from oxidation in the annealing oven, thus minimizing Cu oxidation during the anneal. The bonded oxide surface also hermetically seals the Cu interconnect during operation. Optimizing the CMP condition is the key to producing the right amount of surface characteristics, such as metal recess, dielectric roughness, and dielectric curvature for DBI [26]. Figure 1.7 shows an optimal DBI with 4 μm-pitch and 2 μm-diameter pads.

Metal

Silicon BEOL Oxide

Metal

(a) Metal

Metal (b) Metal

(c)

Metal Metal

Oxide BEOL Silicon Silicon BEOL Oxide Oxide BEOL Silicon Silicon BEOL Oxide Oxide BEOL Silicon

Metal

Metal Metal

Metal Metal

Silicon BEOL (d) BEOL Silicon

Fig. 1.7 Key process steps (fundamental) of hybrid bonding. a Metal (Cu) recess = 3 nm plasma surface activation. b Oxide-to-oxide initial bond at room temperature. c Heating closes dishing gap (metal CTE > oxide CTE) (optional). d Annealing (e.g., 300 °C for 0.5 h) w/o external pressure

1.3 Hybrid Bonding

9

1.3.2 Sony’s CIS with Hybrid Bonding Sony is the first to use bumpless low-temperature Cu–Cu DBI in high-volume manufacturing (HVM) [21, 22]. Sony produced the IMX260 backside-illuminated CMOS image sensor (BI-CIS) for the Samsung Galaxy S7, which shipped in 2016. Electrical test results showed that their robust Cu–Cu direct hybrid bonding achieved remarkable connectivity and reliability. The performance of the image sensor was also super. Top and cross section views of the IMX260 BI-CIS are shown in Fig. 1.8. It can be seen that, unlike in [44] for Sony’s ISX014 stacked camera sensor, the TSVs are eliminated, and the interconnects between the BI-CIS chip and the processor chip are achieved by Cu–Cu DBI. The signals are coming from the package substrate with wire bonds to the edges of the processor chip. Usually, wafer-to-wafer bonding is for the same chip size from both wafers. In Sony’s case, the processor chip is slightly larger than the pixel chip. In order to Processor Chip

BI-CIS Chip

Microlens

BI-CIS Chip

SiO2-SiO2 Wirebonds

BI-CIS Chip

Processor Chip

Cu-Cu

3μm 6μm

Processor Chip

Wirebonds

CIS

CMOS Image Sensor (CIS) SiO2-SiO2

Cu-Cu Image Signal Processor (ISP)

Fig. 1.8 Sony’s CMOS image sensor manufactured by hybrid bonding

ISP

10

1 State-Of-The-Art of Advanced Packaging

perform wafer-to-wafer bonding, some of the areas for the pixel wafer must be wasted, but it can be used for the wirebonding pads. The assembly process of Cu–Cu DBI starts off with surface cleaning, metal oxide removal, and activation of SiO2 (by wet cleaning and dry plasma activation) of wafers for the development of high bonding strength. Then, use optical alignment to place the wafers in contact at room temperature and in a typical cleanroom atmosphere. The first thermal annealing (100–150 °C) is designed to strengthen the bond between the SiO2 surfaces of the wafers while minimizing the stress in the interface due to the thermal expansion mismatch among Si, Cu, and SiO2 . Then, apply higher temperature (300 °C) and pressure (25 kN) for 30 min to introduce the Cu diffusion at the interface and grain growth across the bond interface. The postbond annealing is 300 °C under N2 atm for 60 min. This process leads to the seamless bonds (see Fig. 1.8) formed for both Cu and SiO2 at the same time. Figure 1.9 shows Sony’s future CIS technology. It can be seen that the Cu–Cu hybrid bonding operates on three wafers (pixel, pixel parallel, and logic). Sony demonstrated that the bond pitch can go down to 1.5 μm [23]. Besides Xperi and Sony, there are many others, such as Intel [41], TSMC [29, 30], imec [31–34], GlobalFoundries [35], Mitsubishi [36], Leti [37], SK Hynix [27], and IME [28], who are also working on hybrid bonding. In this section, only TSMC and Intel’s works are briefly mentioned.

SONY's future CMOS image sensors technology

Fig. 1.9 Sony’s future CMOS image sensor technology

1.3 Hybrid Bonding

11

1.3.3 TSMC’s Hybrid Bonding

μbump formation

Bond formation

(b)

SoIC stacking

Flip chip stacking

(Hybrid Bonding)

Insertion Loss (dB)

Figure 1.10a shows the front-end TSMC’s system on integrated chips (SoIC) [29, 30] along with the conventional 3D IC integration with flip-chip technology. It can be seen that the key difference between SoIC and 3D IC integration is that SoIC is bumpless, and the interconnects between the chiplets are Cu-to-Cu hybrid bonding. The assembly process of SoIC can be either wafer-on-wafer (WoW), chip-on-wafer (CoW), or chip-on-chip (CoC) hybrid bonding. The SoIC technology has a better electrical performance than the flip-chip technology, as shown in Fig. 1.10b. (The SoIC chiplets are vertically hybrid bonded, and the flipchips are 2D side-by-side assembled). It can be seen that the insertion loss of SoIC technology is almost zero and is far smaller than that of the flip-chip technology [29, 30]. Figure 1.10c shows the bump density from various bonding assembly technologies, such as flip-chip, 2.5D/3D, SoIC, and SoIC+ . It can be seen that SoIC can go down to the ultrafine pitch with extremely high density. Another advantage of SoIC is free of the chippackage-interaction reliability issue from the fine-pitch flip-chip assembly. Figure 1.11 shows the Cu–Cu bumpless SoIC hybrid bonding of AMD’s 3D Vcache processor [73]. It is a face-to-back hybrid bonding, and the bonding pitch is only

SoIC Hybrid Bonding

Frequency (GHz)

Underfill

C4 FC bumps

RDL (optional)

FC assembly on substrate

FC or Wafer-level system integration

(a)

(c)

Bump Density (counts/mm2)

SoIC+

>1000x

SoIC >10x 2.5D/3DIC

Flip Chip

Bump/Bonding Pitch (μm)

Fig. 1.10 a TSMC’s SoIC by hybrid bonding. b Electric performance: SoIC hybrid bonding versus conventional flip-chip bonding. c Bump density performance: SoIC hybrid bonding versus conventional flip-chip bonding

12

1 State-Of-The-Art of Advanced Packaging

AMD 3D V-Cache

SRA M

B SRAM

F m 9μm

BPV Die interface

BPM

TSV Fig. 1.11 TSMC’s SoIC Cu–Cu hybrid bonding for AMD’s 3D V-cache

9 μm. Figure 1.12 shows the Cu–Cu bumpless SoIC hybrid bonding of Graphcore’s IPU (intelligence processing unit) processor [74]. It is a face-to-face hybrid bonding.

1.3.4 Intel’s Hybrid Bonding During Intel Architecture Day (August 13, 2020), Intel presented a hybrid bonding technology with their FOVEROS along with the conventional μbump flip-chip technology. In [41], they called it FOVEROS Direct, as shown in Fig. 1.13. It can be seen that, with the hybrid bonding technology, the pad pitch can go down to 10 μm and with 10,000 bumpless interconnects per mm2 . This is many times more than the one with 50-μm-pitch μbump flip-chip technology.

1.3.5 SK Hynix’s Hybrid Bonding Currently, the HBM (high bandwidth memory) is constructed by the TCB of individual DRAMs (dynamic random-access memory) with TSVs, C2 microbumps, and

1.3 Hybrid Bonding

13

3D silicon wafer stacked processor 350TeraFLOPS AI compute Optimized silicon power delivery 0.9 GigaByte In-Processor-Memory @ 65TB/s 1,472 independent processor cores 8,832 independent parallel programs 10x IPU-LinksTM delivering 320GB/s

C4 bump

C4 bump

C4 bump

C4 bump

4 x BOW 3D Wafer-on-wafer IPUs 1.4 PetaFLOPS AI compute 3.6 GB In-Processor-Memory @ 260TB/s Up to 256 GB IPU Streaming Memory 2.8 Tb/s IPU-FabricTM Same 1U blade form factor

C4 bump

C4 bump

C4 bump

UBM

BEOL

Cu-Cu bonding

BEOL Colossus Die

Fig. 1.12 TSMC’s SoIC Cu–Cu hybrid bonding for Graphcore’s IPU processor

FOVEROS Direct

FOVEROS (Micro Bumps) Micro bumps

CHIP

CHIP

CHIP

50μm pitch μbump bonding 400 bumps/mm2

CHIP

Bumpless

10μm pitch hybrid bonding 10,000 pads/mm2

Top Die Top Die Bottom Die

Cu Cu-Cu Bonding

FOVEROS Direct

Bottom Die

Cu

Fig. 1.13 Intel’s hybrid bonding (FOVEROS Direct): μbump versus bumpless

14

1 State-Of-The-Art of Advanced Packaging

Hybrid Bonding Interface

Probing Pad

Cu Si

Cu

Hybrid Bonding Interface

Metal 4

Fig. 1.14 SK Hynix’s hybrid bonding of three wafers

NCF (nonconductive film). Recently, SK Hynix demonstrated the DRAMs stacking by wafer-to-wafer Cu–Cu hybrid bonding [27] as shown in Fig. 1.14.

1.4 2D IC Integration There are many kinds of 2D IC integration. Figures 1.15 and 1.16 show a few examples of 2D IC integration, which is defined as having at least two chips on the same package substrate or fan-out RDL substrate [1]. One of the most employed 2D IC integrations is SiP, which has been used extensively for consumer products, such as smartwatches, smartphones, tablets, notebooks, and true wireless stereo. More information on SiP can be found from [1, Chap. 2]. The packaging technology for 2-D IC integration can be flip-chip, wire bonding, fan-out with chip-first, fan-out with chip-last, and so on.

1.5 2.1D IC Integration The 2.1D IC integration is defined as fabricating fine metal linewidth and spacing (L/S) thin-film layers directly on top of a build-up package substrate or high-density

1.5 2.1D IC Integration

15 Flip chip bump Chip2

Chip1

Package Substrate

(a)

Chip1 Chip2

Solder Joint

PCB PCB Encapsulation Flip Chip Bonding

(b)

Wire Bonding

Package Substrate

PCB

Fig. 1.15 Examples of 2D IC integration. a Two flip-chips on a package substrate. b One flip-chip and one MEMS with wirebonds on a package substrate

10mmx10mm SiP

300mm reconstituted wafer

3mmx3mm

3mmx3mm

3mmx3mm

5mmx5mm

Solder Ball

EMC 3mmx3mm

3mmx3mm

PCB

Fig. 1.16 Heterogeneous integration of four chips on a fan-out RDL substrate

RDLs

16

1 State-Of-The-Art of Advanced Packaging Fine Metal L/S RDL-Substrate (Organic Interposer) μbump Thin-Film Layers CHIP

μbump

CHIP/HBM

CHIP/HBM TSV

CHIP

CHIP

CHIP/HBM

RDL

TSV-interposer

C4 bump

Package Substrate Solder Ball

2.1D

2.3D

2.5D

PCB

PCB

PCB

Not-to-scale (a)

(b)

(c)

Fig. 1.17 Schematics of a 2.1D, b 2.3D, and c 2.5D/3D IC integration

interconnect (HDI). In addition, the 2.1D IC integration is defined as embedding fine metal L/S RDLs silicon bridge on top of a build-up organic package substrate or in a fan-out EMC, Fig. 1.17a.

1.5.1 Thin-Film Layers on Package Substrates In 2013, Shinko proposed to make thin-film layers directly on top of the build-up layer of a package substrate and called integrated thin-film high-density organic package (i-ITHOP), as shown in Fig. 1.18 [45]. It can be seen that the thickness, linewidth, and spacing of the thin-film Cu RDLs can be as small as 2 μm. The thin-film Cu RDLs are vertically connected through a 10-μm via. The surface Cu pad pitch is 40 μm, and the Cu pad diameter is 25 μm with a height of 10–12 μm. In 2014, Shinko demonstrated that [46] ultrafine pitch flipchips can be successfully assembled on the i-THOP substrate. One of the challenges of thin-film layers directly on top of a package substrate is to control the warpage in order to increase the manufacturing yield. Recently, JCET proposed a 2.1D organic interposer called ultraformat organic substrate (uFOS) [47], and the key process steps and SEM images are shown in Fig. 1.19. It can be seen that the metal L/S = 2/2 μm (uFOS) is built on top of the coreless package substrate. However, in order to mitigate the warpage issue of the coreless package substrate, an embedded stiffness (e-STF) in the last layer of coreless package substrate is introduced during the substrate manufacturing process. Metallic

1.5 2.1D IC Integration

17 Chip2

Chip1 Thin-film Build-up

Thin-film Build-up

Core

Core

Build-up

PCB

Thin-film Build-up

Φ 10μm

Build-up via (50μm)

Core

φ 25μm-pad

40μm pad-pitch

Line width and spacing = 2μm 2μm

25μm-pad

Fig. 1.18 Shinko’s 2.1D IC integration: i-THOP (integrated thin-film high-density organic package)

pieces are impregnated with prepreg to enhance the substrate’s overall stiffness [47] to resist bending, as shown in Fig. 1.19. Besides Shinko and JCET, Hitachi [48], ASE [49], and SPIL [50] are also working on fabricating thin-film fine metal L/S RDL layer on build-up organic package substrate. As of today, 2.1D IC integration is not in HVM. Recently, a few companies are increasing the metal L/S from 2 to 8–10 μm of the thin-film layers in order to obtain a higher manufacturing yield for HVM.

1.5.2 Fine Metal L/S RDL Bridge Embedded in Organic Package Substrate Figure 1.20 shows one of Intel’s patents and the Agilex field programmable gate array (FPGA) module. The FPGA and other chips are attached on top of a build-up package substrate with an embedded multidie interconnect bridge (EMIB). EMIB is a piece of silicon with fine metal L/S RDLs to allow horizontal interconnection of chips [51]. One of the challenges of the EMIB technology is to fabricate the organic build-up package substrate with cavities for the silicon bridges and then laminate (with pressure and temperature) another build-up layer on top (to meet the substrate

18

1 State-Of-The-Art of Advanced Packaging Chip 1

Chip 2

uFOS

Carrier

ABF/PP RDL2

Surface Treatment

Metal formation and laser via drill

PI Coating

Carrier removal

E-STF

PCB

Metal Formation 8.23 2.78

1.04

Backside Laser via

2.48 PI Coating 8.23

Unit: μm

ENIG Finish Laser via drill

Fig. 1.19 JCET’s 2.1.D IC integration: uFOS (ultraformat organic substrate)

surface flatness requirement) for chiplets (with both C2 and C4 bumps) bonding. The C2 and C4 bumps are not on the bridges. Very recently, IBM proposed a method called direct bonded heterogeneous integration (DBHi) [52]. They make a cavity on the package substrate (see Fig. 1.21). In parallel, they do the wafer bumping and bonding of the chiplets and bridges and then assemble the whole module in the cavity by reflowing the C4 solder bump on the package substrate. The key step in IBM’s method is to do C4 bumping on the chiplet and C2 microbumping (Cu-pillar + solder cap) on the bridge. In this case, there are two different under bump metallurgies (UBMs) on the chiplet wafer, which are fabricated by a double lithography process [52]. The key challenges of DBHi are when there is more than one bridge on a chiplet, and there are more than two chiplets on a package substrate. More information on fine metal L/S RDL bridge embedded in organic package substrate will be discussed in Chap. 5 of this book.

1.5.3 Fine Metal L/S RDL Bridge Embedded in Fan-Out EMC The fine metal L/S RDL silicon bridge (to let chips horizontally communicate with each other) can also be embedded in fan-out EMC. Figure 1.22a shows the Applied

1.5 2.1D IC Integration

19

C4 or C2 bumps

CHIP

CHIP

CHIP

Embedded Bridge Embedded Bridge Package Substrate Solder Ball C4 bump

C2 bump

CHIP1

CHIP2

CHIP

EMIB

CHIP1

CHIP2 EMIB

Organic Package Substrate

PCB Not-to-scale

Fig. 1.20 a Intel’s EMIB (embedded multidie interconnect bridge) embedded in organic package substrate and Agilex FPGA module BRIDGE

C4 Bump

NCP

CHIPLET 1 CHIPLET 2

CHIPLET 1

Build-up Package Substrate

CHIPLET 2

μBump

BRIDGE

CHIPLET 1

BRIDGE

CAVITY

CHIPLET 2

CHIPLET 2

CHIPLET 1 BRIDGE CHIPLET 1

CHIPLET 2

C4 Bump

Underfill

μBump

C2 bump

BRIDGE

Trench

Build-up Package Substrate CHIPLET CHIPLET 2

CHIPLET 1 BRIDGE

UBM C2 bump Cu Solder

Underfill Anchor BRIDGE

Fig. 1.21 IBM’s DBHi (direct bonded heterogeneous integration)

C4 bump

20

1 State-Of-The-Art of Advanced Packaging

Cu-contact Stud (Pillar) CHIP

CHIP

(a)

Backgrinding surface

Bridge RDLs Solder Ball

RDL Substrate

Die attach

C2 bump

C4 bump

Chip 2

Chip 1 RDLs RDLs

(b)

Si Bridge

TMV

EMC/ABF RDLs

Fig. 1.22 a Applied Materials’ bridge embedded in EMC by fan-out chip (bridge) first die face-up process. US 10,651,126, 2020. b Unimicron’s bridge embedded in EMC by fan-out chip (bridge) first die face-down process. US 11,410,933, 2022

Materials’ patent US 10,651,126 [53] with fan-out chip (bridge) first die face-up process, while Fig. 1.22b shows the Unimicron patent TW 1,768,874 with fan-out chip (bridge) first die facedown process. Recently, there are many publications in these areas, such as those given by TSMC [54] [they called the bridge local silicon interconnect (LSI)], SPIL’s fan-outembedded bridge (FO-EB) [55], Amkor’s S-Connect fan-out interposer [56], ASE’s stacked Si bridge fan-out chip-on-substrate (sFOCoS) [57], and IME’s embedded fine interconnect (EFI) [58], as shown in Fig. 1.23a–e, respectively. More information on fine metal L/S RDL bridge embedded in fan-out EMC will be discussed in Chap. 5 of this book.

1.5.4 Fine Metal L/S RDL Flexible Bridge The foregoing bridges are called rigid bridges in which the RDLs are fabricated on a silicon wafer substrate. There is another group of bridges called a flexible bridge, which is the RDL itself. The flexible bridge consists of fine metal L/S conductors

1.6 3D IC Integration

21

(a)

(b) Bridge

(c)

(d)

Bridge

Bridge

(e)

(Bridge) Fig. 1.23 Examples on bridges embedded in EMC. a TSMC’s LSI (local silicon interconnect). b SPIL’s FO-EB (fan-out-embedded bridge). c Amkor’s S-Connect. d ASE’s sFOCoS (stack Si bridge fan-out chip-on-substrate). e IME’s EFI (embedded fine interconnect)

in a dielectric polymer, such as polyimide film. The very first flexible bridge patent U.S. 2006/0095639 A1 was filed by SUN Microsystems on November 2, 2004 (see Fig. 1.24). For fine pitch applications, the C2 and C4 bumps are on the chiplets. The biggest challenge is handling the flexible bridge and chiplets during bonding. For high-speed and high-frequency applications, such as millimeter-wave frequencies, the polyimide can be replaced by liquid crystal polymer (LCP) so-called the LCPflexible bridge.

1.6 3D IC Integration For 2.3D IC integration, Fig. 1.17b, the fine metal L/S RDL-substrate (or organic interposer) and the build-up package substrate or HDI are fabricated separately. After that, the fine metal L/S substrate and the build-up package substrate are interconnected into a hybrid substrate through the solder joints that are enhanced with underfill. Since the fine metal L/S substrate can be fabricated alone with a temporary glass wafer or panel, thus it can go down to 2 μm with a high yield. Thus, as shown in Fig. 1.1, the 2.3 IC integration is ranked to have a higher interconnect density than the 2.1D IC integration.

22

1 State-Of-The-Art of Advanced Packaging

Flexible Bridge

Flexible Bridge

Fig. 1.24 SUN Microsystems’ flexible bridge

There are at least three methods to fabricate the organic interposer, namely: (1) the conventional semi-additive process (SAP)/PCB method [59]; (2) the fan-out with chip-first method [60–63]; and (3) the fan-out with chip-last (or RDL-first) method [64–71]. Table 1.2 shows the comparison between these three methods. It can be seen that: (1) because of wafer bumping, chip-to-RDL substrate bonding, and underfilling, SAP/PCB [59] and fan-out with chip-last methods [64–71] are higher cost than the fan-out with chip-first method [60–63]; (2) on the other hand, SAP/PCB and fan-out with chip-last can house larger chips with larger package sizes; and (3) fan-out with chip-last method leads to the smallest metal L/S of the RDL substrate.

1.6.1 SAP/PCB Method (1) Shinko’s Coreless Organic Interposer: In 2012, Shinko proposed to use the coreless package substrate to replace the TSV interposer, as shown in Fig. 1.25. For sure, the cost of making the coreless substrate is much lower than that of making the TSV/RDL interposer. Warpage could be an issue.

1.6 3D IC Integration Table 1.2 2.3D IC Integration methods’ comparison: SAP/PCB, Fan-out chip-first, and fan-out chip last

23 2.3D IC integration SAP PCB

Fan-out Chip-first

Fan-out Chip-last

Chip size

Large

Medium

Large

Package size

Large

Medium

Large

RDL substrate . 8 μm (metal L/S)

. 5 μm

. 2 μm

RDL substrate . 10 (layers)

.4

.6

Wafer bumping

Yes

No

Yes

Chip-to-RDL substrate bonding

Yes

No

Yes

Underfill or MUF

Yes

No

Yes

Build-up package substrate

Yes

Yes

Yes

Process steps

More

Less

More

Performance

Medium

High

Very high

Cost

High

Medium

High

Applications

Medium performance

High performance

Very high performance

(2) Cisco’s Organic Interposer: Fig. 1.26 shows a chiplet design and heterogeneous integration packaging designed and manufactured with a large organic interposer (TSV-less interposer) with fine-pitch and fine-line interconnections by Cisco [59]. The organic interposer has a size of 38 mm × 30 mm × 0.4 mm and has 12 layers: five top routing layers, two layers around the core, and five bottom routing layers (five-two-five). The 50 mm × 50 mm package substrate has four layers: one top routing layer, two layers around the core, and one bottom routing layer (one-two-two). The minimum metal L/S and thickness of the front side and the back side of the organic interposer are the same and are, respectively, 6, 6, and 10 μm. It is a ten-layer high-density organic interposer (substrate), and the via size is 20 μm. A high-performance application-specific integrated circuit (ASIC) die measured at 19.1 mm × 24 mm × 0.75 mm is attached on top of the organic interposer along with four high-bandwidth memory (HBM) dynamic random-access memory (DRAM) die stacks. The 3-D HBM die stack with a size of 5.5 mm × 7.7 mm × 0.48 mm includes one base buffer die and four DRAM core dice that are interconnected with TSVs and fine-pitch micropillars with solder cap bumps. The pad size and pitch of the front side of the organic interposer are 30 and 55 μm, respectively.

24 Fig. 1.25 Shinko’s 2.3D IC integration with a coreless substrate by the SAP/PCB method. a Coreless substrate supporting multichip. b Coreless substrate supporting chip and memory cube

1 State-Of-The-Art of Advanced Packaging

Coreless Substrate Chip1

Chip2

(a) Build-up package substrate

Memory Cube

Coreless Substrate Chip

(b) Build-up package substrate

1.6.2 Fan-Out with Chip-First Method In 2013, Stats ChipPAC proposed [60] using the fan-out chip-first flip-chip (FOFC)embedded wafer level ball grid array (eWLB) to make the RDLs for the chips to perform mostly lateral and vertical communications. Their objective is to replace the TSV interposer, μbump, and underfill by the RDLs (coreless organic interposer) as indicated in their patent (U.S. 9,484,319 B2, filed on December 23, 2011, and granted on November 1, 2016). Later on, MediaTek [61], ASE [62], and TSMC [63] are basically doing the same thing. For example, Fig. 1.27 shows ASE’s fan-out chip-on-substrate (FOCoS), which employs the fan-out with chip-first and die-down on a temporary wafer carrier and then overmold an EMC by compression method.

1.6.3 Fan-Out with Chip-Last Method The 2.3D IC integration by fan-out with chip-last (or RDL-first) to fabricate the fine metal L/S RDL substrate (or organic interposer) to replace the TSV interposer has

1.6 3D IC Integration

25

HBM_Functional

HBM_Mechanical

Organic Interposer

C2 Bumps

C4 Bumps

ASIC (FPGA)

HBM

HBM_M

Features

ASIC (FPGA)

Organic Interposer

Cu wiring (Dielectric)

SAP (Organic)

Frontside Pad size/pitch

30/55μm

Frontside wiring L/S /T (min) 6/6/10μm No. of routing layers

Organic Interposer 1-2-1 Package Substrate

10

Wiring layer via size

20μm

PTH size/pitch/depth

57/150/200μm

Backside pad size/pitch

100/150μm

Backside wiring L/S/T (min)

6/6/10μm

Fig. 1.26 Cisco’s 2.3D IC integration with a build-up organic interposer by the SAP/PCB method CoWoS Die1

ASEís FOCoS EMC Microbumps + Underfill

Die2

EMC

Die1

TSV-interposer + RDLs

Die2 RDLs

Package Substrate

C4 bumps

Solder Balls

Package Substrate

Underfill

Underfill

Solder Balls

C4 bumps

EMC EMC Chip1

RDLs

C4 bumps

Chip2 Chip1 RDLs C4 bumps

Chip2

Package Substrate

Solder Balls

Underfill

Package Substrate 27

Fig. 1.27 ASE’s 2.3D IC integration with a fan-out (chip-first) RDL substrate (interposer)

RDLs

26

1 State-Of-The-Art of Advanced Packaging

CHIP Cu Solder

C4 bump

RDL Formation

C4 bump Grinding & bump attach

μbump Package substrate

Underfill

Solder ball Multichip bonding

RDL on substrate / ball mount

EMC

Encapsulation

Lid attaching

Fig. 1.28 Samsung’s 2.3D IC integration with a fan-out (chip-last) RDL interposer

been studied by many companies, such as SPIL [64, 65], Samsung [66, 67], ASE [68– 69], TSMC [69], Shinko [70, 428], and Unimicron [71]. Most of these companies use a temporary wafer to fabricate the RDL substrate. For example, Figs. 1.28 and 1.29 show the 2.3D IC integration by Samsung [66, 67] and ASE [68–69], respectively, and their RDL substrate is fabricated on a temporary wafer carrier. Figures 1.30 and 1.31 show Unimicron’s 2.3D IC integration [71], and their RDL substrate is fabricated on a temporary panel carrier, which is higher throughput than with a temporary wafer carrier. The fine metal L/S substrate and the build-up package substrate or HDI substrate can also be combined through an interconnect layer [72]. This is very similar to [64–71] except the solder joint and underfill are replaced by an interconnect layer, as shown in Fig. 1.32.

1.7 2.5D IC Integration The 2.5D IC integration is defined as chips are supported by a passive TSV interposer, which is then attached to a package substrate [75–139], Fig. 1.17c. The passive TSV interposer is just a piece of dummy silicon with TSVs and RDLs. Today, the TSV interposer of 2.5D IC integration is in volume manufacturing by foundries such as

1.7 2.5D IC Integration

27 Silicon Chips

Fan-out RDL Layout

μpad

FC BGA Substrate

Stack vias

Fig. 1.29 ASE’s 2.3D IC integration with a fan-out (chip-last) RDL interposer fabricated on a temporary wafer

Chip 1 DL01 ML1 DL12 ML2 DL23 ML3

Chip 2

μbump

Underfill

Cu Pad Chip 1

Chip 2

Fine metal L/S RDL-

C4 bump

Build-up substrate

Underfill

Solder Mask Pad

CHIP μbump

Solder

Underfill

Cu

Build-up Package Substrate

RDLs

C4

Underfill

Build-up Layers

Solder Mask

Solder Ball

Build-up Package Substrate

Fig. 1.30 Unimicron’s 2.3D IC integration with a fan-out (chip-last) RDL interposer fabricated with PID (photoimageable dielectric)

28

1 State-Of-The-Art of Advanced Packaging

Underfill

Chip 1

Pad

Chip 2

Fine metal L/S RDL-substrate Build-up substrate

Solder

CHIP

50μm

Underfill

Cu

RDLs Underfill

C4 bump

Build-up Layers

Build-up Package Substrate

Fig. 1.31 Unimicron’s 2.3D with a fan-out (chip-last) RDL interposer fabricated with ABF (ajinomoto buildup film) 20mm

Flip chip with μbump

Chip Fine metal L/S RDL-substrate

Chip 2B

Underfill

Chip 2A

Chip

Chip 2A

20mm

Chip 1

Chip 1

Hybrid Substrate

InterconnectLayer

Build-up substrate or HDI

CHIP 1

CHIP 2A Cu-pillar Solder

ML1 ML2

PAD

Underfill RDLs

Solder Ball Via filled with conductive paste

8-Layer HDI

Fig. 1.32 Unimicron’s 2.3D IC integration with an interconnect layer

InterconnectLayer

1.7 2.5D IC Integration

29

UMC (for AMD) [1] and TSMC’s CoW-on substrate (CoWoS) (for Xilinx [96–110], Altera [111, 112], and Nvidia [113]). Xilinx/TSMC’s 2.5D IC integration [114] was the first one in production (shipped in 2013).

1.7.1 AMD/UMC’s 2.5D IC Integration Figure 1.33 shows AMD’s Radeon R9 Fury X graphics processor unit (GPU) shipped in the second half of 2015. The GPU is built on TSMC’s 28-nm process technology and is supported by four HBM cubes manufactured by Hynix. Each HBM consists of four DRAMs with Cu-pillar + solder cap bumps and a logic base with TSVs straight through them. Each DRAM chip has > 1000 TSVs. The GPU and HBM cubes are on top of a TSV interposer (28 mm × 35 mm), which is fabricated by UMC with 64-nm process technology. Some cross section SEM images are also shown in Fig. 1.33. It can be seen that the GPU and the HBM are supported by the TSV interposer with μbumps (Cu-pillar + solder cap). The TSV interposer is supported by the four-two-four build-up package substrate with C4 bumps.

The GPU (23mm x 27mm) is fabricated by TSMC's 28nm Process technology

TSV

C4-bump HBM HBM

HBM HBM

GPU

4-2-4 Build-up substrate

Core

Stiffener Ring

GPU with microbumps

The Si-interposer (28mm x 35mm) is fabricated by UMCís 65nm process technology

TSV

Organic Substrate (54mm x 55mm) is with 2111 balls at 1.2mm pitch

TSVInterposer C4

Solder Cu

μbump (Cu-Pillar + solder Cap)

Fig. 1.33 AMD/UMC’s 2.5D IC integration

Build-up organic substrate

30

1 State-Of-The-Art of Advanced Packaging

μbump TSV C4 bump Package Substrate Solder Ball

HBM2 by Samsung 4DRAMs

HBM2

GPU

μbump

Base logic die TSV Interposer (TSMCís CoWoS-2) Build-up Package Substrate C4 bump Solder Ball

Fig. 1.34 NVidia/TSMC’s 2.5D IC integration

1.7.2 NVidia/TSMC’s 2.5D IC Integration Figure 1.34 shows NVidia’s Pascal 100 GPU, which was shipped in the second half of 2016. The GPU is built on TSMC’s 16-nm process technology and is supported by four high bandwidth memory 2 (HBM2) (16 GB) fabricated by Samsung. Each DRAM chip has > 1000 TSVs. The GPU and HBM2s are attached with μbumps on top of a TSV interposer (1200 mm2 ) called CoWoS-2, which is fabricated by TSMC with 64-nm process technology. The TSV interposer is attached to a five-two-five organic package substrate with Cu–C4 bumps.

1.7.3 Some Recent Advances in 2.5D IC Integration (1) TSMC’s DTC TSV Interposer: Fig. 1.35a shows a conceptual structure of HPC on a new CoWoS platform by TSMC [115]. It consists of a logic die, HBM2Es, a silicon interposer, and a substrate. The logic and HBM2Es are first bonded sideby-side on the silicon interposer to form CoW with the fine pitch and HDI routing among the devices. In the silicon interposer, the deep trench capacitor (DTC)

1.7 2.5D IC Integration

31

Fig. 1.35 TSMC’s 2.5D IC integration with ODC (on-die capacitor) and DTC (deep trench capacitor). b Capacitance density. c Leakage density

is developed with the high aspect ratio silicon etch at dimensions. The high-k dielectric layer of the DTC is sandwiched between top and bottom electrode layers in the silicon trenches of aspect ratio over 10 to form the capacitor. Two distinct process sequences are available to realize the DTC in the silicon interposer [115]. Figure 1.35b also shows normalized capacitance density versus voltage of the DTC that is defined over the equivalent plenary surface area over the DTC structure. The capacitance density at 100 kHz measured by an inductance, capacitance, and resistance (LCR) meter is ∼300 nF/mm2 at zero applied voltage for the high-k dielectric film. It provides the capacitance density of an order higher than the metal–insulator–metal capacitor. Furthermore, Fig. 1.35c shows two normalized I–V curves for this high-k dielectric film measured at 25 °C and 100 °C, respectively. It can be seen that the measured leakage current at ± 1.35V bias is still below 1 fA/μm2 even at the testing temperature of 10 °C. This excellent characteristic prevents the additional power wasted in the DTC [115]. (2) Fraunhofer’s 3D Photonics TSV Interposer: Fig. 1.36 shows the conceptual layout of the single-mode router by Fraunhofer [117]. The interposer is intended

32

1 State-Of-The-Art of Advanced Packaging

to be assembled on a glass-based optical PCB (OPCB), where the interconnectivity between the optical layer of the OPCB and the Si interposer is done vertically by means of one mirror coupling element, as shown in Fig. 1.36 [117]. For the routing operation, each one of the 12 optical channels streamed from the OPCB is fed to a separate photodiode (PD) and its respective electronic transimpedance amplifier (TIA). The TIA can then perform optoelectronic conversion of the incoming signals, while the received electrical signal is then transmitted to an electronic driver amplifier prior to driving the modulation operation of a vertical cavity surface-emitting laser (VCSEL). Each VCSEL is then tuned to a different wavelength through current injection to match the channel spacing of the arrayed waveguide grating (AWG) multiplexer on the silicon layer. TSVs are used for electrical connection of frontside and backside of the wafer using underlying metals stack (left) and so-called optical TSV without metal layers at the TSV bottom (right).

VCSEL

SiO

Chip

Si Interposer

DRIVER SiO

2

Si

TSV

SiO

2

SiO

2

2

UBM

PCB

Glass Layer Waveguide

Electrical TSV

Metal

Optical TSV

No Metal

Fig. 1.36 Fraunhofer’s 3D silicon photonics interposer for Tb/s optical interconnects

1.8 3D IC Integration

33

Fibers (Optical Coupler)

Electrical

ASIC/Switch

TiA

Heat Sink

Signal Fiber

Laser

Driver

PD

Heat Spreader

Signal Fiber

Fiber Block Heat Spreader/Sink

ASIC/Switch TSV

PIC

EIC

μbump

Signal Fiber

TSV-interposer TSV-interposer Thermoelectric Cooler Dummy Fiber

C4 bump

Package Substrate Solder Ball PCB PCB

Fig. 1.37 Packaging for high-speed PIC (photonic IC) and EIC (electronic IC) devices

(3) TSV Interposer for PIC and EIC: The TSV-interposer integration platform for photonic IC (PIC) and electronic IC (EIC) of high-speed and high-bandwidth applications is a very hot topic of co-packaged optics (CPO) nowadays. Figure 1.37 shows a conceptual layout of a 2.5D IC integration of PIC and EIC devices. It can be seen that the package substrate is supporting the TSV interposer, which is supporting the ASIC/switch, EIC and PIC with C2 μbumps. The TSV interposer also supports the fiber assembly with a fiber block for the PIC, which requires very high alignment accuracy (1 μm) in order to achieve good optical coupling efficiency. The TSV interposer is with a deep trench or U-groove for the dummy fiber placement.

1.8 3D IC Integration The 3D integration [9, 11, 20, 21, 140–162] consists of at least 3D IC packaging and 3D IC integration. First, by definition, both 3D IC packaging and 3D IC integration are for stacking the chips in the vertical direction. The key difference between 3D IC integration and 3D IC packaging is 3D IC integration that uses TSVs [10–12], but 3D IC packaging does not.

34

1 State-Of-The-Art of Advanced Packaging

1.8.1 3D IC Packaging (Without TSVs) (1) Kinds of 3D IC Packaging: There are many different kinds of 3D IC packaging. Figure 1.38 schematically shows just a few. Figure 1.38a shows the memory chips stacked with wirebonds. Figure 1.38b shows the two chips are face-toface solder bumped flip-chip and then with wire bonds to the next level of interconnect. Figure 1.38c shows that the two chips are back-to-back bonding; the bottom chip is solder bumped flipchip to the substrate; and the top chip is with wire bonds to the substrate. Figure 1.38d shows that the two chips are face-to-face solder bumped bonding, and the top chip is with solder ball to the substrate. Figure 1.38e shows a PoP for the application chipsets (application processor (AP) + memory). It can be seen that, in the bottom package, the AP is solder bumped flipchip on a package substrate with underfill. The top package is used to house the memories, which is usually cross stacked and wire-bonded on a coreless organic substrate. Figure 1.38f shows another kind of PoP formation for the application chipset. In the bottom package, the AP is fanned-out with RDLs and then solder balled on a PCB. The wafer bumping for flip-chip, package substrate, and underfill are eliminated. The upper package remains the same, which is to house the memory chips. In this section, only PoP with fan-out packaging is briefly mentioned. For other kinds of 3D IC packaging, please read [1, 10–12]. (2) 3D IC Packaging—PoP with Fan-Out Technology: The PoP of the AP chipset with fan-out packaging was first proposed by Statschippad (2012) [141]. In September 2016, TSMC/Apple [142, 143] put the PoP of AP with integrated fan-out (InFO) technology into HVM. This is very significant since this means that fan-out is not just only for packaging small chips, such as baseband, power management IC (PMIC), radio frequency (RF) switch/transceiver, RF radar, audio codec, microcontroller unit, and connectivity ICs; it can also be used for packaging high-performance and large (> 120 mm2 ) system on chip (SoC), such as APs. Figure 1.39 shows the schematic and SEM images of the PoP for the AP chipset in the iPhone. The PoP of the AP (A12) and the mobile DRAMs is fabricated using TSMC’s InFO technology [142, 143]. In order to have better electrical performance, there are a few integrated passive devices (IPDs), which are solder bumped flip-chips at the bottom of the fan-out package, as shown in Fig. 1.39. There are three RDLs, and the minimum metal L/S is 8 μm. The pitch of the solder balls of the package is 0.35 mm. Recently, TSMC’s 4-nm process technology has been used for A16 (shipped in September 2022). Figure 1.40 shows Samsung’s smartwatch in a PoP format (shipped in August 2018). The upper package houses the memory embedded PoP (ePoP), which consists of 2-DRAM, 2NAND flash, and 1NAND-controllers. These memories are wirebonding on a three-layer coreless package substrate, as shown in Fig. 1.40. The dimensions of the upper package are 8 mm × 9.5 mm × 1 mm. The bottom package houses the AP and PMIC side-by-side by their fan-out panel-level packaging technology. The chip size of the AP is ∼ 5 mm × 3 mm, and that of the PMIC is 3 mm

1.8 3D IC Integration

35 Wirebond

Wirebond

Memory3 Memory2 Memory1

Memory Memory

Substrate Chip

(a) Package Substrate Chip1

Wirebond

PCB

Chip2 Substrate

(e)

(b) Wirebond Chip1 Chip2

Memory Memory

Substrate (c)

EMC

Chip

EMC

Fan-out RDLs

Chip1 Chip2

PCB

Substrate (d)

(f)

Fig. 1.38 Few examples on 3D IC packaging (without TSV). a Memory chips stacked with wirebonds. b Two chips are face-to-face solder bumped flip-chip and then with wire bonds to the next level of interconnect. c Two chips are back-to-back bonding; the bottom chip is solder bumped flip-chip to the substrate and the top chip is with wire bonds to the substrate. d Two chips are face-to-face solder bumped bonding and the top chip is with solder ball to the substrate. e PoP with flip chip for the application processor chipsets. f PoP with fan-out for the application processor chipsets

× 3 mm. The key process steps [144] are first to make a cavity on a PCB, then place the chips on the cavity, and laminate an EMC. It is followed by attaching to a carrier, making the RDLs, and mounting the solder balls.

1.8.2 3D IC Integration (with TSVs) There are many different kinds of 3D IC integration with TSVs, such as those schematically shown in Fig. 1.41. It can be seen from Fig. 1.41a that the DRAMs and base logic are stacked with TSVs, microbumps, and underfill. Figure 1.41b shows that a high bandwidth memory chip is attached (with microbumps) on logic with TSVs. Figure 1.41c shows a bumpless chip, which is hybrid bonding on another bumpless chip with TSVs. (1) 3D IC Integration—HBM Specifications: Fig. 1.42 shows the HBM, HBM2, HBM2E, and HBM3. They work with SoC and are a must [113] for HPC

36

1 State-Of-The-Art of Advanced Packaging PoP

AP SoC

3-Layer Coreless Package Substrate

Wirebond Over Mold Memory Memory

Solder Ball Underfill

EMC TIV

A12 AP RDLs

9.9mm x 8.4mm 13.4mm x 14.4mm x 0.815mm

3-Layer Coreless Package Substrate

Memories cross-stacked with wirebonds

Solder bumped flip chip IPD

Solder Ball

A12 AP (150μm) EMC

RDLs

EMC

PCB

Solder bumped flip chip IPD

A12 AP

Solder balls at 0.35mm-pitch

Solder balls

RDLs

Fig. 1.39 Apple/TSMC’s PoP with InFO for the iPhone’s AP chipset 8mm x 9.5mm x 1mm Memory ePoP 2DRAM, 2NAND, 1Controller 3L Package substrate (90µm) 3L Organic Substrate

Underfill

ABF 4RDLs

PMIC

AP

ABF

Solder Ball

Solder Ball

PCB

Package substrate

3L Organic Substrate

AP (5mmx3mm)

Underfill

Solder Ball

ABF

RDL

Fig. 1.40 Samsung’s PoP with FOPLP for their smartwatches

Memory ePoP

PMIC

RDL Solder Ball

ABF

1.8 3D IC Integration

37

Underfill μbump

DRAM4

Memory

Bumpless Chip

μbump DRAM3

TSV

DRAM2

Chip

CPU/ Logic

TSV

TSV

DRAM1

Logic Base Chip

(a)

Package Substrate

(b)

(c)

Fig. 1.41 Examples on 3D IC integration. a HBM with μbumps and TSVs. b CoC with TSVs and μbumps. c CoC with TSVs and bumpless

applications driven by 5G and AI, as shown in Fig. 1.43. In the whole world, only Hynix and Samsung make the HBM chips/modules. Recently, Micron also wants to make it. HBM uses less power but posts higher bandwidth than on double data rate 4 (DDR4) or graphics double data rate 5 (GDDR5) memory with smaller chips, making it appealing to graphic card vendors. HBM technology works by vertically stacking memory chips on top of one another. The memory chips are connected through TSVs and μbumps. In addition, with two 128-bit channels per die, HBM’s memory bus is wider than that of other types of DRAM memory. The first HBM memory cube (with four DRAMs) was produced by Hynix in 2013. Hynix also introduced the HBM2, HBM2E and HBM3 and has secured a market share of 60-70 percent. Recently, Hynix and Samsung enjoy a rush of order for the ChatGPT AI HBMs. HBM2 debuted in 2016, and in December 2018, the JEDEC updated the HBM2 standard. The updated standard is commonly referred to as both HBM2 and HBM2E (to denote the deviation from the original HBM2 standard). The HBM2 standard allows up to 12 dies per stack for a maximum capacity of 24 GB. The standard also pegs memory bandwidth at 307 GB/s, delivered across a 1024-bit memory interface separated by eight unique channels on each stack. Originally, the 2 standard called for up to eight dies in a stack (as with HBM) with an overall bandwidth of 256 GB/s. The HBM3 standard is available which supports up to 6.4 Gbps maximum pin transfer rate, 64-GB capacities and speeds up to 512 GB/s. (2) 3D IC Integration—HBM Assembly: Both Samsung and Hynix use the highbonding force TCB of the C2 (Cu-pillar + solder cap) bumped DRAMs with NCF (after singulation from the NCF laminated C2 bumped wafer), as shown in Fig. 1.6d, to fabricate the 3D IC integration stack, as shown in Fig. 1.42. This 3D memory cube is stacked one chip at a time and each chip takes ∼10 s for the underfill film to gel, the solder to melt and solidify, and the film to cure. Throughput is a problem, however. For the solution to this problem, please

38

1 State-Of-The-Art of Advanced Packaging HBM2 DRAM8 DRAM7

HBM (high bandwidth memory)

DRAM6

DRAM4

DRAM

DRAM5

TSV

DRAM3

TSV

DRAM4

DRAM2

μSolder Joint

DRAM1

DRAM3 DRAM2

Logic Base Chip

μbump (Cu + solder)

NCF (Underfill)

DRAM1 HBM2E (HBM2 Evolutionary)

Max Pin Transfer Rate Max Capacity Max Bandwidth

Logic Base Chip

HBM

HBM2 (Original)

HBM2/HBM2E (Current)

HBM3

1Gbps 4GB 128GBps

2Gbps 8GB 256GBps

2.4Gbps 24GB 307GBps

6.4Gbps 64GB 512GBps

Fig. 1.42 HBM, HBM2, HBM2E, and HBM3

C2 µSolder Joints TSV

C2 µSolder Joints

Cu µSolder Joints

Cu

HBM

SoC CPU/GPU/FPGA/ASIC

DRAM

Cu-C4 Solder Joints TSV Cu

Logic RDLs

TSV

C4

TSV

C4

TSV-interposer

Cu

Build-up Package Substrate

Solder Joint

PCB Fig. 1.43 2.5D IC integration for HPC. The passive TSV interposer is supporting the SoC and HBM

1.8 3D IC Integration

39

read [1, Fig. 7.35]. Hybrid bonding of the DRAM wafers could increase the throughput [27]. (3) 3D IC Integration with Microbump: Fig. 1.44 shows IME’s memory chip and logic chip with TSVs bonded with μbumps. The design, material, process, and fabrication of the test structure have been reported in [145]. The SEM image of the structure, especially the TSVs portion, is also shown in Fig. 1.44. Furthermore, the μbump (Cu-pillar + Sn cap) and under bump metallization (UBM) (electroless Ni immersion Au) of the interconnect are shown in Fig. 1.44. In July 2020, Intel shipped the “Lakefield” processor with their FOVEROStechnology, as shown in Fig. 1.45 [146–148]. It should be noted that this is the very first HVM processors for mobile products, such as the notebook by 3D IC integration. (4) 3D IC Integration with Bumpless: TSMC has been publishing a few papers on bumpless hybrid bonding of chip on chip with TSVs [29, 30, 151], as shown in Figs. 1.10 and 1.11. Also, Intel announced [41, 149] a Cu–Cu hybrid bonding called FOVEROS Direct, as shown in Fig. 1.12. Memory chip Top (memory) chip

μbumps

μbumps between the Memory and Logic

UBM pad Bottom (ASIC) chip

TSV

C4 bump

Metal pad

TSV

Logic chip at the bottom

Top Chip Passivation Ti adhesion

Cu seed Plated Cu Plated Sn

Electroless Ni

Immersion Au

TSV Passivation 2 Passivation 1

Bottom Chip

Fig. 1.44 3D IC integration: the memory chip is microbumped on the ASIC chip with TSVs

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1 State-Of-The-Art of Advanced Packaging μbumps RDLs

Active TSV-interposer

TSVs

C4 bump

µbump

μbumps 10nm Compute Die (Chiplets)

22FFL Base Die

TSV Active Interposer

RDLs

PackageSolder Substrate Ball Solder Ball

TSV

C4 bump

Fig. 1.45 3D IC integration: Intel’s chiplets are face-to-face microbumped on the active TSV interposer

1.9 Chiplet Design and Heterogeneous Integration Packaging Recently, chiplet design and heterogeneous integration packaging are getting lots of tractions [114, 146–164]. FPGA, such as Xilinx/TSMC’s Virtex, microprocessors, such as AMD’s extreme performance yield computing (EPYC), and Intel’s Lakefield are in HVM with chiplet designs and heterogeneous integration packaging. They will be briefly presented in this section. The SoC and the definition and advantages/disadvantages of chiplet design and heterogeneous integration packaging will be briefly mentioned first.

1.9.1 System on Chip (SoC) SoC integrates ICs with different functions, such as central processing unit (CPU), graphic processing unit (GPU), and memory, into a single chip for the system or subsystem. The most famous SoC is Apple’s APs, and their number of transistors versus year with various feature sizes (process technology) is shown in Fig. 1.46 from A10 to A16. It shows the power of Moore’s law, which increases the number of transistors and, thus, functionalities with a reduction of feature size. Unfortunately,

1.9 Chiplet Design and Heterogeneous Integration Packaging

41

25 Predicted A17

A16 A15

15

3nm

A14

10

2016

2017

2018

5nm

2019

2020

4nm

14nm

0

7nm

A11 A10

7nm

5

5nm

A13 A12

10nm

Transistors (billion)

20

2021

2022

2023

Year It is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC.

Fig. 1.46 Apple’s APs: transistors versus A10–A17 in terms of processing technology and year

it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. According to International Business Strategies [164], Fig. 1.47 shows the advanced design cost versus feature size through 5 nm. It can be seen that it will take more than $500 million to just design the 5-nm feature size. For the 5-nm process technology high manufacturing yield development, it will take another $1 billion. The effect of chip size on semiconductor manufacturing yield is shown in Fig. 1.48. It can be seen that the larger the chip size, the lower the semiconductor manufacturing yield.

1.9.2 Chiplet Design and Heterogeneous Integration Packaging Chiplet design and heterogeneous integration packaging contrast with SoC. Chiplet design and heterogeneous integration packaging redesign the SoC into smaller chiplets and then use packaging technology to integrate the dissimilar chiplets with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes, and companies into a system or a subsystem [1, 13] (Figs. 1.49, 1.50, 1.51, 1.52 and 1.53). A chiplet is a functional integrated circuit (IC) block that is often made of reusable intellectual property (IP) blocks. There are at least five different chiplet design and heterogeneous integration packaging, as shown in Figs. 1.49, 1.50, 1.51, 1.52 and 1.53, namely, (1) chip partition and heterogeneous integration (driven by cost and technology optimization), Fig. 1.49a,

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1 State-Of-The-Art of Advanced Packaging

Advanced Design Cost (M)

$580

$542.2

Validation Prototype $435

Software $297.8 $290

Physical

$174.4 $145

Verification

$106.3 $28.5

$37.7

$51.3

65

40

28

$70.3

Architecture IP Qualification

0 22

16

10

7

5

Feature Size / Process Technology (nm)

Fig. 1.47 Advanced design cost of semiconductor chip versus feature size (processing technology)

90

Monolithic Chip 2-Chiplet Design 3-Chiplet Design 4-Chiplet Design

Yield (% of good dies)

80 70 60 50 40 30 20 10 0 10

50

100

150

200

250

300

350

Chip Area (mm2) Fig. 1.48 Yields versus chip area for various chiplet designs and monolithic chips

(2) chip split and heterogeneous integration (driven by cost and semiconductor manufacturing yield), Fig. 1.49b, (3) multiple system and heterogeneous integration with thin-film layer directly on top of a build-up package substrate (2.1D IC integration), Fig. 1.50, (4) multiple system and heterogeneous integration with TSV-less interposer (2.3D IC integration), Fig. 1.51, and (5) multiple system and heterogeneous integration with TSV interposers (2.5D and 3D IC integration), Fig. 1.52. In chip partition and heterogeneous integration, Fig. 1.49a, the SoCs, such as the logic and I/Os, are partitioned into functions (chiplets): logic and I/O. These chiplets can be stacked (integrated) by the front-end CoW or WoW methods [29, 30, 151]

1.9 Chiplet Design and Heterogeneous Integration Packaging

I/O

I/O

I/O

Logic

Logic I/O I/O Partition Chiplets SoC

43

μBump, Bumpless, CoW, WoW

Heterogeneous Integration

Frontend Chiplets Integration (Optional), e.g., SoIC

Backend Chiplets Packaging Integration on the same substrate

(a) Chip partition and heterogeneous integration (Driven by cost and technology optimization)

Logic Split SoC

Logic1 Logic2

μBump, Bumpless, CoW, WoW

Heterogeneous Integration

Logic3

Frontend Chiplets Integration (Optional), e.g., SoIC

Backend Chiplets Packaging Integration on the same substrate

Chiplets

(b) Chip split and heterogeneous integration (Driven by cost and yield)

Fig. 1.49 Chiplet design and heterogeneous integration packaging: a chip partition and heterogeneous integration (driven by cost and technology optimization). b chip split and heterogeneous integration (driven by cost and yield)

HBM SoC CPU/GPU/FPGA/ASIC

DRAM/HBM SoC Substrate

Substrate

Microbump

DRAM

Logic

Chip

Chip

PCB

Multiple System Thin-film layer

Build-up Package Substrate Build-up Package Substrate

BGA Ball PCB PCB

2.1D IC Integration

Fig. 1.50 Chiplet design and heterogeneous integration packaging: multiple system and heterogeneous integration with thin-film layers on top of the build-up package substrate

and then assembled (integrated) on the same substrate of a single package by using heterogeneous integration techniques, Fig. 1.53. It should be emphasized that the front-end chiplets’ integration can yield a smaller package area and better electrical performance but is optional. In chip split and heterogeneous integration, Fig. 1.49b, the SoC, such as logic, is split into smaller chiplets, such as logic1, logic2, and logic3. These chiplets can be

44

1 State-Of-The-Art of Advanced Packaging HBM SoC CPU/GPU/FPGA/ASIC

DRAM

DRAM/HBM Logic

SoC Substrate

Microbump

Substrate Fan-out RDL-interposer

PCB

Cu

C4 bump

Multiple System Build-up PackageSubstrate Build-up Package Substrate

BGA Ball

PCB

PCB

2.3D IC Integration

Fig. 1.51 Chiplet design and heterogeneous integration packaging: multiple system and heterogeneous integration with TSV-less interposers (organic interposers)

HBM SoC CPU/GPU/FPGA/ASIC DRAM/HBM SoC Substrate

Microbump

Logic

Substrate

RDL TSV-interposer

TSV

PCB

Multiple System

DRAM

Cu C4 bump Build-up Package Substrate Build-up Package Substrate

BGA Ball PCB PCB

2.5D IC Integration

Fig. 1.52 Chiplet design and heterogeneous integration packaging: multiple system and heterogeneous integration with TSV interposers

stacked (integrated) by the front-end CoW or WoW methods and then assembled on the same substrate of a single package by using heterogeneous integration techniques. Again, the front-end integration of chiplets is optional. In multiple system and heterogeneous integration with thin-film layers directly on top of the build-up package substrate, Fig. 1.50, the SoC such as the CPU, logic, and HBM are supported by a build-up package substrate with thin-film layers. This is driven by performance and form factor and for high-density and high-performance applications. In multiple system and heterogeneous integration with TSV-less interposers, Fig. 1.51, the SoC such as the CPU, logic, and HBM are supported by a fine metal

1.9 Chiplet Design and Heterogeneous Integration Packaging

Chip (CPU) FAB-1 5nm 12î -wafer

Packaged memory stack

Heterogeneous integration or SiP CPU 1 CPU 2

PBGA Memory Stack

I/O

GPU 1

Chip (I/O) GPU 2

Chip (I/O) FAB-2 90nm 8î -wafer

45

Time-to-market Less IP issues Flexibility Low cost alternative than SoC Optimized signal integrity and power Better thermal performance

Chip (GPU) FAB-3 7nm 12î -wafer

Fig. 1.53 All chips, chiplets, and discrete are on the same substrate of a heterogeneous integration package

L/S RDL-substrate (organic-interposer) and then on a build-up package substrate. This is driven by performance and form factor and for high density and performance applications. In multiple system and heterogeneous integration with TSV-interposers, Fig. 1.52, the SoC such as the CPU, logic, and HBM are supported by a passive (2.5D) or active (3D) TSV-interposer and then on a build-up package substrate. This is driven by performance and form factor and for extremely high-density and high-performance applications.

1.9.3 Advantages and Disadvantages The key advantages of chiplet design and heterogeneous integration packaging, compared with SoCs, are yield improvement during manufacturing. For chip partitioning and/or splitting, the size of the chiplet is smaller than the SoC, and thus, it leads to a higher semiconductor manufacturing yield, which translates to lower manufacturing costs. Figure 1.48 shows the plots of yield (percent of good dies) per wafer versus chip size for monolithic design and two-, three-, and four-chiplet designs [165]. It can be seen that a 360-mm2 monolithic die will have a yield of 15%, while a four-chiplet design (each 99 mm2 ) more than doubles the yield to 37%. The total die area of the four-chiplet design incurs a ∼10% area penalty (36 mm2 for a

46

1 State-Of-The-Art of Advanced Packaging

combined silicon area of 396 mm2 ) but the significant improvement in yield, which directly translates to lower cost. Also, chip partitioning will enhance the time-tomarket. Furthermore, the use of chiplets with CPU cores can reduce silicon design and manufacturing costs [166]. Finally, there is also thermal benefit to using chiplets as the chips are spread out across the package. The disadvantages of chiplet design and heterogeneous integration packaging are: (1) additional area for interfaces (larger package size); (2) higher packaging costs; (3) more complexity and design effort; and (4) past methodologies are less suitable for chiplets.

1.9.4 Xilinx’s Chiplet Design and Heterogeneous Integration Packaging In 2011, Xilinx asked TSMC to fabricate their FPGA SoC with the 28-nm process technology. Because of the large chip size, the yield was very poor. Then, Xilinx redesigned and split the large FPGA into four smaller chiplets, as shown in Fig. 1.54, and TSMC manufactured the chiplets at high yield and packaged them on the CoWoS. On October 20, 2013, Xilinx and TSMC [114] have jointly announced the production release of the Virtex-7 HT family with 28-nm process technology, what the pair claims is the industry’s first chiplet design and heterogeneous integration package in production.

For better manufacturing yield (to save cost), a very large SoC has been split into 4 smaller chips.

(10,000+)

The key function of the RDLs on the interposer is to perform lateral communications between the chips. With 4 RDLs

Fig. 1.54 Xilinx’s chiplet design and heterogeneous integration packaging (chip split)

1.9 Chiplet Design and Heterogeneous Integration Packaging

47

1.9.5 AMD’s Chiplet Design and Heterogeneous Integration Packaging Excited by the Defense Advanced Research Projects Agency (DARPA) program called Common Heterogeneous Integration and Intellectual Property Reuse Strategies (CHIPS), in 2017 UCSB and AMD [156] proposed a future very highperformance system shown in Fig. 1.55. This system comprises a CPU chiplet and several GPU chiplets, as well as HBMs on a passive TSV-interposer and/or on an active TSV-interposer with RDLs. In mid-2019, AMD introduced the second-generation EPYC, 7002-series, codename Rome, which doubled the number of cores to 64. In [154, 155], it shows that the Rome server product makes use of a nine-two-nine package for signal connectivity with four layers above the package core for signal routing, Fig. 1.56a]. For high-performance servers and desktop processors, there are many I/Os. Analog devices and bump pitches for I/Os benefit very little from leading-edge technology and are very costly. One of the solutions is to partition the SoC into chiplets, CPU Chiplet

GPU Chiplet

Fig. 1.55 UCSB/AMD’s chiplets on passive-interposer and active-interposer

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1 State-Of-The-Art of Advanced Packaging

CCD

CCD

CCD

CCD

CCD

CCD

2D IC Integration

(a)

The I/O and CCD (core complex die or CPU compute die) are partitioned The CCD is split into two chiplets (7nm process technology) The I/O chip is with 14nm process technology

CCD

CCD

I/O I/O

9-2-9 package substrate

ENGINEERING THE AMD3D 3D CHIPLET V-CacheTMARCHITECTURE Structural Silicon 64MB L3 Cache Die

(b)

Direct Cu-Cu Bonding

TSVs For Si-to-Si communication Up to 8-Core ìZen 3î CCD

3D IC Integration Fig. 1.56 Chiplet design and heterogeneous integration packaging: a AMD’s EPYC and b AMD’s 3D V-cache

reserving the expensive leading-edge silicon for CPU core while leaving the I/Os and memory interfaces in n − 1 generation silicon [154, 155]. Another solution is to split the CPU core into smaller chiplets. In this case, each core complex die or CPU compute die (CCD) is split into two smaller chiplets. AMD used the expensive 7-nm process technology fabricated by TSMC (in early 2019) for the core CCD chiplets and moved the DRAM and logic to a mature 14-nm I/O die fabricated by GlobalFoundries. The second generation EPYC is a 2-D chiplets IC integration technology, i.e., all the chiplets are side by side on the nine-two-nine build-up package substrate, as shown in Fig. 1.56a. AMD’s next chiplet design and heterogeneous integration packaging [156–158] is 3D chiplets’ integration, i.e., the chiplets are (stacked) on top of the other chiplets, such as logic, so-called the active TSV interposer, as shown in Fig. 1.56b. It is a special Ryzen 9 5900X prototype chip leveraging a 3D V-Cache stack, which enables triple the amount of cache that its cores normally have access to (32 MB versus 96 MB of L3 cache). The first 3D V-Cache chips with 3D chiplet design and heterogeneous integration packaging has been shipped in Q1 of 2022.

1.9 Chiplet Design and Heterogeneous Integration Packaging

49

1.9.6 CEA Leti’s Chiplet Design and Heterogeneous Integration Packaging During IEEE/ECTC2019, Leti/STMicroelectronics demonstrated the feasibility of chiplets on active TSV-interposer. There are six chiplets on a TSV-interposer with the 64 nm CMOS devices called INTACT (active interposer) [160], Fig. 1.57.

Fig. 1.57 Leti/STMicroelectronics’ chiplet on an active-interposer (INTACT)

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1 State-Of-The-Art of Advanced Packaging

1.9.7 Intel’s Chiplet Design and Heterogeneous Integration Packaging In July 2020, Intel shipped their mobile (notebook) processor “Lakefield,” which is based on their FOVEROS technology (see Figs. 1.45 and 1.58). The SoC is partitioned (e.g., CPU, GPU, and LPDDR4) and split (e.g., the CPU is split into one big CPU and four smaller CPUs) into chiplets, as shown in Figs. 1.45 and 1.58. These chiplets are then face-to-face bonded (stacked) on an active TSV interposer (a large 22FFL base chip) with a CoW process [146–148]. The interconnect between the chiplets and the logic base chip is microbump (Cu pillar + SnAg solder cap), as shown in Fig. 1.45. The interconnect between the base chip and the package substrate is C4 bumps and between the package substrate and PCB is solder balls. The final package formant is a PoP (12 mm × 12 mm × 1 mm), as shown in Figs. 1.45 and 1.58. The chiplet heterogeneous integration is in the bottom package, and the upper package is housing the memories with wire bonding technology (Fig. 1.45). The fabrication of the chiplets is with Intel’s 10-nm process technology and of the base chip is 22 nm. Since chiplets’ size is smaller and not all the chips are using the 10-nm process technology, the overall yield must be higher, and thus, it translates 10mm 3D IC Integration

10mm

(a)

The memory and graphics are partitioned The large CPU is split into 5 smaller CPUs (10nm process technology) All the tiles (or chiplets) are attached on an active interposer

Memory, Modem, …

Compute Chip

(b)

FTF Micro-Bumps

Thru-Silicon Vias Solder Bumps

Active Interposer

Package Substrate

Fig. 1.58 Intel’s chiplet design and heterogenous integration packaging. a Chiplets in Lakefield processor. b FOVEROS packaging for Lakefield processor

1.9 Chiplet Design and Heterogeneous Integration Packaging

51

47 Chiplets (16 HPC) Max. size = 41mm2 (8)

(2) (650mm2) (8) (2)

(11)

77.5mm x 62.5mm

Fig. 1.59 Intel chiplet design and heterogeneous integration packaging: spaceship of GPU

to lower cost. It should be noted that this is the very first HVM of 3D chiplets’ integration. Also, this is the very first HVM processors for mobile products, such as the notebook by 3D IC integration. During the Intel Architecture Day (August 13, 2020), they announced a Cu–Cu hybrid bonding for their FOVEROS technology. They called it FOVEROS Direct [41] and demonstrated that, with bumpless hybrid bonding (see Fig. 1.12), the pitch can go down to 10 μm instead of 50 μm, such as the Lakefield shown in Figs. 1.45 and 1.58. One of Intel’s chiplet designs and heterogeneous integration packaging is called Ponte Vecchio GPU, or the “Spaceship of a GPU” [41, 150], which is the largest and most chip designed to date. The Ponte Vecchio GPU is making use of several key technologies, which will power 47 different compute chiplets based on different process nodes and architectures, as shown in Fig. 1.60. While the GPU primarily makes use of Intel’s 7-nm extreme ultraviolet lithography (EUV) process node, Intel will also be producing some Xe-HPC compute dies through external fabs (such as TSMC with the 5-nm note). To be precise, 47 chiplets consist of 16 Xe-HPCs (internal/external), eight Rambos (internal), two Xe-Bases (internal), 11 EMIBs (internal), two XeLinks (external), and eight HBMs (external). The maximum top-die (chiplet) size = 41 mm2 ; the basedie size = 650 mm2 ; die-to-die pitch = 36 μm; and package size = 77.5 mm × 62.5 mm.

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1 State-Of-The-Art of Advanced Packaging

HBM

SoC-1 SoC-2

TSV

Interposer

SoC-3

CoWoS with SoIC

Package Substrate

PCB (a)

DRAM InFO PoP with SoIC

SoC-2

SoC-1

SoC-3

Fan-Out RDLs PCB (b) Fig. 1.60 TSMC chiplet design and heterogeneous integration packaging: a CoWoS with SoIC. b InFO PoP with SoIC

1.9.8 TSMC’s Chiplet Design and Heterogeneous Integration Packaging During the TSMC Annual Technology Symposium (August 25, 2020) TSMC announced their 3D fabric (3D fabrication) technology for mobile, HPC, automotive, and IoT applications [29, 30, 151, 152]. The 3D fabric provides chiplet design and heterogeneous integrations packaging that is fully integrated from front to back. The application-specific platform leverages TSMC’s advanced front-end wafer technology, such as SoIC (see Fig. 1.10), open innovation platform design ecosystem, and 3D fabric for fast improvements and time-to-market. In 3D backend package integration, CoWoS’ increased envelope, and enriched technology content offers exceptionally high computing performance and high memory bandwidth to meet HPC needs on clouds, data centers, and high-end servers (Fig. 1.60). In another 3D backend package integration, InFO derivative technology offers memory-to-logic, logic-to-logic, PoP, and so on applications. The HVM of SoIC + CoWoS and SoIC + InFO is expected by the end of 2022.

1.10 Fan-In Packaging

53

1.10 Fan-In Packaging First, fan-in is a single-chip wafer-level (or panel-level) packaging, which is used to fabricate the wafer- (or panel-) level chip-scale package (W/PLCSP or simply WLCSP) [7, 167–298]. Strictly speaking, according to the criterion of this book, WLCSP should not be considered as advanced packaging. However, because of: (1) the delamination of the dielectric layer in the frontside of the WLCSP, which is particularly true for advanced nodes ( 100,000, and the metal L/S are less and

66

1 State-Of-The-Art of Advanced Packaging 10,000 Flip Chip TCB with large force and reflow of C2 Bumps (NCP/NCF)

Pin-Count

7,000

Flip Chip TCB with small force and reflow of C4 or C2 Bumps (CUF)

5,000

Flip Chip with mass reflow of C4 or C2 Bumps (CUF)

60μm 50μm 30μm

200

150

100

50

0

Pad-Pitch (μm) Fig. 1.74 Roadmap (in the next five years) for chip on organic substrates 200,000

Bumpless Flip Chip Hybrid Bonding CoC, CoW and WoW

Pin-Count

50,000

Flip Chip TCB with large force and reflow of C2 Bumps (NCP/NCF) CoC, CoW and WoW

10,000

Flip Chip TCB with small force and reflow of C4 or C2 Bumps (CUF) CoC, CoW and WoW

Flip Chip mass reflow of C4 or C2 Bumps (CUF) CoC, CoW and WoW 50μm 40μm

100

50

20μm

4μm

0

Pad-Pitch (μm) Fig. 1.75 Roadmap (in the next five years) for chip on chip, chip on TSV interposers, chip on silicon wafer, and silicon wafer on silicon wafer

equal to 1 μm; for fan-out (chip-first) RDL substrate (or interposer), the substrate size can be 600 mm2 , the pin-count can be 2500, and the metal L/S are larger and equal to 5 μm; for fan-out (chip-last) RDL-interposer, the substrate size can be as large as 2500 mm2 , the pin-count can be 5,000, and the metal L/S are larger

1.13 Summary and Recommendation

67

Can be > 100,000 6500

PIN-COUNT ON SUBSTRATE

6000

Bridge (L/S ≥ 2µm)

5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0

500

1000

1500

2000 2500 3000

3500 4000 4500

5000

SUBSTRATE SIZE (mm2)

Fig. 1.76 Roadmap (in the next five years) for various chiplets heterogeneous integrated substrates, such as TSV interposers and TSV-less interposers (e.g., embedded bridges, fan-out RDL-interposers with chip-first formation, fan-out RDL-interposers with chip-last formation, and buildup package substrates)

• • • • •

and equal to 2 μm; and for the bridges, the size is very small (≤ 64 mm2 ), the pin-count is little (< 2000), and the metal L/S are larger and equal to 2 μm. Fan-in six-side molded WLCSP has better solder joint reliability than the ordinary WLCSP. This is important for automotive electronics subjected to ADAS. Fan-outs, such as chip-first (face-down) and chip-first (face-up), have been in HVM for consuming products. Chip-first (face-down) is and will still be used the most. Chip-last or RDL-first is not in HVM yet but will be soon. The TSV-interposer integration platform for PIC and EIC of high-speed and highbandwidth applications is getting lots of traction. A couple of examples have been provided. A heterogeneous integration of AiP and baseband chipset with heat spreader/sink by chip-first and die face-down packaging for high performance and compact 5G millimeter wave system integration has been proposed. Roadmaps of Df and Dk for low-loss dielectric materials of advanced packaging are provided in Figs. 1.77 and 1.78, respectively.

68

1 State-Of-The-Art of Advanced Packaging 0.006

Fig. 1.77 Roadmap for Df (dissipation factor or loss tangent)

0.005 0.004

Df

10GHz ≦ Frequency ≦ 40GHz

0.003 0.002 0.001 0 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

Year

Fig. 1.78 Roadmap for Dk (dielectric constant or permittivity)

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Chapter 2

Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration

2.1 Introduction In this chapter, chiplet design and heterogeneous integration packaging [1–118], especially chip partition and heterogeneous integration and chip split and heterogeneous integration will be presented. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. System-on-chip (SoC) and DARPA (defense advanced research projects agency)’s efforts in chipet heterogeneous integration will be briefly mentioned first.

2.2 DARPA’s Efforts in Chipet Heterogeneous Integration DARPA has been making very good progress on heterogeneous integration in more than 15 years with more than 30 first-tire companies such as Intel, Micron, Cadence, Synopsys, Lockheed Martin, Northrop Grumman, Michigan University, and Georgia Institute of Technology, and their key programs in heterogeneous integration are briefly mentioned. DARPA’s first effort on heterogeneous integration is the COSMOS (compound semiconductor materials on silicon) program [1] which started in May 2007. COSMOS developed three unique approaches to the heterogeneous integration of (indium phosphide) (heterojunction bipolar transistors) with deep submicron Si (complementary metal-oxide semiconductor). COSMOS is now a diverse accessible heterogeneous integration (DAHI) program [2] thrust. The DAHI program is developing the following key technical challenges: (1) heterogeneous integration process development, (2) high-yield manufacturing and foundry establishment, and (3) circuit design and architecture innovation.

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging, https://doi.org/10.1007/978-981-19-9917-8_2

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

DARPA started the CHIPS (common heterogeneous integration and IP (Intellectual Property) reuse strategies) program [3] in 2017. The aim of the CHIPS program is to make modular computers out of chiplets. The CHIPS program is addressing integration standards, IP blocks, and design tools. Intel is providing a royalty-free license for their advanced interface bus technology to CHIPS program participants. Navy proposed a state-of-the-art heterogeneous integrated packaging (SHIP) program [4] in the mid-2019. The primary objective of the SHIP project will be to demonstrate a novel approach to a secure, assessable, and cost-effective state-ofthe-art integrated, design, assembly, and test leveraging the expertise of commercial industry. Designs must also adhere to the interface standards developed under the DARPA CHIPS program to ensure proper insertion and testability of the final product.

2.3 SoC (System-On-Chip) SoC integrates ICs with different functions such as CPU (central processing unit), GPU (graphic processing unit), memory, etc. into a single chip for the system or subsystem (Fig. 2.1). The most famous SoC is Apple’s application processors (AP), which are simply shown in Fig. 2.2 for A10 through A15. The number of transistor versus year with various feature size (process technology) is shown in Fig. 2.3. It can be seen the power of Moore’s law, which increases the number of transistors and functionalities with a reduction of feature size. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. According to International Business Strategies, Fig. 2.4 shows the advanced design cost vs. feature size through 5 nm. It can be seen that it will take more than $500 million to just design the 5 nm feature size. For the 5 nm process technology high manufacturing yield development it will take another $1 billion.

2.4 Chiplet Design and Heterogeneous Integration Packaging Chiplet design and heterogeneous integration packaging contrasts with SoC. Chiplet design and heterogeneous integration packaging redesigns the SoC into smaller chiplets and then uses packaging technology to integrate dissimilar chiplets with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem [5–9]. A chiplet is a functional integrated circuit (IC) block that is often made of reusable IP (intellectual property) blocks. As mentioned in Chap. 1, there are at least five different chiplet design and heterogeneous integration packaging, as shown in Figs. 2.5, 2.6, 2.7 and 2.8, namely, (1)

GPU

GPU

DDR

Fig. 2.1 System-on-chip (SoC)

103

GPU

GPU

DDR

2.4 Chiplet Design and Heterogeneous Integration Packaging

GPU

GPU

L3-cache

L3-cache

CPU

CPU1 CPU1 CPU1

NPU

cache

CPU2 cache

CPU CPU

CPU1

DDR

CPU1

DDR

cache

SL

NPU SL

cache

CPU CPU

chip partition and heterogeneous integration (driven by cost and technology optimization), Fig. 2.5, (2) chip split and heterogeneous integration (driven by cost and semiconductor manufacturing yield), Fig. 2.6, (3) multiple system and heterogeneous integration with thin-film layer directly on top of a build-up package substrate (2.1D IC integration), Fig. 2.7a, (4) multiple system and heterogeneous integration with TSV-less interposer (2.3D IC integration), Fig. 2.7b, and (5) multiple system and heterogeneous integration with TSV interposers (2.5D and 3D IC integration), Fig. 2.7c. (3)–(5) are driven by form factor and performance. In chip partition and heterogeneous integration, Fig. 2.5, the SoCs, such as the logic and I/Os, are partitioned into functions (chiplets): logic and I/O. These chiplets can be stacked (integrated) by the front-end CoW (chip-on-wafer) or WoW (waferon-wafer) methods and then assembled (integrated) on the same substrate of a single package by using heterogeneous integration techniques [10–40]. It should be emphasized that the front-end chiplets’ integration can yield a smaller package area and better electrical performance but is optional. This integration is the focus of this chapter. In chip split and heterogeneous integration, Fig. 2.6, the SoC, such as logic, is split into smaller chiplets, such as logic1, logic2, and logic3. These chiplets can be stacked (integrated) by the front-end CoW or WoW methods and then assembled on the same substrate of a single package by using heterogeneous integration techniques [10–40]. Again, the front-end integration of chiplets is optional. This integration is the focus of this chapter.

A11 consists of: More functions, e.g., 2core Neural Engine for Face ID Apple designed tri-core GPU 10nm process technology Transistors = 4.3 billion Chip area =89mm2

A11

Fig. 2.2 Apple’s application processor (AP): A10–A15

A10 consists of: 6-core GPU (graphics processor unit) 2 dual-core CPU (central processing unit) 2 blocks of SRAMs (static random access memory), etc. 16nm process technology Transistors = 3 billion Chip area = 125mm2

A10

A12 consists of: Eight-core Neural Engine with AI capabilities Four-core GPU (faster) Six-core CPU (better performance ) 7nm process technology Transistors = 6.9 billion Chip area = 83mm2

A12

A13 consists of: Eight-core Neural Engine with Machine Learning Four-core GPU (20% faster > A12) Six-core CPU (20% faster and 35% save energy > A12) 7nm process technology with EUV Transistors = 8.5 billion Chip area = 98.5mm2

A13 A15

A15 consists of: A14 consists of: 16-core Neural Engine 16-core Neural Engine with to speed up AI tasks Machine Learning (11 with Machine Learning trillion/s, 10 times faster > (15.8 trillion/s) A13) Four-core GPU, but 5Four-core GPU (30% faster core for iPhone Pro and > A13) 13Pro Max Six-core CPU (40% faster > Six-core CPU (faster > A13) A14) 5nm process technology 5nm process with EUV technology with EUV Transistors = 11.8 billion Transistors = 15 billion Chip area = 88mm2 Image signal processor

A14

104 2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

2.4 Chiplet Design and Heterogeneous Integration Packaging

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Advanced Design Cost (M)

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40

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Fig. 2.4 Advanced design cost of semiconductor chip versus feature size (processing technology) I/O

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μBump, Bumpless, CoW, WoW

Chiplet Designs

Frontend Chiplets Integration (Optional), e.g., SoIC

Heterogeneous Integration Backend Chiplets Packaging Integration

Fig. 2.5 Chip partition and heterogeneous integration driven by cost and technology optimization

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Frontend Chiplets Integration (Optional), e.g., SoIC

Backend Chiplets Packaging Integration

Fig. 2.6 Chip split and heterogeneous integration driven by cost and semiconductor manufacturing yield Fine Metal L/S RDL-Substrate (Organic Interposer) μbump Thin-Film Layers CHIP

CHIP

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(b)

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Thin-Film Layers = Fine Metal L/S RDL-Substrate (Organic Interposer) Fig. 2.7 Multiple system and heterogeneous integration. a 2.1D IC integration. b 2.3D IC integration. c 2.5D/3D IC integration

In multiple system and heterogeneous integration with thin-film layers directly on top of the build-up package substrate, Fig. 2.7a, the SoC such as the CPU, logic, and HBM are supported by a build-up package substrate with thin-film layers. This is driven by performance and form factor and for high-density and high-performance applications [41–49]. Because of the flatness of the build-up package substrate, the yield loss of this integration is very high and it is not in production today. This integration is out of the scope of this book. In multiple system and heterogeneous integration with TSV-less interposers, Fig. 2.7b, the SoC such as the CPU, logic, and HBM are supported by a fine metal L/S RDL-substrate (organic-interposer) and then on a build-up package substrate [50–81]. This is driven by performance and form factor and for high density and

2.5 Advantages and Disadvantages of Chiplet Design and Heterogeneous …

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90 Monolithic Chip 2-Chiplet Design 3-Chiplet Design 4-Chiplet Design

Yield (% of good dies)

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Fig. 2.8 Yields versus chip area for various chiplet designs and monolithic chips

performance applications. This integration is in small volume production today and will be discussed in Chap. 4. In multiple system and heterogeneous integration with TSV-interposers, Fig. 2.7c, the SoC such as the CPU, logic, and HBM are supported by a passive (2.D) or active (3D) TSV-interposer and then on a build-up package substrate [82–96]. This is driven by performance and form factor and for extremely high-density and highperformance applications. This integration is in volume production today and will be discussed in Chap. 3.

2.5 Advantages and Disadvantages of Chiplet Design and Heterogeneous Integration Packaging The key advantages of chiplet heterogeneous integrations comparing with SoCs are yield improvement (lower cost) during manufacturing, time-to-market, and cost reduction during design. Figure 2.8 shows the plots of yield (percent of good dies) per wafer versus chip size for monolithic design and 2-, 3-, and 4-chiplet design [10]. It can be seen that a 360mm2 monolithic die will have a yield of 15% while a 4-chiplet design (each 99mm2 ) more than doubles the yield to 37%. The total die area of the 4-chiplet design incurs a ~ 10% area penalty (36mm2 for a combined silicon area of 396mm2 ) but the significant improvement in yield which directly translates to lower cost. Also, chip partitioning will enhance the time-to-market. Furthermore, chiplets with CPU cores can reduce silicon design and manufacturing costs. Finally, there is also thermal benefit to using chiplets as the chips are spread out across the package.

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

The disadvantages of chiplet heterogeneous integration are: (1) additional area for interfaces, (2) higher packaging costs, (3) more complexity and design effort, and (4) past methodologies are less suitable for chiplets.

2.6 Xilinx’s Chiplet Design and Heterogeneous Integration Packaging In 2011, Xilinx asked TSMC to fabricate its field-programable gate array (FPGA) system-on-chip (SoC) with 28 nm process technology. Because of the large chip size, the yield was very poor. Then, Xilinx redesigned and split the large FPGA into four smaller chiplets as shown in Fig. 2.9 and TSMC manufactured the chiplets at high yield (with the 28 nm process technology) and packaged them on their chip-on-waferon-substrate (CoWoS) technology. CoWoS is a 2.5D IC integration, which is the key structure (substrate) to let those 4 chiplets do lateral communications. The minimum pitch of the four redistribution layers (RDLs) on the TSV-interposer is 0.4 μm, Fig. 2.10. On October 20, 2013, Xilinx and TSMC [11] have jointly announced the production release of the Virtex-7 HT family with 28-nm process technology, what the pair claims is the industry’s first chiplet design and heterogeneous integration package in production.

For better manufacturing yield (to save cost), a very large SoC has been split into 4 smaller chips.

(10,000+)

The key function of the RDLs on the interposer is to perform lateral communications between the chips. With 4 RDLs

Fig. 2.9 Xilinx/TSMC’s chiplet design and heterogeneous integration packaging

2.7 AMD’s Chiplet Design and Heterogeneous Integration Packaging

Chip

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Interposer C4 Bumps PTH

Build-up Layers

Core

Devices

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(Cannot see)

Si Solder Balls

Micro Bump

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4RDLs

The package substrate is at least (5-2-5)

TSV

Interposer

RDLs: 0.4μm-pitch line width and spacing Each FPGA has >50,000 μbumps on 45μm pitch Interposer is supporting >200,000 μbumps

Fig. 2.10 SEM cross section image of Xilinx/TSMC’s chiplet design and heterogeneous integration packaging

2.7 AMD’s Chiplet Design and Heterogeneous Integration Packaging AMD have been working on chiplet design and heterogeneous integration packaging for the past few years [12–19]. In mid-2019, AMD introduced the 2nd-generation EPYC (Extreme-performance yield computing), 7002-series, codename Rome which doubled the number of cores to sixty-four. The 2nd Gen EPYC is a new breed of server processors which sets a higher standard for data centers. It shows that Rome server product makes use of a 9-2-9 package (Fig. 2.11) for signal connectivity with 4 layers above the package core for signal routing. One of the signaling layers (others are similar) is shown in Fig. 2.12 along with the physical position of the CCD (CPU compute die), IOD (IO die), as well as main external DRAM (dynamic random-access memory) and SerDes interfaces. The AMD chiplets evolution (development) of the hybrid multi-die architecture is shown in Fig. 2.13. For high-performance servers and desktop processors the I/Os are very heavy. Analog devices and bump pitches for I/Os benefit very little from leading edge technology and is very costly. One of the solutions is to partition the SoC into chiplets, reserving the expensive leading-edge silicon for CPU core while leaving the I/Os and memory interfaces in n-1 generation silicon. Because AMD committed to keep the EPYC package size and pin-out unchanged, there need to be a close silicon/package co-design as the number of die increases from four in the first EPYC to nine in the 2nd Gen EPYC.

CCD

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

CCD

110

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CCD Chiplets (7nm process technology)

I/O chip (14nm process technology)

9-2-9 package substrate The I/O and CCD (core complex die or CPU compute die) are partitioned The CCD is split into 2 chiplets and is fabricated by 7nm process technology The I/O chip is fabricated by 14nm process technology

Fig. 2.11 AMD’s 2nd generation EPYC 2D chiplet heterogeneous integration on organic substrate

ROME

Matisse

128 total x 16 SERDES

72 Data + 8 Clk/Ctl (total/CCD)

3rd Gen Ryzen Processor Infinity Fabric (die-to-die) I/O Controllers and PHYs 2 x DDR4 PHYs

2nd Gen EPYC server processor Fig. 2.12 AMD’s 2nd generation EPYC server and desktop processor with chiplets

2.7 AMD’s Chiplet Design and Heterogeneous Integration Packaging Traditional Monolithic

Use the Most Advanced Technology Where it is Needed Most

1st Gen EPYC

Each IP in its Optimal Technology. 2nd Gen Infinity FabricTM Connected

111 2nd Gen EPYC

Centralized I/O Die Improves NUMA

Superior Technology for CPU Performance and Power

2nd Gen EPYC

SERVER Fig. 2.13 AMD’s chiplets evolution

The 2nd Gen EPYC chiplet performance versus cost is shown in Fig. 2.14. AMD reveal that on TSMC’s 7 nm process technology the cost to manufacture a 16-core monolithic die is more than double that of a multi-chiplets CPU. It can be seen from Fig. 2.14 that: (a) the lower the core counts, the lower the saving, (b) higher core counts and performance than possible with a monolithic design, (c) lower costs at all core count/performance points in the product line, (d) cost scales down with performance by depopulating chiplets, and (e) 14 nm process technology for IOD reduces the fixed cost. AMD also optimize the cost structure and improve die yields by using much smaller chiplets. AMD used the expensive 7 nm process technology by TSMC for the core cache dies and moved the DRAM and Pie logic to a 14 nm I/O die fabricated by Global Foundries. The 2nd-generation EPYC is a 2D chiplet design and integration technology packaging, i.e., all the chiplets are side-by-side on the same substrate of a single package. AMD’s future chiplet heterogeneous integration [19] will be 3D chiplets integration as shown in Fig. 2.15, i.e., the chiplets are (stacked) on top of the other chiplet such as logic, so called the active TSV-interposer. During IEEE/ISSC 2022 [12] and IEEE/ECTC 2022 [13], AMD introduced their 3D V-Cache chiplet design and integration technology packaging, Figs. 2.16, 2.17,

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous … 2.0 1.8

Normalized Die Cost

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 64 Cores

48 Cores Chiplet 7nm + 14nm

32 Cores

24 Cores

16 Cores

Hypothetical Monolithic 7nm

Fig. 2.14 AMD’s die cost comparison: chiplet (7 nm + 12 nm) versus monolithic (7 nm)

2.18 and 2.19. Figure 2.16 shows schematically AMD’s 3D V-Cache chiplet design and heterogeneous integration packaging. The key components of this structure are a bottom compute die, top static random -access memory (SRAM) die, and structural dies to balance the structure and provide thermal path for heat dissipation from bottom compute die to the heat sink. The bottom die (81mm2 ) is the “Zen 3’ CPU which is fabricated by TSMC’s 7 nm process technology. The top die (41mm2 ) is the extended L3 die which is also fabricated by TSMC’s 7 nm process technology. The bottom die with TSV (through-silicon via) is face-down with C4 (controlled collapse chip connection) bumps. The top die is also face-down, which is face-toback Cu-Cu hybrid bonding to the bottom die, as shown in Fig. 2.18. Figure 2.19 shows the bonding process and the bonded interface, which is fabricated by TSMC’ SoIC (system on integrated chips) technology. The Cu-Cu hybrid bonding pitch is 9 μm.

2.7 AMD’s Chiplet Design and Heterogeneous Integration Packaging CPU Chiplet

GPU Chiplet

Fig. 2.15 AMD’s future chiplet technology—3D chiplet integration (active TSV-interposer)

AMD 3D V-CacheTM Structural Silicon 64MB L3 Cache Die Direct Cu-Cu Bonding

TSVs For Si-to-Si communication Up to 8-Core ìZen 3î CCD

Fig. 2.16 AMD’s 3D V-cache chiplet design and heterogeneous integration packaging

113

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

Extended L3 die (L3D) TSMC 7nm process technology 64MB L3 Cache extension 41mm2

ìZen 3îCPU CCD (Core Complex Die) TSMC 7nm process technology 8 cores per Core Complex 32MB shared L3 Cache 81mm2

Structural Dies Structural support for thinned CCD Thermal dissipation for CPU cores

ECTC2022

Fig. 2.17 The key components in AMD’s 3D V-cache

L3D Face-Down Cu-Cu hybrid bonding (L3D ó CCD) Face (L3D)-to-Back (CCD) bonding

CCD Face-Down TSVs interconnect to L3D C4 bump to package substrate

Oxide bonded to CCD

ECTC2022

Fig. 2.18 The physical organization of AMD’s 3D V-cache

2.8 Intel’s Chiplet Design and Heterogeneous Integration Packaging Intel have been working on chiplet design and heterogeneous integration packaging for a few years [20–30]. In July 2020, Intel shipped their mobile (notebook) processor

2.8 Intel’s Chiplet Design and Heterogeneous Integration Packaging

SRAM

115

B F

9μm

BPV Die interface

BPM

TSV BPM (bond pad metal) BPV (bond pad via) TSV (through-silicon via) Fig. 2.19 TSMC’s SoIC SRAM (face)-to-CPU (back) Cu-Cu bumpless hybrid bonding of the AMD’s 3D V-cache

“Lakefield”, which is based on their FOVEROS technology (TYPE-3 of the Omnidirectional interconnect announced during the SEMICON West in July 2019). The SoC is partitioned (e.g., CPU, GPU, LPDDR4, etc.) and split (e.g., the CPU is split into one big CPU and 4 smaller CPU) into chiplets as shown in Figs. 2.20 and 2.21. These chiplets are then face-to-face bonded (stacked) on an active TSVinterposer (a large 22FFL base chip) with a CoW (chip-on-wafer) process as shown in Figs. 2.22 and 2.23. The interconnect between the chiplets and the logic base chip is micro bump (Cu pillar + SnAg solder cap) as shown in Figs. 2.22 and 2.23. The interconnect between the base chip and the package substrate is C4 bump and between the package substrate and PCB is solder ball. The final package formant is a PoP (package-on-package) (12 × 12 × 1 mm) as shown in Fig. 2.20. The chiplet design and heterogeneous integration packaging is in the bottom package and the upper package is housing the memories with wire bonding technology. The fabrication of the chiplets is with Intel’s 10 nm process technology and of the base chip is 22 nm. Since chiplets’ size is smaller and not all the chips are using the 10 nm process technology, the overall yield must be higher and thus it translates to lower cost. It should be noted that this is the very first HVM (high volume manufacturing) of 3D chiplets integration. Also, this is the very first HVM of processors for mobile products such as the notebook by 3D IC integration. During Intel Architecture Day (August 13, 2020), they announced a Cu-Cu hybrid bonding for their FOVEROS technology. They called it FOVEROS-Direct [29] and

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10mm

1mm

12mm

10mm

Fig. 2.20 Intel’s Lakefield processor in a PoP for notebook application

10mm 3D IC Integration

10mm

(a)

The memory and graphics are partitioned The large CPU is split into 5 smaller CPUs (10nm process technology) All the tiles (or chiplets) are attached on an active interposer

Memory, Modem, …

Compute Chip

(b)

FTF Micro-Bumps

Thru-Silicon Vias Solder Bumps

Active Interposer

Package Substrate

Fig. 2.21 Intel’s FOVEROS: chiplet (face)-to-active interposer (face) μbump bonding for Lakefield

2.8 Intel’s Chiplet Design and Heterogeneous Integration Packaging

117

10nm Compute Die (Chiplets) 10nm Compute Die (Chiplets)

µbump

TSV

22FFL Base Die C4 bump

TSV

22FFL Base Die

Active Interposer

Substrate

Package Substrate Solder Ball

Fig. 2.22 SEM cross section image on the Lakefield

RDLs

TSV

μbumps

μbumps

RDLs RDLs

TSVs

TSV C4 bump Fig. 2.23 Close-up SEM images on the Lakefield

Active TSV-interposer

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

FOVEROS Direct

FOVEROS (Micro Bumps) Micro bumps

CHIP

CHIP

CHIP

50μm pitch μbump bonding 400 bumps/mm2

CHIP

Bumpless

10μm pitch hybrid bonding 10,000 pads/mm2

Top Die Top Die Bottom Die

Cu Cu-Cu Bonding

FOVEROS Direct

Bottom Die

Cu

Fig. 2.24 Intel’s future packaging technology: FOVEROS–Direct

demonstrated that with bumpless hybrid bonding the pitch can go down to 10 μm instead of 50 μm like the Lakefield as shown in Fig. 2.24. Another Intel’s future chiplet design and heterogeneous integration packaging technology is called Ponte Vecchio GPU, or the “spaceship of a GPU” [20, 26], which is the largest and most chips designed to date, Figs. 2.25, 2.26, 2.27 and 2.28. The Ponte Vecchio GPU is making use of several key technologies, which will power 47 different compute chiplets and 16 thermal dies based on different process nodes and architectures. While the GPU primarily makes use of Intel’s 7-nm extreme ultraviolet lithography (EUV) process node for those 8 RAMBO (random access bandwidth-optimized SRAM tiles), Intel will also be producing some XeHPC compute dies through external fabs (such as TSMC with their 5-nm note for those 16 compute tiles). To be precise (Table 2.1) there are: 47 chiplets consist of 16 Xe-HPCs (internal/external), 16 thermal dies, eight Rambos (internal), two XeBases (internal), 11 EMIBs (internal), two Xe-Links (external), and eight HBMs (external). The maximum top-die (chiplet) size = 41 mm2 ; the base die size = 650 mm2 ; die-to-die pitch = 36 μm; and package layers = 11-2-11, package pins = 4468, and package size = 77.5 × 62.5 mm (Table 2.1). The power envelope is 600 W. A close-up of the EMIB is shown in Fig. 2.29. The thermal management of a structure with 600 W of power envelope is challenge. Intel’s strategies are (Fig. 2.30): (a) using thick interconnect layers in the base and compute tiles act as lateral heat spreaders, (b) using high micro-bump density over potential hotspots to compensate for reduced thermal spreading in a thin-die

2.8 Intel’s Chiplet Design and Heterogeneous Integration Packaging

119

Fig. 2.25 Intel’s future packaging technology: Ponte Vecchio GPU

Fig. 2.26 Key elements of the Ponte Vecchio GPU

stack, and (c) using high array density of power TSVs to reduce C4 bump temperature. In addition, the compute tile thickness is increased to 160 μm to improve thermal mass for turbo performance. Furthermore, there are 16 additional thermal shield dies stacked to provide a thermal solution over exposed base die area to conduct heat. Backside metallization with solder thermal interface material (TIM) is applied on

RAMBO

Compute Tile

Compute Tile

Compute Tile

Compute Tile

Compute Tile

HBM

Thermal Die/HBM PHY

Compute Tile

Thermal Die/Xe Link

RAMBO

Compute Tile

RAMBO

Thermal Die/HBM PHY

Compute Tile

RAMBO

HBM

Thermal Die/HBM PHY

HBM

Thermal Die/T-T Thermal Die/T-T

Thermal Die/HBM PHY Thermal Die/HBM PHY

2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

Thermal Die/PCI G5

120

HBM

Xe Link

Fig. 2.27 Top view of part of the Ponte Vecchio GPU

all the top dies. The TIM eliminates air gaps caused by different die stack heights to reduce thermal resistance. Intel’s road map of chiplet design and heterogeneous integration packaging in terms of interconnect density vs. power efficiency is shown in Fig. 2.31 [21]. It can be seen that Cu-Cu hybrid bonding with < 10 μm pad pitch, > 10,000/mm2 pad density, and < 0.05ρJ/bit power are their goals in the near future.

2.9 TSMC’s Chiplet Design and Heterogeneous Integration Packaging TSMC have been working on chiplet design and heterogeneous integration packaging for a few years [31–37]. On TSMC Annual Technology Symposium (August 25, 2020) TSMC announced their 3DFabric (3D fabrication) technology for mobile, high-performance computing, automotive, and IoT (internet of things) applications.

2.9 TSMC’s Chiplet Design and Heterogeneous Integration Packaging

47 Chiplets (16 HPC) 16 Thermal dies Max. size = 41mm2

121

(8)

(2) (650mm2) (8) (2)

(11)

77.5mm x 62.5mm (11-2-11)

Fig. 2.28 Key components of the Ponte Vecchio GPU Table 2.1 Key components/elements of Ponte Vecchio GPU

Integration

Foveros + EMIB

Power envelope

600 W

Transistor count

> 100B

Total tiles

63 (47 functional + 16 thermal Tiles)

HBM count

8

Package form factor 77.5 × 62.5 mm (4844 mm2 ) Platforms

3 platforms

IO

4 × 16 90G SERDES, 1 × 16PCIe Gen5

Total silicon

3100 mm2 Si

Silicon footprint

2330 mm2 Si footprint

Package layers

11-2-11 (24-layer)

2.5D count

11 2.5D connections

Resistance

0.15 mΩ Rpath /tile

Package pins

4468 pins

Package cavity

186 mm2 × 4 cavities

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Fig. 2.29 SEM images of cross sections showing chiplets, base chips, EMIB, integrated heat spreader, etc.

Integrated Heat Spreader Thermal Interface Material

Integrated Heat Spreader TIM Backside Metallization Thermal Tiles EMIB Package

Fig. 2.30 Thermal management of the Ponte Vecchio GPU

123

Interconnect Density

2.9 TSMC’s Chiplet Design and Heterogeneous Integration Packaging

Power Efficiency Fig. 2.31 Intel’s roadmap for interconnect density and power efficiency

The core technology of 3Dfabric is their SoIC (system on integrated chips), which was announced during the TSMC Annual Technology Symposium (May 1, 2018) in Santa Clara, California. 3Dfabric provides chiplet heterogeneous integrations that are fully integrated from front to back end. The application-specific platform leverages TSMC’s advanced wafer technology, open innovation platform design ecosystem, and 3DFabric for fast improvements and time-to-market. TSMC’s chiplet design and heterogeneous integration packaging roadmap is shown in Fig. 2.32 [36]. Frontend 3D hybrid bonding (stacking) technology SoIC with CoW and WoW, provides flexible chip-level chiplets design and integration (Fig. 2.33). Comparing with the conventional microbump flip chip technology, hybrid bonding SoIC has many advantages, e.g., better electrical performance, Fig. 2.34a, and density, Fig. 2.34b, and better thermal performance and less energy spent per bit data as shown in Fig. 2.35 [37]. In 3D backend package integration, CoWoS’ increased envelope and enriched technology content offers exceptionally high computing performance and high memory bandwidth to meet HPC needs on clouds, data center, and high-end servers as shown in Fig. 2.36a. In another 3D backend package integration, InFO derivative technology offers memory-to-logic, logic-to-logic, PoP, etc. applications as shown in Fig. 2.36b. Figure 2.19 shows one of AMD products fabricated by TSMC’s SoIC technology.

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2.10 Graphcore’s Chiplet Design and Heterogeneous Integration Packaging During July 2022, UK-based AI (artificial intelligence) computer company GraphCore have announced a new integration chip called Bow, which is the world’s first WoW IPU (intelligence processing unit) processor. GraphCore claim that the processor will speed up processes like deep learning by 40% and use 16% less energy than previous generation processors (Figs. 2.37 and 2.38). The Bow IPU is based on TSMC’s 7 nm process technology. Also, the chip-to-chip (Colossus IPU chip to the TSV interposer with deep trench capacitors) assembly is with TSMC SoIC WoW Cu-Cu bumpless bonding (Fig. 2.39). It is a face-to-face bonding and the signals are coming out from the C4 (controlled collapse chip connection) bumps to the next level of interconnect.

2.11 CEA-LETI’s Chiplet Design and Heterogeneous Integration Packaging Figures 2.40 and 2.41 show CEA-LETI’s chiplet design and heterogeneous integration packaging called INTACT (active interposer) [39, 40]. It consists of 6 chiplets on an active TSV interposer. The chiplets are fabricated by a 28 nm process technology. The active interposer is fabricated by a 65 nm process technology. Then, they are face-to-face bonded on the active TSV interposer with microbumps on 20 μm

Fig. 2.32 TSMC’s 3DFabric roadmap

2.11 CEA-LETI’s Chiplet Design and Heterogeneous Integration Packaging

Microbump Flip Chip

125

SoIC Bond formation

μbump formation

SoIC stacking

Flip chip stacking

CoW and WoW)

Underfill

C4 FC bumps

RDL (optional)

FC assembly on substrate

FC or Wafer-level system integration

Fig. 2.33 TSMC’s SoIC (system on integrated chips) technology

Insertion Loss (dB)

Frequency (GHz)

(a)

Bump Density (counts/mm2)

SoIC+ SoIC Hybrid Bonding

>1000x

SoIC >10x 2.5D/3DIC

Flip Chip

Bump/Bonding Pitch (μm)

(b)

Fig. 2.34 TSMC’s Cu-Cu bumpless SoIC versus the conventional microbump flip chip technology, a Electrical performance. b Bump density

pitch. Their future work will be Cu-Cu hybrid bonding between the chiplets and the active interposer, which should offer higher density, better electrical, mechanical, and thermal performance.

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous …

Fig. 2.35 Thermal and energy performance: SoIC versus conventional 3D IC

CoWoS with SoIC

HBM

SoC-1 SoC-2

TSV

Interposer

SoC-3

Package Substrate

PCB (a)

DRAM

InFO PoP with SoIC

SoC-2

SoC-1

SoC-3

Fan-Out RDLs PCB (b)

Fig. 2.36 TSMC’s backend integration. a SoIC + CoWoS. b SoIC + InFO PoP

2.12 UCIe (Universal Chiplet Interconnect Express) The UCIe is a new open industry consortium, which addresses customer requests for a more customization, package-level integration—combining best-in-class dieto-die interconnect and protocol connections from an interoperable, multi-vendor ecosystem [118]. The initial (founding) members of UCIe are AMD, ARM, ASE,

2.12 UCIe (Universal Chiplet Interconnect Express)

3D silicon wafer stacked processor 350TeraFLOPS AI compute Optimized silicon power delivery 0.9 GigaByte In-Processor-Memory @ 65TB/s 1,472 independent processor cores 8,832 independent parallel programs 10x IPU-LinksTM delivering 320GB/s

Fig. 2.37 Graphcore’s IPU (intelligence processing unit) processor

4 x BOW 3D Wafer-on-wafer IPUs 1.4 PetaFLOPS AI compute 3.6 GB In-Processor-Memory @ 260TB/s Up to 256 GB IPU Streaming Memory 2.8 Tb/s IPU-FabricTM Same 1U blade form factor

Fig. 2.38 Structural components of Graphcore’s IPU processor

127

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2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous … C4 bump

C4 bump

C4 bump

C4 bump

C4 bump

C4 bump

C4 bump

UBM

BEOL Cu-Cu Bonding BEOL Colossus IPU Die

Fig. 2.39 Graphcore’s IPU processor by TSMC’s SoIC Cu-Cu bumpless face-to-face bonding

Fig. 2.40 CEA-Leti’s ACTINT (chiplets on active interposer)

Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC. There are more than 45 contributing members such as Micron, Broadcom, Analog Devices, MediaTek, Amkor, Cadence, and Synopsys. More information on UCIe will be discussed in Chap. 5.

2.13 Summary and Recommendations

129

Active

Fig. 2.41 SEM image of the cross section of CEA-Leti’s ACTINT

2.13 Summary and Recommendations Some important results and recommendations are summited as follows. • SoCs with chip scaling are and will be here to stay. However only a handful of companies such as Apple, Samsung, Huawei, Google can afford them at finer feature size (advanced nodes). Usually, there are some reasons for them to do so. Take Apple for example, there are at least three reasons: (a) on April 23, 2008, Apple acquired Palo Alto Semiconductor and has been building their chips with lots of IPs and coupled (integrated) with their software development, (b) partitioning and/or splitting their SoC design into chiplets would not be an attractive prospect (at least right now) because the additional chip-to-chip interconnection and communication overhead would create more headaches than it’s worth, and (c) the world’s number one foundry (TSMC) is Apple’s loyal partner and they committed to Apple’s schedule and Samsung (with their announcement of 3 nm process technology in mass production) also want to serve Apple.

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• Chiplet design and heterogeneous integration packaging provide alternatives (options) to SoCs, especially for advanced nodes, which most companies cannot afford. • Chip partition and heterogeneous integration packaging is driven by cost and technology optimization. • Chip split and heterogeneous integration packaging is driven by cost and semiconductor manufacturing yield. • The most advantage of chiplet design and heterogeneous integration packaging comparing with SoC is lower cost. • The challenges of chiplet design and heterogeneous integration packaging are larger packaging sizes and higher packaging cost. Thus, the opportunities of packaging technologists are to reduce the packaging size and cost. • In order to promote/popular the chiplet design and heterogeneous integration packaging, standards are necessary! The DARPA CHIPS and UCIe are heading into the right direction. • EDA (electronic design automation) tools for automating system splitting and partitioning and design are desperately needed for complex chiplet design and heterogeneous integration packaging.

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8. 9. 10. 11.

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Chapter 3

Multiple System and Heterogeneous Integration with TSV-Interposers

3.1 Introduction As mentioned in Chaps. 1 and 2 and [1], there are at least three different multiple system and heterogeneous integration packaging, as shown in Fig. 3.1, namely, (1) multiple system and heterogeneous integration with thin-film layer directly on top of a build-up package substrate (2.1D IC integration), Fig. 3.1a, (2) multiple system and heterogeneous integration with TSV-less interposer (2.3D IC integration), Fig. 3.1b, and (3) multiple system and heterogeneous integration with TSV interposers (2.5D and 3D IC integration), Fig. 3.1c. All these multiple system and heterogeneous integrations are driven by performance and formfactor. The very first 2.1D IC integration papers were published by Shinko [2] at IMAPS International Symposium on Microelectronics 2013 and [3] at IEEE/ECTC 2014. In general, for 2.1D, thin film layers or fine metal linewidth and spacing (L/S) RDLs (redistributed-layers)-substrate are fabricated directly on the top-layer of a build-up package substrate and become a hybrid substrate [2–10] as shown in Fig. 3.1a. In this case, the yield loss of the hybrid substrate, especially the fine metal L/S coreless substrate is difficult to control and can be very large because of the flatness of the build-up package substrate. Today, 2.1D IC integration, Fig. 3.1a, is not in high volume manufacturing, and it will not be discussed in this book. The very first 2.3D IC integration paper was published by STATS ChipPAC [11] at IEEE/ECTC 2013. Their motivation is to replace the TSV-interposer (2.5D IC integration) by a fan-out fine metal L/S RDL-substrate (or organic interposer). The structure consists of a build-up package substrate, solder joints with underfill [12, 13], and a fine metal L/S RDL-substrate, Fig. 3.1b. Since then, there are many publications [14–45]. References [11, 14–17] are with fan-out chip-first packaging process while [18–45] are with fan-out chip-last packaging process. The 2.3D IC integration (multiple system and heterogeneous integration with TSV-less interposers), Fig. 3.1b will be discussed in Chap. 4 of this book.

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging, https://doi.org/10.1007/978-981-19-9917-8_3

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Fine Metal L/S RDL-Substrate (Organic Interposer) μbump Thin-Film Layers CHIP CHIP/HBM CHIP/HBM CHIP CHIP/HBM CHIP RDL TSV

μbump

3 Multiple System and Heterogeneous Integration with TSV-Interposers

TSV-interposer

C4 bump

Package Substrate

Solder Ball 2.3D

2.5D/3D

PCB

PCB

PCB

(a)

(b)

(c)

2.1D

Not-to-scale

Fig. 3.1 a Multiple system and heterogeneous integration with thin-film layers on top of package substrate (2.1D). b Multiple system and heterogeneous integration with TSV-less interposer (2.3D). c Multiple system and heterogeneous integration with TSV interposer (2.5D/3D)

The very first 2.5D IC integration papers were published by CEA-Leti [46] at IEEE/ECTC 2005 and [47] at IEEE/ECTC 2006. In general, for 2.5D, the chips/HBMs (high bandwidth memories) are supported by a TSV-interposer and then on a build-up package substrate as shown in Fig. 3.1c [46–194]. The very first product (Virtex-7 HT family) of 2.5D was shipped in 2013 by Xilinx and TSMC. The 2.5D with TSV-interposer is known for extremely high-performance and high-density applications and high cost. In this chapter, the recent advances in multiple system and heterogeneous integration with TSV interposers will be presented. Emphasis is placed on definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV interposer. Also, some recommendations of TSV interposers will be provided. The passive TSV interposer (2.5D IC integration) and active TSV interposer (3D IC integration) will be briefly mentioned first.

3.2 Through-Silicon Via (TSV) In general, a TSV is defined as the via in a piece of silicon which let the signals from the topside of the piece of silicon communicate to the signals of the bottom-side or vice versa. The via diameter can be as small as 1 μm, but in general it is about 5–10 μm. The via is usually filled with Cu with a SiO2 insulation layer because silicon is an electrical conductive material.

3.2 Through-Silicon Via (TSV)

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(a) Deep Pit (Hole), which is called TSV today

Many tiny vias (metal contacts) filled with W or Cu

Backside Transistors (cannot see)

Custructure

(b) Low-k material Low-k layers, closest to chip surface

9 low-k Metal layers

Passivation

Frontside

65nm Cu/low-k Chip by Chartered Semiconductor (2006) to show the tiny vias.

Fig. 3.2 a TSV patent. b The tiny vias (metal contacts) in a chip (not the TSVs)

TSV was invented more than 60 years ago by the 1956 Nobel Laureate in Physics, William Shockley. (Yes, the same Shockley who co-invented the transistor, which is generally considered the greatest invention in semiconductor industry.) He filed the patent, Semiconductive Wafer and Method of Making the Same on October 23, 1958, and was granted the US patent (3,044,909) on July 17, 1962. One of the key claims is shown in Fig. 3.2a, which gets the semiconductor world so exacted today. Basically, the “deep pits” (which are called TSVs today) on the wafer allow the signals from its topside to its bottom-side and vice versa. The term “through silicon via” was coined by Sergey Savastiouk, “Industry Insights Moore’s law—the Z Dimension”, in Solid State Technology, January 2000.

3.2.1 Tiny Vias on a Chip Figure 3.2b shows the SEM (scanning-electron microscopy) cross-section images of a 9 Cu-low-k layers chip (made in 2006) with the 65 nm process technology by Chartered Semiconductor, which is called GlobalFoundries today. Besides the tiny

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

devices such as transistors (which cannot be seen in this SEM image), there are many tiny vias (metal contacts) on the chip. They are connected to devices (e.g., 4 vias for each transistor) to build the first metal (M1) layer. Today, the number of these tiny vias, for many chips, already exceeds the world population of over 7.7 billion. One of the core competences and major businesses of foundries is to make these tiny vias (in addition to the transistors). These vias are not the same TSVs for 2.5D/3D integrations. They are much smaller, and their number is many times more than that of the TSVs.

3.2.2 TSV (Via-First Process) For via-first process, the TSV is fabricated (on a bare wafer) before the implantation of the semiconductor devices such as the transistors. Most 2.5D IC integrations (passive TSV-interposers) are fabricated by via-first process because there are not any transistors.

3.2.3 TSV (Via-Middle Process) For via-middle process, the TSV is made after the fabrication of the devices and metal contacts, and before the metal layers as shown in Fig. 3.3. Figure 3.4 shows a SEM image of the cross-section of TSVs made by the via-middle process [65]. Today, most 3D IC integrations (active TSV-interposers) are fabricated by via-middle process.

3.2.4 TSV (Via-Last from the Front-Side Process) For via-last process from the front-side, the TSV is fabricated after the making of the devices and metal contacts, all the metal layers, and passivation. The TSV is made from the front-side of the wafer.

3.2.5 TSV (Via-Last from the Back-Side Process) For via-last process from the backside, the TSV is fabricated after the making of the devices and metal contacts, all the metal layers, and passivation. The TSV is made from the backside of the wafer (Fig. 3.5). Figure 3.6 shows a SEM image of the cross section of TSVs made by the via-last from the back-side process [81].

3.3 Passive TSV-Interposers Versus Active TSV-Interposers

141 BEOL

Contact Device

Metal Layers

TSV Fab.

Back-side

Pass.

Pass. opening

M1 TSV

MOL

TSV

FEOL

TSV

Si Substrate

Back-side

Transistors (cannot see)

TSV

Metal contacts

Passivation Metal layers

Front-side

Fig. 3.3 TSV via-middle process

Fig. 3.4 An example of TSV via-middle process

3.3 Passive TSV-Interposers Versus Active TSV-Interposers There are at least two different groups of TSV-interposers [51, 56, 61, 66, 183, 184], namely, passive TSV-interposers and active TSV-interposer. Passive TSV-interposers are a piece of dummy silicon with TSVs and RDLs, while active TSV-interposers are a piece of silicon with CMOS (complementary metal-oxide semiconductor) devices, TSVs, and RDLs (just like a piece of silicon chip with TSVs.) In industry, passive

142

3 Multiple System and Heterogeneous Integration with TSV-Interposers BEOL Metal Layers FEOL

Pass. opening Pass.

MOL Contact

Device Si Substrate

TSV

Pass.

UBM

C4 bumping Carrier

Carrier

Carrier Backgrinding

TSV Fab.

UBM, C4 Wafer bumping & Temporary Bonding

TSV

Back-side

Front-side

Passivation

Fig. 3.5 TSV via-last (from the backside) process

3μm

Fig. 3.6 An example of TSV via-last (from the backside) process

3.5 Multiple System and Heterogeneous Integration with Active …

143

TSV-interposers are called 2.5D IC integration while active TSV-interposers are called 3D IC integration. Both of them could have integrated passive devices (IPDs) to enhance their electrical performance.

3.4 Active TSV-Interposer Fabrication Since active TSV-interposer involves the fabrication of the CMOS devices with semiconductor technology, it is out of the scope of this book. (Here, only passive TSV interposer fabrication will be discussed.) However, some examples are briefly mentioned next.

3.5 Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration) 3.5.1 UCSB/AMD’s Multiple System and Heterogeneous Integration with Active TSV-Interposer Excited by the Defense Advanced Research Projects Agency (DARPA) program called Common Heterogeneous Integration and Intellectual Property Reuse Strategies (CHIPS), in 2017 UCSB and AMD [128] proposed a future very highperformance system shown in Fig. 3.7. This system comprises a central processor unit (CPU) chiplet and several graphics processor unit (GPU) chiplets, as well as HBMs on a passive TSV-interposer and/or on an active TSV-interposer with RDLs.

3.5.2 Intel’s Multiple System and Heterogeneous Integration with Active TSV-Interposers In July 2020, Intel shipped their mobile (notebook) processor “Lakefield,” which is based on their FOVEROS technology, (Fig. 3.8) [177, 178]. The SoC is partitioned (e.g., CPU, GPU, etc.) and split (e.g., the CPU is split into one big CPU and four smaller CPUs) into chiplets, as shown in Fig. 3.8. These chiplets are then face-to-face bonded (stacked) on an active TSV interposer (a large 22FFL base chip) with a CoW process. The interconnect between the chiplets and the logic base chip is microbump (Cu pillar + SnAg solder cap), as shown in Fig. 3.8. The interconnect between the base chip and the package substrate is C4 (controlled collapse chip connection) bump and between the package substrate and printed circuit board (PCB) is a solder ball. The final package formant is a PoP (12 mm × 12 mm × 1 mm). The chiplet heterogeneous integration is in the bottom package, and the upper package is housing

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

CPU Chiplet

GPU Chiplet

Fig. 3.7 Multiple system and heterogeneous integration with active TSV-interposer (UCSB/AMD)

the memories with wire bonding technology. It should be noted that this is the very first high-volume manufacturing (HVM) of 3D chiplets’ integration. Also, this is the very first HVM of processors for mobile products, such as the notebook by 3D IC integration. One of Intel’s futures chiplet designs and heterogeneous integration packaging is called Ponte Vecchio GPU, or the “Spaceship of a GPU” [179], which is the largest and most chips designed to date. The Ponte Vecchio GPU will be making use of several key technologies, which will power 47 different compute chiplets based on different process nodes and architectures, as shown in Fig. 3.9. While the GPU primarily makes use of Intel’s 7-nm extreme ultraviolet lithography (EUV) process node, Intel will also be producing some Xe-HPC compute dies through external fabs (such as TSMC with the 5-nm note). To be precise, 47 chiplets consist of 16 Xe-HPCs (internal/external), eight Rambos (internal), two Xe-Bases (internal), 11 EMIBs (internal), two Xe-Links (external), and eight HBMs (external). The maximum topdie (chiplet) size = 41 mm2 ; the base-die size = 650 mm2 ; die-to-die pitch = 36 μm; and package size = 77.5 mm × 62.5 mm. Table 3.1 summarizes the key elements

3.5 Multiple System and Heterogeneous Integration with Active …

µbump C4 bump

145

10nm Compute Die (Chiplets)

22FFL Base Die

TSV

Active Interposer

Package Substrate Solder Ball

Fig. 3.8 Multiple system and heterogeneous integration with active TSV-interposer (Intel’s Lakefield processor)

and their dimensions. The compute dies with 3nm process technology are already on the drawing board.

3.5.3 AMD’s Multiple System and Heterogeneous Integration with Active TSV-Interposers During IEEE/ISSC 2022 [180] and IEEE/ECTC 2022 [181], AMD introduced their 3D V-Cache chiplet design and integration technology packaging. Figure 3.10 shows schematically AMD’s 3D V-Cache chiplet design and heterogeneous integration packaging. The key components of this structure are a bottom compute die, top SRAM die, and structural dies to balance the structure and provide thermal path for heat dissipation from bottom compute die to the heat sink. The bottom die (81mm2 ) is the “Zen 3” CPU which is fabricated by TSMC’s 7 nm process technology. The top die (41mm2 ) is the extended L3 die which is also fabricated by TSMC’s 7 nm process technology. The bottom die with TSV (through-silicon via) is face-down with C4 bumps. The top die is also face-down, which is face-to-back Cu-Cu hybrid bonding

Compute Tile

RAMBO

Compute Tile

Compute Tile

RAMBO

Compute Tile

Compute Tile

Compute Tile

HBM

Thermal Die/HBM PHY

RAMBO

Compute Tile

Thermal Die/Xe Link Thermal Die/HBM PHY

Compute Tile

RAMBO

HBM

Thermal Die/HBM PHY

HBM

Thermal Die/T-T Thermal Die/T-T

Thermal Die/HBM PHY

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Thermal Die/HBM Thermal Die/PCI G5 PHY

146

(8)

(2) (650mm2) (8)

HBM

(2)

(11)

Xe Link

77.5mm x 62.5mm (11-2-11)

Fig. 3.9 Multiple system and heterogeneous integration with active TSV-interposer (Intel’s Ponte Vecchio GPU) Table 3.1 The key elements and their dimensions of Ponte Vecchio GPU

Integration

Foveros + EMIB

Power envelope

600 W

Transistor count

> 100B

Total tiles

63 (47 functional + 16 thermal tiles)

HBM count

8

Package form factor 77.5 × 62.5 mm (4844 mm2 ) Platforms

3 platforms

IO

4 × 16 90G SERDES, 1 × 16PCIe Gen5

Total silicon

3100 mm2 Si

Silicon footprint

2330 mm2 Si footprint

Package layers

11-2-11 (24-layer)

2.5D count

11 2.5D connections

Resistance

0.15 mΩ Rpath /tile

Package pins

4468 pins

Package cavity

186 mm2 × 4 cavities

3.5 Multiple System and Heterogeneous Integration with Active …

147

AMD 3D V-Cache

SRAM

SRA M

B F

m 9μm

BPV Die interface

BPM

TSV Fig. 3.10 Multiple system and heterogeneous integration with active TSV-interposer (AMD’s 3D V-cache processor)

to the bottom die. Figure 3.10 shows the bonding process and the bonded interface, which is fabricated by TSMC’ SoIC (system on integrated chips) technology. The Cu-Cu bonding pitch is 9 μm.

3.5.4 CEA-Leti’s Multiple System and Heterogeneous Integration with Active TSV-Interposers Figure 3.11 shows CEA-Leti’s INTACT (active interposer) [182]. The system of six chiplets is supporting by an active TSV-interposer.

148

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.11 Multiple system and heterogeneous integration with active TSV-interposer (CEA-Leti’s INTACT)

3.6 Passive TSV-Interposer Fabrication The fabrication of passive TSV-interposers consists of two key tasks, namely the fabrication of TSV and the fabrication of RDLs on a piece of dummy silicon wafer [109, 118].

3.6 Passive TSV-Interposer Fabrication

149

3.6.1 Fabrication of TSVs The fabrication process of TSVs is shown in Fig. 3.12. The process starts with a SiNx /SiOx insulation layer by either thermal oxidation or PECVD (plasma enhanced chemical vapor deposition) as shown in Fig. 3.12. After photoresist and TSV lithography, the TSV is etched into the Si substrate by Bosch-type DRIE (deep reactive ion etch) [75] to form a high aspect ratio (10.5) via structure. The etched TSV structure is then processed with a SiOx liner by SACVD (subatmosphere chemical vapor deposition), a Ta barrier layer, and a Cu seed layer by PVD (physical vapor deposition) [95]. Cu electroplating is used to fill the TSV structure. The final blind TSV has a top opening of approximately 10 μm in diameter and a depth of about 105 μm, which gives an aspect ratio of 10.5. In such a high aspect ratio via structure, a bottom-up plating mechanism is applied to ensure a seamless TSV with a reasonably low Cu thickness in the field. The SEM cross-sectional images are shown in Fig. 3.13. It can be seen that the diameter of the TSV is slightly decreased at the bottom, which is expected from the etching process. The Cu thickness at the field is < 5 μm. The post-plating anneal is at 400 °C for 30 min. To complete the TSV process, excess Cu in the field is removed by CMP (chemical–mechanical polishing) [92].

TSV

Si substrate

TSV by DRIE

SiO2 SiO2 by thermal oxidation or PECVD

Strip resist

Photoresist

Photoresist SiO2

Mask, Litho/ Patterning

Ti/Cu or Ta/Cu

Cu Plating. Then anneal at 400oC for 30m

Cu

SiO2 etch SiO2

Cu TSV Ti/Cu or Ta/Cu

Fig. 3.12 TSV fabrication process flow

PECVD or SACVD SiO2, PVD barrier layer (Ti or Ta) and seed layer (Cu)

CMP the overburden Cu, Cu seed layer, and barrier layer

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

0.40μm

10.1μm 0.83μm

TSV

100μm

0.44μm

8.67μm

Fig. 3.13 SEM images of TSV cross sections

3.6.2 Fabrication of RDLs In general, RDL consists of the dielectric layer and the metal conducting layer. There are at least two ways to fabricate RDLs [109, 118]. The first method is by using polymers, such as polyimide (PI) PWDC 1000 (Dow Corning), benzocyclobutene (BCB) cyclotene 4024-40 (Dow Chemical), polybenzo-bisoxazole (PBO) HD-8930 (HD Micro Systems), and the fluorinated aromatic AL-X 2010 (Asahi Glass Corporation) to make the dielectric layer and electroplating (such as Cu) to make the metal layers. This method has been used by the OSAT (outsourced semiconductor assembly and test) to fabricate RDLs for wafer-level (fan-in) chip scale package [195–197], embedded wafer-level (fan-out) ball grid array package [198], and (fan-out) redistribution chip package [199]. The second method is the Cu damascene method, which is primarily modified from the conventional semiconductor back-end-of-line to make the Cu metal RDLs. In general, much thinner structures (both dielectric layers and Cu RDLs), finer pitches, smaller linewidth and line-spacing can be obtained with the Cu damascene method. The polymer/Cu-plating method will be mentioned first.

3.6 Passive TSV-Interposer Fabrication

151

3.6.3 Fabrication of RDLs: Polymer + Cu-Plating and Etching Method Continuing with the wafer from Figs. 3.12 and 3.13, the fabrication process for the RDLs using polymers is shown in Fig. 3.14 and also listed as follows. UBM (under bump metallurgy) is included. 1.

Spin the polymers such as PI or BCB on the wafer and cure for 1 h. This will form a 4–7-μm-thick layer. 2. Apply photoresist and mask, then use photolithography techniques (align and expose) to open vias on the PI or BCB. 3. Etch the PI or BCB. 4. Strip off the photoresist. 5. Sputter Ti and Cu over the entire wafer. 6. Apply a photoresist and mask, and then use photolithography techniques to open the redistribution-trace locations. 7. Electroplate Cu in photoresist openings. 8. Strip off the photoresist. 9. Etch off the Ti/Cu and RDL1 is completed. 10. Repeat steps 1–9 for RDL2, and so forth. 11. Repeat step 1 (for UBM). SiO2 Ti/Cu SiO2

TSV (Cu)

Si

TSV

Ta/Cu or Ti/Cu

PI or BCB

TSV TSV

Sputter Ti/Cu

Photoresist

Spin PI or BCB Mask, litho

TSV

TSV

Cu

Photoresist

Cu plating in photoresist opening

TSV Mask, litho TSV

TSV

Ti/Cu

Cu RDL1

PI or BCB

TSV

Etch PI or BCB

Strip resist and etch Ti/Cu

RDL2 PI2 or BCB2 RDL1

TSV

Strip resist

PI1 or BCB1 TSV

Fig. 3.14 RDL fabrication process with polymers as dielectric layers and Cu plating as metal layers

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.15 IZM’s RDLs with BCB polymer

Support wafer

BCB2 BCB1

Interposer wafer with wiring structure

20µm

12. Apply photoresist and mask, and then use photolithography techniques (align and expose) to open vias on the PI or BCB for the desired bump pads and to cover the redistribution traces. 13. Etch the desired vias on the PI or BCB. 14. Strip off the photoresist. 15. Sputter Ti and Cu over the entire wafer. 16. Apply photoresist and mask, and then use photolithography techniques to open the vias on the bump pads to expose the areas with UBM. 17. Electroplate the Cu core. 18. Strip off the photoresist. 19. Etch off the Ti/Cu. 20. Electroless Ni and immersion Au. UBM is completed. A typical cross section of the RDLs with polymers (e.g., BCB) as passivation and Cu plating as metal layers is shown in Fig. 3.15 [84]. It can be seen that the thickness of the passivation layers, BCB1 and BCB2, is about 6–7 μm, and the RDL is about 4 μm. It should be noted that photolithography can be directly applied on PI or BCB for larger dimensions. In that case the first set of photoresists is not needed.

3.6.4 Fabrication of RDLs: SiO2 + Cu Damascene and CMP Method Another method of RDL fabrication is by a Cu damascene process. Starting with the wafer from Figs. 3.12 and 3.13, the fabrication process of RDLs with a Cu damascene technique is primarily based on the semiconductor back-end-of-line process. The details are shown in Fig. 3.16 and listed below [109, 118]. 1. 2.

SiO2 layer by PECVD (plasma-enhanced chemical vapor deposition). Apply photoresist and mask, then use photolithography techniques (align and expose) to open vias on the SiO2 .

3.6 Passive TSV-Interposer Fabrication

153

SiO2 TSV (Cu)

SiO2 Si

Photoresist TSV

V01

Ta/Cu or Ti/Cu Mask. litho

SiO2 TSV

TSV

V01

TSV

V01

TSV

V01

TSV

V01

SiO2 by PECVD RIE of SiO2

Photoresist TSV Mask, litho TSV

TSV

RIE of SiO2

TSV

Strip resist

TSV

Sputter Ti/Cu and plate Cu

V01

TSV

CMP Cu and Ti/Cu

V01

SiO2 by PECVD

Sputter Ti/Cu and plate Cu

RDL1 TSV

CMP Cu and Ti/Cu

V01

RDL2 DL2 DL1

TSV

Strip resist

RDL1 TSV

V01

V12

DL12 DL01

Fig. 3.16 Process flow of RDLs fabricated by Cu Damascene method

3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.

RIE (reactive ion etch) of SiO2 . Strip off the photoresist. Sputter Ti and Cu and electrochemical deposition (ECD) Cu over the entire wafer. CMP the Cu and Ti/Cu. V01 (the via connecting the TSV to RDL1) is completed. Repeat step 1. Apply photoresist and mask, and then use photolithography techniques to open the redistribution trace locations. Repeat step 3. Repeat step 4. Repeat step 5. CMP the Cu and Ti/Cu. RDL1 is completed. Repeat step 1 through step 6 to complete V12 (the via connecting the RDL1 to RDL2). Repeat step 7 through step 12 to complete RDL2 and any additional layers. (For UBM) Repeat step 1. Apply photoresist and mask, and then use photolithography techniques (align and expose) to open vias on the SiO2 for the desired bump pads and cover the redistribution traces.

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

TSV (Cu)

SiO2 Si

SiO2

Mask. litho TSV

Ta/Cu or Ti/Cu

RIE of SiO2 SiO2

TSV TSV

SiO2 by PECVD Strip resist

TSV Photoresist TSV

TSV

Sputter Ti/Cu and plate Cu

V01

RDL1 CMP Cu and Ti/Cu

Mask, litho TSV

TSV

V01

RDL2 DL2 TSV

RIE of SiO2

DL1

RDL1 TSV

V12

V01

DL12 DL01

Fig. 3.17 Process flow of RDLs fabricated by dual Cu damascene method

17. 18. 19. 20. 21. 22. 23. 24.

Etch the desired vias on the SiO2 . Strip off the photoresist. Sputter Ti and Cu over the entire wafer. Apply photoresist and mask, and then use photolithography techniques to open the vias on the bump pads to expose the areas with UBM. Electroplate Cu core. Strip off the photoresist. Etch off the Ti/Cu. Electroless Ni and immersion Au. UBM is completed.

It should be noted that the RDLs can also be fabricated by the dual Cu damascene method as shown in Fig. 3.17 [109, 118]. SEM images of the RDL cross sections fabricated by a Cu damascene technique are shown in Fig. 3.18. The minimum RDL line width is 3 μm. The thickness of RDL1 and RDL2 is 2.6 μm and of RDL3 is 1.3 μm. The passivation thickness between RDLs is 1 μm.

3.6.5 A Note on Contact Aligner for Cu Damascene Method The RDLs in this section are fabricated by the Cu damascene method. Lithography using a contact aligner provides a low-cost process as compared with a

3.6 Passive TSV-Interposer Fabrication

155

UBM V23

RDL3 RDL2 V12

RDL1 V01

TSV

TU TO

RDL3 V23

RDL2 V12

RDL1 V01

RDL2

RDL1

TSV

RDL3

TSV

RDL3 V23

RDL2 V12

RDL1 V01

TSV

Fig. 3.18 SEM images of cross sections of RDLs fabricated by Cu damascene method

stepper/scanner under the same resolution requirements. Since the minimum line width is 3 μm in this case, the mask had to be placed very close to the (photoresist) surface of the 300 mm wafer. In a few cases, particles on the contact aligner mask punched holes on the photoresist. In this case, shorts may happen such as that shown in Fig. 3.19, which happened while fabricating the V12 (the via connecting RDL1 and RDL2). This can be prevented by cleaning the mask between exposures. Alternately, if cost is not an issue, using a stepper/scanner is another solution.

3.6.6 Backside Processing and Assembly The process flow of backside and assembly is shown in Fig. 3.20. It can be seen that after the fabrication of TSV, RDLs, passivation, and UBM, the topside of the interposer wafer is temporary bonded to a carrier by adhesive. The next step is backgrinding the interposer wafer, Si etching, low temperature passivation, and Cu revealing. Next, backside RDL (optional), UBM, and C4 wafer bumping are carried out. After that, the next step is to temporary bond another carrier wafer to the backside (with solder bumps) and de-bond the first carrier wafer. This step is followed by chip-on-wafer bonding and underfilling. After the whole (chip-on) interposer wafer is completed, the next step is to de-bond the second carrier wafer and transfer the thin

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

RDL2 RDL2

Short

RDL1

RDL1

Fig. 3.19 SEM/FIB showing the short between RDL1 and RDL2. The thickness of the passivation layer between RDL1 and RDL2 is < 1 μm

interposer wafer with attached chips to a dicing tape for singulation. The individual TSV/RDL interposer with chips is attached to the package substrate by natural reflow and then underfilled. Figure 3.21 shows more detail on Cu revealing. Right after the temporary bonding of the support carrier, backgrinding the wafer to a few microns to the TSV, Si dry etching (by RIE) to a few microns below the TSV, and low temperature passiving the SiN/SiO2 are performed. Then, CMP for SiN/SiO2 buffing and barrier and Cu seed layers polishing are carried out. Cu revealing is completed and shown in Fig. 3.22 [109, 118].

Carrier #1 Carrier #1

Interposer

Carrier #1

Carrier #1

Backgrinding

Si Etching, Pass., and Cu Revealing

Temporary Bonding

Chip

Carrier #1

Carrier #1

UBM

Carrier #2 C4 Wafer Bumping

Chip

Chip

Chip Wafer bumping & dicing

TSV

Carrier #2 De-bonding Carrier #1

Carrier #2 Chip-on-Wafer. Underfill

Temporary Bonding Carrier #2

De-bonding Carrier #2 and dicing

RDLs Interposer

Package Substrate

Assemble the TSV module on package substrate, then test. Underfill

Fig. 3.20 Conventional process flow for 2.5D/3D IC integration (chip on interposer wafer on package substrate)

3.7 Multiple System and Heterogeneous Integration with Passive …

157

RDLs and UBM

Support Carrier

TSV

Complete

SiO2 frontside RDLs & UBM

Si

Adhesive

Si

Adhesive

TSV

TSV

Si

Ta/Cu passivation

Support Carrier Adhesive

Si

TSV

Temporary bonded to a carrier by adhesive. Backgrinding to a few microns to the TSV

Support Carrier Adhesive

Si

TSV

Cu Solder

SiN/SiO2

CMP for SiN/SiO2 buffing, and barrier and Cu seed layers polishing

Adhesive

Si

Adhesive

Si

TSV

Support Carrier Adhesive

Si

RDLs and UBM

TSV Cu Solder

Ti/Cu Si dry etch (RIE) to a few microns below the TSV

Strip resist and etch Ti/Cu

Support Carrier

SiN/SiO2 SiO 2 Ta/Cu

Support Carrier

Photoresist, Mask, litho, Cu plating, solder plating

Support Carrier

Low temperature SiN/SiO2

passivation SiN/SiO2

Sputter Ti/Cu

Not-to-Scale

TSV Ti/Cu

Fig. 3.21 Backside Cu reveal and UBM/solder plating process flow

SiO2

SiO2

Si

Cu TSV

Si Si

Cu TSV

Si

Fig. 3.22 TSV Cu revealing. Left: Before dry etch of Si. Right: After Si dry etching, lowtemperature SiN/SiO2 , and removal (CMP) of the isolation, barrier, and seed layer

3.7 Multiple System and Heterogeneous Integration with Passive TSV-Interposers (2.5D IC Integration) 3.7.1 CEA-Leti’s SoW (System-on-Wafer) One of the early applications of 2.5D IC integration is system-on-wafer (SoW) given by Leti [46, 47] as shown in Fig. 3.23. It can be seen that a system of chips such as

158

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Energy source

ASIC + memories Si Interposer

MEMS

TSV Solder bump/ball Embedded passives

Demonstrator wafer

Fig. 3.23 CEA-Leti’s SoW (the origin of 2.5D IC integration)

application specific IC (ASIC) and memories, PMIC (power management IC) and MEMS (micro-electro-mechanical system) are on a silicon wafer with TSV s and RDLs. After dicing, the individual unit becomes a system or subsystem and can be attached on an organic package substrate or stand alone.

3.7.2 TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) During the TSMC’s investor conference for the third quarter of 2011 when Dr. Morris Chang (founder of TSMC), without any advance warning, shocked everybody by announcing his company would move into the packaging and testing field. The first product would be chip-on-wafer-on-substrate (CoWoS), which integrates logic computing and memory chips by mounting them on a silicon interposer and then placing them directly on a package substrate. Today, the industry calls CoWoS as 2.5D IC integration.

3.7 Multiple System and Heterogeneous Integration with Passive …

159

3.7.3 Xilinx/TSMC’s Multiple System and Heterogeneous Integration Since 2011 Xilinx have been published papers on 2.5D IC integration [82, 83, 103– 105, 115–117, 125, 126, 141, 142]. As shown in Fig. 3.24, in order for better device manufacturing yield (to save cost), a very large FPGA (field programmable gate array) chip has been split into 4 smaller FPGA chips made by TSMC’s 28 nm process technology (in 2013). The 10,000+ of lateral interconnections between FPGA chips are connected mainly by the 0.4 μm-pitch (minimum) RDLs of the TSV-interposer. The minimum thickness of the RDLs and passivation is ~ 1 μm. Each FPGA has more than 50,000 micro bumps (200,000+ micro bumps on the TSV-interposer) at 45 μm pitch as shown in Figs. 3.24 and 3.25. Thus, passive TSV/RDL interposers are for extremely fine-pitch, high-I/O, high performance, and high-density semiconductor IC applications. On October 20, 2013, Xilinx and TSMC [159] have jointly announced production release of the Virtex-7 HT family with 28 nm process technology, what the pair claims is the industry’s first 2.5D IC integration in production. Today, Xilinx and TSMC are working far beyond the above. Figure 3.26 shows a test vehicle, which consists of a 31.5 mm × 41.7 mm × 100 μm TSV-interposer and is fabricated using TSMC’s CoWoS XLTM 65 nm BEOL technology. There are three

For better manufacturing yield (to save cost), a very large SoC has been split into 4 smaller chips.

Chip

Chip

Metal Layers

Interposer C4 Bumps PTH

Build-up Layers

Core

Devices

Package Substrate

Metal Contacts

(Cannot see)

Si Solder Balls

Micro Bump

Cu Pillar Solder

4RDLs

The package substrate is at least (5-2-5) Fig. 3.24 Xilinx/TSMC’s CoWoS for FPGA

TSV

Interposer

RDLs: 0.4μm-pitch line width and spacing Each FPGA has >50,000 μbumps on 45μm pitch Interposer is supporting >200,000 μbumps

160

3 Multiple System and Heterogeneous Integration with TSV-Interposers Cu-Pillar Microbump

Interposer

Build-up Layers

4RDLs

Core TSV

C4 bumps

Package Substrate is 6-2-6 (12) build-up layers 200,000+ Cu-Pillar microbumps are at 45μm pitch 4RDLs are at (minimum) 0.4μm pitch

Fig. 3.25 Xilinx/TSMC’s CoWoS (6-2-6 build-up package substrate)

FPGAs and two HBMs. The package substrate size is 55 mm × 55 mm × 1.9 mm. For the first Batch of thermal cycling test results there are some failures before the required 1200 cycles. Figure 3.26 shows cross-section SEM failure analysis. The SEM shows a crack in the C4 underfill running from the edge of the interposer to the C4 bump region. The crack is primarily located along the interposer edge, along it occasionally appears along the copper pillar in the C4. The stress which causes failure is primarily due to CTE mismatch between the substrate and die-interposer assembly. The shrinking of the underfill due to curing and thermal aging is a secondary concern. By increasing the substrate thickness, the thermal cycling test passed the 1200 cycles. For more information, please read [142].

3.7.4 Altera/TSMC’s Multiple System and Heterogeneous Integration Figure 3.27 shows one of the cross sections of Altera’s 2.5D IC integration [106, 107]. It can be seen that the chips are supported by the TSV-interposer with Cupillar + solder cap microbumps. Then the TSV-interposer is C4 bumped on a 6-2-6 package substrate. The TSV-interposer is fabricated by TSMC’s CoWoS technology. Unfortunately, this never went into HVM.

3.7 Multiple System and Heterogeneous Integration with Passive …

161

μJoint

Cu

Cu

Si-interposer

Ni SnAg

C4 Si-interposer

SnAg Ni Cu

Cu μSolder Joint

Fig. 3.26 Xilinx/TSMC’s VIRTEX

Interposer

TSV

Chip

C4 Bumps Build-up Layers

Solder

Package Substrate

Solder Balls

Cu Pillar

The package substrate is at least (6-2-6) RDLs TSV

Interposer

Fig. 3.27 Altera/TSMC’s CoWoS

4 RDLs: 0.4μm-pitch line width and spacing Each FPGA has >50,000 μbumps on 45μm pitch Interposer is supporting >200,000 μbumps

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

3.7.5 AMD/UMC’s Multiple System and Heterogeneous Integration Figure 3.28 shows AMD’s Radeon R9 Fury × GPU shipped in the second half of 2015. The GPU is built on TSMC’s 28 nm process technology and is supported by four HBM cubes manufactured by SK Hynix. Each HBM consists of four dynamic random-access memories (DRAMs) with Cu-pillar + solder cap bumps and a logic base with TSVs straight through them. Each DRAM chip has > 1000 TSVs. The GPU and HBM cubes are on top of a TSV interposer (28 mm × 35 mm), which is fabricated by UMC with a 64 nm process technology. The final assembly of the TSV interposer with C4 (controlled collapse chip connection) bumps on a 4-2-4 organic package substrate (fabricated by Ibiden) is by ASE. Some cross section SEM images are shown in Fig. 3.29. It can be seen that the GPU and the HBM are supported by the TSV-interposer with microbumps (Cu-pillar + solder cap). The TSV-interposer is supported by a 4-2-4 build-up package substrate with C4 bumps.

GPU

HBM

HBM

HBM

HBM

The GPU (23mm x 27mm) is fabricated by TSMC's 28nm Process technology

Stiffener Ring The Organic Substrate (54mm x 55mm) is with 2111 balls at 1.2mm pitch The Si-interposer (28mm x 35mm) is fabricated by UMCís 65nm process technology Fig. 3.28 AMD/UMC’s GPU (Fiji)

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163

C4-bump 4-2-4 Buildup substrate

Core

μbump (Cu-Pillar with solder Cap)

TSV

GPU with microbumps TSVInterposer C4 Solder Cu

Build-up organic substrate

Fig. 3.29 SEM images of the AMD/UMC’s GPU module

3.7.6 NVidia/TSMC’s Multiple System and Heterogeneous Integration Figures 3.30 and 3.31 show NVidia’s Pascal 100 GPU, which was shipped in the second half of 2016. The GPU is built on TSMC’s 16 nm process technology [130] and is supported by four HBM2 (16 GB) fabricated by Samsung. Each HBM2 consists of four DRAMs with Cu-pillar + solder cap bumps and a base logic die with TSVs straight through them. Each DRAM chip has > 1000 TSVs. The GPU and HBM2s are attached with microbumps on top of a TSV interposer (CoWoS-2, 1200 mm2 ), which is fabricated by TSMC with a 64 nm process technology. The TSV interposer is attached to a 5-2-5 organic package substrate with Cu-C4 bumps.

3.7.7 TSMC’s Multiple System and Heterogeneous Integration with DTC Figure 3.32a shows a conceptual structure of high-performance computing on a new CoWoS platform [147]. It consists of a logic die, HBM2Es, a silicon interposer, and

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

HBM2 HBM2

GPU HBM2 HBM2

Package Substrate

Fig. 3.30 NVidia/TSMC’s P100 HBM2 by Samsung 4DRAMs

HBM2

GPU

Base logic die TSV Interposer (TSMCís CoWoS-2) Build-up Package Substrate C4 bump Solder Ball

Fig. 3.31 SEM images of the NVidia/TSMC’s P100

µbump

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165

a substrate. The logic and HBM2Es are first bonded side-by-side on the silicon interposer to form chip-on-wafer (CoW) with the fine pitch and high-density interconnect routing among the devices. In the silicon interposer, the DTC (deep trench capacitor) is developed with the high aspect ratio silicon etch at dimensions. The high-k dielectric layer of the DTC is sandwiched between a top and a bottom electrode layer in the silicon trenches of aspect ratio over 10 to form the capacitor [147]. Two distinct process sequences are available to realize the DTC in the silicon interposer. Figure 3.32b shows normalized capacitance density versus voltage of the DTC that is defined over the equivalent plenary surface area over the DTC structure. The capacitance density at 100 kHz measured by an inductance, capacitance, and resistance (LCR) meter is ~ 300 nF/mm2 at zero applied voltage for the high-k dielectric film. It provides the capacitance density of an order higher than metal– insulator-metal capacitor. Figure 3.32c shows two normalized I–V curves for this high-k dielectric film measured at 25 and 100 °C, respectively. It can be seen that the measured leakage current at ± 1.35 V bias is still below 1 fA/μm2 even at the

Fig. 3.32 a TSMC’ CoWoS with deep trench capacitor. b Capacitance density versus applied voltage. c Leakage density versus applied voltage

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

testing temperature of 100 °C. This excellent characteristic prevents the additional power wasted in the DTC [147].

3.7.8 Samsung’s Multiple System and Heterogeneous Integration with Integrated Stack Capacitor (ISC) During IEEE/ECTC 2020, Samsung presented a paper on power integrity performance gain of a novel integrated stack capacitor (ISC) solution for high-end computing applications [162], Fig. 3.33a. Unlike DTC in [147], Samsung use a vertical cylinder array consisting of many capacitive vias called ISC. The trench depth of ISC is lower than that of DTC, Fig. 3.33b. The embedded ISC assumed 40% of the total area of the TSV-interposer, Fig. 3.33a. The power self-impedance in the low frequency band can be suppressed by placing the package level capacitors, and the power self-impedance in the high frequency band shows clearly that the ISC solution is effective, Fig. 3.33c [162]. (a)

Substrate

Embedded

BEOL

ISC

Si

(a) (b)

(c)

Fig. 3.33 Samsung’s multiple system and heterogeneous integration. a 2.5D with ISC. b ISC. c The normalized PDN impedance of the embedded ISC in TSV-interposer

3.7 Multiple System and Heterogeneous Integration with Passive … 4 x BOW 3D Wafer-on-wafer IPUs 1.4 PetaFLOPS AI compute 3.6 GB In-Processor-Memory @ 260TB/s Up to 256 GB IPU Streaming Memory 2.8 Tb/s IPU-FabricTM Same 1U blade form factor

3D silicon wafer stacked processor 350TeraFLOPS AI compute Optimized silicon power delivery 0.9 GigaByte In-Processor-Memory @ 65TB/s 1,472 independent processor cores 8,832 independent parallel programs 10x IPU-LinksTM delivering 320GB/s

C4 bump

C4 bump

C4 bump

C4 bump

167

C4 bump

C4 bump

C4 bump

UBM

BEOL

Cu-Cu bonding

BEOL Colossus Die

Fig. 3.34 Graphcore’s IPU (intelligence processing unit) processor

3.7.9 Graphcore’s Multiple System and Heterogeneous Integration Figure 3.34 shows Graphcore’s Bow—an IPU (intelligence processing unit) processor [186]. The IPU processor system is supporting by a passive TSV-interposer with deep trench capacitors. The assembly is by face-to-face TSMC’s SoIC (system on integrated chips) Cu–Cu bumpless hybrid bonding.

3.7.10 Fujitsu’s Multiple System and Heterogeneous Integration Fujitsu’s Fugaku is the first ‘Exascale’ supercomputer. It is driven by their A64FX leading-edge CPU as shown in Fig. 3.35 [187]. It is fabricated by TSMC’s 7 nm process technology and with 8.786 billion transistors. The packaging system is also shown in Fig. 3.35. It can be seen that the multiple system (CPU and 4 HBMs) is supporting by TSMC’s CoWoS and then on a build-up package substrate (60 mm × 60 mm).

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

HBM2 HBM2

CPU HBM2 HBM2

HBM2

CPU

HBM2

TSV-interposer

Package substrate

Fig. 3.35 Multiple system and heterogeneous integration (Fujitsu’s CPU)

3.7.11 Samsung’s Multiple System and Heterogeneous Integration (I-Cube4) Figure 3.36 shows the I-Cube4 by Samsung [188]. It can be seen that the multiple system is supporting by a passive TSV-interposer and then on a build-up package substrate. There are 4 HBMs, each consists of four or eight DRAMs and a logic base, and they are connected through TSVs and microbumps with underfills.

3.7.12 Samsung’s Multiple System and Heterogeneous Integration (H-Cube) Figure 3.37 shows the H-Cube proposed by Samsung [189]. In this case, there are 6 HBMs and the size of the passive TSV-interposer and the package substrate are much larger than those with 4 HBMs. In order to release the pressure from the package substrate, they add another fine-pitch substrate between the TSV-interposer and the package substrate. The size of the fine-pitch substrate is only slightly larger than that of the TSV-interposer.

Top View

HBM

169

HBM

SoC HBM

TSV Interposer

HBM

3.7 Multiple System and Heterogeneous Integration with Passive …

Package Substrate Bottom View TSV SoC

Cross-section View

DRAM

μbump μbump C4 bump

TSV-Interposer

Package Substrate

Solder Ball

PCB Fig. 3.36 Samsung’s I-Cube4 HBM HBM

HBM

Logic

HBM HBM

HBM

TSV μbump

TSV-

Fine-pitch Substrate

μbump TSV C4 or μbump C4 bump Solder ball

PCB Fig. 3.37 Samsung’s H-Cube

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

HBM HBM

ASIC

(a) HBM

HBM HBM

ASIC

HBM HBM

HBM

EMC Crack

HBM

ASIC

HBM

TSV Interposer

Corner Underfill Crack Package Substrate

PCB

(b) Fig. 3.38 Multiple system and heterogeneous integration (Samsung’s MIoS)

3.7.13 Samsung’s Multiple System and Heterogeneous Integration (MIoS) During ECTC 2021 and 2022, Samsung presented two papers on extremely large 2.5D molded interposer on substrate (MIoS) package as shown in Fig. 3.38a [190, 191]. This MIoS package consists of eight HBMs, two logics, a very large TSVinterposer (51 mm × 55 mm), and a very large package substrate (85 mm × 85 mm). Because of the thermal expansion mismatch among the chip, TSV-interposer, epoxy molding compound (EMC), underfill, and package substrate, the cracking of EMC and the cracking of the corner of underfill are possible as shown as in Fig. 3.38. Thus, proper structural design and material selection are very important.

3.7.14 IBM’s Multiple System and Heterogeneous Integration (TCB) During ECTC 2021, IBM presented a paper on 3D die-stack on substrate (3D-DSS) packaging technology and finite element analysis of (55–75 μm) mixed pitch interconnections on high density laminate [192]. It should be noted that: (a) there are

3.7 Multiple System and Heterogeneous Integration with Passive …

171

Chip Chip-1

Chip-2

Al-pad Micro bump TSV-interposer Micro bump

(a)

Cu

(b)

Thin-film high-density layer

Package substrate

Cu-pad

Solder Via-pad on TSV-interposer

Chip (c)

Micro bump

TSV-interposer

(d)

Micro bump Thin-film layer on package substrate

Fig. 3.39 IBM multiple system and heterogeneous integration (TCB)

microbumps on both sides of the TSV-interposer, Fig. 3.39a, (b) there are thin-film layers on top of the package substrate, and (c) this is for very high-density and highperformance applications. Figure 3.39b shows an individual microbump between the chip and the TSV-interposer. Figure 3.39c shows the microbumps between the chip and the TSV-interposer. Figure 3.39d shows the microbumps between the TSVinterposer and the thin-film layer of the package substrate. All the μbumps are formed by thermocompression bonding (TCB).

3.7.15 IBM’s Multiple System and Heterogeneous Integration (Hybrid Bonding) During ECTC2021, IBM presented a paper on plasma activated low-temperature dielevel direct bonding with advanced wafer dicing technologies for 3D heterogeneous integration [193]. In this paper, they changed the microbumps, Fig. 3.40a, between the chips and the TSV-interposer into bumpless, Fig. 3.40b. Also, they changed the TCB into Cu-Cu D2W (die-to-wafer) hybrid bonding, Fig. 3.40c. On both the top (chip) and bottom (TSV-interposer) wafers with Cu pads, it starts off with chemical vapor deposition (CVD) a dielectric material such as SiO2 and

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Chip-1

Chip-2 Chip-1

Chip-2

Micro bump TSV-interposer Micro bump

TSV-interposer Micro bump

Thin-film high-density layer

Thin-film high-density layer

Package substrate

Package substrate

(a)

(b) Cu Dishing SiO2

Chip Wafer Si

Chip Wafer

Bumpless Cu-Cu hybrid bonding

CMP

TSV-interposer Wafer Si

TSV-interposer Wafer CMP

Dicing

Plasma

Hydration

Cu Dishing SiO2

Individual chip-toTSV-interposer Wafer bonding (RT) Plasma

Annealing & then Dicing

Hydration

(c) Fig. 3.40 IBM multiple system and heterogeneous integration (hybrid bonding)

then it is planarized by an optimized CMP process. This is the most critical step (in hybrid bonding) to obtain the desirable oxide surface topography and Cu pad dishing height. Then, dice the top wafer into individual chips (still on the blue tape of the wafer) after coating protective layer on the wafer surfaces to prevent any particle and contaminant that may cause interface voids during the subsequent bonding process. It is followed by activating the bonding surface by plasma and hydration processes for better hydrophilicity and higher density of hydroxyl group on the bonding surface. Finally, stack the chips on the bottom wafer by hybrid bonding and place the whole module in a high temperature annealing chamber for covalent bonding between oxide layers and metallic bonding between Cu-Cu contact and diffusion of Cu atoms.

3.7.16 Multiple System and Heterogeneous Integration of EIC and PIC (Side-by-Side) The TSV-interposer integration platform for photonic IC (PIC) and electronic IC (EIC) of high-speed and high-bandwidth applications is getting lots of tractions. Figure 3.41 shows a conceptual layout of a multiple system and heterogeneous

3.7 Multiple System and Heterogeneous Integration with Passive …

Laser

Driver

TiA

Heat Sink

Signal Fiber Fibers (Optical Coupler)

Electrical

ASIC/Switch

173

PD

Heat Spreader

Signal Fiber

Fiber Block Heat Spreader/Sink

ASIC/Switch TSV

PIC

EIC

μbump

Signal Fiber

TSV-interposer TSV-interposer Thermoelectric Cooler Dummy Fiber

C4 bump

Package Substrate Solder Ball PCB PCB

Fig. 3.41 ASIC, EIC, and PIC heterogeneous integration with passive TSV-interposer (sis-by-side)

integration of PIC and EIC devices as well as ASIC/switch [10]. It can be seen that the package substrate is supporting the TSV interposer with a thermoelectric cooler, which is supporting the ASIC/switch, EIC and PIC with C2 (chip connection) μbumps. The TSV interposer also supports the fiber assembly with a fiber block for the PIC, which requires very high alignment accuracy (1 μm) in order to achieve good optical coupling efficiency. The TSV interposer is with a deep trench or U-groove for the dummy fiber placement.

3.7.17 Multiple System and Heterogeneous Integration of EIC and PIC (3D Stacked) In Fig. 3.41, the EIC and PIC are integrated side-by-side on a TSV interposer. In Fig. 3.42, the EIC and PIC are stacked in the vertical direction (3D). They are face-toface bonding with microbumps or bumpless Cu-Cu hybrid bonding. There are TSVs in the PIC for vertical communications between the EIC and PIC. This structure design is not only less in-plane area but also better opto-electrical performance.

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

EIC

PIC

Fibers (Optical Coupler)

ASIC/Switch

Electrical

Signal Fiber

Signal Fiber

Heat Sink

Heat Spreader

Heat Spreader/Sink

Fiber Block

Face-to-Face EIC PIC

ASIC/Switch μbump TSV

Dummy Fiber TSV-interposer TSV-interposer Thermoelectric Cooler

TSV

Signal Fiber

C4 bump Package Substrate Solder Ball PCB PCB

Fig. 3.42 ASIC, EIC, and PIC heterogeneous integration with TSV-interposer (3D-stacked)

3.7.18 Fraunhofer’s Multiple System and Heterogeneous Integration with Glass-Interposer Figure 3.43 shows the conceptual layout of the single-mode router by Fraunhofer [149]. The interposer is intended to be assembled on a glass-based optical PCB (OPCB), where the interconnectivity between the optical layer of the OPCB and the Si interposer is done vertically by means of one mirror coupling element, as shown in Fig. 3.43 [149]. For the routing operation, each one of the 12 optical channels streamed from the OPCB is fed to a separate photodiode (PD) and its respective electronic transimpedance amplifier (TIA). The TIA can then perform optoelectronic conversion of the incoming signals, while the received electrical signal is then transmitted to an electronic driver amplifier prior to driving the modulation operation of a vertical cavity surface-emitting laser (VCSEL) [67]. Each VCSEL is then tuned to a different wavelength through current injection to match the channel spacing of the arrayed waveguide grating (AWG) multiplexer on the silicon layer. TSVs are used for electrical connection of frontside and backside of the wafer using underlying metals stack (left) and so-called optical TSV without metal layers at the TSV bottom (right).

3.7 Multiple System and Heterogeneous Integration with Passive … Fig. 3.43 Fraunhofer’s 3-D silicon photonics interposer for Tb/s optical interconnects

175

VCSEL

Si Interposer Chip

DRIVER SiO

SiO

2

Si

TSV

SiO

2

SiO

2

2

UBM

PCB

Glass Layer Waveguide

Electrical TSV

Metal

Optical TSV

No Metal

3.7.19 Fujitsu’s Multiple System and Heterogeneous Integration with Glass-Interposer Figure 3.44 shows Fujitsu’s multilayer glass interposer. The through glass vias (TGVs) are fabricated by the laser induced deep etching (LIDE). The TGVs are filled by screen printing of a conductive paste. The microbumps (Cu-pillar + solder cap) at 40 μm-pitch are the interconnects between the chip and the glass interposer. For more information of this package, please read [150].

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3 Multiple System and Heterogeneous Integration with TSV-Interposers μbumps

CHIP

Glass Interposer

CHIP

Solder

TGV Conductive Paste

Cu-Pillar

Fig. 3.44 Fujitsu’s glass interposer with TGV filled with conductive paste

3.7.20 Dai Nippon/AGC’s Multiple System and Heterogeneous Integration with Glass-Interposer Figure 3.45 shows Dai Nippon/AGC’s glass interposer for high-frequency and highspeed applications, especially for antenna-in-package (AiP) [151]. Their basic structure consists of coplanar waveguide (CPW) on top of a quartz substrate with through quartz via (TQV) connecting top to bottom circuits. The typical TGV (through-glass via) and Cu wiring are also shown. The interposer thickness is 400 μm, and the topdiameter of the TGV is approximately 80 μm while the bottom-diameter is 50 μm. The linewidth and spacing of the Cu wire are 2 μm.

3.7.21 GIT’s Multiple System and Heterogeneous Integration with Glass-Interposer Figure 3.46 shows schematically a large-body-sized glass-based interposer for highperformance computing by George Institute of Technology (GIT) [194]. It can be seen that; (a) the glass interposer with TGVs is supporting chiplets as well as active routers and passive components, and (b) there are RDLs on the active interposer’s topside and bottom-side. Also, the electrical performance (insertion loss per unit

Cu-seed

177

Glass

3.7 Multiple System and Heterogeneous Integration with Passive …

TGV Cu

Cu wire: L/S = 2μm RF Front End IC

AiP

Fig. 3.45 Dai Nippon/AGC’s glass interposer for AiP

length) for different traces on glass interposer is better than that on silicon. A cross section of the sample is shown in the middle of Fig. 3.46. It can be seen that a 100 μmthick die embedded in the glass cavity is connected to the chiplet (not shown) on top of the TGV-interposer with RDLs.

3.7.22 Leibniz University Hanover/Ulm University’s Electroless Glass Interposer First of all, TGVs are commonly metallized using PVD (physical vapor deposition), CVD (chemical vapor deposition), or electroless deposition for a seed layer followed by the electrochemical deposition (ECD) of copper. In [195], inspired by molded interconnect devices (MID) technologies, Leibniz University Hanover and Ulm University presented a paper at ECTC2022 on approaches for a solely electroless metallization of TGVs. The objective of their paper is a solely electroless TGV filling on the basis of three priming approaches: (a) self-assembling monolayers of (3-mercaptopropyl) trimethoxysilane (MPTMS), (b) a photocatalytic layer of titanium tetraisopropoxide (TTiP) and (c) a sol-gel process. Priming with a TBuT solution proved to be particularly suitable. This coating has high-temperature resistance, good adhesion in the TGVs, and allows a solely electroless filling with a layer

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Chiplet Passive Glass

(a)

Chiplet Router

TGV

178

Passive

µm

(b)

µm µm

(c)

Fig. 3.46 a Schematic of glass-based active interposer. b Fabricated sample. c Insertion loss/mm for various traces on glass active interposers and Silicon

stack of NiCuNiAu and CuNiAu. Their process and the successful samples are shown in Fig. 3.47.

3.7.23 Summary and Recommendations Some important results and recommendations are summarized as follows. • TSV was invented by the 1956 Nobel Laureate in Physics, William Shockley on October 23, 1958. • TSV can be fabricated by at least 4 processes: (a) via-first; (b) via-middle; (c) via-last from the frontside; and (d) via-last from the backside. • There are at least 2 groups of TSV interposers: (a) passive TSV-interposer (2.5D IC integration), and (b) active TSV-interposer (3D IC integration). • Passive TSV-interposers are and will be used the most. However, recently active TSV-interposers are getting lots of tractions.

3.7 Multiple System and Heterogeneous Integration with Passive …

179

Fig. 3.47 Leibniz University Hanover/Ulm University’s electroless glass interposer

• Active TSV-interposer which involves (besides the TSVs and RDLs) the fabrication of the CMOS devices and thus it is out of the scope of this packaging study. However, the multiple system and heterogeneous integration with active TSV-interposer reported by UCSB, Intel, CEA-Leti, and AMD has been briefly mentioned. • Passive TSV-interposer which involves the fabrication of TSVs (with the via-first process) and RDLs (with the polymer + Cu-plating and etching process and with the SiO2 + Cu damascene and CMP process) has been presented. Also, more than 25 examples of multiple system and heterogeneous integration have been briefly mentioned.

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

• For better electrical performance and power self-impedance in the high frequency band, DTC [147] and ISC [162] are recommended for multiple system and heterogeneous integration with passive TSV-interposer. • For high-density and high-performance applications, it is recommended to replace the C4 bumps between the TSV-interposer and the build-up package substrate into microbumps and add thin-film layers on top of the build-up package substrate [192]. • For extremely high-density and high-performance applications, it is recommended to replace the microbumps between the chips/HBMs and the TSV-interposer into bumpless and assemble the chips/HBMs to the TSV-interposer by Cu-Cu bumpless hybrid bonding [186, 193]. • Multiple system and heterogeneous integration with glass-interposer can be niche applications such as AiP [151]. • Co-packaged optics (CPO) are getting lots of tractions. A couple of examples of multiple system and heterogeneous integration of EIC and PIC (side-by-side and 3D stacked) with TSV-interposer have been presented. • With chips/HBMs on both sides of the passive TSV-interposer could be an alternative to the traditional 2.5D IC integration. • One of the trends in multiple system and heterogeneous integration with passive TSV-interposer is increasing the size of the interposer. This posts challenges (opportunities) on: (a) the C2 TCB assembly yield of chips and HBMs on the TSV-interposer due to the large warpage of the interposer, (b) the C4 reflow assembly yield of the TSV-interposer on the build-up package substrate due to the large warpage of the interposer and package substrate, and (c) the solder joint reliability between the TSV-interposer and the chips/HBMs and between the TSVinterposer and the package substrate. Underfill helps. However, when the size of the TSV interposer is very large, cracks in the underfill are possible. Thus, lower modulus underfill (≤ 3 GPa, 25–100 °C) should be used. • The other trend in multiple system and heterogeneous integration with passive TSV-interposer is increasing the size of the build-up package substrate. For examples, (a) the package substrate size in [191] is 85mm x 85mm, (b) the package substrate size in [15] is 91mm x 91mm, and (c) the size of the build-up package substrate is at least 70 mm × 78 mm if the size of the passive TSV-interposer is 2400 mm2 . This posts great challenges (opportunities) on: (a) the fabrication yield of the build-up package substrate, (b) the warpage control of the package substrate, and (c) the solder joint reliability between the passive TSV-interposer and the build-up package substrate and between the package substrate and the PCB. Thus, proper structural design and material selection are utmost important.

3.8 Heterogeneous Integration with Stacked TSV Interposers

181

3.8 Heterogeneous Integration with Stacked TSV Interposers The development of a 2.5D IC integration using silicon carrier with TSV for the integration of RF, baseband, memory chips is presented in this section [50, 63].

3.8.1 Module Construction A 3D module consists of two stacks assembled one over other with three chips (Fig. 3.48). The module size is 12 mm × 12 mm × 1.3 mm. The silicon carrier is 12 mm × 12 mm × 0.2 mm with 168 peripherally populated via. The bottom carrier (Carrier 1) is assembled with a 5 mm × 5 mm flip-chip. The top carrier (Carrier 2) is assembled with a 5 mm × 5 mm flip-chip and two 3 mm × 6 mm wirebonded chips. Carrier 2 is overmolded to protect the wire bond chip. The silicon carrier has been fabricated with two metal layers with SiO2 as dielectric/passivation layer. Electrical connections through the carrier are formed by TSVs. A schematic of the two-stack module and chip arrangement on Carriers 1 and 2 are shown in Fig. 3.48.

3.8.2 Thermo-Mechanical Design Thermo-mechanical design of the 3D silicon module is important for the reliable package structure. Structural parameters like via size, via shape, and solder joint are analyzed for the minimum thermo-mechanical stresses. The finite element (FE) analysis is carried using ABAQUS [196]. 2D eight node solid element is used for the FE model. The stress-free temperature state is taken as 125 °C for thermo-mechanical analysis. Material properties used for the thermo-mechanical analysis are given in Table 3.2. The TSV can be designed in cylindrical shape and tapered shape, thermomechanical stresses of the TSV have been studied using FE analysis. The tapered TSV structure of size 50 and 100 μm diameter has been analyzed. The interfacial stress between the copper and the surrounding silicon carrier is comparable for both via sizes. But the tapered shape showed 8% higher shear stress than the cylindrical shape. The tapered via is preferred for TSV fabrication processes like conformal deposition of dielectric/barrier/seed layer and void free copper filling. Small via size allows high density routing in the carrier. In this section, we chose via size of 100 μm tapering to 50 μm. The interfacial stress of tapered via and cylindrical via is shown in Fig. 3.49. The location of the solder joint with respect to the TSV is critical for interconnect reliability and redistribution layer (RDL) design. Pad-on via and off-set via designs have been evaluated. The pad-on design, where the solder ball is directly on the

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Chip1

Chip2

Carrier-1

Chip3

182

Carrier-2

Fig. 3.48 Schematic of 3D silicon module and carrier layout

copper plug (TSV), but the copper plug is much smaller compared to the solder pad area as shown in Fig. 3.50. The pad-on via design has advantages in terms of shorter electrical path from chip to the board and un-broken power/ground plane design. Both the designs show comparable stress condition in the solder joint. The simulation results show maximum stress concentration at the smaller section of the via. Therefore, the pad-on via design has been selected for the module construction.

3.8.3 Carrier Fabrication An eight-inch silicon wafer is used for the TSV carrier fabrication. Main processes steps are via etching, deposition of dielectric/barrier/seed layer, via filling, CMP of copper overburden, RDL formation, wafer thinning, via exposure, and dielectric/under bump metallization (UBM) deposition.

3.8 Heterogeneous Integration with Stacked TSV Interposers

183

Table 3.2 Material properties Young modulus (GPa)

Poisson ratio

Coefficient of thermal expansion (ppm/°C)

Benzocyclobutene (BCB)

2.9

0.34

52

SiO2

70

0.16

0.6

Ti

116

0.34

8.9

Silicon

129.617 (25 °C)

0.28

2.813 (25 °C)

128.425 (150 °C) SnAgCu

44.4 (25 °C)

3.107 (150 °C) 0.4

21

30.7 (75 °C) 18.8 (125 °C) Printed circuit board (PCB)

Ex,y = 22.4 (30 °C) Ex,y = 19.3 (125 °C) Ez = 16 (30 °C) Ez = 1 (125 °C)

vx = 0.2 vy,z = 0.1425

αx, y = 16 αz = 65

Cu

E = 130.0

0.34

18

εp = 0 σ = 0.1379 εp = 0.098982 σ = 0.2715

The via–first approach is preferred for the silicon carrier technology, because most of TSV fabrication processes are carried out with the full wafer thickness, then the wafer is thinned to required thickness for via exposure. The thinned wafer is processed further to form the necessary back side metallization/UBM. The carrier fabrication process flow is shown in Fig. 3.51. The silicon wafer is etched using the deep reactive ion etch process forming blind via of 50 μm diameter and 200 μm deep. Via tapering is accomplished by a controlled isotropic etch chemistry consisting of SF6, Argon (Ar), and O2 plasma after the straight etch process. The via formation process is split into three steps viz.: (1) straight via formation; (2) via tapering process by a controlled isotropic etch; and (3) corner rounding by a global isotropic etch process. Tapered via of size 50 μm at the base and 100 μm at the top is achieved after via tapering steps. A dielectric layer of 1 μm SiO2 has been deposited by the plasma enhanced chemical vapor deposition (PECVD) process. Barrier and seed layers of Ti and Cu are deposited using the physical vapor deposition process. The sidewall deposition uniformity is characterized by cross section analysis. The oxide thickness varied from 0.8 μm at the top of the via to 0.4 μm at the bottom of the via as shown in Fig. 3.52. Damascene copper plating is used for the via filling. Typical composition of copper plating electrolyte includes CuSO4, H2SO4, Cl− , with additives such as Suppressor, Accelerator, and Leveler. The plating solution used is Everplate-Cu200 from Atotech. We developed the pulse reverse plating process recipe and demonstrated void free via

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.49 Thermo-mechanical analysis of via shape Fig. 3.50 Via arrange on the carrier

Off-set Pad Design

On-Pad Design

3.8 Heterogeneous Integration with Stacked TSV Interposers

Via etching

CMP

185

Oxide/barrier/seed

Damascene plating of via

Via exposure Multi-level Metallization

UBM deposition and detach the support wafer

Attach with a support wafer and backside metallization

Fig. 3.51 Carrier fabrication process flow

filling. The plating current has been optimized and complete via plating is achieved in three steps viz.: (1) step 1—low forward current plating; (2) step 2—medium forward current plating; and (3) step 3—high forward current plating. A thick layer of copper overburden (30–40 μm) was observed on the TSV wafer surface because of the long plating time required for filling the 200 μm deep via. The wafer warpage/bow observed to be lager (> 500 μm) due to the thick copper overburden, it was measured using an optical probe. Different methods were considered for the removal of the copper overburden. Chemical etching took long time to remove the thick copper overburden and observed non-uniform etch rate across the wafer. CMP was evaluated using aggressive Cu polishing slurry from Rohm and Hass. We developed twostep polishing to remove the thick copper: step 1 to remove the bulk of the copper with high down force (320 g/cm2 ), and step 2 to remove a thin layer of copper with lower down force (100 g/cm2 ). The wafer images before and after the CMP are shown in Fig. 3.53. After CMP, an RDL has been deposited for electrical

186

3 Multiple System and Heterogeneous Integration with TSV-Interposers 98.01μm

Top

70.1μm Mid

Bottem

Fig. 3.52 Coverage of SiO2 in deep silicon via

re-distribution on the carrier wafer. We evaluated BCB and SiO2 as dielectric layer and both the materials were found suitable for our application. A low-temperature (250 °C) PECVD process was used for the SiO2 dielectric deposition. Exposing the buried copper via in the carrier TSV wafer is a challenge, because it requires grinding brittle silicon and ductile copper simultaneously. Conventional backgrinding wheel is found not suitable for the ductile copper and observed wheel clogging. We used a rough grinding step followed by a fine grinding step and CMP to relieve the stress. The carrier wafer was thinned to 250 μm thickness by course grinding, remaining 50 μm was removed with the vitrified bond wheel. Then the wafer was polished by the wet method to remove the sub-surface damages. The wafer

Fig. 3.53 Wafer images after TSV formation

3.8 Heterogeneous Integration with Stacked TSV Interposers

187

Fig. 3.54 Wafer images after TSV formation

surface roughness (Ra) is 17 and 0.45 nm after grinding and wet polishing, respectively. The wafer surface was analyzed by energy dispersive X-ray spectroscopy and AUGERE and found no copper contamination on the wafer. The carrier wafer showing exposed Cu via is given in Fig. 3.54.

3.8.4 Thin Wafer Handling TSV wafer of 200 μm thickness through multiple process steps like oxide deposition, lithography, copper RDL plating is difficult. It is not allowed to process such a thin wafer in most of the wafer processing tools. We developed a thin wafer handler process using a perforated support wafer and temporary adhesive. The temporary adhesive used in the project is spin on polymer from Brewer Science. The polymer is spin coated on the TSV carrier wafer and bonded with the perforated support wafer using EV Group wafer bonder. The wafer bonding was done at 1.2 kN force, 150 °C for 5 min. The bonded wafer was processed for the backside metallization/UBM and passivation layers. After all the processes, the carrier wafer was debonded by wet stripping the temporary adhesive through the perforated support wafer. This method is found suitable for our project but observed some polymer residues on the wafer surface. A sacrificial layer of Titanium was deposited on the TSV carrier wafer before attaching with the support wafer. The sacrificial layer was etched by wet process after debonding from the support wafer. This sacrificial layer helped to protect the carrier wafer surface and polymer residue was etched away along with the sacrificial layer. Figure 3.55 shows images of wirebond and flip-chip pads after debonding.

3.8.5 Module Assembly We evaluated gold stud bump and solder interconnect for chip 1 and chip 2, respectively. Chip 1 has been designed with 72 peripheral I/O. Chip 1 is stud bumped using

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Polymer residue without sacrificial layer

No residue with sacrificial layer

Fig. 3.55 Images of carrier wafer after debonding. a Polymer residue without sacrificial layer. b No residue with sacrificial layer

stud bump bonder. The stud bumping parameters have been optimized and achieved 45 μm bump height with 4 kgf coining force. The stud bump shear and failure mode have been evaluated for high temperature storage up to 1000 h. The bumps showed good shear value of > 60 g. Three NCP materials have been evaluated and the interconnect reliability has been assessed up to 1000 thermal cycles (TC). All the three materials with bonding force > 10 kgf showed no failure. Figure 3.56 shows the stud profile and cross section of the chip attachment. Chip 2 has been designed with 252 I/O at 200 μm bump pitch. Chip 2 was bumped using SAC305 type 6 solder paste and achieved bump height of 55 μm. The bump shear has been evaluated for Pb free reflow condition (five times) and found the bump shear value > 60 g with bulk solder failure mode. Chip 3 represents memory die in our module design. Stacking of two chips has been demonstrated using dicing die attach film (DDAF) and wire embedding film. Three DDAF materials have been evaluated and all the materials showed no void after the Moisture Sensitivity Level 3 condition test. The materials have also been evaluated in hot shear test at 260 °C. One of the materials has been selected based

Fig. 3.56 Images of stud bump interconnection

3.8 Heterogeneous Integration with Stacked TSV Interposers

189

Fig. 3.57 Images of stacked wire bond chips

Overmold

Chip 3

Chip 1

Chip 2

Chip 1

Carrier 1

Chip 3

(a)

Chip 2

Carrier 2

(b)

(c)

Fig. 3.58 Images of 3D silicon module. a Cross section of the 3D module. b 3D module with over molding. c 3D module without over molding.

on minimum bleeding. Wire embedding film is an emerging technique to stack wire bond chips. The film is soft enough to flow over the wires and there is no need for a spacer die. This method gives small stand-off for the stacked wire bond chips.

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

The bond parameters like top/bottom heater temperature and bond speed have been optimized. Carrier 2 is assembled with flip-chip and wire bond chip. Therefore, the pad finish should be suitable for both the chip attachment methods. Pads on the carrier top and bottom side are plated with electroless NiPdAu. Wire bondability and wire pull strength are found good on the NiPdAu pads. Two chips have been stacked and demonstrated low loop height (< 50 μm) for the chip stacking. Figure 3.53 show the stacked wire bond die assembled for this paper. Carrier 1 is mounted on a FR4 PCB using SAC305 solder of 250 μm diameter. Carrier 1 assembly is underfilled and cured at 165 °C for 3 h. Carrier 2 is over molded using the transfer molding process. Then Carrier 2 is assembled on the Carrier 1 and underfilled. Figure 3.54 shows the images of the double stacked TSV interposers. We prepared samples having Carrier 2 with and without overmold for reliability assessment.

3.8.6 Module Reliability Assessment The double stacked TSV interposers module is assembled onto a two-layer PCB. The PCB design is based on JESD22-B111 in terms of package layout, metal traces, and pad opening design. Separate daisy chain for the three chip interconnections, Carrier 1 to PCB and Carrier 1 to Carrier 2 has been designed. The 3 double stacked TSV interposers module was tested for drop and thermal cycle reliability test condition. Preliminary drop test of the double stacked TSV interposers module without underfill showed complete detachment of the carrier from the PCB. Samples with underfill and overmold passed the 30 drops at 1500 G, 0.5 ms pulse duration. The drop test setup and results are shown in Fig. 3.59. The reliability of the double stacked TSV interposers module has been assessed for thermal cycle reliability conditions (− 40 °C to 125 °C, ramp 15 C/min, dwell 15 min). Figure 3.60 shows the cross section of solder and TSV of Carrier 1 and Carrier 2. Electrical continuity of the TSV and solder joint was monitored by separate daisy chains. The daisy chain resistance was monitored every 250 cycles. The solder interconnects and TSV joints showed no crack or detachment at time zero. However some of TSV chains showed open, when we measured the resistance after 500 cycles. The failed samples were cross-sectioned and failure analysis was performed. The failed samples show detachment of RDL/UBM metal layer form the copper via as shown in Fig. 3.61. During the carrier fabrication, the 1 μm thick SiO2 layer was used as the dielectric layer after the via exposure and the contact opening on the via was patterned. Then the barrier layer of 1 KA Ti and the seed layer of 2 KA Cu were sputtered for copper RDL formation. Poor adhesion of the sputtered metal layers on the TSV and stress due to thermal expansion of TSV are potential cause for the above failure. Chip 1 and chip 2 are assembled with the carrier using solder. The solder height is ∼50 μm, which helps to reduce the stack height. The carrier and chip are silicon,

Acceleration (G). Strain 680 x log R

3.8 Heterogeneous Integration with Stacked TSV Interposers

191

2000 1500 1000 500 0 -500 -1000 -1500 -2000 0

1

2

3

4

5

6

Time (ms) Fig. 3.59 Drop test setup and results

Fig. 3.60 Cross section of solder and TSV

Fig. 3.61 SEM micro graph failed sample for TC test

7

8

9

10

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Table 3.3 Chip solder interconnect thermal cycling results Daisy chain resistance (Ω) Time 0

500 cycles

1000 cycles

2000 cycles

Chip 1

24.3

24.3

24.3

34.3

Chip 2

17.3

18

18.9

20.5

therefore no thermal mismatch between them. Both the chips showed good interconnect reliability, no failure in solder interconnection was observed even after 2000 TC cycles. The chip 1 and 2 solder joint reliability is measured by electrical continuity of the daisy chain and electrical resistances are given Table 3.2.

3.8.7 Summary and Recommendations Some important results and recommendations are summarized as follows • A double stacked passive TSV-interposer module platform technology using silicon carrier technology has been developed and demonstrated for chiplet design and heterogeneous integration packaging applications. Silicon carrier (substrate) with TSV interconnection is developed for chip attachment and embedded passives integrations. • The module thermomechanical and reliability performances have been reported. Chip interconnection methods, such as flip-chip, wirebond, and gold stud bump have been evaluated and interconnections reliability is reported. • A tapered via structure has been designed and void free filling has been achieved using damascene pulse-reverse plating. • Silicon carrier fabrication process based on the via-first approach is established and developed 200 μm thick carrier with TSV for 3D module assembly. • Thin wafer handling technique using spin-on temporary adhesive is evaluated and found suitable for the silicon carrier fabrication.

3.9 Multiple System and Heterogeneous Integration with TSV Interposers 3.9.1 The Structure Figure 3.62 schematically shows a cross section of the test vehicle under consideration [73, 74, 89, 90]. It can be seen that the interposer (with 15 μm vias) supports four electrical memory chips (with 10 μm vias) stacked, one thermal chip, and one mechanical chip. It is over molded for pick-and-place purpose as well as protecting

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

193

Not-to-scale TSV is optional

TSV: 10μm

Electrical

Micro bumps

Stress sensor Mechanical

100μm

TSV:15μm

TSV/RDL/IPD Interposer

100μm

RDL RDL

`

Ordinary bumps

80μm

1mm

50μm IPD

TSV:10μm

Thermal TSV:15μm

TSV:15μm

`

Organic substrate

I/O:400 ball array, pitch:450µm Solder balls

350μm

1.2mm

PCB

I/O:400 ball array, pitch:1mm

Fig. 3.62 ITRI Multiple system and heterogeneous integration test vehicle

the chips from harsh environments. There are RDLs (redistribution layers) on both top and bottom sides of the interposer. Also, stress sensors are implanted on the top side and IPDs (integrated passive devices) are fabricated through the thickness (100 μm) of the interposer (12.3 mm × 12.2 mm). The top-side (left-hand side) and bottom-side (right-hand side) of the interposer are shown in Fig. 3.63. It can be seen that the interposer dimensions are 12.3 mm × 12.2 mm × 100 μm and the areas of stress sensors, thermal measurement, and daisy chain for electrical and mechanical measurements are highlighted. Basically, the memory-chip stacking for electrical measurement is located on the right-hand side and the thermal and mechanical chips are located on the left hand side. There is a chip site at the bottom-side of the interposer which is meant for the process development of 2-side C2W bonding. Figure 3.64 shows the layout of the thermal/mechanical (left-hand side) and the electrical test chips (right-hand side). As mentioned early there are electrical, thermal, and mechanical chips in this study. Actually, the mechanical and thermal are the same chip but used for different purposes. The TSV diameter of all the electrical chips is 10 μm and the mechanical/thermal is 15 μm. The microbump size for all the chip is ~ 10 μm. The electrical test chip is used for providing the electrical signal so we can: (a) analysis the signal transmission performance of the chip, interposer, BT-substrate and PCB; (b) analysis the signal transmission performance among the SiPs; (c) analysis the interconnect performance of 3D IC SiP under assembly processes; (d) analysis the single MOS-IPD and combine IPD and electrical test chip performance; and (e) verify the electrical empirical equations and simulation results with the measurement results.

194

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.63 Interposer layouts (left = topside and right = see-through) to support the thermal, mechanical, and 4-stacked electrical (memory) chips

Daisy chain

Dummy metal

Connect to electrical chip

Heater and Thermal sensor

TSV

TSV

Heater and Thermal sensor

Stress sensor

(a)

(b)

Fig. 3.64 Thermal/mechanical (a) and electrical (b) test chips

The thermal test chip is used for providing the heat source so we can: (a) measure the junction and case temperatures and consequently determine the thermal resistance (Θjc); (b) measure the junction and ambient temperatures and determine the thermal resistance (Θja); and (c) verify the thermal empirical equations and simulation results with the measurement results. The mechanical test chip is used to: (a) measure the stress and warpage in the chips and interposer; (b) determine the microbump, ordinary bump, and ball reliability; and (c) verify the empirical equations and simulation results with the measurement results.

3.9 Multiple System and Heterogeneous Integration with TSV Interposers Fig. 3.65 Interposer with Thermal, mechanical and 4-steaked electrical (memory) chips

195

IPD

Mechanical

Electrical

Thermal IPD

Test Pad

Molding Region

Figure 3.65 shows the top-view of the thermal, mechanical, and electrical test chips on the interposer. Their locations on the interposer and some of the test pads are clearly shown. Also, the molding compound region for pick-and-place and chip protection is shown. This test vehicle can be degenerated to the case of: (a) wide I/O DRAM if there are not mechanical and thermal chips and the interposer is an ASIC chip; (b) wide I/O memory if there is not the memory-chip stacking nor the TSVs in the mechanical/thermal chips and the interposer is either an ASIC or microprocessor; and (c) wide I/O interface if there is not the memory-chip stacking and there is not any TSV in the thermal/mechanical chips (which is like Xilinx/TSMC’s FPGA wide I/O interface).

3.9.2 TSV Etching and CMP Table 3.4 shows the process procedures and the corresponding process parameters of the TSV /RDL interposer. The interposer (100 μm - thick) is fabricated on a 300mm P-type Si (100) substrate. (A) TSV Etching [75]: Most TSVs are formed by deep reactive ion etch (DRIE) and the etch rate is the most important factor for obtaining high-quality TSVs such as smooth sidewall, i.e., minimum sidewall scallop. Usually, SF6 will be used in etch cycle (including the removal of the passivation) whereas C4 F8 in passivation cycle. If etch cycle time is too long and passivation cycle time is

196

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Table 3.4 Processed and parameters for making the TSV/RDL interposer

Process stage

Process parameters

Inter-layer dielectrics (ILD) TSV

• TSV diameter = 15 μm • TSV depth = 100 μm • TSV SiO2 liner (SACVD) = 1 μm @ top • Ta barrier = 0.1 μm @ top

Top RDL

• Cu damascene • Line-width = 30 μm • Metal thickness = 1 μm • Ti barrier = 0.1 μm

Top passivation opening

• Opening size = 20 μm

Top UBM

• UBM size = 25 μm • Cu thickness = 5 μm • NiPdAu = 2 μm

Temporary bonding to Si carrier

• Glue thickness = 30 μm

Backside thinning

• Grinding + CMP

Si recess and TSV backside reveal

• Dry etching

Backside isolation

• PECVD • Temperature < 200 °C • Thickness = 1 μm

CMP for TSV Cu reveal

Backside isolation remained > 0.8 μm on the field area

Bottom RDL

• Line-width = 30 μm • Metal thickness = 1.5 μm • Ti Barrier = 0.1 μm

Bottom passivation opening

• Opening size = 20 μm

Bottom UBM

• UBM size = 25 μm • Cu thickness = 5 μm • NiPdAu = 2 μm

too short, then the via will not be straight and sidewall will be rough (large scallops), which will affect the consequent processes and quality of the TSVs. On the other hand, if the passivation cycle time is too long and the etch cycle time is too short, then it slows down the throughputs. Thus, the etch rate should be balanced and optimized. A DoE (design of experiments) has been executed to determine the optimal etch rate of TSVs in 300 mm wafer [75]. It is found that [75]: (1) the higher the etch rates the larger the scallops; (2) the larger the TSV diameter the deeper

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

197

the TSV depth; (3) the larger the etch cycles the deeper the TSV depth; (4) the higher the TSV etch rate the larger the TSV diameter; (5) the larger the etch cycles the smaller the etch rate; (6) the larger the TSV diameter the larger the maximum scallop; and (7) the larger the etch cycles the smaller the scallop. Figure 3.66 shows a typical result for 10 μm-diameter TSVs, the effect of etch rate on the scallop is visible and the scallop is ranging from 107 to 278 nm (for etch rate ranging from 3.5 to 5.8 μm/min). More TSV etching data and process guidelines can be found in [75]. (B) TSV CMP [92]: Recently, low resistivity of Cu by damascene technique has been used as the TSV conducting material. However, due to long Cu plating times for deep TSVs, the Cu plating residues (overburden) on top of the wafer must be removed by CMP. Slurry is the key enabling material for CMP and its removal profiles (flow rate, down force, and head/platen speed) are the key factors to be optimized in order to achieve high removal rate, better uniformity, and less stress. In [92], the Cu dishing performance of Cu CMP for removing thick Cu plating overburden due to Cu plating for deep TSVs in a 300 mm wafer has been optimized. In order to obtain a minimum Cu dishing on the TSV region, a proper selection of

Fig. 3.66 10 μm-diameter TSVs on 300 mm wafer. Top: 145 μm depth with 235 nm scallops; and Bottom: 105 μm depth with 99 nm scallops

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Platen1

Platen2

Dishing @ 10μm via

Test 1

Slurry 1

3psi

Slurry 1

1psi

~ 12000≈

Test 2

Slurry 1

3psi

Slurry 2

3psi

< 250≈

Test 1

Test 2

Fig. 3.67 Dishing at the 10 μm-diameter TSV with Test 1 (top) and Test 2 (bottom) processes

Cu slurries in different polishing steps has been achieved for the current two-step Cu CMP. At the first step, the bulk of Cu is removed with the slurry of high Cu removal rate. At the second step, the Cu surface is then planarized with the slurry of high Cu passivation capability. Typical results are shown in Fig. 3.67. It can be seen that with the proposed method the dishing has been improved drastically (from 1.2 μm to 300 Å). More experimental data for CMP on RDLs and Cu exposure and CMP process guidelines can be found in [92].

3.9.3 Thermal Measurement In general TSVs enhance the thermal performance of 3D IC integration, since the thermal conductivity of copper is 2.6 times of silicon. However, this advantage can be reduced substantially if there are defects such as voids/seams in the copper filled TSVs, which can be measured by conventional thermal measurement techniques. However, the conventional measurements can only be done after wafer thinning, which could lead to a higher manufacturing cost if the thermal performances of the TSVs don’t meet the specification. In order to resolve the issue, a simple test method which employs a unique test-key embedded in a TSV wafer has been proposed [69, 70] to evaluate TSVs’ thermal performance before wafer thinning, i.e., blind TSV and the test set-up is shown in Fig. 3.68. The measured results show that the test-key can produce a ΔR that is large enough to measure and are in good agreement with the simulation results. For test keys design guidelines, measurement methods, and judgments of G or NG TSVs, refer to [69, 70] for more details.

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

(c) Schematic of the test platform

199

(d) Actual setup of the test platform

Fig. 3.68 a Target test-key pattern; b Reference test-key pattern; c Schematic of the test platform; and d Actual setup of the test platform

3.9.4 Thin-Wafer Handling Handling thin wafers with 50 μm or less through all the semiconductor fabrication and packaging assembly processes is very difficult. Usually, the wafer is temporarily bonded on a supporting wafer with an adhesive and thinned down to the required thickness to expose the Cu stud of the TSVs. Then the composite wafers go through all the semiconductor fabrication processes, such as passivation and metallization, and the packaging processes, such as UBM (under bump metallurgy), solder bumping and dicing. After all these are done, removing the thin wafer from the supporting wafer poses another big challenge. Adhesive is the key enabling material for thin-wafer handling and how to select adhesive materials for temporary bonding and de-bonding of thin-wafer handling is the focus of [80]. The requirements are: (1) after temporary bonding the adhesive materials should be able to withstand process environment and thermal budget; (2) during de-bonding the adhesive materials should be able to dissolve and clean-up easily; and (3) after de-bonding there is not any residual and chipping on the thin wafer. It is found in [80] that during all the processes, only the PECVD (plasma enhanced chemical vapor deposition) and sputtering conducted in vacuum chamber are the most critical factors in selecting adhesives. Some typical results are shown in

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Just after de-bond

After flue cleaning

(a)

(b)

50μm

25μm

(c)

(d)

Fig. 3.69 Results after de-bonding of thin device wafer: a just after de-bond and b after flue cleaning. Results of blanket thin wafer de-bond with various wafer thickness: c 50 μm and d 25 μm

Fig. 3.69. For more data and characterization results on chemical resistance, backside micro-bumping, wafers with ordinary solder bumps, and wafers with TSVs and microbumps, please see [80].

3.9.5 Microbumping, C2W Assembly, and Reliability Assessment (A) “Copper Pumping” in 3D Chip Stacking [201]: Due to the local thermal expansion mismatch between the silicon chip (2.62 × 10–6 /o C) and the TSV filled copper (17 × 10–6 /o C), there are very high stresses acting at the TSV corner, which are the driving force for “copper pumping” [185]. A 3D finite element model (Fig. 3.70) has been established in [201] for nonlinear stress simulations of the TSV structure subjected to thermal cycling. The chip dimensions are 4.8 mm × 4.0 mm × 50 μm. TSV diameter is 10 μm and micro solder joint diameter is 20 μm. The thickness of the top copper pad, Cu3 Sn and IMC (intermetallic compounds), and bottom copper pad are 4, 2, and 4 μm, respectively. Polyimide (PI) is used as the passivation layer on the substrate and its thickness is 4 μm. Figure 3.70 shows the von Mises stress contours acting at the TSV and micro solder joints at 125 °C [201]. Since the CTE (coefficient of thermal expansion) of copper is a few times larger than that of silicon, the copper tends

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

201

Fig. 3.70 Nonlinear simulation of a chip bonded on the substrate and the results (von Mises stress) of TSVs and micro solder joints at 125 °C

to expand more than the silicon. This CTE mismatch creates a von Mises stress (135.5 MPa) at the corner of the TSV. If the thin films above the copper TSV are not strong enough, then these films will be peeled or cracked easily. This failure mode is known as “copper pumping” [185]. The stress at the micro solder joint is also very high, especially between the IMC and the bottom copper (110– 123 MPa). These stresses are due to the thermal expansion mismatch between the silicon substrate and the PI passivation. For thermal cycling (− 55 ↔ 125 °C) test results and SEM image of cross-section of failed samples (micro solder joint cracked between the IMC and the bottom copper), please refer to [201]. (B) Solder Mircobumping and Assembly [202]: The Cu/Sn (3 μm of Cu and 3 μm of Sn) lead-free solder microbumps on 10 μm pads with 20 μm pitch have been designed and fabricated in [202]. The chip size is 5 mm × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbumps are fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness (Ti = 50 nm/Cu = 120 nm) is designed and applied to minimize the undercut (< 1 μm) due to wet etching but still achieved good plating uniformity; (bump height + RDL) variation < 10%. Figure 3.71 shows the solder microbumping process flow and a typical cross section of the microbumps. In [202], the Cu-Sn lead-free solder micro bumped chip has been bonded on a Si wafer (chip-to-wafer or C2W bonding). Also, the micro-gap between the bonded chips is filled with a special (very small filler size) underfill. The bonding and filling integrity have been evaluated by shear test, open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs have been evaluated by thermal cycling test (− 55 ↔ 125 °C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5 μm pads on 10 μm pitch) lead-free solder microbumping has been explored. For detailed information on microbumps,

202

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.71 Process flow of Solder microbumping with RDLs and SEM image of CuSn micro solder bumps on 10 μm pads with 20 μm pitch

assemblies by natural reflow and thermal compression bonding (TCB) methods and reliability assessments please refer to [202]. (C) Solder Fluxless Microbumped chip to Wafer Bonging [203]: A fluxless chip-towafer (C2W) bonding process by using the plasma cleaning to replace the use of flux has been reported in [203]. It has been found that with the optimized plasma-process (75%Ar-25%H2 gas flow ratio) and bonding parameters (in Step 1, for connecting the solder joints, the temperature is ranging from 250 to 300 °C for 15 s and in Step 2, for cooling, the temperature is set at 50 °C for 10 s), high-yield (90%) lead-free micro solder joints can be achieved (Fig. 3.72). Also, it has been found that the effect of bonding temperature on the shear strength of micro solder joints is: the higher the bonding temperature the higher the shear strength of the micro solder joints. However, there is no relationship between the bonding temperature and C2W yield. The C2W yield strongly depends on the solder microbumping quality of the wafers: the more uniform-thickness of the Sn layer the better the C2W yield. Finally, it has been found that, for 3D IC chip-stacking module, the most desired features of underfills are: (1) smaller filler size, (2) lower viscosity, and (3) the filler content should be less than 60%. For more information on reliability assessment results, please refer to [203]. (D) 3D Chip Stacking with Wafer Applied Underfill (WAUF) [204]: It is well-known that, for 3D IC integration, the micro-bump interconnections are very small. Thus, it is hard to apply flux during the bonding process due to the difficulty in cleaning the remained flux residue. A novel assembly process using WAUF material as the protection and support for micro-bump interconnections in 3D IC silicon chips or interposers has been proposed in [200]. Such a process only

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

203

Fig. 3.72 Fluxless automatic C2W bonder and a full loaded (bonded) wafer with 91 chips. The x-section of a typical good micro solder joint

requires a high accuracy bonding technique and well controlled TCB parameters to achieve a compact and reliable 3D packaging structure (Fig. 3.16). No additional dispenser for capillary underfill dispensing is needed and, consequently, lowers overall manufacturing costs. The characteristics of WAUF are: Tg (by TMA) = 74 °C; CTE = 49 × 10–6 /°C and 284 × 10–6 /o C; Filler content = 30%; Filler size = nano SiO2 ; and Modulus = 1.7 GPa. In the WAUF process, flux is already the intrinsic content of the WAUF material and, therefore, no cleaning approach is necessary to achieve a fully compact structure. Moreover, the bonding temperature for the solder joints can also be lowered to 240 °C, which is more beneficial than conventional lead-free solders which need more than 265 °C to achieve soldering without flux. The concept proposed in [204] is a 3-stage bonding process design for material application (Fig. 3.73). For reliability assessment and failure modes, please refer to [204] for more details.

3.9.6 Failure Mechanism of 20 µm Pitch Micro Solder Joints The failure mechanisms of micro solder joints on 10 μm pads with 20 μm pitch for 3D IC integration SiP assembled by TCB method has been investigated in [205], where two underfills (A and B) have been studied. It was found that with both underfills,

204

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Completely sealed by WAUF

Ni3Sn4 IMC at interfaces

Fig. 3.73 Bonding process flow of chip stacking with a wafer-applied underfill material (WAUF) and the X-section images of the micro solder joints (top) completely sealed by WAUF and (bottom) Ni3 Sn4 IMC at interfaces

the characteristic life (at 63.2% failures), as shown in Fig. 3.74, of the microjoints is larger than 3700 thermal cycles (− 55 to 125 °C) even the bonding time is as short as 15 s. Also, with limit amount of thermal cycling data, the mean life of microjoints with Underfill A is better than that with Underfill B with only 51% confidence. Basically, both underfulls behave the same. The failure mechanism of micro solder joints has been found to be attributed to the formation of Sn depletion zone close to the interface between the bulk-solder and Ni-layer of the top chip. The growth of the Ni3 Sn4 is controlled by the reaction of Sn and Ni at the interface between Ni-layer and Ni3 Sn4 . This growth has been found to be more rapid at the top chip, which speeds up the formation of Sn depletion zone close to the interface and induces the fracture during thermal cycling test (Fig. 3.74). Please refer to [205] for more technical details.

3.9.7 Electromigration in Solder Micro Joints As mentioned earlier, solder microbumps are one of the important enabling technologies for 3D IC integrations. The ordinary solder bumps (~ 100 μm) are too big for 3D IC SiP applications, which require much smaller solder bumps (< 20 μm). For a given current of 0.05A, the current density of a 20 μm solder bump could reach

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

205

90

Underfill B 50

Underfill A

Percent failed F(x)

Underfill A

10

Sample size = 72 No. of failures = 27 Weibull slope = 1.15 Characteristic life = 4980 cycles

Underfill B Sample size = 45 No. of failures = 18 Weibull slope = 1.38 Characteristic life = 3739 cycles

Underfill A 5

The survival micro solder joint sealed by Underfill B after thermal cycling test

Underfill B b1=1.15, h1=4980, r=0.95 b2=1.38, h2=3739, r=0.93 1 0.5 200

1000

Cycles-to-failure

6000

Failed sample sealed by Underfill B after thermal cycling test

Fig. 3.74 Life distributions of micro solder joints with Underfill A and Underfill B (− 55 °C ↔ 125 °C and failure criterion = infinitive resistance change). The X-section image of the survival micro solder joint sealed by Underfill B after thermal cycling test (top) and failed sample sealed by Underfill B after thermal cycling test (bottom)

a value in the order of 104 A/cm2 . Thus, the effect of current crowding induced by EM is expected to become more prominent. Also, during EM, a large number of Kirkendall voids may cause conspicuous microstructure degradation. Furthermore, the IMC can play a very important role in EM behavior of micro solder joints due to the small volume of solder in the joints. The EM investigation of 30 μm pitch chip-to-chip (C2C) micro solder joints has been carried out in [206]. Current density distributions in the solder micro joints for various applied current have been determined by finite element simulation (Fig. 3.75). Two different types of micro solder joints have been constructed by thermal annealing process. It has been found that the annealed micro solder joints have stable and higher EM resistance than the non-annealing ones. During EM test, it has been found that the resistance of type I micro solder joints (with current density of more than 104 A/cm2 ) increased rapidly and then failed in 600 h (Fig. 3.75). On the other hand, Type II micro solder joints have been found to have strong EM resistivity and survived longer than type I joints. The EM failures have been occurred in Al trace and UBM, which implied there is high current density in the Al trace of the micro bump interconnection. These failures have been caused by joule heating induced from current crowding. High current density applied in Al trace could be one of the serious reliability issues in micro bump interconnection. It has been found that the situation of Ni layer induced failure is following the direction of electron flow in daisy chain. This phase transformation induced failure is another reliability problem in fine pitch micro bump interconnection. For more test data and results, please refer to [206].

206

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Direction of current flow

Cu (5um) Ni (2um) Ni3Sn4 (5um) Voltage: 0

Ni (2um)

3D finite element Model

Current stress

Ti (1k) Al (8k)

Cu (5um)

Boundary conditions

void eNi3Sn4 void void

Crack of Al trace

void

Fig. 3.75 3D finite element model and boundary conditions for the determination of current density distribution in the micro solder joints. Failure modes of Type I solder micro joint under current stress of 0.3 A at 484 h

3.9.8 Final Structure Figure 3.76 shows the assembled test vehicle. Figures 3.77 and 3.78 show the SEM image of the cross sections and x-ray image, respectively. Figure 3.79 shows the SEM and x-ray images of the stacked memory chips. It can be seen that the structure is properly constructed.

3.9.9 Leakage Current Issue Wafer thinning starts with the temporary bonding with a Si carrier at the front-side (glue thickness = 30 μm). CMP is used for the Cu revealing. Unfortunately, the measured leakage currents, as shown in Table 3.5, are too large compared to those with blind vias [204]. SEM images of cross sections reveal that there are at least two different shorts to cause the very large current: (a) one is between the bulk Cu pad and the Si substrate as shown in Figs. 3.80 and 3.81, and (2) the other is between the bulk Cu at the TSV edge and the Si substrate as shown in Figs. 3.82 and 3.83. In order to avoid the leakage current issue, the wafer is thinned by grinding and chemical–mechanical polishing (CMP) to the point with a 5 μm-distance to the TSV bottom (i.e. the remained Si substrate is 105 μm). The backside Si surface is then

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

Mechanical Chip

207

4-chip stacked

Thermal chip

TSV interposer

BT-substrate Fig. 3.76 ITRI test vehicle sample

Microbump

TSV Interposer

TSV

Thermal chip

Organic substrate

Solder ball Ordinary solder bump PCB

Fig. 3.77 SEM image of the cross section of the ITRI test vehicle

208

3 Multiple System and Heterogeneous Integration with TSV-Interposers

TSV Interposer

Thermal chip TSV

Fig. 3.78 X-ray images of the ITRI test vehicle

dry-etched to make the TSV revealed and protruded, as shown in Fig. 3.22. After the backside isolation (process temperature < 200 °C), CMP is utilized to remove the isolation layers on the protruded TSV and expose the Cu surface of TSV backside. The leakage current measurement results of the Cu reveal by the new method are shown in Fig. 3.84. It can be seen that their magnitudes are in the pA ball park which indicate that there is no leakage current problem anymore with the new method. Bottom RDL is then formed by Cu plating after lithography patterning. Bottom UBM (25 μm in diameter; the same process as the top UBM) is formed with a passivation opening of 20 μm.

3.9.10 Thermal Simulation and Measurement of the Structure When the thermal chip on the interposer is heated, the chip’s thermal resistance (that is from junction to ambient) can be determined from the temperature and generated power. The 3D SiP is attached to a JEDEC standard thermal test printed circuit board (PCB). Figure 3.85 shows the heater layout of the thermal test chip, which sizes are

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

209

TSV (10μm)

3rd layer 2nd layer

(a) 1st layer

substrate

1st

2nd

3rd

4th

RDL substrate

(b)

Fig. 3.79 a 3-chip stacking on a Si substrate. b 4-chip stacking on a Si substrate

Table 3.5 Leakage current of TSV at different temperatures and voltages 1V

2V

3V

4V

5V

6V

7V

8V

9V

10 V

23.6 °C

0.76

2.82

6.56

11.6

17.6

24.6

32.3

41

50.4

60.7

36.6 °C

0.66

2.52

6.12

11.2

17.3

24.2

32

40.7

50.3

60.7

61 °C

0.63

2.75

6.4

11.5

17.5

24.3

31.7

39.9

48.8

58.4

108 °C

1.21

3.14

6.21

10.6

16.4

23.4

34.5

40.2

49.7

59.6

132 °C

1.6

3.67

6.67

10.8

16.4

23.6

31.7

40.5

50

59.8

Unit μA

4.0 mm in width and in length; 100 μm in thickness. The folded heater is deposited by electroplating and its material is pure copper. To measure thermal resistance of the SiP, the test board is placed in a temperaturecontrolled chamber. In the beginning of the test, the chip heater’s TCR (temperature coefficient of resistivity) correlation, between its electrical resistance and temperature, is measured first. Then, a constant current is applied to the SiP and record its

210

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Case One: Short between the bulk Cu pad and Si substrate

TSV (Cu)

TSV (Cu) TSV liner and backside passivation dielectrics (SiN + SiO) is not connected. (See Fig. 3.81 for zoom-in)

BLD (Cu)

BLD (Cu)

Fig. 3.80 Short between the bulk Cu pad and Si substrate

TSV (Cu)

Si

TSV (Cu)

BLD (Cu)

Si

BLD (Cu) TSV liner and backside passivation dielectrics (SiN + SiO) is not connected. Ti-barrier is directly short to Si substrate

Case One: Short between the bulk Cu pad and Si substrate Fig. 3.81 Short between the bulk Cu pad and Si substrate

stable electrical resistance and generated power that related to the measured voltage. Finally, using TCR correlation, the heater temperature can be calculated and the thermal resistance (Rja ) from heater junction to ambient can be determined. The ambient temperature is controlled at about 25.6 °C.

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

211

Case Two: Short between the bulk Cu at the TSV edge and Si substrate

TSV (Cu)

BLD (Cu)

TSV (Cu)

Trace Cu at TSV edge after Si CMP (for TSVs protrusion) to Sisubstrate (Fig.83 for zoom-in)

BLD (Sn)

Fig. 3.82 Short between the bulk Cu at the TSV edge and Si

Case Two: Short between the bulk Cu at the TSV edge and Si substrate

Si

TSV (Cu)

BLD (Cu)

TSV (Cu)

Trace Cu at TSV edge after Si CMP (for TSVs protrusion) to Sisubstrate (Fig.83 for zoom-in)

Si

BLD (Cu)

Fig. 3.83 Short between the bulk Cu at the TSV edge and Si

During the test, we found the chip has an electrical problem; the current leakage occurs in the test chip (which is before the improvement of Cu TSV revealing). Due to metallic materials, the heater should have a positive linear TCR curve. Once the current leakage effect exists in a metallic heater, the joule heat is not only generated by the heater but also by other elements. The most probable other heating element is the silicon and silicon is a semiconductor material and has a negative as well as non-linear TCR curve. Therefore, a metallic heater having current leakage effect

212

3 Multiple System and Heterogeneous Integration with TSV-Interposers -13

TSV leakage (A)

1.5x10

Probing between two TSVs Site 1 Site 2 -13

1.0x10

-14

5.0x10

0.0 0

2

4

6

8

10

TSV Bias (V) Fig. 3.84 Leakage current measurement of the improved Cu TSV reveal

Fig. 3.85 Thermal test chip with dimensions (4-mm square and 100 μm in thickness)

would result in a bended TCR curve. The curve is linear or not could be identified very easily by fitting the data. Figure 3.86 shows the un-improved chip’s TCR curve in dotted blue line which is not linear and in a slightly bending trend. Simulations are used to verify the measurement results. The simulation analyses use equivalent models that have been described in previous literatures [70, 87]. The embedded TSVs have the dimensions of 15 μm in diameter, 0.5 μm in passivation thickness and 50 μm in pitch. All the boundary conditions of the simulation are as same as those of the measurement. Figure 3.87 shows the simulation model and its temperature distribution. The measured chip’s thermal resistance depended on various joule heat generation are shown in Fig. 3.88. Also, Fig. 3.88 compares the measurement data with the

3.9 Multiple System and Heterogeneous Integration with TSV Interposers

213

Heater Electrical Resistance (Ohm)

19

18.5

18

17.5 17

Linear fitting curve

16.5

16 30

40

50 60 Temperature (oC)

70

80

Fig. 3.86 The thermal chip’s TCR correlation

simulation results. For the results from both measurement and simulation, when a higher joule heat of the chip is generated, the chip’s thermal resistance becomes smaller. This phenomenon is reasonable because a higher heat generation can cause a higher chip’s temperature; a higher temperature can result in a stronger natural convection air flow and thus yield a lower thermal resistance of the chip from its junction to ambient. It can also be seen that the measurement data are lower than those of the simulation (about 8–9 °C/W in thermal resistance, which is considered to be caused by current leakage effect.) Based on the same heater and joule heat generation, the chip having current leakage should have a larger heating area and thus a lower power density, which leads to a lower chip’s junction temperature.

3.9.11 Summary and Recommendations • A multiple system and heterogeneous integration with TSV-interposer test vehicle has been designed and developed. • The reliability concerns (failure modes) of Cu TSV revealing have been presented and discussed. • The assembly processes of the thermal, mechanical, and electrical test chips onto the interposer; of the interposer module to the BT-substrate; and of the package module to the PCB have been presented. SEM image and x-ray images have also been provided for the assembly. • Some key enabling technologies such as TSV etching and CMP, thin-wafer handling, thermal management, solder microbumping, assembly, and reliability assessment have been developed through the multiple system and heterogeneous integration with TSV-interposer test vehicle.

214

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.87 Simulation model and temperature distribution

• This test vehicle can be degenerated to the case of (a) wide I/O DRAM, (b) wide I/O memory, and (c) wide I/O interface. Thus, the enabling technologies developed with this test vehicle can have very broad applications.

3.10 Multiple System and Heterogeneous Integration with Chips on Both-Side of TSV Interposers In general, 2.5D IC integration consists of a piece of device-less silicon with throughsilicon vias (TSVs), redistribution layers (RDLs), and/or integrated passive devices supporting one or more high-performance, high-density, fine-pitch chips without TSVs, and HBMs (high bandwidth memories). This is schematically shown in the

3.10 Multiple System and Heterogeneous Integration with Chips …

215

50

Thermal Resistance Rja (oC/W)

45

Simulation data

40

35

30 Measurement data 25

20 0

0.5

1

1.5

2

2.5

3

Heat Generation (W)

Fig. 3.88 Comparison between the measurement data and the simulation results

top drawing of Fig. 3.89. It can be observed that the TSV/RDL interposer is supporting Chip-1 and Chip-2 side-by-side on its top surface. Another design is shown in the bottom drawing of Fig. 3.89. It can be observed that the interposer is supporting these two chips on its top and bottom sides. In this case, the size of the interposer can be smaller (or more chips can be placed on the same size of interposer), and the electrical performance can be better because the chip-to-chip interconnects are face-to-face instead of side-to-side.

3.10.1 The Structure Figure 3.90 shows the schematics of the interposer with chips on it both sides under consideration [64, 110, 111]. Figure 3.91 shows the layout of the interposer. It can be seen that: (a) on the top-side (Left), there are pads for the top 2 chips and (b) on the bottom-side (Right), there are pads for the bottom chip and the organic package substrate. The size of the package substrate is 35 mm × 35 mm × 970 μm. Underfills are used between the chips and interposer and the interposer and package substrate. The TSVs’ diameter is 10 μm and on 150 μm pitch. The diameter of the solder bumps between the chips and interposer and between the interposer and package substrate is 90 μm and on 125 μm pitch. The diameter of the solder balls between the package substrate and the PCB is 600 μm and on 1000 μm pitch. Table 3.6 summarizes the geometry of the 3D IC integration with a TSV interposer supporting chips on its both sides [64, 110, 111].

216

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Chip-1

Micro Bump

Chip-2

TSV/RDL Interposer

TSV

Advantages: Micro Bump Chip-1

TSV/RDL Interposer

TSV

Chip-2

Smaller size of interposer (or same size of interposer supporting more chips) Better electrical performance (face-toface interconnects instead of side-by-side) 3D IC integration

Fig. 3.89 2.5D IC integration with a passive interposer

3.10.2 Thermal Analysis—Boundary Conditions Boundary conditions for the thermal analyses of the 3D IC integration module are shown schematically in Fig. 3.92; the thermal loading conditions are included in Tables 3.6 and 3.7 along with the boundary conditions. As for the part’s geometries, the dimensions are listed in Tables 3.6 and 3.7. It can be seen that: (a) the power dissipation of each chip soldered on the interposer is 5 W; (b) the thermal resistance, Rca, to imitate the cooling capability of a suppositional heat sink that attached on the heat spreader is from 0.1 to 4.0 °C/W; and (c) the heat transfer coefficient (h) of both sides of the PCB is 20 W/m2 °C.

3.10.3 Thermal Analysis—TSV Equivalent Model The equivalent Eqs. (2.19) and (2.20) in Chap. 2 of [184] can be used for the design and analysis of 2.5D/3D IC integration by establishing an equivalent model. This equivalent model is used to replace the real detail TSV model for simplifying the thermal simulations. In the conversion, the arrays of TSV, solder bump, and solder ball can be replaced by many coupled equivalent zones with their equivalent thermal

3.10 Multiple System and Heterogeneous Integration with Chips …

217

Chip-2 Chip-2

Chip-1 Chip-1

Underfill TSV interposer Solder ball

Organic substrate

Chip-3 Chip-3

C4 bump

Package substrate

PCB

Fig. 3.90 Schematics of the interposer (with 2 chips on its topside) and one chip on its bottom-side) for 3D IC integration

conductivities (Fig. 3.93). Particularly, the SiO2 layer on interposer has to be retained in the equivalent model for accurateness. For example, a 2 × 2 TSV array with 10 μm in diameter, 0.2 μm in thickness of sidewall SiO2 , 100 μm in height (thickness) and 50 μm in pitch, could be converted to an equivalent zone with 100 μm × 100 μm in area and having 144.56 W/m K of kxy and 156.34 W/m K of kz .

3.10.4 Thermal Analysis—Solder Bump/Underfill Equivalent Model The equivalent thermal conductivities of solder bump and solder ball should be determined by thermal resistance parallel-series correlation. To be worth mentioning, because disconnection and large pitch, the equivalent thermal conductivity of a bump array that is with underfill material should approach to that of the underfill in the x–y direction. For the same reason, a solder ball array without underfill, its equivalent kxy should be very small and is nearly equal to zero. Figure 3.93 shows the model conversion rules and the calculated thermal conductivities of each equivalent zone.

218

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Pad layout for the top 2 chips on the top-side of the interposer.

(a)

Pad layout for the bottom chip and the organic package substrate of the interposer

(b)

Fig. 3.91 a Pad layout for the top 2 chips on the topside of the interposer. b Pad layout for the bottom chip and the organic package substrate of the interposer

3.10.5 Thermal Analysis—Results Figure 3.94 shows the top view temperature contours of each chip (applied boundary condition: Rca = 1.0 °C/W on heat spreader), and Fig. 3.95 shows the 3D temperature distribution of the 3D IC integration module. From these figures, it can be seen that the temperature distribution of chip#1 and chip#2 are rather non uniform, but that of chip#3 is not. The maximum temperature difference of chip#1 and chip#2 is about 4.7 °C (63.2–58.5 °C), and that of chip#3 is just about 0.4 °C (70.6–70.2 °C). Therefore, chip#1 and chip#2 have a more severe thermal issue about temperature non uniformity than that of chip#3; the issue can damage the chips’ quality and reliability performance. Also, from the same figures, it can be seen that a heat sink is necessary for cooling the 3D IC integration module, because chips #1 and #2 and chip#3 can reach to a very high temperatures, 410 and 417 °C, respectively, under a natural convection condition and without heat spreader attachment. The relationships between chip’s average temperature and the applied cooling capability (Rca ) to the heat spreader/sink are shown in Fig. 3.96. The figure can help us to select an appropriate heat sink that attached on the heat spreader. For instance, if the temperature specification of the chips is 100 °C, a heat sink with cooling capability, Rca , less than 3.7 °C/W is essential to cool the 3D IC integration module.

3.10 Multiple System and Heterogeneous Integration with Chips …

219

Table 3.6 Geometry of the 3D IC integration with a TSV interposer supporting chips on its both sides

Chip#l–3

Length (mm)

Width (mm)

Height (μm)

Diameter (μm)

Pitch (μm)

Note

6.5

3.8

850

–

–

The three chips are in the same sizes

Interposer

11.9

9.4

100

–

–

Organic substrate

35

35

970

–

–

Cavity

5.74

8.46

–

–

–

PCB

60

60

1600

–

–

Heat spreader

3.35

3.35

500

–

–

C4 bump

–

–

–

90

125

Between chip and interposer

C4 bump

–

–

–

75

125

Between interposer and organic substrate

Solder ball

–

–

–

600

1000

Between organic substrate and PCB

TSV

–

–

–

10

150

Regular distribution in the interposer

Fig. 3.92 Schematic of the thermal analysis model and the boundary conditions

The cavity is in the organic substrate

220

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Table 3.7 Boundary conditions and thermal loading conditions Thermal loading

5W per chip (#1, #2, #3)

Boundary conditions

The thermal resistance (Rca) of a heat sink: tunable for parameter study The convection coefficient (h): 20 W/m2 K on PCB both sides Other surfaces are regarded as adiabatic

Fig. 3.93 Model conversion rules and the calculated thermal conductivities of each equivalent zone

On the other hand, if the chips, temperatures must be under 60 °C, then we have to choose a very powerful heat sink that has a Rca less than 0.3 °C/W. From Fig. 3.96, it can be seen a severe thermal issue for the 3D IC integration structure. The issue is the chip planted on the bottom side of the interposer is always hotter than the chips planted on the interposer topside. This is because the chips on interposer topside can be directly contact with the main cooling mechanism— heat spreader and heat sink, but the chip on the interposer bottom side cannot. The difference of the chips’ average temperature is equal to 9.0 °C. The higher temperature of chip#3 is inevitable because the heat spreader plays a major role to dissipate the chips’ generated heat, and the temperatures of chip#1 and chip#2 barricade the heat dissipation from the chip#3 to the heat spreader. It is very hard to solve the severe issue without any structural change of the 3D IC integration module. To thicken the

3.10 Multiple System and Heterogeneous Integration with Chips …

221

With heat spreader (Rca=1.0 C/W) Top chips

Bottom chip

Top chips

Bottom chip

Without heat spreader (natural convection)

Fig. 3.94 Temperature distribution of (a1) chips #1 and #2 and (a2) chip #3 (Rcs = 1.0C/W); and (b1) Chips #1 and #2 and (b2) chip #3l (without heat spreader, natural convention). The four temperature bars are not in the same scale

heat spreader could reduce the chips’ temperatures, but the enhancement is limited. A useful and simple technique has been proposed in [70], which is to insert a metallic heat slug from the PCB side and to directly contact to the backside of chip#3. The inserted slug can effectively drain out the heat of chip#3 and also help to reduce the temperature of chip#1 and chip#2 noticeably.

3.10.6 Thermomechanical Analysis—Boundary Conditions For thermomechanical simulations, nonlinear finite element modeling and analysis are conducted to realize the thermal stress distributions of the structure. At the same time, the reliability estimation of solder joints in the architecture is examined. In order to realize the non-linear temperature and time dependent creep behavior of solder joints, the structure is simulated under a thermal cycling condition of − 25 to 125 °C for 5 cycles.

222

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Top 2 chips

With the top 2 chips and interposer removed

Fig. 3.95 The temperature contour of the integration of organic substrate, interposer, and chips #1, #2 and #3. Top: Chip #3 is shielded. Bottom: Interposer and chips #1 and #2 are invisible

Chip #3 Chips #1 and #2

Fig. 3.96 Correlation between the chips’ average temperatures and the applied cooling capability on the heat spreader

3.10 Multiple System and Heterogeneous Integration with Chips … Table 3.8 Material properties

223

Young’s Poisson’s modulus (GPa) ratio

CTE (ppm/K)

Silicon

130

0.28

2.8

BT substrate

X: 26

0.39

X: 15

0.28

X: 18

Y: 11

Y: 52

FR4

X: 22

Underfill

9.07

0.3

40.75

Solder alloy

Temperature dependent

0.35

Temperature dependent

Electroplated Cu

70

0.34

18

Cu low-k pad

8

0.3

10

SiO2

70

0.16

0.6

IMC (Cu6 Sn5 )

125

0.3

18.2

Nickel

131

0.3

13.4

Y: 10

Y: 70

3.10.7 Thermomechanical Analysis—Material Properties All the thermomechanical material properties such as the Young’s modulus, Poisson’s ratio and coefficient of thermal expansion for the material used in the structure are shown in Table 3.8. Since lead-free solders are temperature and time dependent, the nonlinear temperature and time dependent Garofalo constitutive equations are used [12, 13]. Only 2D finite element modeling is performed in the thermomechanical analyses. Since the structure is symmetry and thus only half of the structure is modeled. The symmetry axis is the Y-axis and proper displacement and rotational boundary conditions are applied. The temperature cycling condition is shown in Fig. 3.97, which is − 25 °C ↔ 125 °C on a 60-min cycle. Stress free is at 25 °C.

3.10.8 Thermomechanical Analysis—Results The 2D element (PLANE182) of ANSYS Mechanical R14 is used to construct the half finite element model as shown in Figs. 3.98 and 3.99. It can be seen that the symmetry–axis is in the Y-axis. Detailed modeling of the TSVs in the interposer and the surrounding areas is shown in Fig. 3.98. Detailed modeling of the solder bumps between the chips and interposer and the interposer and package substrate, and the solder balls between the package substrate and PCB is shown in Figs. 3.98 and 3.99. The whole model is subjected to the thermal cycling loading shown in Fig. 3.97 and the results are shown in the following.

224

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.97 Thermal cycling boundary condition (− 25 °C ↹ 125 °C)

Figure 3.100 shows the von Mises stress contours in the corner TSVs at 125 °C (stress free at 25 °C). It can be seen that the maximum stress is ~ 135 MPa and the critical locations are near the interface between the filled Cu and SiO2 of the TSV and underfill. It is important to study the creep responses for multiple cycles by observing when the hysteresis loops become stabilized. Figure 3.101 shows the shear stress and shear creep strain hysteresis loops for multiple cycles at the corner solder bumps between Chip-2 and the interposer, It can be seen that the shear creep strain versus shear stress loop is quite stabilized after the third cycle. As a matter of fact, for those solder bumps their hysteresis loops are stabilized after the first cycle. Figure 3.101 shows the creep strain energy density history for the corner solder bumps between Chip-2 and the interposer. It can be seen that the creep strain energy density per cycle of the corner solder bumps between Chip-2 and the interposer is 0.0107 MPa. This magnitude is too small to create solder joint thermal-fatigue reliability problem [12, 13] under the environmental condition: − 25 °C ↔ 125 °C on a 60-min cycle. Underfill helps!

3.10.9 Fabrication of the TSV The schematic of the present TSV/RDL Si interposer is shown in Fig. 3.102. It can be seen that the interposer has three RDLs (TR1, TR2, and TR3) on its front-side (topside) and two RDLs (BR1 and BR2) on its backside, which are fabricated on

3.10 Multiple System and Heterogeneous Integration with Chips …

225

Chip-2 Chip-3

BT substrate Solder ball

PCB

Y

Symmetry axis

X Chip-2

Underfill

Underfill

Interposer Electroplated Cu

TSV interposer

SiO2 (0.5μm thick)

BT Substrate

Interposer

Interposer

TSV

Underfill Fig. 3.98 Finite element analysis model of half of the 2.5D IC integration module (showing the details of TSV and surrounding areas)

a 300mm Si wafer. All the metal layers of the RDLs are formed by a Cu damascene technique. Lithography using a contact aligner provides a low-cost process as compared to a stepper/scanner under the same resolution requirements. The five layers pose challenges for manufacturing the backside RDL using a Cu damascene process. The process flow of this TSV/RDL interposer is listed in Table 3.9. The process starts with a SiNx /SiOx insulation layer by PECVD. After TSV lithography, the TSV is etched into the Si substrate by Bosch-type DRIE to form a high-aspect ratio via structure. The etched TSV structure is then processed with a procedure of SiOx liner by SACVD, Ta barrier and Cu seed layers by PVD. Cu electro-plating is used to fill the TSV structure. The final blind TSV has a top opening of approximately 10 μm in diameter and a depth about 105 μm, which give an aspect ratio of 10.5. In such a high-aspect ratio via structure, a bottom-up plating mechanism is applied to ensure a seamless TSV with a reasonably low Cu thickness at the

226

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Chip-2 Chip-3

BT substrate Solder ball

PCB

Y

Symmetry axis

X Chip-2

Interposer

BT substrate

C4 bump

C4 bump

Solder Ball

underfill

Interposer

BT substrate

PCB

Fine mesh for the solder joint at corner Fig. 3.99 Finite element analysis model of half of the 2.5D IC integration module (showing the details of solder bumps between chip 2 and interposer and interposer and package substrate, and solder ball between the package substrate and PCB

Fig. 3.100 Maximum stress acting at the TSV at 125 °C (stress free at 25 °C)

3.10 Multiple System and Heterogeneous Integration with Chips …

227

Fig. 3.101 Top: Hysteresis loop (5 cycles) at the corner solder bump between chip 2 and interposer. Bottom: Creep strain energy density versus time at the corner solder bump between chip2 and interposer

field. The SEM cross-section images are shown in Fig. 3.103. It can be seen that the diameter of the TSV is slightly decreased at the bottom, which is expected from the etching process point of view. The Cu thickness at the field is less than 5 μm. After annealing (400 °C for 30 min), to complete the TSV process, excess Cu at the field is removed by CMP.

3.10.10 Fabrication of the Interposer with Topside RDLs After the TSV formation, the Si interposer wafer goes through three RDL processes on the front-side, using a Cu damascene technology, primarily modified from the conventional Cu BEOL (back-end-of-line) process. The critical dimension (CD) of these RDL layers is 3 μm, which is limited by the resolution of the contact aligner. Three RDL layers are built sequentially, followed by the front-side UBM pads for flip-chip solder bumps attachment. The UBM consists of Cu-UBM pad and NiPdAu

228

3 Multiple System and Heterogeneous Integration with TSV-Interposers TU TO TR3 TV23 TR2 TV12 TR1 TV01

TSV

Si interposer

BV01 BR1 BV12 BR2 BO BU

Fig. 3.102 Schematic of the cross section of the TSV/RDL interposer with 3 RDLs on top and 2 RDLs at the bottom

finishing, which gives room for underfill between the active chip and the interposer and also lowers the possibility of bonding failure. Figure 3.104 shows the SEM crosssectional images of the front-side layers (TSV, 3 front-side RDLs and Top UBM). Figure 3.105 shows the top-view of the interposer. As shown in the top-view photo, inter-connecting region refers to the area for the two active die attachments, while the rest of the area is designed for passive test structures.

3.10 Multiple System and Heterogeneous Integration with Chips … Table 3.9 Processed and parameters for making the TSV/RDL interposer

229

Process stage Inter-layer dielectric (ILD) TSV

• TSV diameter = 10 μm • TSV depth = 105 μm • TSV SiO liner (SACVD) = 0.5 μm @ top • Ta barrier = 0.08 μm @ top

3 front-side RDLS

• Cu damascene • Minimum line-width = 3 μm • Minimum via diameter = 3 μm • Metal thickness = 2 μm and 15 μm • Ta barrier =0.05 μm

Top passivation opening

• Opening diameter = 60 μm

Top UBM

• UBM size = 75 μm • Cu thickness = 5 μm • NiPdAu = 2 μm

Front-side temporary bonding • Glue thickness = 25 μm to SI carrier Backside thinning

• Grinding + CMP

Si recess and TSV backside reveal

• Dry etching

Backside isolation

• PECVD SiO • Temperature < 200 °C • Thickness = 1 μm

CMP tor TSV Cu explosion

• Backside isolation remained > 0.8 μm on the field area

2 backside RQLs

• Cu dual-damascene • Minimum line-width = 5 μm • Minimum via diameter = 5 μm • Metal thickness = 2 μm • Ta Barrier = 0.05 μm

Bottom passivation opening

• Opening diameter = 60 μm

Bottom UBM

• UBM size = 75 μm • Cu thickness = 5 μm • NiPdAu = 2 μm

3 Multiple System and Heterogeneous Integration with TSV-Interposers

TSV

230

Fig. 3.103 SEM cross-section images of the TSV

3.10.11 TSV Reveal of the Cu-Filled Interposer with Topside RDLs After the front-side process is done, wafers thinning starts with the temporary bonding process. The Si interposer wafer is temporarily bonded to a Si carrier before being ground and polished at the backside of the Si interposer wafer, which stops before the TSV is revealed. The thickness distribution across the wafer for the remaining Sisubstrate after the backside grinding/polishing process is very uniform. The profile distribution is shown in Fig. 3.106. The wafer backside was then dry-etched to reveal the TSV and also to recess the Si surface. The isolation dielectrics are deposited before CMP to expose the TSV backside Cu surface for connecting to backside RDL. Due to the maximum working temperature of the temporary bonding adhesive, the temperature of the backside processes is restricted to less than 200 °C.

3.10.12 Fabrication of the Interposer with Bottom-Side RDLs Due to the concerns of mask alignment capabilities with the contact aligner and the wafer warpage from both front-side processing and the temporary bonding process,

3.10 Multiple System and Heterogeneous Integration with Chips …

231

Fig. 3.104 SEM cross-sectional images of the topside of the interposer (TSV, RDLs: TR1, TR2, TR3, and the top UBM)

the minimum CD of the backside RDL is relaxed to 5 μm. Also, to reduce processinduced cracking or chipping on the thinned wafer, the backside RDL process utilizes Cu dual-damascene technique (RDL + via formation with one ECD and CMP). The SEM cross-section image of the first backside RDL/via Cu dual-damascene metallization (connecting to the TSV backside) is shown in Fig. 3.107. Similar to the front-side process, two backside RDLs were done sequentially, followed by the backside UBM pads for the solder bumps for the backside flip-chip attachment and for the organic substrate, respectively.

232

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.105 Top-view of the TSV/RDL interposer

Fig. 3.106 Mapping of the Si-substrate remained thickness after backside grinding

3.10 Multiple System and Heterogeneous Integration with Chips …

233

Fig. 3.107 SEM cross-sectional image of Cu dual-damascened first backside RDL (BR1 + BV01) connecting to the bottom of TSV

Figure 3.108 shows the SEM cross-section of all backside layers (TSV, 2 backside RDLs and Bottom UBM) and Fig. 3.109 shows the bottom-view of the interposer. Figure 3.110a shows the SEM cross sections of the front-side layer and Fig. 3.110b shows the SEM cross sections of the back-side layer. To complete the Si interposer process, de-bonding of the thinned Si interposer wafer from the Si carrier is performed before the thinned Si interposer wafer is diced. The diced interposer die is ready for heterogeneous integration packaging and also for passive electrical characterization on the interposer and package.

3.10.13 Passive Electrical Characterization of the Interposer Measurement and modeling results for various micro-striplines, striplines, and coplanar waveguide lines of the fabricated interposer have been reported in [76]. Figure 3.111 shows the electrical performance (insertion loss and return loss) for three different cases. There is discrepancy shown between the measured and the 3D field solver modeling results when nominal design dimensions are used. However, when actual manufactured dimensions are used as shown in Fig. 3.112, the correlation between the model and measured results is very good.

234

3 Multiple System and Heterogeneous Integration with TSV-Interposers

TSV

BR1 BR2

Bottom UBM

Fig. 3.108 SEM cross-sectional images of the backside of the interposer (TSV, RDLs: BR1, BR2, and bottom UBM)

3.10.14 Final Assembly Figure 3.113 schematically shows the process flow of the final module assembly. First, attach the backside chip on the interposer, then reflow the solder, apply and cure the underfill. Attach the interposer on the topside of the organic package substrate and reflow. Then apply the underfill and cure. Attach the two top-side chips on the topside of the interposer, reflow the solder, then apply and cure the underfill. Finally, solder ball mounting on the bottom-side of the package substrate and reflow as shown in steps 7 and 8 of Fig. 3.113.

3.10 Multiple System and Heterogeneous Integration with Chips …

235

Fig. 3.109 Bottom-view of the TSV/RDL interposer

Figure 3.114 shows an assembled package, which consists of a passive TSV/RDL interposer supporting two active chips on the topside (with underfill) (left-hand side of Fig. 3.114) and one active chip on the bottom-side (with underfill) (right-hand side of Fig. 3.114). This interposer with the chip set is soldered to the topside of a package substrate with cavity. Figure 3.115 shows the cross-sections of the fully assembly module. It can be seen that the interposer is properly supporting the 3 chips with underfill. This interposer is soldered (with underfill) to a 4-2-4 package substrate. Figure 3.116 shows the X-ray image from the top-view of the fully-assembly module, demonstrating the assembly is done properly. It can be seen that the two dies (un-thinned) at the frontside and one die at the backside are perfectly aligned, with solder bumps (connecting the interposer to the package substrate) at the peripheral regions on the interposer backside.

3.10.15 Summary and Recommendations • Equivalent thermal conductivities of TSV with SiO2 and Cu-filling have been provided. • Examples in using the equivalent thermal conductivities for the present 3D IC integration module have been presented and discussed. • The relationships between chips’ average temperature and the applied cooling capability (Rca ) to the heat spreader/sink of the 3D IC integration module have been provided. Examples in using these relationships have also been given.

236

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Top UBM TR3

TR2

(a)

TR1

TSV

TSV

(b) BR1 BR2

Bottom UBM

Fig. 3.110 TSV/RDL. a Near the topside. b Near the bottom-side

• The maximum stress (135 MPa) at 125 °C (stress free is at 25 °C) in the TSVs occurred at the corner TSV and the location is at the interface between the SiO2 , Cu, and underfill. • The maximum creep strain energy density per cycle occurred at the corner solder bumps between Chip-2 and interposer, Chip-3 and interposer, and interposer and package substrate and the magnitudes are respectively 0.0107, 0.0117, and 0.0125 MPa. These values are too small to have solder joint thermal-fatigue problem. Underfill helps!

3.10 Multiple System and Heterogeneous Integration with Chips …

237

Fig. 3.111 Simulation and measurement correlation results

Fig. 3.112 SEM cross-sectional image of the interposer for simulation and measurement

• The maximum creep strain energy density per cycle of the solder balls between the package substrate and PCB occurred at the corner solder ball and the magnitude is 0.071 MPa. Again, this value is too small to have solder ball thermal-fatigue problem. • There are 5 RDLs on the passive interposer; 3-RDL on its front-side and 2-RDL at its backside. • Contact aligner has been used for all lithography processes for the interest on process cost. However the wafer warpage induced lithography difficulty using contact aligner is a concern.

238

3 Multiple System and Heterogeneous Integration with TSV-Interposers

(1)

(1) Attach back-side chip on Si interposer

(2)

(2) Die bonding by Reflow & underfill dispensing

(3)

(3) Attach Si interposer on organic package substrate by Reflow

(4)

(4) Underfill dispensing of Si interposer

(5)

(5) Attach two top-side chips on Si interposer

(6)

(6) Die bonding by reflow & underfill dispensing of two top-side chips

(7)

(7) Solder ball mounting & reflow

(8)

(8) Finished

Fig. 3.113 Final TSV/RDL interposer and chips assembly process flow

• The RDL process on both sides of the interposer using a contact aligner has been modified from the typical CMOS BEOL Cu-damascene process technique. • Minimum CD is relaxed for the backside process based on the concerns of the thinned-wafer warpage induced by front-side process and temporary bonding. • SEM cross-section images showed that all the double-sided wiring layers (RDLs) and vias have been properly fabricated. Also, void-less Cu-filled TSVs have been achieved. • For the final assembly, the chips have been successfully attached to the interposer and underfilled. The multichip interposer module has also been attached onto an organic package substrate. The cross-section and x-ray results indicated that

3.10 Multiple System and Heterogeneous Integration with Chips …

239

Fig. 3.114 Fully assembled 3D IC integration module. a Topside showing the two chips. b Bottomside showing the one chip Interposer

Underfill

Chip-1

Underfill

Chip-3

Chip-1

4-2-4 substrate

Interposer

Chip-1

Interposer

Chip-2

4-2-4 Substrate

Underfill

Chip-2

Chip-3

Fig. 3.115 Cross-section of the fully assembled module (3 chips, interposer, package substrate, and underfill)

the fully-assembly module with the active dies on the double-sided TSV/RDL interposer is done properly. • The electrical VNA testing of passive test structures corresponded well with 3D field solver modeling results.

240

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Fig. 3.116 X-ray image from the top-view of the fully assembled SiP

3.11 Multiple System and Heterogeneous Integration with Through-Silicon Hole TSV is the heart and most important key enabling technology of 2.5D and 3D IC integration. Usually, there are six key steps in making a TSV, namely: (1) via formation by either deep reactive ion etch (DRIE) or laser drilling; (2) dielectric layer by plasma-enhance chemical vapor deposition (PECVD); (3) barrier and seed layers by physical vapor deposition; (4) via Cu-filling by electroplating; (5) chemical– mechanical polishing (CMP) to remove the overburden Cu; and (6) TSV Cu reveal by backgrinding, Si dry-etching, low-temperature passivation, and CMP. Thus, how to make low-cost TSVs is one of the important research topics for 2.5D and 3.D IC integration. In this section, a class of very low-cost interposer with through-silicon holes (TSHs) and with chips on both of its sides is developed [119, 120]. Figure 3.117 schematically shows a multiple system and heterogeneous integration with a TSH interposer supporting a few chips on its top and bottom sides. The key feature of TSH interposers is there is not metallization in the holes and the dielectric layer, barrier and seed layers, via filling, CMP for removing overburden copper,

3.11 Multiple System and Heterogeneous Integration with Through-Silicon … Through-Si Holes (TSH) Interposer

chip

Micro Solder joints

Non-metallization holes on the TSH interposer

RDL

RDL Solder RDL bump

chip

RDL

RDL chip

Cu wire or pillar

241

RDL chip

Solder bump

Organic Package Substrate Solder ball

Solder ball

Printed Circuit Board Not-to-Scale Underfill is needed between the TSH interposer and package substrate. Underfill may be needed between the TSH interposer and chips.

Fig. 3.117 SiP that consists of a TSH interposer supporting chips with Cu pillars on its top side and chips with solder bumps on its bottom side

and Cu revealing are not necessary. Comparing with the TSV interposers, TSH interposers only need to make holes (by either laser or DRIE) on a piece of silicon wafer. Just like the TSV interposers, RDLs are needed by the TSH interposers. The TSH interposers can be used to support the chips on its top side as well as bottom side. The holes can let the signals of the chips on the bottom-side transmit to the chip on the top side (or vice versa) through the Cu pillars and solders. The chips on the same side can communicate to each other with the RDLs of the TSH interposer. Physically, the top and bottom chips are connected through Cu pillars and microsolder joints. In addition, the peripherals of all the chips are soldered to the TSH interposer for structural integrity to resist shock and thermal conditions. In addition, the peripherals of the bottom side of the TSH interposer have ordinary solder bumps that are attached to a package substrate. It has been shown in [119, 120] that the electrical performance of the TSH interposer is better than that of the TSV interposer. In this section, a very simple test vehicle is fabricated to demonstrate the feasibility of this SiP with TSH interposer technology. The design, materials, and process of the top chip with Cu pillars, bottom chip with solder bumps, and TSH interposer will be presented. The final assembly of the SiP test vehicle that consists of the chips, interposer, package substrate, and printed circuit board (PCB) will also be provided. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure. A simple simulation showing the electrical performance of the TSH interposer is better than that of the TSV interposer will be presented first.

242

3 Multiple System and Heterogeneous Integration with TSV-Interposers

3.11.1 Electrical Simulation and Results Figure 3.118 shows the material, geometry, and dimension of the TSV and THS under simulations. It can be observed that 3D axial-symmetry structure is used, the finite element code is ANSYS-HFSS, and simulation frequency is up to 20 GHz. The thickness of both interposers is the same (100 μm). Two different pitches are considered, one is 100 μm and the other is 200 μm. The size of the TSV is 15 μm and two different SiO2 thicknesses are considered, 0.2 and 0.5 μm. The size of the TSH is 15 μm and two different sizes of the airhole are considered: 7.5 and 15 μm. The simulation code and procedures have been verified in [203]. The simulation results are shown in Figs. 3.119 and 3.120 for via pitches equal to, respectively, 100 and 200 μm. It can be observed that: (1) for both pitches, there is very small difference in S21 for the two sizes of airhole considered in TSH; this gives more freedom for mechanical design without affecting the electrical performance and (2) for both pitches, the S21 of the TSH is much better than TSV, which means the TSH has much smaller insertion loss than TSV for high-frequency signal transit. Thus, as expected, the electrical performance of the new design TSH is better that the conventional TSV. Comparing with TSV, TSH has thicker isolation gap, which results in smaller via parasitic capacitance. Therefore, like parallel transmission lines, increasing the TSH pitch will lead to higher parasitic inductance and result in higher S21.

TSV Cu

Si

Port 2

U nits (μm) 15

SiO2

0.5, 0.2

TSH

15

Hole

7.5, 15

Pitch

100, 200

Thickness

100

Port 1 TSH Si

Pitch Cu

Hole

Material property silicon

DK=11.9 , σ =20 s/m

SiO2

DK=4

Air

DK=1.0006

Copper

σ =5.8*107 s/m

TSH

Fig. 3.118 Electrical simulation structure of the TSV and TSH interposers

Port 2

Cu

Air

Pitch SiO2

Items TSV

Air

Cu

SiO2

Si

SiO2

Thickness

Port 1

Thickness

TSV

Si

3.11 Multiple System and Heterogeneous Integration with Through-Silicon …

243

Fig. 3.119 S21 for TSH and TSV interposers (pitch = 100 μm)

Fig. 3.120 S21 for TSH and TSV interposers (pitch = 200 μm)

3.11.2 Test Vehicle The test vehicle is shown in Fig. 3.121. It can be observed that it consists a TSH interposer, which is supporting a top chip with Cu pillars and a bottom chip with UBM and solder. The interposer module is connected to a package substrate and then attached to a PCB. The dimensions of the top chip are 5 mm × 5 mm × 725 μm. The chip has (16 × 16 = 256) Cu pillars at its central portion and two-row (176) of Cu UBM/pads at its

244

3 Multiple System and Heterogeneous Integration with TSV-Interposers Non-metallization holes on the TSH interposer Cu Pillar Top Chip

TSH Interposer Bottom Chip Package Substrate

Not-to-Scale

PCB

Fig. 3.121 SiP test vehicle that consists of a top chip with Cu pillars and a bottom chip with solder bumps on a TSH interposer

peripherals. The diameter of the Cu pillars is 50 μm. They are 100-μm tall and on 200-μm pitch, as shown in Fig. 3.122 and Table 3.10. The thickness of the peripheral Cu UBM/pads is 9 μm and with electroless (2 μm) Ni and immersion (0.05 μm) Au (ENIG). The dimensions of the bottom chip are also 5 mm × 5 mm × 725 μm. The chip has 432 Cu UBM/pads (4 μm) and coated with Sn solders (5 μm). The central 256 are for the interconnections of the Cu pillars of the top chip. The dimensions of the TSH interposer are 10 mm × 10 mm × 70 μm (Figs. 3.122 and 3.123). It has 256 holes at its central portion to let the Cu pillars to pass through. The diameter of the holes is 100 μm, and the pitch of the holes is 200 μm. There are two-row (176) of peripheral Cu UBM/pads (4 μm) coated with Sn solders (5 μm) on the top side of the TSH interposer for the interconnections of the top chip. On the other hand, there are two-row (176) of peripheral Cu UBM/pads (9 μm) with ENIG (2 μm) on the bottom side of the TSH interposer for the interconnections of the bottom chip. The dimensions of the organic package substrate are 15 mm × 15 mm × 1.6 mm. There is a cavity (6 mm × 6 mm × 0.5 mm) on the top side of the substrate for the bottom chip. The dimensions of the PCB are 132 mm × 77 mm × 1.6 mm, which is a standard size of the JEDEC (JESD22-B111) specification.

3.11.3 Top Chip with UBM/PAD and Cu Pillar The process flow of fabricating the top chip with Cu pillars is shown in Fig. 3.124. Since this is not a device chip but a piece of silicon, the daisy chain (RDL) will be fabricated first. A SiO2 is deposited on a Si wafer with PECVD provided by Lam Research at 200 °C. Then, 0.1-μm Ti and 0.3-μm Cu are sputtered by the MRC

3.11 Multiple System and Heterogeneous Integration with Through-Silicon …

245

Top Chip

725μm

Cu UBM/Pad (9μm) + 2μm ENIG Cu-Pillar (CD = 50μm; Tall = 100μm; Pitch 200μm)

Sn Solder (5μm) Si Hole 70μm

Cu UBM/Pad (4μm)

TSH Interposer Si Hole (CD = 100μm; Pitch = 200μm)

Cu UBM/Pad (9μm) + 2μm ENIG

Sn Solder (5μm) Cu UBM/Pad (4μm)

725μm

Bottom Chip

Not-to-Scale

Fig. 3.122 Geometry, dimension, and interconnects of the top chip, bottom chip, and TSH interposer Table 3.10 Dimensions of the TSH interposer

Top-chip with Cu-pillar Dimension

5 mm × 5 mm × 725 μm

Cu-pillar

CD = 50 μm; Tall = 100 μm; Pitch = 200 μm

Cu UBM/Pad

9 μm + 2 μm (ENIG) Bottom-chip without Cu-pillar

Dimension

5 mm × 5 mm × 725 μm

Cu UBM/pad

4 μm 5 μm

Sn solder

TSH interposer Dimension

10 mm × 10 mm × 70 μm

TSH

CD = 100 μm; Pitch = 200 μm; Depth = 70 μm

Top-side: Cu UBM/pad and Sn solder

4 μm (Cu) and 5 μm (Sn)

Bottom-side: Cu UBM/pad

9 μm + 2 μm (ENIG)

Package substrate (cavity) 15 mm × 15 mm × 1.6 mm (6 mm × 6 mm × 9 mm) PCB 132 mm × 77 mm × 1.6 mm

246

3 Multiple System and Heterogeneous Integration with TSV-Interposers

TSH Interposer

10mm

Holes for Cu Pillars Pitch = 200μm Diameter = 100μm

Daisy chain

Pads for top/bottom chips

Pads for package substrate 10mm Fig. 3.123 Layout of the TSH interposer

machine. It is followed by spin coating a photoresist and patterning with a mask using a photolithography technique (align and expose). Electroplate the Cu (2 μm) RDL. Then, strip off the photoresist and etch off the TiCu. A SiO2 (0.5 μm) is deposited on top of the whole wafer with PECVD. Again, photoresist and patterning is performed. Then, dry etch the SiO2 by reactive ion etch. It is followed by stripping off the photoresist and now it is ready for wafer bumping. First, sputter the seed layer: (0.1 μm) Ti and (0.3 μm) Cu. Then, photoresist (9.5 μm from JSR) and pattern all 432 pads. It is followed by electroplating the Cu UBM/pad (9 μm). Strip off the photoresist and etch off the TiCu seed layer. Then, a positive type of photoresist (100 μm) provided by HD Microsystems is laminated (hard pressed) on the wafer and it is followed by patterning only the central 256 pads, and Cu plating (90 μm) with Semitool (now Applied Materials) at room temperature. Then, the top surface of the wafer is flattened by DISCO’s fly cut. It is followed by stripping off the photoresist and etching off the TiCu. Finally, electroless Ni (2 μm) and immersion Au (0.05 μm). Figure 3.125 shows the SEM images of the Cu pillars, Cu UBM/pads, and Cu RDLs (daisy chains) on the top chip. The smaller diameter (45 μm) on top of the Cu pillars is because of the smaller opening on top of the dry film photoresist.

3.11.4 Bottom Chip with UBM/Pad/Solder The process flow in fabricating the bottom chip with UBM/pad and solder is shown in Fig. 3.126. It can be observed that the process in making the Cu RDL is the

3.11 Multiple System and Heterogeneous Integration with Through-Silicon … TiCu SiO2

Si

PR, Patterning

SiO2, Sputter TiCu Pad UBM

Photoresist (PR), Patterning

Cu UBM/Pad Plating (9μm), Strip PR, Etch TiCu

Cu Plating (2μm) RDL

247

TiCu Strip PR, Etch TiCu

Sputter TiCu, PR (100μm), Patterning

SiO2 PECVD SiO2 (0.5μm) Cu Pillar PR, Patterning

Cu Plating (90μm), Strip PR, Etch TiCu

SiO2 Etch Cu Pillar Strip PR

SiO2

TiCu Sputter (0.1μm)Ti (0.3 μm)Cu

UBM RDL

ENIG Electronless (2μm)Ni(.05μm)Au (ENIG)

Si

Fig. 3.124 Process flow in fabricating the top chip with RDL, Cu UBM/pad, and Cu pillar

same as those of the top chip. For most of the wafer bumping processes, they are the same except the photoresist thickness and solder. After photoresist (9.5 μm) and patterning all (432) pads, it is followed by electroplating the Cu UBM/pad (4 μm) and electroplating the Sn solder (5 μm). Strip off the photoresist and etch off the TiCu. A photo of the RDL, Cu UBM/pad, and Sn solder cap on the bottom chip is shown in Fig. 3.126.

3.11.5 TSH Interposer The process flow in fabricating the TSH interposer with Cu UBM/pad + Sn solder on its top side and Cu UBM/pad on its bottom side is shown in Fig. 3.127. It can be observed that, the RDL and Cu UBM/pad on the bottom side of the interposer will be fabricated first and the processes are basically the same as those for the top chip. Except after the strip off of the photoresist and etch off of the seed layer (TiCu) of the 9-μm-thick UBM/pad, it is followed by ENIG (2-μm Ni–0.05-μm Au). Then, the bottom side of the interposer wafer with UBM/pad is temporary bonded with an adhesive to a 750-μm-thick silicon supporting wafer (carrier). It is followed by thinning the top side of the interposer wafer down to 70 μm. Then, repeat all the process steps in fabricating the UBM/pad + Sn solder of the bottom chip

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Si

9μm

50μm

Cu Pad/UBM

45μm Cu Top-view of Cu pillars with Photoresist

Center =319 Radius = 22.53μm Length =141.56 μm Area = 1594.68 μm2

Photoresist

Fig. 3.125 SEM images of the Cu UBM/pads and Cu pillars (diameter = 50 μm at the bottom and = 45 μm at the top)

mentioned earlier. Finally, debond the carrier wafer from the interposer wafer at room temperature. At this stage, the interposer wafer with 176 peripheral UBM/pads + Sn solders on its top side and 176 peripheral UBM/pads at its bottom side is achieved. The 256 holes are fabricated with UV laser drilling by the Siemens MicroBeam 3205. The power is 3400 mW. Figure 3.128 shows the photo images of the 70-μm-thick TSH interposer wafer with RDLs, pads for the package substrate, peripheral pads for the chips, and 100-μm-diameter holes on 200-μm pitch.

3.11.6 Final Assembly The process flow of the final assembly of the SiP with TSH interposer test vehicle is shown in Fig. 3.129. First, the top chip with the 176 peripheral UBM/pads is thermocompression (TC) bonded (with the SuSS FC-150 bonder) to the peripheral UBM/pads + Sn solders on the top side of the TSH interposer. (The Cu pillars passed through the holes of the TSH interposer.) The TC bonding conditions are shown in Fig. 3.130. It can be observed that: (1) the maximum bonding force is 1600 g; (2) the maximum temperature of the chuck is 150 °C; (3) the maximum temperature of the head is 250 °C; and (4) the cycle time is 120 s.

3.11 Multiple System and Heterogeneous Integration with Through-Silicon …

249

TiCu Si

SiO2

SiO2, Sputter TiCu PR, Patterning, Cu Plating (2μm)

RDL

TiCu Strip PR, Etch TiCu SiO2 PECVD SiO2 (0.5μm)

RDL

PR, Patterning

Cu Pad

SiO2 Etch, Strip PR Si TiCu Sputter (0.1μm)Ti(0.3μm)Cu

Solder (Sn) on top of the UBM (Cu)

PR (9.5μm), Patterning

RDL Si

UBM

Solder SiO2

UBM Cu Plating (4μm), Solder Sn Plating (5μm), Strip PR, Etch TiCu

Fig. 3.126 Process flow in fabricating the bottom chip with RDL, and Cu UBM/pad + Sn solder

Then, all the 432 UBM/pads + Sn solders on the bottom chip are TC bonded to the tip of the 256 central Cu pillars and 176 peripheral UBM/pads on the bottom side of the TSH interposer. The bonding conditions are basically the same as those of the top chip except the bonding force is reduced to 800 g. It is followed by solder (Sn3wt%Ag0.5wt%Cu) bump (350-μm diameter) mounting on the bottom side of the TSH interposer. Then, a capillary-type underfill with 50% filler contents (average filler size = 0.3 μm and maximum filler size = 1 μm) is dispensed along two adjacent sides of the top chip. After, the underfill: (1) fills the gap between the top chip and the TSH interposer; (2) flows through the holes of the TSH interposer; and 3) fills the gap between the bottom chip and the TSH interposer, then it is cured at 150 °C for 30 min. The whole TSH interposer module is solder reflowed on the package substrate by a standard lead-free temperature profile with a maximum at 240 °C. To enhance the solder joint reliability, the underfill is applied between the TSH interposer and the organic package substrate. It is followed by solder (Sn3wt%Ag0.5wt%Cu) ball (450-μm diameter) mounting on the bottom side of the package substrate. Finally,

250

3 Multiple System and Heterogeneous Integration with TSV-Interposers TiCu

Si TSH Interposer

RDL

SiO2

TiCu

Electronless (2μm)Ni(.05μm)Au (ENIG)

SiO2, Sputter TiCu PR, Patterning, Cu Plating (2μm)

Carrier Temporary bonding to a carrier

Strip PR, Etch TiCu SiO2 PECVD SiO2 (0.5μm)

Thin down the TSH interposer to 70μm

PR, Patterning

Repeat the process of making Cu-Sn solder bumps of the bottom chip

SiO2 Etch, Strip PR TiCu Sputter (0.1μm)Ti (0.3μm)Cu Pad PR (9.5μm), Patterning Pad UBM

Cu Plating: UBM(4μm), Pad(5μm), Strip PR, Etch TiCu

RDL SiO2

RDL UBM

UBM

ENIG Debond the carrier

SiO2 Solder

Fig. 3.127 Process flow in fabricating the TSH interposer with Cu UBM/pad + Sn solder on its top side and Cu UBM/pad on its bottom side

the whole SiP package is solder reflowed on the PCB with the same lead-free reflow temperature profile just mentioned. The final assembled SiP test vehicle is shown in Fig. 3.131. It can be observed that the PCB is supporting the package substrate, which is supporting the TSH interposer, which is supporting the top chip. The bottom chip is blocked by the TSH interposer and cannot be seen. Figure 3.132 shows the X-ray images of the final assembled SiP. It can be observed that: (1) the Cu pillars are not contacting the side wall of the TSH and (2) the Cu pillars are almost at the center of the TSH. Figure 3.133 shows the SEM image of a cross section of the SiP, which includes all the key elements such as the top chip, TSH interposer, bottom chip, package substrate, PCB, microbumps, solder bumps, solder ball, TSH, and Cu pillars. It can be observed through the X-ray and SEM images that the key elements of SiP structure are properly fabricated.

3.11.7 Reliability Assessments In this study, the reliability assessments to verify the structural and thermal integrity of the assembled SiPs are drop test and thermal cycling test.

3.11 Multiple System and Heterogeneous Integration with Through-Silicon …

251

TSH Interposer Wafer

RDLs, Pads for the Package Substrate, and peripheral Pads for the chips

Pads for Substrate

Laser Drilled TSH on the Interposer Wafer

Hole RDLs

Si Pads for Chips

100μm

Fig. 3.128 TSH interposer wafer (T) with laser drilled holes (R) and RDL and pads for chip (L)

(A) Shock (Drop) Test and Result: The drop test board and setup are based on JESD-B111. The SiPs are facing upward during the test. Four standoffs on the fixture provide the support and the spacing for deflections of the PCB during impacts, as shown in Fig. 3.134. The drop height is 460 mm, which leads to the acceleration = 1500 g, as shown in Fig. 3.135. After 10 drops, there is not any failure, i.e., no resistance changes of the daisy chains. In addition, after careful inspection, there is not any obvious damage, such as crack and delamination. (B) Thermal Cycling Test and Results: The thermal cycling test conditions are − 55 °C ↔ 125 °C, and 1-h cycle (15-min ramp-up and ramp-down and 15 min at dwells). Figure 3.136 shows a Weibull plot [12, 13] of the test results and it can be observed that for the median (50%) rank, the Weibull slope is 2.52, and the sample characteristic life (at 63.2% failures) is 1175 cycles. (For the given test conditions, if the characteristic life is larger than 1000 cycles, then it is considered acceptable.) The sample mean life of the daisy chained solder joints is defined as the mean time to failure = 1175 ┌(1 + 1/2.52) = 1036 cycles, where ┌ is the Grammar function. This mean life occurs at F(1036) = 1 − exp[−(1036/1175)2.52] = 0.52, that is, 52% failures. Figure 3.136 also shows the test results at 90% confidence level, that is, in nine of ten cases, we would like to find out the intervals for the true Weibull slope and

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

Top-chip bonded on TSH interposer by TCB TSH interposer module on package substrate by reflow and underfill dispensing and curing

Bottom-chip bonded on TSH interposer by TCB

Solder ball mounting Solder bump mounting

Underfill dispensing and curing TSH interposer package assembled on PCB

Fig. 3.129 Process flow in the final assembly of SiP

1800 1600

ARM

1400

250

Force (g)

Temperature (oC)

300

CHUCK

200 150 100

1000 800 600 400

50 0 0

1200

200 50

100

Time (s)

150

0

0

20

40

60

80

100

120

140

Time (s)

Fig. 3.130 TC conditions in bonding the top chip to the top side of TSH interposer: temperature (L) and force (R)

the true mean life of the daisy chained solder joints. It can be observed that the true mean life of the solder joints (in 90 of 100 cases, the other 10 cases, no one knows) will be no less than 843 cycles but no larger than 1524 cycles. In addition, the true Weibull slope (β) falls into the intervals 2.16 ≤ β ≤ 2.88. One of the typical failure modes is shown in Fig. 3.137. It can be observed that there is a crack in the solder bump between the TSH interposer and the pad of the organic package substrate. The failure (crack) location is in the solder bump near the interface between the solder

3.11 Multiple System and Heterogeneous Integration with Through-Silicon …

253

PCB

TSH Interposer

Underfill

Top Chip

Package Substrate PCB Fig. 3.131 Final assembled SiP

and the UBM of the TSH interposer. It failed at 1764 cycles and the failure criterion is infinitive resistance changed.

3.11.8 Summary and Recommendations Some important results and recommendations are summarized as follows. • A heterogeneous integration that consists of a TSH interposer with chips on its top and bottom side has been developed. • The electrical performance of the TSH interposer is better than that of the TSV interposer. • The RDL (daisy-chain) top chip with 256 100 μm Cu pillar + 2 μm ENIG at its central portion and 176 9 μm UBM/pad + 2 μm ENIG around the peripherals has been properly fabricated. • The RDL (daisy-chain) bottom chip with 432 4 μm UBM/pad + 5 μm Sn solder has been properly fabricated. • The RDL (daisy-chain) TSH interposer with 256 central holes (drilled by laser), 176 4 μm UBM/pad + 5 μm Sn solder around the peripherals on its top-side, and

254

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Solder bumps between TSH Interposer and package substrate

Solder bumps between TSH Interposer and Top- Chip and Bottom-Chip

Holes in the TSH Interposer

Cu-Pillars

Fig. 3.132 X-ray images showing the location of Cu pillars and TSHs of the SiP that consists of the top chip, TSH interposer, bottom chip, package substrate, and PCB

• • •

•

176 9 μm UBM/pad + 2 μm ENIG around the peripherals on its bottom side has been properly fabricated. The final assembly of the top chip, bottom chip, TSH interposer, package substrate, and PCB has also been properly fabricated. These are evidenced by the SEM and X-ray images. The structural integrity of the SiP has been demonstrated by drop test. Based on the JEDEC specification, after 10 drops, there is not any obvious failure. The thermal cycling test conditions are − 55 °C ↔ 125 °C, and 1-h cycle (15min ramp-up and ramp-down and 15 min at dwells). Since the characteristic life (1175) is larger than 1000 cycles, the solder-joint thermal fatigue is considered acceptable. The chips (especially the bottom chip) should be thinned down to less than 200 μm. In that case, the cavity in the package substrate is not needed.

3.11 Multiple System and Heterogeneous Integration with Through-Silicon …

255 Underfill

Top Chip TSH Interposer Bottom Chip

Microbump

Solder Bump

Underfill Package Substrate Solder Ball

PCB

TSH Interposer

Cu Pillar

Hole partially filled with underfill

Cu Pillar

Top Chip

TSH Interposer

Bottom Chip Microbump

Fig. 3.133 SEM image showing a cross section of the SiP that consists of the top chip, TSH interposer, bottom chip, package substrate, and PCB

Package Substrate PCB

Fig. 3.134 Drop test of the SiP setups

3 Multiple System and Heterogeneous Integration with TSV-Interposers

Acceleration (g)

256

Time (s) Fig. 3.135 Drop test profile according to JESD22-B111

3.11 Multiple System and Heterogeneous Integration with Through-Silicon …

257

99.00 95% rank 90.00

Percent failed, F(x)

50.00 5% rank 10.00

50% rank

At 90% confidence level: The true mean life (µ) will fall in the intervals: 843 ≤ µ ≤ 1524 cycles. The Weibull slope error = 0.36. Thus the true Weibull slope (β) will fall into the intervals: 2.16 ≤ β ≤ 2.88.

5.00

1.00 0.50 500

At median (50%) rank: Weibull slope = 2.52 Characteristic life = 1175 cycles. Mean (MTTF) life = 1036 cycles Mean life occurs at F = 52% failures

1000

3000

Cycles-to-failure, (x) Fig. 3.136 Weibull plot of daisy-chained solder joint under thermal cycling testing, − 55 °C ↔ 125 °C, and 1-h cycle (15-min ramp-up and ramp-down and 15 min at dwells). The required confidence level was 90%

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3 Multiple System and Heterogeneous Integration with TSV-Interposers

TSH Interposer Package Substrate

Top Chip

Bottom Chip

PCB

TSH Interposer Cracks Solder Bump Pad on package substrate

Fig. 3.137 Failure (solder joint cracking) mode due to thermal cycling test

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136. Wang, J., Niu, Y., Park, S., & Yatskov, A. (2018). Modeling and design of 2.5D package with mitigated warpage and enhanced thermo-mechanical reliability. In IEEE/ECTC Proceedings, pp. 2471–2477. 137. Okamoto, D., Shibasaki, Y., Shibata, D., Hanada, T., Liu, F., Sundaram, V., & Tummala, R. (2018). An advanced photosensitive dielectric material for high-density RDL with ultra-small photo-vias and ultra-fine line/space in 2.5D interposers and fan-out packages. In IEEE/ECTC Proceedings, pp. 1543–1548. 138. Cai, H., Ma, S., Zhang, J., Xiang, W., Wang, W., Jin, Y., Chen, J., Hu, L., & He, S. (2018). Thermal and Electrical characterization of TSV interposer embedded with Microchannel for 2.5D integration of GaN RF devices. In IEEE/ECTC Proceedings, pp. 2150–2156. 139. Hong, J., Choi, K., Oh, D., Shao, S., Wang, H., Niu, Y., & Pham, V. (2018). Design guideline of 2.5D package with emphasis on warpage control and thermal management. In IEEE/ECTC Proceedings, pp. 682–692. 140. Nair, C., DeProspo, B., Hichri, H., Arendt, M., Liu, F., Sundaram, V., & Tummala, R. (2018). Reliability studies of excimer laser-ablated microvias below 5 micron diameter in dry film polymer dielectrics for next generation, panel-scale 2.5D interposer RDL. In IEEE/ECTC Proceedings, pp. 1005–1009. 141. Xu, J., Niu, Y., Cain, S., McCann, S., Lee, H., Ahmed, G., & Park, S. (2018). The experimental and numerical study of electromigration in 2.5D packaging. In IEEE/ECTC Proceedings, pp. 483–489. 142. McCann, S., Lee, H., Ahmed, G., Lee, T., & Ramalingam, S. (2018). Warpage and reliability challenges for stacked silicon interconnect technology in large packages. In IEEE/ECTC Proceedings, pp. 2339–2344. 143. Hsiao, Y., Hsu, C., Lin, Y., & Chien, C. (2019). Reliability and benchmark of 2.5D nonmolding and molding technologies. In IEEE/ECTC Proceedings, pp. 461–466. 144. Pares, G., Michel, J., Deschaseaux, E., Ferris, P., Serhan, A., & Giry, A. (2019). Highly compact RF transceiver module using high resistive silicon interposer with embedded inductors and heterogeneous dies integration. In IEEE/ECTC Proceedings, pp. 1279–1286. 145. Okamoto, D., Shibasaki, Y., Shibata, D., & Hanada, T., Liu, F., Kathaperumal, M., & Tummala, R. (2019). Fabrication and reliability demonstration of 3 μm diameter photo vias at 15 μm pitch in thin photosensitive dielectric dry film for 2.5 D glass interposer applications. In IEEE/ECTC Proceedings, pp. 2112–2116. 146. Wang, H., Wang, J., Xu, J., Pham, V., Pan, K., Park, S., Lee, H., & Ahmed, G. (2019). Product level design optimization for 2.5D package pad cratering reliability during drop impact. In IEEE/ECTC Proceedings, pp. 2343–2348. 147. Chen, W., Lin, C., Tsai, C., Hsia, H., Ting, K., Hou, S., Wang, C., & Yu, D. (2020). Design and analysis of logic-HBM2E power delivery system on CoWoS® platform with deep trench capacitor. In IEEE/ECTC Proceedings, pp. 380–385. 148. Bhuvanendran, S., Gourikutty, N., Chua, K., Alton, J., Chinq, J., Umralkar, R., Chidambaram, V., & Bhattacharya, S. (2020). Non-destructive fault isolation in through-silicon interposer based system in package. In IEEE/EPTC Proceedings, pp. 281–285. 149. Sirbu, B., Eichhammer, Y., Oppermann, H., Tekin, T., Kraft, J., Sidorov, V., Yin, X., Bauwelinck, J., Neumeyr, C., & Soares, F. (2019). 3D silicon photonics interposer for Tb/s optical interconnects in data centers with double-side assembled active components and integrated optical and electrical through silicon via on SOI. In IEEE/ECTC Proceedings, pp. 1052–1059. 150. Iwai, T., Sakai, T., Mizutani, D., Sakuyama, S., Iida, K., Inaba, T., Fujisaki, H., Tamura, A., & Miyazawa, Y. (2019). Multilayer glass substrate with high density via structure for all inorganic multi-chip module. In IEEE/ECTC Proceedings, pp. 1952–1957. 151. Tanaka, M., Kuramochi, S., Dai, T., Sato, Y., & Kidera, N. (2020). High frequency characteristics of glass interposer. In IEEE/ECTC Proceedings, pp. 601–610. 152. Ding, Q., Liu, H., Huan, Y., & Jiang, J. (2020). High bandwidth low power 2.5D interconnect modeling and design. In IEEE/ECTC Proceedings, pp. 1832–1837.

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Chapter 4

Multiple System and Heterogeneous Integration with TSV-Less Interposers

4.1 Introduction In this chapter, the recent advances in multiple system and heterogeneous integration with TSV (through-silicon via)-less interposers (organic interposes or 2.3D IC integration) will be presented. Unlike 2.5D IC integration discussed in Chap. 3, the TSV-interposer is replaced by the TSV-less interposers, which are meanly constructed by the fan-out packaging technology. The very first 2.5D IC integration papers were published by CEA-Leti [1] at IEEE/ECTC 2005 and [2] at IEEE/ECTC 2006. In general, for 2.5D, the chips/HBMs (high bandwidth memories) are supported by a TSV (through-silicon via)-interposer and then on a build-up package substrate as shown in Fig. 4.1c [1–15]. The very first product (Virtex-7 HT family) of 2.5D was shipped in 2013 by Xilinx and TSMC. The 2.5D with TSV-interposer is known for extremely high-performance and high-density applications and high cost and has been discussed in Chap. 3 of this book. The very first 2.1D IC integration papers were published by Shinko [16] at IMAPS International Symposium on Microelectronics 2013 and [17] at IEEE/ECTC 2014. In general, for 2.1D, thin film layers or fine metal linewidth and spacing (L/S) RDLs (redistributed-layers)-substrate are fabricated directly on the top-layer of a build-up package substrate and become a hybrid substrate [16–25] as shown in Fig. 4.1a. In this case, the yield loss of the hybrid substrate, especially the fine metal L/S coreless substrate is difficult to control and can be very large because of the flatness of the build-up package substrate. As of today, 2.1D is not in high volume manufacturing and will be out of the scope of this book. The very first 2.3D IC integration structural patent was granted to MediaTek [26], Fig. 4.2a. A similar structural patent was also granted to STATSChipPac [27], Fig. 4.2b. The very first 2.3D IC integration paper was published by STATSChipPac [28] at IEEE/ECTC 2013. Their motivation is to replace the TSV-interposer (2.5D IC integration) with a fan-out fine metal L/S RDL-substrate (or organic interposer). The structure consists of a build-up package substrate [or high-density interconnect © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging, https://doi.org/10.1007/978-981-19-9917-8_4

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4 Multiple System and Heterogeneous Integration with TSV-Less Interposers Fine Metal L/S RDL-Substrate (Organic Interposer) μbump Thin-Film Layers CHIP

CHIP

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(b)

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Fig. 4.1 Multiple system and heterogeneous integration. a 2.1D. b 2.3D. c 2.5D/3D IC integration

(a)

EMC

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Fig. 4.2 2.3D patents. a MediaTek. b STATS ChipPAC

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(HDI)], solder joints with underfill [29, 30], and a fine metal L/S RDL-substrate, Fig. 4.1b. Since then, there have been many publications [31–62]. Yoon et al. [28], Chen et al. [31], Yip et al. [32], Lin et al. [33], Yu [34] are with fan-out chip-first packaging process while [35–62] are with fan-out chip-last packaging process. For 2.3D IC integration with fan-out chip-last packaging process [35–62], the fine metal L/S RDL-substrate and the build-up package substrate are fabricated separately. Kurita et al. [35], Motohashi et al. [36], Huemoeller and Zwenger [37], Lim et al. [38], Jayaraman [39], Suk et al. [40], You et al. [41], Lin et al. [42–44], Chang et al. [45], Lai et al. [46], Fang et al. [47], Cao [48], Cao et al. [49], Lee et al. [50], Yin, et al. [51], and Li et al. [52] build the fine metal L/S RDL-substrate first, then bond the chips on the fine metal L/S RDL-substrate, underfilling and EMC (epoxy molding compound) molding, and finally assemble the module (chips + fine metal L/S RDL-substrate) on the build-up package substrate—chip-bonding first process (Fig. 4.3). On the other hand, in Miki, Murayama, et al. [53, 54], Kim [55], and Lau et al. [56, 57], Chou et al. [58], Chen et al. [59], Lau [60], Peng, et al. [61, 62], the fine metal L/S RDL-substrate and the build-up package substrate are first interconnected into a hybrid substrate through the solder joints that are enhanced with underfill [56–60] or through the interconnection-layer [61, 62]. Then, test the combined substrate and make sure it is a known-good hybrid substrate. Finally, they bond the chips on the known-good hybrid substrate: - chip-bonding last process (Fig. 4.4). In this case, the Design and Simulation of the Structure

Wafer bumping

Fine Metal L/S RDL-Substrate

Build-up Package Substrate

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Chip to Fine Metal L/S RDL-Substrate bonding

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Assemble the module (chip + Fine metal L/S RDL-substrate) on the Package Substrate

Solder Ball Mounting and Dicing

Reliability Testing and Data Analysis

Fig. 4.3 2.3D fan-out chip-last process (chip-bonding first)

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Design and Simulation of the Structure

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Hybrid Substrate Fabrication and Testing

Chip to Known-Good Hybrid Substrate bonding

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Reliability Testing and Data Analysis Fig. 4.4 2.3D fan-out chip-last process (chip-bonding last)

yield loss of the hybrid substrate especially the fine metal L/S RDL-substrate is easier to control and smaller. Also, there is a very little chance of losing the known-good dies. Furthermore, the logistic is simpler; after receiving the known-good hybrid substrate from the substrate houses, the OSAT (outsourced semiconductor assembly and test) houses just bond the chips/HBMs on the known-good hybrid substrate. In this chapter, the recent advances of 2.3D IC heterogeneous integration will be discussed. Some of the challenges (opportunities) of 2.3D IC integration will also be presented. Finally, some recommendations of 2.3D IC integration will be provided. Some fundamentals and recent advances in fan-out technology will be briefly mentioned first.

4.2 Fan-Out Technology The biggest difference between fan-out technology [28, 31–180] and flip-chip technology is that fan out needs to fabricate the redistribution layers (RDLs), but flip chip uses the substrate with RDLs. There are at least two different formations of fan-out RDLs, namely: chip-first [63–82] and chip-last (or RDL-first) [35–62, 82–92]. For

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chip-first, there are also two different kinds: (a) chip-first with die face-down and (b) chip-first with die face-up.

4.2.1 Chip-First with Die Face-Down Figure 4.5 shows an example of heterogeneous integration of four chips and four capacitors using chip-first with die face-down fan-out packaging [78]. The package size is 10 × 10 mm, which consists of one 5 × 5 mm chip, three 3 × 3 mm chips, and four 0402-capacitors. The process flow is very simple. First, the chips are picked up and then placed face down on a temporary carrier with a double-sided thermal release tape. Then, the carrier and the chips are molded with epoxy molding compound (EMC) using the compression method and then post-mold cured (PMC) before removing the carrier and the double-sided tape. Next comes building the RDLs from the original Al or Cu pads on the chips. Finally, solder balls are mounted and the whole reconstituted carrier (with chips, EMC, RDLs, and solder balls) is diced into individual packages as shown Fig. 4.5. There are two RDLs in each package. Each RDL consists of the photosensitive polyimide dielectric layer and the Cu conductor layer. Because an under bump metallization (UBM)-less pad has been used for the solder ball, the Cu conductor layer of RDL2 is thicker than that of RDL1. This is because of the Cu consumption due to solder reflow and during operation. For detailed information on the design, materials, process, fabrication, and reliability of the PCB assembly of the heterogeneous integration package, please see [78]. The temporary carrier for this case is a 300 mm-wafer. Figure 4.6 shows an example of heterogeneous integration of mini-light-emitting diodes (LEDs) for an RGB display using chip-first with die face-down fan-out packaging [83]. The mini-LEDs are red (R) (125 × 250 × 100 μm), green (G) (130 × 270 × 100 μm), and blue (B) (130 × 270 × 100 μm). The spacing among the RGB mini-LEDs is 80 μm, the pixel-to-pixel spacing is also ~80 μm, and the pixel pitch is 625 μm. There are two RDLs in each package. A printed circuit board (PCB) (132 mm × 77 mm) is designed and fabricated for the drop testing that is done on the mini-LED package. Thermal cycling of the mini-LED surface mount device (SMD) PCB assembly is also performed by a nonlinear temperature- and time-dependent finite-element simulation [83]. The temporary carrier is a 510 mm × 515 mm panel.

4.2.2 Chip-First with Die Face-Up Figure 4.7 shows an example of chip-first with die face-up fan-out packaging [77]. The chip size is 10 mm × 10 mm and the package size is 13.42 mm × 13.42 mm. The process steps of chip first with die face up is a little more complicated than that of chip first with die face down.

276

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers SiP (10mmx10mm)

Reconstituted Wafer with 629 SiPs

3x3mm

3x3mm

5x5mm

3x3mm

300mm

Capacitor EMC

Chip RDL1 RDL2

VC1

V12

UBM-less pad Solder Ball

Metal L/S = 10μm

EMC 3mmx3mm

3mmx3mm

Solder Joint PCB Fig. 4.5 Heterogeneous integration of four chips and four capacitors (chip first die face down with a temporary wafer process)

On the device wafer, one is to fabricate a Cu stud (about 15 μm) on the original (Al or Cu) contact pads and the other is to laminate a die-attach film (DAF) on the bottom side of the device wafer. The function of the DAF is to attach (adhere) the die solidly onto the temporary carrier to avoid die shift caused by compression molding of the EMC; and the function of the Cu stud is to protect the original contact pads during backgrinding of the EMC, which is done to expose the Cu stud. On the temporary glass wafer carrier, a light-to-heat conversion (LTHC) layer (about 1 μm) is spin coated onto the temporary glass wafer carrier. The chips are picked and placed face up on the LTHC carrier. In order to cure the DAF, a bonder with temperature and pressure should be used. The DAF process is carried out at 120 °C (both bond head and bond stage) with a bond force of 2 kg for 2 s for

4.2 Fan-Out Technology

277

R 75μm

G

LED B

EMC(ABF) G

R

B

25μm 10μm

25μm 25μm Solder Mask

RDLs Solder Joint

Solder Mask

Cu Pad

PCB

Not-to-Scale

Driver Chip

Solder Joint

LED EMC (ABF) R

G

B

R

G

B

RDLs

PCB

Fig. 4.6 Heterogeneous integration of mini-LEDs for an RGB display (chip first die face down with a temporary panel process)

each chip. The temporary carrier, therefore, will expand during the pick and place process. However, during patterning/photolithography of the RDLs, the reconstituted carrier (temporary carrier + chips + EMC) is at room temperature. Therefore, pitch compensation caused by the DAF heating is needed [77]. After EMC dispensing, compression molding, and then PMC are done. Then, the following are done: (1) backgrinding of the EMC to expose the Cu stud; (2) fabricating the RDLs; (3) and mounting the solder balls. Those processes are then followed by scanning a laser through the temporary glass carrier to the LTHC layer—the LTHC layer becomes powder, and the temporary glass carrier is then very easy to remove. Finally, the reconstituted wafer (with chips, EMC, RDLs, and solder balls) is diced into individual packages. There are three RDLs in each package and the minimum metal line width (L) and spacing (S) are 5 μm. For detailed information on the design, materials, process, fabrication, and reliability of the chip-first with die face-up fan-out packaging, please see [77]. TSMC’s integrated fan-out (InFO) [73, 74] used for Apple’s application processor is one of the chip-first with die face-up fan-out processes.

278

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers Solder balls on package (13.42mm x 13.42mm)

RDLs Chip corner

300mm-wafer

Chip (10mm x 10mm)

Package

CHIP Cu Stud

Contact Pad

RDL1 V12 UBM-less Pad

325 @13.42 x13.42mm packages

VC1 RDL2

RDL3

V23

Metal L/S of RDL1 = 5µm Metal L/S of RDL2 = 10µm Metal L/S of RDL3 = 15µm

Solder ball

Solder Joint

Chip

EMC

PCB

Fig. 4.7 A chip-first with die face-up packaging process for a large chip

4.2.3 Die Shift Issues In [77], we determined the die shift caused by compression molding by measuring the position of each chip before and after molding. (The die size is 10 mm × 10 mm and the minimum metal L/S are 5 μm.) Fig. 4.8 shows the statistical plots of the x-position die shift and y-position die shift caused by the compression molding. It can be seen that because of the DAF (which solidly holds the chip to the carrier), the die shift (can be controlled within ± 3 μm) is too small to be an issue when making the RDLs. In general, in order to avoid the die shift issues, the chip-first with die face-down process is used mostly for smaller die (≤ 5 mm × 5 mm) and larger metal L/S RDLs (≥ 10 μm), and chip-first with die face-up processing is used for larger die (≤ 12 mm × 12 mm) and smaller metal L/S RDLs (≥ 5 μm).

4.2 Fan-Out Technology

279

Because of the Die-attach film (DAF), the die-shift is very small!

Fig. 4.8 Die shift measurement of a chip-first with die face-up packaging process

4.2.4 Warpage Issues Another critical issue for chip-first fan-out packaging is warpage [75, 80]. There are at least two kinds of warpage about which we should be concerned: (1) the warpage of the reconstituted carrier should not be too large to affect the downstream fan-out process flow such that the reconstituted carrier cannot be placed/operated on the RDL equipment; and (2) the warpage of the individual fan-out package should not be too large so that it affects the quality and reliability of the surface mount technology (SMT) assembly, such as causing a stretched solder joint, for example. For detailed discussion and the allowable warpage for chip-first fan-out packaging, please see [75, 80]. For the chip-first with die face-up example [77], it is interesting to note that the warpage of the temporary carrier + chips + EMC right after PMC has been found to be in the shape of a smiling face [80]. The average maximum warpage is equal to 609 μm, Fig. 4.9a. The shadow Moiré measurement result has been found to be in excellent agreement with the simulation result, Fig. 4.9b. The warpage of the temporary carrier + chips + EMC right after backgrinding of the EMC to expose the Cu stud has been found by the shadow Moiré method to have changed from a smiling face to a crying face, Fig. 4.9a. A similar trend has been found by the simulation method, Fig. 4.9b [80].

4.2.5 Chip-Last (RDL-First) The very first papers on chip-last (or RDL-first) technology were published by NEC Electronics Corporation (now Renesas Electronics Corporation) at IEEE/ESTC 2010 [35] and IEEE/ECTC 2011 [36]. In the past few years, many companies such as Amkor, IME, ASE, SPIL, TSMC, Samsung, Shinko, and Unimicron, have also published papers on this topic. The process steps of the chip-last approach are much

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4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Right after Post Mold Cure

592µm (smiling face) Simulation Result Right after Post Mold Cure by Shadow Moire Warpage = 609µm (Smiling Face)

Right after Backgrinding

864 (crying face) Simulation Result Right after Backgrinding by Shadow Moire Warpage = 811.9µm (Crying Face)

(a)

(b)

Fig. 4.9 Warpage measurement and simulation of a reconstituted wafer fabricated by the chip-first with die face-up packaging process

more complicated than those of chip-first with face-up and face-down processes. The chip-last process is meant for high-density and high-performance (and therefore, higher cost) applications. Figure 4.10 shows an example of heterogeneous integration of three chips on a fine-metal L/S RDL-substrate [86, 87]. The size of the large chip is 10 mm × 10 mm, and that of the smaller chip is 5 mm × 7 mm. There are three layers of the RDL-first substrate, and the minimum metal L/S is equal to 2 μm. One practical application of heterogeneous integration is for the application processor chipset, i.e., the large chip could be an application processor and the small chips could be memories. The process steps for fabricating the RDL-first substrate are as follows. First, a LTHC film (1 μm) is slit coated on a temporary rectangular glass carrier (515 mm × 510 mm) and that step is followed by slit coating a photo-imageable dielectric (PID) for the solder mask (or passivation layer) dielectric layer (DL) DL3B, as shown in Fig. 4.10. Then, a Ti/Cu seed layer is formed by physical vapor deposition (PVD). That step is followed by applying photoresist, then using laser direct imaging (LDI), followed by photoresist development. Then, electrochemical deposition (ECD) of Cu is done following stripping off the photoresist and etching off the Ti/Cu to obtain the metal layer (ML) ML3 of RDL3. Those steps are followed by slit coating a PID and then using LDI to obtain the DL (DL23) of RDL3.

4.2 Fan-Out Technology

281 EMC Chip 2

Chip 1

Fine metal L/S RDL-substrate

Cu pillar

DL01 ML1 DL12 ML2 DL23 ML3

Solder Cap Cu Pad Pad RDL1 RDL2 RDL3 Solder Mask

DL3B Solder Joints Not-to-scale

PCB

RDL L/S: ML1 = 2/2μm; ML2 = 5/5μm; ML3 = 10/10μm Bonding pad

ML1

ML2

Underfill

Cu Pillar Solder cap

Chip 20mm Underfill

Chip 1

Chip 2A

Chip 1 (10 x 10)

RDLs

Chip 2B Chip 2A (5 x 7)

20mm

Chip 2B (5 x 7)

ML3 Solder Joint Contact pad

Fine metal L/S RDL-substrate

PCB Cu trace

Fig. 4.10 Heterogeneous integration of three chips on a fine-metal L/S (2 μm-minimum) RDL substrate using a chip-last fan-out panel process

The next steps are sputtering the Ti/Cu seed layer, slit coating the photoresist, using LDI and then developing the photoresist, and then using ECD to deposit the Cu. These steps are followed by stripping off the photoresist and etching off the TiCu seed layer to get the ML (ML2) of RDL2. Next comes slit coating a PID and LDI to get the DL (DL12) of RDL2. The same process steps are repeated to obtain the ML (ML1) and DL (DL01) of RDL1. Next comes sputtering the Ti/Cu, slit coating the photoresist, LDI and develop, and using ECD to deposit the Cu. Those steps are followed by stripping off the photoresist and etching off the TiCu to get the bonding pad (lead) for the chips. The last step in the fabrication of the RDL substrate immediately before the chips-to-substrate bonding is the surface finishing of the Cu bonding pads. Electroless palladium and immersion gold (EPIG) surface finishing is used. The fabrication of the fine-metal L/S RDL substrate is thereby completed. In parallel with the fabrication of the RDL-first substrate, the wafer bumping of the large and small chips with the standard PVD and ECD Cu and solder process is performed. The next step is dicing the wafers into individual chips. For all the chips, the bump consists of the Cu pillar, Ni barrier, and SnAg cap. Now, we are ready to do the chips-to-RDL substrate bonding. It should be noted that, because of the support of the temporary glass carrier, the substrate is very stiff and flat prior to bonding. After the chips-to-RDL substrate bonding is complete, the next step is underfilling and EMC molding. The temporary glass carrier is removed by a laser

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4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

so that we can make the solder resist opening and perform surface finishing on the Cu contact pads. Those steps are followed by solder ball mounting and dicing into individual packages. Finally, the individual package on the PCB is surface mounted. For more information on the design, materials, process, fabrication, and reliability of the PCB assembly of the heterogeneous integration package described above, please see [86, 87]. Figure 4.11 shows an example of a hybrid substrate supporting two chips with microbumps. The hybrid substrate is fabricated by combining a fine metal L/S RDLsubstrate made from a PID and a build-up package substrate through the C4 solder joints and underfill. The large chip could be a system-on-chip (SoC) and the smaller chip could be memory or a memory cube. For more information on the design, materials, process, fabrication, and reliability of the heterogeneous integration of two chips with 50 μm pitch on a hybrid substrate by a fan-out RDL-first panel-level package, please see [56–58]. Figure 4.12 shows the same structure as Fig. 4.11 except the fine metal L/S RDL-substrate is made from an ABF (Ajinomoto Build-Up Film) [59], which will be elaborated in Sect. 4.10 of this chapter. The fine-metal L/S substrate and the build-up package substrate, or HDI substrate, can also be combined through an interconnect layer [61, 62] into a hybrid substrate. This is very similar to [56–59] except the C4 solder joint and underfill are replaced by an interconnect layer as shown in Fig. 4.13. For more information on the design, materials, process, fabrication, and reliability of the heterogeneous integration of three chips on a hybrid substrate with an interconnect layer by a fan-out RDL-first panel-level package, please read Sect. 4.10 of this book. Again, Chip1 could be a SoC and Chip2A and Chip2B could be memories or memory cubes.

Chip 1 DL01 ML1 DL12 ML2 DL23 ML3

Chip 2

μbump

Underfill

C4 bump Solder Mask

Fine metal L/S RDL-substrate

Cu Solder

Pad Fine metal L/S RDLsubstrate

Chip 1

Chip 2

Build-up substrate

Underfill Pad

CHIP Solder

μbump

Underfill

Cu

Build-up Package Substrate

RDLs

C4

Underfill

Build-up Layers

Solder Mask

Solder Ball

Build-up Package Substrate

Fig. 4.11 Heterogeneous integration of two chips on a hybrid substrate made by PID

4.2 Fan-Out Technology

283

Underfill

Chip 1

Chip 2

Fine metal L/S RDL-substrate Build-up substrate

Solder

50μm

CHIP

Underfill

Cu

RDLs C4 bump

Underfill

Build-up Layers

Build-up Package Substrate

Fig. 4.12 Heterogeneous integration of two chips on a hybrid substrate made by ABF 20mm

Flip chip with μbump Fine metal L/S RDL-substrate

Chip 2B

Underfill

Chip 2A

Chip 2A

20mm

Chip 1

Chip 1

Hybrid Substrate

InterconnectLayer

Build-up substrate or HDI

CHIP 1

CHIP 2A Cu-pillar Solder

ML1 ML2

PAD

Underfill RDLs

Solder Ball Hybrid Substrate

Via filled with conductive paste

InterconnectLayer

8-Layer HDI

Fig. 4.13 Heterogeneous integration of three chips on a hybrid substrate (a combination of the fine-metal L/S RDL-substrate by chip-last fan-out panel process and the build-up package substrate with the interconnect layer)

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Underfill

Laser

TiA

PD

Fiber Fibers (Optical)

ASIC/Switch

EMC

Driver

Electrical

284

Fiber

μbump Heat Sink

Heat Spreader/Sink EIC PIC (Driver/TiA) (Laser/PD)

ASIC/Switch Fine metal L/S RDL-substrate

Fiber Fiber Block

C4 bump

C4 bump

Package Substrate Solder Ball PCB

Fig. 4.14 Heterogeneous integration of switch, EIC, and PIC on a fine-metal L/S RDL substrate for a data center application

4.2.6 Heterogeneous Integration of EIC and PIC Devices Figure 4.14 shows a conceptual layout of a multiple system and heterogeneous integration of a switch, PIC (photonic integrated circuits) and EIC (electronic integrated circuits) devices with a chip-last fan-out process to achieve lower power, higher speed, smaller form factor, and lower cost needed to achieve a higher data bandwidth for data center applications. It can be seen that the package substrate is supporting the fine-metal L/S RDL-substrate, which is supporting the ASIC/switch, EIC and PIC with μbumps. This structure is believed to be lower cost than the 2.5D IC integration of a switch, PIC and EIC devices with a through-silicon via (TSV) interposer shown in Figs. 1.37 and 3.42.

4.2.7 Antenna-In-Package (AiP) In [181], TSMC demonstrated that the InFO_AiP (integrated fan-out antenna-inpackage) for high-performance and compact 5G millimeter-wave system integration is superior than that of solder-bumped flip-chip AiP on substrate: (1) in the 28 GHz frequency range, InFO RDLs transmission loss (0.175 dB/mm) is 65% less than

4.3 Patent Issue

285 Patch Antenna Polymer protection layer Insulation layer Light to heat conversion layer Dielectric Polymer

Patch Antenna Ground RDL1

RF CHIP

TIV

Epoxy molding compound

RDL2

Solder Ball

Through InFO via

Die attach film

(a)

(b) Fig. 4.15 a TSMC’s AiP patent: US 10,312,112, June 4, 2019 (Chip-first and die face-up). b Unimicron’s heterogeneous integration of baseband and AiP patent: TW 1,209,218, November 1, 2020 (Chip-first and die face-down)

that on a flip-chip substrate trace (0.288 dB/mm), and (2) in the 38 GHz frequency range, the transmission loss for InFO RDLs (0.225 dB/mm) is 53% less than that (0.377 dB/mm) on a flip-chip substrate trace. TSMC’s patent on InFO_ AiP is shown in Fig. 4.15a—it is a chip-first with die face-up fan-out process. Figure 4.15b shows the Unimicron patent of the heterogeneous integration of AiP and a baseband chipset using a chip-first with die face-down fan-out process. It can be seen that the radio frequency (RF) chip and the baseband chipset (modem application processor and the dynamic random-access memory [DRAM]) are placed side-by-side with RDLs and coupled with the antenna patches. A heat spreader/sink is also proposed, which is almost impossible using a chip-first with die face-up fan-out process.

4.3 Patent Issue The two fundamental fan-out 2.3D IC integration patents were granted to MediaTek [26] in 2010, Fig. 4.2a, and STATSChipPac [27] in 2016, Fig. 4.2b. These two patents are very similar, but with very different objectives. MediaTek filed their patent (US 7,838,975) on February 12, 2009, and was granted the patent on November 23, 2010

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4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

[26]. Their objective is to use fan-out packaging technology to enlarge the fine-pitch pad on a chip to release the pressure on the package substrate with larger pad pitch. STATSChipPac filed their patent (US 9,484,319) on December 23, 2011, and was granted the patent on November 1, 2016 [27]. Their objective is using the fan-out RDL-substrate (interposer) to replace the TSV-interposer, i.e., TSV-less interposer.

4.4 2.3D IC Integration with Fan-Out (Chip-First) Packaging 4.4.1 Fan-Out (Chip-First) Packaging The very first fan-out (chip-first) patent was filed by Infineon on October 31, 2001 [63]. The very first technical papers were also published (at IEEE/ECTC 2006 [64] and IEEE/EPTC 2006 [65]) by Infineon and their industry partners: Nagase, Nitto Denko, and Yamada. Since then, there are many publications in fanout with chip-first [66–82].

4.4.2 STATSChipPac’s 2.3D eWLB (Chip-First) At ECTC2013, STATSChipPac proposed [28] using the chip-first fan-out flip chip (FOFC)-eWLB (embedded wafer level ball grid array) to make the RDLs for the chips to perform mostly lateral communications, Fig. 4.16. Their objective is to replace the TSV-interposer, microbump, and underfill with the fine metal L/S RDL-substrate.

4.4.3 MediaTek’s Fan-Out (Chip-First) During ECTC2016, MediaTek [31] proposed similar TSV-less interposer RDLs fabricated with fan-out chip-first wafer-level packaging technology as shown in Fig. 4.17. Instead of the C4 bumps like Fig. 4.16, they used a microbump (Cu-pillar + solder cap) to connect the bottom RDL to a 6-2-6 package substrate. Recently, they demonstrated the reliability of their structure [32].

4.4.4 ASE’s FOCoS (Chip-First) During ECTC2016, ASE [33] proposed using the fan-out wafer-level packaging technology (chip-first and die-down on a temporary wafer carrier and then over

4.4 2.3D IC Integration with Fan-Out (Chip-First) Packaging

287

TSV interposer µbump Underfill-2 Analog Logic

Underfill-1 C4 bump

Solder Ball Package Substrate The µbump, underfill-1, and TSV-interposer are eliminated. The RDLs are made by fan-out technology.

Underfill-2

RDLs

EMC Logic

Analog

C4 bump

Solder Ball Package Substrate Fig. 4.16 STATS ChipPAC (chip-first) RDLs μbump Package substrate

RDLs

μbump

Package substrate

Fig. 4.17 MediaTek: fanout (chip-first)

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4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

CoWoS Die1

ASEís FOCoS EMC

Die2

Microbumps + Underfill

EMC

Die1

TSV-interposer + RDLs

Die2 RDLs

Package Substrate

C4 bumps

Solder Balls

Package Substrate

Underfill

Underfill

Solder Balls

C4 bumps

EMC EMC Chip1

RDLs

C4 bumps

Chip2 Chip1 RDLs C4 bumps

Chip2

Package Substrate

Solder Balls

RDLs

Package Substrate

Underfill 18

Fig. 4.18 ASE: fanout (chip-first)

molded by the compression method) to make the RDLs for the chips to perform mostly lateral communications as shown in Fig. 4.18; the technology is called fanout wafer-level chip-on-substrate (FOCoS). The TSV interposer, wafer bumping of the chips, fluxing, chip-to-wafer bonding, and cleaning, and underfill dispensing and curing are eliminated. The bottom RDL is connected to the package substrate using under bump metallurgy (UBM) and the C4 bump. Basically, MediaTek’s [31] and ASE’s [33] are very similar to STATSChipPac’s [28].

4.4.5 TSMC’s InFO_oS and InFO_MS (Chip-First) Figure 4.19 schematically illustrates TSMC’s fan-out RDL-substrates for heterogeneous integrations [34]. Figure 4.19a shows the integrated fan-out on substrate (InFO_oS) for heterogeneous integration, which eliminates the micro bumps, underfill, and TSV interposer with the RDLs. Figure 4.19b shows the integrated fanout with memory on substrate (InFO_MS), which is meant for higher performance applications.

4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging CHIP1

289

EMC

CHIP2

RDLs

C4 Bump

InFO_oS (Integrated Fan-Out on Substrate)

Package Substrate

(a)

Solder Ball

PCB

Memory Cube with TSVs EMC

Logic

Memory Cube without TSV

TSV RDL

Package Substrate

C4 Bump

Logic

EMC

Package Substrate

(b) PCB

InFO_MS (Integrated Fan-Out with Memory on Substrate)

Fig. 4.19 TSMC: fanout (chip-first)

4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging For 2.3D integration with fan-out (chip-last or RDL-first) packaging, the fine metal L/S RDL-substrate and the build-up package substrate are fabricated separately. Then, there are at least two different assembly processes: (a) first bond the chips/HBMs on the fine metal L/S RDL-substrate and then assemble the module (chips/HBMs + fine metal L/S RDL-substrate) on the build-up package substrate (Fig. 4.3), Sects. 4.5.1, 4.5.2, 4.5.3, 4.5.4, 4.5.5 and 4.5.6, and (b) first combine the fine metal L/S RDL-substrate and the build-up package substrate into a hybrid substrate and test to make sure it is a good substrate, and then bond the chips/HBMs on the known-good hybrid substrate (Fig. 4.4), Sects. 4.5.7, 4.5.8 and 4.5.9.

4.5.1 NEC/Renesas’ Fan-Out (Chip-Last or RDL-First) Packaging The very first papers on fan-out RDL-first (chip-last) were published by NEC Electronics Corporation (now Renesas Electronics Corporation) at IEEE/ESTC 2010

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4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

[35] and IEEE/ECTC 2011 [36]. The FTI (feedthrough interposer) used in their SMAFTI (SMArt chip connection with FeedThrough Interposer) is a film with ultrafine linewidth and spacing RDLs. The dielectric of the FTI is usually a SiO2 or polymer, and the conductor wiring of the RDLs is Cu. The FTI not only supports the RDLs underneath within the chip, but it also provides support beyond the edges of the chip. Area array solder bumps are mounted at the bottom-side of the FTI, which are to be connected to the next-level of interconnect such as the package substrate. Epoxy molding compound (EMC) is used to embed the chip and support the RDLs and solder bumps. Since then, there are many chip-last (RDL-first) papers [37–62, 84–92].

4.5.2 Amkor’s SWIFT (Chip-Last) Since 2015 Amkor have been promoting their silicon wafer integrated fan-out technology (SWIFT) [37–39], which is very similar to [35, 36]. Figure 4.20 shows a typical cross section of SWIFT. It can be seen that the TSV-interposer is replaced by the fine metal L/S RDL-substrate, which is fabricated by a fan-out chip-last (or RDL-first) packaging process.

Underfill (UD)

Cu

Die

Solder

UF

bump RDLs

RDLs

RDL1

RDL2

RDL3

D1 D2

Solder Ball

BGA Solder Ball Cu-Pad

Fig. 4.20 Amkor: fanout (chip-last) and chip bonding first

4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging

291

4.5.3 Samsung’s Si-Less RDL Interposer (Chip-Last) During ECTC2018, Samsung [40, 41] proposed the use of chip-last or RDL-first fan-out packaging to eliminate the TSV-interposer for high performance computing heterogeneous integration applications (Fig. 4.21). First of all, the RDLs are built on a bare glass—either in a wafer or a panel format. In parallel, wafer bumping of the logic and HBM chips will be done. Then, the following processes are done: fluxing, chip-to-wafer or chip-to-panel bonding, cleaning, underfill dispensing and curing. Those steps are followed by EMC compression molding. Then, backgrinding the EMC, chips, and HBM cube and C4 wafer bumping are done. After those steps, one can attach the whole module on the build-up package substrate. Finally, solder ball mounting and lid attachment are done. Samsung called the resulting structure a Si-less RDL interposer [40]. Samsung’s test vehicle is shown in [41]. The RDL interposer is 55 mm × 55 mm and consists of 5-RDLs including bonding layer, signal and ground layers. Samsung showed that the thermal cycling performance of the C4 solder joint in the organicinterposer module is better than that of the TSV-interposer module [40]. This is because the thermal expansion mismatch between the silicon-interposer and build-up package substrate is larger than that between the organic-interposer. CoWoS C4 Bump

Si-less RDL-Interposer

TSV-Interposer

HBM

Logic

Package Substrate

Underfill

µBump

EMC

RDL µBump C4 Solder Bump

Fig. 4.21 Samsung: fanout (chip-last) and chip bonding first

Solder Package Ball Substrate

292

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

4.5.4 TSMC’s Multilayer RDL Interposer (Chip-Last) Figure 4.22 shows TSMC’s multilayer RDL-interposer for heterogeneous device and module integration [42–44]. The structure consists of: (a) the chips are attached on an organic or inorganic RDL interposer with microbumps and underfill, (b) the RDL interposer is attached to a build-up package substrate with C4 bump with underfill, and (c) the package substrate is attached to a PCB with BGA (ball grid array) solder ball. Figure 4.23 shows some images of the assembly. It can be seen that the chips and DRAM are attached to a multilayer RDL-interposer with μbumps and then attached to a package substrate with C4 bumps. There are 6 RDLs with various via structures such as stager vias, two stacking vias, and four stacking vias. Recently, they demonstrated the reliability of their structure (Fig. 4.23) [43] and integrated both a large amount of high density integrated passive devices (IPDs) and fine pitch Si-based connection block of convenient IP migration (Fig. 4.24) [44].

Package Substrate

Package Substrate

Fig. 4.22 TSMC: Fanout (chip-last) and chip bonding first

4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging

Test Item

(a)

Test Conditions and Results

Precon + TCC (-65oC ↔ 150oC)

1300 cycles

Passed

Precon +TCG (-40oC ↔ 125oC)

2400 cycles

Passed

Precon + uHAST (110oC/85%RH)

264 hrs

Passed

Procon + HTS (150oC)

1000 hrs

Passed

Test Item

(b)

293

Test Conditions and Results

Precon + TCC (-65oC ↔ 150oC)

1000 cycles

Passed

Precon +TCG (-40oC ↔ 125oC)

2500 cycles

Passed

Precon + uHAST (110oC/85%RH)

264 hrs

Passed

Procon + HTS (150oC)

1000 hrs

Passed

Fig. 4.23 TSMC Reliability data: a SoC and 2HBM chiplets. b Two chiplets

CoWoS-R (Organic interposer)

(a) New Organic Interposer (CoWoS-R+)

De-cap integrated passive device (IPD) (b)

Si-based connection block for convenient IP migration

Fig. 4.24 TSMC: a Organic interposer (CoWoS-R), b New organic interposer (CoWoS-R+ )

294

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

4.5.5 ASE’s FOCoS (Chip-Last) Figures 4.25 and 4.26 show ASE’s FOCoS with fan-out chip-last process [45–51]. First, they fabricate an RDL-interposer on a temporary glass carrier. It can be seen from Fig. 4.25 that there are at least 4 RDLs with stacked vias and non-stacked vias. In parallel, they perform the wafer bumping for the microbump. Then, they perform the chip-to-RDL-wafer bonding, underfilling, and molding. It is followed by debonding the temporary carrier, C4 bump mounting, and dicing into individual modules. Finally, the module is attached on a build-up package substrate. Recently, they have demonstrated the electrical, thermal, mechanical and reliability performance of their fan-out chip-last 2.3D packaging [48–51] and renamed the FOCoS to FOBGA (fan-out ball grid array) [49].

CoWoS

FOCoS

Stacked Vias

Non-stacked Vias

Cross sections of FOCoS Fig. 4.25 ASE: fanout (chip-last) and chip bonding first

4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging

295

Fig. 4.26 ASE: fanout (chip-last) and chip bonding first

4.5.6 SPIL’s Large Size Fan-Out Chip-Last 2.3D During IEEE/EPTC 2021, SPIL presented a paper on 2.3D IC integration [52] with a very large package size (6000 mm2 ) and a 6-layer fine metal L/S = 2 μm (minimum) RDL-substrate as shown in Fig. 4.27. They demonstrated the qualifications such as the thermal cycling test and high temperature storage life test of their test vehicle.

4.5.7 Shinko’s 2.3D Organic Interposer (Chip-Last) Figure 4.28 shows Shinko’s 2.3D organic interposer for high performance computing applications [53, 54]. It can be seen from Fig. 4.29 that Shinko use NCF (nonconductive film) as the underfill between the organic interposer and build-up package substrate. Also, between the organic RDL interposer and the build-up package substrate, they use Sn-Bi solder alloy instead of the SnAgCu. In fabricating the organic RDL interposer they use a temporary carrier and a rigid layer, so they don’t have to switch to another temporary carrier before chip-to-panel bonding. Figure 4.28 shows the SEM images of the organic interposer (thin-film layer). It can be seen that

296

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Fig. 4.27 SPIL: fanout (chip-last) and chip bonding first

the metal L/S are 2/2 μm with stacking vias. In parallel, they perform the wafer (Cupillar + solder cap) bumping. The pitch is 40 μm for the large chip and 55 μm for the small chip. The chip-to-panel bonding is by TCB (thermocompression bonding). Figure 4.29 shows the cross section of the assembly between the organic interposer and the build-up package substrate. It can be seen that the interconnect material is SnBi.

4.5.8 Samsung’s Cost-Effective 2.3D Packaging (Chip-Last) At ECTC 2021, Samsung presented a cost-effective 2.3D packaging by using fanout panel level RDL [55]. Their fine metal L/S (7/8 μm) RDL-substrate consists of a 3-layer coreless substrate with 2 RDLs and an eight-layer (3-2-3) package substrate as shown in Fig. 4.29.

4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging

297

Fig. 4.28 Shinko: fanout (chip-last) and chip-bonding last

4.5.9 Unimicron’s 2.3D IC Integration (Chip-Last) The feasibility of the design, materials, process, and fabrication of a heterogeneous integration of two chips with 50-μm pitch on a 2.3D hybrid substrate (Fig. 4.30) by a fan-out RDL-first panel-level packaging has been demonstrated [56–58]. In order to increase throughput, the fine metal L/S (2 μm) RDL-substrate has been fabricated on a temporary glass panel. The hybrid substrate has been fabricated by soldering the fine metal L/S RDL-substrate on a build-up package substrate and underfilled. The 50-μm pitch microbumped chips are bonded to the hybrid substrate and underfilled. Reliability of the assembly has been demonstrated by the thermal cycling simulation. It is found that: (a) the creep response of the microbump solder joints between the chips and the RDL substrate is larger than that between the RDL substrate and the build-up package substrate and (b) the maximum creep responses pre cycle are too small and localized to create reliability concerns in most operating conditions for mobile products. The hybrid substrate has been shown to pass the drop test [58]. In [56–58], the dielectric material for the fine metal L/S RDL-substrate is PID (photoimageable dielectric). Recently, the dielectric material has been changed to ABF (Ajinomot build-up film), which leads to much flatter metal traces of the RDLs as shown in Fig. 4.31 [59]. More details of this structure can be found in section xxx. The fine-metal L/S RDL-substrate and the build-up package substrate (HDI substrate) can also be combined through an interconnect layer [61, 62] into a hybrid

298

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Fig. 4.29 Samsung: fan-out (chip-last), chip-bonding last Underfill

Chip 1 DL01 ML1 DL12 ML2 DL23 ML3

Chip 2

μbump

Underfill

Cu

Solder Cap Pad RDL1 RDL2 RDL3

C4 bump Underfill Solder Mask Pad

Chip 2

Chip 1

Fine L/S RDL-substrate Build-up substrate

Solder

Cu-pillar

Build-up Package Substrate C4

CHIP

RDLs Underfill

Build-up Layers Solder Mask Not-to-scale

Solder Ball

Build-up Package Substrate

Fig. 4.30 Unimicron: fan-out (chip-last) and chip-bonding last. PID dielectric

4.6 Other 2.3D IC Integration Structures

299

Underfill

Chip 1

Chip 2

Fine metal L/S RDL-substrate Build-up substrate

Solder

50μm

CHIP

Underfill

Cu

RDLs C4 bump

Underfill

Build-up Layers

Build-up Package Substrate

Fig. 4.31 Unimicron: fan-out (chip-last) and chip-bonding last. ABF dielectric

substrate. This is very similar to [56–59] except the C4 solder joint and underfill are replaced by an interconnect layer as shown in Fig. 4.32. For more information on the design, materials, process, fabrication, and reliability of the heterogeneous integration of three chips on a hybrid substrate with an interconnect layer by a fan-out RDL-first panel-level package, please read Sect. 4.8

4.6 Other 2.3D IC Integration Structures In this section, other 2.3D (TSV-less interposer) structures will be briefly presented.

4.6.1 Shinko’s Coreless Organic Interposer In 2012, Shinko proposed to use the coreless package substrate to replace the TSVinterposer as shown in Fig. 4.33. For sure, the cost of making the coreless substrate is much lower than that in making the TSV and RDLs (which require semiconductor equipment). Warpage could be an issue.

300

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers 20mm Flip chip with μbump Fine metal L/S RDL-substrate

Chip 2B Chip 2A

Chip 2A

20mm

Chip 1

Chip 1

InterconnectLayer

Build-up substrate or HDI

CHIP 1

Solder Ball

Hybrid Substrate

CHIP 2A Cu-pillar Solder

ML1 ML2

Underfill

PAD

Underfill RDLs

Via filled with Interconnectconductive paste Layer

8-Layer HDI

Fig. 4.32 Unimicron: fan-out (chip-last) and chip-bonding last. Interconnection-layer Fig. 4.33 Shinko’s 2.3D with coreless substrate

Coreless Substrate Chip

Chip

(a) Build-up substrate

Memory Cube

Coreless Substrate Chip

(b) Build-up substrate

4.6 Other 2.3D IC Integration Structures

301

Fig. 4.34 Intel’s Knights Landing

4.6.2 Intel’s Knights Landing Figure 4.34 shows Intel’s Knights Landing CPU with Micron’s HMC (hybrid memory cube), which have been shipping to Intel’s favorite customers since the second half of 2016. It can be seen that the 72-core processor is supported by 8 multi-channel DRAMs (MCDRAM) based on Micron’s HMC technology. Each HMC consists of 4 DRAMs and a logic controller (with TSVs), and each DRAM has > 2000 TSVs with Cu-pillar bump with solder cap. The CPU and the DRAM + logic controller stack is attached to an organic package substrate.

4.6.3 Cisco’s Coreless Organic Interposer Figure 4.35 shows a heterogeneous integration designed and manufactured with a large organic interposer (TSV-less interposer) with fine-pitch and fine-line interconnections by Cisco [182]. The organic interposer has a size of 38 mm × 30 mm × 0.4 mm. The minimum line width, spacing, and thickness of the front side and back side of the organic interposer are the same and are, respectively, 6 μm, 6 μm, and 10 μm. It is a 10-layer high density organic interposer (substrate) and the via size is 20 μm. The major manufacturing steps for making the organic interposer are the same as those for the organic build-up package substrate. These include (a) plating

302

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers HBM_Functional

HBM_Mechanical

Organic Interposer

Cu Micro-Pillar

C4 Bumps

HBM

ASIC (FPGA)

HBM_M

Features

ASIC (FPGA) Organic Interposer 1-2-1 Package Substrate

Organic Interposer

Cu wiring (Dielectric)

SAP (Organic)

Frontside Pad size/pitch

30/55μm

Frontside wiring L/S /T (min) 6/6/10μm No. of routing layers

10

Wiring layer via size

20μm

PTH size/pitch/depth

57/150/200μm

Backside pad size/pitch

100/150μm

Backside wiring L/S/T (min)

6/6/10μm

Fig. 4.35 Cisco’s 2.3D with organic interposer

through-hole (PTH) generation and filling for the core layer, (b) circuitization of the core layer, and (c) building Cu wiring layers on two sides of the core layer with SAP. A high-performance application-specific IC (ASIC) die measured at 19.1 mm × 24 mm × 0.75 mm is attached on top of the organic interposer along with four highbandwidth memory (HBM) dynamic random-access memory (DRAM) die stacks. The 3D HBM die stack with a size of 5.5 mm × 7.7 mm × 0.48 mm includes one base buffer die and four DRAM core dice that are interconnected with TSVs and fine-pitch micro-pillars with solder cap bumps. The pad size and pitch of the front side of the organic interposer are 30 μm and 55 μm, respectively. Figure 4.35 shows a top view of the organic interposer manufactured and the cross-sectional view of the good solder joint made between the HBM die-stacks and the organic interposer [182].

4.6.4 Amkor’s SLIM Figure 4.36 shows Amkor’s SLIM (silicon-less integrated module) [37, 39, 183, 184]. The key difference between SWIFT and SLIM is that hybrid RDL is used for SLIM. In order to lower the metal L/S (go down to submicron), the hybrid RDL is fabricated with inorganic RDL first and organic RDL last. Figure 4.36 shows

4.6 Other 2.3D IC Integration Structures

RDL2

Solder RDL1

Cu

303

bump

RDL3

Cu Pillar

EMC

Solder

Chip RDL1: 0.5μm L/S Capillary Underfill

RDL2: 5µm L/S RDL1

RDL2

Solder Ball

RDL3

RDL3 Cu Pillar

Solder

Solder Ball

Fig. 4.36 Amkor’s SLIM

the 0.5 μm metal L/S (RDL1) made by the semiconductor process and equipment (inorganic RDL method) and RDL2 and RDL3 made by the polymer and ECD (organic RDL method).

4.6.5 Xilinx/SPIL’s SLIT In 2014, Xilinx/SPIL proposed a TSV-less interposer for sliced FPGA chips called silicon-less interconnect technology (SLIT) [185]. The upper right-hand corner of Fig. 4.37 shows the new packaging structure along with the old one, which is shown in the left-hand corner. It can be seen that the TSVs and most of the interposer are eliminated and only the four RDLs needed for performance, mainly, the lateral communication of the sliced FPGA chips, remain.

4.6.6 SPIL’s NTI During ECTC2016, SPIL proposed the NTI (non-TSV interposer) for 2.3D IC integration with coreless inorganic interposer [186]. First, they used the 65 nm process

304

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Xilinx/TSMCís CoWoS Devices (Cannot see)

Metal Contacts

Xilinx/SPILís SLIT

Metal Layers

Si Chip

Cu Pillar Micro Bump

Cu Pillar Solder

Solder

Si Chip

Micro-bump

4RDLs 4RDLs

C4

TSV and most interposer are eliminated! Only RDLs remained.

Lower cost Better performance Lower profile

TSV

Interposer

65nm RDLs C4/Contact via

C4

C4

TSVinterposer

Package Substrate Solder Ball

No entire TSV fabrication module No thin wafer handling technology No novel backside TSV revealing process No multiple inspection & metrology steps for TSV fabrication & backside TSV revealing steps.

Fig. 4.37 Xilinx/SPIL’s SLIT

technology to make the RDLs with a 0.4 μm-pitch minimum on a wafer. Then, they performed the chip-to-wafer bonding on the RDLs, underfilled the gap between the chips and the RDL interposer and molded the chips with EMC. Figure 4.38 shows the cross section of the assembly. It can be seen that the chips are attached to the inorganic interposer with microbump (Cu-pillar + solder cap). Then, the RDLs interposer is attached to the build-up package substrate with C4 bump.

4.6.7 Samsung’s TSV-Less Interposer Recently, Samsung proposed a new TSV-less interposer, Fig. 4.39, [187, 188]. They used the chip-last (RDL-first) method to fabricate the TSV-less interposer (RDLsubstrate) on a temporary glass carrier with PECVD (plasma enhanced chemical vaper deposition) for the SiO2 dielectric layers and PVD (physical vaper deposition) + ECD (electrochemical deposition) for the Cu conductor metal layers.

4.7 Summary and Recommendations

CHIP1

CHIP2

305

µbump on the top-RDL CHIP

Package Substrate Cu

Solder Balls

CHIP1

CHIP2

Solder Cu RDLs

Package Substrate

C4 bump with UBM at the bottom-RDL RDLs UBM

BGA C4 bump

Pad on substrate

Bottom side optical image post backside silicon removal

Fig. 4.38 SPIL’s NTI

4.7 Summary and Recommendations Some important results and recommendations are summarized in the follows. • 2.5D IC integration (with TSV-interposer supporting the chips/HBMs and then on a build-up package substrate) is meant for extremely high-density, highperformance and high-cost applications and has been in production since 2013. It has been discussed in Chap. 3. • 2.1D IC integration is meant to replace the 2.5D IC integration by building the thin-film layers on top of the build-up package substrate. However, because of the flatness of the build-up package substrate the yield loss of 2.1D is very large and thus it is not in high volume manufacturing. • 2.3D IC integration is meant to replace the 2.5D IC integration by combining the fine metal L/S RDL-substrate and the build-up package substrate into a hybrid substrate. Currently, it is in small volume production, and it will be in high volume production by the end of 2022. Eventually, 2.3D IC integration will take away some of the market shares from 2.5D IC integration. • The key differences on chip size, number of HBM, metal L/S and number of layer of the organic/TSV interposer, total package profile, package substrate size, process steps, cost, density, performance, and application among the 2.1D, 2.3D, and 2.5D have been shown in Table 4.1.

306

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

PECVD, PVD, ECD, etc. Temporary Carrier

TSV-less Interposer

Fig. 4.39 Samsung’s TSV-less interposer

• The structural patents and original papers of 2.3D IC integration have been provided. Their motivations have also been presented. • 2.3D IC integration with fan-out (chip-first) process is simpler and lower cost than that with fan-out (chip-last or RDL-first) process. However, the advantages of 2.3D IC integration with fan-out (chip-last) process are for: (a) larger die size, (b) larger package size, (c) less die shift issue, and (d) finer metal L/S of the RDLs. • For 2.3D IC integration with fan-out (chip-last), there are at least two different processes, namely chip-bonding first (Fig. 4.3) and chip-bonding last (Fig. 4.4). Because of the straightforward logistic and less chance to through away the known-good dies, it is recommended to use the chip-bonding last process (Fig. 4.4). • The ever increase demands for larger size of the fine metal L/S RDL-substrate and the build-up package substrate post great challenges (opportunities) on designs, materials, processes, and assemblies in high-yield manufacturing. Due to the large size of the structure and the thermal expansion mismatch among the structural elements, reliability could be an issue.

4.8 2.3D IC Heterogeneous Integration with ABF

307

Table 4.1 Comparison between 2.1D, 2.3D, and 2.5D for chiplet design and heterogeneous integration packaging 2.1D

2.3D (Chip-Last)

2.5D

SoC size

≤ 15 × 15 mm

≤ 20 × 20 mm

≤ 25 × 25 mm

No. of HBMs

4

6

8

RDL interposer

Cu traces in polymer

Cu traces in polymer

Cu traces in SiO2

RDL (Metal L/S) interposer

≥ 2 μm

≥ 2 μm

< 1 μm

RDL (Layer) interposer

≤3

≤6

≤8

Vertical interconnect

Via in RDL interposer

Via in RDL interposer

TSV

C4 bump

None

Yes

Yes

Underfill (chip/interposer)

Yes

Yes

Yes

Underfill (interposer/sub.)

None

Yes

Yes

Total package profile

Tall

60-80 μm taller

60-80 μm taller

Package substrate size

Big

Bigger

Biggest

Process steps

Much

More

Most

Density

High

Higher

Highest

Performance

Highest

High

Higher

Decoupling capacitor

Discrete IPD

Discrete IPD

Embedded DTC

Cost

High

Higher

Highest

Applications

HPC etc

HPC, data center

HPC, high bandwidth data center

• The ever increase demands for smaller feature size (down to submicron) of the fine metal L/S RDL-substrate post great challenges (opportunities) on designs, materials, and processes in high-yield manufacturing. • Besides the 2.3D IC integration with fan-out packaging technology, there are other 2.3D IC integration structures such as those given by Shinko (coreless substrate), Cisco (organic interposer), Amkor (SLIM), and SPIL (NTI).

4.8 2.3D IC Heterogeneous Integration with ABF In [56–58] we have developed a hybrid substrate based on a photoimageable dielectric (PID) for heterogeneous integration of multiple chips. Unfortunately, it yields uneven (not flat) metal layers of the fine metal L/S/H RDL-substrate. In this section,

308

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

instead of the PID, we use the Ajinomoto build-up film (ABF) as the dielectric material to fabricate the fine metal L/S RDL-substrate of the hybrid substrate [59]. It is fabricated by a fan-out chip-last (RDL-first) process on a large temporary glass panel (515 mm x 510 mm). The new hybrid substrate (with a minimum L/S/H = 2 μm/2 μm/3 μm) with the ABF yields a much flatter metal layer of the RDLs and thus much better electrical performance. This new hybrid substrate is supporting the heterogeneous integration of one large chip (10 × 10 mm) and one smaller chip (5 × 5 mm). The thermal reliability of the structure will be demonstrated by simulation. Some recommendations will be provided.

4.8.1 The Structure Figure 4.40 schematically shows the structure under consideration. The two chips (Chip 1 and Chip 2) are supported by a hybrid substrate, which is fabricated by combining the fine metal L/S/H RDL-substrate (20 mm × 15 mm × 53 μm) and the build-up package substrate (23 mm × 23 mm × 1.3 mm) through the C4 (controlled collapse chip connection) solder joints and underfill. The fine metal L/S/H RDL-substrate is shown in Fig. 4.41 with dimensions. It can be seen that there are three RDLs, each consisting of a dielectric layer (DL) and a Cu metal layer (ML). The DL material of [56–58] is PID and of this study is an ABF with the materials properties shown in Table 4.2. The L/S/H of ML1 (metal layer 1) are 2 μm/2 μm, of ML2 are 5 μm/5 μm, and of ML3 are 10 μm/10 μm, which are the same as [56–58]. The dielectric layer between the contact pad and ML1 (DL01)

Chip 1

Not-to-scale

DL01 ML1 DL12 ML2 DL23 ML3

Chip 2

μbump

Underfill Cu

C4 bump

Solder Mask

Pad Pad RDL1 RDL2 RDL3

Underfill Pad

Build-up Package Substrate

Solder Mask

Not-to-scale

Fig. 4.40 Cross section of the structure

Solder Cap

Solde r Ball

4.8 2.3D IC Heterogeneous Integration with ABF

309

is 3.5 μm, DL12 (dielectric layer between ML1 and ML2) is 10 μm, and DL23 (dielectric layer between the ML2 and ML3) is 7.5 μm, which are different from [56, 57] as shown in the table of Fig. 4.41. All the vias between the metal layers are 20 μm, which is also different from [56–58]. DL01 ML1 DL12 ML2 DL23 ML3

Pad V01 V23

Solder Mask Pad diameter = 36μm; Pad thickness = 8μm Solder Mask opening = 80μm; Thickness (DL3B) = 5μm Key Elements of RDL

Line width (L) / Spacing (S)

ML1 (Metal layer 1)

2/2μm

DL01 (Dielectric layer between the contact pad and ML1) V01 (Via opening between contact pad and ML1)

RDLs

RDL1

RDL2

RDL3

RDL1 RDL2 Pad RDL3

V12

DL3B

Thickness (H) PID

ABF

3μm

3μm

NA

3μm

3.5μm

NA

10μm

20μm

ML2 (Metal layer 2)

5/5μm

5μm

8μm

DL12 (Dielectric layer between ML1 and ML2)

NA

6μm

10μm

V12 (Via opening between ML1 and ML2)

NA

20μm

20μm

ML3 (Metal layer 3)

10/10μm

5μm

8μm

DL23 (Dielectric layer between ML2 and ML3)

NA

4μm

7.5μm

V23 (Via opening between ML2 and ML3)

NA

18μm

20μm

Fig. 4.41 Dimensions of the fine metal L/S RDL-substrate

Table 4.2 ABF material properties Items

ABF (RDL-Substrate)

ABF (Build-up Substrate)

Curing condition, °C for min

200 for 90

190 for 90

CTE (25 − 150 °C), 10–6 /°C

37

39

CTE (150 − 240 °C), 10–6 /°C

98

117

Tg, °C

156

153

Dielectric constant (Dk), 5.8 GHz

3.2

3.2

Loss tangent (Df), 5.8 GHz

0.011

0.017

Young’ modulus (23 °C), GPa

7.5

5.0

Tensile strength (23 °C), GPa

125

98

Elongation (23 °C), %

5.4

5.6

310

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers 50 15 22

40 5 5

775

Unit: μm

Si-Wafer

20 32 40

Not-to-Scale

Fig. 4.42 Wafer bumping of test chips

4.8.2 Test Chips The dimensions of Chip 1 are 10 mm × 10 mm × 150 μm and of Chip 2 are 5 mm × 5 mm × 150 μm. There are 3592 daisy-chained pads on Chip 1 and 1072 daisychained pads on Chip 2. The minimum pitch of these chips is 50 μm. The material and geometry of the microbump (μbump) of both chips are the same (Fig. 4.42): the Ti/Cu (0.1/0.2 μm) UBM (under bump metallurgy) pad size is 32 μm-diameter, the passivation (PI2) opening is 20 μm-diameter, the Cu-pillar is 32 μm-diameter and 22 μm-tall, the SnAg solder cap is 15 μm with a barrier (Ni = 3 μm).

4.8.3 Wafer Bumping The process flow of the wafer bumping of the test chips is shown in Fig. 4.42. The cross sections of the μbumps are shown in Fig. 4.43.

4.8.4 Fine Metal L/S/H RDL-Substrate (Organic Interposer) The top-view and bottom-view of the fine metal L/S/H RDL-substrate are shown in Fig. 4.44a and b, respectively. It can be seen that there are 4664 pads for the μbump

4.8 2.3D IC Heterogeneous Integration with ABF

311

Microbumps

Si

50μm Ni

SnAg

Cu

Si Fig. 4.43 μbumps on test chips

from the chips and there are 4039 pads for the C4-bumps from the build-up package substrate. The process in fabricating the fine metal L/S/H RDL-substrate is shown in Fig. 4.45. A sacrificial layer (1 μm-thick light-to-heat conversion released film) is slit coating on a temporary glass panel (515 mm × 510 mm × 1.1 mm) and then a Ti/Cu seed layer is PVD (physical vapor deposition) on the top. The contact pad can be obtained by photoresist, laser direct imaging (LDI), development, ECD (electrochemical deposition) Cu, and stripping off the photoresist. Then, laminate a 12.5 μm-thick raw ABF with nano-filler (Table 4.2) on the whole panel. There are two operating stages of the ABF: (1) at the first stage, the temperature is 120 °C for 30 s at vacuum condition and then press (0.68 MPa) for 30 s with the temperature and vacuum on, and (2) at the second stage, the temperature is 100 °C and press (0.58 MPa) for 60 s. The first DL (dielectric layer) DL01 (3.5 μm-thick) of RDL1 is drilled by a UV laser to obtain the blind via. It is followed by PVD the Ti/Cu, photoresist, LDI and development, ECD the Cu, strip off the photoresist, and etch off the TiCu to obtain the first ML (metal layer) ML1 of RDL1. DL12 and ML2 of RDL2, and DL23 and ML3 of RDL3 can be obtained by repeating the same process steps.

312

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers 20mm

Site for Chip 1

Site for Chip 2

10mm

5mm

10mm

(a)

15mm

5mm

(c)

1072 pads 3592 pads

(b)

15mm

20mm

Number of pads = 4039 Pitch = 225μm Pad size = 105μm Pad opening = 80μm

(d)

Fig. 4.44 RDL-substrate. a Top view. b Bottom-view. c Fabricated top-view with glass removed and Ti/Cu etched. d Fabricated bottom-view In parallel, make the build-up substrate with solder bump Released Film & PVD Seed Layer Temporary Glass Carrier

ML1 : Photoresist & LDI Build-up substrate

Pad : Photoresist & LDI ML1 : Plating Cu Hybrid substrate formation

Pad : ECD (Plating) Cu ML1 : Strip Photoresist & Etch TiCu

Temporary Glass Carrier

Pad : Strip-off Photoresist

DL01 : Ajinomoto Build-Up Film (ABF)

Repeat the above processes to get ML2 and ML3 DL3B : PID Lamination & LDI Underfill and glass debond to expose the Cu-pad

DL01 : UV laser drill

ML1 : TiCu (Seed Layer) Sputtering

Surface Finish (ENEPIG)

Temporary Glass Carrier

Fig. 4.45 RDL-substrate process flow

Build-up substrate

4.8 2.3D IC Heterogeneous Integration with ABF

ML1 (2/2/3μm) ML2 (5/5/8μm) ML3 (10/10/8μm)

V12

313

V01 V23

ML1 (2/2/3μm)

ML2 (5/5/8μm)

ML3 (10/10/8μm)

Fig. 4.46 Images of the cross section of the fine metal L/S/H RDL substrate with ABF

The 5 μm-thick solder mask (passivation) can be obtained by laminating a 10 μmthick raw dry film PID and LDI. Then, the surface is finishing with electroless nickel electroless palladium immersion gold (ENEPIG). The fabrication of the fine metal L/S/H RDL substrate is completed. The top-view and bottom view of the RDL-substrate are shown in Fig. 4.44c and d, respectively. The SEM image of the RDL substrate is shown in Fig. 4.46. Table 4.3 shows the metal L, S, and H from design and fabrication. For RDL1, L = 2.4 μm (not 2 μm), S = 1.8, 2.0 μm (not 2 μm), and H = 3.2, 3.5 μm (not 3 μm). For RDL2, L = 5.1, 5.0 μm (not exactly 5 μm), S = 4.8, 4.4 μm (not exactly 5 μm), and H = 7.2, 7.4 μm (not exactly 8 μm). For RDL3, L = 9.9, 10.3 μm (very close to 10 μm), S = 9.4, 9.2 μm (not exactly 10 μm), and H = 8.2, 8.6 μm (close to 8 μm). Thus, there is room for improvements, e.g., better estimation of compensation of photoresist, LDI, ECD Cu, Cu etching, etc. Figure 4.47 shows the image of the fine metal L/S/H RDL-substrate with PID as dielectric material. It can be seen that the metal lines are not as flat as those shown in Fig. 4.46 with ABF as dielectric material.

4.8.5 Build-Up Package Substrate Figure 4.48 shows the top-view and bottom-view of the 2–2-2 build-up package substrate (23 mm × 23 mm × 1.3 mm) which is also made from an ABF with SiO2 normal filler (Table 4.2), and its cross section is shown in Fig. 4.49. The C4 bumps

314

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Table 4.3 L/S/H comparison: design vs. fabricate RDLs

Items

Design (μm)

Measured (μm)

Metal of RDL1 (ML1)

Linewidth (L)

2

2.4, 2.4, …

Spacing (S)

2

1.8, 2.0, …

Thickness (H)

3

3.2, 3.5, …

Linewidth (L)

5

5.1, 5.0, …

Spacing (S)

5

4.8, 4.4, …

Thickness (H)

8

7.2, 7.4, …

Linewidth (L)

10

9.9, 10.3, …

Spacing (S)

10

9.4, 9.2, …

Thickness (H)

8

8.2, 8.6, …

Metal of RDL2 (ML2)

Metal of RDL3 (ML3)

Fig. 4.47 Image of the fine metal L/S RDL substrate with PID

are fabricated by stencil printing a Sn3Ag0.5Cu solder paste with a 29-μm-thick stainless-steel stencil on the build-up substrate. During solder-reflow process, due to the surface tension of the molten solder, which creates smooth truncated spherical 30-μm diameter solder bumps [56–58].

4.8 2.3D IC Heterogeneous Integration with ABF

315

23mm

23mm

23mm

23mm

0.225mm

(a)

(b)

(c)

Fig. 4.48 a Panel for fabricating the build-up substrate. b Top view. c Bottom-view 225μm 30μm Build-up layer

Top-side

Build-up layer

Build-up package substrate

Build-up layer Bottom-side

Build-up layer

Fig. 4.49 Cross section of the build-up substrate

316

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Fig. 4.50 Shadow Moire warpage measurement of build-up substrate (BU), fine metal L/S RDL substrate on glass carrier RDL(G), and fine metal L/S RDL substrate on organic carrier RDL(O)

4.8.6 Warpage Measurements The warpage of the build-up package substrate (BU), fine metal L/S RDL substrate with glass carrier RDL (G), and fine metal L/S RDL substrate with organic carrier RDL (O) at various temperatures has been measured by the shadow Moiré method via the TherMoire Platform. The results are shown in Fig. 4.50. It can be seen that the warpage of BU and RDL (G) is very small. However, the warpage of RDL (O) is very large compared with the others. (This is because the thermal expansion mismatch between the glass carrier and the RDL substrate is smaller than that between the organic carrier and the RDL substrate.) Thus, in this study, the hybrid substrate will be formed by the combination of the build-up package substrate and the fine metal L/S RDL substrate with the temporary glass carrier.

4.8.7 Hybrid Substrate The hybrid substrate is fabricated by combining (assembling) the fine metal L/S/H RDL-substrate (Fig. 4.46) and the build-up package substrate with C4 solder bumps [13] (Fig. 4.49). In order to remove the contamination from the Cu pads of the fine metal L/S/H RDL-substrate, first apply water-soluble flux (Wf-6070SP-6-1) at the fine metal L/S/H RDL-substrate. It is followed by placing the RDL-substrate on a hot plate and heating up to 190 °C for 2.5 min and cooling down then rinsing with warm water. Then, the flux (WF 6317) is applied on the build-up package substrate. The bonding profile of the assembly is shown in Fig. 4.51. It can be seen that the bond head temperature at contact is 170 °C, the bond stage temperature is 175 °C, and the bonding temperature is 285 °C for 6 s. The bonding force is reduced from 600 to 300 g during bonding. Flux cleaning is by hot water shower. A typical sample of the hybrid substrate assembly is shown in Fig. 4.52. It can be seen the top views of the hybrid substrate with and without the temporary glass carrier. It can also be

4.8 2.3D IC Heterogeneous Integration with ABF

317

Temperature (oC)

Force (g) 902 600

464

Bond Force

391

297

318

Bond Head Temperature

-5

245 172

-307

Bond Head Height -609 437

99 2960

5484

8008

10532

Time (ms) Fig. 4.51 Hybrid substrate bonding profile

seen the cross section which consists of the build-up substrate, RDL-substrate, and the C4 solder joints. The hybrid substrate is properly assembled. Figure 4.53 shows the metal lines (ML1, ML2, and ML3) in the hybrid substrate fabricated with the ABF (top) and the PID in [56–58] (bottom). It can be seen that the metal lines with ABF are much flatter than those with PID. However, the hybrid substrate fabricated with ABF is thicker than that with PID.

4.8.8 Final Assembly The final assembly of the heterogeneous integration of chips on the hybrid substrate is performed by chip-to-substrate bonding. Figure 4.54 shows the top view and cross section view of the assembly.

4.8.9 Finite Element Simulation and Results (A) Assumptions: The first assumption of the analysis is to use an equivalent block (53 μm-thick) to represent the fine metal L/S/H RDL-substrate as shown in Fig. 4.55. The material property of the structure is shown in Table 4.4. The equivalent Young’s modulus, equivalent CTE (coefficient of thermal expansion), and equivalent Poisson’s ratio are calculated as below. For equivalent Young’s modulus:

318

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers Hybrid Substrate

Hybrid Substrate Build-up Substrate

Cross Section

Fine metal L/S RDLsubstrate with glass removed and seed layer etched

Fine metal L/S RDL-substrate with glass carrier

Site for Chip1

Build-up Substrate

Site for the Chip2

C4-bump Fine metal L/S RDL-substrate

Build-up Substrate

Fine metal L/S RDL-substrate

Build-up Substrate

C4-bump

Build-up Layer

Fig. 4.52 Hybrid substrate, top view and cross-sectional view

121 × (8 + 3 + 8 + 8) + 7.5 × (3.5 + 10 + 7.5) + 7.5 × 5 = 65.32 GPa (8 + 3 + 8 + 8) + (3.5 + 10 + 7.5) + 5 For equivalent CTE: 16.3 × (8 + 3 + 8 + 8) + 37 × (3.5 + 10 + 7.5) + 37 × 5 = 26 × 10−6 /o C (8 + 3 + 8 + 8) + (3.5 + 10 + 7.5) + 5 For equivalent Poisson’s ratio: 0.34 × (8 + 3 + 8 + 8) + 0.3 × (3.5 + 10 + 7.5) + 0.3 × 5 = 0.32 (7 + 3 + 8 + 8) + (3.5 + 10 + 7.5) + 5

4.8 2.3D IC Heterogeneous Integration with ABF

319

ML1 RDLs

ML2 ML3 C4 Bump

Solder Mask

Cu Pad Build-up Substrate

ML1 ML2 ML3

RDLs C4 Bump Solder Mask Cu Pad Build-up Substrate

Fig. 4.53 Images of the fine metal lines in the hybrid substrate. Top (ABF). Bottom (PID) Build-up substrate Underfill Fine metal L/S RDL-substrate

Solder

50μm

CHIP

Underfill

Cu

RDLs

Chip 1

Chip 2

C4 bump

Underfill

Build-up Layers

Build-up Package Substrate

Fig. 4.54 Top view and cross section view of the assembly

320

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Chip 1 32μm

Chip 2 Cu

Underfill Solder

μbump

150μm 22μm 18μm

Cu pad layer = 8μm DL01 = 3.5μm ML1 =3μm DL12 =10μum ML2 = 8um DL23 = 7.5μm ML3 = 8μm DL3B = 5μm

20mm

Equivalent Block (Metal + Dielectric + SR)

53μm 80μm 30μm

C4 bump

Underfill

SR(PCB)

Cu

21μm

80μm

1.3mm

Build-up Package Substrate

23mm

Fig. 4.55 Cross section of structure for modelling

Table 4.4 Material properties for modelling Material

Young’s modulus (GPa)

Poisson’s ratio

CTE (10–6 /°C)

Silicon

131

0.278

2.8

Copper

121

0.34

16.3

Solder

49 − 0.07 T(°C)

0.3

21 + 0.017 T(°C)

Underfill

4.5

0.35

50

ABF

7.5

0.3

37

Solder mask (RDL)

7.5

0.3

37

Equivalent block

65.32

0.32

26.45

Solder mask (PCB)

4.1

0.3

39

PCB

Ex = Ey = 22; Ez = 10

0.28

αx = αy = 18; αz = 70

The second assumption is that the 2D generalized plane-strain method is adopted in this study. (B) Finite Element Modelling: Figure 4.56 shows the cross section of structure for simulation. The bumps between the chips and the fine metal L/S/H RDL-substrate are μbumps (A, B, C, and D) and the bumps between the RDL-substrate and the build-up substrate are C4-bumps (E and F). Figure 4.57 shows the finite element model. It can be seen that finer meshes have been used for the critical μbumps B and C. All the other bumps are not shown in Fig. 4.57.

4.8 2.3D IC Heterogeneous Integration with ABF

A

321

B

Chip 1

C

D

Chip 2

RDL-Substrate

Build-up Substrate

E

F

A and B are the μbumps under Chip 1. C and D are the μbumps under Chip 2. E and F are the solder joints under the RDL-substrate. 32μm Cu-pillar

RDL-Substrate (Equivalent block)

22μm

80μm 32um μbumps under chips

RDL-Substrate (Equivalent block)

μbumps: A

Underfill

Solder joint under RDL

B

C

18μm Cu

SR (PCB) 53μm

PCB

Solder joints: E

D

F

Fig. 4.56 Structure, μbump, and solder joint

A

B

Chip 1

C

Chip 2

D

RDL-Substrate

Build-up Substrate

E

F

A and B are the μbumps under Chip 1. C and D are the μbumps under Chip 2. E and F are the solder joints under the RDL-substrate. RDL-Substrate

Chip 2

Chip 1

PCB

Gap (100μm)

Chip 1

Chip 2

Underfill μbump B

μbump C

Fig. 4.57 Finite element model for structural analysis

Equivalent Block

322

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Fig. 4.58 Thermal boundary condition

The material properties of the structural elements are shown in Table 4.4. It can be seen that all the materials are assumed to be constants except the Sn3Ag0.5Cu solder, which is assumed to obey the generalized Garofalo creep equation [29, 30]: dε/dt = 500, 000 [sinh (0.01σ )]5 exp[−5800/T (k)], where ε is the strain, σ is the stress in Pa, and T is the temperature in Kelvin. The CTE and Young’s modulus of the solder are, respectively, 21.3 + 0.017 T and 49 − 0.07 T, and T is the temperature in Celsius. The kinetic boundary condition is thermal cycling. Five temperature cycles are executed, and the temperature profile is: −40 ↔ 85 °C. The cycle time is 60 min and the ramp-up, ramp-down, dwell-at-hot, and dwell-at-cold are each 15 min (Fig. 4.58). (C) Simulation Results—Hysteresis Loops: It is important to study the creep responses for multiple cycles by observing when the hysteresis loops become stabilized. Figure 4.59 shows the creep shear strain—shear stress hysteresis loops at μbump C. It can be seen that the creep shear strain versus shear stress loop is stabilized after the second cycle. (D) Simulation Results—Deformations: The deformed shape and undeformed shape of the structure are shown in Fig. 4.60. It can be seen at 450 s (85 °C), the hybrid substrate expands more than the chips and the structure is deformed in a concave shape (smiling face), Fig. 4.60a. At 2250 s (−40 °C), the hybrid substrate shrinks more than the chips and the structure is deformed into a convex shape (crying face), Fig. 4.60b. (E) Simulation Results—Accumulated Creep Strain: The accumulated creep strain contour distributions at the critical μbump solder joints A, B, C, and D and the critical C4-bump solder joints E and F are shown in Fig. 4.61 and the maximum

4.8 2.3D IC Heterogeneous Integration with ABF

323

24 16 Shear Stress (MPa)

8 0 -8

μbump C

-16 -24 -32 -40 -48 -56 -1

0

1 2 Creep Shear Strain

3

4

(x10-2)

Fig. 4.59 Creep shear strain—shear stress hysteresis loops of μbump C

Fig. 4.60 Deformed shape (color contours) and un-deformed shapes (dark lines) of the structure at a 450 s and b 2250 s

accumulated creep strain time history at these locations are shown in Fig. 4.62. It can be seen that the maximum accumulated creep strain occurs near the corner of all the joints A, B, C, D, E, and F. Also, the maximum accumulated creep strain per cycle in the μbump solder joints A, B, C, and D is at least four times larger than that in the C4-bump solder joints E and F. This is because the thermal expansion mismatch between the chips and the RDL substrate is larger than that between the RDL substrate and the build-up package substrate. Also, the solder volume of the μbump solder joints is smaller than that of the C4-bump solder joints. Furthermore, the stiffness of the μbump could be larger

324

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers RDL-Substrate

Build-up Substrate μbump under Chip 1

μbump under Chip 2

Solder bump under RDL

A

C

E

B

D

F

A

C

B

D

(a)

E

(b) F

Fig. 4.61 Accumulated creep strain contours at various μbumps and solder joints

than that of the C4-bump. The maximum accumulated creep strain per cycle in the μbump joints is 5.89% and it occurs at a very small area. Thus, this structure should be reliable for most operating conditions. (F) Simulation Results—Creep Strain Energy Density: The creep strain energy density contour distributions at the μbump joints A, B, C, and D and the C4bump solder joints E and F are shown in Fig. 4.63 and the maximum creep strain energy density time history at these joints are shown in Fig. 4.64. It can be seen that the maximum creep strain energy density occurs near the corner of the joints A, B, C, D, E, and F. Also, the maximum creep strain energy density per cycle in the μbump joints A, B, C, and D is at least six times larger than that in the C4-bump solder joints E and F. Again, this is because the thermal expansion mismatch between the chips and the RDL substrate is larger than that between the RDL substrate and the build-up package substrate. The maximum creep strain energy density per cycle in the μbump joints is only 2.61 MPa and it occurs at a very small area. All the other areas have very small creep strain. Again, this structure should be reliable for most operating conditions.

4.8 2.3D IC Heterogeneous Integration with ABF

325 RDL-Substrate

Build-up Substrate μbump C

Accumulated Creep Strain

0.300 μbump A = 5.42%/cycle μbump B = 4.74%/cycle μbump C = 5.89%/cycle μbump D = 5.38%/cycle C4-bump E = 0.996%/cycle C4-bump F = 1.003%/cycle

0.250 0.200

μbump A, D

0.150

μbump B 0.100

C4-bump E, F 0.050 0.000 0

2000

4000

6000

8000

10000

12000

14000

16000

1800

Time(s)

Fig. 4.62 Maximum accumulated creep strain time history at various μbumps and solder joints RDL-Substrate

Build-up Substrate μbump under Chip 1

μbump under Chip 2

Solder bump under RDL

E

A

C

B

D

A

C

E

B

D

F

(a)

F

(b)

Fig. 4.63 Creep strain energy density contours at various μbumps and solder joints

326

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers RDL-Substrate

Creep Strain Energy Density (MPa)

Build-up Substrate μbump C 14.00

μbump A = 2.36MPa/cycle μbump B = 2.01MPa/cycle μbump C = 2.61MPa/cycle μbump D = 2.34MPa/cycle C4-bump E = 0.32MPa/cycle C4-bump F = 0.32MPa/cycle

12.00 10.00 8.00

μbump A, D

6.00

μbump B

4.00

C4-bump E, F

2.00 0.00 0

2000

4000

6000

8000

10000

12000

14000

16000

18000

200

Time(s)

Fig. 4.64 Maximum creep strain energy density time history at various μbumps and solder joints

4.8.10 Summary and Recommendations Some important results and recommendations are summarized as follows. • The design, materials, and assembly process of the fine metal L/S/H RDLsubstrate with ABF have been provided and the SEM images have been demonstrated the RDL-substrate has been properly done. • The SEM images of the build-up package substrate have been demonstrated the substrate and the C4 bumps have been properly done. • A hybrid substrate with ABF for heterogeneous integration of two chips has been developed. This hybrid substrate is fabricated by combining the fine metal L/S/H RDL-substrate and the build-up package substrate with solder joints which are enhanced with underfill. The dielectric material for the fine metal L/S/H RDLsubstrate is the ABF instead of the PID used in [56–58]. • The metal lines of the fine metal L/S/H RDL-substrate made by ABF are much flatter than those made by PID. However, the thickness of the fine metal L/S/H RDL-substrate made by ABF is thicker than that made by PID. • The thermal reliability of a heterogeneous integration of two chips on the hybrid substrate has been performed through finite element method and demonstrated.

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer Chip 1

Chip 2A

Chip 2B

20mm

Flip chip with μbump

Fine metal L/S RDLsubstrate

20mm

Chip 1

Chip 2A

327

InterconnectLayer

Build-up substrate or HDI

Not-to-scale

Solder Ball

Fig. 4.65 Top-view and cross section view of chiplets heterogeneous integration on hybrid substrate with interconnect-layer

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer 4.9.1 The Structure Figure 4.65 schematically shows the top-view and cross section view of a heterogeneous integration of chips on a high-density organic hybrid substrate. It consists of four major parts: (a) the chips with microbumps, (b) the fine metal L/S RDL-substrate or organic interposer (∼ 37 μm), (c) the interconnect-layer (∼ 60 μm), and (d) the HDI printed circuit board (PCB) (∼1 mm) as shown in Fig. 4.66 [61, 62].

4.9.2 Test Chips The test chips for this study are shown in Fig. 4.67. It can be seen that the size of the large chip (Chip 1) is 10 mm × 10 mm × 150 μm with 3760 area array pads on 90-μm pitch and are daisy chained. The Cu pad size is 50 μm × 50 μm. The size of the small chips (Chip 2A and 2B) is 7 mm × 5 mm × 260 μm with 1512 area array daisy chained pads on 60-μm pitch and the Cu pad size is 44 μm × 44 μm. For all the chips, the Ti/Cu (0.1/0.2 μm) under bump metallurgy (UBM) pad size is 35-μm diameter, the passivation (PI2) opening is 20-μm diameter, the Cu-pillar is 35-μm diameter, and 37-μm tall, the SnAg solder cap is 15 μm with a barrier (Ni = 3 μm).

328

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers Chip 1

Chip 2

Cu

Chips with μbump Solder Cap

5/5μm

2/2μm

60μm

Fine metal L/S RDLsubstrate (~37μm) 300μm’

350μm Conductive Paste

Interconnect- Layer (~60μm)

Via

100μm’

Prepreg

80μm’

350μm

300μm’

HDI PCB (8-layer, ~1mm)

Not-to-scale Fig. 4.66 Key parts of the test package

4.9.3 Fine Metal L/S RDL-Interposer There are three RDLs in the RDL-substrate and each RDL consists of one metal layer (ML) and one dielectric layer (DL). Figure 4.68 shows the definition and value of RDLx, MLx, DLxy, Vxy, and L/S/H. It can be seen that the L/S/H of ML1 are 2/2/2.5 μm and ML2 are 5/5/3.5 μm. ML3 is the contact PAD with a diameter = 300 μm and a thickness = 5 μm. The thickness of DLs DL01, DL12, and DL23 are, respectively, 7.5, 6.5, and 5 μm. The temporary panel for fabricating the RDLsubstrate is shown in Fig. 4.69a. It can be seen that the panel size is 515 mm × 510 mm × 1.1 mm and is made of glass with a coefficient of thermal expansion (CTE) equals 8.5 × 10 -6 /°C. The panel is divided into 18 strips and each strip (132 mm × 77 mm) has 8 (20 mm × 20 mm) RDL-substrates. Thus, in one shot, it can make RDLsubstrates for 432 chips in 144 heterogeneous integration packages. Figure 4.69b and c show the topside and bottom-side of an individual hybrid substrate. On the topside, there are 2 × 1512 + 3760 = 6784 pads, Fig. 4.69b, which are for bonding the chips to the fine metal L/S RDL-substrate. On the bottom-side, there are 2780 Cu pads (300-μm diameter) on 350-μm pitch, Fig. 4.69c. These pads are for the interconnection of the interconnect layer. The key process steps in fabricating the fine metal L/S RDL-substrate are shown in Fig. 4.70. First, a released film (sacrificial layer) is slit coated on a temporary glass carrier (515 mm × 510 mm) and then a Ti/Cu seed layer is formed by PVD. It is followed by photoresist, LDI, and development. Then, electrochemical deposition (ECD) Cu and strip off the photoresist and etch off the Ti/Cu to obtain the ML

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

329

Fig. 4.67 Schematic of the test chips

(ML3 or PAD) of RDL3. It is followed by slit coating a PID and LDI to get the DL DL23 of RDL3. Then, sputter the Ti/Cu, photoresist, LDI, develop, and ECD the Cu. It is followed by stripping off the photoresist and etching off the TiCu to get the ML ML2 of RDL2. Repeat the same process steps to obtain the ML ML1 of RDL1 and DLs DL12 and DL01 of RDL2 and RDL1, respectively. Then, sputter the Ti/Cu, photoresist, LDI, and develop, and ECD the Cu. It is followed by stripping off the photoresist and etching off the TiCu to get the bonding pad (lead) for the chips. Figure 4.71 shows the panel with 144 three-layer (20 mm × 20 mm) RDL-substrates. Figures 4.72 and 4.73 show, respectively, the OM images of the top side of the (L/S = 2/2 μm) RDL-substrate at 500 and 1000 times of magnifications and the typical cross section. Figure 4.74 shows a typical SEM image of the cross section of the RDL-substrate. It can be seen that (a) for ML1, the line widths (L) are 1.91, 1.98, 1.91, and 1.78 μm, which are close to the target (2 μm), the line spacing (S) are 2.31, 2.37, and 2.37 μm, which are reasonably close to the target (2 μm), and the thicknesses (H) are 3.1 and 3.1 μm, which are close to the target (2.5 μm), (b) for ML2, the L are 7.92 and 7.72 μm, which are not close to the target (5 μm), the S are 2.83 and 2.84 μm, which are far from the target (5 μm), and the H is 5.61, which is far from the target (3.5 μm), and (c) for ML3, the H is 8.31 μm, which is

330

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers Pad diameter = 35μm

DL01 ML1

RDL1

V01

DL12

V12

ML2

RDL2 V23

RDL3

PAD

DL23 ML3

Pad thickness = 7μm

Pad

PAD diameter = 300μm

PAD thickness = 5μm

RDLs

Key Elements of RDL

Line width/ Spacing (L/S)

Thickness (H)

Via Dia. (T/B)

ML1 (Metal layer 1)

2/2μm

2.5μm

NA

RDL1

DL01 (Dielectric layer between Pad and ML1)

NA

7.5μm

NA 17/10μm

RDL2

RDL3

V01 (Via opening between contact Pad and ML1)

NA

NA

ML2 (Metal layer 2)

5/5μm

3.5μm

NA

DL12 (Dielectric layer between ML1 and ML2)

NA

6.5μm

NA

V12 (Via opening between ML1 and ML2)

NA

NA

32/25μm

ML3 (Metal layer 3) (PAD)

NA

5μm

NA

DL23 (Dielectric layer between ML2 and ML3)

NA

5μm

NA

V23 (Via opening between ML2 and ML3)

NA

NA

32/25μm

Fig. 4.68 Fine metal L/S 3-layer RDL-substrate

also far from the target (5 μm). Thus, there is room for improvements, e.g., a better estimation of the compensation of photoresist, LDI, ECD Cu, Cu etching, etc.

4.9.4 Interconnect-Layer Figure 4.75 shows the interconnect layer. First, laminate a polyester (PET) on both sides of a prepreg (PP). Then, laser drill vias and print conductive paste into vias. It is followed by stripping off the PET. Both the paste and PP of the interconnect-layer are in β-stage.

4.9.5 HDI PCB The 975-mm-thick HDI PCB has eight layers (Fig. 4.66 and Table 4.5) and is fabricated by the conventional process.

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

331

541.02 mm 510 mm

132 20

515mm

(a)

617.22 mm

20

77

(b)

(c)

Fig. 4.69 a Panel for making the RDL-substrates. RDL-substrate: b Top- and c bottom-view Released Film and Seed Layer Coating Released Film Seed Layer

ML1: Plating Cu ML2: Plating Cu

Pad: Plating Cu

Glass Carrier ML3: Photoresist and LDI ML1: Stripping and Etching ML2: Stripping and Etching ML3 (PAD): Plating Cu

ML3: Stripping and Etching

Pad: Stripping and seed layer etching

DL01: PID Coating and LDI DL12: PID Coating and LDI Organic panel and adhesive Lamination

DL23: PID Coating and LDI ML1: Seed Layer Sputtering

Pad: Seed Layer Sputtering

ML2: Seed Layer Sputtering

ML1: Photoresist and LDI

Pad: Photoresist and LDI

ML2: Photoresist and LDI

Fig. 4.70 Key process steps in making the fine metal L/S RDL-substrate

Glass Debond

332

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Glass Carrier

20mm

20mm

20mm

Chip 2B

MR: X500

MR: X1000

MR: X1000

MR: X1000

Fig. 4.72 OM images of the RDL-substrate (topside)

20mm

Fig. 4.71 Glass panel for making the RDL-substrate

Chip 1

Chip 2A

Bonging pads for Chip 1 and Chip 2A & 2B

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

333

Contact Pad

ML1

ML2

ML3 (PAD)

Fig. 4.73 Typical OM image of the RDL-substrate

1.91

1.91

1.98

1.78 3.1

ML1 2.31

2.37

2.37

2.84

2.83

ML2 7.92

3.1

5.61

7.72

Units in μm

ML3 (PAD)

Fig. 4.74 SEM image of the RDL-substrate

4.9.6 Final Assembly of the Hybrid Interposer First, attach the fabricated RDL-substrate with the glass carrier to an organic panel with an adhesive, and then debond the glass carrier as shown in Fig. 4.76. The key final assembly process steps (Fig. 4.77) of these three substrates are by thermal compression. The alignments and correct positions of these three substrates are fixed by more than ten nails around the four sides of these three panel substrates. After thermal compression (lamination), the PP and conductive paste of the interconnect

334

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Laser Drill Via PP

Prepreg (PP)

PET

Via

Polyester (PET) Lamination Conductive Paste PP

β-Stage PP

Conductive Paste Printing

PP with vias (no conductive paste)

Strip-off PET Interconnect-Layer

PP with vias filled with conductive paste

Fig. 4.75 Interconnect-layer (PP and paste are in β-stage) Table 4.5 HDI PCB materials and spec Category

Layer

HDI

L1

Material

Item

Diameter/Width (μm)

Thickness (μm)

Cu

Pad dia

300

22

PP 1067

Bottom dia

100

55

L2

Cu

Pad dia

200/400

25

PP 1067

Bottom dia

250

60

L3

Cu

Pad dia

400

17

Core

MTH dia

250

254

L4

Cu

Pad dia

400

17

PP 1067

Bottom dia

250

55

L5

Cu

Pad dia

400

17

Core

MTH dia

250

254

L6

Cu

Pad dia

400

17

PP 1067

Bottom dia

250

60

L7 L8

Cu

Pad dia

200/400

25

PP 1067

Bottom dia

100

55

Cu

Pad dia

200

22

SR

Bottom dia

600

20

HDI total thickness

975

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

335

layer are fully cured (C-stage) and the nails are removed. It is followed by dry film lamination at the bottom of the hybrid substrate and then organic panel debonding. It is followed by Cu foil etching, dry film stripping, adhesive plasma etching, and surface finishing.

Organic Panel (100μm )

Adhesive (25μm)

Fig. 4.76 Attach an organic panel to the RDL-substrate and debond the temporary glass carrier

Hybrid Substrate Pre-Bonding

Organic panel debonding

Cu Foil Etching

Hybrid Substrate Lamination and Dry Film Lamination Dry Film Stripping

Fig. 4.77 Process steps in making the hybrid substrate

Adhesive Plasma Etching

Surface Finishing

336

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

ML1

ML2

ML3

Fine metal L/S RDL- substrate Interconnect -layer

Conductive Paste

Prepreg

8-layer HDI

Fig. 4.78 Typical cross section of the hybrid substrate

4.9.7 Characterizations of the Hybrid Substrate (A) X-Ray and OM: Figs. 4.78 and 4.79 show the OM and X-ray images of the fabricated hybrid substrate. Figure 4.78 shows a typical cross section of the hybrid substrate which consists of the fine metal L/S RDL-substrate, the interconnectlayer, and the HDI PCB. Figure 4.78 also shows the vias filled with the conductive paste nicely and there are not any obvious large void and delamination. The thickness of the interconnect layer is 60 μm, which is thinner than the C4 solder joint (usually 100 μm) of the 2.3-D IC integration. Figure 4.79 shows the pad for chip bonding, the pads for interconnect layer, the conductive paste, and ML1, ML2, and ML3 with their targets. Figure 4.79 also shows the X-ray image of the conductive paste, the contact pads, and the daisy-chain on PCB. All these demonstrated the assembly is properly done. (B) Continuity Check: Fig. 4.80 shows the nets for continuity checks. There are 21 hybrid substrates that pass all the nets.

4.9.8 Final Assembly After the hybrid substrate is ready, it is time to perform chips to hybrid substrate bonding and underfilling. A typical heterogeneous integration of three chips on the hybrid substrate is shown in Fig. 4.81.

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

337

Fine metal L/S RDL Interposer ML1

ML2

ML3

ML1 (2/2μm) ML2 (5/5μm)

Conductive paste Prepreg ML3 (300μm) PAD HDI Prepreg Conductive paste

Cu trace on HDI Pad for chip bonding

ML2 (5/5μm) ML1 (2/2μm) Conductive paste for interconnection

ML3 (300μm) PAD Conductive Paste

Fig. 4.79 Close-up views of the hybrid substrate

Fig. 4.80 Schematic nets for continuity measurement

338

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Chip 2B Chip 2A

Chip 1

Underfill

Hybrid Substrate

CHIP 2A

CHIP 1 Cu-pillar Solder

Underfill

Fine Metal L/S RDLs

PAD ML1

ML2

Via filled with conductive paste

InterconnectLayer 8-Layer HDI

Fig. 4.81 Heterogeneous integration of three chips on the hybrid substrate (top- and cross-sectional view)

4.9.9 Reliability Assessment (A) Six-Time Reflow: A total of 15 hybrid substrates (without chips) with 26 nets and eight hybrid substrates (with chips) with 37 nets are subjected to six-time reflow with the temperature profile shown in Fig. 4.82. Except for a few failed at the first time of reflow (earlier failures), most passed the six-time reflow test. The failure criterion is when the open circuit is found in a two-wire resistance measurement. (B) Drop Test: The drop test setup is according to JEDEC Standard JESD22-B111, as shown in Fig. 4.83. After a few tries, the right height (1120 mm) of the drop table is obtained, which yields the drop spectrum with 1500 G/ms (1500-Gs, 0.5-ms half-sine pulse). The sample size is eight packages (hybrid substrates and chips) with 37 nets. After more than 30 drop tests, there are two failures: one failed at 20 drops and the other at 30 drops. The measurement method is a fourwire resistance measurement, and the failure criterion is when the resistance change (R-shift) is 50%. A failure analysis reveals that the failure mode is the cracking of the solder joint as shown in Fig. 4.84 and not at the hybrid substate. This could be due to the poor assembly of the chips to hybrid substrate bonding.

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

339

Temperature (oC)

300 250 200 150 100 50 0 0

30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480

Time (s) Fig. 4.82 Reflow temperature profile

Thus, the fabricated hybrid substrate in this article is considered reliable for dropping mobile products. (C) Thermal Cycling by Simulation: The structural elements and their dimensions of the heterogeneous integration of three chips on the hybrid substrate are shown in Figs. 4.85 and 4.86 and their finite element model is shown in Figs. 4.87 and 4.88. Since the conductive paste filled via and the solder joint are the focus

Hybrid Substrate Test Board

Drop Tower

4-wire Measurement

Fig. 4.83 Drop test set-up and measurement

340

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Chip

Cu RDL1

Solder Fine Metal L/S RDL-substrate

RDL2 RDL3

Solder Crack

Fig. 4.84 Failure mode due to drop test

point of interest, much finer meshes are used in the paste filled via areas and the Cu pillars and the solder caps near the chip corners. Due to symmetry about the AA’-axes only half of the structure is modeled. The material properties of the structural elements are shown in Table 4.6. The electroplated Cu is assumed as an elastic–plastic (bilinear kinematic hardening) material with the stress–strain relation shown in Fig. 4.89 (first Young’s modulus = 121 GPa, second Young’s modulus = 1.2 GPa, and yield strength = 173 MPa). The HDI is assumed to be an anisotropic material. The SAC (Sn3Ag0.5Cu) solder is assumed to be a temperature dependent material; the Young’s modulus = (40–0.07 T) GPa and the CTE = (21 + 0.017 T) × 10 -6 °C. The constitutive equation for the SAC is assumed to obey the Garofalo hyperbolic sine creep equation and is the same one shown in Sect. 4.8.9. The temperature boundary condition is also the same one shown in Sect. 4.8.9. The deformed shape and undeformed shape of the heterogeneous integration of three chips on the hybrid substrate are shown in Fig. 4.90. At 450 s (85 °C), the hybrid substrate expands more than the chips and the whole structure is deformed in a concave shape (smiling face), Fig. 4.90a. At 2250 s (−40 °C), the hybrid substrate shrinks more than the chips and the structure is deformed into a convex shape (crying face), Fig. 4.90b. This is because the CTE of silicon chip is smaller than that of the hybrid substrate. The maximum warpage of the individual package (20 mm × 20 mm) is 255 μm. According to [75], the allowable warpage for a 13.42 mm × 13.42 mm individual package is 200 μm. Thus, the warpage of the present package should be acceptable. Fig. 4.91 shows the Mises (equivalent) stress acting at the via filled with conductive paste (Location C in Fig. 4.87). Figure 4.91a shows the Mises contours at 85 °C (450 s), while Fig. 4.91b at −40 °C (2250 s). It can be seen that: (a) for both times

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

Location C (Conductive paste)

Location A (Chip1 corner solder joint) Chip 2A (5 x 7)

20mm

Chip 2B (5 x 7)

A’

A

A

20mm

Chip 1 (10 x 10)

341

Location B (Chip1 corner solder joint)

A’

Y UX, UY=0 X

UY=0

Chip1 Copper pillar Underfill

Solder joint

Pad

Fine L/S RDL-substrate

Conductive Paste filled via

Prepreg

HDI Pad

HDI PCB

Fig. 4.85 Structure geometry

35μm

329μm

Chip 1

Copper pillar

275μm

37μm 12μm

39μm

Underfill

Fine metal L/S substrate

Solder cap

300μum 5um

60μm

Interconnect- Layer

Via

Prepreg

Conductive Paste

22μm

Copper 300μm 20mm

HDI (PCB)

Not-to-scale Fig. 4.86 Structural elements for finite element modeling

20mm

1mm

Chip 1 (10 x 10)

Chip 2A (5 x 7)

Chip 2B (5 x 7)

342

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers Location C

Location A

Copper pillar (Coarse mesh)

Corner copper pillar (Fine mesh)

Corner solder joint (Fine mesh)

Solder joint (Coarse mesh)

Conductive Paste filled via

Location B

Copper pillar (Coarse mesh)

Corner copper pillar (Fine mesh)

Corner solder joint (Fine mesh)

Solder joint (Coarse mesh)

RDL-Substrate Pad HDI Pad

Fig. 4.87 Finite element mesh distribution A

Aí

Z Fixed UX,UY,UZ =0

Fixed UZ=0

Y

A Symmetric boundary condition A-Aí Fixed UX=0

Fine Metal L/S RDL Cu Pad Via filled with Conductive Paste EMC HDI Cu Pad

Y X

Aí

Finite element meshes

Fig. 4.88 Finite element mesh near the via filled with conductive paste

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

343

Table 4.6 Materials properties Materials

CTE (10–6 /°C)

Young’s Modulus (GPa)

Poison’s ratio

Copper

16.3

121

0.34

HDI PCB

αx = αy = 18 αz = 70

Ex = Ey = 22 Ez = 10

0.28

Silicon (chip)

2.8

131

0.278

EMC

10 (< 150 °C)

19

0.25

Solder

21 + 0.017 T

49 − 0.07 T

0.3

RDL substrate

27.9

47.8

0.3

Conductive paste

19.01

20.33

0.3

Prepreg (Interconnect-layer)

15

26

0.39

Underfill

50

4.5

0.35

where T is in Celsius x105 Yield Stress = 173MPa 1800

σ (Stress) (Pa)

1600

Tangent Modulus = 1.2GPa

1400 1200 1000 800

E = 121GPa

600 400 200

X10-3

0 0

.5

1

1.5

2

2.5

3

3.5

4

4.5

5

[ (Strain) Consider copper Bauschinger effect, Kinematic hardening is used in this material.

Fig. 4.89 Stress–strain relation for electroplated Cu

(or temperatures) the maximum Mises stress occurs near the interface between the interconnect-layer and the fine metal L/S RDL-interposer (this is due to the expansion mismatch between the RDL-interposer and the interconnect-layer is larger than that between the interconnect-layer and the HDI PCB) and (b) the Mises stress contour at both times is not much different, and (c) the maximum Mises stress (∼20 MPa) is very small to create reliability issues, such as cracking and delamination.

344

(a)

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

85oC (450s)

Unit: μm

(b)

-40oC (2250s)

Unit: μm

Fig. 4.90 Structural deformation during the first thermal cycle. a At 85 °C (450 s). b At − 40 °C (2250 s)

The accumulated creep strain contour distributions at the critical microbump solder joint A (at Location A in Fig. 4.87) is shown in Fig. 4.92 (the contour distributions for solder joint B at Location B in Fig. 4.87 are very similar). The accumulated creep strain time history in solder joints A and B is shown in Fig. 4.93. It can be seen that the maximum accumulated creep strain occurs near the corner of the solder joints. Also, the maximum accumulated creep strain per cycle in the microbump solder joints A and B is almost the same. The maximum accumulated creep strain per cycle in the microbump solder joints A and B is 3.8% and it occurs at a very small area. Thus, this structure should be reliable for most operating conditions. The creep strain energy density contour distributions at the microbump solder joint A are shown in Fig. 4.94 (the contour distributions for solder joint B are very similar) and the maximum creep strain energy density time history at solder joints A and B are shown in Fig. 4.95. It can be seen that the maximum creep strain energy density occurs near the corner of the solder joints. The maximum creep strain energy density per cycle in the microbump solder joints A and B is only 1.53 MPa and it

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

345

(a) 85oC (450s)

(b) -40oC (2250s)

Units: MPa

Fig. 4.91 Von Mises stress acting at the via filled with conductive paste. a 85 °C (450 s). b − 40 °C (2250 s)

85oC (450s)

85oC (450s)

-45oC (2250s)

-45oC (2250s)

(a)

(b)

Fig. 4.92 Accumulated creep strain at solder joint A during the first thermal cycle. a At 85 °C (450 s). b At − 40 °C (2250 s)

346

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Accumulated creep strain

0.20 0.18

Location A Corner solder joint: 3.8% per cycle

0.16 0.14

Location B Corner solder joint: 3.79% per cycle

0.12 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 0

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

Time(s) Fig. 4.93 Accumulated creep strain time-history at solder joints A and B

85oC (450s)

-45oC (2250s)

(a)

85oC (450s)

-45oC (2250s)

(b)

Fig. 4.94 Creep strain energy density at solder joint A during the first thermal cycle. a At 85 °C (450 s). b At −40 °C (2250 s)

occurs at a very small area. Again, this structure should be reliable for most operating conditions.

4.9.10 Summary and Recommendations Some important results are summarized as follows. • A high-density organic hybrid substrate for heterogeneous integration has been developed. This hybrid substrate consists of three major parts, namely the fine metal L/S RDL-substrate, the interconnect-layer substrate, and the HDI substrate.

4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer

347

Creep strain energy density (MPa)

8.00 7.00 Location A Corner solder joint: 1.53MPa per cycle 6.00 Location B Corner solder joint: 1.52MPa per cycle 5.00 4.00 3.00 2.00 1.00 0.00 0

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

-1.00

Time(s) Fig. 4.95 Creep strain energy density time-history at solder joints A and B

• The fine metal L/S RDL-substrate with a minimum metal L/S = 2/2 μm has been fabricated by a fan-out panel level RDL-first process. • The interconnect layer has been fabricated by the PP and vias filled with conductive paste in β-stage. • The eight-layer HDI PCB has been fabricated by the conventional process. • The hybrid substrate has been formed by thermocompression of the RDLsubstrate, the interconnect-layer substrate, and the HDI substrate and the interconnect-layer become in C-stage. • Hybrid substrate characterizations, such as OM, X-ray, and SEM demonstrated that the interconnect-layer (both conductive paste and prepreg), MLs, pad for chip bonding, daisy-chains on PCB, etc. are properly fabricated. Continuity checks of the hybrid substrate have been passed • The hybrid substrate has passed the reflow test and drop test. • Nonlinear finite element analysis and result show that the stress state acting at the conductive paste filled via and the surrounding structural elements is very small to create reliability issues, such as delamination and cracking. Also, the accumulated creep strain and the creep strain energy density are too small to create solder joint reliability problems, such as cracking of solder joints.

348

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC Heterogeneous Integration 4.10.1 Why Low-Loss Dielectric? According to the US Federal Communications Commission: (a) the mid-band spectrum (also called Sub-6 GHz5G) is defined as 900 MHz < frequency < 6 GHz and data speeds ≤ 1 Gbps; and (b) the high-band spectrum (also called 5G millimeter wave or 5G mm Wave) is defined as 24 GHz ≤ frequency ≤ 100 GHz and 1 Gbps < data speeds ≤ 10 Gbps. In order to meet the requirements for boosting signal transmission speed/rate and managing a huge data flood, advanced development of semiconductors, packaging, materials, etc. is necessary. With respect to the electrical performance of insulation materials, low-loss Df (dissipation factor or loss tangent) and Dk (dielectric constant or permittivity) materials are highly preferred for 5G applications [208–229]. The following equation shows the transmission loss, which is equal to the sum of the conductor loss and dielectric loss. Conductor loss is proportional to the conductor skin resistance and the square root of Dk. Usually, the higher the frequency, the closer to the conductor surface the current signal flows (skin effect). For a rough surface conductor, the current signal is presumed to travel a longer distance on the surface, which leads to greater transmission loss. Thus, utilizing copper with lower surface roughness can reduce the conductor skin resistance. (Conductor loss is outside the scope of this book.) The dielectric loss is proportional to the frequency, Df, and the square root of Dk. Thus, in order to achieve lower transmission loss, lower values of Df and Dk are needed [208–229]. Transmission Loss = Conductor Loss + Dielectric Loss √ Conductor Loss ≈ Conductor Skin Resistance × Dk √ Dielectric Loss ≈ f × Df × Dk where f Frequency Df Dissipation Factor (Loss Tangent) Dk Dielectric Constant (Permittivity). In this section, the Dk and Df of three different raw dielectric materials are characterized by the Fabry–Perot open resonator (FPOR) measurement technique [229, 230]. The sample preparation is based on IEC 61189:2015. These values are compared with those from the data sheets of the raw materials, and the difference will be discussed. With the help of Polar and ANSYS’ HFSS (high-frequency structure simulator) software, a coplanar waveguide with ground (CPWG) test vehicle with one of these raw dielectric materials (vendor 1) is designed and fabricated, as shown in the

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

349

Fig. 4.96 Flowchart of dielectric materials characterization

flowchart of Fig. 4.96. Then, the impedance of the test vehicle is measured by TDR (time-domain reflectometer), and the effective Dk of the test vehicle is calculated through a closed-form equation and the real cross-section of the metal line width, spacing, and thickness as shown in the flowchart of Fig. 4.96. Separately, the insertion loss and return loss are measured with the VNA (vector network analyzer) of the test vehicle with pads. Finally, the measurement and simulation results are correlated [229].

4.10.2 Raw Materials and Their Data Sheets The raw materials data sheets of three different vendors are shown in Table 4.7, where their Dk, Df, and other important physical and mechanical material properties are also provided. It can be seen that: (a) for vendor 1, it is a BCB (benzocyclobutene) polymer with a curing temperature of 170 °C or 200 °C, and its Dk and Df are, respectively, 2.66 and 0.0031 at 28.3 GHz and 2.64 and 0.0032 at 39.6 GHz; (b) for Vendor 2, it is a PPE (polyphenylene ether) polymer with a curing temperature of 200 °C, and its Dk and Df are, respectively, 2.48 and 0.003 at 28 GHz and 2.57 and 0.003 at 40 GHz; and (c) for vendor 3, it is a PI (polyimide) polymer with a curing temperature of 230 °C, and its Dk and Df are, respectively, 3.07 and 0.01 at 19.36 GHz, 3.11 and 0.01 at 29.1 GHz, and 2.9 and 0.01 at 38.9 GHz.

350

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Table 4.7 Raw materials vendor and their data sheets Items –

Type Tone

–

Curing

Physical properties

Vendor 2

Vendor 3

BCB

PPE

PI

Negative

Temperature °C

170/200

200

230

Time

60/60

–

–

min

PGMEA

PGMEA

–

Dielectric constant (Dk)

2.66, 2.64

2.48, 2.57

3.07, 3.11, 2.9

Dissipation factor (Df)

0.0031, 0.0032 0.003, 0.003

0.01, 0.01, 0.01

Frequency (GHz)

28.3, 39.6

28, 40

19.36, 29.1, 38.9

Developer Electrical properties

Vendor 1

CTE α1 (< Tg)

ppm/K 31

60

–

Tg

°C

170

215

–

Moisture absorption

%

0.17 0.03 2.23 (23°C/45%RH) (23°C/85%RH) (23°C/80%RH)

Residual stress

MPa

20 @ 23 °C

14

–

340

413 @ N2

340

GPa

2.4

1.6

3.9

%

13

35

62

Tensile strength

MPa

84

60

197

Poisson’s ratio

–

0.36

–

–

5% weight loss temp. °C Mechanical Young’s modulus properties Elongation (RT)

4.10.3 Sample Preparation The sample preparation procedure is based on the guidance of IEC 61189:2015, which is basically shown in Fig. 4.97, and the sample preparation conditions are recommended by the vendors, as shown in Fig. 4.98. It can be seen that, in this study, we use a T5 core panel to let the raw materials, PID (photoimageable dielectric), to be spun on. The spin coating condition for each vendor is shown in Fig. 4.99. It can be seen that for vendors 1 and 2, the initial speed is 250 rpm for 10 s and then 500 rpm for 20 s, and for vendor 3, the initial speed is 1000 rpm for 10 s and 1500 rpm for 20 s. The resulting sample thickness (Table 4.8) for vendor 1 is 28 μm, for vendor 2 is 57 μm, and for vendor 3 is 17 μm. There are at least two reasons for the difference in sample thickness: (a) different viscosity—the higher, the thicker; and (b) different spin coating speed—the faster, the thinner. After the sample preparation procedure (Fig. 4.97) and condition (Fig. 4.98) for vendors 1, 2, and 3, the typical images of after post-curing and after pre-conditioning are shown in Fig. 4.100.

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

351

Fig. 4.97 Sample preparation procedure for the measurement

Fig. 4.98 Sample preparation condition for vendors

4.10.4 Fabry–Perot Open Resonator (FPOR) The Fabry–Perot open resonator (FPOR) measurement technique is adopted in this study (Fig. 4.100). It can measure the sample sizes of 10 cm × 10 cm × 10 μm to 2 mm with a spot size of 5 cm in diameter and the Dk and Df from 20 to 44 GHz. The ambient test temperature should be (23 ± 2) °C. The variation should not exceed 1 °C during the test. Furthermore, the data are taken from at least 11 points on the sample.

352

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers 1600

Speed (rpm)

1400 1200

Vendor 3

1000 800 600

Vendor 1 and Vendor 2

400 200 0 0

10

20

30

Time (sec) Fig. 4.99 Speed versus time Table 4.8 Sample dimensions Incoming raw materials and samples (Film) Form Type

Vendor 1

Vendor 2

Vendor 3

BCB √

PPE √

PI √

Raw Material

Liquid

Sample (Film)

Prepared by Unimicron

10 cm × 10 cm × 28 μm (UMTC 1)

10 cm × 10 cm × 57 μm (UMTC 2)

10 cm × 10 cm × 17 μm (UMTC 3)

Prepared by Vendor

10 cm x×10 cm × 18 μm (Vendor 1)

10 cm × 10 cm × 30 μm (Vendor 2)

NA (Vendor 3)

After post curing

Initialize

• Read File • Calibration

After pre-condition

Set Parameter

• Sample thickness • Frequency point

Sample

Measurement

• At least 11 points

Frequency: 21 ~ 43.5GHz Sample Size: 10cm x 10cm, thickness = 10µm ~ 2mm Spot Size (Diameter): 5cm Environment: 25 ± 10%oC, < 60%RH Test condition: 23 ± 2oC. The variation 1oC during test Fig. 4.100 Fabry–Perot open resonator (FPOR)

Fabry-Perot open resonator (FPOR)

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

353

(A) FPOR Measurement Results of Vendor 1: Table 4.9 tabulates the data sheet values and measurement results (Dk and Df) of vendor 1’s low-loss dielectric material for various frequencies. In this table, it shows: (a) the Dk and Df measured from the sample that we made (UMTC 1) and the sample provided by the vendor (vendor 1) and the Dk and Df from the data sheet of vendor 1 (and all of these are summarized in Figs. 4.101 and 4.102); and (b) the percent deviation in Dk and Df. It can be seen that: (a) for Dk, the results from UMTC 1 (2.51 at 28.2 GHz and 2.46 at 38 GHz) are very close to those from vendor 1 (2.653 at 28.2 GHz and 2.62 at 38); (b) additionally, for Dk, the results from UMTC 1 are very close to those from the data sheet of vendor 1 (2.66 at 28.3 GHz and 2.64 at 39.6 GHz); (c) for Df, the results from UMTC 1 (0.003 at 28.2 GHz and 0.0034 at 38 GHz) are very close to those from vendor 1 (0.00328 at 28.2 GHz and 0.00302 at 38 GHz) are very close to those from vendor 1 (2.59 at 28.2 GHz and 2.62 at 38 GHz); and (d) also for Df, the results from UMTC 1 are very close to those from the data sheet of vendor 1 (0.0031 at 28.3 GHz and 0.0032 at 39.6 GHz). The trend of Dk is independent of the frequency; however, the trend of Df is frequency-dependent—the higher the frequency, the higher the Df. Table 4.9 Df and Dk of vendor 1 Measurement results of vendor 1 Samples Frequency /Data sheet 21.3 25.5 Dk

28.2

32.4

35.2

38

40.7

UMTC 2.56 1 (Sample)

2.53

2.51

2.49

2.48

2.46

2.44

Vendor 2.67 1 (Sample)

2.66

2.653

2.649

2.64

2.62

2.618

Vendor 1 (Data sheet)

NA

NA

2.66 NA (28.3 GHz)

NA

2.64 NA (39.6 GHz)

4.12%

4.88%

5.39%

6.00%

6.06%

6.11%

6.79%

NA

NA

5.63%

NA

NA

6.81%

NA

0.0033

0.0030

0.0029

0.0029

0.0034

0.0043

Percent From deviation sample From data sheet Df

UMTC 0.0025 1 (Sample)

Vendor 0.00163 0.00324 0.00328 1 (Sample) Vendor 1 (Data sheet) Percent From deviation sample From data sheet

0.00256 0.00405 0.00302

0.00354

NA

NA

0.0031 NA (28.3 GHz)

NA

0.0032 NA (39.6 GHz)

53.3%

1.8%

8.5%

13.3%

28.4%

12.6%

21.5%

NA

NA

3.22%

NA

NA

6.25%

NA

354

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers 4.5

Fig. 4.101 Measured Dk of Vendor 1

Dk

Dielectric Constant

4.0 3.5 3.0 2.5 2.0 UMTC 1

1.5 1.0

Vendor 1

0.5

Vendor 1 Datasheet

0 18

22

26

30

34

38

42

Frequency (GHz)

0.005

Fig. 4.102 Measured Df of Vendor 1

Dissipation Factor

Df 0.004

0.003

0.002 UMTC 1 0.001

Vendor 1

Vendor 1

0 18

22

26

30

34

Datasheet 38 42

Frequency (GHz)

(B) FPOR Measurement Results of Vendor 2: Table 4.10 tabulates the data sheet values and measurement results (Dk and Df) of the low-loss dielectric material from vendor 2 for various frequencies (Figs. 4.103 and 4.104). It can be seen that: (a) for Dk, the results from UMTC 2 (2.4719 at 28.2 GHz and 2.4705 at 38 GHz) are very close to those from vendor 2 (2.59 at 28.2 GHz and 2.62 at 38); (b) additionally, for Dk, the results from UMTC 2 are very close to those from the data sheet of vendor 2 (2.48 at 28 GHz); (c) for Df, the results from UMTC 2 (0.00247 at 28.2 GHz and 0.00262 at 38 GHz) are reasonably close to those from vendor 2 (0.00282 at 28.2 GHz and 0.00277 at 38 GHz); and (d) also for Df, the results from UMTC 2 are reasonable close to those from the data sheet of vendor 2 (0.003 at 28 GHz). Again, the trend in Dk is basically independent of the frequency. On the other hand, the trend in Df is to be higher for higher frequencies.

Percent deviation

Df

Percent deviation

Dk

NA 62.82% NA

Vendor 2 (Data sheet)

From sample

From data sheet

0.00156

Vendor 2 (Sample)

NA 0.00254

UMTC 2 (Sample)

From data sheet

NA

Vendor 2 (Data sheet) 4.04%

2.578

Vendor 2 (Sample)

From sample

2.4738

21.3

Frequency

UMTC 2 (Sample)

Samples /Data sheet

Measurement results of vendor 2

Table 4.10 Df and Dk of vendor 2

25.5

NA

2.39%

NA

0.00251

0.00257

NA

4.3%

NA

2.5806

2.4694

17.67%

12.41%

0.003 (28 GHz)

0.00282

0.00247

0.33%

4.56%

2.48 (28 GHz)

2.59

2.4719

28.2

32.4

NA

0.81%

NA

0.00247

0.00245

NA

5.77%

NA

2.6

2.45

35.2

NA

25.59%

NA

0.0034

0.00253

NA

3.07%

NA

2.61

2.53

38

NA

5.42%

NA

0.00277

0.00262

NA

5.71%

NA

2.62

2.4705

40.7

0.33%

6.56%

0.003 (40 GHz)

0.0032

0.00299

3.87%

5.53%

2.57 (40 GHz)

2.615

2.4705

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC … 355

356

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers 4.5

Fig. 4.103 Measured Dk of Vendor 2

Dk

Dielectric Constant

4 3.5 3 2.5 2 1.5

UMTC

2

Vender 2

1

Datasheet

(Vendor 2)

0.5

0 18 20 22 24 26 28 30 32 34 36 38 40 42

Frequency (GHz)

0.005

Fig. 4.104 Measured Df of Vendor 2

Df

Dissipation Factor

0.004

0.003

0.002

0.001

0

UMTC 2 Vender 2 Datasheet (Vendor 2) 18 20 22 24 26 28 30 32 34 36 38 40 42

Frequency (GHz)

C.

FPOR Measurement Results of Vendor 3: Table 4.11 tabulates the data sheet values and measurement results (Dk and Df) of the low-loss dielectric material from vendor 3 for various frequencies (Fig. 4.105 and 4.106). It canbe seen that: (a) for Dk, the measurement results from UMTC 3 (3.26 at 21.3 GHz, 3.24 at 28.2 GHz, and 3.23 at 40.7 GHz) are very close to those from the data sheet of vendor 3 (3.07 at 19.36 GHz, 3.11 at 29.1 GHz, and 2.9 at 38.9 GHz); and (b) for Df, the results from UMTC 3 (0.0119 at 21.3 GHz, 0.0127 at 28.2 GHz, and 0.0136 at 40.7 GHz) are reasonably close to those from data sheet of vendor 3 (0.01 at 19.36 GHz, 0.01 at 29.1 GHz, and 0.01 at 38.9 GHz). Again, Dk is frequency-independent, and Df is frequency-dependent—the higher the frequency, the higher the Df.

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

357

Table 4.11 Df and Dk of vendor 3 Measurement results of vendor 3 Samples Frequency /Data sheet 21.3 Dk

25.5

28.2

32.4

35.2

38

40.7

UMTC 3.26 3 (Sample)

3.25

3.24

3.23

3.20

3.23

3.23

Vendor NA 3 (Sample)

NA

NA

NA

NA

NA

NA

3.07 NA (19.36 GHz)

3.11 NA (29.1 GHz)

NA

NA

2.9 (38.9 GHz)

NA

NA

NA

NA

NA

NA

NA

6.19%

NA

4.18%

NA

NA

NA

11.38%

Vendor 3 (Data sheet) Percent From deviation sample From data sheet

UMTC 0.0119 3 (Sample)

0.0121 0.0127

0.0125 0.0122 0.0129 0.0136

Vendor NA 3 (Sample)

NA

NA

NA

NA

NA

0.01 NA (19.36 GHz)

0.01 NA (29.1 GHz)

NA

NA

0.01 (38.9 GHz)

NA

NA

NA

NA

NA

NA

NA

19%

NA

27%

NA

NA

NA

36%

Fig. 4.105 Measured Dk of Vendor 3

4.5

Vendor 3 (Data sheet) Percent From deviation sample From data sheet

4

Dielectric Constant

Df

NA

Dk

3.5 3 2.5 2 1.5 1

UMTC 3 Datasheet (Vendor3)

0.5 0 18 20 22 24 26 28 30 32 34 36 38 40 42

Frequency (GHz)

358

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers 0.02

Fig. 4.106 Measured Df of Vendor 3

Dissipation Factor

Df 0.015

0.01 UMTC 3 Datasheet (Vendor 3)

0.005

0

18 20 22 24 26 28 30 32 34 36 38 40 42

Frequency (GHz)

(D) Comparison between the Measurement Results from Vendors: With the frequencies under consideration (up to 40 GHz) in this study, the ranges of measurement results of Dk from the dielectric materials provided by vendor 1 and vendor 2 are within 2.45 and 2.67 and of Df are within 0.0025–0.004. These values of Dk and Df agree (in the same ballpark) with most of the values published. These materials are made from BCB and PPE, with a curing temperature ≤ 200 °C. On the other hand, the measurement results of Dk (3.2–3.26) and Df (0.0119–0.0136) from the dielectric material provided by vendor 3 are on the high side, especially the Df, which is a few times higher than those of vendors 1 and 2. The material of vendor 3 is made from PI, with a curing temperature of 230 °C. According to the above measurement results, the BCB and PPE samples show better performance in the electrical material properties (Dk and Df) and repeatability. In contrast, the PI sample shows the worst repeatability and electrical material properties. The Dk and Df measurement results may be affected by environment, measuring instrument, and sample fabrication flow. According to Table 4.7, the PID, which is PI-based, shows the highest moisture absorption (about 2.23%). In other words, the PI-based samples are easily affected by the environment. The BCB- or PPE-based materials are suitable for the following test vehicle fabrication.

4.10.5 Test Vehicle Designed by Polar and ANSYS (A) Test Vehicle Designed by Polar: The dimensions of coplanar waveguide with ground (CPWG) are designed by Polar design: the dielectric height = 7 μm; dielectric constant of vendor 1 = 2.66; trace width = 15 μm; trace spacing = 15 μm; trace thickness = 4 μm; and impedance = 50.78 Ω, which is acceptable (Fig. 4.107).

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

H1 (Dielectric Height)

359

7µm

Er1 (Dielectric Constant)

2.66

W1&W2 (Trace Width)

15µm

D1 (Space)

15µm

T1 (Trace Thickness)

4µm

Impedance

≈ 50.78

Fig. 4.107 Test vehicle designed by Polar

(B) Test Vehicle Verified by ANSYS: Guided by the result of Polar, a detailed CPWG design is shown in Fig. 4.108. It can be seen that: (a) glass thickness = 1.1 mm; (b) ground metal = 6 μm; (c) the PID = 7 μm; (d) the via size = 50 μm and minimum via pitch = 150 μm; (e) the top metal = 4 μm; (f) metal line width = 15 μm and line spacing = 15 μm; and (g) there are two different kinds of pad size: 50 and 80 μm. In this study, the specifications are impedance = 50 ± 2.5 Ω; insertion loss (S21) > − 3 dB; and return loss (S11) < − 10 dB. The model for ANSYS’ HFSS is shown in Fig. 4.109, where the results (Smith charts) are also shown. It can be seen that, for the frequencies under consideration (1–40 GHz) and for the case of pure line, the impedance is 50 Ω, which confirms the design by Polar. The effect of the pad sizes (50 μm and 80 μm) for the transmission line measurement is to increase the impedance. Figure 4.110 shows the return loss (S11) and insertion loss (S21) of the test vehicle with Dk and Df from vendor 1 and with different pad sizes for measurement purposes. It can be seen that the insertion loss is almost the same for the pad size = 0, 50, and 80 μm, and the values are larger than −3 dB, which is acceptable. On the other hand, the return loss is dependent on the pad size. In general, the smaller the pad size, the smaller the dBs of the return loss. Nevertheless, all their values are less than −10 dB, which meets the specification. Thus, this design will be fabricated for the cross-section analysis, TDR, and VNA measurements.

360

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Line width/spacing: 15μm/15μm Pad size for transmission line measurement = 50 and 80μm

Via distribution

S

Test vehicle (unit: μm) Glass thickness RDL1 Thickness Thickness drill size D12 Via12 Min. via pitch RDL2

Symbol

Spec.

A

1100

B

6

C

7

D1

50

D2

150

Thickness

E

4

Min. Line W/S

F/ G1,G2

15/15

Fig. 4.108 Detailed test vehicle

Pure Line

Line with 50μm-pad

Line with 80μm-pad Frequency Range: 1~40GHz Line Width = 15µm; Space = 15µm Center of Smith Chart means impedance is 50©

Fig. 4.109 ANSYS HFSS model and Smith charts

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

361

0 S21 (Pad width = 0/50/80µm)

-10 S11 (Pad width = 80µm)

-20

dB

S11 (Pad width = 50µm)

-30 -40 Return Loss (S11) Insertion Loss (S21) -50 Line width = 15µm Line length = 5mm

-60

1

7.54

S11 (Pure Line)

14.08

20.62

27.16

33.7

40.24

Frequency (GHz) Fig. 4.110 Return loss (S11) and insertion loss (S21) of test vehicle with Dk and Df from vendor 1 (ANSYS)

4.10.6 Test Vehicles Fabrication Figure 4.111 shows the schematic and process flow of the test vehicle. The key process steps are: after cleaning, first slit coat a released film on a glass carrier (515 mm × 510 mm × 1.1 mm) then PVD (physical vapor deposition) Ti/Cu (50/300 nm). It is followed by photoresist and laser direct imaging (LDI) and development then EDC (electrochemical deposition) Cu, photoresist striping, and Ti/Cu etching to form the Cu ground plane or RDL1. In order to spin coat the PID (photoimageable dielectric), the carrier is laser drilled (cut) into nine subpanels (150 mm × 150 mm). It is followed by laser drilling on the PID, sputtering Ti/Cu, spinning photoresist, LDI and development, EDC Cu, photoresist striping, and seed layer etching to form the Cu line or RDL2. Figure 4.112a shows the scanning electric microscope (SEM) image of the test vehicle, and Fig. 4.112b shows the detailed dimensions of the actual test vehicle. Figure 4.113 shows the cross sections. The average width, space, and thickness of the trace for both pads (50 and 80 μm) are, respectively, ~15 μm, ~ 15 μm, and ~4 μm. The thickness of the ground layer is about 6 μm. These values are close to the design specification. However, the thickness of the dielectric layer is 9.2 μm (50 μm pad width) and 9.7 μm (80 μm pad width). These values are > 30% higher than the specification. In addition, the Pt layer is only the pre-sputter protection layer, which reduces the charge effect during SEM observation.

362

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

Fig. 4.111 Process flow in fabricating the test vehicle

(a)

W RDL 2 H1

D1

T1

D12 RDL 1 GLASS

(b)

Fig. 4.112 a The SEM image of test vehicle for TDR measurement and b detailed dimensions of actual test vehicle

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

Sample

First

363

Second

Third

Line with 80μm-pad

Line with 50μm-pad

First

Via

Second

Third

G S G

Fig. 4.113 Cross-section images

(a)

Pad Width: 80μm, 63.19Ω

(b)

Pad Width: 50μm, 61.92Ω Fig. 4.114 TDR measurement results. a For 80 μm pad width. b For 50 μm pad width

364

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

a

Fig. 4.115 Definition of algebra in the impedance equation

RDL 2 h

D12

b

RDL 1 GLASS

4.10.7 TDR Measurement and Results The TDR measurement of the test structure is performed by the Oscilloscope TD8000/DSA8300 at 20 GHz. The test temperature is at room temperature (23 ± 2) °C. The line width is 15 μm, and the line length is 10 mm. The test pad sizes are 50 and 80 μm, respectively. The measurement results are shown in Fig. 4.114. It can be seen that the impedance for pad width equal to 50 μm is 61.92 Ω, while for 80 μm, it is 63.19 Ω. These values are higher than that (~50 Ω) predicted by the Polar/ANSYS. This is due to the difference in the dielectric thickness between the design/analysis and the real structure. This also could be due to the variation of material properties (in design and simulation).

4.10.8 Effective Dielectric Constant (1eff) The effective dielectric constant (1eff) provides a reference dielectric constant for design and simulation of complex material and/or stack structure. In this study, the effective Dk (1eff) of the test vehicle is calculated by a closed-form equation [231]. Figures 4.115 and 4.116 show the definition of algebra in the impedance equation. It can be seen that 1eff = 2.19 for pad width = 80 μm and 1eff = 2.116 for pad width = 50 μm. These values are smaller than the measured value (~2.5) but are reasonably close. Impedance Equation: 60π Z0 = √ εeff

1 K (k) K (k ' )

+

K (k1) K (k1' )

Re-write the equation: ⎛ εeff = ⎝

⎞2 Z0 ×

[

60π K (k) K (k ' )

+

K (k1) K (k1' )

]⎠

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

365

Metal PID Metal

Substrat

Fig. 4.116 The schematic of GCPW with electric field

Transmission line with 50μm-pad 0

S21

-5 ANSYS

-10

dB

-15

ANSYS VNA

S11

ANSYS

-20

VNA

-25 VNA

-30 -35 -40 0.1

3.1

6.1

9.1 12.1 15.1 18.1 21.1 24.1 27.1 30.1 33.1 36.1 39.1

Frequency (GHz) Fig. 4.117 The VNA measurement results of test vehicle (50 μm pad) and correlation with ANSYS results

366

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

√ √ ' tanh πa where k = ab ; k ' = 1 − k 2 ; k1 = 1 − k12 ; and k = tanh( π4hb ) ; “a” is the trace ( 4h ) width, “b” is the sum of the track width plus the gap on either side, “h” is the height of the dielectric layer, shown in Fig. 4.115. Elliptical equation: K (k) =

π 2an

√ √ ' tanh πa n−1 ; bn = an−1 − k 2 ; k1 = 1 − k12 ; k = tanh( π4hb ) ; and n is where an = an−1 +b b ( 4h ) iteration. As shown in Fig. 4.116, the electric field (red dashed line) travels across dielectric and air. In other words, the effective dielectric constant consists of the effects from fabrication and air in the study. Otherwise, the value of the dielectric constant may also be affected by the method of pre-treatment of the sample, measurement instrument, and measurement environment.

4.10.9 VNA Measurement and Correlation with Simulation Results (A) VNA Measurements: The VNA (vector network analyzer) of the test vehicle is by Anritsu. The chuck size is 10 × 10 cm2 , and it is measured at room temperature, 23 ± 2 °C. The designed line length and width are, respectively, 5 mm and 15 μm. The pad widths are 50 and 80 μm. The frequencies are from 1 to 67 GHz. Figures 4.117 and 4.118 show the measurement results (up to 40 GHz). First of all, it can be seen that for both cases, S21 is greater than − 3 dB, and S11 is less than −10 dB. For S21, the responses are not dependent on the pad width, except (with slight difference) at very high frequencies. On the other hand, for S11, the responses are dependent on the pad width; even the trends are basically the same. The one with 50 μm pad width performs better than the one with 80 μm. (B) Correlation of VNA Measurements with ANSYS Simulations: First of all, the simulation results (with PID = 7 μm) shown in Fig. 4.110 cannot be used to compare with the VNA measurement results of the real structure (with PID > 9 μm). Further AYSYS/HFSS simulations with the real PID thicknesses— 9.2 μm for 50 μm pad and 9.7 μm for 80 μm pad—are performed, and the results are shown in Figs. 4.117 and 4.118. It can be seen that the simulation results and the measurement results, in both the trend and magnitude, correlated very well. A comparison between the VNA measurement results of the test vehicles with the 50 μm pad and 80 μm pad is shown in Fig. 4.119. It can be seen that, for S11, the 50 μm pad performs better than the 80 μm pad.

4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC …

367

Transmission line with 80μm-pad 0

-5

ANSYS

-10

S11

-15

dB

ANSYS VNA

S21

ANSYS VNA

-20 VNA

-25 -30 -35 -40

0.1

3.1

6.1

9.1 12.1 15.1 18.1 21.1 24.1 27.1 30.1 33.1 36.1 39.1

Frequency (GHz) Fig. 4.118 The VNA measurement results of test vehicle (80 μm pad) and correlation with ANSYS results

4.10.10 Summary and Recommendations • A systematic approach and complete flow to characterize the electrical performance (from 1 to 40 GHz) of low-loss insulation materials by utilizing the FPOR, simulation, and S-parameter measurement have been provided. The Dk and Df of low-loss dielectric materials have been measured by the FPOR technique and based on the IEC 61189:2015, a sample preparation produced. These values compared very well with those from the data sheets of the raw materials. It has been found that: (a) the BCB and PPE samples have a better performance in terms of the electrical material properties (Dk and Df) and repeatability; (b) the PI sample has the worst repeatability and electrical material properties; and (c) the Dk and Df measurement results are affected by environment, measuring instrument, and sample fabrication flow. • Based on Polar and ANSYS’ HFSS, a CPWG test vehicle was designed and fabricated. The impedance of the test vehicle was measured by TDR, and the effective Dk of the test vehicle was calculated through a closed-form equation and the real dimensions of the metal line width, spacing, and thickness of the fabricated test vehicle. The insertion loss and return loss of the test vehicle were measured by VNA, and their trends and values correlated very well with the ANSYS’ HFSS simulation results based on the real dimension of the fabricated test vehicle. It was found that the thickness of the dielectric material (PID) plays

368

4 Multiple System and Heterogeneous Integration with TSV-Less Interposers

0 50µm

-5

80µm

-10 80µm

dB

-15 -20 -25 50µm

-30 -35 -40 0.1

4.1

8.1

12.1

16.1

20.1

24.1

28.1

32.1

36.1

40.1

Frequency (GHz) Fig. 4.119 Comparison of VNA measurement results between the test vehicle with 50 μm pad and 80 μm pad

a very important role in the electrical performance, such as the insertion loss and return loss. Thus, controlling the thickness of the PID is a very critical process step during manufacturing. • The systematic approach to design, measurement, and simulation presented herein [229] could be useful in design and/or manufacturing for high-speed and highfrequency applications. • The most important task in high speed and frequency circuits is to reduce transmission loss, which is equal to the sum of conductor loss and dielectric loss. The solution to conductor loss is to use high adhesion technology for very low surface roughness Cu foil, and the solution to dielectric loss is to use excellent dielectric properties and stable low loss Dk and Df for a wide range of frequency, temperature, humidity, etc. • For high speed and frequency applications such as 5G, the dielectric materials are not only should be low loss (value) and stable Dk and Df through varied humidity conditions, but also should have low CTE, low curing temperature, low Young’s modulus (< 2GPa), low moisture absorption (< 0.3%), low shrinkage during curing (< 5%), high elongation, high tensile strength, long shelf life, easy of manufacturability, suitable for assembly, etc.

References

369

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Chapter 5

Chiplets Lateral Communications

5.1 Introduction As mentioned in Sec. 2.5, the key disadvantages of chiplet design and heterogeneous integration packaging are larger packaging size and higher packaging cost. The reasons are very simple [1]: (a) in order to obtain higher semiconductor manufacturing yield, which translates to low cost, the system-on-chip (SoC) is partitioned and/or split into smaller chiplets (thus the size and cost of the package are larger and higher), and (b) in order to let those chiplets to perform lateral or horizontal communication, addition packaging are needed (thus the cost of the package are higher). In the past, the lateral (horizontal) communication of chiplet design and heterogeneous integration packaging is by, for examples (a) fan-out redistribution-layers, (b) build-up high-density organic substrate, and (c) fine metal line width and spacing (L/S) through-silicon via (TSV)-interposer. Figure 5.1 shows an application processor chipset in the smartphone of HTC (Desire 606 W), which was shipped in 2013. The application processor chipset is SPREADTRUM SC8502, which is a heterogeneous integration of the modem and application processor by the fan-out chip-first process. These chips are supported by the fan-out 2-layer RDLs (redistribution-layers) substrate and then solder balled on a PCB (printed circuit board). Figure 5.2 shows AMD’s 2nd-generation extreme-performance yield computing (EPYC) server processors [2, 3], the 7002-series, shipped in mid-2019. As mentioned in Sect. 2.7, one of AMD’s solutions is to partition the SoC into chiplets, reserving the expensive leading-edge silicon for the central processing unit (CPU) core while leaving the I/Os and memory interfaces in n−1 generation silicon. Another solution is to split the CPU core into smaller chiplets. In this case, each core complex die (CCD), or CPU compute die, is split into two smaller chiplets. AMD used the expensive 7 nm process technology fabricated by TSMC (in early 2019) for the core CCD chiplets and moved the dynamic random-access memory (DRAM) and logic to a mature 14 nm I/O die fabricated by GlobalFoundries. The 2nd-generation EPYC is a 2D chiplets © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging, https://doi.org/10.1007/978-981-19-9917-8_5

381

382

5 Chiplets Lateral Communications Package Size: 7.4 x 7.4 x 0.71mm 430µm

115µm

Modem (2.8 x 2.8mm)

Apps Processor (3x3mm)

PCB

Over Mold

Modem Chip

2 RDLs: 20µm L/S

230 solder balls @0.4mm pitch

Fig. 5.1 Heterogeneous integration of modem and processor on a fan-out RDL

IC integration technology, i.e., all the chiplets are side-by-side on a 9-2-9 build-up package substrate. The 20-layer fine metal L/S organic substrate is not cheap. Figure 5.3 shows the Virtex-7 HT family shipped by Xilinx in 2013. As mentioned in Sect. 2.6, in 2011Xilinx asked TSMC to fabricate its field-programable gate array (FPGA) system-on-chip (SoC) with 28 nm process technology [4, 5]. Because of the large chip size, the yield was very poor. Then, Xilinx redesigned and split the large FPGA into four smaller chiplets as shown in Fig. 5.3 and TSMC manufactured the

CCD

CCD

CCD

CCD

CCD

I/O

CCD

CCD

CCD

CCD Chiplets (7nm process technology)

I/O chip (14nm process technology)

9-2-9 package substrate Fig. 5.2 Heterogeneous integration of CPU and I/O on a 9-9-2 build-up package substrate

5.2 Rigid Bridges Versus Flexible Bridges

383

For better manufacturing yield (to save cost), a very large SoC has been split into 4 smaller chips.

(10,000+)

The key function of the RDLs on the TSV interposer is to perform lateral communications between the chips. With 4 RDLs

Fig. 5.3 Heterogeneous integration of split FPGAs on a TSV interposer

chiplets at high yield (with the 28 nm process technology) and packaged them on their chip-on-wafer-on-substrate (CoWoS) technology. CoWoS is a 2.5D IC integration, which is the key structure (substrate) to let those 4 chiplets do lateral communications. The minimum pitch of the four redistribution layers (RDLs) on the TSV-interposer is 0.4 μm. The TSV-interposer is known to have a very high cost. It should be noted that the requirement of lateral communications (RDLs) between chiplets is fine-metal L/S/H (thickness) and at a very small and local area of the chiplets. There is no reason to use the whole RDL-substrate, the whole build-up package substrate, or the whole TSV-interposer to support the lateral communication between chiplets. Therefore, the concept of using small area and a fine-metal L/S/H RDLs bridge (a piece of chip without device) to connect the chiplets to perform lateral communication (to reduce cost) for chiplet design and heterogeneous integration packaging has been proposed in the industry [6–30] and is a very hot topic today. There are at least two different groups of bridge, namely rigid bridge and flexible bridge.

5.2 Rigid Bridges Versus Flexible Bridges Rigid bridge consists of the RDLs and the substrate, which could be silicon. Most rigid bridges are with silicon substrate and the RDLs are fabricated on a silicon wafer. Some rigid bridges are even with TSVs. Flexible bridge is the RDL itself. Today,

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5 Chiplets Lateral Communications

most of the products and publications with bridges are rigid bridges. The focus of this chapter is mainly on rigid bridges w/o TSVs. There are at least two groups of rigid bridges, namely, (a) rigid bridges with build-up package substrate, Sects. 5.3 and 5.4 and (b) rigid bridges with fan-out RDL-substrate, Sects. 5.5–5.11.

5.3 Intel’s EMIB The most famous rigid bridge is Intel’s EMIB (embedded multi-die interconnect bridge) [6–9]. Figure 5.4 shows one of Intel’s EMIB patents [6]. It can be seen that the EMIB die is embedded in the cavity of a build-up package substrate, which is supporting the chiplets. Figure 5.5 shows Intel’s processor (Kaby Lake) that combine its high-performance × 86 cores with AMD’s Radeon Graphics into the same processor package using Intel’s own EMIB as well as HBM (2017). Intel cancelled all the Kaby Lake-G products in October 2019. Figure 5.6 shows the Agilex FPGA (field programable gate array) module. It can be seen that the FPGA and other chips are attached on top of a build-up package substrate with EMIB with fine-metal L/S/H RDLs. The TSV interposer is eliminated. For EMIB, there are at least three important tasks, Fig. 5.7, namely: (a) wafer bumping of two different kinds of bumps on the chiplets wafer (but there are not bumps on the bridge); (b) embedding the bridge in the cavity of a build-up substrate and then laminating the top surface of the substrate; and (c) bonding the chiplets on the substrate with the embedded bridge.

5.3.1 Solder Bumps for EMIB It can be seen from Fig. 5.7 that there are two kinds of bumps on the chiplet, namely the C4 (controlled collapse chip connection) bumps and the C2 (chip connection or copper-pillar with solder-cap micro) bumps. Thus, wafer bumping of the chiplets wafer poses a challenge, but Intel has already taken care of this issue. C4 or C2 bumps

CHIP

CHIP

CHIP

Embedded Bridge Embedded Bridge (EMIB) Package Substrate Solder Ball

Fig. 5.4 One of Intel’s EMIB patent

5.3 Intel’s EMIB

385 GPU HBM2 EMIB

PCle CPU

PCB

DRAM

High Bandwidth Memory-2 (HBM2)

DRAM

DRAM

DRAM

GPU

DRAM

GPU

DRAM

DRAM

Cu-pillar

Solder-cap

Logic Base

DRAM Solder-cap

Cu-pillar

Logic Base Build-up Layers

Build-up Layers

Embedded Multi-die Interconnect Bridge (EMIB)

RDLs

Embedded Silicon Bridge

Cu-pillar

PCB

PCB

Fig. 5.5 Intel’s Kaby Lake processor with AMD’s Radeon graphics as well as HBM with EMIB

CHIP1

EMIB

C2 bump C4 bump

CHIP2

CHIP1

CHIP2

C2 bump

EMIB

Organic Package Substrate

PCB Not-to-scale The surface of package substrate with EMIB

C2 Microbumps

CHIP 1

C4 Bumps

CHIP 2

EMIB

EMIB Build-up Package Substrate

Fig. 5.6 Intel’s Agilex FPGA with EMIB

386

5 Chiplets Lateral Communications CHIP C4 bump Chip 1

C4 bump

C2 bump

C2 bump

(b)

(a) Micro Solder Joint C4 Solder Joint

C4 Solder Joint HBM RDL EMIB

FPGA Package Substrate

Micro Solder Joint HBM RDL EMIB

Via

Solder Joint

PCB (c) Fig. 5.7 a Chiplet with two different kinds of bump (C2 and C4). b EMIB in the cavity of a package substrate. c Schematic of the cross section of a FPGA and HBMs system with EMIBs

5.3.2 Fabrication of EMIB Substrate There are two major tasks in fabricating the organic package substrate with EMIB (Fig. 5.8). One is to make the EMIB, and the other is to make the substrate with EMIB. To make the EMIB, one must first build the RDLs (including the contact pads) on a Si-wafer. The way to make the RDLs depends on the line width/spacing of the conductive wiring of the RDLs. Finally, attach the non-RDL side of the Si-wafer to a die-attach film, and then singulate the Si-wafer. To make the substrate with an EMIB, first place the singulated EMIB with the die-attached film on top of the Cu foil in the cavity of the substrate, Fig. 5.8a. It is followed by laminating a dielectric film on the whole organic package substrate. Then, drilling (on the dielectric film) and Cu plating to fill the holes (vias) to make connections to the contact pads of the EMIB. Continue Cu plating to make lateral connections of the substrate as shown in Fig. 5.8b. Then, it is followed by laminating another dielectric film on the whole substrate and drilling (on dielectric) and Cu plating to fill the holes and make contact pads, Fig. 5.8c. (Smaller pads on a finer pitch are for C2 bumps, while larger pads on a gross pitch are for C4 bumps.) The organic package substrate with an EMIB is ready for bonding of the chips as shown in Fig. 5.8d.

5.3 Intel’s EMIB

387

(a)

(b)

(c)

(d)

Fig. 5.8 a Attach the EMIB in the cavity of a build-up substrate. b RDL for lateral communications. c Contact pad for C4 and C2 bumps. d Chips mounted on the build-up substrate with EMIB

Today, the minimum metal L/S/ H is 2 μm/2 μm/2 μm and the bridge size is from 2 mm × 2 mm to 8 mm × 8 mm [7], but most are equal and less than 5 mm × 5 mm [8]. The dielectric layer thickness is 2 μm. Usually, there are ≤ 4 RDLs. One of the challenges of the EMIB technology is to fabricate the organic buildup package substrate with cavities for the silicon bridges and then laminate (with pressure and temperature) another build-up layer on top (to meet the substrate surface flatness requirement) for chiplets (with both C2 and C4 bumps) bonding. Intel and its suppliers are working toward high-yield manufacturing of the substrate.

5.3.3 Bonding Challenges for EMIB A few months ago, Intel published a paper at IEEE/ECTC 2021 [9] that pointed out the bonding challenges of chiplets: • • • • • • • •

Die bonding process. Manufacturing throughput. Die warpage. Interface quality. Die attach film material design. Die shift. Via-to-die-pad overlay alignment. Integrated process considerations.

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5 Chiplets Lateral Communications

5.4 IBM’s DBHi During IEEE/ECTC2021 and 2022, IBM presented 7 papers on “Direct Bonded Heterogeneous Integration (DBHi) Si Bridge” [10–16], Fig. 5.9. The major differences between Intel’s EMIB and IBM’s DBHi are as follows: • For Intel’s EMIB, there are two different (C4 and C2) bumps on the chiplets (and there are no bumps on the bridge), Fig. 5.7, while for IBM’s DBHi, there are C4 bumps on the chiplets and C2 bumps on the bridge, Fig. 5.10a. • For Intel’s EMIB, the bridge is embedded in the cavity of a build-up substrate with a die-attach material and then laminated with another build-up layer on top. Therefore, the substrate fabrication is very complicated as mentioned in Sect. 5.3.2. For IBM’s DBHi, the substrate is just a regular build-up substrate with a cavity on top as shown in Fig. 5.10b.

5.4.1 Solder Bumps for DBHi As shown in Fig. 5.10a, there are C2 bumps on the bridge. However, there are C4 bumps and Cu pads on the chiplet of the same wafer. Thus, wafer bumping post a challenge. IBM use a double lithography process to resolve this issue [10], which is shown in Fig. 5.11. It can be seen that, the first lithography is used for making the UBM and metal pad, and the second lithography is used to make the C4 bumps by injection molded solder (IMS) method.

BRIDGE

C4 Bump

NCP

CHIPLET 1 CHIPLET 2

CHIPLET 1

Build-up Package Substrate

CHIPLET 2

μBump

BRIDGE

CHIPLET 1

BRIDGE

CAVITY

CHIPLET 2

CHIPLET 2

CHIPLET 1 BRIDGE CHIPLET 1

CHIPLET 2

Underfill

μBump

C2 bump

C4 Bump

BRIDGE

Trench

Build-up Package Substrate

CHIPLET 2

CHIPLET 1 BRIDGE Underfill Anchor

Fig. 5.9 IBM’ DBHi

5.4 IBM’s DBHi

389

BRIDGE

(a)

C4 bump

Chip 1

Cu C2 bump

C4 bump

UBM

C4 bump

CHIPLET

(b)

Chip 2

Build-up Package Substrate with Cavity

Fig. 5.10 IBM’s DBHi. a C2 bumps on the bridge while C4 bumps on the chiplet. b Ordinary build-up package substrate with cavity

Photoresist Seed Layer

Metal Pad UBM

Si wafer Lithography

Plating

Photoresist

Dry-Film Lithography

Strip-off Photoresist

Etch Seed Layer

Solder

Injection Molded Solder

C4 bump

Strip-off Photoresist

Fig. 5.11 IBM’s double lithography process in making the C4 bumps and Cu pads

5.4.2 DBHi Bonding Assembly The bonding assembly process of DBHi is very simple, Fig. 5.12. First, apply the nonconductive paste (NCP) on Chip 1. Then, bond the Chip 1 and the bridge with thermal compression bonding (TCB). After bonding, the NCP becomes the underfill between Chip 1 and the bridge. Then, apply NCP on the bridge and bond Chip 2

390

5 Chiplets Lateral Communications (a)

(b)

Heater

Heater

Nozzle

Nozzle

C4 bump

Bridge

Chip 1

Underfill

Chip 2

μbump

TCB + NCP

Chip 1 Bridge

Pedestal Heater (c) Underfill Underfill (Optional)

Chip 2

Chip 1

C4 Reflow Bridge Organic Package Substrate with cavity

Cavity

Fig. 5.12 DBHi bonding process. a TCB of the bridge die to Chip 1 with NCP. b TCB of the bridge die to Chip 2 with NCP. c C4 solder reflow of the Chip 1 and Chip 2 on the package with cavity and then underfill

and the bridge with TCB. Those steps are followed by placing the module (Chip 1 + bridge + Chip 2) on the organic substrate with a cavity and then going through the standard flip-chip reflow assembly process. The stage temperature, bonding force, and bond-head temperature vs. time during bonding are shown in Fig. 5.13. It can be seen that: (a) the bonding stage temperature (T1 ) is small and kept at constant all the times, (b) the bond-head temperature consists of three stages; (i) at the first stage the temperature (T2 ) is larger than T1 , which is used to melt and flow the NCP: (ii) at the second stage the temperature (T3 = 2T1 ) is the largest, which is used to reflow the solder; and (iii) at the final stage the temperature (T4 ) is less than T2 and larger than T1, which is used to solidify the solder joints. The underfill under the bridge is optional. Figure 5.9 shows the demonstration by IBM [9]. If the bridge is very thin, e.g., 50 μm and the C2 bump is very short, e.g., 30 μm, then the cavity of the package substrate is not needed if the C4 solder bump height is > 85 μm as shown in Fig. 5.14. In [15, 16], a detailed study on the TCB with NCP has been given. Figure 5.15 shows the structure for simulation. It can be seen that there are two chiplets and one bridge as shown in Fig. 5.15a. Figure 5.15b shows the zone-in of the one chiplet and the bridge. Figure 5.16a schematically shows the cross section of the DBHi. During thermal cycling (− 25 ↔ 125 °C), due to the thermal expansion mismatch between the silicon chip (2.5 × 10–6 /°C) and the build-up package substrate (18.5 × 10–6 /°C),

5.4 IBM’s DBHi

391 Head Temp Stage Temp Bond Force

F2 F1

Force

Temperature

T3=2T1

T2 0 T4 T1 0

t1

t2

t3

t4

Time

Fig. 5.13 DBHi TCB temperature-force–time profile

C2 Bumps CHIP B

CHIP A

C4 Bumps

Bridge

Build-up Package Substrate Cavity

C2 Bumps CHIP B

CHIP A Bridge

C4 Bumps

Build-up Package Substrate

Fig. 5.14 DBHi options

the C4 bumps are subjected very large shearing stress as shown in Fig. 5.16b. Thus, underfill is needed to ensure the C4 solder joint reliability. The tensile stress is shown in Fig. 5.16c. The test vehicle is shown in Fig. 5.17. It consists of an organic package substrate (laminate), a Si interposer, μC2 or μC4 bumps, and a Si chip. Apparently, the chip is for the chiplet, the Si interposer is for the bridge, and the organic laminate is for

392

5 Chiplets Lateral Communications

(a)

Chiplet

Chiplet Bridge

DBHi Chiplet with C4 Bumps

19mm (b)

Bridge Die with C2 Bumps

Bridge Connection Areas

Fig. 5.15 DBHi structure for simulations. a Two chiplets and a bridge die. b Close-up of the structure

the build-up package substrate. Figure 5.18a shows the solder joints with entrapped fillers while Fig. 5.18b shows the optimal solder joints without fillers. Figure 5.19 shows the optimal solder joint cracks after thermal cycling test at 1000 cycles (− 55 ↔ 125 °C).

5.4.3 DBHi Underfilling In [13], IBM study the underfill flow characteristic of their DBHi structure. Figure 5.20a schematically shows the side-view and top-view of the DBHi structure. In order to observe the flow of the underfill between the gaps by a high-speed camera, the material of all the key components is made of glass. Figure 5.20b shows the underfill dispensing pattern. The critical dimensional parameters to be studied are shown in Fig. 5.21. It can be seen that these parameters are: (a) the gap between the two chips, (b) the gap between the chips and the package substrate, (c) the gap between the bridge bottom and the package substrate cavity, (d) the gap between the bridge sidewall and the package substrate cavity, and (e) the gap between the module (chips + bridge) and the package substrate.

5.4 IBM’s DBHi

393

Max

Processor chiplet µC2 + NCP

(b)

C4 + CUF

Si-Bridge

(Build-up Layer) (Core Layer)

Max

Laminate substrate Package center

(a)

(c)

Fig. 5.16 a Close-up of the chiplet, bridge, C4 bump + underfill, and substrate. b Shear stress distribution in the C4 bump. c Tensile stress distribution in the C4 bump. (− 25 ↔ 125 °C)

Si chip

Si interposer Organic laminate Fig. 5.17 DBHi test vehicle

394

5 Chiplets Lateral Communications

Fig. 5.18 DBHi TCB with NCP. a Solder joint with entrapped fillers. b Optimal solder joints

Si Chip Cu (a)

Solder

Cu Entrapped Fillers

Underfill

Si Interposer

Si Chip (b)

Cu Solder Cu

Underfill

Ideal Joint Si Interposer

Fig. 5.19 Thermal cycling test results. Solder cracks at 1000 cycles (− 55 ↔ 125 °C)

Si Chip Underfill

Si interposer Si Chip Cu Solder cracking Underfill

Cu Si interposer

5.4 IBM’s DBHi

395

Side-view Glass subassembly Glass chip Adhesive Spacer Underfill dispenser Glass bridge

Glass substrate

Scan

Top-view Glass chip

Spacer Glass substrate

Glass bridge

(b)

Glass bridge (a)

Glass substrate

Glass chips

Fig. 5.20 a Glass mock-up for a DBHi structure. b The underfill dispense pattern

Side-view Glass chips

Top-view

Adhesive

Glass chips Glass Si bridge Spacer

Glass substrate

Glass bridge Glass substrate Chip-to-chip gap

C4 height

Bridge-cavity sidewall gap

Bridge-cavity bottom gap Bridge-cavity sidewall gap

Fig. 5.21 Critical dimensional parameters of the underfill flow in the DBHi structure

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5 Chiplets Lateral Communications

Glass substrate Spacer (a)

Glass substrate

Sample

C4 Height

Time from starting UF dispense 15 sec

I-A

49μm

I-B

85μm

20 sec

25 sec

(b)

Spacer Fig. 5.22 a Test vehicle. b Underfill flow characteristics for different C4 bump heights

Figure 5.22a shows the test vehicle to investigate the underfill flow characteristics between two glass substrates connected with C4 bumps. There are two different C4 bump heights: 49 μm and 85 μm. Figure 5.22b shows the underfill dispensing characteristics. The dark areas are filled with underfill from the top-view of the samples. It can be seen that: (a) the longer the times the more underfills are filled, and (b) the larger the C4 bump heights the more underfills are filled. Figure 5.23a shows another test vehicle to investigate the underfill flow characteristics between two chips. This is to study the effect of gap between the bridge sidewall to the cavity of the package substrate. Two gaps are studied, 44 μm and 86 μm and the C4 bump height of both chips is 50 μm. Figure 5.23b shows the underfill dispensing characteristics. The dark areas are filled with underfill from the top-view of the samples. It can be seen that: (a) the larger the gaps between the bridge sidewall and the cavity the larger the underfills filled, and (b) the longer the times the more the underfills are filled.

5.5 Université de Sherbrooke/IBM’s Self-aligned Bridge

397

Glass chips Spacer (a)

Glass substrate Sample

Bridge-cavity sidewall gap

Time from starting UF dispense 25 sec

II-A

86μm

II-B

44μm

30 sec

35 sec

(b)

Fig. 5.23 a Test vehicle. b Underfill flow characteristic for different bridge-cavity sidewall gaps

5.4.4 DBHi Challenges The challenges in IBM’s DBHi are: • Handling and bonding of a portion of the tiny rigid bridge on a portion of the large chiplet with very fine-pitch pads. • Dealing with a situation in which there are more than one rigid bridge on a chiplet. • Dealing with a situation in which there are more than two chiplets on a package substrate.

5.5 Université de Sherbrooke/IBM’s Self-aligned Bridge Université de Sherbrooke/IBM’s self-aligned bridge is shown in Fig. 5.24 [17]. It can be seen that in this study they are trying to use self-aligned method to assembly the bridge and the self-aligned structure is the V-groove opening of the bridge and Sn3Ag0.5Cu solder spheres. When the solder spheres reflow, the surface tension of the melted solder [31–59] is supposed to pull (self-align) the bridge to the accurate position. In this study, the substrate is not an organic package substrate but a silicon substrate.

398

5 Chiplets Lateral Communications Chip 1

Substrate

Si Bridge

μbump

Self-aligned Structure

Chip 2

C4 Bump

Fig. 5.24 Self-aligned structure in an embedded bridge in the cavity of package substrate

5.5.1 Process Flow of the V-Groove Opening of the Self-aligned Bridge The process flow of the V-groove opening of the self-aligned bridge is shown in Fig. 5.25 [17]. First, fabricate the Cu-pillars on the topside of a piece of silicon sample (3.35 mm × 2.5 mm × 0.2 mm) and then spin coat BrewerScience’s Waferbond CR200 (65 μm-thick) to cover the Cu posts and BrewerScience’s Protek PSB to the backside of the sample, Fig. 5.25a–c. The CR200 is to protect the Cu posts from potassium hydroxide (KOH) etching bath and the ProTEK PSB is an alternative to SiO2 . It is followed by the photolithography exposure and development of hard mask layer (ProTEK PSB), Fig. 5.25d. Then, wet etching in KOH bath of V-groove on the backside of the Si bridge and then removing the ProTEK PSB as shown in Fig. 5.25e, f. It is followed by removing the CR200 and cleaning the sample, Fig. 5.25g, h. The mean height of the Cu posts is 39 μm before the V-groove opening and is 38.1 μm after. The mean diameter of the Cu posts is 37.1 μm before the V-groove opening and is 38.2 μm after. The KOH etching bath conditions are: concentration = 32%, formulation = 400 mL 45% KOH solution + 160 mL DI water, total volume = 560 mL, temperature = 75 °C, additive = 60 mL isopropanol, stirring (not applied), and duration = 45 min. Figure 5.26a shows the laser confocal microscopy image of the top-down view of the etched V-groove before the removal of ProTEK PSB. It can be seen that noticeable defects such as: (a) undesired undercuts, (b) four round corners, and (c) slightly curved outlines in some regions. Figure 5.26b shows the images of the etched V-groove after the removal of the ProTEK PSB. Figure 5.26c shows the optical-laser 3D top-down view of the etched V-groove after the removal of the ProTEK PSB and it can be seen that there are some tiny dents on the sidewall, but generally it is smooth. The SAC305 solder spheres with an average diameter equals to 102 μm are shown in Fig. 5.27a. The Cu bonding pad (101.5 μm) with NiAu finishing on a silicon substrate for the solder sphere is shown in Fig. 5.27b. The reflow temperature profile with a peak temperature equals to 260 °C is shown in Fig. 5.28. The assembly

5.5 Université de Sherbrooke/IBM’s Self-aligned Bridge

399

(1) Prepare sample (5) Open V-groove

(2) Spin coat CR200 (6) Remove ProTEK PSB

(3) Spin coat ProTEK PSB

(4) Pattern ProTEK PSB

(7) Remove CR200

(8) Clean sample

Fig. 5.25 Process flow of the self-aligned bridge

of the bridge (with Cu posts on its topside and V-groove at its bottom-side) and the silicon substrate are shown in Fig. 5.29 (the central portion of the assembly is not shown). The L shape is for alignment purposes. Underfill has been applied between the gap of the bridge and substrate.

5.5.2 Measurement Results The measurement results show that: (a) the rotation of the Si bridge with respect to the silicon substrate is very small (0.001 degree), (b) the Si bridge shift merely 2.5 ± 0.9 μm in the short dimension, and (c) the Si bridge shift 9.5 ± 2.2 μm in the long dimension.

5.5.3 Challenges of Self-aligned Bridge The most challenge of self-aligned bridge is the vertical variation between the Cu posts of the Si bridge and the top-surface of the Si substrate, which has not been discussed in the paper. The flatness of the surface (from the Cu posts of the Si bridge and from the Si substrate) is the most important factor for the high-yield assembly of chips bonding.

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5 Chiplets Lateral Communications

10.0

Round corner

148.3

Etching window Undercut 50μm

(a)

(b)

11.0 11.5

10.5μm

(c)

Fig. 5.26 a Top-view of the V-groove before the removal of ProTEK PSB. b Top-view of the Vgroove after the removal of ProTEK PSB. c 3D optical-laser view of the V-groove after the removal of the V-groove

5.6 Patents on Rigid Bridges with Fan-Out Packaging Intel’s and IBM’s rigid bridges are either embedded in or are on an organic package substrate. There is another class of rigid bridge, which is embedded in the fan-out EMC and/or connected to the fan-out RDL-substrate. On May 12, 2020, Applied Materials obtained the US patent 10,651,126 [18]. The company’s design embedded the bridge in EMC by the fan-out chip (bridge) first and die face-up process (Fig. 5.30). This could be the very first patent of a rigid bridge embedded in fanout EMC. On June 21, 2022, Unimicron obtained the US patent 11,410,933 [19] in which the bridge is embedded in the fan-out EMC by the chip (bridge) first and die facedown process (Fig. 5.31). For the patent on rigid bridge embedded in the EMC and connected to the RDL-substrate by the chip (bridge) last or RDL-first fan-out process, IME obtained the US patent 11,018,080 on May 25, 2021 (Fig. 5.32) [20].

5.6 Patents on Rigid Bridges with Fan-Out Packaging

(a)

Sphere 1

Sphere 2

Sphere 3

Sphere 4

50μm

101.5μm

(b)

Fig. 5.27 a Top-view of the SAC solder spheres. b Pad geometry

Fig. 5.28 Lead-free reflow temperature profile

401

402

5 Chiplets Lateral Communications

L Shape mark on Si substrate

L Shape mark on Si bridge

Si substrate Si bridge

Underfill

Cu post

200µm

Fig. 5.29 SEM images of the four corners of the final stack. Alignment (L shape) mark is on the bridge as well as on the substrate

Applied Materials’ Fan-out Chip (Bridge) First and die Face-Up Process Cu-contact Stud (Pillar) CHIP

CHIP Bridge RDLs

Die attach

Backgrinding surface RDL Substrate

Solder Ball

Fig. 5.30 Applied materials’ bridge patent with fan-out chip (bridge) first and die face-up process (US 10,651,126)

5.8 SLIP’s FO-EB and FO-EB-T

403

Unimicron’s Fan-out Chip (Bridge) First and Die Face-Down Process

C2 bump

C4 bump

Chip 2

Chip 1 RDLs RDLs Si Bridge

TMV

EMC/ABF RDLs

Fig. 5.31 Unimicron’s bridge patent with fan-out chip (bridge) first and die face-down process (US 11,410,933)

5.7 TSMC’s LSI On August 25, 2020, during TSMC’s Annual Technology Symposium, the company announced its local silicon interconnect (LSI) technology for chiplet lateral communication. The integrated fan-out local silicon interconnect (InFO_LSI) is schematically shown in Fig. 5.33a and the chip-on-wafer-on-substrate local silicon interconnect (CoWoS _LSI) is shown in Fig. 5.33b.

5.8 SLIP’s FO-EB and FO-EB-T During IEEE/ECTC and IEEE/EPTC 2020 to 2022, SPIL published at least 5 papers on bridges embedded in EMC and connected to RDL-substrate [21–25]. They called it fan-out embedded bridge (FO-EB) and fan-out embedded bridge with TSV (FOEB-T).

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5 Chiplets Lateral Communications

IME’s Fan-out Chip (Bridge) Last (RDL –First) Process Chip 1Chip 2

RDLs EMC TMV

PCB Bridge Fig. 5.32 IME’s bridge patent with fan-out chip (bridge) last or RDL-first process (US 11,018,080) Fig. 5.33 a TSMC’s InFO-LSI. b CoWoS-LSI

InFO_LSI

(a)

LSI

HBM

LSI

HBM

LSI

ASIC HBM

(b)

HBM

CoWoS_LSI

LSI

5.8 SLIP’s FO-EB and FO-EB-T

405

5.8.1 FO-EB Figure 5.34 shows the FO-EB by SPIL [21–24]. It can be seen that the SoC is connected to the HBM with the embedded silicon bridge die. The silicon bridge die is embedded in an EMC and is connected to the RDL. The assembly process is shown in Fig. 5.35. It can be seen that on the temporary glass carrier, they first build the RDL1, Cu-pad, and electroplate the Cu post, and then attach the bridge die on the RDL1, Fig. 5.35a. It is followed by molding and grinding to expose the Cu posts, Fig. 5.35b. Then, fabricate RDL2 and the micro pads, Fig. 5.35c. It is followed by SoC and HBM bonding on RDL2 and then molding, Fig. 5.35d. Then, remove the temporary glass carrier and C4 bumping, Fig. 5.35e. Finally, flip chip assembly the module on a package substrate, Fig. 5.35f. A typical cross section SEM image of the FO-EM is shown in Fig. 5.30. The bridge, SoC, HBM, μbump, RDL1 and RDL2 are clearly seen. A test vehicle of FO-EB is shown in Fig. 5.36. It can be seen that the fan-out RDL2 is supporting the GPU (graph processor unit) and the 4 HBMs on its topside and the 4 ICDs (inter connect dies) or bridges on its bottom-side. The whole module is attached on a build-up package substrate. The maximum bridge die size is 36mm2 . The module size is 30 mm × 45 mm and the package size is 70 mm × 80 mm. Bridge Die

(a)

(b)

RDL2

Bridge Die

RDL1

(c) Fig. 5.34 SPIL’s FO-EB. a SEM image of FO-EB. b Schematic of FO-EB. c Schematic of the FO-EB structure

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5 Chiplets Lateral Communications

(a) Cu post and bridge die

(b) Organic interposer

(c) RDL2 and μPad

(d) Logic and memory die

(e) C4 bumps

(f) Flip chip Fig. 5.35 Process flow of FO-EB

Figure 5.37 shows the SEM images of some critical areas. Figure 5.38a shows the interface between the SoC and the HBM. Figure 5.38b shows fan-out RDL2 with the Cu-stud of the GPU on its topside and the bridge with μbump on its bottom-side. Figure 5.38c shows the bridge. Figure 5.38d shows a couple of the TIY (through interconnect vias), and Fig. 5.38e shows the underfill. All these images demonstrate the key components are properly done.

5.8.2 FO-EB-T Figure 5.39 shows the schematic of the FO-EB-T [25]. It can be seen that the key difference between the FO-EB and the FO-EB-T is there are TSVs in the bridge of the FO-EB-T as shown in Fig. 5.40. The assembly process of the FO-EB-T is exactly

5.8 SLIP’s FO-EB and FO-EB-T

407

HBM ICD

SPIL ICD HBM

GPU ICD HBM

HBM ICD

ICD (Inter Connect Die) = Bridge Underfill EMC Underfill

C2 Bump

ICD

HBM

RDL2

GPU

HBM

C2 Bump TIV C4 Bump

Package Substrate BGA Solder Ball Fig. 5.36 Test vehicle of FO-EB

RDL2 RDL1 μbump

Fig. 5.37 SEM image of the FO-EB

the same as that of the FO-EB, except while fabricate the RDLs on the silicon wafer the TSVs should also be fabricated. The electrical performances between FO-EB-T, FO-EB, and 2.5 IC integration are shown in Table 5.1. It can be seen that; (a) for SoC and HBM construction, the

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5 Chiplets Lateral Communications

RDL1

RDL2

HBM

Bridge

RDL2

EMC

TIV

GUP

Bridge or ICD TIV

Cu Stud, RDL2, μPad, μBump

Bridge

Fig. 5.38 Details of the FO-EB

Underfill EMC Underfill

C2 Bump

ICD

HBM

RDLs

GPU

HBM

C2 Bump TMV C4 Bump

RDLs

TSV

TSV

Package Substrate BGA Solder Ball ICD (Inter Connect Die) = Bridge Fig. 5.39 SPIL’s FO-EB-T

electrical simulation is performed by RC (resistive-capacitive) delay from the SoC to the HBM, (b) for SoC and C4 bump construction, the simulation is performed by DCR (direct current resistant) from the SoC to C4 bump, and (c) for SoC and solder ball construction, the simulation is performed by the insertion loss from the SoC to solder ball. The simulation results of the 2.5D are to be taken as the baseline and some of the results are summarized in Table 5.1. It can be seen that the RC delay and insertion loss of FO-EB and FO-EB-T are lower (better) than that of 2.5D. This is because of the wider line width and spacing of the RDL of the FO-EB and FO-EB-T. The DCR of FO-EB is higher than that of 2.5D because the power transmission by TIV is poorer than that of TSV. On the other hand, the DCR of FO-EB-T (the bridge with TSVs) is the same as the 2.5D IC integration. The simulation result shows [25] that because of the bridge with TSVs there are 55% resistance improvement.

5.9 ASE’s sFOCoS

409

HBM

HBM µbump

RDL2

RDL2

TMV RDL1

TMV RDL1

RDL

μBump

Fig. 5.40 Comparison between FO-EB and FO-EB-T

Table 5.1 Electrical comparison between FO-EB and FO-EB-T Platform

2.5D

Configuration

SoC + HBM

RDL layer, L/S

4L, 0.4/0.4 μm

FO-EB

FO-EB-T

1L, 10/10 μm

1L, 10/10 μm

SoC to HBM

RC delay

Baseline

Lower

Lower

SoC to C4 bump

DCR (power)

Baseline

Higher

Same as baseline

SoC to solder ball

Insertion loss (1 GHz)

Baseline

Lower

Lower

5.9 ASE’s sFOCoS 5.9.1 The Structure and Process of sFOCoS Figure 5.41 shows the bridge embedded in EMC and connected to fan-out RDLs which called sFOCoS (stacked Si bridge fanout chip on substrate) [26]. It can be seen that the fan-out (L/S = 10/10 μm) RDLs are supporting the one ASIC and one HBM on its topside and the (L/S = 0.8 μm) Si bridge die (6 mm × 6 mm) at its bottom-side. The assembly process is shown in Fig. 5.42. First, separately, prepare the temporary glass wafer carrier and bridges with μbumps from a silicon wafer. Then, attach the bridge with μbumps to the wafer carrier and electroplate the Cu posts from the

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5 Chiplets Lateral Communications

ASIC

HBM

EMC

μbumps

Underfill

μbumps Cu post

RDLs

EMC

Si Bridge Underfill

Package Substrate

C4 Bumps

BGA Solder Ball

Fig. 5.41 ASE’s sFOCoS

wafer carrier. It is followed by EMC molding of the whole wafer carrier, grinding the EMC to expose the Cu post, and fabricating the RDLs. Then, attach the ASIC and HBMs on the RDLs and mold the EMC. It is followed by removing the temporary glass wafer carrier, mounting the C4 bumps, and dicing the reconstituted wafer into individual module (27 mm × 14 mm). Finally, attach the module to a package substrate (40 mm × 30 mm) and underfilled. This process is very similar to SPIL’s.

5.9.2 The Structure and Process of FOCoS-CL Figure 5.43 shows a schematic of ASE’s FOCoS-CL (chip-last). It can be seen that one ASIC and two HBMs are supporting by a fan-out chip-last (or RDL-first) 4-layer (L/S = 2/2 μm) RDL with μbumps, which is connected to a build-up package substrate (47.5 mm × 47.5 mm) with C4 bumps. The process flow is shown in Fig. 5.44. It can be seen that, first fabricate the RDLs on a temporary glass wafer carrier. It is followed by attaching the ASIC and HBM on the RDLs, molding the EMC, removing the temporary carrier, and mounting the C4 bumps. Then, backgrind the EMC and dicing the reconstituted wafer into individual module (30 mm × 28 mm). Finally, attach the individual module to a package substrate.

5.9 ASE’s sFOCoS

411 µbump

Wafer Carrier & Bridge with µbump

Wafer Carrier

Bridge

Cu Post

Attach bridge to the wafer carrier and then Cu post plating

µbump HBM

ASIC

The wafer is molded and grinded to expose the Cu post. Then build the RDLs. It is followed by ACIS and HBM attachment, and then molding.

Underfill

RDLs

ASIC

Temporary wafer Carrier removing and C4 bump mounting. Dicing into individual module.

HBM

C4 bump

Module on package substrate and underfill

Underfill Package Substrate

EMC

Fig. 5.42 Process flow of sFOCoS

ASIC

HBM

μbumps Underfill

Underfill

RDLs C4 bumps Build-up layers Package Substrate (core) Build-up layers BGA Solder Ball

Fig. 5.43 Schematic of ASE’s FOCoS-CL

5.9.3 Reliability and Warpage Between sFOCoS and FOCoS-CL The reliability and warpage comparing between the sFOCoS and FOCoS-CL is shown in Fig. 5.45. Figure 5.45a shows the JEDEC standard reliability test results. It

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5 Chiplets Lateral Communications

Temporary wafer carrier

C4 bumps

Wafer glass carrier

RDLs Remove carrier and C4 bumping Fabricate the RDLs ASIC

HBM Backgrind the EMC and dicing the wafer into individual module

Chip/HBM bonding on RDLs EMC Package Substrate

Underfilling and EMC molding

BGA Solder Ball Attach the module on package substrate

Fig. 5.44 Process flow of FOCoS-CL

can be seen that for all the tests, the performances of the FOCoS are better than those of the sFOCoS. One of the key reasons could be the existing of the Si bridge (2.5 × 10–6 /°C), which is very close to the organic package substrate (18.5 × 10–6 /°C). Nevertheless, both FOCoS-CL and sFOCoS passed all the reliability tests. Figure 5.45b shows the warpage comparison between the FOCoS-CL and sFOCoS. The temperature profile is the lead-free soldering reflow profile: from room temperature to peak temperature (260 °C) and then return to room temperature. First of all, the overall warpages between the FOCoS-CL and sFOCoS are very close and in the acceptable range. Near at room temperature, the warpage of the sFOCoS is slightly lower than that of the FOCoS-CL, while near at peak temperature, the warpage of the sFOCoS is higher than that of the FOCoS-CL.

5.10 Amkor’s S-Connect

413

FOCoS (Chip-Last)

Bridge

(b)

Warpage (µm)

(a)

FOCoS (Chip-Last) sFOCoS

Temperature Fig. 5.45 Comparison between FOCoS-CL and sFOCoS. a Reliability tests. b Warpage

5.10 Amkor’s S-Connect Figures 5.46 and 5.47 show the schematic of Amkor’s embedded bridge in EMC and connected to a fan-out RDL substrate called S-connect [27]. It can be seen that the fan-out RDL is supporting the ASIC and HBM on its topside and the bridge and some IPD (integrated passive devices) at its bottom-side. Their bridge can be either the ordinary Si bridge made from a silicon wafer (Fig. 5.46), or a molded RDL bridge die made from fan-out packaging as shown in Fig. 5.47. Thus, there are two different S-connects, one is with the ordinary Si bridge, Fig. 5.46, and the other is with the molded RDL bridge, Fig. 5.47.

5.10.1 S-Connect with Si-Bridge The S-connect with Si-bridge is shown in Fig. 5.46. The assembly process of the key components is also shown in 5.48. First, separately: (a) fabricate the RDL on a temporary wafer glass carrier, (b) wafer bumping of the ASIC and HBM and then

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5 Chiplets Lateral Communications μbump

Underfill

HBM ASIC TMV RDLs

µbump RDLs Si-Bridge

IPD

C4 bump

Underfill Package Substrate

BGA Solder Ball

Fig. 5.46 Amkor’s S-Connect with Si-bridge μbump

Underfill

HBM ASIC

µbump RDLs

(a) TMV RDLs

Bridge IPD

C4 bump

Underfill Package Substrate

BGA Solder Ball μbump (b)

Multi-layer RDLs on a mold block having Cu vertical through via (molded RDL bridge die)

RDLs Cu

EMC

Molded RDL Bridge Die

Fig. 5.47 Amkor’s S-Connect with molded RDL bridge die

singulation, (c) fabricate the Si-bridge with μbumps and then singulation, and (d) fabricate the IPD with μbumps and then singulation. Then, assembly all the key components into a module shown in the right-hand side of Figs. 5.46 and 5.48. The SEM image of the S-connect cross section with Si-bridge is shown in Fig. 5.49.

5.10 Amkor’s S-Connect

415

ASIC and HBM µbump plating and singulation

HBM

ASIC

Fabrication of RDLs on a carrier wafer

IPD, Si Bridge, and molded RDL bridge µbump plating and singulation

ASIC

μbump

μbump

μbump Cu

Si RDL Bridge

IPD

Mold RDL Bridge

HBM

HBM ASIC

IPD

IPD Molded RDL Bridge

Si RDL Bridge

S-connect module with molded RDL bridge die

S-connect module with Si RDL bridge die

Fig. 5.48 Process flow of S-Connect with Si-bridge and molded RDL bridge

Fig. 5.49 SEM images of S-Connect with Si-bridge

ASIC µbump

HBM

RDL

Si-Bridge

(a) RDLs-interposer. (b) Si RDL bridge die.

5.10.2 S-Connect with Molded RDL-Bridge The S-connect with molded RDL bridge is shown in Fig. 5.47. The assembly process of the key components is also shown in 5.48. First, separately: (a) fabricate the molded RDL bridge on a mold block having Cu vertical through via as shown in Fig. 5.47b,

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5 Chiplets Lateral Communications

d

HBM

ASIC

µbump Molded RDL-Bridge

(b)

HBM µbump RDL

Molded RDL-Bridge

Fig. 5.50 SEM image of S-Connect with molded RDL bridge. a RDLs. b HBM. c Molded RDLbridge. d ASIC

(b) wafer bumping of the ASIC and HBM and then singulation, (c) fabricate the Si-bridge with μbumps and then singulation, and (d) fabricate the IPD with μbumps and then singulation. Then, assembly all the key components into a module as shown in the left-hand side of Figs. 5.47 and 5.48. The SEM image of the S-connect cross section with molded RDL-bridge is shown in Fig. 5.50.

5.11 IME’s EFI Figure 5.51 shows the embedded bridge in EMC and connected to fan-out RDL called EFI (embedded fine pitch interconnect) [28]. It can be seen that RDL layer is supporting the ASIC, HBM, and SERDES on its topside and the Si-bridge on its bottom-side. The whole module is attached to a PCB (printed circuit board).

5.11.1 Process Flow of EFI The fabrication process flow is shown in Fig. 5.52. It can be seen that the RDL is first fabricated on a temporary glass wafer carrier with a sacrificial layer, Fig. 5.52a, b. It is followed by electroplating the Cu posts and attaching the Si-bridge on the

5.11 IME’s EFI

417

ASIC

SERDES

PHY

PHY

HBM

RDLs Cu post

EMC

EFI PCB

(Bridge)

Fig. 5.51 IME’s bridge with EFI

RDL, Fig. 5.52c, d. Then, mold the EMC on the whole wafer, backgrind the EMC to expose the Cu post, and make isolation layer and UBM, Fig. 5.52e, f. It is followed by removing the temporary carrier by laser de-bonding and cleaning, solder ball mounting, and singulating into individual unit, Fig. 5.52g, h. Then, attach the ASIC and memory on the individual unit (a module) and finally attach the individual module to a PCB, Fig. 5.52i. Figure 5.53 shows some of the image of a test vehicle of the EIF. It can be seen that the RDL is supporting one ASIC and two HBMs and the Si bridge.

(a) Sacrificial layer deposited on glass carrier (f) Bottom isolation layer and UBM fabrication (b) RDL & UBM fabrication on sacrificial layer (g) Carrier laser de-bonding & cleaning

(c) Cu pillar (TMI) formation

(h) Interposer singulation & solder ball attachment

(d) Assemble of EFI chip

(e) Wafer level molding and TMI reveal

Fig. 5.52 Process flow of EFI

(i) ASIC & HBM and interposer assembly

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5 Chiplets Lateral Communications

ASIC

HBM HBM

RDLs

ASIC

HBM

Bridge

RDLs Pad Solder

RDLs Pad Solder Cu

Cu Bridge

Bridge

Fig. 5.53 Images of the EFI

5.11.2 Thermal Performance of EFI Because of the Cu posts and the module is directly attached to the PCB (better thermal conductivity and shorter heat path), the thermal performance should be very good, even the module is consisted of EMC. Figure 5.54 shows the thermal performance comparison between a 2.5D IC integration and the EFI structure. It can be seen that the thermal performance of the EFI structure is better than that of the 2.5D structure.

5.12 imec’s Bridge Figure 5.55 shows imec’s bridge [29, 30]. It can be seen that imec proposed the use of the bridges + fan-out wafer-level packaging (FOWLP) technology to interconnect the logic chip, wide I/O DRAM, and the flash memory. The objective is not to use TSVs for all the device chips.

5.12 imec’s Bridge

419

Chip

Chip

Chip

Mold Interposer

Bridge

Chip

TSV TMV

Package Substrate

PCB

PCB

To maintain maximum chip temperature under 85oC Maximum dissipated heating power = 3.4W

Maximum dissipated heating power = 3.1W

Fig. 5.54 Comparison between the EFI and 2.5D IC integration

Flash Memory

Wide I/O DRAM Logic Chip

TPV Bridge with RDLs

TPV Bridge with RDLs

Cu-Pillar

RDLs

No TSVs on Device -Chips TPV is a piece of Si with TSVs Fig. 5.55 Imec’s bridge for chiplet interconnection

5.12.1 The Structure of imec’s Bridge There are seven separate dies in imec’s bridge: wide I/O DRAM, flash memory, logic, two high density through package vias (TPVs), and two Si bridges. All these dies are with μbumps (Cu pillar + solder cap). The key components are the TPVs (with 5 μm-diameter and 50 μm-deepth TSVs) and the Si bridges (20-30 μm-thick with 20 μm-pitch for the logic die and 40 μm-pitch for the TPV die).

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5 Chiplets Lateral Communications

Seven separate dies with μbumps and Cu-pillars

Fig. 5.56 Process flow for imec’s heterogeneous integration with bridges

5.12.2 The Process of imec’s Bridge The assembly process of imec’s bridge is shown in Fig. 5.56. It can be seen that, first prepare the seven dies with μbumps and Cu-pillars, Fig. 5.56a. Then, attach the die (logic, and two TPVs on a temporary wafer carrier 1 with a temporary bond material (TBM), Fig. 5.56b. It is followed by stacking those two Si bridges, waferlevel compression molding an EMC, and grinding the EMC and the backside of the bridges to expose the Cu-pillars, Fig. 5.56c, d. Then, attach another temporary carrier wafer 2 to the backside of those two bridges and Cu-pillar and remove the temporary carrier wafer 1 as shown in Fig. 5.56e. It is followed by attaching the memory dies to the logic die and TPV dies, and then wafer-level compression molding, Fig. 5.56f, g. Then, remove the temporary carrier wafer 2, C4 solder bumping, and package singulation as shown in Fig. 5.56h.

5.12.3 The Challenges of imec’s Bridge The most challenge of imec’s bridge is the stacking of the bridges on the logic die and the TPV die as shown in Fig. 5.56c. The surface of the logic die and TPV die

5.13 UCIe Consortium

421

Si Bridge 2

Si Bridge 1 Logic Carrier Wafer 1

Si Bridge 1 Logic Carrier Wafer 1 Fig. 5.57 Challenges for imec’s heterogeneous integration with bridges

must be very flat for the bonding of the Si bridge die. Otherwise, the bridge die shift or tilt could happen as shown in Fig. 5.57.

5.13 UCIe Consortium According to UCIe™ (Universal Chiplet Interconnect Express™)’s website, UCIe addresses customer requests for a more customizable, package-level integration— combining best-in-class die-to-die interconnect and protocol connections from an interoperable, multi-vendor ecosystem. This new open industry standard establishes a universal interconnect at the package-level. As of August 2, 2022, the UCIe board of directors and leadership (promoters) includes founding members ASE, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung Electronics, and TSMC, and newly-elected members, Alibaba and NVIDIA. On March 2, 2022, the consortium published the UCIe 1.0 specification, which provides a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing. Figure 5.58 shows the examples of standard packaging and advanced packaging with chiplet design and heterogeneous integration and Table 5.2 shows key metrics for standard and advanced packaging.

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5 Chiplets Lateral Communications

Die 1

Standard Package

Die 2

Package Substrate Die 1

Advanced Packaging: Examples

Die 0

Si Bridge (e.g., EMIB)

Die 1

Die 0 Package Substrate Die 0

Die 2 Si Bridge (e.g., EMIB)

Die 2

Interposer (e.g., CoWoS)

Package Substrate Die 1 Si Bridge

Die 0 Fanout Interposer (e.g., FOCoS)

Die 2 Si Bridge

Package Substrate Fig. 5.58 UCIe’s standard and advanced packaging with bridges

5.14 Flexible Bridge In addition to the rigid bridges embedded in build-up organic substrate (e.g., EMIB and DBHi) and fan-out EMC (e.g., Applied Materials, TSMC, Unimicron, ASE, Amkor, SPIL, imec, and IME), there is the flexible bridge, which is the RDL itself. The flexible bridge consists of the fine-metal L/S/H conductors in a dielectric polymer, such as polyimide film [51]. The very first flexible bridge patent application US 2006/0095639 A1 was filed by SUN Microsystems on November 2, 2004 (Fig. 5.59). For high-speed and high-frequency applications such as millimeter wave frequencies, the dielectric layer can also be a liquid crystal polymer and is called LCP-flexible bridge. The assembly process of flexible bridge is very simple and very similar to IBM’s DBHi as shown in Fig. 5.10. However, both the C4 bumps and C2 bumps should be on the chiplet (just like Intel’s EMIB case). This is because it is very difficult to do wafer bumping on a flexible bridge. The biggest challenge of the flexible bridge is handling the chiplets and flexible bridges during bonding. Also, there are other challenges if there are more than one flexible bridge on a chiplet and there are more than one chiplet with multiple flexible bridges.

5.15 Unimicron’s Hybrid Bonding Bridge

423

Table 5.2 UCIe 1.0: characteristics and key metrics Characteristics

Standard package

Date rate (GT/s)

4, 8, 12, 16, 24, 32

Advanced package Comments

Width (each cluster)

16

64

Width degradation in standard, spare lanes in advanced

Bump pitch (μm)

100–130

25–55

Interoperate across bum pitches in each package type across nodes

Channel reach (mm)

≤ 25

≤2

Lower speeds must be supported—interop, e.g., 4, 8, 12 for 12G devices

KP1/Target for key metrics

Standard package

Advanced package

Comments

B/W shoreline (GB/s/mm)

28–224

165–1317

B/W density (GB/s/mm2 )

22–125

188–1350

Conservatively estimated: AP: 45 μm; standard: 110 μm; Proportionate to data rate (4G–32G)

Power efficiency target 0.5 (ρJ/b)

0.25

Low-power entry/exit latency

0.5 ns ≤ 16G, 0.5–1 ns ≥ 24G

Power savings estimated at ≥ 85%

Latency (Tx + Rx)

< 2 ns

Incudes D2D adapter and PHY (FDI to bump and back)

Reliability (FIT)

0 < FIT (failure in time) < < 1

FIT: #failures in a billion hours (expecting ~ 1E-10) w/UCIe Flit mode

5.15 Unimicron’s Hybrid Bonding Bridge Unimicron proposed the use of Cu-Cu hybrid bonding for the bridge between chiplets in chiplet design and heterogeneous integration packaging, Fig. 5.60. The advantages of this structure are: (a) higher density and finer pitch, (b) better performance, and (c) ordinary package substrate. There are at least two options, one is with C4 bumps on the package substrate and the other is with C4 bumps on the chiplet wafer.

5.15.1 Hybrid Bonding Bridge with C4 Bumps on the Package Substrate Figure 5.61 shows the process flow of hybrid bonding bridge with C4 bumps on the package substrate. For the bridge wafer, it starts off with CVD to make a dielectric material such as SiO2 and then it is planarized by an optimized CMP process to

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5 Chiplets Lateral Communications

Flexible Bridge

Fig. 5.59 Sun Microsystems’ flexible bridge

make the Cu dishing. Then, dice the bridge wafer into individual chips (still on the blue tape of the wafer) after coating protective layer on the wafer surfaces to prevent any particle and contaminant that may cause interface voids during the subsequent bonding process. It is followed by activating the bonding surface by plasma and hydration processes for better hydrophilicity and higher density of hydroxyl group on the bonding surface. For the chiplet wafer, repeat the CVD for the SiO2 , CMP for the Cu dishing, and plasma and hydration of the activation of the bonding surface. Then, pick and place the individual bridge chip on the chiplet wafer and perform the SiO2 -to-SiO2 bonding at room temperature. It is followed by annealing for covalent bonding between oxide layers and metallic bonding between Cu-Cu contact and diffusion of Cu atoms. For the package substrate, stencil print the solder paste on the substrate and then reflow into C4 solder bumps. For the final assembly, the bridge + chiplets module is picked and placed on the package substrate, then reflow the C4 bumps.

5.15 Unimicron’s Hybrid Bonding Bridge

425 Bridge Bumpless Cu-Cu Hybrid Bonding

μbump Chip 2

Chip 2

Chip 1 C4 bump

Bridge

Chip 1 Bridge

C4 bump

Package Substrate

Package Substrate

(b)

(a)

Finer pitch (Higher density) Better performance Simpler package substrate Potentially lower cost Cu-Cu Hybrid Bonding

Chiplet

Chiplet

50μm

C4 Bump

(c)

Si-Bridge

Package Substrate

Unimicron, US patent filed on October 20, 2022

Fig. 5.60 a Conventional bridge structure. b New hybrid bonding bridge. c Hybrid bonding bridge patent application Cu Dishing SiO2

Wafer Bridge

Chiplet

Bridge Wafer

CMP

Dicing

Plasma

TopView

Chiplet

Bridge

Bridge

Hydration Chiplet

Bridge Chiplet

≤50μm Chiplet

Cu Pad

Cu Dishing SiO2

Individual Bridge-to-Chiplet Wafer bonding (RT)

Si

Chiplet Wafer

Chiplet

Cu-Cu hybrid bonding Bridge

X-View

Chiplet Wafer

Bridge

Bridge Wafer Si

CMP

Plasma

Annealing & then Dicing

Hydration

Final Assembly Squeegee Solder

Stencil

C4 bump

Package Substrate

Chiplet Cu

C4

Package Substrate

Cu

Chiplet

Bridge

Package Substrate Stencil Printing Solder

Solder Reflow

Fig. 5.61 Hybrid bonding bridge with C4 bumps on package substrate

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5 Chiplets Lateral Communications C4 bump

Wafer Chiplet

CMP

Dicing

Plasma

Hydration

CMP

Cu-Cu hybrid bonding C4 bump Bridge ≤50μm X-View

Chiplet

Chiplet

Individual Bridge-to-Chiplet Wafer bonding (RT). Then, C4 wafer bumping

Si

Chiplet Wafer

Chiplet

Cu Pad

Cu Dishing SiO2

Chiplet Wafer

Chiplet

Bridge

Chiplet

Bridge

Bridge Wafer

Top-View

Bridge

Bridge

Bridge

Cu Dishing SiO2

Bridge Wafer Si

Plasma

Annealing & then Dicing

Hydration Final Assembly

Package Substrate Package Substrate

Chiplet

Chiplet Cu

C4 bump

Cu

Bridge

Package Substrate

Fig. 5.62 Hybrid bonding bridge with C4 bumps on chiplet wafer

5.15.2 Hybrid Bonding Bridge with C4 Bumps on the Chiplet Wafer Figure 5.62 shows the process flow of hybrid bonding bridge with C4 bumps on the chiplet wafer. It can be seen that, comparing with the C4 bumps on the package substrate case, the process steps for the bridge wafer and the chiplet wafer are the same up to bridge-to-chiplet wafer bonding. After that, the C4 bumps are fabricated by wafer bumping on the chiplet wafer. Then, dice the chiplet wafer into individual module (bridge + chiplets with C4 bumps). The final assembly is by picking and placing the individual module on the package substrate and reflowing the C4 solder bumps.

5.16 Summary and Recommendations • Bridge is a small piece of chip without devices but with RDLs to let the chiplets perform mainly horizontal communication. • Some bridges also perform vertical communication like a chip without devices but with RDLs and TSVs. • There are two groups of bridges: rigid bridge and flexible bridge. • For rigid bridges, the RDLs are fabricated on a silicon wafer substrate. • Today, the rigid bridges are embedded on an organic package substrate such as the EMIB and DBHi, and embedded in fan-out EMC and connected to fan-out RDLs, such as those by Applied Materials, TSMC, Unimicron, ASE, Amkor, SPIL, IME, and imec. • A new rigid bridge called hybrid bonding bridge has been proposed which leads to a high-performance, high-density, and fine-pitch package.

References

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• For a flexible bridge, the RDL comprises the conductor layer and the polyimide dielectric layer. • For 5G millimeter wave high-frequency applications, it is recommended to replace the polyimide with the liquid crystal polymer (LCP), i.e., a LCP-flexible bridge. • The challenges of various bridges have been provided. • Bridge standards are desperately needed. UCIe is the way to go.

References 1. Lau, J. H. (2022). Bridges for chiplet design and heterogeneous integration packaging, Chip Scale Review, 26(January/February Issue), 21–28. 2. Naffziger, S., Lepak, K., Paraschour, M., & Subramony, M. (2020, February). AMD chiplet architecture for high-performance server and desktop products. In Proceedings of IEEE/ISSCC (pp. 44–45). 3. Naffziger, S. (2020, June). Chiplet meets the real world: benefits and limits of chiplet designs. In Symposia on VLSI technology and circuits (pp. 1–39). 4. http://press.xilinx.com/2013-10-20-Xilinx-and-TSMCReach-VolumeProduction-on-all28nm-CoWoSbased-All-Programmable-3D-ICFamilies 5. Banijamali, B., Chiu, C., Hsieh, C., Lin, T., Hu, C., Hou, S., & et al. (2013, May). Reliability evaluation of a CoWoS enabled 3D IC package. In Proceedings of IEEE/ECTC (pp. 35–40). 6. Chiu, C., Qian, Z., & Manusharow, M. (2014). Bridge interconnect with air gap in package assembly. US Patent No. 8,872,349. 7. Mahajan, R., Sankman, R., Patel, N., Kim, D., Aygun, K., Qian, Z., & et al. (2016). Embedded multi-die interconnect bridge (EMIB)—a high-density, high-bandwidth packaging interconnect. Proceedings of IEEE/ECTC (pp. 557–565). 8. Mahajan, R., Zhiguo, Q., Viswanath, R., Srinivasan, S., Avgun, K., Jen, W., Sharan, S., & Dhall, A. (2019). Embedded multidie interconnect bridge—a localized, high-density multichip packaging interconnect. IEEE Transactions on Components, Packaging and Manufacturing Technology, 9(10), 1952–1962. 9. Duan, G., Knaoka, Y., & McRee, R. (2021, May). Die embedded challenges for EMIB advanced packaging technology. In Proceedings of IEEE/ECT C (pp. 1–7). 10. Sikka, K., Bonam, R., Liu, Y., Andry, P., Parekh, D., Jain, A., Bergendahl, M., & et al. (2021, June). Direct bonded heterogeneous integration (DBHi) Si Bridge. In IEEE/ECTC Proceedings (pp. 136–147). 11. Matsumoto, K., Bergendahl, M., Sikka, K., Kohara, S., Mori, H., & Hisada, T. (2021). Thermal analysis of DBHi (direct bonded heterogeneous integration) Si Bridge. In Proceedings of IEEE/ECTC (pp. 1382–1390). 12. Jain, A., Sikka, K., Gomez, J., Parekh, D., Bergendahl, M., Borkulo, J., Biesheuvel, K., Doll, R., & Mueller, M. (2021, May). Laser versus blade dicing for direct bonded heterogeneous integration (DBHi) Si Bridge. In Proceedings of IEEE/ECTC (pp. 1125–1130). 13. Marushima, C., Aoki, T., Nakamura, K., Miyazawa, R., Horibe, A., Sousa, I., Sikka, K., & Hisada, T. (2022, May). Dimensional parameters controlling capillary underfill flow for voidfree encapsulation of a direct bonded heterogeneous integration (DBHi) Si-bridge Package. In Proceedings of IEEE/ECTC (pp. 586–590). 14. Horibe, A., Watanabe, T., Marushima, C., Mori, H., Kohara, S., Yu, R., Bergendahl, M., Magbitang, T., Wojtecki, R., Taneja, D., Godard, M., Cristina, C., Pulido, B., Sousa, I., Sikka, K., & Hisada, T. (2022). Characterization of non-conductive paste materials (NCP) for thermocompression bonding in a direct bonded heterogeneoussly integrated (DBHi) Si-Bridge Package. In Proceedings of IEEE/ECTC (pp. 625–630).

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15. Horbe, A., Marushima, C., Watanabe, T., Jian, A., Turcotte, E., Sousa, I., Sikka, K., & Hisada, T. (2022). Super fine jet underfill dispense technique for robust micro joint in direct bonded heterogeneous integration (DBHi) silicon bridge packages. In Proceedings of IEEE/ECTC (pp. 631–634). 16. Chowehury, P., Sakuma, K., Raghawan, S., Bergendahl, M., Sikka, K., Kohara, S., Hisada, T., Mori, H., Taneja, D., & Sousa, I. (2022, May). Thermo-mechanical analysis of thermal compression bonding chip-joint process. In Proceedings of IEEE/ECTC (pp. 579–585). 17. Qiu, Y., Beilliard, Y., Sousa, I., & Drouin, D. (2022). A self-aligned structure based on v-groove for accurate silicon bridge placement. In Proceedings of IEEE/ECTC (pp. 668–673). 18. Hsiung, C., & Sundarrajan, A. (2020, May 12). Methods and apparatus for wafer-level die bridge, US 10,651,126, date of patent. 19. Lau, J.H., Ko, C., Lin, P., Tseng, T., Tain, R., & Yang, H. (2022, August 9). Package structure and manufacturing method thereof. TW 1768874, patent date: June 21, 2022. Also, US 11,410,933, patent date. 20. Weerasekera, R., Bhattacharys, S., Chang, K., & Rao, V. (2021, May 25). Semiconductor package and method of forming the same. US 11,018,080, patent date. 21. Lin, J., Key Chung, C., Lin, C. F., Liao, A., Lu, Y., Chen, J., & Ng, D. (2020, May). Scalable chiplet package using fan-out embedded bridge. In Proceedings of IEEE/ECTC, (pp. 14–18). 22. You, J., Li, J., Ho, D., Li, J., Zhuang, M., Lai, D., Chung, C., & Wang, Y. (2021). Electrical performances of fan-out embedded bridge. In Proceedings of IEEE/ECTC (pp. 2030–2034). 23. Lin, V., Lai, D., & Wang, Y. (2022, May). The optimal solution of fan-out embedded bridge (FOEB) package evaluation during the process and reliability test. In Proceedings of IEEE/ECTC (pp. 1080–1084). 24. Su, P., Ho, D., Pu, J., & Wang, Y. (2022, May). Chiplets integrated solution with FO-EB package in HPC and networking application. In Proceedings of IEEE/ECTC (pp. 2135–2140). 25. Liu, S., Kao, N., Shih, T., & Wang, Y. (2021, December). Fan-out embedded bridge solution in HPC application. In Proceedings of IEEE/EPTC (pp. 222–225). 26. Cao, L., Lee, T., Chang, Y., Huang, S., On, J., Lin, E., Yan, O. (2021, May). Advanced HDFO packaging solutions for chiplets integration in HPC application. In Proceedings of IEEE/ECTC (pp. 8–13). 27. Lee, J., Yong, G., Jeong, M., Jeon, J., Han, D., Lee, M., Do, W., Sohn, E., Kelly, M., Hiner, D., & Khim, J. (2021, May). S-Connect fan-out interposer for next gen heterogeneous integration. In Proceedings of IEEE/ECTC (pp. 96–100). 28. Chong, C., Lim, G., Ho, D., Yong, H., Choong, C., Lim, S., & Bhattacharya, S. (2021, May). Heterogeneous integration with embedded fine interconnect. In Proceedings of IEEE/ECTC (pp. 2216–2221). 29. Podpod, A., Slabbekoorn, J., Phommahaxay, A., Duval, F., Salahouedlhadj, A., & Gonzalez, M., et al. (2018). A novel fan-out concept for ultra-high chip-to-chip interconnect density with 20-μm pitch. In Proceedings of IEEE/ECTC (pp. 370–378). 30. Podpod, A., Phommahaxay, A., Bex, P., Slabbekoorn, J., Bertheau, J., Salahouelhadj, A., Sleeckx, E., Miller, A., Beyer, G., Beyne, E., Guerrero, A., Yess, K., & Arnold, K. (2019, May). Advances in temporary carrier technology for high-density fan-out device build-up. In Proceedings of IEEE/ECTC (pp. 340–345). 31. Lau, J. H. (2023). Chiplet design and heterogeneous integration packaging. Springer. 32. Lau, J. H. (2021). Semiconductor advanced packaging. Springer. 33. Lau, J. H., & Lee, N. C. (2020). Assembly and reliability of lead-free solder joints. Springer. 34. Lau, J. H. (2019). Heterogeneous integrations. Springer. 35. Lau, J. H. (2018). Fan-out wafer-level packaging. Springer. 36. Lau, J. H. (2016). 3D IC integration and packaging. McGraw-Hill. 37. Lau, J. H. (2013). Through-silicon via (TSV) for 3D integration. McGraw-Hill. 38. Lau, J. H. (2011). Reliability of RoHS compliant 2D & 3D IC interconnects. McGraw-Hill. 39. Lau, J. H., & Lee, C. K., Premachandran, C. S., Aibin, Y. (2010). Advanced MEMS packaging. McGraw-Hill.

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Chapter 6

Cu-Cu Hybrid Bonding

6.1 Introduction Cu-Cu hybrid bonding is one of the flip chip assembly technologies [1]. There are many flip chip assembly methods [1]. The most used one is the C4 (controlled collapse chip connection) solder bumped flip chip assembly. For finer-pitch and higher-density applications, the C2 (chip connection, μbump, or Cu-pillar with solder cap) bumped flip chip assembly [1] is frequently used. However, for extremely high-density and fine-pitch applications such as artificial intelligence and high-performance computing, bumpless direct Cu-Cu bonding is preferred. The advantages of direct Cu-Cu bonding are to provide much lower electrical resistivity, extremely fine-pitch (high-density), and lower electromigration than any other interconnects. There are at least two different groups of direct Cu-Cu bonding, namely Cu-Cu thermal compression bonding (TCB) [2–11] and room-temperature direct Cu-Cu bond interconnect (hybrid bonding) [12–126]. Most direct Cu-Cu TCBs operate at high temperature (normally 350−400 °C) and high pressure to drive the diffusion of Cu atoms across the interface to form monolithic copper. Hybrid bonding (that combines a dielectric bond with a metal bond to form an interconnection) is very different from Cu-Cu TCB. The focus of this chapter is on direct Cu-Cu hybrid bonding. However, the direct Cu-Cu TCB and direct SiO2 -SiO2 TCB will be briefly mentioned first.

6.2 Direct Cu-Cu TCB 6.2.1 Some Fundamental on Direct Cu-Cu TCB In order to reduce the tendency to form native oxides which strongly affect the bonding quality and reliability, direct Cu-Cu bonding usually operates at high temperature (~400 °C) and pressure and long process time (60−120 min). These are not © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging, https://doi.org/10.1007/978-981-19-9917-8_6

431

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6 Cu-Cu Hybrid Bonding

Interfacial Adhesion Energy, G (J/m2)

desirable for throughput (not to mention the cool-down time) and the device quality and reliability. Figure 6.1 shows the effect of bonding temperature on the critical interfacial adhesion energy. (The critical interfacial adhesion energy is also called critical energy release rate at the interface. If the maximum interfacial adhesion energy is larger than the critical interfacial adhesion energy, then the interfacial delamination will take place.) It can be seen that the higher the bonding temperature the higher the critical interfacial adhesion energy (Gc ), i.e., the stronger the bond (joint). Also, it is shown from Fig. 6.1 that the higher the temperatures, the less the seams between the interface and the original bond interface tends to disappear due to an activated interdiffusion through the two interfacial layers. That’s the major reason why high temperature is needed for Cu-to-Cu bonding [1]. One way to reduce the bonding temperature and obtain high quality bonds (interconnects) is by annealing. Figure 6.2 shows the effects of various annealing temperatures on the critical interfacial adhesion energy, Gc . It can be seen that for bonding temperature at 300 °C for 30 min under 25kN force on an 8'' wafer, after annealing temperature at 300 °C for 60 min under N2 atm, the Gc is increased from 2.8 J/m2 (without annealing) to 12.2 J/m2 . Even for 60 min of annealing temperature at 250 °C, the Gc is increased to 8.9 J/m2 . However, too low an annealing temperature won’t help, e.g., 200 °C as shown in Fig. 6.2.

300oC

5

seam

4 3 2

350oC

1

seam

0 300

350

400

Bonding Temperature (oC)

Experimental Conditions Si(100)/SiO2/Ta(25nm)/PVD-Cu(1.5µm) No pre-bond/post-bond treatments Bonding temperature: 300, 350 and 400oC Bonding: 25kN, 10-3Torr, N2atm, 30min

(a)

400oC no seam

(b)

1um

Fig. 6.1 Effect of bonding temperature on bond interface properties: a interfacial adhesion energies, and b SEM images of microstructures

6.3 Direct SiO2 -SiO2 TCB

433

Interfacial Adhesion Energy, G (J/m2)

Experimental Conditions Si(100)/SiO2/Ta(25nm)/PVD-Cu(1.5µm) Wafer-level bonding: 300oC, 25kN, 10-3Torr, N2atm, 30min Post-bond annealing: 200, 250 and 300oC for 60min under N2atm 15

no annealing

200oC

large seam

12

large seam

9 6

Minimum requirement

300oC

250oC 3 0

small seam N no anneal

200

250

Almost no seam

300

Annealing Temperature (oC)

1µm (a)

(b)

Fig. 6.2 Effect of (Cu-Cu) post-bond annealing temperature on the bond interface properties: a interfacial adhesion energies, and b SEM images of microstructures

6.2.2 IBM/RPI’s Cu-Cu TCB Figure 6.3a schematically shows the IBM/RPI bonding structure of two device layers bonded in a face-to-face approach, and Fig. 6.3b shows one with the face-to-back approach [3–5]. A typical Cu-Cu interconnect is shown in Fig. 6.3c, which shows a high-quality bonding interface. Before bonding, the Cu interconnects (pads) are fabricated with the standard BEOL (back end of line) damascene process, followed by the oxide CMP (chemical–mechanical polishing) process (oxide touch-up) to recess the oxide level to 40 nm lower than the Cu surface. The bonding temperature is ramped up to 400 °C.

6.3 Direct SiO2 -SiO2 TCB 6.3.1 Some Fundamental on SiO2 -SiO2 TCB SiO2 -SiO2 bonding usually takes three steps, pre-bonding, bonding, and postbonding. The pre-bonding is operated at room temperature, which eliminates run-out errors in wafer alignment, and thus leads to higher post-bond alignment accuracy. In order to achieve covalent bonds (interconnects), the bonding temperature is very high (~400 °C). In order to achieve strong chemical bonds (interconnects) with lower annealing (post-bond) temperature (200−400 °C), the surface chemistry must

434

6 Cu-Cu Hybrid Bonding

Fig. 6.3 a Face-to-face WoW bonding. b Face-to-back WoW bonding. c IBM/RPI’s Cu-to-Cu WoW bonding

be modified by plasma activation. Figure 6.4 shows the effects of annealing temperature on the critical bonding energy. As expected, the higher the annealing temperatures the stronger the critical bonding energy. Unfortunately, due to the maximum allowable temperature of most devices, 400 °C is the most used. Figure 6.5 shows the effect of temperature annealing time on the critical surface energy at 300 °C annealing temperature. It can be seen that: (1) the longer the annealing time the larger the critical surface energy; (2) one hour annealing time is more than enough; and (3) the plasma activation on the surface chemistry before bonding has a great impact on the critical surface energy.

6.3.2 MIT’s SiO2 -SiO2 TCB Figure 6.6 schematically shows MIT’s oxide-to-oxide bonding structure of three device layers bonded at 275 °C [127–133]. It can be seen that: (a) two completed circuit wafers (Tier 1 and Tier 2) are planarized, aligned, and bonded face-to-face together; (b) a wet etch of the handle silicon exposes the buried oxide (BOX) of the upper wafer; (c) 3D vias are patterned and etched through the BOX and deposited oxides expose metal contacts in both layers; (d) a Ti/TiN liner and 1 μm of tungsten (W) are deposited to fill the 3D vias (with the larger diameter equal to 1.5 μm) and electrically connect the two layers; and (e) a third layer can then be bonded with its face to the BOX (back) of Tier (layer) 2 and 3D vias are formed. Figure 6.7 shows a typical cross section of the three-layer 3D (ring oscillator) structure. It can

6.3 Direct SiO2 -SiO2 TCB

435

Surface Surface Hydrogen bonding

Annealing Surface

Bonding energy (J/m2)

Surface

Fig. 6.4 Bonding energy (SiO2 -to-SiO2 ) as a function of temperature of annealing

Surface Energy (J/m2)

Anneal at 300ºC

Annealing Time (hour)

Si to SiO2 wafer bonding Surface energy vs. annealing time at 300oC Fig. 6.5 Surface energy as a function of thermal annealing time at 300 °C (SiO2 -to-SiO2 )

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6 Cu-Cu Hybrid Bonding

be seen that: (1) the layers are bonded and interconnected with W-plugs, (2) the conventional interlevel connections are in the bottom two layers, and (3) the 3D vias are located in the isolation (field) region between transistors. A few functional 3D structures/circuits have been created and demonstrated [127–133].

MIT’s Assembly Process for a 3D Si integration: 1. Two completed circuit wafers are planarized, aligned, and bonded face to face. 2. The handle silicon is removed. 3. 3-D vias are etched through the deposited buried oxide (BOX) and the field oxides. 4. Tungsten plugs are formed to connect circuits in both tiers. 5. After tier 3 is transferred, bond pads are etched through the BOX for testing and packaging.

WaferWafer Bond

3D Vias

W Plugs Bond Pads

Fig. 6.6 MIT’s WoW assembly process for SiO2 -to-SiO2

The tiers are bonded and interconnected with tungsten plugs; the conventional interlevel connections are seen in tiers 2 and 3, which are FDSOI tiers. Note that the 3-D vias are located in the isolation (field) region between transistors

Fig. 6.7 MIT’s SiO2 -to-SiO2 WoW bonding results

The metal pattern of tier 3 is viewed through the BOX. Tiers 2 and 1 are visible at the edge of the wafer where the tiers did not bond because of nonplanar surfaces

6.4 A Brief History of Cu-Cu Hybrid Bonding

437

6.3.3 Leti/Freescale/STMicroelectronics’ SiO2 -SiO2 TCB Figure 6.8 shows Leti/Freescale/STMicroelectronic’s dielectric-to-dielectric bonding structure of two device layers bonded at < 400 °C [134–136]. It can be seen that: (a) first, a metal level is formed on a 200 mm bulk wafer and SOI wafer; next, these wafers are bonded face to face, and then the bulk silicon of the SOI wafer is removed down to the BOX layer; (b) the interstrata vias (ISVs) are formed, which make contact from upper strata to lower strata; and (c) a metal layer is formed at the top of the back side of the SOI wafer. The typical cross-section of an ISV is shown in Fig. 6.9 [134–136], and it can be seen that this ISV (~1.5 μm) makes good contact.

6.4 A Brief History of Cu-Cu Hybrid Bonding Hybrid bonding or DBI was invented by Research Triangle Institute (RTI). They started off with the ZiBond (a direct oxide to oxide bonding that involves wafer-towafer processing at low temperatures to initiate high bond strengths). Between 2000 and 2001, Fountain, Enguist, Tong, and several other colleagues founded Ziptronic as a spin-out of RTI. Between 2004 and 2005, based on their ZiBond technology, Ziptronic combined the dielectric bond with embedded metal to simultaneously bond

Fig. 6.8 Leti/Freescale/STMicroelectronic’s SiO2 -to-SiO2 WoW bonding

438

6 Cu-Cu Hybrid Bonding Silicon BEOL Metal Oxide

Metal (Cu) recess = 3nm (a) Plasma surface Activation

Metal

Metal

Oxide Metal BEOL Silicon

Oxide to Oxide Initial Bond (b) at Room Temperature

Silicon BEOL Metal Oxide Metal Metal Oxide Metal BEOL Silicon

Heating Closes Dishing Gap (Metal CTE > Oxide CTE) (c)

Silicon BEOL Oxide Metal Oxide Metal BEOL Silicon

(300oC

Metal Metal

Silicon BEOL

Annealing for 0.5h) (d) w/out External Pressure BEOL Silicon

Fig. 6.9 Key process steps of Cu-Cu hybrid bonding

wafers and form the interconnects at low temperature (so called direct bond interconnect (DBI)). Some of their fundamental patents are shown in [12–15]. Ziptronix was acquired by Tessera on August 28, 2015. Tessera has changed its name to Xperi on February 23, 2017. In 2022, Xperi was renamed to Adeia Inc. The breakthrough for Ziptronix DBI technology came in the spring of 2015 when Sony, already using its “Zibond” oxide to oxide bonding technology extended its license to include DBI. DBI is now being used for much of the CMOS (Complementary Metal Oxide Semiconductor) image sensor market in the world’s smartphones and other image-based devices. Also, for example, YMTC (Yangtze Memory Technologies Co., Ltd.) is using the Ziptronix DBI technology in its 232-layer 3D NAND with a density of 15.2 GB/mm2 products.

6.5 Some Fundamental on Cu-Cu Hybrid Bonding Figure 6.9 shows the key process steps for the low temperature DBI [12–126]. First of all, controlling nano-scale topography is very important for the DBI technology. The dielectric surface should be extremely flat and smooth before activation and

6.6 Sony’s Direct Cu-Cu Hybrid Bonding

439

bonding. Chemical–mechanical polishing (CMP) should achieve a very low dielectric roughness (< 0.5 nm RMS) and a certain recess of metal areas below the dielectric surface as shown in Fig. 6.9a. Upon contact, the dry plasma-activated dielectric surfaces bond together instantaneously as shown in Fig. 6.9b at room temperature. The dishing gap can be closed by heating as shown in Fig. 6.9c. (This step is optional because the dishing gap can also be closed by the following annealing step.) Metalto-metal bond occurs during a subsequent batch annealing. The coefficient of thermal expansion of metals are typically far larger than dielectrics. The metal expands to fill the gap and then build up the internal pressure as shown in Fig. 6.9d. It is under this internal pressure and annealing temperature that metal atoms diffuse across the interface, making good metal-to-metal bond and hence electrical connection [56]. External pressure is optional for this type of bonding. In this case, the copper oxidation during bonding is minimized. Because the bonded oxide layer surrounding the copper interconnect protects the interconnect from oxidation in the annealing oven, thus minimizing Cu oxidation during the anneal. The bonded oxide surface also hermetically seals the Cu interconnect during operation. The impact of CMP on DBI can be seen from Fig. 6.10 [56]. Figure 6.10a shows the bonding without optimized CMP. It can be seen that there is large seams (nonbonded SiO2 -to-SiO2 areas), and they are near the Cu bonding areas. Figure 6.10b shows the bonding with much flatter oxide by CMP and DBI design, which lead to minimize the occurrence of seams. Figure 6.10c shows the bond interface of optimal CMP and DBI design, which yield no visible seam. Optimizing the CMP condition is the key to produce the right amount of surface characteristics such as metal recess, dielectric roughness, and dielectric curvature for DBI [56]. Figure 6.11 shows an optimal DBI with 4 μm-pitch and 2 μm-diameter pads.

6.6 Sony’s Direct Cu-Cu Hybrid Bonding Sony’s evolution and future prospects of stacked CMOS images sensors (CIS) are shown in Fig. 6.12 [16–21]. It can be seen that the trends of CIS are from 2D integration (the logic chip and the pixel chip are side-by-side) to 3D integration (three or more chips stacking with high density connection) and the advantage is for a smaller size package. In this section, some of their CIS with Cu-Cu hybrid bonding will be discussed. However, their CIS with oxide-oxide TCB will be briefly mentioned first.

6.6.1 Sony’s CIS with Oxide-Oxide TCB Sony’s CIS with TSV is shown in Fig. 6.13. It can be seen that the CIS consists of two chips, the CIS pixel chip and the logic circuit chip and they are vertically connected through TSVs (through-silicon vias) around their edges as shown in Fig. 6.13. The

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6 Cu-Cu Hybrid Bonding

Fig. 6.10 Cross-sectional SEM images of DBI. a Significant non-bonded SiO2 area (seam) near the Cu pads. b Minimal seam during bond. c Optimized CMP DBI without visible seams Fig. 6.11 SEM image of optimized Cu-Cu hybrid bonding

SiO2 SiO2

SiO2 SiO2

6.6 Sony’s Direct Cu-Cu Hybrid Bonding

441

Fig. 6.12 Sony’s evolution and future prospect of stacked CIS

advantages of this design are that (a) more pixels can be placed on the same CIS pixel chip size (or smaller chip size can be used for the same number of pixels) and (b) the CIS pixel chip and logic chip can be fabricated separately with different process technologies. As a result, the CIS chip size is reduced by 30% and the scaling of the logic circuit chip is increased from 500 k gates to 2400 k gates [137]. The number of TSVs is in the order of thousands, including signals, power supplies, and grounds. There is no TSV in the pixel array area. The column TSVs are placed in between the comparators on the pixel CIS chip and the counters of the logic circuits chip. The row TSVs are placed in between the row drivers of the CIS

Fig. 6.13 TCB−3D CIS pixel chip and logic IC integration with TSVs

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6 Cu-Cu Hybrid Bonding

chip and the row decoders of the logic chip (Fig. 6.13). These arrangements of the TSVs can reduce the influence of noise and make it easy to manufacture the CIS chip. For example, to reduce the influence of noise, comparators are arranged on the pixel CIS chip, which can be manufactured by using Sony’s matured process technology, rather than on the logic circuit chip. The CIS pixel chip is fabricated by the Sony conventional 1P4M BI-CIS (90 nm) process technology. The logic chip is fabricated by the matured 65 nm 1P7M logic process technology. The size of the pixel chip and the logic chip is about the same. The CIS Si-insulator of the CIS wafer is bonded to the logic Si-insulator of the logic wafer (SiO2 -to-SiO2 wafer-to-wafer Zibond). The TSVs are then formed, and Cu filled after the bonding of the wafers. Figures 6.14 and 6.15 show the cross-section images of the 3D CIS pixel chip and logic IC chip integration. It can be seen that (a) the top part is the CIS chip, (b) the bottom part is the logic chip, (c) the CIS wafer and the logic wafer are insulator-to-insulator (wafer-to-wafer) bonding (Fig. 6.14), and (d) the CIS chip is connected to the logic chip through TSVs (Fig. 6.15). Figure 6.16 shows a three-chip (pixel, DRAM, and logic) Cu-Cu TCB stacked CIS published by Sony in 2017 [138]. It can be seen that these chips are connected with TSVs, and the data obtained from the parallel analog-to-digital converters are buffered in the second-layer DRAM to enable slow-motion capture.

On chip color filter and micro lens BI-CIS Process Technology

W2W Bonding Surface

CIS (Si)

CIS (Insulator) Logic (Insulator)

Logic Process Technology Logic (Si) 50μm Fig. 6.14 TCB−CIS (insulator) wafer to logic (insulator) wafer bonding

6.6 Sony’s Direct Cu-Cu Hybrid Bonding

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On chip color filter and micro lens CIS (Si)

Logic (Si)

TSV

Fig. 6.15 TCB−TSVs connecting the CIS pixel chip and the logic circuit chip

6.6.2 Sony’s CIS with Cu-Cu Hybrid Bonding Sony’s CIS without TSV but with Hybrid bonding is shown in Figs. 6.17, 6.18and6.19. Sony is the first to use low temperature Cu-Cu DBI in high volume manufacturing [16–21]. Sony produced the IMX260 backside illuminated CMOS image sensor (BI-CIS) for the Samsung Galaxy S7, which shipped in 2016. Electrical test results showed that their robust Cu-Cu direct hybrid bonding achieved remarkable connectivity and reliability. The performance of the image sensor was also super. A top view and cross section views of the IMX260 BI-CIS are shown in Figs. 6.17, 6.18and6.19, respectively. It can be seen that, unlike in [137] for Sony’s ISX014 stacked camera sensor, the TSVs are eliminated and the interconnects between the BI-CIS chip and the processor chip are achieved by Cu-Cu DBI (Figs. 6.18 and 6.19). The signals are coming from the package substrate with wire bonds to the edges of the processor chip (Fig. 6.17). Usually, wafer-to-wafer bonding is for the same chip size from both wafers. In Sony’s case, the processor chip is slightly larger than the pixel chip. In order to perform wafer-to-wafer bonding, some of the area for the pixel wafer must be wasted. Also, since there are not TSVs in both chips, wire bonding on the processor chip is used to let the signals go to the next level of interconnects. The assembly process of Cu-Cu DBI starts off with surface cleaning, metal oxide removal, and activation of SiO2 or SiN (by wet cleaning and dry plasma activation) of wafers for the development of high bonding strength. Then, use optical alignment to place the wafers in contact at room temperature and in a typical cleanroom atmosphere. The first thermal annealing (100−150 °C) is designed to strengthen the bond between the SiO2 or SiN surfaces of the wafers while minimizing the stress in the interface due to the thermal expansion mismatch among the Si, Cu, and SiO2 or SiN. Then, apply higher temperature and pressure (300 °C, 25 kN, 10-3 Torr, N2atm) for

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6 Cu-Cu Hybrid Bonding

Fig. 6.16 TCB−Cu-Cu 3-chip stacked CIS

30 min to introduce the Cu diffusion at the interface and grain growth across the bond interface. The post-bond annealing is 300 °C under N2atm for 60 min. This process leads to the seam-less bonds (Figs. 6.18 and 6.19) formed for both Cu and SiO2 or SiN at the same time.

6.6 Sony’s Direct Cu-Cu Hybrid Bonding

445

Processor Chip

Processor Chip BI-CIS Chip

BI-CIS Chip

Wirebonds

Wirebonds

Fig. 6.17 3D CIS and processor IC integration without TSVs (hybrid bonding)

Microlens

BI-CIS Chip SiO2-SiO2

3μm

Cu-Cu 6μm

Processor Chip

Fig. 6.18 SEM image of 3D CIS and processor IC hybrid bonding

6.6.3 Sony’s Three-Wafer Hybrid Bonding During IEEE/ECTC 2022, Sony published a paper on the development of face-toface and face-to-back ultra-fine pitch Cu-Cu hybrid bonding of three wafers together

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6 Cu-Cu Hybrid Bonding

CIS CMOS Image Sensor (CIS) SiO2-SiO2

Cu-Cu

Image Signal Processor (ISP)

ISP

Fig. 6.19 SEM image of 3D CIS and processor IC hybrid bonding

[20]. Figure 6.20 schematically shows the structure of the stacking of three chips (pixel, pixel parallel, and logic). The top wafer (face-down) and the middle wafer (face-up) are face-to-face hybrid bonding, while the middle wafer (face-down) and the bottom wafer (face-up) are face-to-back hybrid bonding. The TSVs in the middle wafer are fabricated by the via-last TSV process (Sect. 3.2.5). The advantages of this structure are the waferlevel Cu-Cu hybrid bonding can electrically connect the upper and lower chips with extremely high density compared to the conventional microbump technology.

SONY’s future CMOS image sensors technology

Fig. 6.20 The structure of three-chip stacked (hybrid bonding)

6.6 Sony’s Direct Cu-Cu Hybrid Bonding

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Figure 6.21 shows the assembly process. It can be seen that the top wafer (facedown) and the middle wafer (face-up) are face-to-face hybrid bonding, Fig. 6.21a. In order for the convenience in fabricating the TSVs in the middle wafer and reducing the total module thickness, the middle wafer is thinning down to ≤ 50 μm, Fig. 6.21b. Then, fabricate the TSVs and Cu-pads in the middle wafer as shown in Fig. 6.21c. Finally, the top and middle wafer (face-down) and the bottom wafer (face-up) are face-to-back hybrid bonding, Fig. 6.21d. Figure 6.22 shows a typical HAADF (highangle annular dark field) STEM (scanning transmission electron microscopy) image of the face-to-back hybrid bonding between the bottom wafer and the middle wafer (1.4 μm pitch) [20]. It can be seen that the Cu-Cu hybrid bonding is properly done. Also, Sony shows that face-to-face hybrid bonding can go down to 1.0 μm pitch.

Fig. 6.21 Hybrid bonding assembly process flow of three-chip stacked

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6 Cu-Cu Hybrid Bonding

Fig. 6.22 HAADF STEM image of three-chip stacked (hybrid bonding)

6.6.4 Sony’s Bond Strength on W2W Hybrid Bonding During IEEE/ECTC 2022, Sony presented another paper on the behavior of bond strength on wafer-to-wafer Cu-Cu hybrid bonding [21]. They showed that before the annealing process, the bonding strength of oxides decreases linearly as misalignment between the Cu and oxide increases as shown in Fig. 6.23a. After annealing process, the bonding strength of oxides increases due to dehydration condensation. Also, the bonding strength behavior is complex as shown in Fig. 6.23b. This is due to the mixed result of the bonding strength from Cu-oxide, Cu-Cu, and oxide-oxide. The values of bonding strength in both graphs of Fig. 6.23 are normalized by the maximum value of each graph.

6.7 SK Hynix’s Cu-Cu Hybrid Bonding 6.7.1 Hybrid Bonding for DRAM Applications Currently the HBM (high bandwidth memory) [139] is fabricated by TCB with μbumps and NCP (nonconductive paste) or NCF (nonconductive film), one DRAM (dynamic random-access memory) at a time. Throughput is an issue. It would be nice if we could use WoW (wafer-on-wafer) hybrid bonding to assembly the DRAMs into HBMs. During IEEE/ECTC 2022, SK Hynix published a paper on WoW hybrid

449

Normalized Bonding Strength

Normalized Bonding Strength

6.7 SK Hynix’s Cu-Cu Hybrid Bonding

Cu/SiO2 Contact Area (%)

(a)

Cu/SiO2 Contact Area (%)

(b)

Fig. 6.23 a Before annealing−bonding strength versus misalignment. b After annealing−bonding strength versus misalignment

bonding for DRAM applications [22]. They demonstrated that the application of hybrid bonding can be extended to commercially available DRAM of HBM. Figure 6.24 schematically shows the assembly process of the hybrid bonding of DRAMs. Figure 6.24a shows the commercially available DRAM wafer. Figure 6.24b shows the metallization process for the bonding Cu pads (with a dishing < 5 nm) on the commercially available DRAM wafer and the other bare silicon wafer (thinned down to a few μm). Figure 6.24c shows the hybrid bonding of these two wafers. Figure 6.24d shows the fabrication of the TSVs by the via-last process and then metallization the bonding Cu pads. It should be pointed out that they use the SiCN as the dielectric material for the passivation, because the bonding strength of SiCN is stronger than that of the SiO2 . The hybrid bonding structures have been investigated in [22] by TEM (transmission electron microscopy) analysis. Figure 6.25 shows both the bad one and good one. Figure 6.25a shows the bad one, which the voids are obviously. On the other hand, Fig. 6.25b shows the good one, which is voidless. Figure 6.26 shows the SEM cross section image of the hybrid bonding of the two wafers. It can be seen that the hybrid bonding is properly done.

6.7.2 Bonding Yield Improvement During IEEE/ECTC 2022, SK Hynix published another paper on the wafer bonding yield improvement through control of SiCN film composition and Cu pad shape [23]. They found that: (a) after attaching only dielectric, it was confirmed that the high carbon ratio and using O2 (oxygen) plasma shows the best bonding strength (this is due to the number of dangling bonds which made by plasma treatment through breaks the Si–C bond), (b) when Cu pad exists, it was confirmed that better bonding

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6 Cu-Cu Hybrid Bonding

(b) SiCN

Si Substrate

FLIP

SiCN

(a)

Metal 4

Metal 4

(d) (c) Si Substrate

Hybrid Bonding Interface

Metal 4 Metal 4

Probing Pad

TSV

Si

Hybrid Bonding Interface

Metal 4

Fig. 6.24 a Commercially available DRAM wafer. b Metallization for the Cu pads on the DRAM wafer and the other bare silicon wafer. c Hybrid bonding of the two wafers. d Fabrication of the TSVs and then metallization of the bonding Cu pads

quality when using a film with a high carbon ratio (the yield is improved by about 30% by changing the film to the higher carbon ratio), and (c) the Cu pad has the best bonding quality when it is in a dishing state of 3 to 5 nm.

6.8 Samsung’s Cu-Cu Hybrid Bonding During IEEE/ECTC 2022, Samsung published at least five Cu-Cu hybrid bonding papers [24–28]. In this section, some of their results will be briefly presented.

6.8 Samsung’s Cu-Cu Hybrid Bonding Fig. 6.25 a Voids. b Voidless

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(a) Cu

Cu Void Cu

Cu

(b) Cu Voidless Cu

Fig. 6.26 SEM cross section image of the optimized hybrid bonding Cu

Cu

Cu

Cu

DRAM

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6 Cu-Cu Hybrid Bonding

6.8.1 Characterization of Hybrid Bonding In [24], Samsung study the characterization of die-to-wafer hybrid bonding using heterogeneous dielectrics. First, they measure the CTE (coefficient of thermal expansion) of Cu pad versus various Cu pad volume as shown in Fig. 6.27. It can be seen that the larger the Cu volume the larger the CTE of Cu pad. Based on the measurement results, they fitted it into the following equation. α R = 0.1254 ln(V ) + 0.2175 If bonding starts from the level at which the expansion amount becomes 80%, then the target dishing values can be obtained as follow ( ) D = 0.8 × αΔT = 17.556 ln πr 2 t + 30.45 where α R is the Cu pad CTE, V is the Cu pad volume, D is the target Cu dish value, r is the Cu pad radius, and t is the Cu pad thickness. Also, in [24], they found that with more than 90% of the oxide bonding area, which determines most of the hybrid bonding strength. They studied two different combinations of dielectric materials, namely CVD#1 and CVD#1, which are primarily used in the final passivation layer, and CVD#1 and CVD#2, which are primarily used in bare wafer. They found that CVD#1-CVD#2 dielectric combination used in their study has a bonding strength (Fig. 6.28) that is 38.9% higher than that of CVD#1-CVD#1 at 2.5 J/m2 in low-temperature annealing.

CTE (Å/oC)

Fig. 6.27 CTE of Cu pad versus Cu pad volume

Cu Pad Volume (µm3)

6.8 Samsung’s Cu-Cu Hybrid Bonding

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Fig. 6.28 Excellent bonding interface/strength between CVD#1-CVD#2 dielectric combination

6.8.2 Effect of Pad Structure and Layout on Hybrid Bonding In [25], Samsung study the bonding pad structure and layout for fine pitch hybrid bonding. By using the six misalignment designs (75, 50, 35, 25, 15 and 5%) in four directions as shown in Fig. 6.29, the misalignment direction and distance can be determined by using the misalignment TEG (thermoelectric generator) through electrical test. It can check shift level by performing electrical test of specific TEG to check whether a corresponding net is electrically connected or disconnected. For example, if 1.5/1 μm misalignment net is open, 0.7/0.5/0.3/0.1 μm misalignment net is connected, the amount of misalignment can be estimated as 0.7 ~ 1.0 μm [25]. Thus, they recommend that even there is no high-resolution IR (infrared radiation) metrology equipment, if misalignment TEG is involved in the design, it will help to measure misalignment numerical values. In designing the Cu-Cu hybrid bonding, the Cu pad as well as oxide expansion at annealing temperature must be considered. The initial Cu pad design including pad dishing should be determined based on the thermal expansion of the structure at process conditions. The amount of Cu extrusion at annealing temperature can be adjusted with an appropriate pad size or by changing the bonding shape.

6.8.3 Voids in Cu-Cu Hybrid Bonding During IEEE/ECTC 2022, Samsung published a paper on the process and design optimization for Cu-Cu hybrid bonding void [26]. They pointed out that surface shape, outgassing, and foreign substances are the sources of various voids. There are at least three different kinds of foreign substances, namely, hard particles in the form of small dots such as silicon dust, atypical soft particles like polymer residue, and surface contamination from touch. The void size versus particle size for the hard particle, soft particle, and contamination are shown in Fig. 6.30. One of the risks of bonding voids is silicon popping in the subsequent heat treatment process. Figure 6.31 shows their experiments and results of two dielectric materials, two temperature conditions, and two time periods. (The dielectric material CVD1 film

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6 Cu-Cu Hybrid Bonding

Daisy Chain Misalignment Cu Cu Daisy-Chain

Overlapped Area

Top Pad

Bottom Pad

Misalignment

Overlapped Area (%)

Misalignment

75

0.2 x Radius

50

0.4 x Radius

25

0.6 x Radius

5

0.85 x Radius

Fig. 6.29 Concept of misalignment TEG design

Void Size (µm)

◆) soft particle (▼) contamination (Ā) hard particle (▲,◆

Particle Size (µm)

Fig. 6.30 The void size versus particle size for the hard particle, soft particle, and contamination

is formed by low-temperature CVD while for CVD2, which is formed by hightemperature CVD.) It can be seen that: (a) for dielectric material CVD1 and annealing temperature 1, the percent voids are ≤ 1% and almost the same from 10 to 120 min, (b) for dielectric material CVD2 and annealing temperature 2 (which is higher than temperature 1), the percent voids are from 0.35% to 5.45%, and (c) for dielectric material CVD2 and annealing temperature 2, the percent voids are ≤ 0.85% and are almost the same from 10 to 120 min. Thus, dielectric material CVD2 is chosen.

6.8 Samsung’s Cu-Cu Hybrid Bonding

Sample

455

Time

Anneal Temp

CVD1

Temp1

CVD1

Temp 2

CVD2

Temp 2

10 minutes

120 minutes

Fig. 6.31 Experiments and results of two dielectric materials, two temperature conditions, and two time periods

6.8.4 CoW Hybrid Bonding of 12-Momery Stacked During IEEE/ECTC 2022, Samsung presented a paper on memory stack process by hybrid copper bonding technology [27]. It is a die-to-wafer (D2W) Cu-Cu hybrid bonding process as shown in Fig. 6.32. It can be seen that on both the top and bottom wafers with Cu pads, it starts off with chemical vapor deposition (CVD) a dielectric material such as SiO2 and then it is planarized by an optimized chemical–mechanical polishing (CMP) process. This is the most critical step (in hybrid bonding) to obtain the desirable oxide surface topography and Cu pad dishing height. Then, dice the top wafer into individual chips (still on the blue tape of the wafer) after coating protective layer on the wafer surfaces to prevent any particle and contaminant that may cause interface voids during the subsequent bonding process. It is followed by activating the bonding surface by plasma and hydration processes for better hydrophilicity and higher density of hydroxyl group on the bonding surface. Finally, stack 12 chips vertically up on the bottom wafer by hybrid bonding and place the whole module

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6 Cu-Cu Hybrid Bonding

(a) Top Wafer Process CVD

CMP

Sawing

Plasma

Hydration

(c) D2W Bonding D2W Bonding

CVD

CMP

Plasma

Anneal

Hydration

(b) Base Wafer Process

Fig. 6.32 Die-to-wafer (D2W) Cu-Cu hybrid bonding process. a Top wafer. b Bottom wafer, c D2W bonding

in a high temperature annealing chamber for covalent bonding between oxide layers and metallic bonding between Cu-Cu contact and diffusion of Cu atoms [27]. Figure 6.33 shows the successful demonstration of a 12 stacked package structure by applying all the optimized process steps shown in Fig. 6.32. Figure 6.34 shows the images of the cross section by C2W Cu-Cu hybrid bonding. Figure 6.34a shows the FIB (focused ion beam) image, while Fig. 6.34b shows the HRTEM (high-resolution transmission electron microscopy) image. Although there are a few tiny voids along the interface, however the electrical connectivity has been confirmed that there is not circuit open or leakage failure occurred in the 12 stacked chip packages. Figure 6.35 shows the thermal performance of the 12 stacked chip package by the conventional flip chip micobump plus underfill connection and the Cu-Cu hybrid bonding connection. It can be seen that the thermal resistance of the Cu-Cu hybrid bonding package is 16.3% lower than that of the flip chip microbump with underfill package. This is due to the presence of the underfill and microbumps of the conventional flip chip technology. Cu-Cu hybrid bonding is bumpless and there is no gap for the underfill.

6.9 TEL’s Cu-Cu Hybrid Bonding 6.9.1 Simulation of Hybrid Bonding During IEEE/ECTC 2022, TEL presented a paper on the multi-physics simulation of wafer-to-wafer bonding dynamics [29]. Figure 6.36 shows the schematic of the bonding process steps for them to establish their mathematic equations. It can be seen there are four steps. Initially, the upper wafer is horizontally flat and held by the upper vacuum chuck. In the first step (before initiation) the upper wafer falls down

6.9 TEL’s Cu-Cu Hybrid Bonding

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Fig. 6.33 Successful demonstration of a 12 stacked package structure by applying all the optimized process steps. a Low magnification image. b A tilted SEM image. c A cross section SEM image of the 12 stacked package

due to the effect of gravity while fixed at the edge by the vacuum chuck. Shortly after (about 0.01 s), a striker pushes the wafer down. In this step (initiation) the wafer displacement caused by the application of the striker is resisted by the thin layer of air that is trapped between the two wafers. The upper wafer center is displaced until contact between the two wafers initiates, leading to the third step (contact) in the process. In the fourth step (bonding propagation) the adhesion force between the two wafers causes the contacted area to expand by expelling the air between the two wafers, resulting in the propagation of bonding front through the wafer domain. During the process, the upper wafer edge is released from the edge vacuum chuck. The lower wafer is considered flat and clamped to the lower vacuum chuck. Figure 6.37a shows the problem definition with two important parameters in their equations, namely, the gap (h) between the wafers and the distance from the center (r) of wafers. Figure 6.37b shows the simulation results at different steps during hybrid bonding. In their equations, some other important parameters such as the bonding (adhesion) strength, bond gap, vacuum chuck pressure, displacement,

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Fig. 6.34 Images of the cross section by C2W Cu-Cu hybrid bonding. a The FIB (focused ion beam) image. b The HRTEM (high-resolution transmission electron microscopy) image

(a) Void

TSV

Fig. 6.35 The thermal performance of the 12 stacked chip package: conventional flip chip micobump plus underfill connection versus the Cu-Cu hybrid bonding connection

Thermal Resistance (oC/W)

(b)

Micro Solder Bump

Cu-Cu Hybrid Bonding

wafer thickness, material properties, etc. are also included. Thus, their equations are useful in optimizing the bonding process to key performance metrics, e.g., distortion uniformity and misalignment [29].

6.9.2 Wet Atomic Layer Etch of Cu It is well-known that nanometer-level control of copper pad recess to create electrical contacts by CMP is one of the most critical tasks in Cu-Cu hybrid bonding. During IEEE/ECTC 2022, TEL presented another paper on wet atomic layer etching of copper structures for highly scaled copper hybrid bonding and fully aligned vias.

6.9 TEL’s Cu-Cu Hybrid Bonding

459

Striker

Bond gap

Center of Wafers

Vacuum Chuck

Step 2: Initiation step

Step 1: Before initiation step

Step 4: Propagation step

Step 3: Contact step

Fig. 6.36 Schematic of the bonding process steps for TEL to establish their mathematic equations

Wafer height (μm)

Before initiation step

Radius

(a)

Radius (mm)

(b)

Fig. 6.37 a Problem definition with the gap (h) and the distance from the center (r) of wafers. b Simulation results at different steps during hybrid bonding

In order to compensate for the loss of recess control during CMP due to feature scaling, a wet atomic layer etch (W-ALE) was proposed as a supplement [30]. It is a two-step cyclical wet etch to create recesses in copper patterns with sub-nanometer level control. Figure 6.38 shows the Cu etch amount versus etch-cycle number of the cyclical W-ALE process. It can be seen that the W-ALE chemistry achieved an etch rate of 0.28 nm/cycle for both sizes (2 μm-pad/3 μm-pitch and 0.5 μm-pad/1 μm-pitch) of bond pads. The number is roughly the atomic diameter of copper and indicates

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6 Cu-Cu Hybrid Bonding

Cu Etch Amount (nm)

Fig. 6.38 Cu etch amount versus etch-cycle number of the cyclical W-ALE process

Blanket Coupon Patterned Coupon (2μm pad / 3μm pitch) Patterned Coupon (0.5μm pad / 1.0μm pitch) Full Patterned Wafer (0.5μm pad / 1.0μm pitch)

Etch Cycles (#)

that one monolayer of copper is removed per etch cycle. The purge time plays a significant role in etches behavior. When the purge time reduces from 3 to 1 s, the etch rate increases from 0.28 to 0.45 nm/cycle, which indicates the loss of ALE character. Figure 6.39 shows the effects of etch concentration on copper roughness. Figure 6.39a shows the initial Cu surface. Figure 6.39b shows the Cu surface with a 50 mM (millimole) etch chemical concentration, while Fig. 6.39c shows the Cu surface with a 5 mM etch chemical concentration. It is pointed out in [30] that the concentration must be lower than 10 mM. If the concentration is increased, such as Fig. 6.39b, the etch solution will begin to etch oxidized copper and the removal becomes uncontrollable.

6.10 Tohoku’s Cu-Cu Bonding 6.10.1 Cu Grain Enlargement During IEEE/ECTC 2022, Tohoku/T-Micro/JCU presented a paper on Cu-SiO2 hybrid bonding yield enhancement through Cu grain enlargement [31]. They create the (100) oriented along with an enlarged (10−15 μm) Cu grains by the modification of an electroplating method and the post processing. Figure 6.40a shows the fabrication process flow of the test vehicle. By using a Cu-electrolytic bath containing modified additives to fabricate the 5 μm-thick Cu film with pre-sputtered Cu seed layer on the wafers. The electroplated wafers are subjected to post heat treatment at two different temperatures under N2 ambient to obtain the oriented as well as enlarged Cu grains.

6.10 Tohoku’s Cu-Cu Bonding

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Fig. 6.39 a Initial Cu surface. b Cu surface with a 50 mM etch chemical concentration. c Cu surface with a 5 mM etch chemical concentration

Figure 6.40b shows the relative XRD (x-ray diffraction) peak intensity fraction for (200) and (220) peaks with respect to (111) peak at two different plating chemistries (A and B). It can be seen that the intensity fractions for the film electroplated using modified chemistry B are 13% and 2%, i.e., a six-fold increase of (200) oriented grains with respect to grains with (220) orientation. This improved grain orientation might also facilitate the Cu diffusion between the similarly oriented Cu grains of the top and bottom electrode during direct Cu-Cu hybrid bonding [31]. Figure 6.41 shows the SEM images prior to EBSD (electron back-scattered diffraction) analysis of the Cu films deposited using the conventional electrochemistry A, Fig. 6.41a, and the modified chemistry B, Fig. 6.41b. It can be seen that the Cu-grains fabricated by the conventional chemistry A is very short (1-2 μm) while by the modified plating chemistry B leads to larger Cu crystallites (20 μm). This improved grain sizes might also be helpful in the μjoint quality after bonding. Figure 6.42 shows the cross-section SEM images of the direct Cu-Cu hybrid bonding using the Cu-film with the conventional chemistry A, Fig. 6.42a, and with the modified chemistry B, Fig. 6.42b. The bonding interface looks good for both cases. However, a closer look at Fig. 6.41b, a nearly single Cu-grain between the top

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6 Cu-Cu Hybrid Bonding

Fig. 6.40 a Fabrication process flow of the test vehicle, b Relative XRD peak intensity fraction for (200) and (220) peaks with respect to (111) peak at two different plating chemistries (A and B)

and bottom chips has been observed [31]. Figure 6.43 shows the cross-section SEM image of the direct Cu-Cu hybrid bonding with a pair of whole Cu pads.

6.10.2 Hybrid Bonding with Cu/PI Systems During IEEE/ECTC 2022, Showa Denko/Hitachi/Tohoku presented a paper on the comprehensive study on advanced chip on wafer hybrid bonding with copper/polyimide systems [32, 33]. Instead of the SiO2 dielectric material for the passivation on the silicon substrate for most of the Cu-Cu hybrid bonding, they use a special polyimide (PI) with CTE (coefficient of thermal expansion) equals to 75 × 10–6 /°C. Since the CTE of PI is a few times larger than that of Cu (16.8 × 10–6 /°C), designing of Cu protrusion height is a key task. Figure 6.44a shows the fabrication process flow of PI/Cu preliminary test wafers. It can be seen that after the standard processes in making the seed layer, Cu pads, and the PI coating, then CMP to expose the Cu surface. Figure 6.44b shows the fabrication process flow of PI/Cu daisy-chain wafers. First, the Cu pillars are fabricated on a

6.10 Tohoku’s Cu-Cu Bonding

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Fig. 6.41 a SEM images prior to EBSD analysis of the Cu films deposited using the conventional electrochemistry A. b Using the modified chemistry B

Fig. 6.42 Cross-section SEM images of the direct Cu-Cu hybrid bonding using the Cu-film with the conventional chemistry A (a), and with the modified chemistry B (b)

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6 Cu-Cu Hybrid Bonding

Fig. 6.43 Cross-section SEM image of the direct Cu-Cu hybrid bonding with a pair of whole Cu pads

SiO2 dielectric layer, and then the PI layer is overcoated by the same process as the preliminary test wafers. For both cases, the Ra (Roughness Average) is less than 1 nm for both Cu and PI.

(a)

(b)

Fig. 6.44 a Fabrication process flow of PI/Cu preliminary test wafers. b Fabrication process flow of PI/Cu daisy-chain wafers

6.10 Tohoku’s Cu-Cu Bonding

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Figure 6.45a schematically shows the thermal expansion of Cu and PI and the equation for calculate the Cu protrusion (H), while Fig. 6.45b shows the relationship between Cu protrusion height and bonding temperature for different PI thickness. Figure 6.46 shows the cross-section SEM image of a Cu/PI daisy-chained test coupon. It has been pointed out that the Cu protrusion height design, CMP to make the Cu electrode protrusion slightly more than the surrounding PI area, aqueous citric or ascorbic aqueous acid treatment, etc. are all critical to make Cu-Cu with Cu/PI hybrid bonding successful [33]. The practical Cu-Cu and PI-PI junctions are achieved with permanent bonding at 250 °C and 5 MPa for 20 min.

PI CTE = 75x10-6/oC

PI Thickness

H: Cu protrusion height D: PI thickness ΔT: Temperature difference during bonding αPI : CTE of PI (75x10-6/oC) αCu : CTE of Cu (16.8x10-6/oC) (a)

(b)

Fig. 6.45 a Thermal expansion of Cu and PI and the equation for calculating the Cu protrusion (H). b Relationship between Cu protrusion height and bonding temperature for different PI thickness

Cu Cu

Fig. 6.46 Cross-section SEM image of a Cu/PI daisy-chained test coupon

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6 Cu-Cu Hybrid Bonding

6.11 Imec’s Cu-Cu Hybrid Bonding Imec have been doing some research works on Cu-Cu hybrid bonding [34–40]. In this section, some of their works will be briefly mentioned.

6.11.1 Hybrid Bonding with Cu/SiCN Surface Topography During IEEE/ECTC 2020, imec published a paper on novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding [34]. Figure 6.47 shows the schematic of Cu-Cu hybrid bonding with the SiCN dielectric material. It can be seen that slightly protruding Cu nano-pad on the top wafer and slightly recessing (but larger) Cu nano-pad on the bottom wafer. A SiCN dielectric surface roughness of 0.15 nm rms (root mean square) is required. The step height and space are very important in the Cu protrusion topography to control the bonding voids as shown in Fig. 6.48. It can be seen that the out-of-plane Cu would create voids between the Cu protrusion and the SiCN dielectric surface. The size of the voids depends on the step height and the spacing of the Cu protrusion. If the spacing is very small (extremely high-density like case 2), then the void is larger as shown in Fig. 6.48. Figure 6.49 shows an optimized TEM image of the Cu/SiCN to Cu/SiCN hybrid bonding.

Top Wafer Small protruding Cu pad array

SiCN

Bottom Wafer Larger recessed Cu pad array

Fig. 6.47 Schematic of Cu-Cu hybrid bonding with the SiCN dielectric material

6.11 Imec’s Cu-Cu Hybrid Bonding Fig. 6.48 Relation between Cu protrusion topography (step height and space) and bonding voids

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Space Step height

SiCN surface

Void

Case 1: Case 2: Iso space dense space

Fig. 6.49 An optimized TEM image of the Cu/SiCN to Cu/SiCN hybrid bonding

6.11.2 Die-To-Wafer Hybrid Bonding During IEEE/ECTC 2022, imec/Brewer Science/SUSS published a paper on carrier systems for collective die-to-wafer bonding [39]. Figure 6.50 shows the collectivehybrid die-to-wafer bonding flow. There are 4 key tasks, namely (I) die preparation, (II) die pick and place, (III) bonding, and (IV) debonding. For die preparation, first mount the top die wafer on a carrier substrate with an adhesive and then thin-down the backside of the wafer to 50 μm. It is followed by attaching the backside of the wafer to glass carrier substrate 2 with a TBM (temporary bond material) called acoustic layer (AL) and a laser release layer (LRL). The acoustic

468

6 Cu-Cu Hybrid Bonding (I) Die Preparation

Cu Pads

Mounting

Top die wafer

LRL/AL on die

Top die wafer

Protection layer Wafer flip TBM/acoustic layer coating TBM/acoustic layer

Thinning

Carrier substrate

Carrier substrate Target wafer

Debonding & cleaning

Target wafer

Organic layer removal

Bonding

Glass carrier

Glass carrier

LRL/AL on carrier Debonding & cleaning

Target wafer

(IV) Debonding

Bonding

Glass carrier

(III) Bonding

Carrier substrate 2

Die placement

Dicing

Die placement

Dicing cleaning

Glass carrier Organic layer removal

Target wafer

Glass carrier

Carrier substrate 2

Glass carrier

(II) Die Pick & Place

Fig. 6.50 Collective-hybrid die-to-wafer bonding flow: (I) die preparation, (II) die pick and place, (III) bonding, and (IV) debonding

layer is used to avoid damage to the corners of the dies during the laser ablation process. Then, coat a protection layer on the front side of the top die wafer. This protection coating is used to protect the bonding surface of the dies from particles and protect die chipping during blade dicing. For die pick and place (P&P), there are two parts, namely LRL/AL on die and LRL/AL on carrier. For P&P LRL/AL on die, first place the top wafer with the AL and LRL on a dicing tape and, after laser debonding of the carrier substrate 2, diced. Then, attach the wafer with the AL and LRL on another glass carrier with adhesive. For P&P LRL/AL on carrier, first clean up the AL and LRL from the top wafer and then attach the top wafer on another glass carrier with adhesive. For bonding, again there are two parts, namely LRL/AL on die and LRL/AL on carrier. For bonding LRL/AL on die, first remove the protection coating layer of the top wafer and then attach the top wafer to a target wafer. For bonding LRL/AL on carrier, first remove the protection coating of the top wafer and then attach the top wafer to a target wafer. For debonding, there are also two parts. For LRL/AL on die, debond the glass carrier and remove the LRL and AL and clean the chips. For LRL/AL on carrier, debond the glass carrier and clean the chips. Finally, annealing at high temperature is performed for increasing the dielectric bond strength and enabling the Cu connections to be formed via the Cu bulge out mechanism [39]. In [39], three different systems with the AL (TBM) and LRL on the carrier are studied, Fig. 6.51. The reference system consists of the glass carrier, a very thick TBM, a very thin LRL, a very thin AL, and the die. System A consists of the glass carrier, a thin layer of LRL, a thick layer of TBM, and the die. System B consists of the glass carrier, a thick TBM, a thick LRL, and the die. System C consists of the glass

6.11 Imec’s Cu-Cu Hybrid Bonding

469

Fig. 6.51 Three different systems (A, B, C) with the AL (TBM) and LRL on the carrier are studied

carrier, a thick LRL, and the die. The material for the LRL is BrewerBOND T1107 or BrewerBOND701 and the material for AL (TBM) is BrewerBOND C1301-50. Figure 6.52 shows the actual target wafer after hybrid bonding along with the SAM images after bond and after carrier laser debond. The DoW hybrid bonding results are shown in Table 6.1. It can be seen that the systems with a thin LRL underneath the TBM (System A) or a thick LRL on top of the TBM (System B) are both successful in allowing a 100% die transfer rate with very high bond yields [39].

6.11.3 Thermal and Mechanical Reliability of Hybrid Bonding Figure 6.53 shows imec’s test vehicle with TSV which is integrated in a unit cell of 240 × 240μm2 for hybrid bonding [40]. The unit cells are arranged in an array of 16 × 16 within the square die of 4.32 × 4.32 mm. The variable size test chips can finally be diced from a wafer with the step of 4.32 mm. To enable face-to-face hybrid bonding, the wafer pairs received an additional surface finish, i.e., 500 nm SiO2 and 120 nm SiCN. The hybrid interface consists of 0.54 μm square pads embedded into the dielectric of the top wafer and 1.17 μm square pads plated on the bottom wafer

470

6 Cu-Cu Hybrid Bonding

Fig. 6.52 Pictures of transfer results (left) of System A, B and C with the corresponding SAM before (middle) and after (right) laser debonding

Table 6.1 DoW hybrid bonding results Carrier system

Die placement (% die lost with N2 test)

Resist strip (% die lost after strip)

Post-bond bond yield (% bonded area)

Transfer yield (% die transferred from carrier to target)

Process yield (% dies placed and transferred to target)

Post-Debond Bond Yield (% bonded area)

REF

OK

OK

99

100

100

98

A

OK

OK

82

100

100

99

B

OK

OK

86

100

100

98

C

−14%

−17%

78

82

64

94

as shown in the TEM (transmission electron microscopy) image in Fig. 6.54. The alignment and bonding are done at room temperature and with the following postbond anneal at 250 °C for 2 h [40]. The cross section of the hybrid stack is shown in Fig. 6.55. The top wafer is thinned down to 50 μm to reveal the integrated (via-middle) through TSVs from the backside. The redistribution layer and the flip-chip pillars are processed on the back side of the top wafer to allow electrical measurements and to enable flip-chip assembly.

6.11 Imec’s Cu-Cu Hybrid Bonding

471

Fig. 6.53 Test vehicle with TSV which is integrated in a unit cell of 240 × 240 μm2 for hybrid bonding

Fig. 6.54 Cross section TEM image of Cu-Cu hybrid bonding

The mechanical response of the hybrid bonded structure is performed by a fourpoint bending test as shown in Fig. 6.56 [40]. The applied force is shown in Fig. 6.57a. A total of 1000 cycles have been applied. The percent failures are shown in Fig. 6.57b. It can be seen that there is no significant change in hybrid bonding pad resistance. The thermal response of the hybrid bonded structure is performed by a finite element method as shown in Fig. 6.58 [40]. The fine mesh of the finite element model and its schematic cross section are shown in Fig. 6.58b and c. After stabilizing the temperature, sensors located in surrounding 25 cells (within the limits indicated by the red rectangle in Fig. 6.58a) on the top and bottom wafers are measured. In the second phase of the experiment power is removed from the heater and the sensors are measured again. The response of the temperature sensors measured in two phases is converted into the relative temperature increase as reported in Fig. 6.59a for the sensors located in five cells along the yellow axis “x” (indicated in Fig. 6.58a). It can be seen that the measurement results correlated very well with the finite element simulation results. Figure 6.59b shows the temperature increase when the power is applied to the bottom tiers of the hybrid bonding structure. It can be seen that for the hot spot

472

6 Cu-Cu Hybrid Bonding

Fig. 6.55 Cross section and SEM image of the hybrid stack

Fig. 6.56 Four-point bending test

temperature T 4 captured by the top wafer sensor correlated very well with the finite element simulation results. On the other hand, the hot spot temperature T 6 captured by the bottom wafer sensor is off by as much as 25% from the finite element simulation results.

6.12 CEA-LETI’s Cu-Cu Hybrid Bonding In the past few years, CEA-LETI have been working on Cu-Cu hybrid bonding [41–44]. Some of their works are briefly reported in this section.

6.12 CEA-LETI’s Cu-Cu Hybrid Bonding

473

Fig. 6.57 a force–time history. b Percent failures

Fig. 6.58 Finite element method and sensor measurement. a Sensor location. b Finite mesh. c Close-up of the finite element mesh

(a)

Temperature Increase (oC)

6 Cu-Cu Hybrid Bonding

(b)

Temperature Increase (oC)

474

Heater Top / Sensor Top Heater Top / Sensor Bottom FEM

Heater Bottom / Sensor Top Heater Bottom / Sensor Bottom FEM

Fig. 6.59 Relative temperature change measured by the sensors located on top and bottom wafers and simulated by the finite element analysis when the power is applied to the top a and bottom b tiers of the hybrid stack

6.12.1 CEA-LETI/ams Cu-Free Hybrid Bonding During IEEE/ECTC 2020, CET-LETI/ams published a paper on a reliable copperfree level hybrid bonding technology for high-performance medical imaging sensors [41]. Figure 6.60 shows the key process steps of their hybrid bonding. Their Ti/SiO2 hybrid bonding is developed on a 200 mm non-functional short loop wafers. Figure 6.60 (1) shows the metal pattern preparation. First a TiN is deposited as a barrier layer. Then, a Ti layer (500 nm) is deposited by sputtering. Finally, the Ti is capped by a thin TiN layer. Figure 6.60 (2) shows the metal stack patterning. Figure 6.60 (3) shows the dielectric deposition. After patterning, the pads are encapsulated by a tetraethylorthosilicate (TEOS) oxide. After the TEOS oxide deposition, an annealing step is applied for two reasons: (i) for densification of the dielectric and (ii) to eliminate the water molecules absorbed in the dielectric layer in order to prevent future bonding void formation by outgassing. Figure 6.60 (4) shows the CMP for the planarization and surface preparation of the wafers. For Ti/SiO2 planarization the CMP process starts with the SiO2 removal and stops in the final Ti/SiO2 hybrid surface. The topography measurement are carried out by white-light interferometry (WLI) and oxide surface roughness by atomic force microscopy (AFM) indicating excellent surface planarity and roughness [29]. Figure 6.60 (5) shows the top and bottom wafers bonding. Figure 6.60 (6) shows the annealing for metal connection. Finally, the bonded wafers were annealed at 400 °C for two hours in order to ensure

6.12 CEA-LETI’s Cu-Cu Hybrid Bonding

475

Fig. 6.60 Key process steps of Cu-free hybrid bonding

Fig. 6.61 TEM image which demonstrates an excellent Ti/Ti connection

a proper metal/metal connection. The bonding interface quality is locally assessed with focused ion beam scanning electron microscopy (FIB-SEM) and transmission electron microscopy (TEM). Figure 6.61 shows the TEM image which demonstrates an excellent Ti/Ti connection and there is not seams in the metal and dielectric interfaces [41].

6.12.2 CEA-LETI/SET D2W Hybrid Bonding During IEEE/ECTC 2021, CEA-LETI/SET published a paper on towards 5 μm interconnection pitch with die-to-wafer (DTW) direct hybrid bonding [42]. Their direct wafer-to-wafer (WTW) and DTW Cu-Cu hybrid bonding process flows are

476

6 Cu-Cu Hybrid Bonding

shown in Fig. 6.62. It can be seen that there are two Cu damascene levels on the last BEOL (back-end-of-line) level on both top and bottom wafers. The first level is composed of conductive Cu vias. The second level is composed of Cu pads into the oxide matrix specifically designed to ensure a high-quality bonding. A CMP step is specially developed to reach surface topography requirements. Figure 6.63 shows an optimized SEM cross-sectional image of Cu-Cu hybrid bonding.

Fig. 6.62 WTW and DTW Cu-Cu hybrid bonding process flows

Fig. 6.63 An optimized SEM cross-sectional image of Cu-Cu hybrid bonding

6.12 CEA-LETI’s Cu-Cu Hybrid Bonding

477

6.12.3 CEA-LETI/Intel D2W Self-assembly for Hybrid Bonding During IEEE/ECTC 2022, CEA-LETI/Intel published a paper on collective die-towafer self-assembly for high alignment accuracy and high throughput 3D integration [43]. Self-assembly process is based on the use of small water (surface tension = 72.1 mN/m) drops to align through capillary forces a chip on a target site. After the water drop evaporation, direct bonding occurs as shown in Fig. 6.64a. The very low surface roughness of the chip and the target is the prerequisite for a good bonding quality. Another critical task to ensure self-alignment is to have a good containment (to avoid water overflow) on the bonding site as shown in Fig. 6.64b. It is controlled by topographical and/or chemical contrast. Topographical contrast is achieved by realizing a step surrounding the bonding site, while the chemical contrast is obtained by spreading a hydrophobic material all around the hydrophilic bonding site [43]. Their self-assembly process flow is shown in Fig. 6.65a. It can be seen that there are two key tasks, one is for the dies and the other is for the target (wafer). For the target wafer, a first photolithography step defines two verniers used for alignment purpose and a second photolithography step and consecutive etching process define a 14 μm height step (the physical contrast). The chemical contrast is generated by depositing a hydrophobic material, containing fluorine, all over the wafer by spin coating. Then, remove the hydrophobic material from the bonding site [43].

Fig. 6.64 a Different steps of the self-assembly. b Water containment on bonding site is controlled by topography (physical) and hydrophobic (chemical) contrast

478

6 Cu-Cu Hybrid Bonding

Fig. 6.65 a Self-assembly process flow. b Wafer droplets are deposited on the target wafer. c Droplets on target wafers after dip coating

For the die wafer, the process is almost the same, except the dies are singulated right after the etching step. Then deposit the hydrophobic material to prevent particular contamination due to blade dicing. Finally, place the dies in silicon holders to be collectively cleaned. Holder cavities have a die site mapping matching the bonding site mapping of target wafers. The self-assembly is carried out with five steps: (a) surface preparation, (b) wafer droplet deposition, (c) collective self-assembly process, (d) drying, and (e) annealing. Wafer droplets are deposited on the target wafer, Fig. 6.65b and c. For more information on self-assembly, please read [43].

6.13 IME’s Cu-Cu Hybrid Bonding In the past few years, IME have done some works on Cu-Cu hybrid bonding [45–49]. Some of their results are briefly mentioned in this section.

6.13 IME’s Cu-Cu Hybrid Bonding

479

6.13.1 Simulation of SiO2 W2W Hybrid Bonding The common design and process parameters such as dishing value, annealing temperature and dwell duration, TSV pitch, and depth with regard to thermo-mechanical bonding performance have been studied in [45, 46]. The structure under thermomechanical simulation is shown in Fig. 6.66 and the important dimensions are shown in Table 6.2. The finite element model is shown in Fig. 6.67. It can be seen that a localized quarterly-symmetric finite element model including only 2 × 2 sets of Cu pads is proposed as shown in Fig. 6.67a. The mesh details are shown in Fig. 6.67b and c. The annealing temperature profile is shown in Fig. 6.68. All the parameters used in defining annealing temperature profile and dishing values used in surface treatment before annealing process are listed in the table of Fig. 6.68. The material properties used in the simulations are presented in Table 6.3. Elastic–plastic-creep material properties for copper material are listed in Table 6.4 [46]. Figure 6.69 shows the effect of annealing temperature on Cu-to-Cu bonding area after annealing process with different dishing values. It can be seen that both

Fig. 6.66 Dishing geometry. a Before annealing. b After annealing. c Dimensions shown in Table 6.2

480 Table 6.2 Design parameters

6 Cu-Cu Hybrid Bonding Design parameters

Values (μm)

Cu pad/bonding pad/TSV pitch

6, 9, 12

Cu pad diameter ϕ1

3

Bonding pad diameter ϕ2

4

TSV diameter ϕ3

2

Cu pad thickness D1

0.6

Bonding pad thickness D2

0.6

SiO2 layer thickness D3

0.2

TSV depth D4

5, 10, 15

Si thickness D5

30

Fig. 6.67 Quarterly symmetric FEA model. a Finite element analysis model. b Mesh (bottom half model). c Mesh (front view cross-section)

6.13 IME’s Cu-Cu Hybrid Bonding

481

Fig. 6.68 Hybrid bonding annealing temperature profile

Table 6.3 Material properties used in the simulations Materials

Young’s modulus (GPa)

Poisson’s ratio

CTE (10-6 /°C)

Silicon

131

0.28

2.6

Copper

91.8

0.34

17.6

Dielectric (SiO2 )

73

0.17

0.5

Table 6.4 Elastic–plastic-creep material property for copper Material properties

Value

Yield strength (MPa)

321

Tangent Modulus (MPa)

2000

Creep constant C1

1.43 × 1010

Creep constant C2

2.5

Creep constant C3

−0.9

Creep constant C4

23,695

C1 , C2 , C3 , and C4 are the constants of the Carofalo hyperbolic equation

annealing temperature and dishing value play a very important role in forming Cuto-Cu bonding. The higher the annealing temperature (400 °C) and the smaller the dishing (5 nm) lead to a good Cu-Cu bonding (. 97% copper pad area). It also can be seen from Fig. 6.69 that at a low annealing temperature (300 °C) the dishing effect is more critical than that at high annealing temperature such as .350 °C [46]. Thus, Cu dishing is recommended to be as low as 5 nm.

482

6 Cu-Cu Hybrid Bonding

Fig. 6.69 Effects of annealing temperature and dishing value on Cu-to-Cu bonding area

Fig. 6.70 Effects of annealing temperature and dishing value on peak peeling stress on Cu interfaces

Similar findings are observed for peak peeling stresses on copper interfaces as shown in Fig. 6.70 [46]. The peak stress on Cu-Cu bonding interface decreases with higher annealing temperature and less dishing. This is in line with the trend for forming Cu-Cu bonding area. However, the trend is on the opposite side for the peeling stress on dielectric bonding interface as shown in Fig. 6.71. It can be seen that the higher annealing temperature and less dishing the higher the peak peeling stress on dielectric interface, which leads to higher chance of delamination or even crack in the dielectric layers.

6.13.2 Simulation of SiO2 C2W Hybrid Bonding During IEEE/ECTC 2022, IME presented a paper on numerical simulation on SiO2 based chip to wafer hybrid bonding performance by finite element analysis [47]. Figure 6.72a schematically shows the structure for analysis. It can be seen that there are four chips vertically stacked and the area for the finite element modelling is

6.13 IME’s Cu-Cu Hybrid Bonding

483

Fig. 6.71 Effects of annealing temperature and dishing value on peak peeling stress on dielectric material (SiO2 ) bonding interfaces

indicated. First, Cu recessing by CMP and then the SiO2 -to-SiO2 bonding takes place at room temperature as shown in Fig. 6.72b. During annealing, because the thermal expansion of the Cu is many times larger than that of the SiO2 , the Cu pads protrude towards each other (Cu-Cu bonding), Fig. 6.72c.

Fig. 6.72 a The structure for analysis. b SiO2 -to-SiO2 bonding takes place at room temperature, c After annealing

484

6 Cu-Cu Hybrid Bonding

Fig. 6.73 a Design parameters shown in Table 6.5. b A close-up look of the initial dishing cap

The design parameters are shown in Fig. 6.73a and Table 6.5. A close-up look of the initial dishing cap is shown in Fig. 6.73b. Figure 6.74 shows the finite element model for the analysis of SiO2 -to-SiO2 and Cu-to-Cu hybrid bonding. The annealing temperature profile is shown in Fig. 6.75. The dishing gap closure at various time instant for the case (1 μm thick and 5 μm Ø Cu pad, 5 nm dishing and 250 °C annealing temperature for 1 h dwell) is shown in Fig. 6.76. Figure 6.76a is at the end of ramp-up. Figure 6.76b is at the end of dwell, and Fig. 6.76c is for the end of cool-down, Table 6.6. It can be seen that the final Cu bonding area ratio achieved for 1 μm thick, 5 μm Ø Cu pad, and 5 nm dishing is 70%, i.e., the bonded area covers 84% of Cu diameter, left with a unbonded thin edge of 8% of Cu diameter [47].

6.13.3 Simulation of Cu/Polymer C2W Hybrid Bonding During IEEE/ECTC 2022, IME presented another paper on numerical simulation of Cu/polymer-dielectric hybrid bonding using finite element analysis [48]. One of the reasons to use polymer instead of SiO2 for C2W hybrid bonding is to avoid the

6.13 IME’s Cu-Cu Hybrid Bonding Table 6.5 Design parameters

485

Design parameters

Values

Dishing

3 nm, 5 nm

SiO2 layer/Cu pad thickness D1

1 μm, 3 μm

Cu pad/bonding pad/TSV pitch

10 μm

Cu pad diameter Ø1

5 μm

Bonding pad diameter Ø2

6 μm

TSV diameter Ø3

6 μm

Bonding pad thickness D2

1 μm

Fig. 6.74 Finite element model for the analysis of SiO2 -to-SiO2 and Cu-to-Cu hybrid bonding Fig. 6.75 Annealing temperature profile

486

6 Cu-Cu Hybrid Bonding

Fig. 6.76 Dishing gap closure at various time instant. a At the end of ramp-up. b At the end of dwell. c At the end of cool-down

Table 6.6 Annealing temperature profile

Process parameters

Values

Dishing

5, 10, 15 nm

Initial/end temperature T1

25 °C

Annealing temperature T2

300, 350, 400 °C

Ramp-up/cool-down duration Δt

0.5 h

Annealing dwell duration Δtd

1, 2, 3 h

particle sensitivity and brittle fracture issues observed with SiO2 . Since the CTE of most polymers is larger than that of the electroplated Cu, thus instead of doing Cu recess, Cu protrusion should be performed. Figure 6.77 shows the schematics of Cu/polymer bonding before and after TCB for Cu protrusion (Fig. 6.77a), and Cu dishing (Fig. 6.77b), and final bonding during annealing (Fig. 6.77c). Figure 6.78a is for Cu pad protrusion, while Fig. 6.78b is for the Cu pad dishing. The design parameters are shown in Table 6.7. The nominal Cu pad protrusion is 5 nm and the nominal Cu pad dishing is also 5 nm. Figure 6.79 shows the finite element modeling and the mash distribution. Figure 6.79 schematically shows the finite element analysis model cross sections, showing the bonding interface details. The thermal compression bonding (TCB) profile is shown in Fig. 6.80. It can be seen that the nominal bonding load on the 6 × 6 mm die is 100 N, the nominal

6.13 IME’s Cu-Cu Hybrid Bonding

487

Fig. 6.77 Cu/polymer bonding before and after TCB for Cu protrusion and Cu dishing, and final bonding during annealing

Fig. 6.78 a Cu pad protrusion. b Cu pad dishing

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6 Cu-Cu Hybrid Bonding

Table 6.7 Design parameters Design parameter [units]

Min

Max

Polymer layer/Cu pad thickness, t1 [μm]

2

3

2

Cu pad/TSV diameter, Ø1 [μm]

…

…

5

Bonding pad thickness, t2

…

…

1

Bonding pad diameter, Ø2 [μm]

…

…

6

Cu pad/bonding pad/TSV pitch, P [μm]

…

…

10

Cu pad protrusion, Fig. 6.79a [nm]

5

15

5

Cu pad dishing, Fig. 6.79b [nm]

3

5

5

(a) Schematic showing FEA model cross-section and its position in the C2W HB layout

(c) Bottom portion showing the bonding interface with 2x2 Cu pads

Nominal

(b) FEA model with boundary conditions and bonding loads

(d) Mash details at the bonding interface

Fig. 6.79 Finite element modeling and the mash distribution

6.13 IME’s Cu-Cu Hybrid Bonding

489

bo×nding interface temperature is 215 °C, the nominal bond head temperature is 250 °C, the nominal bottom chuck temperature is 100 °C, the nominal ramp-up duration is 4 s, the nominal dwell time is 3 s, and the cooldown duration is 8 s. The annealing temperature profile is shown in Fig. 6.81. It can be seen that the nominal annealing temperature is 250 °C, the nominal ramp-up/cooldown duration is 1 h, and the nominal dwell duration is 2 h. The material properties for modeling are shown in Table 6.8 and the elastic–plastic-creep material properties for copper material are listed in Table 6.4. The simulation results show that the effects of TCB bond head temperature, TCB bonding load, and TCB bottom chuck temperature on the polymer bonding area are minimum [48]. However, the effect of Cu pad protrusion and the thickness of polymer layer on the polymer bonding area is significant, Fig. 6.82. It can be seen that: (a) for the 15 nm protrusion case. the reduction of polymer B thickness from 3 μm to 2 μm resulted in reduction of bonding area from 84% to zero, and (b) for the 5 nm protrusion case, the effect of polymer thickness reduction is negligible. The maximum Cu pad interface peel stress due to TCB for polymer A and B is shown in Fig. 6.83a, while the maximum polymer interface peel stress due to TCB for polymer A and B is shown in Fig. 6.83b. It can be seen that for both maximum Cu pad interface peel stress and maximum polymer interface peel stress at various bond head temperatures, the values of the polymer A are larger than those of the polymer B. This is due to the very large CTE of polymer A (Table 6.8). Figure 6.84 Fig. 6.80 Thermal compression bonding (TCB) profile

490

6 Cu-Cu Hybrid Bonding

Fig. 6.81 Annealing temperature profile

Table 6.8 Material properties for modeling

Material

E (GPa)

Poisson’s ratio

CTE (×10-6 /°C)

Cu

91.77

0.34

17.6

Si

131

0.28

2.6

SiO2

73

0.17

0.5

Polymer-A

2.47

0.3

110.4

Polymer-B

1.8

0.3

11.5 (25 °C) 46.0 (400 °C)

Fig. 6.82 Effect of Cu pad protrusion and the thickness of polymer layer on the polymer bonding area

shows basically the same results due to annealing [68]. Thus, a lower CTE polymer should be used.

6.13 IME’s Cu-Cu Hybrid Bonding

491

Fig. 6.83 a Maximum Cu pad interface peel stress due to TCB for polymer A and B. b Maximum polymer interface peel stress due to TCB for polymer A and B

6.13.4 Yield Improvement on C2W Hybrid Bonding During IEEE/ECTC 2022, IME presented another paper on yield improvement in chip to wafer hybrid bonding [49]. Their process is shown in Fig. 6.85. First, apply a protective layer on a bare silicon wafer and then mount the wafer on a dicing tape. It is followed by pre-cut a 50 μm silicon trench on a 6 × 6 mm die size and then the removal of the protective layer. Finally, clean and inspection. IME tried both dry film and liquid film protective layers and found the liquid film leads to the better results as shown in Fig. 6.86. Figure 6.86a shows the residues of a 5 μm-thick dry film. For a thicker dry film protective, e.g., 10 and 30 μm, it is unable to peel off from the singulated die. Figure 6.86b shows the wafer yield (> 90%) for the photo-definable liquid film and non-photo definable liquid film. Voids usually are detected by CSAM (C-mode scanning acoustic microscopy). Figure 6.87a shows the CSAM images of the C2W hybrid bonding without protective layer during dicing process. Five out of 30 dies dropped off. The void precent is from 0.2 to 91%. Figure 6.87b shows the one with protective layer. It can be seen that not only there is not any die dropped off, the void precent is from 0.144% to 3.238%. It is much improved from the initial 0.2−91%.

492 Fig. 6.84 a Maximum Cu pad interface peel stress due to annealing for polymer A and B. b Maximum polymer interface peel stress due to annealing for polymer A and B

Fig. 6.85 Yield improvement (with protective layer) in chip to wafer hybrid bonding process flow

6 Cu-Cu Hybrid Bonding

6.15 Xperi’s Cu-Cu Hybrid Bonding [51–57]

493

Fig. 6.86 a The residues of a 5 μm-thick dry film. b Wafer yield (> 90%) for the photo-definable liquid film and non-photo definable liquid film

6.14 Intel’s Cu-Cu Hybrid Bonding During IEEE/ECTC 2021, Intel presented a paper on hybrid bonding interconnect for advanced heterogeneously integrated processors [50]. Their test vehicle is shown in Fig. 6.88, which consists of 4 chips on an active TSV interposer (a base chip). Their die to wafer assembly flow for hybrid bonding is shown in Fig. 6.89. It can be seen that on the die wafer, first CMP to recess the Cu pad and polish the top wafer surface, then singulation individual die and clean. For the bottom wafer, first CMP to recess the Cu pad and polish the bottom wafer surface, then plasma activation the whole surface. It is followed by picking and placing the die to the bottom wafer. Finally, thermal annealing the assembly. One of the optimized SEM cross section images is shown in Fig. 6.89. It can be seen that the assembly is properly done.

6.15 Xperi’s Cu-Cu Hybrid Bonding [51–57] Xperi have been working on Cu-Cu hybrid bonding for a few years [51–57]. Some of their results are briefly mentioned in this section.

494

6 Cu-Cu Hybrid Bonding

Fig. 6.87 a CSAM images of the C2W hybrid bonding without protective layer during dicing process. b With protective layer

Fig. 6.88 a Test vehicle. b Top view of the hybrid bonding pad layer

6.15 Xperi’s Cu-Cu Hybrid Bonding [51–57]

495

Fig. 6.89 a Process flow. b One of the optimized SEM cross section images

6.15.1 D2W Hybrid Bonding—Die Size Effect During IEEE/ECTC 2022, Xperi published a paper on die to wafer hybrid bonding for chiplet and heterogeneous integration: die size effects evaluation-small die applications [51]. Figure 6.90 shows their thoughts on the D2W applications by hybrid bonding with various die sizes. It can be seen that, for very small die size (< 0.1mm2 ) or dies with similar footprint and high-test yield, W2W is a better choice. On the other hand, for die size of 0.1mm2 and larger or die footprints are not the same, D2W is better. They demonstrated that [51], Fig. 6.91, void free bonding yield of 94% and electrical continuity yield of 96% are achieved on the first assembly lot of the 3 × 3 mm die; 100% void free bonding yield and 100% electrical continuity yield on the first assembly lot of the 1 × 1 mm die; and 99.7% electrical continuity yield on the first assembly lot of the 0.4 × 0.4 mm die.

6.15.2 Multi-Die Stacks with Hybrid Bonding During IEEE/ECTC 2022, Xperi presented another paper on analysis of die edge bond pads in hybrid bonded multi-die stacked [52]. The top of Fig. 6.92a schematically shows the layer stack for the logic die and cap die, while the bottom of Fig. 6.92a shows the layer stack for the through (middle) dies with TSVs. Figure 6.92b shows schematically the full stack, which includes the cap die, the series of dies with TSVs,

496

6 Cu-Cu Hybrid Bonding

Fig. 6.90 D2W applications by hybrid bonding with various die sizes

Fig. 6.91 a Test vehicle and results. b SEM cross section image. c Close-up view

and the logic die. Figure 6.93 shows an example of 8-die stack after annealing. It can be seen from the bonding interface that the DBI pad is bonded directly to the backside surface of the TSV.

6.15 Xperi’s Cu-Cu Hybrid Bonding [51–57]

497

Fig. 6.92 a The layer stack for the through (middle) dies with TSVs. b Full stack, which includes the cap die, the series of dies with TSVs, and the logic die

Fig. 6.93 a 8-die stack. b SEM cross section image of the 8-die stack. c Close-up view. d Enlarge view

498

6 Cu-Cu Hybrid Bonding

6.16 Applied Material’s Cu-Cu Hybrid Bonding In the past couple of years, Applied Materials have published a couple papers on Cu-Cu hybrid bonding [58, 59]. Some of their results will be briefly mentioned.

6.16.1 Dielectric Materials for Hybrid Bonding During IEEE/ECTC 2021, Applied Materials published a paper on dielectric materials characterization for hybrid bonding [58]. Figure 6.94 shows their Cu-Cu hybrid bonding with non-polymer dielectric process flow, while Fig. 6.95 shows their CuCu hybrid bonding with polymer dielectric process flow. In Fig. 6.94, the dielectric material is either SiO2 or SiCN fabricated by PECVD. Then, lithography patterning, dry etch plus photoresist strip, and PVD the seed layer. It is followed by Cu dual damascening and CMP to recess the Cu pads and smooth the dielectric surface. The thickness of SiCN is recommended to be between 1−1.5 μm and of Cu dishing ≤ 10 nm but 5 nm is preferred. The dielectric Ra is preferred ≤ 0.5 nm and the Cu roughness ≤ 1 nm [58]. In Fig. 6.95, after the photoresist patterning, electroplating, the polymer is a polyimide spin coated on a wafer and then patterning. It is followed by photoresist striping and Cu/Ti etching. Then, polymer coat and cure. Finally, CMP to protrude the Cu pads and smooth the polymer surface. The thickness of the polymer is between 5−10 μm and of the Cu protrusion is 5 nm. The polymer Ra is 2 nm and the Cu roughness ≤ 1 nm [58]. Figure 6.96 shows the Cu-Cu hybrid bonding with SiO2 dielectric. Figure 6.96a shows the poor Cu-Cu bonding with insufficient post-bond annealing temperature, while 6.96b shows the good Cu-Cu bonding with excess post-bond annealing temperature. Figure 6.96c shows the very good Cu-Cu bonding with post-bond annealing Fig. 6.94 Cu-Cu hybrid bonding with non-polymer dielectric process flow

6.16 Applied Material’s Cu-Cu Hybrid Bonding

499

Fig. 6.95 Cu-Cu hybrid bonding with polymer dielectric process flow

Fig. 6.96 a Poor Cu-Cu bonding with insufficient post-bond annealing temperature. b Good Cu-Cu bonding with excess post-bond annealing temperature. c Very good Cu-Cu bonding with post-bond annealing temperature of 300 °C and the average Cu dishing value is 5 nm

temperature of 300 °C and the average Cu dishing value is 5 nm. Table 6.9 summaries the surface roughness (pre CMP and post CMP) and bond strength (bonding energy and shear strength) for various dielectric materials.

6.16.2 Development Platform for Hybrid Bonding During IEEE/ECTC 2022, Applied Materials presented a paper on a holistic development platform for hybrid bonding [59]. Their process step for Cu-Cu hybrid bonding with dielectric SiO2 is shown in Fig. 6.97. It can be seen that it starts off with EPCVD for the SiO2 on a device wafer and then etch the SiO2 . It is followed by PVD for

500

6 Cu-Cu Hybrid Bonding

Table 6.9 Surface roughness and bond strength for various dielectric materials Dielectric materials

Ave contact angle (°)

Surface roughness (nm)

Bond strength

Pre CMP

Post CMP

Bonding energy (J/m2 )

Shear strength (MPa)

Low T TEOS-SiO2

11

0.6−0.8

0.3–0.4

0.9–1.1

12–15

High T TEOS-SiO2

9

0.6−0.8

0.3–0.4

1.2–1.4

18–20

SiN

15

1.1−1.25

0.6–0.75

0.6–0.8

7–10

SiCN (High Carbon)

5

0.45−0.6

0.2–0.3

1.6–1.8

26–30

High T curable polymer

≥ 45

28−32

1.5–2

> 2.5

45–50

Low T curable polymer

23

1.9−2.2

1–1.2

> 2.5

35–40

the seed layer and ECD for the Cu pad. Then, CMP for the Cu dishing and SiO2 smoothing. Finally, SiO2 to SiO2 bonding at room temperature and annealing at high temperature. In [59], Applied Materials have done the simulations: (a) to study the interactions happening at the dielectric interface during the hybrid bonding formation, (b)

Fig. 6.97 Process step for Cu-Cu hybrid bonding with dielectric SiO2

6.17 Mitsubishi’s Cu-Cu Hybrid Bonding

501

Fig. 6.98 Model for electrical analysis

to control dishing and optimize the bump pattern with the modeling of the CMP process, and (c) to study electromigration reliability of hybrid bond interconnects with electrical analysis. In this section, only their electrical analysis results are briefly mentioned. Figure 6.98 shows the model for their electrical analysis. The thickness of all the metal and dielectric layers is assumed to be 1 μm. The Cu-Cu contact resistance is assumed to be 140 mΩ·μm2 (annealing temperature = 200 °C) and the contact resistance layer thickness is 50 nm. Figure 6.99 shows insertion loss versus various frequencies for different area reductions due to CMP. It can be seen that the larger the area reduction the large the insertion loss. Figure 6.100 shows the insertion loss versus various frequencies for different pad misalignment due to pick and place. It can be seen that the larger the pad misalignment the larger the insertion loss.

6.17 Mitsubishi’s Cu-Cu Hybrid Bonding The key process steps of Mitsubishi’s hybrid bonding are shown in Fig. 6.101 [60]. It can be seen that the Cu electrode, SiO2 , Ti, and Al-wire of the wafer before CMP is shown in Fig. 6.101a. Figure 6.101b shows the structure after CMP. The deference in level between Cu electrode and SiO2 is 10−20 nm. Figure 6.101c shows the bonded wafers using a Si thin film. The bonding is between a 6'' test-element-group (TEG) wafer and an 8'' TEG wafer. The surface of the wafers is activating through an Ar fast atom beam (FAB). A Si thin film is deposited on the lower 6'' TEG wafer surface at a rate of approximately 0.4 nm/min. The total thickness of the Si thin film is estimated to be approximately 4 nm after the bonding. The 8-in and 6-in TEG wafers are then brought into contact with a bonding compression force of 10,000kgf after alignment with very high accuracy.

502

6 Cu-Cu Hybrid Bonding

Fig. 6.99 Insertion loss versus various frequencies for different area reductions due to CMP

All of the Ar-FAB irradiation processes are performed at a background vacuum pressure smaller than approximately 5 × 10−6 Pa [60]. Figure 6.102 shows the hybrid bonding results. Figure 6.102a shows a SEM cross-sectional image of the bonded Cu/SiO2 hybrid interface. There are no seams or gaps can be observed in the cross-section, and the alignment error is estimated to be approximately 1 μm. Figure 6.102bshows a TEM cross-sectional image of the interface of the bonded Cu/Cu electrodes, and Fig. 6.102cshows a TEM cross-sectional image of the bonded SiO2 /SiO2 interface. At both bonding interfaces, there are no micro voids are observed. However, there is an intermediate layer with a thickness of approximately 5 nm. The layer is assumed to be amorphous Si layers.

6.18 Unimicron’s Hybrid Bonding Unimicron proposed the use of Cu-Cu hybrid bonding for the bridge between chiplets in chiplet design and heterogeneous integration packaging (Sect. 5.15). There are at least two options, one is with C4 bumps on the package substrate and the other is with C4 bumps on the chiplet wafer.

6.18 Unimicron’s Hybrid Bonding

503

Fig. 6.100 Insertion loss versus various frequencies for different pad misalignment due to pick and place

Al wire SiO2 film

Si thin film

Cu electrode Ti

Thermal oxide layer (a)

10~20nm

Si (b)

(c)

Fig. 6.101 Key process steps for hybrid bonding. a Before CMP b After CMP c Bonded wafers using a Si thin film

Figure 6.103 shows the process flow of hybrid bonding bridge with C4 bumps on the package substrate. For the bridge wafer, it starts off with CVD to make a dielectric material such as SiO2 and then it is planarized by an optimized CMP process to make the Cu dishing. Then, dice the bridge wafer into individual chips (still on the blue tape of the wafer) after coating protective layer on the wafer surfaces to prevent any particle and contaminant that may cause interface voids during the subsequent bonding process. It is followed by activating the bonding surface by plasma and

504

6 Cu-Cu Hybrid Bonding

Fig. 6.102 a SEM cross-sectional image of the bonded Cu/SiO2 hybrid interface. b TEM crosssectional image of the interface of the bonded Cu/Cu electrodes. c TEM cross-sectional image of the bonded SiO2 -SiO2 interface

hydration processes for better hydrophilicity and higher density of hydroxyl group on the bonding surface. For the chiplet wafer, repeat the CVD for the SiO2 , CMP for the Cu dishing, and plasma and hydration of the activation of the bonding surface. Then, pick and place the individual bridge chip on the chiplet wafer and perform the SiO2 -to-SiO2 bonding at room temperature. It is followed by annealing for covalent bonding between oxide layers and metallic bonding between Cu-Cu contact and diffusion of Cu atoms. For the package substrate, stencil print the solder paste on the substrate and then reflow into C4 solder bumps. For the final assembly, the bridge + chiplets module is pick and place on the package substrate, then reflow the C4 bumps. Figure 6.104 shows the process flow of hybrid bonding bridge with C4 bumps on the chiplet wafer. It can be seen that, comparing with the C4 bumps on the package substrate, the process steps for the bridge wafer and the chiplet wafer are the same up to bridge-to-chiplet wafer bonding. After that, the C4 bumps are made by wafer bumping on the chiplet wafer. Then, dice the chiplet wafer into individual module (bridge + chiplets). The final assembly is by picking and placing the individual module on the package substrate and reflowing the C4 solder bumps (Fig. 6.104).

CMP

Squeegee

Cu Dishing SiO2

Solder Stencil

Plasma

Plasma

Stencil Printing Solder

Dicing

Wafer

Bridge

Bridge

Chiplet

Individual Bridge-to-Chiplet Wafer bonding (RT)

Chiplet

Solder Reflow

C4 bump

Hydration

Hydration

Fig. 6.103 Hybrid bonding bridge with C4 bumps on the package substrate

Package Substrate

Package Substrate

Chiplet Wafer

Si

CMP

Chiplet Wafer

Bridge Wafer

Si

Cu Dishing SiO2 Bridge Bridge

Bridge Wafer

C4

Chiplet

Cu

≤50μm Chiplet

Annealing & then Dicing

Cu Pad

Bridge

Chiplet

Package Substrate

Bridge

Cu

Chiplet

Cu-Cu hybrid bonding

Chiplet

Bridge

Final Assembly Chiplet

X-View

TopView

6.18 Unimicron’s Hybrid Bonding 505

CMP

Cu Dishing SiO2

Dicing

Cu Dishing SiO2

Plasma

Plasma

Hydration

Hydration

Fig. 6.104 Hybrid bonding bridge with C4 bumps on the chiplet wafe

Package Substrate

Package Substrate

Chiplet Wafer

Si

CMP

Chiplet Wafer

Bridge Wafer

Si

Bridge Wafer

Chiplet

Bridge

Bridge

Bridge

Wafer

Bridge

Chiplet

Individual Bridge-to-Chiplet Wafer bonding (RT). Then, C4 wafer bumping

C4 bump

Bridge

Chiplet

Cu

Chiplet

Package Substrate

Bridge

Cu

Chiplet

Annealing & then Dicing

Cu Pad

Bridge ≤50μm

Final Assembly

C4 bump

Chiplet

Cu-Cu hybrid bonding

Chiplet

C4 bump

Chiplet

X-View

Top-View

506 6 Cu-Cu Hybrid Bonding

6.20 Summary and Recommendation Transistor Scales

100s

507

10000s

Millions

Trillions

Smartphones, Self-drive Cars, Social Media

$1000 Annual Semiconductor Rev. ($B)

Billions

Phones, Video, PCs, DRAM 5G/6G, AI, IoT, Cloud, Data Center

$300 PCs, Military, Radios Laptop, Internet, Digital Cellular,

$30

$1 1970

1980

1990

2000 Year

2010

2020

2030

Fig. 6.105 Computer centric, mobile centric, and data centric

6.19 D2W vs. W2W Hybrid Bonding Table 6.10 shows the advantages, disadvantages, and applications of D2W vs. W2W hybrid bonding. It can be seen that the advantages of W2W hybrid bonding are high throughput, know-hows, and already in HVM. On the other hand, the advantages of D2W hybrid bonding are high assembly yield with KGD and design flexibility. The disadvantages of W2W are high assembly yield loss with KGDs bonded on bad dies, the chip sizes have to be almost the same, and the topography control of the Cu/dielectric surface. There are many challenges of D2W hybrid bonding as shown in Table 6.10 and it is more difficult to assemble than W2W. Some of these challenges can be handled by, e.g., collective die-to-wafer hybrid bonding process proposed by EVG [140].

6.20 Summary and Recommendation Some important results and recommendations are summarized as follows. • Hybrid bonding is one of the flip chip assembly technologies. • Hybrid bonding can be applied to very fine-pitch (as low as 1 μm) pads and used for extremely high-density and high-performance applications such as data centric, Fig. 6.105. • Hybrid bonding leads to a very low-profile package.

508

6 Cu-Cu Hybrid Bonding

Table 6.10 Advantages, disadvantages, and applications of D2W vs. W2W hybrid bonding Hybrid Bonding Advantages W2W

D2W (C2W)

Disadvantages (Challenges)

Applications

• High throughput

• High assembly yield loss • CIS

• Mutual technology

• Similar die sizes

• HBM

• High Volume manufacturing

• Topography control of the Cu/dielectric surface

• NAND flash

• High assembly yield with • The edge effects due to KGD singulation

• Design flexibility

• AI

• Contaminants due to singulation

• HPC

• Particles due to singulation

• Machine leaning

• The requirement of higher accuracy pick & place machines

• Logic

• Slightly larger pads to compensate the pick & place tolerance

• SoC

• CMP for metal recess, clean, and flat surface • Topography control of the Cu/dielectric surface

• Hybrid bonding is mostly suitable for silicon-to-silicon assembly such as CoC, CoW, and WoW. • Because of the throughput issue, CoC bonding will not be popular. Because of the chip-size and yield issues, WoW bonding is limited even it will be used more than today. Because of the flexibility, CoW will be the mainstream. • Some of the challenges of CoW hybrid bonding are given as follows: – – – – – –

the edge effects; contaminants; particles due to singulation; the requirement of higher accuracy pick & place machines; slightly larger pads to compensate the pick & place tolerance; CMP for metal recess, clean, and flat surface.

• So far, the dielectric materials for hybrid bonding are SiO2 , SiCN, and polymer such as polyimide. For the seek of the quality of the chips after bonding, other dielectric materials for lower annealing temperature and shorter duration should be investigated. • So far, the metal contact for hybrid bonding is Cu. Thus, for the seek of the quality of the chips after bonding, the ECD Cu solutions to fabricate the Cu-pad for lower annealing temperature and shorter during should be investigated.

References

509

• A hybrid bonding bridge for chiplet design and heterogeneous integration packaging has been proposed. This hybrid bonding bridge leads to the lowest packaging profile. • So far, Sony’s BI-CSI, YMTC’s 3D NAND flash, Graphcore’s BOW, and AMD’s 3D V-Cache are the HVM product using Cu-Cu hybrid bonding technology. In the near future, HBM will also be manufactured by hybrid bonding technology. • In order to have more HVM products using the bumpless hybrid bonding technology, more research and development efforts should be placed on areas such as: – – – – – – – – – – – – – – –

Cost reduction Nanoscale topography (CMP) Thin-wafer handling Design parameter optimization Process parameter optimization High-precision pick and place equipment Bonding environment CoW and WoW bonding alignment Wafer distortion and warpage Inspection and testing Contact integrity Contact quality and reliability Manufacturing yield Manufacturing throughput Thermal management

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