Моделирование элементов микросистемной техники в VHDL-AMS

Citation preview

621.382.8(07) 851

№ 3412

VHDL-AMS 201900, 220500 550700, 551100

2003

621.382.8(07)

: . .

, . .

" VHDL-AMS".

:

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, 2003. 26 .

VHDL-AMS. ,

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VHDL-AMS.

hAMSter.

. 8.

.: 4

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, . VHDL (VHDL-AMS – Very High Speed Integrated Circuits Hardware Description Language Analog-Mixed Signals), , , , , , ., / , . , VHDL-AMS. hAMSter ver.2.0 (High performance AMS Tool for Engineering and Research) Ansoft Corporation, [1]. VHDL-AMS, VHDL,

hAMSter

VHDL-AMS, hAMSter.

-

4 1.

VHDL-AMS VHDL-1076-1993

IEEE

.

IEEE – VHDL Std 1076.1-1999, VHDL-AMS (Very High Speed Integrated Circuits Hardware Description Language Analog-Mixed Signals) [2,3]. [2,3]: • ; • ; • , ; • ; • , . , / . VHDL-AMS Std 1076.1-1999 [1,2,3]: 1) : ( . . ) ; , . . ; 2) : , ( ); ; ; 3) , , ; 4) VHDL ; ; , . 2.

VHDL-AMS 2.1. , . [1, 2, 3]. Std 1076.1-1999

-

5 VHDL-AMS

VHDL, [2]: across, contribution, ground, nature, quantity, reference, terminal, through, tolerance. , , entity architecture. 2.2. VHDL-AMS Std 1076.1-1999 [1, 2]: == – := – = – +– -– *– /– ** –

; ;

, ;

; ,

; ;

, ,

;

,

; ,

real sin(real x), real cos(real x), real tan(real x) real asin(real x), real acos(real x), real atan(real x) real sinh(real x), real cosh(real x), real tanh(real x) real log(real x), real log10(real x)

–

;

,

, ;

–

,

, ;

–

,

, ;

– ;

real exp(real x) real sqrt(real x)

– –

; ;

real pow(real a, real x)

– ;

integer abs(integer x)

–

.

2.3. VHDL-AMS

, VHDL-AMS

[2,3]: • real – • integer – • natural – • positiv –

VHDL. -

; ; ; ;

-

6

• • • • •

bit – boolean – vector – bit_vector – time – ,

{‘0’, ‘1’}; {false, true}; real; bit; “ ”. VHDL-AMS

-

, (domain) [3]: electrical_systems; mechanical_systems; fluidic_systems; radiant_systems; thermal_systems; chemical_systems. . 2.4. VHDL-AMS 1. Constant –

[2,3]. .

-

. ,

.

2. Variable –

.

, . .

3. Signal –

.

, (

). 4. Quantity –

-

.

. -

,

. Quantity

. quantity.

quantity . .

Quantity

,

,

. Quantity .

quantity . quantity (IN, OUT, INOUT):

ENTITY example IS PORT ( QUANTITY inl, in2: IN real; QUANTITY out1: OUT real); END example;

quantity, ,

-

7 • Q'dot – • Q'integ – • Q'delayed(t) –

quantity: quantity Q quantity Q quantity Q

; ; , t ≥ 0);

-

• ANOW – ; • Q'slew (max_rising_slope, max_falling_slope) –quantity Q, ( ) ; • Q'ltf(num,den) – quantity Q . num – REAL_VECTOR, ; den – REAL_VECTOR, . Q s. . quantity, Q'Dot Q'lnteg; • Q'zoh (T,initial_delay) – quantity Q. Q. – , ; initial_delay – , ( 0.0); • S'ramp (tr,tf) – quantity, S, ; • S'slew (max_rising_slope, max_falling_slope) – quantity, S, ( ), ; • Q'ztf (num, den, T, initial_delay) – Zquantity Q . num – REAL_VECTOR, ; den – REAL_VECTOR, ; – real, ; initial_delay– real, ( 0.0). ZQ 1/z. , Zquantity. . STANDARD . 5. Terminal ( ) nature , (

8 . Branch_quantity (

)

-

. nature – electrical_systems, mechanical_systems . . branch_quantity: - across quantity – , , , ; - through quantity – , , . nature ( . 1).

,

-

,

,

-

[1]:

SUBTYPE voltage IS real; SUBTYPE current IS real; NATURE electrical IS voltage ACROSS; current THROUGH; TERMINAL plus, minus: electrical; QUANTITY v ACROSS i1, i2 THROUGH plus TO minus; (v – across, v = vt1 - vt2; i1, i2 – through, plus minus).

tl

t2:

, :

– voltage ( nature electrical; nature electrical .

-

)

current ( quantity across

.1. И Across quantity , a quantity through ( plus minus). branch_quantity . . . , quantity through il i2 – . quantity, . nature . quantity

);

through

nature electrical -

nature quantity across v – "

"

9 "

"

( ). ,

-

. . PORT (TERMINAL anode, cathode: electrical);

: -

. nature

-

, nature. N quantity ( . 2) [1]: T'Reference N " "); quantity T'Contribution through quantity,

-

-

N'Reference.

-

quantity across N'Reference ( . .

-

quantity through, ( ,

). branch_quantity

.

.2. T'Reference,

T'Contribution

,

.

.

across quantity .

(referance) quantity , quantity quantity “

. , . ”

( ) (branch_quantity), . . . branch_quantity

, , . . ,

quantity

–

-

10 (

). 2.5. VHDL-AMS

[3]. VHDL-AMS

, . (package)

, .

, VHDL-AMS

-

, [4]: PACKAGE < < END < _

_

> IS ,

,

,

>;

>;

PACKAGE BODY < _ < >; END < _ >;

> IS

electrical_system [2]: PACKAGE electrical_system IS TYPE current IS RANGE -1.0e+6 TO 1.0e+6; UNITS A; mA = 1.0e-3 A; uA = 1.0e-3 mA; kA = 1.0e+3 A; END UNITS; TYPE voltage IS RANGE -1.0e+9 TO 1.0e+9; UNITS V; mV = 1.0e-3 V; uV = 1.0e-3 mV; kV = 1.0e+3 V; END UNITS; NATURE electrical IS voltage ACROSS current THROUGH; END electrical_system; , ,

, [4]:

11 LIBRARY < USE < _

_

>; _

>.
.
; . -

, ALL, USE
.
.ALL; :

LIBRARY IEEE; USE ieee.electrical_systems.ALL; , – entity , )

, , entity

entity. generic_clause ( entity [4]:

ENTITY < _ > IS GENERIC (< PORT (< _ END < _ >; AMS terminal

entity.

_

port_clause ( ) [2,3].

_ >);

_

_

>);

VHDL

:

quantity.

terminal

, quantity

natural, (

).

(

-

,

)

[2,3]. entity SIGNAL < >:< TERMINAL < >:< QUANTITY < >:
< >;

[3]:

> (:= < >
);

>; IN (

), OUT (

), INOUT ( entity:

ENTITY resistor IS GENERIC (CONSTANT r : resistance);

).

-

12 PORT (TERMINAL node1, node2 : electrical); END resistor; entity .

entity

. (architecture_body). architecture_body

“

”

, . .

. ,

[2,3,4]. , . [2,3,4]. architecture_body

ARCHITECTURE < < _ BEGIN < _ END < _

_

> OF
IS

>; >; >;

VHDL-AMS

VHDL – (terminal_declaration)

(quantity_declaration) [2,3]. Terminal_declaration

-

natural. branch_quantity,

teminal. , , Quantity_declaration

terminal_declaration – branch_quantity – / . quantity, . .

-

-

, , architecture_body:

.

ARCHITECTURE behavioral OF resistor IS QUANTITY v ACROSS i THROUGH node1 TO node2; BEGIN v == i*r; END behavioral; entity

architecture_body, [3,4].

-

13 2.6.

: simultaneous_statement simultaneous_statement

concurrent_statement [3]. .

simultaneous_statement – ,

.

-

quantity. :

,

quantity. -

, , ,

, .

VHDL-AMS

terminal. architecture_body simultaneous_statement [3]. simple_simultaneous_statement –

1.

, .

quantity

signal,

-

,

,

, .

simple_simultaneous_statement,

real

, integer.

:

+, -, *, /, **. . simple_simultaneous_statement: a’DOT == 2.0*(b + x**3.0); simultaneous_if_statement simultaneous_case_statement

2.

. quantity,

signal.

. simultaneous_if_statement: IF
USE _ _1>; _2> USE _ _2>;

< ELSIF < < … ELSE < _ END USE;

_n>;

simultaneous_if_statement: IF sig = ‘1’ USE var == a + b; ELSE var == a + b**2.0; END USE;

-

14 simultaneous_if_statement

sig – var

bit. quantity

-

. simultaneous_case_statement:

simultaneous_case_statement: CASE < WHEN < < WHEN < < … END CASE;

CASE sig USE WHEN 0 USE var == a + b; WHEN 1 USE var == a + b**2.0; WHEN 2 USE var == a + b**3.0; WHEN OTHER USE var == a; END CASE;

> USE _1> USE _1>; _2> USE _2>;

simultaneous_case_statement sig – integer. sig var quantity . , < > simultaneous_if_statement < > simultaneous_case_statement , quantity. oncurrent_statement

-

. .

concurrent_statement [3]. [3].

oncurrent_statement 1.

(process)

-

, . , VHDL-AMS process, (< _ >) PROCESS (< _ < _ BEGIN < _ END PROCESS (< 2.

. -

[3]:

>) >; >; _

>);

selected_signal_assignment

, .

selected_signal_assignment [3]:

15
WHEN < _2> ELSE _2> WHEN < _2> ELSE _(n-1)> WHEN
ELSE
; -

‘ABOVE. FALSE,

q’ABOVE(v)

q

boolean, q < v, v–

quantity TRUE, q > v,

. selected_signal_assignment: s