Symbolic Analysis and Reduction of VLSI Circuits 0387239049, 9780387239040

Citation preview

Symbolic Analysis and Reduction of VLSl Circuits

Zhanhai Qin Sheldon X. D. Tan Chung-Kuan Cheng

Symbolic Analysis and Reduction of VLSI Circuits

a- springer

Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available

from the Library of Congress. ISBN 0-387-23904-9 e-ISBN 0-387-23905-7 Printed on acid-free paper. O 2005 Springer Science+Business Media, Inc. All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, Inc., 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now know or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if the are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.

Printed in the United States of America. 9 8 7 6 5 4 3 2 1

SPIN 11352921

To our wives Li, Yan, and Jenny.

Contents

Dedication List of Figures List of Tables Preface Acknowledgments Part I Fundamentals 1. INTRODUCTION 1 What is Symbolic Analysis 1.1 A "Hello-World" Example 1.2 Problem Formulation for Symbolic Analysis 2 Linear Circuit Reduction 2.1 Projection-Based Model Order Reduction 2.2 Generalized Y-A Transformation 3 Symbolic Analysis for Analog Circuit in a Nutshell 3.1 Topological Analysis 3.2 Determinant Decision Diagram 3.3 Symbolic Analysis of Nonlinear Circuits 4 What's Covered in this Book 4.1 Symbolic Analysis in Digital Circuitry 4.2 Symbolic Analysis in Analog Circuitry 5 Summary

2. BASICS OF CIRCUIT ANALYSIS 1 Time Domain Analysis 1.1 RC Interconnect Circuit Formulation

v

...

Xlll

xix xxi xxiii

...

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Vlll

2

3

4

1.2 RLC Interconnect Circuit Formulation 1.3 General RLC Interconnect Circuit Formulation 1.4 Remarks Responses in Time Domain 2.1 Responses in Closed Form 2.2 Taylor Expansion in Time Domain s Domain Analysis 3.1 Transfer Function 3.2 Responses from s Domain to Time Domain Preliminaries of Symbolic Analysis 4.1 Matrix, Determinant, and Cofactors 4.2 Cramer's Rule

Part I1 Linear VLSI Circuits 3. MODEL-ORDER REDUCTION 1 s Domain Analysis 2 Moments and Moment-Matching Method 2.1 Concept of Moments 2.2 Delay Estimation Using Moments 2.3 Deriving Moments from MNA Formulation 2.4 Deriving Moments for RLC Trees 3 Realizable Topological Reduction Methods 3.1 TICER 3.2 Realizable RLC T-Model Reduction 3.3 Scattering-Parameter-Based Macro Model Reduction 4 Summary 4. GENERALIZED Y-A TRANSFORMATION FUNDAMENTAL THEORY 1 Introduction 2 Classical Y-A Transformation 2.1 Numerical Example 2.2 Y-A Transformation and Gauss Elimination 2.3 Notations and Terminologies to be Used 3 Generalized Y-A Reduction 3.1 Branch with RCLK Elements 3.2 Branches with Current and Voltage Sources

Contents

4 5 6

3.3 RCLK-VJ Generalized Formulae for Y-A Transformation 3.4 Higher-Order Truncation Node Ordering Generalized Y-A Reduction Flow Summary

ix 71 72 73 74 76

5. GENERALIZED Y-A TRANSFORMATION ADVANCE TOPICS 77 Common-Factor Effects 77 1.1 Example on Common-Factor Effects 77 1.2 Existence of Common Factors 79 1.3 Common Factors in Current Source Transformation 82 Revised Generalized Y-A Reduction Flow -A Redundancy-Free Version 83 Multiport Y-A Reduction 85 3.1 Backward-Solving in LU Factorization 85 3.2 A-Y Recovery 87 3.3 Multiport Y-A Reduction Flow 89 Treating Roundoff Errors 89 4.1 Fundamentals of Roundoff Errors 89 4.2 Roundoff Errors in Y-A Transformations 91 4.3 Solution to Roundoff Problems in Y-A Transformation 92 Experimental Results 95 Summary 97 Appendices 97 7.1 Existence of Type-I1 Common Factor 97 7.2 Recursive Existence of Type-I1 Common Factor 103 7.3 Existence of Type-I andType-I1Common Factors in Current Source Transformation 103 7.4 Simplest Form of Y-A Transformation 111 6. Y-A TRANSFORMATION: APPLICATION I - MODEL STABILIZATION 1 Hurwitz Polynomial 117 2 The Routh-Hurwitz Criterion 118 2.1 Necessary Conditions 118 2.2 The Routh-Hurwitz Criterion -A Necessary and Sufficient Condition 119 2.3 Proof of the Routh-Hurwitz Criterion 123

x

SYMBOLIC ANALYSIS AND REDUCTION OF VLSl CIRCUITS

3 4 5

Stabilizing Models After Y-A Reduction Experimental Results Summary

7. Y-A TRANSFORMATION: APPLICATION I1 REALIZABLE PARASITIC REDUCTION 1 First-Order realization 2 Admittance Not Realizable in Nature 3 Idea of Templates 4 Geometric Programming 4.1 Intuitions 4.2 Primal and Dual Functions 4.3 Orthogonality Conditions 4.4 Solution Space of Dual Problems 4.5 Geometric Programming with Constraints 5 Template Realization Using Geometric Programming 6 Experimental Results 7 Summary Part I11 Analog VLSI Circuits 8. TOPOLOGICAL ANALYSIS OF PASSIVE NETWORKS 1 Review of Node Admittance Matrix 1.1 Incidence Matrix of Undirected Graph 1.2 Incidence Matrix of Directed Graph 1.3 Composition of Node Admittance Matrix 2 Problem Formulation 2.1 Driving-Point Admittance Y ,(s) 2.2 Open-Circuit Impedance Zij (s) 2.3 Network Transfer Functions 3 Topological Formulas 3.1 Topological Formula for Determinant A 3.2 Topological Formula for Aij 3.3 Time Complexity 4 Flow-Graph Technique 5 Summary

Contents

9. EXACT SYMBOLIC ANALYSIS USING DETERMINANT DECISION DIAGRAMS 1 Combination Set Systems and Zero-Suppressed Binary Decision Diagrams 2 DDD Representation of Symbolic Matrix Determinant 3 An Effective Vertex Ordering Heuristic 4 Manipulation and Construction of DDD Graphs 4.1 Implementation of Basic Operations 4.2 Illustration of Basic Operations and its Use in Circuit Sensitivity 5 DDD-based Exact Symbolic Analysis Flow 6 Related to Other Decision Diagram Concepts 7 Application to Symbolic Analysis of Analog Circuits 8 Summary 9 Historical Notes on Symbolic Analysis Techniques 10. S-EXPANDED DETERMINANT DECISION DIAGRAMS FOR SYMBOLIC ANALYSIS 1 Introduction 2 s-Expanded Symbolic Representations 3 Vertex Ordering for s-Expanded DDDs 4 Construction of s-Expanded DDDs 4.1 The Construction Algorithm 4.2 Time and Space Complexity Analysis 5 Applications of Deriving Transfer Functions 6 Summary 11. DDD BASED APPROXIMATION FOR ANALOG BEHAVIORAL MODELING 1 Introduction 2 Symbolic Cancellation and De-cancellation 3 Dynamic Programming based Generation of Dominant Terms 4 Incremental k-Shortest Path Algorithm 4.1 DDD-based Approximation Flow 5 Application to AC Characterization of Analog Circuits 6 Summary 7 Historical Notes on Symbolic Approximation 8 Appendix

xi

185 187 191 196 197 200 203 204 206 208 209

21 1 212

228 23 1 237 238 240 240 24 1

xii

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

12. HIERARCHICAL SYMBOLIC ANALYSIS AND HIERARCHICAL MODEL ORDER REDUCTION 245 1 DDD-based Hierarchical Decomposition 246 1.1 Subcircuit Reduction 246 1.2 Overview of The Simulation and Reduction Algorithm 249 2 DDD-based Hierarchical Decomposition 250 3 Cancellation Analysis for Subcircuit Reduction 253 3.1 Cancellation Due to Circuit Devices 253 3.2 Cancellation Due to Subcircuit Reduction 254 3.3 Theoretical Analysis of Cancellation Conditions 257 3.4 Device-Level Cancellation From Subcircuit Reduction's Perspective 259 3.5 Cancellation at Different Hierarchical Circuit Levels 259 4 General s-Domain Hierarchical Network Modeling and Simulation Algorithm 26 1 4.1 Cancellation-FreeRational Admittance 26 1 4.2 Y-expanded DDDs 262 4.3 Computation of Cancellation-FreeRational Admittances 264 4.4 Clustering Algorithm 267 5 Hierarchical Analysis of Analog Circuits - Examples 267 6 Summary 270 7 Historical Notes on the Model Order Reduction 27 1 References

273

Index

28 1

List of Figures

Symbolic analysis of a simple RC circuit RC circuit for illustration of DDD A matrix determinant and its DDD representation. A RC tree demonstrating nodal analysis formulation: current flowing out of a node is equal to currents flowing into the node

RLC parasitics of a segment of interconnect on metal layers:(a) illustration of orthogonal interconnect layers (b) RLC parasitic model of an interconnect segment in layer 3. RLC circuit meeting the two prerequisites. Shaded ones are the so-called intra-branch nodes A RLC tree demonstrating modified nodal analysis formulation. A linear network with two inputs and three outputs. Scenario that the median and mean points mismatch: when the unit impulse response H ( t ) (scaled) is not symmetric, 50% delay of unit step response Y ( t ) ,or the median point of H ( t ) , does not overlap with the mean point of H ( t ) . Scenario that the median and mean points of H ( t ) overlap: when H ( t ) is symmetric, 50% delay point of Y ( t )matches the mean point of H ( t ) ,i. e., the approximation is exact. The original RLC tree in Example 3.3. The "resistive tree" for computing

MO

in Example 3.3.

The "resistive tree" modified based on the original RLC circuit by zeroing out inputs and replacing capacitors and inductors with current and voltage sources, respectively.

xiv

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

3.6

Illustration showing a type of non-tree circuit configuration having trivial DC solutions: (a) A RLC network; (b) the companion network of (a) for which all the links can be specified by current sources (or capacitors in the original network).

3.7

Two .rr models connected in series. (a) The original circuit; (b) the reduced circuit.

3.8

Two .rr models connected in parallel. (a) The original circuit; (b) the reduced circuit.

3.9

Transfer function evaluation and propagation. Each branch in the tree is a RLC .rr model.

3.10 2-port network showing incident waves ( a l ,a 2 )and reflected waves (bl, b2) used in scattering parameter definitions. 3.11 A multiport representation 3.12 Merge the two networks denoted by X,,, and Y,, perfectly interconnected nodes nx, and ny,.

at two

3.13 Illustration of self merging 4.1 A numerical example on Y-A transformation: (a) before the transformation; (b) after the transformation. 4.2

Conversion on mutual K in s-domain: (a)given mutual K element; (b) converted self K elements.

4.3

Y-A transformation with current source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

4.4

Y-A transformation with voltage source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

5.1

A numerical example showing common factor existence: (a) no is to be eliminated; (b) n l is to be eliminated; (c) after both no and nl are eliminated.

5.2

Example revisit -Y-A transformations: (a) original circuit; (b) after the transformation on node no; (c) after the transformation on noden1 .

5.3

An example floating point number system

5.4

(a) algorithm requiring enumeration of the numerator of Yij: addition and multiplication operations only; (b) algorithm requiring extra division operation.

5.5

Finding common partial terms in the numerator of Yij by partition. 94

List of Figures

Transient response evaluated using Y-A transformation with Hurwitz approximation as compared to AWE method and SPICE simulations for coupled RLC bus lines. Order of admittance after Y-A transformation with recognizing common factors as compared to a naive implementation without recognizing common factors. Three Y-A Transformations in Proof of Th. 5.3: (a) eliminating no; (b) eliminating n,; (c) eliminating n l A Series of Y-A Transformations in Proof of Th. 5.4: (a) eliminating nk; (b) eliminating n,,; (c) eliminating n,,; (d) eliminating n f . Three Y-A Transformations in Proof of Th. 5.3: (a) eliminating no; (b) eliminating n,; (c) eliminating n l Illustrating orders of admittances in Y-A transformation on = lull = 5 ; (b) 6-node complete graph: (a)

9,

, 1 4= 9; (c) p = ~;j;, * Iw31 = 12; (d)

y(2) =i B~,,

yf4) = 1

x(5)

1w4l = 14; (e) = Illustration for proof of Theorem 5.6: (a) n l , ng, n5, n7 are to be eliminated; (b) n2, n s are to be eliminated; (c) n g is to be eliminated; (d)transformation finished. A s-plane plot showing vectors s - si. Examples showing the sign difference of s and s - s, for different s, locations. s, must lie on the imaginary axis to make s and s - s, agree on sign. 2-D and 3-D Plots of y(s) when k = 5. 2-D and 3-D Plots of Re(p) when k = 0. 2-D and 3-D Plots of Re(p) when k = -5. Plot of root locations for different k values. Pole analysis using Y-A transformation with Hurwitz approximation as compared to Y-A transformation only and AWE method for RLC powerlground mesh. First Order Realization: (a) RC configuration; (b) RL configuratiod42 Unrealizable admittance after Y-A transformation (YI2 and Y2g) 143 Brune's Admittance Structure 144 Comparison of two reduced circuits 151 151 Comparison of responses of a RC network Comparison of responses of a RLC network 152 B~WB

xvi

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

An undirected graph G1 with 4 vertices and 6 edges. 156 A directed and connected graph G2 with 4 vertices and 6 edges. 157 A directed and unconnected graph Gg with 7 vertices and 9 edges158 A 4-node linear network used in Example 8.4. 160 One-port network driven by single current source ISi. 161 Two-port network driven by two current sources Isi and Isj. 162 Illustration of the two-port in determining open-circuitimpedances163 164 A loaded passive two-port N Removing leaf node one at a time corresponds to expanding the row of the node in Ai and its minor matrices. 167 An illustrative one-port example. 168 All the possible trees of the one-port with resistive branches only169 Minor matrix Y,j. 169 Computing minor matrix Y,j from (A&)-i and (AT) +. 170 Network N-2 deduced from N from Fig. 8.4 by merging @ and the ground. 171 A 2-tree example used in Example 8.15. 171 Using topological formulas to solve for open-circuit transfer impedance of a 2-port. 172 Using topological formulas to solve for open-circuit transfer impedance of a 2-port. 173 Counter-example showing invalid 2-trees in the computation of cofactors Aij 173 The flow graph of (4.2). 175 The subgraph of Gc in (4.2). 177 The two connections of G,,. 177 The four one-connections of G,: (a)(b)The two one-connections from 1 to X I ; (c)(d) The two one-connections from 1to 22. 178 181 Graph G, of the proof of Lemma 8.1. 181 Graph G: of the proof of Lemma 8.2. (a) A ZBDD example. (b) An illustration of the zero-suppression rule. 186 A ZBDD representing {adgi,adhi, af ej, cbgj,cbih) under orderi n g a > c > b > d >f > e > g > i > h > j . 188 A signed ZBDD for representing symbolic terms. 189 191 A determinant decision diagram for matrix M. DDD representing det (M) under ordering a > c > d > f > 9 > h>b>e>i>j. 192

List of Figures

A DDD vertex ordering heuristic. An illustration of DDD vertex ordering heuristic. An illustration of DDD construction for band matrices. A comparison of DDD sizes verse numbers of product terms for band matrices. A three-section ladder network. Illustrations of DDD graph operations. DDD-based derivation of cofactors. Illustration of DDD-based cofactoring. DDD-based exact symbolic analysis flow A determinant expansion and its DDD representation. The MOSFET small-signal model. The Bipolar transistor model. The circuit schematic of bipolar pA741. The circuit schematic of MOS cascode Opamp. pA741 frequency responses versus COMP values An example circuit A complex DDD for a matrix determinant An s-expanded DDD by using the labeling scheme The s-expanded DDD construction with the second labeling scheme The basic s-expanded DDD construction algorithms MULTIPLY(P[~], D.x) operation U N I O N ( P[i]~, P2[i]) operation Product term distribution of pA741 by the second labeling scheme. Sizes of s-expanded DDDs vs sizes of the complex DDDs. A simplified two-stage CMOS opamp. Matrix patterns causing term cancellation. Cancellation-free COEFFMULTIPLY. Cancellation-free multi-root DDD. Dynamic programming based dominant term generation. Implementation of SUBTRACT() for symbolic analysis and applications. A reverse DDD. Incremental k-shortest path algorithm. Incremental k-shortest path based dominant term generation

xvii

193 193 195 196 196 198 202 202 204 205 206 207 207 208 209 213 214 216 218 218 219 220 222 223 226 227 228 228 230 23 1 233 234 235

xviii

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

11.10 THERELAX() operation. 11.11 DDD-based symbolic approximation flow 11.12 CPU time vs number of ladder sections. 11.13 Memory use vs number of ladder sections. 12.1 A hierarchical circuit 12.2 The general hierarchical network reduction algorithm flow 12.3 Illustration of Theorem 12.1 12.4 Matrix patterns causing term cancellation. 12.5 A simple RC circuit. 12.6 Cancellation pattern due to subcircuit reduction 12.7 An impedance stamp and the stamp in the reduced matrix. 12.8 A determinant and its YDDD. 12.9 Y-expanded DDD construction. 12.10 Term-Cancellation Free YDDDMULTIPLY. 12.11 Computation of the cancellation-free rational function from a YDDD. 12.12 A second-order active filter. 12.13 A linear model of an Opamp circuit. 12.14 An active low-pass filter. 12.15 An FDNR subcircuit. 12.16 The frequency response of the active filters (exact vs 8th, loth, 16th order approximation).

List of Tables

CPU runtime using Y-A technique as compared to SPICE3f4 for five industrial circuits. 7.1 Efficiency comparison 9.1 Summary of Basic Operations. 11.1 Poles and zeros for opamp Twostage.

5.1

96 152 197 238

Preface

Symbolic analysis is an intriguing topic in VLSI designs. The analysis methods are crucial for the applications to the parasitic reduction and analog circuit evaluation. However, analyzing circuits symbolically remains a challenging research issue. Therefore, in this book, we survey the recent results as the progress of on-going works rather than as the solution of the field. For parasitic reduction, we approximate a huge amount of electrical parameters into a simplified RLC network. This reduction allows us to handle very large integrated circuits with given memory capacity and CPU time. A symbolic analysis approach reduces the circuit according to the network topology. Thus, the designer can maintain the meaning of the original network and perform the analysis hierarchically. For analog circuit designs, symbolic analysis provides the relation between the tunable parameters and the characteristics of the circuit. The analysis allows us to optimize the circuit behavior. The book is divided into three parts. Part I touches on the basics of circuit analysis in time domain and in s domain. For an s domain expression, the Taylor's expansion with s approaching infinity is equivalent to the time domain solution after the inverse Laplace transform. On the other hand, the Taylor's expansion when s approaches zero derives the moments of the output responses in time domain. Part I1 focuses on the techniques for parasitic reduction. In Chapter 3, we present the approximation methods to match the first few moments with reduced circuit orders. In Chapter 4 we apply a generalized Y-Delta transformation to reduce the dynamic linear network. The method finds the exact values of the low order coefficients of the numerator and denominator of the transfer function and thus matches part of the moments. In Chapter 5, we handle two major issues of the generalized Y-Delta transformation: common factors in fractional expressions and round-off errors. Chapter 6 explains the stability of the reduced expression, in particular the Ruth-Hurwitz Criterion. We make an effort to

xxii

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

describe the proof of the Criterion because the details are omitted in most of the contemporary textbooks. In Chapter 7, we present techniques to synthesize circuits to approximate the reduced expressions after the transformation. In Part 111, we discuss symbolic generation of the determinants and cofactors for the application to analog designs. In Chapter 8, we depict the classical topological analysis approach. In Chapter 9, we describe a determinant decision diagram (DDD) approach that exploits the sparsity of circuit matrices for a compact representation of a symbolic determinant. In Chapter 10, we apply the DDD approach to deriving the s-expanded polynomial from a determinant. In Chapter 11, we take only significant terms when we search through determinant decision diagram to approximate the solution. In Chapter 12, we extend the determinant decision diagram to a hierarchical model. The construction of the modules through the hierarchy is similar to the generalized Y-Delta transformation in the sense that a byproduct of common factors appears in the numerator and denominator. Therefore, we describe the method to prune the common factors.

Acknowledgments

Jeff Qin is obliged to Professor Chung-Kuan Cheng for his guidance and enlightenment during his graduate study at University of California, San Diego. Jeff Qin is grateful to Dr. Li-Pen Yuan for his encouragement while Jeff works at Synopsys. Sheldon X.-D. Tan is grateful to Professor Richard C.-J. Shi for his advising during his graduate studies at the University of Iowa and the University of Washington, which leads to some of the works presented in this book. Chung-Kuan Cheng is indebted to Professor Ernest Kuh for his guidance and inspiration toward circuit analysis research. Jeff Qin thanks his wife Li Yang, Sheldon X.-D. Tan thanks his wife, Yan Ye, and Chung-Kuan Cheng thanks his wife Jenny Cheng for their consistent patience and encouragement throughout the course of writing this book. Jeff Qin and Chung-Kuan Cheng would like to acknowledge the support of the NSF, GSRC, SRC, Cal IT2, and California MICRO program matched by Altera, Conexant, Fujitsu, HP, Mentor Graphics, NEC, Qualcomm, Sun Microsystems, and Synopsys. The support is essential to keep the project surviving throughout Jeff's Ph.D. program and the composition process of the book. Sheldon X.-D. Tan would like to thank for the support of UC Regent's Faculty Fellowship.

PART I

FUNDAMENTALS

Chapter 1

INTRODUCTION

1.

What is Symbolic Analysis?

Symbolic analysis is to calculate the behavior or the characteristics of a circuit in terms of symbolic parameters. Symbolic analysis was pioneered by topological analysis methods such as the spanning tree enumeration methods [12] and signal flow graph methods [%I, which were based on the topology of given circuits. Symbolic expressions can also be generated directly from admittance matrix as shown in the some modern symbolic analyzers [37,77]. Symbolic analysis offers great advantages over numerical simulators such as SPICE 1631, which only provide numerical results, in that symbolic simulators present the relationship between circuit parameters and circuit behavior in symbolic closed-form expressions. As contribution of circuit parameters to circuit characteristics becomes obvious to designers when symbolic analysis is used. The technique is being used in many applications such as optimum topology selection, design space exploration, behavioral model generation, and fault detection, which have been summarized and illustrated by researchers [38]. On the other hand, symbolic analysis cannot replace the numerical analysis as it cannot analyze very large circuits in general. Instead it is an essential complement to numerical simulation. This is especially the case for analog circuit designers where the circuit sizes are not very large, yet circuit performance characteristics are dynamically determined by settings of many different circuit parameters [29]. Algebraic analysis lies between symbolic analysis and numerical simulation. Thus it has the advantages of both, i. e., circuit parameters are numerical values and transfer functions are presented in closed-form. Thus it explicitly shows the relationship of circuit inputs and outputs and it is able to handle very large circuits.

4

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

1.1

A "Hello-World" Example

As a simple example, Fig. 1.1 shows a circuit with two resistors and two capacitors. This circuit is stimulated by a voltage source, and the other end is

Figure 1.1. Symbolic analysis of a simple RC circuit

grounded. Symbolically in s domain, vl can be written as

This symbolic equation tells us that it is a second order low-pass filter with DC gain = 1. Of course for this simple circuit, every electrical engineer can write up the actual equation in the old pencil-and-paper style. But when circuits become large, such kind of transfer functions can grow exponentially in terms of number of product terms such as 9192. On the other hand, symbolic analysis may be able to generate them automatically. If a symbolic analyzer produces a symbolic transfer function with hundreds or thousands of symbolic product terms and with all circuit parameters mixed together, it's hard to identify the influence of every parameter to the whole function. Simplification can be applied to sort out the dominant terms of parameters. There are two strategies of doing this: rn

Mixed symbolic-algebraic analysis keeps only a small number of circuit parameters as symbols and the rest as numerical values. It helps reduce the number of total product terms and the length of each of them. The extreme of this approach is the algebraic analysis in which all circuit parameters are numerical values and the only symbol in the expressions is the complex frequency s.

rn

Symbolic simplification discards insignificant terms based on the relative magnitudes of symbolic parameters and the frequency defined at some nominal design points or over some ranges. It can be performed before, during, or after the generation of symbolic terms [8,42, 73, 107,27, 37,981.

1.2

Problem Formulation for Symbolic Analysis

Consider a lumped linear(ized) time-invariant analog circuit in frequency domain. Its circuit equation can be formulated, for example, by the nodal

Introduction analysis approach in the following general form 1961:

The circuit unknown vector x may be composed of n node voltages, and the admittance matrix A is an n x n sparse symbolic matrix, b is a vector of external sources. Symbolic analysis of analog circuits can be stated as the problem of solving the symbolic equation (1.1), i. e., to find a symbolic expression of any circuit unknowns in terms of symbolic parameters in A and symbolic excitations expressed by b. According to Cramer's rule, the kth component x k of the unknown vector x is obtained as follows: Xk

=

C y = l bi ( - l ) i f kdet(Aai,,) det ( A )

7

where d e t ( A ) is the determinant of matrix A , and (- l ) i " C d e t ( ~ a , , , )in (1.2) is the cofactor of d e t ( A ) with respect to element ai,k of matrix A at row i and column k. Most symbolic simulators are targeted at finding various network functions, each being defined as the ratio of an output from x to an input from b. Generally, a transfer function of a linear(ized) circuit can be obtained as a rational function in the complex frequency variable s :

where f i ( p l ,p2, . ,pm) andgj ( p l ,pa, . . . ,p,) are symbolic polynomial functions in circuit parameters pj ,j = 1 , ..., m. These polynomials in turn can be expressed in a nested form or an expanded sum-of-product form. Again, we can categorize symbolic analysis in terms of number of symbols in a given circuit: 1 If the polynomial coefficients, f i ( . . ) and gj (. it is namedfully or exact symbolic analysis.

. ), contain only symbols,

2 If only some circuit parameters are represented as symbols, it is named partial or mixed symbolic analysis.

3 In the extreme case is that transfer function H ( s ) has only one symbol - the complex frequency s , which happens when all circuit parameters are numerical values and the symbolic analysis degenerates to algebraic analysis. The central issue in symbolic analysis is to find symbolic expressions of det ( A )and the cofactors of d e t ( A ) .

6

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Linear Circuit Reduction

2.

linear circuits targeted in this book refer to interconnect parasitics in modern VLSI designs. Interconnects become more important to digital circuit designers than never before, because the quality of the interconnects needs to be examined in every aspect from delay to signal integrity issues. Although accurate analysis is preferable, turn-around time is never a negligible factor to be considered. Because a huge amount of interconnects are present in typical VLSI designs. Nowadays, a million-transistor design can easily accommodate miles of interconnects. To analyze interconnect parasitics accurately and quickly, linear circuit reduction has to be adopted. Researchers have devised a lot of techniques on this hot topic. Their works can be classified into two categories:

=

projection-based model order reduction. generalized Y-A transformation.

2.1

Projection-Based Model Order Reduction

Modeling complicated linear circuits with simple yet accurate circuits is called model order reduction. The idea is to analyze or simulate the simplified models to reduce circuit verification time. A number of projection-based model-order reduction based techniques have been introduced [23, 24, 25, 64, 66, 80, 791 to analyze the transient behavior of interconnects. Those projection-based algorithms mainly work for passive linear networks as the computation of moments and Krylov space base vectors requires a special partitioning of circuit matrices and solving of the partitioned circuit matrices iteratively. The reduction is typically done in frequency or s domain, where s is the complex frequency variable and defined as j w , where w is the radical frequency in complex domain analysis. In frequency domain analysis, storage elements such as capacitors and conductors all have their impedance written in s in frequency domain. For example, a capacitor with capacitance value 0.1 farad can be written as 0.1s in frequency domain as its impedance value.

2.2

Generalized Y-A Transformation

Another different approach to circuit complexity reduction is by means of local node reduction and realization of reduced networks based on local node elimination and realization [22,74,2,69,75,82]. The main idea is to reduce the number of nodes in the circuits and approximate the elements of the reduced system with either order-reduced rational functions or realized low order RLCM networks. The major advantage of these methods over projection-based methods is that the reduction can be done in a local manner and no overall solutions

Introduction

7

of the entire circuit are required, which makes these methods very amenable to attack large linear networks. This idea was first explored by selective node elimination for RC circuits [22, 741, where time constant analysis is used to select nodes for elimination. Generalized Y-A transformation [69,68], RLCK circuit crunching [2], and branch merging [75] have been developed based on nodal analysis, where inductance becomes susceptance in the admittance matrix. Generalized Y-A transformation provides a general node elimination based parasitic reduction technique [68]. A generalized block Y-A transformation based on modified nodal analysis formulation has been proposed [82, 831 recently, which leads to the general hierarchical model order reduction techniques and it can be applied to any linear circuits with any linear device. Both Generalized Y-A transformation and hierarchical model order reduction techniques will be discussed in detail in the following chapters. Both projection-based and node elimination based model order reduction methods can be viewed a special symbolic analysis where only the complex frequency variable is the symbol. In general, transfer functions are functions of s, which are called semi-symbolic analysis format from the perspective of symbolic analysis.

3.

Symbolic Analysis for Analog Circuit in a Nutshell

Research on symbolic analysis can be dated back to the last century. Developments in this field gained real momentum in 1950's when electric computers were introduced and used in circuit analysis. Methods developed from the 1950's to the 1980's can be basically categorized as: 1 Tree Enumeration methods, 2 Signal Flow Graph methods, 3 Parameter Extraction methods, 4 Numerical Interpolation methods and 5 Matrix-Determinant methods. The details of these method can be found in [38,53]. In the late 19803, symbolic analysis gains renewed interests as industrial demands for analog design automation increased. Various methods are proposed to solve the long-standing circuit-size problem. The strategies used in modern symbolic analyzers in general come in two categories: those based on hierarchical decompositions [41, 81,911 and those based on approximations [30,98, 107,42,107, 18,48,49,86].

8

3.1

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Topological Analysis

Symbolic analysis started with topological analysis [53]. The most two important algorithms are tree enumeration methods and signaljlow graph methods. Tree enumeration method is one of the oldest, fully symbolic analysis methods proposed in the last century when Kirchoff and Maxwell first stated their results on RLC networks, which include only resistance, inductance and capacitance, in their classical works. In this method, a passive RLC network is represented as an undirected weighted graph G ( N ,E ) , where N is the set of nodes in the network and E is the set of edges with each edge representing a circuit element between the nodes the edge connects. The weight of each edge is the admittance of the corresponding circuit element. The basic idea in this method is that the determinant of the node admittance of an RLC network equals the sum of all tree-admittance products of the graph G ( N ,E). A tree-admittance product is the product of all the edge weights in a spanning tree of the G ( N ,E ) . So network transfer function calculation amounts to enumerating spanning trees of the undirected weighted graph. Some transfer functions, such as trans-impedance or voltage gain, may require finding a 2-tree. A 2-tree is a pair of node-disjoint subgraphs that individually are connected, acyclic, and together include all nodes. The attractive feature of this method is that all the product terms generated are irreducible or term-cancellation free. For an active RLC-9, network (with voltage-controlled current source), however, the original tree enumeration method cannot be directly applied. Two extension methods were proposed to solve this problem. The first is 2-graph approach [60] and the second is directed-tree approach [ I l l . In the 2-graph approach, each admittance of RLC circuit element is treated as a voltagecontrolled current source (VCCS) with controlling and controlled nodes coinciding. Signal-flow graph based methods are based on the signal-flow diagrams [%I, which is a weighted, directed graph representing a set of linear equations, which can be expressed in the following general form:

'

where X is the vector formed by the n dependent node variables, U is the vector formed by the m independent node (source node) variables, and A and B are transmittance matrices constructed from the coefficients of the linear equations. Given a linear equation set in the form of (3.1), a signal flow graph can be constructed by the following rules: (1) Node weights represent variables (known 'Term cancellation is due to the fact that two symbolic terms with the same symbol combination but opposite signs cancel each other.

Introduction

9

or unknown). (2) Branch weights (transmittance) represent the coefficients in the relationships among node variables. (3) Each dependent node variable equals the sum of the products of the incoming branch weight and the node variable from which the branch originates. Any transfer function from an input variable xi to an output variable xi can be computed by Mason's rule [58] as follows:

where

A = 1 - (sum of all loop weights) + (sum of all second-order loop weights) - (sum of all third-order loop weights) + . . . , Pk = weight of the kth path from the source nodes x, to the dependent node xi

A, = sum of those terms in A without any constituent loops touching the path Pk. The nth-order loop is defined as the loop set formed by n non-touching loops. The weight of the nth order loop is the sum (over all possible loop sets) of the products of the branch weights in these n non-touching loops. Signal-flow graph method can be applied to various types (passive or active) of circuit networks, as the signal-flow graph is directly derived from linear equations and is independent of circuit formulations. This method, however, also suffers from the term-cancellation problem.

3.2

Determinant Decision Diagram

As we have introduced, symbolic analysis can be performed on topology of a given circuit, it can also be based on system matrix of the circuit. Determinant decision diagram belongs to the latter category. Determinant decision diagram is based on the two observations on symbolic analysis of large analog circuits: (a) the admittance matrix is sparse and (b) a symbolic expression often shares many sub-expressions. Under the assumption that all the matrix elements are distinct, each product term can be viewed as a subset of all the symbolic parameters. Therefore, a special data structure called Zero-suppressed Binary Decision Diagrams (ZBDDs) is adopted, which was introduced originally for representing sparse subset systems [61]. ZBDD is a variant of Binary Decision Diagram(BDD) introduced by Akers [I] and popularized by Bryant [4]. The decision graph based symbolic analysis method is inspired by the success of BDDs as an enabling technology for industrial use of symbolic analysis and formal verification in digital logic design [5]. This leads to a new graph

10

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

representation of a symbolic determinant, called Determinant Decision Diagram(DDD). As determinant is the building block of the explicit solution of any linear systems based on the Cramer's rule, a fully symbolic analysis of any linear system will become possible with the DDD graphs. DDD representation has several advantages over both the expanded and arbitrarily nested forms of a symbolic expression. First, similar to the nested form, DDD-graph representation is compact for a large class of analog circuits. A ladder-structured network can be represented by a diagram where the number of vertices in the diagram (called its size) is equal to the number of symbolic parameters. As indicated by the experiments, the size of DDD is usually dramatically smaller than the number of product terms. For example, 5.71 x lo2' terms can be represented by a diagram with 398 vertices [77]. Second, similar to the expanded form, DDD representation is canonical, i.e., every determinant has a unique representation, and is amenable to symbolic manipulation. The canonical property is critical to efficient symbolic analysis [62]. Finally, evaluation and manipulation of symbolic determinants (such as sensitivity calculation) have time complexity proportional to the DDD sizes. The formal definition of DDDs will be introduced in Chapter 9. Here we just use the example circuit in 1.1 to illustrate the basic idea of the DDD representation of a determinant. By using the nodal analysis, the simple RC circuit in Fig. 1.2 can be formu-

Figure 1.2. RC circuit for illustration of DDD

lated as

The 3 x 3 matrix is the admittance matrix that we are interested. We view each entry in the admittance matrix as one distinct symbol, and rewrite its system determinant in the left-hand side of Fig. 1.3. Then its DDD representation is shown in the right-hand side.

Introduction

0 edge

Figure 1.3. A matrix determinant and its DDD representation.

A DDD is directed acyclic graph and each non-terminal DDD vertex has two outgoing edges, called 1-edge and 0-edge. A 1-path in a DDD corresponds a product term in the original DDD, which is defined as a path from the root vertex (A in our example) to the 1-terminal including all symbolic symbols and signs of the vertices that originate all the 1-edges along the 1-path. In our example, there exist three 1-paths representing three product terms: ADG, - A F E and -CBG. The root vertex represents the sum of these product terms. Size of a DDD is the number of DDD vertices, denoted by I DDDI. DDD graph is also an ordered graph like Binary Decision Diagrams . This implies that the order of each symbol in any 1-path from (root vertex to 1terminal) is fixed with respect to other symbols. The ordering used in our example is A > C > B > D > F > E > G. Notice that the size of a DDD depends on the size of a circuit in a complicated way. Both circuit topology and vertex ordering have huge impacts on the DDD sizes. Given the best vertex ordering, if the underlying circuit is a ladder circuit, IDDDl is a linear function of the sizes of the circuit. For general circuits, the size of DDD graph may grow exponentially in the worse case. But like BDDs, with proper vertex ordering, the DDD representations are very compact for many real circuits [77, 781.

3.3

Symbolic Analysis of Nonlinear Circuits

For wireless/communication applications, a number of circuits which operate at radio frequencies (RF) typically exhibits so-called mildly or weakly nonlinear properties where devices typically have a fixed dc operating point and the inputs are ac signals. When the amplitude of these input signals is small (such that their operation points do not change too much), the nonlinearities in these

12

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

circuit can be approximated adequately Volterra functional series [71] in both time and frequency domains. Volterra functional series can represent a weakly nonlinear function in terms of a number of linear functions called Volterra kernels. From circuit theory's perspective, it leads to a set of linear circuits, called Volterra circuits, whose responses can adequately approximate the response of the original nonlinear circuit. Volterra function series based symbolic analysis has been explored in [97, 1001. Symbolic analysis of harmonic distortion in weakly nonlinear circuits was also reported by the same author in [loo]. Symbolic analysis based on DDD graph and Volterra series for transient and distortion analysis was proposed in [loll. Symbolic analysis for hard nonlinear analysis based on piecewise linear concept was reported in [57, 561, which is based on the ideal diode modeling of piecewise linear functions and solves the so-called complementary linear program (CLP) symbolically using complementary-decision diagrams. The new method can derive the symbolic expressions for the nonlinear circuit responses in time domain. But its modeling and simulation capacity is still limited due to limitation of exact DDD-graph based symbolic analysis [77].

4.

What's Covered in this Book

We start with review of the basics of circuit analysis methods in chapter 2. We discuss the nodal and modified nodal analysis formulation of RLC circuits and computation of their response in both time and frequency domains. We also review some of basic mathematic concepts in the symbolic analysis.

4.1

Symbolic Analysis in Digital Circuitry

Part I1 of the book focuses on the techniques for linear parasitic circuit reduction. The corresponding chapters are presented in Chapter 3 to Chapter 7. In Chapter 3 presents moment-based model order reduction technique for fast RLC linear circuit analysis. A realizable topological analysis based on local node elimination and first-order approximation will be discussed. Chapter 4 presents a generalized Y-A transformation to reduce the dynamic linear networks in frequency domain. The method finds the exact values of the low order coefficients of the numerator and denominator of the transfer function and thus matches part of the moments. Chapter 5 discusses in detail two major issues in the general Y-A transformation: common factors in fractional expressions and round-off numerical errors. The theoretical analysis and cancellations during the Y-A transformation are presented. Chapter 6 gives theoretical analysis of the stability of the reduced expressions from Y-A transformation via Ruth-Hurwitz Criterion. We make an effort to

Introduction

13

describe the proof of the Criterion because the details are omitted in most of the contemporary textbooks. Chapter 7 presents a template-based circuit realization technique to approximate the reduced expressions after the Y-A transformation.

4.2

Symbolic Analysis in Analog Circuitry

In Part I11 of this book, we discuss symbolic generation of the determinants and cofactors for the application to analog circuit analysis and designs. The corresponding chapters in this book are Chapter 8 to Chapter 12. We mainly present DDD-based symbolic analysis techniques as they represent the startof-the-art approaches to the symbolic analysis. Chapter 8 shows the relationships of circuit responses and circuit topologies, using the matrix approach. Because the topology-based circuit analysis method provides essential physical insights of circuits, a combination of it with model order reduction concepts raises special interest to researchers in layout-driven circuit reduction. Chapter 9 introduces the concept of determinant decision diagrams and their basic operations for symbolic analysis. A variable ordering heuristic is also presented and is shown to be optimal for ladder circuits. Chapter 10 introduces the concept of s-expanded determinant decision diagrams for symbolically representing s-expanded polynomials from a determinant. We show how s-expanded DDD can be constructed from complex DDDs and the variable ordering used for s-expanded DDDs. Chapter 11 presents several efficient algorithms for obtaining approximate symbolic expressions based DDD presentation of symbolic expressions. We show a dominant term of a determinant can be found by searching shortest paths in the DDD graphs. A incremental Ic shortest paths search scheme was developed, which can efficiently find Ic dominant product terms from DDD graphs presenting a determinant. Chapter 12 presents a general hierarchical model order reduction techniques, which is generalized Y-A transformation algorithms discussed in previous chapters. Some theoretical results regarding the term cancellation in the context of general hierarchical reduction are presented.

5.

Summary

In this section, we briefly review the concept of symbolic analysis and present the general formulation of symbolic analysis. Symbolic analysis has a long history and in a broad sense includes from classic topological based symbolic analysis methods to modern model order reduction techniques as frequency or s domain analysis can be viewed as a special symbolic analysis. We then briefly survey existing symbolic analysis

14

SYMBOLIC ANALYSIS AND REDUCTION OF VLSl CIRCUITS

and parasitic model order reduction methods reported in the past several years. We briefly review the generalized Y-A transformation and DDD graph-based symbolic analysis methods, which will be presented in detail in the following chapters. Analyzing circuits symbolically, however, still remains a challenging research issue. Instead of providing a solution of this field, we survey the recent advances in symbolic analysis in this book. Specifically, we will present the start of the art general Y-A transformation based parasitic reduction technique and DDD graph-based symbolic analysis methods. We hope those promising techniques will lead to more efficient modelin and analysis solutions to the current and future VLSI designs.

Chapter 2

BASICS OF CIRCUIT ANALYSIS

There has been striking progress in linear circuit reduction since the last two decades or so. Linear circuits that we will discuss throughout the book refer to parasitic RC and RLC circuits that represent interconnects on metal layers in modern ICs. As we are entering the very deep submicron era with the smallest CMOS transistor less than 65nm in width, interconnects start playing a significant role than ever before. Interconnects are important to designers in terms of timing, crosstalk, electro-migration, power, process variation, etc. Having stressed on the importance of interconnects, analyzing the effects caused by congested interconnects are still the bottleneck in state-of-the-art commercial EDA softwares. The reason is very simple: there are too many to analyze. A typical interconnect connecting two gates in one design module is about a few microns long. To accurately model the interconnect, a parasitic circuit with tens of RC or RLC segments shown in has to be used to model the interconnects' electrical characteristics. For all the RC and RLC circuits that we are interested, each node has one or more resistive path to others. It is an important assumption. All the reduction methods that will be introduced in this chapter take it as a prerequisite. This chapter reviews some, but not all, of the representative work that is well established in theory and widely used in circuit reduction and simulation. A trend in linear circuit reduction is that reduced circuits are preferably passive or realizable, so that they can be simulated in standard circuit simulators such as SPICE [63]. We start the chapter by introducing time and s domain analysis methods used in circuit simulation. Then we review linear circuit reduction techniques, which can be classified into three categories: moment-matching reduction via Pad6

16

SYMBOLIC ANALYSIS AND REDUCTION OF VLSl CIRCUITS

approximation, passive reduction, and realizable reduction, with each more sophisticated than the previous one.

1

Time Domain Analysis

In this section, we describe RC and RLC network analysis in time domain progressively in three steps. Our first step is to present an approach to analyzing RC circuits. And then the second step is to formulate RLC circuits with certain special structure. Our last step is to introduce the formulation of RLC circuits of general structure. Each of them begins with a simple example and are presented formally in matrix terminologies afterwards.

1.1

RC Interconnect Circuit Formulation

RC interconnect circuits can be formulated using nodal analysis formulation. Nodal analysis is a classical circuit analysis method based on Kirchhoff's Current ~ a w (KCL) ' and branch constitutive equations2. For a given RC linear circuit with n 1nodes, nodal analysis formulates the problem in the following two steps:

+

step 1. choose a ground or reference node, which usually is taken to be at a potential of zero volt. All other node voltages constitute n unknowns3; step 2. establish KCL equations for all the n nodes by representing branch currents in terms of node voltages using branch constitutive equations. Example 2.1. Refer to the RC tree in Fig. 2.1. In nodal analysis formulation of the circuit, we first determine the unknowns. Since vl is equal to v, which

Figure 2.1. A RC tree demonstrating nodal analysis formulation: current fbwing out of a node is equal to currents fbwing into the node

is the given input, we use node voltages vz,us,and ve as unknown variables to 'Kirchhoff's Current Law: for lumped circuits, the algebraic sum of the currents entering (leaving) a node is zero. 2~ branch constitutive equations are i-v relationships for circuit elements such as resistors, capacitors, inductors, dependent and controlled sources, etc. For example, the branch constitutiveequation for a resistor of value r is i = v/R. 3 ~ hne node voltages are independent because they linearly represent n independent voltage drops on tree trunks on any tree of the circuit.

Basics of Circuit Analysis

write the three KCL equations

or if we order the unknown variables on the right-hand side of the equations, we may have

The matrix form of the above three simultaneous equations would be

.

.

Note that we have put a minus sign outside the square matrix. Without loss of generality, we assume that the voltage drop and the current from @ to @ are two output variables that we are interestedj. e., i, ans v, are

As the reader can imagine, we can use some linear combination of the unknowns to obtain voltages between any two nodes or currents on any branch in the circuit. In (1.7), each row is derived from KCL for each node in Fig. 2.1. For example, the first equation states that the current flowing out of node @ through C1,i. e., CIG1,is equal to the currents flowing into the node through G , and G1,which are G,(v, - v2)and G1(v3- v2),respectively. In general, RC circuit formulation can be expressed as

where V denotes the n unknown nodal voltages in RC circuits. In (1.9), the matrices G E W x nand C E Xnxn represent the conductance and capacitance elements, respectively. Please note that matrix C may be singular, i. e., some rows in C may be zero. It happens when the corresponding node does not connect to any capacitor. It is

18

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

worth noting as well that the G matrix in (1.7) is non-singular if and only if the RC interconnect circuits meet the requirement that each node has one or more resistive path to some other nodes. Being a non-singular matrix is a necessary condition for the most linear reduction techniques.

1.2

RLC Interconnect Circuit Formulation

Formulation of a type of RLC circuits can be easily obtained by augmenting the RC formulation we have introduced. The RLC circuits in this class require that every inductor must be in series with a resistor. In fact when L is considered, the parasitics of an interconnect segment typically is modeled as a RLC branch as shown in Fig. 2.2. The branch constitutive equation of L in Fig. 2.2 is given

Figure 2.2. RLC parasitics of a segment of interconnect on metal layers:(a) illustration of orthogonal interconnect layers (b) RLC parasitic model of an interconnect segment in layer 3.

by

v1( t )- v z ( t )= ~ i L ( t ) ,

where vl ( t )and v2(t)are the two nodal voltages of the inductor. The formulation method that we described for RC circuits can be used to formulate RLC circuits with minor modifications. We have known that each row in the formulation is constituted by KCL. KCL equations are established in terms of nodal voltages and their derivatives as unknowns. If we want to keep the formulation, i L( t )has to be represented with nodal voltages. In general, i L ( t )can be calculated by

This integral equation, however, is apparently not a fit to our RC formulations because only nodal voltages and their derivatives can be used as unknowns. Fortunately, provided that the inductor is in series with a resistor in our RLC circuits, i L ( t )is equal to the current flowing through the resistor as well, i.e.,

19

Basics of Circuit Analysis

where v o ( t )and v l ( t ) are the two nodal voltages of the resistor. Therefore, insert (1.13) into (1.1I), we can rewrite (1.11) into the form of

v1( t )- v, ( t )

=

LL( t )

=

LG (iro(t)- irl ( t ) ).

(1.14)

Essentially we have used the nodal voltages of the resistor to represent the current of the inductor. RLC circuit formulation can be augmented based on RC formulation as follows:

step 1. choose a ground or reference node, which usually is taken to be at a potential of zero volt. All other node voltages constitute n unknowns; step 2. establish KCL equations for all the inter-branch nodes (those on the joints of branches) by representing branch currents in terms of node voltages using branch constitutive equations. For branch that is an inductor; use (1.13) to represent the current in the inductor: step 3. establish (1.14) for all intra-branch nodes (those inside branches between resistors and inductors). Example 2.2. We change the circuit in Fig. 2.1 to the one in Fig. 2.3 by adding two inductors L1 and L2 in series with G1 and G2,respectively. This circuit structure meets our requirement: L1 is in series with G I , and Lz is in series with G2.

Figure 2.3. RLC circuit meeting the two prerequisites. Shaded ones are the so-called intrabranch nodes

The circuit can be formulated as (1.15). The first three equations are established based on Step 2. While the last two are based on Step 3. In terms of nodes, the first three rows are derived from KCL for three inter-branch nodes. The last two rows are modified branch constitutive equations (1.14) for two

20

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

intra-branch nodes.

Letting the branch current and voltage of La be the outputs, we have

In general, RLC circuit formulation can be expressed as

Similar to the RC formulation, V denotes the n unknown nodal voltages in RLC circuits, and matrices G E X n x n and C E X n x n represent the conductance and capacitance elements. In addition, the two matrices contain other elements such as 1 and GL due to the introduction of modified branch constitutive equations (1.14). Same as the RC formulation, matrix C may be singular. We assume that this will not happen in RLC circuits throughout our discussion. The same assumption for RC circuits applies to the RLC circuits to ensure that matrix G is non-singular.

1.3

General RLC Interconnect Circuit Formulation

For more general RLC circuits of which our assumption to the topology of L does not hold, a more general formulation is needed. Modified nodal analysis is yet another classical circuit formulation method which improves nodal analysis method by adding currents in inductors as unknown variables. The introduction of the inductance current variables would help keep modified nodal analysis formulation in the differential form.

Basics of Circuit Analysis

For example, the branch constitutive equation of an inductor is

where L is the inductance value. If we had to use nodal analysis, in the KCL equations involving the inductor, iL has to be represented in terms of V L ,i. e., i~ = v ~ d t i ( t o ) .While in the modified version, introducing i L into the unknowns would keep the KCL equations in the differential form. The cost, however, is an additional equation (1.19). Our general RLC circuit formulation can take one step further from modified nodal analysis, additional inductance current variables can be removed from the formulation by block Gauss elimination. However, this can be done only in s domain.

Lt

+

step 1. choose a ground or reference node, which usually is taken to be at a potential of zero volt. All other node voltages constitute n unknowns; step 2. create a current variable for each inductor with certain direction defined; step 3. establish KCL equations for all the n nodes by representing branch currents of RC elements in terms of node voltages and current variables pre-defined in step 2; step 4. establish the branch constitutive equation of inductance in differential form of (1.19) using pre-defined current and nodal voltage variables; step 5 (optional). remove current variables using block Gauss elimination in s domain. Step are the procedure of modified nodal analysis on general RLC circuits. Step 5 is the post-procedure for removal of current variables.

Example 2.3. Fig. 2.4 shows an RLC circuit with a mutual inductance M between L1 and L2. Note that L2 in the circuit does not meet our assumption in 1.2, i. e., it does not run in series with any resistor. In order to formulate the circuit using modified nodal analysis, i l and i2 are two current variables in addition to the four nodal voltages. The modified nodal

SYMBOLIC ANALYSIS AND REDUCTION OF VLSl CIRCUITS

Figure 2.4. A RLC tree demonstrating modifi ed nodal analysis formulation.

analysis formulation of the circuit is given by

Let V6 be the output voltage; then we have

In (1.20), the first four rows are derived from KCL for the five circled nodes. The last two rows are branch constitutive equations of the two inductors and the mutual one, which are added because of the two extra variables, il and i2. In general, modified nodal analysis formulation can be expressed as

MR(t)= -Gx(t) y(t) = Qx(t)

+Pu(t)

(1.22)

(1.23)

Basics of Circuit Analysis

where

where V and I are the modified nodal analysis variables (yielding a total number of n unknowns in (1.22)) corresponding to the node voltages and the branch currents for floating voltage sources and inductors. In (1.22), the matrices G E Xnxnand M E X n x nrepresent the conductance and susceptance matrices (except that the rows corresponding to the current variables are negated). In (1.24), C and L are generally capacitance and inductance matrices of the circuit. However, please note that C may be singular, i. e., some rows in C may be zero. It happens when the corresponding node does not connect to any capacitor. Similarly, L may be singular too, and it happens when the corresponding branch is a floating voltage source. To go one step further to remove the extra variables in s domain, (1.21) can be symbolically represented by

Using block Gauss elimination,

I can

be first written as

Replace I in (1.26) with (1.27),

1.4

Remarks

We reviewed three kinds of circuit analysis approaches: 1) RC formulation, 2) RLC formulation, and 3) general RLC formulation. The first one, also known as nodal analysis, is widely used in circuit simulation tools such as SPICE[63] for its robustness and simplicity in implementation. The second formulation method is augmented based on the RC formulation and it is different from the well-known modified nodal analysis, for it does not introduce current variables into the formulation. Therefore, our RLC formulation is more compact, and has the nice property that it guarantees the non-singularity of matrix M in (1.22) under certain assumptions. The last one is to be used on general RLC circuits which may also contain mutual inductance. Further simplification can be done to reduce the matrix size in s domain.

24

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

In the next subsection, we will give a closed form for circuit responses to

RC and RLC formulations that we have introduced. In some ill cases, matrix M in (1.22) may be singular. When it happens, the closed form solution will not be available. Therefore we reiterate our assumptions to the RC and RLC circuits of our interest: when an inductor is present in circuits, there has to be a series resistor with it; each inter-node has a coupling or ground capacitor. Under these assumptions, M is non-singular.

2. Responses in Time Domain 2.1 Responses in Closed Form Before proceeding to s domain analysis, we discuss the time domain solution of linear networks derived from RC and RLC formulations in the previous subsection. Let us pre-multiply matrix M-l on both sides of (1.22); then we have

where A r -M-lG and B can be written as

= M-l

P. Pre-multiply e-At on both sides, (2.1)

The solution to the above differential equation is the time-domain response on circuit nodes:

x(t)= xo +

lo t

eA(t-T)B u ( r ) d r

(2.3)

where xo is the initial condition, i. e., xo = x(t)lt=to. The output response in time domain is derived from (2.3) by pre-multiplying matrix Q:

~ ( t=)Q x ( t ) = Q x O+ Q

t

Lo

e A ( t - T ) ~ ~d(rr )

(2.4)

The first term is the output at time t = to. The second term is the convolution of the impulse response and the input waveform. The result can be verified by Laplace and inverse Laplace transformations.

2.2

Taylor Expansion in Time Domain

The matrix exponential eAt is defined by Taylor expansion:

25

Basics of Circuit Analysis

Therefore, the solution (2.3), with to = 0 without losing any generality, can be rewritten as:

If we approximate x ( t ) by first lc terms:

Define

Therefore, k-1

~ ( t=)xo

+ E [ a i x i ( t ) .]

(2.10)

i=O

We can get all the ai by lc Matrix-Vector multiplications. If the matrix is in Harwell-Boeing Format, the complexity of Matrix-Vector multiplication grows linearly with the number of non-zero elements in Matrix. The evaluation of xi(t)needs to take the source vector U ( t ) into account. For a vector of constant sources, u(t)= C Y ,

For a vector of linear sources, u ( t ) = at,

Sources with classical waveforms, such as exponential or sinusoidal function, have also closed form representation of (2.10). Some sources, on the other hand, are combinations of different ones mentioned above. One of its kind is piecewise linear voltage or current source, which is a combination of a series of timed

26

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

ramp inputs. Because system analyzed here is a linear network, if system has different kinds of source, we can calculate x i ( t )for each independent source alone and sum the response together. Please note that ai and bi have no relation to source u ( t ) and time t , thus ai and bi need to be computed only once. For each interested time point t , calculate the x i ( t ) ,substitute into (2.10), we can get the result value. The choice of k will greatly affect the accuracy of this method. For a given error tolerance, we want to find out the smallest k that satisfies the accuracy requirement. Since the value of u ( t )is bounded in real circuit(e. g., less than 5V), We consider u ( t )is constant a. Substitute (2.11) into (2.10), local truncation error L T E can be approximated as:

(11

00

LTE 2

A

i=k

11) ; II Ba II ti+l (i + I)!

#

must be Here 11 . 11 is 1-norm(l1 . 11 or m-norm(/l . 11), of matrix. smaller than 1,otherwise the local truncation error does not converge. Because 11 A 11 is a fixed value for a given circuit, k and t can be adjusted mutually to satisfy the convergence condition. Specifically, if t is equal to T, the time point when circuit response is desired, then k has to be large enough such that k 2 is greater than 11 A 11 T. On the other hand, if k is set to a fixed value, e. g., 100, T may have to be time stepped such that individual time step t is small enough to make 11 A 11 t smaller than k 2. In summary, the smaller t is, the smaller k could be. For a given time point T , the absolute truncation error A T E = $ LTE, i. e.,

+

+

ATE


2). Suppose a network has n ports, then the S-parameters of the network will be a n x n matrix. According to the definition,

we connect all ports by resistors whose resistance are equal to their respective characteristic impedances, which makes ar, = 0 for k = 1,2,. . . ,n. Then set initial incident wave at port j be unity, i. e., a j = 1, and measure reflective waves at all port bi for i = 1,2, . . . , n. From above definition, we have Sij = bi. In this way, we will measure all the S-parameters of the network.

56

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

So far, we have introduced S-parameters and admittance matrix (Y -parameters) of linear multi-port networks. Note that we have used different sets of independent and dependent variables for the two kinds of parameters5, However, all parameter sets contain the same information about a network, and it is always possible to calculate any set in term of any other set. For example, S-parameters can be written in terms of Y-parameters as S(s) = ( I

+ Y ) - ~ ( I - Y).

(3.29)

And alternatively, Y-parameters can be represented by S-parameters:

+

Y(s) = (I s ) - ~ ( I - S ) .

(3.30)

3.3.2 Scattering-Parameter-BasedReduction We would derive the reduction merely based on S-matrix first. And we will explain the result using the original multi-port network on which the S-matrix is defined. Let us start with the most general case in (3.31), where each entry in the S-parameter matrix is a symbol (full matrix). We want to eliminate two independent variable a1 and a2 using Gauss elimination.

From the first equation of (3.31),

Replace a1 using the above equation, the last n - 1equations in (3.31) can be rewritten as

w e have used incident waves and re&ctive waves as independent and dependent variables in S-parameters, and nodal voltages and branch currents as independent and dependent variables in Y -parameters, respectively.

57

Model-Order Reduction

Now we go through another similar iteration to eliminate a2 in (3.33); we

where

and

In (3.35), although the matrix size has be reduced by 2, & is still related to bl and b2. As bl and b2 are used to represent a1 and a2, it is impossible to eliminate a1 and a2 without introducing bl and b2 into the reduced system, except that bl and b2 are zero. We can continue the elimination process to further reduce the size of Smatrix. But let us stop here and turn to look at the physical meaning of eliminating two nodes in S-matrix from the circuit point of view. The network reduction problem based on S-parameters can be defined as follows: given a linear distributed-lumped network, find a multiport representation of the network as illustrated by Fig. 3.11, where the multiport is characterized by its S-matrix. All nodes in the network are internal to the multiport except the node connected to the driving source ( n l )and the loads of interest (n2through n,). These external nodes are specified by the user.

Figure 3.11. A multiport representation

To obtain such a multiport representation with m external ports from an arbitrary distributed-lumped network of n original nodes, the network is reduced

58

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

by merging the nodes into the rnultiport one at a time while keeping all user specified nodes external. There are two basic reduction rules: Adjoined Merging Rule:

Figure 3.12. Merge the two networks denoted by X,,, nected nodes nx, and ny, .

and Y,,,

at two perfectly intercon-

Let X and Y be two multiport network in Fig. 3.12. If the two networks share the same ground, but are not connected at n x l and ny,, the S-matrix for the two networks are given by

in which, a b

-

=

T

[axl ax2

...

[bxl bx2

. . . bxm byl by2 . . . by,IT,

ax,

S.. 23 = 0 if ni E X and

ayl ay2

nj E

Y.

...

ay,]

, (3.38)

Now if the two networks are perfectly interconnected at nxl and ny,, then the voltages at the two nodes are equal; and for the central node in between, KCL holds. Therefore, besides (3.37), we have two additional equations, i. e.,

59

Model-Order Reduction

because nxl and nyl are actually the same node, so Zxl = Zyl. Insert (3.41) into (3.37) by replacing bxl and bxl, we have

where

rn

T

bX2 ... bXm by2 ... byn] . Note that in (3.42 only boxed entries are changed. Comparing (3.31) with the above equation, if we eliminate nxl and ny,, it is equivalent to eliminate the two rows with -1 in (3.42). Because of some special values (e. g., 0,-1) in the above equation, we could rewrite (3.35) and (3.36), b'

Note that (3.43) is derived because of the two zeros in the left column in (3.42). Self Merging Rule: Let X be an m-port network with a self loop connected to nxl and nx2 in X (see Fig. 3.13). The only difference of the self-merging scenario from adjoined-merging is that the equation (3.38) can not be applied in self-merging rule. However, (3.41) still holds when Yl is replaced by X2. i. e.,

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 3.13. Illustration of self merging

Therefore, if we eliminate the first two rows from the above system, then the entries are given by

where (3.49) A = sxlx, sxzxz - ((Sx1x2 - 1) (Sxzxl - 1)). Given an arbitrary distributed-lumped network, let En be the set of external n nodes. The network reduction process begins with merging all internal components by repeatedly utilizing the adjoined merging rule for all the nodes n i that does not belong to En. The self merging rule is applied to eliminate all the self loops introduced by the adjoined merging process. Finally, an n-port network characterized by its scattering parameters is derived. Note that the S-parameters are approximated by their lower order moments. 3.3.3 Getting 'lkansfer Functions Once we have obtained the reduced S-matrix, we can use (3.25) and (3.27) to covert ai and bi into port voltages and currents. Thus, we can use various combinations of them to get any transfer function of interest. Once the transfer function is obtained, the Pad6 approximation method introduced before can be used to analyze the system.

3.3.4 Remarks S-parameter based macro model of distributed-lumped networks was first introduced by Liao[51]. The S-parameter based macromodel is flexible that the accuracy of the model can be controlled by adjusting the order of approximation. However, it uses Pad6 approximation to obtain macromodels. Later

Model-Order Reduction

61

on, Liao proposed a realizable reduction method[50] based on S-parameters. Yet the method is only applicable to RC circuits only, and realizable circuit is first order only. Another limitation of the proposed macromodel method is that scattering parameters are used only as an intermediate result, as the given distributed-lumped networks and desired transfer functions (macromodels) are all in Laplace transform. Therefore, it is apparently more preferable to use Laplace transforms directly. Generalized Y-A transformation is just one such method (Chapter 4).

4.

Summary

In this chapter, we first laid the foundation for linear circuit simulation and reduction --basics of circuit analysis in time domain and s-domain. We then presented two state-of-the-art research directions in linear reduction area: explicit moment-matching method with Pad6 approximation and realizable topological reduction methods. The two directions have their advantages and limitations. Nowadays, these the methods are all implemented and widely used to solve real industry designs. And their limitations, however, are the motivations of the research in this thesis -generalized Y-A transformation.

Chapter 4

GENERALIZED Y-A TRANSFORMATION FUNDAMENTAL THEORY

In the previous part of this thesis, we have equipped ourselves with all the elements necessary to further investigate the problem, which is the topic of the remaining of the thesis: linear model order reduction using generalized Y-A transformation. Particularly, we have been familiar with various state-of-the-art methodologies. In Chapter 3, we have seen analysis methods in both time and s domains. Particularly in s domain, the moment-matching technique proposed by Pillage [66] has been used widely to approximate waveforms of a linear interconnect network by matching lower order moments with Pad6 approximation. As each moment can be computed in linear time after an one-time LU factorization, the algorithm runs very efficiently. However, it is well known that Pad6 approximation may generate undesired positive poles. To overcome the drawback, [74] [102][51][50] proposed a series of stable and realizable reduction methods. But they have different levels of limitation on either the reducible circuit topology or the types of reducible elements. In another aspect, topological analysis introduced in Chapter 8 is an approach to calculating driving-point admittances using Cramer's rule in s-domain. The determinant of an admittance matrix of a passive network without mutual inductances is equal to the sum of all the tree admittance products of the network. The advantage of topological analysis formula over conventional methods evaluating determinants is that it avoids the usual cancelations inherent in the expansion of determinants in the latter. But enumerating all the trees in a large network is impractical. Recently Ismai1[43] proposes a direct transfer-function truncation method to approximate transfer functions in tree-structured RCL networks in s-domain. The transfer functions are kept in rational expressions in s , and an approximation is acquired by directly truncating high-order terms. Such an approximation

64

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

also matches low-order time moments implicitly, but truncated characteristic denominator may not be stable any more. The method is able to obtain very high-order transfer functions, when AWE fails because of numerical problems.

1.

Introduction

We have proposed a new model order reduction method based on Y-A transformation [69,68] for general RCLK-VJ linear networks. In this approach, we classify nodes in a network into two categories: 1 external nodes: nodes where responses are of interest;

2 internal nodes: all other nodes in the network. The principal idea is that, given a linear network, we perform Y-A transformation on every internal node, until all such nodes are eliminated. Note that the more the external nodes are specified, the sooner the algorithm terminates. After each transformation, any admittance of order higher than user-specified threshold P will be truncated. For example, suppose

is an admittance after a Y-A transformation, the truncation with respect to ,6 would result in a Pth-order admittance

which is an approximation to the exact admittance in (1.1). Different from topological analysis and other traditional symbolic analysis, the approach keeps Y-A admittances of order 5 0. All higher-order terms are discarded. The terms kept, however, are precisely the first ,B 1terms in exact admittances. The main contributions are:

+

1 Y-A admittances are kept in the original rational forms of s , but their orders are reduced to no more than P. In Y-A admittances, all coefficients of powers of s agree with those in exact admittances up to the order p ;

+

2 First p 1 time moments of exact admittances are matched implicitly by truncated Y-A admittances, including the 0th moment mo;

3 Two kinds of common-factor effects are first discovered in Y-A transformation. The findings lead to essential numerical improvement in traditional Y-A transformation, and hence more accurate polelzero approximation;

Generalized Y-ATransformation -Fundamental

Theory

65

4 A Hurwitz polynomial approximation method is employed to treat transfer functions from truncated Y-A admittances, so that stable reduced transfer functions are guaranteed.

5 The proposed algorithm is more general than DTT method [43], as it handles linear networks in arbitrary topology with currentlvoltage sources and inductive K elements proposed by Devgan [20]. 6 A Geometric-Programming optimized circuit reduction methodology is proposed based on Y-A reduction method. This methodology is more general than other realizable approaches in terms of the reducible circuit topology and the types of reducible elements. The remaining of the thesis is organized as follows. In this chapter, we first briefly review the traditional Y-A transformation. Then we generalize the idea from different aspects in order to suit linear reduction needs. The overall reduction flow will be the summary in the end. Chapter-wise, advanced topics related to the generalized Y-Atransformation is presented in Chapter 5. This includes common-factor cancelations, treating round-off errors, etc. In Chapter 6, we present the Hurwitz polynomial approximation method. Chapter 7 shows our yet another application: realizable parasitic reduction.

2. Classical Y-A Transformation 2.1 Numerical Example

Figure 4.I. A numerical example on Y-A transformation: (a) before the transformation; (b)after the transformation.

For the two circuits (a) and (b) depicted in Fig. 4.1, they are equivalent at three ports: nl-n2, nl-ng, and n2-ng. This can be shown using Y-A transformation. In (a), no is adjacent to nl, n2, and ng. Kirchhoff's Current Law (KCL)

66

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

equations for node no, nl, n2, and n3 can be established as follows:

where Vothrough V3are voltages at nodes no through n3, respectively. From (2.1), we can denote Voin terms of Vl,V2,and V3as:

Inserting (2.5) into (2.2)-(2.4) yields

Considering (2.6)-(2.8) as KCL equations for nl, na, and n3 in Fig. 4.l(b), respectively, we can find out values for admittances in the circuit:

2.2

Y-A Transformation and Gauss Elimination

Y-A transformation shown in the example is equivalent to Gauss elimination on the system equations(2.1)-(2.4), in which (2.1) is used to eliminate Voin (2.2)-(2.4). However, with the formulae we will derive in Section 3, we will see that we do not need to establish system equations in Y-A transformation as we did in this example. It is worth noting that we may only need to perform an incomplete symbolic1 LU factorization, because the transformation terminates earlier if more than two external nodes are specified. The symbolic LU factorization is not even full-fledged, in the sense that we always chop off a high-order term in Y-A admittances when the power of s in this term is larger than P, a given threshold. All the coefficients of powers of s in truncated Y-A admittances, however, agree 'The symbol is s in Laplace transforms.

67

Generalized Y - A Transformation -Fundamental Theory

with those obtained using full-fledged symbolic computation, up to the order

p. Polynomial long division suggests us that first ,O + 1 time moments of the Y-A admittances are precisely matched with the exact admittance.

2.3

Notations and Terminologies to be Used

We would like to summarize the notations and conventions we are going to use throughout the book before we continue. A current source is said to bejoating when it flows from one non-datum node to another non-datum node. Decoupling it is to remove the current source, and insert two concatenated ones of the same amount of current between the two end-nodes. They are concatenated at the ground node. Through this equivalent source transformation, current sources become grounded and associated with nodes but not branches, which makes our algorithm simpler. Similarly, voltage sources can be transformed to current sources and decoupled if necessary. For a given linear network: w

nk is denoted as the k-th labeled node, where k starts from 0. Nodes are eliminated in the order labeled;

w

when the k-th node is eliminated, the network will be updated accordingly. We label the network (graph) before the elimination as G k(Vk, Ek), and the network (graph) afer as G ~ +(IV ~ + IEk+l); ,

w

(k) the admittance of (ni ,ni)(k), (ni, nj)(" is the branch between ni and n j , Y,.i (k) (k) Ii the current source impinging on ni, and ri the neighbor set of ni. Here superscript (k) stands for "in graph Gk";

The first neighbor of nk in G(') is the node in);?I w

3.

with the smallest label;

When it is not ambiguous, superscripts will be ignored, i.e., (ni, n j ) represents the branch between node n i and n j , Y , the admittance of branch (ni, nj), and Ii the decoupled current source impinging on node n i in the graph in the context.

Generalized Y-A Reduction

The traditional Y-A transformation is generalized in this paper in the following four aspects: 1 RCL, and especially Mutual K elements are integrated in the transformation through a simple conversion, so that circuits with mutual inductances can be handled as well. 2 CurrentNoltage sources are handled together with admittances in Y-A transformation.

68

SYMBOLIC ANALYSIS AND REDUCTION OF VLSZ CIRCUITS

3 Since many nodes will be eliminated in a general circuit using the transformation, the importance of the order of picking the nodes is studied and treated. The first three points are so important that we dedicate Section 1 and 4 to them. In the next sub-section, we illustrate the conversion of mutual K elements to self K elements. And present the general Y-A transformation formulae at the last sub-section. For the sake of simplicity in our presentation, we assume that all storage elements here have no initial conditions. Initial conditions can be simply modeled in s-domain as constant current or voltage sources.

3.1

Branch with RCLK Elements

Resistors(R), capacitors(C), and self inductors(L) can be handled easily in Y-A transformation. Circuit in Section 2.1 is such an example. This is because RCL elements have well-known admittance forms in s-domain. Mutual inductors, on the contrary have no simple admittance form. Because the branch voltage v, of a mutual inductor may be dependent of current variations of multiple branches other than itself

Including mutual inductors is difficult, because we are not able to eliminate a node if one of its incident branch inductively couples with more than one branch. Alternatively, we use K elements. With K elements, inductive coupling is modeled such that branch current can be written in terms of multiple coupling branch voltages. (14) of [44] gives the branch equation for a self K element

where v and i are voltage and current of the same branch. v-i relationship of a mutual K element is given by

di, --

dt '

where vl ,212, . . are branch voltages. In s-domain (3.1) can be written as:

Klx K2, -vl+-v2+...= S S

I,.

A circuit conversion on mutual K elements will allow us to integrate them into our transformation formulae. In Fig. 4.2(a), the KCL equations for the four

Generalized Y-ATransformation -Fundamental

Theory

Figure 4.2. Conversion on mutual K in s-domain: (a)given mutual K element; (b) converted self K elements.

nodes in terms of Vl and V2 can be written as

One can check that the KCL equations for the four nodes in Fig. 4.2(b) are exactly the same as (3.3), so that (b) is equivalent to (a). However, (b) has only self-K elements. Although some values in (b) are negative, the circuit is still passive because K-based method guarantees the extracted K matrix to be positive definite

70

3.2

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Branches with Current and Voltage Sources

Branches involved in Y-A transformation can not only include resistors, capacitors and self inductors, but also current/voltage sources and mutual inductors. We will give the Y-A transformation formula for circuits with current and voltage sources in this sub-section, and K elements in the next sub-section. Following the similar procedure in Section 2.1, we apply Y-A transformation to node no in Fig. 4.3(a),

Figure 4.3. Y-A transformation with current source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

and And performing Y-A transformation to node no in Fig. 4.4(a) gives

Figure 4.4. Y - A transformation with voltage source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

Generalized Y-A Transformation -Fundamental Theory

71

One can also derive (3.4) and (3.5) from Norton's theorem. A generalization of the two transformation formulas will be given in Theorem 4.1.

3.3

RCLK-VJ Generalized Formulae for Y-A Transformation

The generalized Y-A transformation formulae cover linear resistors, capacitors, self inductors and K elements, and currentlvoltage sources (RCLK-VL). (k) Theorem 4.1. Suppose nk is the node being eliminated. Vni,nj E rl, , (ni,nj)("') E Ek+1 in GkS1afer nk is eliminated. And the admittance Y.!'C+') is calculated as 23

where

For admittances and current sources not mentioned above, they will be inherited by Gk+l from GkTh. 4.1 can be proven by the analysis used in the example in Section 2. The theorem states that when we perform Y-A transformation on n k , neighbors of n k in Gk will become pairwise adjacent in Gk+l. In practice, we calculate Y('e+') in (3.6) up to the term of order ,B only. Since computation of higher23 order terms is skipped, we get an approximation of

Y,!,!") whose numerator -.,

and denominator are equal to the first ,B terms in Y$+')'s numerator and denominator, respectively. I!"') in (3.8) is calculated in the same way. Th. 4.1 does not cover voltage sources, because they can be changed to current sources via source transformation before any elimination begins. It is worth noting from Th. 4.1, that in Y-A transformation, coefficients of admittance are derived directly from admittance in original circuits and are kept in its original rational form. Stable reduced-order models can be derived from

72

SYMBOLIC ANALYSIS AND REDUCTION OF VLSZ CIRCUITS

low-order truncated admittances using Hurwitz polynomial approximation in Section 6. Corollary 4.1. Ifall RLC elements in a linear network are positive, Y$+') (3.6)is a rational function of s

in

and up, bq in (3.9) are non-negative. Corollary. 4.1 holds immediately due to (3.6) in Th. 4.1.

3.4

Higher-Order Truncation

Generally speaking, input admittance of any two nodes in a non-degenerated network (no loop capacitors or cut-set inductors) with n lumped capacitors andlor inductors and any amount of resistors is a n-th rational function of s. Even though n could be huge, we only need to keep coefficients of Y$)'s lower-order terms, i.e., ai and bj in (3.9). Th. 4.2 assures us that for any Y-A admittance $), keeping coefficients of powers of s 5 P in its numerator and denominator throughout the whole reduction process will make the final Y-A admittance be a P-th order truncation of the exact admittance. With no loss of generality, let us refer to (3.7). We assume that ? and Y are admittances from Y-A transformation with and without truncation, respectively. When n k is to be eliminated, a newly Y-A admittance can be computed as

Here YijI@) is in the form

and