Switched Inductor Power IC Design 3030958981, 9783030958985

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Gabriel Alfonso Rincón-Mora

Switched Inductor Power IC Design

Switched Inductor Power IC Design

Gabriel Alfonso Rincón-Mora

Switched Inductor Power IC Design

Gabriel Alfonso Rincón-Mora School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA, USA

ISBN 978-3-030-95898-5 ISBN 978-3-030-95899-2 https://doi.org/10.1007/978-3-030-95899-2

(eBook)

# The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

To Mami and Papi Minyusita

v

Summary

The aim of this textbook is to show and illustrate with insight, analysis, examples, and simulations how to design switched-inductor dc–dc power supplies. The book adopts a ground-up approach, from devices to systems. Chapters 1 and 2 are on diodes and transistors, Chaps. 3 and 4 on power transfer and delivery, Chaps. 5 and 6 on frequency response and feedback control, and Chaps. 7 and 8 on system composition and architecture. The emphasis throughout is on design. Chapter 1 reviews how PN, Zener, and Schottky diodes and bipolar-junction transistors (BJTs) block and conduct current. It starts with how solids and semiconductors behave and how adding impurity dopant atoms alters their behavior. With these concepts in hand, the material then details the operating modalities, characteristics, and response of PN and metal–semiconductor junction diodes and BJTs, including electrostatic behavior, band diagrams, current–voltage translations, capacitances, recovery times, breakdown mechanisms, structural variations, and more. Chapter 2 reviews how junction and metal–oxide–semiconductor (MOS) fieldeffect transistors (FETs) block and conduct current. It describes how MOSFETs accumulate, deplete, and invert their channels and how they saturate their currents in cut off, sub-threshold, and inversion. It also discusses body effect, weak inversion, how gate–channel oxide capacitance distributes across operating regions, and shortchannel effects, like drain-induced barrier lowering (DIBL), surface scattering, hot-electron injection, oxide-surface ejections, velocity saturation, and impact ionization and avalanche. Discussions extend to varactors, MOS diodes, lightly doped drains (LDD), diffused-channel MOSFETs (DMOS), junction isolation, substrate MOSFETs, welled MOSFETs, and electronic and systemic noise coupling and injection. Chapter 3 explains how inductors and transformers work and how switching power supplies use them to transfer power. It discusses the applications that demand these switched inductors and the steps and precautions taken when implementing them with complementary MOS (CMOS) integrated circuits (ICs). It also describes how ideal, asynchronous, and synchronous buck–boost, buck, boost, and flyback dc–dc converters operate and how their voltages, currents, duty cycles, and conduction modes relate.

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viii

Summary

Chapter 4 details how switched-inductor power supplies consume power that is otherwise intended for the output. It discusses the significance of these power losses in voltage regulators, battery chargers, and energy harvesters and the mechanics that govern them. The material explains and quantifies how resistances, diodes, transistors, and gate drivers burn Ohmic, dead-time, current–voltage overlap, and gate-charge power in continuous and discontinuous conduction. Concepts discussed include power-conversion efficiency, fractional losses, maximum-power point, the power theorem, reverse recovery, soft switching, and so on. This chapter also shows how to use these concepts to design power switches and gate drivers and how losses ultimately alter, dominate, and peak conversion efficiency. Chapter 5 describes how switched-inductor power supplies react and respond across frequency to dynamic fluctuations. It explains the guiding principles that govern two-port models to ultimately show how switched inductors reduce to simple current- and voltage-sourced networks. The chapter also shows how couple, shunt, and bypass capacitors and inductors respond individually and collectively with and without current- and voltage-limiting resistances. With this insight, deriving the frequency response of loaded bucks, boosts, buck–boosts, and flybacks in continuous and discontinuous conduction is more insightful and easier to comprehend and apply. Along the way, this chapter introduces and explains capacitor and inductor poles, in- and out-of-phase left- and right-half-plane zeros, reversal poles and zeros, transitional LC frequency, LC quality and gain, peaking and damping effects, and other relevant concepts that help describe switched LC networks. Chapter 6 shows how to control and stabilize switched-inductor power supplies. It explains how inverting feedback loops mix, sample, and translate signals across the loop, how they respond across frequency, and how pre-amplifiers, parallel paths, and embedded loops alter their response. This chapter also discusses how powersupply systems use operational amplifiers (op amps) and operational transconductance amplifiers (OTAs) to stabilize feedback systems. With this understanding and insight in hand, the chapter explains how analog and digital, voltageand current-mode, and voltage and current controllers manage and stabilize switched inductors in continuous and discontinuous conduction. Along the way, it introduces and reviews phase and gain margins, gain–bandwidth product, unity-gain projections, stabilization strategies (Types I, II, and III: dominant pole, pole–zero pair, and pole–zero–zero triplet), non-inverting and inverting feedback and mixed op-amp translations, inherent stability, digital gain and bandwidth, limit cycling, and other relevant concepts that help describe, quantify, and assess feedback controllers. Chapter 7 explains how feedback loops control switched-inductor power supplies. It describes how pulse-width-modulated (PWM), hysteretic, and constant-time peak/valley loops switch the inductor, offset the current or voltage they control, and respond to fast input or output variations. It also illustrates how summing comparators can contract control loops and remove the loading effect that current-mode voltage loops normally exhibit. The chapter ends with compact, fast, and low-cost resistive, filtered, and voltage-mode voltage-looped (voltage-squared) bucks. Along the way, the material introduces and reviews comparators, hysteretic

Summary

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comparators, summing comparators, pulse-width modulators, set–reset (SR) flip flops, pulse generators, sub-harmonic oscillations, and slope compensation. Switching power supplies are microelectronic systems with analog, analog– digital, and digital functions that set, manage, and control their outputs. Chapter 8 shows how to implement and design the building blocks needed for this functionality. Some of the blocks covered are current sensors and feedback translations, hysteretic and summing comparators, sawtooth and one-shot generators/oscillators, gate drivers and dead-time logic, zero-current detectors, ring suppressors, switched diodes, and shutdown and starter functions. The material also reviews the circuits used to realize some of these blocks, like low- and high-side supply-sensing comparators, push–pull logic, class-A inverters, SR flip flops, and others. The appendix is a short reference guide on SPICE simulations. It touches on convergence, models, and structure. It also lists devices, sources, and commands commonly used when simulating switched-inductor power supplies. It ends with behavioral models for common digital blocks and comparators used in this textbook and SPICE code for stabilizers not included in Chap. 6.

Contents

1

Diodes and BJTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Solids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Energy-Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Conduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 PN Junction Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Zero Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Reverse Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Forward Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Metal–Semiconductor (Schottky) Diodes . . . . . . . . . . . . . . . . . 1.3.1 Zero Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Reverse Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 Forward Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.4 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.5 Structural Variations . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Bipolar-Junction Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 NPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Diode-Connected BJT . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . .

1 3 3 4 4 4 7 8 13 14 15 17 23 23 24 24 24 26 27 27 33 39 42 43

2

Field-Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Junction FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 N Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 P Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 N-Channel MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Accumulation: Cut-Off . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Depletion: Sub-threshold . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Body Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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45 48 48 52 55 55 56 59 63 xi

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2.3

2.4

2.5

2.6

2.7 3

2.2.5 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 P-Channel MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.1 Accumulation: Cut Off . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.2 Depletion: Sub-threshold . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.3 Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.4 Body Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.3.5 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.3.6 Unifying Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.4.1 PN Junction Capacitances . . . . . . . . . . . . . . . . . . . . . . . . 76 2.4.2 Gate-Oxide Capacitances . . . . . . . . . . . . . . . . . . . . . . . . 77 2.4.3 MOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.4 MOS Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Short Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.5.1 Drain-Induced Barrier Lowering . . . . . . . . . . . . . . . . . . . 85 2.5.2 Gate–Channel Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.5.3 Source–Drain Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Other Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.6.1 Weak Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.6.2 Junction Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.6.3 Diffused-Channel MOSFETs . . . . . . . . . . . . . . . . . . . . . 96 2.6.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Switched Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Transfer Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Switched Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 DC–DC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Inductor Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Continuous Conduction . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Discontinuous Conduction . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 CMOS Implementations . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 Design Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Buck–Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Ideal Buck–Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Asynchronous Buck–Boost . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Synchronous Buck–Boost . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Ideal Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Asynchronous Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Synchronous Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

103 105 105 107 109 110 110 111 112 114 116 117 118 118 121 127 133 133 135 139

Contents

3.5

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142 142 144 148 152 152 158 161 165

Power Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Voltage Regulators and LED Drivers . . . . . . . . . . . . . . . 4.1.2 Battery Chargers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 Energy Harvesters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Operating Mechanics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Continuous Conduction . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Discontinuous Conduction . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Circuit Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 CMOS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Ohmic Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Ohmic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Continuous Conduction . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Discontinuous Conduction . . . . . . . . . . . . . . . . . . . . . . . 4.4 Diode Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Conduction Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Diode Drain Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Dead-Time Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 iDS–vDS Overlap Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Closing Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Opening Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 Reverse Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 Soft Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5 CMOS Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Gate-Driver Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 Closing Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 Opening Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.4 Driver Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Leaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 Input Switch-Node Capacitance . . . . . . . . . . . . . . . . . . . 4.7.2 Output Switch-Node Capacitance . . . . . . . . . . . . . . . . . . 4.7.3 Cut-off Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.1 Optimal Power Setting . . . . . . . . . . . . . . . . . . . . . . . . . .

167 170 171 171 172 173 174 174 175 176 178 178 180 188 191 191 192 192 196 196 201 204 210 211 214 214 216 218 219 221 221 222 223 225 225

3.6

3.7 4

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Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Ideal Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Asynchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Synchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . Flyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Ideal Flyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Asynchronous Flyback . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Synchronous Flyback . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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225 229 233 236 239

5

Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Two-Port Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Bidirectional Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Forward Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 LC Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Shunt Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Couple Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Couple Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Shunt Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Bypassed Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Bypassed Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 LC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Current-Sourced LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Voltage-Sourced LC . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 LC Tank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Phase Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Switched Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Signal Translations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Small-Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

241 243 244 244 247 248 248 249 253 256 260 263 263 267 270 270 278 285 285 286 286 287 294 304

6

Feedback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Translations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5 Loop Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Op-Amp Translations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Operational Transconductance Amplifier . . . . . . . . . . . . 6.2.3 Feedback Translations . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Stabilizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Amplifier Translations . . . . . . . . . . . . . . . . . . . . . . . . .

307 309 309 310 311 312 314 316 316 317 318 324 324 326

4.9

4.8.2 Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.5 Power-Conversion Efficiency . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . .

Contents

6.4

6.5

6.6

6.7 7

xv

6.3.3 Feedback Translations . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Mixed Translations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Voltage Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.5 Discontinuous Conduction . . . . . . . . . . . . . . . . . . . . . . . Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Transconductance Gain . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Type I: Inherent Stability . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 Type II: Pole–Zero Stabilization . . . . . . . . . . . . . . . . . . . 6.5.5 Discontinuous Conduction . . . . . . . . . . . . . . . . . . . . . . . Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Voltage Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 Digital Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.4 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 PWM Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Hysteretic Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Summing Contractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Summing Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 PWM Contractions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Hysteretic Contraction . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 Load Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Constant-Time Peak/Valley Loops . . . . . . . . . . . . . . . . . . . . . . 7.3.1 SR Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3 Constant On-Time Valley Loop . . . . . . . . . . . . . . . . . . 7.3.4 Constant Off-Time Peak Loop . . . . . . . . . . . . . . . . . . . 7.3.5 Constant-Period Peak/Valley Loops . . . . . . . . . . . . . . . 7.3.6 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Oscillating Voltage-Mode Bucks . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Resistive Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 RC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

328 336 342 342 343 344 346 351 356 359 359 359 360 363 366 369 369 369 370 370 371 373 376 376 385 394 394 395 398 400 404 404 404 404 406 410 412 417 418 418 422 428 428

xvi

8

Contents

Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 1. Current Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 Sense Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Voltage Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Voltage Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Phase-Saving Voltage Divider . . . . . . . . . . . . . . . . . . . . 8.2.3 Voltage-Dividing Error Amplifier . . . . . . . . . . . . . . . . . . 8.3 Digital Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Push–Pull Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 SR Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Dead-Time Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Comparator Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Hysteretic Comparators . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Summing Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Timing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 Clocked Sawtooth Generator . . . . . . . . . . . . . . . . . . . . . 8.5.2 Sawtooth Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.3 One-Shot Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Switch Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Class-A Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Supply-Sensing Comparators . . . . . . . . . . . . . . . . . . . . . 8.6.3 Zero-Current Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.4 Ring Suppressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.5 Switched Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.6 Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

431 434 434 441 444 444 444 446 448 449 449 454 455 464 465 465 467 468 470 470 472 474 476 476 477 480 481 483 484 488

Appendix: SPICE Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

1

Diodes and BJTs

Abbreviations BJT FET MOS AJ αT α0 β0 CDEP CDIF CJ CJ0 DN DH e– EB EBG EC EE EF EV gm γE h+ iB iC iD iE

Bipolar-junction transistor Field-effect transistor Metal–oxide–semiconductor Junction area Base-transport factor Baseline transport factor Baseline base–collector current gain Depletion capacitance Diffusion capacitance Junction capacitance Zero-bias junction capacitance Electron diffusion coefficient Hole diffusion coefficient Electron Energy barrier Band-gap energy Conduction-edge energy Electron energy Fermi energy level Valence-edge energy Small-signal transconductance Emitter injection efficiency Hole (missing electron) Base current Collector current Diode current Emitter current

# The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 G. A. Rincón-Mora, Switched Inductor Power IC Design, https://doi.org/10.1007/978-3-030-95899-2_1

1

2

iF iR iRC IS KB LN LP μN μP nE nH nI NA NB NC ND NE qE qFR qRR tFR tR tRR TJ τF τH τN vB vBC vBE vC vCE vCE(MIN) vD vE vR VBD VBI Vt wB wB0 WB

1

Forward diode current Reverse diode current Recombination current Reverse saturation current Boltzmann’s constant Electron’s average diffusion length Hole’s average diffusion length Electron mobility Hole mobility Electron density Hole density Intrinsic carrier concentration/ideality factor Acceptor doping concentration Base doping concentration Collector doping concentration Donor doping concentration Emitter doping concentration Electronic charge Forward-recovery charge Reverse-recovery charge Forward-recovery time Recovery time Reverse-recovery time Junction temperature Forward transit time Hole’s average carrier lifetime Electron’s average carrier lifetime Base voltage Base–collector voltage Base–emitter voltage Collector voltage Collector–emitter voltage Minimum collector–emitter voltage Diode voltage Emitter voltage Reverse diode voltage Breakdown voltage Built-in (potential) voltage Thermal voltage Effective base width Zero-bias base width Metallurgical base width

Diodes and BJTs

1.1 Solids

3

Power supplies use switches to draw, steer, and deliver charge from input sources into rechargeable batteries and microelectronic loads. Semiconductor companies use diodes, bipolar-junction transistors (BJTs), and complementary metal–oxide–semiconductor (CMOS) field-effect transistors (FETs) for this purpose. Of these, FETs are oftentimes preferable because they drop lower voltages than diodes and require less current to switch than BJTs, so they consume less power. Still, diodes do not require a synchronizing signal like FETs and BJTs and BJTs cost less money. Plus, MOSFETs incorporate diodes and BJTs that can at times activate and steer some or all of the current. So understanding how diodes and BJTs conduct current is essential.

1.1

Solids

1.1.1

Energy-Band Diagram

Electrons in populated orbits of a material are bound to their home sites around the nucleus in Fig. 1.1. Electrons in the outermost orbit are responsible for bonding with other atoms. These are the valence electrons that populate the valence band and form covalent bonds. Electrons that break free are available for conduction. These free charge carriers are in the conduction band. Although available for conduction, electron affinity keeps these electrons in their orbits. Combined potential and kinetic energy is lower for tightly bound electrons. So electron energy EE in the conduction band in Fig. 1.2 is greater than in the valence band. Conduction-edge energy EC is the minimum energy that liberated electrons carry. Valence-edge energy EV is the maximum energy that bound valence electrons hold. Electrons orbit around the nucleus at discrete energy levels. So no electrons reside between the valence and conduction bands. The energy span between these two bands is the band gap. This band-gap energy EBG is the energy needed to liberate and promote valence electrons into the conduction band. EBG is therefore the difference between EC and EV. Fig. 1.1 Atom

Nucleus: Protons & Neutrons Valence Electrons

Fig. 1.2 Energy-band diagram

EE

EC EF EV

Conduction Band EBG Valence Band

4

1.1.2

1

Diodes and BJTs

Conduction

Electrons that rise into the conduction band leave voids in the valence band. Once liberated, these free electrons drift easily. Neighbor valence electrons also shift easily into valence holes. And as these valence electrons shift positions, holes drift in the opposite direction. So holes in the valence band carry charge like electrons in the conduction band. Since liberated electrons create holes, the probability of finding electrons in the conduction band of a homogeneous material is equal to the probability of finding holes in the valence band. Because free electrons reside in the conduction band and holes in the valence band, the most probable energy level for a charge carrier (when neglecting that the band gap excludes electrons and holes) is halfway between the bands. The probability that this charge carrier is an electron or a hole is 50%. This 50% probability is what the Fermi energy level EF indicates and why EF in homogeneous material is halfway between EC and EV. The probability of finding charge carriers above and below this level falls exponentially. EF is effectively an indicator of charge-carrier density. And like water in a lake, charges do not flow when the concentration across a material is uniform. So EF is uniform across a material when current is zero and sloped when current is not zero.

1.1.3

Classification

Conductors like metal and aqueous solutions of salts conduct charge easily because valence electrons are so weakly bound to their home sites that they are practically free and available for conduction. This is another way of saying that the valence band overlaps the conduction band. Valence electrons in insulators like rubber and plastic, on the other hand, require so much band-gap energy to liberate that they hardly conduct. The band gap in semiconductors like silicon Si and germanium Ge is moderate, so they conduct moderately well. In silicon, the band-gap energy is 1.1 eV or 1.8
1019 J at 27  C.

1.1.4

Semiconductors

Thermally excited electrons that break free from their valence positions avail electron–hole pairs that can carry charge. These thermionic emissions produce an equal number of holes and electrons. This is the intrinsic carrier concentration ni of a semiconductor. This concentration is higher when the band-gap energy that binds valence electrons is lower and the temperature that energizes them is higher. ni for silicon at 27  C is 1.45
1010 cm3. Hole density nH and electron density nE in intrinsic semiconductors equal this ni because these materials are homogeneous and pure. Dopant atoms with partially populated outer orbits are impurities that can alter these concentrations. So doped

1.1 Solids

5

semiconductors are semiconductors with atomic impurities that produce uneven carrier concentrations. A. N Type Electrons in the outer orbit of donor atoms are so loosely bound in doped semiconductors that they are free in the conduction band. These dopant atoms effectively “donate” negatively charged electrons e–’s. This is why engineers say material doped with donor atoms is negative or N type. In spite of this appellation, the material is electrically neutral because the intrinsic and dopant atoms that comprise it are neutral. With more electrons in the conduction band, the probability that thermionic holes in the valence band recombine is higher. Electron and hole carrier concentrations are lower as a result. nH, for example, reduces to the number of thermionic holes nh that do not recombine. nh is therefore lower than ni by the amount that donor doping concentration ND dictates: nH ¼ nh ¼

ni 2 < ni , ND

ð1:1Þ

which is what the mass-action law states. The situation for nE is different because dopants add ND electrons to the conduction band. Plus, ND is normally orders of magnitude higher than ni. So ND is so much higher than the number of thermionic electrons that do not recombine ne that nE is nearly ND: nE ¼ ND þ ne  ND :

ð1:2Þ

ND therefore determines the extent to which the material is N type. nh is so much lower than the resulting nE that holes in N-type material are minority carriers and electrons are majority carriers.

Example 1: Find nH at 27  C in silicon when doped with 1014/cm3 donor atoms. Solution:
2 1:45
1010 ni 2 nH ¼ nh ¼ ¼ ¼ 2:10
106 cm3 ND 1014

6

1

Fig. 1.3 Band diagram of N-type semiconductors

e– #/m3 E E h+

Diodes and BJTs

Conduction Band

EC EF

EBG Valence Band

EV

When doped this way, the probability of finding free electrons e–’s is higher than that of finding holes h+’s. So EF in N-type material is closer to the conduction band in Fig. 1.3 than to the valence band. Since the probability of finding charge carriers drops exponentially away from EF and the band gap is free of carriers, nE peaks at the edge of the conduction band and decreases exponentially above EC. Although to a lower extent, nH similarly peaks at the edge of the valence band (where electrons are more likely to break free) and decreases exponentially below EV. B. P Type Acceptor atoms produce the opposite effect. Electrons in the outermost orbit of acceptor atoms are so tightly bound in doped semiconductors that they are in the valence band. This outer orbit is incomplete, however, with electron vacancies or holes h+’s. Since these impurities are more likely to “accept” than donate electrons, engineers say material doped with acceptor atoms is positive or P type. The material is nevertheless electrically neutral because the intrinsic and dopant atoms that comprise it are neutral. With more holes in the valence band, the probability that thermionic electrons in the conduction band recombine is higher, so nE and nH are lower. nE therefore reduces to the number of thermionic electrons ne that do not recombine. ne is lower than ni by the amount that acceptor doping concentration NA dictates: nE ¼ ne ¼

ni 2 < ni : NA

ð1:3Þ

Since dopants add NA holes to the valence band and NA is normally orders of magnitude greater than ni, NA holes overwhelm the thermionic holes that do not recombine nh. As a result, nH is nearly NA: nH ¼ NA þ nh  NA :

ð1:4Þ

NA determines the extent to which the material is P type this way. ne is so much lower than this nH that free electrons are minority carriers in P-type material and holes are majority carriers. When doped this way, the probability of finding holes is higher than that of electrons. So EF in P-type material is closer to the valence band in Fig. 1.4 than to the conduction band. Since the probability of finding charge carriers drops exponentially

1.2 PN Junction Diodes Fig. 1.4 Band diagram of P-type semiconductors

7

Conduction Band

e–

EE #/m3 h+

EC

EBG Valence Band

EF EV

away from EF and the band gap is free of carriers, nH peaks at the edge of the valence band and decreases exponentially below EV. Similarly, but to a lower extent, nE peaks at the edge of the conduction band and decreases exponentially above EC. C. Mobility Carrier mobility is the ease with which carriers flow when exposed to an electric field. It increases with temperature because thermal energy excites electrons into more mobile states. This higher kinetic energy eases their movement and, with it, conduction. Bound valence electrons shift into holes in the valence band with less ease than free electrons drift in the conduction band. Valence and nucleic bonds are to blame for this. The effective nucleic mass of holes is therefore higher than that of free electrons. As a result, hole mobility μP is usually two to three times lower than electron mobility μN. D. Notation Superscripted plus and minus signs normally indicate relative concentration levels. So ND+, ND, and ND–, respectively, produce heavily, moderately, and lightly doped N-type material that engineers denote with N+, N, and N–. ND+ is also usually orders of magnitude greater than ND and ND is similarly greater than ND–. The same applies to P-type semiconductors. NA+, NA, and NA– produce heavily, moderately, and lightly doped material P+, P, and P–. Unless otherwise specified, ND+ in N+ is usually on the same order of magnitude as NA+ in P+ and likewise for ND in N and NA in P and ND– in N– and NA– in P–. When doping concentration is so high that Ohmic resistance is comparable to metal, the semiconductor is degenerate. So degenerate semiconductors are good Ohmic contacts.

1.2

PN Junction Diodes

A PN junction diode is a piece of semiconductor doped so acceptor impurity atoms outnumber donor impurity atoms on one side and donor impurity atoms outnumber acceptor impurity atoms on the other side. The material transitions from one type to the other at the metallurgical junction XJ shown in Fig. 1.5. This is where doping concentrations effectively cancel. The doping difference NA – ND transitions across

8

1

Fig. 1.5 P+N junction

Diodes and BJTs

Metallurgical Junction NA+

P Type

N Type #/m3

NA – ND

ND

x

XJ Fig. 1.6 Zero-bias P+N junction

Metallurgical Junction P Type NA+

Depletion Region

––– O OOO – ––– O OOO – O – – O BI – O – O – O – O – – O O – O – O – O – O – – O O

V

dP

N Type ND

dN dW

this zero point abruptly in step junctions and more gradually in linearly graded junctions.

1.2.1

Zero Bias

A. Electrostatics Diffusion Diffusion is the force in nature that impels motion from dense regions to sparse spaces. In a PN junction, holes in the P side outnumber holes in the N side by orders of magnitude. Electron density in the N side is also much greater than electron density in the P side. Majority carriers therefore diffuse across the junction: holes to the N side and electrons to the P side. Depletion Diffusing electrons eventually populate holes in the P side when the system reaches thermal equilibrium. Diffusing holes similarly capture free electrons in the N side. This recombination process depletes the region near the junction of charge carriers. This carrier-free space in Fig. 1.6 is the depletion region. Ionization Parent atoms lose and receive charge as carriers diffuse in and out of their orbits. Departing holes and incoming electrons charge the P side negatively, and departing electrons and incoming holes charge the N side positively. So the P side begins to repel incoming electrons and the N side to repel incoming holes. Charge carriers nevertheless continue to diffuse until the electric field is strong enough to repel further action, which happens when carrier density (and EF) is uniform across the junction. The field that results across this space-charge region

1.2 PN Junction Diodes

9

when the system reaches thermal equilibrium establishes a built-in (potential) voltage VBI. Held majority carriers must therefore overcome the energy barrier EB that this VBI sets to diffuse across the junction: EB ¼ qE VBI ,

ð1:5Þ

where qE is the electronic charge, which refers to the 1.60
1019 Coulombs of charge that each electron carries. B. Energy-Band Diagram The band gap is constant throughout the material because both P- and N-type regions are part of the same semiconductor. The probability of finding charge carriers is also uniform because net current flow is zero. Since hole and electron concentrations are high in P and N regions, respectively, EF is closer to EV in P material and closer to EC in N material. So when piecing the band diagram together, EBG and EF are uniform across the device. EF in Fig. 1.7 is closer to EV in the P side than to EC in the N side because NA+ is much higher than ND. EC in the P side is higher than in the N side because N-side electrons need additional energy to overcome the energy barrier qEVBI that impedes further diffusion. C. Carrier Concentrations Hole and electron densities nH and nE far away from the junction and at the edge of the depletion region are uniform because they do not lose carriers to diffusion. This means that to the left of dW in Fig. 1.8, where the material is P type, nH is NA and nE is ne’s ni2/NA. nE is similarly ND and nH is nh’s ni2/ND to the right of dW, where the material is N type.

EC EF EV +

OOOOOOO OOOO 3 O

h /m

Fig. 1.8 Carrier densities across PN junction

q EVBI

NA+

– ––

e–/m 3

VBI

dW

ND

q EVBI

P Type nH ≈ NA

EBG

EBG

Fig. 1.7 Band diagram of zero-bias P+N junction

EC EF EV

Log #/m 3 xi

N Type n E ≈ ND

ni nE ≈ n e

dW XJ

nH ≈ n h x

10

1

Diodes and BJTs

Since fewer dopant carriers reduce the propensity for thermionic carriers to recombine, P-side holes that diffuse away not only reduce nH but also increase nE into the depletion region and N-side electrons that diffuse across do the opposite. The material is intrinsic where carrier densities match (at xi) because dopant electrons and holes neutralize. Here, thermionic emissions avail intrinsic concentrations of holes and electrons, which means nH and nE equal ni. When asymmetrically doped, the highly doped region diffuses more carriers across the junction than the lightly doped side. In the case of Fig. 1.8, for example, NA+ is much greater than ND. So nH near the junction XJ is greater than nE. This is why nH and nE crisscross further in the N side at xi (and not at XJ). Interestingly, minority carrier concentration in the lightly doped side is greater than in the highly doped counterpart. This is because fewer dopants reduce the number of thermionic carriers that recombine, so more thermionic carriers survive. nE’s ne in the P side is lower than nH’s nh in the N side because of this: because NA+ is greater than ND.

Example 2: Find nH and nE outside the depletion region at 27  C for a PN junction doped with 1017/cm3 acceptor atoms and 1014/cm3 donor atoms. Solution: nHðPÞ  NA ¼ 1017 cm3 nEðPÞ

nHðNÞ


2 1:45
1010 ni 2  neðPÞ ¼ ¼ ¼ 2:10
103 cm3 NA 1017
2 1:45
1010 ni 2  nhðNÞ ¼ ¼ ¼ 2:10
106 cm3 ND 1014 nEðNÞ  ND ¼ 1014 cm3

Note: nE(P)’s ne(P) is lower than nH(N)’s nh(N) because the P side is more heavily doped than the N side, so more thermionic electrons recombine.

1.2 PN Junction Diodes

11

D. Depletion Width More densely populated regions require less space to neutralize incoming carriers. So depletion distances from the junction are shorter when doping concentrations are higher. Total depletion width dW is shorter when NA and ND are higher for this reason: rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 1 dW ¼ dP þ dN / þ : NA ND

ð1:6Þ

Opposing doping concentrations across PN junctions are usually vastly different. In such cases, the highly doped region diffuses more carriers than the lightly doped side. With more incoming carriers and less neutralizing agents, depletion distance in the lightly doped side is far greater than in the highly doped region. So dN across the P+N junction that NA+ and ND establish, for example, is usually so much longer than dP that dW is nearly dN. In other words, dW is largely the depletion distance into the lightly doped region.

Example 3: Draw the band diagram of a zero-bias PN+ junction and approximate the relative location of the metallurgical junction XJ. Solution: EF in Fig. 1.9 is closer to EC in the N region than to EV in the P region because ND+ avails more free electrons than NA avails holes. dW extends more into the P region (from XJ) because the P region is lightly doped and the N region is heavily doped. So the P region requires more space to neutralize all the electrons that diffuse from the N side.

E. Built-In Barrier Voltage

EC EF EV

h+/m3

NA O

e–/m 3

X J q EVBI

dW VBI

q EVBI

– ––– ––––– ––––––––––

N D+

EC EF EBG

Fig. 1.9 Band diagram of zero-bias PN+ junction

EBG

The energy barrier across the junction indicates that dopant electrons in the N side need EB more energy than their equilibrium thermal energy to diffuse. The Fermi

EV

12

1

Diodes and BJTs

energy level indicates exponentially fewer electrons in the conduction band carry higher energy. So when combined, ne(P) is lower than ND by the exponential amount that EB and VBI overwhelm the thermal energy Et and thermal voltage Vt that junction temperature TJ establishes: nEðPÞ  neðPÞ ¼

    qE VBI ni 2 EB ¼ ND exp ¼ ND exp NA Et KB TJ   VBI ¼ ND exp , Vt

ð1:7Þ

where KB is Boltzmann’s constant 1.38
1023 J/K, TJ is in Kelvin K, Et is KBTJ, and Vt is KBTJ/qE. VBI is therefore a Vt and a logarithmic translation of how much NA and ND dwarf ni2: VBI

  NA ND ¼ Vt ln : ni 2

ð1:8Þ

Example 4: Find VBI at 27  C for a PN junction doped with 1017/cm3 acceptor atoms and 1014/cm3 donor atoms. Solution:       NA ND KB TJ NA ND VBI ¼ Vt ln ¼ ln qE ni 2 ni 2 "
# "
 
# 1:38
1023 ð300Þ 1017 1014
 ¼ ln
2 1:60
1019 1:45
1010
 ¼ ð25:9mÞ ln 0:70
1011 ¼ 650 mV

1.2 PN Junction Diodes

–

iR ≈ I S

Diffuse

Drift

NA+

vR +

OOOOOOO OOOO 3 O

h /m

q E (VBI + vR) dW

– ––

e–/m 3

ND

EBG

Fig. 1.10 Band diagram of reverse-bias PN junction

13

O

Drift

1.2.2

Diffuse

EC EF EV

Reverse Bias

A. Electrostatics Dopant Carriers Applying a negative voltage across the PN junction reinforces the built-in electric field. This effectively raises the energy barrier that majority carriers must overcome to diffuse, so dopant carriers do not diffuse. This reverse voltage vR in Fig. 1.10 increases the barrier to qE(VBI + vR). Thermionic Carriers Since the higher barrier deactivates dopant carriers, thermionic emissions avail more minority carriers than dopants in the other side of the junction avail majority carriers. In other words, P-side electrons outnumber N-side electrons and N-side holes outnumber P-side holes. Thermionic carriers therefore diffuse, and with the reverse field that VBI and vR set, drift across the depletion region. This flow of thermionic carriers establishes a reverse current iR. B. I–V Translation iR peaks and saturates quickly with increasing vR because thermal energy in semiconductors liberates few electrons. This is why reverse saturation current IS is normally low and why a vR of only three Vt’s raises iR to 95% of the IS that is possible:    vR iR ¼ IS 1  exp : nI Vt

ð1:9Þ

nI is the ideality factor used to compensate for second-order effects. Structural imperfections in the depletion region, for example, can trap mobile electrons. Since this reduces the effect of vR, nI is usually higher (up to two) than in the ideal case, for which nI is one. Several components dictate IS’s charge rate dqS/dtS. Electronic charge qE is the most basic of these. Charge-carrier concentrations are next. IS is proportional to cross-sectional junction area AJ, for example, because larger areas supply more carriers:

14

1

Diodes and BJTs

rffiffiffiffiffiffiffi rffiffiffiffiffiffi  dqS DN DP þ nhðNÞ IS  ¼ qE AJ neðPÞ dtS τN τP   2    2   ni DN ni DP ¼ qE AJ neðPÞ þ : NA LN ND LP

ð1:10Þ

IS is similarly proportional to thermionic carrier concentration: minority electron density ne(P) in the P region, minority hole density nh(N) in the N region, and the junction temperature that produces them. These minority carrier concentrations ultimately hinge on doping concentrations NA and ND. The number of carriers that cross also depends on diffusivity, which is the ability of charge carriers to diffuse. Electron and hole diffusion coefficients DN and DP quantify this effect. Charge rate also depends on the time that traversing carriers require to recombine. IS is therefore higher when N- and P-type average carrier lifetimes τN and τP are shorter. Another way to describe the temporal effect of τN and τP is spatially with average diffusion lengths LN and LP because LN and LP are, respectively, square-root translations of carrier diffusivity and lifetime: DNτN and DNτN. C. Depletion Width Note that vR applies a negative voltage to the P region and a positive voltage to the N region. So vR attracts dopant holes and electrons away from the junction. vR therefore widens the depletion region and the depletion distances that quantify this separation: dP, dN, and dW.

1.2.3

Breakdown

A. Impact Ionization When the reverse voltage is very high, vR accelerates thermionic electrons to such an extent and with such kinetic force that they collide and liberate bound electrons. So one energized electron in Fig. 1.11 drifts, collides, and frees one electron–hole pair that avails another electron and a hole. vR energizes the two liberated electrons to the same degree, so they generate two other electrons and two other holes. This multiplicative action continues as long as vR is above the breakdown voltage VBD that induces it. This process of colliding and releasing built-up energy to liberate electrons is impact ionization. Since reverse current builds and grows in avalanche fashion, this phenomenon is known as avalanche breakdown. The breakdown voltage for this mechanism is higher when doping concentrations are lower because, with the wider depletion regions that result, field intensity is lower. Typical avalanche VBD’s are greater than 5 V.

1.2 PN Junction Diodes

15

–

Dr

iR > I S

Diffuse

ift

h /m

––

–O

3

O

–O–O O

q E (VBI + vR)

OOOOOOO OOOO O

he nc ala Av

+

–

–– ––

e–/m 3

O

–

Tunneling

ND ift Dr

dW

– ––

EC EBG

NA+

vR

O

Diffuse

EF EV

Fig. 1.11 Band diagram of PN junction in reverse breakdown

B. Tunneling When vR is high and depletion width is very narrow, the field is so intense that valence electrons in the P region in Fig. 1.11 break away and tunnel through the depletion region. This is Zener tunneling. Reverse current climbs above IS this way as long as vR is higher than the VBD that induces iR. For the depletion width to be so narrow, doping concentrations must be very high. This is why Zener breakdown normally happens across highly doped junctions. Typical Zener VBD’s are less than 7 V. C. Convention Irrespective of which mechanism dominates, engineers normally call diodes optimized to operate in breakdown Zener diodes. In practice, many of these diodes “break” around 6–7 V. At this level, iR is the result of both avalanche and tunneling effects. Note, by the way, that neither breakdown mechanism is destructive.

1.2.4

Forward Bias

A. Electrostatics Applying a positive diode voltage vD across the PN junction opposes the built-in electric field. This effectively reduces the energy barrier that dopant carriers must overcome to diffuse to the qE(VBI – vD) that Fig. 1.12 shows. As vD reduces EB, an exponentially increasing number of dopant carriers become available.

16

1

– ––

NA+

vD

q E(VBI – vD ) dW

OOOOOOO OOOO O

h+/m3

e–/m 3

Diffuse

ND O

Drift

EBG

iD > 0

Diffuse

Drift

–

Diodes and BJTs

EC EF EV

Fig. 1.12 Band diagram of forward-bias PN junction

Since doping concentrations are so much higher than thermionic concentrations, dopant carriers quickly outnumber minority (thermionic) carriers in the opposing regions. The resulting concentration difference actuates diffusion of dopant carriers across the junction. The electric field present sweeps these dopant carriers across the depletion region to establish a forward diode current iF or iD. Note that diffusing electrons penetrate the P region and diffusing holes enter the N region to establish iD. So electrons become minority carriers in the P region, and holes become minority carriers in the N region. In other words, iD is the result of minority carrier conduction. B. I–V Translation iD is zero with zero bias. iD climbs when incoming carriers outnumber thermionic carriers. Since IS is thermionic current and raising vD avails an exponential number of diffusing carriers, iD is a scalar translation of IS that is zero when vD is zero and increases exponentially with vD:     vD iD ¼ IS exp  1 / AJ : nI V t

ð1:11Þ

Doping concentration is so high that three Vt’s can establish an iD that is 20 times greater than the thermionic current that limits iR to IS. When vD overcomes the built-in potential, the barrier fades and the depletion region shrinks. Since little impedes diffusion, the diode practically becomes a short. So iD skyrockets past the “knee” that VBI sets. Ideality The ideality factor when iD is low is similar to iR’s (greater than one) because imperfections trap a substantial fraction of diffusing electrons. All traps eventually fill, however, so higher current reduces the fraction of electrons lost to traps. Since diffusing electrons increase exponentially with vD, nI falls as vD climbs and approaches one when vD is roughly 0.5VBI to VBI, when diffusion overwhelms second-order effects. Near and above VBI, incoming carriers can outnumber dopant carriers, so fewer carriers recombine and nI is again greater than one. This high-level injection occurs first in the region with the lowest doping concentration. With these higher current

1.2 PN Junction Diodes

17

levels, the bulk regions and their contacts drop an Ohmic voltage that compresses (shrinks) vD. When this happens, iD reduces to a linear translation of the external voltage applied. C. Depletion Width Note that vD applies a positive voltage to the P region and a negative voltage to the N region. So vD repels dopant holes and electrons into the junction. vD therefore narrows the depletion region and the depletion distances that quantify their separation: dP, dN, and dW.

1.2.5

Model

A. Symbol The PN junction conducts substantial current when forward-biased and hardly any current when reverse-biased. So the symbol that represents it in Fig. 1.13 is an arrow that points in the direction of forward current iD. To highlight that current does not reverse (by much), a blocking line crosses the tip of the arrow. iD enters the anode terminal of the diode and exits from the cathode terminal. Diodes optimized to operate in breakdown receive the same basic symbol because the overall behavior is the same. But since breakdown conducts substantial reverse current, the blocking line in Fig. 1.14 flares out. These “wings” essentially indicate that the blocking mechanism is conditional. B. I–V Translation Notice that the equation for iD matches iR when iD and vD are negative. So the expression describes both forward and reverse conditions, but not breakdown. So since iD is high and negative in breakdown, iD in Fig. 1.15 falls abruptly near –VBD, saturates to –IS in reverse bias, increases exponentially with vD in forward bias, and skyrockets near VBI. Fig. 1.13 PN diode symbol

iD

vD

Fig. 1.14 Zener diode symbol

iR

p n

vR n p

1

iD

Breakdown

VBD

Zero Bias Reverse Bias

Diodes and BJTs

Forward Bias

18

–I S

vD VBI

Fig. 1.15 Diode’s current–voltage translation

The diode is practically a short in breakdown and at VBI and an open circuit otherwise. This is why engineers often use them as on–off switches. When used this way, the diode switch closes and drops close to VBI with forward current and opens whenever current reverses.

Example 5: Determine iD when vD is 650 mV, IS is 50 fA, nI is 1, and VBD is 6.8 V at 27  C. Solution:
 1:38
1023 ð300Þ KB TJ  ¼ 25:9 mV Vt ¼ ¼
qE 1:60
1019  

    vD 650m iD ¼ IS exp  1 ¼ 4:0 mA  1 ¼ ð50f Þ exp nI Vt ð1Þð25:9mVÞ

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Diode: I-V Curve vd vd 0 dc¼650m d1 vd 0 ndiode 1 .temp 27 .model ndiode d is¼50f n¼1 bv¼6.8 .op .dc vd -7.3 700m 10m .end Tip: Plot i(D1), comment or remove the .dc line, re-run the simulation, and view the output/log file.

1.2 PN Junction Diodes

19

C. Dynamic Response Small Variations Shifting the operating point of a diode requires charge flow. Raising the barrier voltage, for example, repels recombined carriers back to their home regions. The number of carriers that diffuse across the junction also decreases. Moving these carriers changes the charge concentration across the junction. This process requires time because iD carries a finite amount of charge per second. So the current and charge needed ΔiD and ΔqD to vary the voltage ΔvD dictate the response time ΔtR of the diode. Junction capacitance CJ, which is the charge held across the junction with one volt, relates these parameters: CJ ¼

ΔqD ΔiD ΔtR ¼ ¼ CDEP þ CDIF : ΔvD ΔvD

ð1:12Þ

Depletion capacitance CDEP is the component that the depletion region holds. Diffusion capacitance CDIF is the diffusion charge held in-transit. The depletion region is void of charge carriers and non-conducting, like an insulator, with the P and N regions as Ohmic contacts. This parallel-plate structure is what establishes CDEP. CDEP therefore increases with junction area and field intensity, and as a result, with AJ/dW: CJ0 AJ CJ0 '' AJ CJ0 '' A ffi ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffi ffi ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffi ffi/ J: CDEP ¼ qffiffiffiffiffiffiffiffiffiffiffi v v d VBI vD W 1  VDBI 1 þ VBIR V

ð1:13Þ

BI

Since a positive diode voltage narrows dW, CDEP also increases with higher vD. Doping concentration determines how many charge carriers are available and the barrier voltage VBI – vD how many of those vanish in the depletion region. So CDEP not only rises with vD but also with NA and ND. Since diffusion current fades with zero bias, measuring CJ when vD is zero to determine the zero-bias junction capacitance CJ0 and using CJ0 to extrapolate the effect of vD in VBI – vD on CJ is a practical way of quantifying CDEP. Normalizing CJ0 to area with CJ0'' is even better because AJ is a design variable. Forward-biased carriers diffuse across the junction to become minority carriers. If the doped regions are short, these carriers in Fig. 1.16 can reach the metallic contacts without recombining. Irrespective, diffusing carriers require forward transit time τF to feed iD. The voltage that sets this iD dictates the number of in-transit charge qDIF “held” by this mechanism. Fig. 1.16 In-transit diffusion charge when forward-biased

WN WF

vD

iD In-Transit q DIF

––––––– + OOOOO OOOOOOO OOOOOOOOO OOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOO

P N Junction

WF

WP

20

1

Diodes and BJTs

CDIF is the charge needed ΔqDIF for the voltage to vary ΔvD: CDIF ¼

     ΔqDIF ΔiD τF  ∂iD ID ¼   τ τ  gm τ F : F ΔvD ΔvD Small Variations Vt F ∂vD

ð1:14Þ

Since ΔiD avails ΔqDIF after τF, CDIF is sensitive to iD and the vD that sets iD. CDIF is nonlinear because iD is an exponential translation of vD. For small variations, however, ΔiD/ΔvD is roughly the linear translation that iD’s partial derivative ∂iD/∂vD or ID/Vt sets. This derivative is the small-signal transconductance gm of the diode, where ID is the static (non-varying) component of iD. Since all carriers ultimately recombine in long diodes, τF is their average lifetime. τF in asymmetrically doped junctions is the average lifetime of the dominant carrier. So τF is nearly τP in P+N junctions and τN in PN+ junctions. τF, however, is a fraction of that in short diodes, in which case CDIF is lower. In other words, short diodes are fast. CDIF climbs exponentially with vD because diffused carriers in iD increase exponentially with vD. So CDIF in Fig. 1.17 overwhelms CDEP 200–400 mV before vD reaches VBI. In other words, CJ is practically CDEP in reverse bias and light forward bias and CDIF when vD is within 100 mV or so of VBI.

Example 6: Determine CD for the diode in Example 5 when CJC0 is 100 fF, VBI is 650 mV, and τF is 1 ns. Solution: vD ¼ 650 mV ¼ VBI ¼ 650 mV ∴ CD ¼ CDEP þ CDIF  CDIF  

I 4:0m ð ln Þ ¼ 154 pF CDIF  D τF ¼ 25:9m Vt

Forward Bias IF

P

CJ0 0

vD

C DE

CD

Reverse Bias

Log C J

Fig. 1.17 Junction capacitance

VBI

1.2 PN Junction Diodes

21

Example 7: Determine CD for the diode in Examples 5 and 6 when vD is 2 V. Solution: vD ¼ 2 V < 0 ∴

CD ¼ CDEP þ CDIF  CDEP

CJ0 100f ffi ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi CDEP ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffi
2 ffi ¼ 50 fF vD 1  VBI 1  650m Note: Reverse-bias capacitance is usually much lower than forward-bias capacitance.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Diode: Capacitance vd vd 0 dc¼650m d1 vd 0 ndiode 1 .temp 27 .model ndiode d is¼50f n¼1 bv¼6.8 cjo¼100f vj¼650m tt¼1n .op .end Tip: View the output/log file.

Large Transitions When used as switches, diodes transition between the on and off states that forward- and reverse-bias conditions set. Reverse-recovery time tRR refers to the time needed to reverse-bias the junction from a forward-bias state. tRR is therefore the time needed to pull in-transit diffusion carriers qDIF back to their home regions and to recombine carriers qDEP in the depletion region. But of these, qDIF is usually much greater than qDEP. tRR is largely the time that reverse current iR requires to collect the reverserecovery charge qRR that qDIF sets: tRR

q q þ qDEP qDIF ¼ RR ¼ DIF   iR iR iR

  iF τ , iR F

ð1:15Þ

22

1

Fig. 1.18 Reverse-recovery current

Diodes and BJTs

iF

iD

tRR Time

qRR –iR(LIM)

–iR(PK) where qDIF is the charge that forward-bias current iF produces with τF and iR can vary with time. So tRR ultimately hinges on iF and the iR that circuit conditions avail. When unchecked, iR can peak to a level iR(PK) in Fig. 1.18 that is comparable to and possibly higher than –iF. When limited to iR(LIM), iR(LIM) extends tRR. This is unfortunate either way because the diode should be off, not conducting this much reverse current. Forward-recovery time tFR refers to the time needed to forward-bias a reversebiased junction. tFR is therefore the time needed to supply in-transit diffusion and depletion carriers. Since qDIF is much greater than qDEP, forward-recovery charge qFR is nearly qDIF. This transition is more benign than reverse recovery in two ways. First, the forward current iF needed to supply qDIF flows from anode to cathode, as a diode should. Second, the circuit avails the iF that sets qDIF in the first place: tFR ¼

qFR qDIF þ qDEP qDIF iF τF ¼   ¼ τF : iF iF iF iF

ð1:16Þ

So tFR is nearly the forward transit time of the diode.

Example 8: Determine tRR for the diode in Examples 5 and 6 when recovering the reverse state in Example 7 and the resistance that limits this vD variation is 10 kΩ. Solution: ΔvD 650m  ð2Þ ¼ 260 μA ¼ 10k RR     qDIF iF 4:0m ð ln Þ ¼ 15 ns   τ ¼ 260μ iR iR F iR ¼

tRR

1.3 Metal–Semiconductor (Schottky) Diodes

23

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Diode: Reverse Recovery vd vx 0 dc¼-2 rs vx vd 10k d1 vd 0 ndiode 1 .ic v(vd)¼650m .model ndiode d is¼50f n¼1 bv¼6.8 cjo¼100f vj¼600m tt¼1n .tran 10n .end Tip: Plot v(vd) and i(D1).

1.3

Metal–Semiconductor (Schottky) Diodes

Electrons in metal are so weakly bound that they are practically free and available for conduction. Still, the probability of finding electrons above the Fermi level of metal EFM decreases exponentially with electron energy EE. The Fermi level EFS of a semiconductor is greater than EFM when the semiconductor has more high-energy electrons, like the N-type semiconductor in Fig. 1.19.

1.3.1

Zero Bias

Since carrier concentration at higher energy levels is higher in the semiconductor, electrons diffuse into the metal when connected together. Diffusing electrons deplete and ionize the semiconductor region near the junction XJ. Electrons continue to diffuse until the growing electric field is high enough to repel further action. Since current cannot flow under zero-bias conditions, the probability of finding charge carriers (i.e., EFM and EFS) in Fig. 1.20 is uniform across the junction. Higher electron density in the semiconductor nE(S) induces more diffusion. As a result, the semiconductor ionizes more, and the built-in voltage VBI that the barrier establishes Fig. 1.19 Band diagram of separate metal and N-type semiconductor solids

EE –

e–/m 3

–– ––– –––––

e–/m 3–––––––––––

EFM

–––––––– –––––––––––– –––––––––––––––

Metal

EBG N-Type Semi.

EC E FS EV

24

1

Fig. 1.20 Band diagram of zero-bias N-type metal– semiconductor junction

–

E FM

e

/m 3 – –– –

XJ

–––––– –––––––––– –––––––––––––––

q EVBI

Diodes and BJTs

– –––

e–/m 3

EBG N Semi.

Metal dW

EC E FS EV

is higher. The depletion width is narrower when nE(S) is higher because depleting a region that is more denser with electrons is more difficult.

1.3.2

Reverse Bias

Applying a positive voltage vR to the semiconductor raises the barrier voltage VBI + vR that electrons in the semiconductor need to overcome and diffuse into the metal. So no electrons diffuse. Still, vR pulls thermionic electrons in the metal into the semiconductor. But since thermionic electron density is low, reverse current saturates with little vR to the reverse saturation current of the junction.

1.3.3

Forward Bias

Applying a positive voltage vD to the metal does the opposite: reduces the barrier voltage VBI – vD that electrons in the semiconductor need to overcome and diffuse into the metal. So electrons diffuse and establish current flow. Since the number of high-energy electrons climbs exponentially with a lower barrier voltage, iD increases exponentially with vD.

1.3.4

Model

A. Symbol The metal–semiconductor junction conducts substantial iD when forward-biased and hardly any iR when reversed. So like the PN diode, the symbol that represents the metal–semiconductor junction in Fig. 1.21 is an arrow that points in the direction of iD. To highlight that current does not reverse (by much), a blocking line crosses the tip of the arrow. But to distinguish it from the PN diode, the ends of the blocking line square back. Engineers often call this structure a Schottky or Schottky barrier diode after the physicist recognized for this diode. Hot-electron and hot-carrier diodes are also common names for this device because diffusing electrons carry more energy than electrons in the metal.

1.3 Metal–Semiconductor (Schottky) Diodes Fig. 1.21 Metal– semiconductor (Schottky) diode symbol

25

iD

vD s

B. I–V Translation iD rises so much when vD reaches VBI that the junction practically shorts like Fig. 1.15 shows. Reinforcing the barrier with a negative vD induces so little iR that the device opens like a switch. When the reverse voltage is high enough, however, the junction “breaks down” and shorts to conduct substantial iR. In short, this diode behaves very much like the PN diode. This diode, however, normally diffuses fewer carriers with zero bias than the PN junction. So the VBI that these diffusing electrons establish is usually lower, about 150–300 mV. The metal also avails more thermionic electrons, so reverse current is higher when vD reverses. Since diffusing electrons into the metal do not recombine like they would in a P region, the ideality factor is closer to one. C. Dynamic Response Carriers that diffuse away and vanish from the depletion region ionize the junction. Since the barrier voltage VBI – vD keeps more carriers from diffusing, reducing vD reduces the number of carriers that vanish and the charge they establish. Depletion capacitance CDEP therefore holds less charge when vD falls and reverses like in the PN diode. CDEP also scales with doping concentration because more carriers diffuse when carrier density is higher. Unlike PN diodes, however, forward-bias electrons do not traverse a P region before reaching a metallic contact. And no holes diffuse into the semiconductor. So carriers do not require forward transit time τF to feed iD. This means that the process of supplying and retrieving electrons is nearly instantaneous. And in-transit charge and diffusion capacitance are nil. With no qDIF to recover, reverse-recovery time is very short. D. Diode Distinctions Metal–semiconductor diodes are faster than PN diodes. Plus, they drop lower voltages, so they burn less power. The drawback is, they also leak more reverse current. All this is because diffused electrons are majority carriers in metal and minority carriers in a P region. So forward iD is the result of majority carrier conduction in Schottkys and minority carrier conduction in PN diodes. In a way, Schottkys behave like P–N junctions with very short P regions because diffusing electrons alone establish VBI and feed iD, and τF in the P region is very short.

26

1.3.5

1

Diodes and BJTs

Structural Variations

A. P Type The P-type Schottky diode is the complement of the N type. When EFS in Fig. 1.22 is below EFM and the two materials connect, semiconductor holes need less energy than metal electrons to diffuse. So metal electrons populate and pull semiconductor holes into the metal, ionizing the semiconductor until the field that is growing is high enough to keep other holes from diffusing. VBI in Fig. 1.23 is the barrier that keeps other holes from diffusing. The number of holes that diffuse and vanish from the depletion region is usually so low that VBI is very low. So the reverse leakage current that results (with such a low VBI) is correspondingly high. This is why N-type Schottkys are more prevalent in practice, because they are easier to optimize (for lower leakage). B. Contacts The depletion region is so narrow when the N semiconductor is highly doped that electrons can tunnel easily across. As a result, both positive and negative voltages across the junction induce substantial forward and reverse currents. This way, the junction forms a Schottky contact. When high-energy electron density in the metal is higher than in the N semiconductor (i.e., EFM is higher than EFS) is higher than, metal electrons diffuse into the semiconductor with zero bias. When this happens, electrons accumulate near the junction. So electrons can flow easily in both directions. This way, the junction is an Ohmic contact. Fig. 1.22 Band diagram of separate metal and P-type semiconductor solids

e–/m 3

EFM

–– –––––– –––––––––––––

EC

EE

EBG

Metal P-Type Semi.

Fig. 1.23 Band diagram of zero-bias P-type metal– semiconductor junction

dW E FM

e–/m 3– –––––––– –

XJ

–––––––––– –––––––––––––––

EC

EBG P Semi. OO

Metal

+

q EVBI

h /m

EFS EV

3

EFS EV

1.4 Bipolar-Junction Transistors

1.4

27

Bipolar-Junction Transistors

The bipolar-junction transistor (BJT) is basically two diodes head-to-head or backto-back where the sandwiched “head” or sandwiched “back” is narrow. The transistor is “bipolar” because the structure is symmetrical, so the transistor can steer current in both directions. Engineers call the middle region the base because, when first built, it served as the mechanical base and support for the structure.

1.4.1

NPN

In an NPN, head-to-head diodes sandwich a thin P-type base like Fig. 1.24 shows. The short distance between the junctions is the metallurgical base width WB. The effective base width wB is shorter because base holes near the junctions diffuse away into the N regions. So the depletion regions effectively squeeze the base to wB. A. Active Bias With a short base, the BJT activates when one diode forward-biases and the other diode reverses. In Fig. 1.25, the base voltage vB forward-biases the junction on the left with respect to vE and reverse-biases the junction on the right with respect to vC. So vC is greater than vB, which is in turn greater than vE. As a result, the field barrier and depletion region on the left decrease and the counterparts on the right increase. Electrostatics Electrons and holes therefore diffuse across the junction on the left. wB is so short that diffused electrons reach the opposite end of the base without recombining. Since vC is greater than vB, vC pulls these base electrons across the depletion region into the N region on the right. Fig. 1.24 NPN BJT structure

Metallurgical Junctions Base P wB

N Depleted Fig. 1.25 Band diagram of NPN when activated

WB

N Depleted

Diffuse – –– –––– –––––––

Dr

P

iE vE

N Emitter

EF

wB OOO OO O

Diffuse

vB iB

ift

IEL D

– –– –––– –––––––

iC N vC Collector

28

1

Diodes and BJTs

This way, the N-type region on the left “emits” the electrons that the N-type region on the right “collects.” And as this happens, the P-type base injects holes into the N-type emitter. So the emitter receives the electron and hole currents iE– and iE+ that the collector and base supply with collector and base currents iC and iB: iE ¼ iE þ iEþ ¼ iC þ iB :

ð1:17Þ

Determinants Of the emitter current iE, iC loses iE+ to iB. This iE+ is largely the fraction of iE– that the base and emitter doping concentrations NB and NE and effective diffusion distance of electrons in the base wB (because wB is shorter than the average diffusion length of electrons across a long base LB–) and average diffusion length LE+ of holes in the emitter set: iEþ ¼ iE



NB DEþ LEþ



wB NE DB

 /

   NB wB , NE LEþ

ð1:18Þ

along with diffusivity of holes in the emitter DE+ and diffusivity of electrons in the base DB–. So emitter injection efficiency γE, which is the fraction of iE that iE– avails, is mostly an NELE+ fraction of NBwB and NELE+: γE 

iE iE NE LEþ ¼ / : iE iEþ þ iE NB wB þ NE LEþ

ð1:19Þ

But not all electrons in iE– reach the collector. Some of them recombine with holes in the base. And more recombine when wB is a larger fraction of LB–. The recombination current iRC that results is a quadratic wB/LB– fraction of half iE–:  iRC  0:5iE

wB LB

2 :

ð1:20Þ

So the base transport factor αT, which is the fraction of iE– that feeds iC, is αT 

 2 iC i  iRC wB ¼ E  1  0:5 : iE iE LB

ð1:21Þ

Notice that αT is nearly 90% when wB is 45% of LB–. iRC and αT also depend on collector voltage vC because vC sets the width of the depletion region that squeezes wB. So a higher vC expands the depletion region, which in turn shrinks wB, reduces iRC, and raises αT. wB is therefore shorter than the unbiased base width wB0 (when emitter voltage vE, vB, and vC are zero). The ultimate effect of this base-width modulation is a linear variation in iC. Since depleting the region near the junction is easier when lightly doped, this effect is more severe when collector doping concentration NC and NB are lower.

1.4 Bipolar-Junction Transistors

29

Current Translations γE and αT set the BJT’s overall baseline transport factor α0: i α0  C ¼ γE αT0 / iE



NE LEþ NB wB þ NE LEþ

"



w 1  0:5 B0 LB

2 # :

ð1:22Þ

This α0 is nearly 100% when NE is much greater than NB and wB0 is much shorter than LE+ and LB–. Note that α0 is the emitter-to-collector current gain translation. α0 is close to 100% when iC loses little to iB. This is another way of saying that the base-to-collector baseline current gain β0 is high. Since NB and NE dictate how iE splits into iE– and iE+ and wB/LB– determines how much of iE– is lost to iRC, wB0/LB– limits the gain that NE/NB sets: 2 iC iE  iRC iE  0:5iE ðwB0 =LB Þ ¼ ¼ iB iEþ þ iRC iEþ þ 0:5iE ðwB0 =LB Þ2 )  ( 1  0:5ðwB0 =LB Þ2 NE ¼ : NB ½ðDEþ wB Þ=ðLEþ DB Þ þ 0:5ðNE =NB ÞðwB0 =LB Þ2

β0 

ð1:23Þ

α0 and β0 relate because iE in α0 feeds iB in β0 and iC in α0 and β0: α0 

β0 iC iC 1 ¼ ¼ : ¼ iE iB þ iC iB =iC þ 1 1 þ β0

ð1:24Þ

α0 and β0 are ultimately measures of quality in a BJT that improve when wB is shorter (i.e., when WB is shorter, NB is lower, and vC is higher). Collector Current The iE– that iC collects is the forward-bias diode current that vB and vE establish with base–emitter voltage vBE or vB – vE:        v vBE v iC  iE 1 þ CE  IS exp  1 1 þ CE / AJBE : VA nI V t VA

ð1:25Þ

iC is therefore proportional to IS and, in consequence, to the cross-sectional area of the base–emitter junction AJBE. But since raising vC narrows wB, which in turn increases the fraction of iE– that feeds iC, iC climbs with collector–emitter voltage vCE. VA is the process-dependent constant that models this linear effect that basewidth modulation produces. Engineers call this parameter Early voltage after the scientist that first observed and modeled this behavior. B. Saturation The BJT saturates when vB forward-biases both junctions. As a result, both barrier voltages and depletion regions decrease and charge carriers in Fig. 1.26 diffuse across both junctions. Electron densities at the edges of the base match

30 Fig. 1.26 Band diagram of symmetrically biased NPN in saturation

1

Diffuse

Diffuse

– –– –––– –––––––

– –– –––– –––––––

P

iE vE

N

iC N

wB OOO OO O

vB

– –– –––– –––––––

iB

Diffuse – –– –––– –––––––

P

iE vE

N

vC

Diffuse

Diffuse

Fig. 1.27 Band diagram of asymmetrically biased NPN in saturation

Diodes and BJTs

iC

wB

N

OOO OO O

vC

Diff.

Diffuse

vB

iB

vBE > vBC

when the junctions forward-bias equally. So instead of diffusing across the base, all emitter and collector electrons recombine with base holes. As a result, vB feeds current to both N regions. When one junction is less forward-biased than the other, fewer electrons diffuse across this junction. So the excess difference diffuses across the base to the least forward-biased end (to the right in Fig. 1.27). A fraction of these electrons recombines with the few base holes that diffuse in the same direction. So when vBE exceeds the base–collector voltage vBC, the electrons that survive establish an iC that flows into vC and, together with iB, flow out of vE as iE. Current Translations Collector electrons that diffuse into the base diminish electron diffusion across the base, so iC collects fewer electrons. Decreasing NC reduces this effect. iC also loses electrons to forward-biased base holes, so iRC falls when NB is lower. iC loses so much to these effects when deeply saturated that iC can reverse direction. But even if only lightly saturated, α0 and β0 are still lower in saturation than in the active region. C. Optimal BJT The emitter injects more diffusion current that the collector receives when NE is higher than NB. Plus, the collector loses less diffusion current to the base when NC is lower than NB. So α0 and β0 are greater when NE > NB > NC. But reducing NB and NC also increases base-width modulation, which sensitizes iC to vC with a lower VA. The optimal BJT therefore reduces NB and NC only to the extent that an acceptably high VA allows. Typical values for α0, β0, and VA of an optimized N+PN– BJT are 98–99% A/A, 50–70 A/A, and 50–100 V.

1.4 Bipolar-Junction Transistors

31

Fig. 1.28 NPN BJT symbol

iC iB vCE vBE

n– p n+

iE

D. Symbol Engineers design NPNs so collectors receive most of the electrons that emitters inject. This way, when active, iB is very low. The orthogonal wall-like line into which iB in Fig. 1.28 flows represents the base of the NPN for this reason, because a short base effectively blocks iB. In this mode, only the base–emitter junction forward-biases. So vBE in an NPN is positive and iB flows into the base and out of the emitter. To illustrate this diode-like behavior, an arrow between the base and emitter terminals points in the direction of iB: toward the emitter. E. Modes Direction Given their symmetry, BJTs are bidirectional. As long as one diode forward-biases and the other reverses, the BJT is active. When saturated, the BJT favors the junction with the highest forward-bias current. Orientation When asymmetrically doped, the end with the highest doping concentration can inject more carriers into the base that the other side can collect. This highly doped terminal is therefore more optimal as an emitter than a collector. So by convention, the “emitter” usually refers to the highest doped end. In an N+PN–, for example, the N+ terminal is normally the emitter and the N– terminal is the collector. Forward Active The BJT is forward active when the base–emitter junction forwardbiases and the base–collector junction reverses. So in the NPN, vBE is positive and vBC is negative. In other words, vCE is higher than vBE and iC in Fig. 1.29 is exponential with vBE and linear with vCE when the BJT is forward active. Forward Saturation The BJT saturates when both junctions forward-bias. So the forward-active NPN saturates when vCE falls below vBE. Since the transition happens when vCE matches vBE, iC along the active–saturation boundary climbs exponentially with the vBE that vCE’s saturation point sets. When the base–collector junction forward-biases by less than 200 mV or so, base–emitter diffusion is so much greater that the effects of base–collector diffusion

32 Fig. 1.29 N+PN– collector current

1

Deep Sat.

Diodes and BJTs

Light Sat. vBE3 > vBE2

vCE = vBE

vBE2 > vBE1

vCE ≤ vCE(MIN) iC

Cut Off vBC1 > 0 V vBC2 > vBC1 vBC3 > vBC2

Rev. Act. Light Sat.

vBE1 > 0 V

Forward Active vCE Deep Sat.

are negligible. So iC remains exponential with vBE and linear with vCE. In other words, light saturation is largely an extension of the active region. Forward-biasing the base–collector junction by more than 200 mV or so diffuses so many electrons and holes that their effects are no longer negligible. Fewer electrons reach the collector, and of these, a larger fraction recombines with the base holes that diffuse in the same direction. So iC in deep saturation falls appreciably with vCE when vCE falls below the minimum collector–emitter voltage vCE(MIN) that doping concentrations and parasitic resistances ultimately dictate. vCE(MIN) is oftentimes 200–400 mV. Reverse Active The junctions reverse roles in reverse modes. So the base–collector junction forward-biases and the base–emitter junction reverses in reverse active. In the NPN, vBC is positive and vBE is negative, and as a result, vEC is higher than vBC and iC is exponential with vBC and linear with vEC. Reverse Saturation The reverse-active NPN saturates when the base–emitter junction forward-biases, which happens when vEC falls below vBC. Forward-biasing the base–emitter junction by less than 200 mV or so, however, diffuses so few carriers that their effects are negligible. Current falls appreciably with vEC when vEC falls below the vEC(MIN) that process parameters and resistances set. Optimal Behavior Since forward modes forward-bias the highly doped N region, forward injection efficiency is usually higher than in reverse. α0 and β0 are therefore greater in forward bias than in reverse under similar bias voltages. This is why the magnitude of iC is usually higher in forward modes. Cut off BJT currents are ultimately the result of carrier diffusion. So when both junctions reverse and diffusion stops, currents fade. This is the cut off region, which happens in the NPN when vBE and vBC are both zero and negative. The x axis in Fig. 1.29 marks this mode because iC is zero along that line.

1.4 Bipolar-Junction Transistors

33

Example 9: Determine iC and iB when vBE is 650 mV, vC is 4 V, vE is 0, βF is 50 A/A, IS is 50 fA, nI is 1, and VA is 50 V at 27  C. Solution:  

    

vBE v 650m 4 iC  IS exp 1 1þ  1 1 þ CE ¼ ð50f Þ exp 50 nI Vt VA ð1Þð25:9mÞ ¼ 4:3 mA iB 

iC 4:3m ¼ 86 μA ¼ 50 βF

Explore with SPICE: See Appendix A for notes on SPICE simulations. * NPN BJT: I-V Curves vc vc 0 dc¼4 vb vb 0 dc¼650m q1 vc vb 0 npnbjt 1 .model npnbjt npn is¼50f va¼50 bf¼50 .op .dc vc 20m 5 10m vb 650m 600m 10m .end Tip: Plot ic(Q1), comment or remove .dc line, re-run the simulation, and view the output/log file.

1.4.2

PNP

The PNP is the NPN’s complement. In a PNP, tail-to-tail diodes sandwich the thin N base in Fig. 1.30. WB is the short metallurgical distance between the junctions. wB is Fig. 1.30 PNP BJT structure

Metallurgical Junctions

P Depleted

Base N wB

WB

P Depleted

34

1

Fig. 1.31 Band diagram of PNP when activated

Diodes and BJTs

iB vB Diffuse

vC

P

– –– ––––

iC Collector OOOOO OOO O

wB EF Dr

IEL D

N

P

vE

Emitter iE OOOOO OOO O

ift

Diffuse

the distance between the depletion regions that base electrons near the junctions leave behind when diffusing into the P regions. A. Active Bias With a short base, the PNP activates when one diode forward-biases and the other diode reverses. The base voltage vB in Fig. 1.31 forward-biases the junction on the right with respect to vE and reverse-biases the junction on the left with respect to vC. So vE is greater than vB, which is in turn greater than vC. As a result, the field barrier and depletion region on the right decrease and the counterparts on the left increase. Electrostatics With that junction forward-biased, electrons and holes diffuse across the junction on the right. wB is so short that almost all diffused holes reach the other end of the base without recombining. Since vC is lower than vB, vC pulls these base holes across the depletion region into the P-type region on the left. In other words, the P-type region on the right “emits” the holes that the N-type region on the left “collects.” And as this happens, the N-type base injects electrons into the emitter. So the emitter supplies the hole and electron currents iE+ and iE– that the collector and base terminals receive with iC and iB: iE ¼ iEþ þ iE ¼ iC þ iB :

ð1:26Þ

Determinants Of iE, iC loses iE– to iB. This iE– is the fraction of iE+ that NB and NE and effective diffusion distance of holes in the base wB (because wB is shorter than the average diffusion length of holes across a long base LB+) and average diffusion length of electrons in the emitter LE– set: iE ¼ iEþ



NB DE LE



wB NE DBþ

 /

   NB wB , NE LE

ð1:27Þ

along with diffusivity DE– of electrons in the emitter and diffusivity of holes DB+ in the base. So injection efficiency γE is largely an NELE– fraction of NELE– and NBwB:

1.4 Bipolar-Junction Transistors

γE 

35

iEþ iEþ NE LE ¼ / : iE iEþ þ iE NE LE þ NB wB

ð1:28Þ

Some holes in iE+ recombine with base electrons. And more recombine when wB is a larger fraction of LB+. iRC is a quadratic wB/LB+ fraction of half iE+:  iRC  0:5iEþ

wB LBþ

2 :

ð1:29Þ

So the fraction of iE– that feeds iC is  2 iC iEþ  iRC wB αT  ¼  1  0:5 : iEþ iEþ LBþ

ð1:30Þ

Notice that this base transport factor αT is nearly 90% when wB is 45% of LB+. iRC and αT also depend on vC because vC sets the width of the depletion region that squeezes wB. So a lower vC expands the depletion region, which in turn shrinks wB, reduces iRC, and raises αT. wB is therefore shorter than the unbiased base width wB0 (when vE, vB, and vC match). This base-width modulation produces a linear variation in iC that is more severe when the region near the junction is easier to deplete, which happens when NB and NC are lower. Current Translations γE and αT set the overall baseline transport factor α0 of the PNP: i α0  C ¼ γE αT0 / iE



NE LE NE LE þ NB wB

"



w 1  0:5 B0 LBþ

2 # :

ð1:31Þ

α0 nears 100% when NE is much greater than NB and wB0 is much shorter than LE– and LB+. α0 is close to 100% when iC loses little to iB, which happens when baseline β0 is high. Since NE and NB dictate how iE splits into iE+ and iE– and wB/LB+ determines how much iE+ is lost to iR, wB0/LB+ limits the gain that NE/NB sets: 2 iC iEþ  iRC iEþ  0:5iEþ ðwB =LBþ Þ ¼ ¼ iB iE þ iRC iE þ 0:5iEþ ðwB =LBþ Þ2 )  ( 1  0:5ðwB =LBþ Þ2 NE ¼ : NB ½ðDE wB Þ=ðLE DBþ Þ þ 0:5ðNE =NB ÞðwB =LBþ Þ2

β0 

ð1:32Þ

α0 and β0 are higher when wB is shorter (i.e., when WB is shorter, NB is lower, and vC is higher).

36

1

Diodes and BJTs

Collector Current The iE+ that iC receives is the forward-bias diode current that vEB sets:        v v v iC  iEþ 1 þ EC  IS exp EB  1 1 þ EC / AJBE : VA Vt VA

ð1:33Þ

iC is therefore proportional to IS and, in consequence, to AJBE. But since raising vEC narrows the base, which in turn increases the fraction of iE+ that feeds iC, iC climbs with vEC. VA models this base-width modulation effect in iC. B. Saturation The PNP saturates when both junctions forward-bias. Charge carriers diffuse across both junctions when this happens. When symmetrically forward-biased, hole densities at the edges of the base in Fig. 1.32 match. So instead of diffusing across the base, holes recombine with base electrons. As a result, the base pulls current from both P regions. When one junction forward-biases less than the other, fewer holes diffuse across that junction. So the excess difference diffuses across the base to the least forwardbiased side (to the left in Fig. 1.33). A fraction of these holes recombines with the few base electrons that diffuse in the same direction. So when vEB is greater than vCB, the holes that survive establish an iC that flows out of vC, which is what remains of the iE that flows into vE after vB pulls iB. Translations Collector holes that diffuse into the base diminish hole diffusion across the base, so iC collects fewer holes. Decreasing NC reduces this effect. iC Fig. 1.32 Band diagram of symmetrically biased PNP in saturation

vB Diffuse

vC iC

iB

– –– ––––

wB

P

N

OOOOO OOO O

Diffuse

Fig. 1.33 Band diagram of asymmetrically biased PNP in saturation

vEB > vCB vC iC

OOOOO OOO O

P OOOOO OOO O

vE iE

Diffuse

iB Diff.

P

Diffuse

vB – –– ––––

Diffuse

wB N

P OOOOO OOO O

Diffuse

vE iE

1.4 Bipolar-Junction Transistors

37

loses holes to forward-biased electrons, so iRC falls with lower NB. iC loses so much to these effects when deeply saturated that iC can reverse. But even if only lightly saturated, α0 and β0 are still lower in saturation than in the active region. C. Symbol Engineers design PNPs so collectors receive most of the holes that emitters inject. This way, when active, iB is very low. The orthogonal wall-like line out of which iB in Fig. 1.34 flows represents the base of the PNP for this reason, because a short base effectively blocks this iB. In this mode, only the base–emitter junction forward-biases. So in a PNP, the emitter–base voltage vEB is positive and iB flows into the emitter and out of the base. To illustrate this diode-like behavior, an arrow between the emitter and base terminals points in the direction of iB: toward the base. D. Modes Forward Active In forward active, the base–emitter junction forward-biases and the base–collector junction reverses. So vEB is positive and vCB is negative. vEC is therefore higher than vEB and iC in Fig. 1.35 is exponential with vEB and linear with vEC when the PNP is forward active.

Fig. 1.34 PNP BJT symbol

iE vEB vEC iB

p+ n p–

iC Fig. 1.35 P+NP– collector current

Deep Sat.

Light Sat. vEB3 > vEB2

vEC = vEB

vEB2 > vEB1

vEC ≤ vEC(MIN) iC

Cut Off vCB1 > 0 V vCB2 > vCB1 vCB3 > vCB2

Rev. Act. Light Sat.

vEB1 > 0 V

Forward Active vEC Deep Sat.

38

1

Diodes and BJTs

Forward Saturation The forward-active PNP saturates when the base–collector junction forward-biases. This happens when vEC falls below vEB. iC along this active–saturation boundary rises exponentially with the vEB that vEC’s saturation point sets. But when the base–collector junction forward-biases by less than 200 mV or so, the effects of saturation are negligible. iC falls noticeably when this junction forward-biases by more, which happens when vEC falls below vEC(MIN). Reverse Modes Due to its symmetry, the PNP is reversible. So reverse modes behave the same way. But when asymmetrically doped, the higher-doped end injects more charge carriers into the base than the lighter-doped side under similar conditions. So the higher-doped terminal is, by convention, the emitter. This is why α0, β0, and iC are higher in forward active and saturation (when the forwardbiased base–emitter junction dominates) than in reverse active and saturation (when the forward-biased base–collector junction dominates). Cut Off All currents fade when both junctions zero-bias or reverse. So iC is zero when vEB and vCB are both zero and negative. The x axis in Fig. 1.35 marks this mode because iC is zero along that line.

Example 10: Determine iC and iB when vEB is 650 mV, vE is 4 V, vC is 0 V, βF is 50 A/A, IS is 50 fA, nI is 1, and VA is 50 V at 27  C. Solution:  iC  IS



vEB exp nI Vt



 1

v 1 þ EC VA











650m 4 1 1þ ¼ ð50f Þ exp 50 ð1Þð25:9mÞ

¼ 4:3 mA iB 

iC 4:3m ¼ ¼ 86 μA 50 βF

1.4 Bipolar-Junction Transistors

39

Explore with SPICE: See Appendix A for notes on SPICE simulations. * PNP BJT: I-V Curves ve ve 0 dc¼5 vb vb 0 dc¼4.35 vc vc 0 dc¼1 q1 vc vb ve pnpbjt 1 .model pnpbjt pnp bf¼50 va¼50 is¼50f .op .dc vc 4.98 0 10m vb 4.35 4.40 10m .end Tip: Plot –ic(Q1), comment or remove .dc line, re-run the simulation, and view the output/log file.

1.4.3

Dynamic Response

A. Small Variations Shifting the operating point of the diodes in the BJT requires charge qD. And supplying or removing this qD requires time. In the BJT, iB and iC supply or remove the qD that base–emitter and base–collector junction capacitances CBE and CBC need. Engineers often use variables Cπ and Cμ to refer to CBE and CBC. Base–Emitter Capacitance Junction capacitance CJ includes two components: the charge held across the depletion region in CDEP and the charge held in-transit in CDIF. Since the base–emitter junction is zero- or reverse-biased in cut off, CBE(DIF) does not hold charge in those regions. So CBE reduces to CBE(DEP) when vBE is low, zero, or negative: 300500mV     ∂iC I  CBEðDIFÞ  τF  C τF  gm τF , Vt ∂vBE

ð1:35Þ

Since small variations in iC/vBE are roughly the linear translation that iC’s partial derivative ∂iC/∂vBE or IC/Vt or small-signal transconductance gm sets, CBE reduces to CBE(DIF)’s gmτF. Base–Collector Capacitance Since the base–collector junction only forward-biases in saturation, CBC(DIF) does not hold charge when the BJT activates or cuts off. So CBC in Fig. 1.36 reduces to CBC(DEP) in the active and cut-off regions when vCE nears, matches, or surpasses vBE: v vCEðMINÞ vCE v ðMINÞ Cμ vCE  CBC jvCE vCE BE CE vBE CJBC0 A CJBC0 '' AJBC CJBC0 '' ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  CBCðDEPÞ ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ rJBC  : vCB VBI  vBC v  v BE 1þ 1 þ CE VBI VBI V BI

ð1:36Þ CJBC0 here is CBC’s zero-bias capacitance, AJBC is the cross-sectional area of the base–collector junction, and CJBC0'' is CJBC0 per unit area. Forward-biasing the base–collector junction increases the charge that CBC(DIF) holds exponentially. But when lightly saturated, the effect is so minimal that CBC(DEP) dominates. So CBC is nearly CBC(DEP) when vCE matches or surpasses vCE(MIN). In deep saturation, however, CBC(DIF) holds more charge than CBC(DEP). So below vCE(MIN), CBC is largely the in-transit charge that CBC(DIF) holds with vBC. Note that CBC is much lower than CBE when lightly saturated and activated.

Log Capacitance

Fig. 1.36 BJT capacitances

C BE Deep Sat. CBC(D

EP)

0

Light Sat.

Active

C BC CJBC0 C BC(DIF) vCE(MIN) vBE

vCE

1.4 Bipolar-Junction Transistors

41

Example 11: Determine CBE and CBC for the NPN BJT in Example 9 when τF is 100 ps, CJBC0 is 100 fF, and VBI is 650 mV. Solution:

∴

CBE

vBE ¼ 650 mV ¼ VBI ¼ 650 mV  

I 4:3m ð100pÞ ¼ 17 pF  CDIF  C τF ¼ Vt 25:9m

vBC ¼ vBE  vCE ¼ 650m  4 ¼ 3:35 V < 0 V ∴

CJBC0 100f ffi ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi CBC  CDEP ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi ¼ 40 fF vBC 1  VBI 1  3:35 650m

Note: CBE is usually much greater than CBC in forward active.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * NPN BJT: Capacitance vc vc 0 dc¼4 vb vb 0 dc¼650m q1 vc vb 0 npnbjt 1 .model npnbjt npn is¼50f va¼50 bf¼50 tf¼100p cjc¼100f vjc¼650m þmjc¼0.5 .op .end Tip: View the output/log file. B. Large Transitions BJTs activate after iB and iC supply the depletion and in-transit charge qBE(DEP) and qBE(DIF) that the base–emitter junction requires. To saturate, iB and iC must

42

1

Diodes and BJTs

Fig. 1.37 Schottky-clamped BJT

DS

Fig. 1.38 Diode-connected NPN and PNP BJTs

iD vBE

vEB iD

similarly supply the qBC(DEP) and qBE(DIF) that the base–collector junction requires. So when used as a switch, the BJT activates and saturates after iB and iC supply this charge. The BJT cuts off after iB and iC reverse this charge. These large transitions require substantial iB and, when iB is low, substantial recovery time tR because qBE(DIF) and qBC(DIF) are high. Keeping the base–collector junction from entering deep saturation reduces qBC(DIF) to qBC(DEP) levels. This way, tR can be shorter. A Schottky diode across the base and collector (like DS in Fig. 1.37) achieves this by shunting current away from the base–collector junction. Since DS drops less voltage than the PN junction, DS “clamps” vBC to a level that keeps the PN junction from forward-biasing too much. This way, deep saturation does not occur, so qBC(DIF) is always as low as or lower than qBC(DEP). And DS does not cancel the resulting reduction in tR because DS does not hold in-transit charge.

1.4.4

Diode-Connected BJT

The basic difference between PN diodes and BJTs is that BJTs split the diode current into its constituent electron and hole parts. In the NPN, for example, the forwardbiased base–emitter junction produces a diode current iD that flows entirely out of the emitter. Of iD, the collector supplies the electron component iD– the base supplies the hole component iD+. Similarly, the PNP steers iD+ of the diffused emitter current iD into the collector and iD– into the base. The base-to-collector connection in Fig. 1.38 combines and forces both parts to flow through one collector–base terminal. This connection combines the diode current that BJTs normally split. This way, BJTs behave like diodes, inducing a diode current iD that climbs exponentially with vBE in the NPN and vEB in the PNP. Engineers call this a diode connection. This connection essentially shorts and deactivates the base–collector junction. In other words, diode connections reduce BJTs to their base–emitter junctions. Sometimes this connection is implicit, like when other transistors or components connect these base and collector terminals together.

1.5 Summary

43

Example 12: Determine vBE when iC is 1 mA for the NPN BJT in Example 9. Solution:      vBE v iC ¼ 1 mA  IS exp  1 1 þ BE nI Vt VA  



vBE v ¼ ð50f Þ exp  1 1 þ BE 50 ð1Þð25:9mÞ ∴

vBE ¼ 620 mV

Note: The effect of base-width modulation (vCE) is minimal when VA is 10 V or greater.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * NPN BJT: Diode-Connected ic 0 vbe dc¼1m q1 vbe vbe 0 npnbjt 1 .model npnbjt npn is¼50f va¼50 bf¼50 .op .end Tip: View the output/log file.

1.5

Summary

Thermal energy can liberate and avail loosely bound electrons. When exposed to an electric field, these electrons and the holes they leave behind drift in opposite directions. Conductors, semiconductors, and insulators conduct these charge carriers easily, moderately well, and poorly, respectively. Dopant atoms add electrons or

44

1

Diodes and BJTs

holes to semiconductors, so the resulting N- or P-type material avails more of one than the other. Between these, electrons flow more easily than holes. The carrier concentration difference across a PN junction is so high that electrons and holes diffuse across, leaving behind a depleted carrier-free region. This process continues until the electric field they establish keeps other carriers from diffusing. Reinforcing the field with a reverse voltage keeps carriers from flowing. Opposing the field with a forward voltage, on the other hand, avails an exponentially increasing number of carriers for conduction. Only a negative diode current can reverse and drain these in-transit carriers. Schottky diodes behave essentially the same way, except the metallic side is so full of electrons and void of holes that the metal does not deplete and holes do not diffuse into the semiconductor. Since diffusing carriers are immediately available for conduction, Schottkys are faster than PN diodes. Plus, their built-in field is usually lower, so they drop a lower voltage when they conduct. BJTs are two head-to-head or back-to-back PN diodes with a short P- or N-type base. They activate when one diode forward-biases and the other reverses. The base is so short that, biased this way, diffused minority carriers reach the other end of the base, where the field of the reversed diode pulls them to the collector. When the emitter’s doping concentration is much higher than that of the base, the majority carriers that the base feeds are much lower than the minority carriers that feed the collector. In other words, collector current is a much greater fraction of emitter current than base current is. Forward-biasing the collector junction steers majority carriers away from the emitter. So emitter–collector and base–collector current translations fall. The reduction is lower when the collector is lightly doped and when the forward-biasing voltage across the base–collector junction is low. Reversing and draining forwardbias charges with limited base current requires considerable time. Schottky-clamped BJTs need less time because Schottkys do not hold in-transit carriers. Switched-inductor power supplies need transistors to energize the inductor. Although they are not always BJTs, all MOSFETs incorporate unintended BJT structures, so understanding BJTs is essential. Plus, BJTs usually cost less money. Diodes are more basic and vital because they do not require a synchronizing signal to switch. So they can not only drain the inductor automatically but also steer current when transistors are busy transitioning between states.

2

Field-Effect Transistors

Abbreviations BJT CMOS DIBL DMOS EHP FET JFET LDMOS LDD MOS NBTI RSS SNR SiO2 VCO VDMOS AJ β0 CCH CDB CDEP CGB CGD CGS CJ CJ0 COL

Bipolar-junction transistor Complementary MOS Drain-induced barrier lowering Diffused-channel or double-diffused MOS Electron–hole pair Field-effect transistor Junction FET Lateral DMOS Lightly doped drain Metal–oxide–semiconductor Negative bias temperature instability Root sum of squares Signal-to-noise ratio Silicon dioxide Voltage-controlled oscillator Vertical DMOS Junction area Base–collector current gain Channel capacitance Drain–body capacitance Depletion capacitance Gate–body capacitance Gate–drain capacitance Gate–source capacitance Junction capacitance Zero-bias junction capacitance Overlap capacitance

# The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 G. A. Rincón-Mora, Switched Inductor Power IC Design, https://doi.org/10.1007/978-3-030-95899-2_2

45

46

COX CSB dW EBG ECN/P EF EK ε0 εOX fC fO fSW ΔfBW gm γN/P iB iD iDIF iFLD iG iIN inc inf ins int iS iSUB ISN/P KB KF KN/P KN/P' LCH LMIN LOL LOX or L λN/P μN μP nd nI qE RCH RON RDS

2

Oxide capacitance Source–body capacitance Depletion width Band-gap energy Critical electric field Fermi energy level Kinetic energy Permittivity in vacuum Relative permittivity of SiO2 Noise-corner frequency Operating frequency Switching frequency Frequency bandwidth Small-signal transconductance Body-effect parameter Body current Drain current Diffusion current Drift current Gate current Input current Coupled noise current Flicker noise current Shot noise current Thermal noise current Source current Substrate current Saturation current Boltzmann’s constant Flicker noise coefficient Baseline conductivity Transconductance parameter Channel length Minimum oxide length Overlap length Oxide length Channel-length modulation parameter Electron mobility Hole mobility Spectral noise density Ideality factor Electronic charge Channel resistance On resistance Drain–source resistance

Field-Effect Transistors

Abbreviations

RSH tOX TJ vB vBS vD vDD vDS vDS(SAT) vDS(SAT)' vDS(SAT)'' vE vG vGS vGSP, vGST, and vSGT vH vJR vnt vS vTN/P VA VBI VP Vt VTN/P0 ψB ψS wB WCH or W

47

Sheet resistivity Oxide thickness Junction temperature Body terminal/voltage Body–source voltage Drain terminal/voltage Positive power supply Drain–source voltage Drain–source pinch-off saturation voltage Drain–source sub-threshold saturation voltage Drain–source velocity-saturation voltage Electron velocity Gate terminal/voltage Gate–source voltage Gate drive Hole velocity Reverse junction voltage Thermal noise voltage Source terminal/voltage Threshold voltage Early voltage Built-in (potential) voltage Pinch-off voltage Thermal voltage Zero-bias vTN/P Surface–body barrier potential Surface potential Effective base width Channel width

Power supplies use switches to steer and feed current into batteries and microelectronic systems. Metal–oxide–semiconductor (MOS) field-effect transistors (FETs) are popular in this space because they drop millivolts and do not require static gate current to close. Although bipolar-junction transistors (BJTs) usually cost less to fabricate, they need static base current to close and saturate when they close, so they require substantial reverse current to open. Diodes do not need this static current, but they drop 400–700 mV and only close when terminal voltages allow. Still, MOSFETs incorporate substrate diodes and BJTs that can help and at times also hurt. The fundamental mechanism that establishes conductivity in FETs is an electric field. In the case of MOSFETs, parallel-plate MOS capacitors establish this field. The underlying purpose of the capacitor is to form a conducting N-type channel in NFETs and a P-type channel in PFETs. Although poly-silicon is nowadays more

48

2

Field-Effect Transistors

popular than metal as the upper plate, engineers still use MOS to refer to these and other oxide-sandwiched structures on semiconductors.

2.1

Junction FETs

The junction FET (JFET) is a simpler junction-based realization of the MOSFET. Although not as pervasive, JFETs are useful as resistors and low-noise transistors. Electronic noise in JFETs is low because carriers flow well below (and away from) the uneven silicon surface.

2.1.1

N Channel

N-channel JFETs are N-doped semiconductor strips sandwiched between P-type regions. In the case of Fig. 2.1, top and bottom P+ and P gates sandwich an N channel contacted by highly doped N+ regions. Channel length LCH or L and width WCH or W are the longitudinal length and transverse width of the overlapping P+–N channel–P gate layers. The Ohmic surface contact of the bottom gate (on the left in Fig. 2.1) is another highly doped P+ region. A. Triode The NJFET is basically an N-type resistor compressed by P-type regions. The geometry and doping concentration of the channel set the baseline channel resistance RCH. RCH increases as the depletion space against the top and bottom P regions in Fig. 2.2 expands to squeeze the channel. These P regions are the gates vG of the JFET because their voltages adjust RCH. RCH is high when L is long, W is narrow, and baseline conductivity KN is low. The channel dematerializes (and opens) when the gate–channel voltage reverses Fig. 2.1 N-channel JFET structure

P+ P+

N+

P Gate

N+

H

WC

N Ch.

LCH

Fig. 2.2 Uniformly biased N-channel JFET in triode

vS P+

P Gate

VP < vGS ≈ vGD < 0 vD ≈ v S N+

P + Gate

N+

N Channel

Depletion Regions

2.1 Junction FETs

49

enough to pinch the entire channel. This negative vG is the pinch-off voltage VP. So RCH spikes sharply when vGS and vGD reach this VP: >VP  RCH jvvGS DS VP ¼ iD jvvGS DS >vGSP

ð2:3Þ

This iD corresponds to saturation because iD is sensitive to vGS and largely insensitive to vDS. This is another way of saying iD saturates with respect to vDS. Since a higher vD depletes more of the channel, LCH' shrinks as vDS increases, which means RCH falls and iD increases. This is channel-length modulation. Channel-length modulation parameter λN models this effect with respect to the L that circuit designers define. Interestingly, the effects of vDS fade as L lengthens. This is because the variation in LCH' becomes a smaller fraction of L. So drain current iD becomes less sensitive to vDS, which is another way of saying λN is lower. C. I–V Translation iD is sensitive to vDS in triode and largely insensitive to vDS in saturation like Fig. 2.5 shows. Since N+ regions can reverse roles, negative vGD and vDS establish a negative iD that mirrors the iD that a negative vGS and a positive vDS produce. iD is zero (in cut off) when vGS and vGD reach VP. The x axis represents this mode because iD is zero along that line. iD saturates when vDS overcomes vDS(SAT)’s vGSP. Since iD is a quadratic translation of vGSP in saturation, the vDS(SAT) boundary in Fig. 2.5 is a squared-root reflection of iD: vDSðSATÞ

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iD ¼ vGS  VP  : ðW=LÞKN ð1 þ λN vDS Þ

ð2:4Þ

λNvDS fades with longer L’s because LCH' modulation diminishes. Fig. 2.5 N-channel JFET current

vDS = vDS(SAT) = vGS – VP

Cut Off

vGS2 < v GS3

iD

vGS1 < v GS2

Triode Saturation

VP < v GS1 ≤ 0

Saturation vDS

VP < v GD1 ≤ 0 vGD1 < vGD2 vGD2 < vGD3

Triode vSD = vSD(SAT) = vGD – VP

2.1 Junction FETs

51

Fig. 2.6 N-channel JFET symbol

iD

iG

vDS vGS

iS

D. Symbol JFETs are three-terminal devices with interchangeable vS and vD terminals that conduct iD in Fig. 2.6 when vGS is zero or negative and vDS is positive. The two vertical lines into which vG connects symbolize the PN depletion capacitance that pinches the channel. Gate current iG is close to zero because vG reverse-biases the gate–channel junction. So source current iS outputs almost all the iD that vD receives. The arrow indicates the P gate and N channel form a PN junction.

Example 1: Determine iD when vD is 4 V, vG and vS are 0 V, W/L is 1, KN is 100 μA/V2, VP is 2 V, and λN is 5%. Solution: vDS ¼ vD  vS ¼ 4  0 ¼ 4 V

and vGS ¼ vG  vS ¼ 0  0 ¼ 0 V

vDS ¼ 4 V > vDSðSATÞ ¼ vGS  VP ¼ 0  ð2Þ ¼ 2 V

∴

Saturated



 W KN ðvGS  VP Þ2 ð1 þ λN vDS Þ L 2
 100μ ½0  ð2Þ2 ½1 þ 5%ð4Þ ¼ ð 1Þ 2 ¼ 240 μA

iD 

Explore with SPICE: See Appendix A for notes on SPICE simulations. NJFET: I-V Curves vd vd 0 dc¼4 vg vg 0 dc¼0 vs vs 0 dc¼0 j1 vd vg vs njfet 1 .model njfet njf beta¼50u vto¼-2 lambda¼50m (continued)

52

2

Field-Effect Transistors

.op .dc vd 0 5 10m vg 0 -1 100m .end Tip: Plot id(J1), comment or remove the .dc line, re-run simulation, and view the output/log file.

2.1.2

P Channel

PJFETs are and operate exactly the same way as NJFETs, except with a P channel. So top and bottom N+ and N gates in Fig. 2.7 sandwich a P channel contacted by highly doped P+ regions. LCH or L and WCH or W are the longitudinal length and transverse width of the overlapping N+–P channel–N gate layers. A highly doped N+ region (on the left in Fig. 2.7) contacts the bottom gate. A. Triode The PJFET is basically a P-type resistor compressed by N-type regions. RCH is high when L is long, W is narrow, and KP is low. The channel dematerializes (opens) when the gate–channel voltage reverses enough to pinch the entire channel. So RCH spikes sharply when vSG and vDG reach VP: >VP RCH jvvSG SD vSGP

 
vSDðSATÞ vSDðSATÞ  W ¼  vSDðSATÞ KP vSG  VP  RCH 2 LCH '

 W KP  ðvSG  VP Þ2 ð1 þ λP vSD Þ: L 2

ð2:7Þ

LCH' shrinks as vSD climbs because a lower vD depletes more of the channel. This means that RCH falls and iD increases. Lengthening L reduces λP because variations in LCH' become a smaller fraction of L. C. I–V Translation iD is sensitive to vSD in triode and largely insensitive to vSD in saturation like Fig. 2.9 shows. Since P+ regions can reverse roles, negative vDG and vSD establish a negative iD that mirrors the iD that a negative vSG and a positive vSD produce. iD is zero in cut off when vSG and vDG reach VP. iD saturates when vSD overcomes vSD(SAT)’s vSGP. Since iD is a quadratic translation of vSGP in saturation, the vSD(SAT) boundary in Fig. 2.9 is a squared-root reflection of iD:

54

2

Field-Effect Transistors

Fig. 2.10 P-channel JFET symbol

vSG

iS vSD

iG

vSDðSATÞ

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iD ¼ vSG  VP  : ðW=LÞKP ð1 þ λP vSD Þ

iD

ð2:8Þ

λPvSD fades with longer L’s because LCH' modulation diminishes. D. Symbol PJFETs conduct iD in Fig. 2.10 when vSG is zero or negative and vSD is positive. iG is close to zero because vG reverse-biases the gate–channel junction. So iD outputs nearly all the iS that vS receives. The arrow indicates the N gate and P channel form a PN junction and the parallel lines next to it symbolize the capacitance that the junction establishes.

Example 2: Determine iD when vS and vG are 5 V, vD is 1 V, W/L is 1, KP is 50 μA/ V2, VP is 2 V, and λP is 5% V1. Solution: vSD ¼ vS  vD ¼ 5  1 ¼ 4 V

and vSG ¼ vS  vG ¼ 5  5 ¼ 0 V

vSD ¼ 4 V > vSDðSATÞ ¼ vSG  VP ¼ 0  ð2Þ ¼ 2 V

 W KP ðv  VP Þ2 ð1 þ λP vSD Þ iD  L 2 SG 50μ ½0  ð2Þ2 ½1 þ 5%ð4Þ ¼ ð 1Þ 2 ¼ 120 μA

∴

Saturated

2.2 N-Channel MOSFETs

55

Explore with SPICE: See Appendix A for notes on SPICE simulations. * PJFET: I-V Curves vs vs 0 dc¼5 vg vg 0 dc¼5 vd vd 0 dc¼1 j1 vd vg vs pjfet 1 .model pjfet pjf beta¼25u vto¼-2 lambda¼50m .op .dc vd 5 0 10m vg 5 6 100m .end Tip: Plot is(J1), comment or remove the .dc line, re-run the simulation, and view the output/log file.

2.2

N-Channel MOSFETs

The N-channel MOSFET is a smaller and slightly more involved NJFET. Structurally, a MOS capacitor is on P-type material that constitutes the body or bulk of the transistor. The thin oxide SiO2 in the MOS capacitor in Fig. 2.11 sets the oxide length LOX or L of the FET and, together with the N+ regions, the width of the channel WCH or W to be established under this oxide. LCH is the distance between these highly doped N+ regions. The N+ terminals extend into the oxide region (across overlap length LOL) to ensure they connect to the N channel that the oxide field forms. The highly doped P+ region (on the left of the structure in Fig. 2.11) is an Ohmic surface contact to the body.

2.2.1

Accumulation: Cut-Off

Thin Oxide Poly-Silicon Gate SiO2 P+

N+

P Body LOL

LCH LOX

CH

Fig. 2.11 N-channel MOSFET structure

W

The P body usually connects to the most negative potential (ground in Fig. 2.12) to keep body–N+ junctions from forward-biasing. So the electrons and holes that diffuse recombine and deplete the regions near those junctions. Applying a negative

N+ LOL

56

2

Fig. 2.12 N-channel MOSFET in accumulation and cutoff

Field-Effect Transistors

vG < 0

P+

N+

P Body

N+

OOOOOOOOOOOO

Depletion Regions

Fig. 2.13 N-channel MOSFET in depletion

0 < vG < vTN P+

N+

N+

OOOOOOOOO

P Body Fig. 2.14 Band diagram of N-channel MOSFET in depletion

0 < vG < vTN – –– ––––

N+

EF

E BG

– –– ––––

N+

vG to the poly-silicon gate pulls holes in the body toward the oxide. Holes therefore accumulate near the surface of the semiconductor. This way, in accumulation, current cannot flow. So the NFET is in cut off.

2.2.2

Depletion: Sub-threshold

Applying a positive vG does the opposite: pushes holes away from the semiconductor surface in Fig. 2.13. This depletes the region under the oxide of holes. With fewer holes with which to recombine, N+ electrons diffuse farther before recombining. A positive vG also pulls and loosens electrons from their N+ home sites. So vG reduces the barrier voltage that keeps N+ electrons from diffusing and extends their diffusion length. In depletion, the carrier density near the surface under the oxide falls to the point of becoming nearly intrinsic. This is why the Fermi energy level EF in this region in Fig. 2.14 is nearly halfway across the band gap EBG. Without any voltage between the N+ regions, current does not flow. Raising the voltage of one of the N+ terminals (vD in Fig. 2.15) elevates the barrier and expands the depletion region around that terminal. The resulting electric field ɛFLD pulls diffusing electrons into vD. As ɛFLD intensifies, more electrons (that would otherwise recombine) reach vD. Recombination nearly stops when vD is three to four thermal voltages Vt’s over vS, which is equivalent to 75–100 mV or so at room temperature.

2.2 N-Channel MOSFETs

57

Fig. 2.15 Band diagram of N-channel MOSFET in sub-threshold

0 < vGS < vTN – –– –––––

Diffuse

D rif t

E

vS

N

FL D

+

Source vDS

Fig. 2.16 Voltage divider across gate oxide and surface– body terminals

COX

– –– –––––

N+

vD

Drain

iD

vG

vG COX

N+ CDEP

N+ \S

CDEP

\S

P Body

vD is the drain because the N+ terminal with the higher potential drains these diffusing electrons. And vS is the source because the terminal with the lower potential supplies these electrons. The resulting flow of electrons establishes an iD that flows into vD and out of vS. A. Triode iD rises with vGS because a positive gate–source voltage reduces the gate–source barrier. This rise is exponential because vGS avails exponentially more electrons than junction temperature TJ avails with Vt: iD j

0vTN ¼ iD jvvGS DS vTN vDS = vDS(SAT) –

qD

vGS – vDS = vTN

N+

P+

P Body

Fig. 2.20 Inverted N-channel MOSFET in saturation

N+

vGS > vTN vDS > vDS(SAT) LCH '

vGS – vDS < vTN

N+ vDS(SAT)

62

2

Fig. 2.21 Inverted N-channel MOSFET current

vDS = vDS(SAT) = vGS – vTN

Cut Off

Field-Effect Transistors

vGS3 > vGS2

iD

Triode

vGS2 > vGS1 v GS1 > v TN

Saturation vDS

Saturation v GD1 > vTN vGD2 > vGD1 vGD3 > vGD2

>vTN RCH jvvGS DS >vGST

Triode vSD = vSD(SAT) = vGD – vTN

#  " LCH ' vGS  vTN W 0:5KN ' ðvGS  vTN Þ2 

 3 L 1 >vTN  : ¼ 1:5RCH jvvGS DS LMIN rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iD :  ðW=LÞKN '

vDSðSATÞ ¼ vGS  vTN 

ð2:16Þ

λN diminishes as L extends beyond the minimum oxide length possible LMIN because LCH' modulation is a small-ER fraction of a long-ER L.

Example 4: Determine vDS(SAT) when iD is 100 μA, vDS is 1 V, W is 10 μm, L is 180 nm, LOL is 30 nm, KN' is 200 μA/V2, and λN is 2%.

2.2 N-Channel MOSFETs

63

Solution:

vDSðSATÞ

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ð100μÞ½180n  2ð30Þ 2iD ¼  ð10μÞð200μÞ½1 þ ð2%Þð1Þ ðWCH =LCH ÞKN ' ð1 þ λN vDS Þ ¼ 110 mV

2.2.4

Body Effect

vGS induces a field through COX that avails electrons for vDS to pull. The body– source or bulk–source voltage vBS also avails electrons the same way via CDEP. So the P+ body terminal in Fig. 2.11 is a bottom gate. A positive vBS in NFETs pulls electrons into the channel and a negative vBS repels some of the electrons that vGS avails. So vBS effectively reduces vTN: vTN ¼ VTN0 þ γN


pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi 2ψB  vBS  2ψB :

ð2:17Þ

vTN is the baseline zero-bias threshold VTN0 when vBS is zero. vTN is the voltage that vGS overcomes to invert a channel. To invert in equal proportion, vGS should not only negate the surface–body barrier potential ψB but also re-assert another ψB in the opposite direction. vBS reduces this 2ψB translation. So vBS alters vTN by the amount that the body-effect parameter γN allows. This is the body or bulk effect, where ψS is 2ψB in inversion and γN and ψB can be 600 m√V and 300 mV, respectively.

Example 5: Determine vTN when VTN0 is 400 mV, vBS is 100 mV, γN is 600 m√V, and ψB is 300 mV. Solution:
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi 2ψB  vBS  2ψB
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 400m þ ð600mÞ 2ð300mÞ þ 100m  2ð300mÞ ¼ 440 mV

vTN ¼ VTN0 þ γN

64

2

Field-Effect Transistors

Note: A negative vB repels channel electrons back to vS, so vGS needs to overcome a higher vTN to induce conduction.

Example 6: Determine vTN when VTN0 is 400 mV, vBS is 100 mV, γN is 600 m√V, and ψB is 300 mV. Solution:
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi 2ψB  vBS  2ψB
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 400m þ ð600mÞ 2ð300mÞ  100m  2ð300mÞ ¼ 360 mV

vTN ¼ VTN0 þ γN

Note: A positive vB pulls vS electrons into the channel region, so vGS induces conduction more easily (with a lower vTN).

Explore with SPICE: See Appendix A for notes on SPICE simulations. * NMOSFET: Body Effect vbs vbs 0 dc¼100m m1 0 0 0 vbs nmosfet w¼10u l¼180nm .model nmosfet nmos vto¼400m kp¼200u ld¼30n lambda¼100m +gamma¼600m phi¼600m .op .end Tip: View the output/log file.

2.2 N-Channel MOSFETs

65

Fig. 2.22 N-channel MOSFET symbols

iD iG = 0 vDS vGS

vBS iS = i D

2.2.5

Symbols

The NMOS is a four-terminal device with interchangeable vS and vD terminals that conduct iD in Fig. 2.22 when vGS and vDS are positive. The two vertical lines at the gate symbolize the oxide capacitance that induces an N-type channel. Static gate current iG is zero because dc current into this COX is zero. So iD is also the iS that flows out of vS. The arrow attaches to the vS terminal that sets vGS and points in the direction of iS. The symbol sometimes excludes the body terminal to indicate other transistors share the same body. In these cases, independent access to the body is not possible. The arrow is also sometimes absent to show that source and drain terminals can reverse roles – this is typical in digital circuits. Although less of a convention, some switching power supplies add arrows to both terminals to indicate iD can reverse direction.

Example 7: Determine iD when vD is 3 V, vG is 2 V, vS is 1 V, vB is 0 V, W is 10 μm, L is 1 μm, KN' is 200 μA/V2, VTN0 is 400 mV, γN is 600 m√V, ψB is 300 mV, and λN is 5%. Solution: vDS ¼ vD  vS ¼ 3  1 ¼ 2 V

vTN

vGS ¼ vG  vS ¼ 2  1 ¼ 1 V vBS ¼ vB  vS ¼ 0  1 ¼ 1 V pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi ¼ VTN0 þ γN ð 2ψB  vBS  2ψB Þ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 400m þ ð600mÞ 2ð300mÞ  ð1Þ  2ð300mÞ ¼ 690 mV

vDS ¼ 2 V > vDSðSATÞ ¼ vGS  vTN ¼ 1  690m ¼ 310 mV

∴

Saturation

66

2

Field-Effect Transistors


 '  W KN iD  ðvGS  vTN Þ2 ð1 þ λN vDS Þ 2 L  
 10μ 200μ ð1  690mÞ2 ½1 þ 5%ð2Þ ¼ 110 μA ¼ 1μ 2

Explore with SPICE: See Appendix A for notes on SPICE simulations. * NMOSFET: I-V Curves vd vd 0 dc¼3 vg vg 0 dc¼2 vs vs 0 dc¼1 vb vb 0 dc¼0 m1 vd vg vs vb nmosfet w¼10u l¼1u .model nmosfet nmos vto¼400m kp¼200u lambda¼50m gamma¼600m +phi¼600m .op .dc vd 1 5 10m vg 2 3 200m .end Tip: Plot id(M1), comment or remove the .dc line, re-run the simulation, and view the output/log file.

2.3

P-Channel MOSFETs

Thin Oxide Poly-Silicon Gate SiO2 N+

P+

N Body LOL

LCH LOX

CH

Fig. 2.23 P-channel MOSFET structure

W

PFETs and NFETs operate the same way, except PFETs rely on holes for conduction. So the PMOS structure is the complement of the NMOS. In PFETs, the WCH  LOX MOS capacitor in Fig. 2.23 hangs over N material and overlaps highly doped P+ regions (across LOL) that are LCH apart. The P+ terminals extend into the oxide region to connect them to the P channel that the oxide field forms. The highly doped N+ region (on the left in Fig. 2.23) is an Ohmic surface contact to the body.

P+ LOL

2.3 P-Channel MOSFETs

2.3.1

67

Accumulation: Cut Off

The N body usually connects to the most positive potential (positive power supply vDD in Fig. 2.24) to keep P+N junctions from forward-biasing. So the electrons and holes that diffuse recombine and deplete the regions near those junctions. Applying a positive vG to the gate pulls electrons in the body toward the oxide. As a result, electrons accumulate near the semiconductor surface. This way, in accumulation, current cannot flow, so the PFET is in cut off.

2.3.2

Depletion: Sub-threshold

Applying a negative vG does the opposite: pushes electrons away from the semiconductor surface in Fig. 2.25, which depletes the region under the oxide of electrons. With fewer electrons with which to recombine, P+ holes diffuse farther before recombining. A negative vG also presses bound electrons into their home sites, which eases hole movement. So vG reduces the barrier voltage that keeps P+ holes from diffusing and extends their diffusion length. The carrier density near the surface under the oxide falls to the point of becoming nearly intrinsic. EF in this region in Fig. 2.26 is therefore nearly halfway across EBG. But without any voltage between the P+ regions, current does not flow. Decreasing the voltage of one of the P+ terminals elevates the barrier and expands the depletion region around that terminal (vD in Fig. 2.27). The resulting field pulls diffusing holes into vD. As ɛFLD intensifies, more diffusing holes that would Fig. 2.24 P-channel MOSFET in accumulation and cutoff

vG > 0 vDD N+

P+

N Body

P+

–––––––––––––

Depletion Regions

Fig. 2.25 P-channel MOSFET in depletion

vTP < v G < 0 N+

P+

P+

–––––––––––––

N Body Fig. 2.26 Band diagram of P-channel MOSFET in depletion

vTP < v G < 0

E BG

P+

P+

EF OOO O

OOO O

68

2

Field-Effect Transistors

Fig. 2.27 Band diagram of P-channel MOSFET in sub-threshold

vTP < v G < 0 P+

vD

Drain i D

vS Source

E

OOO O

Diffuse

D FL

OOO O

D rif t

P

+

vSD

otherwise recombine reach vD. Recombination nearly stops when vD is 3 or 4 Vts below vS. The negative terminal is the drain because vD outputs diffusing holes. The positive terminal is the source because vS supplies these holes. The resulting flow of holes establishes an iD that flows into vS and out of vD. A. Triode iD increases with vSG because a positive vSG reduces the gate–source barrier. This rise is exponential because vSG avails exponentially more holes than TJ avails with Vt: iD j

0 vSD(SAT) P+ vSD(SAT)

Fig. 2.31 Inverted P-channel MOSFET in saturation

vSD: vSD  vSD(SAT). iD saturates because the voltage across the channel that LCH' establishes is vSD(SAT), which is independent of vSD:  
vSDðSATÞ vSDðSATÞ  W ¼ vSDðSATÞ KP ' vSG  jvTP j  RCH 2 LCH '
 '  W KP  ðvSG  jvTP jÞ2 ð1 þ λP vSD Þ 2 L  
 '  W KP vSD 2 vSGT 1 þ  : 2 L VAP

>jvTP j ¼ iD jvvSG SD >vSGT

ð2:22Þ

So iD is sensitive to vSG and largely insensitive to vSD. Since a lower vD depletes more of the channel, LCH' shrinks as vSD increases. So RCH falls and iD rises with vSD. λP models this LCH' modulation with respect to the L that circuit designers define. The effects of vDS fade as L lengthens because the variation becomes a smaller fraction of L, which is equivalent to saying λP decreases and VAP increases. Since CGS falls with LCH', vSG pulls fewer source holes into the P channel when L is shorter, which means RCH is higher. Although a shorter LCH' also increases conduction, the field effect of CGS is dominant. So RCH is roughly 50% higher in saturation than in triode: vSDðSATÞ iD #  " vSG  jvTP j LCH ' ¼ W 0:5KP ' ðvSG  jvTP jÞ2 

 3 L 1 >jvTP j  : ¼ 1:5RCH jvvSG SD >vSGT 2 W 0:5KP ' ðvSG  jvTP jÞ

>jvTP j RCH jvvSG ¼ SD >vSGT

ð2:23Þ

RCH, however, is only a fraction of RDS in saturation. RDS is usually much higher than RCH because iD is largely insensitive to vDS. C. I–V Translation iD in inversion is sensitive to vSD in triode and insensitive to vSD in saturation like Fig. 2.32 shows. Since P+ regions can reverse roles, a positive vDG and a negative vSD establish a negative iD that mirrors the iD that positive vSG and vSD produce. iD is zero when vSG and vDG are negative.

2.3 P-Channel MOSFETs Fig. 2.32 Inverted P-channel MOSFET current

73

vSD = vSD(SAT) = vSG – |vTP|

Cut Off

vSG3 > vSG2

iD

Triode

vSG2 > vSG1 v SG1 > |vTP|

Saturation vSD

Saturation v DG1 > |vTN | vDG2 > vDG1 vDG3 > vDG2

Triode vDS = vDS(SAT) = vDG – |vTP |

In inversion, iD is a squared translation of vSGT and iD saturates when vSD overcomes vSGT. So the vSD(SAT) boundary in Fig. 2.32 is a squared-root reflection of iD: vSDðSATÞ ¼ vSG  jvTP j rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2iD 2iD   :  ðW=LÞKP ' ð1 þ λP vSD ÞL>>LMIN ðW=LÞKP '

ð2:24Þ

λPvSD fades as L extends beyond LMIN because LCH' modulation becomes a smaller fraction of L.

Example 9: Determine W so vSD(SAT) is no greater than 110 mV, iD is 100 μA, vSD is 1 V, L is 180 nm, LOL is 30 nm, KP' is 40 μA/V2, and λP is 2%. Solution:

vSDðSATÞ

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ð100μÞ½180n  2ð30nÞ 2iD ¼  ' WCH ð40μÞ½1 þ ð2%Þð1Þ ðWCH =LCH ÞKP ð1 þ λP vSD Þ 110 mV ∴ W  WCH 49 μm

Note: W is 5 wider than the NMOS in Example 4 because μP in KP' is that much lower than μN in KN'.

74

2.3.4

2

Field-Effect Transistors

Body Effect

vSG induces a field through COX that avails holes for vSD to pull. The source–body or source–bulk voltage vSB also avails holes the same way via CDEP. So the N body terminal in Fig. 2.23 is a bottom gate. A negative vB (positive vSB) in the PMOS pulls holes into the channel and a positive vB repels some of the holes that vSG avails. So vSB effectively reduces |vTP|: jvTP j ¼ jVTP0 j þ γP


pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi 2ψB  vSB  2ψB :

ð2:25Þ

|vTP| is the baseline VTP0 when vSB is zero. |vTP| is the voltage that vSG overcomes when inverting a channel. To invert in equal proportion, vSG should not only negate the barrier ψB but also re-assert another ψB in the opposite direction. vSB reduces this 2ψB translation and alters |vTP| by the amount that γP allows.

2.3.5

Symbols

The PMOS is a four-terminal device with interchangeable vS and vD terminals that conduct iD in Fig. 2.33 when vSG and vSD are positive. The two vertical lines at the gate symbolize the COX that induces a P-type channel. iG is zero because dc current into COX is zero. So iD is also the iS that flows into vS. The arrow attaches to the vS that sets vSG and points in the direction of iS. The symbol sometimes excludes the body terminal to indicate other transistors share the same body. In these cases, independent access to the body is not possible. The arrow is also sometimes absent in digital circuits to show that source and drain terminals can reverse roles or on both terminals in switching power supplies to show they can reverse roles. A “bubble” next to the gate distinguishes arrowless PFETs from NFETs. This indicates, like in a digital inverter, that PFETs “invert” the action of NFETs. Fig. 2.33 P-channel MOSFET symbols

iS = i D vSG

vSB vSD

iG = 0 iD

2.3 P-Channel MOSFETs

75

Example 10: Determine iD when vB is 5 V, vS is 4 V, vG is 3 V, vD is 2 V, W is 10 μm, L is 1 μm, KP' is 40 μA/V2, VTP0 is 400 mV, γP is 600 m√V, ψB is 300 mV, and λP is 5%. Solution: vSD ¼ vS  vD ¼ 4  2 ¼ 2 V vSG ¼ vS  vG ¼ 4  3 ¼ 1 V vSB ¼ vS  vB ¼ 4  5 ¼ 1 V
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi 2ψB  vSB  2ψB jvTP j ¼ jVTP0 j þ γP
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ j400mj þ ð600mÞ 2ð300mÞ  ð1Þ  2ð300mÞ ¼ 690 mV vSD ¼ 2 V > vSDðSATÞ ¼ vSG  j vTP j¼ 1  690m ¼ 310 mV ∴ Saturated
 '  W KP iD  ðvSG  jvTP jÞ2 ð1 þ λP vSD Þ 2 L  
 10μ 40μ ¼ ð1  690mÞ2 ½1 þ 5%ð2Þ ¼ 23 μA 1μ 2

Explore with SPICE: See Appendix A for notes on SPICE simulations. * PMOSFET: I-V Curves vb vb 0 dc¼5 vs vs 0 dc¼4 vg vg 0 dc¼3 vd vd 0 dc¼2 m1 vd vg vs vb pmosfet w¼10u l¼1u .model pmosfet pmos vto¼-400m kp¼40u lambda¼50m gamma¼600m +phi¼600m .op .dc vd 4 0 10m vg 3 2 200m .end Tip: Plot is(M1), comment or remove the .dc line, re-run the simulation, and view the output/log file.

76

2.3.6

2

Field-Effect Transistors

Unifying Convention

PFETs and NFETs function the same way. Accumulation, depletion, and inversion result, respectively, when vGS in NFETs and vSG in PFETs are negative, positive and below vTN and |vTP|, and positive and above vTN and |vTP|. iD saturates when vDS in NFETs and vSD in PFETs reach vDS(SAT)' and vSD(SAT)' in sub-threshold and vDS(SAT) and vSD(SAT) in inversion. vTN and |vTP| decrease when vBS in NFETs and vSB in PFETs are positive. Everything that is positive in one is negative in the other. In PFETs, vGS, vDS, and vTP are negative, and a negative vBS reduces vTP. So NFETs and PFETs deplete when vGS reverses, invert when vGS overcomes vT’s vTN or vTP, and saturate when vDS overcomes the vDS(SAT)' or vDS(SAT) that 3Vt or vGS  vT sets. So general vGS, vDS, vBS, and vT discussions apply to both: NFETs and PFETs.

2.4

Capacitances

The terminals of the MOSFET require time to charge and discharge. The most noticeable of these is the gate because tOX is very thin (on the order of nanometers), which means the resulting COX" is substantial. Still, PN junction capacitances at the source and drain also require charge and time to transition.

2.4.1

PN Junction Capacitances

Body terminals normally connect to voltages that zero- or reverse-bias their PN junctions to sources and drains. A reverse junction voltage vJR reinforces the diminishing effect that the built-in potential VBI induces on zero-bias junction capacitance (per unit area) CJ0''. So junction capacitance CJ peaks to the CJ0 that CJ0'' and junction area AJ set and vJR reduces CJ to CJ0 '' AJ CJ0 ffi ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffi ffi, CJ ¼ qffiffiffiffiffiffiffiffiffiffiffiffi vJR VBI þvJR 1 þ V V BI

ð2:26Þ

BI

where CJ0'' and VBI depend strongly on the body’s doping concentration. Although source and drain geometries do not always match, AJ’s are usually the same or comparable. vSB, however, is usually lower than vDB. So source–body capacitance CSB is normally higher than drain–body capacitance CDB. vJR’s in NFETs are vSB and vDB and in PFETs are vBS and vBD. Although not necessarily so, doping densities in NFETs and PFETs usually differ. CJ0'' in NFETs is therefore different in PFETs.

2.4 Capacitances

77

Fig. 2.34 Gate-oxide capacitances C OX C CH

Acc. Off

Dep. Sub-v T

Inversion Sat. Triode

CGB CGS , CGD

C OL

0

2.4.2

C OL + (2/3)C CH

CGS

0.5C OX

CGS , CGD C OL + (1/2)CCH

CGD

vT

vT + vDS

vGS

Gate-Oxide Capacitances

Oxide capacitance decomposes into overlap and channel components. Overlap capacitance COL is the COX fraction that hangs over source and drain diffusions (along WCH and across LOL in Figs. 2.11 and 2.23): COL ¼ COX '' WCH LOL :

ð2:27Þ

Channel capacitance CCH is the LCH fraction of LOX along WCH that LOL’s over source and drain diffusions exclude: CCH ¼ COX '' WCH LCH ¼ COX '' WCH ðLOX  2LOL Þ:

ð2:28Þ

But since the channel does not always extend across LCH, COX decomposes into gate components differently across regions in Fig. 2.34. A. Cut-Off In accumulation, the region under the oxide in Figs. 2.12 and 2.24 is a good Ohmic contact to the body. This means that CCH connects the gate to the body, so gate–body capacitance CGB comprehends all of CCH in Fig. 2.34. Since the gate overlaps the source and drain diffusions across LOL, gate–source and gate–drain capacitances CGS and CGD only incorporate COL. So in cut off, the largest fraction of COX is in CGB. CSB and CDB are the CJ’s that their AJ’s and vJR’s set. B. Sub-threshold When depleted, a depletion region separates the semiconductor surface (in Figs. 2.13 and 2.25) from the body. So CCH stacks over CDEP and CGB is the series combination that results:  CGB ¼ CCH  CDEP ¼

1 1 þ CCH CDEP

MinfCCH , CDEP g:

1 ¼

CCH CDEP CCH þ CDEP ð2:29Þ

78

2

Field-Effect Transistors

Like parallel resistors, the series combination is lower than the smaller capacitance. CGB is therefore lower than CCH and CDEP. And since the depletion region widens with higher vGS’s, CGB falls with CDEP as vGS rises. With so little conduction in sub-threshold, COL is dominant in CGS and CGD, and CJSB and CJDB are dominant in CSB and CDB. C. Triode Inversion When inverted in triode, a channel across the semiconductor surface connects vS and vD. CCH therefore connects to vG and the channel and CDEP to the channel and vB. Since vS and vD both connect to the channel, CGS and CGD share CCH, and CSB and CDB share CDEP. So combined, CGS and CGD incorporate their COL’s plus matching CCH halves: CGS=GDðTRIÞ ¼ COL þ 0:5CCH ,

ð2:30Þ

and CSB and CDB incorporate their CJ’s plus matching CDEP halves: CSB=DBðTRIÞ ¼ CJSB=DB þ 0:5CDEP :

ð2:31Þ

In other words, CGS and CGD carry equal COX fractions. Note that FETs invert into triode when vGS overcomes vT + vDS because vDS overcomes vDS(SAT)’s vGS  vT when this happens. Also notice that CGS, CGD, CSB, and CDB model all capacitances present in triode inversion. CGB is the series combination of CDEP (which is very low in inversion) and the CCH that CGS and CGD model (and vS and vD affect). D. Saturated Inversion Inverted MOSFETs saturate when vGD or vGS  vDS drops below vT, which happens when vGS is between vT and vT + vDS. In this mode, the channel (in Figs. 2.20 and 2.31) disconnects from vD and shortens to LCH'. So CDB is CJDB and CGD is only the COL that LOL sets. Since the channel still connects to vS, CSB carries CJSB plus the CDEP fraction that LCH' sets, and CGS carries COL plus a similar fraction of CCH: CSBðSATÞ  CJSB þ ð2=3ÞCDEP

ð2:32Þ

CGSðSATÞ  COL þ ð2=3ÞCCH ,

ð2:33Þ

where this fraction is roughly two-thirds. The CCH and CDEP fractions near vD that LCH' excludes are no longer in CGD and CDB. CGB carries these fractions, but since CGD is the series combination of these fractions and CDEP and CDEP is much lower, CGB is usually negligible. In this mode, the largest fraction of COX is in CGS.

2.4 Capacitances

79

Example 11: Determine CGS and CGD in saturation when W is 10 μm, L is 180 nm, LOL is 30 nm, and COX'' is 2.76 fF/μm2. Solution: COL ¼ COX '' WCH LOL ¼ ð2:76mÞð10μÞð30nÞ ¼ 0:83 fF CCH ¼ COX '' WCH LCH ¼ COX '' WCH ðLOX  2LOL Þ ¼ ð2:76mÞð10μÞ½180n  2ð30nÞ ¼ 3:3 fF CGS ¼ COL þ ð2=3ÞCCH ¼ 0:83f þ ð2=3Þð3:3f Þ ¼ 3:0 fF CGD ¼ COL ¼ 0:83 fF

Explore with SPICE: See Appendix A for notes on SPICE simulations. * NMOSFET: Capacitance in Saturated Inversion vd vd 0 dc¼600m m1 vd vd 0 0 nmosfet w¼10u l¼180n .model nmosfet nmos vto¼400m kp¼200u tox¼12.5n ld¼30n cgso¼83p +cgdo¼83p .op .end Tip: View the output/log file. E. Transition CGS and CGD share CCH equally when inverted in triode and vDS is zero. As vDS rises, the charge in the channel shifts toward the source. So CGS acquires the corresponding CCH fraction that CGD in Fig. 2.35 loses. This continues until the channel pinches, when vDS reaches vDS(SAT)’s vGS  vT. As the channel recedes from the drain past vDS(SAT), the source and drain lose a small but growing fraction of CCH to the body. As a result, CGS acquires less of CCH than CGD loses as vDS rises past vGS  vT. This continues until CGD’s fraction fades and CGS’s share maxes to two-thirds. CGS and CGD reach their saturation limits when vDS matches vGS.

80

2

Fig. 2.35 Inverted gate– source and gate–drain capacitances

Field-Effect Transistors

Triode

C OL + (2/3)C CH C OL + (1/2)CCH

Saturation CGS

vGS > vT

CGD

C OL

0 C OX

Dep.

Inv.

vDS

vG

CG vB

Acc.

vGS

C CH

vG

vGS – vT

vB

CG

2COL

0

|vTP |

vBG

Fig. 2.36 Bi-modal P-channel MOSFET varactor

2.4.3

MOS Varactors

A. Bi-modal The MOS structure is fundamentally a parallel-plate capacitor with a thin dielectric. When used as a capacitor, paralleling all oxide components yields the highest capacitance. The PMOS in Fig. 2.36 combines all capacitive components by shorting vS, vB, and vD terminals. This way, gate capacitance CG incorporates CGS, CGB, and CGD: CG ¼ CGS þ CGB þ CGD 2COL þ CCH ¼ COX ¼ COX '' WCH LOX :

ð2:34Þ

When a positive vG (negative vBG) accumulates electrons in the channel region, CGB is CCH, so CG includes CGS and CGD’s 2COL and CGB’s CCH. When a vBG that is greater than |vTP| inverts the channel that connects vS and vD, CGS and CGD each carry COL and half of CCH. So even though CGB is very low, CGS and CGD in CG still carry 2COL and CCH. When a negative vG (positive vBG) depletes the channel region without inverting it, CGB becomes the series combination of CCH and CDEP. As vBG climbs, vG depletes more of the body, so CDEP decreases, and with it, CGB. So as vBG rises above zero toward |vTP|, CG loses CGB’s CCH, falling from COX to the 2COL that CGS and CGD carry. This structure is useful as a capacitor because CG is high at COX when vBG is negative and greater than |vTP|. CG is not a perfect variable capacitor or varactor because CG is not monotonic with vBG. A rise in vBG does not always raise CG because CG is bi-modal. (The PMOS symbol in Fig. 2.36 has two “source” arrows to indicate both P+ diffusions supply holes when inverting the channel.)

2.4 Capacitances

81

B. Inversion Mode Disconnecting vB from vS and vD removes CGB from CG. This way, the CCH and CDEP that CGB in Fig. 2.34 adds in accumulation and depletion disappear from CG in Fig. 2.37. So CG’s transition between 2COL and COX is now monotonic with vSG. The drawback to this inversion-mode varactor is that the vSG range that changes CG is usually narrow. (vB connects to the highest potential to reverse-bias the PN junctions that connect vS and vD to vB.) C. Accumulation Mode CGB’s transition in depletion in Fig. 2.34 is more gradual than CGS and CGD’s in inversion. A gradual transition is appealing because extending the voltage range that transitions capacitance is usually desirable in a varactor. So the purpose of the accumulation-mode structure in Fig. 2.38 is to eliminate the inversion mode from the bi-modal case. The fundamental difference here is that the body is the same type of material as the source and drain. So the body connects the two N+ terminals when vGS is zero. The line across the source/drain terminals of the NMOS in Fig. 2.38 represents this connection. A positive vGS reinforces this connection because it pulls and accumulates electrons under the oxide. A negative vG, however, repels electrons and depletes the channel. This way, depletion reduces CG from COX to 2COL. Since no part of the structure can avail holes, the channel never inverts.

C OX

vG

Acc.

Dep.

Inv.

C CH

vG

CG vS

vS

CG

2COL

0

|vTP |

vSG

Fig. 2.37 Inversion-mode P-channel MOSFET varactor

vG

vG

C OX

Depletion

Acc.

vG

C CH

vS

CG N

+

N

N Body

+

vS

2COL

vS

0 Fig. 2.38 Accumulation-mode N-channel MOSFET varactor

vGS

82

2

Field-Effect Transistors

D. Variations The varactors in Figs. 2.36, 2.37, and 2.38 are P-, P-, and N-channel FETs because most fabrication technologies stack NFETs on P substrates. This means that independent P-type body terminals are not accessible. If they were, N-, N-, and P-channel devices would also be possible. These varactors are useful in voltagecontrolled oscillators (VCO) because their voltages can adjust the frequency that their capacitances set.

2.4.4

MOS Diodes

Another useful application of MOSFETs in power supplies and other analog circuits are as diodes. Key to their realization is CGS, first as a stand-alone component and then as the agent that induces conduction. The other critical element is an inverting feedback loop. A. Diode Connection In Fig. 2.39, the drain–gate connections close a feedback loop around CGS and the channel that induce the MOSFETs to behave like diodes. The NMOS, for example, is off when vS is grounded and vG is low. But when a circuit feeds an input current iIN into the drain–gate node, iIN charges CGS. When vGS overcomes vT, channel current iD begins to sink some of iIN. The rest of iIN continues to charge CGS until iD is able to sink all of iIN, at which point CGS stops charging. So in effect, iIN “forwardbiases” the NFET. Since vDS equals vGS, vDS is usually greater than the 3Vt that sets vDS(SAT)'. So if iIN is not high enough to invert a channel, the MOSFET saturates in sub-threshold. This means that vGS is a logarithmic translation of iIN that vT offsets:  vGS  vT þ nI Vt ln

 iIN < vT : ðW=LÞISN

ð2:35Þ

When iIN inverts a channel, vDS is also greater than the vGS  vT that sets vDS(SAT) because vDS matches vGS. So the MOSFET inverts into saturation. vGS is therefore not only a vDS(SAT) reflection but also a squared-root translation of iIN that vT offsets:

Fig. 2.39 N- and P-channel MOSFET diodes

i IN vGS

vSG i IN

2.4 Capacitances

83

Fig. 2.40 Implicit N- and P-channel MOS diode action

i IN

vG vSG vGS i IN

vGS ¼ vT þ vDSðSATÞ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iIN :  VTN0 þ γN 2ψB  vBS  2ψB þ ðW=LÞK' ð1 þ λvDS Þ

vG

ð2:36Þ

Note that body effect alters vT, LCH' modulation alters vDS(SAT), and LCH' modulation is higher when L is shorter. When iIN is no longer present, iD discharges CGS to vT in inversion and below vT in sub-threshold. So iIN activates and cuts off diode-connected MOSFETs like iIN would a junction diode. The only difference is that a diode drops a logarithmic translation of iIN and MOSFETs drop a squared-root translation offset by vT. MOS diodes that drop 300–500 mV, however, are often preferable because iIN burns less power across 300–500 mV than across the 600–800 mV that diodes usually establish. Pulling iIN from vS when the gate–drain terminals connect to a voltage that is above ground similarly charges CGS until iD conducts iIN. The PMOS does the same when a circuit feeds or pulls iIN to vS or from the gate–drain node. The only difference is their vGS because vTN and μN do not match |vTP| and μP. B. Diode Action Sometimes this diode action results from an implicit connection. One example is when other circuit components connect gate and drain terminals together. Another example is pulling iIN from vS in Fig. 2.40 when a voltage or a large capacitor holds vG. Here, iIN charges CGS until iS (and whatever connects to vD) supplies iIN. The PMOS does the same when a circuit feeds iIN to vS: iIN charges CGS until iS (and whatever connects to vD) sinks iIN.

Example 12: Determine vS for an NMOSFET when iIN pulls 100 μA from vS, W is 10 μm, L is 180 nm, LOL is 30 nm, KN' is 200 μA/V2, VTN0 is 400 mV, γN is 600 m√V, ψB is 300 mV, λN is 10%, and vB, vG, and vD are 0 V. Solution: LCH ¼ L  2LOL ¼ 180n  2ð30nÞ ¼ 120 nm

84

2

Field-Effect Transistors

vDS ¼ vD  vS ¼ vGS ¼ vG  vS ¼ vBS ¼ vB  vS ¼ 0  vS ¼ vS
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iIN vGS ¼ vS  VTN0 þ γN 2ψB  vBS  2ψB þ ðWCH =LCH ÞKN ' ð1 þ λN vDS Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ð100μÞ ¼ 400m þ 600m 2ð300mÞ þ vS  2ð300mÞ þ ð10μ=120nÞð200μÞð1  10%vS Þ

¼ 340 mV

!

vS ¼ 340 mV

Note: vBS reduces vT more than VDS(SAT) raises vGS. λN suppresses vDS more than γN suppresses vBS, so neglecting LCH modulation yields a similar vGS. These implicit diode conditions are typical for ground NMOSFETs in switched-inductor power supplies. (Example 15 shows why the FET is in inversion.)

Explore with SPICE: See Appendix A for notes on SPICE simulations. * NMOSFET: Diode Action m1 0 0 vs 0 nmosfet w¼10u l¼180n iin vs 0 dc¼100u .model nmosfet nmos vto¼400m kp¼200u ld¼30n lambda¼100m +gamma¼600m phi¼600m .op .end Tip: View the output/log file.

2.5

Short Channels

Smaller geometries are appealing in three basic ways. First, they occupy less silicon area, so FETs cost less and microchips can fit more circuits. Second, capacitances are lower, so FETs require less charge power and less time to transition. And third, electric fields are stronger, so conduction requires less voltage, and as a result, less power. Unfortunately, geometric reductions and stronger electric fields also produce unappealing effects in conductivity and noise that are not always easy to model or counter. These usually surface when LCH is comparable to the depletion widths dW

2.5 Short Channels

85

around the source and drain regions. This is why sub-micron devices suffer from short-channel effects that fade and disappear in longer-channel devices.

2.5.1

Drain-Induced Barrier Lowering

In NFETs, increasing vD in Fig. 2.41 pulls N+ electrons away from the PN junction toward vD’s contact and pushes P-body holes away into the body. So vD’s depletion region expands in all directions. When LCH is comparable to dW’s, vD’s depletion region can extend and merge into vS’s. The merging of two depletion regions this way is punch-through. vD’s field is so close to vS that it pushes holes away from the channel region near vS and loosens nearby electrons. So raising vDS helps deplete and invert the channel. This way, a lower vGS can more easily induce conduction. This means, vDS reduces the barrier voltage vB in Fig. 2.42 that keeps electrons from diffusing. This draininduced barrier lowering (DIBL) effectively reduces vT. This is a problem because vDS can induce current flow with zero vGS. So vG may not be able to cut the NFET off, which is another way of saying vG can lose control of the NFET. Unfortunately, this effect is not static because vD changes with time. In PFETs, vD’s field is so close to vS that it pushes electrons away from the oxide region near vS and presses nearby valence electrons into their home sites. Holes can therefore drift more easily. So PFETs also suffer a dynamic reduction in vT when vD falls.

Fig. 2.41 Drain-induced punch-through

vD P+

P Body

N+

LCH

dW(S)

N+ dW(D)

Fig. 2.42 Drain-induced barrier lowering in an N-channel MOSFET

q EvB

– –– –––––

N+

– –– –––––

N+ vD

86

2

Field-Effect Transistors

Fig. 2.43 Channel coupling components

COX

vG CJD

vS CJS

CJB

vB

Fig. 2.44 Surface scattering and hot-electron injection in the NMOS

vS P+

i G vDS > 0

vGS > vTN –

N+

–––

–– –

vD

\S

–– –

– ––

– –

–

N+

P Body

A. Thinner Oxide The surface potential is ultimately the result of capacitor coupling from vG, vB (via the body effect), and vD (with DIBL). So in the absence of vG and vB, ψS in Fig. 2.43 is the voltage-divided fraction that vD’s depletion capacitance CJD to the channel couples across vG’s COX, vS’s CJS, and vB’s CJB. DIBL is noticeable because short channels increase CJD’s coupling. The effect of COX, CJS, and CJB is to shunt CJD’s coupling. So raising COX reduces DIBL. This is one of the driving reasons why engineers scale tOX with LOX. Another reason is higher current density iD/WCH and vGS-to-iD gain because COX'' in K' climbs with reductions in tOX. Reducing tOX from 25 to 5 nm, for example, can suppress the 250-mV reduction in vT that 100 mV across vDS can produce when LOX is 40 nm.

2.5.2

Gate–Channel Field

A. Surface Scattering Thinner tOX’s intensify vertical gate–channel fields. So on their way to the drain, carriers accelerate and collide with the oxide on the surface of the semiconductor in Fig. 2.44 more often and with greater force. This scattering effect reduces surface mobility and produces noise in iD. Surface scattering intensifies as LCH and tOX scale down. B. Hot-Electron Injection Positive gate–channel fields energize, accelerate, and direct N-channel electrons into the oxide. When charged with sufficient kinetic energy EK, these hot electrons can break into or tunnel through the oxide. Electrons that break into and stay in the lattice (in Fig. 2.44) leave the oxide negatively charged. So over time, a higher vGS is

Fig. 2.45 Fringing electric field lines around an N-channel MOSFET

87

WCH

2.5 Short Channels

N+

vGS > 0

N+

LOX

necessary to deplete and invert the channel, which means vTN increases. And electrons that tunnel through the thin oxide establish a gate current iG. PFETs are largely immune to hot-electron injection because their vGS’s are usually negative, whose effect is to repel electrons. C. Oxide-Surface Ejections In repelling electrons, negative gate–channel fields weaken electron bonds along the silicon–oxide interface. When sustained and at elevated temperatures, they break silicon–hydrogen (Si–H) bonds and dispel negatively charged H atoms into the body. These atoms leave behind positively charged “hole” traps that counter the action of negative vGS’s. So PFETs need a higher vSG to deplete and invert the channel, which means |vTP| increases. But as vSG weakens the field, electrons repopulate holes, so vTP recovers. vTP therefore fluctuates as vSG stresses and relaxes the oxide. This negative bias temperature instability (NBTI) is less prevalent in NFETs because they are less prone to negative vGS’s. D. Fringing Fields Shrinking planar dimensions enhance the effects of fringing fields along the periphery of the gate-oxide region in Fig. 2.45 on the channel. These field lines deplete and invert space outside the WCH that source and drain diffusions define, extending the width of the channel. This WCH variation ΔWCH is negligible in larger FETs, but substantial in sub-micron devices.

2.5.3

Source–Drain Field

A. Velocity Saturation Electron velocity vE in the conduction band scales linearly with voltage up to 100 km/s or so. Hole velocity vH scales similarly, but saturates at 60 km/s or so. vH(SAT) is lower than vE(SAT) because the valence electrons that shift holes are more tightly bound to their home sites than electrons in the conduction band. Their mobility ultimately determines the critical electric fields ɛC that accelerate them to these levels:

88

2

Fig. 2.46 Velocity saturation and pinch-off effects in inversion

Field-Effect Transistors

Long L CH

iD vDS(SAT)

Short LCH vDS(SAT) " EC LCH vGS – v T

vGS > vT

vDS

vEðSATÞ μN

ð2:37Þ

vHðSATÞ : μP

ð2:38Þ

ɛCN ¼ and ɛCP ¼

ɛCN and ɛCP in silicon are 1.4 and 4.2 V/μm at room temperature. ɛCP is higher because μP is lower than μN more than vH(SAT) is lower than vE(SAT). In triode inversion, iD scales with vDS until vDS saturates vE or vH. The velocity saturation voltage vDS(SAT)'' that ɛC across LCH sets is vDSðSATÞ '' ¼ ɛC LCH :

ð2:39Þ

vE and vH therefore saturate when vDS across a 1-μm channel reaches 1.4 and 4.2 V. But if the vDS(SAT) that vGS  vT sets is less than 1.4 V in 1-μm NFETs and 4.2 V in 1-μm PFETs, vE and vH do not saturate. vDS(SAT)'' for sub-micron channels can be so low that iD can saturate before vGD pinches the channel at vDS(SAT). iD in Fig. 2.46, for example, scales with vDS in triode inversion until vDS reaches vGS  vT when LCH is long and ɛCLCH when LCH is short. Normally, MOSFETs begin to suffer from velocity saturation when LCH is less than 1 μm.

Example 13: Determine vDS(SAT)'' and vSD(SAT)'' when LCH is 180 nm. Solution: vDSðSATÞ '' ¼ ɛCN LCH ¼ ð1:4=μÞð180nÞ ¼ 250 mV vSDðSATÞ '' ¼ ɛCP LCH ¼ ð4:2=μÞð180nÞ ¼ 760 mV

2.5 Short Channels

89

Note: vDS(SAT)'' and vSD(SAT)'' are over the 130-mV vDS(SAT) and vSD(SAT) that 10and 50-μm-wide and 180-nm-long N- and P-channel MOSFETs set with 100 μA (from previous examples), so vGD pinches their channels before carrier velocities saturate.

B. Impact Ionization Electrons gain speed and ɛK when source–drain fields intensify. ɛK can be so great that these hot electrons can collide and liberate otherwise immobile electrons from their home sites. Engineers call this process impact ionization because atoms ionize on impact. Each energized electron can free an electron that avails a hole. Two electrons can then gain enough ɛK to liberate another two electron–hole pairs (EHP), like Fig. 2.47 shows. This vDS-induced process repeats, multiplies, and grows in avalanche fashion. Impact ionization is a problem in MOSFETs because, while electrons in NFETs scatter toward the positively charged drain, holes flow into the negatively charged body. Since the body is moderately doped, body resistance drops a voltage that forward-biases vBS’s PN junction. So vS’s N+ electrons also diffuse across the junction into the body. Forward-biasing this body–source junction activates the lateral NPN across the source–body–drain regions. When LCH is very short, the N+ drain “collects” most of the electrons that the N+ source “emits” into the channel. So the NPN draws body current iB from vB and conducts iD. In other words, the NPN can short the NFET with zero vGS. PFETs suffer the same effect, except holes scatter toward the negatively charged drain and electrons flow into the positively charged body. The resulting iB drops a voltage that forward-biases vSB’s PN junction and activates the lateral PNP across the source–body–drain regions. So even with zero vSG, the PNP can short the PFET.

Fig. 2.47 Impact ionization, avalanche, and hot-electron injection

EDC

vG vB P+ iB

vS + N – O

–

–

––

–O – O

– O OO

vDS >> 0

– ––

N+

O

P Body

90

2

Fig. 2.48 Lightly doped drain MOSFETs

Oxide Spacers N+ P Body

Oxide Spacers N+

N

–

Field-Effect Transistors

P+ N Body

P+ P

–

C. Arcing Field Shrinking planar dimensions enhance the effects of arcing channel–drain field ɛDC lines that pass through the gate oxide near the drain in Fig. 2.47. This ɛDC intensifies as LOX shortens, vD rises, and the vDS(SAT) across the channel that vGS  vT sets falls. LOX in sub-micron devices is so short and lateral and arcing fields are so intense as a result that N-channel electrons can gain enough ɛK to break into the oxide and stay there. These hot electrons charge the oxide, increasing vTN. D. Lightly Doped Drain In triode inversion, the channel drops vDS across LCH. When pinched, the channel drops the vDS(SAT) that vGS  vT sets across LCH'. So the depletion region between the drain and channel drops the remainder vDS  vDS(SAT) or vDG + vT across LCH  LCH'. Of these distances, LCH  LCH' is the shorter. So the most intense field usually results across this short drift space. This field intensifies when LCH shortens and vDG rises. Outside of lengthening LCH and reducing vDG, the only other way of weakening this field is by extending vD’s depletion length between the drain and the channel. The lightly doped drain (LDD) regions in Fig. 2.48 do this by depleting farther into the drain. Because with fewer carriers, vD depletes farther into the LDD region. This way, the resulting drift length is longer than LCH  LCH'. For this, engineers first implant LDD dopants into the silicon without the oxide spacers shown. Then, with the spacers, implanting more dopants forms the highly doped regions without altering the LDDs. Both source and drain regions receive LDDs because they swap roles when iD reverses. Only the voltage at the terminal that acts as the drain can deplete, leaving the source largely intact. This practice reduces impact ionization, avalanche, and electron injection. And since LDDs are shallow and lightly doped, vD depletes less channel space, so DIBL is also lower.

2.6

Other Considerations

2.6.1

Weak Inversion

Not surprisingly, inverting the channel does not keep carriers from diffusing across source–drain terminals. In fact, vDS induces carriers to both diffuse and drift. And vGS determines to what extent.

2.6 Other Considerations

91

Log iD

Fig. 2.49 Drain current as MOSFET channel forms

Sub-v T Weak Inv. Inv.

i D(FLD) i D(DIF)

vT

vGS

Deep in sub-threshold, when vGS is well below vT in Fig. 2.49, drift current iFLD is so low that diffusion current iDIF dominates iD. And iFLD is so high in strong inversion, when vGS is well above vT, that iFLD dwarfs iDIF. Near vT, iDIF and iFLD are comparable. In this context, vT is the vGS that produces matching iDIF and iFLD components. So in weak inversion, as the channel forms, iD reflects both conduction mechanisms. Solving accurate sub-threshold and inversion expressions for every single transistor across time in a system that incorporates thousands if not billions of transistors can be time-consuming for a computer. To save computing time, computer algorithms model one region well and estimate the other. Or if they model both regions well, they approximate weak inversion. So for more predictable and reliable operation, engineers often design MOSFETs to operate deep in sub-threshold or in strong inversion. A. Voltage Bias Digital circuits and switching power supplies normally use MOSFETs as switches. These FETs close and open into the on and off states that vGS determines. The vGS that closes FETs is usually much greater than vDS because vDS is only millivolts after FETs close. FETs open when vGS is zero. So these FETs switch between triode and cut off and saturate only during transitions. When closed, they are in sub-threshold when vGS cannot overcome vT and in inversion when vGS can. To assert the least and most resistive on and off states, circuit designers normally apply the highest and lowest vGS’s possible. When voltages higher than vT are not available, MOSFETs cannot invert a channel when they close. So they switch between sub-threshold and cut off. Inversion is only possible when voltages higher than vT are available, in which case on resistance RON is RCH in triode inversion. B. Current Bias Amplifiers and linear power supplies normally bias FETs at particular vGS–vBS– vDS–iD settings. Then, they vary one or two of these variables and use variations in one or two of the others to drive other circuits into action. vGS is normally 0.5–2 V and vDS is higher than 300 mV. So for the most part, these FETs operate in saturation

92

2

Field-Effect Transistors

or on the edge of saturation. In other words, triode operation is less likely in these applications. Analog performance is sensitive to bias conditions, so current and voltage settings should be predictable and stable. Predicting and stabilizing a vGS-defined iD is difficult, for example, because iD is sensitive to vGS and vT, vGS is noisy, and vT varies across fabrication corners. Defining vGS with iD is usually better because the exponential and quadratic vGS terms that set iD in sub-threshold and inversion suppress the vGS variations that changes in iD produces. This is why iD (instead of vGS) is usually one of the design parameters used to bias transistors in analog circuits. Inverting a MOSFET, however, is not an option when voltages higher than vT are not available. But it is otherwise. Still, analog designers often prefer sub-threshold for low-power consumption because both voltages and currents are low. They like inversion for high speed because the higher currents that inversion induces charge and discharge capacitances faster. Since vGS is an indirect logarithmic or square-root translation of iD that vT shifts, ensuring iD-biased MOSFETs are in sub-threshold or inversion is not straightforward. Luckily, what usually matters most to analog design engineers is predictable small-signal performance. And this hinges on small-signal transconductance gm' because gm translates small-signal variations in vGS on iD and vice versa. Small vGS signals are so much smaller than vGS that a linear slope translation can approximate their effect on iD fairly well. This gm slope is iD’s first partial derivative ∂iD/∂vGS with respect to vGS. Since vGS is within an exponential term in iD in sub-threshold, ∂iD/∂vGS matches iD, but with vGS’s 1/nIVt coefficient as a multiplier: GS v DSðSATÞ

ð2:48Þ

So RCH is 1/gm in triode and 1.5/gm in saturation. Since tOX is thinner with shorter LCH’s, surface scattering in short-channel devices raises RCH in saturation to 2/gm or 3/gm. So RCH’s 1/gm to 3/gm generates thermal noise. Shot Electrons “shoot” through gaps randomly. Diodes, BJTs, JFETs, and MOSFETs all suffer from this shot noise because their electrons cross the drift space that their respective depletion regions establish. The resulting shot noise current ins is proportional to electronic charge qE and intensifies with higher conduction iD: 2 2 Z ins ¼ ins ¼ 2qE iD : Δf BW df O

ð2:49Þ

Shot noise is so random in nature that it spreads evenly across frequency. So like thermal noise, shot noise is also a form of white noise. ins is therefore the statistical sum of individual strengths across ΔfBW. Flicker Like the “flicker” of a flame, flicker noise is mostly a low-frequency phenomenon. In electronics, it refers to 1/f noise because noise power falls with fO

100

2

Field-Effect Transistors

n d [dB]

Fig. 2.55 Spectrum of flicker and thermal (white) noise

n dw n df

fC

Log f O [Hz]

at 20 dB per decade. It is a form of pink noise (from audio engineering) for this reason. Since flicker noise ndf fades with fO, white noise ndw in Fig. 2.55 overpowers ndf past the noise corner frequency fC, where ndf and ndw cross. fC is an indirect measure of noise content nd because fC increases with higher ndf. In other words, ndf is more powerful when fC is higher. Slow carriers have more time to recombine (when crossing PN junctions and BJT bases) and to fall into surface oxide traps (when crossing MOS channels) than fast carriers. Slow carriers also have more time to scatter (along the oxide surface when crossing MOS channels) than fast carriers. So the noise that these random mechanisms produce fades with fO. Flicker noise is usually worse in MOSFETs than in BJTs and JFETs because the effects of random recombination on conduction are less severe than oxide irregularities and scattering along the oxide surface. The NMOS is worse in this respect because their channel electrons are more loosely bound than the valence electrons that shift holes in the PMOS. BJTs and JFETs generate less 1/f noise because they conduct well beneath the surface of the semiconductor, where the silicon structure is less imperfect. Surface effects in MOSFETs are more profound across shorter channels because surface defects are a larger fraction of the channel. More intense vGS fields and higher conduction increases their effects. So flicker noise current inf climbs with lower LCH and COX'' and higher iD: 2 KF iD Z inf ¼ : COX '' LCH 2 f O df O

ð2:50Þ

Traps and their effects on scattering are so dependent on the fabrication process that engineers normally derive the flicker noise coefficient KF empirically from measurements. Side Note: Brown noise falls quadratically with fO. This noise is relevant in audio engineering because low-frequency 1/f2 noise can overpower 1/f noise. In electronics, pink 1/f noise is usually more powerful, so brown 1/f2 noise is less discernable and, as a result, less relevant.

2.7 Summary

101

C. Systemic Noise Coupling As capacitances charge and discharge, they draw and supply displacement currents. When capacitances are the unintended byproducts of devices, these currents become and produce coupled noise current inc. inc appears everywhere because all components incorporate capacitances. inc is systemic because the capacitances and voltages that produce inc depend entirely on the circuit. inc is therefore consistent and predictable over time. Substrate capacitances that result from junction isolation are especially problematic because they couple noise into the shared substrate. So the substrate collects, integrates, and spreads this noise to every component embedded in the substrate. Large digital blocks and switching power supplies, for example, generate switching noise at their switching frequency fSW that normally appears almost everywhere in the system. Injection The effects of forward-biasing substrate junctions are more severe. This is because iSUB can be higher and more sustained. Substrate and well resistances can therefore drop voltages that de-bias parasitic substrate diodes and lateral and vertical BJTs into action. Audio amplifiers, power supplies, and power amplifiers are more prone to injection because they conduct lots of power at near-breakdown voltages. So impact ionization and avalanche currents are more likely to flow into and across the substrate and wells. Switched inductors in power supplies are also more likely to feed and forward-bias these junctions.

2.7

Summary

MOSFETs are the evolutionary offspring of JFETs. And JFETs are nothing but resistors that gate fields pinch with their depletion regions. What is perhaps most interesting is that current saturates when the channel voltage saturates. Past this vDS(SAT), iD is only sensitive to vGS. MOSFETs similarly use fields to alter channel resistance. But to invert channels, vG should overcome vT. Their channel regions deplete below vT and accumulate opposite charge carriers when vG reverses. vG in sub-threshold reduces the barrier that carriers must overcome to diffuse, vG in inversion pulls carriers into the channel, and vDS propels all these carriers across the channel. vD, however, opposes vGD’s barrier reduction and charge formation until iD saturates. In inversion, vD pinches and saturates the channel voltage like JFETs. Also like JFETs, vB is a bottom gate that can reinforce or counter the action of vG. Without a channel, CGB incorporates all the oxide capacitance to the channel region. CGS and CGD are low in cut off because gates overlap sources and drains across a very short LOL. CGB, however, loses CCH to CGS and CGD when the channel forms. And when vD pinches the channel, CGB loses its share of CCH to CGS and

102

2

Field-Effect Transistors

CGD, but mostly to CGS because the inverted channel is a large fraction of LCH that still connects to vS. When paralleled, these capacitances become a bi-modal varactor. Disconnecting or reversing the semiconductor type of the body eliminates the non-monotonicity that bi-modal behavior engenders. And connecting the gate and source closes a feedback loop around CGS that converts the MOSFET into a diode. Short channels are desirable in microelectronics because microchips can fit more transistors and perform more functions. Unfortunately, the depletion region that vD induces when LCH is short reaches so far into the channel that it reinforces the action of vG. Thinning the oxide helps shunt the effect of vD on the channel. But the stronger gate–channel and source–drain fields that result induce surface scattering, hot-electron injection, oxide-surface ejections, velocity saturation, and impact ionization. Reducing vD’s doping concentration helps because it extends the short drain– channel drift region, which weakens the lateral field. As MOSFETs invert, drift and diffusion currents compete. Luckily, switching applications switch between cut off and triode. So predicting iD accurately across short-lived transitions is not critical. To avoid this relatively unpredictable region of operation, analog designs often bias MOSFETs deep in sub-threshold or in strong inversion. Noting that MOSFETs effectively “invert” their channels when vDS(SAT) surpasses 2nIVt is helpful in this respect. When integrated into the same substrate, substrate and welled MOSFETs incorporate substrate diodes and source–drain and substrate BJTs. Engineers zero- or reverse-bias all substrate PN junctions to deactivate unintended components and isolate designed-in devices. Diffusing a body region under the source that extends to a lightly doped N-well drain extends vDS’s breakdown limit. These diffused-channel MOSFETs cost more because they require additional fabrication steps. Thermal energy, conduction across depleted spaces, and silicon-surface imperfections produce random electronic noise in iD. Substrate capacitances also couple and spread circuit-generated noise. The effects of near-breakdown operation are worse because impact-ionization currents de-bias substrate diodes and BJTs into action. Systems with large switching transistors, like switched-inductor power supplies, usually suffer the most from noise coupling and injection.

3

Switched Inductors

Abbreviations BJT FET LED MOS RMS CCM DCM ASi dD DDG DDO dE dIN dO dX EM EL fLC fO fSW iIN iL iL(HI) iL(LO) iL(MIN) iL(PK) iO

Bipolar-junction transistor Field-effect transistor Light-emitting diode Metal–oxide–semiconductor Root-mean-squared Continuous-conduction mode Discontinuous-conduction mode Silicon area Drain duty cycle Ground drain diode Output drain diode Energize duty cycle Input duty cycle Output duty cycle Coil distance Magnetic energy Inductor energy LC resonant frequency Operating frequency Switching frequency Input current Inductor current Inductor current’s peak in CCM Inductor current’s valley in CCM Minimum inductor current Inductor current’s peak in DCM/peak variation in PDCM Output current

# The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 G. A. Rincón-Mora, Switched Inductor Power IC Design, https://doi.org/10.1007/978-3-030-95899-2_3

103

104

iXI/O ΔiL ΔiLD kC kL KN/P' LCH LX MDG MDO MEG MEI PDD PDT PIN PL PLOSS PO PR RCH RD RE RL RL(AC) RL(DC) RESR RSER SDG SDO SEG SEI tC tD tDT tE tSW tLC τLC σLOSS vB vD vDI vE vEI vG

3 Switched Inductors

Input/output-referred transformer current Inductor CCM ripple current Load dump Coupling factor/coefficient Transformer translation MOS transconductance parameter MOS channel length Switched transfer inductor Ground drain MOSFET Output drain MOSFET Ground energize MOSFET Input energize MOSFET Diode drain power Dead-time power Input power Inductor power Power losses Output power Ohmic power MOS channel resistance Drain resistance Energize resistance Inductor resistance Inductor ac resistance Inductor dc resistance Equivalent series resistance Series resistance Ground drain switch Output drain switch Ground energize switch Input energize switch Conduction time Drain time Dead time Energize time Switching period LC resonant period LC time constant Fractional losses Body voltage Drain voltage Ideal drain voltage Energize voltage Ideal energize voltage Gate voltage

3.1 Transfer Media

vIN vL vL ' vO vS vSW vSWI vSWO vTN/P ΔvO WCH

105

Input node/voltage Intrinsic inductor voltage Extrinsic inductor voltage Output node/voltage Source voltage Switching node/voltage Input switching node/voltage Output switching node/voltage N/P-channel MOS threshold voltage Output voltage ripple MOS channel width

The fundamental purpose of power supplies is to transfer power. Switched inductors (SLs) are pervasive in this space because they output a large fraction of the power they draw from an input source. The fundamental reason for this is low Ohmic losses, and that’s because switches in the network only drop millivolts. So the Ohmic power PR these switches burn when they conduct current is low. This means that power-conversion efficiency ηC, which is the fraction of input power PIN delivered to the output, is usually high, between 85% and 95% when PIN is moderate to high. This is because output power PO is the PIN that power losses PLOSS avail. So fractional losses σLOSS, which is the fraction of PIN lost to PLOSS, are what determine and limit ηC: ηC


PO PIN  PLOSS P ¼ ¼ 1  LOSS ¼ 1  σLOSS : PIN PIN PIN

ð3:1Þ

In the absence of these losses, switched inductors deliver all the PIN they draw. Diode switches, however, consume power and drop voltages that alter some of the switching characteristics of the circuit. Resistors produce similar effects, but to a lesser extent because resistances are (by design) very low. Either way, the basic mechanics are the same.

3.1

Transfer Media

3.1.1

Inductor

A. Ideal Inductor Inductors magnetize and demagnetize with voltages of opposing polarity. In other words, they energize and drain their magnetic fields with positive and negative voltages. So as the alternating inductor voltage vL in Fig. 3.1 raises and lowers

106

3 Switched Inductors

inductor current iL across time tX, the magnetic or inductor energy EM or EL that the transfer inductor LX holds rises and falls quadratically with iL:
iL ¼

 vL t LX X

EM
EL ¼ 0:5LX iL 2 :

ð3:2Þ ð3:3Þ

+vL is the energize voltage +vE that magnetizes LX and vL is the drain voltage vD that demagnetizes LX. But since iL can also flow in the opposite direction, vL can be the +vE that energizes LX and +vL the vD that drains LX. Notice +vL in Fig. 3.1 supplies power when iL flows to the right and sinks power when iL flows to the left. vL similarly supplies power when iL flows to the left and sinks power when iL flows to the right. LX’s inductance is a measure of how much energy iL can hold. So a higher LX holds more energy with the same current than a lower LX. Since more magnetic space stores more EM, LX scales with the cross-sectional area AL of the loop across the coil that implements the inductor and the number of turns NL in the coil. LX scales more with NL when the loops align because the magnetic fields of the loops reinforce one another to establish an even stronger magnetic field. B. Actual Inductor In practice, the coil is resistive. This means that inductors also burn Ohmic power. The equivalent series resistance RESR in inductors is the inductor resistance RL in Fig. 3.2. This RL drops a voltage that effectively reduces the voltage across the intrinsic LX. As a result, the intrinsic vL is lower than the extrinsic inductor voltage vL' that a circuit applies. RL scales with NL because the length of the wire is longer with more turns. RL is also inversely proportional to the cross-sectional area of the wire, so RL is higher with thinner coils. Plus, nearby coils produce an alternating magnetic field that induces local eddy currents that effectively push current away from the edges. Fig. 3.1 Magnetizing inductor

Fig. 3.2 Actual inductor

3.1 Transfer Media

107

This means RL also scales with the number of nearby coils and the alternating frequency of the current flowing through the coils. This is the proximity effect. Fast-moving charges also tend to flow along the outer edges of the coil. This is why RL also scales with operating frequency fO, which is the skin effect. So from a circuit’s perspective, PR in RL decomposes into the low- and high-frequency components that dc and ac inductor resistances RL(DC) and RL(AC) consume: PRL ¼ iLðAVGÞ 2 RLðDCÞ þ ΔiLðRMSÞ 2 RLðACÞ :

ð3:4Þ

Here, iL(AVG) is iL’s average dc current and ΔiL(RMS) is the root-mean-squared (RMS) equivalent of the alternating ac ripple. C. Optimal Inductor The optimal LX carries lots of EL and burns little PRL. LX should therefore deliver high EL with low iL. This happens when magnetic permeability, which is the ability to form a magnetic field, is high, for which a large magnetic core is usually necessary. RL should also be low, which means the coil should be thick. Although higher NL raises LX, lengthening the coil and the proximity effect of more nearby turns also increase RL. So the optimal (high-inductance and low-resistance) LX is large. Confining LX to smaller dimensions and cheaper materials ultimately sacrifices power for space and cost savings.

3.1.2

Transformer

A. Ideal Transformer A transformer is nothing but two inductor coils that share the same magnetic space and have access to the same magnetic field. So when neglecting unintended parasitic effects, LI and LO in Fig. 3.3 hold the same EM: EM ¼ 0:5LI iLI 2 ¼ 0:5LO iLO 2 :

ð3:5Þ

This means that the coil with the higher inductance conducts lower current. This is why LI’s current iLI is the transformer translation kL of LO’s current iLO that LO/LI establish. When LO is higher than LI, iLO is a reverse kL fraction of iLI: iLI ¼ iLO

rffiffiffiffiffiffi LO
kL : LI

ð3:6Þ

The ideal transformer has no resistive components. So PR is negligible, which means the output receives the power that the input supplies:

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3 Switched Inductors

Fig. 3.3 Ideal transformer

PIN ¼ iLI vLI ¼ PO ¼ iLO vLO :

ð3:7Þ

LO’s voltage vLO is therefore the kL translation that iLI/iLO and, ultimately, LO/LI determine. In short, iLI is a kL translation of iLO and vLO is a kL translation of vLI: vLO i ¼ LI ¼ kL ¼ vLI iLO

rffiffiffiffiffiffi LO NO  : LI NI

ð3:8Þ

When LI’s and LO’s geometries match, kL reduces to the ratio of the number of loops in LO to those in LI. This is the turns ratio to which literature refers when using NO/NI to quantify kL.

Example 1: Derive an expression for PIN when vIN supplies LI and RLD loads LO. Solution:
PIN ¼ iLI vIN ¼ iLO kL vIN ¼ ¼


 vLO vIN kL k v ¼ kL vIN RLD L IN RLD

ðvIN kL Þ2 vLO 2 ¼ ¼ PLD ¼ PO RLD RLD

B. Actual Transformer In practice, coupled inductors access a fraction of the magnetic field they share. When decomposed into the pieces that actually couple (LI and LO) and the ones that do not (LI' and LO') like Fig. 3.4 shows, only a kCI fraction of the input couples to a kCO fraction of the output:

3.2 Switched Inductors

109

Fig. 3.4 Actual transformer

LI LI þ LI '

ð3:9Þ

LO : LO þ LO '

ð3:10Þ

kCI ¼ kCO ¼

This means that LO avails a kCI fraction of the energy that vLI supplies. So LI' reduces kL to v v k k kL '
LO ¼ LI CI L ¼ vLI vLI




LI LI þ LI '

rffiffiffiffiffiffi LO : LI

ð3:11Þ

This also means that LO' is a load to LO. kCI and kCO, which set the coupling factor or coupling coefficient kC of the transformer, are one in ideal transformers and less than one in practical realizations. Since separating the coils decreases the fraction of inductance that couples, LI and LO and their resulting kC fall with increasing coil distance dX. Misalignment between the coils also reduces kC. Coupling also depends on the geometry of the coils, so variations in dX manifest in kC in a variety of ways. LI and LO are also resistive and, as a result, not lossless. So input and output resistances RLI and RLO further alter the kC fraction that couples and reaches vLO. Needless to say, better transformers couple more and resist less.

3.2

Switched Inductors

Switched inductors energize and drain in alternating phases of a switching cycle. An input source at vIN first energizes a switched inductor LX (in Fig. 3.5) across the energize time tE. The energize voltage vE should always include elements of the input voltage vIN to receive PIN. The load that the output vO feeds then drains LX across the drain time tD. For this, the switching network connects LX in such a way that elements of the output voltage vO apply an opposing vD across LX. This way, LX drains into vO.

110

3 Switched Inductors

Fig. 3.5 Phases of the switched inductor

Fig. 3.6 Inductor waveforms in dc-supplied switched inductors

3.2.1

DC–DC Applications

Many consumer applications transfer power from static dc sources to loads that impose or require steady voltages. Conventional sources include lithium-ion (Li-ion), nickel (Ni), and lead-acid batteries and ac–dc rectifiers that convert dynamic ac sources to static dc outputs. Chargers recharge Li-ion and nickel batteries, voltage regulators feed systems that require steady supplies, and light-emitting diode (LED) drivers feed diodes whose voltages are, for the most part, steady. All these outputs are essentially dc because the capacity (or equivalent capacitance) of batteries is usually high and feedback controllers in regulators and LED drivers steady their outputs. Although controllers cannot respond instantly, designers normally add capacitance to their outputs. So switched-inductor inputs and outputs in all these applications are, for all intents and purposes, nearly dc.

3.2.2

Inductor Current

Since vIN and vO in dc–dc applications are largely static, the iL that vE and vD establish is a steady linear ramp diL/dtX: diL v ¼ L: dtX LX

ð3:12Þ

So like Fig. 3.6 illustrates, vE ramps iL up linearly across tE. The opposing voltage that vD applies similarly ramps iL down across tD. tE and tD are opposite phases of the conduction time tC. Energizing and draining LX this way across tC produces the triangular current ripple ΔiL shown.

3.2 Switched Inductors

3.2.3

111

Duty Cycle

The energize duty cycle dE is the tE fraction of tC across which vE energizes LX: dE


tE : tC

ð3:13Þ

The drain duty cycle dD is the opposite: the tD fraction of tC across which vD drains LX: dD


tD tC  tE ¼ ¼ 1  dE : tC tC

ð3:14Þ

But since tD is the time that remains across tC after tE elapses, tD is also tC  tE and dD is, in consequence, the complement that 1  dE sets. Under static steady-state conditions, iL in one cycle should rise as much as it falls. vE across tE therefore increases iL by the same ΔiL that vD across tD decreases iL:
ΔiL ¼


 vE vD tE ¼ t : LX LX D

ð3:15Þ

This means (i) vEtE’s and vDtD’s volts–seconds products match; (ii) time, duty-cycle, and reciprocal voltage ratios tE/tD, dE/dD, and vD/vE match: t E dE dE v ¼ ¼ ¼ D; t D dD 1  dE vE

ð3:16Þ

and (iii) dE is a vD fraction of the combined vE and vD applied: dE ¼

vD : vE þ vD

ð3:17Þ

A. Ohmic Loss A lossless LX delivers all the input energy it receives. In practice, however, resistances in the network burn energy ER that LX does not receive or deliver. So LX requires longer tE and higher dE to energize. RL and energize resistances RE drop voltages vRL and vRE that decrease vE below its ideal level vEI. Since iL flows to vO when LX drains, RL and drain resistances RD drop voltages vRL and vRD that increase vD over its ideal level vDI. Reducing vE extends the tE that LX needs to energize across ΔiL in Fig. 3.7 and raising vD reduces the tD that LX needs to drain EL. This rise in tE and fall in tD increase dE to the extent that iL, RL, RE, and RD dictate:

112

3 Switched Inductors

Fig. 3.7 Inductor current with Ohmic losses

dE ' ¼

vD vE þ vD

vDI þ vRL þ vRD ðvEI  vRL  vRE Þ þ ðvDI þ vRL þ vRD Þ vDI þ vRL þ vRD ¼ ðvEI  vRE Þ þ ðvDI þ vRD Þ v þ vRL þ vRD > dE :  DI vEI þ vDI

¼

ð3:18Þ

On average, RL subtracts from vE the same vRL that RL adds to vD. Similarly, RE and RD subtract from vE and add to vD similar voltages when RE and RD are similar, which is not unlikely. But since dE is a vD fraction of vE and vD, vRL and vRD in vD invariably raise dE' over its ideal counterpart dE. In all, vR’s scale with iL, oppose vE, and reinforce vD. iL is increasingly less linear (and more parabolic) across tE and tD. In short, resistances distort iL and increase dE. So when a feedback controller adjusts dE so vO nears a target, the resulting rise in dE is a reflection of the Ohmic power lost in the switching network. Since vIN is usually steady and vIN-to-vO translations need higher dE’s when resistances are present, resistances shift vO from their ideal targets when controllers do not adjust dE. In these cases, which are less typical, the shift in vO reflects the power lost. vO in simulations that exclude feedback controllers, for example, varies with RL, RE, and RD and the iL that sets their voltages.

3.2.4

Continuous Conduction

In continuous-conduction mode (CCM), LX conducts continuously across time. In this mode, LX’s conduction period extends across the entire switching period tSW. This way, iL is never static, which is to say diL/dt is never zero. In steady state, iL’s peaks and valleys iL(HI)’s and iL(LO)’s do not vary, so iL ripples periodically like Fig. 3.8 shows. Since tC is tSW in CCM, dE and dD become dE jCCM and

 tE  t ¼  ¼ E tC CCM tSW

ð3:19Þ

3.2 Switched Inductors

113

Fig. 3.8 Inductor current in continuous conduction

dD jCCM

 tD  t ¼  ¼ D ¼ 1  dE : tC CCM tSW

ð3:20Þ

In this mode, iL ripples about iL’s average iL(AVG), iL(AVG) is iL’s low iL(LO) plus half iL’s CCM ripple ΔiL, and iL(AVG) can be positive or negative, which happens when iL reverses direction:   Δi iLðAVGÞ CCM ¼ iLðLOÞ þ ΔiLðAVGÞ CCM ¼ iLðLOÞ þ L : 2

ð3:21Þ

Example 2: Determine tE, tD, and ΔiL in CCM when vE is 2 V, vD is 1 V, tSW is 1 μs, and LX is 10 μH. Solution:

dE ¼ ∴

vD 1 ¼ 33% ¼ vE þ vD 2 þ 1

tE ¼ dE tC ¼ dE tSW ¼ ð33%Þð1μÞ ¼ 330 ns

tD ¼ tC  tE ¼ tSW  tE ¼ 1μ  330n ¼ 670 ns

 vE 2 ΔiL ¼ ð330nÞ ¼ 66 mA t ¼ 10μ LX E

114

3 Switched Inductors

Fig. 3.9 Inductor current in discontinuous conduction

3.2.5

Discontinuous Conduction

In discontinuous-conduction mode (DCM), LX energizes and depletes before tSW ends. This way, like Fig. 3.9 shows, iL climbs across tE to peak inductor current iL(PK), falls across tD to zero, and remains zero until another cycle begins. The dead period between tC’s is the discontinuity in conduction that characterizes DCM. In other words, LX’s conduction period does not extend across the switching cycle. Since tC is not tSW, dE and dD do not relate to tSW like they do in CCM. dE and dD should therefore remain in their more primitive forms: tE/tC and tD/tC. CCM borders DCM when iL reaches zero at the end of the switching cycle. When this happens, iL(LO) is zero, iL(HI) is ΔiL, and iL(AVG) is half ΔiL. LX enters DCM just below this level, when iL(AVG) is less than half the CCM ripple ΔiL:  iLðAVGÞ 

DCM

 ¼ ΔiLðAVGÞ 

DCM



 iLðPKÞ tC Δi ¼ < L: 2 tSW 2

ð3:22Þ

In DCM, iL(PK) is lower than ΔiL, and iL(AVG) across tC is half iL(PK) and across tSW is a tC fraction of tSW lower.

Example 3: Determine tE, tD, and ΔiL when vE is 2 V, vD is 1 V, iL(AVG) is 25 mA, iL valleys to 0 mA, tSW is 1 μs, and LX is 10 μH. Solution: dE ¼ 33% and ΔiL ¼ 66 mA in CCM from previous example  Δi  66m iLðAVGÞ ¼ 25 mA < iLðLOÞ þ L  ¼ 33 mA ∴ DCM ¼0þ 2 2 CCM

 iLðPKÞ tC iLðAVGÞ ¼ 2 tSW

3.2 Switched Inductors

115





 vE vE iLðPKÞ ¼ t ¼ d t LX E LX E C sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   ffi L tSW 10μ 1μ ¼ 870 ns ¼ 2ð25mÞ ! tC ¼ 2iLðAVGÞ X 2 vE dE 33% tE ¼ dE tC ¼ ð33%Þð870nÞ ¼ 290 ns tD ¼ tC  tE ¼ 870n  290n ¼ 580 ns

 vE 2 iLðPKÞ ¼ ð290nÞ ¼ 58 mA t ¼ 10μ LX E

Pseudo-discontinuous-conduction mode (PDCM) mimics DCM. LX in these cases energizes and drains to a minimum static level before tSW ends. So like in DCM, iL rises and falls across tC before tSW lapses. But unlike DCM, iL falls to a minimum inductor current iL(MIN) in Fig. 3.10 that is not zero. This way, LX energizes, drains, and “holds” until the next cycle begins. This means that diL/dt is greater than, less than, and equal to zero across tE, tD, and the dead period between tC’s, respectively. For iL to remain static between conduction periods this way, vL across LX must be zero. LX enters this mode of operation when iL(AVG) is over this iL(MIN) by less than half the CCM ripple ΔiL:   iLðAVGÞ PDCM ¼ iLðMINÞ þ ΔiLðAVGÞ DCM

 iLðPKÞ tC Δi ¼ iLðMINÞ þ < iLðMINÞ þ L : 2 tSW 2

ð3:23Þ

iL(AVG) in PDCM is over iL(MIN) by a tC/tSW fraction of half iL’s peak variation iL(PK).

Fig. 3.10 Inductor current in pseudo-discontinuousconduction mode

116

3.2.6

3 Switched Inductors

CMOS Implementations

Switches in a complementary metal–oxide–semiconductor (CMOS) implementation are MOS field-effect transistors (MOSFETs). Replacing each switch with the parallel combination of complementary N- and P-channel MOSFETs is the most straightforward translation, though not always the most effective one. Available gate drive vGST or vGS  vT and the sheet resistivity RSH that vGST establishes can dictate which type of transistor is more efficient. This is why switches in many applications are N- or P-channel transistors, not the parallel combination of N- and P-channel devices. Although electron mobility μN is usually two to three times greater than hole mobility μP, vGST can outweigh that difference in RSH: RSH ¼ RCH



 WCH v WCH  ¼ DS LCH iDðTRIÞ LCH vDS dE : vE þ v D vO vO tSW vO tSW ð3:62Þ

Example 14: Determine dE'' when vIN is 2 V, vO is 4 V, DDO drops 800 mV, tDT is 50 ns, and tSW is 1 μs. Solution:

  2ð50nÞ v v  v v 2t 4  2 800m D O IN DO DT dE '' ¼ ¼ 52%  þ þ ¼ 1μ 4 4 vE þ vD vO vO tSW Note: dE'' here is higher than dE in the ideal example because DDO raises vD. But since the diode does so only two tDT fractions of tC, tD shortens and tE's fraction of tC increases less than dE' in the asynchronous example.

150

3 Switched Inductors

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Synchronous Boost in CCM vge vge 0 dc¼0 pulse 0 4 50n 1n 1n 520n 1u vgdb vgdb 0 dc¼0 pulse 0 4 0n 1n 1n 620n 1u vin vin 0 dc¼2 lx vin vswo 10u meg vswo vge 0 0 nmos0 w¼100m l¼250n mdo vo vgdb vswo vo pmos0 w¼300m l¼250n co vo 0 5u ro vo 0 10 .lib lib.txt .tran 700u .end Tip: Plot v(vo), i(Lx), and v(vswo) and view across 700 μs and from 695 to 700 μs. C. Power With a higher dE, and as a result, a lower dD, iL(AVG)’s iIN(AVG) is a higher reverse dD translation of iO(AVG). So for the same iO and vO, vIN supplies more iIN than in the ideal boost. But since vDO raises vD only across two tDT fractions of tSW, iIN is lower than the asynchronous iIN. In other words, PIN is higher than PO, but not as high as in the asynchronous case. Since vEdE matches vDdD, vE supplies dEiL(AVG), and vD receives dDiL(AVG), vE still delivers the power vD consumes. vD, however, is a diode over vO across two tDT’s. vO therefore loses about two tDT fractions of the PDD that DDO consumes across tD in the asynchronous stage:
PDT ¼ iLðAVGÞ vDO

2tDT tSW




¼ iLðAVGÞ vDO dD

2tDT tD

 ¼ PDD


 2tDT : tD

ð3:63Þ

This PDT is what the boost sacrifices to DDO across tDT’s. SEG and SDO also consume power, but much less than DDO. This is because the voltages MEG and MDO drop are usually much lower. D. Conduction Modes Since the boost is the part of the buck–boost that boosts, MEG and MDO switch the same way and produce the same vSWO. So like in the buck–boost, the synchronous boost operates like the asynchronous sibling when the controller opens and closes MDO like DDO naturally would, except MDO drops millivolts and DDO drops

3.5 Boost

151

600–800 mV. But since MDO is off across tDT’s, MDO’s body diode plays the role of DDO across tDT’s. If the controller does not open MDO when iL falls to zero before tSW lapses, MDO lets iL reverse direction. Since MDO’s body diode cannot conduct reverse current, MEG’s body diode steers this negative iL to vIN across the tDT that follows. vSWO therefore falls to vEG across tDT like Fig. 3.18 shows. Returning energy to vIN this way means LX transfers and burns more power than necessary. Note one tDT is in tD and another in tE when iL reverses, whereas without negative conduction, tD includes both tDT’s. And since vSWO rises and falls by a similar diode voltage across similar tDT’s, diode effects on vSWI(AVG) tend to cancel. So with negative conduction, dE is close to the ideal case (lower than dE''). Explore with SPICE: See Appendix A for notes on SPICE simulations. * Synchronous Boost with Negative Conduction vge vge 0 dc¼0 pulse 0 4 50n 1n 1n 450n 1u vgdb vgdb 0 dc¼0 pulse 0 4 0n 1n 1n 550n 1u vin vin 0 dc¼2 lx vin vswo 10u meg vswo vge 0 0 nmos0 w¼100m l¼250n mdo vo vgdb vswo vo pmos0 w¼300m l¼250n vo vo 0 dc¼4 .ic i(lx)¼-50m .lib lib.txt .tran 2u .end Tip: Plot i(Lx) and v(vswo). E. Diode Conduction If MDO’s threshold voltage is lower than a diode voltage, MDO conducts across tDT’s when vSWO climbs a |vTP| over MDO’s vO-supplied gate voltage. MDO’s body diode does not inject substrate current when this happens because it does not conduct. A Schottky diode across MDO similarly steers dead-time current away from the body diode and the substrate into which the parasitic bipolar-junction transistors (BJTs) present inject current. Explore with SPICE: Use the previous SPICE code, set VTN0 to 400 mV and VTP0 to 400 mV (use “nmos1” and “pmos1” models), and re-run the simulation.

152

3 Switched Inductors

3.6

Flyback

3.6.1

Ideal Flyback

A. Power Stage The flyback is an interesting variation of the buck–boost. Like all switched inductors, vIN magnetizes the core of an inductor LI. vO similarly demagnetizes the core, but with another inductor LO. In other words, LI draws power from vIN that a coupled LO delivers to vO. The advantage of this setup is separate grounds for vIN and vO for what engineers call galvanic isolation. This way, without a direct connection, stray noise currents do not couple. Ground levels can also be at different potentials. Galvanic isolation is ultimately a form of protection. Aside from separate inductors, flybacks switch and operate like buck–boosts. LI in Fig. 3.28 magnetizes the core when the input switch SEI connects vIN across LI. LO demagnetizes the core after SEI opens, when the output drain switch SDO connects vO across LO. vO drains the core because LI and LO couple in opposite directions, so vLO is vO. LI’s iLI in Fig. 3.29 therefore ramps up with the vE that vLI’s vIN impresses across LI and LO’s iLO ramps down with the vD that vLO’s vO impresses across LO. Fig. 3.28 Ideal (supplyswitched) flyback

Fig. 3.29 Continuous-conduction waveforms in the flyback

3.6 Flyback

153

Since SDO opens across tE and SEI opens across tD, iLO is zero across tE and iLI is zero across tD. As a result, vIN couples a transformer translation of vIN to LO across tE and vO couples “back” a transformer translation of vO to LI across tD. So when SEI opens, vLI practically “flies” from vIN to vO/kL and vLO from vINkL to vO. This “flyback” action on LI is how this power converter derives its name. As a whole, the coupled inductors LI:LO operate and behave like LX in the buck– boost. They energize and drain with vIN and vO. And the combined current they produce iL ripples about an average iL(AVG) that the controller adjusts like Fig. 3.6 shows. B. Duty-Cycle Translation In steady state, the average voltages across LI and LO are zero. Since vIN is across LI a tE fraction of tC and vO/kL couples back across LI a tD fraction, vLI(AVG) incorporates duty-cycled fractions of vIN and vO/kL: vLIðAVGÞ





rffiffiffiffiffiffi tE vO tD LI ¼ vIN  ¼ vIN dE  vO d ¼ 0: tC kL tC LO D

ð3:64Þ

Similarly, vLO(AVG) incorporates duty-cycled fractions of vINkL and vO because vINkL couples across LO a tE fraction of tC and vO is across LO a tD fraction: vLOðAVGÞ


rffiffiffiffiffiffi

 tE tD LO d  vO dD ¼ 0: ¼ vIN kL  vO ¼ vIN tC tC LI E

ð3:65Þ

Since dD is 1  dE, dE is a vO fraction of vINkL + vO: dE ¼

vO =kL vD vO ¼ , ¼ vE þ vD vIN þ ðvO =kL Þ vIN kL þ vO

ð3:66Þ

like LI’s vIN for vE and vO/kL for vD and LO’s vINkL for vE and vO for vD in the general expression predict. Notice that vO is a duty-cycled scalar dE/dD of vINkL. And together, vO/vIN scales with kL and dE/dD:

rffiffiffiffiffiffi
 vO dE LO dE ¼ kL ¼ : vIN dD LI 1  dE

ð3:67Þ

dE/dD is greater than one, and vO is correspondingly greater than the transformer translation of vIN when dE is greater than 50% (and dD is less than 50%). dE/dD is less than one and vO is correspondingly less than the transformer translation of vIN otherwise. So like the buck–boost, the flyback can buck and boost vIN.

154

3 Switched Inductors

Example 15: Determine dE when vIN is 2 V, LI is 5 μH, LO is 20 μH, and vO is 2 V. Solution: rffiffiffiffiffiffi rffiffiffiffiffiffiffiffi LO 20μ kL ¼ ¼ ¼2 5μ LI dE ¼

vD vO 2 ¼ 33% ¼ ¼ vE þ vD vIN kL þ vO 2ð2Þ þ 2

Example 16: Determine dE for the transformer in Example 15 when vIN is 2 V and vO is 6 V. Solution: kL ¼ 2 from Example 15 dE ¼

vD vO 6 ¼ ¼ ¼ 60% vE þ vD vIN kL þ vO 2ð2Þ þ 6

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Flyback in CCM vde de 0 dc¼0 pulse 0 1 50n 1n 1n 333n 1u vin vin 0 dc¼2 sei vin vswi de 0 sw1v li vswi 0 5u k1 li lo 1 lo 0 vswo 20u (continued)

3.6 Flyback

155

ddo vswo vo idiode co vo 0 5u ro vo 0 10 .lib lib.txt .tran 700u .end Tip: Plot v(vo), i(Li), i(Lo), v(vswi), and v(vswo) and view across 700 μs and from 695 to 700 μs. C. Power Without a physical (galvanic) connection, vIN cannot deliver power directly to vO like the buck and boost can. LI:LO therefore carries all the energy vIN delivers. This means that the two switches carry more current than their buck and boost counterparts. So like the buck–boost, the flyback usually burns more Ohmic power than the buck and boost. Together, iLI and iLO carry the transformer current iX that LI:LO’s magnetic core carries. With respect to LI, iXI carries iLI and a kL translation of iLO. iXO similarly carries iLO and a reverse kL translation of iLI with respect to LO. So iXI is kLiXO and iXO is iXI/kL: iXI ¼ kL iXO ¼ iLI þ kL iLO iXO ¼

iXI iLI ¼ þ iLO : kL kL

ð3:68Þ ð3:69Þ

Like the buck–boost, vO receives a dD fraction of iXO, so the output delivers vOiXO(AVG)dD with vOiO(AVG): PO ¼ vO iOðAVGÞ ¼ vO iXOðAVGÞ dO ¼ vO iXOðAVGÞ dD ¼ vO iXOðAVGÞ ð1  dE Þ: ð3:70Þ And because vIN supplies a dE fraction of iXI and iXI is a kL translation of iXO, vIN supplies vIN(iO(AVG)/dD)kLdE with vINiXI(AVG)dE: PIN ¼ vIN iINðAVGÞ ¼ vIN iXIðAVGÞ dIN ¼ vIN iXIðAVGÞ dE
 iOðAVGÞ ¼ vIN iXOðAVGÞ kL dE ¼ vIN kL dE : dD

ð3:71Þ

Since ideal switches do not burn power, this PIN matches PO (because vDdD’s vOdD matches vEdE’s vINdE, which is to say iXI(AVG) is iXO(AVG)kL, iXO(AVG) is iO(AVG)/dD, and vO is vINkLdE/dD). In short, vO receives the energy vIN supplies with LI:LO.

156

3 Switched Inductors

Fig. 3.30 Ground- and supply-switched flyback variations

D. Variants Although ground and supply switches can (at the same time) connect and disconnect LI from vIN and LO from vO, only one switch per side is necessary like Figs. 3.28 and 3.30 show. A second switch would burn power, require space, and complicate the controller needlessly. Of these, the ground-switched input and supply-switched output variant in Fig. 3.30 is probably the most popular because a low-side switch is often less resistive and connecting LO to vO’s ground plane produces less ground noise. Device availability, breakdown voltage, and conductivity ultimately dictate which switches are possible, more reliable, and less lossy. E. Snubbers In practice, parts of LI and LO do not couple. This means that LO cannot drain the energy that vIN injects across tE into LI’s uncoupled fraction. So when SEI opens, remnant iLI charges the parasitic capacitances CSWI that remain attached to SEI’s switching node vSWI. This is often a problem because vSWI can swing above SEI’s breakdown level. Snubbers protect switches from overvoltage conditions of this sort. Without protection, LI’s uncoupled fraction LI' drains into CSWI, CSWI drains back into LI', and if SEI does not break, CSWI and LI' exchange energy until parasitic resistances burn the energy or tSW lapses. One way of limiting vSWI’s swing is to dissipate some of this energy quickly. The purpose of RSI in the damper that RSI and CSI implement in Fig. 3.31 is just this: to burn remnant energy in the core. For this, CSI should shunt and short below the resonant frequency fLC. In other words, RSI and CSI’s combined impedance ZSI at the resonant frequency fLC should be lower than CSWI’s ZSWI. This way, ZSI can steer remnant iLI away from CSWI into RSI when SEI opens. So RSI burns energy, CSWI peaks to a lower voltage, and LI and CSI together with CSWI exchange energy across fewer cycles.

3.6 Flyback

157

Fig. 3.31 Input-damped flyback

Fig. 3.32 Input-clamped flyback

ZSI, however, should not load LI across tSW to the extent that CSWI cannot “fly” to vIN + vO/kL. In other words, CSI should only shunt and short above fSW, not below. More to the point, RSI should current-limit CSI at a frequency fSI that is greater than fSW:  1  sCSI f SW dE : vIN kL þ vO tSW

dE '' ¼

ð3:78Þ

Example 18: Determine dE'' for the transformer in Example 15 when vIN is 2 V, vO is 6 V, DDO drops 400 mV, tDT is 50 ns, and tSW is 1 μs. Solution: kL ¼ 2 from Example 15 vD vE þ vD

 vO vDO 2tDT  þ vIN kL þ vO vIN kL þ vO tSW   2ð50nÞ 6 800m ¼ ¼ 61% þ 1μ 2ð 2Þ þ 6 2ð 2Þ þ 6

dE '' ¼

Note: dE'' here is higher than dE in the ideal example because DDO raises vD. But since the diode does so only two tDT fractions of tSW, tD shortens and tE’s fraction of tC rises less than dE' in the asynchronous example.

164

3 Switched Inductors

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Synchronous Flyback in CCM vge vge 0 dc¼0 pulse 0 2 50n 1n 1n 610n 1u vgdb vgdb 0 dc¼0 pulse 0 6 0n 1n 1n 710n 1u vin vin 0 dc¼2 li vin vswi 5u meg vswi vge 0 0 fnmos0 w¼100m l¼250n cswi vswi 0 1f k1 li lo 1 lo 0 vswo 20u mdo vo vgdb vswo vo fpmos0 w¼300m l¼250n cswo vswo 0 1f co vo 0 5u ro vo 0 10 .lib lib.txt .tran 700u .end Tip: Plot v(vo), i(Li), i(Lo), v(vswi), and v(vswo) and view across 700 μs and from 695 to 700 μs. C. Conduction Modes If the controller opens and closes MDO when the asynchronous diode DDO would, the only difference between asynchronous and synchronous operation is the voltage dropped across the switch: millivolts with FETs and 600–800 mV with diodes. But since MDO is off across dead-time periods, MDO’s body diode conducts across tDT’s like DDO in the asynchronous flyback. If the controller does not open MDO when iXO reaches zero before tSW lapses, MDO lets iXO reverse direction. Since MDO’s body diode cannot conduct this negative iXO across the tDT that follows, MEI’s body diode conducts iXI’s kLiXO into vIN. So vSWI falls a diode voltage across this tDT and returns to zero when MEI closes. Returning energy to vIN this way means LX transfers and burns more power than necessary. Note one tDT is in tD and another in tE when iXO reverses, whereas without negative conduction, tD includes both tDT’s. And since vSWI falls and vSWO rises by a similar diode voltage across similar tDT’s, diode effects on vL(AVG)’s tend to cancel. So with negative conduction, dE is close to the ideal case (and lower than dE'').

3.7 Summary

165

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Synchronous Flyback with Negative Conduction vge vge 0 dc¼0 pulse 0 2 50n 1n 1n 550n 1u vgdb vgdb 0 dc¼0 pulse 0 6 0n 1n 1n 650n 1u vin vin 0 dc¼2 li vin vswi 5u meg vswi vge 0 0 fnmos0 w¼100m l¼250n k1 li lo 1 lo 0 vswo 20u mdo vo vgdb vswo vo fpmos0 w¼300m l¼250n vo vo 0 dc¼6 .ic i(lo)¼-60m .lib lib.txt .tran 2u .end Tip: Plot i(Li), i(Lo), v(vswi), and v(vswo). D. Diode Conduction If MDO’s threshold voltage is lower than a diode voltage, MDO closes across tDT’s when vSWO climbs |vTP| over MDO’s vO-supplied gate voltage. MDO’s body diode does not inject noise current into the substrate when this happens because it does not conduct. A Schottky diode across MDO similarly channels dead-time current away from the body diode and the substrate into which the parasitic BJT present injects current. Explore with SPICE: Use the previous SPICE code, set VTN0 to 400 mV and VTP0 to 400 mV (use “nmos1” and “pmos1” models), and re-run the simulation.

3.7

Summary

Inductors that share magnetic space can energize and drain that space with voltages of opposing polarities. This is how switched inductors and transformers transfer input power to output loads. Unfortunately, series resistances burn some of this energy. And nearby coils and fast-changing currents restrict the medium through which their currents can flow. So the power lost to resistance in the coil increases with more nearby coils and higher switching frequency.

166

3 Switched Inductors

But since this loss is a small fraction of the power drawn, many consumer products use this method to transfer power from ac–dc chargers and internal batteries to electronic systems that require stable dc power supplies. In these applications, the inputs and outputs of the switched inductors are static or quasi-static voltages. Switchers use these dc voltages to ramp their inductor currents up and down. Since inductor current rises as much as it falls in steady state, these same voltages set the duty-cycle fractions of the switching period that energize and drain the inductors. CMOS solutions use MOSFETs to energize inductors and diodes or MOSFETs to drain them. Which type of MOSFET to select depends on the gate drive available. To supply the energy these switches ultimately burn, switchers must energize inductors across a longer duty-cycle fraction of the switching period. This way, they can overcome the losses and deliver the power their loads require. Switched inductors can buck and boost input voltages to lower and higher output levels with four switches. Removing the two input or two output switches sets an average voltage that only a higher voltage at the opposite end can balance. This is why two switches can buck or boost, but not both. Asynchronous circuits drain the inductor with diodes and synchronous circuits with MOSFETs. To avoid momentary shorts, synchronous solutions insert dead times between the conduction periods of adjacent switches. Body, MOS, or Schottky diodes conduct the inductor current across these times. In flybacks, an input inductor magnetizes the space that an output inductor drains. This way, input sources and output loads need not share a common ground (for galvanic isolation). But since parts of the input inductor do not couple to the output, engineers use snubbers to burn leftover energy. Switched inductors are vital in electronic systems. One reason for this is they can boost input supply voltages to higher output levels, which is not possible with linear (non-switched) power stages. Another reason is they burn less power than their linear counterparts when transferring moderate to high power levels. This is why switched inductors are so pervasive in power supplies.

4

Power Losses

Abbreviations BJT CCM CMOS DCM ESD ESR FET FM LED MOS MPP MPPT NMOS PDCM PFM PM PMOS RMS SL ZCS ZVS CCH CDB CG CGD CGS COL

Bipolar-junction transistor Continuous-conduction mode Complementary MOS Discontinuous-conduction mode Electrostatic-discharge protection Equivalent series resistance Field-effect transistor Frequency modulation Light-emitting diode Metal–oxide–semiconductor Maximum-power point MPP tracker N-channel MOSFET Pseudo-DCM Pulse FM Peak modulation P-channel MOSFET Root-mean-square Switched inductor Zero-current switching Zero-voltage switching Channel capacitance Drain–body capacitance Gate capacitance Gate–drain capacitance Gate–source capacitance Overlap capacitance

# The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 G. A. Rincón-Mora, Switched Inductor Power IC Design, https://doi.org/10.1007/978-3-030-95899-2_4

167

168

CSB CSWI CSWO dD dE dIN DDG DDO DDT dO fSW iD iDS iG iLD iIN iL iL(HI) iL(MIN) iL(LO) iL(PK) iO iOFF iRR iSUB ΔiL iΔ IS K' LCH LMIN LX PB PD PDD PDT PG PGI PIN PIV PL PLD PLOSS PMOS PO

4

Source–body capacitance Input switch-node capacitance Output switch-node capacitance Drain duty cycle Energize duty cycle Input duty cycle Ground drain diode Output drain diode Dead-time diode Output duty cycle Switching frequency Driver current Drain–source current Gate current Load current Input current Inductor current Inductor current peak in CCM Minimum inductor current Inductor current valley in CCM Peak inductor current in DCM Output current Off current Reverse-recovery current Substrate current CCM inductor ripple current Triangular current Reverse saturation current Transconductance parameter Channel length Minimum allowable oxide length Switched/transfer inductor Battery power Drive power Diode drain power Dead-time power Gate-charge power Driver gate-charge power Input power iDS–vDS overlap power Inductor power Load power Power losses MOS power Output power

Power Losses

Abbreviations

POFF PR PRR PSWI PSWO qDIF qRR RCH RD RDG RDO RE REG REI RL(AC) RL(DC) RN ROFF RP RS SDG SDO SEG SEI tC tD tDT tE tSW TJ τF vB vD vDD vDS vDS(SAT) vE vGS vIN vO vS vSWI vSWO vT vTH

Cut-off power Ohmic power Reverse-recovery power Input switch-node power Output switch-node power Diffusion charge Reverse-recovery charge Channel resistance Drain resistance Ground drain resistance Output drain resistance Energize resistance Ground energize resistance Input energize resistance Inductor’s ac resistance Inductor’s dc resistance Pull-down N-type resistance Off resistance Pull-up P-type resistance Source resistance Ground drain switch Output drain switch Ground energize switch Input energize switch Conduction time Drain time Dead time Energize time Switching period Junction temperature Forward transit time Battery voltage/battery Drain voltage Power supply Drain–source voltage Saturation voltage Energize voltage Gate–source voltage Input voltage/input Output voltage/output Source voltage/source Input switching node/voltage Output switching node/voltage MOS threshold voltage Gate–source threshold

169

170

4

VT0 WCH WCH' λ ηC σLOSS

Power Losses

Zero-bias threshold Channel width Optimal channel width Channel-length modulation parameter Power-conversion efficiency Fractional loss

Switched-inductor (SL) power supplies are pervasive in electronic systems because they output a large fraction of the power they draw from their inputs. The main reason for this is the voltages that switches drop are a very small fraction of the input and output voltages. So the inductor current draws and delivers a lot more input power into the output than switches consume. Still, the heat that burning power generates can compromise electronic performance and mechanical integrity. And losing battery energy or ambient power to the switched inductor reduces the charge life or functionality of an electronic system. So understanding the nature, makeup, and sensitivity of these losses is important. The most fundamental of these is conduction power. This is the power that components consume when they conduct inductor current. Series resistances, diodes, and transistors are to blame for this. Another loss is the power that gate drivers need to transition switches between states. Stray capacitances and large switches also leak power. The operating mechanics of the switched inductor dictate how these components ultimately consume power. Quantifying losses, however, is not enough. Their significance ultimately rests on the applications they serve and the functionality they provide.

4.1

Power Conversion

Power-conversion efficiency ηC is the fraction of input power PIN that the input vIN delivers to the output vO in Fig. 4.1: ηC


PO PO P  PLOSS P ¼ ¼ IN ¼ 1  LOSS ¼ 1  σLOSS : PIN PO þ PLOSS PIN PIN

ð4:1Þ

In addition to this output power PO, PIN also supplies the power PLOSS lost to components in the circuit. So PO outputs what is left: the difference PIN – PLOSS, Fig. 4.1 Power supply

4.1 Power Conversion

171

fractional loss σLOSS is the fraction of PIN lost in PLOSS, and ηC is below 100% by the amount σLOSS dictates. ηC and σLOSS are complementary measures of efficiency. PIN is critical in ηC and σLOSS because PLOSS is a larger fraction of PIN when the iO that sets PO and PIN is lower. This is because iIN’s average is an input duty-cycle dIN fraction of iL’s average, which is a reverse output duty-cycle dO translation of iO’s average. So when the load is light (i.e., iO is low), PLOSS is a higher fraction of PIN, and ηC is, in consequence, lower by the higher σLOSS that PLOSS and PIN set: σLOSS ¼

PLOSS PLOSS PLOSS PLOSS  ¼ ¼ ¼
: PIN iINðAVGÞ vIN iLðAVGÞ dIN vIN iOðAVGÞ =dO dIN vIN

ð4:2Þ

But since boosts connect vIN directly to the transfer inductor LX (without input switches), dIN is one, not a fraction. Similarly, dO is one in bucks because they connect LX directly to vO (without output switches). In other words, iO’s translation to iIN hinges on LX’s connectivity to vIN and vO.

4.1.1

Voltage Regulators and LED Drivers

Voltage regulators incorporate feedback loops that keep vO near a prescribed target. This way, vO hardly varies with the load current iLD that vO in Fig. 4.2 supplies. The vO that light-emitting diode (LED) drivers establish is also steady because these drivers similarly keep the output current iO near a target. Since vO is steady either way and iO and iLD are independent variables, engineers calculate and show how ηC varies across iO or the PO that vO outputs with iO: η Cð RÞ ¼

iOðAVGÞ vO PO PO iLD vO ¼ ¼ ¼ , PIN PO þ PLOSS iOðAVGÞ vO þ PLOSS iLD vO þ PLOSS

ð4:3Þ

where vO’s static dc component VO is typically much greater than vO’s dynamic ac variation ΔvO. vIN is usually a good voltage source (with low source resistance RS), so vIN can supply all the PIN that iO with vO and PLOSS require.

4.1.2

Battery Chargers

Battery chargers normally incorporate feedback loops that keep iO in Fig. 4.3 steady. This iO charges a battery vB across its operating range. Since iO is steady and vB

Fig. 4.2 Voltage regulator and LED driver

172

4

Power Losses

Fig. 4.3 Battery charger

Fig. 4.4 Energy-harvesting charger

Fig. 4.5 Energy-harvesting supply

climbs across a prescribed range, showing how ηC varies across vB is often more revealing than across the PO that iO with vB set: η Cð CÞ ¼

iOðAVGÞ vO iOðAVGÞ vB PO PO ¼ ¼ ¼ , PIN PO þ PLOSS iOðAVGÞ vO þ PLOSS iOðAVGÞ vB þ PLOSS

ð4:4Þ

where iO’s static dc component IO is typically much greater than iO’s dynamic ac variation ΔiO. vIN is typically a low-resistance source that can supply all the PIN that iO with vB and PLOSS require. vB’s resistance is also low for a good battery. So ηC(C) is ultimately the PIN fraction that iO(AVG) and vB’s static component determine.

4.1.3

Energy Harvesters

The fundamental difference between an ambient-derived source vS and a typical input is that vS is deficient. In other words, part or all of PO’s range overloads vS. This is why many energy harvesters are chargers that supply what vS avails. So they cannot always output the iO (in Fig. 4.4) that charges vB quickly or the iO that maximizes vB’s capacity. Still, ambient energy is so pervasive that they can always charge, albeit slowly (with little iO) and asynchronously (when enough ambient energy is available). Smarter energy-harvesting systems charge and supply loads at the same time. This is possible when PIN’s maximum exceeds PO’s minimum. So when PIN in Fig. 4.5 surpasses PO by more than PLOSS, the harvester supplies PO and charges vB

4.2 Operating Mechanics

173

with excess PIN. Otherwise, the harvester draws assistance from vB, in which case PIN and battery power PB supply PO and PLOSS. vS here is the effective source that transducers establish when converting ambient energy into electrical power. RS models the imperfections that current-limit vS. vIN therefore peaks to vS when input current iIN is zero and iIN maxes to vS/RS when the harvester grounds vIN. RS also limits PIN. This RS is also present in conventional regulators, LED drivers, and chargers. In these, however, PIN(MAX) is greater than PO(MAX), so PO cannot overload PIN. Ambient sources, on the other hand, do not always avail the same PIN, so PO in harvesters can and will at times overload PIN. A. Maximum-Power Point The significance of power-conversion efficiency is that reducing losses conserves energy. ηC is less consequential in a harvester because unused ambient energy transforms into forms that the transducer cannot tap. So harvesters should convert and deliver all the power possible. Good harvesters draw the PIN that supplies the highest PO. The feedback loops that keep them at the maximum-power point (MPP) are MPP trackers (MPPTs). PO(MAX) is therefore a good metric for harvesting efficacy. Since PO(MAX) reflects how much energy is available, PO(MAX) changes with ambient conditions. The highest possible PO results when ηC peaks at the MPP. At this point, the harvester draws the most PIN and loses the least PLOSS. When ambient conditions change, the PIN that corresponds to the new MPP changes. So ηC shifts from its peak and PO(MPP) is no longer PO(MAX). MPPTs usually keep PO near PO(MPP) by adjusting PIN. Engineers try to max ηC at the most probable PIN so PO(MPP) matches PO(MAX) more frequently. The general aim, however, is to keep ηC high across PIN’s range.

4.2

Operating Mechanics

The purpose of a switched inductor is to transfer vIN energy to vO. For this, input and ground energize switches SEI and SEG in Fig. 4.6 energize LX from vIN and ground and output drain switches SDG and SDO drain LX into vO in alternating phases. This way, vIN produces an inductor current iL that draws PIN from vIN and outputs PO to vO. vIN establishes an energize voltage vE that raises iL across energize time tE in Fig. 4.7. vO similarly sets an opposing drain voltage vD that reduces iL across drain Fig. 4.6 Switched inductor

174

4

Power Losses

Fig. 4.7 Inductor current

time tD. iL rises and falls this way across tC to produce a ripple current ΔiL that repeats across cycles:  ΔiL ¼

   vE vD tE ¼ t : LX LX D

ð4:5Þ

Here, energize and drain duty cycles dE and dD refer to corresponding tE and tD fractions of tC: tE/tC and tD/tC. So tE-to-tD’s ratio follows dE to dD’s and matches vD to vE’s: t E dE vD dE ¼ ¼ ¼ : t D dD vE 1  dE

ð4:6Þ

Since tD is tC – tE and dD is 1 – dE, dE is vD’s fraction of vE and vD: dE ¼

vD : vE þ vD

ð4:7Þ

dE is therefore a function of the vE and vD that vIN and vO set.

4.2.1

Continuous Conduction

In continuous-conduction mode (CCM), LX conducts continuously across the entire switching period tSW. This way, tE and tD in Fig. 4.8 establish a conduction time tC that extends across tSW. iL’s CCM valley iL(LO) is zero or higher, so iL(AVG) is half iL’s ripple ΔiL or higher.

4.2.2

Discontinuous Conduction

LX conducts a fraction of tSW in discontinuous-conduction mode (DCM). So tC is less than tSW, and iL in Fig. 4.9 reaches zero at tC and remains zero until tSW lapses. iL(AVG) across tSW is therefore a fraction of iL’s average iC(AVG) across tC, which is half iL’s DCM peak iL(PK). iL(PK) is ultimately a reflection of the iO that iL(AVG) across tSW feeds. Fig. 4.8 Inductor current in continuous conduction

4.2 Operating Mechanics

175

Fig. 4.9 Inductor current in discontinuous conduction

Fig. 4.10 Switched-inductor buck

Since tE is a dE fraction of tC and vE across LX raises iL to iL(PK) across tE, tC also scales with iL(PK): tC ¼

tE ¼ dE

   iLðPKÞ LX : dE vE

ð4:8Þ

iL averages half of iL(PK) across tC and a tC/tSW fraction of that half across tSW:  iLðAVGÞ ¼ iCðAVGÞ

tC

tSW

 ¼

   iLðPKÞ iLðPKÞ 2 LX tC : ¼ 2 tSW 2dE vE tSW

ð4:9Þ

iL(PK) is therefore a square-root translation of iL(AVG):

iLðPKÞ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi      iOðAVGÞ vE vE ¼ 2dE tSW ¼ 2dE t i , LX SW LðAVGÞ LX dO

ð4:10Þ

which is in turn a reverse output duty-cycle dO translation of iO. In short, tC and iL(PK) scale with √iO(AVG). Although not often the case, iL can also fall to and remain at an iL(MIN) that is not zero. In these cases, iL rises and falls with vE and vD across LX and flattens with zero volts. This is pseudo DCM, which engineers often abbreviate to PDCM.

4.2.3

Circuit Variants

LX in Fig. 4.6 can “step” vIN down or up to a lower or higher vO. If vO is less than vIN, vIN – vO can establish the positive vE needed to energize LX. So removing SEG and SDO and connecting LX to vO transform the buck–boost in Fig. 4.6 into the buck in Fig. 4.10. In this case, dO is the fraction of tC that tE and tD together set, which is one. So iL(AVG) matches iO, and since the input duty-cycle dIN is a tE fraction of tC, iIN is similarly a dIN fraction of iL(AVG).

176

4

Power Losses

Fig. 4.11 Switched-inductor boost

Fig. 4.12 CMOS switched inductor

When vIN is less than vO, vO – vIN can set the vD needed to drain LX. So removing SEI and SDG and connecting vIN to LX transform the buck–boost into the boost in Fig. 4.11. Here, iIN matches iL(AVG) and iO is a dO fraction of iL(AVG). Converting a buck–boost into a boost or a buck when possible is good because fewer switches occupy less space and require less power.

4.2.4

CMOS Implementation

N-channel metal–oxide–semiconductor (MOS) field-effect transistors (FETs) MDG and MEG in Fig. 4.12 implement the ground switches in Fig. 4.6 because P-channel MOS switches would require negative gate voltages to close. Similarly, P-channel transistors MEI and MDO normally realize the input and output switches because NMOS transistors would require above -vIN and -vO gate voltages to close. Paralleling an NMOS with MEI or MDO reduces resistance when vO or vIN is much higher than vIN or vO, in which case gate voltages can rise with vO or vIN well above vIN or vO. Note that all source-terminal arrows point in the direction they steer iL. A. Dead-Time Conduction Dead time tDT between the conduction periods of adjacent switches keep MEI– MDG and MEG–MDO from momentarily grounding vIN and vO, which could pull too much power from vIN and vO. Since vIN directs iL into vO, MDG’s and MDO’s body diodes conduct iL into vO across these tDT’s. The body connections shown ensure only these body diodes can conduct iL. When MOS threshold voltages vT’s are less than 500 mV or so, iL discharges and charges capacitances at the input and output switching nodes vSWI and vSWO below and above the vT’s needed to engage MDG and MDO. So MDG and MDO conduct all

4.2 Operating Mechanics

177

or part of iL across tDT’s. Still, the effect is similar because MDG and MDO behave like diodes in this mode. B. Duty Cycle This diode action ultimately reduces the vD that drains LX. But since this happens across two small fractions of tC and diode voltages are usually small fractions of vE and vD, the effect on dE is normally low. The resulting dE'' is nevertheless greater than the ideal dE by these fractions. In CCM, tC extends across tSW, so dE is    vD v þ vDG 2tDT þ DO vE þ v D vE þ vD tC    v þ vDG 2tDT ¼ dE þ DO > dE : vE þ vD tSW

dEðCCMÞ'' 

ð4:11Þ

The effect is lower in DCM because the controller opens the drain switches when iL is zero. So these diodes only conduct considerable iL across the other tDT: ''  dEðDCMÞ

      vD v þ vDG tDT v þ vDG tDT þ DO ¼ dE þ DO < dE '' : vE þ vD vE þ vD tC vE þ vD tC ð4:12Þ

This tDT, however, is a larger fraction of tC because tC ends before tSW lapses. C. Switching Voltages When energize switches open, iL pulls vSWI low and vSWO high until ground and output drain diodes DDG and DDO conduct iL. So vSWI falls from vIN to –vDG and vSWO rises from zero to vDO over vO when tE ends in Fig. 4.13. vSWI rises to zero and vSWO falls to vO a tDT into tD when SDG and SDO close. Drain switches SDG and SDO open a tDT before tD ends, so DDG and DDO pull vSWI a vDG below ground and vSWO a vDO over vO. And vSWI climbs to vIN and vSWO falls to zero when energize switches SEI and SEG close at the beginning of tE. This sequence repeats every tSW. Fig. 4.13 Switching voltages

178

4.3

4

Power Losses

Ohmic Loss

Ohmic power PR in this chapter refers to power that resistances in the switched inductor consume when conducting iL. This is a loss because they burn vIN power that vO does not receive. The average power a device that conducts iA and drops vA consumes across time tX is

PAX

t 1
PAðAVGÞ 0X ¼ tX

ZtX

1 PA dt ¼ tX

0

ZtX iA vA dt:

ð4:13Þ

0

In truth, all power losses are fundamentally Ohmic in nature and all of them are ultimately lost in the form of heat. Here, Ohmic refers to resistance because Ohms is the unit that characterizes resistance. So any component that behaves like a resistor burns, from the perspective of this chapter, Ohmic power.

4.3.1

Ohmic Power

Since the voltage vR across a resistor RX that conducts iX is iXRX, RX power PR is iXvR and iX2RX. When iX ramps linearly across time tX like Fig. 4.14 shows, PR climbs quadratically with iX and PR’s average PRX across tX rises quadratically with iX’s root-mean-square (RMS) iX(RMS): PRX ¼

1 tX

ZtX 0

0 iX vR dt ¼ @

1 tX

ZtX

1 iX 2 dtARX ¼ iXðRMSÞ 2 RX :

ð4:14Þ

0

This means that PRX’s rise across time accelerates with iX. A. Triangular Current The triangular current iΔ in Fig. 4.15 ramps across tX to ΔiΔ. Squaring this iΔ and averaging iΔ2 across tX reduces iΔ(RMS) to Fig. 4.14 Resistor power with ramp current

Fig. 4.15 Triangular current

4.3 Ohmic Loss

179

Fig. 4.16 Alternating triangular current

Fig. 4.17 Non-zero crossing ramp current

iΔðRMSÞ

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u ZtX  sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2   ffi u u1 ΔiΔ t ΔiΔ 2 tX 3 Δi ¼ pffiffiΔffi : ¼t dt ¼ 3 tX tX 3 tX 3

ð4:15Þ

0

So the RMS of a triangular current is a root-three fraction of its peak ΔiΔ. B. Alternating Current Positive and negative currents through a resistor burn power in the same way. RMS accounts for this because its squaring function desensitizes RMS from polarity. So when an alternating current iAC is symmetrical, iAC’s negative half burns as much power as iAC’s positive half. iAC across each half in Fig. 4.16 is triangular like iΔ in Fig. 4.15. So iAC(RMS) across each 0.5tX is the same across tX and like iΔ across 0.5tX:    0:5Δi iACðRMSÞ
iACðRMSÞ tX ¼ iACðRMSÞ 0:5tX ¼ iΔðRMSÞ 0:5tX ¼ pffiffiffiAC : 3

ð4:16Þ

And since each half triangle traverses 0.5ΔiAC, iAC(RMS) is a root-three fraction of half iAC’s ripple ΔiAC. C. Power Theorem iX in Fig. 4.17 ramps about an iX(AVG) that is greater than zero. Since iX rises from iX(MIN) across ΔiX in tX and iX(MIN) is half a ripple below iX's average, iX across time t is     ΔiX ΔiX ΔiX þ iX ¼ iXðMINÞ þ t ¼ iXðAVGÞ  t: tX 2 tX

ð4:17Þ

Squaring iX and averaging iX2 across tX reveals that iX(RMS)2 decomposes into average and alternating components iX(AVG)2 and iAC(RMS)2:

180

4

iXðRMSÞ

2

1 ¼ tX

Power Losses

ZtX iX 2 dt 0

   3    2  tX  1 ΔiX 2 t ΔiX t  ¼ iXðMINÞ 2 t þ þ 2i XðMINÞ 2 tX 3 tX 2 0 tX " # 2   1 ΔiX ΔiX 2 tX ΔiX ¼ iXðAVGÞ  tX þ þ iXðAVGÞ  ΔiX tX tX 2 3 2  2

 2  ΔiX 4 0:5ΔiX pffiffiffi ¼ iXðAVGÞ 2 þ 1 þ  2 ¼ iXðAVGÞ 2 þ 3 2 3 2 2 ¼ iXðAVGÞ þ iACðRMSÞ : ð4:18Þ When RX conducts iX across a tX fraction of the switching period, RX consumes a similar tSW fraction of PRX. So overall, PR reduces to  PR ¼ PRX

tX tSW



 ¼ iXðRMSÞ RX 2

tX tSW




 ¼ iXðAVGÞ 2 þ iACðRMSÞ 2 RX



 tX : tSW

ð4:19Þ

This expression is very useful because it extrapolates the power that resistances burn when conducting across irregular fractions of tSW.

4.3.2

Continuous Conduction

A. Switched Inductor iL in CCM ripples about an iL(AVG) that keeps iL(LO) at or above zero. LX’s equivalent series resistance (ESR) RL conducts this iL across all of tSW. But since skin and proximity effects keep dynamic current near the edges of the coil, RL is higher for the ripple than for the static component of iL. So iL(AVG) burns power with the inductor’s dc resistance RL(DC) and iAC(RMS) with the inductor’s higher ac resistance RL(AC): PRL  iLðAVGÞ 2 RLðDCÞ þ iACðRMSÞ 2 RLðACÞ    2 iOðAVGÞ 2 0:5ΔiL pffiffiffi ¼ RLðDCÞ þ RLðACÞ , dO 3

ð4:20Þ

where iL(AVG) is a reverse dO translation of iO(AVG) and iAC(RMS) is a root-three fraction of half ΔiL.

4.3 Ohmic Loss

181

Example 1: Determine PRL and σRL for LX in an ideal buck–boost in CCM when vIN is 2 V, vO is 4 V, iO(AVG) is 250 mA, LX is 10 μH, tSW is 1 μs, and RL is 200 mΩ. Solution: vO 4 ¼ 67% ∴ dO ¼ dD ¼ 1  dE  1  67% ¼ 33% ¼ vIN þ vO 2 þ 4       vE vIN 2 ð67%Þð1μÞ ¼ 130 mA ΔiL ¼ t ¼ d t  10μ LX E LX E SW " ( 2    2 # 2 ) iOðAVGÞ 2 0:5ð130mÞ 0:5ΔiL 250m pffiffiffi pffiffiffi  þ þ RL ¼ ð200mÞ dO 33% 3 3

dIN ¼ dE 

PRL

¼ 120 mW σRL ¼


PRL 120m   ¼ 12% iOðAVGÞ =dO dIN vIN ð250m=33%Þð67%Þð2Þ

Note: RL consumes roughly 12% of PIN.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Buck-Boost with RL in CCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 692n 1u vin vin 0 dc¼2 sei vin vswi de 0 sw1v ddg 0 vswi idiode lx vswi vl 10u rl vl vswo 200m seg vswo 0 de 0 sw1v ddo vswo vo idiode vo vo 0 dc¼4 .ic i(lx)¼700m .lib lib.txt (continued)

182

4

Power Losses

.tran 1u .end Tip: Plot i(Rl), v(vswi), and v(vswo); extract i(Rl)’s RMS; and use it to calculate iR(RMS)2RL. B. Energize and Drain Resistances Energize switches conduct iL across tE only. So their current iRE is iL across tE and zero across tD, like Fig. 4.18 shows. Energize resistance RE therefore consumes a tE/tSW fraction of the power RE burns across tE. Since iRE’s average and ripple across tE match iL’s iL(AVG) and ΔiL, input and ground energize resistances REI and REG in RE dissipate




PRE ¼ iREðRMSÞ RE ¼ iEðAVGÞ þ iACðRMSÞ RE 2

" ¼

iOðAVGÞ dO

2

 þ

2

0:5ΔiL pffiffiffi 3

2

2 #



tE



tSW

ðREI þ REG ÞdE ,

ð4:21Þ

where iRE’s iE(AVG) and iAC(RMS) across tE match iL’s across tSW. Drain components similarly conduct iL across tD only. Dead times, however, shorten the times that drain switches close. So drain-switch current iRD is iL across the tD that excludes two tDT’s: tD' or tD – 2tDT and zero across tE. Drain resistance RD therefore consumes a tD'/tSW fraction of the power RD burns across tD'. Since iRD’s average across tD' matches iL’s iL(AVG) when tDT’s are symmetrical and iRD’s ripple matches iL’s ΔiL when tDT’s are much shorter than tSW, ground and output drain resistances RDG and RDO in RD burn: PRD ¼ iRDðRMSÞ 2 RD  
 t  2tDT ¼ iDðAVGÞ 2 þ iACðRMSÞ 2 RD D tSW " 2    2 # iOðAVGÞ 0:5ΔiL 2t pffiffiffi  þ ðRDG þ RDO Þ dD  DT , dO tSW 3 where iRD’s iD(AVG) and iAC(RMS) across tD roughly match iL’s across tSW.

Fig. 4.18 Energize and drain resistor currents

ð4:22Þ

4.3 Ohmic Loss

183

Example 2: Determine PRE and σRE for MEG in the ideal buck–boost from Example 1 in CCM when REG is 200 mΩ. Solution: dIN ¼ dE  67%, dO ¼ dD  32% and ΔiL  130 mA from Example 1 "   2 # iOðAVGÞ 2 0:5ΔiL pffiffiffi PRE ¼ þ REG dE dO 3 ( 2  2 ) 0:5ð130mÞ 250m pffiffiffi ¼ þ ð200mÞð67%Þ ¼ 77 mW 33% 3 σRE ¼


PRE 77m  ¼ 7:6% ¼ iOðAVGÞ =dO dIN vIN ð250m=33%Þð67%Þð2Þ

Note: MEG dissipates less of PIN than RL because MEG conducts iL a tE fraction of tSW. But since MDO conducts the other tD fraction of tSW, MEG and MDO together can consume as much as RL.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Buck-Boost with REG in CCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 684n 1u vin vin 0 dc¼2 sei vin vswi de 0 sw1v ddg 0 vswi idiode lx vswi vswo 10u seg vswo 0 de 0 sw1v200m ddo vswo vo idiode vo vo 0 dc¼4 .ic i(lx)¼700m .lib lib.txt (continued)

184

4

Power Losses

.tran 1u .end Tip: Plot i(Seg), v(vswi), and v(vswo); extract i(Seg)’s RMS; and use it to calculate iR(RMS)2REG. C. Output Capacitor The ultimate aim of voltage regulators and LED drivers is to supply iO. Supplying this iO, however, is impossible when the output switch is open. The purpose of CO in Fig. 4.19 is to supply iO when SDO opens. DC current into CO must be zero for vO and iO to remain steady. So on average, SDO outputs the iO that feeds the load. But since SDO opens a tE fraction of tSW, iDO’s iD(AVG), which matches iL(AVG), supplies a correspondingly higher reverse dO translation of iO: iO/dO. iDO is zero otherwise like Fig. 4.20 shows. So CO supplies iO when SDO opens and receives iO/dO minus iO otherwise. CO’s ESR RC therefore burns power with iO across tE and with iDO across tO: PRCðDOÞ ¼ PRC jtE þ PRC jtO   h i  
2 tE t 2 2 ¼ iOðAVGÞ RC þ iDðAVGÞ  iOðAVGÞ þ iACðRMSÞ RC O tSW tSW " 2  2 # iOðAVGÞ 0:5ΔiL 2 pffiffiffi ¼ iOðAVGÞ RC dE þ  iOðAVGÞ þ RC dO , dO 3 ð4:23Þ where iO(AVG) is equivalent to iO in Fig. 4.19, RC’s iC(AVG) across tO is iDO(AVG)’s iO/dO minus iO, and iAC(RMS) is a root-three fraction of half iDO’s ripple ΔiL.

Fig. 4.19 Switched-inductor voltage regulator or LED driver

Fig. 4.20 Duty-cycled inductor drain current

4.3 Ohmic Loss

185

Example 3: Determine PRC and σRC for CO in an ideal boost in CCM when vIN is 2 V, vO is 4 V, iO(AVG) is 250 mA, LX is 10 μH, tSW is 1 μs, and RC is 200 mΩ. Solution: Boost

∴

dIN ¼ 1

vD v  vIN 4  2 ¼ 50% ∴ dO ¼ dD ¼ 1  dE ¼ 1  50% ¼ 50% ¼ O ¼ 4 vE þ vD vO       vE vIN 2 ð50%Þð1μÞ ¼ 100 mA ΔiL ¼ tE ¼ dE tSW  10μ LX LX " 2  2 # i 0:5Δi O ð AVG Þ L pffiffiffi PRC ¼ iOðAVGÞ 2 RC dE þ  iOðAVGÞ þ R C dO dO 3 ( 2  2 ) 0:5ð100mÞ 250m 2 pffiffiffi  250m þ ¼ ð250mÞ ð200mÞð50%Þ þ ð200mÞð50%Þ 50% 3 ¼ 13 mW dE ¼

PRC 13m  σRC ¼
¼ ¼ 1:3% iOðAVGÞ =dO dIN vIN ð250m=50%Þð1Þð2Þ Note: RC consumes 1.3% of PIN.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Boost with RC in CCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 504n 1u vin vin 0 dc¼2 lx vin vswo 10u seg vswo 0 de 0 sw1v ddo vswo vo idiode (continued)

186

4

Power Losses

co vo vc 5u rc vc 0 200m io vo 0 dc¼250m .ic i(lx)¼450m v(vo)¼4 .lib lib.txt .tran 1u .end Tip: Plot i(Rc) and v(vswo), extract i(Rc)’s RMS, and use it to calculate iR(RMS)2RC. In a buck, LX connects to vO. This means that iL ripples about the average that supplies iO(AVG). In other words, iO is iL(AVG), iC(AVG) is zero, and CO conducts iL’s ripple. So the purpose of CO in the buck is to supply and sink up to half iL’s ripple. Since half ΔiL is oftentimes much lower than the iO that CO in Fig. 4.19 supplies across tE, PRC in the buck in Fig. 4.21 is usually much lower than in the boost and buck–boost:
 PRCðBKÞ ¼ iCðRMSÞ 2 RC ¼ iCðAVGÞ 2 þ iACðRMSÞ 2 RC "  2 #  2 0:5Δi 0:5ΔiL L 2 pffiffiffi pffiffiffi ¼ 0 þ RC , RC ¼ 3 3

ð4:24Þ

where iC’s iAC(RMS) matches iL’s.

Example 4: Determine PRC and σRC for CO in an ideal buck in CCM when vIN is 4 V, vO is 2 V, iO(AVG) is 250 mA, LX is 10 μH, tSW is 1 μs, and RC is 200 mΩ. Solution: Buck

Fig. 4.21 Switched-inductor buck voltage regulator or LED driver

∴

dO ¼ 1

4.3 Ohmic Loss

187

vD v 2 ¼ O ¼ ¼ 50% ∴ dD ¼ 1  dE ¼ 1  50% ¼ 50% vE þ vD vIN 4       vE vIN  vO 42 ð50%Þð1μÞ ¼ 100 mA ΔiL ¼ tE ¼ dE tSW ¼ 10μ LX LX

dIN ¼ dE ¼

PRC ¼

 2  2 0:5ð100mÞ 0:5ΔiL pffiffiffi pffiffiffi RC ¼ ð200mÞ ¼ 170 μW 3 3

PRC 170μ  ¼ < 0:1% σRC ¼
iOðAVGÞ =dO dIN vIN ð250m=1Þð50%Þð4Þ Note: RC dissipates less of PIN in the buck than in the boost because RC conducts half of ΔiL only. In the boost, RC conducts iO-level currents.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Buck with RC in CCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 500n 1u vin vin 0 dc¼4 sei vin vswi de 0 sw1v ddg 0 vswi idiode lx vswi vo 10u co vo vc 5u rc vc 0 200m io vo 0 dc¼250m .ic i(lx)¼200m v(vo)¼2 .lib lib.txt .tran 1u .end Tip: Plot i(Rc) and v(vswi), extract i(Rc)’s RMS, and use it to calculate iR(RMS)2RC.

188

4

4.3.3

Power Losses

Discontinuous Conduction

A. Switched Inductor iL in DCM rises to iL(PK) after tE and falls to zero before tSW ends. Since no part of iL is steady across tSW, all of iL flows through the skin of LX. This means that RL(AC) is the only part of LX that consumes PRL. This PRL is a tC/tSW fraction of the RMS power burned across tC: PRL ¼ iLðRMSÞ 2 RLðACÞ ¼ iCðRMSÞ 2 RLðACÞ



tC



tSW    2 iLðPKÞ t ¼ pffiffiffi RLðACÞ C , t SW 3

ð4:25Þ

where iC(RMS) is iL’s RMS across tC, which is a root-three fraction of half iL’s DCM peak iL(PK).

Example 5: Determine PRL and σRL for LX in the ideal boost from Example 3 in DCM when iO(AVG) is 10 mA and RL(AC) is 200 mΩ. Solution:

iLðPKÞ

dIN ¼ 1, dE ¼ 50%, and dO ¼ dD ¼ 50% from Example 3 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi  

  ffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  vE iO 2 10m ¼ 63 mA ¼ 2ð50%Þð1μÞ ¼ 2dE tSW 10μ 50% LX dO 

     iLðPKÞ LX 63m 10μ tC ¼ ¼ 630 ns ¼ 2 dE vE 50% 

PRL ¼

iLðPKÞ pffiffiffi 3



2 RLðACÞ

tC

tSW



 2   63m 630n ¼ 170 μW ¼ pffiffiffi ð200mÞ 1μ 3

PRL 170μ  ¼ 0:4% ¼ σRL ¼
ð 10m=50% Þ ð 2Þ iOðAVGÞ =dO dIN vIN Note: RL dissipates 0.4% of PIN.

4.3 Ohmic Loss

189

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Boost with RL in DCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 315n 1u vin vin 0 dc¼2 lx vin vl 10u rl vl vswo 200m seg vswo 0 de 0 sw1v ddo vswo vo idiode co vo 0 5u io vo 0 dc¼10m .ic i(lx)¼0 v(vo)¼4 .lib lib.txt .tran 1u .end Tip: Plot i(Rl) and v(vswo), extract i(Rl)’s RMS, and use it to calculate iR 2 (RMS) RL. B. Energize and Drain Resistances Energize and drain switches similarly consume tE/tSW and tD/tSW fractions of the RMS power RE and RD burn across tE and tD: PRE ¼ iREðRMSÞ 2 RE   t ¼ iEðRMSÞ 2 RE E tSW     iLðPKÞ 2 t ¼ pffiffiffi ðREI þ REG ÞdE C t SW 3 PRD ¼ iRDðRMSÞ 2 RD   t ¼ iDðRMSÞ 2 RD D tSW     iLðPKÞ 2 t ¼ pffiffiffi ðRDG þ RDO ÞdD C : t SW 3

ð4:26Þ

ð4:27Þ

REI and REG in RE burn PRE and RDG and RDO in RD burn PRD. iL’s RMS across tE, tD, and tC are all root-three fractions of iL(PK) because iL is triangular and peaks to iL(PK) in all three cases.

190

4

Power Losses

C. Output Capacitor In DCM, SDO opens across tE and the period that follows tC before tSW ends. This corresponds to the part of tSW that excludes tO. CO supplies iO across this time and the part of iO that iL does not when SDO closes. So RC consumes power with iO(AVG) across tSW – tO and with iD – iO across tO: PRCðDOÞ ¼ PRC jtSW tO þ PRC jtO   h i  
2 t t t ¼ iOðAVGÞ 2 RC SW O þ iDðAVGÞ  iOðAVGÞ þ iACðRMSÞ 2 RC O tSW tSW  #    " 2    iLðPKÞ 0:5iLðPKÞ 2 t t pffiffiffi  iOðAVGÞ þ ¼ iOðAVGÞ 2 RC 1  dO C þ RC dO C : tSW 2 tSW 3

ð4:28Þ Across tO, iD’s average iD(AVG), which is half iL(PK), minus iO(AVG) burns steady power and iD’s ripple iL(PK) burns alternating power.

Example 6: Determine PRC and σRC for CO in the ideal boost from Examples 3 and 5 in DCM when RC is 200 mΩ. Solution: dIN ¼ 1, dE ¼ 50%, dO ¼ dD ¼ 50%, iLðPKÞ ¼ 63 mA, and tC ¼ 630 ns from Examples 3 and 5 2     # iLðPKÞ 0:5iLðPKÞ 2 t pffiffiffi PRC ¼ iOðAVGÞ RC 1  dO þ  iOðAVGÞ þ RC dO C tSW 2 tSW 3 2 #    "  2    630n 63m 63m 630n 2 ¼ ð10mÞ ð200mÞ 1  50% ð200mÞð50%Þ þ  10m þ pffiffiffi 1μ 2 1μ 2 3 

2



tC



"

¼ 64 μW

PRC 64μ  ¼ 0:2% σRC ¼
¼ iOðAVGÞ =dO dIN vIN ð10m=50%Þð1Þð2Þ Note: RC dissipates less of PIN than RL in Example 5 because RC does not conduct the part of iL that feeds iO.

4.4 Diode Loss

191

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Boost with RC in DCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 315n 1u vin vin 0 dc¼2 lx vin vswo 10u seg vswo 0 de 0 sw1v ddo vswo vo idiode co vo vc 5u rc vc 0 200m io vo 0 dc¼10m .ic i(lx)¼0 v(vo)¼4 .lib lib.txt .tran 1u .end Tip: Plot i(Rc) and v(vswo), extract i(Rc)’s RMS, and use it to calculate iR 2 (RMS) RC. In a buck, RC conducts iL – iO across tSW because LX connects to vO. But since iL is non-zero only across tC, RC consumes power with iL – iO across tC and with iO across tSW – tC: PRCðBKÞ ¼ PRC jtC þ PRC jtSW tC   h
i   2 tC tSW  tC 2 2 ¼ iCðAVGÞ  iOðAVGÞ þ iACðRMSÞ RC þ iOðAVGÞ RC tSW tSW : " # 2      2 iLðPKÞ 0:5iLðPKÞ t t pffiffiffi ¼  iOðAVGÞ þ RC C þ iOðAVGÞ 2 RC 1  C 2 tSW tSW 3 ð4:29Þ Across tC, iL’s average 0.5iL(PK) minus iO burns steady power and iL’s ripple iL(PK) burns alternating power.

4.4

Diode Loss

4.4.1

Conduction Power

A static dc voltage vX that conducts a ramping current like iX in Fig. 4.17 burns the power that iX’s average across that time iX(AVG) into vX sets:

192

4

PVX ¼

1 tX

ZtX

0 iX vX dt ¼ @

1 tX

0

ZtX

Power Losses

1 iX dtAvX ¼ iXðAVGÞ vX :

ð4:30Þ

0

This iX(AVG) is iX’s minimum iX(MIN) plus half iX’s variation ΔiX:

iXðAVGÞ

1 ¼ tX

ZtX

1 iX dt ¼ tX

ZtX 

0

  ΔiX Δi iXðMINÞ þ t dt ¼ iXðMINÞ þ X : tX 2

ð4:31Þ

0

So PV’s average PVX climbs linearly with iX’s average iX(AVG).

4.4.2

Diode Drain Power

Asynchronous drain diodes conduct iL across tD. So on average, DDG and DDO burn power with vDG and vDO and iL’s average across a tD fraction of tSW. This tD fraction is dD in CCM and a tC fraction of tSW lower in DCM:  PDD  iLðAVGÞ ðvDG þ vDO Þ

tD tSW



 ¼

   iOðAVGÞ t ðvDG þ vDO ÞdD C , dO tSW

ð4:32Þ

where iL(AVG) is a reverse dO translation of iO(AVG). This diode drain power PDD is higher in CCM. This is because tD scales with dD and tD is a larger fraction of tSW in CCM than in DCM. The resulting fractional loss σDD can be significant when DDG and DDO drop 600–800 mV across more than 10% of tSW. Synchronous implementations are more efficient because MDG and MDO usually drop much lower voltages, on the order of millivolts. Dead-time diodes still conduct and burn power with vDG and vDO and iL, but only across tDT’s, which are typically shorter than tD. These benefits fade, however, when tDT’s become larger fractions of tSW, which happens when fSW is high.

4.4.3

Dead-Time Power

A. Continuous Conduction Dead-time diodes conduct across tDT’s the iL that LX holds before and after LX energizes. Although iL ramps over time, tDT’s are usually so much shorter than tSW that iL is fairly steady across tDT’s. So across the tDT that follows tE, when LX begins to drain, iL is fairly steady at iL(HI). iL is similarly steady at iL(LO) across the tDT that precedes tE. DDG and DDO consume power with iL(HI) and iL(LO) across these tDT’s. Since iL is nearly steady and diode voltages are largely insensitive to current variations, these

4.4 Diode Loss

193

diodes burn static power across tDT’s and dead-time fractions across tSW. So deadtime power PDT is 

   tDT t þ iLðLOÞ ðvDG þ vDO Þ DT tSW tSW   t  2iLðAVGÞ ðvDG þ vDO Þ DT tSW     iOðAVGÞ 2tDT ¼ ðvDG þ vDO Þ : dO tSW

PDT  iLðHIÞ ðvDG þ vDO Þ

ð4:33Þ

Diode voltages can be so insensitive to current variations that DDG and DDO can drop similar vDG’s and vDO’s with iL(HI) and iL(LO). So iL(HI) and iL(LO) burn power with approximately equal tDT fractions of similar vDG’s and vDO’s. And since iL(HI) and iL(LO) average iL(AVG), iL(HI) and iL(LO) add to 2iL(AVG). This means that a reverse dO translation of iO(AVG) burns PDT with vDG and vDO across two tDT fractions of tSW. Interestingly, PDT is nearly a constant (current-independent) fraction of PIN. This is because PDT and PIN both scale linearly with iL(AVG): σDT

P PDT PDT ¼ DT ¼ ¼ ¼ PIN iINðAVGÞ vIN iLðAVGÞ dIN vIN



vDG þ vDO dIN vIN

  2tDT : tSW

ð4:34Þ

So PDT’s fraction of PIN ultimately hinges on the voltage and time fractions that diode voltages and tDT’s establish with dINvIN and tSW.

Example 7: Determine PDT and σDT in an ideal boost in CCM when vIN is 2 V, vO is 4 V, iO(AVG) is 250 mA, LX is 10 μH, tSW is 1 μs, DDO drops 800 mV, and tDT is 50 ns. Solution: Boost ∴ dIN ¼ 1   

 vD v  vIN v 2tDT 42 800m 2ð50nÞ dE ¼ ¼ 52% þ ¼ O þ DO ¼ 1μ 4 4 vE þ vD vO vO tSW ∴ dO ¼ dD ¼ 1  dE ¼ 1  52% ¼ 48%       vE vIN 2 ΔiL ¼ ð52%Þð1μÞ ¼ 100 mA tE ¼ dE tSW  10μ LX LX

194

4

PDT

Power Losses

       iOðAVGÞ 2ð50nÞ 2tDT 250m ¼ 42 mW ð800mÞ ¼ vDO ¼ 1μ dO tSW 48% σDT ¼


PDT 42m  ¼ 4:0%  ð 250m=48% Þ ð 1Þ ð 2Þ iOðAVGÞ =dO dIN vIN

Note: Dead-time diodes can consume considerable power.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Boost with Dead Time in CCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 519n 1u vdo do 0 dc¼1 pulse 0 1 570n 1n 1n 381n 1u vin vin 0 dc¼2 lx vin vswo 10u seg vswo 0 de 0 sw1v sdo vswo vo do 0 sw1v ddo vswo vo fdiode1 vo vo 0 dc¼4 .ic i(lx)¼470m .lib lib.txt .tran 1u .end Tip: Plot i(Ddo), v(vswo), and I(Ddo)*(v(vswo)-v(vo)) and extract the average of the product term.

B. Discontinuous Conduction iL in discontinuous conduction rises to iL(PK) after tE and falls to zero across tD before tSW ends. So iL is nearly iL(PK) across the first tDT in tD and nearly zero across the second. Dead-time diodes therefore consume noticeable power only across the first tDT:  PDT  iLðPKÞ ðvDG þ vDO Þ

 tDT : tSW

PDT’s fraction of PIN is the product of three ratios:

ð4:35Þ

4.4 Diode Loss

σDT

195

P P PDT ¼ DT ¼ DT ¼ ¼ PIN iIN vIN iLðAVGÞ dIN vIN



   vDG þ vDO tDT : ð4:36Þ iLðAVGÞ dIN vIN tSW iLðPKÞ

The current ratio is greater than one, the voltage ratio is lower than one, and the time ratio is usually a small fraction. So diode and tDT fractions counter the effect of current gain. And since iL(AVG) scales faster with iO(AVG) than iL(PK) with √iO(AVG), PDT’s fraction of PIN falls with increasing √iO(AVG).

Example 8: Determine PDT and σDT in an ideal buck in DCM when vIN is 4 V, vO is 2 V, iO(AVG) is 10 mA, LX is 10 μH, tSW is 1 μs, tDT is 50 ns, and DDG drops 700 mV. Solution: ∴ dO ¼ 1    vD v v tDT v 2 dIN ¼ dE ¼ ¼ O þ DG  O ¼ ¼ 50% vE þ vD vIN vIN tC vIN 4 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi     ffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi vE 42 iLðPKÞ ¼ 2dE tSW ð10mÞ ¼ 45 mA i  2ð50%Þð1μÞ LX O 10μ Buck

 PDT ¼ iLðPKÞ vDG σDT ¼


tDT tSW

  ð45mÞð700mÞ

  50n ¼ 1:6 mW 1μ

PDT 1:6m  ¼ 8:0%  iOðAVGÞ =dO dIN vIN ð10m=1Þð50%Þð4Þ

Note: PDT is a higher fraction of PIN in DCM than in CCM because PIN scales down faster with iO than PDT with √iO.

196

4

Power Losses

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Buck with Dead Time in DCM vde de 0 dc¼0 pwl 0 1 225n 1 225.1n 0 vdo do 0 dc¼1 pwl 0 0 275n 0 275.1n 1 432n 1 432.1n 0 vin vin 0 dc¼4 sei vin vswi de 0 sw1v sdg vswi 0 do 0 sw1v ddg 0 vswi fdiode1 cswi vswi 0 1p lx vswi vo 10u vo vo 0 dc¼2 .ic i(lx)¼0 .lib lib.txt .tran 1u .end Tip: Plot i(Ddg), v(vswi), and i(Ddg)*v(vswi) and extract the average of the product term.

4.5

iDS–vDS Overlap Loss

iDS–vDS overlap power PIV refers to the transitional power transistors consume when switching between on and off states. PIV is essentially the power the drain–source current iDS burns across the drain–source voltage vDS the transistor drops when iDS and vDS transition. This loss hinges on the iL that iDS carries, the voltage vDS collapses, and their transition times. Since iDS scales with gate–source voltage vGS, the underlying goal of gate drivers is to transition gate voltages quickly. So they charge and discharge gate–source and gate–drain oxide capacitances CGS and CGD with low pull-down and pull-up N- and P-type resistances RN and RP. The resulting transitions should be (by design) shorter than dead times. This way, iL is practically steady across these events.

4.5.1

Closing Switch

A. Power When a switch is open, vGS and iDS are zero and vDS is high at a level that other circuit components set. This vDS is, in effect, the variation ΔvSW the switch collapses after it closes. So when closing, vGS and iDS climb and vDS falls.

4.5 iDS–vDS Overlap Loss

197

Fig. 4.22 Closing switch

In Fig. 4.22, MSW closes as RP charges CGS and CGD. iDS climbs with vGS after vGS overcomes MSW’s zero-bias threshold VT0. vDS falls later, when iDS is high enough to sink the iL that LX carries and the iGD and iSW that CGD and other switchnode capacitances CSW need to discharge. When this happens, iP slews CGD at the vGS (and iDS) needed to sink iL, iP, and iSW, so vGS is fairly flat across this time. When iL overwhelms iP and iSW, vDS falls after iDS reaches iL. Since vDS remains at ΔvSW across the time tI that iDS needs to reach iL, MSW burns power PI across tI with ΔvSW and iDS’s average: ZtI 1 PI ¼ iDS vDS dt tI 0 0 t 1 ZI 1 ¼@ iDS dtAΔvSW tI 0 2 t 3   ZI   1 i i L 2 5 4  t dt ΔvSW  L ΔvSW : tI 3 tI 2

ð4:37Þ

0

iDS’s rise is almost quadratic with time t because vGS is close to linear when iDS climbs to iL and iDS scales with vGS2 in MOSFET inversion. So across tI, iDS’s quadratic increase averages to about a third of iL. iL also burns power PV with vDS’s average because iDS is iL across the time tV that vDS requires to collapse: PV ¼

1 tV

ZtV

0 iDS vDS dt  iL @

1 tV

0

ZtV

1 vDS dtA  iL



 ΔvSW : 2

ð4:38Þ

0

vDS averages half of ΔvSW because vDS is largely linear. When combined, MSW consumes 33% and 50% of iLΔvSW across tI and tV, so PIV across tSW is:  PIV ¼ PI

tI

tSW



 þ PV

tV

tSW



  iL ΔvSW

 tI t þ V : 3tSW 2tSW

ð4:39Þ

198

4

Power Losses

B. Delays iDS scales with vGS and maxes when vGS reaches the vGS threshold vTH needed to sustain iL, iP, and iSW. This vTH is usually higher than VT0 because iL is normally high. Since vDS exceeds vGS at this point, MSW inverts in saturation when vGS overcomes VT0. When iL is much greater than iP and iSW, the closing vTH is largely the vGS needed to sustain iL: vTHðCÞ ¼ vGS jiLðCÞ þiP þiSW

  VT0 þ vDSðSATÞ 

iLðCÞ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iLðCÞ ,  VT0 þ K' ðW=LÞ

ð4:40Þ

where vDS(SAT) is the saturation voltage of MSW in inversion. iDS does not rise much until MSW inverts. So tI(C) is mostly the time vGS requires to rise from VT0 to vTH(C). In other words, tI is the fraction of the time tTH needed to charge CGS to vTH(C) that excludes the time tT0 needed to charge CGS to VT0. Since the gate driver’s power supply vDD and RP require RC time tX to charge CGS and CGD across ΔvX, tX and tI(C) are  tX ¼ τRC ln

vDD vDD  ΔvX

and



 tIðCÞ  tTH  tT0 ¼ τRCðCÞ ln

 vDD  VT0 , vDD  vTHðCÞ

ð4:41Þ

ð4:42Þ

where τRC(C) is the time constant of RP and CGS and CGD in saturation:

 h i 2 CCH , τRCðCÞ ¼ RP ðCGS þ CGD Þ  RP 2COL þ 3

ð4:43Þ

and COL is overlap capacitance, CCH is channel capacitance, and CGS is COL plus two-thirds CCH and CGD is COL in saturated inversion. vDS falls when iDS sinks iL, CGD’s iP, and CSW’s iSW. Although iDS is sensitive to vGS and capable of sinking more current, RP limits the current that feeds CGD. So the time tV(C) that vDS requires to collapse across ΔvSW is the time CGD’s voltage vC needs to traverse ΔvSW, which is a slew-rate translation of RP’s current iP into CGD:  tVðCÞ 

 ΔvC CGD iP

 0:5CCH  vGS COL ΔvSW þ 2  h

 i RP C  COL ΔvSW þ CH vTHðCÞ : vDD  vTHðCÞ 4 

RP vDD  vGS





ð4:44Þ

iP slews CGD at the vGS needed to sustain iL, iP, and iSW. So vGS is steady at vTH(C) across tV and vDD – vTH(C) across RP sets iP. As vDS collapses, MSW transitions from saturation to triode, so CGD receives half of CCH.

4.5 iDS–vDS Overlap Loss

199

The 0.25CCH average of this 0.5CCH therefore traverses the vDS that transitions MSW into triode, which starts when vDS matches vGS at vTH(C) when vGD is zero. This is why vDS collapses more quickly at the beginning of the transition: because CGD’s saturated COL is easier to discharge than CGD’s triode counterpart, which carries COL plus half of CCH. In short, CGD slows vDS’s transition when vDS falls below vGS.

Example 9: Determine PIV and σIV for MEG in the ideal boost from Example 7 in CCM when MEG closes, vDD for MEG’s gate driver is vO, WEG is 50 mm, LEG is 250 nm, LOL is 30 nm, VTN0 is 400 mV, KN' is 200 μA/V2, COX'' is 6.9 fF/μm2, and RP is 100 Ω. Solution: dIN ¼ 1, dE ¼ 52%, dO ¼ dD ¼ 48%, and ΔiL ¼ 100 mA from Example 7 MEG closes when iL ¼ iLðLOÞ iLðLOÞ ¼

iO ΔiL 250m 100m  ¼ 470 mA ¼  2 dO 2 48% WCH ¼ WEG ¼ 50 mm

vDSðSATÞ

LCH ¼ LEG  2LOL ¼ 250n  2ð30nÞ ¼ 190 nm sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iLðLOÞ 2ð470mÞ  ¼ ¼ 130 mV 0 KN ðWCH =LCH Þ ð200μÞð50m=190nÞ

vTHðCÞ  VTN0 þ vDSðSATÞ ¼ 400m þ 130m ¼ 530 mV COL ¼ COX 00 WCH LOL ¼ ð6:9mÞð50mÞð30nÞ ¼ 10 pF CCH ¼ COX 00 WCH LCH ¼ ð6:9mÞð50mÞð190nÞ ¼ 66 pF

 h

 i h i 2 2 τRCðCÞ ¼ RP 2COL þ CCH ¼ ð100Þ 2ð10pÞ þ ð66pÞ ¼ 6:4 ns 3 3  

 vDD  VT0 4  400m ¼ 240 ps tIðCÞ  τRCðCÞ ln ¼ ð6:4nÞ ln 4  530m vDD  vTHðCÞ vSWO ¼ vO þ vDO ¼ 4 þ 800m ¼ 4:8 V before MEG closes ∴

ΔvSWO ¼ 4:8 V

200

4

Power Losses



PIV

h

 i RP C tVðCÞ  COL ΔvSWO þ CH vTHðCÞ vDD  vTHðCÞ 4  

 100 66p ¼ ð10pÞð4:8Þ þ ð530mÞ ¼ 1:6 ns 4  530m 4    tIðCÞ tVðCÞ 240p 1:6n þ ¼ 2:0 mW  iLðLOÞ ΔvSWO þ ¼ ð470mÞð4:8Þ 3tSW 2tSW ð3Þ1μ ð2Þ1μ PIV 2:0m  ¼ ¼ 0:2% σIV ¼
iOðAVGÞ =dO dIN vIN ð250m=48%Þð1Þð2Þ

Note: This PIV excludes the power consumed when MEG opens and other switches open and close.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * I-V Overlap Loss when MEG Closes without Reverse Recovery vdd vdd 0 dc¼4 rp vdd vg 100 lx 0 vswo 10u meg vswo vg 0 0 nmos1 w¼50m l¼250n ddo vswo vo fdiode1 vo vo 0 dc¼4 .ic i(lx)¼470m v(vg)¼0 .lib lib.txt .tran 5n .end Tip: Plot id(Meg), v(vg), v(vswo), and id(Meg)*v(vswo), extract the average of the product term across 5 ns, and average across the 1-μs period (multiply by 5 ns of the 1-μs period or 0.5%) to determine PIV. id(Meg) often includes CGD’s current, so the extraction is not perfect. In this case, iD is considerably greater than iGD, so the approximation is fair.

4.5 iDS–vDS Overlap Loss

201

Fig. 4.23 Opening switch

4.5.2

Opening Switch

A. Power After MSW closes, vGS is high, iDS carries iL, and vDS is close to zero. To open MSW, RN in Fig. 4.23 collapses vGS. iDS, however, does not fall until vGS drops below the vTH needed to sink iL minus CGD’s iN and CSW’s iSW. Even then, iN slews CGD at the vGS (and iDS) needed to sustain this iDS. So vGS is fairly flat when iN and iSW charge CGD and CSW across ΔvSW. vDS rises across the tV(O) that iN needs to charge CGD across the ΔvSW other circuit components set. PV is the power vDS’s average 50%ΔvSW burns across tV(O) with iDS at iL minus iN and iSW. When iL overwhelms iN and iSW, vTH is largely the vGS needed to sustain iL: vTHðOÞ ¼ vGS jiLðOÞ iN iSW

  VT0 þ vDSðSATÞ 

iLðOÞ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iLðOÞ :  VT0 þ K' ðW=LÞ

ð4:45Þ

Since vDS stops rising after transitioning across ΔvSW, the effect of iN on CGD after tV(O) is to decrease vGS. For this to happen, part of iN must also discharge CGS. The end result is that iDS drops across the tI(O) that iN needs to reduce vGS from vTH(O) to VT0. PI is roughly the power iDS’s quadratic average 33%iL burns across this tI(O) with vDS at ΔvSW. B. Delays Since vGS is vTH(O) across tV(O), iN is an Ohmic RN translation of vTH(O). So vTH(O)/RN slews CGD’s COL across ΔvSW and CGD’s channel average 0.25CCH across the vDS that transitions MSW into triode, which starts when vDS matches vGS’s vTH(O). The resulting tV(O) is tVðOÞ 

      ΔvC RN 0:5CCH vGS CGD  COL ΔvSW þ iN vGS 2  h

 i RN C  COL ΔvSW þ CH vTHðOÞ : vTHðOÞ 4

ð4:46Þ

202

4

Power Losses

Once vDS reaches ΔvSW, RN’s current iN reduces vGS. So iDS falls across the tI(O) that RN needs to discharge CGS (and CGD) from vTH(O) to VT0. In other words, tI(O) is the part of the time tT0 needed to discharge CGS to VT0 that excludes the time tTH needed to discharge CGS to vTH(O). CGS therefore discharges vDD – vTH(O) across tTH, vDD – VT0 across tT0, and vTH(O) – VT0 across their difference tT0 – tTH, which is tI(O): tIðOÞ  tT0  tTH


 vDD  vDD  vTHðOÞ ¼ τRCðOÞ ln vDD  ðvDD  VT0 Þ   vTHðOÞ ¼ τRCðOÞ ln , VT0 

ð4:47Þ

where τRC(O) is the time constant of RN and CGS and CGD in saturation:

 h i 2 CCH : τRCðOÞ ¼ RN ðCGS þ CGD Þ  RN 2COL þ 3

ð4:48Þ

Note that RP pre-charges CGS to vDD before RN collapses CGS’s vGS.

Example 10: Determine PIV and σIV for MEG in the boost from Examples 7 and 9 in CCM when MEG opens and RN is 20 Ω. Solution: dIN ¼ 1, dE ¼ 52%, dO ¼ dD ¼ 48%, and ΔiL ¼ 100 mA from Example 7 LCH ¼ 190 nm, COL ¼ 10 pF, and CCH ¼ 66 pF from Example 9 MEG opens when iL ¼ iLðHIÞ iO ΔiL 250m 100m þ ¼ 570 mA ¼ þ 2 dO 2 48% sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iLðHIÞ 2ð570mÞ ¼  ¼ 150 mV ' ð200μÞð50m=190nÞ KN ðWCH =LCH Þ iLðHIÞ ¼

vDSðSATÞ

vTHðOÞ  VTN0 þ vDSðSATÞ ¼ 400m þ 150m ¼ 550 mV vSWO ¼ vO þ vDO ¼ 4 þ 800m ¼ 4:8 V after MEG opens ∴ ΔvSWO ¼ 4:8 V  h

 i RN C tVðOÞ  COL ΔvSWO þ CH vTHðOÞ vTHðOÞ 4  

 20 66p ð10pÞð4:8Þ þ ð550mÞ ¼ 2:1 ns ¼ 550m 4

4.5 iDS–vDS Overlap Loss

PIV

203

 h

 i h i 2 2 CCH ¼ ð20Þ 2ð10pÞ þ ð66pÞ ¼ 1:3 ns τRCðOÞ ¼ RN 2COL þ 3 3     vTHðOÞ 550m tIðOÞ  τRCðOÞ ln ¼ 410 ps ¼ ð1:3nÞ ln 400m VTN0    tIðOÞ tVðOÞ 410p 2:1n þ ¼ 3:2 mW  iLðHIÞ ΔvSWO þ ¼ ð570mÞð4:8Þ 3tSW 2tSW ð3Þ1μ ð2Þ1μ PIV 3:2m  ¼ 0:3% ¼ σIV ¼
ð 250m=48% Þð1Þð2Þ iOðAVGÞ =dO dIN vIN

Note: RN is lower than RP to balance response times (because vTH(O) is lower than vDD – vTH(C) in tV and vGS reaches VTN0 near the end of RN’s exponential response, where the response is slower). MEG still consumes more power opening than closing because iDS is higher at iL(HI).

Explore with SPICE: See Appendix A for notes on SPICE simulations. * I-V Overlap Loss when MEG Opens rn vg 0 20 lx 0 vswo 10u meg vswo vg 0 0 nmos1 w¼50m l¼250n ddo vswo vo diode1 vo vo 0 dc¼4 .ic i(lx)¼570m v(vg)¼4 .lib lib.txt .tran 9n .end Tip: Plot id(Meg), v(vg), v(vswo), and id(Meg)*v(vswo), extract the average of the product term across 9 ns, and multiply by 0.9% (9 ns of the 1-μs period). id(Meg) often includes CGD’s current, so the extraction is not perfect. In this case, iD is considerably greater than iGD, so the approximation is fair.

204

4.5.3

4

Power Losses

Reverse Recovery

A. Power Forward-biased in-transit charge across PN junctions reverses direction when diodes reverse-bias. In switched inductors, dead-time diodes carry this reverse-recovery charge qRR when conducting iL. qRR is the charge in the junction that iL feeds and forward transit time τF across the junction sets to iLτF. The challenge with qRR is that a switch must recover it when reverse-biasing a diode. In Fig. 4.24, for example, dead-time diode DDT conducts iL when MSW is open. So for vDS to fall when MSW closes, iDS must first rise to a peak iDS(RR) that sinks iL, iGD, iSW, and qRR held in DDT. And a higher iDS dissipates more PIV. As MSW closes, iDS climbs with vGS mostly after vGS overcomes VT0. If iL overwhelms iP and iSW, iDS reaches iL after tI(C) when vGS reaches vTH(C). iDS requires another tRR to reach a level that can sink qRR. Approximating iDS’s rise past iL to be linear with the slope ∂iDS/∂t that iDS’s quadratic climb (iL/tI(C)2)t2 reaches iL at tI(C) yields a tRR that is roughly a square-root translation of tI(C) and τF: ZtRR qRR ¼

ZtRR iDS dt 

0

0

    ZtRR  2iLðCÞ iLðCÞ ∂iDS  tdt  tdt ¼ t 2 ¼ iLðCÞ τF ð4:49Þ tIðCÞ tIðCÞ RR ∂t tIðCÞ 0

tRR 

pffiffiffiffiffiffiffiffiffiffiffiffi tIðCÞ τF :

ð4:50Þ

iDS(RR) is therefore a corresponding tRR extension of iL:  rffiffiffiffiffiffiffiffi! 2iLðCÞ τF  iLðCÞ þ t ¼ iLðCÞ 1 þ 2 : tIðCÞ RR tIðCÞ 

iDSðRRÞ

ð4:51Þ

The vGS that MSW requires to sink this iDS(RR) is vTH(RR):

vTHðRRÞ

 ¼ VT0 þ vDSðSATÞ 

iDSðRRÞ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iDSðRRÞ :  VT0 þ K' ðW=LÞ

ð4:52Þ

Since vDS is steady at ΔvSW across tI(C) and tRR, PI' is the power iDS(RR)’s quadratic average 33%iDS(RR) burns with ΔvSW across tI(C) and tRR.

Fig. 4.24 Closing switch with reverse recovery

4.5 iDS–vDS Overlap Loss

205

After iDS recovers qRR, iDS(RR) sinks more than iL supplies, so the excess discharges CGD and CSW. The iGD that iDS(RR), iL, and iSW avail is so much greater than iP that the part of iGD that excludes iP discharges CGS. CGD, CSW, and CGS discharge this way until iDS falls to the level that carries iL, iP, and iSW, which happens when vGS reaches vTH(C). Since iP is much lower than iGD, CGS supplies most of the charge ΔqGS that discharges CGD across ΔvDG, which amounts to ΔvDS minus ΔvGS: ΔqGD ¼ CGD ΔvDG ¼ CGD ðΔvDS  ΔvGS Þ
 ¼ CGD ΔvSW  vDSðRRÞ  ΔvGS
  ΔqGS ¼ CGS ΔvGS ¼ CGS vTHðRRÞ  vTHðCÞ

ð4:53Þ

¼ CGS ΔvTH , where CGS discharges across ΔvGS or ΔvTH from vTH(RR) to vTH(C) and vDS falls across ΔvDS from ΔvSW to vDS(RR). Solving this reveals vDS falls to approximately 

vDSðRRÞ

 CGS  ΔvSW  þ 1 ΔvTH : CGD

ð4:54Þ

This transition to vDS(RR) is quick because iGD is substantial. After iDS falls to a level that carries iL, iP, and iSW, iP discharges CGD across the tV(C)' that collapses vDS(RR). tV(C)' is shorter than tV(C) because vDS collapses a vDS(RR), that is lower than ΔvSW:  tVðCÞ ' 

RP vDD  vTHðCÞ

h

 i C COL vDSðRRÞ þ CH vTHðCÞ : 4

ð4:55Þ

Since iDS is steady near iL across tV(C)' when iL overwhelms iP and iSW, PV' is largely the power iL burns with vDS(RR)’s average 50%vDS(RR). And PIV' is a tSW fraction of PI' and PV':     tIðCÞ þ tRR tVðCÞ ' PIV ' ¼ PI ' þ PV ' tSW tSW     

v t iDSðRRÞ tIðCÞ þ tRR DSðRRÞ VðCÞ ' ΔvSW  þ iL : 3 tSW 2 tSW

ð4:56Þ

Interestingly, qRR not only raises the iDS that consumes PI' (to iDS(RR)) and extends the time the switch burns PI' (by tRR) but also reduces the vDS (to vDS(RR)) that burns PV'. The rise in iDS, however, normally raises PI' more than the fall in vDS(RR) reduces PV'. So reducing qRR usually saves power.

206

4

Power Losses

Example 11: Determine PIV and σIV for MEG in the ideal boost from Examples 7 and 9 in CCM when MEG closes and DDO’s τF is 5 ns. Solution: dIN ¼ 1, dE ¼ 52%, dO ¼ dD ¼ 48%, and ΔiL ¼ 100 mA from Example 7 iLðLOÞ ¼ 470 mA, vTHðCÞ ¼ 530 mV, ΔvSWO ¼ 4:8 V, LCH ¼ 190 nm, COL ¼ 10 pF, CCH ¼ 66 pF, RP ¼ 100 Ω, τRC ¼ 6:4 ns, and

tRR

tIðCÞ  240 ps from Example 9 pffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  tIðCÞ τF ¼ ð240pÞð5nÞ ¼ 1:1 ns

vDD  vTHðCÞ 4  530m ¼ ¼ 35 mA 100 RP      2iLðLOÞ 1:1n iDSðRRÞ  iLðLOÞ þ ¼ 4:8 A tRR ¼ ð470mÞ 1 þ 2 240p tIðCÞ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iDSðRRÞ 2ð4:8Þ vTHðRRÞ  VTN0 þ ¼ 400m þ ¼ 830 mV KN 0 ðWCH =LCH Þ ð200μÞð50m=190nÞ iP 




 COL þ ð2=3ÞCCH þ 1 vTHðRRÞ  vTHðCÞ vDSðRRÞ ¼ ΔvSWO  COL  10p þ ð2=3Þð66pÞ þ 1 ð830m  530mÞ ¼ 2:9 V ¼ 4:8  10p  h

 i 1 C tVðCÞ '  COL vDSðRRÞ þ CH vTHðCÞ iP 4  

 1 66p ¼ ð10pÞð2:9Þ þ ð530mÞ ¼ 1:1 ns 35m 4 PIV

    

v t iDSðRRÞ tIðCÞ þ tRR DSðRRÞ VðCÞ '  vSWO þ iLðLOÞ 3 tSW 2 tSW   



 4:8 240p þ 1:1n 2:9 1:1n ¼ ð4:8Þ þ ð470mÞ ¼ 11 mW 3 1μ 2 1μ PIV 11m  ¼ 1:1% ¼ σIV ¼
ð 250m=48% Þð1Þð2Þ iOðAVGÞ =dO dIN vIN

Note: This PIV is higher than in Example 9 because iDS(RR) is higher than iL(LO) and tI(C) + tRR is longer than tI(C) to a greater extent than vDS(RR) is lower than ΔvSWO.

4.5 iDS–vDS Overlap Loss

207

Explore with SPICE: Use the SPICE code from Example 9 and use “diode2” for DDO’s model. B. Approximation This reverse-recovery analysis approximates the peak that iDS reaches when recovering qRR. Although not bad, this calculation requires several steps. Another approach is to approximate the behavior of iDS in a way that, to some extent, preserves PIV. Like before, though, vDS is close to ΔvSW when MSW first closes and iDS climbs to iL(C) across tI(C). But instead of iDS climbing over iL(C) after tI(C) quadratically, assuming iDS reaches and maxes to twice iL(C) quickly (like Fig. 4.25 shows) simplifies the analysis. This way, the reverse-recovery current iRR that sinks qRR is iL(C). But since a quadratic rise in iL(C) recovers qRR more quickly than the constant iL(C) assumed, tRR is shorter than τF. Approximating tRR' to half τF reduces reverserecovery power PRR in PIV to iL(C)ΔvSW(τF/tSW). Although not very accurate, this PRR is not a bad approximation that is easy to calculate:  PRR  iDSðRRÞ ' ΔvSW

tRR ' tSW



  2iLðCÞ ΔvSW

0:5τF tSW



 ¼ iLðCÞ ΔvSW

 τF : ð4:57Þ tSW

And instead of vDS collapsing across a noticeable tV(C), assuming iDS(RR) is so high that it collapses vDS across a negligible tV(C) is not unreasonable, especially when considering the tRR that τF establishes with iL. With this approximation, the part of iDS(RR) that excludes iL discharges CGD and CGS to the extent vDS collapses and vGS falls to vTH(C) very quickly. PIV therefore excludes the PV(C) that a negligibly short tV(C) induces: PIV ¼ PIVðCÞ þ PIVðOÞ  PIðCÞ þ PRR þ PIðOÞ þ PVðOÞ     tIðCÞ tIðOÞ tVðOÞ τ  iLðCÞ ΔvSW þ F þ iLðOÞ ΔvSW þ : 3tSW tSW 3tSW 2tSW

Fig. 4.25 Closing switch with approximated reverse recovery

ð4:58Þ

208

4

Power Losses

All other close- and open-switch non-reverse-recovery components of PIV remain the same: PI(C) across tI(C), PI(O) across tI(O), and PV(O) across tV(O). Although behaviorally imprecise, this estimate is not bad. This is because qRR balances iRR and tRR in PRR: the shorter tRR that a higher iDS needs to recover qRR consumes similar PRR with ΔvSW as the longer tRR that a lower iDS requires. Halving τF approximates the tRR that a quadratically increasing iDS needs to recover qRR.

Example 12: Approximate PIV and σIV for MEG in the ideal boost in CCM from Examples 7, 9, and 11 when MEG closes and iEG maxes to iL. Solution: iLðLOÞ ¼ 470 mA, ΔvSWO ¼ 4:8 V, tIðCÞ ¼ 240 ps,

PIV

and tSW ¼ 1 μs from Examples 7, 9, and 11    tIðCÞ τF 240p 5n þ ¼ 12 mW  iLðLOÞ ΔvSWO þ  ð470mÞð4:8Þ 3tSW tSW 3ð1μÞ 1μ PIV 12m  ¼ ¼ 1:2% σIV ¼
iOðAVGÞ =dO dIN vIN ð250m=48%Þð1Þð2Þ

Note: This σIV is only 0.1% higher than the more accurate σIV from Example 11, which is 0.9% higher than the σIV that excludes reverse recovery from Example 9.

C. Implicit MOS Diodes The diffusion charge qDIF that sets reverse-recovery charge is greatest when body diodes conduct iL, which happens when switches are off. MDG and MDO in Fig. 4.26, for example, open when the controller grounds MDG’s gate and connects MDO’s gate Fig. 4.26 Switched inductor during dead time

4.5 iDS–vDS Overlap Loss

209

to vO. This way, dead-time iL discharges vSWI’s CSWI and charges vSWO’s CSWO until MDG’s and MDO’s body diodes conduct iL. When these diodes conduct, vSWI falls a diode voltage below ground and vSWO rises a diode voltage over vO. Interestingly, MDG’s vGS and MDO’s vSG are positive under these conditions. Although sub-threshold current is not always negligible, MDG and MDO remain largely off when their threshold voltages match or surpass a PN diode voltage. MDG and MDO start conducting some of iL when threshold voltages are lower. So the currents that feed qRR’s drop as VT0’s fall below 600–700 mV. This diminishes the effect of qRR on PIV. The effect is minimal when the vGS and vSG that MDG and MDO need to sustain iL are less than 600–700 mV, which can happen when VT0’s are 300–500 mV. MDG and MDO, however, also need qRR to charge their CGS’s across the vGS’s needed to sustain iL. Even when vGS is below VT0, CGS still draws charge. So in effect, qRR is the combined charge CGS and the diode need to conduct iL together. qDIF in qRR falls with lower VT0’s. Very low VT0’s are uncommon because large low-VT0 switches leak too much current with zero vGS. Although technologies and applications vary, 400–600-mV VT0’s are more common. With these VT0’s, the effect of qRR on PIV is still present, but not as severe. Letting body diodes conduct poses another challenge: substrate noise. This is because MOSFETs on the substrate conduct body-diode current through the substrate. And MOSFETs in wells over the substrate activate vertical bipolar-junction transistors (BJTs) that inject current into the substrate. Switching events therefore produce, inject, and propagate noise energy across the substrate, coupling and affecting other circuits along the way. So the implicit diode action of low-VT0 MOSFETs keeps body diodes from generating substrate current iSUB. They also reduce the dead-time voltages that produce PDT. And as already mentioned, they reduce the qRR that burns PIV. Explore with SPICE: See Appendix A for notes on SPICE simulations. * I-V Overlap Loss when MEG Closes & VTP0 is -400 mV vdd vdd 0 dc¼4 rp vdd vg 100 lx 0 vswo 10u meg vswo vg 0 0 nmos1 w¼50m l¼250n ddo vswo vo diode2 mdo vo vo vswo vo pmos1 w¼150m l¼250n vo vo 0 dc¼4 .ic i(lx)¼470m v(vg)¼0 .lib lib.txt .tran 5n .end (continued)

210

4

Power Losses

Tip: Plot id(Meg), v(vg), v(vswo), and id(Meg)*v(vswo), extract the average of the product term across 5 ns, and multiply by 0.5% (5 ns of the 1-μs period) to determine MEG’s PIV. id(Meg) often includes CGD’s current, so the extraction is not perfect. In this case, iD is considerably greater than iGD, so the approximation is fair. D. Schottky Diodes Connecting Schottky diodes in parallel with MDG’s and MDO’s body diodes like Fig. 4.27 offers similar benefits. This is because they drop lower voltages than typical PN diodes without a junction that traps in-transit charge. So they steer current away from body diodes without trapping qDIF or generating iSUB. The only component that holds charge in Schottkys is depletion capacitance. Good Schottky diodes, however, are not always available on-chip. And off-chip diodes require board space and money. Still, the advantages of lower noise and lower power can outweigh the added volume and cost of additional components or manufacturing steps.

4.5.4

Soft Switching

PIV hinges on the currents and voltages that power switches carry and collapse. Soft switching refers to transitions that carry low currents or collapse low voltages. Although zero-current switching (ZCS) and zero-voltage switching (ZVS) are extreme cases, engineers often use ZVS and ZCS to refer to “soft” events. Either way, the net result is low PIV. A. Zero-Voltage Switching Collapsing vIN or vO is not ZVS. Energize switches fall into this category. MEI, for example, collapses vIN plus vDG because MEI connects vIN to vSWI and DDG conducts iL before and after MEI closes. MEG similarly collapses vO and vDO because DDO conducts iL into vO before and after MEG closes. These are hard-switching examples.

Fig. 4.27 Switched inductor with Schottky diodes

4.5 iDS–vDS Overlap Loss

211

Fig. 4.28 Soft zero-voltage switching events

Fig. 4.29 Zero-current switching events

Collapsing diode voltages like drain switches do is “soft.” MDG, for one, collapses DDG’s vDG when MDG grounds vSWI a tDT before and after tE in Fig. 4.28. And MDO collapses DDO’s vDO when MDO connects vSWO to vO at those same times. These transitions soften further into ZVS when vDG and vDO are smaller fractions of vIN and vO. B. Zero-Current Switching ZCS happens in DCM when iL reaches zero. Drain switches, for example, open with ZCS because iL reaches zero when tD ends in Fig. 4.29. Energize switches similarly close with ZCS because iL is zero when tE starts. So PIV when tD ends and tE starts is usually negligibly low.

4.5.5

CMOS Expressions

NFETs are active high, which means they close when their gate voltages are high. Discussions, graphs, and expressions to this point reflect this context. In this light, vGS, vDS, and VT0 are positive values. PFETs behave like NFETs, except they are active low, which is to say they close with low gate voltages. So pull-down resistors close them and pull-up resistors open them. CMOS stands for complementary MOS transistors for this reason: because NFETs and PFETs are complementary and available for use. Not coincidentally, NFET expressions also apply to PFETs, except vGS, vDS, and VT0 for PFETs are negative, which is not always intuitive. Replacing vGS, vDS, and VT0 with vSG, vSD, and |VT0| or |VTP0| is more insightful because PFETs collapse vSD when vSG overcomes |VT0|. But when generalizing, expressions with vGS, vDS, and VT0 apply to both: NFETs and PFETs.

212

4

Power Losses

Example 13: Determine PIV and σIV for MEI in the ideal buck in CCM when MEI closes, vDD for MEI’s gate driver is vIN, vIN is 4 V, vO is 2 V, vDG is 800 mV, iO(AVG) is 250 mA, LX is 10 μH, tSW is 1 μs, tDT is 50 ns, WEI is 50 mm, LEI is 250 nm, LOL is 30 nm, VTP0 is 400 mV, KP' is 40 μA/V2, COX'' is 6.9 fF/μm2, and RN is 50 Ω. Solution: Buck ∴ dO ¼ 1   

 vD v v 2tDT 2 800m 2ð50nÞ ¼ 52% ¼ dE ¼ ¼ O þ DG ¼ þ 1μ 4 4 vE þ vD vIN vIN tSW

dIN

 ΔiL ¼

vE LX



∴ dD ¼ 1  dE ¼ 1  52% ¼ 48%     vIN  vO 42 ð52%Þð1μÞ ¼ 100 mA tE ¼ dE tSW  10μ LX

iLðLOÞ ¼

iOðAVGÞ ΔiL 250m 100m  ¼  ¼ 200 mA 2 dO 2 100%

WEI , LEI , LOL , and COX '' match MEG ’s from Example 9 ∴

WCH ¼ 50 mm, LCH ¼ 190 nm, COL ¼ 10 pF, CCH ¼ 66 pF from Example 9

vSDðSATÞ

MEI closes when iL ¼ iLðLOÞ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2iLðLOÞ 2ð200mÞ  ¼ ¼ 200 mV KP 0 ðWCH =LCH Þ ð40μÞð50m=190nÞ

vTHðCÞ  jVTP0 j þvSDðSATÞ ¼ 400m þ 200m ¼ 600 mV

 h

 i h i 2 2 τRCðCÞ ¼ RN 2COL þ CCH ¼ ð50Þ 2ð10pÞ þ ð66pÞ ¼ 3:2 ns 3 3  

 v  jVTP0 j 4  400m ¼ 180 ps tIðCÞ  τRCðCÞ ln DD ¼ ð3:2nÞ ln 4  600m vDD  vTHðCÞ vSWI ¼ vDG ¼ 800 mV before MEI closes vSWI  vIN ¼ 4 V after MEI closes ∴

vSD swings ΔvSWI ¼ vIN  ðvDG Þ ¼ vIN þ vDG ¼ 4 þ 800m ¼ 4:8 V

4.5 iDS–vDS Overlap Loss

213



PIV

h

 i RN C tVðCÞ  COL ΔvSWI þ CH vTHðCÞ vDD  vTHðCÞ 4     50 66p ¼ ð10pÞð4:8Þ þ ð600mÞ ¼ 850 ps 4  600m 4    tIðCÞ tVðCÞ 180p 850p þ ¼ 470 μW  iLðLOÞ ΔvSWI þ ¼ ð200mÞð4:8Þ 3tSW 2tSW ð3Þ1μ ð2Þ1μ PIV 470μ  ¼ ¼ 0:1% σIV ¼
iOðAVGÞ =dO dIN vIN ð250m=1Þð52%Þð4Þ

Note: This PIV excludes the power consumed when MEI opens and other switches open and close.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * I-V Overlap Loss when MEI Closes without Reverse Recovery vin vin 0 dc¼4 rn vg 0 50 mei vswi vg vin vin pmos1 w¼50m l¼250n ddg 0 vswi fdiode1 lx vswi vo 10u vo vo 0 dc¼2 .ic i(lx)¼200m v(vg)¼4 .lib lib.txt .tran 5n .end Tip: Plot id(Mei), v(vg), v(vswi), and id(Mei)*(v(vin)-v(vswi)), extract the average of the product term across 5 ns, and multiply by 0.5% (5 ns of the 1-μs period). id(Mei) often includes CGD’s current, so the extraction is not perfect. In this case, iD is considerably greater than iGD, so the approximation is fair.

214

4

4.6

Gate-Driver Loss

4.6.1

Gate Driver

Power Losses

Typical gate drivers use pull-up PFETs to charge gates and pull-down NFETs to discharge gates. Since PFETs are active low and NFETs are active high, a high input vI in Fig. 4.30 shuts MP and activates MN, which grounds the output vO. A low vI does the opposite: shuts MN and activates MP, which pulls vO to the power supply vDD. As vI climbs from zero, MN starts to conduct when vI surpasses VTN0. vO transitions low when MN pulls as much current as MP can supply. The shoot-through current iST that MN and MP conduct maxes at this point. The trip point VTP of the driver is the vI that balances MN’s and MP’s strengths this way. So iST maxes when vI reaches VTP and vO halves vDD:   

 i h WN KN ' v ðVTP  VTN0 Þ2 1 þ DD λN DS 2 LN 2 2   

 i h ' WP KP vDD 2 DD VTP ¼ iP jvvSG ¼V V ð Þ λP , ¼  V  V 1 þ j j vDD DD TP TP0 SD ¼ 2 2 LP 2

TP ¼ iSTðMAXÞ ¼ iN jvvGS ¼V v ¼ DD

ð4:59Þ where vI at VTP and vO at half vDD invert and saturate MN and MP. A few points are worth noting. VTP is half vDD when VT0’s and channel-length modulation parameters λ’s match and MP’s W/L is greater than MN’s by the same amount that MN’s transconductance parameter K' is greater than MP’s. vO can rail to zero and vDD because, one transistor is on when the other one is off and vice versa. Static power when vI is within a VT0 of the supplies is nearly zero because iST is close to zero. This is why this circuit is so attractive as a digital inverter, because power is zero when vI is high or low. The gate capacitances CG that load the driver need MP’s iP to charge and MN’s iN to discharge. This means that iN wastes power when iP charges and iP wastes power when iN discharges. But if MN’s vDS is low when CG charges and MP’s vSD is low when CG discharges, their triode currents waste less power. This happens when vO transitions more slowly than vI, which results when MP and MN charge and discharge CG slowly.

Fig. 4.30 Inverting gate driver

4.6 Gate-Driver Loss

215

Across the tI and tV that switches carry iL, the driver’s vO is VT0 to vTH above ground or below vDD. Since MN’s vGS is vDD and vDS(SAT) is vDD – VTN0, MN’s vDS is lower than vDS(SAT) across tI and tV. MP’s vSD is similarly lower than vSD(SAT)’s vDD – |VTP0|. So MN and MP are in triode across tI and tV, when vDS is largely vTH or vDD – vTH, which means their triode resistances set the RN and RP that open and close power transistors: RN=P ¼

vDS 1 ¼ iTRI ðWCH =LCH ÞK' ðvGS  VT0  0:5vDS Þ   LCH 1 ¼ : WCH K' ðvDD  VT0  0:5vDS Þ

ð4:60Þ

Example 14: Determine the W’s for the gate driver that closes and opens MEG in the ideal boost from Examples 7, 9, and 10 when vDD is vO, L’s are 250 nm, LOL is 30 nm, VTN0 is 400 mV, VTP0 is 400 mV, KN' is 200 μA/V2, and KP' is 40 μA/V2. Solution: vDD ¼ vO ¼ 4 V, RP ¼ 100 Ω, vTHðCÞ ¼ 530 mV, RN ¼ 20 Ω, and vTHðOÞ ¼ 550 mV from Examples 9 and 10 LCH ¼ L  2LOL ¼ 250n  2ð30nÞ ¼ 190 nm MP ’s vSD ¼ vDD  vTHðCÞ LCH
 RP KP ' vDD  jVTP0 j  0:5 vDD  vTHðCÞ 190n ¼ ¼ 26 μm ð100Þð40μÞ½4  400m  0:5ð4  530mÞ

WP ¼

MN ’s vDS ¼ vTHðOÞ LCH
 RN KN ' vDD  VTN0  0:5vTHðOÞ 190n ¼ ¼ 14 μm ð20Þð200μÞ½4  400m  0:5ð550mÞ

WN ¼

216

4

Power Losses

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Boost with Dead Time, MEG, & MEG’s Driver in CCM vdeb deb 0 dc¼4 pulse 4 0 0 1n 1n 515n 1u vdo do 0 dc¼1 pulse 0 1 570n 1n 1n 385n 1u vdd vdd 0 dc¼4 mp vg deb vdd vdd pmos1 w¼26u l¼250n mn vg deb 0 0 nmos1 w¼14u l¼250n vin vin 0 dc¼2 lx vin vswo 10u meg vswo vg 0 0 nmos1 w¼50m l¼250n sdo vswo vo do 0 sw1v ddo vswo vo fdiode1 vo vo 0 dc¼4 .ic i(lx)¼470m .lib lib.txt .tran 1u .end Tip: Plot id(Meg), v(vg), and v(vswo) and view across 1 μs, first 20 ns, and between 520 and 540 ns.

4.6.2

Closing Switch

When closing MSW in Fig. 4.31, MP supplies the gate current iG that CGB, CGS, and CGD need and the iST that MN leaks. iST is low and short-lived (by design) because MSW’s low vGS suppresses MN’s vDS as vI’s fall collapses MN’s vGS. iG is much greater because MP’s vSG and vSD are high across the time MN leaks iST. So the driver current iD that vDD supplies is mostly the charge qG that CGB, CGS, and CGD need to close MSW.

Fig. 4.31 Gate driver closing switch

4.6 Gate-Driver Loss

217

For vI to fall in the first place, the pre-driver must sink the charge qGI that MN and MP’s gate capacitances CGI store when vI is at vDD. This means that the pre-driver drains and burns CGI’s energy. The drive power PD that vDD supplies is therefore the power MSW needs to close: PDðCÞ ¼ PG þ PSTðCÞ  PG ,

ð4:61Þ

where gate-charge power PG is the power vDD supplies with qG:  PG ¼ vDD iGðAVGÞ ¼ vDD

 qG , tSW

ð4:62Þ

and PST(C) is the power MN leaks with the iLK that vDD supplies across tST: 0 PST ¼ vDD iLKðAVGÞ

1 ¼ vDD @ tSW

ZtLK

1 iLK dtA:

ð4:63Þ

0

Components in CGB and CGS change as vGS traverses vDD. The reason for this is vGS’s rise inverts MSW into saturation (because vDS is high), and afterwards, vDS’s fall collapses MSW into triode. So CGB’s CCH charges to VT0, CGS’s COL charges to VT0 (in sub-threshold), CGS’s COL and two-thirds CCH charge from VT0 to vTH(C) (in saturation), and CGS’s COL and half CCH charge from vTH(C) to vDD in triode. The charge qGBS that CGB and CGS draw is


 2 C v  VT0 qGBS  CCH VT0 þ COL vDD þ 3 CH THðCÞ


 1 þ C v  vTHðCÞ : 2 CH DD

ð4:64Þ

iG not only raises CGD’s vGS across vDD but also collapses vDS across vSW, which means CGD charges across vDD and vSW. CGD’s COL charges with vGS to vDD and with vDS across vSW. Since CGD begins to receive half CCH when vDS falls below vGS’s vTH(C), half CCH’s average 0.25CCH charges across vTH(C). After vDS falls, CGD’s half of CCH charges with vGS from vTH(C) to vDD (in triode): qGD  COL ðvDD þ ΔvSW Þ þ




 1 1 CCH vTHðCÞ þ CCH vDD  vTHðCÞ : 4 2

ð4:65Þ

iG delivers both components: qGBS and qGD. Since vTH is the vGS needed to sustain iL, which is vDS(SAT) over VT0, qG reduces to

218

4

Power Losses

qG ¼ qGBS þ qGD

vDSðSATÞ  V ¼ COL ð2vDD þ ΔvSW Þ þ CCH vDD þ T0  3 12

 VT0  COL ð2vDD þ ΔvSW Þ þ CCH vDD þ 3  ð2COL þ CCH ÞvDD þ COL ΔvSW :

ð4:66Þ

Since vDS(SAT) is usually lower than VT0, a 12th is negligibly lower. Since MSW is mostly in saturated inversion when vDS collapses, COL in CGD is, for the most part, the only component that charges across ΔvSW. Whereas all capacitances connected to vG: COL and CCH in CGS and CGB and COL in CGD, charge across vDD when vG transitions. So reducing qG to the charge these capacitances and swings require is not a bad approximation, especially when vDD is considerably greater than a fourth of VT0.

4.6.3

Opening Switch

When opening MSW in Fig. 4.32, MN sinks the iG that drains CGB, CGS, and CGD and the iST that MP leaks. iST is low and short-lived (by design) because MSW’s high vGS suppresses MP’s vSD as vI’s climb collapses MP’s vSG. iG is much greater because MN’s vGS and vDS are high across the time MP leaks iST. So the PST that vDD supplies with iST across tST is low. For vI to rise in the first place, the pre-driver must supply the qGI needed to charge MN and MP’s gate capacitances CGN and CGP to vDD. Since MSW’s vGS (which sets MN’s vDS) is close to vDD across this transition, vI’s climb inverts MN into saturation. CCHN in CGB therefore charges across VTN0, COLN in CGSN and CGDN across vDD, and (2/3)CCHN in CGSN across vDD – VTN0. Since MN’s vGS matches vDS at vDD after vI rises, vDS’s fall charges COLN and half CCHN’s average 0.25CCHN in CGDN across vDD. So in all, CGN requires

Fig. 4.32 Gate driver opening switch

4.6 Gate-Driver Loss

219

 2 C v C qGN  CCHN VTN0 þ COLN ð3vDD Þ þ ðv  VTN0 Þ þ CHN DD 3 CHN DD 4 ð4:67Þ

 V  COLN ð3vDD Þ þ CCHN vDD þ TN0 : 3 MP starts in triode and ends in cut off when vI climbs because MSW’s vGS, which is high across vI’s transition, suppresses MP’s vSD. COLP’s in CGSP and CGDP therefore charge across vDD, half CCHP’s in CGSP and CGDP across vDD – |VTP0|, and CCH in CGB across |VTP0|. After vI rises, as MSW’s vGS falls and MP’s vSD climbs in cut off, COLP in CGDP charges across another vDD. So CGP requires

 CCHP CCHP ðvDD  jVTP0 jÞ þ CCHP jVTP0 j þ 2 2 ¼ ð3COLP þ CCHP ÞvDD :

qGP  COLP ð3vDD Þ þ

ð4:68Þ

qGN and qGP are the qGI that vDD supplies CGI. And PGI is the driver gate-charge power that vDD supplies with qGI:  PGI ¼ vDD iGIðAVGÞ ¼ vDD

qGI tSW



  qGN þ qGP ¼ vDD : tSW

ð4:69Þ

Together, CGI’s qGI and MP’s iST draw PD(O) from vDD when MSW opens: PDðOÞ ¼ PGI þ PSTðOÞ :

4.6.4

ð4:70Þ

Driver Power

MSW’s CG receives charge qG or CGvDD to charge to vDD. With this qG, vDD supplies qGvDD or CGvDD2 and CG stores 0.5CGvDD2. This means that MP burns half the energy vDD supplies. MN later consumes the other half when MN drains CG. So vDD ultimately loses the PG that CG draws. vDD similarly loses the PGI that CGI requires. vDD also leaks PST when closing and opening MSW. But PST is so much lower than PG (by design) that PD reduces to the qG and qGI that CG and CGI need: PD ¼ PDðCÞ þ PDðOÞ  PG þ PGI     q þ qGI q þ qGN þ qGP  vDD G ¼ vDD G : tSW tSW

ð4:71Þ

220

4

Power Losses

Example 15: Determine PD and σD for MEG’s driver in the ideal boost from Examples 7, 9, and 13. Solution: dIN ¼ 1, dO ¼ 48%, vDD ¼ vO ¼ 4 V, VTN0 ¼ 400 mV, ΔvSWO ¼ vO þ vDO ¼ 4:8 V, COX '' ¼ 6:9 fF=μm2 , LOL ¼ 30 nm, COL ¼ 10 pF, and CCH ¼ 66 pF from Examples 7 and 9 LCH ¼ 190 nm, WN ¼ 14 μm, and WP ¼ 26 μm from Example 13 qG  COL ΔvSWO þ ð2COL þ CCH ÞvDD ¼ ð10pÞð4:8Þ þ ½2ð10pÞ þ 66pð4Þ ¼ 390 pC COLN ¼ COX '' WN LOL ¼ ð6:9mÞð14μÞð30nÞ ¼ 2:9 fF

qGN

CCHN ¼ COX '' WN LCH ¼ ð6:9mÞð14μÞð190nÞ ¼ 18 fF



 V 400m  COLN ð3vDD Þ þ CCHN vDD þ TN0 ¼ ð2:9f Þð3Þð4Þ þ ð18f Þ 4 þ 3 3 ¼ 110 fC COLP ¼ COX '' WP LOL ¼ ð6:9mÞð26μÞð30nÞ ¼ 5:4 fF CCHP ¼ COX '' WP LCH ¼ ð6:9mÞð26μÞð190nÞ ¼ 34 fF qGP  ð3COLP þ CCHP ÞvDD ¼ ½3ð5:4f Þ þ 24f ð4Þ ¼ 160 fC     qG þ qGN þ qGP 390p þ 110f þ 160f PD  vDD ¼ 1:6 mW ¼4 1μ tSW σD ¼


PD 1:6m  ¼ 0:2% ¼ ð 250m=48% Þ ð 1Þ ð 2Þ iOðAVGÞ =dO dIN vIN

Note: qG is usually much greater than qGI. This PD, which is 0.2% of PIN, excludes the power MDO’s driver consumes.

4.7 Leaks

221

Explore with SPICE: Use the SPICE code from Example 13. Tip: Plot id(Meg), v(vg), v(vswo), and i(Vdd)*v(vdd) and extract the average of the product term.

4.7

Leaks

MOS transistors also incorporate source– and drain–body junction capacitances CSB and CDB. The terminals that do not connect to the switching nodes connect to ground, vIN, or vO, which are nearly fixed. So CSB and CDB add input and output switch-node capacitances CSWI and CSWO that charge and discharge with vSWI and vSWO in Fig. 4.33. Electrostatic-discharge protection (ESD), pads, pins, and board connections also add capacitance to CSWI and CSWO. Charging CSWI and CSWO draws vIN and LX energy that vO does not fully recover. Power switches burn this difference. These same switches also leak current when they are off, especially when they are large and hot. Although these losses are usually low, they become increasingly larger fractions of PIN when PO is lower, especially in low-power applications when their systems idle.

4.7.1

Input Switch-Node Capacitance

vSWI rises and falls between –vDG and vIN and between –vDG and ground. When MEI closes to start tE, vIN supplies the charge needed to raise vSWI from –vDG to vIN: vINqSWI or vINCSWI(vIN + vDG). During this transition, CSWI loses the energy it held with –vDG and receives the energy it stores with vIN: 0.5CSWIvDG2 + 0.5CSWIvIN2. When MEI opens to end tE, as iL collapses vSWI to ground, LX helps vO recover the charge CSWI held with vIN. But as vSWI falls below ground to –vDG, LX loses the energy CSWI needs to charge to –vDG. This is LX energy vO loses. So across this transaction, vO recovers 0.5CSWIvIN2 and LX loses 0.5CSWIvDG2. After the first tDT in tD, MDG burns the energy CSWI holds with –vDG. When MDG opens to start the second tDT, LX loses the energy CSWI needs to charge to –vDG: 0.5CSWIvDG2. So across every cycle, vIN loses vINCSWI(vIN + vDG), vO recovers Fig. 4.33 Switched inductor with parasitic diodes and capacitances

222

4

Power Losses

0.5CSWIvIN2, and LX loses 0.5CSWIvDG2 two times. This means that the average input switched-node power PSWI leaked across tSW is PSWI ¼ ESWI f SW  
 CSWI ¼ vIN ðvIN þ vDG Þ  0:5vIN 2 þ 2 0:5vDG 2 tSW    CSWI
¼ 0:5vIN 2 þ vIN vDG þ vDG 2 : tSW

4.7.2

ð4:72Þ

Output Switch-Node Capacitance

vSWO rises and falls between ground and vDO over vO and between vDO over vO and vO. When MEG opens to start tD, LX supplies the energy CSWO needs to charge to vDO over vO: 0.5CSWO(vO + vDO)2. A tDT after that, when MDO closes, vO receives the charge CSWO outputs when vSWO falls from vDO over vO to vO. So of the energy LX loses after raising vSWO to vDO over vO, vO recovers vOqSWO or vOCSWOvDO. Later when MDO opens, LX supplies the energy CSWO needs to raise vSWO from vO to vDO over vO. Here, LX loses the energy CSWO holds with vDO over vO that excludes the energy CSWO stores with vO. LX therefore loses the difference: 0.5CSWO(vO + vDO)2 minus 0.5CSWOvO2. MEG burns the energy CSWO holds with vDO over vO when MEG collapses vSWO to ground. So across every cycle, LX loses 0.5CSWO(vO + vDO)2, vO recovers vOCSWOvDO, and LX loses 0.5CSWO(vO + vDO)2 minus 0.5CSWOvO2. This means that the average output switched-node power PSWO leaked across tSW is PSWO ¼ ESWO f SW  n h io CSWO ¼ 0:5ðvO þ vDO Þ2  vO vDO þ 0:5ðvO þ vDO Þ2  0:5vO 2 tSW    CSWI
¼ 0:5vO 2 þ vDO 2 þ vO vDO : tSW ð4:73Þ

Example 16: Determine PSWI and PSWO in a synchronous buck–boost when vIN is 2 V, vO is 4 V, tSW is 1 μs, CSWI and CSWO are 5 pF each, and DDG and DDO drop 400 mV.

4.7 Leaks

223

Solution: 

  CSWI
0:5vIN 2 þ vIN vDG þ vDG 2 tSW  h i 5p ¼ 0:5ð2Þ2 þ ð2Þð400mÞ þ 400m2 ¼ 15 μW 1μ    CSWO
PSWO ¼ 0:5vO 2 þ vDO 2 þ vO vDO tSW  

5p
2  ¼ 0:5 4 þ 400m2 þ ð4Þð400mÞ ¼ 49 μW 1μ PSWI ¼

Note: CSWO leaks more than CSWI because LX helps vO recover more when vSWI collapses vIN to ground than vO recovers when vSWO drops vDO.

4.7.3

Cut-off Power

MOS current is zero when vGS and vDS are zero. Raising vDS when vGS is zero establishes an electric field that induces some iDS. Body diodes also conduct zero current when their voltages are zero and close to reverse saturation current IS when they reverse. These off currents iOFF climb with channel width WCH and junction temperature TJ. So the off resistance ROFF that they exhibit falls with increasing WCH and TJ. Power-supply switches and body diodes usually leak noticeable iOFF because they are large. Plus, the power they burn when they conduct heats them to an extent that keeps them hot when they open. A 30-mm-wide, 180-nm-long MOSFET, for example, can leak 80 nA with 1.8 V at 25 C and 800 nA at 125 C. This is 0.38–3.8 TΩ for each length-to-width (L/W) square. In a switched inductor, energize switches are off across tD. SEI drops vIN and SEG drops vO across the tD that excludes dead times. When dead-time diodes conduct, SEI drops vIN and vDG and SEG drops vO and vDO. So the average cut-off power they consume across tSW is

224

4



Power Losses

    ðvIN þ vDG Þ2 ðvO þ vDO Þ2 2tDT tD  2tDT þ þ REIðOFFÞ REGðOFFÞ tSW REIðOFFÞ REGðOFFÞ tSW    2 2 vIN vO tD  þ : REIðOFFÞ REGðOFFÞ tSW

POFFðEÞ ¼

vIN 2

þ

vO 2



ð4:74Þ But since tDT’s are small fractions of tSW and diode voltages are usually lower than vIN and vO, the effects of vDG and vDO are minimal. Drain switches are off across tE and across dead times within tD. SDG drops vIN and SDO drops vO across tE and SDG drops vDG and SDO drops vDO across tDT’s. So the average cut-off power they consume across tSW is  POFFðDÞ ¼

vIN 2

þ



vO 2

tE



 þ

RDGðOFFÞ RDOðOFFÞ tSW    2 2 vIN vO tE  þ : RDGðOFFÞ RDOðOFFÞ tSW

vDG 2 RDGðOFFÞ

þ



vDO 2 RDOðOFFÞ

2tDT tSW



ð4:75Þ The effects of vDG and vDO are minimal because DDG and DDO conduct short tDT fractions of tSW and drop lower voltages than vIN and vO. Excluding dead times, SEI and SDG alternate conduction to vSWI and SEG and SDO alternate conduction to vSWO. So one switch is always off at vSWI and one at vSWO. The one at vSWI drops vIN and the one at vSWO drops vO. Since off resistances for similarly large switches are comparable, cut-off power POFF is largely consistent and similar across time:  POFF  

vIN 2 REIðOFFÞ 2

þ

vO 2 REGðOFFÞ



tD

tSW



 þ

vIN 2

RDGðOFFÞ

þ

vO 2 RDOðOFFÞ

2

vIN vO þ : RIðOFFÞ ROðOFFÞ



tE



tSW ð4:76Þ

Example 17: Determine POFF in a buck–boost when vIN is 2 V, vO is 4 V, W’s are 50 mm, L’s are 250 nm, LOL is 30 nm, TJ is 125 C, and ROFF/SQ at this TJ is 380 GΩ per L/W square. Solution: LCH ¼ L  2LOL ¼ 250n  2ð30nÞ ¼ 190 nm

4.8 Design

225

 ROFF ¼ ROFF=SQ POFF 

LCH WCH

 ¼ ð380GÞ



 190n ¼ 1:4 MΩ 50m

vIN 2 v 2 22 42 þ O ¼ þ ¼ 14 μW ROFF ROFF 1:4M 1:4M

4.8

Design

4.8.1

Optimal Power Setting

Power losses normally consume the lowest fraction of input power at a particular load level. With sufficient flexibility, engineers can define and set this optimal output power PO'. In practice, however, applications and technologies impose operating conditions and parametric limits that constrain PO'. But even then, design choices can still influence PO'. Setting PO' to PO(MAX) saves the most power, but not the most energy, especially when PO(MAX) is an improbable extreme. The system saves the most energy when PO' is at the most probable setting. If this setting is unknown, halfway between PO(MIN) and PO(MAX) is often a good alternative. Although more involved and less practical, PO' can also be the PO that produces the highest peak efficiency or the highest average efficiency.

4.8.2

Power Switch

MOSFETs require power in four ways: Ohmic power when they conduct iL, gatedrive power when they close, iDS–vDS overlap power when they transition, and off power when they are open. Of these, POFF is usually a negligible part of PO'. Although PIV may not be as insignificant, gate drivers can reduce the impact of PIV on PO'. The only design variables that can suppress PR and PG are MOSFET dimensions. Longer channels raise channel resistance RCH and gate capacitance and, as a result, gate charge. So the RCH and qG that set PR and PG increase with channel length LCH. This means that the MOS power PMOS that PR and PG require is minimal when L is the minimum allowable oxide length LMIN that can sustain vSW’s swing without breakdown effects: PMOS
PR þ PG :

ð4:77Þ

Wider channels decrease RCH and increase CG. So the RCH that sets PR in Fig. 4.34 falls with increasing WCH’s as the qG that sets PG climbs:

226

4

Power Losses

Fig. 4.34 Ohmic and gatecharge MOS power

PR ¼ iRðRMSÞ 2 RCH ¼

kR WCH

ð4:78Þ

PG ¼ EG f SW ¼ vDD qG f SW ¼ kG WCH ,

ð4:79Þ

where kR and kG are WCH-independent coefficients. These opposing trends tend to desensitize PMOS from WCH. Still, PMOS falls with PR when WCH is narrow and rises with PG when WCH is wide. PMOS is minimal when additional charge losses in PG cancel PR savings. This happens when PMOS’s slope ∂PMOS/∂WCH is zero:    ∂PMOS  ∂PR  ∂PG  k ¼ þ ¼  R 2 þ kG ¼ 0, ∂WCH WCH ' ∂WCH WCH ' ∂WCH WCH ' WCH '

ð4:80Þ

which results at the optimal channel width WCH': rffiffiffiffiffiffi kR WCH ' ¼ , kG

ð4:81Þ

when PR and PG match: PR jW ' ¼ PG jW ' ¼ CH CH

pffiffiffiffiffiffiffiffiffiffi kR kG ,

ð4:82Þ

and PMOS(MIN) is twice the PR or PG that WCH' sets: PMOSðMINÞ ¼ PMOS jW ' ¼ PR jW ' þ PG jW ' ¼ 2PR jW ' ¼ 2 CH CH CH CH

pffiffiffiffiffiffiffiffiffiffi kR kG :

ð4:83Þ

In practice, on-chip, bond-wire, and board contacts and traces add resistance to switches. So Ohmic power is greater than the PR that RCH burns. Still, switches require the least power with WCH'. kR and kG are functions of parameters and variables that applications and manufacturing technologies frequently define. vIN and vO, for example, set duty cycle. Accuracy and noise sensitivity often specify or constrain current ripple and switching frequency. And device parameters dictate the shortest dead time that keeps adjacent switches from cross-conducting. In other words, kR and kG are often pre-set.

4.8 Design

227

Example 18: Determine MDG’s optimal WDG, LDG, PMOS, and σMOS in a buck– boost in CCM when vDD for MDG’s gate driver is vIN, vIN is 2 V, vO is 4 V, DDG and DDO drop 400 mV, iO(AVG) is 250 mA, LX is 10 μH, tSW is 1 μs, tDT is 50 ns, LMIN is 250 nm, LOL is 30 nm, VTN0 is 400 mV, KN' is 200 μA/V2, and COX'' is 6.9 fF/μm2. Solution:

dIN

   vO vDO þ vDG 2tDT ¼ dE  þ vIN þ vO vIN þ vO tSW

2ð50nÞ 4 400m þ 400m ¼ ¼ 68% þ 1μ 2þ4 2þ4 ∴ dO ¼ dD ¼ 1  dE  1  68% ¼ 32%      vE vIN 2 ð68%Þð1μÞ ¼ 140 mA tE ¼ dE tSW  10μ LX LX

 ΔiL ¼

LDG
LMIN ¼ 250 nm ∴ LCH ¼ LDG  2LOL ¼ 250n  2ð30nÞ ¼ 190 nm     LCH 1 190n 1 590μ RDG  ¼ ¼ WCH ð200μÞð2  400mÞ WCH WCH KN ' ðvDD  VTN0 Þ "  #    2 2 iO 0:5ΔiL 2t pffiffiffi PR ¼ þ RDG dD  DT dO tSW 3 ( 2   2 )  0:5ð140mÞ 2ð50nÞ 250m 590μ 79μ pffiffiffi  ¼ þ 32%  1μ W W 32% CH CH 3 COL ¼ COX '' WCH LOL ¼ ð6:9mÞWCH ð30nÞ ¼ ð210pÞWCH CCH ¼ COX '' WCH LCH ¼ ð6:9mÞWCH ð190nÞ ¼ ð1:3nÞWCH vSWI is vDG before MEI closes and vIN after MEI closes ∴

ΔvSWI ¼ vIN þ vDG ¼ 2 þ 400m ¼ 2:4 V

qG  COL ΔvSWI þ ð2COL þ CCH ÞvDD ¼ fð210pÞð2Þ þ ½2ð210pÞ þ 1:3nð2ÞgWCH ¼ ð3:9nÞWCH

228

4

Power Losses

 ð3:9nÞWCH ¼ ð7:8mÞWCH PG ¼ vDD  ð 2Þ 1μ rffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffi kR 79μ ¼ 100 mm WDG
WCH ' ¼ ¼ 7:8m kG 

qG tSW



590μ ¼ 5:9 mΩ WDG pffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2 kR kG ¼ 2 ð79μÞð7:8mÞ ¼ 1:6 mW RDG 

PMOS σMOS ¼


PMOS 1:6m  ¼ ¼ 0:2% iOðAVGÞ =dO dIN vIN ð250m=32%Þð68%Þð2Þ

Note: PMOS, which includes the PR that MDG burns and the PG the driver supplies, is much lower than PR in Example 2 because RCH is much lower. This PMOS excludes the dead-time power MDG consumes across tDT’s, when MDG conducts iL like a 400-mV diode.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Buck-Boost with Dead Time & MDG in CCM vde de 0 dc¼0 pulse 0 1 0 1n 1n 673n 1u vido ido 0 dc¼2 pulse 0 2 730n 1n 1n 227n 1u vdd vdd 0 dc¼2 sh vdd do ido 0 sw2v sl do 0 vdd ido sw2v vin vin 0 dc¼2 sei vin vswi de 0 sw1v mdg 0 do vswi 0 nmos1 w¼100m l¼250n lx vswi vswo 10u seg vswo 0 de 0 sw1v ddo vswo vo idiode vo vo 0 dc¼4 .ic i(lx)¼710m .lib lib.txt .tran 1u .end (continued)

4.8 Design

229

Tip: Plot id(Mdg), v(vswi), and id(Mdg)*v(vswi) and view between 731 and 951 ns, extract the average of the product term, and multiply by 22% (220 ns of the 1-μs period) to determine MDG’s PR. Plot v(do) and i(Vdd)*v(vdd), and extract the average of the product term to determine MDG’s PG.

4.8.3

Gate Driver

Similar transition times balance propagation delays and distribute switching losses across the switching period. This way, dead times and response time are consistent and peak transient power balances across switching events. Pull-up and pull-down resistances in the gate driver (which transistor W/L’s, KN' and KP', vGS and vSG, and VTN0 and VTP0 set) match opposing vDS transition times tV(C) and tV(O) when RP-to-RN’s ratio is #  " vDD  VTN0  0:5vTHðOÞ KN '
 KP ' vDD  jVTP0 j  0:5 vDD  vTHðCÞ    vDD  vTHðCÞ COL vSW þ 0:25CCH vTHðOÞ
: vTHðOÞ COL vSW þ 0:25CCH vTHðCÞ

RP ¼ RN



WN WP



LP LN

ð4:84Þ

Although not perfectly matched, these resistances produce similar iDS transitions tI(C) and tI(O). And since dead-time diodes set vDS before and after switches close, vDS swings the same ΔvSW when closing and opening. So excluding the reverserecovery power that body diodes induce (i.e., assuming the switches are low-VT0 MOSFETs or low-voltage Schottkys parallel the body diodes), the overlap power that switches consume when closing and opening reduces to         tIðCÞ tVðCÞ tIðOÞ tVðOÞ þ PVðCÞ þ PIðOÞ þ PVðOÞ tSW tSW tSW tSW  
 tI t  iLðLOÞ þ iLðHIÞ ΔvSW þ V 3tSW 2tSW     iOðAVGÞ tI t k ¼2 þ V ΔvSW ¼ IV : dDO 3tSW 2tSW WN

PIV ¼ PIðCÞ

ð4:85Þ

Switches either energize (raise iL(LO) to iL(HI)) or drain LX (reduce iL(HI) to iL(LO)), so they steer iL(LO) in one transition and iL(HI) in the other. Since iL(LO) and iL(HI) average iL(AVG), their sum is twice the iL(AVG) that iO(AVG) and dO set. The only design variable left is the RN that sets RP, tI, and tV. Since WN relates to RN and WP to the RP that RN sets, RN determines the total gate capacitance of the driver. Increasing WN not only reduces the RN that shortens tI and

230

4

Power Losses

Fig. 4.35 Overlap and driver gate-charge power

tV and reduces PIV but also increases the CGI that vDD charges. So PGI in the driver climbs with WN as PIV falls:  PGI ¼ vDD

qGI tSW



  qGN þ qGP ¼ vDD ¼ kGI WN , tSW

ð4:86Þ

where kIV and kGI are WN-independent coefficients for PIV and PGI. Longer channels increase channel resistance and gate capacitance, and as a result, gate charge. So the RP, RN, and qGI that set PIV and PGI climb with LCH. This means that PIV and PGI’s sum is lowest when L is the LMIN that can sustain vDD without breakdown effects. PGI’s rise with WN in Fig. 4.35 opposes PIV’s fall like PG and PR in PMOS. So PIV and PGI’s sum is minimal when additional charge losses cancel PIV savings. This happens when the slope of PIV and PGI’s sum is zero, which results when WN is at the optimal width WN' and PIV and PGI match:   ∂PIV  ∂PGI  k þ ¼  IV 2 þ kGI ¼ 0,   ∂WN WN ' ∂WN WN ' WN ' rffiffiffiffiffiffiffi kIV , kGI pffiffiffiffiffiffiffiffiffiffiffiffiffi PIV jW ' ¼ PGI jW ' ¼ kIV kGI : N N WN ' ¼

ð4:87Þ

ð4:88Þ ð4:89Þ

The WP and WN that raise PGI to the point PGI matches PIV can be so high that iP and iN can reach iL levels. This amplifies the effects of iP and iN on the closing and opening thresholds that vGS reaches when vDS transitions. Although incorporating this shift in vTH is not impossible, the vTH(C) and vTH(O) that set PIV in Section 5 are good first-order approximations. Computer models and simulations can account for the rest, including sub-threshold and weak-inversion effects.

4.8 Design

231

Example 19: Determine the optimal W’s and L’s, PIV, and PGI for the gate driver that switches MEG in the boost from Examples 7, 9, 10, and 13 when LMIN is 250 nm and iO(AVG) is 250 mA. Solution: dE ¼ 52%, dO ¼ dD ¼ 48%, and ΔiL ¼ 100 mA from Example 7 vDD ¼ vO ¼ 4 V, VTN0 ¼ 400 mV, KN ' ¼ 200 μA=V2 , LOL ¼ 30 nm, COX '' ¼ 6:9 fF=μm2 , COL ¼ 10 pF, CCH ¼ 66 pF, ΔvSWO ¼ 4:8 V, and vTHðCÞ ¼ 530 mV from Example 9 vTHðOÞ ¼ 550 mV from Example 10 VTP0 ¼ 400 mV and KP ' ¼ 40 μA=V2 from Example 13 L
LMIN ¼ 250 nm

∴

LCH ¼ L  2LOL ¼ 250n  2ð30nÞ ¼ 190 nm

LCH
 WP KP ' vDD  jVTP0 j  0:5 vDD  vTHðCÞ 190n 2:6m ¼ ¼ WP WP ð40μÞ½4  400m  0:5ð4  530mÞ

RP 

LCH
 ' WN KN vDD  VTN0  0:5vTHðOÞ 190n 290μ ¼ ¼ WN WN ð200μÞ½4  400m  0:5ð550mÞ    vDD  vTHðCÞ COL ΔvSWO þ 0:25CCH vTHðOÞ RP
RN vTHðOÞ COL ΔvSWO þ 0:25CCH vTHðCÞ   4  530m 10pð4:8Þ þ 0:25ð66pÞð550mÞ ¼ ¼ 6:3 550m 10pð4:8Þ þ 0:25ð66pÞð530mÞ    RP 2:6m WN ¼ ¼ 6:3 ∴ WP ¼ 1:4WN ! WP RN 290μ RN 

232

4



Power Losses

h

 i C tV  COL ΔvSWO þ CH vTHðOÞ vTHðOÞ 4     290μ=WN 66p 30f ¼ ð550mÞ ¼ ð10pÞð4:8Þ þ 4 WN 550m 

 h i v 2 THðOÞ CCH ln tIðOÞ  RN 2COL þ 3 VTN0   h

 i  290μ 2 550m 5:9f ¼ ð66pÞ ln ¼ 2ð10pÞ þ WN 3 400m WN     iOðAVGÞ tI t PIV  2 þ V ΔvSWO dDO 3tSW 2tSW      250m 5:9f 30f 1 85n ¼2 ð4:8Þ þ ¼ WN 48% 3ð1μÞ 2ð1μÞ WN RN

qGP ¼ ð3COLP þ CCHP ÞvDD

PGI

¼ COX''WP ð3LOL þ LCH ÞvDD ¼ ð6:9mÞð1:4WN Þ½3ð30nÞ þ 190nð4Þ ¼ ð11nÞWN

 V qGN ¼ COLN ð3vDD Þ þ CCHN vDD þ TN0 3 h

i V ¼ COX''WN LOL ð3vDD Þ þ LCH vDD þ TN0 3 h

i 400m ¼ ð6:9mÞWN ð30nÞð3Þð4Þ þ ð190nÞ 4 þ 3 ¼ ð7:9nÞWN     q þ qGN 11n þ 7:9n ¼ vDD GP WN ¼ ð76mÞWN ¼ ð4Þ 1μ tSW rffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi kIV 85n ¼ 1:1 mm WN
WN ' ¼ ¼ 76m kGI

WP ¼ 1:4WN ¼ 1:4ð1:1mÞ ¼ 1:5 mm

∴

PIV  80 μW

and

PGI  84 μW

Note: WN and WP are much wider than in Example 13 and PIV and PGI are much lower than PIV’s in Examples 9 and 10.

4.8 Design

233

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Ideal Boost with Dead Time, MEG, & MEG’s Optimal Driver in CCM vde de 0 dc¼0 pulse 0 4 0 1n 1n 519n 1u vdo do 0 dc¼1 pulse 0 1 570n 1n 1n 381n 1u vdd1 vdd1 0 dc¼4 sh deb vdd1 vdd2 de sw4v sl deb 0 de 0 sw4v vdd2 vdd2 0 dc¼4 mp vg deb vdd2 vdd2 pmos1 w¼1.5m l¼250n mn vg deb 0 0 nmos1 w¼1.1m l¼250n vin vin 0 dc¼2 lx vin vswo 10u meg vswo vg 0 0 nmos1 w¼50m l¼250n sdo vswo vo do 0 sw1v ddo vswo vo fdiode1 vo vo 0 dc¼4 .ic i(lx)¼470m .lib lib.txt .tran 1u .end Tip: Plot id(Meg), v(vg), and v(vswo) and zoom into transitions to explore. Plot i(Sh), v(deb), and i(Vdd1)*v(vdd1), and extract the average of the product term to determine PGI. Isolating PIV is challenging because id(Meg) often includes CGD’s current, which in this case is a significant fraction of id(Meg).

4.8.4

Operation

A. Switch Configuration Direct vIN–LX–vO connections in bucks and boosts deliver vIN power that LX does not transfer. This is because vIN supplies vO as LX energizes in bucks and as LX drains in boosts. This way, bucks and boosts supply more power than LX transfers. In bucks, the inductor power PL that vO receives with iL(AVG) across a tD fraction of tSW is less than the dE fraction iL(AVG) draws from vIN. LX in boosts similarly delivers less PL with the iL(AVG) that vIN supplies across a tE fraction of tSW than iL(AVG) draws from vIN. In both cases, PIN supplies more than PL:

234

4

Power Losses

PINðBKÞ ¼ iINðAVGÞ vIN ¼ iLðAVGÞ dE vIN ¼ iOðAVGÞ dE vIN ,   t PLðBKÞ ¼ iLðAVGÞ vD D ¼ iOðAVGÞ vO dD tSW

ð4:90Þ ð4:91Þ

¼ iOðAVGÞ vE dE ¼ iOðAVGÞ ðvIN  vO ÞdE , PINðBSTÞ ¼ iINðAVGÞ vIN ¼ iLðAVGÞ vIN ,   t PLðBSTÞ ¼ iLðAVGÞ vE E ¼ iINðAVGÞ vIN dE : tSW

ð4:92Þ ð4:93Þ

The buck–boost, on the other hand, delivers across tD the energy vIN feeds LX across tE. So PL is the PIN that vIN supplies. This means that, for the same PO, LX in bucks and boosts transfers less energy than in buck–boosts. Since lower inductor energy translates to lower iL, bucks and boosts burn less Ohmic, dead-time, and overlap power. These direct vIN–LX–vO transfers are one reason why bucks and boosts are more efficient than buck–boosts. The other reason is fewer switches. Buck–boosts need two more switches than bucks and boosts, which require additional Ohmic, gate-drive, dead-time, overlap, and switch-node power. This is why engineers normally resort to buck–boosts only when absolutely necessary, when vIN’s and vO’s operating ranges overlap. When a buck–boost is unavoidable, behaving like a buck when bucking and like a boost when boosting saves energy. This way, by switching two of the four switches while keeping a third closed and the fourth open, gate-drive power is lower. And with the lower iL that results, Ohmic loss in RL is also lower. So when bucking, the controller should switch SEI and SDG, open SEG, and close SDO. SEI should similarly close, SDG open, and SEG and SDO switch when boosting. The controller should switch all transistors only when vIN and vO are close. B. Discontinuous Conduction In discontinuous conduction, iL rises to iL(PK) and falls to zero across tC before tSW ends. The average Ohmic power PR(C) that a switch consumes across tC is a squared RMS translation of the current RE or RD carry across tE or tD, which is a root-three reflection of iL(PK): PRðCÞ  iE=DðRMSÞ

2

      iLðPKÞ 2 tE=D tE=D k RE=D RE=D ¼ pffiffiffi ¼ RC : tC t W C CH 3

ð4:94Þ

The average gate-charge power PG(C) needed across tC is the power vDD supplies when feeding gate charge qG into the gate:  PGðCÞ ¼ vDD iGðAVGÞ ¼ vDD

qG tC

 ¼ kGC WCH :

ð4:95Þ

Since RCH and PR(C) fall and qG and PG(C) rise with wider WCH’s, PR(C) and PG(C)’s sum PMOS(C) is minimal with the width that flattens the slope of PMOS(C) to

4.8 Design

235

zero. This optimal WCH' is the square-root ratio of the Ohmic and gate-drive coefficients kRC and kGC:    ∂PMOSðCÞ  ∂PRðCÞ  ∂PGðCÞ  k ¼ þ ¼  RC 2 þ kGC ¼ 0 ∂WCH WCH ' ∂WCH WCH ' ∂WCH WCH ' WCH ' WE=D

rffiffiffiffiffiffiffiffi kRC
WCH ' ¼ : kGC

ð4:96Þ

ð4:97Þ

With this WCH, PR(C) and PG(C) match, reducing PMOS(C) to PMOSðCÞ ¼ PRðCÞ þ PGðCÞ ¼ 2PRðCÞ ¼ 2PGðCÞ ¼ 2

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi kRC kGC :

ð4:98Þ

So across tSW, the optimal switch consumes PMOS(C) a tC fraction of tSW:  PMOS ¼ PMOSðCÞ

tC

tSW

 ¼2

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi kRC kGC tC f SW :

ð4:99Þ

Across each tSW, PO outputs the energy LX collects with iL(PK) and the additional power PE/D that vIN in bucks and boosts supplies. This PE/D is what iL’s average 0.5iL(PK) supplies vO across tE in bucks or draws from vIN across tD in boosts. Either way, the resulting PO climbs with switching frequency fSW:       iLðPKÞ tE=D EL 1 2 þ PE=D þ L i vO=IN tE=D f SW : PO   tSW tSW 2 X LðPKÞ 2

ð4:100Þ

This is fortunate because PMOS, PDT, PIV, PGI, and PSW also scale with fSW. So if LX’s energy EL is constant (with fixed tE, iL(PK), tD, and tC), powerconversion efficiency would be similarly independent of fSW, and as a result, of PO, because PO and losses scale with fSW: ηC ¼

PO PO f  / SW 6¼ f ðPO Þ: PIN PO þ PMOS þ PDT þ PIV þ PGI þ PSW f SW

ð4:101Þ

And with WCH', this ηC would also be optimally high. For this, the controller should adjust tSW (not dE), which is a form of frequency modulation (FM). Constant on-time control and pulse-FM (PFM), for example, fix tE and vary the frequency that LX delivers energy packets. Burst mode is a variation that adjusts either the number of consecutive energy packets delivered between conduction gaps or the conduction gap between consecutive energy packets. Figure 4.36 shows the measured efficiency of a photovoltaic battery-charging voltage regulator that adjusts the frequency of energy packets in discontinuous conduction. ηC is nearly constant at 95% when LX is 3  3  1.5 mm3. ηC is lower but still constant when LX is 1.6  0.8  0.8 mm3 because a smaller LX is more resistive and therefore lossier. ηC drops when the load power PLD that sets PO nears zero because the controller consumes quiescent power that does not scale with fSW (or PO).

236

4

Power Losses

Fig. 4.36 Measured efficiency of frequency-modulated DCM system

4.8.5

Power-Conversion Efficiency

Power-conversion efficiency refers to the fraction of PIN that PO outputs. This ηC is ultimately a reflection of fractional losses. So increasing ηC amounts to reducing σLOSS. A. Discontinuous Conduction In DCM, PR scales with iL(PK)2, tC, and fSW; PDT and PIV scale with iL(PK) and fSW; and PG, PGI, and PSW scale with fSW. PCNTRL and POFF are largely independent of iL(PK) and fSW. And PIN scales with the iO that sets PO.

Frequency Modulation With FM, iL(PK) and tC are constant and fSW scales with iO. This way, PCNTRL and POFF scale with iO0 and PR, PDT, PIV, PG, PGI, PSW, and PIN with iO1. So their fractional losses σDCM0 and σDCM1 scale with iO1 and iO0. This means σDCM0 falls with iO and σDCM1 is close to constant: σDCM0  σDCM1 

PCNTRL þ POFF iO 0 1 / 1/ iO PIN iO

PR þ PDT þ PIV þ PG þ PGI þ PSW iO 1 / 1 6¼ f ðiO Þ: PIN iO

ð4:102Þ ð4:103Þ

4.8 Design

237

Fig. 4.37 Power-conversion efficiency in DCM

When lightly loaded, iO-dependent losses are so low that PCNTRL and POFF dominate. In this region in Fig. 4.37, ηC rises because σDCM0 falls with iO. ηC eventually peaks and flattens in Region II when PR, PDT, PIV, PG, PGI, and PSW dominate because σDCM1 is constant across that range.

Peak Modulation Peak modulation (PM) is another way of controlling PO. In this scheme, fSW is constant. And the controller adjusts iL(PK) so iL(AVG) delivers the iO(AVG) the load demands. This way, iL(PK) and tC scale with √iO. And PG, PGI, PSW, PCNTRL, and POFF scale with iO0, PDT and PIV with iO0.5, and PR with iO1.5. So σDCM0, σDCM0.5, and σDCM1.5 scale with iO1, iO0.5, and iO0.5. In other words, σDCM0 and σDCM0.5 fall and σDCM1.5 rises with iO: σDCM0 

 0 PG þ PGI þ PSW þ PCNTRL þ POFF i k ¼ kD0 O 1 ¼ D0 , PIN iO iO  0:5  P þ PIV i k ffiffiffiffi , σDCM0:5  DT ¼ kD0:5 O 1 ¼ pD0:5 PIN iO iO  1:5  pffiffiffiffi P i σDCM1:5  R ¼ kD1:5 O 1 ¼ kD1:5 iO : PIN iO

ð4:104Þ ð4:105Þ ð4:106Þ

When lightly loaded, iO reduces PR to such an extent that PDT, PIV, PG, PGI, PSW, PCNTRL, and POFF dominate. ηC rises in Region I in Fig. 4.37 because σDCM0.5 and σDCM0 fall with iO. ηC falls in Region II when PR dominates because σDCM1.5 climbs with iO. Their combined σLOSS reaches its minimum when its slope flattens with respect to iO. This happens when σCCM1.5’s rise cancels σDCM0 and σDCM0.5’s fall. At this optimal iO', ηC maxes (with one minus this σLOSS at iO'):

238

4

Power Losses

Fig. 4.38 Power-conversion efficiency in CCM

 ∂σ DCM0 ∂σ DCM0:5 ∂σ DCM1:5  k k kD1:5 ffiffiffiffiffiffi ¼ 0: ffiffiffiffiffiffiffi þ p þ þ ¼  D02  qD0:5 ∂iO ∂iO ∂iO iO ' 3 iO ' 2 iO ' 2 iO '

ð4:107Þ

So ηC peaks when PR balances PDT, PIV, PG, PGI, PSW, PCNTRL, and POFF. B. Continuous Conduction In CCM, PR(AC), PG, PGI, PSW, PCNTRL, and POFF scale with iO0; PDT, PIV, and PIN with iO1; and PR(DC) with iO2. So their corresponding fractional losses σCCM0, σDCM1, and σDCM2 scale with iO1, iO0, and iO1. In other words, σDCM0 falls and σDCM2 rises with iO and σDCM1 is close to constant: σCCM0 

PRðACÞ þ PG þ PGI þ PSW þ PCNTRL þ POFF kC0 ¼ , PIN iO   PDT þ PIV i ¼ kC1 O ¼ kC1 , σCCM1  PIN iO  2 PRðDCÞ i σCCM2  ¼ kC2 O ¼ kC2 iO : PIN iO

ð4:108Þ ð4:109Þ ð4:110Þ

When iO is low, PR(AC), PG, PGI, PSW, PCNTRL, and POFF often outweigh iO-dependent losses. ηC rises in Region III in Fig. 4.38 because σDCM0 falls with iO. ηC flattens in Region IV when PDT and PIV dominate because σDCM1 is largely insensitive to iO. ηC falls in Region V when PR(DC) dominates because σDCM2 climbs with iO. Their combined σLOSS reaches its minimum when its slope flattens with respect to iO. This happens when σCCM2’s rise cancels σDCM0’s fall. At this optimal iO'', ηC maxes (with one minus this σLOSS at iO''):  ∂σCCM0 ∂σCCM1 ∂σCCM2  k þ þ ¼  C02 þ 0 þ kC2 ¼ 0, ∂iO ∂iO ∂iO iO'' iO '' rffiffiffiffiffiffiffi kC0 iO '' ¼ , kC2

ð4:111Þ

ð4:112Þ

4.9 Summary

239

σCCM0 jiO'' ¼ σCCM2 jiO'' ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffi kC0 kC2 ,

ηCðPKÞ ¼ 1  σCCM0 jiO''  σCCM1 jiO''  σCCM2 jiO'' pffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 1  σCCM1  2 kC0 kC2 :

ð4:113Þ

ð4:114Þ

So ηC peaks when PR(DC) balances PR(AC), PG, PGI, PSW, PCNTRL, and POFF. C. Response The operating range of a load can sometimes exclude ηC’s outer regions. Wireless microsensors, for example, can exclude Regions IV–V because output power is never high. Less mobile higher-power applications, on the other hand, can exclude Regions I–II because their loads are never low. Although not often the case, ηC can peak twice when fSW is constant: once in DCM and another time in CCM. ηC can also shrink or skip regions. ηC can, for example, reduce or jump Regions II–III when PDT and PIV are heavy or Regions III– IV when PDT and PIV are light and PR is heavy. Maxing ηC is ultimately more important than peaking it. In other words, reducing σLOSS across loads saves more energy than peaking ηC at a particular load. This is because the highest ηC for a particular iO is not necessarily where ηC peaks.

4.9

Summary

Switched-inductor power supplies are popular in electronics because they condition and transfer most of the power they receive. Power-conversion efficiency is high because losses are low. Still, resistances, diodes, and transistors consume power that the output does not receive. Resistances in switches, inductors, and capacitors burn Ohmic power when they conduct. The current that sets this conduction power decomposes into static and alternating components. The dc portion is ultimately a reflection of the load. The ac portion accounts for ripples, including those that connecting and disconnecting the load creates. Diodes that conduct dead-time current when switches are off consume power. These diodes conduct twice every switching cycle in continuous conduction. In discontinuous conduction, they only conduct once per cycle because inductor current is zero after LX drains. Transistors burn iDS–vDS overlap power when they switch. Input, output, and diode voltages set the voltage they swing and inductor current sets the current they conduct. Recovering in-transit charge held in diodes increases the current and time they conduct. Although gate drivers ensure these transitions are short, overlap power is not always negligibly low. Luckily, diode voltages are usually so much lower than input and output voltages that transitioning across these voltages burns a small fraction of drawn input power.

240

4

Power Losses

Overlap power is similarly low when inductor current reaches zero in discontinuous conduction. Soft-switching events like these are desirable in power supplies. Gate drivers and pre-drivers draw and burn the supply power needed to switch transistors: half when charging gates and the other half when draining gates. They also leak shoot-through power. This leakage is low, however, when input and output voltage transitions do not overlap. Switch-node capacitances leak the energy they need to charge. Although the inductor helps the output recover some of this energy, switches ultimately burn most of it. Large power transistors also leak current in cut off, especially when they are hot. Although not always known, minimizing losses at the most probable load level saves the most energy. Ohmic and gate-charge power in MOSFETs can balance at this load setting with a particular channel width. Gate drivers can similarly balance driver gate-charge and iDS–vDS overlap power with specific N- and P-channel widths. Since bucks steer input power into the output when they energize and boosts when they drain, bucks and boosts deliver more power than their inductor transfer. So bucks and boosts need less current to draw and deliver power than buck–boosts. Bucks and boosts also need fewer switches. And with lower current and fewer switches, Ohmic losses are lower. Efficiency is usually low when loads are light because quiescent power in the controller is a large fraction of the input power drawn. Efficiency is also low when loads are heavy because dc Ohmic losses scale faster with output power than input power does. Frequency modulation in discontinuous conduction flattens efficiency when MOS Ohmic and gate-charge losses balance. Efficiency peaks in continuous conduction when ac ripple and charge losses similarly balance dc Ohmic losses. High efficiency is important in voltage regulators, LED drivers, and chargers because it saves energy. Although not to the same extent, it is also important in energy harvesters. Output power is ultimately more important in harvesters because ambient energy is not always available. Still, output power is higher when efficiency peaks at the maximum-power point, which is not always possible, especially when the ambient source and the corresponding maximum-power point drift over time.

5

Frequency Response

Abbreviations CCM CMOS DCM LED SL RSS A0 AGI AGO AHF AII AIO AN AT AVI AVO AZI AZO CB CC CO CS dD dO dE dE ' ΔiL

Continuous-conduction mode Complementary metal–oxide–semiconductor Discontinuous-conduction mode Light-emitting diode Switched inductor Root sum of squares Zero-/low-frequency gain Input transconductance Output transconductance High-frequency gain Input current gain Output current gain Norton gain Thévenin gain Input voltage gain Output voltage gain Input transimpedance Output transimpedance Bypass capacitor Couple capacitor Output capacitor Shunt capacitor Drain duty cycle Output duty cycle Energize duty cycle Energize command CCM current ripple

# The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 G. A. Rincón-Mora, Switched Inductor Power IC Design, https://doi.org/10.1007/978-3-030-95899-2_5

241

242

fLC fO fSW CG i iDO iIN iL iN iO is LC LDO LS LX pC pL pLC pSW pX QLC RC RDO RI RIN RL RLD RLD' RN RO RP RS RT RV sA sC sI sO tC tD tE tO tSW vD vE

5 Frequency Response

Transitional LC (resonant) frequency Operating frequency Switching frequency Gate capacitance Imaginary unit Duty-cycled current Input current Inductor current Norton current Output current Small-signal current source Couple inductor Duty-cycled inductance Shunt inductor Switched (transfer) inductor Capacitor pole Inductor pole LC double pole Switching pole Reversal pole LC peak quality Couple resistor/capacitor resistance Duty-cycled resistance Current-limit resistor Input resistance Inductor resistance Load resistance Equivalent load resistance Norton resistance Output resistance Parallel resistance Series resistance Thévenin resistance Voltage-limit resistor Analog signal Control signal Input signal Output signal Conduction time Drain time Energize time Output conduction time Switching period Drain voltage Energize voltage

5.1 Two-Port Models

vIN vL vO vs vT ωO zC zDO ZDO zL zX

243

Input voltage/input Inductor voltage Output voltage/output Small-signal voltage source Thévenin voltage Angular frequency Capacitor zero Duty-cycled zero Duty-cycled impedance Inductor zero Reversal zero

The principal aim of power supplies is to transfer input power to the output. Conditioning this power into a form that the load can receive and use is a crucial component of this directive. This is what turns voltage regulators into voltage sources and battery chargers and light-emitting diode (LED) drivers into current sources. To suppress deviations, power supplies incorporate feedback loops that monitor and oppose variations in the output. This opposition is ultimately a reaction to a disturbance. So understanding how switched inductors (SL) respond to the adjustments that disturbances prompt is critical. Since fluctuations decompose into frequency components, frequency response describes how systems react to dynamic variations. This response is well-understood in linear systems. Nonlinear systems like the switched inductor are not so straightforward. In these cases, isolating and modeling the dynamic elements peel away the complexities of nonlinearity.

5.1

Two-Port Models

Two-port models are four-component networks that predict the reverse and forward response of a circuit when stimulated and loaded. The input and output of the model are interdependent resistive voltage or current sources. The input loads the circuit that drives the network and models feedback effects and the output drives the load of the network and models forward translations. The fundamental advantage of these two-port models is simplicity, because four components can emulate the effects of complex circuits. This is possible because the components model orthogonal effects. In other words, each component models what the others do not. Each interdependent source incorporates two components: resistance and gain. Resistance models loading in the absence of gain and gain models amplification in the absence of a load. Extracting one parameter therefore requires test conditions that nullify the other.

244

5 Frequency Response

Fig. 5.1 Thévenin voltage source

RT sC A T

Fig. 5.2 Norton current source

RN

vT

iN

sC AN

5.1.1

Primitives

A. Voltage Source The Thévenin model is a dependent voltage source in series with a resistor. The Thévenin gain AT is the unloaded gain translation to the Thévenin voltage vT in Fig. 5.1 and the Thévenin resistance RT is the resistance into the circuit. When loaded, vT manifests the effects of AT and RT. To nullify the effects of RT on vT, RT should drop zero volts. This happens when RT’s current is zero, which results when the load is absent. So removing the load eliminates the effects of RT when deriving AT. Zeroing AT’s control signal sC similarly extinguishes the effects of AT on vT when extracting RT. B. Current Source The Norton model is a dependent current source paralleled by a resistor. The Norton gain AN is the zero-volt gain translation to the Norton current iN in Fig. 5.2 and the Norton resistance RN is the resistance into the circuit. When loaded, iN manifests the effects of AN and RN. To nullify the effects of RN on iN, RN should not conduct current. This happens when RN’s voltage is zero, which results when the output terminals short. So shorting the output removes the effects of RN when deriving AN. Zeroing AN’s sC similarly eliminates the effects of AN on iN when extracting RN.

5.1.2

Bidirectional Models

A. Impedance: Voltage The impedance voltage model in Fig. 5.3 uses voltage sources to model the input and output. Input and output transimpedances AZI and AZO model feedback and forward

5.1 Two-Port Models

245

Fig. 5.3 Bidirectional impedance voltage model

i IN vIN

Fig. 5.4 Bidirectional conductance/admittance current model

iO RZI i OAZI

iINAZO

i IN vO A GI

RGO

RGI

vINAGO

i IN vIN

vO

iO

vIN

Fig. 5.5 Bidirectional hybrid voltage–current model

RZO

vO

iO RVI vOAVI

RIO

vO

i INAIO

translations to the input voltage vIN and output voltage vO. And resistances RZI and RZO model loading effects. The elegance of this model is that all extractions require open-circuit conditions. Removing the input source, for example, eliminates the input current iIN that nullifies RZI when deriving AZI and AZO when deriving RZO. Similarly, removing the output load zeros the output current iO that nullifies RZO when deriving AZO and AZI when deriving RZI. B. Conductance/Admittance: Current The conductance or admittance current model in Fig. 5.4 uses current sources to model the input and output. In this case, input and output transconductances AGI and AGO model feedback and forward translations to iIN and iO and all extractions require short-circuit conditions. Shorting vIN nullifies RGI when deriving AGI and AGO when deriving RGO. Shorting vO similarly nullifies RGO when deriving AGO and AGI when deriving RGI. C. Hybrid: Voltage–Current The hybrid voltage–current model in Fig. 5.5 uses a voltage source for the input and a current source for the output. The input voltage gain AVI models feedback to vIN and the output current gain AIO models forward translations to iO. Here, removing the input source eliminates the iIN that nullifies RVI when deriving AVI and AIO when deriving RIO. And shorting vO nullifies RIO when deriving AIO and AVI when deriving RVI.

246

5 Frequency Response

Fig. 5.6 Bidirectional reverse-hybrid current– voltage model

iO

i IN i OAII vIN RII

RVO vINAVO

vO

D. Reverse Hybrid: Current–Voltage The reverse-hybrid current–voltage model in Fig. 5.6 uses a current source for the input and a voltage source for the output. The input current gain AII models feedback to iIN and the output voltage gain AVO models forward translations to vO. Shorting vIN nullifies RII when deriving AII and AVO when deriving RVO. Removing the output load similarly zeros the iO that nullifies RVO when deriving AVO and AII when deriving RII.

Example 1: Extract hybrid voltage–current parameters for the impedance voltage model. Solution:

RVI



  ðiIN AZO =RZO ÞAZI vIN

iIN RZI þ iO AZI AZO ¼ ¼ R þ ¼ R þ AZI ZI ZI iIN
vO ¼0 iIN iIN RZO


  
iO AZI

iIN AZO  vO AZI

¼
vO iIN ¼0 RZO vO
i ¼0 iIN ¼0 IN    vO AZI AZI ¼ ¼ RZO vO RZO
i A =R i
A
O

¼ IN ZO ZO ¼ ZO iIN vO ¼0 iIN RZO



AVI
vvINO


AIO

RIO



vO

iO
i

¼

¼ IN ¼0


iIN AZO  iO RZO

¼ RZO
iO iIN ¼0

Note: Two-port models are transformable.

5.1 Two-Port Models

247

Fig. 5.7 Forward voltagesourced models

i IN RIN vIN

Fig. 5.8 Forward currentsourced models

vO

vIN

iO

i IN RO

vIN iINAI

iO RIN

RO iINAZ

RIN

5.1.3

i IN

iO

RO

iO

i IN RIN vO

vO

vINAV

RO vO

vIN vIN A G

Forward Models

Many circuits incorporate little to no feedback. In such cases, modeling the negligible feedback component is an unnecessary complication. This is why forward-only models are so popular: because they are simple. Without feedback, the current or voltage source that models the input reduces to the input resistance RIN shown in Figs. 5.7 and 5.8. Since no other component models the input, test conditions do not apply to RIN. This means that RIN is the same in all forward models. Since vIN and iIN are Ohmic RIN translations of one another, zeroing one eliminates the other. So nulling forward translations ultimately produces the same effect on the output. This means that the output resistance RO is also the same in all forward models. The only variation in forward models is the forward translation. This forward translation is a series voltage when using a voltage source and a parallel current when using a current source. And it responds to vIN or an Ohmic RIN translation of vIN, which is iIN.

Example 2: Extract voltage-driven current-source parameters for the impedance voltage model when feedback effects are negligible. Solution: Negligible feedback

∴

AZI  0 RIN  RZI RO  RZO
i A =R i
AZO AG
O

 IN ZO ZO  vIN vO ¼0 iIN RZI þ iO AZI RZI RZO

248

5 Frequency Response

5.2

LC Primitives

5.2.1

Impedances

A. Capacitor Capacitors do not consume power like resistors. Instead, they draw, hold, and supply energy. They are reactive components because they are reacting when they receive and release power. The voltage across them indicates how much electrostatic energy their plates hold. Discharged capacitors draw current when connected across a voltage source. Larger capacitors pull more charge. They also draw more current when charged more frequently. So capacitor impedance ZC falls with increasing capacitance CX and operating frequency fO: ZC ¼

1 1 1 1 ¼ ¼ / , sCX iωO CX ið2πf O ÞCX f O

ð5:1Þ

where “s” in the Laplace domain is iωO or i(2πfO), “i” is the imaginary unit whose square i2 is 1, ωO is angular frequency in radians per second, fO is in cycles per second, and each cycle is 2π radians long (i.e., 2π radians per cycle). Capacitors are like switches that close and short with fO. They open at low fO, close and shunt resistances as fO climbs, and short at high fO. Parallel resistors fade when capacitors shunt them and capacitors effectively short when series resistances overwhelm them. B. Inductor Inductors are also reactive because they also draw, store, and deliver energy. In their case, current indicates how much magnetic energy their windings and core hold. They draw this current when connected across a voltage source. This current scales with voltage, is lower with more windings and larger loops, and rises with time. So inductor impedance ZL climbs with the inductance LX that windings set and the shorter energize periods that higher fO avails. In short, ZL is ZL ¼ sLX ¼ iωO LX ¼ ið2πf O ÞLX / f O :

ð5:2Þ

Inductors are like switches that open with fO. They close at low fO, open and overcome resistances as fO climbs, and altogether open at high fO. Series resistors effectively short when inductors overcome them and inductors open and fade when parallel resistors limit their voltage.

249

vIN

RO

CS

AV0 RO

o

0

CS

AV [ o]

RC

pC c. de B/ 0d –2

vO

A V [dB]

5.2 LC Primitives

–45

o

pC –90

Log Freq. [Hz]

o

Log Freq. [Hz]

Fig. 5.9 Shunt capacitor

5.2.2

Shunt Capacitor

A. Response Nodes in a circuit incorporate the parasitic capacitance that components and traces on a board add. These are shunt capacitors because they “shunt” current and energy away from their intended recipients. CS in Fig. 5.9 is one such example because CS steers current away from RO. Gain The effect of CS on vO is low at low fO because CS opens at low fO. So the zero- or low-frequency gain AV0 to vO is the voltage-divided fraction of vIN that couple resistor RC feeds RO: AV0 

RO : RC þ RO

ð5:3Þ

But as ZS falls with fO, CS sinks more and more current away from RO. And with less current available, RO drops a lower voltage. CS begins to dominate the response at the fO that CS’s impedance Zs or 1/sCS shunts the parallel resistance that RO and RC into vIN establish across CS:
1

ZS ¼ sCS
f O 

1
pC 2πðRO kRC ÞCS

 RO kRC :

ð5:4Þ

So RO sets the gain below this capacitor pole pC and CS above it. Since ZS shunts RO and RC surpasses ZS past this pC, the gain to vO past pC reduces to ZS/RC, which scales with 1/fO: AV ¼



RO kZS Z 1 1
 S¼ / : RC sRC CS f O RC þ ðRO kZS Þ
f O >p

ð5:5Þ

C

This gain AV drops 10 or 20 dB when fO climbs 10 or a decade. In short, AV falls when CS shunts the resistance at vO.

250

5 Frequency Response

The overall gain to vO is the voltage-divided fraction of vIN that RC feeds RO and CS: AV


RO kZS vO ¼ ¼ vIN RC þ ðRO kZS Þ



RO RC þ RO



1



1 þ sðRO kRC ÞCS

¼

AV0 : 1 þ s=2πpC ð5:6Þ

The gain drops with fO in “s” when s(RO || RC)CS exceeds 1, 2πfO in “s” overcomes 2πpC, or more simply, fO surpasses pC, as already stated. AV’s magnitude |AV| is the ratio of the root sum of squares (RSS) of the real and imaginary components in AV0 and 1 + s(RO || RC)CS or 1 + s/2πpC: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi AV0 2 þ 02 AV0 j AV j¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi : 2 2 2 1 þ ðf O =pC Þ2 1 þ ðf O =pC Þ

ð5:7Þ

So |AV| is nearly AV0 a decade below pC, √2 or 3 dB lower at pC, and almost 10 or 20 dB lower a decade past pC. Phase Since CS requires time to charge (and raise vO), CS delays vIN-to-vO translations. The delay between vIN and vO sinusoids when 1/sCS swamps RO || RC effects is 90 of the 360 cycle. This lagging (negative) delay halves when 1/sCS matches RO || RC and fades when CS opens. So AV’s phase ∠AV is nearly 0 a decade below pC, 45 at pC, and almost 90 a decade past pC: ∠AV ¼  tan

1



 fO : pC

ð5:8Þ

Transitional frequencies that prompt gain and phase to drop 20 dB per decade and up to 90 this way are poles. B. Current-Limit Resistor The shunting effects of capacitors fade when they short. And they effectively short when resistors limit their current. Consider CS and current-limit resistor RI in Fig. 5.10. CS shunts resistances past pC and shorts past an fO that RI sets. Gain RI adds to the resistance RO and RC into vIN present. So CS and RI shunt RO with RC into vIN when ZS falls below the parallel resistance that RI and RO with RC set. And AV falls past the pC that their RC frequency determines:

251

vIN

RI RO

CS

pC AV [dB]

vO

RC

AV0 RO

–2

RO || R I 0d

B/ de c.

CS

z CX

AV(HF)

AV [ o ]

5.2 LC Primitives

o

0

pC –45

–90

Log Frequency [Hz]

o

zCX

o

Log Frequency [Hz]

Fig. 5.10 Current-limited shunt capacitor


1

ZS ¼ sCS
f O 

1
pC 2π½RI þðRO kRC Þ CS

 RI þ ðRO kRC Þ:

ð5:9Þ

RI lowers the pC that CS induces because RI adds series resistance to CS. The gain to vO drops past pC as ZS falls with 1/fO. When CS shorts, RI parallels RO, so the high-frequency voltage-divided gain AV(HF) flattens to AVðHFÞ 

RO kRI : RC þ ðRO kRI Þ

ð5:10Þ

This happens because RI limits the current that CS can pull. So the effects of pC fade when CS shorts with respect to RI: ZS ¼


1

sCS
f O 

1 2πRI CS
zCX

 RI :

ð5:11Þ

In eliminating the effects of pC, RI is effectively raising gain 20 dB per decade and recovering up to 90 of phase. Transitional frequencies that prompt gain and phase to climb this way are zeros. This particular zero is a reversal zero because resistors that current-limit shunt capacitors reverse the effects of capacitor poles. The overall voltage gain to vO is the voltage-divided fraction of vIN that RC feeds RO and CS with RI: AV


RO kðZS þ RI Þ vO ¼ vIN RC þ ½RO kðZS þ RI Þ    RO 1 þ sRI CS ¼ RC þ RO 1 þ s½RI þ ðRO kRC Þ CS   1 þ s=2πzCX ¼ AV0 : 1 þ s=2πpC

ð5:12Þ

252

5 Frequency Response

AV is AV0 when fO is very low and AV0pC/zCX or AV(HF) when fO is very high. AV falls with fO when s[RI + (RO || RC)]CS exceeds 1 or fO surpasses pC and flattens when sRICS exceeds 1 or fO surpasses zCX. Phase Since zCX recovers the phase that pC loses, ∠AV adds up to 90 of phase at higher fO. So when pC is much lower than zCX, ∠AV is close to 0 a decade below pC, 45 at pC, and almost 90 a decade past pC: ∠AV ¼  tan 1



fO pC



þ tan 1



 fO : zCX

ð5:13Þ

∠AV does not recover much phase a decade below zCX, recovers 45 at zCX, and recovers almost all 90 a decade past zCX.

Example 3: Determine AV0, AV(HF), and related poles and zeros when RC is 50 Ω, RO is 100 Ω, CS is 5 μF, and RI is 10 mΩ. Solution:

AV0  pC ¼

RO 100 ¼ 670 mV=V ¼ 3:5 dB ¼ RC þ RO 50 þ 100

1 1 ¼ 950 Hz ¼ 2π½RI þ ðRO kRC Þ CS 2π½10m þ ð100k50Þ ð5μÞ zCX ¼

AVðHFÞ 

1 1 ¼ ¼ 3:2 MHz 2πRI CS 2πð10mÞð5μÞ

RO kRI 100k10m ¼ 200 μV=V ¼ 74 dB ¼ RC þ ðRO kRI Þ 50 þ ð100k10mÞ

Note: In practice, RI and RO can be the parasitic resistance that CS incorporates and the load resistance that a circuit presents.

5.2 LC Primitives

253

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Shunt Capacitor vin vin 0 dc¼0 ac¼1 rc vin vo 50 ro vo 0 100 ri vo vc 10m cs vc 0 5u .ac dec 1000 10 100e6 .end Tip: Plot v(vo) in dB to inspect AV.

5.2.3

Couple Capacitor

A. Response Capacitors can also short terminals together. In this sense, they are like switches that shunt and short the infinite resistance between disconnected nodes. Consider the couple capacitor CC in Fig. 5.11. CC feeds current iC as it connects and eventually shorts vIN to vO. Gain ZC is so high at very low fO that CC drops almost all of vIN. Since RO drops a very small fraction of vIN, the low-fO gain to vO is very low. In fact, ZC is so much greater than RO that ZC overwhelms RO. This means, the voltage gain to vO reduces to RO/ZC and, as a result, scales with fO:
RO

AV ¼ ZC þ RO
f O p ZC sLC f O

ð5:23Þ

L

Past this inductor pole pL, AV drops 20 dB when fO increases a decade. AV falls because LC dominates when ZC overcomes the resistance at vO. The gain to vO is the voltage-divided vIN fraction that LC feeds RO: AV


vO RO RO 1 AV0 ¼ ¼ ¼ ¼ : vIN ZC þ RO sLC þ RO 1 þ sLC =RO 1 þ s=2πpL

ð5:24Þ

The gain drops with fO when sLC/RO exceeds 1 or fO surpasses pL. |AV| is the ratio of the root sum of squares of the real and imaginary components in AV0’s 1 and 1 + sLC/RO or 1 + s/2πpL: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi AV0 2 þ 02 AV0 q ffi: ffi ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi j AV j¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 2 2 1 þ ðf O =pL Þ 1 þ ðf O =pL Þ

ð5:25Þ

So |AV| is nearly AV0’s 1 upto a decade below pL, √2 or 3 dB lower at pL, and almost 10 or 20 dB lower a decade past pL. Phase Since LC requires time to grow its current iC, LC delays vIN-to-iC translations. The delay between vIN and iC sinusoids after sLC swamps RO is 90 of the 360 cycle. This lagging (negative) delay halves when sLC matches RO and fades when LC shorts. So AV’s phase ∠AV is close to 0 a decade below pL, 45 at pL, and almost 90 a decade past pL: ∠AV ¼  tan

1

  fO : pL

ð5:26Þ

B. Voltage-Limit Resistor The effects of inductors overcoming resistances disappear when inductors open. They open when resistors limit the voltage they drop. Consider LC and voltage-limit resistor RV in Fig. 5.14. LC overcomes series resistances past pL and opens past an fO that RV sets. Gain LC drops a negligible fraction of vIN at low fO, so AV0 is nearly one. AV falls when ZC begins to drop a noticeable part of vIN. This happens when sLC overcomes the resistance that RO and RV into vIN establish across LC:

RV

vO LC

vIN

RO

pL 0 dB

–2

0d

B/ de c.

RO

LC

RV + R O z LX AV(HF)

AV [ o ]

5 Frequency Response

AV [dB]

258

o

0

pL –45

–90

Log Frequency [Hz]

o

zLX

o

Log Frequency [Hz]

Fig. 5.14 Voltage-limited couple inductor

ZC ¼ sLC jf

RO jjRV O  2πL
pL C

 RO kRV :

ð5:27Þ

Notice that adding RV to the circuit reduces the pL that LC induces. LC eventually opens when RV limits the voltage LC drops, which happens when sLC surpasses RV, which is the resistance that parallels LC: ZC ¼ sLC jf O  RV
zLX  RV : 2πLC

ð5:28Þ

Past this reversal zero, RV and RO alone drop vIN, so the high-fO AV flattens to AVðHFÞ 

RO : RV þ RO

ð5:29Þ

In eliminating the effects of pL, RV is effectively raising gain 20 dB per decade and recovering up to 90 of phase. So resistors that limit the voltage that couple inductors drop reverse inductor poles. Overall, AV is the voltage-divided vIN fraction that LC and RV feed RO:   1 þ sLC =RV 1 þ s=2πzLX RO ¼ AV ¼ ¼ AV0 : ðZC kRV Þ þ RO 1 þ sLC =ðRO kRV Þ 1 þ s=2πpL

ð5:30Þ

AV is AV0’s 1 or 0 dB when fO is very low and AV0pL/zLX or AV(HF) when fO is very high. AV falls with fO when sLC/(RO || RV) exceeds 1 or fO surpasses pL and flattens when sLC/RV exceeds 1 or fO surpasses zLX. |AV| is the ratio of the root sum of squares of real and imaginary components in 1 + sLC/RV and 1 + sLC/(RO || RV): 2qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi3 2 2 6 1 þ ðf O =zLX Þ 7 j AV j¼ AV0 4 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 5: 12 þ ðf O =pL Þ2

ð5:31Þ

When zLX is much higher than pL, |AV| is nearly AV0 a decade below pL, √2 or 3 dB lower at pL, and almost 10 or 20 dB lower a decade past pL. |AV| is √2 or 3 dB above AV(HF) at zLX and nearly AV(HF) a decade past zLX.

5.2 LC Primitives

259

Phase Since zLX recovers the phase that pL loses, ∠AV adds up to 90 of phase at high fO. So when pL is much lower than zLX, ∠AV is close to 0 a decade below pL, 45 at pL, and almost 90 a decade past pL: ∠AV ¼  tan 1

    fO f þ tan 1 O : pL zLX

ð5:32Þ

∠AV recovers 45 at zLX and almost all 90 a decade past zLX.

Example 5: Determine AV0, AV(HF), and related poles and zeros when LC is 10 μH, RV is 1 kΩ, and RO is 100 Ω. Solution: AV0  1 V=V ¼ 0 dB pL ¼

RO kRV 100k1k ¼ ¼ 1:4 MHz 2πLC 2πð10μÞ

zLX ¼ AVðHFÞ 

RV 1k ¼ 16 MHz ¼ 2πLC 2πð10μÞ

RO 100 ¼ 91 mV=V ¼ 21 dB ¼ RV þ RO 1k þ 100

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Couple Inductor vin vin 0 dc¼0 ac¼1 lc vin vo 10u rv vin vo 1k ro vo 0 100 .ac dec 1000 10k 1g .end Tip: Plot v(vo) in dB to inspect AV.

5 Frequency Response

LS

vIN

RC

o

0 dB

LS

90

AV [ o]

CO

RC

pLX +2 0d B/ de c.

vO

A V [dB]

260

o

45

pLX o

0

z L0 Log Freq. [Hz]

Log Freq. [Hz]

Fig. 5.15 Shunt inductor

5.2.5

Shunt Inductor

A. Response Shunt inductors block and avail current as they impede current flow and open with fO. So inductors that shunt vO unload with fO. Consider the shunt inductor LS in Fig. 5.15. Gain ZS is so low at very low fO that LS drops a small fraction of vIN. Since RC drops almost all of vIN, the low-fO gain to vO is very low. This gain scales with ZS as fO climbs. ZS is so low that RC overwhelms ZS, so the voltage gain to vO reduces to ZS/RC, which scales with fO:
ZS

AV ¼ RC þ ZS
f O f LC ¼ 2πLX 2πð10μÞ

1 1 ¼ 740 Hz ¼ 2π½RC þ ðRLD kRL Þ CO 2π½10 þ ð100k50Þ ð5μÞ zC ¼

f LS ¼

1 1 ¼ 3:2 kHz ¼ 2πRC CO 2πð10Þð5μÞ

RL þ ðRC kRLD Þ 50 þ ð10k100Þ ¼ ¼ 940 kHz 2πLX 2πð10μÞ

zCP  f CP < pC  f CS < zC < f LC < pL  f LS  

 p 740 ¼ 17 mA=V ¼ 35 dB AGðLCÞ  AG0 C ¼ ð6:7mÞ 290 zCP  

 p 740 ¼ 160 mV=V ¼ 16 dB AVðLCÞ  AV0 C ¼ ð670mÞ 3:2k zC !

Note: zCP is absent in AV and zC is absent in AG.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Voltage-Sourced LC vin vin 0 dc¼0 ac¼1 lx vin vl 10u rl vl vo 50m *rl vl vo 10 *rl vl vo 50 rc vo vc 10m (continued)

5.4 LC Circuits

285

*rc vo vc 10 co vc 0 5u rld vo 0 100 *rld vo 0 1.4 .ac dec 1000 10 100e6 .end Tip: Plot i(Lx) and v(vo) in dB and comment/un-comment rl’s, rc, and rld to see their effects on AG and AV.

5.4.3

LC Tank

Energy offers another perspective of the peaking that results when LX and CO interact at fLC. LX holds magnetic energy 0.5LXiL2 with iL and CO stores electrostatic energy 0.5COvC2 with vC. At fLC, iL charges and discharges CO and vC energizes and drains LX. As this happens, iL draws vIN energy. This way, LX and CO become an LC tank that collects and exchanges vIN energy. LC energy grows until iL is so high that resistances in the network burn the energy vIN supplies. This is how resistances limit and dampen the peaking in iL and vC at the LC resonant frequency fLC.

5.4.4

Phase Shift

The gain of parallel and series LC structures peaks when ZL and ZC swap dominance at fLC. This happens when ZL and ZC eclipse resistive effects. So the phase shift across pLC is the phase difference that ZL and ZC produce. Since ZL and ZC set vO in parallel networks, sLX induces a zL0 that adds 90 and 1/sCO produces a pC0 that sheds 90 . Series combinations are similar because the 1/ZC and 1/ZL that set iL induce a zC0 and a pL0 that also add and shed 90 . When gain shifts between ZL or 1/ZC and ZC or 1/ZL, signals lose the 90 that zL0 or zC0 adds and the 90 that pC0 or pL0 deducts. So LC structures lose 180 across pLC. When resistive effects are negligible, this shift is abrupt. As resistances dampen the interaction, phase shifts more gradually. When QLC is one, for example, the pL that LX establishes and the pC that CO sets coincide at fLC without peaking the gain. Fig. 5.29 LC phase shift

o

QLC

A LC [ o ]

0

pLC 10

1 o –90 –180

o

pLC 10pLC

Log Frequency [Hz]

286

5 Frequency Response

So pL and pC start and stop losing noticeable phase in Fig. 5.29 a decade below and above fLC. As QLC increases, the transition band narrows and the edge sharpens. The arc tangent is useful when expressing phase because it outputs up to 90 with operands. In the case of LC phase ∠ALC, subtracting 90 removes the offset tan1 produces when fO is less than fLC. This way, the result matches the 0 to 180 range that LX and CO shift:    f f ∠ALC ¼ tan 1 QLC LC  O  90 : f O f LC

ð5:79Þ

fLC/fO minus fO/fLC inside the tan1 term senses how fO relates to fLC (determining the polarity of the tan1) and QLC magnifies the difference. So when QLC is high, small positive and negative differences output close to 90 – 90 , which is 0 , and 90 – 90 , which equals 180 . Large differences produce similar results when QLC is low.

5.5

Switched Inductor

5.5.1

Signal Translations

The underlying aim of power supplies is to regulate the output voltage vO in voltage regulators and the output current iO in battery chargers and LED drivers. For that, they incorporate a controller that compares vO or iO with a reference, amplifies the error, and uses the result to adjust and steady vO or iO. Together, the switched inductor and controller close a feedback loop that regulates vO or iO by sensing and responding to small variations in the output. A. Analog Response How vO or iO responds to changing operating conditions hinges on small-signal translations. Luckily, feedback loops suppress variations to such a degree that linear projections approximate them fairly well. The linear slope of the exponential-like

Fig. 5.30 Linear projection of small-signal variation

wsO wsI

sO SO

so

si

SI

sI

5.5 Switched Inductor

287

response in Fig. 5.30, for example, can project small variations in the input signal sI to the output signal sO that are very close to sO’s actual variations. si represents small signals in sI that the slope (partial derivative) of sI at sI’s static point SI projects to small signals so in sO: so ¼ si A X  si

  ∂sO : ∂sI

ð5:80Þ

This linear projection is fairly close to the actual translation AX because si and so are small variations about SI and SO. The approximation loses accuracy when variations grow to become larger fractions of SI and SO. Nomenclature Lowercase variables with uppercase subscripts include small- and large-signal components. Uppercase variables with uppercase subscripts are the static steady-state components. And lowercase variables with lowercase subscripts are the dynamic small-signal components. When combined, SA and sa components complete the analog signal sA: sA ¼ SA þ ∂sA ¼ SA þ sa ,

ð5:81Þ

where ∂sA also refers to small variations in sA. B. Switched Response Switched inductors energize and drain with large volt-level energize and drain voltages vE and vD in alternating phases of a switching cycle. The resulting inductor voltage vL pulses volts and swings the inductor current iL across amp-level ramps. These variations in vL and iL are large signal. But when conditions settle, the power supply reaches a steady state that pulses vL and ripples iL to peaks and about averages that do not vary much over time. So cycles repeat and variations between cycles fade. This is the static periodic steady state of the switched inductor. When operating conditions vary, the controller uses the error it senses in the output to adjust the switching cycle by a small amount. This small variation in amplitude, duty cycle, or frequency is the dynamic manifestation of the feedback command. So cycle-to-cycle variations in vL and iL reflect small-signal translations across the switched inductor.

5.5.2

Small-Signal Model

The switched inductor is a network of switches that connects the transfer inductor LX in Fig. 5.31 to the input vIN, output vO, and ground. The digital input that adjusts

dE'

vL iL

LX

Switches

5 Frequency Response

Switches

288

de'

vO

is CG

i DO

de'

vo

ZDO

vs

vo

de'ALV

CG

de'ALI

ZDO

Fig. 5.31 Small-signal model of the switched inductor Fig. 5.32 Small-signal inductor-current variation in CCM

iL

I L(LO)

qd

vD / L

/L X

vE TE

te

i l(hi)

I L(HI)

qe

X

TD

Time

+ te t C = t SW

i l(lo) – te 2tSW

the connectivity of the network is the energize command dE'. dE' feeds logic that configures the switches so LX energizes when dE' is high. dE' is the fraction of the switching period tSW that energizes LX. This dE' in modern power supplies connects to the gates of complementary metal–oxide–semiconductor (CMOS) transistors. These gates are capacitive and largely insensitive to the behavior of the network. So dE' connects to gate capacitance CG and the smallsignal model that incorporates this CG excludes a feedback translation. Variations in dE' ultimately alter the duty-cycled current iDO that the network outputs. ZDO is the impedance that dO duty-cycles in the absence of dE' variations de'. ALI is the small-signal translation that projects small dE' variations de' to small iDO variations ido without vO variations vo. ALV is the unloaded voltage that ALI produces across ZDO, which is ALIZDO. A. Continuous Conduction LX in continuous-conduction mode (CCM) conducts continuously. This is because LX energizes and drains continuously across alternating energize and drain times tE and tD of tSW in Fig. 5.32. iL climbs when vE energizes LX and falls when vD drains LX. dE' in CCM is also the energize duty cycle dE because LX’s conduction time tC extends through tSW, so tE’s fraction of tC and tSW is the same. iL is also iDO in bucks because LX energizes and drains directly into vO. iDO in boosts and buck–boosts is a drain duty-cycle dD fraction of this iL because LX connects to vO only when LX drains. In other words, the output duty cycle dO is one for bucks and dD for boost-derived topologies, which duty-cycle LX into vO. So generally, iDO is a dO translation of iL: iDO ¼ iL dO ,

ð5:82Þ

where dO in boost-based power supplies in CCM is dD’s tD/tSW and tO/tSW and tO is the output conduction time that dO steers iL into vO.

5.5 Switched Inductor

289

Duty-Cycled Impedance ZDO is the output impedance of the switched inductor in the absence of dE' variations. More specifically, ZDO is the impedance into LX that results when tO and tSW are static and dO connects LX to vO. In this light, ZDO is the duty-cycled inductance LDO that loads vo across TSW with the energy LX draws across TO. This is equivalent to saying the energy ELO that LDO draws from vo across TSW is the energy ELX that LX extracts across TO. From this perspective, iLX is the current LX draws from vo across TO: a DO fraction of TSW, and ELX is the energy LX collects after iL reaches iLX: ELX



   2  2  2  1 1 vo vo DO 2 L i L ¼ ¼ ¼ T TSW 2 : 2 X LX 2 X LX O 2 LX

ð5:83Þ

iLO, on the other hand, is the current LDO draws from vo across TSW and ELO is the energy LDO collects after iL reaches iLO: ELO

  2  2  



 1 1 vo vo 1 2 L i L ¼ ¼ ¼ T T 2: 2 DO LO 2 DO LDO SW LDO SW 2

ð5:84Þ

But since ELO is the energy ELX loads (i. e., ELO and ELX equal), LDO is a reverse quadratic DO translation of LX: LX : DO 2

LDO ¼

ð5:85Þ

Although often negligible, RL also loads vo when LX connects to vO. Like with LX, RL loads vo across TO the power duty-cycled resistance RLO loads across TSW. Since RL’s PRL is a TO/TSW fraction of vo2/RL, RLO’s PRO is vo2/RLO, and PRO is the power RLO loads, RLO is a reverse DO translation of RL:  PRL ¼

vo 2 RL



TO TSW

PRO ¼

 ¼

vo 2 , RL =DO

ð5:86Þ

vo 2 , RLO

ð5:87Þ

RL : DO

ð5:88Þ

RLO ¼

This RLO is greater than RL when SDO duty-cycles LX into vO because RLO alternates between RL (a DO fraction of TSW) and infinity (across what remains of TSW). Gain When dE' rises in CCM, tE lengthens by the same amount tD shortens. vL is therefore positive (with vE) longer than vL is negative (with vD). This net rise in vL across LX increases iL. This is the Ohmic translation that ALI and ALV model.

290

5 Frequency Response

Generally, iL is an Ohmic ZL translation of vL. vL is in turn a dE fraction of vE and an inverting dD fraction of vD. But since dD in CCM is the fraction of tSW that excludes tE, iL is ultimately a dE translation of vE and vD into ZL: iL ¼

vL vE dE  vD dD vE dE  vD ð1  dE Þ ðvE þ vD ÞdE  vD ¼ ¼ ¼ : ZL ZL ZL ZL

ð5:89Þ

Under static conditions (when small variations fade), vE and vD fractions in vL cancel because dE is vD/(vE + vD). This is equivalent to saying vL averages zero and LX shorts at low fO. Dynamic (nonzero fO) adjustments to dE alter this vL. So de' produces a small vL variation vl that induces a corresponding small iL variation il. AL is the part of ALI that projects de' to il when small vO variations vo are absent. Since vIN is an independent voltage source, small vIN variations vin are zero. So vE and vD in AL’s projection ∂iL/∂dE' are static and il’s short-circuit component il' (when vo is zero) is
 

∂iL

il '
il

vo ¼0 ¼ de ' AL  de ' ∂dE


vo ¼0

 ¼ de '

 VE þ VD : ZL

ð5:90Þ

In boost-derived supplies, LX only delivers charge across tD. So of the ql that il' garners, id delivers the part that tD carries. When averaged across TSW and dutycycled across TO, this id approximates to a DO fraction of il'. Extending tE in boost-derived supplies also shortens tD (and tO) when tSW is constant. So vO loses charge qe to tE across tE’s small extension te in Fig. 5.32 when iL reaches iL(HI). This qe across tSW is a te current ie that ido loses: ie ¼

te iLðHIÞ te ILðHIÞ qe ¼  ¼ de ' ILðHIÞ , TSW TSW TSW

ð5:91Þ

where iL(HI)’s static component IL(HI) is much greater than iL(HI)’s dynamic counterpart il(hi). Bucks do not lose this ie because LX in bucks connects to vO also across tE. ALI translates de' to ido when disabling ZDO with zero vo. This short-circuit ido is a small-signal current source is. Since iL and dO in iDO both vary with dE, is carries two components:
 

∂iDO

is
ido

vo ¼0 ¼ de ' ALI ¼ de ' ∂dE
vo ¼0     

∂iL ∂dDO ¼ de ' DO þ ILðHIÞ

∂dE ∂dE vo ¼0 ¼ il ' DO  de ' ILðHIÞ ¼ id  ie :

ð5:92Þ

The first component is a DO fraction of il', which is the td current id that qd in Fig. 5.32 delivers. The second term is zero for bucks because dO is one and an

5.5 Switched Inductor

291

inverting de' fraction of iL at IL(HI) for boosts because dO is dD’s 1 – dE. This last component is the ie that is loses to tE, which is the qe lost by teIL(HI) across TSW. Luckily, id is much higher than ie at low fO because ZL in the il' that sets id is very low. il', however, falls with fO 20 dB per decade as ZL’s sLX climbs. Since ie is constant, is drops with il' until id falls below ie (past zDO): id ¼ il ' DO  de '

 

VE þ VD 

DO



V þV sLX fO E D 2πLX

 DO ILðHIÞ

R



'

LD
z
2πL DO  X

VE þVD 2πLX



DO 2 IO



 ie  de ' ILðHIÞ :

ð5:93Þ

This duty-cycled zero zDO is a reversal out-of-phase zero because is stops falling with the pL that sLX sets and ie inverts is. When the CCM current ripple ΔiL is a small fraction of iL(AVG), IL(HI) and IL(HI)DO near IL and IO’s ILDO. In this light, zDO surfaces when LX overcomes the equivalent load resistance RLD' that vL’s VE and VD, DO, and iO’s average IO set. Bucks do not exhibit this zDO because they do not lose ie. ALI’s translation to is is therefore a duty-cycled ZL Ohmic translation of VE and VD that il' sets and zDO inverts and reverses with increasing fO:
    is

VE þ VD s  ALI

DO 1  : 2πzDO ZL de ' vo ¼0

ð5:94Þ

ALV is the unloaded Ohmic translation that ALI feeds ZDO: ALV


     vs

ZL VE þ VD s

¼ ALI ZDO ¼ ALI  1 : 2πzDO DO de ' io ¼0 DO 2

ð5:95Þ

Part of this ZDO in ALI cancels the ZL and DO that translates de' to il' and il' to is. So ALV is a reverse DO translation of VE and VD that zDO inverts and increases with fO. ALV’s independence of ZL in ZDO indicates the switched inductor in CCM is more a voltage-sourced inductor than the current-sourced inductor ALI models. From this view point, the role of the switcher is to set a small-signal voltage source vs that drives and feeds an inductor LDO into vo. This vs is largely a DO translation of the VE and VD that the switcher applies to LX. The signal-flow graph in Fig. 5.33 is an insightful way of summarizing and visualizing these translations. This graph breaks and traces individual components to is. All translations are operation-based, from the behavior of vL and iL across tSW cycles. Fig. 5.33 Signal-flow graph of the switched inductor in CCM

de'

VE + VD ZL

pSW

–1

i l' do

DO

I L(HI)

is

ZL DO 2

vs

292

5 Frequency Response

This graph shows that dE' variations produce iL and dO variations that propagate to iDO (via is). ido’s short-circuit component is is in part a DO fraction of il', which is an Ohmic translation of de', and in part an inverting IL(HI) translation of de'. do inverts and keeps is from falling with il' when DO’s fraction of il' falls below do’s inverting translation. And vs is an Ohmic ZDO translation of is. But as mentioned earlier, the inverting bypass path that do feeds is is absent in bucks because vO receives all of il'. B. Discontinuous Conduction LX in discontinuous-conduction mode (DCM) conducts a fraction of tSW. This is because LX energizes and drains across tC before tSW in Fig. 5.34 ends. So iL climbs with vE, falls with vD, and flattens before and until another tSW cycle begins. Several observations are worth noting. First, dE and dD are tE and tD fractions of a tC that is shorter than tSW. So dE is not the tE/tSW that the input dE' commands. Second, LX energizes and depletes every cycle. So LX delivers all the charge it collects. This means is does not lose the ie that inverts and alters is in CCM. As a result, ALI and ALV in DCM exclude zDO. Third, extending tE in DCM extends tD when tSW is constant. This is because adding te raises iL(PK), and with it, the 0.5LXiL(PK)2 energy that LX collects. So LX requires more tD to drain. In fact, tD and tC scale proportionately with tE within tSW because the vE and vD that project iL are static. So the fraction of vE that de applies to LX cancels the fraction of vD that dd applies. This means that the resulting small-signal voltage vl across LX is zero: vl V d  VD dd ¼ E e ¼ 0: ZL ZL

ð5:96Þ

Losing sensitivity to fO this way removes inductive effects from ALI, ALV, and ZDO. Since vE and vD projections are static, variations in tE induce variations in tC that track TE and TC and the DE that TE and TC set: dE ¼

TE þ te TE te ¼ ¼ ¼ DE : TC þ tc TC tc

ð5:97Þ

So dE is static, which means de is zero. And te’s fraction of TE matches tc’s fraction of TC: Fig. 5.34 Small-signal inductor-current variation in DCM

TC iL 0

I L(PK)

/L X

TE

ql QL

vD /LX

vE

TD

Time

tc

te

i l(pk)

+ te t SW

≈ ql

+ td 2tSW

5.5 Switched Inductor

293

kd


ilðpkÞ te t ¼ c ¼ : TE TC ILðPKÞ

ð5:98Þ

These fractions (defined as kd here) also match il(pk)’s fraction of IL(PK) because vE and vD projections of iL are steady. Duty-Cycled Impedance ZDO is the output impedance of the switched inductor in the absence of dE' variations de'. So ZDO is the impedance into LX that results when tC and tSW are static and LX connects to vO a dO fraction of tC. Since ZDO is insensitive to fO (because LX’s vl is zero), ZDO is a duty-cycled resistance RDO that loads vo across TSW with the energy LX draws across DO’s fraction of TC. In this light, iLX is the current LX draws from vo across DO’s fraction of TC and ELX is the energy LX collects after iL reaches iLX: ELX

2  2   2 



   1 1 vo vo DO 2 L i L ¼ ¼ DO TC ¼ TC 2 : 2 X LX 2 X LX 2 LX

ð5:99Þ

This ELX is the power PRO that RDO burns across TSW: PRO ¼

vo 2 E ¼ LX ¼ RDO TSW



vo 2 2

 2  2  DO TC : LX TSW

ð5:100Þ

So RDO is a frequency-independent translation of LDO in CCM, TC, and TSW. RL’s duty-cycled translation raises this RDO, but usually not by much: 

RDO

LX ¼2 DO 2

    TSW RL TSW  2LDO þ : DO TC 2 TC 2

ð5:101Þ

Gain ALI translates de' to ido when disabling ZDO with zero vo. While iDO outputs all the charge qL that LX collects, ido delivers the part of qL that excludes the static component QL. Since iL ramps in straight lines, qL and QL are the areas (current into time) under the triangles that iL and IL outline. qL’s tC and iL(PK) are TC and IL(PK) plus corresponding kd fractions of TC and IL(PK) because tc and il(pk) scale with TC and IL(PK): qL ¼ 0:5tC iLðPKÞ ¼ 0:5TC ð1 þ kd ÞILðPKÞ ð1 þ kd Þ ql ¼ qL  QL ¼ 0:5TC ILðPKÞ ð1 þ kd Þ2  0:5TC ILðPKÞ

¼ 0:5TC ILðPKÞ kd 2 þ 2kd

ð5:102Þ

ð5:103Þ

 TC ILðPKÞ kd ¼ tc ILðPKÞ : Since kd is a small fraction and te/tc is DE, 2kd swamps kd2 and tc is te/DE. So ql is roughly the rectangular area that tc and IL(PK) outline and is is ql/TSW:

294

5 Frequency Response

Fig. 5.35 Signal-flow graph of the switched inductor in DCM

de'

IL(PK) DE

is

RDO

vs

pSW

is ¼ ido jvo ¼0 ¼

  tc ILðPKÞ te ILðPKÞ ILðPKÞ ql  ¼ ¼ de ' : TSW TSW DE TSW DE

ð5:104Þ

Like Fig. 5.35 shows, ALI is ultimately the IL(PK)/DE translation ql sets:
ILðPKÞ is

ALI

 : ' DE de vo ¼0

ð5:105Þ

And ALV is the unloaded Ohmic translation that ALI feeds ZDO’s RDO: ALV


  ILðPKÞ vs



¼ ALI ZDO ¼ ALI RDO  RDO : DE de ' io ¼0

ð5:106Þ

Still, the independence of ALI and RDO indicates a current-sourced resistor is a better model. Notice ALI, ALV, and RDO are all independent of fO. C. Switching Pole The switcher requires up to one switching cycle after tE ends to adjust the next tE. This adjustment in tE is the switcher’s response to variations in dE'. Even with multiple sub-cycle dE' variations, the switcher’s response is still one tE adjustment. This is like saying the switcher delays and masks (and suppresses) dE' variations that are faster than the switching frequency fSW that tSW sets. Since poles also delay and suppress higher-fO signals, a switching pole pSW can model this behavior. Although the delay and suppression are not necessarily linear or consistent, pSW is a useful, albeit imperfect, way of indicating the switcher filters higher-fO signals. Note this pSW affects the de' that feeds and propagates to il', do, is, and vs.

5.5.3

Power Stage

Switched inductors deliver vIN energy with iDO. Engineers add CO in Fig. 5.36 to voltage regulators and LED drivers to supply iO when dO disconnects LX from vO. In the case of chargers, CO is the effective capacitance of the battery, which is usually very high. RL and RC are the parasitic series resistances in LX and CO. iLD is the static part of the load and RLD is the part that responds to small vO variations vo. The small-signal gain to vO is critical in voltage regulators because the feedback loop regulates this vO. In LED drivers, iO is more important because the brightness

Fig. 5.36 Power stage

dE'

vL iL RL

LX

Switches

295

Switches

5.5 Switched Inductor

i DO

iO

vO RC

iLD

RLD

CO

R LO

de'ALV

RC

io R LD

CO

pLC

pLC 1/Z

' C 1/Z

pSW

L'

zDO zCP Log Freq. [Hz]

AVO/IO [dB]

L DO

vo ADO/IL [dB]

ido vs

Z C '/Z L ' Z C'/Z C '

zDO

pSW zC

Log Freq. [Hz]

Fig. 5.37 Small-signal model of the power stage in CCM

de'

VE + VD ZL

pSW

–1

i l' do

DO

is

ZL DO 2

vs

I L(HI)

AV AG

vo

1 RLD

io

ido

Fig. 5.38 Signal-flow graph of the power stage in CCM

and spectrum of the emitted light depend on the iO the LEDs receive. iDO is critical in chargers because iDO is what feeds the battery. iL is also important when systems control the iL that LX conducts. This is why small-signal dE' translations to vO, iO, iDO, and iL are relevant. A. Continuous Conduction Frequency Response The switched inductor in continuous conduction is a voltagesourced inductor. So the switcher in Fig. 5.36 sets a small-signal voltage vs in Fig. 5.37 that drives LDO and RLO into RLD and CO with RC. iLD is absent because iLD does not respond to small signals. Small dE' variations de' in Figs. 5.36, 5.37, and 5.38 feed and propagate to il', is, vs, ido and vo, and io. il' and is are the short-circuit components of il and ido that result when vo is zero. do bypasses il' and inverts is past zDO only in boost-derived topologies, when dO is a fraction of tSW.

296

5 Frequency Response

The gain ADO to ido incorporates ALV’s translation to vs and the voltage-sourced transconductance gain AG into the LC network to ido: ADO


    is vs ido ¼ ALV AG is vs il '    1  s=2πzDO VE þ VD ¼ AG : DO 1 þ s=2πpSW

ido ¼ de '



il ' de '

ð5:107Þ

Since il and ido scale with their short-circuit counterparts il' and is, the gain AIL to il is a reverse DO translation of ido without the zDO that dO induces: 
 
  
il

ido il '

1

¼ No zDO ¼ ADO

' i D ido
No zDO de s O No zDO    AG =DO VE þ VD ¼ : DO 1 þ s=2πpSW

i AIL
l ¼ de '



ido de '



ð5:108Þ AG is 1/[(RL/DO) + RLD)] when LX shorts and CO opens at low fO. AG climbs with the 1/ZC' that CO and RC set past zCP when CO and RC shunt RLD, peaks at fLC, and falls with the 1/ZL' that LDO and RLO set past the double pole pLC that fLC sets when ZL' surpasses ZC'. The gain AVO to vo is the gain ido sets into CO with RC and RLD. This gain incorporates ALV’s translation to vs and the voltage-sourced voltage gain AV across the LC network to vo: AVO


     vo i is vs vo ¼ l il is vs de ' de ' ¼ ADO ½ðZC þ RC ÞjjRLD ¼ ALV AG ½ðZC þ RC ÞjjRLD     ðZC þ RC ÞjjRLD 1  s=2πzDO VE þ VD AG ¼ ALV AV ¼ : DO 1 þ s=2πpSW ZLO þ RLO þ ½ðZC þ RC ÞjjRLD

ð5:109Þ And the gain AIO to io is an Ohmic RLD translation of AVO: AIO

i
o ¼ de '



vo de '

      io 1 1 ¼ AVO ¼ ALV AV : RLD RLD vo

ð5:110Þ

AV is close to one when LX shorts and CO opens at low fO and RLO is much lower than RLD. AV peaks at fLC, falls 40 dB per decade past the double pole pLC that fLC sets when LDO opens and CO shunts, and falls 20 dB per decade past zC when CO shorts. AG and AV behave this way when LX overcomes RL and CO and RC shunt RLD below fLC and CO shorts with respect to RC above fLC, which is often the case in power supplies. ALV to vs is largely a reverse DO translation of VE and VD. In ADO, AVO, and AIO, however, this ALV inverts and rises past zDO when do bypasses il. This out-of-phase zero zDO is absent in bucks because LX feeds vO all of il. In all cases, the switcher delays and suppresses at- and above-fSW signals.

5.5 Switched Inductor

297

Example 17: Determine ADO and AVO at low fO and related poles and zeros in CCM when vE is 2 V, vD is 4 V, dE is 67%, dO is 33%, iL(HI) is 190 mA, and tSW is 1 μs with the LX, RL, CO, RC, and RLD specified in Example 9. Solution:

ALV0 ¼ AG0 

VE þ VD 2 þ 4 ¼ 18 V=V ¼ 25 dB ¼ DO 33%

1 1 ¼ 10 mA=V ¼ 40 dB ¼ ðRL =DO Þ þ RLD ð50m=33%Þ þ 100 AV0 ¼ AG0 RLD  ð10mÞð100Þ ¼ 1 V=V ¼ 0 dB

ADO0 ¼ ALV0 AG0  ð18Þð10mÞ ¼ 180 mA=V ¼ 15 dB AVO0 ¼ ALV0 AV0  ð18Þð1Þ ¼ 18 V=V ¼ 25 dB f CP ¼ 320 Hz and zC ¼ 3:2 MHz from Example 9 LDO ¼ fL ¼

LX 10μ ¼ ¼ 92 μH DO 2 33%2

RL =DO 50m=33% ¼ ¼ 260 Hz 2πLDO 2πð92μÞ

1 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 7:4 kHz 2π LDO CO 2π ð92μÞð5μÞ       VE þ VD DO 2þ4 33% ¼ 170 kHz ¼ ¼ 2πLX ILðHIÞ 2πð10μÞ 190m f LC ¼

zDO

f SW ¼

1 1 ¼ 1 MHz ¼ tSW 1μ

f CP < f L < f LC < zDO < f SW < zC ∴

zCP  f CP < pLC ¼ f LC < zDO < pSW  f SW < zC

Note: zCP is absent in AVO and zC is absent in ADO because AV excludes zCP and AG excludes zC. zC is largely inconsequential because it appears above fSW.

298

5 Frequency Response

C PSW

v 1 AZDO

vo

vl vs

v2

vb

R PSW de'APSW

C ZDO

–vb

v1

va

L DO

R LO

v2 A SL

R ZDO R PX

RC

CO

R LD vc

Fig. 5.39 Duty-cycled CCM frequency-response model of the switched inductor

Circuit Model The circuit in Fig. 5.39 models the duty-cycled CCM response of the switched inductor. APSW buffers de' (with a gain of one) so CPSW can establish pSW in v1 when CPSW shunts RPSW into APSW. This way, APSW is 0 dB at low frequency and falls 20 dB per decade past pSW:
1

sCPSW
f O 

1 2πRPSW CPSW
pSW

 RPSW :

ð5:111Þ

AZDO buffers v1 into the voltage divider RZDO and RPX implement so CZDO can inject zDO into v2. AZDO recovers the gain lost across RZDO and RPX so the low-fO gain to v2 is one. This way, the overall low-fO gain from de' to v2 is also one: AZDO


RZDO þ RPX : RPX

ð5:112Þ

CZDO feeds an inverting (out-of-phase) vb signal that bypasses RZDO past zDO. RPX reverses this zDO past pZX when CZDO shorts with respect to RPX and RZDO into AZDO. Since this pZX is an artificial byproduct of the model, RPX should be low enough to push pZX over pSW, where its presence is largely inconsequential:
1

sCZDO
f O 
1

sCZDO
f O 

1 2πRZDO CZDO
zDO

 RZDO

1
pZX >pSW 2πðRZDO kRPX ÞCZDO

ð5:113Þ

 RZDO kRPX :

ð5:114Þ

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Switched Inductor: Duty-Cycled CCM Frequency-Response Model vde de 0 dc¼0 ac¼1 epsw va 0 de 0 1 (continued)

5.5 Switched Inductor

299

rpsw va v1 1 cpsw v1 0 159.2n ezdo vb 0 v1 0 1001 enzdo nvb 0 vb 0 -1 rzdo vb v2 1 czdo nvb v2 940n rpx v2 0 1m esl vs 0 v2 0 18 ldo vs vl 92u rlo vl vo 150m rc vo vc 10m co vc 0 5u rld vo 0 100 .ac dec 1000 10 10e6 .end Tip: Plot v(vs), i(Ldo), v(vo), and i(Rld) in dB to inspect ALV, ADO, AVO, and AIO.

Example 18: Determine AIL and AIO at low fO and related poles and zeros in CCM when vE and vD are 2 V, dE is 50%, dO is 100%, and iL(HI) is 130 mA with the LX, RL, CO, RC, tSW, and RLD specified in Example 17. Solution: f CP ¼ 320 Hz, f L ¼ 800 Hz, and zC ¼ 3:2 MHz from Example 9 f SW ¼ 1 MHz from Example 17 LDO ¼

LX L ¼ X2 ¼ LX ¼ 10 μH DO 2 1

∴

f LC ¼ 22 kHz from Example 9

ALV0 ¼ VE þ VD ¼ 2 þ 2 ¼ 4 V=V ¼ 12 dB RLO ¼

RL RL ¼ ¼ RL DO 1

300

5 Frequency Response

AG0 ¼

1 1 ¼ 10 mA=V ¼ 40 dB ¼ RL þ RLD 50m þ 100

AV0 ¼ AG0 RLD ¼ ð10mÞð100Þ ¼ 1 V=V ¼ 0 dB AIL0 ¼ ALV0 AG0 ¼ ð4Þð10mÞ ¼ 40 mA=V ¼ 28 dB AIO0 ¼

ALV0 AV0 ð4Þð1Þ ¼ 40 mA=V ¼ 28 dB ¼ 100 RLD

f L < f CP < f LC < f SW < zC

∴

zCP  f CP < pLC ¼ f LC < pSW  f SW < zC

Note: zDO is absent because do does not bypass il and AIL0 and AIO0 match because iL flows to RLD at low fO.

Explore with SPICE: Remove AZDO, CZDO, RZDO, and RPX from the model and feed v1 into ASL to exclude zDO from the response. See Appendix A for notes on SPICE simulations. * Switched Inductor: CCM Frequency-Response Model of the Buck vde de 0 dc¼0 ac¼1 epsw va 0 de 0 1 rpsw va v1 1 cpsw v1 0 159.2n esl vs 0 v1 0 4 lx vs vl 10u rl vl vo 50m rc vo vc 10m co vc 0 5u rld vo 0 100 .ac dec 1000 10 10e6 .end Tip: Plot v(vs), i(Lx), v(vo), and i(Rld) in dB to inspect ALV, ADO, AVO, and AIO.

vo

ido

RDO

RC

de'ALI

AVO/IO [dB]

is

301

io R LD

CO

pC

ADO/LI [dB]

5.5 Switched Inductor

pSW zC

Log Freq. [Hz]

pC

pSW

zCP

Log Freq. [Hz]

Fig. 5.40 Small-signal model of the power stage in DCM Fig. 5.41 Signal-flow graph of the power stage in CCM

de'

IL(PK) DE

is

RDO || RLD || Z C'

pSW

Fig. 5.42. DCM frequencyresponse model of the switched inductor

v1

va R PSW de'APSW

1 RLD R 1 LD | |Z C'

vo

io ido

vo is

C PSW v1ASL

RDO

RC

R LD

CO

B. Discontinuous Conduction Frequency Response The switched inductor in discontinuous conduction is a current-sourced resistor. So a short-circuit current is and RDO in Fig. 5.40 output a small-signal current ido into RLD and CO with RC. iLD is absent because iLD is static. dE' variations de' in Figs. 5.36, 5.41, and 5.42 propagate to is, vo, ido, and io. The gain to vo is ALI’s is into RDO, RLD, and CO with RC: AVO

  is vo ¼ ALI ½RDO kRLD kðZC þ RC Þ ' is de    ILðPKÞ RDO kRLD 1 þ sRC CO ¼ : DE 1 þ s=2πpSW 1 þ s½RC þ ðRDO kRLD Þ CO

v
o ¼ de '



ð5:115Þ

AVO is ALI’s IL(PK)/DE into RDO and RLD when CO opens at low fO. AVO falls past pC when CO and RC shunt RDO and RLD, zC reverses pC when CO shorts with respect to RC, and pSW accelerates AVO’s fall past fSW. ZC' in Fig. 5.41 is CO’s impedance with RC.

302

5 Frequency Response

The gain to io is an Ohmic RLD translation of AVO’s vo: AIO


  io vo   A ALI RDO 1 þ sRC CO ¼ VO ¼ : RLD RDO þ RLD 1 þ s½RC þ ðRDO kRLD Þ CO

io ¼ de '



vo de '

ð5:116Þ

AIO is a current-divided RDO/(RDO + RLD) fraction of ALI’s IL(PK)/DE when CO opens at low fO. Since AIO is just an Ohmic RLD translation of AVO, AIO includes AVO’s pC, zC, and pSW. The gain to il and ido is an Ohmic translation of AVO’s vo into RLD and CO with RC: ADO

i i
do ¼ l ¼ ' de de '



vo de '

  ido vo

AVO ¼ ¼ RLD kðZC þ RC Þ



ALI RDO RDO þ RLD



1 þ sðRC þ RLD ÞCO : 1 þ s½RC þ ðRDO kRLD Þ CO ð5:117Þ

ADO is a current-divided RDO/(RDO + RLD) fraction of ALI’s IL(PK)/DE when CO opens at low fO. ADO climbs with 1/ZC' past the zCP that fCP sets when CO and RC in ZC' shunt RLD and flattens with AVO’s pC when CO shorts with respect to RC and RDO with RLD. AVO’s pSW then reduces ADO past fSW.

Example 19: Determine AVO and ADO at low fO and related poles and zeros in DCM when dE and dO are 50%, tC is 570 ns, tSW is 1 μs, iL(PK) is 57 mA, and RLD is 500 Ω with the LX, RL, CO, and RC specified in Example 9. Solution: 

RDO

LX ¼2 DO 2

  

 TSW RL 10μ 1μ 50m ¼ 250 Ω ¼2 þ þ 2 2 2 D 50% 50% TC O 570n

ALI 

ILðPKÞ 57m ¼ 110 mA=V ¼ 19 dB ¼ DE 50%

5.5 Switched Inductor

303

AVO0 ¼ ALI ðRDO k RLD Þ ¼ ð110mÞð250 k 500Þ ¼ 18 V=V ¼ 25 dB ADO0 ¼ zCP ¼ pC ¼

AVO0 18 ¼ ¼ 36 mA=V ¼ 29 dB 500 RLD

1 1 ¼ 64 Hz ¼ 2πðRC þ RLD ÞCO 2πð10m þ 500Þð5μÞ

1 1 ¼ 190 Hz ¼ 2π½RC þ ðRDO kRLD Þ CO 2π½10m þ ð250k500Þ ð5μÞ pSW  f SW ¼ 1 MHz from Example 17 zC ¼ 3:2 MHz from Example 9

Note: ADO excludes zC. zCP is in ADO and absent in AVO because ADO is an Ohmic translation of AVO that CO and RC set.

Circuit Model The circuit in Fig. 5.42 models the DCM response of the switched inductor. APSW buffers de' so CPSW can establish pSW when CPSW shunts RPSW into APSW. APSW is one so the low-fO gain from de' to v1 is one. This way, pSW is the only effect of the buffer stage on the overall gain of the model. Explore with SPICE: See Appendix A for notes on SPICE simulations. * Switched Inductor: DCM Frequency-Response Model vde de 0 dc¼0 ac¼1 epsw va 0 de 0 1 rpsw va v1 1 cpsw v1 0 159.2n gsl 0 vs v1 0 110m rdo vs 0 250 vio vs vo dc¼0 rc vo vc 10m co vc 0 5u rld vo 0 500 .ac dec 1000 10 10e6 .end Tip: Plot i(Gis), i(Vio), v(vo), and i(Rld) in dB to inspect ALI, ADO, AVO, and AIO.

304

5.6

5 Frequency Response

Summary

Two-port models are two- to four-component networks that can model the behavior of almost any circuit. Their inputs and outputs are interdependent sources with impedances. These networks work because sources model what impedances do not. In other words, sources are the voltages or currents that result when the effects of impedances are absent and impedances are the Ohmic translations that result when disabling sources. This way, input–output combinations can model feedback and forward translations. Impedances can be resistive, capacitive, and inductive. Resistance is the part that does not scale with frequency. Capacitors and inductors are, in a way, like Ohmic switches. This is because capacitors close and inductors open as frequency increases. They also delay translations because capacitors and inductors require time to energize. So capacitor voltages and inductor currents lag the currents and voltages that drive them. Couple capacitors feed current and shunt capacitors pull current. And couple inductors impede current and shunt inductors avail current. Poles are the transitional frequencies that result when gain and the phase shift that delay produces in sinusoids fall. Zeros oppose these effects: they raise gain and recover phase by the same amount poles lose them. The effects that capacitors and inductors produce when they shunt and overcome resistances reverse when they short and open. So resistors that current-limit capacitors and voltage-limit inductors reverse the poles and zeros that capacitors and inductors produce. And bypass capacitors add zeros when they feed more current than the circuits they bypass. These zeros are out-of-phase when they invert translations. Poles and zeros in LC circuits hinge on the frequency where inductor impedance overcomes capacitor impedance. At this fLC, ZL and ZC are equal complements, so parallel LC networks open and series LC networks short (as much as their parallel and series resistors allow). This is how parallel and series combinations can peak their voltages and currents at fLC. But peaking results only when resistors do not keep inductors and capacitors from interacting at fLC. So to peak, capacitors should shunt parallel resistances, inductors should overcome series resistances, and capacitors should not short below fLC. If not, the peak fades and the double pole that produces the peak splits or reduces to one lower-frequency pole. Switched inductors in power supplies behave this way because they feed output capacitors that help supply a load. Although inductor voltage and current are largely nonlinear, variations across cycles are small, and in consequence, almost linear. Switched inductors respond and propagate small signals like LC networks for this reason. Switchers in continuous conduction duty-cycle energize and drain voltages across the inductor that feeds the output and its capacitor. The voltage-sourced LC networks that result normally peak at fLC because series resistances are usually low and load resistance is a few Ohms or higher. A zero reverses the pole that the output capacitor

5.6 Summary

305

induces when the capacitor shorts. And the switcher delays and suppresses sub-cycle variations that would otherwise generate signals above the switching frequency. Boost-derived switched inductors in continuous conduction add an out-of-phase zero. This is because their outputs receive current only when the inductor drains. Since extending energize time shortens drain time, raising inductor energy reduces drain current. This sacrifice eventually overcomes the gain because inductors carry less energy at higher frequencies (i.e., inductor impedance climbs with frequency). Switched inductors are less sensitive to frequency in discontinuous conduction. This is because energize and drain times scale together. So variations in one do not oppose the other (which is what causes the out-of-phase zero in the first place). And average inductor voltage is always the same (whose variation in continuous conduction is responsible for inductive effects). So in this mode, switched inductors are current-sourced resistors that output capacitors shunt and eventually short to produce a pole and a zero. Like in CCM, the switcher delays and suppresses signals that surpass the switching frequency.

6

Feedback Control

Abbreviations ADC CCM DCM DSP GBW GM LED LSB OA OTA PM PWM SL A0 Aβ ACL ADIG AE AF AFW AG ALG APRE APWM AS ASL AV

Analog–digital converter Continuous-conduction mode Discontinuous-conduction mode Digital-signal processor Gain–bandwidth product Gain margin Light-emitting diode Least-significant bit Operational amplifier/op amp Operational transconductance amplifier Phase margin Pulse-width modulator Switched inductor Zero-/low-frequency gain Feedback gain Closed-loop gain Digital gain Error amplifier/amp Overall forward gain Forward gain Transconductance gain Loop gain Pre-amplifier/pre-amp gain PWM gain Stabilizer gain Switched-inductor gain Amplifier voltage gain

# The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 G. A. Rincón-Mora, Switched Inductor Power IC Design, https://doi.org/10.1007/978-3-030-95899-2_6

307

308

βFB CX CO dO dE dE ' ΔiLD f0dB f180
fBW fBW(CL) fLC fO fSW iFB iI iL iLD iL(PK) iO is LDO NCLK NLSB pA pBW pC pL pO pPWM pSW QLC RC RDO RIN RL RLO RLD RO RS sE sI sO sFB

6

Feedback translation/scaler Parasitic capacitance Output capacitor Output duty cycle Energize duty cycle Energize duty-cycled command Load dump Unity-gain frequency Inversion frequency Bandwidth frequency Closed-loop bandwidth Transitional LC (resonant) frequency Operating frequency Switching frequency Feedback current Input current Inductor current Load current Peak inductor current in DCM Output current Small-signal current source Duty-cycled inductance in CCM Number of clock cycles Number of LSBs Amplifier pole Bandwidth-setting pole Capacitor pole Inductor pole Output pole PWM pole Switching pole LC quality factor Capacitor resistance Duty-cycled resistance in DCM Input resistance Inductor resistance Duty-cycled inductor resistance Load resistance Output resistance Series resistance Error signal Input signal Output signal Feedback signal

Feedback Control

6.1 Negative Feedback

309

While the underlying aim of power supplies is to transfer power, the more visible and distinguishable objective is conditioning it into a form that the load can use. In most cases, this amounts to setting and regulating the voltage or current with which the power supply delivers power. Voltage regulators, for example, set voltages and battery chargers and light-emitting diode (LED) drivers set currents. This responsibility of setting the output rests on the feedback controller. Its basic function is to adjust the switching action of the power supply so the output nears its target. This way, the controller counters the deviations that external factors (like load variations) would otherwise produce in the output. But when delayed, rather than correcting the error, adjustments can reinforce and amplify the error. Avoiding this is not so easy when considering the switched inductor (SL) already delays the response and circuits in the controller require time to react. So in addition to sensing and correcting fluctuations in the output, the feedback controller must also manage delays.

6.1

Negative Feedback

6.1.1

Model

Negative feedback sets and keeps the output from deviating. It does this by sensing and comparing the output against a reference input and using the error sensed to adjust the output. Sensing, comparing, and adjusting the output closes a feedback loop in Fig. 6.1 that couples the input to the output. Amplifying the error reduces deviations in the output. And translating the output before the comparison extends how far the output can reach. In other words, the efficacy and flexibility of the loop center on gain and translation. In all, feedback loops perform four basic functions: sense, translate, compare, and amplify. The sampler in Fig. 6.2 senses the output signal sO and the feedback scaler Fig. 6.1 Feedback actions

Amplify Input

Feedback Loop

Compare Fig. 6.2 Inverting feedback loop

Translate

Output Sense

Forward Gain Sampler

Mixer sE sI sFB

AFW

EFB

Feedback Translation

sO

310

6

Feedback Control

βFB translates sO to the feedback signal sFB. The mixer compares this sFB to the input signal sI and the forward gain AFW amplifies the error signal sE that results. So by definition, βFB and AFW are sFB sO

ð6:1Þ

sO sO ¼ : sE sI  sFB

ð6:2Þ

βFB  and AFW 

sI, sFB, and sE carry the same dimensional units because the mixer can only compare and output signals of the same nature. The loop gain ALG is the gain across the loop, which by definition, is also the gain from sE to sFB: ALG 

sFB sFB ¼ ¼ AFW βFB : sE sI  sFB

ð6:3Þ

The loop is inverting because sE inverts sFB fluctuations. This negative feedback action is what counters deviations in the output.

6.1.2

Translations

Since sE is the difference between sI and sFB and ALG translates sE to sFB, sE is ultimately a loop-gain fraction of sI: sE ¼ sI  sFB ¼ sI  sE AFW βFB ¼ sI  sE ALG ¼

sI : 1 þ ALG

ð6:4Þ

This means that sE is as low as ALG is high. And when ALG is much higher than one, sE is so low that sFB becomes a mirrored reflection of sI and sO a reverse βFB translation of this reflection: sI/βFB. But generally, sFB is sFB ¼ sE AFW βFB ¼ ðsI  sFB ÞALG ¼

sI ALG : 1 þ ALG

ð6:5Þ

Since sE is sI – sFB, AFW translates sE to sO, and βFB translates sO to sFB, sO is ultimately a loop-gain fraction of sIAFW: sO ¼ sE AFW ¼ ðsI  sFB ÞAFW sI AFW sA ¼ ðsI  sO βFB ÞAFW ¼ ¼ I FW : 1 þ AFW βFB 1 þ ALG So the closed-loop gain ACL from sI to sO is a loop-gain fraction of AFW:

ð6:6Þ

6.1 Negative Feedback

ACL 

311

sO AFW AFW 1 ¼ ¼ ¼ AFW jj : βFB sI 1 þ ALG 1 þ AFW βFB

ð6:7Þ

When ALG is much greater than one, AFW’s cancel and ACL reduces to 1/βFB. ACL is like the parallel combination of two forward translations: AFW and 1/βFB. Using this analogy, ACL follows the lowest forward translation. This is useful when determining the effects of feedback on ACL, which diminish as AFW falls and disappear when AFW drops below 1/βFB, which happens when ALG is less than one.

6.1.3

Frequency Response

Fig. 6.3 Closed-loop response with constant βFB

Gain [dB]

ACL follows the frequency response of the lowest forward translation. In Fig. 6.3, for example, ACL (the boundary of the gray region) follows AFW up to pX1 and past pX2 because AFW is lower than 1/βFB below pX1 and above pX2. ACL in Fig. 6.4 similarly follows AFW between pX1 and pX2 and past pX34. 1/βFB sets ACL otherwise. So zeros and poles in AFW are in ACL when AFW is lower. zFW1 and pFW4 in Fig. 6.3, for instance, are z1 and p3 in ACL. And zFW1 in Fig. 6.4 is z2 in ACL. Zeros and poles in βFB are poles and zeros in 1/βFB. In Fig. 6.4, pFB1 and pFB2 in βFB are zeros in 1/βFB and zFB1 in βFB is a pole in 1/βFB. Zeros and poles in 1/βFB are also in ACL when 1/βFB is lower than AFW. In Fig. 6.4, for example, pFB1 and pFB2 are zeros in 1/βFB that set z1 and z3 in ACL. Poles and zeros also appear or disappear at gain crossings. In Fig. 6.3, zFW1 disappears at pX1 and pFW3 appears at pX2. In Fig. 6.4, z1 disappears at pX1, z2 disappears at pX2, and z3 disappears and pFW2 appears at pX34. Reversing z3 and falling with pFW2 at pX34 produces a double pole in ACL. Each pole and zero raises and lowers gain by the same amount that frequency climbs: 10 or 20 dB for every 10 or decade rise in frequency. In other words, gain and frequency scale. pX1, for example, is (1/βFB)/AFW0 times greater than z1 in AFW

pFW1

1 EFB

pFW2

pFW3 1 + ALG

zFW2 pX1

z1 = z FW1

ACL

AFW0

pX2 p 3 = pFW4

Fig. 6.4 Closed-loop response with variable βFB

Gain [dB]

Log Frequency [Hz] 1 EFB zFB1

AFW pX1

pFW1

pX34

pX2 z3 = pFB2

z2 = z FW1 ACL z1 = pFB1 Log Frequency [Hz]

pFW2

312

6

Feedback Control

Fig. 6.3 and AFW0/(1/βFB0) times greater than z1 in Fig. 6.4, where “0” in subscripts refers to gain at low frequency. Similarly, ACL past pX2 in Fig. 6.4 is 1/βFB past zFB1, which is zFB1/pFB1 times greater than 1/βFB0. Like with gain, ACL’s phase follows the phase of the lowest forward translation. So ∠ACL in Figs. 6.3 and 6.4 climbs up to 90
with zFW1 in AFW and loses up to as much past pX1 in Fig. 6.3 and pX2 in Fig. 6.4 when 1/βFB begins to dominate ACL. ∠ACL in Fig. 6.4 also climbs up to 90
with the zero that pFB2 in βFB sets and loses up to as much plus up to another 90
past pX34 when pFW2 in AFW reduces ACL.

6.1.4

Stability

A. Gain Objective The principal aim of a feedback loop is to set an sO that is a reverse βFB translation of sI’s mirrored reflection. For ACL to follow this translation, 1/βFB should be lower than AFW. But since gain is another goal, this 1/βFB should be one or greater. So in practice, AFW is usually higher than 1/βFB across frequencies of interest and βFB is lower than or equal to one. B. Stability Criterion High ALG is desirable in feedback systems because amplifying sE reduces the mismatch between sI and sFB. Translating sO to sFB, comparing sFB to sI, and amplifying the resulting sE so this ALG is high and sO is accurate usually requires two or more stages in the loop. Since each stage incorporates one or more poles, finding two or more poles in ALG is not uncommon. In Fig. 6.5, just to cite an example, ALG’s zero- or low-frequency gain ALG0 is well over 1 or 0 dB. ALG falls 20 dB per decade past p1 and another 20 dB per decade past p2. ALG crosses 0 dB at a unity-gain frequency f0dB that is much higher than p1 and p2. Since each pole loses up to 90
of phase shift, ∠ALG reaches 180
(at the inversion frequency f180
) before ALG crosses 0 dB. Since ALG inverts with 180
past f180
and this inversion happens below f0dB, ALG at f0dB is 1. With this much phase shift, positive feedback peaks ACL at f0dB towards infinity:

Fig. 6.5 Unstable loop-gain response

Fig. 6.6 Closed-loop response

313

ACL [dB]

6.1 Negative Feedback

0 dB

90o > PM 1 > PM 2 ACL0 ≈ E1 FB

PM 2 PM 1

PM 0 = 90 o Log Frequency [Hz] fBW(CL) = f0dB

–3 dB

Fig. 6.7 Stable loop-gain response

ACL


1 AFW

A ¼ AFW jj ¼ ¼ FW ! 1: βFB 1 þ ALG
ALG ¼1∠180
1  1

ð6:8Þ

To limit this peak, ALG should reach f0dB with less than 180
of phase shift. In other words, ALG should reach f0dB before f180
. This is the stability criterion. So ACL follows 1/βFB in Fig. 6.6 and peaks at f0dB to the extent that ∠ALG allows. The peak diminishes when the guard-band of unused phase-shift allowance, which is known as phase margin (PM), increases: PM ¼ 180
þ ∠ALGð0dBÞ > 0
:

ð6:9Þ

The peak fades when this PM is 90
, which happens when p2 is absent. Without p2, p1 produces the effect of a typical pole in ACL at f0dB. f0dB in ALG is a gain crossing in AFW || 1/βFB, where the effects of p1 in AFW appear in ACL when AFW falls below 1/βFB. So this f0dB sets ACL’s closed-loop bandwidth fBW(CL). And ACL is stable (with a finite peak) when this f0dB in Fig. 6.7 precedes f180
. ALG at f180
should therefore be less than 1 or 0 dB. The guard-band this gain sets, known as gain margin (GM), is another measure of stability: GM ¼ 0 dB  ALGð180
Þ > 0 dB:

ð6:10Þ

C. Stabilization ACL is stable when ALG crosses 0 dB with less than 180
of phase shift, like Fig. 6.7 shows. Feedback stability is largely independent of what happens well below f0dB. So ALG can incorporate any combination of poles and zeros that keep ∠ALG from reaching 180
at f0dB.

6

Fig. 6.8 Single-pole response

AX [dB]

314

pBW

Feedback Control

AX0 –20d B/de c.

f0dB

0 dB

Log Frequency [Hz]

Even if ∠ALG dips to 180
before reaching f0dB, ACL remains stable as long as ∠ALG recovers PM at f0dB. Engineers, however, normally keep ∠ALG from ever reaching 180
to keep the power-up process from creating and latching the system to an unstable condition. Because as the system powers, ALG0 rises and shifts f0dB across frequencies that precede the targeted steady-state f0dB. Stabilization starts by setting one dominant low-frequency pole p1. Letting a second pole p2 land at f0dB is not uncommon. This way, ∠ALG loses 90
to p1 and another 45
to p2 at f0dB, leaving 45
of PM. In-phase (left-hand-plane) zeros should accompany any intermediate poles to ensure their combined contributions keep PM above 25
–30
. Out-of-phase (right-half-plane) zeros should be ten times or more than ten times greater than f0dB. This is because they invert and add gain. So they not only subtract phase but also extend f0dB to higher frequency, where parasitic poles can deduct more phase. D. Gain–Bandwidth Product Gain AX falls 20 dB per decade towards 0 dB like Fig. 6.8 shows when AX incorporates one pole. The gain–bandwidth product (GBW) is AX’s low-frequency gain AX0 times this bandwidth-setting pole pBW: GBW  AX0 pBW  AX f BW jf BW pBW ¼ f 0dB ¼ Constant:

ð6:11Þ

Since AX drops as much as operating frequency fO climbs past pBW, GBW is also the product of AX and the bandwidth frequency fBW that fO sets past pBW, which as a result, is also f0dB at 0 dB. This means that AXfBW past pBW is not only constant but also f0dB. Projecting f0dB this way: from the GBW that one pole sets, is useful when predicting and managing frequency response.

6.1.5

Loop Variations

A. Pre-amplifier Amplifying the input of a feedback loop is equivalent to amplifying all forward translations. This is because a pre-amplifier APRE, or pre-amp for short, amplifies the forward translation that dominates:

6.1 Negative Feedback

315

Fig. 6.9 Pre-amplified feedback loop

sI

APRE EFB

Fig. 6.10 Feedback loop with multiple inputs and outputs

AFW Feedback Loop

sO(M)

sI1

sI2

Feedback Loop

AFW1

AFWN EFB1

sO

...

sI

sO1

sI(N)

...

sO2 Fig. 6.11 Feedback loop with parallel paths

sO

EFBM

  sO 1 A AX  ¼ APRE AFW jj ¼ ðAPRE AFW Þjj PRE  AF jjAβ : βFB sI βFB

ð6:12Þ

So the overall gain in Fig. 6.9 follows the pre-amplified lowest forward translation to sO: the pre-amplified overall forward gain AF that APREAFW sets or the pre-amplified feedback gain Aβ that APRE/βFB sets. B. Multiple Taps A feedback loop can mix and sample multiple inputs and outputs. Since the loop is linear near its operating point, loop signals superimpose linear translations of the inputs. So an output in Fig. 6.10, which can be any signal in the loop, is the sum of individual closed-loop translations to that point: sOðXÞ ¼

N X K¼1

sIðKÞ ACLðKÞ ¼

N X K¼1

 sIðKÞ AFWðKÞ jj

1 βFBðKÞ

 :

ð6:13Þ

Each output is ultimately a unique closed-loop translation of each input. C. Parallel Paths Parallel paths in Fig. 6.11 can also amplify the error and translate the output. In these cases, the mixer and sampler add parallel AFW’s and βFB’s. This way, the highest-gain paths can dominate and set ACL, and individual paths win dominance when their gains overwhelm the others:

316

6

Fig. 6.12 Feedback loop with embedded loops

sI

ACL ¼ ΣAFWðXÞ jj

1 ΣβFBðXÞ

   Max AFWðXÞ jj

A1 EM

Feedback Control

... ...

1 n o: Max βFBðXÞ

AN E1

sO

ð6:14Þ

The frequency response of each parallel path dictates which translation dominates which frequency range. In practice, one path can set the low-frequency range and another the high-frequency range. This way, one sets the static translation and the other one sets f0dB (i.e., bandwidth and stability criterion). D. Embedded Loops A feedback loop often embeds inner loops. The closed-loop translations of these embedded loops determine AFW, βFB, and as a result, ALG. Inner loops in the forward path (in Fig. 6.12) set AFW and inner loops in the feedback path set βFB: ACL ¼ AFW jj

1 1 ¼ ΠN : X¼1 AX jj M βFB ΠX¼1 βX

ð6:15Þ

Designing feedback systems with embedded loops is usually a recursive process that starts with the outer loop. Determining ALG and βFB requirements for the outer loop is the first step. Setting and stabilizing individual inner loops is next. This way, with bandwidth-limited closed-loop translations of the inner loops in hand, formulating AFW and βFB and stabilizing ALG is more straightforward.

6.2

Op-Amp Translations

6.2.1

Operational Amplifier

The operational amplifier (OA) in Fig. 6.13, or op amp for short, is useful in feedback systems because it can sense, amplify, and translate voltages. Its basic function is to amplify the difference between two input voltages, which is commonly known as the differential input voltage vID. Two other important features are high input resistance RIN and low output resistance RO. RIN is so much higher than other resistances that almost no current flows into the op amp. And RO is so much lower than other resistances that RO drops negligibly

6.2 Op-Amp Translations Fig. 6.13 Operational amplifier

317

vP

vP

vO

AV

vN

RIN

vO

RO

(vP – vN )AV

Fig. 6.14 Operational transconductance amplifier

vO

vP

RIN

AG

vN

vP

iO

vN

(vP – vN )AG

vN

vO iO RO

low voltages. This way, RIN does not load the input and the gain to the output voltage vO is insensitive to loads that connect to the output. The amplifier voltage gain AV amplifies the vID between the positive and negative inputs vP and vN. AV is normally constant up to the amplifier pole pA. Past this pA, AV falls 20 dB per decade of frequency: AV 

vO AV0  , vP  vN 1 þ s=2πpA

ð6:16Þ

where AV0 is AV’s low-frequency gain. Zeros and other poles, if any, are so high, by design, that they do not affect frequencies of interest.

6.2.2

Operational Transconductance Amplifier

The operational transconductance amplifier (OTA) in Fig. 6.14 is basically an op amp with high RO. RO is so much higher than other resistances that the OTA is practically a current source. So the gain to the output current iO is largely the transconductance gain AG that amplifies vP minus vN: AG 

iO  AG0 : vP  vN

ð6:17Þ

This AG in OTAs is, also by design, largely independent of frequency. So AG excludes the pA that reduces AV in op amps. Still, parasitic capacitance CX across the load resistance RLD at vO reduces the gain to vO past the output pole pO that CX sets when CX shunts RO and RLD:
1

sCX
f O 

1 ¼pO 2πR 1 C 2πðRO jjRLD ÞCX LD X

 RO jjRLD  RLD :

ð6:18Þ

318

6

Fig. 6.15 Non-inverting (voltage-mixed) op amp

vIN R1

6.2.3

Feedback Control

vO

AV

vFB

R2

Feedback Translations

A. Non-inverting Op Amp R2 in Fig. 6.15 closes an inverting feedback loop around the op amp. R2 with R1 sample and translate vO to the feedback voltage vFB that feeds the op amp. This way, AV mixes the input voltage vIN and vFB. AFW is nearly AV because AV amplifies the error voltage vE between vIN and vFB to vO and AV’s RO is very low: AFW 

vO vO AV0 ¼  AV ¼ : vE vIN  vFB 1 þ s=2πpA

ð6:19Þ

Since AV’s RIN is very high, βFB is the vO fraction that R2 sets across R1: βFB 

vFB R1  : vO R1 þ R2

ð6:20Þ

So ALG is AFWβFB and ALG reaches 0 dB at ALG0pA or AFW0βFBpA:  ALG ¼ AFW βFB 

AV0 1 þ s=2πpA



R1 R1 þ R2

 f 0dB  ALG0 pA ¼ AFW0 βFB pA  AV0



 R1 p : R1 þ R2 A

ð6:21Þ ð6:22Þ

And the voltage gain AVO to vO is ACL’s AV0 || 1/βFB up to f0dB: AVO 

vO 1 ¼ AFW jj  βFB vIN

   R þ R2 1 AV0 jj 1 : R1 1 þ s=2πf 0dB

ð6:23Þ

This AVO reduces to 1/βFB’s (R1 + R2)/R1 up to f0dB when AFW’s AV0 is much greater than 1/βFB.

Example 1: Determine AFW0, βFB, ALG0, f0dB, AVO0, and fBW(CL) when AV0 is 100 V/V, pA is 10 kHz, R1 is 10 kΩ, and R2 is 90 kΩ.

6.2 Op-Amp Translations

319

Solution: AFW0  AV0 ¼ 100 V=V ¼ 40 dB βFB 

R1 10k ¼ 100 mV=V ¼ 20 dB ¼ R1 þ R2 10k þ 90k

ALG0 ¼ AFW0 βFB  ð100Þð100mÞ ¼ 10 V=V ¼ 20 dB f 0dB  ALG0 pA  ð10Þð10kÞ ¼ 100 kHz AVO0 ¼ AFW0 jj

1 1 ¼ 100jj ¼ 9:1 V=V ¼ 19 dB βFB 100m

f BWðCLÞ ¼ f 0dB  100 kHz Note: AVO0’s 9.1 V/V is slightly lower than 1/βFB’s 10 V/V because AFW0’s AV0 is only ten times greater than 1/βFB.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Non-inverting Op Amp vi vi 0 dc¼0 ac¼1 eav0 va 0 vi vn 100 rpa va vb 1 cpa vb 0 15.92u eavo vo 0 vb 0 1 r1 0 vn 10k r2 vn vo 90k .ac dec 1000 1k 10e6 .end Tip: Plot v(vo) in dB to inspect AVO. B. Inverting Op Amp R2 in Figs. 6.15 and 6.16 close the same inverting feedback loop around the op amp. In Fig. 6.16, however, AV’s inputs do not mix vIN and vN. In this case, R1 translates vIN into an input current iI, R2 samples and translates vO into a feedback current iFB, and vN mixes iI and iFB.

320

6

Fig. 6.16 Inverting (currentmixed) op amp

Feedback Control

R1

vIN

iI

R2 vN

Fig. 6.17 Inverting (currentmixed) op-amp model

vIN R1 iI R1

iFB

vO AV

vN iFB

iN2

vO R2

Fig. 6.18 Approximate inverting (current-mixed) op-amp model

vO

AV

R1

AV

vN iFB vO R2

R2

vN R2

R2

vIN R1 iI

iO2

vO

iN2 R2

To visualize and quantify how vN mixes iI and iFB, consider R1’s and R2’s two-port models in Fig. 6.17. iI–R1 and iN2–R2 are Norton translations of vIN–R1 and vO–R2 where iI and iN2 feed vIN/R1 and vO/R2 when a grounded vN disables R1 and R2. iO2–R2 is a Norton translation of vN–R2 where iO2 feeds vN/R2 when a grounded vO disables R2. vN is therefore the voltage that iI and iN2 drop across R1 and R2. But since iN2 is an inverted feedback translation of vO, vN is an Ohmic reflection of iI minus iFB. This is how vN mixes iI and iFB. When AV’s RO is much lower than R2, RO sets the parallel resistance that RO and R2 establish at vO. When AV’s equivalent current source vIDAV/RO, which reduces to –vNAV/RO in Fig. 6.17, is similarly much greater than iO2’s vN/R2, AV sets the combined gain that AV and R2 establish. In other words, the effects of R2 on vO are negligible when AV is a good op amp. In these cases, the simplified model in Fig. 6.18 is a good approximation. Since RIN is very high and RO is very low in AV, AFW is the Ohmic and inverting translations that R1 and R2 establish at vN and AV sets across the op amp: AFW 

ðR jjR ÞA vO vO ¼  ðR1 jjR2 ÞðAV Þ ¼  1 2 V0 : iE iI  iFB 1 þ s=2πpA

βFB is an inverting reflection of the iN2 that vO into R2 sets:

ð6:24Þ

6.2 Op-Amp Translations

321

βFB 

iFB i 1 ¼  N2 ¼  : R2 vO vO

ð6:25Þ

So ALG is AFWβFB and ALG reaches 0 dB at ALG0pA or AFW0βFBpA: ALG ¼ AFW βFB       ð6:26Þ ðR1 jjR2 ÞAV0 1 R1 AV0 ¼   ¼ R2 R1 þ R2 1 þ s=2πpA 1 þ s=2πpA     R1 jjR2 R1 f 0dB  ALG0 pA ¼ AFW0 βFB pA  AV0 pA ¼ AV0 pA : ð6:27Þ R2 R1 þ R2 And AVO is 1/R1’s iI translation of vIN times ACL’s translation AFW0 || 1/βFB of iI up to f0dB: AVO

  1 AFW jj βFB    R2 AV0 R2 1 ¼ AF jjAβ   jj  : R1 þ R2 R1 1 þ s=2πf 0dB

v  O ¼ vIN



iI vIN

ð6:28Þ

AVO follows the lowest forward translation to vO. AF is the voltage-divided fraction that R1 sets into R2 times –AV and Aβ is an Ohmic R1 translation into 1/βFB’s –R2. So when AVR2/(R1 + R2) in AF is greater than R2/R1 in Aβ, AVO follows Aβ’s –R2/R1 up to f0dB.

Example 2: Determine AFW0, βFB, ALG0, f0dB, AVO0, and fBW(CL) with the AV0, pA, R1, and R2 specified in Example 1. Solution: AFW0  ðR1 jj R2 ÞAV0 ¼ ð10k jj 90kÞð100Þ ¼ 900 kV=A ¼ 120 dB βFB ¼ 

1 1 ¼ 11 μA=V ¼ 99 dB ¼ R2 90k

ALG0 ¼ AFW0 βFB  ð900kÞð11μÞ ¼ 9:9 ¼ 20 dB f BWðCLÞ ¼ f 0dB  ALG0 pA  ð9:9Þð10kÞ ¼ 99 kHz

322

6

Feedback Control

R2 AV0 R jj  2 R1 þ R2 R1 ð90kÞð100Þ 90k jj  ¼ ¼ 90jj 9 ¼ 8:2 V=V ¼ 18 dB 10k þ 90k 10k

AVO0 ¼ 

Note: Round-off errors reduce ALG0 and f0dB to 9.9 and 99 kHz. Without these errors, ALG0 and f0dB would be 10 and 100 kHz.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Inverting Op Amp vi vi 0 dc¼0 ac¼1 r1 vi vn 10k eav0 va 0 0 vn 100 rpa va vb 1 cpa vb 0 15.92u eavo vo 0 vb 0 1 r2 vn vo 90k .ac dec 1000 1k 10e6 .end Tip: Plot v(vo) in dB to inspect AVO. C. Differential Op Amp The op amp in Fig. 6.19 translates voltage- and current-mixed inputs into one vO. Since AV mixes vI with vFB and vFB mixes iI with iFB, vFB matches vI and iFB matches iI to the extent ALG determines. And vO superimposes voltage- and currentmixed forward translations of vIN1 and vIN2:



vO ¼ vIN1 AF1 jjAβ1 þ vIN2 AF2 jjAβ2 :

ð6:29Þ

AF1 translates vIN1 to vI and vI – vFB to vO in the absence of vIN2 and AF2 translates vIN2 to iI and iI – iFB to vO in the absence of vIN1:

6.2 Op-Amp Translations

323

Fig. 6.19 Differential op amp

vIN1 R1 R1

R2 vI

AV

vIN2 iI

R2 vFB

 AF1 ¼  AF2 ¼

iI

vI vIN1

vO

iFB




 
vO R2
 AV vI  vFB
vIN2 ¼0 R1 þ R2



vIN2


 
vO R2
 ðAV Þ ¼ AF1 : iI  iFB
vIN1 ¼0 R1 þ R2

ð6:30Þ ð6:31Þ

Aβ1 translates vIN1 to vI and vI to vO in the absence of vIN2 and Aβ2 translates vIN2 to iI and iI to vO in the absence of vI1. So Aβ1’s 1/β1 and Aβ2’s 1/β2 are  
  
vI vO

vI 1

¼ βFB1
v ¼0 vIN1 vI
vIN2 ¼0 vIN1 IN2 ð6:32Þ    R2 R1 þ R2 R2 ¼ ¼ R1 þ R2 R1 R1   
  
  1 iI vO

iI 1

1 ¼ ¼ ¼ ¼ ðR2 Þ ¼ Aβ1 : β2 βFB2
v ¼0 R1 vIN2 iI
vIN1 ¼0 vIN2 Aβ1 ¼

Aβ2

1 ¼ β1



IN1

ð6:33Þ Since AF2 and Aβ2 are mirrored inversions of AF1 and Aβ1, the differential gain to vO balances and matches vIN1’s forward translations: AVO 

vO RA R ¼ AF1 jjAβ1  2 V jj 2 : vIN1  vIN2 R1 þ R2 R1

ð6:34Þ

When Aβ1’s R2/R1 is much lower than AF1’s low-frequency gain, AVO follows Aβ1 until pA in AV reduces AF1 below Aβ1:  

R2 AV0
R1 þ R2 1 þ s=2πpA
f O >pA
   
pA

R2 R   Aβ1 ¼ 2 ,  A 1 R1 þ R2 V0 f O

f O AV0 R RþR R1 pA ¼f 0dB 1 2 

AF1 

ð6:35Þ

where the “s” term overwhelms 1 above pA. In other words, AVO is nearly R2/R1 up to the f0dB of the feedback loop that R2 closes.

324

6

Feedback Control

D. Tradeoffs Interestingly, but not surprisingly, ALG and f0dB are the same for all op-amp configurations. This is because R2 closes the same feedback loop. Their voltage gains to vO, however, are not all the same. The forward current-mixed translations to vO (AF and Aβ) are lower in magnitude than their voltage-mixed counterparts. So for the same bandwidth, the voltage-mixed AVO amplifies more than the current-mixed AVO. Or for the same gain, the voltagemixed AVO amplifies to a higher f0dB than the current-mixed AVO. But when inverting is necessary or convenient, or a differential translation is desirable, the sacrifice may be acceptable. For equal and opposite gains to vO, for example, the voltage divider that feeds the voltage-mixed input of the multi-mixed op amp reduces the voltage-mixed gain AVO. This way, the differential gain to vO balances and matches the lower current-mixed gain AVO.

6.3

Stabilizers

Feedback systems are stable when their loop gains reach 0 dB with less than 180
of phase shift. When needed, stabilizers add poles and zeros to ensure this happens. Although not always generalized this way, stabilizers normally adopt one of three basic strategies: Type I, II, or III.

6.3.1

Strategies

A. Type I: Dominant Pole

Fig. 6.20 Dominant-pole stabilization

Gain [dB]

Type I adds one low-frequency pole pS1 that alone reduces ALG in Fig. 6.20 to 0 dB. This way, after losing 90
of phase to pS1, ALG reaches f0dB with 90
of phase margin. Even with a second pole pS2 at f0dB, which loses another 45
at f0dB, the margin reduces to 45
, which is still stable. The stabilizer gain AS is the part of ALG that adds pS1. Since no other pole or zero alters ALG below f0dB, ALG drops with AS past pS1. And if AS includes pS2, ALG falls faster with AS past this pS2. Although often off by a constant gain factor, ALG with Type I stabilization usually follows AS up to at least f0dB.

ALG

pS1 AS

Log Frequency [Hz]

f0dB pS2

0 dB

6.3 Stabilizers

325

B. Type II: Pole–Zero Pair Type II adds pS1 and a zero zS1 that recovers the phase an intermediate pole p1 in ALG loses. This way, ALG in Fig. 6.21 loses 180
of phase to pS1 and p1, recovers 90
with zS1, and reaches f0dB with 90
of margin. Even with the loss of another pole pS2 at f0dB, the margin is still 45
, which is stable. AS is the part of ALG that adds pS1 and zS1. zS1 should be within a decade of p1 to keep ALG from shifting 180
. Although often off by a constant gain factor, ALG with Type II stabilization usually follows AS up to p1. Past p1 and zS1, ALG falls and AS flattens. And if AS includes pS2, ALG falls faster than AS past this pS2. C. Type III: Pole–Zero–Zero Triplet

Fig. 6.21 Pole–zero stabilization

Gain [dB]

Type III adds pS1 and two zeros zS1 and zS2 that recover the phase two intermediate poles p1 and p2 in ALG lose. This way, ALG in Fig. 6.22 loses 270
of phase to pS1, p1, and p2 and recovers 180
with zS1 and zS2, reaching f0dB with 90
of margin. Even with the loss of another pole pS2 at f0dB, the margin is still 45
, which is stable. Additional poles in AS should be a decade or more higher than f0dB to keep phase margin near 40
. AS is the part of ALG that adds pS1, zS1, and zS2. zS1 and zS2 should be above pS1 to let pS1 reduce ALG, but within a decade of p1 and p2 to keep phase from shifting 180
. This way, ALG follows AS up to p1 and continues to fall after zS1 and zS2 in AS counter the effects of p1 and p2 in ALG. Parasitic poles in AS eventually limit AS’s bandwidth. So after zS1 and zS2, AS flattens with pS2 and falls with pS3. Although pS2 and pS3 are not always apart, only one of these poles can be close to f0dB to keep PM from dipping below 30
–40
.

ALG

p1

pS1

f0dB

zS1

AS

0 dB

Fig. 6.22 Pole–zero–zero stabilization

Gain [dB]

Log Frequency [Hz]

ALG AS

p1 pS1

zS1

p2 zS2

Log Frequency [Hz]

pS2

f0dB 0 dB

pS2

pS3

326

6

Fig. 6.23 Dominant-pole and pole–zero OTAs

vIN

vIN

vO AG RF

6.3.2

Feedback Control

vO AG

RC RF

CF

CX

CF

Amplifier Translations

An op amp can add pS1. This op amp, however, cannot be any op amp. This is because the low-frequency gain AS0 and pS1 that AV0 and pA set should establish an f0dB that keeps the feedback system stable: AS 

AV0 : 1 þ s=2πpA

ð6:36Þ

The OTAs in Fig. 6.23 can also add pS1. AS0 is the gain that AG sets across RF. In the first implementation, AS falls past pF when CF shunts RF:  AS  AG

1 RF jj sCF

 ¼

AG RF AG RF ¼ : 1 þ sRF CF 1 þ s=2πpF

ð6:37Þ

Current-limiting CF with RC adds zS1. With RC, AS falls past pC when CF and RC shunt RF before parasitic capacitance CX at vO shunts RF. pC eventually fades past zCX when RC current-limits CF. Once CF shorts, AS flattens to AG(RF || RC) and later falls past pO when CX shunts RF and RC: AS ¼ AG ½RF jjðZF þ RC ÞjjZX ¼

AG RF ð1 þ sCF RC Þ s2 RC CF RF CX þ s½ðRF þ RC ÞCF þ RF CX þ 1



AG RF ð1 þ sRC CF Þ ½1 þ sðRC þ RF ÞCF ½1 þ sðRF kRC ÞCX

¼

AG RF ð1 þ s=2πzCX Þ : ð1 þ s=2πpC Þð1 þ s=2πpO Þ

ð6:38Þ

This way, AGRF sets AS0, pC sets pS1, zCX sets zS1, and pO sets pS2. Bypassing the R1 that feeds AG in Fig. 6.24 adds zS2. Here, AS0 voltage-divides with R1 and R2 and amplifies with AG and RF. zB raises AS when CB bypasses R1 and pBX reverses zB when the parallel resistance R1 and R2 set current-limits CB:

6.3 Stabilizers

327

Fig. 6.24 Pole–zero–zero OTA

vP

vO

CB vIN

AG

RC RF

R1 R2

CX

CF



 R2 A ½R jjðZC þ RC ÞjjZX ðR1 jjZB Þ þ R2 G F    ð1 þ R1 CB sÞð1 þ s=2πzCX Þ R2 AG RF ¼ R1 þ R2 ½1 þ ðR1 jjR2 ÞCB s ð1 þ s=2πpC Þð1 þ s=2πpO Þ    ð1 þ s=2πzB Þð1 þ s=2πzCX Þ R2 AG RF ¼ : R1 þ R2 ð1 þ s=2πpBX Þð1 þ s=2πpC Þð1 þ s=2πpO Þ



AS

ð6:39Þ

This way, pS1 is pC, zS1 and zS2 are zCX and zB, pS2 is pBX, and pS3 is pO.

Example 3: Determine R2, CB, AG, CF, RC, and CX so AS0 is 40 V/V, pS1 is 1 kHz, zS1 and zS2 are 10 kHz, pS2 exceeds 100 kHz, and pS3 matches or exceeds 1 MHz when R1 and RF are 500 kΩ. Solution: pS1  pC < zS1  zCX ¼ zS2  zB < pS2  pBX < pS3 ¼ pO zS1 zCX RC þ RF RC þ 500k 10 kHz   ¼  RC 1 kHz pS1 pC RC pS2 pBX R1 500k 100 kHz   ¼  10 kHz zS2 zB R1 jjR2 500kjjR2 AS0 ¼

R2 ¼ 56 kΩ

∴

R2 AG RF ð56kÞAG ð500kÞ  40 V=V ¼ 32 dB ¼ 500k þ 56k R1 þ R2

pS1  pC 

RC ¼ 56 kΩ

∴

∴

1 1 ¼  1 kHz 2πðRC þ RF ÞCF 2πð56k þ 500kÞCF

zS2  zB 

1 1 ¼  10 kHz 2πR1 CB 2πð500kÞCB

∴

AG ¼ 790 μA=V ∴

CF ¼ 290 pF

CB ¼ 32 pF

328

6

pS3 ¼ pO 

1 1 ¼  1 MHz ∴ 2πðRC jjRF ÞCX 2πð56kjj500kÞCX

Feedback Control

CX  3:2 pF

Note: When integrated on chip, CX is usually lower than 3.2 pF.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Type III OTA vi vi 0 dc¼0 ac¼1 r1 vi vp 500k cb vi vp 32p r2 vp 0 56k gag 0 vo vp 0 790u rf vo 0 500k cf vo vc 0 290p rc vc 0 56k cx vo 0 3.2p .ac dec 1000 10 10e6 .end Tip: Plot v(vp) and v(vo) in dB to inspect zB and pBX and AS.

6.3.3

Feedback Translations

AS for feedback implementations of the stabilizer follows the lowest forward translation to vO. The feedback translation component of AS turns zeros and poles in the feedback path βFB into poles and zeros in the forward path 1/βFB. So when the overall forward gain AF exceeds the feedback gain Aβ, AS follows Aβ, turning zeros and poles in βFB into poles and zeros in Aβ and AS. A. Non-inverting The op amp in Fig. 6.25 turns the zero–pole pair in βFB into pS1 and zS1. 1/βFB starts at (RF + RB)/RB at low fO (when CF opens), falls past pF when CF shunts RF, and flattens to one past zFX when RB || RF current-limit CF. AS follows this 1/βFB until pA reduces AF’s AV below 1/βFB’s one. So pS1 is pF, zS1 is zFX, and pS2 is AV0pA’s projection to pX, but only when AV0 and pX exceed Aβ0 and zFX:

6.3 Stabilizers

329

vO AV

RF

RB

vN

CF

pA Gain [dB]

vIN

AV0 AF

pF AS

0 dB

zFX Log Frequency [Hz]

AE0

AE

pX

Fig. 6.25 Pole–zero non-inverting feedback translation Fig. 6.26 Pole–zero–zero non-inverting feedback translation

vIN C B

R1 vP

R2 RF

RB

vN

AFW

vO

AV

CF



 

pA

AV0 1


  AV0  1 f O
f O AV0 pA pX βFB
f O >zFX 1 þ s=2πpA
f O >p

ð6:40Þ

A

1 AS ¼ AFW jj βFB    1 þ sðRB jjRF ÞCF RF þ RB  RB ð1 þ sRF CF Þð1 þ s=2πAV0 pA Þ Aβ0 ð1 þ s=2πzFX Þ ¼ : ð1 þ s=2πpF Þð1 þ s=2πpX Þ

ð6:41Þ

Bypassing the R1 that feeds AV in Fig. 6.26 adds zS2. Here, AS0 voltage-divides with R1 and R2 and amplifies with AFW and 1/βFB. zB raises AS when CB bypasses R1 and pBX reverses zB when R1 || R2 current-limits CB. This way, pS1 is pF, zS1 and zS2 are zFX and zB, pS2 is pBX, and pS3 is AV0pA’s projection to pX, but only when AV0 and pX exceed Aβ0 and zFX: AS ¼ AF jjAβ    R2 1 ¼ AFW jj βFB ðR1 jjZB Þ þ R2

R2 AV0 jjAβ0 ð1 þ s=2πzB Þð1 þ s=2πzFX Þ  : ðR1 þ R2 Þð1 þ s=2πpBX Þð1 þ s=2πpF Þð1 þ s=2πpX Þ

ð6:42Þ

330

6

Feedback Control

Example 4: Determine R2, CB, pA, RB, CF, and zS1 with the AS0, pS1, zS2, pS2, pS3, R1, and RF used in Example 3 when AV0 is 1 kV/V. Solution: zS1  zFX

and

pS1  pF < zS2  zB < pS2  pBX < pS3 ¼ pX

R2 ¼ 56 kΩ and CB ¼ 32 pF from Example 3   

R2

RF þ RB AS0  AV0 R1 þ R2 RB     56k 500k

¼ 1k 1 þ  40 V=V ¼ 32 dB 500k þ 56k RB ∴ pS1  pF 

RB ¼ 760 Ω

1 1 ¼  1 kHz 2πRF CF 2πð500kÞCF

zS1  zFX 

∴

CF ¼ 320 pF

1 1 ¼ ¼ 660 kHz 2πðRB jjRF ÞCF 2πð760jj500kÞð320pÞ

pS3 ¼ pX  AV0 pA ¼ ð1kÞpA  1 MHz

∴

pA  1 kHz

Note: Setting AS0 and pS1 automatically sets zS1 (with 1/βFB0). 1/βFB0 is high because R1 and R2 reduce AS0, so RB sets a high zS1.

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Type III Non-inverting Feedback Translation vi vi 0 dc¼0 ac¼1 r1 vi vp 500k cb vi vp 32p r2 vp 0 56k eav0 va 0 vp vn 1k rpa va vb 1 cpa vb 0 159.2u eavo vo 0 vb 0 1 (continued)

6.3 Stabilizers

331

cf vo vn 320p rf vo vn 500k rb vn 0 760 .ac dec 1000 10 10e6 .end Tip: Plot v(vp) and v(vo) in dB to inspect zB and pBX and AS. B. Inverting The inverting op amp in Fig. 6.27 turns a zero in βFB into pS1. Aβ starts with –RF/ RB and falls past pF when CF shunts RF. AS follows this Aβ until AF drops below Aβ at pX. So when AF0 and AF’s projection to pX exceed Aβ0 and pF, AS0 is –RF/RB, pS1 is pF, and pS2 is pX: Aβ  

Aβ0 RF =RB ¼ 1 þ sRF CF 1 þ s=2πpF

AS ¼ AF jjAβ 

ð6:43Þ

RF =RB : ð1 þ s=2πpF Þð1 þ s=2πpX Þ

ð6:44Þ

AF voltage-divides vIN with RB into RF–CF and amplifies vN with –AV. As a result, AF falls with pA in AV and pC' when CF shunts RF || RB: 

 ½RF =ðRB þ RF Þ AV0 RF jjZF  : ðAV Þ  AF  RB þ ðRF jjZF Þ ð1 þ s=2πpA Þ 1 þ s=2πpC '

ð6:45Þ

With two poles, AF falls faster than Aβ. So AF eventually drops below Aβ:

pA pC'

AV

vN

RF CF

Gain [dB]

vO

vIN RB

AS

Fig. 6.27 Dominant-pole inverting feedback translation

pF

AE0

AF0 AF AE

Log Frequency [Hz]

pX

332

6

pA

vO

vIN RB

vN

Gain [dB]

AV

RF CF

RC

AS

pC''

Feedback Control

AF0

pC

–RC/R1

AF

AE0

zCX pX Log Frequency [Hz]

AE

Fig. 6.28 Pole–zero inverting feedback translation

jAF jf O >pA ,pC 0






RF AV0 pA pC '


2
ðRB þ RF Þf O


fO

AV0 RB pA pC

ðRB þRF ÞpF

' p



R p 
Aβ
f O >p  F F : F RB f O

ð6:46Þ

X

Current-limiting CF with RC in Fig. 6.28 reverses CF’s pole in Aβ and AF. This way, Aβ falls past pC when CF and RC shunt RF and flattens to –(RC || RF)/RB past zCX when CF shorts with respect to RC. AS follows this Aβ until AF drops below Aβ at pX. So when AF0 and AF’s projection to pX exceed Aβ0 and zCX, AS0 is –RF/RB, pS1 is pC, zS1 is zCX, and pS2 is pX: RF jjðZF þ RC Þ R  B  RF 1 þ RC CF s ¼ RB 1 þ ðRC þ RF ÞCF s    1 þ s=2πzCX R ¼ F RB 1 þ s=2πpC

Aβ  

AS ¼ AF jjAβ  

ðRF =RB Þð1 þ s=2πzCX Þ : ð1 þ s=2πpC Þð1 þ s=2πpX Þ

ð6:47Þ

ð6:48Þ

AF voltage-divides vIN with RB into RF–CF–RC and amplifies vN with –AV. So AF falls with pA in AV and pC'' when CF and RC shunt RF || RB and zCX reverses pC" when RC current-limits CF: AF 

½RF jjðZF þ RC Þ ðAV Þ RB þ ½RF jjðZF þ RC Þ



RF AV ð1 þ RC CF sÞ ðRB þ RF Þf1 þ ½RC þ ðRF jjRB Þ CF sg



RF AV0 ð1 þ s=2πzCX Þ  : ðRB þ RF Þð1 þ s=2πpA Þ 1 þ s=2πpC ''

With two poles and a zero, AF eventually drops below Aβ’s (RC || RF)/RB:

ð6:49Þ

6.3 Stabilizers

vO

RB

AV

RF

CB

vN

RC CF

p C'''' Gain [dB]

vIN

333

AF AE

pC

AE0 p A

AF0 pBX'

AS

zCX zB pC2 pX Log Frequency [Hz]

CF2

Fig. 6.29 Pole–zero–zero inverting feedback translation

jAF jf O >zCX 



RF AV0 pA pC '' R p R jjR 
Aβ
f O >zCX  F C ¼ C F RB zCX RB ðRB þ RF ÞzCX f O

ð6:50Þ

when  fO >

RB AV0 RB þ RF



pA pC '' pC

!  pX :

ð6:51Þ

Bypassing RB with CB in Fig. 6.29 raises Aβ and AF. This way, Aβ starts with –RF/RB at low fO, falls past pC when CF and RC shunt RF, and flattens and rises past zCX and zB when RC current-limits CF and CB bypasses RB. Adding CF2 flattens Aβ past pC2 when CF2 shunts RC || RF, past which Aβ remains –CB/CF2. AS follows this Aβ until AF drops below Aβ at pX. So when AF0 and AF’s projection to pX exceed Aβ0 and pC2, pS1 is pC, zS1 and zS2 are zCX and zB, pS2 is pC2, and pS3 is pX: 

  ð1 þ RC CF sÞð1 þ RB CB sÞ RF RB ½1 þ ðRC þ RF ÞCF s ½1 þ ðRC jjRF ÞCF2 s    ð1 þ s=2πzCX Þð1 þ s=2πzB Þ R  F RB ð1 þ s=2πpC Þð1 þ s=2πpC2 Þ

Aβ  

AS ¼ AF jjAβ    ð1 þ s=2πzCX Þð1 þ s=2πzB Þ RF AV0 RF  jj : RB þ RF RB ð1 þ s=2πpC Þð1 þ s=2πpC2 Þð1 þ s=2πpX Þ

ð6:52Þ

ð6:53Þ

AF voltage-divides vIN with RB–CB into RF–CF–RC–CF2 and amplifies vN with –AV. So AF falls with pA in AV and pC''' when CF and RC shunt RF || RB before pBX' later reduces AF when RF || RC || RB current-limits CB and CF2 (which also corresponds to CF2 and CB shunting RF || RC || RB) and climbs with zCX and zB when RC current-limits CF and CB bypasses RB:

334

AF

6

Feedback Control



½RF jjðZF þ RC ÞjjZF2 ðAV Þ ðRB jjZB Þ þ ½RF jjðZF þ RC ÞjjZF2



RF AV ð1 þ RC CF sÞð1 þ RB CB sÞ ðRB þ RF Þf1 þ ½RC þ ðRF jjRB Þ CF sg½1 þ ðRF jjRC kRB ÞðCB þ CF2 Þs



½RF =ðRB þ RF Þ AV0 ð1 þ s=2πzCX Þð1 þ s=2πzB Þ   : ð1 þ s=2πpA Þ 1 þ s=2πpC ''' 1 þ s=2πpBX ' ð6:54Þ

With three poles and two zeros, AF eventually drops below the Aβ that CB/CF2 sets after CB shunts RB and CF2 shunts RF || RC: jAF jf O >pC

'''',pA ,zCX ,zB ,pBX 0

RF AV0 pA pC''''p

BX ' ðRB þ RF ÞzCX zB f O

R p p C 
Aβ
f O >p ,zCX ,zB ,p  F C C2 ¼ B C C2 RB zCX zB CF2



ð6:55Þ

when fO 

RB AV0 pA pC''''pBX '  pX : ðRB þ RF ÞpC pC2

ð6:56Þ

Without CF2, AS would rise past zCX and zB with Aβ and later fall with AF. Falling after rising this way is the effect of a double pole pS23: the disappearance of a zero (zB) and appearance of a pole (pBX'). The purpose of CF2 is to split this pS23 into pS2 and pS3. This way, pS2 appears at an f0dB that keeps the feedback system stable without losing much phase shift to pS3.

Example 5: Determine pA, RB, CB, CF, RC, and CF2 with the |AS0|, pS1, zS1, zS2, pS3, and RF used in Example 3 so pS2 matches or exceeds 100 kHz when AV0 is 1 kV/V. Solution: pS1  pC < zS1  zCX ¼ zS2  zB < pS2  pC2 < pS3 ¼ pX RC ¼ 56 kΩ and CF ¼ 290 pF from Example 3

6.3 Stabilizers

335

AS0

    ð500kÞð1kÞ 500k RF AV0 RF ¼ jj ¼ jj RB þ RF RB RB þ ð500kÞ RB  40 V=V ¼ 32dB ∴ RB ¼ 12 kΩ

zS2  zB  pS2  pC2 

1 1 ¼  10 kHz 2πRB CB 2πð12kÞCB

∴

CB ¼ 1:3 nF

1 1 ¼  100 kHz 2πðRC jjRF ÞCF2 2πð56kjj500kÞCF2

∴

CF2  32 pF

RB AV0 pA pC ' pBX ' ðRB þ RF ÞpC pC2 ½AV0 pA RB =ðRB þ RF Þ ðRC þ RF ÞðRF jjRC ÞCF2  ½RC þ ðRB jjRF Þ ðRF jjRC jjRB ÞðCB þ CF2 Þ     AV0 pA ð12kÞ 56k þ 500k ð500kjj56kÞð32pÞ  12k þ 500k 56k þ 12k ð9:7kÞð1:3n þ 32pÞ pS3  pX 

¼ ð24mÞAV0 pA ¼ ð24mÞð1kÞpA  1 MHz

Explore with SPICE: See Appendix A for notes on SPICE simulations. * Type III Inverting Feedback Translation vi vi 0 dc¼0 ac¼1 rb vi vn 12k cb vi vn 1.3n eav0 va 0 0 vn 1000 rpa va vb 1 cpa vb 0 3.791u eavo vo 0 vb 0 1 rf vn vo 500k cf vn vx 290p rc vx vo 56k cf2 vn vo 32p .ac dec 1000 10 10e6 .end Tip: Plot v(vo) in dB to inspect AS.

∴

pA  42 kHz

336

6

6.3.4

Feedback Control

Mixed Translations

Forward gains can also play a dominant role in AS. In these cases, AS follows AF before transitioning to Aβ and ultimately succumbing again to AF. This way, AF and Aβ set AS0 and add pS1, zS1, and zS2 before AF limits AS at high frequency. A. Non-inverting AF in the non-inverting op amp in Fig. 6.30 amplifies vIN with AV and Aβ with RF and CF. AF starts at AV0 and falls past AV’s pA. Aβ starts high with ZC/RF, falls as CF shorts, and flattens to one past zFX when CF shorts with respect to RF: AF  AV ¼

AV0 1 þ s=2πpA

ð6:57Þ

ZC þ RF 1 þ sRF CF 1 þ s=2πzFX ¼ ¼ RF sRF CF s=2πp      F  pF ZC s s ¼ 1þ 1þ ¼ : 2πzFX 2πzFX RF fOi

Aβ ¼

ð6:58Þ

So AS follows AF’s AV0 until Aβ drops below AF’s AV0 at pX1. AS then falls and flattens with Aβ past zFX until AF falls below Aβ’s one at pX2. This way, AS0 is AV0, pS1 is pX1, zS1 is zFX, and pS2 is pX2, but only when Aβ’s projection to pX1 precedes pA and zFX and AF’s projection to pX2 exceeds zFX:


Z 1
 AF
f O