Substrate Noise Coupling in RFICs (Analog Circuits and Signal Processing) [1 ed.] 1402081650, 9781402081651, 9781402081668

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SUBSTRATE NOISE COUPLING IN RFICS

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: SUBSTRATE NOISE COUPLING IN RFICs Helmy, Ahmed, Ismail, Mohammed ISBN: 978-1-4020-8165-1 BROADBAND OPTO-ELECTRICAL RECEIVERS IN STANDARD CMOS Hermans, Carolien, Steyaert, Michiel ISBN: 978-1-4020-6221-6 ULTRA LOW POWER CAPACITIVE SENSOR INTERFACES Bracke, Wouter, Puers, Robert, Van Hoof, Chris ISBN: 978-1-4020-6231-5 LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES ¨ Haartman, Martin v., Ostling, Mikael ISBN-10: 1-4020-5909-4 CMOS SINGLE CHIP FAST FREQUENCY HOPPING SYNTHESIZERS FOR WIRELESS MULTI-GIGAHERTZ APPLICATIONS Bourdi, Taoufik, Kale, Izzet ISBN: 978-14020-5927-8 ANALOG CIRCUIT DESIGN TECHNIQUES AT 0.5V Chatterjee, S., Kinget, P., Tsividis, Y., Pun, K.P. ISBN-10: 0-387-69953-8 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN-10: 1-4020-5082-8 FULL-CHIP NANOMETER ROUTING TECHNIQUES Ho, Tsung-Yi, Chang, Yao-Wen, Chen, Sao-Jie ISBN: 978-1-4020-6194-3 THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: 0-387-47100-6 PRECISION TEMPERATURE SENSORS IN CMOS TECHNOLOGY Pertijs, Michiel A.P., Huijsing, Johan H. ISBN-10: 1-4020-5257-X CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS Yuan, Fei ISBN: 0-387-29758-8 RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS Reynaert, Patrick, Steyaert, Michiel ISBN: 1-4020-5116-6 ADVANCED DESIGN TECHNIQUES FOR RF POWER AMPLIFIERS Rudiakova, A.N., Krizhanovski, V. ISBN 1-4020-4638-3 CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM del R´ıo, R., Medeiro, F., P´erez-Verd´u, B., de la Rosa, J.M., Rodr´ıguez-V´azquez, A. ISBN 1-4020-4775-4 SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING Philips, K., van Roermund, A.H.M. Vol. 874, ISBN 1-4020-4679-0 CALIBRATION TECHNIQUES IN NYQUIST AD CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN 1-4020-4634-0 ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN 0-387-32154-3 WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: 0-387-30415-0

Substrate Noise Coupling in RFICs by

AHMED HELMY Ohio State University, Columbus, OH, USA

and

MOHAMMED ISMAIL Analog VLSI Lab, The Ohio State University, Columbus, OH, USA

Dr. Ahmed Helmy Ohio State University Dept. Electrical & Computer Engineering 2015 Neil Avenue Columbus OH 43210 USA [email protected]

ISBN: 978-1-4020-8165-1

Dr. Mohammed Ismail Analog VLSI Lab The Ohio State University Dept. Electrical & Computer Engineering 2015 Neil Avenue Columbus OH 43210 USA [email protected]

e-ISBN: 978-1-4020-8166-8

Library of Congress Control Number: 2008922524 2008 Springer Science+Business Media B.V. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

c 

Printed on acid-free paper 9 8 7 6 5 4 3 2 1 springer.com

This book is dedicated to Yasmin, Zeina, Aly, Omar and Mohammed Ismail’s family

Preface

Substrate noise coupling in integrated circuits (ICs) is the process by which interference signals in the form of voltage and current glitches cause parasitic currents to flow in the silicon substrate to various parts of the IC. The source of such glitches and parasitic currents could be from the switching noise of high speed digital clocks on the same chip. In RF and mixed signal ICs the switching noise is coupled to sensitive analog and RF nodes in the IC causing degradation in performance that could severely impact the yield. Thus, overcoming substrate coupling is a key issue in successful “system on chip” first-pass integration where RF and mixed signal blocks, high speed digital I/O interface are integrated with digital signal processing algorithms on the same chip. This is particularly true as we move to sub-90 nanometer system on chip integration. In this book a substrate aware design flow is built, calibrated to silicon and used as part of the design and validation flows to uncover and fix substrate coupling problems in RF ICs. The flow is used to develop a comprehensive RF substrate noise isolation design guide to be used by RF designers during the floor planning, circuit design and validation phases. This will allow designers to optimize the design, maximize noise isolation and protect sensitive analog/RF blocks from being degraded by substrate noise coupling. Several effects of substrate coupling on circuit performance will be identified and remedies will be given based on the proposed design guide. Three case studies are designed to analyze the substrate coupling problem in RFICs. The case studies are designed to gradually attack the problem at the device (Case 1), circuit (Case 2) and system levels (Case 3). At the device level a special emphasis is given to the design of on chip inductors as an important device in today’s SOC systems and the impact of substrate noise coupling on the inductor performance is characterized. An accurate model is developed for a broadband fit of the inductor scattering parameters to a lumped macro model that is used in the system analysis of case study 3. This model is shown to be scalable and is proven to be accurate when applied to various frequency bands and inductor geometries. A special emphasis is put on the DFM effects that affect the design robustness. A circuit level case study is developed and results are compared to simulations and silicon measurements to highlight the need for such a flow before silicon fabrication “taping out” to ensure a yielding part. In case study 3 a system level problem is studied on a GSM cellular receiver chain. vii

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Preface

The results are used as a demonstration vehicle to debug and resolve a system level substrate noise coupling problem that would otherwise have caused the receiver to malfunction, with adverse implication on yield and profit margin for such a high volume product. Chapter 1 introduces the work and highlights the motivation, objective and contribution. Chapter 2 discusses the phenomena of substrate coupling. Devices to substrate interface, noise injection, reception and propagation are explained in details. The industry standard algorithms used to model the substrate are studied and compared. The design methodology used to account for and integrate the substrate model in the design flow is highlighted. In Chapter 3 the design experiments are discussed, a test chip is described together with the de-embedding technique and measurement procedure. The design flow is then developed to model the substrate and is calibrated to the measurement data and simulations vs. measurements are reported as a foundation of a design flow that is used in the next chapters. In Chapter 4 a substrate isolation guide is developed based on two main methodologies. First, circuit and layout considerations are presented to maximize isolation, namely floor planning techniques. Supply line distribution and ground rails are also designed to maximize substrate isolation. Secondly, isolation structures are introduced and designed. Biasing and sizing of such structures are discussed; all are based on the calibrated design environment developed in Chapter 3. In Chapter 5 understanding the impact of these isolation structures and the substrate characteristics is used to develop a design flow for on chip spiral inductors. Measurements and simulations are compared to validate the flow and various flavors of on chip inductors are designed to fit the needs of several RF applications. A scalable inductor macro model is developed that is shown to be usable to a very good accuracy across a wide variety of inductor geometries and frequency bands. DFM effects are studied and their impacts are highlighted on the inductor performance. Chapter 6 presents three industrial case studies. The case studies are designed to gradually show the impact of substrate coupling at a device, a circuit and then at a system level. Simulation and measurement results are shown with and without applying the isolation techniques and results are compared. Chapter 7 concludes the work and proposes future work. This book is intended for RF and mixed signal design engineers, system-on-chip designers and process engineers as well as graduate students and researchers in the fields of integrated circuits and systems on chip design and optimization. The work has its roots in the Ph.D. dissertation of the first author, completed at the Analog VLSI Lab, the Department of Electrical and Computer Engineering, The Ohio State University. We would like to thank all those who assisted us during different phases of this work including our colleagues at the Analog VLSI Lab and at Intel Corporation. We also like to thank the Semiconductor Research Corporation for partially funding this work. Finally, we would like to thank our families for their help and support. Columbus, Ohio

Ahmed Helmy Mohammed Ismail

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Motivation and Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 5 5

2 Analysis of Substrate Noise Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Process Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Process Cross Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Connection of Devices to the Substrate . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Noise Coupling Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Substrate Doping Profile Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Substrate Model Extraction in the IC Design Flow . . . . . . . . . . . . . . . 2.7 Doping Profile Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Substrate Model Extraction Kernels . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 7 8 10 12 18 18 19 20 24

3 Experimental Data to Calibrate the Design Flow . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 The Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Baseline Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Effect of p-Guard Ring on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Effect of n-Guard Ring on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Effect of Deep n-Well on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Effect of Deep Trench on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 De-embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 25 26 28 30 32 35 37 38 41

4 Design Guide for Substrate Noise Isolation in RF Applications . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Isolation in Low Resistivity Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Isolation vs. Frequency for Different Isolation Structures . . . . . . . . . . 4.4 Effect of Back Plane Connection on the Noise Isolation in High Resistivity Substrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

43 43 43 44 45 ix

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Contents

4.5 4.6 4.7 4.8 4.9 4.10 4.11

Substrate Contacts: Frontside or Backside? Both . . . . . . . . . . . . . . . . . P+ Guard Ring Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P+ and N+ Guard Rings Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Floor Planning Techniques to Minimize Coupling . . . . . . . . . . . . . . . . Circuit Techniques to Minimize Coupling . . . . . . . . . . . . . . . . . . . . . . Active Guard Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48 48 55 56 59 60 60

5 On Chip Inductors Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Integrated Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Inductor Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Analytical Exploration of the Design Space . . . . . . . . . . . . . . . . . . . . . 5.5 Inductor Model and Substrate Parasitics . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Calibrating the Field Solver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Model Fit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 DFM Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

63 63 63 65 65 71 74 75 77 85

6 Case Studies for the Impacts and Remedies of Substrate Noise Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2 System Level Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3 Block Level Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4 Device Level Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 A Scattering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 B Measurements Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

List of Figures

1.1 1.2 1.3 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12

History of Moore’s law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trend in silicon systems and products . . . . . . . . . . . . . . . . . . . . . . . . . . . . Substrate noise coupling at a glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cross section of a general BICMOS process . . . . . . . . . . . . . . . . . . . . . . . Contacts in N-well resistors and capacitors . . . . . . . . . . . . . . . . . . . . . . . . Poly resistor model showing substrate network . . . . . . . . . . . . . . . . . . . . . Device models must be studied to accurately separate devices from the substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device to substrate capacitive coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . Cross section of a packaged chip showing bond wire noise . . . . . . . . . . . Substrate cut-off frequency f c as a function of resistivity ␳sub . . . . . . . . . Substrate as an undesired noise transfer medium . . . . . . . . . . . . . . . . . . . Disretization of substrate doping profiles . . . . . . . . . . . . . . . . . . . . . . . . . . Representing a substrate by a mesh of resistors . . . . . . . . . . . . . . . . . . . . . The design flow used to characterize substrate noise coupling . . . . . . . . The test bench used to simulate the substrate model of the isolation structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Die photograph of the test chip used to measure the isolation of different substrate structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout and cross section of the structure used to measure and simulate the baseline isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement vs. simulation for baseline isolation structure . . . . . . . . . . Layout and cross section of the structure used to measure and simulate the p+ guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . Careful grounding is needed not to increase substrate noise coupling . . p+ guard ring isolation once surrounding the receiver and once surrounding the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout and cross section of the structure used to measure and simulate the n+ guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . Measurement data for n+ guard ring isolation structure . . . . . . . . . . . . . . Measurement vs. simulation for n+ guard ring isolation structure . . . . . Comparison between isolation techniques . . . . . . . . . . . . . . . . . . . . . . . . .

2 2 3 8 9 11 12 13 15 17 19 20 21 26 26 27 28 29 30 31 31 33 33 34 34

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3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10

List of Figures

Layout and cross section of the structure used to measure and simulate the deep n-well guard ring isolation structure . . . . . . . . . . . . . . . Measurement and simulation data of the deep n-well guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison between the isolation of two deep n well guard rings and two n well guard rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout and cross section of the structure used to measure and simulate the deep trench isolation structure . . . . . . . . . . . . . . . . . . . . . . . . Isolation of a p guard ring with a surrounding deep trench as compared to a regular p guard ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout and equivalent circuit of the GSG structure with the DUT . . . . . Layout and equivalent circuit of the GSG open structure . . . . . . . . . . . . . Layout and equivalent circuit of the GSG short structure . . . . . . . . . . . . . Test structure used to simulate the backplane impact on isolation for resistive coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseline isolation for resistive coupling vs. backplane inductance . . . . . Test structure used to simulate the backplane impact on isolation for capacitive coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseline isolation for capacitive coupling . . . . . . . . . . . . . . . . . . . . . . . . . Test structure used to simulate the impact of guard rings on isolation . . Guard ring Isolation vs. distance D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guard ring grounding schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guard ring grounding scheme simulation data LGR = 1 nH . . . . . . . . . . . Guard ring Isolation vs. distance “d” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guard ring isolation vs. distance “d” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure used to simulate guard ring isolation vs. distance “w” . . . . . . . Guard ring Isolation vs. ring width “w” . . . . . . . . . . . . . . . . . . . . . . . . . . . P and N Guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . P and N guard ring isolation vs. enclosure distance “d” . . . . . . . . . . . . . . Floor planning to minimize substrate noise coupling . . . . . . . . . . . . . . . . Placements and biasing of the guard rings and ground lines . . . . . . . . . . Layout used to simulate the impact of guard rings on differential noise . Differential isolation using p guard ring and dual p and n-well guard rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductor design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductor layout showing design parameters and some DFM rules . . . . . L contours as a function of OD and W at a given N and S . . . . . . . . . . . . Q contours as a function of OD and W at a given N and S . . . . . . . . . . . . L, Q contours as a function of OD and W at a different N and S . . . . . . . Q vs. f showing different losses mechanisms . . . . . . . . . . . . . . . . . . . . . . . Differential inductor macro model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test bench used to extract model parameters . . . . . . . . . . . . . . . . . . . . . . . Q and L simulation vs. measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q and L simulation vs. measurement zoom in (left), parallel differential inductor (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35 36 37 38 38 39 39 40 45 46 47 47 49 49 51 51 52 52 53 54 55 56 57 58 59 60 66 67 68 69 70 71 71 73 74 75

List of Figures

5.11 5.12a 5.12b 5.13 5.14 5.15 5.16 5.17 5.18 5.19a 5.19b 5.19c 5.20a 5.20b 5.21 5.22 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22

xiii

Q and L macro model fit vs. sp file and percentage error . . . . . . . . . . . . . 76 Inductor physical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Inductor macro model and its fitting parameters . . . . . . . . . . . . . . . . . . . . 77 Q and L macro model fit vs. sp file and percentage error (left) inductor parameters (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Macro model fitting parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Bump relative positions to the on-chip inductor . . . . . . . . . . . . . . . . . . . . 79 Impact of bumps on the inductor Q and L (OD = 120 um, W = 4.7 um, S = 0.6 um, N = 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Impact of temperature on the inductor Q and L . . . . . . . . . . . . . . . . . . . . . 81 Impact of process variation on inductor performance . . . . . . . . . . . . . . . . 81 Inductor with top metal fill pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Inductor with n–1 metal fill pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Inductor with n–2 metal fill pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Inductor with metal fill patterns for other metal layers . . . . . . . . . . . . . . . 84 Inductor with poly and diffusion fill patterns . . . . . . . . . . . . . . . . . . . . . . . 84 Inductor with via fill patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Impact of dummification on Q and L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Block diagram of the RF receiver used in the case study . . . . . . . . . . . . . 88 LO phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LO phase noise mixing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Substrate noise coupling model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Layout of the VCO, LO and mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Substrate noise coupling distribution (case of vco perturbation) . . . . . . . 92 Substrate noise coupling distribution (case of blocker perturbation) . . . . 93 Layout comparison of both versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Adding deep trenches in and around the VCO . . . . . . . . . . . . . . . . . . . . . . 94 Noise levels without deep trenches added (left), and with deep trenches added (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Noise aggressor and victim points using the modified VCO (left), noise levels (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 A die photograph showing the VCO mixer section . . . . . . . . . . . . . . . . . . 96 Transmit buffer schematic without substrate network . . . . . . . . . . . . . . . . 97 Transmit buffer schematic with substrate network . . . . . . . . . . . . . . . . . . 98 Pout and Pgain vs. Pin with and without substrate model vs. silicon data at 1.9 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 S12 measured vs. simulation with and without substrate model at 1.9 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Transmit buffer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Cascode stage in the transmit buffer layout . . . . . . . . . . . . . . . . . . . . . . . . 100 Transmit buffer PN unmodified layout (right) modified layout and measurement (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Inductor test cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Inductance vs. freq for the four test cases . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Quality factor vs. freq for the four test cases . . . . . . . . . . . . . . . . . . . . . . . 103

xiv

A.1 A.2 B.1 B.2 B.3 B.4

List of Figures

Low-frequency description of two-port . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 High-frequency description of two-port. Z0 is the characteristic impedance of the lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 VNA setup to measure S-parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Layout of the measured differential inductors . . . . . . . . . . . . . . . . . . . . . . 110 Layout of the measured differential inductors with all de embedding structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Transmit buffer measurement setup and calibration steps . . . . . . . . . . . . 112

List of Tables

5.1 5.2 5.3 6.1 6.2 6.3 6.4 6.5

Set of parameters that should be considered during designing the inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Process information relevant to the inductor design . . . . . . . . . . . . . . . . . 75 Process corner definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Calculations for the receiver chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Substrate noise coupling level at mixer input relative to the noise source 93 Substrate noise coupling level at victim points with and without deep trenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Substrate noise coupling level at victim points for all three versions . . . 95 Inductor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

xv

Chapter 1

Introduction

1.1 Motivation and Objectives The current trend in process technologies is marching towards 45 nm production in 2007 and 32 nm production in 2009 [60]. The trend is still obeying Moor’s law [61], which states that the number of transistors on a single chip doubles every 2 years. Figure 1.1 shows the history of Moore’s law. In addition to the number of transistors, the demand on system on chip “SOC” and system in package “SIP” is increasing drastically to implement low cost, low power and small die size products. Figure 1.2 shows the trend in silicon products as of 2005 [60]. Examining this figure shows that the number of digital content is increasing in the presence of analog/RF and low power circuitry to achieve “SOC”. The increased number of digital gates is accompanied by the introduction of multi clock domains that can fulfill the signaling requirement. Such environment generates tremendous amount of interference signals that can couple to the analog/RF and other sensitive parts of the SOC, and in the presence of a scaled down supply voltage (to cope with the scaled geometry) the analog/RF become even more sensitive to noise, in addition, the noise margins of the digital gates are also decreased. Signal isolation, especially between the digital and analog regions of the chip, is an increasing challenge for deep submicron technologies due to the increased integration complexity. Noise coupling may occur through the power supply, ground rails and shared silicon substrate. The difficulty of integrating analog and high-speed digital functions on a chip increases with scaling in both device geometry and supply voltage. Signal isolation is critical for the success of co-integrating high performance analog circuits and highly complex digital signal processing (DSP) functions on the same die or substrate. Such co-integration is driven by the growth of the personal mobile computers and handheld communications market in recent years to reduce size, power, and cost and present to the end user a single ship solution. In such an environment, noise disturbances generated by high switching rates of digital circuits and the presence of strong interference signals between tightly coupled channels can propagate through the common silicon substrate due to the finite conductivity and permitivity of the substrate material and couple to circuits located in different parts of the substrate. Figure 1.3 shows the substrate noise coupling A. Helmy, M. Ismail, Substrate Noise Coupling in RFICs,  C Springer Science+Business Media B.V. 2008

1

2

Fig. 1.1 History of Moore’s law [61]

Fig. 1.2 Trend in silicon systems and products [60]

1 Introduction

1.1 Motivation and Objectives

3

Fig. 1.3 Substrate noise coupling at a glance

phenomena at a glance. Coupling occurs between a noise transmitter, which in most cases, is a fast switching digital block, and a noise receiver, which in most cases, is a sensitive analog or RF block. Coupling takes place due to the capacitive and resistive nature of the substrate-devices interface. The disturbances may, in many cases, be significant enough to degrade the performance of the sensitive analog and RF circuits sharing the same substrate with the digital block. Certain types of circuits have traditionally been built on separate substrates in order to minimize noise coupling between them. For example low-noise amplifiers and switching circuits such as dividers and high-power circuits such as buffers and power amplifiers are traditionally built on separate substrates. Then a SIP or a “system in package” is designed to build a single chip “module” to be presented to the end user as a single package solution for integration on the system board. Such a process although beneficial in many cases adds a huge overhead to project resources as far as design, validation, testing and integration. Higher levels of integration have several associated advantages and disadvantages. Obvious advantages are the reduced package count and die area. This leads to lowered costs and reduced sizes. The power dissipation can also be reduced as fewer pads and interconnect lines need to be driven, thereby avoiding the associated capacitance and parasitic self and mutual inductances. It may be possible to improve the high frequency response of the circuits or even extend the frequency range of the circuits’ performance, as the package interconnect parasitics often degrade the frequency response at the high frequency end of the application. A major disadvantage of integration is the increased interaction between circuits. This interaction can appear in two major ways. It can occur due to the significant mutual inductance and capacitance, which exist between any two bond wires and pins in a package. The second method for interaction is through the common substrate shared by the circuits.

4

1 Introduction

Integrating high-power switching noise generating circuits and sensitive lownoise circuits on the same silicon substrate while avoiding performance degradation due to substrate coupling is currently being viewed as a major challenge by circuit and system designers. In this book the problem of substrate coupling is addressed. The goals of this book are as follows. First is to build a calibrated design flow and develop a substrate design guide that can be adopted in a production worthy design environment that is capable of designing the substrate isolation structures and debugging the substrate coupling problems and implement fixes to such problems on device, circuit and system levels. Second is to design these fixes to take into consideration design for manufacturing effects. Examples of DFM effects are process skew variations, temperature variation, and effect of density dummification, wire bonds and C4 bumps. Such effects are being ignored for a while as being second order effects, but as technology scales these effects have started to surface as critical issues that must be addressed early in the design cycle. The objective here is to study the impact of such effects to ensure high resolution functionality and to eliminate costly reiterations. The sources of coupling are identified in different technologies as well as in various devices, both actives and passives. Then the mechanisms of noise reception and propagation through the substrate and the problem of efficient modeling of substrate coupling are discussed. The impact of substrate coupling on circuit behavior is discussed. Experimental results that verify the design flow will be carried on silicon. In this book different layout and isolation techniques will be suggested and verified to minimize substrate noise coupling. The third objective of the book is to study the impact of the substrate characteristics and isolation techniques on the design of RF passive devices. Precision passive devices are a new demanding challenge for current and future on-chip architectures. The request for high quality capacitors, inductors and resistors is mainly driven by advanced mixed-signal, high frequency (RF) and (SOC) applications. In the past, the traditional method of realizing passive circuit elements (for example, capacitors, resistors) on ICs was integration during front end processing. In this case doped monocrystalline Si substrate, polycrystalline Si and Si-oxides or Si-oxynitrides are used [1]. Because of their vicinity to the Si substrate, those passive devices fabricated during front end processing suffer increased performance degradation especially when used at high frequencies. Therefore, there is an increasing demand for low loss, low parasitics, but high quality passive devices in the interconnect levels. A part of this book is dedicated to develop an accurate inductor design flow that takes into consideration the substrate characteristics, isolation techniques and design for manufacturing effects. The focus is put on high quality on-chip inductors as they are critical components in analog/mixed signal and high frequency (RF) applications. With increasing frequencies, on-chip inductors will gain even more importance in the future [1–3]. Currently they are widely used in RF circuits especially for impedance matching, RF filters, RF transceivers, voltage controlled oscillators (VCO), power amplifiers and low noise amplifiers. Several design examples are developed in this book relying on the inductor design methodology that is also developed and adopted to design these structures. The impact of substrate is highlighted and isolation techniques are

1.3 Book Organization

5

implemented. The designed inductors are selected to span the different flavors of on chip spiral inductors that fit various RF application needs. The fourth objective is to apply the learning to real life circuits and system level problems and demonstrate how to uncover a substrate noise coupling problem, its impacts and remedies.

1.2 Contributions The objectives are carefully selected to complement the previous work found in the literature [62–92] and to provide simulation and measurement based analysis instead of the rule-of-thumb guidelines now used to deal with substrate noise problems. The focus will be on the RF and high speed serial IO link applications and their frequency of operation. The book contributions are summarized as follows:

r r r r

r

r r

A substrate aware design flow is build that uses the substrate model kernel extractor that represents the industry standard. The emphasis is focused on calibrating the flow to the process technology at hand. The flow is calibrated to silicon measurements, based on a test chip that is designed and tested for this purpose. The emphasis of this work is put on the RF and high speed serial IO links frequencies (1 ∼10 GHz). A complete substrate noise isolation design guide is developed based on the calibrated design flow. The design guide studies various isolation structures in modern process technologies used for RF and mixed signal ICs, their geometrical and electrical parameters, frequency of operation, floor plan, power and ground domains design. A design flow is developed to design on-chip spiral inductors based on analytical formulas found in the literature and an industrial tool used as a 3D full wave field solver. The flow is calibrated to silicon measurements and is used to study the substrate parameters and their impact on the inductor performance. The DFM effects are studied that impact the on-chip inductor performance. Such effects that directly impact robustness and yield. The two design flows are used in the design phase and is applied to three case studies on device, circuit and system levels where the noise coupling issue is uncovered and fixed. Simulation and silicon measurements are used to validate the existence of the problem and to validate the fix implemented.

1.3 Book Organization In Chapter 2 the phenomena of substrate coupling is studied. Devices to substrate interface, noise injection, reception and propagation are discussed in details. The industry standard algorithms used to model the substrate are studied and compared. The design methodology used to account for and integrate the substrate model in the design flow is discussed. In Chapter 3 the design experiments are discussed, a

6

1 Introduction

test chip is described together with the de-embedding technique and measurement procedure. The design flow is then developed to model the substrate and is calibrated to the measurement data and simulations vs. measurements are reported as a foundation of a design flow that is used in the next chapters. In Chapter 4 a substrate isolation guide is developed based on two main methodologies. First, circuit and layout considerations to maximize isolation, namely floor planning techniques, power line distribution as well as ground rails are designed to maximize substrate isolation. Second is the design of isolation structured that will aid the isolation level. Biasing and sizing of such structures are discussed all are based on the calibrated design environment developed in Chapter 3. In Chapter 5 the learning of the impact of these isolation structures and the substrate characteristics is used to develop a design flow for on chip spiral inductors. Measurements to simulations are compared to validate the flow and various flavors of on chip inductors are designed to fit the needs of several RF applications. A scalable inductor macro model is developed that is shown to be usable to a very good accuracy across a wide variety of inductor geometries and frequency bands. DFM effects are studied and their impacts are highlighted on the inductor performance. Chapter 6 concludes the book by applying the learning to three industrial case studies. The case studies are designed to gradually show the impact of substrate coupling on a device, a circuit and then a system. The isolation techniques developed are applied to the case studies to enhance the performance, simulation and measurement results are shown with and without applying the isolation techniques and results are compared.

Chapter 2

Analysis of Substrate Noise Coupling

In this chapter the steps needed to prepare the design environment that will be used in the next chapters to characterize the substrate noise coupling problem are studied. First, the device models of the process are studied to clearly define the devicessubstrate interface. Second, the noise injection, reception and transmission mechanisms are studied to understand the process parameters involved and frequency limitation that impacts the coupling phenomena, so that approximations and justifications can be engineered. Finally, the field solvers are studied and compared and an industry standard kernel is adopted in our flow. To set the foundation of analyzing the substrate coupling mechanism a generic cross section of a modern BICMOS process is shown in Fig. 2.1. The process is characterized by regions and cross sections [93]. The motivation behind this diagram is to study where and how the devices are connected to the substrate and what should be considered part of the substrate model that is connected to the circuitry and what should be left out from the substrate model since it is usually accounted for in the device model. Care should be exercised here since failing to make this distinction may result in double counting junction caps and substrate parasitics or in some cases missing these parasitics from the model of the entire system completely. In other words at the interface between the devices and the substrate a clear cut should be made to distinguish between features that are modeled in the front end device models and features that are not and hence should be part of the substrate model with no features left out and no features accounted for twice. In the next section, process regions and cross sections are explained; a BICMOS process is used since it has both Bipolar and CMOS devices and acts as a superset of process technologies.

2.1 Process Regions Figure 2.1 lists the process different regions as follows: Default: This corresponds to the default p substrate where there is no well implant present. Devices implemented in this region are NMOS devices. N-well: This corresponds to the region where an n-well implant has been made to create an n-well tub for including p-type PMOS devices. A. Helmy, M. Ismail, Substrate Noise Coupling in RFICs,  C Springer Science+Business Media B.V. 2008

7

8

2 Analysis of Substrate Noise Coupling

Fig. 2.1 Cross section of a general BICMOS process

Deep n-well: This region has an n-well implant (similar to the n-well region above) but in addition to this implant, there is a buried n-layer underneath the n-well thus increasing the depth of the n-well in the substrate. Devices implemented in this region are PMOS devices that need special substrate isolation. Triple well: This region corresponds to a p-well tub that has been completely separated from the default substrate region by the presence of the buried n-well structure that forms the floor of the tub. Devices implemented in this region are triple well NMOS. In addition to noise isolation, triple well NMOS are usually used to eliminate body effect or back bias by furnishing a dedicated bulk connection to this transistor that is separated from the rest of the common substrate and hence can be connected to a dedicated connection without sharing the common substrate connection. This is used to bias the device in a drowsy mode, which is used for power saving during stand-by operations. The overhead of such device is both wafer cost and die area. Sinker: This region corresponds to the n-type buried layer that is contacted through an n-sinker. This normally occurs in the bipolar transistors. Deep trench: This region represents the oxide trench that goes deep into the substrate. This is used primarily for substrate noise isolation. Passives: This region represents the place where passive devices are implemented on higher level metal layers. Examples of passive devices are poly resistors, inductors, metal capacitors and routing interconnects. This region can be combined with the default region where NMOS transistors are not present.

2.2 Process Cross Sections Seven distinct cross sections are shown in Fig. 2.1 where the arrows are pointing. 1-Default: This corresponds to the section with no active diffusion implants in the process. This is the section with only the field thick oxide or Shallow Trench Isolation “STI”. 2-Contact: This cross-section denotes the active diffusions that are bias contacts (substrate and/or well ties or taps) into the substrate mostly from power and ground supplies (for example P+ ties in the default region is connected to ground pads,

2.2 Process Cross Sections

9

while N+ contacts in the n-well regions will be connected to power supply pads). In some cases these contacts are also present in well resistors and well capacitors (N+ in n-well) where they are not necessarily connected to power and ground pads as shown in Fig. 2.2. 3-Source drain: This cross-section denotes a p-n junction which is formed by a diffusion implant in the substrate (P+ in n-well, N+ in default p-substrate). This would be used for connecting to sources and drains of MOS transistors as well as p-n junction diodes. Note that the source-drain cross section in the substrate should not include the junction parameters for the p-n junction. These are obtained from the device models as discussed later in this chapter. 4-channel: This cross-section represents the substrate underneath the gate of the MOS device under active conditions. MOS devices are connected to the substrate via this cross section and its bulk terminal. 5-deep device: This is primarily used to account for devices that include the n-well to substrate p-n junction inside the device model. Here the profiles representing the substrate start from below the n-well junction to the bulk substrate. 6-Bipolar: This is used to account for devices that already include the n-buried layer to substrate junction inside the device model. Here the profile representing the substrate starts from below the n-buried layer junction to the bulk substrate. 7-passives: This cross section lies under passive devices such as inductors and metal capacitors. In many situations these devices are surrounded by substrate taps or guard rings to isolate the substrate region under the devices which minimizes noise coupling to/from these devices. The combination of a region and a cross section denotes a unique profile in the substrate and this in turn ties to devices appropriately. The following discussion for the different active and passive devices present in today’s technologies clarifies the connectivity of different devices into the substrate. First, the regions and cross sections associated with each other are as follows:

Fig. 2.2 Contacts in N-well resistors and capacitors

10

2 Analysis of Substrate Noise Coupling

Region default can only have these cross sections: default, contact, channel, s/d. Region n-well can only have these cross sections: default, contact, channel, s/d, deep device. Region deep n-well can only have these cross sections: default, contact, channel, s/d, deep device. Region sinker can only have these cross sections: bipolar. Region deep trench can only have these cross sections: default. Region triple well can only have these cross sections: default, contact, channel s/d, deep device. Region passives can only have these cross sections: default, contact.

In addition to that, substrate taps (or ties) are extracted as a one pin device (“TIE”). The single pin of the device is connected to the appropriate supply connection. This is achieved by stamping the connectivity to the metal layers on top. Next will be how each device is modeled and how will this impact the connection to the substrate. For example, the n-well resistor device can have three terminals where the third terminal (“sub”) is connected to p-sub. This means that the device model includes a diode modeling the n-well to substrate junction. In this case, the n-well shape associated with this device is taken out from the n-well region shape output in the substrate model because it is accounted for already in the model. If the “sub” terminal of the n-well resistor is a contact in the n-well then the substrate model should consider the n-well p-sub junction and its capacitance as part of the substrate model underneath this device.

2.3 Connection of Devices to the Substrate This section lists the connection between the different types of devices and the substrate. Some devices are considered directly connected to the substrate while others are indirectly connected as explained below.

2.3.1 Devices Directly Connected to the Substrate Network MOS Devices: These MOS devices are connected to the substrate through the bulk pin “sub” or “B”. They are connected to the “channel” cross section in the substrate. Poly Resistors: Since almost all poly resistor models account for the capacitance to substrate and the substrate network underneath the poly resistors as shown in Fig. 2.3, these resistors are connected to the substrate through the bulk pin “B”. These are connected to the “default” or “deep device” cross section if they are poly over sub or poly over n-well respectively. Same argument applies to all passive devices, inductors, MIM capacitors, etc.

2.3 Connection of Devices to the Substrate

11

Fig. 2.3 Poly resistor model showing substrate network

N-well Resistor: The n-well resistor is connected to the substrate through the bulk pin “sub”. This is connected to the “deep device” cross section (n-well-sub diode is part of the device model). Inductors: The inductors are connected to the substrate through the bulk pin “sub”. They are connected to the “default” or contact cross sections, depends on whether the inductor has a guard ring TIE around it or not. MIM Capacitors: The Metal to Metal capacitors are connected to the substrate through the bulk pin “sub”. They are connected to the “default” or deep device cross section depending if the MIM is over sub or over n-well (n-well-sub diode is part of the device model). Poly Gate Capacitor: This capacitor is connected to the substrate through the bulk node “sub”. It is connected to the “deep device” cross section (n-well-sub diode is part of the device model).

2.3.2 Devices Indirectly Connected to the Substrate Network The devices diode, bipolar and the varactor are considered indirectly in the substrate network. These devices always have a guard ring (tied to a supply) around them, so the guard ring is considered as a TIE which is connected to the substrate network via the default cross section. Now that the device models are studied and a decision is made to identify the devices-substrate interface, substrate is modeled separately as a semiconductor medium and then its model is connected back to the circuit to create a netlist with the substrate modeled. Figure 2.4 shows a methodology for such separation.

12

2 Analysis of Substrate Noise Coupling

Fig. 2.4 Device models must be studied to accurately separate devices from the substrate [94]

2.4 Noise Coupling Mechanism Three processes act sequentially to complete the substrate noise coupling phenomena. First the noise currents are injected from the devices into the substrate through the devices-substrate interface, and then noise propagates through the substrate medium to reach other locations on the same substrate. The nature of such propagation depends on the substrate resistivity and isolation structures implemented as well as grounding techniques and frequency of operation. Finally the substrate noise is received at the sensitive circuit node, where it modifies device characteristics. The challenge of modeling the substrate coupling is therefore a three-fold issue. Modeling of the injection mechanisms, substrate medium and the reception mechanisms is required to accurately analyze substrate coupling. Injection and reception mechanisms are modeled within the device models. The modeling of the substrate medium is provided separately. In this section, we will discuss substrate noise injection, propagation and reception mechanisms.

2.4.1 Substrate Noise Injection Mechanisms In mixed signal designs, devices induce currents in the substrate through several mechanisms. The most dominant are diffusion capacitive coupling, impact ionization and inductive coupling due to power grid fluctuations at substrate contacts with power and ground lines. According to [5], there are other less significant mechanisms through which currents are injected to the substrate, gate-induced drain leakage (GIDL) due to the gate induced barrier lowering, photon-induced reverse current and diode junction leakage current. The effects of these mechanisms are negligible compared to the above mentioned ones. They become only significant under certain bias conditions not applicable to the majority of applications, thus we will not focus on such effects in our analysis.

2.4 Noise Coupling Mechanism

13

2.4.1.1 Noise Injection Through Capacitive Coupling An important mechanism by which noise is injected to the substrate is capacitive coupling. Devices inject currents into the substrate through the p-n junction depletion capacitance of drain and source regions or collector regions to substrate C j s .

C js =



qε 2(ψ + V b)



N1N2 N1 + N2



(2.1)

where Cjs is the capacitance per unit area of the abrupt p-n junction, q is the charge of an electron, ␧ is the Si dielectric constant, ψ is the junction built in potential, Vb is the magnitude of the reverse bias voltage, N1 and N2 are the doping concentration of the p and n regions of the junction. The strength of the coupling is dependent on the device size and the switching frequency. As technology feature size is reduced, the doping concentration of the diffused regions is increased to avoid total pinchoff effect. Higher doping concentration leads to higher depletion capacitance and therefore lower capacitive impedance from the diffusion regions to the substrate and hence more coupling effects. Note that this capacitance is always included in circuit simulators such as SPICE as model elements “CJ0” and “CJSW” (these are the source/drain-to-substrate capacitance). Figure 2.5 shows a few types of devicesto-substrate capacitive coupling. Other than the p-n junction capacitive coupling, passive devices like resistors, capacitors and inductors can also capacitively induce current into the substrate. Resistors in modern processes are either poly-type or diffused. Poly resistors have a comparatively smaller parasitic capacitance to the substrate Thus diffusion resistors inject more noise into the substrate than poly resistors for the same dimensions. Capacitors can be either metal-to-metal, or poly-to-substrate types. Metal-tometal capacitors have the largest ratio of the parasitic capacitance to the substrate for a given capacitance. Hence if these devices are used for implementing large on-chip capacitors, they can act as significant substrate noise-injectors. On-chip inductors and interconnects inject noise into the substrate through the parasitic oxide

Fig. 2.5 Device to substrate capacitive coupling

14

2 Analysis of Substrate Noise Coupling

capacitance with the substrate. The substrate parasitic can lead to lowering of the inductor quality factor. Thus the substrate loss must be modeled to obtain an accurate prediction of inductor performance as discussed in Chapter 5. 2.4.1.2 Noise Injection Through Impact Ionization As transistor feature sizes are being reduced, the electric field in the channel increases and therefore impact ionization currents are becoming more significant compared to other injection mechanisms. When MOS devices are biased in saturation regime, a high electric field in the depleted region of the channel is formed near the drain. Due to the high electric field, impact ionization takes place when “hot” carriers dissipate their excess energy via collision generating electron-hole pairs. For a p-type substrate, in case of NMOS transistors, the generated holes are swept to the substrate generating an effective drain to-substrate current [5]. For PMOS transistors, the impact ionization current is less due to the lower hole mobility. In addition, PMOS transistors are physically located inside n-well regions. The well junctions serve to reduce coupling of currents to the surrounding p-type substrate due to its capacitive impedance. Thus it may be expected that PMOS devices cause lower substrate bounce than comparably sized NMOS devices. This is indeed the case as long as the n-well has a very low impedance ac ground contact. If the well potential is allowed to vary with respect to the substrate potential, the well acts as a large injector, with a large reverse biased well to substrate capacitance and can cause significant substrate noise injection. The impact ionization substrate current dependence on the transistor drain current is given by the following semi-analytical expression [6]. Isub = K 1 (Vds − Vdsat )I d exp



−K 2 Vds − Vdsat



(2.2)

where Id is the drain current Vds is the drain to source voltage and Vdsat is the drain to source voltage at saturation. K1 and K2 are empirical constants. K2 depends on the oxide thickness tox and the drain junction depth x j as K2 ␣ tox 1/3 x j 1/2

(2.3)

This phenomenon is discussed extensively in [6]. It is derived by considering the exponential dependence of the carrier ionization coefficients on the electrical field in the channel. Integrating the substrate current generated per unit length over the length of the channel results in Eq. (2.2). Recent experimental evidence suggests that hot-electron induced substrate currents are the dominant cause of substrate noise in NMOSFETs up to at least one hundred megahertz [7]. Shorter device channel lengths in future technologies are likely to increase the impact ionization currents due to increased channel fields and smaller tox and x j . The nature of current injection due to capacitive coupling and impact ionization induced currents is different because hot-electrons induced currents are always

2.4 Noise Coupling Mechanism

15

injected into the substrate irrespective of the polarity of the injectors. In a switching CMOS inverter, hot-electrons induced current will be injected into the substrate during both the 0-1 and 1-0 transitions, while the capacitive component of the current will reverse direction during the two edges. As a consequence, hot-electron induced currents will possess large even-harmonics of the fundamental switching frequency and a DC component. On the other hand, the capacitive currents will possess large odd-harmonics and no DC component. Thus careful circuit design such as differential circuit techniques can minimize the even-harmonics and decrease the impact ionization component. The presence of a DC component in any substrate current can be potentially very harmful to circuit operation. In addition to causing a drift in threshold voltages, it can also lead to an increase in minority-carrier injection into the substrate due to partial forward-biasing of device-to-substrate junctions. This leads to severe degradation in the circuit performance or in many cases a malfunction. For small-signal analysis, the effect of the hot-electron induced current can be modeled as a drain-to-body transconductance gdb [8] given by gdb =

⭸Isub K 2 Isub = . ⭸VD (Vds − Vdsat )2

(2.4)

The major effect of this parameter on small-signal circuit analysis is that this term appears in parallel with the ro of the device and tends to lower the output impedance of the transistor in saturation hence lowering its gain in saturation.

2.4.1.3 Noise Injection Due to Power Grid Fluctuations Due to parasitic effects associated with the package, mainly bond wire inductance, power supply lines become very noisy because of currents drawn by the switching digital circuits. These currents induce large voltage glitches when they switch (Ldi/dt noise) at substrate and well contacts. This represents a significant amount of noise injection into the substrate depending on the switching speed and the availability of other noiseless substrate ties. In addition, the power grid noise can be also capacitively coupled through metal-to-substrate parasitic capacitance. Figure 2.6 shows a cross section of a packaged chip and the coupling between bond wires.

Fig. 2.6 Cross section of a packaged chip showing bond wire noise

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2 Analysis of Substrate Noise Coupling

2.4.2 Substrate Noise Reception Mechanisms The reception of noise by most devices on the silicon surface takes place through capacitive sensing. This is true for BJTs, resistors, capacitors and interconnects lines. For MOS transistors, noise couples through drain and source junctions. For devices like diffusion resistors and well-to-poly capacitors, the noise is coupled through the well junction capacitance. Because junction capacitances are typically small, capacitive coupling effects become significant only at high frequencies. Metal interconnects and poly resistors are also capacitively linked by oxide capacitance to the substrate. Substrate noise can also indirectly affect the circuit performance through the package and interconnect parasitics, ⌬I noise across bond wire inductance may cause serious performance issues. In addition to capacitive pickup through the source and drain depletion junctions, MOS devices also exhibit a more severe form of substrate interaction due to the body effect. The threshold voltage of a MOS transistor is a relatively strong function of the substrate potential. For a uniform surface impurity concentration, the dependence of the threshold voltage is given by [8].

Vt = Vt0 + γ



2φ f + Vsb −



2φ f



(2.5)

where Vt0 is the threshold voltage at zero source-to-bulk bias ␥ is bulk threshold parameter and ␾ f is the surface inversion potential. The change in threshold voltage has a direct effect on the drain current Id through the following equation:

Id =

K W (Vgs − Vt )2 . 2 L

(2.6)

The dependence is represented as gmb , the bulk-to-source small-signal transconductance gmb

gmb =

⭸Id γ = gm  ⭸Vbs 2 2φ f + Vsb

(2.7)

where gm is the gate-to-source transconductance at the same operating point. In typical processes the ratio (gmb /gm ) varies from 0.1 to 0.3. The parasitic bodyto-source gain is thus lower than the gate-to-source gain by a factor of 14–20 dB only. The body effect in MOSFETs makes these devices especially vulnerable to substrate noise reception. While the capacitive pickup exhibited by most devices becomes significant only at high frequencies, the body effect can be an issue at low frequencies.

2.4 Noise Coupling Mechanism

17

2.4.3 Substrate Noise Transmission Mechanisms Substrates act as the media for coupling of noise from one device to another. Thus in order to understand the phenomenon of substrate coupling, it is essential to study the nature of the substrate as a transmission media and the process technology parameters that affect that as well as the frequency impact on the behavior of the substrate as the transmission media. Since the substrate acts as a lossy dielectric, a derivative of Maxwell’s equations shown below is applicable to the substrate [27] J = (σ + j ωε Si )E

(2.8)

where J is the current density in the substrate (A/cm2 ), E is the electric field (V/cm), σ is the conductivity (S/cm) and εsi is the dielectric permittivity of silicon (␧o 8.854e-14 ∗ ␧r 11.7 F/cm), ω is the frequency in rad/s. The substrate impedance and the behavior of the substrate as a noise transmission medium are frequency dependent. As long as σ >> ωε Si the current in the substrate will be dominated by the resistive nature. At low frequencies, dielectric capacitive behavior of the substrate is insignificant and hence, it can be considered merely as a resistive medium. This assumption is valid below a certain cut-off frequency f c given as [9] f c = 1/(2␲␳sub ␧si )

(2.9)

where ␳sub is the resistivity of the substrate. Figure 2.7 shows a plot between the substrate resistively ␳ = 1/␴ and the frequency at which ␴ = ωε Si called the cutoff frequency f c. . For ␳sub = 10 ⍀-cm, the substrate can be considered as a resistive medium below 15 GHz. Thus for most of the cases in this book the substrate

Fig. 2.7 Substrate cut-off frequency f c as a function of resistivity ␳sub

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2 Analysis of Substrate Noise Coupling

medium is treated as a resistive medium except in some specific conditions that will be highlighted where they fit. The above model considers current flow only due to drift (field induced) currents. This model would be sufficient for low-level majority-carrier conduction. Minoritycarriers, once injected into the substrate, can exist for long periods of time (carrier lifetime) and cause significant local variations in conductivity. However a large injection of minority-carriers into the substrate usually indicates a fault condition, as this occurs when a device-to-substrate junction is turned on. Hence to model substrate cross-talk we only consider the drift-induced substrate currents.

2.5 Substrate Doping Profile Tradeoffs Conductivity is the parameter that determines the nature of the noise transmission media in the substrate. The conductivity ␴ depends on the carrier concentration “p” and the hole mobility “␮p ” and hence is a function of the doping profiles in the substrate. Substrate coupling depends on the type of the substrate whether it is lightly-doped or heavily-doped. Intuitively, the higher the resistivity of the substrate the lower the noise coupling will be. Tradeoff between noise coupling, latch up effects and wafer cost is what dictate the wafer doping profile of different process technologies based on the target application. The modern process technologies are categorized into three main types. First, the memory and RF processes with a high resistivity substrate (all TSMC and UMC processes [10, 11]). Second the digital CMOS processes with a low resistivity substrate and a high resistivity epitaxial layer (option for all TSMC and UMC, STMicro, IBM [10–13]). Third, the bipolar processes with high resistivity substrate and epitaxial layer and low resistivity buried layers (IBM, STMicro [12, 13]). High resistivity substrates are used for RF application since noise isolation is critical as well as to minimize eddy currents in the substrate and hence enhance the quality factor of all the passive devices built on it that are critical for RF applications. Many CMOS fabrication processes today use a lightly doped epitaxial layer grown on top of a heavily doped bulk substrate. The lightly doped epitaxial layer provides a tightly controlled level of doping for device performance, while the low resistivity of the heavily doped bulk helps to prevent latchup. The buried layers are usually low resistivity p-layers at the top of the substrate that prevents inversion of the bulk regions outside the transistor channel areas.

2.6 Substrate Model Extraction in the IC Design Flow In the circuit design flow, the substrate model is in the form of a sub-circuit RC network that represents the substrate. The resulting substrate model is considered an additional subsystem to be electrically linked to the original design that assumes no substrate coupling. The substrate is represented by a linear multi-port network

2.7 Doping Profile Considerations

19

Fig. 2.8 Substrate as an undesired noise transfer medium

Fig. 2.8 and the role of the substrate model is to extract the admittance/impedance matrix elements representing the electrical behavior of the substrate. The substrate model acts as a transfer function between the noise sources and the sensitive circuits. The electrical behavior of the substrate transfer function is determined by the process parameters, layout and substrate impedance to ground. For high-resolution analog circuits, the substrate transfer function is designed to strongly attenuate noise injected by digital circuits. This can be achieved by careful layout design such as the placement of carefully designed guard rings as will be discussed in Chapter 4.

2.7 Doping Profile Considerations In order to model the effect of substrate coupling, doping information is required to calculate the resistivity of the silicon at different points. Doping profiles for a certain process can be obtained either by physical measurements on fabricated wafers or through accurate computer device simulators. For every process technology, there is more than one doping profile at different regions of the fabricated devices. In order to simplify the substrate-modeling problem, the doping profile at each device region is approximated by a stack of uniformly doped layers of silicon [14]. The doping concentration of each layer is the mean of the non-uniform doping profile within that layer. This process is called profile discretization as shown in Fig. 2.9. As the number of layers increases, a more accurate substrate model can be obtained, however there is always the trade-off between the accuracy and performance of the modeling tool. Depending on the process, modeling engineers could find a suitable refinement level at which the accuracy is acceptable within a reasonable time frame.

20

2 Analysis of Substrate Noise Coupling

Fig. 2.9 Disretization of substrate doping profiles [94]

The discretizations of doping profiles and resistivity setting are determined based on calibrating the modeling tool to Si measurements as pre-processing steps upon which a process specific technology file is produced in our model strategy.

2.8 Substrate Model Extraction Kernels Different techniques had been be employed in the literature to solve the equations governing the physical problem of the substrate coupling, and then to represent it as an equivalent matrix of admittances (or impedances) connecting the terminals (ports). The most common approaches use the Finite Difference techniques and the Boundary Element Method (Green’s function is evaluated). With the discretization of doping profiles mentioned before, the substrate can be treated as a stack of uniformly-doped layers. In these layers, a simplified form of Maxell’s equations, that ignores the influence of the magnetic fields, can be formulated as [15]: ε.

⭸ 1 (∇.E) + ∇.E = 0 ⭸t ρsub

(2.10)

where E is the electric field intensity vector, and ␳sub and ␧si are the sheet resistivity and the dielectric constant of the silicon respectively. Equation (2.10) can be discretized on the substrate volume either in differential form using the Finite Difference (FD) techniques or in integral form using the Boundary Element Methods (BEM). In general, the discretization process leads to a large matrix representing the coupling in the substrate, which can be reduced to a simple equivalent macro-model connecting

2.8 Substrate Model Extraction Kernels

21

the substrate sub-system ports. Before matrix reduction, the Finite Difference method produces a large sparse matrix regardless of the number of the substrate ports. Integral approaches, such as using the Boundary Element Methods, produce a matrix size that is proportional to the number of ports. Although the matrix size is much smaller in BEM, the matrix is very dense and must be inverted, a rather computationally intensive process [16, 95]. Hence there is a compromise between accuracy and complexity in the two famous techniques found in the literature. The industry standard tool used in the book uses the finite difference method.

2.8.1 Finite Difference Method Extraction of the substrate macromodel requires the solution of the Laplace equation in the substrate. Solution of partial differential equations by the use of numerical techniques has been studied extensively and has been presented by several authors [17, 18]. These techniques usually involve approximating the differential equations of the system by difference equations. The resulting matrix is then solved using a method, which is appropriate for the matrix size involved. One of these methods is the finite difference technique. The Finite Difference approach is widely used in modeling the substrate behavior [19, 20]. In this approach, the silicon substrate is modeled as a three-dimensional resistor mesh. Layers of the doping profiles, combined with the device layout geometrical structures, constitute a matrix of cubiods as shown in Fig. 2.10. Every cuboid is modeled as a resistor in parallel with a capacitor [21]. The values of the resistors in the mesh are determined from the process information (layer sheet resistivity or doping density) and the geometry defined by the layout. As indicated earlier, the capacitance can be neglected except for the well-to-substrate junction capacitance. The resulting resistance mesh interconnects the substrate ports and

Fig. 2.10 Representing a substrate by a mesh of resistors [95]

22

2 Analysis of Substrate Noise Coupling

models the electrical behavior of the substrate. The 3D mesh network connecting the ports of the substrate can then be reduced and translated into a SPICE subcircuit consisting of resistors mesh. The sub-circuit could be used to simulate the substrate coupling using a typical circuit simulator such as SPICE3. Being a purely numerical technique, the accuracy of the obtained solution is highly dependent on the resolution of the discretization [22]. Because of its accuracy at high resolutions, the FD method is useful for high accuracy with complex substrate profiles, where analytical methods can be rather complicated [23,95] this is why this method is used in the industry standard tool extracting the substrate model.

2.8.2 Boundary Element Method The Boundary Element Method of extracting the substrate resistances is an analytical method that starts with discretizing each port on the substrate into a collection of panels [24]. This method is based on using Green’s function of the substrate. The Green’s function for a medium is defined as the potential at any point in the medium with suitable boundary conditions due to a unit current injected at any point within the medium [24]. The Green function can be analytically determined for the substrate as in [25]. Using Green’s function of the substrate, the impedance matrix representing the substrate behavior is analytically evaluated. The impedance matrix is then inverted to obtain the substrate admittance matrix [22, 26]. The substrate resistance between the ports is then obtained as the reciprocal of the sum of the corresponding admittance matrix elements. A major advantage of the BEM is that it is not as sensitive to discretization as the Finite Difference technique. As mentioned earlier, the resulting matrix of BEM methods is much smaller; however, the computational advantage of having a dramatically smaller matrix is limited by the fact that the impedance matrix to be inverted is fully dense (unlike the sparse matrix generated by FD method). If heuristics are further employed, the resulting matrix may be sparsified.

2.8.3 Comparison Between the Two Techniques Two techniques have been presented in the literature for computing the substrate macro-models. The first technique is purely numerical while the second utilizes a combination of numerical and analytical methods. The primary advantage of the second technique is the speed of computation, which was found to be significantly superior to the numerical technique for small structures. The computation time in the numerical scheme is small for a small number of grid points, but becomes large as the number of points is increased. For achieving good accuracy, the memory requirement of the numerical technique is seen to be very large. An advantage of the purely numerical technique is its versatility. The technique can be used to model lateral variations in resistivity without any overheads, unlike the analytical method.

2.8 Substrate Model Extraction Kernels

23

The power of the analytically based technique lies in the fact that meshing needs to be done only in the region of the contacts, not in the bulk unlike the FD method that is applied to the 3-D substrate. Hence BEM reduces the problem from a 3-D problem to a 2-D problem. In the analytical technique the number of mesh points rises rapidly with the number of contacts. Another disadvantage of the numerical technique is that for optimization, if a single contact is varied, then the entire problem has to be recomputed. This is not a problem with the BEM [95].

2.8.4 Approximations in the Model Extraction Algorithm Trade-offs between accuracy and simulation time are inevitable, as low computation times are usually achieved by ignoring some of the second order effects in the simulation. In the modeling technique a lumped equivalent macromodel representing the substrate is extracted by solving the differential equations representing the medium. The lumped macromodel relates the voltage and the current vectors at the substrate contacts. Several approximations must be made in order to extract the macromodel in a reasonable amount of time. The approximations involved, their validity and the point at which the approximations fail are discussed below. 2.8.4.1 The Electrostatic Assumptions The first approximation involved is that of considering the substrate as a resistive only media with no capacitance and inductance effects as discussed in Section 2.4.3. This approximation is accurate at low to moderate frequencies but it fails at frequencies above ∼15 GHz in typical silicon substrates of approximately 10 ⍀-cm. Another side of this approximation is to ignore any radiation and wave phenomena in the substrate; this is valid in integrated circuit substrates because the dimensions of the substrates are typically much smaller than the smallest electrical wavelengths, thus distributed effects are not observed in the substrates. Above these frequencies complete solution of Maxwell’s equations is necessary. Another deviation from the electrostatic model will occur when the vertical dimensions of the substrates become comparable to the skin depth in the medium. The skin-effect makes the resistance between two contacts on the surface frequency-dependent. The computational simplification achieved from the electrostatic assumption is enormous. Solution of the Maxwell equations in the substrate involves the solution of two inhomogeneous wave equations [27]. In the electrostatic approximation the scalar potential in the substrate satisfies the Laplace equation, and very efficient numerical techniques for parasitic extraction can be developed. The key inference is that the low frequency formulas suffice for first-order impedance estimates at most frequencies of interest. 2.8.4.2 The Linearity Assumption The conductivity of the silicon substrate is dependent on the electric field in the substrate. Thus the current-field relationship is nonlinear in silicon. This effect becomes

24

2 Analysis of Substrate Noise Coupling

significant at high-fields or at high current densities. The injection of minoritycarriers can also make the conductivity time, location and field dependent. The minority-carrier leakage is avoided by reverse-biasing the devices-substrate junctions. The conductivity of the silicon layers is assumed to be a constant, independent of the field. It is also assumed to be isotropic. Several nonlinear effects are considered in device simulators. These tools, however, are completely unsuitable for parasitic extraction due to the large computation times involved in even one or two devices problems. 2.8.4.3 The Equipotential Assumption The devices-to-substrate junctions are treated as equipotential contacts with the surface. A more accurate model of the junction would consider the devices-to-substrate junction as a depleted semiconductor region (a dielectric). This model is difficult to implement in a fast substrate noise simulator, since the extent of the depletion region depends on the voltage across the junction. The magnitude of the error from this approximation is reduced considerably due to the small dimensions of the devices compared to the substrate. Thus, while the instantaneous variations of the voltage across the reverse-biased junction may change the value of the depletion capacitance considerably, the change in the value of the substrate model impedance values is expected to be small. The nonlinear behavior of the junction capacitors is included in circuit simulators such as SPICE.

2.9 Conclusion In this chapter the device models are studied to accurately identify the devicessubstrate interface. The injection, reception and transmission mechanisms in the substrate are studied together with the solvers that are used for extracting the substrate model.

Chapter 3

Experimental Data to Calibrate the Design Flow

3.1 Introduction In the previous chapter the ingredients of a design flow that models the substrate noise coupling phenomena are studied. The design flow put together is summarized in Fig. 3.1. It starts by defining the devices-substrate interface and integrating this in the runsets (rule files) used for layout vs. schematic check and layout parasitic extraction. The rule files decides based on the substrate-devices interface what to include in the substrate model and what to leave behind as part of device models. The layout data is used to identify the geometries, interconnectivity and location of the devices and the substrate isolation structures that are designed. The process stack information and doping profile are another input to the solver. The above mentioned inputs are fed to the substrate model extraction kernel. A commercially available tool [58] that represents the industry standard is used as the extraction kernel. Figure 3.2 shows the test bench used to simulate the isolation structures with the substrate RC model as part of this test bench. The test bench has two signal ports for the two port single ended scattering parameters simulation that is performed on the substrate model. The substrate model is extracted based on the layout structures that are presented in the next section. To calibrate this design environment a test chip is designed and measured to compare silicon measurements to the simulation results and ensure that the design environment used is accurately predicting silicon behavior. Once this calibration is done the use of the design environment and substrate model extraction and simulations will be extended to other isolation structures to come up with a design guide for substrate noise isolation using circuit techniques, floor planning and substrate isolation structures [96, 97]. Then the environment will be used to assess the impact of substrate noise on device, circuit and system levels. Remedies are then given based on the design guide. Next, they are validated to ensure that the impact of substrate noise coupling on the circuit performance is minimized.

A. Helmy, M. Ismail, Substrate Noise Coupling in RFICs,  C Springer Science+Business Media B.V. 2008

25

26

3 Experimental Data to Calibrate the Design Flow

Fig. 3.1 The design flow used to characterize substrate noise coupling

Fig. 3.2 The test bench used to simulate the substrate model of the isolation structures

3.2 The Test Chip A test chip is designed taped out and measured to assess the impact of different substrate isolation techniques on the substrate noise coupling. The substrate isolation (or crosstalk) characterization is performed on a high resistive substrate of a BICMOS process wafers with a substrate resistivity of 10 ⍀-cm. The test chip used for this characterization contained various substrate crosstalk reduction structures.

3.2 The Test Chip

27

The purpose of this test chip is to calibrate the design flow used to model the substrate network to silicon data and not to measure all the various options of the substrate isolation structures which occupy large die area. Thus, a limited set of structures are designed and measured that scans the process technology features used for isolation, while different sizes and geometries are deferred for being simulated using the calibrated design flow. The frequency characteristics of substrate isolation structures are a function of their vertical and lateral constructions. The vertical construction parameters include substrate resistivity, doping profile, wafer thickness, and thicknesses of all the process wells (n-well, deep n-well, p-well). The lateral construction parameters include the isolation structures between the two circuit blocks that acts as the receiver and the transmitter of the substrate noise and their geometries and relative location on silicon. A metallic ohmic-contact was made to the back surface of the die and was connected to the measurement system ground during the testing. The inductance used in the simulations for the backplane contact to match the measurements is 0.1 nH. The different lateral isolation techniques are discussed in the next sections. Figure 3.3 shows the die photograph of the test chip. The test chip has on wafer probing RF GSG (ground-signal-ground) pads that are used to measure the scattering parameter of the substrate structures vs. frequency. The scattering parameters vs. frequency are measured using a probe station, RF probes and a 40 GHz network analyzer. The probe pads are designed as two port single ended structures and in some cases an extra DC probe pad is used to bias the different n-wells used. The probe pads de-embedding structures are also designed and measured to isolate the pads and feed lines parasitics from the total scattering parameters and extract the substrate structures contribution alone. The de-embedding technique used in measurement is explained later in this chapter, while the measurement setup is discussed in Appendix B. The calibration is done by tuning the doping profile of the various

Fig. 3.3 Die photograph of the test chip used to measure the isolation of different substrate structures

28

3 Experimental Data to Calibrate the Design Flow

isolation structures to match Si data. The structures are designed in a modular way to tune the doping concentration of a single implant at a time. For example baseline isolation is used to tune p-sub concentration; p+ guard ring isolation is used to tune the doping of the p+ implant used in the guard ring and so on.

3.3 Baseline Isolation To start with baseline information, the isolation between two p+ diffusion regions is measured. This information will be used to compare the isolation of the different isolation structures to the bare silicon isolation due to the distance between the noise transmitter and the noise receiver. The layout used for the baseline isolation is shown in Fig. 3.4. The ground “G” pads are tapped to the substrate and to the measurement system ground. The “G” pads are connected together in both X and Y directions to form an equipotential surface that ensures accurate measurements. Without such connection the measurements were too noisy. The ground connection in the Y direction is done using top metal layers, while that in the X direction is done using lower level metals as shown by the line labeled by G joining the ground pads in Fig. 3.4. This is done to prevent shorting to the signal “S” pad which is put on the top metal layer to minimize its parasitic capacitance to the substrate. The feed lines connect the receiver and the transmitter to the signal “S” pads. The resistance of the feed lines and their vias together with the pad parasitic capacitance are de-embedded to get the isolation information of the receiver and transmitter only. Two ports single ended s-parameter measurement is done and the isolation S12 in dB vs. frequency

Fig. 3.4 Layout and cross section of the structure used to measure and simulate the baseline isolation

3.3 Baseline Isolation

29

Fig. 3.5 Measurement vs. simulation for baseline isolation structure

after de-embedding is shown in Fig. 3.5. The simulation result is overlaid on the measurement in Fig. 3.5 after tuning the doping concentration fed to the solver to match the Si data. The S12 values shown below are based on a setup where port 1 is the receiver while port 2 is the transmitter as shown in Fig. 3.2.

3.3.1 Data Analysis Both the receiver and the transmitter are p+ diffusion regions in a p-well substrate, thus they both have ohmic contact to the substrate. Since the substrate used has a resistivity of 10 ⍀-cm it will behave as a resistive network up to the cutoff frequency as discussed in Section 2.4.3. Thus, the equivalent model between the receiver and the transmitter is all resistive and the S12 data looks pretty much constant up to ∼15 GHz, as expected from an all resistive mesh. Beyond this frequency which is identical to the cutoff frequency plotted in Fig. 2.7, the isolation behavior starts to depart from a resistive behavior and it starts to decrease with increasing the frequency due to the contribution of the distributed RC network that will now represent the substrate. The existence of capacitive impedance in the substrate due to the nonzero permittivity and the ␻␧ term in Equation (2.8) will cause a drop in the isolation as frequency increases. The simulation results match the measurement up to 20 GHz then it starts to deviate beyond 20 GHz but remains well within 0.8 dB of accuracy on the pessimistic side up to 30 GHz.

30

3 Experimental Data to Calibrate the Design Flow

3.4 Effect of p-Guard Ring on Isolation The first isolation structure to be studied is the p+ guard ring surrounding the p+ diffusion that acts as the receiver. Figure 3.6 shows the layout and the cross section of the isolation structure. The p+ ring surrounds the p+ diffusion that acts as the receiver. The guard ring is connected to the ground pads using a low ohmic contact connection as shown by the connection labeled by G in Fig. 3.6. This ground connection is needed for the ring to act as a sink to the substrate noise currents. A very low ohmic contact to the ground connection is needed to ensure strong current sink. The layout is also used to serve the purpose of measuring the substrate isolation if the guard ring surrounds the transmitter. This is achieved by also monitoring S21 in addition to S12, i.e. flipping the roles of the noise transmitter and noise receiver during the measurement can achieve this goal. Adding a second guard ring to simultaneously surround both the transmitter and the receiver can be tricky. The reason is that both guard rings have to be grounded to sink the substrate noise current and if they are both tied to the same ground node, this can create a short circuit path to the substrate noise current as shown in Fig. 3.7. If Zsh