Space Microelectronics Volume 2: Integrated Circuit Design for Space Applications [1 ed.] 9781630814694, 9781630812591

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Space Microelectronics Volume 2

Integrated Circuit Design for Space Applications

For a listing of recent titles in the Artech House Space Technology and Applications Series, turn to the back of this book.

Space Microelectronics Volume 2

Integrated Circuit Design for Space Applications Anatoly Belous Vitali Saladukha Siarhei Shvedau

Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. British Library Cataloguing in Publication Data A catalog record for this book is available from the British Library.

ISBN-13:  978-1-63081-259-1 Cover design by John Gomes © 2017 Artech House All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark. 10 9 8 7 6 5 4 3 2 1

Contents Preface

xiii

Introduction

xxi

 CHAPTER 1  Considerations for Selection and Application of Foreign Electronic Component Bases in Designing Domestic Spacecraft

1

1.1  General Problems of ECB Selection for REE of Space Application 1 1.2  Restriction on Export of Foreign-Made Electronic Components to Russia 3 1.2.1  Restriction of ECB Exports from the United States 4 1.2.2  Restriction on ECB Exports from Europe and Other Countries 8 1.2.3  International Export Control Organizations 9 1.3  Peculiarities of Application of Foreign-Made Industrial ECB in Rocket and Space Technology 10 1.4  Counterfeit Microelectronic Products and Methods of Their Detection 19 1.4.1  Types of Counterfeit Components 19 1.4.2  Effective Methods of Detecting Counterfeit Products 20 1.4.3  Electric Testing of Microelectronic Products for Space Application 23 1.5  Peculiarities of Selection and Application of Foreign Processors in Domestic Spacecraft 27 1.5.1  Application Aspects of Foreign Processors in Domestic Spacecraft 27 1.5.2  Versions and Qualifications of UT 699 and GR 712 Microprocessors 30 1.5.3  Architecture and Hardware Features of UT 699 and GR 712 Microprocessors of Leon 3FT Family 30 1.5.4  Peculiarities of Microprocessor Leon 3 Programming 32 1.6  Radiation-Tolerant DC Converters for Space and Military Applications 34 1.6.1  Total Ionizing Dose (TID) 35 1.6.2  Enhanced Low-Dose Rate Sensitivity (ELDRS) 36 1.6.3  Single Event Effects (SEE) 36 1.6.4  Analysis of Parameter Limits in Worst-Case Scenarios 36 1.6.5  MIL-PRF-38534 Standard Class K Requirements 37 1.6.6  Absence of Optocouplers in Hybrid DC-DC Converters 37 1.7  Best Practices of Work Arrangement for Producing Electronic Components of Space System On-Board Equipment 41

v

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Contents

1.8  Accelerated Reliability Testing of ECB SA 1.9  Analysis of Test Results for Microcircuits Purchased in Russia Between 2009 and 2011 References

47 51 60

 CHAPTER 2  Peculiarities of the Technological Process of Production and Basic Constructions of Submicron Transistors and Schottky Diodes�

63

2.1  On the Terminology of Submicron Microelectronics 2.2  Tendencies and Perspectives of Modern Technology Development in Microelectronics 2.2.1  Scaling Problem 2.2.2  Modern Submicron Technology: An Example of Its Implementation for Microprocessor Production 2.3  Peculiarities of Submicron MOS Transistors 2.3.1  MOS Transistors Structures in VLSIC 2.3.2  Methods to Improve MOS Transistor Properties 2.3.3  MOS Transistors with the Structure Silicon on Insulator 2.3.4  Transistors with Double, Triple, and Cylindrical Gates 2.3.5  Other Types of Transistor Structures 2.3.6  The Peculiarities of Transistors for Analog Applications 2.4  Constructional-Technological Peculiarities of High-Temperature Schottky Diodes 2.4.1  Physical Basics of Schottky Diode Functioning 2.4.2  Design-Technological Peculiarities of the Formation of HighTemperature Schottky Diodes 2.4.3  Methods of Ensuring Minimum Reverse Current and Minimum Direct Voltage 2.4.4  Methods of Ensuring Minimum Direct Voltage and Maximum Reverse Voltage 2.5  Design-Technological Peculiarities of Forming the Structures of the Schottky Diode with Increased Resistance to Static Electricity Discharges References Selected Bibliography

63 65 68 70 76 76 79 82 87 92 93

95 95 98 102 103

108 115 118

 CHAPTER 3  Energy Consumption Minimization Methods for Microelectronic Devices 3.1  Main Trends in Energy Consumption Parameters of Microelectronic Devices 3.2  Ways to Reduce the Power Dissipation Rate in CMOS LSIC 3.3  Main Sources of Power Dissipation in CMOS LSICs 3.4  Logical Design of CMOS LSIC with Reduced Power Consumption 3.4.1  Basic Logical Synthesis of CMOS Microcircuits with Reduced Power Consumption 3.4.2  Determining the Sources of Power Dissipation in CMOS Microcircuits

119 119 123 132 137 137 139

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3.4.3  Probabilistic Assessment of Optimization Options Based on Predicted Switching Activity of Microcircuit Units 3.4.4  The Choice of Element Basis While Designing CMOS VLSICs with Reduced Power Consumption 3.4.5  Logic Synthesis of CMOS LSIC in Element Library Basis 3.4.6  Optimization of Two-Level Logical Circuits Regarding Power Dissipation 3.4.7  Selection of Basic Gates of Technology-Independent Functional Circuits 3.4.8  Optimization of Multilevel Logical Circuits Composed of Multi-Input Gates 3.4.9  Optimization of Multilevel Logical Circuits Composed of Two-Input Gates 3.4.10  Technological Representation 3.4.11  Estimation of Power Consumption by the Designed CMOS LSICs at the Logical and Circuit Levels 3.4.12  Technology of Designing CMOS LSICs with Reduced Power Consumption Using PSLS 3.4.13  PSLS Software Complex Architecture 3.4.14  Functional Capabilities of the Software Complex PSLS

3.5  Organization Peculiarities of the Reduced Power Consumption in Modern Interface LSICs 3.5.1  RS-485 Interface Transmitter-Receiver Microcircuits 3.5.2  RS-232 Interface Transceiver Microcircuits 3.5.3  Design and Schematic-Technical Peculiarities of Designing Interface of IC Voltage Comparators with Reduced Supply Voltage 3.5.4  Peculiarities of Designing Electrical Circuits of Transmitter Units of Interface LSICs with Reduced Power Consumption 3.5.5  Thermally Independent Base Voltage Source, Equal to the Width of the Bandgap of the Semiconductor 3.5.6  Design Options for Thermally Independent Base Voltage Sources 3.5.7  Circuit Configuration Methods of Increasing the Resistance of Microcircuits to the Hot Electrons Effect References

141 143 144 146 147 148 150 153 155 156 158 159

162 162 168 182 189 193 194 197 202

 CHAPTER 4  Peculiarities of Radiation Impact on Submicron Integrated Circuits 4.1  Physical Mechanisms of Radiation Impact on Submicron CMOS Integrated Circuits 4.1.1  Property Recovery for Radiation-Exposed MIC Devices 4.1.2  Impact of the Exposure Conditions on the Radiation Tolerance of MIC Devices 4.2  Influence of Radiation on Analog Bipolar Integrated Circuits 4.2.1  Radiation Effects in Integrated Operational Amplifiers 4.2.2  Radiation Effects in Integrated Voltage Comparators

205 206 212 212 216 217 219

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4.3  The Main Methods of Ensuring Radiation Tolerance of Integrated Circuits 4.4  Radiation Tolerance of Modern and Advanced ICs 4.5  Recommended Set of Test Elements For Experimental Research on the Radiation Impact on the Silicon Microcircuit Properties 4.5.1  Element Base of Logic CMOS of Integrated Circuits 4.5.2  The Element Base of Electrically Erasable Programmable Read-Only Memories (EEPROM) 4.5.3  Logic CMOS IC 4.5.4  Memory CMOS LSIC 4.5.5  CMOS LSIC SRAM on the Basis of SOI Structures 4.5.6  BiCMOS LSIC 4.6  Equipment and Methods of Irradiating Test Structures and Studied Samples of Microcircuits 4.7  Methods of Measuring Electric Parameters of Test Structures After Irradiation 4.7.1  Methods of EEPROM Parameters’ Control 4.8  The Experimental Research Results of the Penetrating Radiation Impact on the Parameters of Bipolar Transistor Structures 4.9  Experimental Research of the Ionizing Radiation Impact on the Parameters of Bipolar Analog Integrated Circuits 4.10  Results of Experimental Research on the Impact of Ionizing Radiation on the Parameters of Transistor MOS Structures and Integrated Circuits Based on Them 4.10.1  The Study of the Gamma-Radiation Impact on the Parameters of Transistor MOS Structures 4.10.2  Experimental Studies of the Gamma-Radiation Impact on the MOS Capacitors and Transistor MOS Structure Parameters: Submicron CMOS IC Elements 4.10.3  Peculiarities of the Gamma-Radiation Impact on the Parameters of the MOS Cell of EEPROM 4.10.4  Experimental Research of the Penetrating Radiation Impact on the Parameters of Logic CMOS IC 4.10.5  Impact of the Ionizing Radiation on the Parameters of Memory CMOS LSIC 4.10.6  Experimental Study of the Radiation Impact on the Parameters of MOS/SOI Structures and CMOS LSI RAM Based on Them 4.10.7  Experimental Research on Impact of the Penetrating Radiation on the Parameters of Logic BiCMOS LSIC 4.11  Peculiarities of Using Simulation Methods in Studying of the Radiation Effects in BiCMOS Microcircuits 4.12  Peculiarities of the Mechanisms of the Influence of Space Factors on the Formation of Local Radiation Effects 4.13  Experimental Studies of Radiation-Resistant Hybrid DC/DC Converters of Chinese Manufacture References

220 221 224 224 225 226 226 226 227

227 230 231 233 237

246 246

253 256 259 263 270 276

284 293 300 304

Contents

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 CHAPTER 5  Methods of Prediction and Increase of the Radiation Tolerance of Bipolar and CMOS Integrated Microcircuits

309

5.1  Prediction Methods of Radiation Tolerance of CMOS LSI 5.1.1  Calculation-Experimental Prediction Methods of MOS Tool Radiation Tolerance 5.1.2  Prediction (Selection) Method of CMOS IC According to Radiation Tolerance 5.2  Calculation-Experimental Methods for Calculation of Radiation Tolerance of Bipolar and BiCMOS Tools 5.3  Calculation-Experimental Method of Predicting Radiation Tolerance of EEPROM MOS Memory Elements 5.4  Methods of Increasing IC Resistance to the Impact of Penetrating Radiation 5.4.1  Construction-Technological Methods of Increasing Radiation Tolerance of CMOS and BiCMOS Microcircuits 5.4.2  Standard Construction and Circuit Configuration Methods of Increasing Radiation Tolerance of ICs 5.4.3  New Construction and Circuit Configuration Methods of Increasing Radiation Tolerance of CMOS LSIC References

309 309 316

319 321 321 322 324 332 337

 CHAPTER 6  Analysis of Problems of Designing Very-High-Speed Microelectronic Devices and Systems Based on Them

339

6.1  Problems of Scaling Submicron Microcircuits 6.2  Tendencies and Problems of Designing Silicon Integrated Microcircuits with the Deep Submicron Design Rules 6.2.1  Tendencies of Scaling and Problems of Designing Silicon Submicron ICs 6.2.2  Problem of Power Consumption in Submicron IC 6.2.3  Monitoring Dissipated Power Distribution Across the Chip Area at the Design Stage 6.3  Leakage Currents and Static Power Consumption in the Structure of a Silicon MOS Transistor 6.3.1  Power Consumption in Submicron CMOS Circuits 6.3.2  Analysis of the Currents Flowing in a Submicron Silicon MOS Transistor 6.3.3  Physical Causes of Leakage Currents in Submicron Silicon Transistors 6.3.4  Analysis of the Power Static Consumption Value of a MOS Transistor 6.3.5  Peculiarities of Designing Submicron Analog ICs Taking into Account Static Power Consumption

339 341 342 346 350

353 353 356 359 363 365

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Contents

6.3.6  Peculiarities of Designing Submicron Analog-Digital ICs Taking into Account Static Power Consumption

6.4  Dynamic Power Consumption in a Typical Structure of a Submicron MOS Transistor 6.4.1  Submicron Digital ICs with Reference Delay Value 6.4.2  Signal Distribution Delay at Interconnections 6.4.3  Methods of Reducing Switching Power Consumption 6.4.4  Analysis and Calculation of Dynamic Power Caused by Leakage Currents 6.4.5  Analysis of Dynamic Power Consumption of Silicon Microcircuits 6.5  Influence of Temperature and Process Parameters Spread on Characteristics of Silicon Submicron ICs 6.5.1  Dependence of Leakage Currents on Temperature 6.5.2  Process Parameter Spread and Leakage Currents 6.6  Peculiarities of Designing Layout of Analog ICs with Deep Submicron Design Rules 6.6.1  Influence of Supply Voltage Reduction 6.6.2  Scaling and Delay of Signal Distribution at Interconnections 6.7  General Conclusions and Recommendations References

366

368 369 370 371 372 376

379 379 385 392 392 394 395 398

 CHAPTER 7  Designing Space Application Microcircuits Based on SOS and SOI Structures

401

7.1  Radiation-Tolerant CMOS LSI Circuit Based on SOI Structures 7.2  Impact of Ionizing Radiation Exposure on Silicon and Silicon Dioxide 7.2.1  Radiation Effects in Silicon Under Irradiation 7.2.2  Properties of the Si/SiO2 Interface Region 7.2.3  Impact of Ionizing Radiation Exposure on Dielectric Layers 7.2.4  Radiation Processes Within the Buried Dielectric of Silicon-onInsulator Structures 7.2.5  Comparison of Radiation Properties of SOI Structures Obtained by Various Methods 7.3  Physical Phenomena in MOS/SOI Transistors Under Conditions of IR Exposure 7.3.1  Ionizing Radiation 7.3.2  Full-Dose Effects 7.3.3  Impulse Irradiation Effects 7.4  Results of Experimental Research of Samples of the CMOS LSIC Element Base on SOI Structures 7.4.1  Composition of Test Elements 7.4.2  Experiment Procedure 7.4.3  Experimental Results References

402 411 411 414 418 421 423

424 425 430 433 434 434 435 439 458

Contents

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 CHAPTER 8  System-on-Chip and System-in-Package

465

8.1  General Trends in the Development of Chip Packaging Technology 8.2  BGA Technology of Chip Assembly 8.3  Technology for Chip Mounting on the Board 8.4  Multichip Modules and Printed Boards 8.5  Main Trends in Development of Packaging Technologies for Microelectronic Devices of Space-Related Application 8.5.1  Trend Towards Decrease in the Package Lead Pitch 8.5.2  Wafer Leads Packaging (WLP) 8.6  Peculiarities of the Packaging Technologies for SHF Circuit on the Board 8.7  Technologies of TSV Chip Assembly for Space-Related Applications 8.8  Features of the Assembly of 3D Products with Flip-Chip Technology Used 8.9  Features of the Application of Adhesives and Pastes During 3D Assembly 8.10  System-in-Package Electronic Units for Military Space Microelectronics 8.11  Features of Automatic Design Tools: Systems-in-Package 8.11.1  RF Module Design 8.12  Considering Features of Deep Submicron Technology When Designing VLSICs for SIPs 8.13  The Impact of SIP on the Evolution of the Concepts of Satellite System Construction 8.14  Features of Selection and Application of Known Good Die for SIP 8.15  Package Designs with Integrated Radiation Protection Screens 8.16  SHF Applications of MEMS Technologies 8.16.1  Features of Implementation of Radio Frequency MEMS/CMOS Devices 8.16.2  Radio-Frequency MEMS Switches 8.16.3  Radio-Frequency MEMS Condensers of Variable Capacity 8.16.4  Integrated MEMS/CMOS Resonators 8.16.5  MEMS Technologies in the Task of System Integration of Radar Installations 8.17  Gold and Aluminum Application Features in Power Microwave Transistor Assembly Technique References

465 469 471 473 477 477 479 487 493 498 500 504 508 511 511 516 520 525 529 529 535 539 542 544

552 559

 CHAPTER 9  Methods for Rejection of Silicon Microcircuits with Hidden Defects During Mass Production

561

9.1  Formulation of the Problem for the Case of Parametric Control of Integrated Circuits at Nominal Operating Modes

561

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Contents

9.2  Methods for Determination of Sensitivity Coefficients for Output Parameters of Bipolar Integrated Microcircuits 9.3  Detection of Microcircuits with Hidden Defects Based on the Analysis of Operating Range Boundaries 9.4  Evaluation of Numerical Values of Reliability Indexes Based on the Results of Experimental Tests of Integrated Microcircuits 9.5  Studying the Mechanisms of Influence of Hidden Defects on Numerical Values of the Bipolar IC’s Basic Statistic Parameters 9.6  Analysis of a Model of Mathematical Processing of Forced Test Results of CMOS Microcircuits 9.7  Main Methods of Detection and Rejection of Potentially Unreliable Circuits in Conditions of Mass Production 9.7.1  Method for Determining Potentially Unstable Devices Using Electrostatic Discharge 9.7.2  An Upgraded Method for Implementation of Microelectronic Devices Burn-In Procedure 9.7.3  Method for Detection of Integrated Circuits with Increased Reliability Based on the Critical Supply Voltage Parameter 9.7.4  Method for Rejection of Potentially Unreliable Microcircuits by Dynamic Current Consumption 9.7.5  Method of Supply Voltage Reduction References

563 566 573 575 577 581 582 583 585 586 587 593

About the Authors

595

Index

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Preface Originally, we wanted to introduce modern approaches to the development and application of microelectronic element base to developers of on-board radio-electronic equipment of spacecraft and dual-purpose and special-purpose systems. However, our aim has undergone considerable changes in the course of writing, data collection, and processing, as well as discussions with public officials and domestic and foreign specialists in space and microelectronics industries. The analysis resulted in a collection of extensive additional material; thus, the original format of the book was reconsidered and, apart from developmental aspects and problems of modern microelectronic devices for space and special-purpose equipment, it also provides more in-depth material. This material was organized in two volumes, which now include not only chapters focused on developmental aspects of modern microelectronic devices for space and special (military) application, but also chapters that dwell on other space problems: configuration of modern spacecraft, the role of onboard electronic equipment in reaching the project’s aim, spacecraft accident and failure statistics and their connection with quality and functionality of microcircuits used for on-board REE, reasons for widespread use of counterfeit microcircuits in Russia and ways to stop it, the impact of ionizing space radiation and stream of high-velocity and high-energy microparticles (cosmic dust) on radio-electronic equipment of space application (REE SA), the methods and technology solutions to minimize this impact on the operation of REE of space and special application, and many other aspects. This volume of the book has considerably increased due to information drawn from a major work of A. B. Zheleznyakov, Secrets of Rocket Catastrophes: The Cost of Breakthrough into Space (2011), which presents the entire history of national and international astronautics in a condensed form. The facts and the description of all the seminal stages of mankind going beyond the Earth, set out in this work, show the complexity of such an important endeavor and also the importance of electronic component base (ECB) in space exploration. Certainly, A.B. Zheleznyakov did not suppose that his reliable description of triumphal and tragic events of space exploration would be read by electronics specialists and considered from the point of view of their knowledge and experience. Our readers can refer to this work and learn themselves that, unfortunately, more than one-third of spacecraft accidents and failures are likely to be results of ECB failure.

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�������� Preface

Looking ahead, we consider the main aim of the book to be the following: when developing on-board radio-electronic equipment for spacecraft or choosing an existing one (or developing new ECB) the developers should consider people (astronauts, personnel of spacecraft ground support systems, military) whose life is dependent on the reliability of REE. Thus, the contents of the book were extended to include chapters on structure and composition of spacecraft on-board equipment, comparative analysis of accident statistics, and causes of launch vehicle and spacecraft failures, as well as on counterfeit ECB and ways to stop its usage. In the course of study of this additional material, which is not connected with our professional field (microelectronics and its application), there arose an objective need to compare approaches to the development of relevant infrastructure and principles of ECB application in spacecraft and military equipment in different countries (the United States, the USSR/the Russian Federation, China, European Union (EU) countries, and others). We were surprised to learn that, for example, having entered the space race much later than other countries, China has actually had a higher proportion of successful spacecraft launches compared with the United States and the Russian Federation in recent years; as of the time of this writing, China used at least 98% of domestic ECB for spacecraft (in Russia, it varied from 20% to 30%, according to different sources; the rest comes from abroad), and China does not copy Russian and U.S. spacecraft technological solutions, but even outperforms them. China’s antisatellite weapons have substantially advanced and the country has demonstrated its competitors’ (the United States and Russia) robot satellites (satellite killers) that actively maneuver in orbit and also Jade Rabbit, which operates rather successfully on the Moon. As a result, the readers are presented not with a small one-volume guide to development of highly reliable ICs and semiconductors for space and military equipment, but with an encyclopedia of space electronics that encompasses all the publicly accessible information about causes of major space equipment failures during the entire history of its development, as well as with practical recommendations on development of reliable element base for on-board REE. We express gratitude to our colleagues who have taken an active part in the book’s preparation and discussion, whose critical remarks and additions have contributed to the improvement of both the structure and the contents of the book: P. Bibilo, Y. Bogatyrev, V. Borisenko, V. Bondarenko, L. Dolgy, V. Ovchinnikov, V. Stempitsky, S. Usherenko, V. Korshunov, M. Kritenko, V. Steshenko, A. Turtsevich, V. Tetets, M. Merdanov, Y. Makarov, A. Nikiforov, L. Cheremisinova, V. Schiller, and others. It should be noted that many of the above-mentioned colleagues have provided us with their original studies on the topic and this material has considerably enhanced practical orientation of the book. We also express gratitude to our reviewers: members of the Academy of Sciences, P. Vityazand and V. Labunov, whose remarks and suggestions have contributed to a large extent to the preparation of the final manuscript. A large amount of typographic work was done by S. Gordienko, Y. Sizov and K. Haivoronsky. While writing the book, we used a number of open foreign and domestic sources, the results of our own scientific research, and the practical results from our

Preface

xv

experience in the development of modern microelectronic products, taking into consideration features of the studied topic (i.e., reliable information about results analysis of disasters and accidents in the USSR/the Russian Federation, the United States, and China can be rarely found in open access). That is why we have also used information obtained during personal meetings and negotiations with representatives of space industry from China and India, including Abdul Kalam (often called the Indian Korolev) before he was elected the President of India, and other competent specialists.

Introduction The uniqueness of this book’s subject is space and special-purpose (extreme) microelectronics, the element base of modern rocket-and-space technology (RST), and weapon systems and military equipment. To our knowledge, this is the first attempt in domestic scientific and technical literature to examine all the interrelated stages of development of RST electronic units, starting from development of the requirements for units and their electronic component base to the choice of technology basis for its implementation, methods of designing microcircuits and on-board control equipment of space and special application based on these microcircuits. The structure and order of the book are aimed at making complicated material easily comprehensible but not at the expense of its quality. Readers are presented with a small but sufficient amount of information to understand the subject, from the configuration and classification of spacecraft and their on-board systems, the results of statistical analysis of accidents and failures to peculiarities of choice and application of foreign-made electronic component base (ECB). The majority of the book dwells on aspects of designing microcircuits for space application, from the choice of production technology to methods of their design with regard to deep submicron features. In order to achieve this aim, the material is presented as follows. Chapter 1 is focused on peculiarities of selection and application of foreignmade ECB for construction of domestic spacecraft. General aspects and approaches to selection of such ECB are considered. U.S. and European Union (EU) regulatory documents limiting export of such components to Russia are analyzed, as well as ways and mechanisms to solve associated problems. Since procurement of foreign space-grade ECB is rather challenging, foreign industry-grade ECB (for industrial application) is widely used for development of radio-electronic equipment of space applications (REE SA). Features of application of such products in rocket and space technology are examined in detail; a range of necessary procedures is indicated that an REE developer shall follow to introduce the products in electronic units of designed REE SA. A separate section is focused on problematic aspects of choosing foreign-made ECB for REE used in strategically valuable domestic objects. Counterfeit products pose one of the major problems when selecting imported microelectronic products for REE SA. Notably, not only Russian developers face such problem. In fact, it has a global scale; there have been a number of cases in

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which electronic systems of U.S. and North Atlantic Treaty Organization (NATO) submarines and combat aircrafts, as well as space equipment of NASA and the European Space Agency had counterfeit (fake, cloned) microcircuits of low quality produced in China (such products are mass-manufactured in China). In recent years, a growing number of counterfeit products have been detected by Russian specialists as well, and in a number of cases, such products were proved to be an unambiguous cause of RST failures. The following classifications of counterfeit products are presented: pirate version (clone); the component does not comply with manufacturing standards of the original product; the component is not produced by a certified manufacturer; the component is defective or secondhand, but comes under the guise of a new component; and the component has invalid or counterfeit markings or documentation. Thus, the counterfeit products may belong to one of the following specific groups: reused (secondhand), remarked, defective (faulty), illegally (e.g., in excess of the contract volume) produced, cloned, illegally modified (reconditioned) products, and components with forged documents. The effective methods of detection of each category are provided. One of these effective methods, a special complex of electric and temperature testing, is examined in detail and examples from experience are given. Chapter 1 considers the peculiarities of selection and application of foreignmade processors and microcontrollers in domestic spacecraft for construction of high-performance and reliable on-board digital computer complexes (ODCC), both for payload and spacecraft platform. There is a detailed analysis of processor Leon 3FT (microprocessors UT 699 and GR 712) that was developed by Aeroflex and has been widely used in the U.S. and EU space industry since 2009. Its application options, qualification characteristics, architecture and hardware options, and features of programming are analyzed. A separate section is focused on foreign radiation-tolerant direct current (DC) converters for space and military applications, the import of which to Russia has increased by an order of magnitude in the past 5 years. The power supply system of satellite equipment must be adapted to a high clock frequency and a rapid load change on the power bus. Such DC/DC converters and stabilizers must have a transient response at the level of at least 10 A/μs to load change in the full range and the maximum deviation of the converter output voltage must be within ±5%; otherwise, any excess of the maximum allowable voltage of processor or programmable logic device (PLD) at such load changes can lead to instantaneous or latent failures of on-board REE microcircuits. Chapter 1 also presents a summary of international experience in the organization of manufacturing electronic components for spacecraft on-board equipment, since a feature of ECB SA is that its development differs from the roadmap of general-purpose electronics, which is oriented towards mass production, a short life cycle, and the fast replacement of product types. The features of organizing the development of ECB SA in the United States (the Department of Defense, Department of Energy, and NASA are involved in this process), Europe, Japan, and China are presented. Chapter 2 is focused on the peculiarities of the technological process of production and basic constructions of modern transistors and Schottky diodes used

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for designing and manufacturing microcircuits and semiconductor devices of space microelectronics. This chapter gives an insight to modern trends and prospects of modern microelectronics that developed in the field of the deep submicron. A growing priority is the problem of scaling geometric dimensions of integrated circuits, both reduction of linear (lateral) and vertical (parameters of basic transistor active structure) sizes which has spawned new, previously unknown mechanisms of failures of this microcircuit generation. Thus, the chapter considers peculiarities of production technology and obtained designs of submicron metal-oxide semiconductor (MOS) transistors. There is a general analysis of these designs, description of methods used most widely by large scale integration circuit (LSIC) designers to improve operation characteristics of MOS transistors for design rules of 90, 65, and 45 nm and less; the peculiarities, advantages, and main disadvantages of MOS transistors with silicon-on-insulator (SOI) structure are considered separately, as well as peculiarities of transistors with double, triple, and cylindrical gates and other types of transistor structures used in LSIC VC. A separate section considers peculiarities of the use of special transistor designs for analog applications as part of LSIC SA. Also, a separate section is focused on the design and technology features of manufacturing high-temperature Schottky diodes and their application as part of microelectronic devices: more than 50 versions of their design are presented together with corresponding remarks depending on the tasks they solve as part of certain microcircuits and discrete semiconductor devices for space application. Chapter 3 considers the main solutions to one of the most challenging issues of space microelectronics: reduction of power consumed by microelectronic devices of space application. This is an important issue due to an obvious fact that functionality and performance of on-board REE is constantly increasing, while the law of conservation of energy cannot be discarded. In Chapter 3, another kilogram (ton) of payload is required from the designers of rocket and space technology to reduce redundant functions, while minimization of the power consumed by electronic units requires various methods and techniques based on both microelectronic technology of ECB production and a whole range of unique circuit design methods. This chapter is focused on describing of these methods. The beginning of the chapter considers the main mechanisms of power dissipation in complementary metal-oxide semiconductor (CMOS) microcircuits most widely applied in spacecraft, as well as physical, circuit design, technology, and system (architecture) constraints that should be taken into account by designers and consumers of microcircuits for space application. Special attention is paid to interface microcircuits that ensure the functioning of various blocks, units, and elements of the on-board system as a whole, organizing the interaction of various spacecraft on-board systems and fast data exchange between such internal systems, as well as with external devices. The efficient operation of cutting-edge spacecraft on-board computer and control systems cannot be ensured without an advanced interface. The main elements of the interface include special microcircuits used to construct interface channels that feature a number of types, functional capabilities, circuit, design, and technology solutions, a system of electrical parameters, and peculiarities of application. They are united by the problem of minimizing power consumed

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during operation as part of on-board REE SA systems, as well as by operation conditions [high level of external noise, high values of switching (commutation) and load current, extreme electric loading, exposure to radiation, and mechanical stress]. The peculiarities of designing and applying interface microcircuits of the previous generation were examined in detail in Bipolar Microcircuits for Interfaces of Automatic Control Systems (1990) by A. I. Belous and O. Y. Blinkov. However, the new generation of interface microcircuits faces new problems and consequently requires new solutions; therefore, the reader’s attention is focused on the peculiarities of organizing low-power consumption modes in modern interface microcircuits mainly with serial data transmission, rather than parallel one. Chapter 3 considers microcircuits of low-power transmitter/receiver of RS-232 and RS-485 type that are most often used by developers of on-board REE, presents features of their structure and circuit design, and provides an extended example of designing a circuit of transmitter electric unit and temperature-independent reference voltage source. The main circuit design peculiarities of designing low-power integration circuit (IC) VC are examined in a separate section. Considering the wide application of memory elements (embedded memory) in interface (and other) microcircuits, the last section of Chapter 3 is focused on a detailed analysis of circuit design features of arrangement and application of the most often used basic memory elements (cells); that is, various kinds of D-type flip-flops. Considering the increased level of different kinds of noise generated on-board a spacecraft (orbital station, navigation satellite, interplanetary spacecraft), Chapter 3 also includes a special section focused on the detailed analysis of noise sources and circuit design methods of noise cancellation both at early stages of designing custom microcircuits and their application as part of the on-board REE SA. Chapter 4 focuses on theoretical and experimental analysis of exposure of submicron integrated circuits and semiconductor devices to ionizing space radiation. While the physical mechanism of the radiation effect on pre-submicron microcircuits has been studied thoroughly and presented in many domestic and foreign publications, certain information vacuum-formed around submicron design rules: different sources published completely opposite information, some of them even stating that submicron microcircuits should not be used in space equipment due to their assumed low tolerance to the ionizing radiation of outer space. This can be largely explained by stiff competition on the LSIC SA market as well as by purely economic factors: development of submicron technology at the 90-nm level requires not hundreds of thousands, but hundreds of millions of dollars and several billion dollars for the 45-nm level. Unfortunately, certain decisions were made on the basis of such misleading information by leaders of the domestic rocket and technology field who are decisionmakers in the sphere of ECB application in space instrument-making. Therefore, Chapter 4 thoroughly examines specific features and physical mechanisms of exposure of submicron LSICs (CMOS, bipolar, digital, and analog ones, memory circuits) to radiation, as well as the main methods of ensuring their radiation tolerance including recommendations on composition of testing devices, elements for experimental research on the effect of radiation on properties of silicon microcircuits, recommendations on applied equipment and methods of sample irradiation, and methods of measuring after radiation treatment.

Introduction

xxi

An advantage of this chapter’s material is that instead of assumptions on tolerance or intolerance to radiation of submicron LSIC basic designs, it provides actual results of experimental research (mainly conducted by domestic specialists, as well as by authors and prominent foreign researchers) on the effect of different kinds of radiation on properties of various microelectronic devices. Thus, Chapter 4 provides the summarized results of experimental research on effects of gamma radiation on properties of submicron MOS transistors, MOS capacitors, memory cells on MOS transistors, logic MOS IC, CMOS random acess memory (RAM), read-only memory (ROM), bipolar complementary metal-oxide semiconductor (BiCMOS) LSIC, MOS/SOI structures, and LSIC RAM on their basis. Considering the objective technical and financial problems faced by REE SA developers connected with inability to conduct full-scale tests (Semipalatinsk Test Site used to solve such problems during the time of the Soviets), the last section of Chapter 4 describes the peculiarities of application and physical justification of using proper simulation methods for researching radiation effects, as well as methods of predicting radiation tolerance of CMOS and BiCMOS microcircuits. Chapter 4 also presents specific methods (tested in domestic and foreign practice) to enhance tolerance of different classes of LSIC to impact of penetrating radiation (gamma, alpha, and beta radiation, heavy charged particles, protons, neutrons, and other kinds of ionizing radiation). There is a detailed description of radiation treatment, methods of measuring electric parameters of tested structures and typical samples of the main LSIC classes, composition and features of equipment, tools, and software used for these processes. Chapter 5 is fully focused on description of tested calculation and experimental methods of predicting and calculating levels of radiation tolerance of bipolar (digital, logic and analog), as well as standard CMOS integrated circuits. It also considers the main design and technology as well as circuit design methods of enhancing radiation tolerance of CMOS and BiCMOS microcircuits. Chapter 6 contains fundamental material focused on analyzing general aspects of designing submicron LSIC SA and based on them IC electronic units. The use of submicron technology (design rules of 90 nm and less) poses new challenges in designing both digital and analog CMOS LSICs. Some of these challenges have never arisen before, while others have, but now they are taking significance. When transitioning from 90 nm to 65 nm and especially to 45 nm, the designer faces new problems caused by a growing influence of electrical and physical effects connected with the high density of interconnections and high-density packing of transistors (dynamic voltage loss at resistance, antenna effects and effects of cross-coupling, growing influence of leakage currents, electric migration, and many others). Chapter 6 considers the modern trends of scaling, as well as associated problems and solutions to them. One of the main problems is the growing static and dynamic power consumed by the chip, which is caused by leakage currents. Recommendations are provided on how to control optimal distribution of dissipated power across the chip surface at the stage of designing. There is a detailed analysis of all main types of currents that are present in active and passive structures of the transistor (subthreshold leakage current, gate

xxii

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tunnel current, turn-on current, switching current), causes of their emergence, and equations for calculation of their values. Special attention is paid to the aspects of calculation and controlling the value of dynamic power in the structure of standard submicron silicon MOS transistor (the use of circuit design of units with a set value of switch time delay, proper account of signal distribution delay at interconnections and transition resistance of interlevel contacts, ways of reducing power consumption during switching, and methods of library optimization). Chapter 6 considers two problems that are of importance to developers: the impact of temperature on characteristics of MOS transistors manufactured using deep submicron technology (temperature dependences of subthreshold leakage currents, gate tunnel current, input and output current, junction currents), as well as influence of technological spread (fluctuations) on the main electric parameters of submicron MOS transistors. The deviation of characteristics of a device associated with the technology has always been a serious problem for circuit designers and process engineers. In technical slang, this phenomenon is known as the Yield Killer. To the surprise of researchers, Yield Killer in submicron technology actually “kills” the main performance characteristics of MOS transistors; the smaller the design rules are, the more difficult it is to cope with this effect. Fluctuations (random spread) of process parameters depending on their nature can be roughly divided into two big groups: global and local ones. Global fluctuations significantly influence all identical components (wafers in a reactor are subject to nonuniform heating depending on their location), and local fluctuations influence not only an individual wafer, but also an individual chip (nonuniform heating of a wafer in the center or at the periphery at high-temperature oxidation). Therefore, special attention is paid to influence of such technological fluctuations on leakage currents. In particular, it is shown that subthreshold current Isub (the spread of which is additionally determined by fluctuation of doping dose, gate dielectric thickness, channel length) is exponentially dependent on the major properties of the transistor (i.e., threshold voltage and gate tunnel current), and this dependence has a clear nonlinear character even in case of an insignificant increase of process parameters spread. Chapter 6 formulates specific recommendations on reduction of leakage currents in MOS transistors manufactured using submicron technology, lists the main constraints associated with decreased linear dimensions, and provides specific recommendations on methods to minimize leakage currents during microcircuit designing both at system (architecture), logic, and circuit levels of project implementation. Chapter 7 is fully focused on specific aspects of designing microcircuits for space application based on silicon-on-sapphire (SOS) and SOI structures that are one of the fastest developing fields of radiation-tolerant ICs. This chapter may qualify for fundamental analysis of the development of this microelectronic technology field, since it contains a solid theoretical part (analysis of damage process in silicon (and polysilicon) caused by irradiation with gamma-quantum impulses, description of radiation effects, their complexes and clusters, physical mechanisms determining the impact of radiation exposure on conductivity of dielectric layers, properties of the Si/SiO2 interface, and others).

Introduction

xxiii

There is a comparison of radiation properties of SOI ICs manufactured in different processes, an analysis of ways to increase stability, and reliability of the structures with different dielectric layers. We believe that an undeniable advantage of this chapter is a detailed description of physical phenomena and processes occurring in SOI LSIC under exposure to various kinds of ionizing radiation (single-event upsets, single-effect latch-up, single-effect burnout, single-event gate rupture, single-event snapback of the singletransistor latch-up), as well as impulse irradiation effects and full dose effects. All the conclusions and recommendations provided in the chapter are substantiated with the results of experimental research on samples; the composition of test elements is presented, as well as experimental results for all the basic elements of LSIC (transistors of various configurations, resistors, diodes, capacitors). The chapter concludes with description of the most widely applied design and technological methods as well as circuit design methods to increase tolerance of SOI ICs including charge stabilization in the buried dielectric of SOI structures (by means of implantation of hydrogen ions and fluorine), as well as peculiarities of formation in SOI structures of MOS transistors with ring gates, short-channel SOI MOS transistors, and self-aligned SOI MOS transistors with ring gate. A separate section is focused on summary analysis of design and technological methods of increasing tolerance of SOI structures to exposure factors of outer space that are proposed in U.S. open-access patents. Another section considers aspects of increasing tolerance of SOS and SOI LSIC RAM to hazardous pulsed ionizing radiation (analysis of radiation defects causing failures of basic elements and microcircuits, description of methods and hardware implementation of radiation experiment, ionizing effects in semiconductor layers of SOS and SOI structures, analysis of ionizing reaction of SOS MOS transistor and pulsed ionizing radiation, local ionizing effects in dielectric areas of CMOS SOS MLSIC and others). Chapter 8 focuses on peculiarities of designing system-on-chip (SOC) and system-in-package (SIP) used for on-board REE SA, weapon systems, and military equipment. As defined, SIP is a combination of several different chips of digital logic, memory, interface components, passive components, filters, and antennas in a standard (or specially designed) ceramic and metal or other special package. The chapter considers specific features of designing SIP and SOC and compares their main parameters and design processes. Thus, it is shown that the cost of implementing a standard SOC project is 7 to 10 times higher than that of SIP; it takes 6 to 9 months to implement SIP, whereas development of SOC takes 18 to 36 months. SIP can be developed by a standard team of designers, while SOC requires a bigger number of trained highly qualified engineers; furthermore, it takes 1 to 2 months and 12 to 20 months to debug a SIP and SOC prototypes, respectively. Peculiarities of designing RF modules in SIP are considered separately. Thus, parameterized cells (P-cells) for passive RF devices are a standard component supplied to the CAD market, but they usually do not take into account characteristics of a specific package type chosen by the designer. At the stage of drafting, the developer has to find a number of out-of-the-box solutions (e.g., decide whether to locate required inductance on a chip, where it takes up valuable space, or on the substrate, board, package element).

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A separate section considers some other features of deep submicron technology that shall be taken into account during designing specialized microcircuits for SOC and SIP. In particular, this concerns the use of CAD to take into account the impact of destabilizing factors on the speed of digital microcircuits. Thus, the impact of technological fluctuations and impulse noise on output parameters of digital microcircuits can be disregarded in projects with design rules higher than 0.25 μm and up to 1 million gates. However, deviations of actual values from calculated ones are significant for the 0.18-μm designs. Maximum values of impulse noise in power circuits reach tens of percentages and the greatest amplitude is shown by components with frequencies in the range of 30 to 300 MHz (these are the frequencies that are most often used for internal chip synchronization). The chapter shows that it is sufficient to consider only the capacity of interconnection conductors when calculating dynamic parameters for the 0.25-μm design rules, whereas it is necessary to consider ohmic resistance of communication lines for the 0.18-μm design rules and inductance, and parasitic resistors for 90-nm design rules significantly increase the time needed for calculations. There is a detailed analysis of the peculiarities of designing the layout of chips used for SOC and SIP, as well as recommendations for minimizing various parasitic effects. For example, in order to eliminate the antenna effect (static charge is accumulated on conductors during plasma etching and polishing, which can lead to a breakdown of MOS transistor), it is recommended to limit the maximum area of internal metallization of connecting bus. To balance current density in conductors and reduce thermomechanical damage after chemical and mechanical polishing, using fictitious elements is recommended: fictitious conductors in wide dielectric gaps and fictitious dielectric gaps close to wide conductors. Chapter 9 considers the main methods of rejection of silicon microcircuits with hidden defects during mass production. The proposed methods allow the developers of electronic devices to enhance reliability, in case foreign-made ECB of space grade or industrial grade cannot be procured, to construct prototypes using domestic microcircuits of dual or special purpose that have undergone additional testing in accordance with considered methods. This concerns application of special statistical methods (sensitivity factors of output parameters, operating ranges), model of mathematical processing of forced test results, detecting potentially unreliable microcircuits by using forced electrostatic discharge, special modes of burn-in procedure, and special rejection criteria according to dynamic stress.

CHAPTER 1

Considerations for Selection and Application of Foreign Electronic Component Bases in Designing Domestic Spacecraft

1.1  General Problems of ECB Selection for REE of Space Application All national programs, from simple programs (installation of a communication satellite: navigation) to super programs (manned mission to Mars), are based on building blocks, which are represented by the electronic component base (ECB). This also occurs in the development of a wide range of radio-electronic equipment (REE) for the consumer and industrial purposes (televisions, mobile phones, personal computers, industrial controllers, automated control systems of numerically controlled machines, and the like), but for ECB of special and space applications, it is of paramount importance. It can be said that the ECB in rocket and space technology is fundamental and determines the basis of national security of any space power. In certain political and economic conditions, these national programs (and even more so for super programs) are a fundamental part of which is ECB itself and may eventually be a sort of colossus with feet of clay instead of silicon feet. In a typical example, currently many Russian enterprises produce on-board equipment for the global navigation system GLONASS, which quite successfully competes with the American Global Positioning System (GPS). At the same time, those enterprises use ECB produced in the United States, and in most cases permission is required by the U.S. Department of State, which may or may not allow the delivery or, even worse, to allow for a complete set of experimental and prototype samples and then cancel the resolution (without explaining reasons) for the supply of the same ECB for a complete series of products. It should be noted that the high requirements of the customer for the technical characteristics of the spacecraft and the term of active life under the conditions of exposure to space factors come into conflict with capabilities of modern Russian industry to produce ECB for space applications. As a result, the developer of spacecraft on-board devices has only two ways to produce ECB.

1

2

Considerations for Selection and Application of Foreign Electronic Component Base

The first approach is to conduct further complex testing of domestic ECB. It includes an incoming control, a screening test, diagnostic nondestructive testing, and selective destructive testing. Apart from that, each lot needs to be tested for resistance to radiation effects and to the effects of heavy charged particles. For each type of additional tests, special techniques are either developed or under development, equipment is purchased, and staff is trained. A group of companies has been formed, which regard such tests as their basic and profitable business. There is a paradoxical situation: usually the cost of the selecting domestic ECB exceeds the cost of the component by 1.5 to 3 times [1]. However, this approach is flawed in principle. Efforts and funds are aimed not at achieving adequate quality of domestic industrial processes, but at sorting already sold products in the hope that some of them would be suitable by accident. In addition, the possibility of nondestructive methods is still limited and destructive analysis applies only to a certain sample of a lot. The result of all this work is that only a slightly reduced probability of failure of ECB is selected from the lot. Unfortunately, experience in operating the spacecraft in orbit confirms this. There have been quite a number of failures of equipment, which had selected components. Only multiple redundancy helps, although it reduces spacecraft functional characteristics. The second approach involves the use of foreign-made ECB. Its use is growing quickly and steadily. With regard to space-grade ECB, it is more appropriate to use the term “ECB made in USA” instead of “foreign-made ECB,” because the United States, in this area, has almost an absolute monopoly. Even European satellite companies are dependent on them. American ECB for space applications has many advantages: proper radiation tolerance and resistance to heavy charged particles, and high reliability, which allows one to avoid unnecessary redundancy. However, there are two major drawbacks: the high price and, more importantly, the complexity of procedures for the export of ECB of such grade from the United States. It is uncertain whether the U.S. Department of State will issue permission for the delivery of a particular lot for a specific end user. It is also problematic to create a reserve because ECB is closely connected to a particular program. These issues, as well as adherence to the principle of maximum efficiency at minimum cost and risk acceptability, have led to the need to use imported ECB for commercial application in spacecraft on-board equipment. At the same time, measures are taken to increase the likelihood of long-term ECB work under the exposure to space factors, such as those described in the first approach. The task is complicated by the fact that the items acquired from the open market do not have the required specifications; therefore, some equivalent of technical requirements needs to be produced for each ECB type on the basis of independent research. Because in this case such terms as a “lot” or “uniformity of ECB groups in terms of composition and materials” and the like are not applicable and there is no strict binding to a specific manufacturing line, the results of studies of individual parts do not necessarily apply to the whole group. All of this involves the radiation tolerance, which has to be tested on individual samples from each group of purchased ECB in the hope that the part soldered to a flying device will not be worse than the tested one. However, there are no guarantees. More sophisticated techniques are under development and more advanced test equipment is bought, but the principle

1.2  Restriction on Export of Foreign-Made Electronic Components to Russia

3

is the same: ECB is bought, and then time and money are spent to reduce the risks associated with its application. Here is a typical example from experience [2]: one of the numerous batches of imported ECB worth 1.4 million rubles ($24,000 USD) required certification worth about 2 million rubles plus 7 million rubles to check the radiation tolerance. This situation is advantageous to different engineering and technical centers, but, in general, it is the dead end for the industry.

1.2  Restriction on Export of Foreign-Made Electronic Components to Russia The enterprises of the Roscosmos Federal Agency have already experienced certain sanctions from the U.S. Department of State, which controls overseas supplies of products for space and military applications [1, 2]. The first refusal of electronic component purchase followed the scandal connected with Edward Snowden, a former employee of the U.S. National Security Agency, whose extradition was requested by the Americans from the Russian Federation. In particular, they banned the supply of components for the spacecraft Geo-IK-2, calling it a military one, although Geo-IK-2 can hardly be considered a military satellite. The purposes of the spacecraft include high-precision geodetic measurements, covering the needs of the Russian science in the updating of the Earth model and specifying its geophysical parameters. The constellation consists of two spacecraft. The first satellite Geo-IK-2 was launched in December 2010, but due to the abnormal operation of the upper stage, it was put in wrong orbit. In this regard, the launch of the second spacecraft was postponed, and to replace it, the ISS Reshetnev started constructing a new satellite version based on space-grade electronic components in accordance with the new regulations. Exports of American (including partially American, that is, those tested or adjusted in the United States) parts for the systems of military and dual purposes are regulated by the International Traffic in Arms Regulations (ITAR), a set of rules established by the U.S. government for export of defense-related goods and services. In accordance with the rules of ITAR, export of military (for use in military systems) and space-grade (radiation-resistant components) ECB to Russia is possible only with the permission of the U.S. Department of State. It should be kept in mind that the ECB import in Russia is worth more than $2 billion annually (in the space industry only). Therefore, ECB import from China is considered as one of the options. At the time of this writing, Roscosmos did not use ECB from China; therefore, its quality level is not known for certain. At the same time, China’s space program is developing rapidly, and the failure rate of Chinese space industry products in recent years has been lower than that of Russia. Americans have long refused to deliver military and space-grade ECB to China for quite a well-founded fear that they will be duplicated. Therefore, China has been forced to move to its components, and Chinese experts quickly solved this problem: China now uses up to 98% of the components of its own production in its satellites, which is a good example and a stimulus for the development of the domestic microelectronics.

4

Considerations for Selection and Application of Foreign Electronic Component Base

It should be noted that the ground segment of GLONASS has already experienced the U.S. sanctions, although this was not a parts issue. Therefore, domestic developers of REE for space applications should know and take into account all the details of the existing rules and regulations of international regulatory and legislative framework governing all phases and stages of acquiring imported ECB. 1.2.1  Restriction of ECB Exports from the United States

Foreign manufacturers offer a wide range of components and products with required characteristics. However, due to international politics involving conflict in the Ukraine, foreign governments imposed new restrictions on the supply of necessary components to Russia. Thus, obtaining these components for space or military applications is becoming increasingly more difficult. Thus, both customers of REE for space application, electronics developers, and departments and agencies responsible for the acquisition of foreign-made electronic components need to know all of these restrictions, as well as the procedure for their consideration in the design and implementation of orders for their delivery. In this connection, particular attention should be paid to dual-purpose ECB. Because the dual-purpose products combine both commercial technologies and requirements for military programs, over the last 15 years this field has effectively developed advanced technology and at the same time covered the needs of defense programs. Manufacturers of dual-purpose products become participants of the two markets, so that spending on research and development of products is reduced, as the military and commercial products can be manufactured using the same production line. The main technological trends in the ECB market include miniaturization, increased performance, functionality and density of chips, integration of various electronic and radio components (ERC), transition to new materials, and transition to higher-frequency ranges. Increased requirements for ERC for the space industry and military purposes can also be noted. Primarily they concern resistance to the destabilizing factors, reliability, fault tolerance, and the life cycle. The end use of the product on the world ECB market became the decisive factor for component selection, and its tracking became part of the export control of manufacturing countries. Requirements for components are based on standards that have been developed both in the United States [NASA, the U.S. Department of Defense (series MIL-STD, MIL-SPEC)] and international organizations such as the European Space Agency. Assessment of compliance with the requirements is carried out in the framework of international systems for certification. As a world leader in the development of new technologies, the United States closely monitors its dissemination in the world. As today’s chips are the basis for building efficient military equipment, access to their manufacturing technology and delivery is strictly regulated. Government regulation of exports from the United States came after World War II, when technology became a critical factor in U.S. military strategy. ITAR was approved. In 1976, the Arms Export Control Act (AECA) [2] was adopted, which contained the first restrictive measures. In particular, Section 38 of the Act obliges to provide a list of exported weapons and military equipment and the rules

1.2  Restriction on Export of Foreign-Made Electronic Components to Russia

5

for their export. The system controlling the technologies and weapons exports in the United States refers to a presidential-parliamentary relation; in accordance with the AECA (written and enacted by the U.S. Congress), the executive branch headed by the U.S. President implements government policy in the sphere of military and technical cooperation and regulation of export and import of military goods, while the Congress performs legislative, restrictive, and controlling functions. It is important to know that the responsibility for regulating the export of technology and military products in the United States is divided among several government departments: Department of Defense, Department of State, Department of Commerce, and Department of the Treasury. There are several lists of products associated with this regulation. The most prominent ones are U.S. Munitions List (USML) and Commerce Control/Critical Commodities List (CCL). The functions of the Department of State include implementation of programs of military aid, promoting arms sales to foreign countries and authorizing transactions concluded between the U.S. Department of Defense and other countries. For this purpose, the Department of State is responsible for licensing arms exports and the preparation of periodic revisions of USML. The Department of Defense directly implements arms exports. The Department of State is responsible for approving sales according ITAR list on the basis of AECA (22 U.S.C. 2778). ITAR paragraphs are consistent with the relevant paragraphs of USML [3]. The Department of Defense (DoD) is guided by the Master Urgency List (MUL), which is implemented in the first place. The Bureau of Industry and Security (BIS) of the U.S. Department of Commerce is responsible for regulating the export of dual-purpose technology. In this process, the Department of Homeland Security, the Department of the Treasury, and several other departments take part. On the basis of Export Administration Regulations (EAR), the following exports are governed: ••

Radiation-tolerant ERC;

••

Electronic components, such as microcontrollers, processors, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and programmable logic devices (PLDs), with the extended temperature ranges (−55°C... 125°C, below −55°C, above 125°C);

••

High-voltage and high-speed processors (from 8 bits and capacity of 2.5 MSPS);

••

Radio-electronic components, particularly SHF components (depending on the power and frequency);

••

ERC for the construction of radio systems with implemented cryptographic functions (e.g., system-on-chip microcontroller and RF transceiver).

In addition to the components, the export of software, technology, and products produced with the use of these components and technologies in the United States or other countries, is also regulated. Almost all countries in the world experience certain restrictions on exports from the United States, depending on the types of threats that, according to the U.S. Department of State, a specific country potentially poses. In EAR there is a list of

6

Considerations for Selection and Application of Foreign Electronic Component Base

countries with which any transactions in general are prohibited (Part 746, Embargoes and Other Special Controls). In addition, part 744 (Part 744 Spir, Supplement No. 4 to Part 744, Entity List) defines a list of organizations and individuals who are to obtain permission for delivery of any goods. There are rather significant limitations on the ECB supply to Russia, including the Ministry of Defense, Rosatom, Roscosmos, and research institutes. ECB suppliers are required to have basic information about the final recipient of provided ERC and the types of products made from them. When ECB are exported to Russia, all parties to the contract must take measures to strictly control receiving, transportation, storage, and use. Thus, upon arrival in Russia and after the customs clearance, the goods must be placed in the supplier’s warehouse in a special protected area with limited access. Documents for each transaction must be kept at least for 5 years. Every 6 months, the exporter must submit a report to the Bureau of Industry and Security, and the returned components, including the defective, damaged, or desoldered ones, are sent to the U.S. manufacturer. Both electronic components manufacturers and suppliers are responsible for EAR compliance. Manufacturers ensure transfer responsibility for the distribution of their products to the suppliers by including clauses on mandatory observance of U.S. legislation in the supply contracts. Otherwise, the manufacturer reserves the right to unilaterally terminate the contract with the supplier. The violators, being under U.S. jurisdiction, may be obliged to pay substantial fines, they may have their foreign trade licenses revoked, and the officers of such companies may be prosecuted. The violating companies (end users, suppliers as well as individuals) who are not under U.S. jurisdiction may be entered on the restrictive EAR lists. In this case, their access to U.S.-made products becomes more difficult, because at every purchase their supplier will be obliged to obtain a special license, which is often equivalent to the closing of the business. Therefore, each manufacturer has its own system to monitor the distribution of products. According to EAR, such a system also includes classifications of products and export destinations. BIS has developed a set of documents on the classification of goods, licensing and execution control of Export Administration Regulations (EAR). Part 774, the Commerce Control List, contains a complete list of goods subject to export control. It includes 10 categories of products, including category 3 (electronics), Category 5 (Part 1—Telecommunications, Part 2—Information security). To obtain a license for component export, the exporter has to apply to the BIS with information about the ERC, the product, the final product of the company, the end customer, and the supply chain. The application is assessed and examined in the BIS from the point of view of the danger of propagation of the component in the indicated direction with the assistance of technical experts and professionals from the security services. The term of consideration of the application is 3 to 4 months, and the period of validity of the license, 1 to 2 years. It should be emphasized that for the majority of manufacturers of RF and SHF components, the details section in each USML category is important. As a rule, this category includes missiles, launch equipment, and spaceships. However, it includes a provision stating that all components used in them, specially designed or modified for military use, are in the USML category. To determine whether a product is not intended for military purposes, the Department of State checks the

1.2  Restriction on Export of Foreign-Made Electronic Components to Russia

7

development or modernization of the ERC based on customer specifications. However, experts may even ban the export of commercial ERC without explaining the reasons for refusal [1]. Currently, the law in some cases allows the export of certain goods without obtaining the licenses if they contain parts subject to licensing, but not more than 25% of the total value of the goods. It is also possible to re-export some goods to a foreign partner, if the U.S.-controlled technology accounts for less than 25% of the total value of the product. However, in practice, this is not always implemented. The algorithm for obtaining an export license (Figure 1.1) is a turn-based commodity classification [1, 4]. First, it is determined whether the products have Export Classification Control Number (ECCN). Also, exceptions from the list requiring licensing (EAR99) are analyzed. Note that products classified as EAR99 may require an export permit or may be prohibited from sending embargoed countries or parties.

Figure 1.1  Algorithm for obtaining an export license.

8

Considerations for Selection and Application of Foreign Electronic Component Base

The application specifies the destination and is enclosed with copies of invoices, bill of lading, or other documents that accompany the goods to the final destination and the consumer abroad. The items are controlled before the shipment, and the U.S. Customs Service has the right to inspect the goods delivered to the docks and to confiscate them. After shipping, the companies provide statements about the movement and use of the goods, and the authorized government agency may send a representative to check the products at the place of receiving and application. Former U.S. President Barack Obama’s administration implemented the plan to modernize export control regulation. Its goal was to transition to a more effective monitoring and control of production and transfer of technologies that fall under the classified category, and at the same time to strengthen the cooperation with partners. A number of technologies have been transferred to civilian purposes, such as radars for civil aviation. At the same time, provisions are made for tighter export licensing procedures for equipment and dual-purpose technologies, especially for small and medium-sized companies, for obtaining more information about the importer and its guarantees regarding the right of the inspection of the U.S. Department of Commerce to test equipment after export. The question of creating a single expert agency on a single information platform was discussed in [5]. In general, despite the emerging liberalization of foreign trade trends, the United States continues to tighten export control policy. All these factors must be taken into account by the time of determining specific technical requirements by the RST customer. 1.2.2  Restriction on ECB Exports from Europe and Other Countries

Government control of state military and technical cooperation is widespread in most of the world and is typical in countries exporting military products such as Austria, Switzerland, Italy, Sweden, Portugal, Belgium, and others. The United Kingdom is the world’s second greatest exporter of weapons after the United States. In 2007, the two countries signed a U.S.-U.K. Defense Trade Cooperation Treaty (DTCT). The purpose of this treaty was optimization and improvement of defense export processes, security and defense of both countries, acceleration of the delivery of U.S. production facilities in the United Kingdom, and promotion of cooperation between the military-industrial complexes. In accordance with the DTCT, the exporter must be registered at the U.S. Office of Defense Trade and must obtain an export license (or other form of export authorization) in any U.S. government agency. The export goods consignee must be a member of the British Commonwealth. All necessary documents for such exports should be kept by both the exporter and the consignee and made available upon request of the U.S. government. The French public administration system in the field of arms exports and military equipment of France includes a multistage decision-making mechanism for military goods exports. The Interdepartmental Commission for the Study of Military Product Export provides the necessary decisions on the production and supply of arms and military equipment to foreign countries. In carrying out foreign trade transactions involving military products, the Ministry of Foreign Affairs monitors compliance with the foreign policy interests through the issuance of appropriate authorization, based on which the Ministry of Economy and Finance, through the

1.2  Restriction on Export of Foreign-Made Electronic Components to Russia

9

General Management of Customs and Indirect Taxes, issues a permit for the export of military products abroad. In Germany, in accordance with the law On Arms Control of April 20, 1961, manufacture, use, storage, acquisition, transfer, and transportation of weapons considered for export are carried out on the basis of a federal government export license. Israel has a well-developed defense industry, but the United States has blocked the sale of Israel’s most advanced weapons that have U.S. components used in military and space technology. 1.2.3  International Export Control Organizations

Along with the legislative restrictions on U.S. exports and those of other countries, there are international organizations that control export. In 1949, the United States initiated the first international export control procedure, Coordinating Committee for Multilateral Export Controls (CoCom). Wassenaar Agreements were created to replace CoCom in 1995. The structure of the organization includes 23 countries, including NATO countries and Russia, with the aim: ••

To ensure greater transparency and accountability in relation to the transfer of arms and sensitive goods and technologies;

••

To prevent the supply of goods and dual-purpose technologies for military purposes to a country, the policy of which disturbs the world community;

••

To facilitate the exchange of information and the possibility of coordinated national policies in the field of export control of dual purpose goods and technologies.

At the same time, Wassenaar Agreements are not intended against specific countries, do not impede the implementation of fair trade, and do not infringe upon the rights of states to acquire legitimate means for self-defense (Article 51 of the UN Charter). The European Defense Agency (EDA) is responsible for the defense capability of the European Union (EU) and the development of EU military technologies. The EDA believes that combat capability is based on digital technologies and wellcoordinated functioning of all links of the information chain. This requires new solutions in the field of RF and SHF engineering. EDA supports the development of the most advanced technologies in the field of military electronics and radio electronics and also controls their nonproliferation [6]. All things considered, we can draw only one conclusion: under the existing constraints, the domestic space industry equipment should be based primarily on the competitive domestic parts base, which requires corresponding state programs to support the microelectronic industry. The use of unlicensed imported products (industrial-grade ECB in equipment for space and military purposes) is undermined by several factors. Firstly, reliability and radiation tolerance guaranteed by a manufacturer are insufficient. Secondly, the costs of additional tests and certification of these components are commensurate with the development and manufacturing of specialized LSICs. For the

10

Considerations for Selection and Application of Foreign Electronic Component Base

equipment of the aerospace and military purposes that requires the purchase of certified military and space-grade ECB from certified suppliers, performance monitoring and testing must be in accordance with Russian requirements [1]. Testing of all parameters of imported ERC at domestic testing laboratories is not always possible, because there is no access to ERC technological information. ERC import requires justification of the purchase of licensed components. If the end products are designed for specific operating conditions or for particularly demanding applications (medical, life-support systems), they require a thorough justification of intended purpose. Correct classification of products supplied, comprehensive information and registration of all required licenses and permits are necessary conditions to ensure ERC supplies. At the time of this writing, only few positive trends of lifting ERC export restrictions can be discerned. For example, new aspects of ECCN allow deliveries to Russia of high-speed ADCs with a conversion rate of up to 200 MHz with 12 bits and up to 125 MHz with 14-bit word length. The prospects of delivery of SHF components and assemblies with frequencies up to 26 GHz are opening.

1.3  Peculiarities of Application of Foreign-Made Industrial ECB in Rocket and Space Technology Let us consider the main trends and features of the application of the latest models of foreign ECB in rocket and space technology and related industries that have no domestic analogs in the class of space and military components existing in the Russian Federation, and try to formulate the basic practical advice on choice of elements of the projects, taking into account the evolution of technology and the market of modern electronic components. The need to use a modern foreign-made industrial electronic component base in the rocket and space technology exists due to a number of objective factors. In the past 20 years, there has been a radical redistribution of the market of electronic components for military and space applications, the amount of which is estimated at about $2.0 billion per year. The share of space is only about 1% of the global ECB market of 300 billion. Most manufacturers of ECB do not have the economic incentive to participate in the military and aerospace business. The projected financial gains are too small; the requirements for quality and reliability are too high. Thus, with the development of spacecraft of the Constellation series (England), which applied the most modern technology and a large number of specific space requirements, the advantages of industrial-grade ECB became more necessary and obvious. The pioneers of the use of industrial-grade ECB are the Iridium and Globalstar spacecraft programs (United States). When using industrial-grade ECB of foreign production in similar Russian projects, priority should be given to stable, large manufacturers of space equipment with streamlined precision manufacturing technology. This is proved by the fact that the cost of building a modern factory for the production of microelectronic circuits with 0.35–0.25-µm design rules reaches $2 to 3 billion, and for the design rules of less than 45 nm it is more than $5 to 6 billion. In the absence of developed domestic market and experienced managers as well as in the existing conditions of the world market division, the economic benefit is

1.3  Peculiarities of Application of Foreign-Made Industrial ECB in Rocket and Space Technology 11

unlikely even in the case of a successful launch in Russia of a semiconductor factory specialized in space applications and the full state support. However, the complexity of the selection process, reliable testing, and ensuring long-term production and repair of REE with foreign-made ECB of industrial grade is, in most cases, compensated with its benefits. It is necessary to take into account the fact that the time between foreign-made ECB produced by new technologies is released and taken out of production is steadily declining. This fact is reflected in the features of REE design and manufacture considered below, sets goals for the improvement of test equipment, and brings about changes in the planning of long-term REE production. The evolution of foreign-made ECB changes REE developers’ idea of the composition and structure of the product. When the developed object is constructed from previously developed units, this eliminates or minimizes the potential for design improvements. In this situation, there may be a lack of foreign-made ECB and the most important elements of the heritage equipment may not be suitable for the required modes and characteristics: different supply voltage and higher operating frequencies, which is characteristic of the accelerated evolution of foreign-made ECB during changes in ECB chip technology. This situation is illustrated in Figure 1.2, where the technology located above are novel and more promising in com-

Figure 1.2  Reduction of the life cycle of foreign-made ECB produced by the latest technology.

12

Considerations for Selection and Application of Foreign Electronic Component Base

parison with those located below. For example, when the microcircuit speed is increased, problems connected with signal delay in connectors and boards emerge. New types of packages require redesigned layout of printed boards and the use of other connection solutions, as well as changes in production processes. Development of foreign-made ECB continues, and its life cycle changes too: it is reducing for future generations of foreign-made ECB, as shown in Table 1.1. The average manufacturing time for the next-generation, foreign-made ECB is given in Table 1.2. Memory units illustrate changes in the foreign-made ECB life cycle (Figure 1.3) including changes in technological standards of memory capacity, types of memory, type of package, and the supply voltage during the period from introduction to discontinuation; the useful life of each generation of microcircuits is 2 years. Table 1.3 describes the stages of the foreign-made ECB life cycle in terms of all market participants: manufacturers of foreign-made ECB and competing factories producing similar parts, as well as data describing the processes of component production. Changes of cost over time can be observed as reaction to production development and decline. The development of production and economic life cycle of production determine which items are currently beneficial to use in REE with the greatest possible functionality and which items should be excluded from the list of components used in the development of new models of electronics. Any discrepancy between these market requirements could jeopardize the implementation of specifications or make REE uncompetitive. The reason may be the increased production time due to problems with the supply of legacy items, and the result is the production of outdated models of REE, the functionality of which is lower than that of its competitors operating more efficiently. A well-known dependence formulated by U.K. Components Obsolescence Group (COG) can be used,

Table 1.1  Average Life Cycle of Foreign-Made ECB Period of Complete Obsolescence Category of ECB of Foreign-Made ECB (Years) Foreign-made ECB of military >12.5 and space grade* Foreign-made ECB of industrial Vtn and Vjn < Vtp, where Vtn and Vtp are threshold voltages of n- and p-channel transistors correspondingly. Thus, the lower the difference between these values, the lower the through current is. 2. Values of through current are inversely proportional to the load capacitance CL. In the case of absence of the capacitance, the current value is maximum, but the current reduces with the growth of load capacitance. 3. Through current value is directly proportional to the duration of input signal edges (i.e., the longer the edge, the bigger through current is). To simplify the calculations, through current will be regarded as additional capacitance CSC, which is parallel to CL. Value of this capacitance may be calculated using a simple formula:



CSC =

t SC I peak Vdd



(3.9)

where Vdd is power voltage, Ipeak is the transistor saturation current, and tSC is through current flow time. This allows using the above formula to evaluate dynamic power. Power dissipated by CMOS circuit as a result of through current flow may constitute from 10% to 60% of the total dynamic power. Its value depends on such parameters as volt-ampere properties of transistors (cut-on and cutoff voltage of transistors), duration of front and back edges of input signal, load capacitance, and power voltage. The exact formulae for calculation of through currents and dissipated power will be provided in the next section. Statistic power in CMOS LSICs is dissipated, when the logical element is in some fixed state (0 or 1), and its value is determined by the value of leakage current of the MOS transistor channel, reverse currents of p-n-junctions, and loading currents (Figures 3.13 and 3.14). Ideally, the CMOS element does not consume power in the static state (i.e., the current does not flow through it), although in actual circuits the channel leakage current value constitutes a few picoamperes. Figure 3.13(a) shows the direction of current flow through the closed channel of a transistor. It exponentially depends on the value of the threshold voltage and linearly depends on the level of input signal, geometrical sizes of transistors and

3.3  Main Sources of Power Dissipation in CMOS LSICs

135

Figure 3.13  Static currents of CMOS circuits: (a) channel leakage current isub; and (b) p-n-junction reverse current irev.

Figure 3.14  Static currents of CMOS circuits: (a) circuit wired OR; (b) output with open drain, and (c) circuit with resistive output loading.

circuit layout, temperature (if temperature rises, the current doubles every 8°C to 10°C), and used technology. The other leakage current source is the reverse current of p-n-junctions, which are formed between different CMOS areas of integrated circuit [Figure 3.13(b)]. The reverse current value depends on the used manufacturing technology, p-n-junction area, temperature, and offset voltage and usually constitutes few picoamperes. As the aggregate value of leakage currents is 105 to 106 times smaller than that of dynamic currents, they are generally not taken into account. In such cases, when it is necessary to take into account the power, dissipated due to leakage currents, the following simplified formula can be used:

Plesk = Vdd NKd Ileak

(3.10).

where Vdd is the power voltage, N is the number of transistors, Kd is the empiric coefficient that takes into account features of applied technology, and Ileak is the aggregated leakage current of one transistor. In some cases, such as circuits with open drain, wired OR elements, or resistive load of circuit outputs, CMOS circuits can consume current in static mode (Figure

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Peculiarities of the Technological Process of Production

3.14). Then current value and, correspondingly, dissipated power depend on the logical state and resistance of the load. For example, in wired OR logic [Figure 3.14(a)] or open-drain circuits [Figure 3.14(b)], the current flows in state 0 only. In state 1 it equals zero. In circuits with resistive load, the current flows both in the state of logical 0 and in the state of logical 1 [Figure 3.14(c)]. In general, power dissipated as a result of direct current flow is determined by the formula:

Pstat = Vdd I stat

(3.11).

The following formula can be used to take into account power change depending on the logical state:

0 1 Pstat = p (0) Pstat + p(1)Pstat



(3.12).

where p(0), p(1) is probability to find the circuit unit in states 0 and 1, corre0 1 spondingly; Pstat , Pstat is the power, consumed by circuit unit in the states 0 and 1, correspondingly. It is not recommended to use output resistive load when using CMOS technologies for device designing. If this cannot be avoided, it is necessary to increase load resistance value, reduce power voltage, or minimize the possibility of the circuit being in such logical state, in which current voltage is the highest. As shown above, the main contribution to the dissipated power value is made by two current components that are either flowing through complementary transistors directly from the positive power input to the regular bus or charging (discharging) equivalent to output capacitance (load capacitance). The two components must be taken into account both for the analysis of static value, and dynamic value of power consumption by CMOS inverter. In technical literature, the dissipated power component resulting from through current flow in the circuit positive power input-open transistors-common bus is sometimes called capacity of dissipation of shorted (conducting) inverter, and power component, conditioned by the processes of charging-discharging of loading capacities, are called the switching power of the inverter. Before proceeding with a detailed analysis of these components of power, several additional remarks should be made. As stated above, the dynamic component of total power of CMOS inverter consumption is the determining one, and its value is proportional to the product of load capacitance by power voltage squared. Consequently, the reduction of voltage values Vtn and Vtp is an evident way to reduce total dissipated power, although it is known that a rigid link exists between threshold voltages and minimal threshold of voltage potential value, conditioned by fundamental physical constraints. For example, these parameters in aggregate considerably influence delays of inverters switching, consequently influencing performance (operating frequency) of the designed CMOS LSIC. The lowest thresholds of transistor switches are recommended regarding CMOS inverter speed, However, in the case of very low threshold values, the second component of the total dissipation capacity, static consumption power, increases as a result of the above mentioned problem of subthreshold currents. Thus, in each specific case of designing CMOS LSIC with reduced power consumption,

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

137

it is necessary to choose compromise solutions to the complex problem LSIC structure- switching thresholds-power voltage-performance.

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption 3.4.1  Basic Logical Synthesis of CMOS Microcircuits with Reduced Power Consumption

Progress in the area of microcircuit technologies leads to a permanent increase in integration degree and clock frequency, which, in turn, creates more high-speed and functionally complex devices on one chip. However, together with huge opportunities, which these successes open for electronic devices, they also cause serious problems, primarily related with power dissipation. A high integration degree has led to the aggravation of the reliability problem as compared with similar devices of lower integration degree. These problems cannot be ignored, as more complex products are designed for various spheres of application, including space applications, which must be reliable and capable of operation for a long period of time without battery charging. Ensuring operational capability of integrated microcircuits under conditions of ionizing radiation and autonomous power supply is now becoming a more important problem due to the fact that integrated microcircuits are widely used in military and space systems. The advantage of using CMOS technology for space systems is explained by the fact that microcircuits based on this technology have low-power consumption, increased noise immunity, and sufficient speed. In space applications, these properties become crucial due to the independence of the space systems’ power supply. In order to implement them to the fullest, it is not enough to have good primitive logic gates, but it is also required to design good circuits on their basis. At the logical level of design, aspects of increasing circuit radiation tolerance are not usually taken into account, but power consumption can be reduced by creating efficient logical structure. In recent years, special emphasis has been laid on this field of research since energy dissipation is becoming a stumbling block to increasing integration level, while the market of portable devices with independent power supply is growing, for which it is important to increase operation time without charging. Designing with power consumption taken into account is still, for the most part, an art, which is in particular related to the absence of efficient means to evaluate the effect of heuristics used in the design process on power consumption of the circuit further implemented on a VLSI chip. A solution to the power consumption problem during VLSIC designing is the interest of many specialists and companies, for example, Cadence Design Systems (the leader in computer-aided design), Apache Design, Atrenta, Magma Design Automation, Synopsys, and Mentor Graphics. The main means to reduce dissipated power mentioned in the literature are based on reducing power voltage value; reduction of microcircuit and microinterconnection capacitances; special arrangement of circuits, controlling synchronization and power supply (disconnection of circuit parts from power for the time, during which they do not perform useful work); and reduction of dynamic dissipation

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Peculiarities of the Technological Process of Production

by minimization of the intensity of signal switching on CMOS microcircuits inputs. The first two of these methods of power consumption reduction are applied at a circuit level by choice of successful technological solutions and layout, the third method is implemented at the system level, and the last one is used at the logical level and includes creating a successful logical structure. The reduction of power consumption of the designed circuit can be ensured at different design levels. Furthermore, the earlier the stage, the more important it is to obtain more qualitative solutions. In particular, power dissipation at the logical level (due to the creation of successful logical structure) can be reduced by up to 10% to 20% without any negative impact on circuit speed and complexity. Microelectronic circuit CADs must have means that allow estimating and minimizing circuit power consumption already during their logical design. The complex of programs of Power Saving Logical Synthesis (PSLS) for designing logical circuits from library elements produced on the basis of static CMOS circuit technology will be described below as an example of such CADs [11]. At the moment, this technology is dominant in the sphere of digital VLSICs, as logic produced on the basis of this technology has good technological parameters and power dissipation properties. Most specialized integrated microcircuits (ASIC) are manufactured on the basis of inverse CMOS logic, 95% of ordered integrated microcircuits use static CMOS logic. Description of the approach to the logical design of such CMOS circuits is described below, as well as description of the structure and functional capabilities of the PSLS complex, containing means for optimization of designed digital blocks of ordered CMOS microcircuits at functional and structural levels, state verification of designed circuits, power consumption estimation of both circuits under design, and the circuits designed from library elements. Such PSLS software complex performs the following functions: ••

Allows obtaining structural description of the logical circuit in the design library of CMOS VLSICs based on functional description of the designed device in the high level language VHDL (Very high speed integrated circuits Hardware Description Language) or in the SF language (Structural and Functional description language) [12], which is not the internal language of the complex.

••

Implements the approach to synthesis that allows minimizing CMOS LSI chip area and power consumption measured by average values of power dissipated by circuit.

••

Has interactive means for designing logical circuits, verification and estimation of design solutions.

••

Allows estimating power consumption of circuits made of library elements at logical and circuit levels.

A case of combinational circuit synthesis is analyzed, for which: ••

Synchronous implementation of circuits is required.

••

Synchronization frequency and power voltage are fixed.

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption ••

139

Statistical method based on probabilistic characteristics of input signals is used for estimation of power consumption in circuit synthesis process.

3.4.2  Determining the Sources of Power Dissipation in CMOS Microcircuits

Hereafter, power consumption value means calculated average value of energy dissipated by a circuit. This estimation considerably differs from estimation of maximum power consumed rate in any individual cycle of circuit operation. In general, power consumption of a logical circuit is a complex multifactor function, which depends on delays of signal distribution across the circuit, synchronization frequency, technological parameters of production, and microcircuit layout, and, in the case of CMOS technology, dissipation power considerably depends on sequence of input actions, applied to the circuit. All the power dissipated by a CMOS microcircuit can be divided into static and dynamic components. The static component results from the presence of static conductive routes between power buses or leakage currents. This component of power consumption in many well-designed CMOS circuits is low. In typical CMOS circuits, 60% to 80% of all dissipated power is accounted for by its dynamic component created by instable behavior of circuit units. According a simplified model, energy is dissipated by CMOS microcircuit every time, when the signal changes at its output. This means that CMOS circuits that are more active in terms of switching dissipate more energy. Thus, power dissipation considerably depends on the switching activity of circuit elements, and it, in turn, is determined by the sequence of applied input actions on CMOS circuit (i.e., operational dynamics). Two factors have the highest contribution to the dynamic power in CMOS technology [13]: pure dynamic power Pdy is related to charging and discharging of capacitance load of the unit, and the energy dissipation power due to through currents of microcircuit during switching. Usually the value of the latter is calculated using the notion of internal capacitance of the microcircuit, and at the logical level it can be reduced due to synthesis of such circuit, which allows minimizing the area of the CMOS chip, which is required for placement of a circuit that implements given functionality. Dynamic dissipated power Pdy is the most considerable cause of power consumption by CMOS circuit in dynamics. It is caused by charge/discharge currents of parasitic capacitances of transistors and communication lines; these capacitances are taken into account in the form of capacitance load CL of unit output. When input is switched from 0 to 1, the current flowing through the p-channel transistor charges the capacitance CL; when input is switched from 1 to 0, the capacitance CL is charged with current flowing through the n-channel transistor. In each of these cases, power is dissipated in the open transistor resistor that can be expressed by a known simplified relation:



1 Pdyn = Vdd2 fclk EsCL 2

(3.13).

where Vdd is the power voltage, fclk is the synchronization frequency, Es is the switching activity of circuit output determined as expected value of a number of

140

Peculiarities of the Technological Process of Production

logical transitions of a signal (from 1 to 0 or from 0 to 1) within one synchronization cycle, and CL is the capacitance load of the microcircuit output. The main contribution to the output capacitance value CL of a microcircuit is made by three factors: parasitic capacitance Cp at the microcircuit output; capacitance load Cload of the output caused by aggregated capacity of fed microcircuit transistors; and capacitance Cwire of its output wiring. The value Cwire becomes known only after wiring routing and is usually ignored at the design level. The values Cp and Cload can be calculated based on the data regarding microcircuits contained in the technological library used for design. The relationship (3.13) is deduced on the basis of the following assumptions about operation of a well-designed CMOS microcircuit: 1. All the capacitance of CMOS element is concentrated at its output terminal. 2. Current inside an element flows only from the power source to the output capacitance and from the latter to ground. 3. Voltage at the element output varies only from the power source voltage value to ground voltage and vice versa. This approach ignores power dissipated in the process of switching of internal units of complex CMOS elements, due to through currents of microcircuit inside CMOS elements, and resulting from switching processes (errors, run-ups). The values of parameters Vdd and fclk in (3.13) are determined during architecture design; at the logical level the product 1/2Vdd2fclk (estimating power dissipation per unit capacitance during supply voltage change) can be considered a constant that is equal for all units of the circuit. Thus, minimization of dynamic power is reduced to minimization of the product EsCL (frequently called switching capacity), and the dissipation of energy by the circuit at the level of logics design is estimated as a sum of switched capacities of all its units:



n

Ps = ∑Ei Ci

(3.14)

i =1

where n is the number of units in the circuit (all units of a circuit are summed), Ci is the capacitance load of the i unit, and Ei is the switching activity of i unit of the circuit. The estimation of dynamic power (3.14) can be effectively used for comparison of implementation variants of circuits with given functionality. At the logical design stage, when electric circuit does not yet exist and the technological basis, in which it will be implemented, is not known, power dissipation of a future circuit can be reduced by means of such transformation of circuit description, which ensures the reduction of its switching activity without the change in functionality [14]. The quantity change of switching activity can be used at the logical level to determine which circuit optimization options are most preferable. This approach to estimation of power dissipation provides an opportunity to compare options of circuit implementation during its designing, which allows designing circuits with potentially low-power dissipation already at the logical level.

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

141

3.4.3  Probabilistic Assessment of Optimization Options Based on Predicted Switching Activity of Microcircuit Units

Estimation methods of switching activity of microcircuit units, used in the design process, are based on the approach that relies on probabilistic characteristics of input signals and functional and structural properties of a tested circuit. This approach includes setting probabilities of signal switching at circuit input that reflect value change frequency and are used for calculation of probabilities of signal switching at outputs of circuit units. Estimation methods of switching activity are based on distribution of probability information about the change of signals throughout the circuit from inputs to outputs, and that is why the literature refers to these methods as probabilistic. The probabilistic approach allows determining possible sequences of input actions on a circuit and evaluating circuit power consumption based on the mutual influence of input signals in consecutive moments of time. Vast majority of estimations of signals switching intensity at circuit terminals used in design practice is based on the assumption of zero signal delay by circuit units, when all transitions in a circuit occur simultaneously. These estimations assume that all changes at circuit inputs are distributed across its elements instantly (i.e., simultaneously) and take into account change of signals only in stable states set by function implemented by a unit. These estimations do not take into account switches occurring due to transient processes, which also disperse energy while not making calculations required from the circuit. The use of actual delay models considerably increases the time needed for estimation of circuit switching activity, at the same time increasing accuracy of estimation. However, in the process of synthesis when optimization options are compared, it is sufficient to use simpler, quickly calculated estimations to which estimations on the assumption of zero signal delay belong. In addition, the known methods of probabilities calculation assume that signals at input terminals of any unit of a circuit are independent in time and space. Time independence assumes that signal value at any clock tick does not depend on its values in the previous ticks. Space independence of terminals assumes the absence of correlation of signal values on them. It can appear when spatially connected signals depend on one another, which is caused, for example, by the presence of fanouts or feedbacks. In practice, a stable dependence also caused by other reasons may exist among signals. The literature offers a large number of probabilistic estimation methods of logic circuit power consumption, the majority of which can be applied only to combinational circuits. Power consumption estimation methods are formulated: 1. Concerning various assumptions about signal delays of circuit units, possibility of various types of dependences among signals, and the account of transient processes during signal switching; 2. Using different statistical characteristics (probabilities of signal 1 appearance, probability of signal change at the terminal, and intensiveness of signal switching, signal switching density, balanced probabilities, and probabilistic signal forms); 3. Using various models [based on binary decision diagrams (BDD) and correlation coefficients].

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Peculiarities of the Technological Process of Production

The essence of proposed methods of CMOS circuit synthesis from library elements remains unchangeable when any estimation method of circuit unit switching activity is used; therefore, we use the simplest method, which is based on the following assumptions: 1. Changes at circuit inputs spread across its elements immediately, which means that all switches in the circuit occur simultaneously. 2. There is time independence for each input terminal, assuming that the signal value at any clock tick does not depend on its values in previous ticks. 3. Input terminals are spatially independent, which means the absence of correlation of signal values on them (which can be caused, for example, by the presence of fanouts or feedbacks). There are probability pi1 of signal occurrence 1 (0) at some i terminal and the probability of signal switch at this terminal. The first probability i1 is called signal probability (probability of signal 1 occurrence) and is determined by average fraction of cycles, in which the signal at the i terminal has unit value. The second probability p1→0 (or p0→1) is the probability of a change of the signal value from 1 to 0 (or from 0 to 1) and is determined by the average fraction of cycles, in which the signal at i terminal changes its value in comparison with the value in the previous cycle. According to assumptions of zero delays of elements (which excludes switching due to transient processes) and time dependence of signals, the probability p1→0(or p0→1) equals the product of the probability of signal 1 (0) appearing at it in one cycle by the probability of a signal 0 (1) appearing at it in the next cycle. Correspondingly, the switching activity of the i terminal of a circuit is equal to the product Ei = pi1→0pi0→1 = 2pi1pi0, and on assumption that pi1, pi0 < 1, letting pi represent pi1,

Ei = 2 pi (1 − pi )

(3.15)

Probability pe of signal 1 appearing at the output of element e greatly depends on probabilistic characteristics of signals at its inputs and on the function implemented by this element. In case the signals at element inputs do not correlate in space and time, the signal probabilities of simple elements like inverter, AND, OR, AND-NOT, OR-NOT with n(e) input terminals can be easily calculated, based on truth tables of functions, implemented by them: pe¬ = 1 − p1 n (e )

pe = ∏pi i =1

n (e )



pe∨ = ∏(1 − pi ) i =1

n (e )

pe = 1 − ∏pi i =1

n (e )

pe = ∏(1 − pi ) i =1



(3.16)

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

143

where pi is a signal probability (probability of signal 1 appearance) of the i input element. If signal probabilities of circuit input signals are given, then they can be distributed across outputs of circuit elements and across the whole circuit at its output terminals. Thus, the switching activities of all circuit terminals can be calculated as well as switching activity of the circuit in general as a sum of switching activities of all its terminals. It should be noted that even if the requirement of space (and time) independence for circuit input signals is met, it may have no space for input signals of internal elements of the circuit (resulting from the presence of fanouts and feedback lines). In this case the probabilities, calculated based on formulae (3.15) and (3.16), have an error. However, it suffices to apply simple estimations for comparative evaluation of optimization options instead of more precise estimations that require more complicated calculations. 3.4.4  The Choice of Element Basis While Designing CMOS VLSICs with Reduced Power Consumption

The element basis contains a rather wide range of various logical elements, among which combination logic including simple tree-shaped circuits with AND, OR, NOT gates occupies the central place. This set generally includes elements AND, OR, AND-NOT, OR-NOT for a different number of inputs (usually for two to four, sometimes six to eight inputs, as the basis and tree-like circuits (of AND, OR gates) with the number of input terminals not exceeding four and two to four levels. The number of circuit transistors (or the number of layout basic cells, the sizes of which depend on the technology of CMOS element production) of a library element determine its complexity (price). This number is directly linked with the area, occupied by an element on a chip and its capacitance load, on which element power consumption greatly depends. The element basis of CMOS VLSIC is characterized by the presence of a full set of gates. Structures of library elements can be presented in tree-like networks of AND, OR, NOT gates. Each of these trees has a limited number of leaf peaks and limited fanout. CMOS library is characterized by the fact, that all of its elements generally have an element, implementing the binary function. Thus, Table 3.1 presents the properties of some CMOS library elements, using the example of which the proposed synthesis method will be demonstrated: n is the number of input terminals, k is the aggregate number of gate input terminals, l is the number of layers in its tree-like structure (except inverter), and t is the number of transistors of its microcircuit. The elements of the described CMOS library have the following restrictions: n ≤ 4; k ≤ 9; l ≤ 4; t ≤ 12. To estimate efficiency of circuit presentation options, the quantity parameter of logic efficiency is introduced in technological basis expressed in the number of terminals covered by a library element of a circuit per unit of its complexity, one transistor. Logical efficiency of the element equals relation k/t of the number of gate input terminals, presenting the structure of this library element and the number of microcircuit transistors. The higher this relation is, the higher the functional efficiency of the element becomes (for coverage purposes). Table 3.1 shows that elements with the most complex structure are the most efficient ones: NOAA (2-2AND-2OR-NOT) and NO3A3 (3AND-3OR-NOT) and

144

Peculiarities of the Technological Process of Production

gates reciprocal of them: NAOO (2-2OR-2AND-NOT) and NA303 (3OR-3ANDNOT), the least efficient are the inverter and two-input gates AND and OR (A2 and O2). The price of a complex library component is generally lower than the aggregate price of comprising gates implemented by simpler elements. For example, NOAA element can be implemented in the form of the composition of an inverter, two A2 elements and an O2 element. The price of the NOAA element (eight transistors) is lower than that of the composition (2 + 8 + 4 = 14 transistors). 3.4.5  Logic Synthesis of CMOS LSIC in Element Library Basis

Power consumption of a digital circuit is generally directly proportional to the area that it occupies on a VLSI chip. This means that main route of energy saving during functioning of logic systems primarily implies reduction of the area, occupied by a circuit on a VLSI chip. Practical experience shows that existing methods, Table 3.1  Elements of CMOS Library Library Elements NOT

n 1

k 1

t 2

l 1

Logical Effi- Graphic Representation of ciency Value Elements 0.5

N AND-NOT, OR-NOT, NA, 2, 3,4 2, 3, 4 4, 6, 8 2 NA3, NA4, NOT, NO3, NO4

0.5; 0.5; 0.5

AND, OR

2, 3

2, 3

6, 8

1

0.33; 0.37

4

5

8

3

0.63

4

6

8

3

0.75

4

5

8

3

0.63

5

7

10

3

0.7

5

6

10

3

0.6

A, A3 O, O3 3AND-2OR-NOT 3OR-2AND-NOT NOA3 NAO3 2-2AND-2OR-NOT 2-2OR-2AND-NOT NOAA NAOO 2AND-3OR-NOT 2OR-3AND-NOT NO3A NA3O 2-2AND-3OR-NOT 2-2OR-3AND-NOT NO3AA NA3OO 3AND-3OR-NOT 3OR-3AND-NOT NO3A3 NA3O3

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145

which optimize circuit complexity, are a good starting point for the development of methods aimed at reduction of logical circuit power consumption [15]. The application of these methods as a basis of developing methods of power consumption minimization also requires consideration of new criteria used together with criteria of circuit area minimization. These criteria materially depend on the technology of synthesized logical circuit implementation. In the process of logic synthesis, the abstract description of synthesized circuit behavior (system of Boolean functions) is represented in the basis of elements of CMOS VLSIC technology library. Each element is characterized by its function and physical properties. The approach as well as the majority of well-known synthesis methods is based on division of the logic synthesis process at the stage of technology independent optimization and technological representation. The first stage of synthesis is aimed at logic optimization and decomposition, and the second one is aimed at implementation of obtained functional description in given technological basis. The goal of the first stage is to minimize complexity of a multilevel circuit in technology independent basis of elements. The latter, as a rule, consists of simple gates, the selection of which can be not linked with any element basis and can be chosen based on actual technology library, as it is done in [16]. The complexity of the multilevel circuit is measured by the number of switches, depths of the circuit and evaluation of power dissipation at logical level. The second stage includes translation of multilevel circuit from gates to technological basis based on structural coverage of the corresponding object network with subcircuits implementing library elements. This approach does not imply radical reconstruction of the circuit obtained at the stage of technology independent optimization, and this means, that quality of the desired coverage considerably depends on its structure. Errors made during its synthesis cannot be compensated to the full at the stage of technological representation; therefore, much attention in existing CADs is given to the stage of technology independent optimization. Technology-independent optimization includes minimization of functions of the implemented logic descriptions in the disjunctive normal forms (DNF) class as its first stage. Taking into account specific nature of the CMOS basis, it is rational to perform joint minimization, taking into account function polarity, choosing that form (DNF or its inversion), which has the smallest complexity and power consumption. At the second stage, the minimized DNF system represented by a two-level circuit is decomposed into multilevel object network of gates AND, OR with a limited number of inputs, into which structures of the main CMOS library elements fall, in which the circuit is planned to be represented. The complexity of the circuit and its power dissipation are closely connected in a way that circuit area reduction tends to provide energy consumption reduction, and increase in the area, on the contrary, as a rule, leads to increase of energy consumption. Based on these considerations, we can say that synthesis process requires a compromise between the criteria of power consumption and area minimization. The main problem of circuit optimization lies in the fact that at the logic synthesis stage, which is not yet linked with any technological basis, it is very hard to reliably evaluate power consumption of an actual circuit. Due to this fact, minimization of the dynamic component of circuit power consumption (evaluated by the switching activity of the circuit) at the logic synthesis stage at the expense of circuit complex-

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ity may, after all, result in increased power consumption. This happens due to the growth of other power consumption values. As the solution to the problem of logical circuit optimization is based on the fact that the main means of power saving during logical circuits design implies a reduction of area occupied by the circuit on a chip, the ranked criterion is used to evaluate optimization options at all stages of logic synthesis: first, quantitative evaluation of the area change and then quantitative evaluation of switching activity of the circuit. 3.4.6  Optimization of Two-Level Logical Circuits Regarding Power Dissipation

In order to optimize two-level circuits regarding power dissipation, methods of minimization of functional description of systems of fully or partially determined Boolean functions are used, which are modifications of well-known methods of Boolean function minimization in the DNF class by means of adding heuristics that aim minimization process at obtaining DNF systems implemented by circuits with the lowest-power dissipation degree. Practically all methods of two-level representations of Boolean functions are based on division of the number of desired simple implicants into three subsets: essential, redundant, and conventionally essential. The first must be included in any irredundant solution, the second must not be included in any solution, and the third serves for the selection of irredundant subset, covering all intervals of single areas of minimized function task, which are not covered by essential implicants. Minimization methods vary depending on the method of construction of prime implicants out of the number of conventionally essential ones and the criteria that they must meet to be included in the solution. The following methods are distinguished: 1. Consecutive construction of prime implicants included in the solution (e.g., competing intervals method), by increasing interval of Boolean space arguments, representing the implicant, due to inclusion of elementary conjunctions; 2. Consecutive extension of the interval of Boolean space arguments, representing initial DNF conjunction at first, and in prospect for the prime implicant, covering this conjunction, due to exclusion of some literals, which are part of it (e.g., methods, implemented in ESPRESSO). The simplest minimization method can only use one operation of conventionally essential implicant extension. Minimization methods that are the easiest way to modify regarding power saving are the methods in which candidates to the desired solution are represented by several prime implicants or methods in which the found solution is modified by the method of consecutive improvements. In order to aim minimization at obtaining a power-saving solution, the process of obtaining prime implicants and irredundant coverage requires calculating and taking into account the switching activity of all prime implicants, using (3.15) and (3.16). We shall analyze operations included in practically all minimization methods to explain the procedures that aim the minimization process at obtaining the desired result.

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The interval extension operation is done by excluding its literals. When interval is being extended, the following two goals are taken into account: to reduce the complexity of this interval and to extend it to the highest extent and cover (completely or partially) with it as many uncovered intervals as possible. During power consumption minimization, it is recommended to not exclude any literals, but the most active ones and to not cover any literals but the most power-consuming ones. In view of the first assumption, literals with higher switching activity are first checked for exclusion. In view of the second assumption, the order of the intervals’ extension is important: extending the interval too early may hinder the situation, when some other interval covers this interval under consideration. In order to reduce power consumption, the power contribution of each interval is evaluated, and power-consuming (with high switching activity) intervals are extended by the latter in hope that some other intervals will extend and cover them. The operation of irredundant coverage detection means transforming the current DNF coverage into an irredundant form. When looking for an irredundant multitude of prime implicants, the minimal number of the least active (with the lowest switching activity) implicants is chosen. In this case, the irredundant multitudes of prime implicants with minimal power or aggregate number of literals of all implicants are chosen from irredundant multitudes of prime implicants, which represent the coverage of the initial multitude of intervals of singular areas of the minimized Boolean functions. Each of the selected multitudes is evaluated by the aggregate of switching activities (or switching density [17]) of the implicants in it, and the irredundant multitude with minimal switching activity is chosen as the solution. A comparison of modified minimization methods [18] with initial methods (without taking into account power consumption) has shown that Boolean functions’ minimization regarding switching activity of signals allows obtaining reduction of circuit power consumption without increasing their complexity. In this case, minimization expenses increase slightly. 3.4.7  Selection of Basic Gates of Technology-Independent Functional Circuits

There are various approaches to the selection of basic gates for independent circuit synthesis. Typically, the description of the implemented logic is translated (resulting from minimization) into the equivalent AND-OR-description, which at the decomposition stage is translated into the homogeneous basis of two-input AND-NOT or OR-NOT. The use of minimal number of basic gates due to their simplicity (e.g., 2AND-NOT), as it is accepted in a number of well-known CADs (e.g., MIS, SIS, ABC), leads to the increase of granularity effect of logical network and generally may also increase the quality of library elements coverage due to increasing the number of coverage options. However, in case of CMOS basis, this advantage can be diminished by a considerably higher number of drawbacks: representation by library elements becomes more complicated (in such a shallow basis), a number of representations of the same element increases, and the speed of coverage methods reduces, which, in turn, results in the necessity for their further coarsening. In the case of the CMOS library, the choice of the technology-driven basis of basic gates is more preferable [16]. Basic gates are the ones that comprise library elements of the technological basis. This approach allows obtaining at the

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technology-independent optimization stage a logical network that is very close to the technological basis and correspondingly using effective and simple coverage algorithms for technological representation. This approach also allows simplifying the model representation of library elements (they are represented in the same gate basis, as the covered object network) and their number (and thus the size of the library), which is rather important for the speed of the coverage algorithm. Analysis of the CMOS library content shows that structures of all complex elements can be represented by circuits from the alternating gates AND and OR. This means that simple representation of multiplace functions AND or OR in the form of composition of two-place ones will not provide new possibilities for coverage, but will result in the mentioned negative consequences. Therefore, gates NOT, AND, or OR with limited number of inputs, not bigger than that of the maximum number of gate inputs (AND-NOT, OR-NOT) of such a library, must be used for the analyzed technological basis. In the coverage process, the structural circuits of library elements are compared with fragments of the covered circuit and replace them in the case of complete coincidence. Correspondingly, each library element must be represented by different structures, implementing its function. As already noted, the majority of the most effective elements implement inverse logic, and separate inverters are rather expensive CMOS elements. In view of this fact, binary structures, obtained by transfer of inverters from outputs to inputs (see gates AND at OR, and OR at AND) (Figure 3.15), are offered to be included in the structural description library, together with structures representing their function for structural coverage of the circuit. For example, element 2AND-2OR-NOT (NOA), implementing function ab∨ c, creates element 2OR-2AND (AON) with inverters at inputs, implementing function (a ∨ b)c. 3.4.8  Optimization of Multilevel Logical Circuits Composed of Multi-Input Gates

At this stage, the task of constructing a multilevel logical circuit from gates AND, OR, NOT, implementing Boolean functions system, is considered. This task directly follows the minimization of Boolean functions in the DNF class and precedes the synthesis of logical circuits from library elements created using CMOS technology. The goal of this stage lies in creation of such option of circuit gate representation, which can serve as a good starting point for the technological representation stage in library elements basis. The aggregate number of input terminals of gates and

Figure 3.15  Structures of two nontrivial elements of CMOS library: (a) 2-2OR- 3AND-NOT (NA3OO); and (b) 3AND-3OR-NOT (NO3A3).

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

149

aggregate switching activity of circuit terminals are used for quantitative evaluation of design efficiency. Combinational elements of a typical CMOS VLSIC library can be represented at the logical level in tree-like structures of gates NOT, AND, and OR, implementing inverse logic, for example, two-level AND-NOT, OR-NOT, three-level 2-2AND-2OR-NOT. Elements implemented by multilevel structures include gates with two and three input terminals. Logic efficiency of a library element can be evaluated by the relation of the aggregate number of the terminals of its structure and the number of transistors. The most efficient elements are intensely structured microcircuits of gates AND and OR with 2 or 3 inputs, and the least efficient ones are inverter and two-input gates. Correspondingly, the most attractive from the point of view of library element coverage are intensely structured networks with gates AND, OR with few input terminals. These considerations form the accepted method of multilevel circuit synthesis. The main method of solving the task of decomposing a DNF system, which is used in all CADs, is algebraic decomposition [15], which is based on construction of factorized forms (or factorized DNF) by searching factors, the common parts of conjunctions or disjunctions of a DNF system. The factorized form is the algebraic form of the task of DNF multilevel representation. Transformation of the initial minimized DNF system into a factorized form, which is characterized by a multilevel implementation of gates with limited number of inputs, is done in two stages [19]. ••



Joint nontrivial factorization of a DNF system: Factors are determined (conjunctions or DNF) that have the length (number of literals) not exceeding the maximum number of inputs nmax and mmax of gates AND and OR, and are not included in more than ndl equations. The key aspect of searching the factors is evaluation of their value and energy-saving properties. The value property Ts of factor s, included in the equation from its generating set Us, is evaluated in a simplified manner by the area of the corresponding Boolean matrix minor, providing factorized set of equations:

(

)

Ts = c ( s ) U s − 1

(3.17)

where c(s) is the Quine cost of implementation of the product s.   Energy-saving property of the factor is quantitatively evaluated by the advantage in the switching activity of the desired circuit, which provides definition of this factor. In a factorized set of equations, the switching activities of all equations will not change in comparison with their values in the initial set, but the load of circuit terminals corresponding to the literals that are included in factor s changes: it reduces by (|Us| – 1), and the switching activity of circuit terminals implementing factorized set of equations changes correspondingly. The energy-saving quality of the factor s = {z1, z2,…, zl} is a estimated as:



Ps = ( U s − 1∑ E(Zi ) z1 ∈S



(3.18?)

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Peculiarities of the Technological Process of Production ••



Construction of bracketed DNF equations of every function of the system: This is based in the iterative factoring of common literals of given DNF conjunctions D (i.e., at decomposition): D = k ( A) + B

(3.19)

where D, A, and B are DNF (disjunctions of a certain number of disjunction set), and k is a conjunction consisting of a multitude of literals, common for all conjunctions from A. Conjunction k is chosen in the following manner: its core is formed by the best literal x, and other literals, common for conjunctions from DNF A, are factorized together with this literal. The literal x, which is included in the highest number of l conjunctions from D, is considered the best, and in the case of equal worth of this criterion, the best literal has the maximum values of switching activity. This selection of the literal is justified by the fact that the electric load on the circuit terminal with switching activity Ex and corresponding to the literal x, factored from l expressions, reduces by the value (l – 1)Ex, and the most effective signal will be applied to the circuit closer to the output, which will allow reducing the aggregate switching activity of the circuit. After completion of the iterative factoring process of common conjunction literals, the rest of conjunctions with the rank, higher than nmax, are factorized separately. In this case, the factor first includes literals corresponding to the terminals with the least switching activity, as it is desired that the most active signals are supplied to circuit elements inputs as close to the output, as possible. The performed experimental research [19] has shown that the proposed synthesis method allows obtaining a rather stable advantage in estimation of power dissipation of the designed circuit in comparison with the same method, which does not take power consumption into account. 3.4.9  Optimization of Multilevel Logical Circuits Composed of Two-Input Gates

The optimization of multilevel representations is done both at the level of algebraic representations of Boolean functions systems and at the functional level based on the search of BDD-representations of Boolean function systems, to which multilevel logical circuits of two-input gates AND and OR correspond. BDD representation is built on the basis of consecutive Shannon decomposition in variables xi, applied to Boolean functions f(x1, ..., x2):

f = xi f ( x1 ,  xi −1 ,0, xi +1 ,  xn ) ∨ xi f ( x1 ,  xi −1 ,1, xi +1 ,  xn )

(3.20)

Decomposition coefficients f(x1,….xi-1, 0, xi+1,…. xn) and f (x1,….xi-1, 1, xi+1,….xn) are obtained from the function f(x1, ..., xn) by substituting variable x1 with a 0 or 1 constant correspondingly. BDD gives the sequence of Shannon decomposition of the initial function and obtained decomposition coefficients in the form of a graph. Minimization of BDD complexity is based on the fact that during

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

151

the decomposition process similar coefficients may appear not only for one, but for several (or even for all) decomposed functions of the initial system. Hereafter, BDD decomposition means optimization of multilevel representations of Boolean functions systems corresponding to reduced ordered BDD (ROBDD). For example, when decomposing Boolean functions f 1 = x1 x2 x4 x5 x6 ∨ x1 x4 x5 x6 ∨ x2 x3 x5 ; f 2 = x1 x4 x5 x6 ∨ x1 x3 x5 ∨ x1 x2 x3 x5 x6 ∨ x1 x2 x4 x5 x6 ;





(3.21)

3

f = x1 x2 x3 x6 ∨ x1 x2 x4 x6 ∨ x1 x3 x4 x5 x6 ∨ x1 x2 x5 ∨ x2 x3 x5 ;

based on variables x1, x2, x3, x4, x5, x6, a BDD representation is obtained (Figure 3.16), which is described by the following multilevel representation of the logical circuit of two-input gates AND and OR. f 1 = x1 ψ1 ∨ ψ2 ; f 2 = x1 j2 ∨ x1 ψ3 ; f 3 = x1 ψ2 ∨ x1 ψ 4 ; ψ1 = x2 j1 ∨ x2 j1 ; ψ2 = x2 j2 ; ψ3 = x2 s1 ∨ x2 j3 ; ψ 4 = x2 j4 ∨ x2 j5 ;

j1 = x3 s2 ∨ x3 s1 ; j2 = x2 λ3 ∨ x3 s3 ; j3 = x3 λ4 ; j4 = x3 λ2 ∨ x3 s2 ; 5

2

1

1

2

3

2

3



(3.22)

4

j = x3 s ; s = x4 λ ; s = x4 λ ∨ x4 λ ; s = x4 λ ; λ1 = x5 ω1 ; λ2 = x5 ω1 ∨ x5 ; λ3 = x5 ; λ4 = x5 ω2 ; ω1 = x6 ; ω2 = x6

Shannon decomposition or its special case corresponds to each functional vertex of BDD. BDD complexity is estimated by the number of vertices, marked with symbols of functions, vertices corresponding to the arguments are not taken into account for BDD complexity estimation. For example, the complexity of BDD (Figure 3.16) equals 21. The main problem of BDD construction is the selection of sequence of variables based on which Shannon decomposition is done. In the case of power optimization of the binary decisions diagram (BDD), the first and main criterion is the minimum complexity of BDD, and the second and subordinate one is the criterion related to probabilities of signal changing at circuit inputs. The first criterion is aimed at minimization of complexity (number of transistors) of the logical circuit, which is built at the technological representation stage, as the reduction of the number of transistors allows reducing power consumption. The second criterion allows selecting among BDD of the similar complexity those ones, based on which combined low power consumption logical circuits can be built. The estimation of power quality of the variable x in BDD representation is represented by value

K1 = p1s1 , if p1 < 0.5, K1 − (1 − p1 ) s1 , if p1 ≥ 0.5

(3.23)

where p is probability that a single value of signal x will appear at the input of the logical circuit, implementing BDD; and si is a number of literals of variable xi in a multilevel representation of function system corresponding to BDD.

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Peculiarities of the Technological Process of Production

Figure 3.16  Binary decisions diagram.

Variables xi characterized by probability p that is close to 0.5 cause the highest number of switches at the circuit element inputs. Consequently, it is recommended to minimize the number of literals of such variables in functional representation of BDD. If probability p is close to 0 or 1, such variables will result in a smaller number of signal switches in the circuit. Therefore, it is recommended to arrange

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

153

the variables characterized by the low value of the variable K, in the middle of the sequence of variables based on which BDD is built. It should be noted that logical circuits of two-input gates AND and OR can process optimization programs for multilevel representations as systems of fully determined Boolean functions and systems of partial Boolean functions given by sets of argument values or in interval form. 3.4.10  Technological Representation

At the stage of technological representation, a structural method of coverage (the most effective in practice of complex circuit design) of multilevel circuits of gates AND, OR with library elements is used. In the coverage process, the structural circuits of library elements are compared with the fragments of the covered circuit and replace them in case of complete coincidence. Correspondingly, each library element must be represented by different structures implementing its function. The covered multilevel, multi-output logical network of gates is presented in a directed acyclic graph G = (V, U), hereinafter referred to as an object graph. The vertex of the graph corresponds to basic gates and input terminals of the circuit. The structural description of the library element is a single-output, multilevel logical network of the same basic gates, as the covered target network. Each library element is presented in a tree-like directed graph, hereinafter referred to as a model graph. The covering method is based on consecutive accentuation of subgraphs Gk of the graph G and a comparison of each of them concerning its coverage by graphs Hi and its replacement with graph Hi, which provides the highest value of the selected optimization criteria [20]. Thus, the method ensures local optimization and is approximate. In the covering process, the graph G shrinks due to the exclusion of covered subgraphs from it. At the same time, the resulting graph E is built up (starting from the empty state) and it presents a logical network of library elements, which is functionally equivalent to the initial target network. With regard to coverage optimization criteria, such a variant of the circuit shall be obtained from library elements during coverage process, which will provide the minimum area and power dissipation. The first optimization criterion of the proposed method is the area obtained as a result of circuit coverage, which is measured by the aggregate number of transistors of all library elements and is evaluated by the aggregate cost of model graphs, which are contained in the object graph. Correspondingly, the cost estimation of the subgraph coverage of graph G = (V, U) is presented by the relative cost of coverage of one target network terminal, which is measured by the relation of the number of covered terminals of the network fragment to the value of the covering library element (which is also measured by the number of transistors); the higher this value, the more desirable a coverage option is. Power consumption of the circuit obtained as a result of coverage is evaluated by the aggregate of switching activities of all terminals of the circuit. Correspondingly, the energy-saving estimation of a coverage option for the subgraph of graph

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Peculiarities of the Technological Process of Production

G = (V, U) is presented by the aggregate of switching activities of the gates covered by the library element. If a signal delay in logical elements is ignored, then it is also possible to ignore the intensity of signal switching in internal terminals of library elements during power dissipation estimation. This assumption is justified by the fact that the most considerable contribution to the parasitic capacitance of the circuit is made by connection lines and recharging of this capacitance during the signal switching process involves most of the consumed power of the energy source. Thus, the circuit implemented according to the CMOS technology must be covered with library elements in such a manner that as many circuit units with the highest switching activity as possible are inside library elements. Correspondingly, the value of energy efficiency of the coverage option is presented by the aggregate of the switching activities of the elements, which correspond to the covered vertices, which have become internal vertices of the covering sample. With regard to the increasing speed of the coverage algorithm, searching during coverage is mainly concentrated on selection of the following pair: covered subgraph Gk of graph G and the covering model graph Hj of the library element. The following parameters allow one to shorten searching: 1. Search and coverage of subgraphs Gk of the object graph allowing unique coverage (with a single model graph). In the simplest case, such graphs are vertices with a high degree (corresponding to elements with a large number of input terminals), for which a single coverage option exists (e.g., there are more than three options for many CMOS library series). 2. Model graphs sorting. In the case of ordering model graphs Hj in descending order of their efficiency (measured by the relation of the numbers of terminals of its structure to the number of transistors), then, comparing them in order with the subgraph Gk, detected at some step of coverage algorithm, searching can be reduced in some cases: if for some model graph Hl the value Hl/Gk = Ø, then it is possible not to compare the subgraph Gk with other subgraphs Hl, as they have smaller efficiency and consequently cover smaller part of the graph G. It is possible to search only for the coverage option for subgraph Gk with the highest value of energy efficiency criterion. 3. Layout sorting of object and model graphs. Sorting of the model graph Hl (which is a tree) means ordering of tree branches from the left to the right based on their complexity in the descending order. Branch P is placed to the left from branch R, if P is longer than branch R, or (if they have equal length) when looking at the vertices from the root, the first vertex with higher in degree is observed in branch P, rather than in branch R. Partial sorting of graph G is done in the same manner. Sorting allows faster answering the question, whether it is possible to cover object graph fragment with the given model graph.

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

155

3.4.11  Estimation of Power Consumption by the Designed CMOS LSICs at the Logical and Circuit Levels

Apart from probabilistic estimations of power consumption, the software complex PSLS includes the means that allow evaluating power consumption of the designed combined blocks of custom VLSIC by calculation of the total number of transistor switches in the circuit elements at given test sequences of input sets (tests) using high-speed VHDL modeling (or SF modeling) [21]. The use of logical VHDL/SF modeling for estimation of power consumption allows reducing estimation time by several orders with an acceptable error (about 10% to 15%) of this estimation. Tests for circuit modeling can be given in the form of a text file of a specific format or generated automatically. Tests of four types are generated in the automatic mode: 1. Pseudorandom tests of a given length regarding signal probabilities of input terminals; 2. Sequences of 2n sets of the Boolean space of n dimension in the ascending order of the radix-10 equivalent; 3. Sequences of 2n sets of the Boolean space of n dimension, in the descending order of the radix-10 equivalent; 4. Sequences of 2n (2n – 1) ordered pairs of all sets of the Boolean space. Tests are built in two formats, in particular, for VHDL modeling and for SPICE modeling. Finding the energy-intensive test T reduces to the analysis of all pairs of the sets of input signals values and number of transistor switches of circuit elements corresponding to them on the assumption that the maximum number of switches (in the given cycle) corresponds to the maximum current consumption. If the value of consumed current is set in correspondence with the pair of sets of input signals values, the found test will provide not approximate, but the actual (from the point of view of circuit modeling) current consumption. The value of consumed current determines the minimal width of the conductors in feed and ground networks of VLSIC, the correct width of such conductors is very important to prevent electric migration effects, which result in conductor breaks and failures during VLSIC operation. Let us assume that the multitude of numbers V = {0, 1, 2, …, 2n – 1} is given, each of which represents a radix-10 equivalent of the testing vector, a set of values of the circuit input signals. The multitude L of all 2n (2n – 1) ordered pairs of multitude V elements is analyzed. Listing all such pairs without repetitions, that is, obtaining the ordered sequence L, is possible only according to the triangle rule. In case n = 3, such a triangle will have the following form: 7, 5, 7, 4, 7, 3, 7, 2, 7, 1, 7, 0, 7 6, 4, 6, 3, 6, 2, 6, 1, 6, 0, 6, 5, 3, 5, 2, 5, 1, 5, 0, 5, 4, 2, 4, 1, 4, 0, 4, 3, 1, 3, 0, 3 2, 0, 2 1

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Peculiarities of the Technological Process of Production

0, 1, 2, 3, 4, 5, 6, 7 Having located the rows of the triangle in the linear order, we will receive the sequence L. Weight S is placed in correspondence with each pair and it equals the number of transistor switches in the circuit caused by the change of the testing vector i to vector j. Each ordered sequence P

P =< i1 , i2 , i3 , i4 ,..., ik − 2 , ik −1 , i >

(3.24)

of elements (not necessarily different) of the multitude V corresponds to a multitude of

, , , …,

ordered pairs composed of neighboring sequence elements (3.24). Ordered sequence k (3.24) is called a regular one, if all incoming ordered pairs are different. The task of finding the energy-intensive test T is expressed in the following way: the regular k sequence P with maximum integral weight needs to be created for the given number k using elements of the multitude L k −1



S = ∑(Siq −1, iq + Siq , i q= 2

q +1



(3.25)

If each element of the multitude L corresponds to a vertex of the complete directed graph G, the task can be reformulated in the graph arrangement: in the complete directed graph G, the arcs of which are weighted with nonnegative integers, it is required to find a simple circuit consisting of k arcs and having a maximum integral weight S of arcs included in it. This task and its solution algorithms are known in graphs theory. Algorithms for solving the task of finding the test T for the case, when the number of input variables of the combined circuit does not exceed a score, are proposed in [22]. Software means have been developed to obtain SPICE descriptions of logical circuits and generation of various tests. These means allow estimating power consumption using a circuit modeling system. 3.4.12  Technology of Designing CMOS LSICs with Reduced Power Consumption Using PSLS

Design of digital VLSIC blocks within the complex represents a multistage process of changing the structural and functional description of the circuit. Each of the obtained descriptions of the system gives new state of the project and is called a design decision. The designing process starts from the initial description of the digital block in one of the input design languages and ends with presenting its circuit in the technological basis. Design decisions can be obtained in the automatic mode (using software means of synthesis and optimization) and in the semiautomatic mode (decisions are corrected by a designer). In order to avoid propagation of errors made at one of the earlier stages of designing, the means to verify design decisions

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption

157

at all design stages are included in the complex [23]. Verification includes checking, whether obtained decisions are in relation of equivalence (if both descriptions are completely determined) or implementation (if the initial one is not completely determined). The design process using software complex PSLS includes the following stages (each of which is implemented by a number of alternative design operations): ••

Development of the functional description of the designed circuit;

••

Optimization of the functional descriptions of two-level and multilevel circuits taking into account their complexity and power consumption;

••

Synthesis and optimization of circuits in a given CMOS library of elements, taking into account complexity and power consumption;

••

Verification of design decisions at all stages of design;

••

Generation of test sequences and estimation of power consumption at logical and circuit levels.

Figure 3.17 shows the general structural scheme of data transformation in experimental software complex PSLS for automated design of logical circuits using CMOS library elements with minimization of power consumption. In case of using software complex PSLS, design technology is based on the sequential transformation of the description of the designed circuit presented in SF language. SF language, being an internal language of the system, is oriented towards hierarchical structural and functional descriptions of logical circuits. Combination blocks or elements in the SF language are given in the form of logical

Figure 3.17  Synthesis of logical circuits within the PSLS software complex.

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equations or in the form of matrix (pair of matrices describing DNF system of the Boolean functions). The initial functional and structural description of the designed circuit can be presented in VHDL language. The PSLS complex provides conversion of the circuit description from VHDL into SF language. Reverse conversion of the obtained structural description of the circuit of CMOS VLSIC library components to the VHDL description is also provided. Any intermediate description of the logical circuit designed in PSLS can be also converted into VHDL. Such sequencing of data allows using software complex PSLS together with other existing circuit designing means, for example, with the logical circuits sequencer LeonardoSpectrum [24, 25]. Numerous experiments have proved the efficiency of this approach to design. In this case, preliminary optimization is done using software not available in LeonardoSpectrum and the final stage that includes covering optimized representation with functional descriptions of the target library elements is performed by the industrial sequencer LeonardoSpectrum. 3.4.13  PSLS Software Complex Architecture

The software shell of the PSLS complex has the means for information and language support of design processes. Such means include reference subsystem and issuing express estimations of design operations execution results, and implementation of alternative technological design flows and design operations. Software complex PSLS consists of four subsystems: design creation, design optimization, verification, and power consumption verification. The first subsystem provides support for creation, editing, and transformation of initial design task forms. The second subsystem accompanies the execution of the design procedures of optimization and synthesis. The third subsystem provides monitoring of the transformations of design description. The fourth subsystem supports generation mechanisms of tests and power consumption estimation in the generated or given tests. All the data about the current state of the designed circuit form the project. Apart from the SF description, a number of additional data are defined in the project, part of which is represented by attributes and reflects some properties of the current description of the circuit. They include, for example, current description format, parameters of the performed design operation, name of the latest performed design operation, next possible actions, and history of execution of design operations (e.g., whether circuit minimization has been done or not). According to designation of the software complex, the following data can be used as input data for designing: ••

Functional description of designed circuits of combination logic in VHDL and SF languages;

••

Functional and structural description of designed circuits of combination logic in VHDL and SF languages;

••

Distribution of signal probabilities of value 1 appearance at inputs of the designed circuit;

••

Sets of test sequences, which are used for modeling the designed circuit behavior concerning estimation of their power consumption;

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption ••

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Working models for circuit modeling in SPICE system. Software shell is a set of software and service tools for monitoring the design process and its control. It includes the complex of the following subsystems: •

Session deployment;

•

Project formation or adjustment;

•

VHDL-description import and export;

•

Management of data used in the project;

•

Organization of design operations;

•

Verification of obtained design decisions;

•

•

Estimation of switching activity of circuit implementation of the design decision at all stages of logical circuit optimization and synthesis; Estimation of power consumption of the designed circuit.

The whole design process is aimed at the use of interactive, dialog mode with support and prompts from the system part of the complex. The complex features a developed reference system. All programs of the PSLS complex are written in C++ using data structures developed by the authors and are tested within the tests program in Windows XP OS. 3.4.14  Functional Capabilities of the Software Complex PSLS

Software complex PSLS includes six groups (classes) of programs supporting the full cycle of designing logical circuits from library elements. These programs provide circuit synthesis and optimization in terms of area and power consumption at all stages of designing process. 1. Two-level optimization includes a set of programs for minimization of systems of partially or completely determined Boolean functions in DNF class. The main optimization criterion in this case is the minimum integral estimation. This estimation takes into account complexity of the obtained DNF and aggregate switching activity of the implementing two-level circuits.   The developed software package of two-level optimization includes programs implementing approximate methods. Precise minimization methods are not included in the complex. The reason lies in the fact that obtaining minimal DNF for actual dimension Boolean functions within practically acceptable time poses great difficulties. The current version of the PSLS software complex includes programs for two-level optimization [18] (Figure 3.18), implementing the following methods: • Parametrically adjustable minimization; • Minimization by means of grouping based on classes; • Espresso minimization.   These programs provide minimization with the following potentially possible requirements: • Requirements for optimization object: one completely determined Boolean function or a system of such functions, and one partially determined Boolean function or a system of such functions;

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Figure 3.18  Windows of the software complex in design mode.

•

•

•

•

Requirements for decision method: iterative method of minimization [18], competing intervals method [18], modified minimization method Espresso, and class grouping method; Requirements for the means regarding compatibility of DNF system minimization: separate minimization of DNF system functions and joint minimization of DNF system functions; Requirements for power consumption optimization criterion: not taking into account power consumption and taking into account power consumption; Requirements for account of additional settings, including obtaining paraphrase implementations of DNF, minimization of the number of conjunctions of the resulting DNF system, minimization of the number of conjunction literals of the resulting DNF system, minimization time limit, and algorithm operation mode (for competing intervals method).

2.  Multilevel optimization includes a set of programs for building and optimization of multilevel representation of systems of completely determined Boolean functions. Multilevel representations are given by systems of factorized forms, the conjunction and disjunction of which have limited ranks [16]. This approach approximates the compliance of the multilevel representation with the limits of the target library basis. The current version of the PSLS complex includes programs that implement the approximate methods of joint and separate factorization taking into account power consumption. The initial data for multilevel optimization programs are: • Functional description of the Boolean function system given in the SF language; • Signal probabilities for input terminals of the circuit, if power consumption control is required; • Conjunction ranks limit;

3.4  Logical Design of CMOS LSIC with Reduced Power Consumption •

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Disjunction ranks limit;

3. Synthesis of logical gate circuits includes a set of programs for synthesis and optimization of multilevel circuits of gates AND, OR (using inverters at inputs) with a limited number of input terminals. The main criterion of the multilevel circuit quality is the integral evaluation minimum, which takes into account complexity of the circuit (measured by the number of input terminals of its gates) and aggregate switching activity of all of its terminals (including input, internal, and output terminals).   The current version of the PSLS complex includes programs for logical circuit synthesis from two-input gates, two-input gates of partial functions, and multi-input gates.   The first two of these programs implement methods of multilevel logical circuit synthesis from two-input gates AND, OR (using inverters) for completely and partially determined Boolean functions [20]. The methods are based on BDD building and optimization. The third program implements the method of multilevel logical circuit synthesis from gates AND and OR with the limited number of inputs (number of inputs is determined by the technological basis). The method is based on the combination of algorithms of joint and separate factorization of the DNF systems of Boolean functions taking into account power consumption [19].   The initial data for multilevel optimization algorithms are: • Functional description of the Boolean function system given by the DNF system in the SDF format or LOG format of SF language; • Signal probabilities for input variables, if power consumption control is required; • Limit on the number of input terminals of AND gates; • Limit on the number of input terminals of OR gates. 4. Synthesis from library elements includes a set of programs for technological representation of multilevel circuits of gates AND, OR in element basis of given CMOS VLSIC library. The main criterion of the quality of multilevel circuit from library components is the integral evaluation minimum, which takes into account complexity of the circuit (measured by the number of terminals of all of its elements) and aggregate switching activity of all of its terminals (input, internal, and output terminals).   The current version of the PSLS complex includes programs of circuit synthesis from library elements, which implement approximated coverage methods for multilevel logical circuits of gates AND, OR: • Simplified method of technological representation of gate circuit in library basis; • Method of technological representation of gate circuit in library basis with optimization [20]; • Combined method of technological representation of the system of completely or partially determined Boolean functions in the circuit of library elements.   The combined synthesis method of circuits from library elements includes simultaneous execution of several operations implemented in the known system SIS: minimization of the Boolean functions systems, building

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multilevel circuit from two-input gates AND-NOT or OR-NOT, coverage of this system with given library elements. 5. Verification of project states includes a set of programs, which allow verifying a given pair of design decisions [23]. Verification works for any design decision pairs of the same project (or different projects). The only restriction is the following: the second state must not precede the first one (in the line of performed design operations), that is, the first of the compared objects cannot be more defined than the second one, if at least one description contains behavior uncertainty (e.g., in case of uncertainty or circuit implementation of systems of partially determined Boolean functions). When both compared descriptions are completely defined functionally (e.g., in the case of combination circuits of DNF systems), verification is used to check whether these descriptions are equivalent. If at least one of the descriptions contains behavior uncertainty, verification is used to check whether there is an implementation relation between these descriptions (i.e., whether the first description is implemented by the second one). In cases when the first description is not implemented by the second one, the program verification module allows determining the reason of such nonrealizability, in particular: it determines the interval (or a set) and the function of the initial description or the circuit element, which are the reason of the realizability failure. 6. Power consumption estimation is done using the program of test generation and estimation of power consumption of circuit based on the results of analysis of given test performance. This approach allows evaluating the efficiency of the design decision in the circuit design process after another optimization or synthesis operation, when its implementation on the VLSI chip is not yet obtained. Power consumption estimation within the PSLS complex is done by means of: • Estimation of switching activity of the circuit based on calculation of signal probabilities for terminals of designed object circuit implementation performed automatically after each design operation changing its state; • Calculation of the number of transistor switches for the circuit of library elements on the basis of logical (VHDL or SF) modeling for given test and estimation of average current value consumed in one cycle [21]; • Estimation of power consumption by the circuit of library elements at the circuit level [25] on the basis of test runs and measurement of the consumed current using SPICE modeling.

3.5  Organization Peculiarities of the Reduced Power Consumption in Modern Interface LSICs� 3.5.1  RS-485 Interface Transmitter-Receiver Microcircuits

LSIC interface of the consecutive transmission of RS-485 standard data are widely used in local distribution industrial information collecting and processing networks with the number of receivers and transmitters, connected to the data bus, equal to

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32, 64, or 128, depending on the input resistance of the receivers in use [26,27]. When the central processor controls and processes the data obtained from remote objects, only two of the total number of microcircuits of the distribution network are active at one moment (one microcircuit receives the information, and the second one transmits); the rest do not participate in the exchange process. Due to this fact, in order to reduce the dispersed power of such network, the microcircuits that are not used are switched to the reduced power consumption mode, in other words, standby mode. At first sight, this solution is obvious; however, the study of the evolution of the described microcircuits class will show that it has been implemented in several stages. The special reduced power consumption mode for the family of first RS-485 IC interface with 5-V voltage was implemented only in one microcircuit (MAX483 type) [2] with low data transfer speed (250 Kbps). The time of data distribution delay time and the time of LSIC switching to the reduced power consumption mode and exiting this mode have comparable values and do not require considerable remaking of the device structure by the consumer. For the family of the RS-485 standard interface receiver-transmitter microcircuits of the new generation, which use power current reduced to 3V, the transition to the standby mode with minimum power consumption (to 0.1 μA) is envisaged for both low-speed and high-speed information transmission speed [6]. This fact shows us that the reduced consumption mode is accepted by the consumer, despite the need of certain modernization of the data processing system. Let us take a look at the basic peculiarities of the work of RS-485 standard interface LSIC with the reduced power consumption mode on the example of the most frequently used microcircuit of 5559IN3T type (MAX483 analog). The graphic symbol of the microcircuit with a flow diagram is presented in Figure 3.19, the functional designation of the outputs is presented in Table 3.2, and microcircuit working states are presented in Tables 3.3 and 3.4. The differential inputs of the receiver and differential outputs of the transmitter are united to reduce the number of outputs. A microcircuit consists of one receiver and one transmitter, located on one chip. Let us take a look at the peculiarities of its work. Signals with levels CMOS/TTL are transmitted from the motherboard to the DI transmitter input, are split inside the IC to direct and inverse, transmitted to the RS-485 standard levels, and after that a transmission into a long line is done via output ports of the microcircuit with high load capability. In case of reverse

Figure 3.19  Graphic representation of the receiver-transmitter microcircuit.

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Peculiarities of the Technological Process of Production Table 3.2  Designation of the Outputs of the Developed Microcircuit Output Number Output Name Symbol 01 Receiver output RO 02 Receiver output enable input RE 03 Transmitter output enable input DE 04 Transmitter input DI 05 General output GND 06 Noninversion input (output) of the receiver (transmitter) A 07 Inversion input (output) of the receiver (transmitter) B 08 Power output from voltage source VCC

Table 3.3  Transmitter Truth Table Inputs Outputs RE DE DI B A X 1 1 0 1 X 1 0 1 0 0 0 X Z Z 1 0 X Z Z

Table 3.4  Inputs RE DE 0 0 0 0 0 0 1 0

Receiver Truth Table Outputs A, B RO >+0.2V 1 1 rad/s, the failure is related to the negative drift and at Py < 1 rad/s it is related to the positive drift of threshold voltage of the n-channel MOS transistor (failure criterion ΔVth = +0.45V for Z80A microprocessor). In the transition region (10−1 rad/s < Py< 10 rad), IC failures are caused by the drift of Vth of an n-channel MOS transistor in any direction or by the negative drift of a p-channel transistor. The authors of [36–38] have also identified the presence of maximum at Py= 10−3 to 1 rad/s of the failure dose dependence on Py of CMOS IC of the 564 series, as well as 1526IR6, 1417IR6. Interesting results were obtained in [39] during testing of CMOS transistors using a linear electron accelerator with Ee = 20 MeV and gamma units with Co60 at the dose rate range from 5 ⋅ 10−2 rad/s to 6 ⋅ 109 rad/s. All units have shown that in the case of taking into account the annealing time from the moment of irradiation beginning, the dose rate value practically does not influence the change of CMOS devices parameters at irradiation. It should be noted that charge accumulation in SiO2, the change of carrier mobility in the channel, and other radiation-related effects that appear during long-term exposure at low intensity can considerably differ for various production batches of CMOS devices of the same type [19]. Their difference can be even bigger in case of changes in the design or technology of CMOS production.

4.2  Influence of Radiation on Analog Bipolar Integrated Circuits Analog ICs, which are widely used in the space technology to amplify, transform, and process signals that change according to the analog function law, have some

4.2  Influence of Radiation on Analog Bipolar Integrated Circuits

217

differential characteristics (in comparison with their discrete analogs), which materially determine their radiation tolerance [1, 2, 40]. Analog ICs, as a rule, use direct coupled stages as the use of capacitors in dividing and blocking circuits is almost impossible. Due to the restrictions of microelectronic technologies for LSIC production, the refusal to use capacitors in the submicron LSIC structures will require first the solution to the problem of mode stabilization in terms of direct current, which is difficult to ensure if IC is irradiated. A special approach to designing of mode setting and stabilization circuits is required. The use of direct couplings creates the risk of desynchronization of the operation mode of the following stages due to the changes in the previous stages. As a result, the change of stage operation modes, which form the element chain with direct couplings, results in material final change of the IC output voltage. This circumstance is very often a definitive one for the assessment of IC radiation tolerance. Together with the mentioned parameters of the direct current, the assessment of the analog IC radiation tolerance also demands to take into account the change of IC amplification properties: first of all, the reduction of the amplification coefficient of the processed signal, and in some cases such changes of the input and output resistance, change of passband width, determined by the upper frequency limit ƒu or the frequency of single amplification ƒ1. The change of frequency parameters is very important for the use of analog IC with deep feedback connections. Unfortunately, in this case, there is a possibility of distortion of frequency and transition properties and, in some cases, damage to the device stability. 4.2.1  Radiation Effects in Integrated Operational Amplifiers

Integrated operational amplifiers (IOA) are high-quality precision amplifiers, which belong to the class of universal and multifunction analog microcircuits [41, 42]. Radiation tolerance of analog IC is determined not only by the impact of ionizing radiation on the properties of microcircuit elements (transistors, resistors), but also depends on the IC structure and circuit configuration peculiarities. As the majority of modern analog IC is built based on the IOA structure, it can be used to identify the impact of radiation influences on the properties of analog microcircuits. Radiation tolerance of microcircuits also depends on the IC production technology, in particular, on the way of isolation of elements from each other and from the substrate, as well as on the resistors’ formation technology. In the case of a similar IC structure, the microcircuits with dielectric film insulation and film resistors (instead of diffusion) have a higher resistance to ionizing effects. In microcircuits with isolation using reverse biased p-n-junctions, the radiation tolerance reduces because of the impact of p-n-p-transistors, formed in the places of working transistors’ formation. At the regular operation of IOA, all working transistors in analog devices are in the active area, which is why the active influence of the parasitic transistors is not manifested (they work in the cutoff area), and there is only the impact of reverse currents, which can reach the noticeable value due to large area of the isolating p-n-junctions. When using IOA in nonlinear devices (generators of relaxation and harmonic signals, modulators, demodulators), some transistors can naturally appear in the saturation region during functioning. When the working transistor shifts to the

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saturation region, its collector transfer, which is at the same time the emitter transfer of the parasitic transistor, shifts in the forward direction, and this parasitic transistor starts working in the active area, amplifying the parasitic currents, which can result in microcircuit failure. Independent from the operation mode of the parasitic transistors, their effect is very dangerous during transition processes, which are characterized by the generation of additional ionizing currents, the value of which is materially higher than the value of photocurrents of the regular working transistor (because of the materially larger areas of the isolation p-n-junctions and substrate thickness). It is also necessary to bear in mind that these parasitic transistors, which together with working transistors form a classic semiconductor 4-layer n-pn-p structure, are very often the reason for the no-less-dangerous latch-up effect. That is why, in the majority of microcircuits modifications used for space applications, developers include a special differential stage in each IOA on the input in order to increase the stability of the output potential. In some IOA, this differential stage is included also in the further links as the intermediate amplifier, which at the same time transforms two-phase output into single-phase. The application of differential stages, providing the classic function of suppressing the cophased noises, which no doubt include the effect of deviation from the nominal level of output voltage, caused by the radiation impact, contributes to the considerable increase of the radiation tolerance of IC for space application (SA). Unfortunately, the known circuit configuration solutions in the specialized IOA of customized application, which include microcircuits with increased input resistance, widely used in spacecraft electronic systems, precision and micropower IOA, and fast-responding amplifiers [42], are usually more sensitive to the residual radiation effect, as circuit configuration and technological solutions, applied by developers of civilian microcircuits to achieve the limit values of any parameters, as a rule, result in a decrease of their radiation tolerance. Developers of IC SA should take into account the fact that IOA are very sensitive to radiation impact when working in the sleep mode, or REE energy-saving mode, which is very frequently used in spacecraft. From the point of view of physics, this can be explained by the fact that in the micromode, the degradation processes of the transistor parameters happens at lower radiation fluences. One of the main reasons of the IOA irregular operation is transient ionization effects. Isolation using p-n-junctions is a serious drawback of IOA, working in ionizing radiation fields. The impact of γ-radiation, electronic and high-energy neutron (En > 14 MeV) radiation, results in leakages of rather powerful photocurrents through the isolating p-n-junctions, which very often become the reason for the insulation fault of p and n areas, increase of the dissipated power, occurrence of latch-up effect, and catastrophic breakdown in working and parasitic transistors. In this case from the physical viewpoint, the considerable contribution to the formation of photocurrents belongs to the areas of the substrate contacting the insulated p-n-junctions. Engineers specializing in designing microcircuits of the military and space grades know that these currents can be materially reduced by means of doping the backside of the substrate with gold, which reduces the time of the carrier’s life in the substrate [43]. The most effective technological means of reducing these photocurrents by their numeric value is the use of dielectric insulation [44], as well as replacing diffusion resistors with film resistors.

4.2  Influence of Radiation on Analog Bipolar Integrated Circuits

219

These methods were effectively implemented in the amplifier μA744, produced using the combined technology with dielectric insulation and improved chip surface protection [15, 45]. Apart from the technological means used to increase the tolerance of μA744 to ionizing impact, developers of IMCM have also applied circuit configuration methods: the use of additional transistors in diode connection (to short-circuit photocurrents, which can cause the amplifier failure) and additional resistors between electrical connections circuits of the working elements with power buses. That is why the microcircuit μA744 preserves its functional capacity under the impact of neutron flow up to 1014 neutr./cm2 and ionizing radiation up to 5 ⋅ 106 rad(Si)/s, recovers its functional capacity after pulsed exposure of 5 ⋅ 1010 rad (Si)/sec, and is still used in electronic control systems of SC, LV, and other devices of rocket and space technology. Another effective circuit configuration solution is the inclusion of unipolar transistors to input stages of IOA (as, e.g., in a microcircuit μA740 and domestic ones 544UD1, 140UD8), which contributes to the decrease [46, 47] of their noises levels in the low frequencies zone (ƒ ≤ 103 Hz) and during work using high-resistance signal sources (Rg > 103–104 Ω). The advantage of such IOA is that they are less critical to the choice of the optimal resistance of the Rg.opt. signal sources, which is why the shift of the noise characteristics, caused by radiation, is not accompanied by noticeable increase of noise signals due to inevitable violation of the optimality condition of the nominal Rg. The best noise properties are characteristic of microcircuits with dielectric insulation (noise, related to the formation of photocurrents through insulating p-njunctions, do not form in them), as well as with film resistors (instead of diffusion ones). In this case, low-frequency noises reduce with the decrease of the emitter area and base thickness of the input transistors, which is a characteristic feature in the case of a transition to stricter design rules (e.g., from a 350-nm level to a 180nm level). This is also caused by the use of technological methods, for example, use of various additives (e.g., chrome) in the silicon dioxide (passivation surface) to reduce the SS density [48]. 4.2.2  Radiation Effects in Integrated Voltage Comparators

The circuit configuration solutions for integrated voltage comparators (IVC) in microcircuits of space application differ from industrial IOA mainly in the structure of output stages [42]. In these comparators, the output stages are built in a manner that ensures electric harmonization with digital IC without special harmonizing devices, which transform the output potential levels. That is why IVC can belong to the class of analog-digital ICs. In this case, the radiation tolerance of modern IVC microcircuits of space application is limited in the first place by the part of IC that performs functions of a classic threshold device, the precision properties of which after all determine the limits of the acceptable level of ionizing radiation. Radiation tolerance of the IVC of any digital device of a spacecraft electronic system is limited only by the numeric change of its output potentials V1out and V0out. For precision IVC, the typical representative of which is the microcircuit LM111, the distinctive feature is low input currents (less than 0.1 μA) and considerably larger amplification coefficients (above 105). Due to these enhancements, the precision IVC SA provide better precision of voltage comparison during operation

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on high-resistant sources. However, they lead to the decrease of radiation tolerance, which is first determined by the dependence of the amplification coefficient on the aggregate fluence of ionizing radiation of space factors. This is the result of the transfer of working characteristics to the microcurrents’ area (to reduce Iin. aggr) as well as use of p-n-p-transistor with side injection in the amplifying tract. The results of [41] showed that the standard microcircuit LM111 practically stops performing its functions and amplify at fluences 3 × 1013 electron/cm2. The lowest sensitivity to the radiation is the characteristic feature of fast-responding IVC [42] (e.g., SE527 and AM685, which are widely used in spacecraft). Output potentials V1out and V0out, bias voltage Vin.b, and input shift current of these microcircuits do not change up to the fluence 1014 neutr./cm2. The most noticeable growth caused by the increase of the fluence is observed in the drift current, which is the natural result of the degradation process of the current transfer coefficient of the input transistor’s base. The higher radiation tolerance of the majority of fastresponding IVC is explained by the use of high-frequency transistors and short time of τTN carriers run.

4.3  The Main Methods of Ensuring Radiation Tolerance of Integrated Circuits The decrease of the IC radiation sensitivity is achieved with the help of various design-technological and circuit configuration methods [49–52]. The first group includes the use of optimal layout (e.g., guard bands), optimal chosen thickness of gate oxide, modes of its formation and annealing, the use of self-aligned lowresistance polysilicon contacts, and the use of dielectric insulation of IVC elements. The second group of methods, apart from the above-mentioned ones, includes the use of special circuit solutions for IC (e.g., circuit configuration compensation of the change of parameters of MOS transistors under irradiation), optimization of IC supply voltage, and use of redundancy systems, including information redundancy LSIC RAM by means of excessive data coding. In Belarus JSC INTEGRAL develops and supplies a wide range of bipolar and CMOS microcircuits, including those intended for use in industrial, space, and other special systems. The main results of this work on improvement of the IC design and technology, ensuring the increase of their radiation tolerance, are presented in [1, 2, 50]. Some issues concerning the optimization of the manufacturing technology of SiO2 films from the point of view of their radiation tolerance were analyzed in a number of works [49–54]. Thus, it has been found that from the range of design parameters of CMOS devices, the highest impact on ensuring their radiation tolerance has a property of thickness of gate and insulation oxides. In this case, the most sensible structure (dose effects) are active MOS transistors (especially n-channel), and parasitic MOS transistors, related to the quality of insulating oxide. That is why temperature mode, mechanical voltage, and uncontrolled impurities have the main impact on the radiation tolerance of CMOS IC. First, these factors result in instability of the IC radiation tolerance properties (e.g., formation of gate oxide leakage currents).

4.4  Radiation Tolerance of Modern and Advanced ICs

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The considerable improvement of the radiation tolerance properties of CMOS IC of space application (limit doses 10,400 rad and higher) can be ensured with the help of technological solutions, in particular, highly doped protection areas that prevent the formation of radiation-induced leakage currents, target optimization of production technology of gate dielectric in MOS transistors, use of special methods of rejecting potentially unstable samples, implementation of special radiationthermal treatment, and a number of other additional nontraditional operations in the manufacturing process of CMOS IC [55–58]. The radiation tolerance of CMOS IC of space application can be rather reliably predicted with the help of special calculation and experimental methods that include corresponding relevant mathematical models and the use of the results of radiation tests of specially designed test MOS transistors during designing [59, 60].

4.4  Radiation Tolerance of Modern and Advanced ICs The analysis of fast development trends in the modern technologies of MOS IC production has shown that with the decrease of linear sizes of the microcircuit elements, the radiation tolerance of devices increases in most cases for Total Ionizing Dose effects [61], although it should be noted that this rather disputable expert conclusion was actually obtained using a limited number of produced samples without the analysis of physical reasons. It should be noted that with the increase of the integration degree of LSIC and VLSIC, characterized by the complex and various nature of in-circuit connections, these connections can be implemented only on the basis of the oxide-insulated components, which have extremely small sizes and volumes of active and passive areas and which operate in electric modes close to maximum permissible for the used materials. This results in formation of certain physical restrictions, which inevitably decrease the radiation tolerance of LSIC and VLSIC in comparison with circuits of low-scale and medium-scale integration [1, 2]. The experts have stated that the real dependence of the changes in the stability on the size of IC elements will have a nonmonotonic nature, as with the reduction of geometrical sizes of the elements; the higher impact will belong to the edge effects, related to the peculiarities of the transfer process of minor carriers through peripheral areas [5]. Indeed, if the useful current is proportional to the channel area, the values of the leakage currents should be proportional to the channel perimeter. It is obvious that with the decrease of the linear sizes the numeric value of the perimeter relation to the area increases, which results in even higher contribution of parasitic effects. That is why at the first stage of technological sizes reduction the stability of devices was increased first using technological methods and by decreasing the dielectric thickness. However, at some specific sizes of the IC elements, the contribution of peripheral areas became prevailing, and the stability began to reduce. The area of such optimal linear sizes depends on the specific applied technology. With the development of technology, completely new physical effects and restrictions began to show up in IC SA, which were not observed before. The typical one is the history of development of SOI and SOS technology. These structures are characterized by very thin layers of active devices (less than one-tenth of a

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micrometer), limited on both sides with dielectric structures. Due to small linear sizes of such IC elements and relatively large electric field intensities, multiple experimentally determined effects are present in such structures, which are caused by small sizes and peculiarities of hot electron kinetics [62, 63]. Some of them decrease the breakdown voltage of the drain and are related to the parasitic impact of the bipolar n-p-n-transistor in n-channel SOI MOS transistor. Others result in the floating body effect (Kink effect) of the output drain-source property. The Kink effect is seen best of all in n-channel transistors and is usually absent in p-channel transistors [3]. In case of short-channel tools, there is degradation of properties, caused by the hot electron impact. However, the second semiconductor/oxide interface has the highest value for the assessment of SOI/SOS structures, which can also have floating potential. The presence of this second interface and the probability of noncontrolled radiation-induced charge in the insulating oxide of the substrate of such microcircuit can lead to formation of a conductive channel’s chain on the backside of the substrate and result in the failure of the microcircuit. The main problem of quantitative estimation of the reverse channel impact on the reliability of IC performance is the fact that, as a rule, this oxide is thick and no voltage is applied to it. Consequently, theoretically, it is difficult to estimate the value of the net charge in the oxide volume, which remains after primary recombination processes, for such structures. Unfortunately, as the negative experience of the analysis of IC SA failures shows, in many cases, this charge can form a bad electric field, and also due to the relatively weak electric field intensities, the radiationinduced charge can depend on the MOS transistor operation mode (drain-source voltage), and its position inside the oxide may change due to this reason. The analysis of physical mechanisms of degradation has shown that the presence of thick dielectrics, in which the transfer of the mobile charge is done rather slowly, in the number of IC SA results in delayed (latent) effects. Such latent relaxation processes [64] are seen in spur increase of positive charge annealing time and formation of SS after some (usually, considerable) time after the irradiation is finished. The diffusion of molecular hydrogen in passivation layers of oxide and its cracking is seen as the main mechanism, which leads to the annealing of a positive charge and SS formation [65], as well as relaxation of the volumetric charge in dielectric substrates. The complex analysis of the information, presented in foreign and national scientific and technical periodical literature and materials from conferences on physics and semiconductor devices technologies [50, 51, 66–69], allows drawing a conclusion that within a comparatively short period of time (the past 5 to 7 years), foreign companies, which specialize in the spacecraft IC sphere, have made a considerable breakthrough in the development of radiation-tolerant IC production technologies based on SOI and SOS structures in CMOS (and in perspective BiCMOS) flow and have actually started industrial production of VLSICs, having overcome the layout rules of 0.5 μm, typical of the CIS (Tables 4.1 and 4.2). At the present moment, the CMOS/SOI technology is used for the production of a wide range of microcircuits with various functional properties and design rules of up to 1 μm. In such LSIC, separate units and elements are completely insulated electrically from one another with sapphire substrate and air or solid dielectric gap. Small linear sizes of semiconductor areas of silicon layers allow producing transistors with end-to-end (to the substrate) geometry of drain-source areas. Due to this,

4.4  Radiation Tolerance of Modern and Advanced ICs

223

Table 4.1  Foreign Radiation-Tolerant Element Base SOI CMOS IC, Operating in Space Conditions RadiationRadiation-TolerRadiationTolerant ant Microcircuits RadiationTolerant Microcircuits Microprocessor Mitel Semicond. Tolerant MicrocirPeregrine Set for Series (former GEC Microcircuits cuits Dynex Semicond. B1825, B1620 Parameter Pleassey) Intersil. Semicond. Corp. JSC NPP Sapfir Operating tem−65 to +150 −55 to +125 −55 to +125 −65 to +150 −60 to 85 perature range, °C Maximum radia- 1 ⋅ 106 105–106 3 ⋅ 105 1 ⋅ 106 3 ⋅ 105 tion dose, rad (Si) Error probability, 1 ⋅ 1012 rate (at which the system fails), rad (Si/s)

Table 4.2  Foreign Radiation-Tolerant Element Base CMOS SOS IC, Operating in Space Conditions Honeywell Master slice 1.5 and 8 million gates 4 and 6 Mbit RAM 16-bit embedded microprocessor

1 Mrad (Si) 1 Mrad (Si) 100 krad (Si)

10–12 errors/(bit day) 10–10 errors/(bit day) 10-s errors/(bit day)

ST Microelectronics 12-bit, 50-MHz ADC Set of standard logic microcircuits Circuits for data transfer equipment

300 krad (Si) 100 krad (Si) 300 krad (Si)

60 MeV/(mg-cm2) 72 MeV/(mg-cm2) 72 MeV/(mg-cm2)

Sandia Nat. Lab. Technology CMOS 6R (0.5 μm; 5V) 1 Mrad (Si) 109 rad (Si)/s 40 MeV/(mg-cm2) Technology CMOS 7 (0.35 μm; 3.3V) 1 Mrad (Si) 1011 rad (Si)/s 40 MeV/(mg-cm2)

the decrease of ionization and heat currents level is ensured, as well as parasitic capacitive links between active elements of microcircuits are suppressed. This results in their higher resistance to the impact of radiation fields of various natures in comparison to LSIC on monolithic silicon [1, 2]. The problem of transition to the production of microcircuits SA with design rules of less than 0.5 μm is solved by means of using SOI structures as the substrate, the defect degree of device layers of which is much lower than that of the silicon films of SOS compositions [68]. At present, several well-known technological options of initial SOI structures production have been developed, which are used in mass production by companies IBIS, Canon (United States), and SOITEC (France). The specialists believe that structures with the best electro-physical properties and quality of device layers are ensured by Smart-Cut technology. It is expected that it will be possible to manufacture ultraLSI (ULSI) with MOS transistors with a channel length of only 5 to 15 nm on the basis of the structures with nanometer thicknesses of cutoff silicon layers, obtained using this method. Thus, Atmel (France) has mastered the new mixed analog-digital technology DMILL, the LSI developed using this technology can tolerate higher radiation

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Peculiarities of the Technological Process of Production

doses; moreover, at present, Atmel has switched to mass production of 0.25-micron technologies CMOS and BiCMOS with 4 layers of metallization; in 2013, it switched to 0.18-micron technologies with 5 layers of metallization. In the market, there are a number of Atmel radiation-tolerant microcircuits that are produced using 0.8-micron BiCMOS technology, which ensures the functional capability with a very low noise level in the case of impact of hard ionizing radiation with a dose up to 10 Mrad and neutron fluence 1014 n/cm2. The analysis presented above shows that the problem of the impact of the penetrating radiation on the properties of bipolar or MOS transistors and corresponding IC remains rather acute. The data in the international literature show that issues of ensuring (predicting and increasing) radiation tolerance of bipolar and CMOS IC, especially advanced IC (CMOS/SOI, BiCMOS, submicron CMOS), are of vital importance for ensuring minimal risk of emergencies of the space equipment at the present time and in the future for the implementation of ambitious space programs of the leading industrially developed countries.

4.5  Recommended Set of Test Elements For Experimental Research on the Radiation Impact on the Silicon Microcircuit Properties Test elements for assessment of the element base of analog bipolar integrated circuits are: ••

n-p-n-transistors with different emitter area;

••

Horizontal p-n-p-transistors with different base width;

••

Vertical p-n-p-transistors with different emitter area.

Test transistor n-p-n- and p-n-p-structures were manufactured in the test module according to the standard epitaxial-planar technology on epitaxial silicon of ntype (KEF-4.5), grown on p-substrate (KDB-10). Silicon oxide was used for structure passivation. 4.5.1  Element Base of Logic CMOS of Integrated Circuits

It is recommended to produce test silicon transistor MOS structures in the test module using the standard epitaxial-planar technology with induced n-type channels (channel length L = 1.5 μm and width W = 50.5 μm) and p-type channels (L/W = 2.0/50.0); when the thickness of the gate silicon oxide is about 25 nm, it is practical to use the polysilicon gate. First, the radiation behavior of the test parasitic n-MOS transistor on thick oxide with polysilicon gate (L/W = 1.2/50.0) and the n-MOS transistor No. 2 (L/W = 50/3) without leakage protection and n-MOS transistor structures with different relation of layout width to the channel length L/W (1.4/50, 1.4/4, 50/4, 50/50) were tested. Each of the structures was represented by two groups of samples: 1T and 2T. Leakage protection was provided for the devices (“ears”). The recommended content of tests for the element base of submicron (0.35 μm) CMOS IC is:

4.5  Recommended Set of Test Elements

225

••

Test MOS capacitors with thick insulating oxide: oxide thickness was 0.38 to 0.52 μm, substrate for the p-type silicon;

••

Test MOS capacitors with thin gate oxide (7.0 nm) on p-substrate;

••

Producing the test MOSFET with n- and p-type channels (channel length and width L/W = 0.35/10.0 μm) using the standard epitaxial-planar technology, test MOSFET should have classic and ring construction (drain is surrounded by the gate).

4.5.2  The Element Base of Electrically Erasable Programmable Read-Only Memories (EEPROM)

It is efficient to research the test elements of LSIC, manufactured by the typical process flow for microcontrollers with integrated EEPROM units, which contain memory cells of two types. The first type is a one-transistor memory cell with parallel erasure, which usually consists of a memory element and n-channel MOS transistor with floating gate. Such an EEPROM cell should be formed in the p-type substrate, where the floating transistor gate is separated from the substrate by a gate oxide layer. A window of a thin tunnel oxide (injector), 8 to 10 nm thick, should be provided in the drain area. The floating gate should be separated from the control gate with an intermediate dielectric. The second tested type is the two-transistor memory cell of classic full functional EEPROM, which usually consists of two n-channel MOS transistors: selection transistor (address transistor) and memory transistor with floating gate. Technologies of manufacturing cell memories of the second type should be basically similar to those of the first type. It is recommended to use voltage stabilizers (VS), operational amplifiers (OA), and voltage comparators (VC) produced by JSC Integral as test objects (Table 4.3). In particular, the following sections contain the results of experimental studies of these production components. Thus, for example, the microcircuit 1467CA2P has 4 voltage comparators with common supply, located on one semiconductor chip, the main function of such comparator is to switch the output level at the moment corresponding to the given excess of the base voltage by the input signal (externally preset activation threshold) and is widely used in spacecraft electronic systems of data processing of various application.

Table 4.3  Tested Analog IC IC Type 1244ENST; 1244EN24T 1252ER1T 1253EI5T; 1253EI24T 1467SA1T; 1467SA2P; 1467S3T 1467UD1T; 1467UD2P 1473UD1T

Functional Application Voltage stabilizer

Voltage comparator Operational amplifier

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Peculiarities of the Technological Process of Production

4.5.3  Logic CMOS IC

In the process of choosing the most optimal circuit design solutions of logic elements recommended for solving the tasks of state corporation Roskosmos, the authors have researched the logic CMOS IC of the 1594T series: 1594LL1T—four logic elements 2OR, 1594LN1T—six logic elements NOT. IC of the 1594T series is a functional analog of IC of 1554TBM series and has a different TTL output. Also six types of CMOS IC of 5584 series were studied (developed by research and design center Belmicrosystems): 5584LP5T (logic elements Exclusive OR), IC 5584IR8T (shift register), 5584TM9T (D flip flops), 5584KP11T (selector-multiplexers), 5584AP3T (inverting three-state buffer), and 5584IE10T (binary counter). The results of these researches can be of interest for the developers of spacecraft of various applications and are presented in the following chapters of this book. 4.5.4  Memory CMOS LSIC

The task to create CMOS LSIC RAM with information capacity 256K, set by the developers of ECB SA, required conducting experimental studies of various designtechnological variants of memory cells (MC) realization, and for this matter the test CMOS LSI IN4K with information capacity 4 Kbit was created (organization 4Kx1). The corresponding test LSIC RAM was designed in three design-technological versions, which differ in values of layout gaps between drain (n+) and protection (p+) areas (1.5 μm for versions No. 1 and 2 and 1.0 μm for version No. 3), and between drain area (p+) and p-tub area (4.5 μm for versions No. 1 and 3 and 4.0 μm for version No. 2). EEPROM 1568RR1 with capacity 2 Kbit (256 × 8), developed and manufactured using CMOS technology and designed for the solution of specific technical tasks of state corporation Roskosmos, were chosen as the test objects. Furthermore, LSIC ROM 1632RT1T and 1835RE2T were studied, correspondingly one-time user-programmable and mask ROM with information capacity 32K × 8 and 128K × 8, manufactured according to CMOS technology. 4.5.5  CMOS LSIC SRAM on the Basis of SOI Structures

The experimental studies were done on SOI structures on wafers with a diameter of 150 mm, manufactured using technologies SIMOX [70], Smart-Cut, and Dele-Cut. SOI structures were selected with the similar thickness of silicon film of 0.23 to 0.29 μm and thickness of insulating oxide of 0.28 to 0.4 μm, and processed at Integral as one batch of wafers with 5 wafers in each of the three SOI technologies. A special test matrix was developed for the research, which contained a set of test elements to control electric parameters of the CMOS LSIC element base to control and optimize their production technology. The test matrix content included CMOS LSIC of static random access memory with capacity of 8 Kbit and organization 1,024 × 8 bit on the basis of 6 and 10 transistor memory cells. These LSICs were developed according to design rules of 1.2 μm for serial CMOS process with the same level of polycrystalline silicon and two metallization levels. The gate oxide, 13 nm thick, was obtained at the temperature 850°C using the pyrogenic oxidization method.

4.6  Equipment and Methods of Irradiating Test Structures

227

4.5.6  BiCMOS LSIC

The test object was LSIC of interface transceiver of serial data 5559IN2T designed for use in satellite telecommunication systems with low dispersed power, corresponding to standards RS-485 and RS-422, level broadcasters, transceiver, and industrial facilities control units. Thus, the LSIC of the transceiver 5559IN2T is the typical representative of the interface microcircuit class. It transforms the input signal of the CMOS level to the differential output signal of the RS-485 standard, which is required to ensure the reliable signal transmission via two-wire long line, and vice versa it transforms the differential input signal of RS-485 level into the CMOS output signal. The minimum sensitivity on the differential input of the receiver is 200 mV in the range of input voltages from −7V to +12V, data transmission speed is 2.5 Mbps. The supply voltage range for the transceiver microcircuit is Vcc = 4.5 to 5.5V. The ambient temperature limit is from −60° to +125°C. Microcircuits 5559IN2T were developed based on the combined technology BiCMOS, which ensures the following properties: low supply current characteristic of CMOS technology, and fast switching of signals characteristic of the bipolar technology. These microcircuits possess the increased protection from electrostatic discharges and high-frequency electromagnetic noises, which is achieved with the help of special technical solutions.

4.6  Equipment and Methods of Irradiating Test Structures and Studied Samples of Microcircuits Irradiation of the semiconductor device samples with gamma-quantum Co60 with energy 1.25 MeV was done on the unit Issledovatel at temperature 300K to 310K. The gamma-radiation dose rate was 50 to 100 rad/s, dose – 105÷107 rad. The dosimetry measurements of the gamma-radiation were conducted with the help of reference glucose detectors DOG-0.05/2 or solid glass detectors DTC-0.01/1.0 with error ±7%. The gamma-unit Issledovatel (Figure 4.2) contains lead-steel protection body, in the middle of which an irradiation machine is installed in the form of three cassettes with 36 isotope sources of Co60 of the GIK-7-2 type in each of them, in general, 108 gamma-sources, which are located around the working irradiation chamber with volume 4,200 cm3. The irradiation time is determined by the formula:

t = D P

where D is the gamma-radiation dose and P is the radiation dose rate, which depends on the product arrangement in the container in the working chamber of the unit. The calculated gamma-radiation dose rate was determined on the basis of reference measurements with the help of reference detectors DOG-0.05/2 in different spots of the Issledovatel unit chamber.

228

Peculiarities of the Technological Process of Production

Figure 4.2  The structural diagram of testing the test structures and IC on gamma-unit Issledovatel: 1 denotes irradiated samples; 2 denotes the working chamber of the gamma-unit; 3 denotes the isotope sources of gamma-irradiation Co60; 4 denotes the radiation protection; 5 denotes the gammaunit control board; 6 denotes the multiwire cable; and 7 denotes the control instrumentation.

The calculations were done based on the radioactive decay law: the number of radioactive nuclei reduces exponentially in time. The irradiation intensity (dose rate) decreases in the same manner:

P = Po exp ( −0.693t ) T1 2 

where Po is the initial gamma-irradiation dose rate and T1/2 = 5.272 years and is the half-life of radionuclides Co60. Irradiation of samples using electrons with energy of 4 MeV was performed on a linear accelerator at room temperature. The electrons flow density was 1011–1012 cm−2s−1, and fluence was 1013÷1015 cm−2. The dosimetry (measurement of electron flow density) was controlled with the help of the Faraday cup. The error of the electrons flow density measurement is ±10%. The general diagram of irradiation of the transistor MOS structures and CMOS IC samples on the electronic accelerator ELU-4 is presented in Figure 4.3. The irradiation of the bipolar and MOS transistor samples in the active mode using gamma-quanta or electrons was performed taking into account design peculiarities of the test microcircuit elements and of the irradiation unit itself. Two eight-wire harnesses are brought to the irradiation area of the gamma-unit through the special openings in the stem. The number of the wires is limited by the number of the simultaneously connected outputs of the test module. During irradiation of the samples the electron accelerator uses the control instrumentation unit and 12-m-long shielded cable for irradiation mode remote control (Figure 4.3). The principal diagram of the connection of n-p-n- and p-n-p-transistors during the irradiation in the active mode of the testing unit is presented in Figures 4.4 and 4.5. The connection was done according to the scheme with common emitter. The

4.6  Equipment and Methods of Irradiating Test Structures

229

Figure 4.3  Diagram of transistor structures and IC irradiation on the electronic accelerator: 1 denotes the electron accelerator; 2 denotes the irradiated structures; 3 denotes the cassette-like holder; 4 denotes the radiation protection; 5 denotes 12-m shielded cable for the irradiation mode remote control; and 6 denotes the control instrumentation unit.

Figure 4.4  Connection diagram of n-p-n-transistors (T1-T3) for gamma-quanta Co60 irradiation in the active mode.

Figure 4.5  Connection diagram of p-n-o-transistor (T4) for gamma-quanta Co60 irradiation in the active mode.

230

Peculiarities of the Technological Process of Production

transistor bias V0 during the irradiation was controlled by the voltmeter (V) and maintained at 5 ± 0.05V. It was set by the constant voltage source of the B5-7 type. As Figures 4.4 and 4.5 show, four transistors were connected simultaneously in the testing module: three n-p-n-type and one p-n-p-type. The base current Ib of each transistor was controlled with ampere-meters A1, A2, A3 (Figure 4.4) and A7 (Figure 4.4) with precision ±5%. The type of ampere-meters was determined based on the experiment duration. The value Ib for all transistors was 10 μA. At the given voltage, the duration was regulated with the help of variable resistors R1 to R4 (430÷450 kΩ). Together with the base current, the emitter current Ie of the irradiated transistors was measured using the ampere-meters A2, A4, A6 (Figure 4.4) and A8 (Figure 4.4) with precision ±5%. As the presented microcircuits show, the current Ie equals:

Ie = Ib ( β + 1)

where β is the transistor current amplification factor. Consequently, the measured value of Ie allowed controlling the change of β during the irradiation of the connected transistors. LSIC testing for tolerance to equivalent impact of pulsed gamma-irradiation was performed with the help of laser simulator RADON-5M. The following modes were used: the laser irradiation wave length was 1.08 μm, the irradiation energy in pulse was 50 mJ, pulse duration was 12 ns, and the maximum value of the imitated dose rate was 1012 rad (Si)/s. The microcircuits were irradiated from above with the lid previously removed. Dosimetry measurements were performed based on the readings of the calibrated laser irradiation detector BKLI-601 with error ±10%. LSIC and test structures were tested for tolerance to equivalent impact of steady gamma-irradiation with the help of X-ray simulator REIM-2. The effective energy of the X-ray irradiation was 10 keV. The equivalent dose rate was 70÷100 rad (Si)/s. Dosimetry measurements were performed based on the readings of the calibrated X-ray irradiation detector BKRI-601 with error ±10%.

4.7  Methods of Measuring Electric Parameters of Test Structures After Irradiation The measuring unit Tektronix 370B was used to control the parameters of bipolar transistor structures (current-voltage properties and current amplification factor) with error ±10% [71]. With regard to the measurements of MOS transistor parameters, the currentvoltage properties, threshold voltage, and slope value were performed using the standard measurement device and the automated measuring device of transistor parameters. The error of the measurements was ±10%. CV characteristics of MOS structures were measured using the automated digital LCR measuring unit E7-12 at frequency 1 MHz with error ±10%. The parameters of logic CMOS IC and analog bipolar IC were measured using automated measuring system AMS Dakota with error ±10%.

4.7  Methods of Measuring Electric Parameters of Test Structures After Irradiation

231

4.7.1  Methods of EEPROM Parameters’ Control 4.7.1.1  EEPROM Cell Control

The value of the threshold voltage of the memory element of the EEPROM cell (transistor with floating gate) is controlled in the programmed and erased state before and after irradiation. The memory element of the EEPROM cell (MOS transistor with floating gate) is programmed according to Figure 4.6. The programming mode parameters were: ••

Drain voltage Vd = 0V;

••

Source voltage Vs = 0V;

••

Substrate voltage Vsub = 0V.

The programming voltage impulse is applied to the memory element gate from the impulse generator, with an impulse amplitude of 14V and an impulse duration of 1 ms. The control of the threshold voltage after programming is done according to the diagram presented in Figure 4.7. The memory element of the EEPROM cell (transistor with floating gate) is erased according to the diagram presented in Figure 4.8. Erasing mode parameters: ••

Gate voltage Vg = 0V;

••

Source voltage was not determined (interruption);

••

Substrate voltage Vsub = 0V.

The erasing voltage impulse is applied to the memory element drain from the impulse generator, impulse amplitude 14V, impulse duration 1 ms. The threshold voltage after programming is controlled according to the diagram presented in Figure 4.7.

Figure 4.6  Diagram of programming the memory element of EEPROM cell.

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Peculiarities of the Technological Process of Production

Figure 4.7  Threshold voltage control diagram.

Figure 4.8  Diagram of erasing the memory element of EEPROM cell.

4.7.1.2  EEPROM Unit Control

It is controlled before and after irradiation: supply current, high and low input currents, and functional control of EEPROM unit in the programmed state according to the structural diagram, presented in Figure 4.9. ••

D1: microcircuit;

••

G1: supply voltage source 4.0÷6.0V;

••

G2: direct voltage source 0.0÷6.0V;

••

G3: direct voltage source 4.0÷6.0V;

••

G4: generator of positive polarity impulses with amplitude equal to the supply voltage Es;

••

G5: constant voltage source 4.0 to 6.0V;

••

A1: DC micro ampere-meter;

••

S1, S2: switching devices;

••

R1-R8: resistors with resistance 1.0 kΩ ±5%.

Group A includes outputs 01, 03, 04, 08 to 16, 21 to 23, 25 to 28, 32 to 34, and 47. Group B includes outputs 35 to 40, 45, 46.

4.8  The Experimental Research Results of the Penetrating Radiation

233

Figure 4.9  Structural diagram of EEPROM unit activation during testing of electric parameters and FC control.

4.8  The Experimental Research Results of the Penetrating Radiation Impact on the Parameters of Bipolar Transistor Structures This section contains research results of gamma-radiation impact on the parameters of test transistor structures (elements of analog bipolar ICs) [72–81]. The radiation changes of transistors’ parameters are determined by design and technology properties of their manufacturing, electrical operation mode, influencing radiation parameters [4]. In particular, the study was aimed at the impact of the electrical mode during irradiation of test transistor n-p-n- and p-n-p-structures, as well as the time stability of their parameters after irradiation. The test samples with gamma-quanta Co60 were irradiated in the active electrical mode (voltage on collector Vc = 5V, base current Ib = 10 μA), as well as in passive electrical mode (Vc = 0, Ib = 0). The gamma-radiation dose rate was 800 rad/s, dose of 105–107 rad. The following parameters of the test transistors were controlled: •• ••

••

••

Direct current β amplification factor (VC = 5V, Ib = 10 and 100 μA); Leakage currents Vleak of the collector: emitter junctions Ice0 (VC = 40V), collector junction base Icb0 (VC = 40V), emitter junctions base Ieb0 (Ve = 5V); Breakdown voltages Vbreak of collector: emitter junctions Vce (Ic = 10 μA), collector junction base Vcb (Ic = 10 μA), emitter junction base Veb (Ie = 10 μA); Voltage drop at the emitter: base junction Veb (Ib = Ic = 100 μA) forward shifted Vforw.

234

Peculiarities of the Technological Process of Production

Also the study of the stability of the irradiated transistor parameters was performed. It has been found that the most unstable parameter is the n-p-n-transistor amplification factor. For example, after the irradiation with dose D = 5.7⋅106 rad, the amplification factor of n-p-n-transistor noticeably often recovered within about 100 hours and entered saturation at a longer period of time; in case of p-n-p-transistors the amplification factor after irradiation practically did not change. Here Δβ = β − β0, where β0 is the amplification factor value before irradiation. Table 4.4 contains the test results of transistors under the impact of gammaradiation. Out of all the parameters of the transistors of two types, the most sensible to the radiation was the amplification factor, especially at low base currents. The breakdown voltage and the forward drop at the emitter-base junction practically did not change. Leakage currents have increased by about 10%, mainly for n-p-n-transistors. At 102 hours after irradiation, the leakage currents practically returned to the initial values before irradiation, the amplification factor recovered more noticeable at low base currents, and other parameters with the flow of time remained unchanged. Figure 4.10 shows the typical degradation of output VAC of n-p-n-transistors, influenced by gamma-radiation. We can see that after the irradiation with dose D = 106 rad the output current considerably decreased, and the amplification factor decreased by an order of magnitude. The impact of gamma-radiation on the amplification factor of transistor n-pn-structures at different base currents has nonmonotonic nature (Figure 4.11). A considerable degradation of the amplification factor is observed after the impact at D = (1−5) ⋅ 106 rad. At higher radiation doses, the β degradation decreases (Figure 4.12). The change of transistor parameters in the active electrical mode during and after gamma-irradiation was studied. In case of irradiation with dose D = 106 rad, the amplification factor of the n-p-n-transistor decreased rather noticeably, and after irradiation it partially recovered within ~1,000 hours [Figure 4.13(a)]. In case of p-n-p-transistors the amplification factor after irradiation recovered very little [Figure 4.13(b)].

Table 4.4  Impact of Gamma-Radiation (D = 5.7 to 106 rad) on the Parameters of Test Transistors

Β Transistor Type Impact Mode Ib =10 μA Ib=100 μA n-p-n Before irrad. 200.0 78.0 5 min after irrad. 11.6 31.5

p-n-p

102.5 h after irrad. Before irrad. 10 min after irrad. 102.5 hours after irrad.

Ileak, nA

Vbreak, V

Vforw, V

C-E C-B E-B C-E E-B C-B E-B 18 15 13 57.4 7.2 69.0 0.68 30 30 10 61.0 7.3 65.0 0.71

27.0

40.0

18

16

12

63.0 7.35 67.0

0.72

75.0 2.5

20.5 3.4

40 20

15 25

14 20

53.0 80.0 79.0 60.0 69.0 79.0

0.66 0.66

2.9

4.0

15

15

13

63.0 69.0 76.0

0.65

4.8  The Experimental Research Results of the Penetrating Radiation

235

Figure 4.10   Change of amplification factor of n-p-n- (1, 2) and p-n-p- (3, 4) transistors depending on the time after irradiation (D = 5.7 ⋅ 106 rad): 1, 3 denotes Ib = 10 μA; and 2, 4 denotes Ib = 100 μA.

Figure 4.11  Output VAC of n-p-n-transistor (a) before irradiation, β = 195 and (b) after irradiation (D = 106 rad), β = 23.1.

The impact of the gamma-radiation on the amplification factor at different electrical operation modes of test transistors is presented in Figure 4.14. A considerable degradation of the amplification factor is observed after the impact up to D = (1–4) ⋅ 106 rad. At higher radiation doses the β degradation decreases. The exclusion is the passive mode of p-n-p-transistor irradiation, where a practically linear growth of the value Δβ is observed [Figure 4.14(b)]. It should be noted that the n-p-n-transistor is characterized by a considerable change of the amplification factor under the irradiation in the passive mode, in comparison with irradiation in the active mode [Figure 4.14(a)]. Bipolar transistors change their properties under the irradiation mainly because of the decrease of the life time of minor charge carriers due to the recombination in radiation centers in the active areas of devices. The use of isoplanar technology resulted in semiconductor-dielectric interface approaching the working areas of

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Peculiarities of the Technological Process of Production

Figure 4.12  Dose dependencies of the change in the n-p-n-transistor amplification factor: 1 denotes Ib = 10 μA, 2 denotes Ib = 100 μA.

Figure 4.13  Amplification factor value for (a) n-p-n- and (b) p-n-p-transistors depending on time during and after irradiation (D =106 rad).

Figure 4.14  Gamma-radiation impact on the amplification factor change in (a) n-p-n- and (b) p-np-transistors in passive (1) and active electrical working mode (2): points indicate experiment, and lines indicate calculation.

4.9  Experimental Research of the Ionizing Radiation

237

bipolar transistors, and in its turn this resulted in the increase of the impact of the surface state density and accumulated charge in the insulating oxide on their properties. That is why in a number of cases surface radiation effects are determining for bipolar transistors [1, 2, 4]. The obtained results are explained by the impact of volume and surface radiation defects. In the first case the decrease in the lifetime of minor charge carriers in the base area of the transistors due to the formation of recombination centers should be taken into account in case of β decrease [4]. In the second case the acceleration of the surface recombination results in the decrease of the amplification factor due to the increase of the surface component of the base current, and the increase of leakage currents [1, 2]. It is obvious that the changes in parameters of the studied bipolar transistors are related to structural damages and to ionizing processes of charge incorporation in passivation (protection) oxide in the base area and the bulk charge of emitter junction [1, 2]. In this case, in n-p-n-type devices, the bulk charge in oxide has the highest impact on the surface recombination, and in pn-p-devices the charge in the surface states on the Si-SiO2 interface has the highest impact. This explains the different impact of the electrical mode on the parameters of different types of transistors during irradiation (Figure 4.14). The reduction of β degradation, in the case of large irradiation doses (107 rad), can be explained by the decrease of the impact of the net effective charge of the dielectric due to the compensation of the holes positive charge in the volume SiO2 with the electron negative charge, captured in traps close to the Si-SiO2interface at considerable increase of surface state density [4]. Partial recovery of the value β after the irradiation is caused by the relaxation of the bulk charge in the dielectric due to tunneling of electrons from fast surface states [1, 2]. Usually, n-channel MOS transistors exposed to high doses of radiation are characterized by the threshold voltage degradation decrease due to the increase of the density of negatively charged surface states, which compensate the positive charge in SiO2 [1, 2, 4]. This means that surface effects influence the researched bipolar transistor structures under the impact of gamma-radiation of up to D = 107 rad. Thus, it has been found that at high irradiation doses (107 rad) a decrease of the parameter degradation in the bipolar transistor structures is observed. In addition, a somewhat higher radiation tolerance was found in bipolar devices in passive electrical mode in comparison with irradiation in the active mode.

4.9  Experimental Research of the Ionizing Radiation Impact on the Parameters of Bipolar Analog Integrated Circuits This section contains the research results of radiation impacts on analog bipolar ICs (operational amplifiers, comparators, voltage stabilizers) [82–85]. The integrated bipolar comparators 1467SA2P and operational amplifiers 1473UD1T were studied during exposure to the gamma-radiation Co60. The controlled parameters of comparators 1467SA2P include offset voltage VIO; input offset current IIO; input bias current IIB; supply current ICC; low output current IOL; low output voltage VOL; output leakage current IOH; and voltage amplification factor AUOL.

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Peculiarities of the Technological Process of Production

The following parameters of the operational amplifiers 1473UD1T were tested: supply current ICC, offset voltage IIO, input offset current IIO, output voltage swing Vo+(-), input current II, influence coefficient of the instability of power sources on offset voltage Ksvr, reduction factor of input common-mode voltage Kcmr, voltage amplification factor AU, input differential resistance RIN, gain bandwidth (GBW) (in case of the closed feedback circuit), maximum slew rate low to high(SRLH), and maximum slew rate high to low (SRHL). The impact of gamma-radiation on the parameters of the comparators 1467SA2P has nonmonotonic nature (Figures 4.15 to 4.17). After the radiation impact at D = 103–5 ⋅ 106 rad, a considerable degradation of main parameters takes place. Although at D = 5 ⋅ 106–107 rad, a reduction of degradation of AUOL, as well as of VOL and VIO, is observed. The dose dependencies of the changes in parameters of the operational amplifiers 1473UD1T have a more complex nature (Figures 4.18 to 4.22). Similar to the comparators, a slight recovery of separate parameters (Ksvr, AU, GBW) is observed in operational amplifiers at large radiation doses (up to 107 rad). The degradation β reduction effect (for transistors) and AUOL (for comparators and operational amplifiers) in case of large radiation doses (107 rad) can be explained by the decrease of the impact of the net effective charge of the dielectric due to the compensation of the holes positive charge in the volume SiO2 with the electron negative charge, captured in traps close to the Si-SiO2 interface, at considerable increase of surface state density [4]. Partial recovery of the value β after the irradiation is caused by the relaxation of the bulk charge in the dielectric due to tunneling of electrons from fast surface states [1, 2]. Based on the experimental data the tolerance limits Dlim were obtained (radiation doses, at which the parameters of devices overstep the limits indicated in specification) for test transistors (Table 4.5), comparators (Table 4.6), and operational amplifiers (Table 4.7). Based on the data from Tables 4.7 and 4.8, it is possible to draw a conclusion that the radiation tolerance of lateral p-n-p-transistors is 5 to 10 times lower than that of the n-p-n-transistors. In this case, the degradation of p-n-p-transistors

Figure 4.15  Relative changes of supply current Icc (1), output leakage current Ioh (2), and voltage amplification factor AUOL (3) of the comparators depending on the radiation dose.

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239

Figure 4.16  Relative changes of input bias currents Iib+ (1) and Iib–(2) of the comparators depending on the radiation dose.

Figure 4.17  Relative changes of the low input voltage Vol (1) and offset voltage Vio (2) depending on the radiation dose.

Figure 4.18  Relative changes in the supply current Icc (1) and input differential resistance Rin (2) of the operational amplifiers depending on the radiation dose.

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Figure 4.19  Relative changes in input current Ii (1), influence factor of instability of power sources on the offset voltage Ksvr (2), and voltage amplification factor AU (3) of the operational amplifiers depending on the radiation dose.

Figure 4.20  Relative changes in the output voltage swing Vo+ (1), Vo– (2), and reduction factor of the input common-mode voltage Kcmr (3) of the operational amplifiers depending on the radiation dose.

Figure 4.21  Relative changes in the offset voltage Vi0 (1) and input offset current Ii0 (2) of the operational amplifiers depending on the radiation dose.

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241

Figure 4.22  Relative changes in the gain bandwidth (GBW) (1), maximum slew rate low to high(SRLH) (2), and maximum slew rate high to low SRHL of the operational amplifiers depending on the radiation dose.

Table 4.5  Levels of Test Transistors Tolerance Based on the Amplification Factor β (at Ib = 10 μA) Transistor Type Dlim, rad × 100 n-p-n-transistor, emitter area Se = (18 × 17) μm2 (1.0–1.5) ⋅ 103 n-p-n-transistor, emitter diameter De = 22 μm (3–4) ⋅ 103 2 Lateral p-n-p-transistor, Se = (20 × 20) μm (2–3) ⋅ 102 Lateral p-n-p-transistor, base thickness Wb = 11 μm, De = 26 μm (4–5) ⋅ 102

Table 4.6  Tolerance of Comparators 1467SA2P According to Basic Parameters Parameters Dlim, rad 100 Supply current Icc-5v 105 Output leakage current Ioh 105 Low output current Iol (5–6) ⋅ 102 Low output voltage Vol (5–6) ⋅ 102 Offset voltage Vi0 1.5 ⋅ 103 Input offset current Ii0 Input bias current Iib+ Input bias current IibVoltage amplification factor AUOL

105 0 is preserved, so for the subthreshold mode, it is possible to take Id ≤ 0.1 μA. Then a conclusion is made from (5.13) that for NOT logical elements (at M = 1, Nn = 1), Icons ≤ 0.15 μA. For logical elements 2AND-NOT (at M = 2, Nn = 2), Icons ≤ 0.3 μA. Consequently, the consumption current of logical elements CMOS IC 1594LN1 and 1594LA3 will remain within the SOW at the irradiation up to Dy = 107 rad. The switching voltage Usw is determined as the input voltage, at which the direct line Uout = Uinp crosses the IC static transmission characteristic. In the case of irradiation, a shift of the static transmission characteristic occurs. Then, in the general case, the parameter Usw after irradiation can be calculated after switching on one of M outputs based on the equation [8]:

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313

U sw = [(Usup − U p0 + ΔU p )a + U n0 + ΔU n ] / (1 + a)



(

) )

a = a0  K p / K p0 / ( Kn / Kn0 )  

(

a = Aa K p0 / Kn0

1/2



1/2

(5.15)

The values ΔUp and ΔUn are determined based on (5.1) to (5.3) and (5.4) to (5.6); Kp/Kp0 and Kn/Kn0 are determined from (5.7) to (5.9) and (5.10) to (5.12); Aa = 1 for logical elements NOT; Aa = 1/2 for logical elements 2AND-NOT. The values of coefficient Aa in the general view are presented in Table 5.1. Before irradiation, the switching voltage Usw0 is determined by formula:

Usw0 = [(Usup − |Up0)a0 + Un0]/(1+αo)

(5.16)

So the change of the switching value ΔUsw under the irradiation is determined from (5.15) and (5.16) as:

ΔUsw = Usw – Usw0

(5.17)

The response rate of CMOS logical elements is determined by the signal distribution delay time t10sd t01sd, which are calculated using the equations [7]:

t10sd = C Usup/[2AnKn(Usup – Un)2]

(5.18)



t01sd = C Usup/[2ApKp(Usup – |Up|)2]

(5.19)

where C = Cout + Cl is the summarized capacity at the IC output (Cl is the load capacity); An and Ap are the coefficients that depend on the number of inputs of logical elements (Table 5.1). The impact of irradiation on the dynamic parameters of CMOS IC can be best of all analyzed based on their relative changes, taking into account (5.18) and (5.19):

t10sd/t10sd0 = [(Usup – Un0)/(Usup – Un0 – ΔUn)]2Kn0/Kn

(5.20)



t01sd/t01sd0 = [(Usup – |Up0|)/(Usup – |Up0 + ΔUp|)]2Kp0/Kp

(5.21)

Table 5.1  Values of Coefficients Aα, number of inputs) Logical Element Type NOT AND-NOT 1 1/M Aα = An Ap 1 1

An, Ap (M = OR-NOT M 1/M

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The obtained equations (5.20) and (5.21) are universal for calculating the delay time of any logical CMOS elements, as they do not contain coefficients, which depend on the number of M inputs in IC. Figure 5.5 shows the dose dependences of switching voltage changes ΔUsw and logical CMOS elements NOT, calculated by (5.15) to (5.17), and Figure 5.6 shows elements 2AND-NOT at different electric modes. For comparison purposes, Figure 5.5 shows the experimental data, obtained during irradiation of CMOS IC 1594LN1 with gamma-quanta Co60. A rather good matching of calculated and experimental data is observed.

Figure 5.5  Dependence of changes of the switching threshold ΔUsw on the gamma-radiation for logical CMOS elements NOT (1594LN1) at different electric modes: 1 to 3 denote calculation; 4 to 5 denote experiment; 1 and 4 denote Ucc = 0V; 2 denotes 3V; and 3 and 5 denotes 5V.

Figure 5.6  Calculation dependences of changes DUsw on the gamma-radiation dose for logical CMOS elements 2AND-NOT at different electrical modes.

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315

The calculated dose dependences of the relative time changes in delay time of any logical CMOS elements (NOT, 2AND-NOT, and other), at different electrical modes, obtained from (5.20) and (5.21), are presented in Figures 5.7 and 5.8. Thus, with the help of the calculation-experimental method, the calculation dose dependences of the basic parameters was determined for test n- and p-channel transistor MOS structures, and two types of CMOS IC: 1594LN1 (logical elements NOT) and 1594LA3 (logical elements 2AND-NOT) at different electric modes in the dose range Dy = 105 ÷ 107 rad. The dependences, obtained by calculation, can be used for predicting the radiation tolerance of CMOS IC of 1594 series within each batch of the same type product.

Figure 5.7  Calculated dose dependences of relative changes t10sd/t01sd of logical CMOS elements at different electric modes.

Figure 5.8  Calculated dose dependences of relative changes t01sd/t01sd.0 of logical CMOS elements at different electric modes.

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5.1.2  Prediction (Selection) Method of CMOS IC According to Radiation Tolerance

Let us take a look on the prediction (selection) method of CMOS ICs based on radiation tolerance with the help of test irradiation and current annealing, recommended for practical use. The method is designated for individual selection of CMOS ICs with increased radiation tolerance, as well as for predicting the IC parameters changes during irradiation. This method can also be used on the input control of products assembly at the enterprises, manufacturing radioelectronic equipment operating in ionizing radiation effect conditions. Due to the use of this method, only those products will be chosen from the batch, the radiation tolerance of which exceeds the resistance value Do, set by technical specifications. The structural diagram of the method is presented in Figure 5.9. The method includes the following components: test irradiation of CMOS IC with parameter controller; selection of IC with increased radiation tolerance; current burnout of the irradiated IC with parameters control; calculation of the dependence of IC parameters; and selective control of the sampling results (prediction). Test irradiation includes marking the products of the batch, irradiation of all ICs with the dose (1 to 3) Do and measurement of criteria parameters in the irradiation process. The selection of IC with increased radiation tolerance is done in such manner that the products, the criteria parameters of which do not comply with the TS standards, during the irradiation are removed from the classified batch, and their failure doses are recorded. Current annealing of CMOS IC is done to recover the initial parameters of the irradiated ICs, which remained after selection. The current annealing is determined for each type name of IC according to a special methodology [4]. After current annealing, the main electric parameters of the chosen CMOS ICs are measured. All microcircuits, the parameters of which meet the requirements of

Figure 5.9  Structural diagram of the CMOS IC prediction (selection) method based on radiation tolerance with the help of test radiation.

5.1  Prediction Methods of Radiation Tolerance of CMOS LSI

317

technical specifications, are accepted as ready for operation in radiation conditions at doses (1 to 3) Do. It should be noted that at short-term current burnout the reliability of microcircuits almost does not decrease in comparison with long-term thermal burnout, as the duration of burnout does not exceed 60 seconds, and the neutralization of radiation-inductive charges in CMOS IMC effectively happens due to complex injection and thermal impact of alternate current, flowing through the IMC structure [4]. The calculation of dose dependence of CMOS ICs parameters is done based on the results of tests of the microcircuits, which have shown the increased radiation tolerance, using the regression analysis. Based on the results of the calculations for this batch of ICs, their radiation tolerance is predicted based within doses (0.1 to 3.0) Do. The selection control of the sampling results is made for each IC part type. The volume of sampling is determined according to technical specifications. The selected microcircuits are irradiated to the dose value Do. During the irradiation process, the critical parameters of ICs are measured. The group with increased radiation tolerance is accepted, if all the selected ICs comply with the requirements of technical specifications. We will analyze the results of radiation selection of ICs based on their radiation tolerance using test gamma-radiation of the sample batch (4 pcs) of CMOS IC of 1554LN1 type (logical elements NOT). The value of radiation tolerance of CMOS IC was determined on the level of radiation dose Do = 1 • 104Gy. The irradiation of IC with gamma-quanta Co60 was done on the Issledovatel unit in the dose range (0.5 to 5.0) Do. The results of test irradiation of samples of CMOS IC 1554LN1 are presented in Figure 5.10. According to TS, the following were accepted as failure criteria: consumption current Icc < 100 nA and switch threshold Vt > 1.5V. As a result, the following IC samples with increased resistance were selected: sample No. 1 (according to the parameter Icc, the permissible dose Dd = 3.2 • 104Gy); sample No. 2 (according to the parameter Icc − Dd = 3 • 104Gy); sample No. 3 (on the parameter Icc − Dd = 1.6 • 104Gy).

Figure 5.10  Dose dependences of CMOS IC 1554LN1 parameters: (a) Icc (1, 2, 3, 4 denote IC sample numbers); and (b) 1 denotes Uout1, and 2 denotes Vt.

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The current annealing of the selected microcircuits1554LN1 was done at the AC value of 500 mA, frequency of 50 Hz, and effect duration of 40 seconds. The selective control of the sampling results was done on samples No. 1 and 2. Table 5.2 contains the initial values of CMOS IC 1554LN1 parameters, values of parameters after the first irradiation at D1 = 1 • 104Gy, as well as after the current annealing. The data after the repeated control radiation of IC at D2 = 1 • 104Gy, where the results were similar to the results after the first irradiation. The data in Table 5.2 shows that for sample No. 2 with the maximum parameters changes, the relative prediction error on parameter Vt was 6.1%, and for parameter Icc it was 9.5%. As it has been noted above, the use of current annealing almost does not influence the reliability of CMOS IC. An additional thermal annealing at 358K during 168 hours was used for the preliminary assessment of CMOS IC 1554LN1 reliability after irradiation and current annealing. CMOS IC parameters after thermal annealing did not deteriorate (Icc = 1.5 to 4.0 nA; Vt = 1.76V to 1.9V), that is, that the IC reliability did not decrease. Mathematic processing of the tests results of the selected CMOS IC samples was done in the following manner. The experimental data were used for calculation of analytical dependences of CMOS IC parameters on the radiation dose. The calculations were done based on the regression analysis program, which allows to determine the dependence type and calculate the pair correlation coefficient R between numerical sequences. The calculation data were considered rather reliable, if the following condition was met: |R| > 0.8. In case of 1554LN1 microcircuit (sample No. 1) for consumption current Icc, switch threshold Vt and high-level output voltage Uout−1, the following analytical dependences of parameters on gamma-radiation dose were determined:

Icc(D) = 0.269 + 24.988D + 1.908D2

(5.22)



Vt(D) = 1.905 – 0.262D + 0.0283D2

(5.23)



UOUT1(D) = 5.009 + 0.0111D − 0.0182D2

(5.24)

Table 5.2  The Change in the Parameters of CMOS IC 1554LN1 After Gamma Radiation and Current Annealing Icc, nA Ut, V Sample Sample Sample Sample Impact Mode No. 1 No. 2 No. 1 No. 2 Before irradiation 1.4 1.0 1.74 1.79 29.6 40.0 1.54 1.55 D1 = 1 • 104Gy Current burnout 4.0 3.6 1.68 1.87 4 32.8 44.2 1.56 1.65 D2 = 1 • 10 Gy

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319

Thus, within a batch of CMOS ICs of this type, radiation tolerance for specific microcircuits can be predicted using test irradiation and selection of IC samples, followed by mathematic processing of the test results using regression analysis. The tests of logical CMOS ICs of 564 and 1554 series have shown that the sampling method error (prediction) of CMOS IC on the radiation tolerance with the help of test electronic or gamma-radiation does not exceed 5% to 10%.

5.2  Calculation-Experimental Methods for Calculation of Radiation Tolerance of Bipolar and BiCMOS Tools This section presents the developed assessments (prediction) methods of radiation tolerance of test bipolar transistors and BiCMOS LSIC, which are described in more detail in [8–11]. The assessment of radiation change of the parameters of test bipolar transistor structures was done with the help of calculation-experimental method with the use of regression analysis. The equation was obtained, which describes the change of the amplification factor for n-p-n-transistor depending on the time after irradiation (D = 104Gy) in the passive electric mode (Figure 5.7):

Δβ = 191.553 – 5.255lgt

(5.25)

The calculation-experimental method was used for assessment of the amplification factor of n-p-n- and p-n-p-transistor depending on the radiation dose. In general, these dependences are described by the second-order polynomial:



Y = A + BX + CX2

(5.26)

where Y = Δβ; X is the radiation dose; and A, B, and C are constant coefficients, the values of which are presented in Table 5.3 for each transistor type. The experimental data, with the help of regression analysis [6], were used for the calculation of dose dependences of parameters of bipolar VCs of 1467CA2P type in the form of third-order polynomials:



AU/AU.0 = – 0.072 + 0.506D + 3.264D2 – 1.436D3

(5.27)



Ioh/Ioh.0 = 0.772 – 0.167D + 0.682D2 – 0.24D3

(5.28)

Table 5.3  The Values of Constant Coefficients in (5.26) Passive Mode Active Mode Transistor Type A B C A B n-p-n 87.318 76.922 −24.532 125.087 95.118 p-n-p 71.649 4.529 0 66.345 29.271

C −35.897 −14.288

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and bipolar OAs of 1473UD1T type in the form of the second-order polynomials:



AU/AU.0 = −4.946 + 18.939D – 1.375D2

(5.29)



Ksvr/Ksvr.0 = −0.072 + 0.506D + 3.264D2

(5.30)

The research of BiCMOS LSIC also included modeling of consumption current change in LSI���������������������������������������������������������������� C��������������������������������������������������������������� 5559IN2T depending on the stationary radiation dose. A regression model was chosen in the form of the second-order polynomial, which has a good reflection of the dependence of Icc(D) at doses up to 2.4 ⋅ 105 rad. In order to find the coefficients of the regression line, the method of least squares was applied. This resulted in obtaining the following analytical dependences of LSIC consumption current (Icc, μA) on the radiation dose (D, 104 rad). Thus, the high-level consumption current for the radiation at T = +25°C is determined by the equation:

ICC = 611.257 – 3.252D + 0.123D2

(5.31)

and the low-level consumption current:

ICC = 357.571 – 2.674D + 0.105D2

(5.32)

The high-level consumption current for the radiation at T = −60°C is determined by the equation:



ICC = 496.086 – 2.645D + 0.129D2

(5.33)

and the low-level consumption current:

ICC = 288.543 – 2.014D + 0.099D2

(5.34)

The obtained calculation dependences (5.27) through (5.34) can be used for predicting the radiation tolerance of bipolar analog IC, as well as for BiCMOS LSICs of these types of tolerance to the impact of stationary ionizing radiation. Due to the differences in the production technology of microcircuits on different enterprises, the obtained calculation dependences can be individually corrected for predicting radiation tolerance of bipolar and BiCMOS ICs within each batch of products of this type. In this case, the refinement of the values of constant coefficients in (5.27) through (5.34) is done on the basis of test irradiation of the test samples from a separate batch of products for each IC part type. The volume of IC sampling is determined according to technical specifications.�

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321

5.3  Calculation-Experimental Method of Predicting Radiation Tolerance of EEPROM MOS Memory Elements This section contains the calculation-experimental method of predicting the radiation tolerance of EEPROM MOS memory elements based on the results of their tests for reliability, developed by the specialists [8]. The regression analysis based on the experimental data was used for the calculation of dependences of the threshold voltage of EEPROM memory elements during irradiation. The dependence UT(D) for recording and erasing state can be written in the following way:



UT = A + BlgD

(5.35)



UT = A1 + B1lgD + C(lgD)2

(5.36)

The following calculation dependences UT(N) can be obtained in the same manner from experimental results using the data re-recording cycles:



UT = A2 + B2lgN + C1 (lgN)2

(5.37)



UT = A3 + B3lgN + C2 (lgN)2

(5.38)

where A, B, A1, B1, C, A2, B2, C1, A3, B3, and C2 are constant coefficients. For example, the following values of constant coefficients were determined for memory cells (5.32) and (5.34): A = 3.701, B = −1.653; A2 = 3.942; B2 = 0.546; C1 = 0.115 The obtained analytical dependences (5.35) through (5.38) can be used for predicting radiation tolerance of the memory elements of EEPROM. In particular, we will receive the following from (5.35) and (5.37):



lgD = [A + A2 + B2lgN + C1 (lgN)2]/B

(5.39)

Consequently, the preliminary tests of sample elements of EEPROM for their radiation tolerance and reliability can be used to determine the values of constant coefficients in (5.25) through (5.39). Then the limiting radiation doses for the permissible values UT are determined within one batch of EEPROM based on the results of the impact of recording cycles.

5.4  Methods of Increasing IC Resistance to the Impact of Penetrating Radiation This section contains the basic methods of increasing radiation tolerance of CMOS and BiCMOS microcircuits [1, 6, 8].

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5.4.1  Construction-Technological Methods of Increasing Radiation Tolerance of CMOS and BiCMOS Microcircuits

The resistance of logical CMOS IC and BiCMOS LSIC to the impact of ionizing radiation, thyristor effect (TE) and static electricity is ensured by the following solutions: use of round gates of MOS transistors, guard bands, use of low-temperature oxidization under the gate (pyrogenous oxidization at temperature T = 850°C), as well as thermal treatment of the gate oxide at T ≤ 850°C. Figure 5.11 shows the sketches of n-channel MOS-transistor topology, used in the studied LSIC, and cross-sections of its vertical profile. The guard band of p+type with the concentration of mixture N > 1018 cm−3, formed under the local layer of SiO2, prevents the possibility of inversion of the productivity type in the radiation process. The peculiarity of this construction-technological solution is the need of meeting an important condition; the guard band area should be made with the space from the drain area for the size dmin ≥ 2.6 μm (Figure 5.11), which prevents the possibility of the effect of drain breakdown voltage reduction. In order to prevent the formation of the conductive channels of the leaks of source-drain type in the area of the gate output, the gate in the local SiO2 layer is placed in the area of p+-guard band on the thin gate oxide. Figure 5.12 presents the sketch of the topology and topology cross-section of the construction of n-channel MOS-transistor with increased resistance to ionizing radiation, where a guard p+-band is formed under a thin layer of gate dielectric during the technological process together with the formation of the drain and source areas of p-channel MOS-transistors. Such a construction of the transistor is used in peripheral units of LSIC chips, as during the radiation process with a dose up to 106 rad, this structure ensures not only the effect of leak prevention in the sourcedrain circuit, but also the higher values (not less than 15V) values of the drain area breakdown voltages. Two groups of samples of MOS structures and logical CMOS ICs based on them were studied. The first group was manufactured according to the standard

Figure 5.11  The topology sketch of n-MOS transistor with (a) increased resistance to ionizing effects and (b, c) cross-sections of its vertical profile.

5.4  Methods of Increasing IC Resistance to the Impact of Penetrating Radiation

323

Figure 5.12  Sketch of (a) the topology and (b) cross-section of the construction of n-channel MOS transistor with increased values of drain-source breakdown voltage values.

epitaxial-planar technology. The resistance of the second group of CMOS ICs to the impact of ionizing radiation was ensured by the above construction-technological methods. Figure 5.13 shows the dose dependences of the threshold voltage UT of p-channel transistor MOS structures, with specific production technology. A considerable increase of UT values is observed during the irradiation of structures, manufactured according to the regular technology, in comparison with radiation-resistant MOS structures. Figure 5.14 shows the dose dependences of current consumption Icc and highlevel output voltage UOH of CMOS IC (logical elements NOT), produced according to the standard technology (curve 1) and special radiation tolerant technology (curve 2). We can see that in the latter case the values of ICC and UOH start changing slightly only at dose D ≥ 105 Gy. Thus, it has been determined that the radiation tolerance of transistor MOS structures and CMOS IC on their basis is considerably determined by the peculiarities of the manufacturer’s technology. The use of construction-technological

Figure 5.13  Dose dependences of the threshold voltage of p-channel transistor MOS-structures, manufactured using (a) the regular technology and (b) radiation resistant technology.

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Peculiarities of the Technological Process of Production

Figure 5.14  (a) Dose dependences of consumption current and (b) relative change of the high-level output voltage of CMOS IC, manufactured using the standard technology (1) and radiation tolerant technology (2).

realization of CMOS ICs, aimed at ensuring their resistance to ionizing radiation, has allowed one to significantly (by 1 to 2 orders of magnitude) increase their radiation tolerance. The novelty of this type of radiation-tolerant CMOS ICs is confirmed by the certificates of official registration of topology of integrated microcircuits [9]. 5.4.2  Standard Construction and Circuit Configuration Methods of Increasing Radiation Tolerance of ICs

The circuit configuration methods of increasing radiation tolerance of ICs envisage the complementation of the known circuit solutions of base elements (flip-flops, amplifiers, comparators, and adders) of new elements (transistors, diodes, condensers) and new connections, including internal (in the semiconductor structure), current and/or voltage circuit re-entrancy, which are aimed at compensating the negative IR impacts on the operation of these elements. Creation of new circuit configuration solutions, as a rule, does not require larger time, performing expensive and long experiments, or expensive technological equipment and materials. Most tasks are solved with the help of numerous experiments and using various CAD packages. The development of circuit configuration method of increasing the radiation tolerance of IC of 4-channel micropower voltage comparator 1467SA3T, manufactured using bipolar technology, was done during the study of impulse ionizing radiation (IIR) impact using laser imitator RADON-5M at temperatures from +25°C to +125°C. The results of the experimental studies of IC 1467SA3T have shown the formation of Single Event Latchup (SEL) under IIR impact, which is not typical of bipolar ICs [Figure 5.15(a)]. The degree of SEL formation was reducing by an order of magnitude at the annealing temperature increase from room temperature to +125°C.

5.4  Methods of Increasing IC Resistance to the Impact of Penetrating Radiation

325

Figure 5.15  Oscillograph records of output voltage of IC 1467SA3T under the impact of IIR with the degree 7.5⋅1010 rad/s (a) before and (b) after exclusion of n-p-n-transistor in diode connection.

The circuit configuration analysis has shown that the thyristor effect appears in the current mirror circuit, in the area of n-p-n-transistor in diode connection, connected with the p-type contact to the power source (Figure 5.16). IIR impact transfers the parasitic thyristor structure to the low-resistant area of transmission property, which causes the flow of abnormally large (ampere) currents in the power circuit. The liquidation of this state of the IC is possible only be means of shortterm forced power cutoff.

Figure 5.16  (a) Part of the electrical diagram of micropower 4-channel voltage comparator and (b) parasitic thyristor structure.

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After the microcircuit was redeveloped, in particular, the n-p-n-transistor in diode connection was excluded from the electric diagram and topology, additional experimental studies of new samples were performed, which have shown that SEL in IC VC was completely excluded at room temperature and at increased temperature [Figure 5.15(b)]. The results of the work confirm the need of performing studies of radiation behavior of bipolar ICs in the temperature range, as well as of control of SEL in ICs irrespective of the production technology, as the unsuccessful circuit configuration solutions may result in SEL even in ICs, manufactured according to relatively SEL-resistant bipolar technology. Let us take a closer look on the new way of increasing the resistance of micropower BiCMOS element to the latch-up effect. The presence of additional (in comparison with CMOS flip-flops) n-p-n-transistors and current-setting resistors in BiCMOS element, besides increasing the area also results in the latch-up effect at increased amplitudes of voltage and current impulses emissions in the supply bus and general bus, stipulated by output currents of n-p-n-transistors. New construction and circuit configuration decision of the basic micropower BiCMOS element (Figure 5.17) allows providing resistance to the latch-up effect without increasing the chip area: MOS-transistors VT1-VT3, two bipolar n-p-ntransistors VT4, VT5, and resistor R1 with limited current in the circuit of VT5 base [Figure 5.17(a)]. Figure 5.17(b) shows the equivalent electric diagram of the same element, but already with the inclusion of actually existing in the volume semiconductors of parasitic elements, which activate the latch-up mechanism, when output voltage currents flow in the power buses. This figure shows these parasitic transistors V6 of p-n-p-type and VT7 of np-n-type of thyristor structure, directly responsible for the latch-up mechanism activation. The equivalent resistor RS1 is a distributed ohmic area resistance of n-type, which connects the p-channel transistor pocket with the power bus. This resistor is

Figure 5.17  (a) Electric diagram of BiCMOS element and (b) equivalent diagram highlighting the parasitic elements of thyristor circuit.

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connected in parallel to the junction emitter-base of the parasitic p-n-p-transistor of VT6 thyristor structure. It is through this area, marked as RS1, that the voltage capacity charge current of BiCMOS element runs, which is necessary for increasing (or preserving) the response rate of the element when it is switched from the logical state 0 to 1 and vice versa. The physics of this solution is in the fact that when choosing (calculating) specific conditions, presented below, the value of the current, running through RS1 at the charge/discharge of the voltage capacity Cl, will not allow one to create the voltage drop value, required for unlocking p-n-p-transistor and activation of the thyristor structure. Figure 5.18 shows the sketch of the vertical structure of this element, and Figure 5.19 shows the sketch of its topological solution in the planar plane. The n-channel transistors VT2 and VT3 are formed in the p-type areas, and p-channel transistor, resistor R1, and n-p-n-transistor VT4 are formed in the n-type areas with a hidden layer. The second n-p-n-transistor VT5 is formed in the n-type area with a hidden layer. As we can see in Figure 5.18, the formation of one common n+-type hidden layer for three circuit components (VT1, VT4, and R1) allows using only one n+type area 7 for contact, instead of three, as it is done in known solutions. Also, this solution ensures the execution of three functions at the same time: 1. Connection to area 1 of VT1 pocket to power bus; 2. Connection of power source Ucc to collector VT4; 3. Ensuring the reverse drift of the resistor R1 pocket area. Obviously, this allows one to significantly reduce the area of the BiCMOS element due to exclusion of the previously required two contacts to the hidden layer 4 of n+ type. As we can see in the equivalent electric diagram [Figure 5.17(b)], the ohmic resistance of the second additional p+-area 7 is connected in parallel to the junction emitter-base of the parasitic p-n-p-transistor VT6 of the thyristor structure, in particular, the increased output voltage capacity current runs via this resistance in the process of switching the BiCMOS element.

Figure 5.18  Sketch of the structure of BiCMOS element with increased resistance to thyristor effect.

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Figure 5.19  Sketch of topology of BiCMOS element with increased resistance to thyristor effect.

Using the known equations, which describe the activation mechanism of the thyristor structure [9], we can easily draw equations for calculation of the maximum permissible value of this resistor, at which the thyristor effect will not be manifesting:



RS max =

p U DDP ICp ⋅ β N

(5.40)

where UPDDP is the direct voltage drop at the junction drain-pocket of the p-MOS transistor VT1; IPD is the transistor VT1 drain current; and βN is the amplification factor of the n-p-n-transistor VT4 base current. Only in the case of excessing the value RSmax at given UPDDP, are the parasitic transistors IPD and βN activated, switching the BiCMOS element to the inactive state. Equation (5.40) is a necessary but not sufficient condition of suppressing the thyristor effect. It is necessary to take into account the impact of the second additional area on the operation. In order to prevent thyristor effect formation in the proposed BiCMOS element, it is necessary to support the specific correlation between values of ohmic resistances of the two implemented additional areas 5 and 7 (p and n+ types). In particular, the following correlation should be met:



p   U peak VT 4 VT 1 VT 6 n  β N  Ic max −   β p  RS 2 < U PEAK  RS1 

(5.41)

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329

4 βVT is amplification factor of base VT4 current; IVT1cmax is the maximum value of N

drain VT1 current at maximum voltage levels at the gate and the drain; RS1 is the ohmic resistance of n-type area 5; RS2 is the ohmic resistance of the additional area 4 7 of p-type; βVT is the amplification factor of the base current of the parasitic tranN sistor p-n-p (drain of p-MOS transistor − n-pocket of p-MOS transistor − p-pocket of n-channel transistor); Uppeak, Unpeak is the direct voltage drop source-pocket correspondingly of the p-channel and n-channel transistors. Using (5.40) and (5.41), during the development of LSIC, the corresponding restrictions are set in the subprogram of the topological editor of the used system of automatic design (CAD), which automatically ensures their execution for any geometrical configuration of elements arrangement in LSIC topology. The study of experimental samples of test BiCMOS microcircuit, designed on the basis of construction-technological solution, has proved the absence of parasitic effect of thyristor structure activation in the whole range of input and power voltages. Based on the results of the conducted studies and technological tests, the libraries of the topological solutions of BiCMOS elements, developed on the basis of the offered construction, which realize standard logical functions, are implemented in CAD of the developing departments of OJSC Integral. The increase of the resistance to the IR impact of CMOS of logical IC requires a special structure in comparison with common and industrial ICs with construction-technological know-how, as well as specific electric parameters of IC components [9]. Such changes in the active structure of components considerably increase the parasitic capacities of the components and deteriorate the response rate of ICs, which causes the need to apply special circuit configuration solutions for their compensation. Let us first take a look at some general issues of circuit configuration design of IC series. In order to ensure the performance capacity, reduction of electric parameters loss and ensuring the optimal connection of ICs of single series and of ICs of different series in the content of the equipment, the series of fast-responding logical CMOS ICs should be developed on the basis of a single circuit configuration basic elements (BE) library. Such an approach also allows ensuring technological properties of ICs, construction-technological reserves in electrical parameters, maximum permissible operation modes and reliability properties [10]. The circuit configuration BE library includes: 1. 2. 3. 4. 5.

Basic logical elements (LE); Memory elements (ME); Input coordination elements (CE); Output coordination elements; CE protection elements from input of electrostatic charge (ESC).

During the development and design of electrostatic circuits of fast-responding CMOS ICs, special attention should be paid to circuit configuration optimization, which allows removing the restrictions, imposed by the parameters of active IC components with special structure, in particular:

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1. Optimization for achieving the maximum response rate of electric parameters of the active IC components with high threshold voltages, which ensure the resistance to destabilizing factors; 2. Optimization for achieving maximum response rate of the signal circuits and correlations of the MOS transistor sizes; 3. Optimization of electrical circuits of IC elements to minimize their area on the IC chip. The basic LEs in IC should be represented by the standard CMOS static LEs of AND-NOT, OR-NOT type, the electric circuits of which should be optimized, taking into account the factors, described above. In memory elements, EL of the series of fast-responding logical CMOS ICs are usually elements of the static type and are designed on the basis of R-S-flip-flops, built on OR-NOT-type LEs. The construction of active ME components should be optimized to ensure stable storage of data under IR impact. More complex ME, clocked by the level and front of D and Dt-type, should be built on the basis of passing keys with two-phase clock synchronization, in order to increase the response rate. For input coordination elements, a standard CMOS inverter (transistors VT1 and VT2) (Figure 5.20) with switching threshold Ucc/2 should be used as the basic input CE in the series of CMOS of fast-responding ICs. The constructions of transistors VT1 and VT2 should also be optimized for the minimum loss of threshold voltage and CMOS CE under IR impact and temperature. In order to coordinate the IC series with other types of ICs, first of all TTL, it is recommended to use input CE with TTL input levels in IC. In order to increase the noise resistance, it is recommended to use input CE with hysteresis in inputs on the IC series. For output CE, all IC series should be bufferized in the output to meet the requirements on output currents and voltages and optimized for work under the conditions of IR impact and wide temperature range. The main problem for the series of fast-responding CMOS of logical ICs due to steep wavefronts of output signals is the problem of overshoots in output signals, generated on parasitic inductance of IC power circuits. The task of reducing the shootouts in the output signals should be solved by optimizations of RC circuits of

Figure 5.20  Electric diagram of the base-inverter IC Six inverters with CMOS input levels.

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output cascades for smoother formation of wavefronts of the output signals without considerable reduction of response rate. Thus, the output CE with emissions suppression (Figure 5.19) contains additional components VT7 and R, the implementation and optimization of which allows increasing the duration of wavefronts of output signals and reduce the emissions amplitude from 2.3V to 1.6V. Another rather important requirement to CMOS integrated circuits, which set the modern requirements to their use in space equipment production, is the resistance to the static electricity impact. The main requirement, which is set to the protection elements, is the efficiency of charge biasing, which is characterized by the fact that potential increase in the static electricity impact mode should not result in the irreversible breakdown of the gate insulator or thermal breakdown of p-n-junctions of the protection circuit elements. Due to the fact that impulse currents can have higher values (for example, an impulse current of 2A runs through a protection circuit, resistant to 3-kV discharge), the efficiency of protection circuits is greatly determined by their construction, area, and resistance value. In order to ensure the required degree of the microcircuits resistance to the impact of static electricity, it is recommended to use EP specially developed for these purposes (Figure 5.21). In this case the protection of the IC input consists of two stages. The first stage includes diodes VD1 and VD3 for input power and VD2 for input ground. In order to limit the potential level in the CE inputs, which is stipulated by physical inactivity during the work of diode structures, a limiting diffusion resistor R = 300 ± 100Ω. In the close vicinity to the input CE, the second protection stage is located on the IC chip, which contains a p-MOS transistor VT1 and n-MOS-transistor VT2 in diode connection, the drains of which are connected to the elements of the input buffer (gates or drains of the input transistors). Protection elements of the output or input have diode structures VD3 and VD4 with a large area, which are formed with the drains of output transistors VT5 and VT6,

Figure 5.21  Electrical diagram of EP from the static electricity impact.

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as well as transistor VT7, located between the buses Ucc, 0V, and which ensure the efficient and even drainage of static electricity, preventing the destruction of the gate insulator and IC device output failure. The novelty of the EP construction of this type is confirmed by author’s certificate [10]. The EP of IC series should provide the resistance to the impact of static electricity on the level not less than 2,000V. Topological solutions of the protection elements from static electricity are standard for all ICs of the series and should be included in the content of the circuit configuration of the elements library. Thus, in this section, we described the general issues of designing circuit configuration of the series of fast-responding CMOS of logical ICs, resistant to destabilizing factors, actual examples of electric circuits of internal elements of the series of fast-responding logical CMOS ICs are presented and described, we also described the protection circuits from ESC, and the circuits for suppressing noises in the IC outputs. 5.4.3  New Construction and Circuit Configuration Methods of Increasing Radiation Tolerance of CMOS LSIC

Let us take a look at a specific example of one of the relatively new methods of increasing the radiation stability. Two new additional protection transistors T3 and T2 are introduced into the known standard circuit of a logical inverter [Figure 5.22(a)], and the n-channel transistor T3 has the increased degree of channel area doping, p-channel transistor T2 is formed with the reduced channel doping. Transistors T4 and T5 perform the switching function, in case of necessity replacing (cutoff) the corresponding working transistors T1 and T6, and the doping degrees of the VT4 and VT5 transistors channel areas are calculated in such manner, that in case of absence of ionizing radiation the transistor T4 is always open, T5 is always closed. The circuit works in the following way. During the IR impact on the microcircuit in the working mode, the unfavorable change of threshold voltages of

Figure 5.22  CMOS inverter with increased radiation tolerance: (a) diagram of radiation tolerance of CMOS inverter; and (b) dependence of the threshold switching on the dose: 1 indicates the standard inverter, and 2 indicates the inverter with protection transistors.

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the main working transistors T1 and T6 occur. When these transistors reach the critical values of their threshold voltages (from the point of view of noise resistance), the switching transistor T4 includes into the working circuit a protection p-channel transistor T3, and at the same time the switching transistor T5 deactivates the working n-channel transistor T6 and the inverter continues performing its functions. Figure 5.22(b) shows the dependence of the numeric values of the switching CMOS of the inverter Uthr on the value of radiation dose D in case the supply voltage is Usup = 3.3V. As we can see, the implementation of protection transistors T3 and T2 allows, in comparison with the classic inverter (curve 1), one to increase the overall dose of ionizing radiation by 3 to 5 times (curve 2), at which the inverter still preserves its operating capability. The developers of highly reliable radioelectronic systems, which work under the harsh operation conditions, including the impact of various types of IR, are interested in the use of modern super-integrated element base, manufactured on the basis of submicron design standards (0.5; 0.35; 0.18 μm). However, during the last 2 years, unjustified reduction of this interest is observed due to the facts of failures of a number of technical facilities, which were constructed using submicron LSICs. We have offered a number of new technological solutions, which allow widening the area of submicron LSIC application under IR impact, the essence of one of such of the methods that we will describe next. It is well known that the decrease of geometrical sizes of transistors allows improving the technical-economic parameters of LSIC in the process of their production (reduce the cost, increase the response rate, reduce the power consumption, and so forth). However, the reduction of geometrical sizes of transistors leads to various parasitic effects, resulting in reduction of the output percentage, radiation tolerance and reliability of ICs. In particular, when the MOS transistor channel is decreased, the effect of hot electrons appears, the internal electrical field stress increases, which stipulates the increased power of carriers (electrons and holes), which pass through this transistor channel up to formation of the avalanche process, during which a part of additionally generated excessive carriers are trapped in the gate oxide area, creating the fast states there, which have negative influence on the reliability and RR of ICs. In particular, these states are responsible for the reduction of the transistor amplification factor, appearance of the induced leak currents, reduction of output voltages values, which in the end is one of the main reasons of a material decrease of LSIC radiation tolerance. The well-known circuit configuration means of solving this problem [1, 6], the reduction of the value of power voltage of LSIC, does not solve this problem in general and is not always applicable in actual cases (e.g., it is not always possible to use a power voltage of 3.3V instead of 5.0V). The new circuit configuration method of increasing radiation tolerance is based on the fact that additional protection MOS transistors and special internal protection potential output are introduced to the construction of the base logical element, the CMOS inverter, which compensates the unfavorable changes in the electric properties of main (working) transistors, mainly stipulated by the activity of hot carriers, which appear during the transfer of the production process of nonsubmicron LSIC to the modern technological processes with stricter technological standards.

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Figure 5.23 shows an electric diagram of the simplest logical CMOS inverter, explaining the essence of the proposed solution, where the source of the protection transistor T2 is connected with the drain of the first transistor T1, the drain of transistor T2 is connected with the source of the second transistor T3, and the protection voltage Up is supplied to the gate of the protection transistor T2, and, as it can be seen, the transistors T1 and T2 represent the usual complementary pair, known as the CMOS transistor. The voltage of the input logical signal UIN is supplied from the inverter input to the gates of the corresponding transistors T1 and T3, and the voltage of output logical signal UOUT is transmitted from the drain of the p-channel transistor T1 and source of the n-channel transistor T2 to the inverter output. As the n-channel transistors are more critical to the impact of the hot carrier’s effect than the p-channel ones, the additional protection transistor T12, according to the proposed technological solution, should ensure the conditions under which the potential of the drain of n-channel transistor T3 is limited, so that it does not exceed the given protection potential value Up, even in case of short-term unauthorized excess of the acceptable level of the positive voltage of the external power source +Ucc. It should be noted that in this case the absolute value of the output voltage UOUT, as in the case with the known standard CMOS inverters, also reaches the supply voltage value UCC. Consequently, when logical one input voltage is applied to the inverter input, a p-channel transistor T1 switches to the nonconductive state, and n-channel transistor T3 opens and ensures the logical zero voltage in the output, the voltage on the gate of the protection transistor T2 ensures its unlocking and creation of the low-resistance current flow circuit between the output and the general bus Uss, which is the required state. Alternatively, when low-level voltage is supplied to the input (logical zero), the p-channel transistor T1 opens, the nchannel transistor T3 closes, and the voltage in the inverter output increases to the level of the potential of power voltage Ucc. Correspondingly, obtaining the full range of the voltage in the output (from 0V to 5.0V at Ucc = 5.0V and from 0V to 3.0V at Ucc = 3.0V), at the same time we reach the additional positive effect, we limit the voltage value, dropping on the cross-section of the channel body of the transistor T3 (to the value considerably lower than that of +Ucc), deteriorating the conditions for formation of parasitic effect of accumulation in gate oxide traps of the minor carriers and hot electrons

Figure 5.23  Electric diagram of the inverter with a protection transistor.

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335

and thus increasing the reliability and radiation tolerance of the integrated circuit. The offered circuit configuration approach can be easily used for building more complex integrated microcircuits. Figure 5.24 shows the examples of applying this method for the realization of CMOS integrated microcircuits, which realize logical operations of AND-NOT type [Figure 5.24(a)] and OR-NOT type [Figure 5.24(b)]. Adding the additional transistor and circuits for formation and delivery of the protection potential leads to the increase of the total number of LSIC and VLSIC elements, and correspondingly, to the increase of the chips area (depending on the LSIC complexity, the increase of size can be from 7% to 15%), but the integrated circuits, designed and manufactured based on this invention, provide higher reliability in the operation process and higher yield, as we can see from the tests, performed during mass production at OJSC Integral. Thus, the main conclusions of this chapter can be expressed in the following manner. 1. An effective calculation-experimental method of assessment and prediction of radiation tolerance is represented, based on which the calculated dose dependences of the main parameters of test n- and p-channel transistor MOS structures, as well as two specific types of CMOS IC: 1594LN1 (NOT logical elements) and 1594LA3 (2AND-NOT logical elements) at different electric modes in the dose range Dy = 105 to 107rad. The obtained dependences can be used for predicting the radiation tolerance of any CMOS ICs of logical series within any batch of one type. 2. We have analyzed in detail the bipolar and CMOS IC prediction (selection) method based on radiation tolerance using test radiation and current annealing, where the calculation dose dependences of bipolar and CMOS IC parameters is done based on the results of microcircuits tests, which have

Figure 5.24  Logical diagrams with improved reliability: (b) 2AND-NOT and (b) 2 OR-NOT.

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Peculiarities of the Technological Process of Production

3.

4.

5.

6.

7. 8.

9.

10.

shown increased radiation tolerance, using regression analysis. The tests of logical CMOS ICs of 564 and 1554 series have shown that the sampling method error (prediction) of CMOS ICs on the radiation tolerance with the help of test electronic or gamma-radiation does not exceed 5% to 10%. The dependences of the amplification factor change for the n-p-n- and pn-p-transistors on the radiation dose, obtained with the use of calculationexperimental method, are described by a second-order polynomial. The relevant regression model of the change in the value of consumption current of BiCMOS LSIC depending on the stationary radiation dose is described, it is represented by a second-order polynomial, which reflects the dependence ICC(D) at doses up to 2.4 ⋅ 105 rad. A new calculation-experimental prediction method of the operation of EEPROM MOS memory elements in the ionizing radiation fields, based on the results of reliability tests (under the impact of data re-recording cycles), The results of the tests, performed at the mass production of OJSC Integral (Minsk), have shown that new methods of construction-technological implementation of logical CMOS IC and BiCMOS LSIC, aimed and ensuring their resistance to the impact of impulse and stationary radiation (optimization and implementation of basic elements of new semiconductor layers and areas into constructions), described in this chapter, allowed ensuring the operation capability of all basic IC components under the radiation impact, and also materially increasing (by 1 to 2 orders of magnitude) the overall level of radiation tolerance of microcircuits. A new circuit-configuration method was developed to prevent latch-up effect in bipolar microcircuits under the impact of impulse ionizing radiation. A new construction and circuit configuration solution of the basic micropower BiCMOS element is described in detail, which allows ensuring the resistance to the latch-up effect without increasing the chip area, but due to the original construction-technological developments. The study of the experimental samples of test BiCMOS microcircuit, designed on the basis of construction-technological solution, has proved the absence of the parasitic thyristor structure in the whole range of input and power voltages. We also described the new rules of the circuit organization of library elements while designing fast-responding CMOS of logical IC, resistant to destabilizing factors. Examples of electric diagrams of internal elements of the series of fast-responding logical CMOS ICs are presented and described. Protection circuits from the electric static charges impact were offered, as well as circuit for noise suppression in the IC outputs. A number of new construction and circuit configuration methods of increasing the CMOS LSIC radiation tolerance were analyzed. We have shown that the implementation of protection MOS transistors allows increasing the overall ionizing radiation dose, at which the inverter preserves its functional capability, by 3 to 5 times, in comparison with classic CMOS inverter. Additional protection MOS transistors and special internal protection potential output are implemented into the basic CMOS inverter, which compensate the unfavorable changes in the electrical properties of

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the main (working) transistors, stipulated by the activity of hot carriers in submicron CMOS LSIC. The use of these methods and technical solutions will allow the developers of modern microcircuits for space applications considerably increase their reliability at the stage of designing until the production stage.

References [1]

[2]

[3]

[4]

[5]

[6] [7]

[8]

[9]

[10] [11]

Korshunov, F. P., et al., “Ensuring Performance Capability of Various Perspective Semiconductor Devices Under Radiation Impact,” Microwave Technology and Telecommunication Technologies: Materials of the 17th Intl. Crimean Conference (KryMiKo’2007), Sevastopol, September 10–14, 2007, pp. 651–654. Korshunov, F. P., et al., “Method of Predicting Radiation Tolerance of Integrated Circuits CMOS,” Radiation Tolerance of Electronic Circuits Stoikost 2008: Materials of All-Russian SC Conf., Lytkarino, Russia, June 3–4, 2008, pp. 103–104. Korshunov, F. P., et al., “Method of Predicting the Radiation Tolerance of Integrated Circuits CMOS,” Problems of Nuclear Science and Technology Series: Physics of Radiation Impact of Radioelectronic Equipment, No. 1, 2009, pp. 45–49. Bogatyrev, Y. V., and F. P. Korshunov, “Current Annealing of Irradiated CMOS Integrated Circuits,” Proc. of the 7th European Conf. on Radiation and Its Effects on Components and Systems (RADECS 2003), 2003, pp. 163–174. Korshunov, F. P., et al., “Impact of Gamma-Radiation on Bipolar Transistor Structures,” Solid State Radiation Physics: Works of XIV Intl. Meeting, Sevastopol, July 5–10, 2004, pp. 30–33. Belous, A. I., et al., “Radiation Effects in BiCMOS LSIC Interface Receiver-Transmitter,” Microelectronics, Vol. 37, No. 2, 2008, pp. 139–149. Korshunov, F. P., et al., “Impact of Gamma-Radiation on the Parameters of Various Transistor-Based MOS-Structures: Elements of Integrated Microcircuits,” Report BGUIR, Vol. 1, No. 17, 2007, pp. 67–72. Belous, A. I., V. I. Ovchinnicov, and A. S. Turtsevich, “Features of Microwave Devices Design for Spacecrafts,” Ministry of Education of the Republic of Belarus, Gomel University of Francysk Skoryna, Gomel, 2015. Belous, A. I., et al., “Micropower BiCMOS Element with Increased Resistance to the LatchUp Effect,” St. Petersburg Electronics Journal, Vol. 3, No. 60 to Vol. 4, No. 61, 2009, pp. 93–100. Shvedov, S. V., “Circuit Configuration Methods to Increase the Radiation Tolerance of CMOS LSIC,” Report BGUIR, Vol. 7, No. 45, 2009, pp. 26–32. Chumakov, A. I., “Impact of Space Radiation on Integrated Circuits,” M. Radio and Svyaz, 2004.

CHAPTER 6

Analysis of Problems of Designing VeryHigh-Speed Microelectronic Devices and Systems Based on Them

6.1  Problems of Scaling Submicron Microcircuits Enhancing design complexity of integrated microcircuits (IC), chip-based systems and systems in package is associated with the evolution of applying complementary metal-oxide semiconductor (CMOS) technologies within the ultradeep submicron [1] at the consumer market of telecommunications, navigation, and multimedia in the first place. Such integrated systems imply availability of embedded highperformance digital and analog units or digital-analog processing units as well as digital circuit high-frequency devices (complex processors, various logic units and large memory units) on one chip. Improving the service of a wireless connection and other means of telecommunication causes a need for cheap, highly integrated solutions with enhanced requirements to the characteristics of the designed systems. The application of a submicron CMOS technology (with design rules of less than 65 nm) poses new important problems of circuit design (analog as well as digital). Some of these problems have never been faced before, while others existed earlier, but today, in the era of a deep submicron, they take more significance. Technology scaling is based on certain principles. In particular, when designing digital circuits, size reduction of the elements in the front-end technology (i.e., before a device) and back-end technology (including interconnections) due to adding more levels of interconnections leads to extreme increase of density of digital integrated circuits with the simultaneous reduction of switch time delay. The principal disadvantage of this tendency lies in the fact that supply voltage must be decreasing and it may potentially lead to increasing the switch time delay, and for certain applications, it is unacceptable at all. Scenario of switching to the deep submicron technology implies scaling parameter S to be the same for all geometrical parameters and for all parameters of the MOS transistor voltages. Such an ideal case for the standard CMOS gates leads to increasing density of the package proportionally to S2, decreasing the internal delay proportionally to 1/S, and reducing the consumed power proportionally to 1/S2 at

339

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the constant density of the released power. Noise characteristics of the logical gates also decrease but still remain at the acceptable level. Unfortunately, in practice, such a perfect scenario is not implemented; however, it is possible and proves that scaling was and still remains challenging for digital circuits: circuit speed increases, logic density grows, consumed power reduces, and noise effects also remain at an acceptable level [2]. For analog circuits, scaling is not useful with regard to area, but it gives advantages in terms of speed allowing designing ultrahigh-speed circuits and high-speed analog units, similar to data converters. However, there is another aspect of the problem. As it is shown [2–4], geometrical dimensions and all voltage values in the MOS-transistor decrease by 1/S times at each S scale factor, and substrate impurity concentration increases by S times. As a result, the density of the device increases by S2 times, dissipated power remains constant and the signal delay at the gate decreases by 1/S times. To improve speed, designers increase the IC density. At that, dissipated power remains at the same level. This was a golden rule that ensured development of the modern IC industry. In reality, there are serious problems associated with implementation of the expected theory. At that, increasing dissipated power is the most serious problem. One of the reasons why it is difficult to obtain at least constancy of the dissipated power is impossibility of decreasing the corresponding supply voltage. If supply voltage remains constant, dissipated power increases by S3 times. Another reason of increase in dissipated power real is the obvious sophistication of modern ICs and operating frequency increase. As geometrical dimensions of the IC elements are reduced, designers can place even more transistors on one silicon chip. However, lowering design rules leads to increasing complexity of a chip and causes even more problems associated with the design result quality control. When reaching 90 nm to 65 nm or even 45 nm, designers face problems caused by the increasing electrical and physical effects associated with high density of interconnections and transistors. Even today, the 90-nm and lower technology shows such effects of nondigital behavior of these systems as dynamic voltage loss at resistance, leakage currents, electric migration, vertical component effects, and effects of cross-coupling that may significantly change characteristics of the circuit functioning, bring up problems of reliability and lead to the circuit shutdown. These problems become more significant and even dominant, when performance of a project is improved. The main problems of IC highefficiency physical designing with design rules of a deep submicron are the density of currents and distribution of power, synchronization, and technology parameter fluctuation and noise effects. As shown in [1–5], methods of dynamic analysis are the best approach for solving the specified problems of a deep submicron. When scaling the technology to 90 nm and lower (65, 45, 32 nm), physical and quantum-mechanical effects that are not of high significance in case of a standard technology become more important and, in some cases, even dominant. The example of such effects are leakage currents that earlier were not taken into account in case of a standard technology. Furthermore, when decreasing geometrical dimensions, the process parameter dispersion gains even more importance. It is obvious that dispersion of such output parameters as the response to the fluctuation

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of process parameters becomes more significant, when the absolute values of the specified input parameters decrease. It is true for threshold voltage as well as for the level of doping and geometrical dimensions. For example, deviation of the threshold voltage VTH by 50 mV is more important for a circuit when VTH = 200 mV in comparison to the deviation of the threshold voltage VTH by the same value at VTH = 700 mV. Thus, today the main problem of designing systems with design rules of 90 nm and lower lies in answering the question of whether the specified scaling advantages are being implemented taking into account new physical effects, typical for the deep submicron technology. Is it possible in the modern nanoworld to solve tasks such as reaching IC limit characteristics, consumed power minimization, reliability optimization, manufacturability, and price? What tasks are being solved today and what solutions are proposed in the sphere of physical design of IC manufactured according to the deep submicron technology? Is it possible to preserve high operating characteristics of a modern IC under new constraints? In other words, will the designing circuits for 90-nm technology and lower still bring benefits that were forecasted earlier, or will the design constraints be so strict that developing of this important area of human activity will stop at the 90-nm or 65-nm mark? This chapter is dedicated to the problems that frequently emerge when designing analog and digital circuits made according to the nanodimensional technology (of deep submicron) with the design rules of less than 90 nm. The main problems influencing the results of designing IC with such design rules including increased leakage currents, temperature effects, and technology parameters fluctuation during scaling are considered in this chapter. Moreover, the impact of the indicated factors on the results of designing digital circuits as well as embedded memory circuits, analog circuits including methods of reducing supply voltage are analyzed.

6.2  Tendencies and Problems of Designing Silicon Integrated Microcircuits with the Deep Submicron Design Rules Successful high-efficiency design of microprocessors and other devices of microelectronics with the design rules of less than 90 nm is associated with solving two main problems: ••

Energy dissipation and, as a result, increase of consumed power of specific gates and circuit itself;

••

Change (fluctuation, technological dispersion) of submicron technology parameters.

In this regard, the approach to designing such ICs shall be changed from the deterministic to probabilistic and statistical one. Fundamental work [5], the materials of which are used in this chapter, has described the circuit solutions and possibilities of corresponding upgrading of computer-aided-design systems for solving these problems and showed a certain discrepancy between preserving the historical level of increase (at least up to threshold value of the 0.18 µm design rule) of functionality and decrease of power consumption when entering the generation of

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CMOS technology with the standards of less than 90 nm. The most serious problem is also subthreshold currents that are too big and leakage currents through the gate dielectric. 6.2.1  Tendencies of Scaling and Problems of Designing Silicon Submicron ICs

When scaling the technology of less than 90 nm, increasing density of transistors is subject to Moore’s law as usual, ensuring an even higher level of integration. At that, delay time on a transistor keeps decreasing by up to 30% per each generation of design rules. However, power dissipation and high level of the relative value of process parameters dispersion do not allow using benefits of reaching a high level of integration to the full extent at the decreasing design rule. In the course of technology scaling, the supply voltage VDD slowly decreases by 15% with each new generation due to the difficulties associated with the VTH threshold voltage scaling in the first place, and in the second place due to achievement of goals of designing transistors with enhanced characteristics [5]. Figure 6.1 shows the growth of the microprocessor active power taking into account the historical double growth of the number of transistors and the hypothetical 1.5-fold growth. It is obvious that following the historical tendency, active power changing will hit a dead end at reaching the limit of transistor dimensions, increasing the integration level and chip dimensions with each new generation of the technology. When decreasing a design rule, VTH threshold voltage will continue to decrease moderately until its value reaches the limiting range of transistor characteristics with the simultaneous increase of source-drain (SD) leakage subthreshold currents. Figure 6.2 shows the dependence of the SD leakage current on the design rule for double and 1.5-fold increases of the density of transistors. It should be noted that even at decreasing VTH, SD leakage current power will increase significantly, bringing into question prospects of even 1.5-fold increase of transistor density in each subsequent technology generation and at the decrease of chip dimensions. As will be shown in more detail below, the dispersion of parameters is of high importance when designing chips with design rules of less than 90 nm. Figure 6.3

Figure 6.1  Tendency of changing active power with decreasing design rules.

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Figure 6.2  Dependence of the leakage current power in the source-drain region on design rules [5].

Figure 6.3  Dependence of the microprocessor normalized operating frequency on the normalized subthreshold leakage current.

shows a frequency dependence of a microprocessor on the subthreshold leakage current Isb. The dispersion of the subthreshold current Isb is caused by the channel length variation that is caused by threshold voltage changes. It should be noted that a wide dispersion of leakage current corresponds to the highest frequency, and for this leakage current it corresponds to a large frequency dispersion. Chips of the highest frequency and Isb value as well as low-frequency chips with Isb high enough should be discarded, thus influencing the yield. Differences in the switching activity of various basic elements across the chip and variety of the applied types of logic lead to nonuniform power dissipation even within one chip (Figure 6.4) [6]. These variations may cause nonuniform supply voltage dispersion, appearance of hot temperature spots on the chip and as a result nonuniform dispersion of subthreshold leakage currents across the chip. Therefore, it is important to design microcircuits taking into account deviation of the parameters, substituting deterministic designing style with probabilistic and statistical one. As mentioned above, the onrush of the modern microelectronics especially at switching to submicron technologies, apart from obvious benefits, poses new

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Figure 6.4  Dispersion of the dissipated power density and temperature across the chip [5].

problems that require immediate solutions. One of these problems is the significant growth of power consumption in a static mode at increasing IC operation frequencies (Figure 6.5). The tendency given in Figure 6.5 [6] seems paradoxical as the main advantage of the process traditionally used for manufacturing digital CMOS IC is low consumption in a static mode. The main reason of the specified problem consists in appearance of the leakage currents in the submicron CMOS IC. The main advantage of CMOS gates, negligibly small static power consumption, is now being lost while using these production technologies. Figure 6.6 shows a bar chart of percent ratio of the power consumption associated with leakage currents to the apparent dissipated power for various submicron CMOS IC technologies.

Figure 6.5  Time evolution of the IC consumed power as a function of operating frequency and design rules [6].

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Figure 6.6  Relationship of power consumption ratio caused by leakage currents to the apparent dissipated power for various submicron CMOS technologies.

As illustrated in Figure 6.7 [3], a modern microprocessor manufactured with the deep submicron design rules in the context of heat release, figuratively speaking, is a small nuclear reactor. This heat should be transferred from a semiconductor IC chip. Thus, apart from significant expenses for the IC design itself, it is necessary to invest additional and significant financial means into development of the corresponding cooling systems (Figure 6.8). In the context of the indicated problems, it is necessary to solve one more important task: designing effective power sources for such ICs. If the capacity of modern accumulator batteries increased by 3 to 4 times for the past 10 years, power consumed by devices increased by an order of magnitude by 50 to 70 times (Figure 6.9). There is a tendency according to which consumed power increases by 35% to 40% at the annual growth of the power elements capacity by 10% to 15%. Let us briefly consider the reasons and physical mechanisms of power generation in IC to understand the ways of reduction.

Figure 6.7  Density of power consumed by a modern IC [3].

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Figure 6.8  IC cooling systems cost growth.

Figure 6.9  Development of modern power sources taking into account the relation to the power consumed by devices.

6.2.2  Problem of Power Consumption in Submicron IC

The work [7] illustrated a brief review of the problems associated with leakage currents when designing systems manufactured according to the 90-nm technology and lower, and the main issues concerning power control mechanisms including technologies, methods, and instruments ensuring reduction of the level of leakage currents and the cause of power consumption in modern design approaches are considered. Figure 6.10 illustrates the simplest structure of a MOS transistor. As the thickness (tox) of a gate dielectric shrinks (up to 12Å in the 90-nm technology), volt-

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Figure 6.10  Elementary structure of the MOSFET.

ages in the gate cross-section shall reduce to the level, at which there will be no breakdowns in insulating materials. For designers who mainly developed circuits according to the CMOS technology, the concept of heavy currents in a sleep mode may seem unusual for implementation, especially if chips are supplied by the factories, where circuits with a higher level of energy dissipation are being manufactured. It follows therefore that to eliminate such controversies a certain control system of energy dissipation caused by leakage currents is required. Let us consider this problem in further detail. With regard to energy consumption growth caused by leakage currents, modern processes make designers search for new design methods to reduce dissipation of energy caused by leakage currents. As it follows from Figure 6.11, speed control is one of the most effective ways to reach this goal. To implement this concept, it is necessary to create a corresponding library, with the help of which it would be possible to have a wide selection of cells based on knowledge of the corresponding characteristics of speed and leakage currents for each cell. Data given in Figure 6.11 show that when changing delay time at the gate from 25 to 8 ps, a turn-off current IOFF of a MOS transistor increases in

Figure 6.11  Dependence of MOS transistor turn-off current on delay time value.

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almost four orders of magnitude (i.e., there is exponential dependence at reduction of threshold voltage per each 65 mV). This pattern is typical of both n-MOS and p-MOS transistors. Recently, supply voltage reduced from 5V to 1V and even more for circuits starting from 0.5-µm technology. To reach transistor characteristics that correspond to the new technology generations, threshold voltage should also be reduced. Designed transistors should function with a threshold voltage value that equals 1.25V just as at the 5-V technology, which is impossible at the 1-V technology. Reduction of threshold voltage is of high importance for the solution of the problem of increasing leakage currents in CMOS technologies of the new generation. Typically, subthreshold leakage currents increase exponentially with each 65-mV increase of threshold voltage. Technologies with heavy currents in the sleep mode are not related to any new concept. Designers who previously used the design technologies of bipolar junction circuits made according to ECL or FET technologies are quite aware of currents in n-MOS devices as well as the ways of their reduction. Large modern factories have processes with the help of which n-MOS and p-MOS transistors with different values of threshold voltages are formed on one wafer. Such different types of transistors are used to form separate cells with the same functionality but with different characteristics of speed and leakage currents. Figure 6.12 shows dependences of power (from 1 to 10,000 mW) released by leakage currents of the library logic elements for the 90-nm technology and lower on the transistor operating frequency. Released power value is based on the average leakage current value in a transistor with the low leakage voltage value. Cells with the increased leakage current value (curve 1) contain transistors with the decreased threshold voltage value. The oscillograph chart (curve 2) illustrates the leakage current characteristics for corresponding cells with transistors having

Figure 6.12  Difference between the speed and basic element currents may be used for projects optimized by the frequency characteristics and consumed power.

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increased threshold voltage values. These dependences with the high and low leakage current values show that input values for specific cells may significantly influence a leakage current. The ratio of the transistor speed characteristics and leakage currents may be used when developing projects optimized by the signal duration and dissipated power. Cells that are not on a critical path usually do not require characteristics inherent to the cells with a high level of leakage currents, and they may use slower transistors with lower level of leakage currents. As the input characteristics of cells may significantly influence their leakage currents, modern means of optimization may not only replace cells based on the averaged values of leakage currents. Apart from limiting speed, these means should also help to set other design rule constraints (DRCs), such as maximum number of fan-outs per cell [fan-out is a number of inputs that may be connected to the cell output, before the currents required for inputs exceed the current that may be directed by an output preserving correct (established) logic levels] and transition times. Typically, the best final results are achieved when optimization of power caused by leakage currents is carried out at early design stages. When using cells with mixed (high and low) values of VTH threshold voltages is not effective enough, more complex methods for reduction of power dissipation caused by leakage currents are applied. Typically, these alternative methods require powering down sections of the design, thus virtually excluding leakage current when certain sections of the project are in a sleep mode. This method requires the addition of power-gating transistors that stop current flow to the selected sections of the designed circuit. These can be p-MOS transistors connected to VDD power supply circuits to isolate the selected section from VDD or n-MOS transistors connected to a VSS circuit. Typically, p-MOS transistors are called headers while n-MOS transistors are called footers. To obtain maximum results, headers may be used simultaneously with footers. Such transistors may be introduced to a circuit to control the whole group of cells and even the whole units of a project. Some cell architectures’ headers and footers are incorporated in each cell, creating the possibility of routing the sleep control using cell abutment. If power gating is used in a designed circuit, the designer must decide how this power-gated section is to be handled. There are three main approaches to optimization of power consumption: ••

Throw away the old state and reinitialize on power-up.

••

Scan out the state and store it in memory to be scanned back in after power-up.

••

Use special retention registers that store the state locally in low-leakage latches that can be used to restore the old state after power-up.

The third method is based on the ability to quickly save and restore the state of power-gated sections. Some low-power synthesis solutions provide support for these retention registers and will insert them into selected portions of the design if the designer so chooses. There is a design and technological problem of ensuring safe electrical isolation between power-gated sections and the rest of the designed system. Available

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outputs of these power-gated sections, if allowed to float, will cause the driving gates to drift across chip layout to some intermediate levels. This creates a lot of short circuits or crowbar currents in a gate, hence defeating the intended power savings (crowbar current, current appearing in the transient state of a CMOS system when both transistors, n-MOS as well as p-MOS, are partially enabled; or current that flows directly from VDD to the ground, GND, when switching from the enabled state to the disabled state). Consequently, it is necessary to use isolation cells that will control power-gated sections. It is important to note that the specified registers and isolation are being implemented not only with the help of synthesis and optimization tools but using tools that perform scan insertion, ATPG, and verification [Automatic Test Pattern Generation or Automatic Test Pattern Generator (ATPG) computer-aided technology used for determination of a circuit correct behavior or its behavior with errors caused by the defects in it]. The other way to reduce energy losses caused by leakage currents involves changing a potential placed on the body of MOS transistor. By changing the potential on the body, it is possible to dynamically vary the leakage current and transistor performance characteristics. This method may also be used to improve the quality of a designed circuit; transistor performance may be adjusted to the nominal values if they were changed due to fluctuation of the process parameters. Power associated with leakage currents is a constantly growing problem in the overall process of design. Unlike dynamic power that may be controlled by reducing switching activity, the problem of leakage power exacts its tall for the general problem of losing power. Leakage power is a considerable proportion of the total power of high-performance designs at 90 nm and below, and is critical when meeting requirements for sleep mode in low-power circuits. Libraries of basic cells of devices with different threshold voltages, power-gating, and variable body biases may be used as effective means for reducing leakage currents in circuits manufactured according to the 90-nm technology. Modern means ensure possibilities for using such technologies and help reducing the power of leakage currents in the deep submicron designs. It is obvious that development of a microelectronic device with the best functional characteristics and low-power consumption may be ensured using the following: ••

Reliable monitoring of the dissipated power distribution over the area of a designed chip for all required temperature range;

••

Efficient control of the released power.

6.2.3  Monitoring Dissipated Power Distribution Across the Chip Area at the Design Stage

Optimal power distribution is one of the main problems associated with the IC layout design using the deep submicron technology. The placement of the active and passive elements across the chip and packing of the chip itself in observance of special rules and methods allow in a certain way distributing the VDD/GND values and signals across the chip as well as over its peripherals. However, modern forecasts

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concerning quantitative ratio of specific power to density (integration degree) of devices in the nanometric designs do not always take into account such an approach to placement of devices on a chip. When solving this task, an important aspect is the method of determination and accounting hot spots, clusters of the most actively switching transistors located unevenly across a chip, because assumption concerning even density of the dissipated power distribution is overly optimistic. Usually, when calculating, a hot spot is determined as a region where local density of the dissipated power is 4 times higher than a uniform power density approximation of the value of total density of the dissipated power of a chip in a uniform approximation specified by (Pchip/Achip). Let us consider another problem connected with increasing role of ohmic resistance of signal paths on chip. In the professional slang of LSIC design specialists, it is known as the IR scaling problem (IR is a voltage drop in chip interconnects). Figure 6.13 shows the necessary power rail width (normalized to minimum toplevel metal width) to ensure >VTH) can be written in the following way:

I SUB = μnC

 V  WN 2 Vt exp  − TH  . LN  nVt 

(6.14)

The qualitative analysis of the latter expression allows making a number of conclusions useful for practical application: ••

The subthreshold current exponentially grows at reduction of threshold voltage values of a MOS transistor.

••

The subthreshold current numeric value is increasing in direct proportion to reduction of channel lengths, at that there is an early-known short-channel effect (reduction of threshold voltage VTH) as well as the drain-induced barrier lowering effect (DIBL effect).

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Peculiarities of the Technological Process of Production ••

The subthreshold current numeric value increases at the temperature increase that should be compensated with corresponding circuit solutions to ensure the efficiency at high temperatures of IC operation.

6.3.3.2  Gate Tunnel Current IGATE

Before the nanometer era, gate currents were considered to be purely dynamic, and MOS gates were usually regarded as capacitors and they did not conduct direct currents. However, reducing gate oxide thickness to several nanometers provides the possibility of tunneling current through the gate, and due to that, the leakage current static component appears. Gate leakage current appears only when there is a difference of potentials along the gate (i.e., when the transistor is turned on). Subthreshold leakage current, on the contrary, appears only when the transistor is turned off. MOS transistor gate leakage currents eventually influence the dissipated power as well as IC functionality. In case gate current IGATE is determined for the worst case (Vgs = 1.2V and Vds = Vbs = 0V), its value can be determined in the following way:

(

)

IGATE = W ×L × AIG ×Vgs Vgs − VFB × exp ( −BIG ×Tax )

(6.15)

Here AIG and BIG are the parameters of the gate tunnel current, L is a channel length, and VFB is a voltage of flat bands. As was already noted, device scaling is influenced not only by new technologies but introduction of new materials as well. Thus, nowadays special attention is paid to high-k materials used as gate dielectrics, leading to reduction of leakage current at the gate, as thicker oxides may be used in devices, which do not result reduce the gate capacity and operate at the set values of threshold voltages. 6.3.3.3  Turn-Off Current IOFF

Taking into account the behavior of the IOFF turn-off current of a MOS transistor is very important when designing ICs for various deep submicron technologies. Thus, Figure 6.22 illustrates widely applied results of modeling volt-ampere characteristics, taking into account peculiarities of behavior of the main components of leakage current of a MOS transistor depending on the used design rules and various operation conditions of devices (supply voltage VDD). Calculations were carried out using well-known BSIM4 model with the use of BPT model (Predictive Technology Model, a modification of BSIM4, which makes allowance for deep submicron effects) [11]. Analysis of the modeling results allows making the following conclusions: For VD > VG, the depleted drain layer becomes thinner, which leads to an increased number of electrons passing through the barrier that, in turn, causes IDB and IOFF currents growth (GIDL effect; see Section 6.2). The dependence of threshold voltage on VDS becomes apparent, at that VTH decreases when VDS grows (DIBL effect; see Section 6.2).

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Figure 6.22  Results of modeling volt-ampere characteristics ISD (VGATE) of MOS transistors manufactured using the 45-nm and 130-nm technologies.

For a deep submicron technology (45 nm), the IOFF turn-off current increases by six orders (subthreshold current for VGS = 0) in comparison with the relatively submicron technology (130 nm). 6.3.4  Analysis of the Power Static Consumption Value of a MOS Transistor

Up to the present time, there have been developed a lot of various approaches to reduction of CMOS static power consumption. In this section, we will consider only two already chip tested methods, in which VTH multithreshold values are used to limit IOFF values on one semiconducting chip. The first method of reducing static dissipated power suggests using MOS transistors with various values of the threshold voltage VTH. CMOS IC designed on the basis of this method are called multithreshold (or MTCMOS), and they are characterized by the VTH high value in the sleep mode to prevent leakage current in a standby mode. Transistor in a standby mode is turned on between the ground and logical CMOS element. A sleeping transistor is put between the ground and circuit of the fast CMOS logic with a low value of VTH threshold voltage. Series connection of the transistor increases the signal transmission delay, but it may be reduced by means of enlarging corresponding area. The disadvantages of this method include impossibility of leakage elimination in the active mode and increased area of

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the IC base cell. Other varieties of this method include ways of using the VTH dual threshold voltage, domino-logic, special bias of the substrate voltage to change VTH in a standby mode, and using negative voltages of the n-MOS transistor (for a larger bias of the transistor to the cutoff region). Methods of single-threshold leakage elimination require using transistor operation in a standby mode as well as reduction of the level of leakage currents that depend only on the transistor state. All these methods imply sacrificing the area to limit the static power and in most of the cases eliminate leakage currents only in a ready mode. Basically, the scope of their application is limited by portable device ICs, such as laptop processors. Moreover, some of the proposed methods are ineffective for solving scaling problems, for example, using domino-logic and a substrate bias at VTH control. Today, dual VTH is one of the most effective methods in high-end microprocessors as described below. Let us look more closely at the method called dual threshold voltage method VTH (dual-VTH method) [12]. Today circuit designers together with production engineers have an opportunity to control threshold voltage of MOS transistors on one integrated circuit so as to manufacture a device with either a high or low threshold voltage. The influence of VTH threshold voltage on the delay and energy consumption of the elements, such as inverters and NAND gates, is significant enough. Reducing VTH (at the constant VDD) exponentially increases the turn-off current value and at the same time linearly reduces the signal distribution delay. An additional stage of voltage adjustment using subdoping through ion implantation allows designers to choose the best variant for power saving. Thus, elements located on critical paths can have VTH low values, and noncritical elements in terms of signal distribution time may have VTH high values and long delays when switching. Results of research of such technical solutions show a 40% to 80% reduction of the power consumption caused by leakage currents with a minimal increase of the delay time in comparison with circuits, which use elements with low threshold voltages only [13]. Figure 6.23 shows the turn-on current increase for the elements with low VTH value. Turn-on current ION increases faster at the VTH threshold voltage reduction by 100 mV during technology scaling. The price of the IOFF turn-off current for 20% increase of the turn-on current reduces when technology is scaled. Figure 6.24 illustrates the tendency of the turn-off current reduction when decreasing design rules and VDD values for n-channel and p-channel MOS transistors. The relative difference in the turn-off current value between two identical MOS transistors with different VTH values will remain constant across the whole circuit area (when increasing the turn-off current by 15 times and reducing VTH by 100 mV). Suppose that the turn-off current changes by a constant value, even an improvement of the turn-on current at dimension scaling, shows that the approach to leakage elimination using devices with dual VTH (multi-VTH as an option) can be scaled. It is important to note that the experimentally obtained resulting current increase is 20% higher in comparison with the same parameters when using MOS devices with the high threshold voltage. The 35-nm technology requires a sevenfold turn-off current increase to obtain just a 20% increase of the drive current.

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Figure 6.23  Character of ION turn-on current changing for elements with low VTH value when design rules are scaled.

Figure 6.24  Dependence of the turn-off current specific value reduction on the design rule and supply voltage.

6.3.5  Peculiarities of Designing Submicron Analog ICs Taking into Account Static Power Consumption

Due to the knowledge-intensive nature of analog designing, today most of the analog projects are still a result of the manual work of designers of analog hardware who use SPICE-like programs and interactive media for modeling layout as subsidiary objects. This lengthens the designing of analog systems and predisposes it to failures. That is why, despite the fact that analog circuits usually occupy only a small part of circuits and systems-on-chip and deal with mixed signals, their development

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is usually very field-specific regarding mixed signal systems (analog-digital). Despite the time spent on design and efforts aimed at reducing the cost of tests, analog circuits are often the main causes of failures of the whole digital-analog circuit and require carrying out analysis and expensive additional tests. Such manual work takes a lot of time before the project enters the consumer market. This explains the growing need for CAD tools for designing analog systems with enhanced output capacity, allowing designers to develop an analog system quickly and correctly at the first try and even reduce the time for designing, due to automatic solution of certain tasks (or the whole process) of circuit design. Since the basic level of abstraction of analog devices is the transistor layer, an important problem is development of a commercial CAD tool that ensures design of an analog circuit at the cell level and layout synthesis. For the past 10 years, a significant progress has been noted in this field, and in recent years there have been a number of effective commercial offers in the market [14]. Most of the basic methods within the field of IC design as well as in the field of layout synthesis are based on high-performance computing optimization tools. These means help to develop circuits in shorter time in comparison with manual design. As an example, Figure 6.25 shows the interface for designing a particle detection system using the AMGIE/LAYLA analog synthesis tool [15]. 6.3.6  Peculiarities of Designing Submicron Analog-Digital ICs Taking into Account Static Power Consumption

Signal integrity analysis is a difficult problem when designing mixed-signal semiconductor devices, where precision analog and radio frequency circuits are integrated on one chip of a large digital circuit. The main point of the analysis lies in verification of all unwanted signal interactions through crosstalk or couplings at the system level that may lead to failures in the circuit operation. Parasitic signals (for example, digital switching noise) that mix with a valid signal degrading or even destroying functional characteristics of analog radio frequency circuitry, are

Figure 6.25  Layout of a particle detection circuit obtained using the AMGIE/LAYLA analog synthesis tool.

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generated in analog-digital ICs. These interaction scan come from capacitive or (at higher frequencies) inductive crosstalk, from supply line or substrate couplings, from thermal interactions, from coupling through the package, and from electromagnetic interference. In recent years, special attention has been paid to the analysis of digital switching noise that propagates through the substrate shared by the analog and digital circuits. At the moment of switching a digital circuitry can inject generate spiky signals into the substrate, which then will be propagate to and be picked up by the sensitive analog/radio frequency elements of this circuit. As an example, let us consider a VCO at 2.3 GHz and a digital circuit block (250k gates) running at 13 MHz. Figure 6.26 shows digital clock as FM modulation around the VCO frequency that may cause conflicts with out-of-band emission requirements. Nowadays, active research is carried out to find effective techniques for elimination of such problems. For the noise propagation through the substrate, as a rule, a classic difference method is used (or boundary element method) to solve for the substrate potential distribution due to injected noise sources, allowing one to perform modeling. This propagation analysis should be combined with analysis of the signal-dependent digital switching activity to know the actual time-varying injected signals and analysis of the impact of the local substrate voltage variations on the analog circuit performance. In a number of cases, a designer has to apply such solutions as the reduction of effective number of bits in ADC to solve all the problems at once. As an example, the SWAN methodology determines the switching noise that is generated by the digital circuits in a system, by a priori characterizing every cell in a digital standard cell library with a macromodel that includes the current injected

Figure 6.26  Oscillograph chart of measurements of the FM modulation of a digital-analog IC caused by substrate switching noise coupling [16].

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in the substrate due to an input transition. Then calculation of the total injection of a complex system is performed by combining the contributions of all switching cells over time depending on the event information obtained from a VHDL simulation of the system. Figure 6.27 for example shows the comparison between time-domain SWAN simulations and measurements on a large experimental WLAN system on chip with 220k gates. This system on chip contains an OFDM WLAN modem and low-frequency IF digital (de)modulator manufactured in a 3.3-V, 0.35-µm CMOS 2P2M technology on an EPI-type substrate. Compared to the measurements, the simulated substrate-noise voltage from 0 to 100 ns is within an error of 20% in its RMS value and within an error of 4% in its peak-to-peak value, which is a very good result for a difficult crosstalk effect like substrate noise couplings. Techniques to analyze the impact of this on the performance of the embedded analog blocks are also being developed [17]. In future nanometer technologies, however, other signal integrity problems will show up that need to be analyzed and modeled. These include electromagnetic interactions.

6.4  Dynamic Power Consumption in a Typical Structure of a Submicron MOS Transistor Influence of the threshold voltage VTH on the delay time of logical gates is growing with reduction of design rules [5], as shown in Figure 6.28. It is explained by the fact that accelerating voltage (difference between the supply voltage value and switching threshold voltage value) (VDD – VTH) becomes lower, leading to VTH contribution increase to the accelerating voltage value (VDD – VTH). Technological spread of VTH value can be reduced at the circuit design stage in such a way so that requirements for the signal delay value are calculated by the worst-case scenario (i.e., at the highest VTH value). As an example of how various

Figure 6.27  Comparison of measured and SWAN-simulated noise in the experimental WLAN system on chip.

6.4  Dynamic Power Consumption in a Typical Structure of a Submicron MOS Transistor

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Figure 6.28  Influence of the dispersion of threshold voltage (VTH) on the gate delay.

factors affect signal delay time, Figure 6.28 shows the dependence of the delay numeric value on the threshold voltage of a MOS transistor at various supply voltages VDD approximately from 1.0V to 3.0V. However, such a worst-case approximation affects the results of dissipated power calculations. Reference geometric dimensions of circuit elements and consequently their parasitic capacitances will be larger than necessary when the actual VTH value is not that high. However, the dynamic component of the released power is determined by value CVDD2, which does not depend on VTH. Geometrical dimensions of IC elements influence the dissipated power in a circuit rather than signal distribution delay value. A growing importance has an impact of the worst-case size designing on the level of power in the circuit, which should be properly estimated, and hence IC developers should be trained on this stage of design. We have considered some important peculiarities of the main scaling characteristics for submicron MOS transistors, the physics of which should be understood and taken into account during calculations. 6.4.1  Submicron Digital ICs with Reference Delay Value

As shown above, scaling dimensions into submicron technology leads to increasing the leakage current of MOS transistors up to the level when they cannot be neglected anymore. To reduce this effect, a lot of process and circuit methods were developed, and research in this field is still going on. The first group of such methods, the MTCMOS (multithreshold CMOS circuits), uses the increase of the threshold voltage of those circuit transistors that do not determine a critical time delay characteristic. This method leads to the reduction of subthreshold leakage currents without significant negative influence on the speed of the system. To implement this method, various process methods of increasing VTH are applied. The MTC-

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MOS method includes a solution according to which some circuits with potential leakages are turned off if they are in the inactive, turned-off state. The second group of methods of controlling leakage currents is called VTCMOS (variable threshold CMOS). In this technology, the VTH value of threshold voltage is regulated by changing the level of voltage applied to the substrate. There are a number of design-technical and circuit solutions allowing adapting voltage applied to the transistor substrate [3]. However, all these solutions have the same problem: when scaling the technology down, the body effect reduces. This means that influence of voltage applied to the substrate, depending on a specific VTH value reduces, thus limiting efficiency of the VTCMOS method. These examples show that there is a critical point when further scaling a MOS transistor does not make sense. A delay value in this scaling process can still be reduced a lot, although the increased dissipated power caused by leakage currents and application of a design method by the worst case are not acceptable anymore. Moreover, the problems associated with dispersion of parameters across the wafer come to the forefront. 6.4.2  Signal Distribution Delay at Interconnections

As the signal distribution delay value at interconnections tends to grow with reduction of the design rules, it is more difficult to preserve synchrony between various parts of a digital circuit within one chip (Figure 6.29). In a standard submicron 90-nm technology, the maximum length of an interconnection is approximately 2 mm with the asymmetry ratio less than 20% at 1-GHz frequency. By reducing the interconnection pitch and line width, this distance reduces even more. Such a tendency requires the application of proper architecture solutions: locating information storage and processing units closely on a chip and adding specific coupling networks that are locally synchronized but on the whole are asynchronous with

Figure 6.29  Maximum length of interconnections for the 20% signal phase bias depending on clock frequency for standard (metal 1 and metal 2) interconnections with the design rules of 90 nm.

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chip area. Obviously, it also leads to additional power consumption (and adding silicon regions) together with increasing complexity of the design process itself. 6.4.3  Methods of Reducing Switching Power Consumption

It is important to note that density of dissipated power of storage devices integrated on a chip, such as an on-chip SRAM cache, is usually one order less than that of digital logic devices (Figure 6.30). In this respect, all characteristics of a modern complex processor may be improved in terms of power consumption reduction by means of using more embedded memory elements than circuit logic elements in its architecture [3, 6]. It is obvious that in the future microarchitectures will have more on-chip cache to achieve a higher performance at comparatively small increase of their total power consumption [3, 5]. As it happens, the improvement of general-purpose single-threaded (not pipeline) processor characteristics has traditionally required a bigger number of logic transistors for the simultaneous execution of many parallel actions (operations). For example, the number of transistors was doubled so as to simply increase performance by 40% (Figure 6.31). Obviously, when design rules transition to the deep submicron technology, such a traditional solution to enhancing digital circuit functionality is ineffective from the point of view of using chip transistor resources. This approach is considered to be satisfactory for the existing design level. However, if dissipated power constraints are taken as a basis, modern macroarchitecture should include special hardware and software to improve speed and reduce power consumption and area (Table 6.1) [18]. As the table shows, the study of embedded special functional units in comparison with general-purpose circuits allows reducing power consumption by at least 10% and provides a fourfold increase of performance.

Figure 6.30  Comparative dependence of dissipated power density on the design rules for embedded memory circuits and digital logic circuits.

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Peculiarities of the Technological Process of Production

Figure 6.31  Microarchitecture efficiency.

Table 6.1  Efficiency of Special Purpose Hardware Devices Types of Devices Chip Area Power Performance General purpose 2X 2X ~1.4X Special purpose