Solution Manual For The AVR Microcontroller And Embedded Systems Using Assembly And C [1 ed.] 9780138003319, 1138003319

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Contents CHAPTER 0: INTRODUCTION TO COMPUTING..................................................................... 5 SECTION 0.1: NUMBERING AND CODING SYSTEMS................................................... 5 SECTION 0.2: DIGITAL PRIMER ........................................................................................ 6 SECTION 0.3: SEMICONDUCTOR MEMORY .................................................................. 8 SECTION 0.4: CPU AND HARVARD ARCHITECTURE ................................................ 10 CHAPTER 1: THE AVR MICROCONTROLLERS: HISTORY AND FEATURES.................. 11 SECTION 1.1: MICROCONTROLLERS AND EMBEDDED PROCESSORS............... 11 SECTION 1.2: OVERVIEW OF THE AVR FAMILY ....................................................... 11 CHAPTER 2: AVR ARCHITECTURE & ASSEMBLY LANGUAGE PROGRAMMING ....... 13 SECTION 2.1: THE GENERAL PURPOSE REGISTERS IN THE AVR........................ 13 SECTION 2.2: THE AVR DATA MEMORY ...................................................................... 13 SECTION 2.3: USING INSTRUCTIONS WITH THE DATA MEMORY....................... 14 SECTION 2.4: AVR STATUS REGISTER .......................................................................... 15 SECTION 2.5: AVR DATA FORMAT AND DIRECTIVES.............................................. 16 SECTION 2.6: INSTRUCTION TO AVR ASSEMBLY PROGRAMMING AND .......... 17 SECTION 2.7: ASSEMBLING AN AVR PROGRAM........................................................ 17 SECTION 2.8: THE PROGRAM AND PROGRAM ROM SPACE IN THE AVR ......... 18 SECTION 2.9: RISC ARCHITECTURE IN THE AVR ..................................................... 20 CHAPTER 3: BRANCH, CALL AND TIME DELAY LOOP .................................................... 21 SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING........................................... 21 SECTION 3.2: CALL INSTRUCTIONS AND STACK ...................................................... 21 SECTION 3.3: AVR TIME DELAY AND INSTRUCTION PIPELINE ........................... 22 CHAPTER 4: AVR I/O PORT PROGRAMMING ...................................................................... 24 SECTION 4.1: I/O PORT PROGRAMMING IN AVR ...................................................... 24 SECTION 4.2: I/O BIT MANIPULATION PROGRAMMING......................................... 25 CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS.......................... 29 SECTION 5.1: ARITHMETIC INSTRUCTIONS............................................................... 29 SECTION 5.2: SIGNED NUMBER CONCEPTS AND ARITHMETIC OPERATIONS 31 SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS............................................. 31 SECTION 5.4: ROTATE AND SHIFT INSTRUCTIONS AND DATA SERIALIZATION ................................................................................................................................................... 32 SECTION 5.5: BCD AND ASCII CONVERSION............................................................... 33 CHAPTER 6: AVR ADVANCED ASSEMBLY LANGUAGE PROGRAMMING ................... 35 SECTION 6.1: INTRODUCING SOME MORE ASSEMBLER DIRECTIVES .............. 35 SECTION 6.2: REGISTER AND DIRECT ADDRESSING MODES ............................... 35 SECTION 6.3: REGISTER INDIRECT ADDRESSING MODE....................................... 36 SECTION 6.4: LOOK-UP TABLE AND TABLE PROCESSING..................................... 37 SECTION 6.5: BIT-ADDRESSABILITY ............................................................................. 40 SECTION 6.6: ACCESSING EEPROM IN AVR................................................................ 42 SECTION 6.7: CKECKSUM AND ASCII SUBROUTINES .............................................. 45 SECTION 6.8: MACROS ....................................................................................................... 48 CHAPTER 7: AVR PROGRAMMING IN C ............................................................................... 49 SECTION 7.1: DATA TYPES AND TIME DELAYS IN C................................................ 49 SECTION 7.2: I/O PROGRAMMING IN C ........................................................................ 49 SECTION 7.3: LOGIC OPERATIONS IN C....................................................................... 51 SECTION 7.4: DATA CONVERSION PROGRAMS IN C................................................ 52 SECTION 7.6: MEMORY ALLOCATION IN C ................................................................ 53 CHAPTER 8: AVR HARDWARE CONNECTION .................................................................... 55

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SECTION 8.1: ATMEGA32 PIN CONNECTION .............................................................. 55 SECTION 8.2: AVR FUSE BITS........................................................................................... 55 SECTION 8.3: EXPLAINING THE INTEL HEX FILE FOR AVR ................................. 55 SECTION 8.4: AVR PROGRAMMIN AND TRAINER BOARD ..................................... 56 CHAPTER 9: AVR TIMER PROGRAMMING IN ASSEMBLY AND C.................................. 57 SECTION 9.1: PROGRAMMING TIMERS 0, 1, AND 2 ................................................... 57 SECTION 9.2: COUNTER PROGRAMMING ................................................................... 59 SECTION 9.3: PROGRAMMING TIMERS IN C .............................................................. 60 Chapter 10: INTERRUPT PROGRAMMING IN ASSEMBLY AND C ..................................... 65 SECTION 10.1: AVR INTERRUPTS ................................................................................... 65 SECTION 10.2: PROGRAMMING TIMER INTERRUPTS ............................................. 65 SECTION 10.3: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS ........... 68 SECTION 10.4: INTERRUPT PRIORITY IN THE AVR.................................................. 70 CHAPTER 11: AVR SERIAL PORT PROGRAMMING IN ASSEMBLY AND C ................... 71 SECTION 11.1: BASICS OF SERIAL COMMUNICATION ............................................ 71 SECTION 11.2: ATMEGA32 CONNECTION TO RS232 ................................................. 71 SECTION 11.3: AVR SERIAL PORT PROGRAMMING IN ASSEMBLY..................... 72 SECTION 11.4: AVR SERIAL PORT PROGRAMMING IN C........................................ 74 CHAPTER 12: LCD AND KEYBOARD INTERFACING ......................................................... 76 SECTION 12.1: LCD INTERFACING ................................................................................. 76 SECTION 12.2: KEYBOARD INTERFACING .................................................................. 76 CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING .................................................... 77 SECTION 13.1: ADC CHARACTERISTICS ...................................................................... 77 SECTION 13.2: ADC PROGRAMMING IN THE ATMEGA32 ....................................... 77 SECTION 13.3: SENSOR INTERFACING AND SIGNAL CONDITIONING ............... 78 SECTION 13.4: DAC INTERFACING................................................................................. 78 Chapter 14: RELAY, OPTOISOLATOR, AND STEPPER MOTOR INTERFACING WITH AVR .............................................................................................................................................. 80 SECTION 14.1: RELAYS AND OPTOISOLATORS ......................................................... 80 SECTION 14.2: STEPPER MOTOR INTERFACING ....................................................... 80 Chapter 15: INPUT CAPTURE AND WAVE GENERATION IN AVR .................................... 81 SECTION 15.1: WAVE GENERATION USING 8-BIT TIMERS..................................... 81 SECTION 15.2: WAVE GENERATION USING TIMER1 ................................................ 82 SECTION 15.3: INPUT CAPTURE PROGRAMMING..................................................... 84 SECTION 15.4: C PROGRAMMING .................................................................................. 84 Chapter 16: PWM AND DC MOTOR CONTROL ...................................................................... 87 SECTION 16.1: DC MOTOR INTERFACING AND PWM .............................................. 87 SECTION 16.2: PWM MODES IN 8-BIT TIMERS............................................................ 87 SECTION 16.3: PWM MODES IN TIMER1 ....................................................................... 89 Chapter 17: SPI PROTOCOL AND MAX7221 DESPLAY INTERFACING ............................. 92 SECTION 17.1: SPI BUS PROTOCOL ................................................................................ 92 SECTION 17.2: SPI PROGRAMMING IN AVR ................................................................ 92 SECTION 17.3: MAX7221 INTERFACING AND PROGRAMMING ............................. 92 Chapter 18: I2C PROTOCOL AND DS1307 RTC INTERFACING ........................................... 93 SECTION 18.1: I2C BUS PROTOCOL................................................................................ 93 SECTION 18.2: TWI PROGRAMMING IN AVR .............................................................. 93 SECTION 18.3: AVR TWI PROGRAMMING IN ASSEMBLY AN C............................. 93 SECTION 18.4: DS1307 RTC INTERFACING AND PROGRAMMING ........................ 95

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CHAPTER 0: INTRODUCTION TO COMPUTING SECTION 0.1: NUMBERING AND CODING SYSTEMS 1.

2.

3.

4.

5.

6.

(a) 1210 = 11002 (b) 12310 = 0111 10112 (c) 6310 = 0011 11112 (d) 12810 = 1000 00002 (e) 100010 = 0011 1110 10002 (a) 1001002 = 3610 (b) 10000012 = 6510 (c) 111012 = 2910 (d) 10102 = 1010 (e) 001000102 = 3410 (a) 1001002 = 2416 (b) 10000012 = 4116 (c) 111012 = 1D16 (d) 10102 = 0A16 (e) 001000102 = 2216 (a) 2B916 = 0010 1011 10012, 69710 (b) F4416 = 1111 0100 01002, 390810 (c) 91216 = 1001 0001 00102, 232210 (d) 2B16 = 0010 10112, 4310 (e) FFFF16 = 1111 1111 1111 11112, 6553510 (a) 1210 = 0C16 (b) 12310 = 7B16 (c) 6310 = 3F16 (d) 12810 = 8016 (e) 100010 = 3E816 (a) 1001010 Î 0011 0110 (b) 111001 Î 0000 0111 (c) 10000010 Î 0111 1110 (d) 111110001 Î 0000 1111

7. (a) 2C+3F = 6B (b) F34+5D6 = 150A (c) 20000+12FF = 212FF (d) FFFF+2222 = 12221 8. (a) 24F-129 = 12616

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9.

(b) FE9-5CC = A1D16 (c) 2FFFF-FFFFF = 3000016 (d) 9FF25-4DD99 = 5218C16 (a) Hex: 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 (b) Binary: 11 0000, 11 0001, 11 0010, 11 0011, 11 0100, 11 0101, 11 0110, 11 0111, 11 1000, 11 1001. ASCII (hex) Binary 30 011 0000 31 011 0001 32 011 0010 33 011 0011 34 011 0100 35 011 0101 36 011 0110 37 011 0111 38 011 1000 39 011 1001

0 1 2 3 4 5 6 7 8 9

10. 000000 22 55 2E 53 2E 41 2E 20 69 73 20 61 20 63 6F 75 000010 6E 74 72 79 22 0D 0A 22 69 6E 20 4E 6F 72 74 68 000020 20 41 6D 65 72 69 63 61 22 0D 0A

"U.S.A. is a cou ntry".."in North America"..

SECTION 0.2: DIGITAL PRIMER 11. A

1

B

2

3

4 6

C

12. A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

5

Y 0 1 1 1 1 1 1 1

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13. .

A

1

B

2

3

4 6

C

14. A 0 0 0 0 1 1 1 1

5

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 0 0 0 0 0 0 1

15. A

1

B

2

3

4 6

C

16. A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

5

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 1 1 0 1 0 0 1

Y 1 1 1 1 1 1 1 0

17. Instructor’s Manual for “The AVR Microcontroller and Embedded Systems”

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A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 1 0 0 0 0 0 0 0

D X 0 1

Q NC 0 1

18. LSB

19. LSB

20. CLK No Yes Yes

SECTION 0.3: SEMICONDUCTOR MEMORY 21. (a) 4 (b) 4 (c) 4 (d) 1 048 576, 220 (e) 1024K (f) 1 073 741 824, 230 (g) 1 048 576 K (h) 1024M (i) 8388608, 8192K 22. Disk storage capacity / size of a page = (2*230) / (25*80) = 1 million pages

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23. (a) 9FFFFh – 10000h = 8FFFFh = 589 824 bytes (b) 576 kbytes 24. 232 – 1 = 4 294 967 295 25. (a) FFh, 255 (b) FFFFh, 65535 (c) FFFF FFFFh, 4 294 967 295 (d) FFFF FFFF FFFF FFFFh, 18 446 744 073 709 551 615 26. (a) 216 = 64K (b) 224 = 16M (c) 232 = 4096 Mega, 4G (d) 248 = 256 Tera, 262144 Giga, 268435456 Mega 27. Data bus is bidirectional, address bus is unidirectional (exit CPU). 28. The storage of the chip is measured in Megabits while the Computer memory is measured in Megabytes. 29. True, the more address lines the more memory locations. 30. True, the memory location size is fixed. 31. True, the more data lines the more memory locations 32. True 33. access time 34. True 35. electrically erasable 36. True 37. DRAM 38. SRAM 39. DRAM and SRAM 40. (c) 41. (c) 42. (a) 32Kx8, 256K (f) 8Kx1, 8K (b) 8Kx8, 64K (g) 4Kx8, 32K (c) 4Kx8, 32K (h) 2Kx8, 16K (d) 8Kx8, 64K (i) 256Kx4, 1M (e) 4Mx1, 4M (j) 64Kx8, 512K 43. (a) 128K 14 8 (f) 256K 8 4 (b) 256K 15 8 (g) 8M 20 8 (c) 512K 16 8 (h) 16M 11 4 (d) 2M 18 8 (i) 512K 16 8 (e) 512K 16 8 44. 4000h - 7FFFh 45. A0

A11 A12 A13

1 3 1

2

2

~CS

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46. 8000h - 8FFFh, B000h - BFFFh, E000 – EFFFh 47. A0

8kx8

A12

U? A13 A14 A15 Vcc

1 2 3 6 4 5

A B C G1 G2AN G2BN

Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N

15 14 13 12 11 10 9 7

~CS

74138

Each controls 8K bytes block 48. 6000h - 7FFFh, C000h - DFFFh, E000h – FFFFh 49. A0

32kx8

A14

U? A15 A16 A17 Vcc

1 2 3 6 4 5

A B C G1 G2AN G2BN

Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N

15 14 13 12 11 10 9 7

~CS

74138

Each controls 32K bytes block 50. 4000h - 7FFFh, 8000h - BFFFh, C000h – FFFFh SECTION 0.4: CPU AND HARVARD ARCHITECTURE 51. PC ( Program Counter ) 52. ALU is responsible for all arithmetic and logic calculations in the CPU. 53. Address, control and data

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CHAPTER 1: THE AVR MICROCONTROLLERS: HISTORY AND FEATURES SECTION 1.1: MICROCONTROLLERS AND EMBEDDED PROCESSORS 1. 2. 3. 4. 5. 6. 7. 8. 9.

False. True. True. True. CPU, RAM, ROM, EEPROM, I/O, Timer, Serial COM port, ADC. RAM and ROM. Keyboard, mouse, printer. Computing power and compatibility with millions and millions of PCs. PIC 16x – Microchip Technology, 8051 - Intel, AVR – Atmel, Z8 – Zilog, 68HC11 – Freescale Semiconductor (Motorola). 10. 8051. 11. Power consumption. 12. The ROM area is where the executable code is stored. 13. Very, in case there is a shortage by one supplier. 14. Suppliers other than the manufacturer of the chip. 15. B is absolutely wrong; 16 bit software can not run on an 8 bit system due to special instructions and registers. But A can be true (in the case of software compatibility). SECTION 1.2: OVERVIEW OF THE AVR FAMILY 16. Flash memory is ideal for fast development because Flash memory can be erased in seconds compared to 20 minutes or more needed for the UV-EPROM. 17. 32 pins 18. 32 Kbytes 19. 256 bytes 20. 8 21. 4K 22. 6 23. 2K 24. ATtiny11, ATtiny12, ATting15L 25. All AVRs have Flash ROM; but a few of them, like ATtiny20, ATtiny28L, and ATtiny4 have no EEPROM 26. AT90USB1286, AT90USB1287, AT90USB162, AT90USB646, AT90USB647, AT90USB82 27. AT90CAN128, AT90CAN32, AT90CAN64 28. Program ROM Data RAM (a) ATmega32 32 Kbytes 2048 (b) ATtiny44 2 Kbytes 128

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(c) ATtiny84 8 Kbytes (d) 90CAN128 128 Kbytes

512 4K

29. Program ROM Data RAM ATmega32 32 Kbytes 2048 ATmega16 16 Kbytes 1024 30.

EEPROM 1024 512

512

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CHAPTER 2: AVR ARCHITECTURE & ASSEMBLY LANGUAGE PROGRAMMING SECTION 2.1: THE GENERAL PURPOSE REGISTERS IN THE AVR 1. 2. 3. 4. 5. 6. 7. 8.

8 8 8 0xFF $28 – in R20 (a), (c), (d), (e), (g) (c) This is an illegal instruction since the arguments of ADD should be register. If they instruction was valid 0x44 would be stored in R19 9. This is an illegal instruction since the arguments of ADD should be register. If they instruction was valid 0xFF would be stored in R21 10. True

SECTION 2.2: THE AVR DATA MEMORY 11. 12. 13. 14. 15. 16. 17.

internal SRAM True True False False data memory data memory = general purpose register + I/O registers + SRAM. All AVRs have 32 general purpose registers. AVRs with less than 32 I/O pins, which are not a member of special purpose AVR, have 64 I/O registers. The size of SRAM can be found in figures of Chapter 1. (a) 32 + 64 + 2048 = 2144 (b) 32 + 64 + 1024 = 1120 (c) 32 + 64 + 256 = 352

18. EEPROM does not lose its data when power is off, whereas SRAM does. So, the EEPROM is used for storing data that should rarely be changed and should not be lost when the power is off (e.g., options and settings); whereas the SRAM is used for storing data and parameters that are changed frequently. 19. Yes 20. No, each microcontroller should have general purpose registers and I/O registers. 21. From $60 to $FFFF 22. 65,536 bytes

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SECTION 2.3: USING INSTRUCTIONS WITH THE DATA MEMORY 23. LDI STS LDI STS

R20, $30 $105, R20 R20, $97 $106, R20

LDI STS STS STS STS STS STS STS STS STS

R20, $55 $300, R20 $301, R20 $302, R20 $303, R20 $304, R20 $305, R20 $306, R20 $307, R20 $308, R20

24.

25. LDI R16, $5F OUT PORTB, R16

26. True 27. LDI STS STS STS STS STS STS

R30, $11 $100, R30 $101, R30 $102, R30 $103, R30 $104, R30 $105, R30

LDS LDS ADD LDS ADD LDS ADD LDS ADD LDS ADD

R20, R16, R20, R16, R20, R16, R20, R16, R20, R16, R20,

LDI STS STS STS STS STS STS

R30, $11 $100, R30 $101, R30 $102, R30 $103, R30 $104, R30 $105, R30

$100 $101 R16 $102 R16 $103 R16 $104 R16 $105 R16

28.

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LDS LDS ADD LDS ADD LDS ADD LDS ADD LDS ADD

R20, R16, R20, R16, R20, R16, R20, R16, R20, R16, R20,

$100 $101 R16 $102 R16 $103 R16 $104 R16 $105 R16

STS $105, R20

29. LDI R16, $15 STS $67, R16 LDI LDS ADD ADD ADD ADD ADD

R19, R20, R19, R19, R19, R19, R19,

0 $67 R20 R20 R20 R20 R20

30. LDI R16, $15 STS $67, R16 LDI LDS ADD ADD ADD ADD ADD

R19, R20, R19, R19, R19, R19, R19,

0 $67 R20 R20 R20 R20 R20

STS $67, R19

31. LDُ S R27, $68 ُ COM R27

32. LDُ S R19, $68 ُ OUT PORTC, R19

SECTION 2.4: AVR STATUS REGISTER 33. 8 34. 0, 5

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35. 36. 37. 38.

3, 2 When there is a carry beyond the D7 bit. When there is a carry from the D3 to the D4 bit. C = 1 because there is a carry beyond the D7 bit. Z = 1 because the R20 (the result) has value 0 in it after the addition.

39. (a) $54 0101 0100 $C4 1100 0100 $118 10001 1000 C = 1 because there is a carry beyond the D7 bit. +

R20 = $18

(b) $00 0000 0000 $FF 1111 1111 $FF 1111 1111 C = 0 because there is no carry beyond the D7 bit. +

R23 = $FF

(c) $FF 1111 1111 $05 0000 0101 $FF 10000 0100 C = 1 because there is a carry beyond the D7 bit. +

R30 = $04

40. LDI LDI ADD ADD ADD ADD ADD

R16, R20, R16, R16, R16, R16, R16,

$55 $55 R20 R20 R20 R20 R20

SECTION 2.5: AVR DATA FORMAT AND DIRECTIVES 41. .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU

MYDAT_1 = $37 MYDAT_2 = $62 MYDAT_3 = $47 MYDAT_4 = $50 MYDAT_5 = $C8 MYDAT_6 = $41 MYDAT_7 = $AA MYDAT_8 = $FF MYDAT_9 = $90 MYDAT_10 = $7E MYDAT_11 = $0A MYDAT_12 = $0F

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42. .EQU .EQU .EQU .EQU .EQU .EQU

DAT_1 DAT_2 DAT_3 DAT_4 DAT_5 DAT_6

= = = = = =

$16 $56 $99 $20 $F6 $FB

43. .EQU .EQU .EQU .EQU .EQU .EQU

TEMP0 TEMP1 TEMP2 TEMP3 TEMP4 TEMP5

= = = = = =

$60 $61 $62 $63 $64 $65

LDI STS STS STS STS STS STS

R16, $11 TEMP0, R16 TEMP1, R16 TEMP2, R16 TEMP3, R16 TEMP4, R16 TEMP5, R16

LDS LDS ADD LDS ADD LDS ADD LDS ADD LDS ADD

R20, R21, R20, R21, R20, R21, R20, R21, R20, R21, R20,

TEMP0 TEMP1 R21 TEMP2 R21 TEMP3 R21 TEMP4 R21 TEMP5 R21

SECTION 2.6: INSTRUCTION TO AVR ASSEMBLY PROGRAMMING AND SECTION 2.7: ASSEMBLING AN AVR PROGRAM 44. 45. 46. 47. 48. 49. 50. 51.

Low, High Assembly Assembler True False False No Because they do not produce machine instructions. They just give directions to the assembler. 52. True 53. hex 54. hex, eep, lst, map, and obj

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SECTION 2.8: THE PROGRAM AND PROGRAM ROM SPACE IN THE AVR 55. 0 56. It executes whatever is at location 0 which could be garbage in this case. 57. a) 2 bytes b) 2 bytes c) 2 bytes d) 2 bytes e) 2 bytes f) 2 bytes g) 2 bytes h) 4 bytes 58. (a) LDI STS LDI STS LDI STS LDI STS LDI STS

R20,‘1’ 0x100, R20 R20,‘9’ 0x101, R20 R20,‘5’ 0x102, R20 R20,‘1’ 0x103, R20 R20,‘2’ 0x104, R20

(b) LDI LDS ADD LDS ADD LDS ADD LDS ADD LDS ADD STS

R19,0 R16, 0x100 R19,R16 R16, 0x101 R19,R16 R16, 0x102 R19,R16 R16, 0x103 R19,R16 R16, 0x104 R19,R16 0x306, R19

(c)

59. In AVR, each location of the program memory holds 2 bytes; therefore: a) Memory locations = 32 K / 2 = 16 K = 16 * 1024 = 16384 Î Last location = 16383 = $3FFF

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60. 61. 62. 63.

b) Memory locations = 8 K / 2 = 4 K = 4 * 1024 = 4096 Î Last location = 4095 = $FFF c) Memory locations = 64 K / 2 = 32 K = 32 * 1024 = 32768 Î Last location = 32767 = $7FFF d) Memory locations = 16 K / 2 = 8 K = 8 * 1024 = 8192 Î Last location = 8191 = $1FFF e) Memory locations = 128 K / 2 = 64 K = 64 * 1024 = 65536 Î Last location = 65535 = $FFFF In ATmega32, the program memory is 32K bytes. Since the 32K is organized as 16K x 2 Bytes, the last location has the address of $3FFF. Therefore the program counter can have values between 0 and $3FFF. $7FFF = 32767 Î the program memory has 32767 + 1 = 32768 locations. Therefore, it has 65536 = 64K bytes. $3FF = 1023 Î the program memory has 1024 locations. Therefore, the size of program memory is 2 Kbytes. (a) $1FFF + 1 = 8,192 words = 16,384 bytes = 16 KB (b) $3FFF + 1 = 16,384 words = 32 KB (c) $7FFF + 1 = 32,768 words = 64 KB (d) $FFFF + 1 = 65,536 words = 128 KB (e) $1FFFF + 1 = 131,072 words = 256 KB (f) $3FFFF + 1 = 262,144 words = 512 KB (g) $FFF + 1 = 4096 words = 8 KB (h) $1FF + 1 = 512 words = 1 KB

64. (a) $3FF + 1 = 1024 words = 2 KB (b) $7FF + 1 = 2048 words = 4 KB (c) $7FFFF + 1 = 524,288 words = 1,048,576 KB (d) $FFFFF + 1 = 1,048,576 words = 2048 KB = 2 MB (e) $1FFFFF + 1 = 2,097,152 words = 4096 KB = 4 MB (f) $3FFFFF + 1 = 4,194,304 words = 8192 KB = 8 MB (g) $5FFF + 1 = 24,576 words = 49152 bytes = 48 KB (h) $BFFFF + 1 = 786,432 words = 1,572,864 bytes = 1536 KB = 1.5 MB 65. 2 bytes 66. 2 bytes 67. As shown in Figure 2-14, 8 bits are set aside for K. Therefore, K can be between 0 and 255. 68. $0C01 = 0000 1100 0000 0001. According to the figures of page 92, it is the machine code for the ADD instruction. 69. It is a 4-byte instruction. 16 bits of it are set aside for K. Therefore, K can be between 0 and 65535. In AVR, the data memory is 64 KB; as a result, STS can address the entire memory space. 70. It is a 4-byte instruction. 16 bits of it are set aside for K. Therefore, K can be between 0 and 65535. In AVR, the data memory is 64 KB; as a result, LDS can address the entire memory space. 71. In the JMP instruction, 22 bits are set aside for K. Therefore K can be between 0 and 4,194,303.

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SECTION 2.9: RISC ARCHITECTURE IN THE AVR 72. RISC is reduced instruction set computer; CISC stands for complex instruction set computer. 73. CISC 74. RISC 75. RISC 76. CISC 77. False

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CHAPTER 3: BRANCH, CALL AND TIME DELAY LOOP SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING 1. 2. 3. 4. 5. 6.

256 The instruction following the jump PC Relative jump, 2 4 RJMP is 2 byte whereas JMP is 4 bytes. Therefore RJMP uses less memory location. 7. False 8. False 9. a, b, and d 10. The RJMP instruction is a 2-byte instruction. Of the 16 bits, the first 4 bits are set aside for the opcode and the other 12 bits are used for the address of the destination (operand). The operand can be between -2048 and 2047. 11. True 12. LDI BEGIN:LDI HERE: DEC BRNE DEC BRNE

R20, 10 R21, 100 R21 HERE R20 BEGIN

13. L1: L2: L3:

LDI LDI LDI

R20, 10 R21, 100 R22, 100

DEC BRNE DEC BRNE DEC BRNE

R22 L3 R21 L2 R20 L1

14. 200 * 100 = 20,000 times 15. Negative 16. Positive SECTION 3.2: CALL INSTRUCTIONS AND STACK 17. 4 18. 2

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19. False 20. True 21. In the AVRs whose program counter is not longer than 16 bits, 2 bytes are pushed into the stack. In the AVRs whose program counters are longer than 16 bits, 3 bytes are pushed. 22. In the AVRs whose program counter is not longer than 16 bits, 2 bytes are pushed into the stack. In the AVRs whose program counters are longer than 16 bits, 3 bytes are pushed. 23. 0 24. When the RET instruction at the end of the subroutine is executed, the top location of the stack is copied back to the program counter and the stack pointer is incremented. As a result the CALL is loaded into the PC, and the instruction below the CALL instruction is executed. 25. In AVR, the stack can be as big as the internal RAM. 26. When a subroutine is called, the address of the instruction just below the CALL instruction is pushed onto the stack. SECTION 3.3: AVR TIME DELAY AND INSTRUCTION PIPELINE 27. crystal frequency = 1 / machine cycle = 1 / 1.25 µs = 0.8 MHz. 28. machine cycle = 1 / 20 MHz = 0.05 µs 29. machine cycle = 1 / 10 MHz = 0.1 µs 30. machine cycle = 1 / 16 MHz = 0.0625 µs 31. False 32. LDI BACK: LDI HERE: NOP DEC BRNE DEC BRNE

Machine Cycle R16, 200 1 R18, 100 1 1 R18 1 HERE 2/1 R16 1 BACK 2/1

1 + (1 + (1 + 1 + 2) × 100 – 1 + 1 + 2) × 200 – 1 = 1 + (1 + 400 + 2) × 200 = 1 + 403 × 200 – 1 = 80,600 machine cycles 80,600 × 0.125 µs = 10075 µs = 10.075 ms 33. LDI BACK: LDI HERE: NOP NOP DEC BRNE DEC BRNE

Machine Cycle R20, 200 1 R22, 100 1 1 1 R22 1 HERE 2/1 R20 1 BACK 2/1

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1 + (1 + (1 + 1 + 1 + 2) × 100 – 1 + 1 + 2) × 200 – 1 = 1 + (1 + 500 + 2) × 200 = 1 + 503 × 200 – 1 = 100,600 machine cycles 100,600 × 0.125 µs = 12575 µs = 12.575 ms 34. LDI BACK: LDI HERE: NOP DEC BRNE DEC BRNE

Machine Cycle R20, 200 1 R21, 250 1 1 R21 1 HERE 2/1 R20 1 BACK 2/1

1 + (1 + (1 + 1 + 2) × 250 – 1 + 1 + 2) × 200 – 1 = (1 + 1000 + 2) × 200 = 1003 × 200 = 200,600 machine cycles Instruction cycle = 1 / 4 MHz = 0.25 µs 200600 × 0.25 µs = 50150 µs = 50.150 ms 35. LDI BACK: LDI NOP NOP NOP HERE: DEC BRNE DEC BRNE

Machine Cycle R20, 200 1 R25, 100 1 1 1 1 R25 1 HERE 2/1 R20 1 BACK 2/1

1 + (1 + 1 + 1 + 1 + (1 + 2) × 100 – 1 + 1 + 2) × 200 – 1 = 1 + (4 + 300 + 2) × 200 – 1 = 61,200 machine cycles Instruction cycle = 1 / 10 MHz = 0.1 µs 61200 × 0.1 µs = 6120 µs = 6.12 ms

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CHAPTER 4: AVR I/O PORT PROGRAMMING SECTION 4.1: I/O PORT PROGRAMMING IN AVR 1. 40 pins 2. 2 pins are assigned to VCC: VCC and AVCC; and 2 pins are assigned to GND: GND and AGND. 3. 32 pins 4. 8 pins (pins 33-40) 5. 8 pins (pins 1-8) 6. 8 pins (pins 22-29) 7. 8 pins (pins 14-21) 8. input 9. The DDRx register is used for the purpose of making a given port an input or output port. The contents of PORTx registers determine the value of each port when it is output. 10. .INCLUDE "M32DEF.INC" LDI R20, 0x00 OUT DDRC, R20 LDI R20,0xFF OUT DDRB, R20 OUT DDRD, R20 AGAIN: IN R20, PINC OUT PORTB, R20 OUT PORTD, R20 JMP AGAIN

11. .INCLUDE "M32DEF.INC" LDI R20, 0x00 OUT DDRD, R20 LDI R20,0xFF OUT DDRB, R20 OUT DDRC, R20 AGAIN: IN R20, PIND OUT PORTB, R20 OUT PORTC, R20 JMP AGAIN

12. pins 14 and 15 13. Port DDRA DDRB DDRC

Address $3A $37 $34

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14. (a) .INCLUDE “M32DEF.INC” LDI R16, 0xFF OUT DDRB, R16 OUT DDRC, R16 L1: LDI R16, 0xAA OUT PORTB, R16 OUT PORTC, R16 LDI R16, 0x55 OUT PORTB, R16 OUT PORTC, R16 RJMP L1

(b) .INCLUDE “M32DEF.INC” LDI R16, 0xFF OUT DDRB, R16 OUT DDRC, R16 LDI R16, 0xFF OUT PORTB, R16 OUT PORTC, R16 L1: COM R16 OUT PORTB, R16 OUT PORTC, R16 RJMP L1

SECTION 4.2: I/O BIT MANIPULATION PROGRAMMING 15. In ATmega32, all ports are bit addressable. 16. The advantage of the bit addressing is that it allows each bit to be modified without affecting the other bits. 17. COM PORTB is invalid because AVR ports are not read-modify-write. 18. .INCLUDE “M32DEF.INC” SBI DDRB, 2 SBI DDRB, 5 L1: SBI PORTB, 2 SBI PORTB, 5 CBI PORTB, 2 CBI PORTB, 5 RJMP L1

19. .INCLUDE “M32DEF.INC” SBI DDRD, 3 SBI DDRD, 7 SBI DDRC, 5 L1: SBI PORTD, 3 SBI PORTD, 7 SBI PORTC, 5 CBI PORTD, 3 CBI PORTD, 7 CBI PORTC, 5 RJMP L1

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20. .INCLUDE “M32DEF.INC” LDI R16,0xFF OUT DDRD,R16 CBI DDRC, 3 L1: SBIS PINC, 3 RJMP L1 LDI R16,0x55 OUT PORTD,R16 HERE: RJMP HERE

21. .INCLUDE “M32DEF.INC” LDI R16,0xFF OUT DDRC,R16 CBI DDRB, 7 L1: SBIC PINB, 7 RJMP L1 HERE: LDI R16,0x55 OUT PORTC,R16 LDI R16,0xAA OUT PORTC,R16 RJMP HERE

22. .INCLUDE “M32DEF.INC” LDI R16,0xFF OUT DDRB,R16 CBI DDRA, 0 L1: SBIS PINA, 0 RJMP L2 LDI R16,0x99 OUT PORTB,R16 RJMP L1 L2: LDI R16,0x66 OUT PORTB,R16 RJMP L1

;when PA0 is low the line is executed ;when PA0 is high the line is executed

23. .INCLUDE “M32DEF.INC” CBI DDRB, 5 SBI DDRB, 3 L1: SBIS PINB, 5 RJMP L1 CBI PORTB,3 SBI PORTB,3 CBI PORTB,3 L2: RJMP L2

;jump L1 while PB5 is low ;when PB5 is high the line is executed

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24. .INCLUDE “M32DEF.INC” CBI DDRC, 3 SBI DDRC, 4 L1: SBIS PINC, 3 RJMP L2 SBI PORTC, 4 RJMP L1 L2: CBI PORTC, 4 RJMP L1

;PC3 as input ;PC4 as output ;jump L1 while PC3 is low ;when PC3 is high the line is executed

25. Make PD6 and PD7 input

CBI CBI

DDRD, 6 DDRD, 7

Make PC0 and PC7 output

SBI SBI

DDRC, 0 DDRC, 7

Yes

Is PD6 one

L1:

SBIS PIND, 6

No

Jump to PD6_LOW

RJMP PD6_LOW

Set PC0

SBI PORTC, 0 RJMP L2

Clear PC0

Yes

Is PD7 one

PD6_LOW: CBI PORTC, 0

L2:

SBIS PIND, 7

No

Jump to PD7_LOW

Set PC7

Clear PC7

RJMP PD7_LOW

SBI RJMP PD7_LOW: CBI RJMP

PORTC, 7 L1 PORTC, 7 L1

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.INCLUDE “M32DEF.INC” CBI DDRD, 6 CBI DDRD, 7 SBI DDRC, 0 SBI DDRC, 7 L1: SBIS PIND, 6 RJMP PD6_LOW SBI PORTC, 0 RJMP L2 PD6_LOW: CBI PORTC, 0 L2: SBIS PIND, 7 RJMP PD7_LOW SBI PORTC, 7 RJMP L1 PD7_LOW: CBI PORTC, 7 RJMP L1

;PD6 ;PD7 ;PC0 ;PC7

as as as as

input input output output

;jump PD6_LOW if PD6 is low ;when PD6 is high the line is executed

;jump L1 while PD7 is low ;when PD7 is high the line is executed

26. .INCLUDE “M32DEF.INC” CBI DDRB, 5 CBI DDRB, 6 LDI R16, 0xFF OUT DDRC, R16 L1: SBIC PINB, 5 RJMP L2 IS_LOW: LDI R16, 0x55 OUT PORTC, R16 RJMP L1 L2: SBIS PINB, 6 RJMP IS_LOW LDI R16, 0xAA OUT PORTC, R16 RJMP L1

;jump L2 if PB5 is high

;jump IS_LOW if PB6 is low

27. .INCLUDE “M32DEF.INC” CBI DDRB, 5 CBI DDRB, 6 LDI R16, 0xFF OUT DDRC, R16 L1: SBIS PINB, 5 RJMP L2 IS_HIGH: LDI R16, 0xAA OUT PORTC, R16 RJMP L1 L2: SBIC PINB, 6 RJMP IS_HIGH BOTH_LOW: LDI R16, 0x55 OUT PORTC, R16 RJMP L1 28. 1001 1011 1011 0011 29. 1001 1010 1101 1010

;jump L2 if PB5 is low

;jump IS_HIGH if PB6 is high

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CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS SECTION 5.1: ARITHMETIC INSTRUCTIONS 1. All the calculations are done in hexadecimal system. (a) 3 F +4 5 8 4 C = 0, Z = 0, H = 1 (b)

(c)

(d)

9 9 +5 8 F 1

C = 0, Z = 0, H = 1

1 +F F +0 0 (1) 0 0

C = 1, Z = 1, H = 1

F F +0 1 (1) 0 0

C = 1, Z = 1, H = 1

2. LDI LDI ADD

R20,25 R21,10 R20,R21

LDI LDI ADD LDI ADC

R20,0x25 R21,0x19 R20,R21 R21,0x12 R20,R21

LDI LDI ADD LDI ADD LDI ADD

R20,0x25 R21,0x19 R20,R21 R21,0x12 R20,R21 R21,0x3D R20,R21

(a)

Take 2’s complement of 0x12 (0001 0010): Add to 0x23: 0010 0011 + 1110 1110 1 0001 0001 Result = 0001 0001 = 0x11

3.

4.

5. 1110 1110

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(b)

Take 2’s complement of 0x53 (0101 0011): Add to 0x43: 0100 0011 + 1010 1101 0 1111 0000 Result = 1111 0000 = 0xF0

(c)

99 decimal = 0x63 = 0110 0011 Take 2’s complement of 0x63 (0110 0011): Add to 0x63: 0110 0011 + 1001 1101 1 0000 0000 Result = 0000 0000 = 0x00

1010 1101

1001 1101

6. (a) LDI SUBI

R20,0x23 R20,0X12

LDI SUBI

R20,0x43 R20,0X53

LDI SUBI

R20,99 R20,99

(b) (c)

7. LDI LDI LDI LDI ADD ADC

R23,0x7F R22,0x9A R21,0xBC R20,0x48 R20,R22 R21,R23

LDI LDI LDI LDI SUB SBC

R23,0x7F R22,0x9A R21,0xBC R20,0x48 R20,R22 R21,R23

LDI LDI MUL

R21,77 R20,34 R20,R21

;the result will be in R1:R0

LDI LSR LSR

R21,64 R21 R21

;divide the number by 2. R21 = 64/2 = 32 ;divide the number by 3. R21 = 32/2 = 16

8.

9.

10.

11. R1:R0

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SECTION 5.2: SIGNED NUMBER CONCEPTS AND ARITHMETIC OPERATIONS 12.

(a) 1110 1001 (e) 1000 0000

(b) 0000 1100 (f) 0111 1111

(c) 1110 0100

(d) 0110 1111

13. unsigned 14. (a) LDI LDI ADD

R21,15 R20,-12 R20,R21

0000 1111 + 1111 0100 = (1)0000 0011 V = 0

LDI LDI ADD

R21,-123 R20,-127 R20,R21

1000 0101 + 1000 0001 = (1)0000 0110 V = 1

LDI LDI ADD

R21,+25 R20,+34 R20,R21

0010 0101 + 0011 0100 = (0)0101 1001 V = 0

LDI LDI ADD

R21,-127 R20,+127 R20,R21

1000 0001 + 0111 1111 = (1)0000 0000 V = 0

(b)

(c)

(d)

15. C flag is raised when there is a carry out of D7 of the result, but V flag is raised when there is a carry from D6 to D7 and no carry out of D7 or when there is no carry from D6 to D7 and there is a carry out of D7 of the result. C flag is used to indicate overflow in unsigned arithmetic operations while V flag is involved in signed operations.

16. When there is a carry from D6 to D7 of result, but there is no carry out of D7 (C=0) OR when there is no carry from D6 to D7 of result, but there is a carry out of D7 (C=1) 17. Status register 18. BRVS and BRVC instructions - BRCS and BRCC instructions SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS 19. (a) 0110 0101 AND 0111 0110 = 0110 0100 = 0x64 (b) 0111 0000 OR 0110 1011 = 0111 1011 = 0x7B (c) 1001 0101 EXOR 1010 1010 = 0011 1111 = 0x3F (d) 0101 1101 AND 0111 0101 = 0101 0101 = 0x55 (e) 1100 0101 OR 0001 0010 = 1101 0111 = 0xD7 (f) 0110 1010 EXOR 0110 1110 = 0000 0100 = 0x04 (g) 0011 0111 OR 0010 0110 = 0011 0111 = 0x37

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20. BRSH is used after the compare instruction. If the unsigned binary number represented in Rd was greater than or equal to the unsigned binary number represented in Rr, then program execute a jump. 21. Yes. 22. both (a) and (b) 23. 0x85 SECTION 5.4: ROTATE AND SHIFT INSTRUCTIONS AND DATA SERIALIZATION 24. (a) 0 01010110 Æ 0 01100101 Æ C = 0 Æ 1 00110010 Æ 0 10011001 = 99h (b) 0 0011 1001 Æ C = 1 Æ 0 0111 0011 Æ 0 11100110 = E6h (c) C = 0 Æ 0 0100 1101 Æ 0 1101 0100 Æ 1 1010 1000 Æ 0 1101 0100 = D4h (d) 0 0111 1010 Æ 0 0011 1101 = 3Dh 25. (a) LDI MOV ANDI CLC ROL ROL ROL ROL ANDI CLC ROL ROL ROL ROL ROL OR

R20,0xFA R21, R20 R20,0x0F

LDI MOV ANDI CLC ROR ROR ROR ROR ROR ANDI CLC ROR ROR ROR ROR OR

R20,0xFA R21, R20 R20,0x0F

R20 R20 R20 R20 R21,0xF0 R21 R21 R21 R21 R21 R20,R21

(b)

R20 R20 R20 R20 R20 R21,0xF0 R21 R21 R21 R21 R20,R21

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26. .INCLUDE "M32DEF.INC" LDI R20,0b10111001 LDI R21, 8 ;set a counter to 8 LDI R22, 0 ;set number of zeros to 0 AGAIN:ROL R20 ;move MSB to Carry BRCC NEXT ;branch if no carry INC R22 ;increment number of zeros NEXT: DEC R21 ;decrement the counter BRNE AGAIN

27. LDI LDI AGAIN:ROR BRCS INC CPI BRNE FIN:

R20, 0x68 R21, 0 R20 FIN R21 R21,8 AGAIN

LDI LDI AGAIN:ROL BRCS INC CPI BRNE FIN:

R20, 0x68 R21, 0 R20 FIN R21 R21,8 AGAIN

;set a counter to 0 ;move MSB to Carry ;branch if carry is one ;increment the counter ;Is there any other bit ;Jump AGAIN ;R21 is the position and is ;9 if there is no 1

28. ;set a counter to 0 ;move MSB to Carry ;branch if carry is one ;increment the counter ;is there any other bit ;jump AGAIN ;R21 is the position and is ;9 if there is no 1

SECTION 5.5: BCD AND ASCII CONVERSION 29. (a) LDI MOV ANDI ORI MOV SWAP ANDI ORI

R20,0x76 R21,R20 R21,0x0F R21,0x30 R22,R20 R22 R22,0x0F R22,0x30

;the packed BCD to be converted is 76 ;R21 = R20 = 76H ;mask the upper nibble (R21 = 06H) ;make it ASCII (R21 = 39H) ;R22 = R20 = 76H ;swap nibbles (R22 = 67H) ;mask the upper nibble (R22 = 07) ;make it ASCII (R22 = 37H)

LDI MOV ANDI ORI MOV SWAP ANDI ORI

R20,0x87 R21,R20 R21,0x0F R21,0x30 R22,R20 R22 R22,0x0F R22,0x30

;the packed BCD to be converted is 87 ;R21 = R20 = 87H ;mask the upper nibble (R21 = 07H) ;make it ASCII (R21 = 37H) ;R22 = R20 = 87H ;swap nibbles (R22 = 78H) ;mask the upper nibble (R22 = 08) ;make it ASCII (R22 = 38H)

(b)

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30. LDI LDI ANDI SWAP

R21,'3' R22,'2' R21,0x0F R21

ANDI OR MOV

R22,0x0F R22,R21 R20,R22

;load character 3 (0x33) to R21 ;load character 2 (0x32) to R22 ;mask upper nibble of R21 ;swap nibbles of R21 ;to make upper nibble of packed BCD ;mask upper nibble of R22 ;join R22 and R21 to make packed BCD ;move the result to R20

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CHAPTER 6: AVR ADVANCED ASSEMBLY LANGUAGE PROGRAMMING SECTION 6.1: INTRODUCING SOME MORE ASSEMBLER DIRECTIVES 1. R20 = (0x20 & 0x6F) | 0x14 = (0x20) | 0x14 = 0x34 R21 = 0x6F – (0x20 + 0x14) = 0x6F – 0x34 = 0x3B

2. R30 = LOW (0x100