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SMB1360 Device Revision Guide 80-NH006-4 Rev. C September 15, 2014 Submit technical questions at: https://support.cdmatech.com
Confidential and Proprietary – Qualcomm Technologies, Inc. NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to: [email protected]. Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm or its subsidiaries without the express approval of Qualcomm's Configuration Management. Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express written permission of Qualcomm Technologies, Inc. Qualcomm is a registered trademark of QUALCOMM Incorporated. All QUALCOMM Incorporated trademarks are used with permission. Other product and brand names may be trademarks or registered trademarks of their respective owners. This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S. and international law is strictly prohibited.
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Revision history
80-NH006-4 Rev. C
Revision
Date
Description
AA
October 2013
B
April 2014
Issue 12: Added to Table 4 Known issues. Added to Section 3.2 Issues – description, impact, and workaround Figure 1 SMB1360 part marking (top view, not to scale): Updated the figure to show TTT added to Line 5 Table 2 Part marking line definitions: Updated Line 5 with TTT
C
September 2014
Table 1 Primary documents SMB1360: Added document 80-NH006-3 Table 2 Part marking line definitions: Removed fab location country code Table 3 Device identification code: Added RR value 02 and 03 Section 3 Known Issues: Removed text on known issues for ES 1.0 samples Table 4 Known issues: Added information on RR 02 and 03
Initial release.
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1 Introduction Technical information for the SMB1360 device is primarily covered by the documents listed in Table 1. All documents are available from the CDMATech support website at http://support.cdmatech.com. Table 1 Primary documents SMB1360 Document number
Document title
80-NH006-1
SMB1360 Device Specification
80-NH006-4 (this document)
SMB1360 Device Revision Guide
80-NH006-3
SMB1360 Evaluation Board User Guide
1.1 Scope and intended audience This device revision guide identifies issues with all released SMB1360 samples. The following information is included:
Introduction to this document and its topic (this chapter)
Device identification (Chapter 2)
Device marking
Sample testing – engineering samples (ES) and commercial samples (CS) explanations
Known issues (Chapter 3)
Issue description
Impact to system performance
Possible workarounds (what designers should do to minimize the issue’s impact)
This device revision guide is intended for new product developers who are designing, testing, or evaluating phones or terminals that include the SMB1360 devices.
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2 Device Identification The SMB1360 device is identified by markings on the top surface and by the contents of an identification register; these identification techniques are described in Section 2.1. Further details about each sample type are presented in Section 2.2.
2.1 Device marking
Line 1: Line 2: Line 3: Line 4: Line 5: Ball 1 identifier
Figure 1 SMB1360 part marking (top view, not to scale) Table 2 Part marking line definitions Line
Marking
Description
1
PROD1
Product name 1360
2
PROD2
Configuration/revision/feature code See Table 3
3
XXXXXX
Tracability information
4
FAYWW
F = Wafer fab location source code F = A is for GF F = B is for GF A = Assembly (drop ball) site code A = A is for ASE, Taiwan A = B is for Statschippac, Singapore Y = Single/last digit of year WW = Two digit work week based on calendar year
5
• TTT ##
• = Dot identifying ball 1 TTT = Engineering trace code ## = Additional traceability information
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Table 3 Device identification code SMB variant
RR value
HW ID #
SMB1360
00
ES 1.0
SMB1360
02
ES 2.0
SMB1360
03
CS 2.1
2.2 Sample testing 2.2.1 Engineering samples (ES) These devices have undergone limited testing and may have significant feature limitations. They are suitable to assist with printed circuit board (SMB1360) development, to conduct board-level electrical evaluation tests, and to explore manufacturing considerations. Engineering samples are not to be used for phone-level qualification.
2.2.2 Commercial samples (CS) These devices have undergone full production-level testing and meet the specifications and features described in the device specification, except as otherwise noted in this document. They have passed device-level qualification. Commercial samples are suitable to be used for performance testing and phone-level production and qualification.
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3 Known Issues
3.1 Summary of known issues All known issues for each revision of the SMB1360 device are summarized in Table 4. The text within the Issue column provides links to the sections of this document that explain the issues, regardless of the sample type (or types) on which they occur. An X in any of the other columns indicates that the issue occurs on the corresponding sample type. Table 4 Known issues SMB1360 #
Issue RR = 00
RR = 02
RR = 03
1
ADC performances
X
–
–
2
VCHG
X
–
–
3
Battery missing
X
–
–
4
THERM pin
X
–
–
5
BMD pin deglitch
X
–
–
6
Oscillator shift
X
–
–
7
IRQ thresholds
X
–
–
8
Cutoff SOC forecast
X
–
–
9
Reload on unplug
X
–
–
10
Fast charge current
X
–
–
11
Shutdown current
X
–
–
12
Erroneous power-on-reset
X
X
–
3.2 Issues – description, impact, and workaround Issue 1
ADC performances
Description
Performance specifications of the device may not entirely be met.
Impact
IC validation highlighted that ADC performances are best when the following conditions are met: When the charger is enabled, the duty cycle is in the range 80–100%. When the charger is enabled, the DC-DC buck stage is operated asynchronously (i.e., the low side FET is maintained OFF). A schottky diode is placed in parallel to the low side FET, from the switching node software to ground PGND. An RC snubber is placed in parallel to the the low side FET, from the switching node software to ground PGND.
Workaround
The evaluation kit board provided with the samples is already set to include the external schottky diode and the RC snubber net. Samples are programmed to disable the LS FET. Return to Table 4
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Issue 2
VCHG
Description
The SMB1360 device is provided with a dedicated pin for analog current reporting (VCHG). Voltage at the pin is proportional to the battery current sensed through the dedicated current sense resistor. This feature is not operational.
Impact
No voltage is provided on the pin – information about battery current is not available.
Workaround
STAT pin can alternatively be used to detect if the charger is enabled. Information about battery current is retrievable through dedicated sensing points on the evaluation kit board: J109: Differential sensing across the current sense resistor R10 (20 m) TP125 (CS_P) and TP126 (CS_N): Test points directly connected to the IC pins (filtered differential voltage across current sense resistor R10 (20 m) Return to Table 4
Issue 3
Battery missing
Description
Battery is not reported missing when DCIN is not present. The battery missing detection (BMD) procedure detects when a battery is actually connected to the system. The SMB1360 device is provided with different options to complete BMD procedures: BMD pin THERM pin BMD algorithm and poller When DCIN is not present, the BMD flag is not issued. Consequently, the battery can be detached from the system. The FG algorithm incorrectly computes SoC while the battery voltage decays, as the battery is not reported missing.
Impact
This potentially could affect the SoC accuracy when the battery is newly reinserted while DCIN is still missing.
Workaround
FG testability is not affected by the issue. The algorithm can still be tested with DCIN present. Return to Table 4
Issue 4
THERM pin
Description
The SMB1360 is provided with dedicated circuitry for temperature sensing. Temperature information is retrieved through a thermistor connected to the THERM pin. BIAS pin provides the necessary biasing voltage to the external voltage divider. See Figure 2. Biasing circuitry is malfunctioning. No biasing voltage is provided at RBIAS pin when: The DCIN is not present The THERM pin is not enabled as a battery missing detection option
Impact
Temperature information is not available when the above conditions are not met which affects temperature measurements during battery operation.
Workaround
Full FG algorithm testability is ensured when DCIN is present. Return to Table 4
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RBIAS 10k
THERM PCB Thermistor
Figure 2 Therm schematic
Issue 5
BMD pin deglitch
Description
BMD directly connects to RID pad in the battery package. The BMD pin is the elected option to detect battery insertion or disconnect. The deglitching time at the BMD pin revealed short to avoid faulty battery voltage reading at first battery insertion. The battery is deemed connected and FG operations are resumed while the battery voltage is not stable yet.
Impact
This could potentially lead to faulty battery voltage measurements, affecting SoC accuracy.
Workaround
To avoid faulty readings, increase the deglitching time on the BMD pin. Additional capacitance has been added to the positive node of the battery pads. Return to Table 4
Issue 6
Oscillator shift
Description
Internal oscillator shows 10% shift, linked to the battery voltage.
Impact
The shift could potentially affect the FG algorithm SoC accuracy, tampering the integration of the current in the Coulomb counter.
Workaround
Extensive tests done on bench did not show specific SoC accuracy’s decrease at a higher battery voltage. The SoC improves when approaching the end of the charge cycle (counter-effect of ADC performances improvement at higher duty cycle). Return to Table 4
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Issue 7
IRQ thresholds
Description
Some FG related IRQ are not selectable unless in test mode.
Impact
The following IRQ thresholds (related to FG) are not changeable unless in test mode: Delta SoC: Minimum SoC changing step to be reported JEITA soft cold : Soft cold JEITA threshold JEITA soft hot: Soft hot JEITA threshold Alert-volt min: Low battery voltage alarm threshold Alert SoC max: Full SoC (not 100% Battery SoC) Alert SoC min: Alert for minimum SoC (for example, it can be used to limit the operation of the system) IRQ volt empty: Empty battery voltage alert
Workaround
The IC can operate normally even if this issue is present. The customer must communicate the IRQ thresholds ahead of time and have it trimmed on parts. No later changes are possible through the GUI in the volatile memory. Return to Table 4
Issue 8
Cutoff SOC forecast
Description
This issue could affect FG algorithm performances at low temperature. Temperature variation implies recalculation of the forecast CutOff voltage. At the extreme, passing from room temperature to -20 °C, the CutOff voltage has to be updated to counter effect the account of a largely increased ESR. The way the algorithm is operated now, if the system is in standby (no battery current at all), the CutOff voltage is not updated and the SoC is reported constant as temperature decreases.
Impact
This could marginally affect the operation by the customer. This issue could affect FG performances during cold test operation.
Workaround
It is recommended to guarantee at least 50 mA of residual battery current before proceeding with the test. Return to Table 4
Issue 9
Reload on unplug
Description
The reload on unplug option, when enabled, forces the IC to discard changes made on volatile memory and reupload the OTP stored setup at the DCIN disconnect. If the reload on unplug option is disabled, and reload regulates from OTP, an I2C command is issued and the I2C communication gets stuck.
Impact
The issue could affect customer’s operation with the SMB1360 device.
Workaround
A full power cycle is necessary to resume normal operation. Return to Table 4
Issue 10
Fast charge current
Description
Settings for fast charge current trimming values < 900 mA are not trimmable in the correct range. Values affected are: 450 mA 600 mA 750 mA 950 mA
Impact
It is not trimmable when current is selected < 900 mA.
Workaround
In the device specification, the actual set of values is the one reported above. The actual trim target will be changed to 650 mA, 750 mA, 850 mA, and 950 mA. Return to Table 4
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Issue 11
Shutdown current
Description
Shutdown current and standby current are out of specification. Shutdown supply current does not meet the device specification. It appears to be temperature dependent. The same results will occur if the part is put in shutdown by register or pin control.
Impact
When there is no input present and the charger is running, the standby current is around 1.6 mA; when the FG is in reset, the consumption is 0.928 mA.
Workaround
There is no workaround available for this issue. The issue has been identified and will be fixed in the next revision of the device. Return to Table 4
Issue 12
Erroneous power-on-reset
Description
Depending on the input voltage and the battery voltge slew rate and levels, a few devices may experience an erroneous POR event.
Impact
Fast ramp rates of input or battery voltage may cause this event, resulting in the loss of I2C communication and the SYS_LDO output to remain in a LOW state.
Workaround
It is expected that a slower slew rate of input or battery voltage will prevent the device POR from taking place. The issue has been identified and will be fixed in the next revision of the device. Return to Table 4
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