Silicon-on-insulator (SOI) technology: Manufacture and applications 9780857095268, 9780124200319, 9781455731435, 9780081024010, 9780081024027, 0857095269

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Silicon-On-Insulator (SOI) Technology (ISBN: 9780857095268) FinFet Modeling for IC Simulation and Design: Using the BSIM-CMG Standard (ISBN: 9780124200319) The IGBT Device (ISBN: 9781455731435)

Woodhead Publishing Series in Electronic and Optical Materials

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design Edited by

CHENMING HU SOURABH KHANDELWAL YOGESH SINGH CHAUHAN THOMAS MCKAY JOSEF WATTS JUAN PABLO DUARTE PRAGYA KUSHWAHA HARSHIT AGARWAL

Woodhead Publishing is an imprint of Elsevier The Officers’ Mess Business Centre, Royston Road, Duxford, CB22 4QH, United Kingdom 50 Hampshire Street, 5th Floor, Cambridge, MA 02139, United States The Boulevard, Langford Lane, Kidlington, OX5 1GB, United Kingdom Copyright © 2019 Elsevier Ltd. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from the publisher. Details on how to seek permission, further information about the Publisher’s permissions policies and our arrangements with organizations such as the Copyright Clearance Center and the Copyright Licensing Agency, can be found at our website: http://www.elsevier.com/permissions. This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein). Notices Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary. Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein. British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the Library of Congress ISBN: 978-0-08-102401-0 (print) ISBN: 978-0-08-102402-7 (online) For information on all Woodhead Publishing publications visit our website at https://www.elsevier.com/books-and-journals

Publisher: Matthew Deans Acquisition Editor: Kayla Dos Santos Editorial Project Manager: Sabrina Webber Production Project Manager: Debasish Ghosh Cover Designer: Christian J. Bilbow Typeset by MPS Limited, Chennai, India

CONTENTS List of Contributors

ix

1. Fully-Depleted Silicon on Oxide Transistor and Compact Model

1

Chenming Hu 1.1 1.2 1.3 1.4 1.5

Silicon on Oxide and Pre-2010 SOI CMOS Transistor What Limits the Scaling of the Bulk and PDSOI CMOS Transistors? The Ultrathin-Body Concept and Ultrathin-Body Fully Depleted SOI Comparison of FDSOI with FinFET and Other Ultrathin-Body Transistors Compact Model—The Bridge Between FDSOI Device/Technology and IC Design References

2. Core Model for Independent Multigate MOSFETs

1 3 5 9 10 13

15

Juan Pablo Duarte, Sourabh Khandelwal, Huan-Lin Chang, Yen-Kai Lin, Pragya Kushwaha, Yogesh Singh Chauhan and Chenming Hu 2.1 Introduction 2.2 Independent Multigate MOSFETs 2.3 Core Model 2.4 Core Model Analytical Solution 2.5 Drain Current Model 2.6 Terminal Charge Model References

3. Channel Current Model With Real Device Effects in BSIM-IMG

15 16 18 26 28 30 33

35

Sourabh Khandelwal 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

Introduction Vertical Field Dependence of Carrier Mobility Threshold Voltage Drain Saturation Voltage Quantum Mechanical Effects Lateral Nonuniform Doping Model Output Conductance Model Velocity Saturation Effect

35 35 39 51 56 57 57 59

v

vi

Contents

3.9 Series Resistance Model 3.10 Channel Current Expression References

4. Leakage Current and Thermal Effects

60 62 62

65

Sourabh Khandelwal, Pragya Kushwaha 4.1 Leakage Currents and Their Modeling 4.2 Thermal Effects and Their Modeling References

5. Model for Terminal Charges and Capacitances in BSIM-IMG

65 72 86

89

Sourabh Khandelwal 5.1 Introduction 5.2 Capacitance Calculation From Terminal Charges 5.3 Intrinsic Terminal Charge Model in BSIM-IMG 5.4 Modeling the Impact of Real Device Effects on Terminal Charges 5.5 Extrinsic Capacitance Model in BSIM-IMG References

6. Parameter Extraction With BSIM-IMG Compact Model

89 90 93 98 102 105

107

Harshit Agarwal 6.1 Background 6.2 Extraction of Large-Sized Device Parameters 6.3 Short-Channel Device Extraction and Length Scaling 6.4 Leakage Current Extraction 6.5 Extraction of Temperature Dependence Parameters References

7. Testing BSIM-IMG Model Quality

107 109 114 116 120 123

125

Harshit Agarwal 7.1 Symmetry Tests 7.2 Weak and Strong Inversion Test 7.3 Test for Self-Heating Effect 7.4 Model Validation With Germanium on Insulator FD-SOI Transistor References

125 130 134 136 143

Contents

8. High-Frequency and Noise Models in BSIM-IMG

vii

145

Pragya Kushwaha and Yogesh Singh Chauhan 8.1 Radio-Frequency Characterization 8.2 Radio-Frequency Modeling and Parameter Extraction 8.3 Noise Models 8.4 Thermal Noise Characterization 8.5 Model Validation 8.6 Induced Gate Thermal Noise Model 8.7 Appendix References Index

146 150 159 166 171 179 190 193 201

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LIST OF CONTRIBUTORS Harshit Agarwal

Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, United States Huan-Lin Chang

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States Yogesh Singh Chauhan

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States; Associate Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India Juan Pablo Duarte

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States Chenming Hu

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States; Professor of the Graduate School, University of California, Berkeley, CA, United States Sourabh Khandelwal

Macquarie University, Macquarie Park, New South Wales, Australia; Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States; Research Faculty, University of South Florida, Tampa, FL, United States Pragya Kushwaha

Postdoctoral Researcher, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, United States Yen-Kai Lin

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States

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CHAPTER 1

Fully-Depleted Silicon on Oxide Transistor and Compact Model Chenming Hu Professor of the Graduate School, University of California, Berkeley, CA, United States

1.1 SILICON ON OXIDE AND PRE-2010 SOI CMOS TRANSISTOR Silicon on oxide (SOI) refers to a special type of silicon substrates (wafers) that IC manufacturers purchase from a few SOI wafer manufacturers. (The simple silicon wafer is sometimes called the “bulk” silicon wafer to distinguish it from SOI.) An SOI wafer consists of a thick Si substrate that provides mechanical rigidity, a buried oxide (typically 10
200 nm thick), and a second top silicon layer (10
100 nm thick). The transistors and circuits are fabricated in the top Si layer, and its quality and uniformity is of the ultimate importance. Sometimes, the term SOI is used to refer to the top silicon film itself as well as the film/oxide/substrate combination. Fig. 1.1 shows the steps of making an SOI wafer (Celler, George, and Michael Wolf. “Smart Cut A Guide to the Technology, the Process, the Products,” SOITEC. July 2003). Step 1 is to implant hydrogen into a silicon wafer that has a thin SiO2 film at the surface. The hydrogen concentration peaks at a distance D below the surface. Step 2 is to place the first wafer, upside down, over a second plain wafer. The two wafers adhere to each other by the chemical bonding force. A low-temperature annealing causes the two wafers to fuse together. Step 3 is to apply another annealing step that causes the implanted hydrogen to coalesce and form many tiny hydrogen bubbles at depth D. This creates sufficient mechanical stress to break the wafer at that plane. The final step, Step 4, is to polish the surface. Now the SOI wafer is ready for use. The Si film is of high quality and suitable for IC manufacturing. Fig. 1.2 shows the cross-sectional SEMs of two SOI transistors. Before 2010 SOI complementary metal-oxide-semiconductor (CMOS) employed SOI wafers with relatively thick ( . 30 nm) and relatively heavily

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00001-7

© 2019 Elsevier Ltd. All rights reserved.

1

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 1.1 Steps of making an SOI wafer.

Figure 1.2 Cross section of two SOI transistors. The lower structures are the transistors and contacts. The upper structures are the interconnect lines and vias.

doped silicon film. The combination of the Si film thickness and doping makes the depletion layer under that transistor channel thinner than the Si film thickness. This condition is called partial depletion, and the technology is known as partially depleted SOI (PDSOI). The alternative, a technology

Fully-Depleted Silicon on Oxide Transistor and Compact Model

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employing a thinner and lightly doped (or undoped) Si film, is known as fully depleted SOI (FDSOI) because the film is fully depleted under the transistor channel. It is interesting to note that the PDSOI designation was proudly highlighted by the SOI CMOS manufacturers in the 15 years prior to 2010 because it was known that FDSOI had worse short-channel effects [1] than PDSOI due to the elimination of the beneficial background plane effect provided by the undepleted body [2]. Today’s understanding is exactly the opposite—FDSOI provides superb short-channel behaviors. What changed the understanding is part of the story that this chapter will tell. A PDSOI transistor is basically identical to a bulk transistor except that it is fabricated in a silicon island surrounded by oxide on the bottom and on the four sides. It can be scaled to the same gate length as the bulk transistor. However, it provides faster circuit speeds because the source/drain bottom to body junction capacitance is eliminated as the source/drain diffusion regions extend vertically to the buried oxide. Another source of speed advantage is that the SOI transistor has less body effect (its threshold voltage does not raise as much as in bulk transistor when the source voltage rises). Because the SOI transistor is in a silicon island, its body (the silicon above the buried oxide and bounded by oxide trench isolation on two sides and by source/drain junctions on the two other sides) is electrically floating, not grounded as in a bulk transistor. The potential of the floating body can float up and down with the source voltage, so the source to body voltage, Vbg, is reduced in comparison to bulk transistor. Body effect reduces the on-state current of the transistors that are stacked in series in a multiple fan-in logic gates. Less body effect means faster logic gates. These benefits over the bulk transistor are retained in the post-2010 FDSOI, which also allows scaling beyond the limit of bulk transistor as explained in the next sections.

1.2 WHAT LIMITS THE SCALING OF THE BULK AND PDSOI CMOS TRANSISTORS? The continuing reduction of transistor and circuit sizes has led to steady improvements in the cost, speed, and power consumption of integrated circuits. Another part of the semiconductor industry’s formula for success has been keeping changes incremental, not drastic. The planar bulk metaloxide-semiconductor transistor (MOSFET) served the electronics industry well for 40 years through 2010. Aggressive engineering had managed to

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

reduce the transistor gate length, gate oxide thickness, etc. again and again without changing the transistor’s basic structure. The widely accepted transistor scaling rules held that the transistor gate length scaling would end when gate oxide thickness, the source/drain junction depth, or channel doping concentration could not be scaled any more. By the end of the 1990s, it was clear to all that all those three technology parameters would end and prevent COMS scaling from going beyond 30 nm. It is now known that none of the three parameters would prevent the achievement of single-digit-nm MOSFET with good short-channel behaviors—good subthreshold swing, low Vt sensitivity to Lg and Vd, and low leakage current. What was missed earlier was the supreme importance of the transistor body thickness. Fig. 1.3 explains the root cause of the escalating short-channel problem in the 20th-century MOSFETs [3]. A transistor is turned on and off when Vg lowers and raises the potential barrier between the channel and the source through the gate-to-channel capacitance, Cg. In an ideal transistor the channel potential is only controlled by Vg through Cg. In a short-channel transistor the channel potential is also subject to the influence of Vd through Cd. When Lg is large, Cd is much smaller than Cg, and the drain voltage does not compete with Vg as the sole controlling voltage. As Lg decreases, Cd increases, and Vd can act as a second gate in that it has control over the channel just like a gate. In extreme cases, Vg has less control than Vd, and the transistor can be turned on by Vd alone without Vg and log (Id) versus Vg would be a very flat line. Before reaching that extreme, we get increasingly worse subthreshold swing and Vt sensitivity to Vd and Lg, all leading to large leakage current and power consumption. The solution that worked well in the 20th century was to increase Cg by reducing the gate oxide thickness in proportion to Lg.

Figure 1.3 With decreasing L, rising Cd allows Vd to control the channel potential (lower figure) just as Vg [3]. Scaling the gate oxide thickness was a good solution for this problem in the 20th century.

Fully-Depleted Silicon on Oxide Transistor and Compact Model

5

Figure 1.4 With very short Lg, even a B0 nm thin gate dielectric cannot ensure that the gate is closer to (and thus have more control over) the leakage current than the drain because the leakage current paths can be several nanometers below the interface [3].

However, bulk MOSFET Lg scaling would not have continued even if an ideal “zero thickness” dielectric were available. Fig. 1.4 shows that the source to drain leakage current does not have to flow along the silicon-dielectric interface. Leakage paths nanometers below the interface, illustrated in Fig. 1.4, are more problematic than the surface leakage path because they are separated from the gate electrode by a large distance even if the gate oxide were 0 nm thin. In other words the gate and Vg have only weak control over the potential barrier along these subinterface paths. Therefore the imaginary 0 nm gate oxide would not have helped much with transistor scaling.

1.3 THE ULTRATHIN-BODY CONCEPT AND ULTRATHINBODY FULLY DEPLETED SOI Based on the understanding of the root cause, researchers at UC Berkeley proposed an ultrathin-body (UTB) scaling concept and two structures that implement the concept to US government’s DARPA (Defense Advanced Research Project Agency) in response to its request for proposal for sub25 nm switching devices in 1996. The two proposed thin-body implementations were UTB (FD)SOI and FinFET. By 2000 we successfully demonstrated both implementations and showed that they both can achieve excellent short-channel leakage current [4,5]. By 2002 the International Technology Roadmap of Semiconductors listed these two transistor structures as the only successors to the bulk planar transistor. Today all sub-20 nm CMOS technologies are based on these two transistor structures. This chapter will focus on the FDSOI. Fig. 1.5 illustrates a generic UTB MOSFET. The deepest possible leakage path is at the bottom of the thin body. There are no leakage paths far from the gate like those shown in Fig. 1.4—if the body is thin enough. The bottom of the body (the worst leakage path) is electrostatically

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 1.5 Top: A sufficiently thin Si body eliminates the leakage paths that are far from the gate in Fig. 1.4. Therefore the gate (Vg) dominates over the drain (Vd) in determining the leakage current [3].

Figure 1.6 The 25 nm Lg FDSOI has very poor or excellent subthreshold swing and Ioff depending solely on the body thickness. All three devices are FDSOI transistors with undoped body and 1.5 nm gate oxide [5]. Only UTB FDSOI has excellent swing and leakage current. FDSOI, Fully depleted SOI; UTB, ultrathin body.

separated from the gate by the sum of the body thickness, Tsi, and Tox (εsi/εox). When Lg is equal to twice this sum, the drain and the gate are at equal electrical distance from the midpoint between source and drain at the bottom of the body. Therefore the drain and the gate have roughly equal electrostatic control over the leakage. So, to ensure that the gate has the dominant control of the leakage over the drain, Tsi must be significantly less than Lg/2, say Lg/4 [5]. The UTB concept leads to a new scaling rule: while Tox (εsi/εox) is saturating at 0.5 nm, Lg can be reduced as long as Tsi can be reduced to satisfy.
 Lg εsi Tsi 1 Tox , (1.1) εox 4 Fig. 1.6 shows the cross section of an FDSOI with 25 nm Lg. It also shows the simulated Id versus Vg for three different Tsi. In all three cases the undoped body is fully depleted. The top curve is for Tsi 5 8 nm, and the swing is poor, and the leakage is unacceptable. The middle curve is for Tsi 5 6 nm, and the swing is better and Ioff is about 100 3 lower than the 8 nm body device. The bottom curve is for Tsi 5 4 nm. In this case, Ioff is superbly low, about another 100 3 lower than the 6 nm body case. Clearly, we are looking at a new regime of SOI MOSFET. In this UTB

Fully-Depleted Silicon on Oxide Transistor and Compact Model

7

regime, every 1 nm reduction of body thickness can reduce Ioff by an order of magnitude. Therefore the structure is called UTB-SOI transistor [5]. The UTB is the cause of the superb behavior of the short-channel transistor. There is no cause
effect relationship between full depletion and good short-channel behaviors of SOI MOSFETs. Rather, both are the results of the UTB. When the body is ultrathin, it is naturally fully depleted. But even a 20-nm undoped body would be fully depleted, and its leakage would be much worse than the Tsi 5 8 nm top curve in Fig. 1.6 and worse than a PDSOI (or bulk) MOSFET [1] due to the loss of the beneficial background plane effect provided by the undepleted body [2] as mentioned in the Section 1.1. Fig. 1.7 further explains the UTB concept. Start with the right most plot. It shows the cross section of an FDSOI transistor with 10 nm thin undoped and fully depleted body. Above the body are the yellow gate oxide (1.5 nm) and the green gate electrode. The colored contours show the leakage current density at Vg 5 0 V and Vd 5 0.75 V. The color bar at the upper right corner shows that the current density in a red area is very high 106 A/cm2. It is 10 3 less in the brown areas, 1000 3 less in the green areas, and 1,00,000 times less in the blue areas. In the 10 nm

Figure 1.7 Contour plots of the leakage current density of three FDSOI transistors that are identical except for the silicon body thickness. All three bodies are undoped and fully depleted. The highest leakage current density in the 10 nm Tsi device is 106 A/cm2, and it is 10 A/cm2 in the 5 nm Tsi device. FDSOI, Fully depleted SOI.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Tsi plot the highest leakage current density (red area) is present at the bottom of the silicon film, farthest from the gate with the weakest electrostatic control by the gate, as expected. Right under the gate oxide, the leakage current density is orders of magnitude lower because the location is close to the gate, and the gate control is strong. In other words the electrons flow from the source electrode downward to the bottom of the silicon film, turn sideways, and then upward to the drain electrode. The high leakage current (due to the red area) is clearly unacceptable. What can one do? One can make the Si film thinner, say 7.5 nm thin as in the middle plot of Fig. 1.7. There, the worst leakage current density is again found at the bottom of the silicon film, but the current density is B100 3 lower (yellow). The left most plot in Fig. 1.7 shows that reducing Tsi further to 5 nm leaves only blue areas with 1,00,000 less leakage current than the red area in the 10 nm Tsi device. This explains why every 1 nm reduction in Tsi reduces Ioff by about 10 3 in the UTB regime in Fig. 1.6. Fig. 1.8 shows the scanning electron microscope (SEM) image of the cross section of a UTB FDSOI [6]. It employed 3 nm ultrathin undoped body, 2.6 nm gate oxide, and TiN gate. TiN was chosen for Vt adjustment. UTB FDSOI transistors do not need heavy channel doping or shallow junction technology for suppressing the short-channel effects. Channel doping was needed in bulk, and PDSOI transistors suppress the leakage current in regions far from the gate and to adjust the threshold voltage. Suppression of leakage current is well addressed by the UTB concept. The Vt adjustment function can be performed with the gate metal

Figure 1.8 UTB FDSOI employing 3 nm ultrathin undoped body, 2.6 nm gate oxide and 3 nm TiN gate for Vt adjustment [6]. FDSOI, Fully depleted SOI; UTB, ultrathin body.

Fully-Depleted Silicon on Oxide Transistor and Compact Model

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work functions of the front gate and the back gate (N 1 or P 1 Si well in the substrate). Eliminating doping fundamentally solved the problem of device Vt variation due to random dopant fluctuation. Channel carrier mobility and junction leakage are significantly improved. In addition, undoped body reduces the electric field normal to the semiconductor and oxide interface. This improves the temperature bias instability [negativebias-temperature instability (NBTI) and positive-bias-temperature instability (PBTI)], the gate dielectric tunneling leakage, and dielectric wear out. A highly valuable feature of FDSOI is that its threshold voltage can be adjusted with a back-gate voltage [7]. This is discussed further in the Section 1.4.

1.4 COMPARISON OF FDSOI WITH FINFET AND OTHER ULTRATHIN-BODY TRANSISTORS While the UC Berkeley researchers demonstrated two manufacturable thin-body short-channel transistors, FinFET and UTB FDSOI, at about the same time [4,5], FinFET received more industry development effort (and eventually earlier adoption for mass production in 2011) because UTB-SOI wafers with 10% body thickness (0.5 nm) variation were not available. Around 2010 Soitec succeeded in producing SOI wafers that met the production requirements. Today several IC manufacturers, including GlobalFoundries, Samsung, and ST Microelectronics, are producing FDSOI ICs. Compared to other thin-body transistor structures, such as thin fin, sheet and wire, FDSOI technology does not provide the highest speed. However, FDSOI has several important advantages. Its parasitic capacitances are lower than that of FinFET because of the latter’s tall and dense structure. The lower capacitances lead to higher Ft and Fmax, two critical parameters for radio frequency (RF) applications. With the expanding market of low-power high frequency RF applications, this is a significant advantage. For digital applications, FDSOI has the unique ability to naturally allow Vt adjustment by the back-gate bias [7]. Fig. 1.9 shows that doped N or P well in the silicon substrate can serve as the back gates of the transistors. The buried oxide, in green color, serves as the back-gate dielectric. To adjust the threshold voltages of the two transistors the wells may be separately biased at different voltages to obtain the desired Vt’s, and the well bias voltages may be either positive or negative depending on the

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 1.9 FDSOI’s silicon substrate can be doped and contacted to serve as the back gates. The buried oxide (in green) serves as the back-gate dielectric. The wells may be separately biased at different voltages to obtain the desired Vt’s, and the well bias voltages may be either positive or negative depending on the well doping type. FDSOI, Fully depleted SOI. Courtesy of GlobalFoundries, Inc.

well doping type. This is similar to but much more effective than the well biasing scheme of bulk CMOS technology. Even short-channel transistor Vt can be changed up or down by a good fraction a volt and reduce Ioff by several orders of magnitude, for example. This feature cannot only reduce the standby current of a processor when it is inactive, it can dynamically increase the processor speed when the application demands the speed. Therefore FDSOI may be favored over other thin-body technologies for some low-power applications. What is the prospect of long-term scaling? Like all UTB technologies, FDSOI scaling will eventually be limited by the achievable body thickness or diameter. For FinFET, for example, the equivalent of Eq. (1.1) is:
 Lg Fsi εsi 1 Tox (1.2) , 2 εox 4 where Fsi is the fin thickness. The worst leakage path is the middle of the fin, separated from the gate, electrostatically, by Fsi/2 1 Tox (εsi/εox). While it is impossible to predict how thin SOI silicon films can be mass produced, an intriguing long-term alternative UTB is two-dimensional semiconductors. Two-dimensional semiconductors such as graphene, WSe2 or MoS2 films, may provide the ultimate UTB for UTB transistors.

1.5 COMPACT MODEL—THE BRIDGE BETWEEN FDSOI DEVICE/TECHNOLOGY AND IC DESIGN Designing FDSOI-based integrated circuits requires a FDSOI model for circuit simulation. In order to design ICs, design teams need two things

Fully-Depleted Silicon on Oxide Transistor and Compact Model

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provided by the wafer fabrication partners—design rules and transistor SPICE model. SPICE model is also known as the compact model. Design rules are created by each manufacturing company. The SPICE model, which is a set of long equations that are capable of reproducing the very complex transistor characteristics accurately and fast for computer simulation of complex circuits, is likely a free industry standard model developed and maintained by a university. The BSIM MOSFET (B stands for Berkeley) was chosen in 1996 as the very first industry standard compact model [8]. Researchers at UC Berkeley have continued to develop the model to serve over 12 generations of CMOS technologies from 250 to 5 nm nodes and covering bulk, PDSOI, FinFET, and FDSOI technologies. The cumulative sales of the ICs designed with the help of BSIM easily exceed $1T. UC Berkeley and its researchers provide the BSIM models to the world, royalty free. The BSIM FDSOI model is called BSIM-IMG. IMG stands for independent-multigate, referring to the front and back gates that are biased independently. Fig. 1.10 illustrates the role of a compact model in the semiconductor industry. The FDSOI compact model, for example, translates the physical concepts of the transistor as well as the accurate and detailed electrical behaviors of the transistor into language (model) that computers can understand and use to simulate large circuits. Using BSIM-IMG, cell libraries and IPs and computer-aided IC design tools for FDSOI can be developed. One important attribute of a good compact model is that it

Figure 1.10 Complex device and manufacturing technologies determine the electrical behaviors of a transistor. Compact model captures this information and makes it available for IC and product design.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

must be computationally and storage-wise efficient. The most efficient models today employ mathematical functions. Finite-element simulation and table-look-up approaches, for example, are not competitive. A good compact model must also be very accurate to avoid design respins that are expensive in cost and time-to-market. “First silicon success” has become more common in the past twenty years in spite of the rising complexities of technology and circuits. That is partly due to the improved accuracy of the compact models. If the model does not describe the transistor characteristics accurately, no amount of design effort can guarantee design success. How does a set of mathematical equations achieve excellent accuracy from pA to mA, from DC to THz, and over a range of transistor channel length and width, and temperature? Fig. 1.11 provides some insight. An FDSOI compact model consists of a core model and dozens of “real device phenomena” models. The core model describes the current-voltage (IV) and capacitance-voltage (CV) characteristics of a simple transistor—long channel, abrupt junctions, uniform doping, to some degree of accuracy. The core model often requires solving a complex transcendental equation using a few iterations. To keep the maximum number of iterations required to reach convergence to a very small number, one needs to find an excellent approximate analytical solution as the initial guess. Good insight into the device physics is needed to find such a good approximate solution. The core model of FDSOI, which has two channels that can hold different densities of mobile carriers,

Figure 1.11 A compact model consists of a core IV and CV model and many “realdevice-phenomenon” models. The latter are responsible for the extraordinary accuracy of the compact model.

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is much more complex than the core models of all other MOSFETs, which have only one uniform channel. Surrounding the core model in Fig. 1.11 are some examples of the real-device phenomena of the transistor. This part of the compact model is responsible for the extraordinary accuracy that can be achieved. Each of the many physical phenomena of the device, too complex for the core model to include, is separately modeled with analytical equations. Good real-device-phenomenon models start with accurate physical understanding of the phenomenon and developed with accuracy and computational efficiency in mind. The BSIM-IMG FDSOI compact model not only has a new core model but also has models for many new phenomena created by the strong back-gate control or back channel inversion. Most of the other real-device-phenomenon models also required significant development work on account of the back gate’s presence. The FDSOI real-device-phenomena model equations contain many adjustable parameters. The core model has few parameters. Engineers, with the help of automated parameter extraction tools, choose the parameter values so that the model is customized to accurately reproduce the behaviors of the transistors of a particular technology of a particular IC manufacturing company. The BSIM-IMG model equations, together with the model parameters extracted specifically, for example, for GlobalFoundries 22FDX technology, become the transistor compact model of that FDSOI technology.

REFERENCES [1] L.T. Su, et al., Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET’s, IEEE Electron Device Lett. 15 (1994) 183. [2] C.H. Wann, et al., A comparative study of advanced MOSFET concepts, IEEE Trans. Electron Devices 43 (1996) 1742. [3] C. Hu, Modern Semiconductor Devices for Integrated Circuits, Pearson/Prentice Hall, 2010. Ch. 7. [4] X. Huang, et al., Sub 50-nm FinFET: PMOS, IEDM Technical Digest (1999) 67. [5] Y.-K. Choi, et al., Ultrathin-body SOI MOSFET for deep-sub-tenth micron era, IEEE Electron Device Lett. 21 (2000) 254. [6] Y.-K. Choi, et al., Ultra-thin body PMOSFETs with selectively deposited Ge source/ drain, VLSI Tech. Symposium, 2001, p. 19. [7] P.-S. Wong, et al., Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length generation, International Electron Devices Meeting, 1998, p. 407. [8] J.H. Huang, Z.H. Liu, M.C. Jeng, K. Hui, M. Chan, P.K. KO, et al., BSIM3 Manual, University of California, Berkeley, CA, 1993.

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CHAPTER 2

Core Model for Independent Multigate MOSFETs Juan Pablo Duarte1, Sourabh Khandelwal2, Huan-Lin Chang1, Yen-Kai Lin1, Pragya Kushwaha1, Yogesh Singh Chauhan1,3 and Chenming Hu1 1

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States 2 Postdoctoral Researcher, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, United States 3 Associate Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India

2.1 INTRODUCTION Developing a compact model for independent multigate MOSFETs is challenging due to the nature of the Poisson’s solution with front- and back-gate boundary conditions [1]. It is well known that the Poisson’s solution for these devices [1] lies in trigonometric and hyperbolic domains, making the desired numerical robustness extremely difficult; however, fast speed, numerical robust, and accuracy are fundamental characteristics of compact models for circuit design and technology development. As shown in Fig. 2.1, an industry compact model must be able to calculate terminal (drain, source, front/back gate) currents and charges, which are then utilized by circuit simulator engines to solve a complete circuit under various analyses such as DC, AC, and transient. This chapter presents the fundamentals of the BSIM-IMG compact model for UTBSOI technologies and discusses all the important features of this model, which demonstrates the readiness of BSIM-IMG model for developing process-design kits. Compact model Dimensions, boundary conditions, materials

Charge model

Current model

Poisson’s equation obtaining charge

Transport equation using charge model

Charges Currents

Figure 2.1 Simplified flow of a compact model development. Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00002-9

© 2019 Elsevier Ltd. All rights reserved.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

2.2 INDEPENDENT MULTIGATE MOSFETS Fig. 2.2 shows a three-dimensional schematic of UTBSOI, similar to that demonstrated in Ref. [2]. It has a traditional planar structure similar to conventional bulk MOSFETs, with source, drain, and gate contacts in the top; however, the silicon channel layer is thin (fin) and is placed between front/back insulators, where the additional back gate serves as a potential modulator of the silicon fin. This additional tuning feature can be used in several contexts, for example, as a threshold voltage modulation or device variability control [2,3]. Figs. 2.3 and 2.4 show schematics of structural and energy band crosssectional view of a UTBSOI, respectively, where it is easy to appreciate front and back gates, silicon
insulator layer (or fin), and front and back insulators (EOTf and EOTb, respectively). Fig. 2.4 represents the ideal structure taken as a reference for the derivation of the core model; this model must be able to capture potential in the front and back silicon
insulator interfaces, thus making possible the calculation of back/front charges and mobile charge in the channel. In a different manner compared to conventional FinFETs, front- and backgate potentials can produce different set of bias conditions as shown in Figs. 2.5
2.8. Fig. 2.5 shows the first case, where the channel is in the subthreshold condition and is fully depleted; this is accomplished when

Figure 2.2 Three-dimensional schematic of an ultrathin-body silicon-on-insulator device.

Core Model for Independent Multigate MOSFETs

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Figure 2.3 One-dimensional cross-sectional view of a UTBSOI with independent potential control of the channel from front and back gates.

Figure 2.4 One-dimensional cross-sectional view of the energy diagram of a UTBSOI. Two different boundary conditions define the energy shape in the semiconductor channel.

Figure 2.5 One-dimensional cross-sectional view of a UTBSOI where channel is in the subthreshold condition.

Figure 2.6 One-dimensional cross-sectional view of a UTBSOI where only front surface is in strong inversion condition.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 2.7 One-dimensional cross-sectional view of a UTBSOI where only back surface is in strong inversion condition.

Figure 2.8 One-dimensional cross-sectional view of a UTBSOI where back and front surfaces are in strong inversion condition.

back and front channels are turned off due to the low potential at both gates. The second bias case is when the front potential is large enough for inversion but back is not; Fig. 2.6 shows that there is an inversion in the front gate, but back gate is still off and in the subthreshold condition. The third case, Fig. 2.7, shows the case where front potential is not large enough to produce front charge inversion but the back gate can induce inversion in the back channel. Finally, Fig. 2.8 shows the last case where both, front and back, channels are in inversion condition due to the large potential at both gates. All four configurations must be captured in an accurate and robust manner by a core compact model so it can be used for circuit simulation and design. In the following sections, the core compact model used in BSIM-IMG is described in detail.

2.3 CORE MODEL As described earlier, BSIM-IMG has two options for the core model of fully depleted silicon on oxide (FDSOI) devices: (1) fast core model and (2) extended range model. Depending on their requirements, users can select among these. This section describes both these options in detail.

Core Model for Independent Multigate MOSFETs

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2.3.1 Fast Core Model The core model is derived by solving device electrostatics. This is based on two-dimensional FDSOI MOSFET cross section as shown in Fig. 2.3. A silicon channel of thickness Tsi is sandwiched between the front and the back gate with insulator thicknesses Tox1 and Tox2, respectively, with Eox1 and Eox2 as the respective dielectric constants. The front and the back gates have different work functions (Φg1 and Φg1, respectively). The energy band diagram along the cut A 2 Á is shown in Fig. 2.4. The channel electrostatics is controlled by both the front and the back gates independently. To calculate the active charge, we need to calculate the surface potential. This is calculated by solving the one-dimensional Poisson’s equation: @2 ψ ρðψÞ qNc ððψ2Vch Þ=Vth Þ 52 5 e @x2 εch εch

(2.1)

where ψ is the electrostatic potential in the fin, q is the magnitude of the electronic charge, Nc is the conduction band density of states, εch is the dielectric constant of the channel (fin), Vth is the thermal voltage given by kBT/q, where kB and T are the Boltzmann constant and the temperature, respectively; Vch is the quasi-Fermi potential of the channel (Vch(0) 5 Vs and Vch(L) 5 Vd). The charge contribution of ionized dopants is neglected since the body is lightly doped in FDSOI devices. The continuity of the displacement field at the front and the back interfaces sets up the following boundary conditions at the two interfaces, respectively: Cox1 ðVfg 2 Δφ1 2 ψs1 Þ 5 Esi Es1 (2.2) Cox2 ðVbg 2 Δφ2 2 ψs2 Þ 5 Esi Es2

(2.3)

where Cox1 5 Eox/Tox1 is the front-gate oxide capacitance with Eox and Tox1 as the dielectric permittivity and oxide thickness for the front gate, respectively, and Δφ1 is the work function difference between the front gate and n 1 source junction. The relation between Es1 and Es2 obtained after integration of the Poisson’s equation in the silicon body is
 2qNc Vth ψs1 2 Vch ψs2 2 Vch 2 2 Es1 2 Es2 5 (2.4) exp 2 exp ESi Vth Vth

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

After combining Eqs. (2.2)
(2.4), a relation between front- and backsurface potential can be obtained:

 Vfg 2Δφ1 2ψs1 2 Vbg 2Δφ2 2ψs2 2 Cox1 2 Cox2 ESi ESi (2.5)   2qNc Vth ψs1 2 Vch ψs2 2 Vch 5 exp 2 exp ESi Vth Vth The function in Eq. (2.5) is an implicit expression of two unknown variables ψs1 and ψs2. A relationship between ψs1 and ψs2 can be obtained by assuming the back gate to be in weak inversion and equating the displacement vector at the back interface: ψs2 5

Csi Cox2 ψs1 1 ðVbg 2 Δφ2 Þ CSi 1 Cox2 CSi 1 Cox2

(2.6)

where CSi 5 ESi/TSi with TSi as the silicon body thickness. This is the key point where the fast core model is different from the extended range core model accurate in all regions of device operation. In the fast core model, we assume that that the back interface can only go to weak inversion or depletion and this assumption helps to develop a computationally efficient core model. By combining Eqs. (2.2), (2.3), and (2.6) in Eq. (2.5), we get

2 Vfg 2ψs1 2 Vbg 2ψs1 Cox1 2 ESi TSi 1ðESi =Eox ÞTox2 (2.7)   ðαSi 2 1Þψs1 1 αox Vbg 2qNc Vth ψs1 2 Vch 5 exp 1 2 exp ESi Vth Vth where Vfg 5 Vfg 2 Δφ1 ; Vbg 5 Vbg 2 Δφ2 ; αSi 5 CSi =ðCSi 1 Cox2 Þ, and αox 5 Cox2/(CSi 1 Cox2). The implicit function Eq. (2.7) resembles the implicit relation for surface potential in bulk MOSFETs, but it is more complicated in this case because of the additional terms due to the back gate. In fast core model, an analytical solution for Eq. (2.7) is developed, which enables the calculation of all the other important quantities, and subsequently derive the drain current model. The method to solve Eq. (2.7) is described in the following section. 2.3.1.1 Calculation of Surface Potential in Fast Core Model The implicit relation Eq. (2.7) in ψs1 is expressed in a mathematically more convenient form as

Core Model for Independent Multigate MOSFETs

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x 2 x  fg 2 ðBðxbg 2xÞÞ2 5 expðx 2 xn Þ 2 expðαSi x 1 αox xbg 2 xn Þ (2.8) G pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  where xfg=bg 5 Vfg=bg =Vth , G 5 Tox1 =Eox 2qNc Esi =Vth , B 5 1=ðTSi 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ESi =Eox Tox2 ÞÞ ESi Vth =2qNc , x 5 ψs1/Vth, and xn 5 Vch/Vth. The solution of the function f(x) in Eq. (2.7) for x is computed in the following manner: 1. Compute the solution of Eq. (2.8) x0, by assuming the electric field Es2 as Es2 5

Vfg 2 Vbg ESi =Eox ðTox1 1 Tox2 Þ 1 TSi

(2.9)

and neglecting the second exponent term of the charge at the back gate. This will change the second term on the left-hand side of Eq. (2.8) from being a function of x to an expression only involving xfg and xbg with constants. Following approach is used to calculate x0. 2. Next, we compute the quantities ξ 1, ξ2, f, f 0 , f v, and f vv defined by (2.10)

ξ2 5 expðαSi x0 1 αox xbg 2 xn Þ

(2.11)

x 2x 2 fg 0 2 ðBðxbg 2x0 ÞÞ2 2 ξ1 1 ξ 2 G

(2.12)

22 ðxfg 2 x0 Þ 1 2B2 ðxbg 2 x0 Þ 2 ξ 1 1 αSi ξ 2 G2

(2.13)

f5 f05

ξ1 5 expðx0 2 xn Þ

fv5

2 2 2B2 2 ξ 1 1 α2Si ξ 2 G2

(2.14)

f 0 v 5 2 ξ 1 1 α3Si ξ 2

(2.15)

3. Then we calculate x1 using the following approach:
 f f f v f 2 ð3f v2 2 f 0 f 0 vÞ x1 5 x0 2 0 1 1 02 1 f 2f 6f 04

(2.16)

We recalculate Eqs. (2.10)
(2.15) once more using x1 as the input in place of x0 and finally obtain the output xsp1 from Eq. (2.16). This is done to improve the accuracy of the solution. Then ψs1 is simply given by ψs1 5 xsp1Vth. This solution of ψs1 is compared against the

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 2.9 Front-gate surface potential ψs1 from the numerical solution and the proposed model for different values of channel potentials. ψs1 is measured relative to the quasi-Fermi level at the source side. Vbg 5 0 V.

numerical solution in Fig. 2.9 for different values of the channel potential, and a good agreement between the two is found. We plot the absolute error between the proposed model and numerical solution for extended range of Vfg in Fig. 2.10. The maximum absolute error observed in the full range of Vfg is 0.9 nV. The calculated ψs1 is then used to find ψs2 using Eq. (2.6), Es1 using Eqs. (2.2), and Es2 using Eq. (2.3). From Gauss’s law the inversion charge Qinv is given by Qinv 5 ESi ðEs1 2 Es2 Þ (2.17) The evaluation in Eq. (2.17) involves the difference of two large quantities Es1 and Es2. In a weak inversion, this difference is expected to be small in value. This can cause problems as the accuracy of this calculation is governed by the precision limit of the simulator, which will be lower for calculations involving large numbers. To avoid this, we use Eq. (2.18) and calculate Qinv by ! 2qNc Vth ψs1 2 Vch exp Qinv 5 Es1 1 Es2 Vth !! (2.18) αox Vbg 1 ðαSi 2 1Þψs1 1 2 exp Vth

Core Model for Independent Multigate MOSFETs

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Figure 2.10 Absolute error between the numerical solution and the proposed model of ψs1 for extended range of Vfg. The maximum error observed is 0.9 nV. Vch 5 0, Vbg 5 0 V.

It can be seen that in Eq. (2.18), we avoid this precision limit issue that can cause convergence problems. This completes the calculation of ψs1, ψs2, and Qinv. These quantities are then used to derive the drain current and other important quantities as described in this book. The above described fast core model in BSIM-IMG compact model. The key assumption which allows simplification and development of fast core calculation is the assumption that back interface is in weak inversion or depletion and device does not reach a condition in which back side is in inversion. As a result, this model is less accurate for bias condition in which back side gets inverted. Nevertheless, FDSOI device is typically not used in the bias condition in which back interface is inverted and the simplifying assumption made here significantly improves the computational efficiency of the model. In the next section, core model accurate in all regions of device operation is discussed.

2.3.2 Extended Range Model There is an extensive amount of work related to the development of core compact model for UTBSOI devices. For example, the work presented in Ref. [1] represents a robust solution that simplifies the Poisson’s equation, with a single variable equation that can be solved for devices where front

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

inversion is the dominant component for the current. In Ref. [4], a compact model with three different solution regions was presented; it takes into account hyperbolic and trigonometric domains, having a difficult numerical challenge related to the mathematical implementation of the model to keep accuracy and track of the analytic solution. The work presented in Ref. [5] proposed a set of three equations that can be solved simultaneously to obtain the solution for back and front potentials. Based on the work of Ref. [5], Ref. [6] removed the extra unknown of Ref. [5], leading to a single variable compact model which can be used to obtain the potentials in UTBSOI devices. This paper proposes a robust core compact model based on the work of Ref. [6], which is used to obtain the mathematical equations to be solved, then using the results of Refs. [1,7], a robust algorithm is developed to be used in the core model of BSIM-IMG. The one-dimensional Poisson’s equation (neglecting channel doping) for the cross-sectional section of a UTBSOI device (Fig. 2.4) can be written in the following form: @2 ψ ρðψÞ qni ððψ2Vch Þ=ν T Þ 52 5 e 2 @x εch εch

(2.19)

where ψ is the electrostatic potential in the fin, q is the magnitude of the electronic charge, ni is the intrinsic carrier concentration, εch is the dielectric constant of the channel (fin), vT is the thermal voltage given by kBT/q, where kB and T are the Boltzmann constant and the temperature, respectively, Vch is the quasi-Fermi potential of the channel (Vch(0) 5 Vs and Vch(L) 5 Vd). The next step is to apply boundary conditions at each semiconductor
insulator interfaces. This is done using Gauss’s law boundary condition which gives two boundary conditions: εEOTf

Vgf 2 Vfbf 2 ψsf @ψs f 5 2 εch EOT f @x

(2.20)

Vgb 2 Vfbb 2 ψsb @ψ 5 εch sb EOTb @x

(2.21)

εEOTb

Note that the total charge in the channel can be expressed by the following formula: Qm 5 2 εch

@ψsf @ψ 1 εch sb @x @x

(2.22)

Core Model for Independent Multigate MOSFETs

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Table 2.1 Model variables. Variable Definition

xf, xb, vT ϕ f, ϕ b Cox,f, Cox,b, Cch

VGF 2 ΔΦf VGB 2 ΔΦb kT ; vT ; q vT φf φb vT ; vT εox;f εox;b εch EOTf ; EOTb ; Tcg

kf, kb, keq,f, keq,b

Cox;f Cch

A0

2qni εch Cch vT

qm

Qm vT Cch

(thermal voltage)

k

; CCox;b ; kf kb 1kkb f 1 kb ; kf kb 1 kf f 1 kb ch

Integrating once the Poisson’s equation with respect to potential and after variable normalization (Table 2.1), it is possible to obtain the following two expressions: α2 5 kf ðxf 2ϕf Þ2 2 A0 eϕf

(2.23)

α2 5 kb ðxb 2ϕb Þ2 2 A0 eϕb

(2.24)

The next step is to integrate the electric field using α and then using algebraic manipulations as in Ref. [6], obtaining the following equation: α  

 α coth kf xf 2 ϕf 1 kb xb 2 ϕb 2 (2.25) 

 1 kf kb xb 2 ϕb xf 2 ϕf 1 α2 5 0 The previous three equations form a system of three variables and three equations which can be solved to obtain back and front potentials. Note that if α2 , 0: coth, sinh-cot, sin. However, these equations can be combined into a single variable equation as follows [6]: α       

 kf xf 2 ϕf 1 kb xb 2 ϕb f ϕf 5 kf xf 2 ϕf 1 α coth 2 2 A0 eϕf 5 0 (2.26) with
2   α  α ϕb 5 ϕf 2 ln kf xf 2 ϕf 1 α coth 1 ln 2 sinhðα=2Þ

(2.27)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 2.11 Evaluation of f(ϕf) for different values of ϕf where an iteration example fell into a false solution.

Eq. (2.26) represents a single variable equation that must be solved for the condition f(ϕf) 5 0; thus for different values of ϕf, f must be minimized. The challenge relies on the hyperbolic and trigonometric nature of f for different values of ϕf . For example, Fig. 2.11 shows the evaluation of f(ϕf) for different values of ϕf. Note that for the hyperbolic region, there is a single minimum value (single solution); however, in the trigonometric region, there are several values of ϕf where f(ϕf)B0. This implies a challenging issue, because traditional iterative methods used in compact models, such as Newton’s method, may bring the solution to a false solution as shown in Fig. 2.11, producing discontinuities in the final compact model. Therefore in the following section, a method to limit the solution to valid regions is presented.

2.4 CORE MODEL ANALYTICAL SOLUTION An analytical solution for the derived core model from the previous section consists of two main parts. First, an initial guess that must be continuous and as close as possible to the final solution. The second part of the analytical solution consists of updates to the initial guess solution so the

Core Model for Independent Multigate MOSFETs

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accuracy is further refined. Fig. 2.1 represents a schematic of the analytical solution implemented in BSIM-IMG. The first step is to solve Eq. (2.28). Note that this work calls the solution of this equation as saturation potential. As shown in Fig. 2.11, it represents the maximum value of the front potential where the trigonometric region has a single solution. Knowing this value, it is possible to limit the analytical algorithm to a value lower than this maximum, avoiding false solutions. Eq. (2.28) can be simply solved using Newton’s method. 24π2 5 kf ðxf 2ϕf 2ϕf ;max Þ2 2 A0 eϕf ;max

(2.28)

Once ϕf,max is obtained, it is possible to obtain a very accurate initial guess by taking the minimum, in a smooth manner, of the ϕf,max value and the approximated value of the front potential in the subthreshold region, as obtained in Ref. [1].
 rEOTf ðxf 2 xb Þ ϕf ;guess 5 maxs (2.29) 1 xb ; ϕf ;max Tfin 1 rðEOTf 1 EOTb Þ Since the initial guess is very close to the final solution, only firstorder Newton updates are needed to improve the accuracy of the solution. In addition, in order to keep the final solution in valid regions, the update is smoothly limited to values lower than the saturation maximum potential obtained in Eq. (2.28).
 f ϕf ;max 2 ϕf ;n21 ϕf ;n 5 ϕf ;n21 2 mins 0 ; (2.30) f 2 with ϕf,0 5 ϕf,guess. Note that maxs and mins are smooth versions of max and min functions, respectively (Fig. 2.12). Fig. 2.13 shows the front potential and the channel charge obtained from the proposed compact model versus Technology Computer Aided Design (TCAD) simulations for different front- and back-gate potentials.

Figure 2.12 Schematic of the analytical solution.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 2.13 Front potential versus front-gate voltages for different back-gate biases obtained from compact model and TCAD simulations.

Once surface potentials are obtained, the total mobile charge is calculated using the mobile charge equation proposed in Ref. [7]: qm 5

kf ðxf 2 ϕf Þ 2 αcothðα=2Þ 1 2 ðα2 =sinhðα=2Þ2 Þðexpðϕf Þ=A0 Þ

(2.31)

Figs. 2.14 and 2.15 show the mobile charge versus front-gate voltage for various back-gate voltages. Charge is accurately calculated using Eq. (2.31) from subthreshold to strong inversion condition. Note that back inversion is captured as well for large back bias condition. The proposed model accurately describes the potential and charge in the channel; in addition, Fig. 2.16 shows the CFGFG capacitance versus front-gate voltage. These results show that the proposed compact model smoothly captures the back inversion effect for different back bias configurations.

2.5 DRAIN CURRENT MODEL The drain current model for independent-gate MOSFETs is well known and reported in Ref. [8]. It is based in the one-dimensional Poisson’s equation formulation, thus it is compatible with the core model derived for BSIM-IMG. The normalized current ids0 is then given by

Core Model for Independent Multigate MOSFETs

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Figure 2.14 Channel charge versus front-gate voltages for different back-gate biases obtained from compact model and TCAD simulations.

Figure 2.15 Mobile charge obtained from proposed front surface potential solution and TCAD for different VGB values (23, 21.5, 0, 1.5, and 3 V). EOTf 5 2.4 nm, EOTb 5 12 nm, Tch 5 12 nm, ΔΦf 5 2 39 mV, and ΔΦb 5 0.45 V.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 2.16 CFGFG capacitance versus front-gate voltage for different back-gate biases. Note that back inversion effects are accurately obtained by the compact model.

 ids0 5 2vT ðqfronts 2 qfrontd Þ 2

   q2frontd =cox1 2 q2fronts =cox1

2

q2backd =cox2 2 q2backs =cox2 1 2vT ðqbacks 2 qbackd Þ 2 2

(2.32)

where qfronts, qfrontd, qbacks, and qbackd are front charge at source, front charge at drain, back charge at source, and back charge at source, respectively. Each quantity is calculated using the core model and the back- and frontcharge definitions. Since core and drain current models are completed, additional real device effects are incorporated into the final model in BSIM-IMG. As explained in Ref. [9], several extra models are added to the core and drain current models, such as drain-induced barrier lowering, velocity saturation, short-channel effects, self-heating effect, mobility-field dependence, and substrate-depletion effect. Figs. 2.17 and 2.18 show simulations of BSIM-IMG model, with all real device models included versus measured data. The good accuracy demonstrates the capabilities of the model as an industry standard compact model.

2.6 TERMINAL CHARGE MODEL The inclusion of back-side inversion is a fundamental new feature in BSIM-IMG. Indeed, it is needed to obtain correct values of capacitances

Core Model for Independent Multigate MOSFETs

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Figure 2.17 BSIM-IMG model versus measured data for linear IDS 2 Vfg characteristics at different values of Vbg for a long-channel device [9].

Figure 2.18 BSIM-IMG model versus measured data for linear IDS 2 Vfg and gm 2 Vfg characteristics at different values of Vbg (0, 20.2, 20.5 V) for a long-channel device [9].

for cases where large forward bias is applied to back gate; for this core case, BSIM-IMG has a simple linear partition of the terminal charges: QFG 5

Qfront;D 1 Qfront;S 2

(2.33)

QBG 5

Qback;D 1 Qback;S 2

(2.34)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 2.19 New BSIM-IMG model versus TCAD data of front-gate capacitance at different values of VGB. Previous version of BSIM-IMG model [10] is plotted as reference. EOTf 5 1 nm, EOTb 5 20 nm, Tch 5 6 nm, ΔΦf5 2 39 mV, and ΔΦb 5 0.45 V. TCAD and BSIM-IMG model include real device effects, such as back-gate depletion, and quantum effects [10,11].

Figure 2.20 New BSIM-IMG model versus TCAD data of front-gate capacitance at different values of Tch. TCAD and BSIM-IMG model include real device effects, such as back-gate depletion, and quantum effects [10,11].

Core Model for Independent Multigate MOSFETs

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QD 5

2ðQfront;D 1 Qback;D Þ 1 Qfront;S 1 Qback;S 6

(2.35)

QS 5

Qfront;D 1 Qback;D 1 2ðQfront;S 1 Qback;S Þ 6

(2.36)

Fig. 2.19 shows results from the new model versus TCAD simulation data and older BSIM-IMG version. The new model is important for cases where back bias is larger, that is, when back-side inversion is present. In this case, back capacitance must be taken into account to obtain accurate front-gate capacitance values. Fig. 2.20 shows front-gate capacitance simulation of the proposed new model and TCAD data for different channel thickness. The model can accurately capture channel thickness dependence.

REFERENCES [1] D. Lu, Compact models for future generation CMOS, 2011. [2] Y. Choi, K. Asano, N. Lindert, V. Subramanian, T. King, J. Bokor, et al., Ultra-thin body SOI MOSFET for deep-sub-tenth micron era, Electron Devices Meeting, 1999. IEDM Technical Digest. International, IEEE, 1999, pp. 919
921. [3] V.P.-H. Hu, M.-L. Fan, P. Su, C.-T. Chuang, Threshold voltage design of UTB SOI SRAM with improved stability/variability for ultralow voltage near subthreshold operation, IEEE Trans. Nanotechnol. 12 (4) (2013) 524
531. [4] G. Dessai, G. Gildenblat, Solution space for the independent-gate asymmetric DGFET, Solid-State Electron. 54 (4) (2010) 382
384. [5] A. Ortiz-Conde, F.J. García-Sánchez, Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET, Solid-State Electron. 57 (1) (2011) 43
51. [6] T. Poiroux, O. Rozeau, S. Martinie, P. Scheer, S. Puget, M.A. Jaud, et al., UTSOI2: a complete physical compact model for UTBB and independent double gate MOSFETs, in: 2013 IEEE International Electron Devices Meeting, December 2013, pp. 12.4.1
12.4.4, ,https://doi.org/10.1109/IEDM.2013.6724616.. [7] T. Poiroux, O. Rozeau, P. Scheer, S. Martinie, M.A. Jaud, M. Minondo, et al., LetiUTSOI2.1: a compact model for UTBB-FDSOI technologies—Part I: Interface potentials analytical model, IEEE Trans. Electr. Devices 62 (9) (2015) 2751
2759. Available from: https://doi.org/10.1109/TED.2015.2458339. [8] A. Ortiz-Conde, F.J.G. Sánchez, Unification of asymmetric dg, symmetric dg and bulk undoped-body MOSFET drain current, Solid-State Electron. 50 (11) (2006) 1796
1800. [9] S. Khandelwal, Y.S. Chauhan, D.D. Lu, S. Venugopalan, M.A.U. Karim, A.B. Sachid, et al., BSIM-IMG: a compact model for ultrathin-body SOI MOSFETs with back-gate control, IEEE Trans. Electr. Devices 59 (8) (2012) 2019
2026. Available from: https://doi.org/10.1109/TED.2012.2198065.

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[10] P. Kushwaha, C. Yadav, H. Agarwal, Y.S. Chauhan, J. Srivatsava, S. Khandelwal, et al., BSIM-IMG with improved surface potential calculation recipe, in: 2014 Annual IEEE India Conference (INDICON), December 2014, pp. 1
4, ,https:// doi.org/10.1109/INDICON.2014.7030498.. [11] Y.K. Lin, P. Kushwaha, H. Agarwal, H.L. Chang, J.P. Duarte, A.B. Sachid, et al., Modeling of back-gate effects on gate-induced drain leakage and gate currents in UTB SOI MOSFETs, IEEE Trans. Electr. Devices 64 (10) (2017) 3986
3990. Available from: https://doi.org/10.1109/TED.2017.2735455.

CHAPTER 3

Channel Current Model With Real Device Effects in BSIM-IMG Sourabh Khandelwal Research Faculty, University of South Florida, Tampa, FL, United States

3.1 INTRODUCTION The core channel current model derived in previous chapter assumed an ideal long channel metal oxide field effect transistor (MOSFET) with a constant carrier mobility. However, the current in a realistic device is affected by several physical phenomena, which need to be accounted for in the model. These physical phenomena are also known as real device effects. Real device effects make the device characteristics deviate from the ideal device model presented in the previous chapter as both the device electrostatics and the carrier transport behavior change due to these. BSIM-IMG includes models for all the important real device effects in an fully depleted silicon-on-insulator (FDSOI) MOSFET. In addition to the real device effects seen in planar MOSFETs and three-dimensional fin-shaped field effect transistor (FinFETs), FDSOI MOSFETs exhibit a few unique physical phenomena or unique behavior of specific physical phenomenon due to the back-gate terminal which requires careful modeling. The real device effect model for each phenomenon in the FDSOI device is modeled with a set of physically grounded parameters which can be extracted from defined set of measured data. This chapter describes the real device effects models in BSIM-IMG channel current formulation. A discussion on the regions and device characteristics where these physical phenomena dominate is also given.

3.2 VERTICAL FIELD DEPENDENCE OF CARRIER MOBILITY The core channel current derived in the previous chapter assumed that the mobility of the carriers in the channel remains constant with the applied bias voltages for simplicity. However, the effective carrier mobility is found to depend strongly on the vertical electric field in the channel via Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00003-0

© 2019 Elsevier Ltd. All rights reserved.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

the various carrier scattering mechanisms. The main scattering mechanisms are phonon, coulombic, and surface roughness scattering. Phonon scattering is due to the lattice vibrations that scatters the carriers. Coulombic scattering is due to the scattering carriers undergo in the presence of ionized impurities. Since the oxide
semiconductor interface has manufacturing imperfections, carriers moving close to this interface undergo further scattering which is termed surface roughness scattering. Due to these scattering mechanisms, mobility is found to be depended on various device parameters such as oxide thickness, bias conditions, and substrate doping. It is found [1] that the carrier effective mobility can be expressed in a unified expression as function of the effective vertical electric field. In the case of FDSOI devices the effective vertical electric field should account for the back-gate electric field too. The average vertical electric field is proportional to the average channel charge via the Gauss law and in BSIM-IMG model the effective vertical electric field is expressed as

 Qinv;s 1 Qinv;d Cox1 Eeff 5 η (3.1) 1 qNA TSi 1 Eba 2 εSi where Cox1 is front-gate oxide capacitance, εSi is the dielectric permittivity of silicon, η (ETAMOB) is a model parameter, NA is the substrate doping, Tsi is the thickness of the channel region, and Eba is the average back-side electric field. Then the effective carrier mobility is expressed as function of Eeff given by μ μeff 5 0 (3.2) Dmob and

EU Dmob 5 1 1 UA 1 UCUVbg Eeff 1

UD 1 UDBUVbg

1 1 Qis 1 Qid =2Cox1

(3.3)

where μ0 is a model parameter for the low-field carrier mobility; UA, UC, UD, and UDB are model parameters for the different scattering phenomena; and Vbg is the back-gate voltage. In Eq. (3.3), the first term with UA and UC model parameters accounts for the phonon and surface roughness scattering while the term with UD and UDB models the coulomb scattering. Note that the behavior of the two terms with increasing gate voltage (or channel charge) is different. The terms modeling phonon and surface roughness scattering increase in magnitude while the coulomb scattering term decreases with the more carriers in the channel. Coulomb scattering reduces with increasing number of carriers due to carrier

Channel Current Model With Real Device Effects in BSIM-IMG

37

screening effect where the impact from ionized impurity is reduced due to a large number of carriers. This physical phenomenon is accurately modeled in the mobility model of BSIM-IMG [2]. The effective carrier mobility is used to calculate the final channel current instead of constant mobility used in the previous chapter. The effective mobility model parameters are critical in modeling the transfer characteristics, especially in the linear region or the low drain
source voltage bias condition. These model parameters are also important for getting an accurate fit to the transconductance and further higher order derivatives of the channel current and govern the nonlinear behavior of the device. Expectedly, these mobility parameters are temperature dependent as scattering mechanisms are impacted by change in the temperature. The temperature dependence of these parameters is described in Chapter 4, Leakage Current and Thermal Effects.

3.2.1 Nonmonotonic Back-Gate Bias Dependence of Mobility The back-gate bias dependence of carrier mobility is modeled with the model formulation presented above. However, it is found that the transconductance of the FDSOI devices with thick front-gate oxide can behave nonmonotonically with back-gate bias and needs special considerations [3]. This case is discussed below. Generally, the total drain current in an FDSOI device comes from front-gate channel charge. However, if the amount of charge in the back-gate channel becomes sufficiently large as compared to the frontgate channel charge, the back-gate channel can also make noticeable contribution to the drain current, and the transconductance of the device. If this happens, the behavior of transconductance w.r.t. change in back-gate bias can be quite different than the case when back-gate charge does not make a significant contribution. This is illustrated in Fig. 3.1. For the case when front-gate charge dominates a usual shift in transconductance curve w.r.t. variation in back-gate voltage is observed. This is due to the change in threshold voltage of the device with the back-gate voltage. However, for the case when back-gate charge is comparable to the front-gate charge, the transconductance curves have a different behavior which includes a shift due to the change in the threshold voltage and a change in the position of the transconductance (see Fig. 3.1). This is an anomalous behavior originating from the contribution of back-gate charge to the drain current. The total channel charge responsible for the drain current includes the effect of back-gate charge in the BSIM-IMG model. See Chapter 2, Core

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.1 Different behavior of transconductance w.r.t. back-gate voltage (Vbg) variations for following two cases: (A) when back-gate charge is negligible as compared to the front-gate charge, and (B) when back-gate charge is comparable to the front-gate charge.

Model for Independent Multigate MOSFETs. However, the mobilities of front- and back-gate channel can be different due to different quality of the oxide
semiconductor interfaces at the two gates. This requires modeling of effective mobility which accounts for a different carrier mobility at the back gate. The effective mobility can be calculated as a weighted function of front- and back-gate mobility as described by the following equation: μt;eff 5 wUμeff ;fg 1 ð1 2 wÞUμeff ;bg

(3.4)

where μefft is the total effective mobility, μeff,fg is the effective mobility of the front-gate channel, μeff,fg is the effective mobility of the back-gate channel, and w is the weight. The effective mobilities μeff,fg and μeff,bg are calculated by Eqs. (3.1)
(3.3). The weight w is a function dependent on the amount of front- and back-gate charge. The more the charge at the specific gate the more the weight it has in the total effective mobility. Fig. 3.2 shows the variation in the weight was front- and back-gate voltage is varied. The parameter extraction for devices exhibiting this behavior needs special considerations. First, one should model the Vbg 5 0 I
V curves, extracting the mobility-related parameters from linear transfer characteristics. Next, Vbg bias condition which accumulates/depletes the back-gate charge should be modeled. This is large negative Vbg for N-type

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39

Figure 3.2 Variation in the weight w [see Eq. (3.4)] with front- and back-gate voltage.

MOSFET (NMOS) and large positive Vbg for the P type MOSFET (PMOS) devices. When back side is accumulated/depleted, the back-side channel charge does not contribute to the current, and Vbg causes only a shift in threshold voltage. Afterward, the condition when the back gate is inverted and contributes to the drain current can be modeled.

3.3 THRESHOLD VOLTAGE As the channel length of the devices is scaled down, the one-dimensional electrostatics used for the calculation of surface potential or channel charge becomes less accurate. The two-dimensional nature of the device electrostatics with an influence of drain voltage on the channel charge becomes increasingly important to model. The two-dimensional nature of the device electrostatics is characterized by the concept of field penetration length λ [4]. Field penetration length is a measure of how much the electric field lines from the drain terminal penetrate and affect the channel charge. For a fixed channel length of the device a smaller λ signifies lower short-channel effects (SCEs). Field penetration length λ can be derived by following the twodimensional electrostatics of the device. The two-dimensional Poisson’s equation in the silicon body is

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

d 2 φ d2 φ qNA 1 2 5 dx2 dy TSi

(3.5)

where x and y are vertical and lateral directions, same as in Fig. 2.1, NA is the channel doping and Tsi is the silicon film thickness. At low drain voltage the x and y dependence of the potential φ(x, y) can be expressed using parabolic approximation as φðx; yÞ 5 c0 ðyÞ 1 c1 ðyÞx 1 c2 ðyÞx2

(3.6)

The boundary conditions for the displacement field at the front and the back interfaces that is at x 5 0 and x 5 Tsi are



εox  dφðx;yÞ  5 φ 2 Vfg dx εSi f

x50 (3.7) 

εox   dφðx;yÞ 5 V 2 φ b bg dx εSi x5TSi where φf and φb are front and back-side surface potentials, Vfg 5 Vfg
 Vfb;front and Vbg 5 Vbg
Vfb;back . Using the boundary conditions in Eq. (3.7) along with the fact that φ(x 5 0) 5 φf and φ(x 5 Tsi) 5 φb one can obtain a second order differential equation in φf(y) of the following form, d2 φf ðyÞ φf qNA 2 2 5 εSi dx2 λ

(3.8)

λ is the field penetration length, and for an FDSOI device, λ depends on whether the maximum subthreshold leakage is at the front surface or in the middle of the thickness of the silicon body. When front surface has the maximum leakage in subthreshold condition λ is given by the following equation: ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi s
 εSi λf 5 Tox1 TSi (3.9) εox On the other hand, when the maximum leakage is through the middle of the silicon thickness, λ is expressed as ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi s

 εSi 3 2 λs 5 Tox1 TSi 1 T (3.10) 8 Si εox From Eqs. (3.9) and (3.10), one can see that the field penetration length decreases with Tsi indicating that for scaling channel length for

Channel Current Model With Real Device Effects in BSIM-IMG

41

iso-short-channel performance Tsi should be scaled. The front- and the back-gate bias voltages can change the position of the dominant leakage; and hence, effective λ has a bias dependence. To capture this phenomenon the effective λ in BSIM-IMG compact model is a function of the bias voltages and can vary between λf and λs given by the following equations:





 Vgfb1 UTox2 U εsi =εox 1 Vgfb2 U Tox1 U εsi =εox 1 Tsi 1 1 21 xλ 5 1 tan ASCL 1 BSCL 2 π TSi (3.11)

λ 5 λs 1 xλ λf 2 λs

(3.12)

where ASCL and BSCL are model parameters which can be extracted by fitting the behavior of short-channel effects with the back-gate bias. It is interesting to note that for condition when the back gate is large positive for NMOS that is back interface is in weak or strong inversion, the field penetration length is larger degrading the short-channel performance.

3.3.1 Short-Channel Effects As the channel length of the device is scaled down, the source/drain junction regions effectively become a larger part of the device as these regions typically do not scale as much with the channel length scaling. FDSOI devices have a smaller characteristic length compared to bulk MOSFETs and thus offer relatively better short-channel effects performance. Nevertheless, in aggressively scaled devices, the built-in potential of source/drain regions causes a reduction of the threshold voltage of the device as shown in Fig. 3.3 [5]. This effect is also known as the threshold voltage roll-off. The reduction in threshold voltage increases off current and limits how much one can scale the channel length of the device without unbearable off-state leakage. The characteristic length λ is then used to describe this threshold voltage roll-off effect with the following expression: ΔVth;SCE 5 2



0:5DVT0

Vbi 2 φst cosh DVT1 Leff =λ 2 1

(3.13)

where DVT0 and DVT1 are model parameters, Leff is the effective channel length, Vbi it the built-in voltage for the source/drain body diodes and φst describing source-side surface potential in subthreshold region given by

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.3 Short-channel effects in FDSOI device for two different silicon thicknesses. Data is taken from Y.K. Choi, et al., 30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D. in: 58th DRC. Device Research Conference. Conference Digest (Cat. No. 00TH8526). IEEE, 2000.

φst 5 0:4 1 PHIN 1 ΦB

(3.14)

with the model parameter PHIN modeling the effect of nonuniform vertical doping. Eq. (3.13) describes the threshold voltage roll-off effect at low drain
source voltages. The model parameters DVT0 and DVT1 are typically obtained by fitting the variation of linear threshold voltage with channel length such as the data shown in Fig. 3.3 for two different silicon thicknesses. It is noteworthy that as Tsi is scaled down in the device, the SCE gets reduced, and the BSIM-IMG model follows this trend as the characteristic length in the model will reduce with Tsi.

3.3.2 Drain-Induced Barrier Lowering When the drain-side electric field is large, it can lower the barrier for carriers at the source contact to enter the channel region. This in turn causes the threshold voltage to reduce [6]. The reduction of the barrier is at the source side; and hence, the reduction of threshold voltage originates from the two-dimensional electrostatics in the channel. As oppose to the typical “one-dimensional” scenario in long channel MOSFETs where channel charge is controlled solely by the gate electrode, strong electric fields from drain makes channel charge controlled by both gate- and drain electrodes.

Channel Current Model With Real Device Effects in BSIM-IMG

43

This effect is called drain-induced barrier lowering (DIBL). This is modeled with the following expression in the BSIM-IMG model:

0:5 ETA0 1 ETABUVbg

ΔVth;DIBL 5 2 ðVds Þ (3.15) cosh DSUB Leff =λ 2 1 where ETA0, ETAB, and DSUB are model parameters. These parameters can be extracted from experimental data on the variation of threshold voltage in saturation condition versus the channel length. Similar to the SCE effect described in the section earlier, DIBL effect is dependent on Tsi too. A reduction in Tsi improves gate control and reduces DIBL. This is captured in the model via the characteristic length λ. It is intuitive to expect that DIBL effect will have a channel length dependence, and this effect will reduce at longer channel lengths. This is modeled via the parameter DSUB. Adjusting DSUB will adjust the channel length at which this effect becomes significant. The amount of influence drain-side electric field has is found to be dependent on back-gate bias condition for the FDSOI device. The back-gate bias dependence of DIBL is expected as one can imagine the back-gate voltage to be influencing the device electrostatics and changing the charge centroid. This unique FDSOI phenomenon is captured by the BSIM-IMG model parameters ETAB.

3.3.3 Reverse Short-Channel Effect Halo implants near source and drain regions are used to control the shortchannel effects. These are the regions of heavy doping same type as that of the substrate. By using the heavy doping near the junctions the depletion region width is reduced which reduces the short-channel effects. The halo region lengths do not scale with the channel length of the device. As a result, halo region becomes bigger part of the device for the short-channel devices, and this increases the average substrate doping of the device. The increase in doping causes the threshold voltage of short-channel devices to increase with a decrease in channel length. This effect being opposite to the typical short-channel behavior is termed the reverse SCE (RSCE) [7]. The threshold voltage behavior with channel length with the RSCE is shown in Fig. 3.4. RSCE is modeled in BSIM-IMG compact model with K1RSCE and LPE0 model parameters as shown below:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  pffiffiffiffiffiffi LPE0 21 φst 11 ΔVth;RSCE 5 K1RSCE (3.16) Leff

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.4 Threshold voltage versus channel length indicating the reverse shortchannel effect in halo-implanted devices.

The model parameters K1RSCE and LPE0 are obtained from modeling the linear threshold voltage variation with the channel length. LPE0 parameter controls the channel length from which RSCE becomes pronounced while K1RSCE models the amount of threshold voltage shift it causes. φst is the source-side surface potential in the subthreshold region, same as described in Eq. (3.14).

3.3.4 Threshold Voltage Roll-Off at Moderate Channel Length The device with halo implants are seen to have roll-off in threshold voltage at moderate channel lengths and high drain
source voltage. This anomalous behavior is also known as long channel DIBL or draininduced threshold voltage shift (DITS). This explanation for this effect is as follows. For a large drain
source voltage condition and for a device with halo doping, there exist barriers for carrier flow at both drain and source side. This is in contrast with a uniformly doped device which has barrier only at the source side for large drain voltage condition. Now, a change in drain
source voltage modifies this drain-side barrier for the halo-implanted device as shown in Fig. 3.5. This causes a change in the threshold voltage of the device. The uniformly doped devices do not see this effect as they do not have any barrier at the drain end for high drain voltage condition which will be modified by the drain
source voltage.

Channel Current Model With Real Device Effects in BSIM-IMG

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Figure 3.5 Only drain-side barrier is significantly affected by the drain voltage in the case of long channel devices.

So for moderate channel lengths the halo-doped and uniformly doped device can have a distinct threshold voltage behavior due to the DITS effect. This effect is modeled with DSC0 and DSC1 model parameters in the BSIM-IMG model as described below: ΔVth;DSC 5 2

DSC0 Vds DCS1 1 Leff

(3.17)

3.3.5 Body Doping Effect The number of dopants in the silicon channel region will change the threshold voltage of the device with higher doping indicating a high threshold voltage. This effect is modeled in BSIM-IMG with the following expression:
 qNbody Tsi 0:5Tsi ΔVth;Nbody 5 (3.18) 12 Cox1 Tsi 1 εratio Tox2 where Nbody is the number of dopants in a unit volume of the silicon film thickness Tsi. The term with negative sign in Eq. (3.18) is modeling the fact that the part of the electric field lines from the dopants also terminates at the back gate of an FDSOI device.

3.3.6 Effect of Substrate Depletion on Threshold Voltage The substrate underneath the back-gate oxide layer is a semiconductor material identified as backplane in Fig. 3.6. The backplane region may

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.6 FDSOI device showing the backplane. Vsubdep represents the voltage drop in the depletion region in the substrate region.

have N/P-type doping, and depending on the bias condition, there may be a depletion region formation or not in the backplane. This additional drop in the backplane will change the threshold voltage of the FDSOI device [8]. The presence of backplane with adequate doping also helps improve the device electrostatics and the short-channel performance. This is because the drain electric field lines can terminate at the backplane if available improving the effective gate control. Nevertheless, the depletion in substrate can cause a change in threshold voltage. Device electrostatics at the back-gate interface is solved to develop a model for the shift in threshold voltage due to the substrate depletion effect. All the continuity of displacement field vector at the interface of back-gate oxide and substrate we get pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi εox2 Eox2 5 εsi Esubdep 5 2qεsi Nsub Vsubdep (3.19) where Nsub is the substrate doping, Vsubdep is the voltage drop in the substrate depletion region. Considering Vox2 as the voltage drop across the back-gate oxide, then we have Vbg 5 Δφ2 1 Vox2 1 ψs2 1 Vsubdep

(3.20)

where ψs2 is the back-gate surface potential, and Δφ2 models difference between the back-gate Fermilevel and the reference. Eqs. (3.19) and (3.20) can be solved for Vsubdep, resulting in, sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !2 Vbg 2Δφ2 2ψs2 Vsubdep 5 Vsubdep0 (3.21) 11 21 Vsubdep0 2 . Above model assumes of uniform subwhere Vsubdep0 5 qεsi Nsub =2Cox2 strate doping. The substrate doping profile can be complex which is not accounted for in the model above. To allow model tuning considering

Channel Current Model With Real Device Effects in BSIM-IMG

47

the nonuniform or complex substrate doping, Eq. (3.20) is modified with VKNEE1 as a model parameter in the following way: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !2 Vbg 2Δφ2 2VKNEE1 11 21 (3.22) Vsubdep 5 Vsubdep0 Vsubdep0 Using Eq. (3.21), the threshold voltage shift due to the substrate depletion effect is calculated as
   Csi Cox2 ΔVT ;bg 5 Kvbg Vbg 2 Δφ2 2 BPFACTORUVsubdep ðCsi 1 Cox2 ÞCox1 (3.23) where Kvbg is modeling the channel length dependence of the substrate depletion effect using the field penetration length via the following expression: !! 0:5KBG1

Kvbg 5 min KBG2; KBG0 1 (3.24) cosh DBGULeff =λ 2 1 KBG0, KBG1, KBG2, and DBG are model parameters. The above formulations accurately model the nonlinear variation in the threshold voltage with the back-gate voltage as shown in Fig. 3.7. It is clear from Fig. 3.7 that for a positive Vbg the substrate back-oxide interface is NMOS, p–well 0.15 Model TCAD

0.1

Delta VTHlin (V)

0.05 0 –0.05 –0.1 –0.15 –0.2 –0.25 –3

–2

–1

0 VBGS (V)

1

2

3

Figure 3.7 Change in linear region threshold voltage with the substrate voltage in an FDSOI device modeled with the BSIM-IMG model.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.8 Total threshold voltage shift due to the various real device effects are used to calculate the effective gate voltage which goes into the core model calculations of BSIM-IMG model.

accumulated, and the threshold voltage changes linearly with the increase in positive Vbg. For negative Vbg the substrate gets depleted, and the change in threshold voltage is nonlinear. The behavior of change in threshold voltage in both regions (accumulation and depletion) is captured by the developed model. After modeling of the physical effects described in Sections 3.3.1
3.3.6, the final expression for the shift in threshold voltage at room temperature is given by ΔVt;all 5 ΔVt;SCE 1 ΔVt;DIBL 1 ΔVt;RSCE 1 ΔVt;DSC 1 ΔVt;Nbody 1 ΔVt;Vbg (3.25) The shift in the threshold voltage changes the effective front-gate voltage in the model which is used for the calculation of charge, current, and other quantities in BSIM-IMG model by calculating the effective gate voltage which goes into the core model calculations. This procedure is summarized in Fig. 3.8.

3.3.7 Operating Point Threshold Voltage Threshold voltage (Vt) is an important device parameter as it governs the transition from subthreshold to strong inversion region. Earlier generation models, such as BSIM4, are based on the concept of Vt and are very

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Channel Current Model With Real Device Effects in BSIM-IMG

popular among the users. BSIM-IMG, like other advanced models, uses a surface potential or charge-based approach; however, Vt remains a key parameter since circuit designers need to know it to determine the bias conditions. In this subsection, we will discuss the analytical model developed in BSIM-IMG to report the operating point Vt to the users. There are several ways by which threshold condition can be defined, like gate voltage at which surface potential becomes 2φf 1 several kT/q, where 2φf and kT/q represent the Fermi potential and the thermal voltage, respectively. For the BSIM-IMG model the following definition of Vt is used. Recognizing that the drain current in the subthreshold region is primarily governed by the diffusion mechanism, while in the strong inversion it is primarily drift, Vt is defined as [9] @ V t I d;

drift BI d; diffusion

(3.26)

The inversion charge at the threshold condition can be expressed as Qinv;V t 5 C ox1 3 V t

(3.27)

The threshold voltage is then defined as the gate voltage needed to achieve inversion charge given by the above equation [Eq. (3.26)]. Now consider the inversion charge which is given as sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 ψs1 2 Vch Qinv 5 2Nc kT exp (3.28) 1 ðεSi Es2 Þ2 2 εSi Es2 kT =q where Nc, k, and T represents the conduction-band density of state, Boltzmann constant, and the device temperature, respectively. q is the electron charge. εSi is the permittivity of the silicon. ψs1 is front surface potential, Vch is channel potential, and Es2 is the back-gate electric field which is given as Es2 5

ψs1 2 Vbg 2 Δφ2

εSi =εox ðTox2 Þ 1 TSi

(3.29)

where εox is the permittivity of the oxide, Vbg is back-gate voltage, and Δφ2 is back-gate work function. Tox2 represents the back-gate oxide thicknesses, and Tsi is the silicon body thickness. From Eqs. (3.27) and (3.28)


2Qin εSi ψs1 2

ψs1 2 Vbg 2 Δφ2 2 2Nc kT εSi exp Qin 1 kT =q TSi 1 Tbox εSi =εbox (3.30)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

In the next step, ψs1 at the threshold condition ψs1;V t is analytically obtained from Eqs. (3.28) and (3.29) by using the Halley’s method of numerical calculation. The initial guess is obtained using Eq. (3.28) and substituting Qinv 5 Qinv;Vt
2  Qinv;Vt kT 0 ψs1 5 (3.31) ln 1 Vch q 2Nc kT ψs1;V t is now used to get Vt as follows. Using the Gauss law, inversion charge and surface potential are related as



Cox2 Csi Qinv 5 Cox1 Vfg 2 Δφ2 2 ψs1 1 Vbg 2 Δφ2 2 ψs1 (3.32) Cox2 1 Csi where Vfg and Δφ1 are the front-gate voltage and gate work function, respectively. Cox1 and Csi are oxide and silicon layer capacitances per unit area. The threshold voltage is now given as Vt;long 5



Qinv;Vt Cox2 Csi Vbg 2 Δφ2 2 ψth 1 Δφ1 1 ψs1;Vt 2 Cox1 Cox1 ðCox2 1 Csi Þ (3.33)

The threshold voltage for the short-channel device is expressed as Vt;short 5 Vt;long 2 ΔVt

(3.34)

where the term ΔVt accounts for the SCEs as discussed earlier in this section. The above analytical model for the operating point threshold voltage is validated with the experimental data for different gate length devices ranging from 52 to 961 nm. First, the global parameters are extracted to fit the DC characteristics for various bias conditions. Next, threshold voltage is extracted using following methods: Extrapolation in Linear Region, extrapolation in saturation region, gm/Id, second derivative (SD), SD logarithmic, and constant current methods. The model in is validated with all these methods for different gate lengths, drain and back-gate biases for both the n- and p-channel FDSOI devices. Fig. 3.9A and B show ΔVt as a function of gate length in the linear and saturation region for n-channel device, respectively. As gate length scales down, ΔVt increases due to SCEs. The threshold voltage model shows correct trends with the length scaling and closely matches the

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51

Figure 3.9 Model results for NMOS: ΔVt as a function of gate length in (A) linear region, Vds 5 50 mV (B) saturation region, Vds 5 1.2 V.

threshold voltage extracted with various methods. Fig. 3.10A and B show results for a p-channel device. Again, the model accurately captures the threshold voltage behavior. The model is also tested for different back-gate biases. In Fig. 3.11A and B, threshold voltage is plotted against Vbg in the linear and saturation region of operation, respectively. The shortest gate length device is used for this illustration. The model successfully captures the threshold voltage characteristics for various back biases as well.

3.4 DRAIN SATURATION VOLTAGE The increase in the drain current with the drain voltage saturates once the voltage becomes equal to the drain saturation voltage (Vdsat). The physical

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.10 Model results for PMOS: ΔVt as a function of gate length in (A) linear region, Vds 5 50 mV (B) saturation region, Vds 5 1.2 V.

phenomena which cause the current to saturate are pinch-off and carrier velocity saturation. With an increase in the drain voltage from the linear condition (small Vds), the channel charge at the drain end decreases. The channel charge decreases as it is proportional to Vgs
Vt
Vx with Vx being the potential at any point in the channel. At drain end Vx 5 Vds and increasing Vds decreases the channel charge. When charge at the drain end becomes very small, a very short region of extremely high electric field gets created to support the drain current continuity. Any further increase in the drain voltage does not change the drain-side charge any further. It only increases the length of this extremely small region of high electric field. This effect is called pinch-off. Pinch-off occurs in the case of long channel length devices. For short-channel devices the drain current gets saturated before the condition of pinch-off is reached. This happens due to the phenomenon called the carrier velocity saturation. For low Vds, the carrier velocity linearly increases with Vds and then it saturates

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53

Figure 3.11 Threshold voltage model validation at different back biases: Vt versus Vbg in (A) linear region, Vds 5 50 mV (B) saturation region, Vds 5 1.2 V.

once the carriers move at the saturation velocity. Both these phenomena (pinch-off and velocity saturation) are modeled by calculating the drain saturation voltage due to these. The calculated drain saturation voltage is then used for calculating the effective drain
source voltage given by Vds UVdsat Vdseff 5

MEXP 1=MEXP VdsMEXP 1Vdsat

(3.35)

where MEXP is a model parameter with a value greater than 2. MEXP parameter controls the sharpness with which Vdseff approaches the saturation voltage Vdsat. Higher MEXP indicates that Vdseff reaches Vdsat rapidly as shown in Fig. 3.12. MEXP parameter is very useful in accurate fitting of output conductance. Vdsat is calculated as the minimum of the Vds values at pinch-off and velocity saturation occurs. For pinch-off, Vdsat is approximately (Vg
Vt) because a drain voltage larger than this would mean a very small charge density at the drain side

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.12 Impact of MEXP parameter on how sharply Vdseff approaches Vdsat. Vdsat is 0.7 V in this example.

as the gate-channel voltage in that region will become smaller than the threshold voltage. Vg
Vt is expressed in form of a charge-based expression in BSIM-IMG as Vdsat;pinch-off 5

Qtots Cox1 1 Cox2

(3.36)

where Qtots is the total charge at the source side, Cox1(2) are oxide capacitances of the front and the back gates. For model tuning and to limit the saturation voltage in subthreshold condition to twice the thermal voltage, the following modification of the Eq. 3.36 is implemented in the model:
 Qtots Vdsat;pinch-off 5 KSATIV 1 2Vth UKSUBIV (3.37) Cox1 1 Cox2 with KSUBIV and KSATIV are model parameters, and Vdsat,pinch-off is the saturation voltage due to the pinch-off effect. For strong inversion (high Vgs 2 Vt) conditions the terms with Qtots dominates in Eq. (3.37) while for the subthreshold condition Qtots becomes very small, and Vdsat is approximately VdsatB2.Vth.KSUBIV. Typically KSUBIV 5 1, however, KSUBIV is quite useful in accurate modeling of output conductance (Gds) in the subthreshold region. In the case of velocity saturation effect, Vdsat depends on the saturation velocity VSAT, and the channel length of the device given by Vdsat;vse 5

VSAT Leff μeff

(3.38)

Channel Current Model With Real Device Effects in BSIM-IMG

55

where Vdsat,vse is the saturation voltage due to the velocity saturation effect, μeff is the effective carrier mobility as calculated by Eq. (3.2) described in the section earlier. Note that effective mobility calculation includes bias dependence on front- and back-gate bias voltage, and this dependence affects the current saturation phenomenon. The final Vdsat is the minimum of the two values calculated by Eqs. (3.37) and (3.38). The above calculation of Vdsat and Vdeff assumes that the series resistance at drain and source contact are zero. When including the effect of the series resistance, Vdsat calculations are modified as discussed further for different options of including series resistance in the BSIM-IMG model.

3.4.1 When RDSMOD 5 0 or 2 As discussed later in this chapter, these two options of RDSMOD setting (RDSMOD 5 0 or 2) include the effect of series resistance in the model calculations itself as oppose to instantiating a separate resistor element in the model. The drain
source saturation voltage depends on the series resistance and this dependence takes the form of a quadratic equation with a, b, and c as the coefficients of the square, linear and constant terms of the quadratic equation. The coefficients are given by a 5 2W UVSATUCox1 URds b 5 Vdsat;pin-off 1 Esat Leff 1 3UVdsat;pin-off UW

UVSATUCox1 URds c 5 Vdsat;pich-off Esat Leff 1 Vdsat;pinch-off Ua

(3.39)

where Rds is the series resistance, W is the device width, Esat is the saturation electric field (μeff/VSAT) and Leff is the effective channel length. The drain
source saturation voltage is calculated using the standard formula for calculating the roots of the quadratic equation with coefficients as described in Eq. (3.38). One of the roots comes out to be unphysical and is ignored while other is used in the model as the drain saturation voltage.

3.4.2 When RDSMOD 5 1 In this option, the effect of series resistance is modeled as an explicit resistor implemented in the model. As a result, the simulator solves for the intrinsic drain
source voltage of the device and the drain
source saturation voltage is calculated as the minimum of Eqs. (3.36) and (3.37) as Vdsat 5

Vdsat;vse UVdsat;pinch-off Vdsat;vse 1 Vdsat;pinch-off

(3.40)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

3.5 QUANTUM MECHANICAL EFFECTS The centroid of the inversion charge does not lie at the interface of the gate insulator and semiconductor surface but lies slightly away from the interface due to the quantum mechanical effects [7]. The position of the charge centroid depends on the electric field. The change in the position of the centroid affects the effective oxide capacitance. This effect is included in the BSIM-IMG model with the following expression: Cox1eff 5

Cox1 

PQM  1 1 ðTsi Cox1 Þ=1 1 ðqia 1ETAQMUqba Þ=QM 0 UQMTCENCV (3.41)

where qia and qba are average inversion charge and average dopant charge, respectively. ETQAM, QM0, PQM, and QMTCENCV are model parameters. Setting QMTCENCV to zero results in Cox1eff 5 Cox1 and removes the quantum mechanical effect from the model with. As the gate voltage increases, qia will increase resulting in Cox1eff to decrease, modeling the observed quantum mechanical effect as shown in Fig. 3.13. The parameter PQM can be used to control the rate at which capacitance decreases with the increase in gate voltage due to the quantum mechanical effect. ETAQM becomes important when there is a substantial contribution of the dopant charges.

Figure 3.13 Impact of quantum mechanical effects on CV characteristics of the device.

Channel Current Model With Real Device Effects in BSIM-IMG

57

3.6 LATERAL NONUNIFORM DOPING MODEL The doping along the direction of the channel length of the device is not completely uniform. This leads to a slightly different behavior of the device in C
V characterization as compared to the I
V measurements. The threshold voltage of the device can be slightly different for the C
V and I
V measurements. While ideal way to incorporate this effect is to perform the surface potential and charge calculations separately for I
V and C
V simulations, this will double the computational time for core model. To avoid this computational penalty, following term is included as a multiplied with the drain current expression,


K0 Mnud 5 exp 2 K0SIUqia 1 2Vt



(3.42)

Where K0 and K0SI are the model parameters. This model should be exercised after fitting the C
V to accurately model the threshold voltage of the I
V curve in linear region. K0 parameter can be used to tune the threshold voltage while K0SI can be used to adjust the strong inversion fitting.

3.7 OUTPUT CONDUCTANCE MODEL The physical phenomena of channel length modulation and DIBL affect the output conductance of the device as shown in Fig. 3.14. These are accounted for in the BSIM-IMG model as described in Section 3.7.1.

3.7.1 Channel-Length Modulation As the applied drain voltage is increased, the charge toward the drain end decreases, and the lateral electric field increases, and after sufficient drain voltage, a point if reached where an increase in drain voltage further no longer increases the drain current. For long-channel-length device, this occurs due to the pinch-off effect discussed in Section 3.3. If the drain voltage is increased beyond the saturation voltage, the point of pinch-off in the channel moves toward the source side. This causes an effective decrease in channel length of the device and is referred to as channellength modulation effect. A decrease in channel length causes the current to increase beyond the drain
source saturation voltage causing a finite output conductance. This effect is accounted for in the BSIM-IMG model using the following formulations:

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 3.14 Impact of channel length modulation and drain-induced barrier lowering on output conductance of the device.

8 < PCLM 1 qia UPCLMG 1 1 5

Cclm : 1=PCLM 2 qia UPCLMG

(3.43)

The first Cclm expression is used when parameter PCLMG is positive, and the second is used for the case when PCLMG is negative. PCLM and PCLMG are model parameters. The parameters PCLM and PCLMG can be extracted from fitting the output conductance (Gds) from the measurements. Next, a multiplier Mclm is calculated which is multiplied to the original drain
source current expression to account for the CLM effect. Mclm is given by  1 Vds 2 Vdseff Mclm 5 1 1 ln 1 1 (3.44) Cclm Vdsat 1 Esat L

3.7.2 Output Conductance Due to Drain-Induced Barrier Lowering The DIBL effect also causes finite output conductance in the output characteristics beyond the drain saturation voltage. This effect is modeled with following expressions in the BSIM-IMG model.

1 1 PVAG qia =Esat L PVAG factor 5 (3.45)

1 2 PVAG qia =Esat L

Channel Current Model With Real Device Effects in BSIM-IMG

59

where PVAG is a model parameters, and the first equation in Eq. (3.44) is used when PVAG is positive, and the second one is used when PVAG is negative. 0:5PDIBL1

θrout 5 1 PDIBL2 (3.46) cosh ðDROUTULeff Þ=λ 2 1
 qia 1 2Vt Vdsat UPVAGfactor 12 VADIBL 5 θrout Vdsat 1 qia 1 2Vt MDIBL 5 1 2

Vds 2 Vdseff VADIBL

(3.47)

(3.48)

Here DROUT, PDIBL1, and PDIBL2 are model parameters extracted by fitting the output conductance from the measurements. DROUT models the channel-length dependence of the DIBL effect on the output conductance. The complete output current multiple is then given by the product of MCLM and MDIBL as M oc 5 MDIBL UMCLM

(3.49)

Moc is then multiplied to the final drain-current expression.

3.8 VELOCITY SATURATION EFFECT The impact of velocity saturation effect on drain current is included with the term Dvsat in the BSIM-IMG model. The calculation of Dvsat is as follows: qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

2 1 1 DELTAVSAT 1 Δqi =Esat1 Leff Xsat pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Dvsat 5 1 1 DELTAVSAT (3.50)

1 1 PTWG 2 PTWGBUVbg;pos 2 PTWGB2Vbg qia Δq2i 2 Esat1 5

2UVSAT1 μeff

(3.51)

where Xsat also includes the effect of back-gate voltage in Dvsat, it is given by q ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi

2 0:8 1 VSATBUVbg 1 0:81VSATBUVbg 1 0:01 (3.52) Xsat 5 0:2 1 2

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

In the above calculations, VSAT1 is a model parameter with default value set to VSAT. VSAT1 is allowed to have values different than VSAT for an additional tuning flexibility. VSATB is model parameter which can be used for fitting the saturation region characteristics for different backgate voltages. PTWG and PTWGB are model parameters which can be used for further fine tuning the saturation transconductance fitting for devices which show gradual velocity saturation effect in their characteristics.

3.9 SERIES RESISTANCE MODEL The source and drain regions of the device are resistive which impact the device characteristics. There are two components of the source/drain resistances: (1) bias-independent resistance due to the finite conductivity of the contact metals, and (2) bias-dependent resistance related to the region of the source and drain contacts which overlap with the gate. Both these resistances are modeled in the BSIM-IMG model in different configurations which can be selected by the users depending on their requirements. The model choices are set by the model switch RDSMOD as shown in Fig. 3.15 and further explained below.

Figure 3.15 Options for including parasitic series resistance model in the BSIM-IMG model.

Channel Current Model With Real Device Effects in BSIM-IMG

61

3.9.1 Bias-independent Resistance This resistance is due to the finite conductivity of the source/drain regions in which metal has been diffused via deposition and annealing. This depends on the geometry of the source/drain region and is modeled with the help of sheet resistivity parameters RSHS and RSHD for source and drain, respectively. If NRS and NRD are the number of diffusion squares at source and the drain side, then the bias-independent resistances in these regions are expressed as Rs;geo 5 NRSURSHS Rd;geo 5 NRDURSHD

(3.53)

NRS and NRD are instance parameters, and thus for a process technology, they can vary with each instance of the device, depending on the device geometry.

3.9.2 Bias-Dependent Source/Drain Resistance The heavily doped source and drain regions typically have finite region which overlaps with the gate of the device. This happens due to the carrier diffusion during the high-temperature annealing process step. This part of the source/drain resistances change with the applied bias. This is included in the BSIM-IMG model as follows
 1 RDSW Rds 5 (3.54) WR RDSMIN 1 NFUWeff 1 1 PRWGUqia where NF is the number of fingers of the device, Weff is the effective width of a single finger, RDSMIN is the minimum source to drain resistance needed for simulator convergence, RDSW is the source/drain resistance and low gate-bias condition, PRWG model parameter controls the gate-bias dependence of the source/drain resistance, and qia is the average channel charge. As the gate voltage goes from subthreshold to strong inversion region, the average channel charge increases, reducing the biasdependent part of the source/drain resistance. This decrease in resistance with increasingly larger gate voltage can be explained as follows. For an NMOS the source/drain overlap regions will be N-type and with increasingly large gate voltage, these regions will attract increasingly more carriers, in turn reducing the resistance of this region. In BSIM-IMG, users are given options for modeling the above two parts of resistance model in different configurations (see Fig. 3.15) via the following model options:

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

1. RDSMOD 5 0: When RDSMOD is set to 0, the bias-independent part of the resistances is implemented as external resistors, while the bias dependent is included directly in the model calculations. This will introduce two additional nodes in the simulations, one at the source, and other at the drain terminal as shown in Fig. 3.15 for RDSMOD 5 0. The nodes SI and DI shown in Fig. 3.15 become the internal source/drain nodes, while D and S are the external nodes. The surface potential calculations are performed using the voltages at the intrinsic (SI and DI) terminals. 2. RDSMOD 5 1: When RDSMOD is set to 1, the total resistance at the source and at the drain is modeled via external resistors in the model. This introduces two nodes at each terminal (source and drain), and thus in-total four additional nodes are introduced in the model. This is the most complex scenario w.r.t. to model computations. As a result, RDSMOD 5 1 is computationally slower than the other two options. 3. RDSMOD 5 2: With this option both bias-independent and biasdependent parts of the source/drain resistances are included in the model calculations directly without using any external resistor elements. This does not introduce any additional node. As a result, this option is computationally more attractive.

3.10 CHANNEL CURRENT EXPRESSION The final drain
source current expression accounting for all the earlier described real device effects reads as Ids 5 μ0 Cox1

NFUWeff Moc ðqia Δψ 1 Vt Δqi Þ Leff Dmob Dr Dvsat

(3.54)

NF is the number of fingers of the device. The impact of change in threshold voltage due to the short-channel effects, DIBL, and back-gate effect is accounted for in the calculation of qia, Δqi, and Δψ.

REFERENCES [1] K. Chen, H. Clement Wann, J. Dunster, P.K. Ko, C. Hu, M. Yoshida, Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages, Solid State Electron. 39 (10) (1996) 1515
1518. [2] S. Khandelwal, et al., BSIM-IMG: a compact model for ultrathin-body SOI MOSFETs with back-gate control, IEEE Trans. Electron Devices 59 (8) (2012) 2019
2026.

Channel Current Model With Real Device Effects in BSIM-IMG

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[3] Y.K. Lin, et al., New mobility model for accurate modeling of transconductance in FDSOI MOSFETs,”, IEEE Trans. Electron Devices 65 (2) (2018) 463
469. [4] I. Ferain, C.A. Colinge, J.P. Colinge, Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors, Nature 479 (7373) (2011) 310
316. [5] Y.K. Choi, et al., 30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D. in: 58th DRC. Device Research Conference. Conference Digest (Cat. No. 00TH8526). IEEE, 2000. [6] Y. Cheng, C. Hu, J.H. Huang, P.K. Ko, Threshold voltage model for deepsubmicrometer MOSFET’s, IEEE Trans. Electron Devices 40 (1) (1993) 86
95. [7] C.Y. Lu, J.M. Sung, Reverse short-channel effects on threshold voltage in submicrometer salicide devices, IEEE Electron Device Lett. 10 (10) (1989) 446
448. [8] P. Kushwaha, et al., Modeling the impact of substrate depletion in FDSOI MOSFETs, Solid State Electron. 104 (2015) 6
11. [9] H. Agarwal, et al., Analytical modeling and experimental validation of threshold voltage in BSIM6 MOSFET model, Electron Devices Soc. IEEE J. 99 (2015) 1.

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CHAPTER 4

Leakage Current and Thermal Effects Sourabh Khandelwal1 and Pragya Kushwaha2 1

Research Faculty, University of South Florida, Tampa, FL, United States Postdoctoral Researcher, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, United States

2

4.1 LEAKAGE CURRENTS AND THEIR MODELING The continuous scaling of channel length that enables a tremendous increase in the density of devices per unit area also gives rise to the shortchannel effects (see Chapter 3: Channel Current Model With Real Device Effects in BSIM-IMG). These effects make the device leak current when it is supposed to be off. This leakage current gives rise to static power consumption in digital circuits and requires careful control both at the technology and at the circuit level to meet the energy efficiency requirements. As compared to the traditional bulk MOSFETs, fully depleted silicon-on-insulator (FDSOI) devices alleviate the issue of leakage current by allowing strong gate control of the channel due to the thin silicon body. Nevertheless, as channel lengths are aggressively scaled, FDSOI devices also suffer from leakage current, which needs to be accounted for in the model. As discussed below, there are several different mechanisms that cause the leakage currents. BSIM-IMG compact model accounts for these leakage currents as described next.

4.1.1 Subthreshold Leakage In a CMOS inverter, when the input is low (“0”) and output is high (“1”), the NMOS transistor is biased with gate voltage Vg as zero and drain voltage Vd as Vdd. With the applied Vg below the threshold voltage, NMOS is in off state and ideally should leak very small current. However, in real devices, this leakage can be significant. This current is commonly referred to as the Ioff current. Subthreshold drain-to-source leakage current is a major component of the off current. The main reason for subthreshold leakage is that even though the gate voltage applied is below the threshold voltage, owing to the Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00004-2

© 2019 Elsevier Ltd. All rights reserved.

65

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 4.1 Boltzmann carrier distribution causes drain-source subthreshold leakage.

Boltzmann distribution, there are always high energy carriers that can surmount the barrier at the source end in this bias condition as shown in Fig. 4.1. The Boltzmann distribution of carriers limits the turn-off behavior of MOSFET and puts a theoretical limit on the subthreshold slope of the devices. Theoretical minimum of subthreshold slope at room temperature is 60 mV/decade due to the Boltzmann distribution, and this is also referred to as Boltzmann tyranny. However, in real device, subthreshold slope is much higher than the theoretical minimum due to the short-channel effects. As the channel length is reduced, drain-side control on the channel region increases. Drain voltage can reduce the source-side barrier resulting in higher leakage by degradation in subthreshold slope and a reduction in the threshold voltage. In BSIM-IMG model the short-channel effects have been accurately modeled as described in Chapter 3, Channel Current Model With Real Device Effects in BSIM-IMG. Short-channel effect formulation for the drain-induced barrier lowering (DIBL), threshold voltage roll-off, and subthreshold slope degradation include parameters that can be used to accurately model the subthreshold drain-source leakage in the device.

4.1.2 Gate-Induced Source and Drain Leakage Model For the off-state condition of the device with the gate voltage Vg set to zero and drain voltage Vd at high value equal to Vdd, the electric field at the drain-channel junction is high. It can be high enough to cause direct

Leakage Current and Thermal Effects

67

Figure 4.2 Band-to-band tunneling at the drain junction. Energy band diagram is along A
A0 .

band-to-band tunneling of carriers at the drain-channel junction as shown in Fig. 4.2. This tunneling of carriers causes an additional off-state leakage called gate-induced drain leakage (GIDL). The GIDL current density can be modeled following the tunneling physics. The tunneling current density is given by
 B J 5 AUEs Uexp 2 (4.1) Es where A is preexponential parameters, B is tunneling coefficient, and Es is the electric field. The electric field is formulated in the BSIM-IMG model with the following expression: Es 5

Vds 2 Vfg 2 EGIDL 1 Vfbsd 1 VBGIDLUγ 0 UðVbgs 2 Vfbsdbg 2 VBEGIDLÞ Eratio UEOT1 (4.2)

where Vds, Vfg, and Vbgs are applied drain-to-source, front-, and back-gate voltages. EGIDL and VBEGIDL are model parameters. Vfbsd and Vfbsdbg are front- and back-gate flat-band voltages. γ0 is ratio of back-oxide to silicon capacitance as defined in Chapter 3, Channel Current Model With Real Device Effects in BSIM-IMG. EOT1 is the front-gate oxide thickness. Using Eq. (4.4), the drain-side GIDL current is modeled as

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design


Igidl 5 AGIDLUW UNFUEsPGIDL Uexp

 BGIDL 2 Es

(4.3)

It is important to note that in the case of FDSOI devices the electric field Es causing the GIDL current is also influenced by the back-gate voltage Vbg. This is modeled in Eq. (4.4) with the parameters VBGIDL and VBEGIDL in the BSIM-IMG model. The extraction of GIDL parameters requires careful considerations. If one only has measured drain-current data for the off-state condition with Vg equal to zero, it is hard to distinguish GIDL with the subthreshold leakage as they are both present at this bias condition. To distinguish the two leakage currents, drain-current measurement for negative Vg in the case of NMOS device can be used. While the subthreshold leakage will get smaller as Vg is increased in negative direction, the GIDL current will keep on increasing. Another distinguishing behavior of the GIDL current from subthreshold leakage is its temperature dependence. While subthreshold leakage has strong temperature dependence with leakage current increasing rapidly with a rise in temperature, GIDL being a tunneling phenomenon has much less dependence on temperature. Lastly, this section describes the GIDL at the drain junction, but same mechanism can also happen at the source junction, and the current is termed gate-induced source leakage (GISL). GISL is also modeled in the BSIM-IMG model using the above formulation with a change in the electric field calculation and model parameters. The electric field for GISL current calculation is Es 5

2 Vfg 2 EGISL 1 Vfbsd 1 VBGISLUγ 0 UðVbgs 2 Vfbsdbg 2 VBEGISLÞ Eratio UEOT1 (4.4)

4.1.3 Gate Oxide Leakage For improving the control of gate on the channel and in turn improve the short-channel performance, gate oxide thickness has been continuously reduced with the progression of the technology. As the thickness of gate dielectric gets reduced, the probability of carriers tunneling from gate to channel and to source/drain overlap regions increases exponentially, giving rise to gate oxide leakage. As a result, in advanced technology nodes, gate oxide leakage can be quite significant and needs a careful modeling effort for the accurate prediction of device behavior.

69

Leakage Current and Thermal Effects

Figure 4.3 Different components of gate current in a MOSFET.

The tunneling current can flow between (1) gate and the body of the device, (2) gate and the channel region, and (3) gate and the source/drain via the overlap regions as shown in Fig. 4.3. All of these components are accurately modeled in BSIM-IMG model. These model formulations in BSIM-IMG have been inherited from BSIM4 compact model. These were originally derived for polysilicon gate and silicon-dioxide gate dielectric. However, it is found that due to their excellent flexibility, these formulations work very well for tunneling in metal gate and gate oxide dielectric formed with high-k material too. 4.1.3.1 Gate-to-Body Tunneling Current The tunneling current from gate to body of the device depends on the bias conditions. For device biased in strong inversion region, it is the electrons (holes) in the channel of NMOS (PMOS), which tunnel toward the gate. This is modeled with following model formulations:


 kT qia 2 EIGBINV Vaux 5 NIGBINVU Ulog 1 1 exp (4.5) q NIGBINVUðkT =qÞ Igbinv 5 W ULUNUFUAUTox UVgbg UVaux UIgtemp Uexpð2 BUTOXPðAGBINV 2 qiaUBGBINV Þð1 1 qiaUCGBINV ÞÞ (4.6) where NIBGINV, EIGBINV, AGBINV, BGBINV, and CGBINV are model parameters. TOXP is physical oxide thickness, as oppose to electrical thickness used in drain-current calculations. A and B are physical constants originating from tunneling physics. qia is normalized average channel charge, and Vgbg is voltage between front and back gates.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Igtemp models the temperature dependence of gate current. For modeling the tunneling current in accumulation region, similar model formulations are used with model parameters NIGBACC, EIGBACC, AGBACC, BGBACC, and CGBACC. Total gate-to-body current Igb is the sum of Igbacc and Igbinv. Most of Igb flows toward the source due to the lower barrier. To ensure continuity when Vds is changed from negative to positive, total Igb is divided into Igbs and Igbd in the BSIM-IMG model as follows:
 0:6Vds T0 5 tanh (4.7) Vt Wf 5 0:5 1 0:5:T0

(4.8)

Wr 5 0:5 2 0:5:T0

(4.9)



Igbs 5 Wf U Igbinv 1 Igbacc

(4.10)



Igbd 5 Wr U Igbinv 1 Igbacc

(4.11)

where Vt is the thermal voltage. For large positive Vds, T0 in Eq. (4.7) approaches unity resulting in Wf approaching unity and Wr approaching zero. This ensures that most of the Igb flows toward the source terminal. This situation lets reversed when a negative Vds is applied ensuring physical behavior and continuity of the BSIM-IMG model. 4.1.3.2 Gate-to-Channel Tunneling Current For an NMOS device, electrons from channel region can tunnel to the gate as shown in Fig. 4.4. The gate-to-channel tunneling current is calculated using the following model formulations:

T0 5 qiaU Vgbg 2 0:5Vdsx 1 0:5Vbgs 1 0:5Vbgd (4.12) Igc0 5 W ULUNUFUAUTox UT0 UIgtemp Uexpð2 BUTOXPðAIGC 2 qiaUBIGC Þ ð1 1 qiaUCIGC ÞÞ (4.13) where AIGC, BIGC, and CIGC are model parameters. Vdsx is drain-tosource voltage smoothed for model continuity around zero voltage. Vbgs(d) are back-gate to source (drain) voltage. A and B are tunneling constants.

Leakage Current and Thermal Effects

71

Figure 4.4 Energy band diagram showing electron tunneling from channel to gate.

Igc flows to both source and the drain terminals as shown in Fig. 4.3. The component from gate-to-source is calculated as Igcs 5 Igc0 U

PIGCDUVdseff 1 expðPIGCDUVdseff Þ 2 1024 2 2 2U1024 PIGCD2 UVdseff

(4.14)

Igcd 5 Igc0 U

PIGCDUVdseff 1 expðPIGCDUVdseff Þ 2 1024 2 2 2U1024 PIGCD2 UVdseff

(4.15)

The Eqs. 4.14 and 4.15 for Igcs and Igcd ensure the correct division of total gate-to-channel current between source and drain terminals. This formulation also ensures physical behavior that Igcs and Igcd are zero when the applied Vds is zero. 4.1.3.3 Gate-to-Source (Drain) Tunneling Current Tunneling can also occur in the overlap regions at both source and drain side. This current is modeled in BSIM-IMG model with following formulations:
NTOX W UA TOXREF Igsmult 5 Igtemp U U ðTOXPUPOXEDGEÞ2 ðTOXPUPOXEDGEÞ (4.16) where Igtemp captures the temperature dependence of the gate current, POXEDGE is a factor for gate edge thickness adjustment that can be slightly different than gate oxide thickness in the main channel region, NTOX is the exponent for gate oxide thickness, and TOXREF is the nominal gate oxide thickness for gate tunneling current.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Igs 5 NFUIgsmult UDLCIGSUVgs2 Uexpð2 BUTOXPUPOXEDGE UðAIGS 2 Vgs UBIGS Þð1 1 Vgs UCIGS ÞÞ

(4.17)

Igd 5 NFUIgdmult UDLCIGDUVgd2 Uexpð2 BUTOXPUPOXEDGE UðAIGD 2 Vgd UBIGD Þð1 1 Vgd UCIGD ÞÞ

(4.18)

where AIGS(D), BIGS(D), and CIGS(D) are model parameters. DLCIGS and DLCIGD are the gate overlap lengths at the source and at the drain terminals. A and B are tunneling constants.

4.2 THERMAL EFFECTS AND THEIR MODELING The bulk MOSFET transistors have driven the semiconductor industry for decades, thanks to scaling. However, scaling in submicron regime is very challenging due to poor gate control, random dopant fluctuation, and various short-channel effects [1]. Thin buried oxide (BOX) FDSOI devices (see Fig. 4.5) offer good electrostatic control over the channel region and have threshold voltage tuning facility through back bias [2
6]. However, they are subjected to more device heating compared to bulk MOSFET transistors due to the lower thermal conductivity of BOX [7
9].

4.2.1 Modeling of Self-Heating Effect In the BSIM-IMG model, we have modeled the self-heating effect (SHE) by a thermal network (i.e., an equivalent resistance and capacitance (RC) circuit) as shown in Fig. 4.6. The values of thermal resistance (Rth) and

Figure 4.5 FDSOI transistor structure using Sentaurus TCAD Tool [10,11]. (A) 3D view and (B) cross-section view of 3D device. FDSOI, Fully depleted silicon-on-insulator; TCAD, technology computer-aided design.

Leakage Current and Thermal Effects

73

Figure 4.6 R
C network for self-heating calculation [12,13].

thermal capacitance (Cth) scale with width and are obtained using following equations: WTH0 1 Weff UNF 1 5 Rth RTH0

(4.19)

Cth 5 CTH0UðWTH0 1 Weff UNFÞ

(4.20)

where RTH0 and CTH0 are model parameters corresponding to normalized thermal resistance and thermal capacitance, respectively. WTH0 refers to the minimum width for the calculation of the thermal resistance. NF is the number of fingers, and Weff is the effective gate width. The SHE-induced temperature rise (ΔTSHE) is calculated by SPICE engine by introducing an internal temperature node (T) to this thermal network [12]. When model has self-heating mode ON (i.e., SHMOD 5 1), the power dissipated in the transistor (Ids  Vds) is supplied to the thermal network, and the voltage drop across the network results in an increase in temperature (ΔTSHE). This increase in temperature is then added to the device temperature (TDEVICE 1 ΔTSHE). The geometrical dependence of thermal resistance can be further improved as demonstrated in work [11] as follows: " !# Rtha 1 (4.21) Rth 5 α RTHL 1 Wg Lgβ 1 ΔL th where Lg and Wg are the normalized (to 1 μm) channel length and width, respectively, and Rtha is the model parameter. Rth has nonlinear dependence on Lg as dominant heat flow paths are different at different channel lengths. This behavior is also observed in experimental data [11] as shown in Fig. 4.7 (NMOS devices) and Fig. 4.8 (both NMOS and PMOS devices). This nonlinearity in Rth is captured by a parameter β in (4.21). Rth has weaker Lg dependence for short-channel devices because contacts

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 4.7 Rth variation with channel length (Lg). Rth1 5 21, RTHL 5 0.0031 ΔLth 5 0.07. Symbols: the experimental data [11]; Lines: the BSIM-IMG model.

Figure 4.8 Rth versus channel length (Lg) characteristic for NMOS and PMOS devices. The model shows excellent agreement with the experimental data [11] for both NMOS and PMOS devices. For NMOS, parameter values are Rth1 5 2.75, RTHL 5 0.03, ΔLth 5 0.24, and β 5 0.78. For PMOS, parameter values are Rth1 5 2.15, RTHL 5 0.03, ΔLth 5 0.0748, and β 5 0.5. Symbols: the experimental data [11]; Lines: the BSIM-IMG model.

do not scale with Lg (as shown by plateau in Fig. 4.7). The channel length below which Rth has weaker Lg dependence is captured by parameter ΔLth in (4.21). For short-channel devices, Rth becomes function of ΔLth and Rth1 as shown in (4.22).

Leakage Current and Thermal Effects

75

Figure 4.9 Importance of parameter RTHL in Rth modeling is illustrated. Rth versus channel length (Lg) characteristic for NMOS device with channel width Wg 5 10 mm, oxide thickness Tox1 5 1.9 nm, buried oxide thickness Tbox 5 10 nm, and body thickness Tsi 5 12 nm. Parameter values are Rth1 5 13, ΔLth 5 0.17 and β 5 1, α 5 0.95. Symbols: TCAD data, Lines: the BSIM-IMG model.

Rth 5

Rtha 1 Wgα ΔLth

(4.22)

Parameter RTHL is extracted  for very long  channel length devices, β characterized by RTHLc 1= ΔLth 1 Lg , thus Rth becomes Eq. (4.23). Importance of parameter RTHL in fitting thermal resistance behavior for very long channel length transistors is shown in Fig. 4.9. Rth 5

Rth1 RTHL Wgα

(4.23)

The heat flow plane from the channel into the BOX is like half cylinder for large widths where heat flows through substrate. However, the heat flow plane from the channel into the BOX is like half sphere for narrow widths where heat flow from substrate-to-gate and source-todrain is comparable to substrate [14]. Thus 1/W dependence of thermal resistance is valid for large width devices but deviates in narrow width devices [11]. This deviation is captured by using power dependence on width as shown in (4.21). The importance of power α is shown in Figs. 4.10 and 4.11.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 4.10 Rth versus channel length (Lg) characteristic for NMOS device (Tox1 5 1.9 nm, Tbox 5 10 nm, and Tsi 5 12 nm) for different channel widths (0.1, 0.24, 0.48, 1, 5, and 10 mm). Rth1 5 13, RTHL 5 0.8, ΔLth 5 0.17 and β 5 1, α 5 0.95. Symbols: TCAD data; Lines: the BSIM-IMG model.

Figure 4.11 Rth versus 1/Wg characteristic for NMOS device for different channel lengths (0.03, 0.05, 0.1, 0.5, 5, and 10 mm). Rth1 5 13, RTHL 5 0.8, ΔLth 5 0.17 and β 5 1, α 5 0.95. Symbols: TCAD data; Lines: the BSIM-IMG model.

4.2.2 Temperature Dependence of Parameters Self-heating-induced temperature rise (ΔTSHE) leads to higher device temperature, which degrades device parameters, such as bandgap, intrinsic carrier concentration, threshold voltage, carrier mobility, and carrier saturation velocity [15]. This degradation in device parameters gets reflected

Leakage Current and Thermal Effects

77

in the degradation of drain current, which must be modeled accurately for reliable circuit simulations. 4.2.2.1 Bandgap Temperature Dependence With temperature rise, interatomic space between atoms reduces, which results in the lowering of energy bandgap [16]. In BSIM-IMG model, we have modeled temperature dependence of energy bandgap as [17] Eg 5 BG0SUB 2

TBGASUBUT 2 T 1 TBGBSUB

(4.24)

where T is the temperature (in kelvins), and BG0SUB is a parameter that represents the bandgap (Eg) at T 5 TNOM. TBGASUB and TBGBSUB are the bandgap temperature coefficients, and TNOM is room temperature (300K). 4.2.2.2 Temperature Dependence of the Intrinsic Carrier Concentration At very high temperatures, energy bandgap starts reducing, which increases ni (cdopant concentration); as a result, semiconductor becomes intrinsic, while at lower temperatures dopant nonionization takes place. Thus intrinsic carrier concentration is modeled as
3=2
 Eg T BG0SUB ni 5 NI0SUBU Uexp 2 (4.25) TNOM 2kUTNOM 2kUT where parameter NI0SUB is representing ni at T 5 TNOM. 4.2.2.3 Temperature Dependence of Nc, Vbi, ΦB, and ΦSUB The temperature dependence of the conduction band density of states, source
drain built-in potential, and Fermi potentials at body, substrate regions are given by
3=2 T Nc 5 NC0SUBU (4.26) TNOM
 kT NSDUNBODY Uln Vbi 5 q n2i

(4.27)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design


 kT NBODY Uln ΦB 5 q ni

(4.28)


 kT NBG Uln ΦSUB 5 q ni

(4.29)

where Nc is the conduction band density of states, Vbi is source
drain built-in potential. ΦB and ΦSUB are the Fermi potentials at body and substrate regions, respectively. Parameter NC0SUB represents Nc at TNOM. Parameters NSD, NBODY, and NBG are representing the doping concentration in source/drain, body, and substrate regions. 4.2.2.4 Temperature Dependence of Threshold Voltage The modified device temperature is used to calculate threshold voltage shift (Vth,temp) caused by SHE (see Fig. 4.12). The accurate Vth,temp is used to calculate surface potential and drain current in the model. This increase in device temperature and corresponding decrease in drain current are optimized by SPICE till convergence is achieved. We have used four parameters, KT1, KT2 and KT1L, KT2L, to have more flexibility during parameter extraction procedure. Parameters KT1L and KT2L are especially used to capture length dependence effect on threshold voltage of device while including temperature effects in the model.

 KT1L T ΔVth;temp 5 KT1 1 U 21 Leff TNOM 

KT2L T 2 1 UVbg (4.30) U 1 KT2 1 Leff TNOM 4.2.2.5 Temperature Dependence of Mobility Carrier mobility in inversion layer depends on three major scattering mechanisms, that is, coulomb, phonon, and surface roughness scattering [18]. Coulomb scattering becomes dominant at very low temperatures, while at higher temperatures, two competing effects come into play. First, the average thermal energy of the carrier increases, and thus more carriers can surmount the barriers and participate in current conduction. On the other hand, carrier mobility decreases due to increase in lattice vibrations (phonon scattering) [19]. As a result, the subthreshold current increases,

Leakage Current and Thermal Effects

79

ΔTDEVICE = TDEVICE + ΔTSHE

Transistor parameters calculation: ni (T), Eg(T ), Vt = kT q

Threshold voltage shift calculation:

Vth,temp

Effective front-gate voltage calculation:

Vfgeff = Vfg – Vth,temp

Surface potential calculation

Source/Drain charge calculation

Mobility, saturation velocity, and series resistance calculation

Drain current impact ionization, and GIDL current calculation

ΔTSHE = 0.0K

OFF

Selfheating mode

ON

ΔTSHE ↑

Figure 4.12 An illustration of compact modeling approach for the inclusion of selfheating effect in the BSIM-IMG model.

and strong inversion current reduces due to mobility reduction with temperature (see Fig. 4.13). The temperature dependence of low-field mobility can be expressed as
UTE T μ0 ðT Þ 5 U0U 1 UTLUðT 2 TNOM Þ (4.31) TNOM

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 4.13 Ids versus Vfg characteristics for L 5 961 nm and L 5 52 nm in logarithmic scale (top) and Ids versus Vfg characteristics for L 5 961 nm and L 5 52 nm in linear scale (bottom) with temperature set at T 5 240°C, 25°C, and 85°C. Bias conditions are |Vds| 5 0.05 V (linear mode) and Vbg 5 0.0 V. Symbols: Data [20], Lines: the BSIMIMG model.

Parameters UTE and UTL are the mobility temperature coefficients. In the mobility model, other mobility parameters also have temperature dependence as ETAMOBðT Þ 5 ETAMOBU½1 1 EMOBTUðT 2 TNOM Þ

(4.32)

UAðT Þ 5 UA 1 UA1UðT 2 TNOM Þ

(4.33)

UCðT Þ 5 UC 1 UC1UðT 2 TNOM Þ

(4.34)


UD1 T UDðT Þ 5 UDU TNOM

(4.35)


UCSTE T UCSðT Þ 5 UCSU TNOM

(4.36)

Leakage Current and Thermal Effects

81

where parameters U0, ETAMOB, UA, UC, UD, and UCS are extracted at TNOM. Parameter UA1 is the mobility temperature coefficient for UA, and UC1 is the mobility temperature coefficient for UC. Parameters UD1 and UCSTE are the mobility temperature coefficients. 4.2.2.6 Temperature Dependence of Drain-Induced Barrier Lowering To have extra flexibility in short-channel parameter extraction, parameter TETA0 is used to capture temperature dependence on DIBL-induced threshold voltage shift. ETA0ðT Þ 5 ETA0Uð1:0 1 TETA0UðT 2 TNOM ÞÞ

(4.37)

where parameter ETA0 is extracted at TNOM. Parameter TETA0 captures temperature dependence for DIBL effect. 4.2.2.7 Temperature Dependence of Velocity Saturation At higher temperatures, electron velocity in the channel reduces due to lattice vibrations. Thus the temperature dependence of saturation velocity is modeled as VSATðT Þ 5 VSATUð1 2 ATUðT 2 TNOM ÞÞ

(4.38)

VSAT1ðT Þ 5 VSAT1Uð1 2 ATUðT 2 TNOM ÞÞ

(4.39)

VSATBðT Þ 5 VSATBUð1 2 ATBUðT 2 TNOM ÞÞ

(4.40)

VSATCVðT Þ 5 VSATCVUð1 2 ATUðT 2 TNOM ÞÞ

(4.41)

PTWGðT Þ 5 PTWGUð1 2 PTWGTUðT 2 TNOM ÞÞ

(4.42)

MEXPðT Þ 5 MEXPUð1:0 1 TMEXPUðT 2 TNOM ÞÞ

(4.43)

where parameters VSAT, VSAT1, VSATB, VSATCV, PTWG, and MEXP are extracted at TNOM. Parameter AT is the saturation velocity temperature coefficient, parameter TMEXP is the temperature coefficient for smoothing function factor for Vdsat. Parameter ATB is the back bias sensitivity parameter for saturation velocity temperature coefficient, and parameter PTWGT is the temperature coefficient of parameter PTWG.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

4.2.2.8 Temperature Dependence of Leakage Currents The empirical relation between leakage current and temperature is given as • Gate current
IGT T Igtemp 5 (4.44) TNOM

•

•

Temperature dependence of gate current is obtained by multiplying Igtemp factor with the gate current value extracted at TNOM. Parameter IGT is the gate current temperature coefficient. Gate-induced drain/source leakage BGIDLðT Þ 5 BGIDLUð1 1 TGIDLUðT 2 TNOM ÞÞ

(4.45)

BGISLðT Þ 5 BGISLUð1 1 TGISLUðT 2 TNOM ÞÞ

(4.46)

where the parameters BGIDL and BGISL are extracted at TNOM. Parameter TGIDL is the GIDL temperature coefficient, while TGISL is the GISL temperature coefficient. Impact ionization
IIT T BETA0ðT Þ 5 BETA0U (4.47) TNOM where parameter BETA0 is extracted at TNOM, and parameter IIT is the impact ionization temperature coefficient.

4.2.2.9 Temperature Dependence of Parasitic Source/Drain Resistances Parasitic source/drain resistances reduce the drain current. Thus an accurate modeling of parasitic resistances is important, which we have already discussed in detail in Chapter 3. Parasitic source/drain resistance consists of three resistances, that is, contact resistance, diffusion resistance, and spreading resistance at the edge of the inversion layer. These resistances show different temperature coefficients due to different materials and doping concentrations [21]. Model captures the temperature dependence of all these resistances as RDSWMINðT Þ 5 RDSWMINUð1 1 PRTUðT 2 TNOM ÞÞ RDSWðT Þ 5 RDSWUð1 1 PRTUðT 2 TNOM ÞÞ

(4.48) (4.49)

Leakage Current and Thermal Effects

83

RSWMINðT Þ 5 RSWMINUð1 1 PRTUðT 2 TNOM ÞÞ

(4.50)

RDWMINðT Þ 5 RDWMINUð1 1 PRTUðT 2 TNOM ÞÞ

(4.51)

RSWðT Þ 5 RSWUð1 1 PRTUðT 2 TNOM ÞÞ

(4.52)

RDWðT Þ 5 RDWUð1 1 PRTUðT 2 TNOM ÞÞ

(4.53)

Rs;geo ðT Þ 5 Rs;geo Uð1 1 PRTUðT 2 TNOM ÞÞ

(4.54)

Rd;geo ðT Þ 5 Rd;geo Uð1 1 PRTUðT 2 TNOM ÞÞ

(4.55)

where parameters RDSWMIN, RDSW, RSWMIN, RDWMIN, RSW, RDW, Rs,geo, and Rd,geo are extracted at TNOM. Parameter PRT is series resistance temperature coefficient.

4.2.3 Impact of Ambient Temperature on Thermal Resistance Silicon material thermal conductivity decreases with ambient temperature [22], which does not allow heat to flow out easily. This obstruction in heat flow raises the device temperature (ΔT 5 TDEVICE 2 TNOM) and leads to increment in Rth with ambient temperature. Thus we have modeled Rth as a linear function of ambient temperature as [23] RTHTemp 5 Rth ½1 1 RTHT 3 ΔT 

(4.56)

where RTHT is the slope of rise in Rth versus temperature (T) characteristic and is used as a fitting parameter for capturing the dependence of ambient temperature on Rth. Rth is the thermal resistance at T 5 300K. To quantify the effect of self-heating on device characteristics, we have simulated the device for different ambient temperatures ranging from 240°C to 125°C. Fig. 4.14 shows Ids versus Vds characteristics of an FDSOI transistor with and without SHE. When self-heating mode is activated (SHMOD 5 1), the drain current reduces as compared to the draincurrent value at SHMOD 5 0. For large values of thermal resistance (RTH0), drain current starts decreasing with drain voltage, which causes negative output conductance gds. The model can accurately capture the SHE on drain current at different ambient temperatures and shows

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Drain current (mA)

10 8

T = –40ºC

Vfg = 1.2 V

NMOS To x= 1.9 nm

Vbg = 0.0 V

Tbox = 10 nm Tsi = 12 nm

6 T = 125 º C 4 Model TCAD data without Self-heating TCAD data with Self-heating

2 0 0.0

0.2

0.4

0.6

0.8

1.0

1.2

Drain volatge (V) Figure 4.14 Ids versus Vds characteristic with temperature set at T 5 2 40°C, 25°C, and 125°C. Bias conditions are Vfg 5 1.2 V and Vbg 5 0 V. Device dimensions are channel length Lg 5 30 nm, gate width Wg 5 10 μm, front-gate oxide thickness Tox 5 1.9 nm, back-gate oxide thickness Tbox 5 10 nm, and channel silicon thickness Tsi 5 12 nm. Symbols: TCAD data, Lines: the BSIM-IMG model.

excellent agreement with TCAD data as demonstrated in Fig. 4.14. The benchmark test to check correct implementation of the SHE is shown in Chapter 7.

4.2.4 Frequency Dependence of Self-Heating Effect Small-signal voltage gain in analog circuits and the propagation delay in digital circuits depend on output conductance (gds). gds of FDSOI MOSFET is dependent on both frequency and temperature. For RF applications, it is necessary to capture these dependencies in a compact model [24]. As the frequency of the applied small signal increases, the device temperature gradually loses its ability to follow the applied signal [25]; as a result, δIds (i.e., the change in small-signal drain current) increases. This increment in δIds reflects as increase in gds (see Fig. 4.15) up

to certain frequency called isothermal frequency, fiso 5 1=ðRth 3 Cth Þ [26]. The isothermal frequency is used to determine the device thermal time constant. From work [26], we know that the isothermal frequency of this device is around 20 MHz. The first transition in Real Y22 curve is achieved around 20 MHz; hence, parameters related to SHE are extracted in the following frequency range 105 2 107 Hz (i.e., below the isothermal frequency, where thermal contribution dominates over electrical contribution). Fig. 4.15 shows that first-order thermal network is accurately

Leakage Current and Thermal Effects

85

Figure 4.15 Measured and extracted real part of Y22 using first-order thermal network. Device dimensions are channel length Lg 5 100 nm, gate width Wg 5 0.5 μm, number of fingers NF 5 60, front-gate oxide thickness Tox 5 1.2 nm, back-gate oxide thickness Tbox 5 10 nm, and channel silicon thickness Tsi 5 8 nm. Bias conditions are Vfg 5 Vds 5 1.1 V and Vbg 5 0 V. Symbols: Experimental data [26], Lines: the BSIM-IMG model.

capturing Real Y22 variation with frequency up

to 20 MHz [27,28]. Beyond isothermal frequency fiso . 1=ðRth 3 Cth Þ , gds further increases due to the gate and substrate effects [29,30]. These effects are discussed in detail in Chapter 3. 4.2.4.1 Extraction of Rth, Cth Small-signal AC conductance technique [12] is one of the methods to extracted device’s thermal resistance from gds versus frequency characteristic as shown in Fig. 4.15. ΔGSHE is the difference of Real Y22 value between the isothermal frequency [26] and asymptotes low-frequency

[12], and the slope of Ids versus temperature dIds =dT is determined from the hot chuck measurement as shown in Fig. 4.16. Rth 5

ΔGSHE

Ids U dIds =dT

(4.57)

From hot chuck measurement method, Rth comes around 505.8 K/W. As dynamic self-heating is more pronounced below the isothermal frequency, thus Cth is extracted by fitting the Real Y22 data till isothermal frequency.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 4.16 Hot chuck measurement result is used to determine the slope of Ids versus temperature (T) for Lg 5 100 nm, Wg 5 0.5 μm, and NF 5 60. A line is drawn to show trend. Bias conditions are Vfg 5 Vds 5 1.1 V.

REFERENCES [1] S. Markov, A. Zain, B. Cheng, A. Asenov, Statistical variability in scaled generations of n-channel UTB-FD-SOI MOSFETs under the influence of RDF, LER, OTF and MGG, in: Proc. of SOI Conference, 2012, pp. 1
2. [2] J.P. Noel, O. Thomas, M.A. Jaud, O. Weber, T. Poiroux, C. Fenouillet-Beranger, et al., Multi-vt UTBB FDSOI device architectures for low-power CMOS circuit, IEEE Trans. Electr. Devices 58 (8) (2011) 2473
2482. [3] C. Fenouillet-Beranger, P. Perreau, L. Tosti, O. Thomas, J.P. Noel, O. Weber, et al., Low power UTBOX and back plane (BP) FDSOI technology for 32 nm node and below, in: Proc. of IEEE International Conference on IC Design Technology, 2011, pp. 1
4. [4] Q. Liu, A. Yagishita, N. Loubet, A. Khakifirooz, P. Kulkarni, T. Yamamoto, et al., Impact of back bias on ultra-thin body and BOX (UTBB) devices, in: Proc. of Symposium on VLSI Technology (VLSIT), 2011, pp. 160
161. [5] J. Colinge, FinFETs and Other Multi-Gate Transistors., Springer, 2007. [6] Q. Xie, C.J. Lee, J. Xu, C. Wann, J. Sun, Y. Taur, Comprehensive analysis of shortchannel effects in ultrathin SOI MOSFETs, IEEE Trans. Electr. Devices 60 (6) (2013) 1814
1819. [7] L. McDaid, S. Hall, P. Mellor, W. Eccleston, J. Alderman, Physical origin of negative differential resistance in SOI transistors, Electron. Lett. 25 (13) (1989) 827
828. [8] R. Tu, C. Wann, J. King, P.-K. Ko, C. Hu, An AC conductance technique for measuring self-heating in SOI MOSFET’s, IEEE Electron. Device Lett. 16 (2) (1995) 67
69. [9] E. Pop, R. Dutton, K. Goodson, Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices], Tech. Digest IEDM 12 (2003) 36.6.1
36.6.4. [10] Sentaurus Device User Guide, Synopsys, Inc., Mountain View, CA, Version Z2007.03, Mar. 2007. [11] P. Kushwaha, B.K.K., H. Agarwal, et al., Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG, Microelectr. J. 56 (2016) 171
176.

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[12] W. Jin, W. Liu, S. Fung, C. Chan-Philip, C. Hu, SOI thermal impedance extraction methodology and its significance for circuit simulation, IEEE Trans. Electr. Devices 48 (4) (2001) 730
736. [13] BSIMSOIv4.5.0 Technical Manual. [Online]. Available: ,http://www-device.eecs. berkeley.edu/bsim/?page 5 BSIMSOI_LR.. [14] P. Canfield, S. Lam, D. Allstot, Modeling of frequency and temperature effects in GaAs MESFETs, IEEE J. Solid-State Circ. 25 (1) (1990) 299
306. [15] BSIM4 Technical Manual. [Online]. Available: ,http://www-device.eecs.berkeley. edu/bsim/?page 5 BSIM4.. [16] H. Fan, Temperature dependence of the energy gap in semiconductors, Phys. Rev. 82 (1951) 900905. [17] Y. Varshni, Temperature dependence of the energy gap in semiconductors, Physica 34 (1) (1967) 149154. [18] C. Hu, Modern Semiconductor Devices for Integrated Circuits, Prentice Hall, 2010. [19] Y. Tsividis, Operation and Modeling of the MOS Transistor., Oxford, 2013. 2013. [20] Y. Morita et al., Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate, in: IEEE Symposium on VLSI Technology, 2008, pp. 166
167. [21] Y. Chauhan, FinFET Modeling for IC Simulation and Design, Academic Press, 2015. [22] D.J. Walkey, T.J. Smy, T. Macelwee, M. Maliepaard, Compact representation of temperature and power dependence of thermal resistance in Si, Inp and GaAs substrate devices using linear models, Solid-State Electron. 46 (6) (2002) 819
826. [23] C. Anghel, R. Gillon, A. Ionescu, Self-heating characterization and extraction method for thermal resistance and capacitance in HV MOSFETs, IEEE Electron Device Lett. 25 (3) (2004) 141
143. [24] F. Ichikawa, Y. Nagatomo, Y. Katakura, M. Itoh, S. Itoh, H. Matsuhashi, et al., Fully depleted SOI process and device technology for digital and RF applications, Solid-State Electron. 48 (6) (2004) 999
1006. [25] S. Makovejev, B. Kazemi-Esfeh, V. Barral, N. Planes, M. Haond, D. Flandre, et al., Wide frequency band assessment of 28nm FDSOI technology platform for analogue and RF applications, Solid-State Electron. 24 (6) (2015) 414
416. [26] M.A. Karim, Y.S. Chauhan, S. Venugopalan, A.B. Sachid, D.D. Lu, B.Y. Nguyen, et al., Extraction of isothermal condition and thermal network in UTBB SOI MOSFETs, IEEE Electron Device Lett. 33 (9) (2012) 1306
1308. [27] P. Kushwaha, H. Agarwal, S. Khandelwal, J.P. Duarte, A. Medury, C. Hu, et al., BSIM-IMG: compact model for RF-SOI MOSFETs, in: Proc. of IEEE International Conference on Device Research (DRC), 2015, pp. 287
288. [28] P. Kushwaha, S. Khandelwal, J.P. Duarte, C. Hu, Y.S. Chauhan, RF modeling of FDSOI transistors using industry standard BSIM-IMG model, in: accepted in IEEE Transactions on Microwave Theory and Techniques, May 2016. [29] S. Makovejev, V. Kilchytska, M.K.M. Arshad, D. Flandre, F. Andrieu, O. Faynot, et al., Self-heating and substrate effects in ultra-thin body ultra-thin BOX devices, in: Proc. of 12th International Conference on Ultimate Integration on Silicon (ULIS), 2011, pp. 1
4. [30] A.J. Scholten, G.D.J. Smit, R.M.T. Pijper, L.F. Tiemeijer, H.P. Tuinhout, J.L.P.J. van der Steen, et al., Experimental assessment of self-heating in SOI FinFETs, in: IEEE International Electron Devices Meeting (IEDM), 2009, pp. 1
4.

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CHAPTER 5

Model for Terminal Charges and Capacitances in BSIM-IMG Sourabh Khandelwal Macquarie University, Macquarie Park, New South Wales, Australia

5.1 INTRODUCTION Compact models need to accurately model not only the static current of the device but also its dynamic behavior. To capture the dynamic behavior of the device, accurate model of device capacitances and its terminal charges are required. This is needed for accuracy in time- and frequencydomain circuit simulations that are necessary in circuit design. An accurate model for capacitances is extremely critical as the timing properties of digital circuits depend on this. Many key properties of analog/RF circuits, such as bandwidth, frequency behavior, also need a very accurate capacitance model. Device capacitances and terminal charges depend on the bias conditions and the region of operation the device is in. Compact model needs explicit formulations for the terminal charges (and capacitances) that capture their variation with the bias. In addition to this requirement the model should be formulated in a manner that it satisfies the charge conservation principle for good convergence [1,2]. For charge conservation, BSIM-IMG has explicit formulations of the terminal charges such that the charge conservation is naturally satisfied. Capacitances between different terminals are obtained as the derivatives of the charges from the expressions of terminal charges as described in Section 5.2. Different physical effects in the device, such as drain-induced barrier lowering, quantum-mechanical effects, short-channel effects [3], affect the capacitances, and the model needs to account for these. These physical effects also affect the static drain current of the device; and hence, the model should capture this physical behavior in a consistent manner. This chapter describes how these critical requirements are met in BSIM-IMG model. As the model for terminal charges depends on the core model calculations (see Chapter 2: Core Model for Independent Multigate Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00005-4

© 2019 Elsevier Ltd. All rights reserved.

89

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

MOSFETs), BSIM-IMG charges models are described in Section 5.3 for the two different core models: fast and extended range core model.

5.2 CAPACITANCE CALCULATION FROM TERMINAL CHARGES The model of terminal charges needs to follow the law of charge conservation. This is extremely important for a good convergence of the model in circuit simulations. Failing this, unphysical charge is accumulated at nodes in the transient simulations leading to nonconvergence. This situation can be illustrated with an example as shown in Fig. 5.1. Fig. 5.1 shows two cases in which transient simulations are being performed: (A) bias-independent capacitor and (B) bias-dependent capacitor. For case (A) with a bias-independent capacitor, as simulator performs the transient analysis while the input voltage V linearly increases from time t 5 0 to t 5 t1, the amount of charge deposited on the capacitor is   Qdep 5 CU V ðt1Þ 2 V ðt0Þ (5.1)

Figure 5.1 Transient simulations for the case of: (A) bias-independent and biasdependent capacitor showing the unphysical residue charge in case (B).

Model for Terminal Charges and Capacitances in BSIM-IMG

91

Now, as the input voltage comes back to the original value at t 5 t2, the amount of charge released from the capacitor is   Qrel 5 CU V ðt2Þ 2 V ðt1Þ (5.2) One can see from Eqs. (5.2) and (5.1) that if V(t2) 5 V(t0), Qdep and Qrel are equal and opposite, which ensures that there is no unphysical charge accumulated at the node. This indicates that modeling biasindependent capacitive behavior as a circuit element capacitor causes no unphysical charge accumulation and does not negatively impact simulator convergence. However, when we analyze the case (B) of Fig. 5.1, the situation becomes different. The amount of charge deposited is     Qdep 5 C V ðt0Þ U V ðt1Þ 2 V ðt0Þ (5.3) While the amount of charge released is     Qrel 5 C V ðt1Þ U V ðt2Þ 2 V ðt1Þ

(5.4)

Now, one can see from Eqs. (5.3) and (5.4) that even though V(t0) 5 V(t2), Qdep and Qrel will not be equal and opposite due to the change in the value of the capacitor. As a result, there will be a small unphysical residue charge left. This can lead to nonconvergence in simulators. This situation can be avoided when instead of modeling the bias-dependent capacitive behavior as a capacitor element, it is directly modeled as a charge. By modeling the charge at the node as a function of voltage, one ensures to get the exact same charge if after transients the voltage reaches the same value such as the scenario represented in Fig. 5.1. This is illustrated with Fig. 5.2 where the capacitive behavior is now modeled by developing a model for the charge. As the charge is explicitly expressed as a function of voltage, it is guaranteed that if the voltage returns to the initial value, the charge will also do the same without any spurious accumulation. The capacitance of this system is the derivative of the charge model w.r.t. voltage V given by CðV Þ 5

dQðV Þ dV

(5.5)

It can be seen from Eq. (5.5) that the capacitance has the bias dependence; however, modeling it in the form of charge ensured conservation. This leads to correct physical behavior w.r.t. charge conservation principle. The device capacitances are bias dependent, and to adhere to charge conservation principle, they are modeled via the charge equations in BSIM-IMG model.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 5.2 Modeling the bias-dependent capacitor in the form of charge ensured charge conservation.

In order to ensure charge conservation in BSIM-IMG model, explicit formulas for charges are used, which satisfy the law of charge conservation naturally. The device capacitances are then derived from these terminal charges. Fully depleted silicon-on-insulator (FDSOI) has four terminals: front gate (fg), back gate (bg), source, and drain. In BSIM-IMG, charges associated with each of the terminals are calculated as ðL Qfg 5 W Qinv ðxÞUdx (5.6) 0

Qd 5 W

ðL 0

Qbg 5 W

x Qinv ðxÞUdx L

ðL

(5.7)

Qb ðxÞUdx

(5.8)

Qs 5 2 Qfg 2 Qbg 2 Qd

(5.9)

0

Model for Terminal Charges and Capacitances in BSIM-IMG

93

where x is a location in the channel with x 5 0 representing the source, and x 5 L the drain terminal, Qinv (x) is the inversion charge density at x, W and L are channel width and length, respectively. The above charge description satisfies the charge conservation automatically [4]. The device capacitances can be calculated from the model of terminal charges using the following: dQi dVj dQi Cii 5 dVi Cij 5 2

(5.10)

Eq. (5.10) can give all the device capacitances, where the indices i and j represent the terminals fg, bg, d, and s. When i 5 j, the capacitance is called self-capacitance, and they are called transcapacitances [5] otherwise. For a four-terminal FDSOI device, there are total 16 device capacitances; out of which, 9 are independent, and the rest 7 can be derived from them.

5.3 INTRINSIC TERMINAL CHARGE MODEL IN BSIM-IMG Terminal charges depend on the core surface-potential calculations. As described in Chapter 2, Core Model for Independent Multigate MOSFETs, BSIM-IMG has two different core models to cater to the different performance requirements of the model. This section describes the terminal charge model for both the core models of the BSIM-IMG model.

5.3.1 Terminal Charges in Fast Core Model Fast core model makes justifiable simplifying approximations to reach the solution for the calculation of the surface potential in the FDSOI device. The surface potential is calculated at both source and drain terminals of the FDSOI device. The terminal charges are then derived as the functions of source- (ψs1,s) and drain-end (ψs1,d) surface potentials. As seen in Eqs. (5.6)
(5.8), an expression for inversion charge density is required to derive the terminal charges. In FDSOI the exact expression of inversion charge density is complex. Nevertheless, for the fast core model BSIMIMG assumes the back gate does not enter inversion region of operation. For such a case, Qinv(x) can be expressed as [6,7]

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

   Cox2 CSi   Qinv ðxÞ 5 Cox1 Vfg 2 ψs1 ðxÞ 1 Vbg 2 ψs1 ðxÞ Cox2 1 CSi

(5.11)

where the symbols have the same meaning as described in Chapter 2, Core Model for Independent Multigate MOSFETs. Qinv(x) has two parts: the first term in Eq. (5.11) is the charge due to the front-gate-oxide capacitor, and the second term represents the back-gate-oxide capacitance in series with the silicon body capacitance CSi. In Eq. (5.11) the inversion charge density is expressed as a function of the surface potential at location x. To calculate the terminal charges from Eqs. (5.6)
(5.9), we need a relation between x and the surface potential. To this end, current continuity property of the channel current is used. The drain current at any location x can be expressed as  



W Qinv;s 1 Qinv;x kT Ids ðxÞ 5 μ Qinv;s 2 Qinv;x ψs1;x 2 ψs1;s 1 η x q 2 (5.12) Using Eqs. (5.7) and (5.6), x can be expressed in terms of the surface potential ψs1 as

W x 5 μCox1 ψs1 ðxÞ 2 ψs1;s I  ds  

ψs1 ðxÞ 1 ψs1;s ψs1 ðxÞ 1 ψs1;s kT   3 Vfg 2 1 1 γc 1 γ c Vbg 2 1η q 2 2 (5.13) where γc 5

1 Cox2 CSi Cox1 Cox2 1 CSi

(5.14)

Using Eqs. (5.12), (5.13), and (5.6), the front-gate charge expression can be derived. The derived mode for the total gate charge is given by ( )

2 ψ 1 ψ B ψ 2ψ s1;s s1;d s1;s s1;d

 (5.15) 1  Qfg 5 Cox1 WL Vfg 2 2 6 A 2 B ψs1;s 1 ψs1;d where A 5 Vfg 1 γc Vbg 1 η

kT 1 1 γc q

Model for Terminal Charges and Capacitances in BSIM-IMG

an



1 1 γc B5 2

95

(5.16)

Similarly using Eq. (5.5) with Eqs. (5.12)
(5.14), the total drain charge is derived to be (

Cox1 WL Vfg 1 γc Vbg 2 1 1 γ c Qd 5 2 " ψs1;s 1 2ψs1;d ðψs1;d 2ψs1;s Þ2  (5.17) 3 1B  3 6 A 2 Bðψs1;s 1 ψs1;d Þ #) ðψs1;d 2ψs1;s Þ3 2 2B  2 30 A2Bðψs1;s 1ψs1;d Þ Eq. (5.17) is derived by partitioning the total channel charge into the drain charge based on Ward
Dutton partitioning scheme that has been shown to be better for circuit convergence as compared to fixed-charge partitioning schemes. The total back-gate charge is derived as ðL  Cox2 CSi   Qbg 5 W Vbg 2 ψs1 ðxÞ Udx (5.18) 0 Cox2 1 CSi and is given by

 n o Qbg 5 γ c Qfg 2 WLCox1 Vfg 2 Vbg

(5.19)

The total source charge is calculated by using the charge conservation law as given in Eq. (5.9). This method of modeling preserves the law of charge conservation by derivation, and all the capacitances can be obtained from the derived charge expressions by using Eq. (5.10). Fig. 5.3 compares the capacitance model of BSIM-IMG with Technology Computer Aided Design (TCAD) simulations for Cfg,fg, Cbg,fg, Cd,fg, and Cs,fg, showing an excellent agreement between the two as the bias condition is swept from below threshold voltage to strong inversion condition. In Fig. 5.4, BSIM-IMG model capacitances, Cds, Csd, Css, and Cdd, are compared with TCAD. This also shows an excellent agreement between TCAD and BSIM-IMG model.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 5.3 Comparison of BSIM-IMG capacitance model with TCAD simulations of an FDSOI device. Lines: BSIM-IMG model and Symbols: TCAD.

Figure 5.4 Comparison of BSIM-IMG capacitance model with TCAD simulations of an FDSOI device. Lines: BSIM-IMG model and Symbols: TCAD.

The intrinsic charge model for extended range core model is described in the next subsection.

5.3.2 Intrinsic Charge Model in Extended Range Core Model The extended range core model in BSIM-IMG models the surface potential, including the back-side inversion effect accurately. Extended range

Model for Terminal Charges and Capacitances in BSIM-IMG

97

core model can be selected by the users by using the appropriate version of BSIM-IMG model. The details of this core model formulation are described in Chapter 2, Core Model for Independent Multigate MOSFETs. The terminal charge model for this new core model is described here. In extended range core model, surface potential at the drain and the source end are calculated as described in Section 3.2. The source and the drain terminal charges are derived as functions of the surface potentials.
 ψfgðs;dÞ Qfgðs;dÞ 5 qni exp (5.20) Vth where ψfg is the front-side surface potential at the source and the drain for corresponding charge calculations. Similarly, back-gate charges are calculated using the back-gate surface potential from the core calculations.
 ψbgðs;dÞ Qbgðs;dÞ 5 qni exp (5.21) Vth After the calculations of the front- and the back-gate charges at both the terminals, a linear charge approximation is used to calculate total front-gate (Qfg) and the back-gate charge (Qbg) as shown below. Qfg 5

Qfg;s 1 Qfg;d 2

(5.22)

Qbg 5

Qbg;s 1 Qbg;d 2

(5.23)

and

Using the linear approximation, the terminal charges at the drain and at the source are modeled as

2 Qfg;d 1 Qbg;d 1 Qfg;s 1 Qbg;s Qd 5 (5.24) 6 and



2 Qfg;s 1 Qbg;s 1 Qfg;d 1 Qbg;d Qs 5 6

(5.25)

In Fig. 5.5 a comparison is drawn for the capacitance from the fast core model and the extended range core model. The key difference is for the case when back-side inversion becomes prominent as apparent from Fig. 5.5.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 5.5 A comparison of front-gate capacitance calculated from the fast core and the extended range core model in BSIM-IMG model. Extended range core model is more accurate for regions in which back-side inversion effect is prominent. Solid lines: fast core; Dashed lines: extend range core; and Symbols: TCAD.

In Fig. 5.6, we show that the terminal charge model with the extended range core calculation is physical and scales correctly with varying channel thickness. The model results for front-gate capacitance are compared with TCAD simulations for three different channel thicknesses. TCAD and the model show an excellent agreement. Terminal charges also depend on real device effects as described in Section 5.1. This needs to be accounted for in the model for high accuracy. The details of modeling the effect of real device effects on the terminal charges and capacitances in BSIM-IMG are described in the next section.

5.4 MODELING THE IMPACT OF REAL DEVICE EFFECTS ON TERMINAL CHARGES Several of the real device effects described in Chapter 3, Channel Current Model With Real Device Effects in BSIM-IMG, also affect the terminal charges and capacitances of an FDSOI device. These effects are included in BSIM-IMG model as described in this section. The real device effects affecting the threshold voltage of the device (see Section 3.3) change the surface potential of the device. These effects

Model for Terminal Charges and Capacitances in BSIM-IMG

99

Figure 5.6 Comparison of front-gate capacitance model results with TCAD simulations. Lines: model and Symbols: TCAD.

include short-channel effect, body-doping effect, body-bias effect, draininduced barrier lowering, and reverse short-channel effect. These are accounted for in BSIM-IMG charge model as the terminal charges depend on the surface potential (see Eqs. 5.15, 5.17, and 5.19). The surface-potential calculation accounts for these effects via a calculation of effective gate voltage. This modeling methodology can be summarized in Fig. 5.7. In addition to the physical effects changing the threshold voltage of the device, mobility degradation, velocity saturation, and pinch-off effects are also found to impact the device capacitances. These effects are accounted for in the charge model of BSIM-IMG as discussed next.

5.4.1 Impact of Mobility Degradation It is found that the impact of variation of carrier mobility with vertical electric field on charge or capacitances is slightly different than the effect on the drain current. To model this phenomenon the vertical field dependence of carrier mobility used in charge model is given a separate set of model equations and parameters. The parameter ηCV (ETACV) that weighs in the amount of inversion and fixed charge which goes into the vertical electric field calculation for C
V is separate than the I
V model. The default values are same as that of the I
V model and is given by

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 5.7 Real device effects affecting threshold voltage of the device are accounted for in the terminal charge model in BSIM-IMG through the surfacepotential calculations.

 ηCV 5

1=3PMOS 1=2NMOS

(5.26)

As required, ηCV can be tuned to fit the C
V model better without affecting the I
V model fitting. The effective vertical electric field for C
V model is then calculated as

 Qinv;s 1 Qinv;d Cox1 EeffCV 5 1 qNA TSi ηCV (5.27) 2 εSi Using Eq. (5.27), the mobility degradation factor for C
V DmobCV is calculated as UD EU DmobCV 5 1 1 ðUAÞEeffCV 1

UCS 11 ðQis 1Qid Þ=2Cox1

(5.28)

DmobCV is used to calculate the effective mobility which goes further into the drain
source saturation voltage calculations used in the C
V model as detailed in Section 5.4.3.

5.4.2 Impact of Pinch-Off and Velocity Saturation The charge and capacitances also depend on pinch-off and velocity saturation effects. Under pinch-off condition, as the influence on drain voltage

Model for Terminal Charges and Capacitances in BSIM-IMG

101

Figure 5.8 Modeling methodology for the saturation and pinch-off effects in the terminal charges and capacitances.

on the channel charge becomes very small, the capacitance Cgd becomes extremely small. The impact of velocity saturation and the pinch-off effect on the terminal charges is included in the BSIM-IMG model also via the surface-potential calculations. The terminal charges depend on the drainside surface potential (see Eqs. 5.15, 5.17, and 5.19) that is calculated by the calculation of effective drain
source voltage (Vdseff). The calculation of effective drain
source voltage models the effect of velocity saturation and the pinch-off effect through the calculation of drain
source saturation voltage Vdsat. This is illustrated in Fig. 5.8.

5.4.3 Impact of Channel-Length Modulation The channel-length modulation effects reduce the effective channel length, in turn decreasing the intrinsic device capacitances that are proportional to

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

the channel length. This is accounted for in the C
V model in the following manner. The drain saturation electric field is calculated as EsatCV 5

2UVSATCV UDmobCV μ0

(5.29)

where VSATCV is the saturation velocity parameter for C
V model, DmobCV is the mobility degradation factor for C
V model given by Eq. (5.28), and μ0 is the low-field carrier mobility. The impact of CLM is modeled with a multiple to the charge calculations MCLMV given as
 Vds 2 Vdseff 1 MCLMCV 5 1 1 PCLMCV (5.30) ln 1 1 PCLMCV Vdsat 1 EsatCV Leff where PCLMCV is a model parameter. The inverse of the factor MCLMCV is then multiplied with all the terminal charges.

5.5 EXTRINSIC CAPACITANCE MODEL IN BSIM-IMG An FDSOI device has several capacitances in addition to the intrinsic terminal capacitances described in the previous sections. These additional capacitances are also called extrinsic capacitances. Extrinsic capacitances are also important for device behavior and need to be accounted for in the model very accurately [8]. This section describes the different extrinsic capacitances and their modeling methodology in BSIM-IMG model.

5.5.1 Outer Fringe Capacitance This capacitance is present due to the capacitive coupling from the gate metal to the source/drain contact metal vias as shown in Fig. 5.9. The outer fringe capacitance [9] is modeled as an equivalent parallel plate capacitor with the capacitance per unit width controlled by the fitting parameters CFS and CFD at the source and at the drain side, respectively. The charge associated with the outer fringe capacitance for capacitance between the gate and the source is modeled as Qfgs;ofs 5 Weff ;CV UCFSUVgs

(5.31)

Qfgd;ofd 5 Weff ;CV UCFDUVgd

(5.32)

and

Model for Terminal Charges and Capacitances in BSIM-IMG

103

Figure 5.9 Schematic diagram showing the source- and drain-side outer fringe capacitance Cs,of and Cd,of, respectively. These capacitances are modeled in BSIM-IMG model.

where Weff,CV 5 W 2 2 3 ΔW with W as the drawn width and ΔW models offsets in actual width as compared to the drawn width due to layout and fabrication margins.

5.5.2 Overlap Capacitance Model The gate electrode of the device may have a small overlap with the heavily doped source and drain regions of the device as shown in Fig. 5.9. These overlap regions effectively create another “parallel plate” like capacitance between gate and the source and the drain terminals. The overlap capacitance depends on the length of the overlap region and the frontgate-oxide thickness. If the source and the drain regions are doped very heavily, it can be assumed that under different voltage bias conditions, there is a negligible depletion region created in the overlap region. For such a device the overlap capacitance can be modeled as bias-independent capacitances. In BSIM-IMG, this is modeled with the following equation for the charge associated with the overlap capacitance between gate and source: Qfg;ovs 5 WeffCV ULOVSUCox1 UVgs

(5.33)

where LOVS is a model parameter representing the overlap regions length toward the source side. The equivalent charge model for the drain side is Qfg;ovd 5 WeffCV ULOVDUCox1 UVgd

(5.34)

For devices where source and drain overlap regions are not heavily doped, the assumption of no depletion in the overlap regions becomes invalid. This makes the overlap capacitances to be bias dependent [10]. The

104

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

applied bias changes the depletion region thickness in the overlap region affecting the capacitances. This is modeled in BSIM-IMG with following formulations:

T0 5 Vfbgs 2 Vfbsd 1 δ1 1 PCOVBS1 Vbgs 2 Vfbsdbg 2 PCOVBS0 (5.35)
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 Vfg;ov 5 T0 2 T02 1 4δ1 2 1 T2 5 CKAPPAS 2

"rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi # 4Vfg;ov 12 21 CKAPPAS



Qfg;ov;bias 5 NFUWeff ;CV UCGSL Vfgs 2 Vfbsd 2 Vfgs;ov 2 T2

(5.36)

(5.37)

(5.38)

where PCOVBS0 and PCOVBS1 are model parameters for capturing the back-gate bias dependence of the overlap capacitance, CKAPPAS and CGSL are model parameters capturing the front-gate bias dependence of the overlap capacitance, and δ1 is a smoothening constant. The total overlap charge is then Qfgs;ovt 5 Qfgs;ov 1 Qfgs;ov;bias

(5.39)

If CKAPPAS is set to zero, the overlap capacitance becomes bias independent with the value of per unit width capacitance to be CGSO 1 CGSL. CKAPPAS with the calculation shown for the variable T2 is modeling the impact of depletion region on the capacitance. The above formulations are described for the source-side overlap capacitance. Equivalent formulations with appropriate change in input voltages are used for the drain-side overlap capacitance in the BSIM-IMG model.

5.5.3 Source/Drain to Substrate Fringe Capacitance In an FDSOI device, substrate terminal is present below the buried oxide (BOX) layer as shown in Fig. 5.10. There are two paths for the electric fields originating from the source and the drain to terminate at the substrate terminal: (1) directly from source and drain terminal to the substrate through the BOX and (2) from the edge of source and drain regions through the silicon layer thickness and the BOX to the substrate terminal. Both these components are modeled in BSIM-IMG model with the

Model for Terminal Charges and Capacitances in BSIM-IMG

105

Figure 5.10 FDSOI device with fringe capacitance from source/drain terminal to the substrate connection below the BOX. BOX, Buried oxide.

following formulations. The first component depends on the area of the source and the drain regions and is modeled as Qsbg1 5 NFUCox2 UASUVsbg

(5.40)

where AS is the area of the source region and NF is the number of fingers in the device. The second component scales as the length of the source- and drainregion scales and is modeled as   Qsbg2 5 NFU ðPS 2 W ÞCsdbgsw0 Vsbg (5.41) where PS is the perimeter of the source region and Csdbgsw0 is given by
 TSI Csdbgsw0 5 CSDBGSW Uln 1 1 (5.42) EOT 2 The total source/drain terminal to substrate capacitance is the addition of two components described by Eqs. (5.40) and (5.41).

REFERENCES [1] P. Yang, B.D. Epler, P.K. Chatterjee, An investigation of the charge conservation problem for MOSFET circuit simulation, IEEE J. Solid State Circ. 18 (1) (1983) 128
138. [2] D.E. Root Nonlinear charge modeling for FET large-signal simulation and its importance for IP3 and ACPR in communication circuits, in: Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium, IEEE, vol. 2, 2001, pp. 768
772. [3] Y. Cheng, M.J. Deen, C.H. Chen, MOSFET modeling for RF IC design, IEEE Trans. Electron Devices 52 (7) (2005) 1286
1303. [4] D.E. Ward, R.W. Dutton, A charge-oriented model for MOS transistor capacitances, IEEE J. Solid State Circ. 13 (5) (1978) 703
708.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

[5] A.I. Cunha, M.C. Schneider, C. Galup-Montoro, An MOS transistor model for analog circuit design, IEEE J. Solid State Circ. 33 (10) (1998) 1510
1519. [6] S. Khandelwal, Y.S. Chauhan, D.D. Lu, S. Venugopalan, M.A. Karim, A.B. Sachid, et al., BSIM-IMG: a compact model for ultrathin-body SOI MOSFETs with backgate control, IEEE Trans. Electron Devices 59 (8) (2012) 2019
2026. [7] D.D. Lu, Compact Models for Future Generation CMOS., University of California, Berkeley, CA, 2011. [8] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue, Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies, IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 29 (2) (2010) 250
260. [9] A. Bansal, B.C. Paul, K. Roy, Modeling and optimization of fringe capacitance of nanoscale DGMOS devices, IEEE Trans. Electron Devices 52 (2) (2005) 256
262. [10] P. Klein, K. Hoffmann, B. Lemaitre, Description of the bias dependent overlap capacitance at LDD MOSFETs for circuit applications, in: Electron Devices Meeting, 1993. IEDM’93. Technical Digest International, IEEE, December 5, 1993, pp. 493
496.

CHAPTER 6

Parameter Extraction With BSIM-IMG Compact Model Harshit Agarwal Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, United States

Parameter extraction is an important part of compact model development. Compact model is built upon a core model derived with an assumption of ideal and long-channel device. In order to accurately describe the behavior of a real device, fitting parameters are necessary. Most of the time, the parameters have physical meaning, while they may also be associated with some empirical or phenomenological models. It is very common for different sets of parameter to give similar fitting results. However, one has to be cautious since setting parameter to extremely large or small (against expected value) or to unphysical value is not a good practice. It may give unexpected and unrealistic model results outside the geometry/ bias domain over which the parameter extraction was carried out. In fact, convergence of a model also depends on the extracted values of the parameters. BSIM-IMG, too, contains various parameters, and before parameter extraction one should have a picture of physical origin of that parameter. The parameters are classified into different types, and there is a systematic approach that should be followed for good overall fit.

6.1 BACKGROUND In general, there are two broad ways to categorize parameters: local and global. Local parameter reflects the physics at work and can have few other parameters which define the geometrical dependence of that parameter. For better understanding, consider U0 which represents the low field mobility of a carrier. The effective low field mobility (U0i) used in the BSIM-IMG model is given as U0i 5 U0 3 (1.0 2 UP 3 Lg2LPA). Here, U0 is a local parameter, and UP and LPA are the geometrical parameters which governs the behavior of U0 with gate length Lg. Likewise, there are several parameters which have geometrical dependence. If the Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00006-6

© 2019 Elsevier Ltd. All rights reserved.

107

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

extraction needs to be done for a single device, local parameters should be tuned. In order to extract parameters for a group of devices with different gate lengths and widths, both local and their geometrical parameters should be extracted. After the extraction, one parameter set will fit all the devices in the group [1]. In next section, we will discuss strategy for global extraction. Extended range model (see Chapter 2: Core Model for Independent Multigate MOSFETs, for more details) and fast core model have the same set of parameters, and the following procedure is valid for both the models.

6.1.1 First Step of Parameter Extraction BSIM-IMG has several advanced models, with flags to activate them, which may be important for some applications and less important for other. For example, the gate network which contains resistors/capacitors as a part of gate network is crucial for RF applications and may be of little importance for others. It is preferable to turn them off whenever not required by selecting the appropriate flag parameter, so that simulations are faster. All such modes should be identified and properly set before the parameter extraction. In addition, there are other parameters which are directly measurable or known, such as oxide thickness, permittivity of Table 6.1 Parameters that should be set before parameter extraction Parameter name description

EPSROX EPSRSUB EOT1 EOT2 NBODY NSD NGATE XW/XL L W NF TNOM GIDLMOD RGATEMOD RDSMOD

TYPE

Relative gate dielectric constant Relative dielectric constant of the channel Electrical gate equivalent oxide thickness of front gate Electrical gate equivalent oxide thickness of back gate Channel doping concentration S/D doping concentration 0: Metal gate, .0: Poly-gate doping Channel W/L offset due to mask/etch effect Designed gate length Designed gate width Number of fingers in parallel Nominal temperature 0: Off 1: On 0: Off 1: On 0: Fixed bias dependence, 1: External bias dependence 2: Both bias-dependent and geometry-dependent parts of source/drain resistance 21: PMOS, 1:NMOS

Parameter Extraction With BSIM-IMG Compact Model

109

gate dielectric. Value of all these parameters should also be fixed prior to parameter extraction. Table 6.1 lists some of these parameters.

6.2 EXTRACTION OF LARGE-SIZED DEVICE PARAMETERS Device with large length and width is used to extract parameters which are less affected by short/narrow-channel effects and parasitic resistance. Once these parameters are extracted, parameters related to short-channel and narrow-width effects are extracted.

6.2.1 Gate Capacitance CGG Versus VGS As a first step, process parameters and parameters related to quantum mechanical effect are extracted. Some of the parameters may have already been assigned to process parameters; however, a fine-tuning should be made in order to accurately fit the electrical behavior of the device. From CGG versus VGS curve at small VDS the following process parameters are extracted: NBODY, EOT1, EOT2 and NGATE, PHIG1, PHIG2. Each of these parameters affects a different region or in a different way. Further, capacitance behavior is affected by quantum mechanical effects; and therefore, parameters PQM, QM0, and ETAQM are also extracted from CGG versus VGS analysis. For VDS 5 VDD, VSATCV, PSATCV, and PCLMCV should be extracted. Fig. 6.1 shows the model’s C
V characteristics validation with experimental data for NMOS and PMOS at Vbg 5 0.0 V and |Vds| 5 0.0 V for long- and wide-channel devices. The model is showing correct behavior for all capacitances in all regions of operation from depletion to inversion.

6.2.2 Drain Current IDS Versus VGS at Small VDS In this step, VDS is set to small value, typically |VDS| 5 50 mV. The dependence of drain current on applied gate voltage is extracted from weak to strong-inversion region of operation. 6.2.2.1 Subthreshold Region In subthreshold region (VGS , VTH, where VTH represents the threshold voltage), drain current is an exponential function of gate voltage. It is important to fit both threshold voltage and subthreshold slope for an accurate modeling of off-current. IDS versus VGS is commonly plotted on a semilog plot and parameters PHIG1 (for threshold voltage) and CIT (for subthreshold slope) are extracted for VBG 5 0. For VBG6¼0, threshold

110

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 6.1 Normalized total gate capacitance Cfgfg versus Vfg at Vbg 5 0.0 V. (A) NMOS device and (B) PMOS device, with device dimensions (W 5 2160 μm, L 5 961 nm) and (W 5 3360 μm, L 5 344 nm). Symbols: data [2]; lines: the BSIM-IMG model [3].

voltage shifts linearly with VBG in the absence of back-gate depletion. However, in the presence of back-gate depletion, it behaves nonlinearly with back-gate voltage. For this case the flag BPFACTORPW (for ptype well) or BPFAC-TORNW (for n-type well) is set, and the parameters VKNEE1PW (VKNEE1NW) are extracted. Extracted parameters

Device and experimental data

Extraction methodology

PHIG1, CIT

Long device IDS versus VGS @ VDS 5 VD,lin @ VBG 5 0.0 V Long device IDS versus VGS @ VDS 5 VD,lin @ VBG6¼0.0 V

Observe threshold voltage and subthreshold slope

CBGCBG0, CBGCBG0P, KBG0P(N)W, KBG2P (N)W, BP-FACTORP (N)W, VKNEE1P(N)W, VKNEE2P(N)W

Observe threshold voltage and subthreshold slope for different back bias

6.2.2.2 Strong-Inversion Region Carrier mobility and series resistance parameters should be extracted in strong inversion. This includes low field mobility U0, the parameter for the effective field ETAMOB, the parameters related to the effect

Parameter Extraction With BSIM-IMG Compact Model

111

of mobility reduction due to vertical field UA and EU and the parameters for the Coulomb scattering effect UD and UCS. UD and UCS may change the threshold voltage, and fine-tuning may be needed. For series resistance, depending on the choice of RDSMOD (internal or external S/D series resistances), RDSW, RSW, and RDW are extracted along with their bias dependence parameters PRWG and PRWB. Extracted parameters

Device and experimental data

Extraction methodology

U0, UA, EU, ETAMOB, UD, UCS, PRWG, RSW, RDW

Long device IDS versus VDS @ VDS 5 VD,lin @ VBG 5 0.0 V

UC, UDB, PRWB

Long device IDS versus VDS @ VDS 5 VD,lin @ VBG6¼0.0 V

Observe stronginversion region IDlin and gmlin in linear scale Observe stronginversion region IDlin and gmlin in linear scale

6.2.3 Drain Current IDS Versus VGS at VDS 5 VDD 6.2.3.1 Subthreshold Region For VBG 5 0, threshold voltage shift due to high drain bias is extracted by the parameter ETA0, and subthreshold swing is fitted by CDSCD. For VBG6¼0, extract ETAB and CBGCBGD. Extracted parameters

Device and experimental data

Extraction methodology

ETA0, CDSCD

Short and long devices IDS versus VGS @ VDS 5 VD,sat @ VBG 5 0.0 V Short and long devices IDS versus VGS @ VDS 5 VD,sat @VBG6¼0.0 V

Observe subthreshold region of all devices in the same plot

ETAB, CBGCBGD

Observe subthreshold region offset and slope

6.2.3.2 Strong-Inversion Region Drain current in the strong inversion is governed by the carrier velocity. The following parameters are extracted. For better results, these parameters should be tuned not only by observing IDS 2 VGS in saturation but also IDS 2 VDS.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Extracted parameters

Device and experimental data

Extraction methodology

VSAT, VSAT1, PTWG, KSATIV, MEXP

Long device and medium devices IDS versus VGS @ VDS 5 VD,sat @ VBG 5 0.0 V Long device and medium devices IDS versus VGS @ VDS 5 VD,sat @VBG6¼0.0 V

Observe strong-inversion region IDsat, gmsat

VSATB, PTWGB, PTWGB2

Observe strong-inversion region IDsat, gmsat

6.2.4 IDS and gDS Versus VDS Extract output conductance parameters from gDS fitting and fine-tune velocity saturation parameters obtained in previous step for overall IDS and gDS fits. gDS parameters include MEXP for IDS linear to saturation transition, PCLM and PCLMG for channel-length modulation and PDIBL2 for DIBL effect on gDS. At high VDS values, self-heating effect is also dominant, thus parameter RTH0 is also extracted in this region. Extracted parameters

Device and experimental data

Extraction methodology

MEXP, PCLM, PDIBL2, PVAG

IDS versus VDS @ different VGS @ VBG 5 0.0 V

Thermal resistance (RTH0) for the self-heating model

IDS versus VDS @ different VGS @ VBG 5 0.0 V

Observe strong-inversion region IDS versus VDS and gDS versus VDS @ different VGS @ VBG 5 0.0 V Observe data trend and tune RTH0

6.2.5 Note on Back Bias Effect on Threshold Voltage We have seen in Chapter 4, Leakage Current and Thermal Effects, that threshold voltage of the FDSOI transistor is a function of back-gate voltage. For highly doped substrate, substrate may not be depleted on the application of back bias. In such case, Vth varies linearly with VBG. However, in the presence of back-gate depletion in lightly doped substrate, it is a nonlinear function of VBG, and BPFACTORPW (or BPFAC-TORNW for N-type back gate) should be set to activate the model for back-gate depletion. Fig. 6.2 shows threshold voltage shift, Vth 2 Vth(Vbg 5 0), as a function of VBG obtained from TCAD for lightly doped substrate. Note the nonlinear behavior. If the measured data show such deviation from straight line behavior: (1) set VKNEE1PW

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Figure 6.2 Vth versus back-gate voltage Vbgs, NMOS with p-type substrate (p-well). The substrate depletion effect is turned off in the model [4].

Figure 6.3 Vth versus back-gate voltage Vbgs, NMOS with p-substrate (well), including substrate depletion effect [4].

(or VKNEE1NW) equal to the back-gate voltage at which the lines depart and (2) start increasing BPFACTORPW (or BPFACTORNW) and adjust VKNEE2PW (or VKNEE2NW) for a good fit. See Fig. 6.3 for the model results.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 6.4 Threshold voltage versus gate length characteristics for different back bias Vbg 5 [ 2 1.0, 0.0, 1.0] V at |Vds| 5 0.05 and 1.5 V. Dotted lines are showing that the substrate depletion effect is turned off in the model as parameter BPFACTOR 5 0. Solid lines are showing that the substrate depletion effect is turned on in the model as parameter BPFACTOR6¼0. Symbols: data [2]; lines: the BSIM-IMG model [3].

6.3 SHORT-CHANNEL DEVICE EXTRACTION AND LENGTH SCALING Once the parameters of wide- and long-channel device are extracted, next step is the extraction of the parameters that are either related to short-channel effects or express the different length dependencies. • Plot threshold voltage versus gate length characteristics as shown in Fig. 6.4. Vth tends to decrease as gate length scales down due to shortchannel effects. On the other hand, it may increase at intermediate lengths due to reverse short-channel effect. Parameters DVT0, DVT1, K1RSCE, and LPE0 are extracted based on Vth versus Lg characteristics. One should be able to get reasonable behavior of threshold voltage with gate length.

Parameter Extraction With BSIM-IMG Compact Model

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Extracted parameters

Device and experimental data

Extraction methodology

DVT0, DVT1, K1RSCE, LPE0, CDSC

Both short and medium devicesIDS versus VGS @ VDS 5 0.05 V @ VBG 5 0.0 V Both short and medium devices IDS versus VGS @ VDS 5 0.05 V @ VBG6¼0.0 V

Observe subthreshold region of all devices in the same plot

VKNEE1N(P)W, VKNEE2N(P)W, KBG0N(P)W, KBG1N(P), KBG2N (P), CBGCBG, CBGCBGP, CBGCBGD

•

Observe subthreshold region of all devices in the same plot

Extract scaling parameters of low field mobility: UP and LPA. Like threshold voltage, it is convenient to plot low field mobility versus gate length and then extract the parameter. In linear region, current is to the first order, governed by low field mobility and series resistance. Channel resistance of the transistor scales down with the channel length; and therefore, series resistance effect is even more pronounced in short-channel devices. Geometrical scaling parameters ARD(S)W, BRD(S)W of resistance should be extracted in linear region.

Extracted parameters

Device and experimental data

Extraction methodology

UP, LPA, AUA, AEU, AUC, AUD, AUDB, ARDSW, ARSW, ARDW, BUA, BEU, BUC, BUD, BUDB, BRDSW, BRSW, BRDW

Short and medium devices IDS versus VGS @ VDS 5 0.05 V @ VBG 5 0.0 V

Observe strong-inversion region Idlin and gmlin. Determine scaling parameters of U0, UA, UD, and RDSW that gives good fit to experimental data, varying them simultaneously

•

Plot threshold voltage versus gate length for VDS 5 VDD. In shortchannel devices, threshold voltage is relatively more sensitive to the drain voltage. This is modeled by the length-dependent parameter DSUB. Fine-tune ETA0 if needed.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Extracted parameters

Device and experimental data

Extraction methodology

ETA0, DSUB, ETAB

Both short and medium devicesIDS versus VGS @ VDS 5 VDD

Observe subthreshold region of all devices in the same plot

• •

Plot IDS versus VGS at VDS 5 VDD for all the devices. AVSAT and BVSAT which are scaling parameters of the long-channel parameter VSAT are extracted, similarly for PTWG. Output conductance parameter: Extract PDIBL1 and DROUT for DIBL impact on short-channel gds.

Extracted parameters

Device and experimental data

Extraction methodology

AVSAT, AVSAT1, APTWG, BVSAT, BVSAT1, BPTWG

Short and medium devices IDS versus VGS @ VDS 5 VDD, @ VBG 5 0.0 V Short and medium devices IDS versus VDS and gDS versus VDS

Observe stronginversion region of IDsat and gmsat

PDIBL1, DROUT, PVAG

•

Extract geometry parameter.

scaling

parameters

Should be cooptimized with IDS versus VGS for better results

for

smoothing

function

Extracted parameters

Device and experimental data

Extraction methodology

AMEXP, BMEXP

long and short devices IDS versus VDS @ different VGS

Observe data trend; extract AMEXP and BMEXP

A sample global fitting for long-channel and short-channel PMOS device is shown in the Figs. 6.5
6.7.

6.4 LEAKAGE CURRENT EXTRACTION 6.4.1 Gate-Induced Drain Leakage Gate-induced drain leakage (GIDL) is the band-to-band tunneling leakage at off state [5] as discussed in Chapter 4, Leakage Current and Thermal Effects. First, the selector GIDLMOD should be set to 1 to activate GIDL/gate induced source leakage (GISL) currents, and then the parameters AGIDL, BGIDL, EGIDL, and PGIDL are extracted. For different back biases, parameters VBGIDL and VBEGIDL should be extracted.

Parameter Extraction With BSIM-IMG Compact Model

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1x10–3 8x10

PMOS |Vds| = 0.05 V

–4

Symbols—measured data Lines—model

gm (A/V)

Vbg = –1.0, 0.0, 1.0 V 5x10–4 L = 961 nm W = 10 μm

3x10

L = 52 nm W = 10 μm

–4

0 5x10–4

10–4 PMOS OS |Vds| = 0.05 V

I ds ( A )

4x10– 4

10–9

3x10–4 2x10–4 1x10

10–14

L = 961 nm W = 10 μm L = 52 nm W = 10 μm

–4

0 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0.0

0.2

0.4

0.6

10–19 0.8

Front-gate voltage (V )

Figure 6.5 IDS versus VGS characteristics for PMOS device with Lg 5 961 nm and Lg 5 52 nm, Symbols: data [2]; lines: the BSIM-IMG model [3].

gm ′ (A / V 2)

L = 961 nm W = 10 μm 0

PMOS |Vds| = 0.05 V –2x10–4

Vbg = –1.0, 0.0, 1.0 V –4x10–4

gm′′(A/ V3)

2x10–3 1x10

PMOS |Vds| = 0.05 V

–3

Vbg = –1.0, 0.0, 1.0 V

0 –1x10–3 –2x10

Symbols—measured data Lines—model

–3

–1.0

–0.5

0.0

0.5

Front gate voltage (V)

Figure 6.6 First and second derivative of the transconductance versus front-gate voltage. Symbols: data [2]; lines: the BSIM-IMG model.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

gds (A/V)

1x10– 2 1x10

L = 52 nm W = 10 μm L = 961 nm W = 10 μm

–3

1x10– 4

|Vfg| = 1.2V 1x10– 5

Vbg = –1.0, 0.0, 1.0 V

1x10– 6 2x10– 3

Ids (A)

2x10– 3

Vbg = –1.0, 0.0, 1.0 V Symbols—Measured data Lines—Model

PMOS

1x10– 3 5x10– 4 0 – 1.5

–1.0

– 0.5

0.0

Drain voltage (V) Figure 6.7 IDS versus VDS characteristics for PMOS device with Lg 5 961 nm and Lg 5 52 nm. Symbols: data [2]; lines: the BSIM-IMG model [3].

Ideally, GIDL and GISL currents should be equal, so it is sufficient to extract drain-side parameters. In case GIDL and GISL currents differ, then parameters AGISL, BGISL, CGISL, EGISL, and PGISL should be extracted. Extracted parameters

Device and experimental data

Extraction methodology

AGIDL, BGIDL, EGIDL

Long and short devices IDS versus VGS @ different VDS @ VBG 5 0.0 V

VBGIDL, VBEGIDL

Long and short devices IDS versus VGS @ different VDS @ VBG6¼0.0 V

Observe drain current in off state or negative (positive) gate voltage for NMOS (PMOS) Observe leakage current at different back bias

Fig. 6.8 shows NMOS and PMOS drain current versus gate voltage at different back biases. The BSIM-IMG accurately models the back bias dependence of the GIDL current.

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119

Figure 6.8 IDS 2 VGS characteristics of the UTB SOI (A) P-MOSFET and (B) N-MOSFET. Lines and symbols represent BSIM-IMG model and measured data, respectively. The drain is biased at saturation region. Back-gate bias is from positive (left) to negative (right) values.

6.4.2 Gate Leakage Current From IGS versus VGS analysis, parameters related to the gate current can be extracted. First, the tunneling components should be activated by setting the selectors IGCMOD and IGBMOD to 1. Different parameters are extracted in different regions of operation and more specifically in the following regions: 6.4.2.1 Accumulation to Weak-Inversion Region • For IGBMOD 5 1, AIGBACC, BIGBACC, CIGBACC, and NIGBACC, which are linked to the gate-to-substrate current should be extracted. • AIGS, BIGS, and CIGS, which are associated with the tunneling current between the gate and the source diffusion region and AIGD, BIGD, and CIGD, with tunneling current between the gate and the drain diffusion region. This tunneling current is activated by IGCMOD 5 1. Moreover, extract DLCIGS and DLCIGD, which are linked to the S/D overlap length for IGS and IGD, respectively. The parameter DIGC captures the back-gate bias dependence of the gate current and should be extracted in the accumulation region [5].

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 6.9 Gate current versus gate voltage characteristics of the UTB SOI (A) longand (B) short-channel N-MOSFETs. The ratio of long and short gate length is 100 with the same gate width.

6.4.2.2 Weak to Strong-Inversion Region • AIGBINV, BIGBINV, CIGBINV, EIGBINV, and NIGBINV determine gate-to-substrate current. These parameters are associated with IGBMOD 5 1. • For gate-to-channel current, parameters AIGC, BIGC, CIGC, and PIGCD should be extracted for IGCMOD 5 1, along with DIGS and DIGD which models the back-gate bias dependence of the gate current in the strong-inversion region. The model emulates the gate current behavior fairly well as seen in the Fig. 6.9 which shows gate current versus gate voltage for different back-gate biases.

6.5 EXTRACTION OF TEMPERATURE DEPENDENCE PARAMETERS Up to this point of the parameter extraction procedure the temperature dependence of the parameters has been ignored since all the parameters were extracted at TNOM. In this part, the parameters that are related to the impact of temperature on the behavior of devices are extracted, and for that, data across the temperature range of the technology are necessary. The behavior of devices is studied with the same geometrical sequence as the previous steps, while the temperature dependence

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121

parameters are extracted in the same regions of operation as the parameters of the corresponding physical effects. The first step, in the extraction of temperature dependence parameters, is to extract the behavior of a long- and wide-channel device @ different T and for different analyses. It is recommended that the same device as the one in Section 6.2 is used. In detail: ID versus VGS analysis @ VDS 5 VD,lin, VS 5 0 V and VB 5 0 V • From weak-inversion region (ID vs VGS characteristic when y-axis is in logarithmic scale), the parameters TBGASUB and TBGBSUB, which control the temperature dependence of bandgap Eg, are extracted. Parameter KT1 is extracted for fitting the VTH across T. • From strong-inversion region the temperature dependence of low field mobility (U0), UTE, and the temperature coefficients: (1) for mobility reduction due to vertical field effect, namely UA1 and UD1, (2) for Coulomb scattering effect, UCSTE and UC1, and (3) for S/D series resistances, PRT, are extracted. ID versus VGS analysis @ VDS 5 VD,sat • From weak-inversion region (ID vs VGS characteristic when y-axis is in logarithmic scale), the parameter TETA0, which is related to the temperature dependence of DIBL effect is extracted. • In strong-inversion region the parameters that are used to model to the temperature dependence of velocity saturation effect, that is, AT and PTWGT are extracted. It is very important that in the earlier analyses, both ID and gm of all the devices are studied at once. Furthermore, in depletion region, for both linear mode and saturation mode of ID versus VGS analysis, the parameter TGIDL, which controls the temperature dependence of GIDL effect, is extracted. ID versus VDS analysis @ various VGS, VS 5 0 V and VB 5 0 V From ID versus VDS analysis in different temperatures, TDELTA, which is related to the temperature dependence of the smoothing factor for the transition between VDS and VDS,sat, is extracted. IDS versus VGS analysis @ VDS 5 VDS,lin and various VBG • From weak-inversion region (ID vs VGS characteristic when y-axis is in logarithmic scale), KT2 is extracted which is linked to the temperature dependence of VTH shift. • From strong-inversion region the temperature coefficient for mobility variation with VBG bias, UC1, is extracted.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

6.5.1 Length Scaling of Temperature Parameters Temperature dependence of short-channel device can be fitted by extracting length-dependent temperature parameters. For this, data @ different T of a set of devices with different channel lengths are required. ID versus VGS analysis @ VDS 5 VD,lin • Length dependence parameter of KT1, KT1L is extracted in weakinversion region at different T. In strong inversion, parameter UTL should be extracted. Fig. 6.10A compares threshold voltage at (A) 0.6

Threshold voltage (V)

NMOS 0.3

º

T = –40 C,

25ºC,

°

85 C |Vds | = 0.05 V |Vds | = 1.5 V

0.0

Symbols—measured data Lines—model –0.3

T = –40ºC, 25ºC, 85°C PMOS

–0.6 0.1

1

Gate length (nm) (B) 1x10–5

Ids (A)

1x10

T = –40ºC, 25ºC, 85ºC L = 52 nm W = 10 μm L = 961 nm W = 10 μm

–7

1x10–9 1x10–11

PMOS |Vds| = 0.05 V |Vbg| = 0.0 V

1x10–13 4x10–4

T = – 40ºC

Ids (A)

3x10

2x10–4 1x10

PMOS

–4

Symbols—measured data Lines—model T = 85ºC

T = 85ºC L = 52 nm W = 10 μm L = 961 nm W = 10 μm

–4

T = – 40ºC –1.0

–0.5

0.0

0.5

Front-gate voltage (V)

Figure 6.10 (A) Threshold voltage in the linear and saturation region (B) drain current versus gate length for different temperature.

Parameter Extraction With BSIM-IMG Compact Model

123

different operating temperatures for various gate lengths. In Fig. 6.10B, drain current versus front-gate voltage is shown for a long- and short-gate length device at different temperatures [3]. ID versus VGS analysis @ VDS 5 VD,sat • From strong-inversion region the parameters that are used to model the temperature dependence of velocity saturation effect across L, that is, ATL and PTWGTL, are extracted. It is very important that in the above analyses both ID and gm of all the devices are studied at once. For validating that the values of length scaling parameters for temperature dependence parameters are extracted correctly, it is useful to check also ID versus VDS and gds versus VDS characteristics and, if needed, to fine-tune their value by repeating Step 6.5.1. Once DC parameters are successfully extracted, RF modules in the model should be activated and relevant parameters should be extracted [6,7]. Like DC, RF parameters, too, need to be extracted by following a systematic procedure, as discussed in detail in Chapter 8, High-Frequency and Noise Models in BSIM-IMG.

REFERENCES [1] J. He, J. Xi, M. Chan, H. Wan, M. Dunga, B. Heydari, et al., Charge-based core and the model architecture of bsim5, in: International Symposium on Quality Electronic Design, 2005, pp. 96
101. [2] Y. Morita et al., Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate, in: IEEE Symposium on VLSI Technology, 2008, pp. 166
167. [3] P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J.-P. Duarte, et al., Modeling the impact of substrate depletion in FDSOI MOSFETs, Solid-State Electron. 104 (2015) 6
11. [4] BSIM-IMG 102.8 Independent Multi-Gate MOSFET Compact Model, BSIM Group, The Regents of the University of California. [Online]. Available from: ,http://bsim.berkeley.edu/models/bsimimg/., 2017. [5] Y.K. Lin, P. Kushwaha, H. Agarwal, H.L. Chang, J.P. Duarte, A.B. Sachid, et al., Modeling of back-gate effects on gate-induced drain leakage and gate currents in UTB SOI MOSFETs, IEEE Trans. Electron Devices 64 (10) (2017) 3986
3990. [6] P. Kushwaha et al., BSIM-IMG: compact model for RF-SOI MOSFETs, in: 73rd Annual Device Research Conference, 2015, pp. 287
288. [7] P. Kushwaha, S. Khandelwal, J.-P. Duarte, C. Hu, Y.-S. Chauhan, RF modeling of FDSOI transistors using industry standard BSIM-IMG model, IEE Trans. Microwave Theory Tech. 64 (6) (2016) 1745
1751.

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CHAPTER 7

Testing BSIM-IMG Model Quality Harshit Agarwal Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, United States

Compact models are a vital part of a process design kit. A good compact model has to accurately capture all the real device effects, and at the same time, it should produce them in a form suitable for maintaining high computational efficiency. Apart from accurate fitting with the experimental data, a compact model must behave physically by preserving basic device properties. For example, transistors (bulk/SOI/FinFETs) are intrinsically symmetric, and therefore compact model should give symmetric currents and capacitances. Further, iterations during the SPICE solution may lead to unexpected high voltages/currents which a compact model should gracefully handle. Another key aspect of the compact model is that it should give smooth derivatives since they are used by the SPICE while solving Kirchhoff ’s Voltage Law (KVL) and Kirchhoff ’s Current Law (KCL). Moreover, analog and RF simulations impose even harder requirements for convergence. In that sense, well-written compact model helps in achieving convergence during SPICE simulations. To broadly validate the physical correctness of a compact model, several tests were designed over the years [1
5]. We have already discussed in Chapter 2, Core Model for Independent Multigate MOSFETs, that special efforts are made to ensure that BSIM-IMG preserves all the fundamental properties of the FD-SOI transistor, including volume inversion, back bias effect, symmetry, etc. to name few. In this chapter, the qualitative correctness of the BSIM-IMG model (for both fast and extended range models) will be established by rigorous testing against several benchmark tests.

7.1 SYMMETRY TESTS FD-SOI transistor is inherently symmetric in nature, that is, source and drain terminals are indistinguishable. The bias conditions at these two terminals decide the name “source” or the “drain.” For a compact model, Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00007-8

© 2019 Elsevier Ltd. All rights reserved.

125

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

it is crucial to properly model this symmetric nature of the device since the asymmetric model may lead to inaccurate simulation results [6]. One simple example to understand its importance is in applications where the transistors are used as a bidirectional switch. In such cases, inaccuracy due to the asymmetric model may significantly impact the overall performance of the circuit. In addition, if a model does not comply with the symmetry requirements, this puts a severe limitation on its physical nature. The symmetry of the BSIM-IMG model is tested using well-established symmetry tests for the DC (currents) as well as AC (capacitances).

7.1.1 Gummel Symmetry Test Fig. 7.1 shows the circuit to test model symmetry for the DC. The transistor (represented by M1) is biased at a gate voltage Vg. Voltage source (Vx) is connected to drain (source) terminal of the device and voltagedependent voltage source with dependency factor of 21 is connected at the source (drain) terminal (i.e., Vd 5 Vx, Vs 5 2 Vx). The voltage Vx is swept to drive the transistor symmetrically in forward and reverse direction, and current (and derivatives) are observed [5]. The symmetric model should satisfy



Ix Vg ; Vx ;
Vx ; Vb 5
Ix Vg ;
Vx ; Vx ; Vb (7.1) From the above equation, it follows that all the even order of derivatives of Ix should be 0 for Vx 5 0. Further, along with current Ix, all the derivatives should be smooth (no sharp peaks) and continuous. Fig. 7.2 shows the model results with BSIM-IMG model in strong and weak inversion in Fig. 7.2A and B, respectively. Fig. 7.3 shows the test results

Figure 7.1 Gummel symmetry test setup for currents.

Testing BSIM-IMG Model Quality

127

Figure 7.2 Gummel symmetry test (A) strong inversion Vg 5 0.8 V and (B) weak inversion Vg 5 0.2 V. The model gives symmetric and continuous derivatives for any order of magnitude (shown here up to fourth derivative). The current and derivatives are normalized to their maximum value.

for the extended range BSIM-IMG model in weak and strong inversion region. From the figures, it is clearly seen that the current and derivatives are smooth and continuous. Here, although we have shown results up to fourth order, derivatives in BSIM-IMG model exist over nth order which is governed by the parameter MEXP (default value 4). Quantities in Figs. 7.2 and 7.3 are normalized to their maximum value for the clarity of presentation.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 7.3 Gummel symmetry test for extended range BSIM-IMG model (A) strong inversion Vg 5 0.8 V and (B) weak inversion Vg 5 0.2 V. The current and derivatives are normalized to their maximum value.

7.1.2 AC Symmetry Test In addition to the drain current, terminal charges and capacitances should also be symmetric (with respect to the source and drain terminal). This symmetry feature is tested using the circuit shown in Fig. 7.4. AC sources in-phase and out-of-phase are applied to the source and the drain of the device and terminal currents are monitored as shown in Fig. 7.4. DC voltages Vx and 2 Vx are applied to the drain and the source terminals of the device, respectively. The imaginary part of the AC terminal current Ig for in-phase (Ig1 ) and out-of-phase sources (Ig2 ) is then given by [4]

Testing BSIM-IMG Model Quality

129

Figure 7.4 Gummel symmetry test setup for capacitances.

Figure 7.5 AC symmetry test (A) δCg and (B) δCsd versus Vx as obtained from BSIMIMG model. δCg and δCsd and their derivative are smooth, continuous, and symmetric around Vx 5 0.



Ig1 5 2πf Cgs 1 Cgd

(7.2)



Ig2 5 2πf Cgs 2 Cgd

(7.3)

where Cgs and Cgd are the gate-to-source and gate-to-drain capacitance, respectively. f is the operating frequency. δCg defined as follows: δCg 5

Ig2 Ig1

5

Cgs 2 Cgd Cgs 1 Cgd

(7.4)

should be an odd function of Vx. Drain-to-source charge model can be tested in a similar way by defining δCsd as δCsd 5

Css 2 Cdd Css 1 Cdd

(7.5)

where Css and Cdd are the source and drain capacitance, respectively (Fig. 7.5).

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

7.1.3 Harmonic Balance Test MOS transistors are essentially nonlinear in nature with Ids ~ expðVgs 2 Vth Þ in subthreshold region and IDS ~ ðVgs 2Vth Þ2 in onstate. As a result, the output contains frequency components other than the input frequencies. Theoretically, it is possible to show that the nth harmonic depends on nth power of the input signal [7], that is, the second harmonic depends on the square of the signal, third harmonic on the cube of the signal, and so on. For various analog and mixed signal circuits, such as low noise amplifiers, differential pair, and mixers, harmonics are critically important. For example, harmonic distortion is one of the key performance parameters of the mixer design. Compact model, therefore, should accurately reproduce harmonic behavior. Setup to test harmonics is shown in Fig. 7.6A. RF signal is applied to the source/drain of the device and the harmonic components of the drain current are plotted as a function of the input RF signal. Fig. 7.6B shows the harmonic balance simulation results for the BSIM-IMG model, where it can be clearly seen that the BSIM-IMG model reproduces the correct slope of harmonics.

7.1.4 Capacitances Reciprocity Test We have already discussed that for a symmetric device, such as FD-SOI, currents and charges are symmetric. Further, at Vds 5 0, all the capacitances are reciprocal, that is, capacitance between any two terminals i and j must follow Cij 5 Cji. Here, Cij 5 δij

Qi ; Vj

δij 5 2 1 for i 6¼ j otherwise 1

(7.6)

Physical compact model should give reciprocal capacitances at Vds 5 0. Fig. 7.7 shows Cgs and Csg (normalized to W 3 L 3 Cox) as a function of gate voltage for Vds 5 0 as obtained from the BSIM-IMG model. From the figure, it can be seen that Cgs 5 Csg, and thus the model preserves the reciprocity property of the device.

7.2 WEAK AND STRONG INVERSION TEST 7.2.1 Conductance Test The qualitative behavior of the FD-SOI devices in weak and strong inversion regions is very different. Like conventional bulk and FinFet devices, while the drain current varies linearly in the strong inversion

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Figure 7.6 (A) Circuit setup for harmonic balance test and (B) BSIM-IMG model results, shown up to fifth harmonic. The model agrees well with the theoretical calculations. L 5 110 nm, W 5 2 μm, Vg 5 0.7 V.

(for small drain voltage), it has exponential dependence in the subthreshold region. The ability of a compact model to correctly reproduce, such Vds dependence, can be tested by several ways and conduction test is one of them [1]. In a very simplified form, drain-to-source current in weak inversion region can be expressed as (please refer Chapter 3: Channel Current Model With Real Device Effects in BSIM-IMG, for actual drain current equation).

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 7.7 Capacitance reciprocity test: FD-SOI is a symmetric device, and therefore Cij 5 Cji at Vds 5 0. BSIM-IMG passes this test as Cgs and Csg are equal (also Cgd 5 Cdg, not shown in the figure). Capacitances are normalized to W 3 L 3 Cox.

  Ids ~ 1 2 e2Vds =Vt

(7.7)

gds ~ e2Vds =Vt

(7.8)

From Eq. (7.8), it is easy to note that the quantity gds UeVds =Vt is independent of Vds. Similarly, it is possible to show that gds UeVds =Vt has the finite slope in the strong inversion when plotted against Vds. In the conductance test, gds UeVds =Vt behavior is tested for different gate voltages. Fig. 7.8A shows the result with the BSIM-IMG model and Fig. 7.8B shows for the extended range model. In line with the theoretical prediction, gds UeVds =Vt is independent of Vds in the subthreshold region and shows finite slope in the above-threshold region. Thus the model successfully passes this test.

7.2.2 Slope Ratio Test This test checks the model’s ability to capture drain bias dependence from subthreshold to the above-threshold region of operation. In this test, slope ratio (SR) is calculated for different gate voltages Vgs,

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Figure 7.8 Conductance test to check whether

Vds dependency is properly taken care of in the BSIM-IMG model. Gd Uexp Vds =Vth is plotted as a function of drain bias for different Vg. L 5 1 μm and W 5 1 μm.





Ids;2 1 Ids;1 Vds;2 2 Vds;1



SR 5 Vds;2 1 Vds;1 Ids;2 2 Ids;1

(7.9)

where Ids,1 and Ids,2 represent the drain current at drain voltage Vds,1 and Vds,2, respectively. In the subthreshold region, Ids ~ 1 2 e2Vds =Vt ,  

2 2 e2ðVds;2 =Vt Þ 2 e2ðVds;1 =Vt Þ Vds;2 2 Vds;1  SR 5 (7.10)

 Vds;2 1 Vds;1 e2ðVds;1 =Vt Þ 2 e2ðVds;2 =Vt Þ At room temperature, SR from above is  1.31 for Vds,2 5 20 mV and Vds,1 5 10 mV. Similarly in strong inversion, SR  1.0. Thus theoretically, for this case, SR should smoothly vary from 1.31 in weak inversion to 1.0 in strong inversion. Note that the value of SR in the subthreshold region depends on the temperature as well as on the two drain voltages. Fig. 7.9 shows the slope ratio obtained from the BSIM-IMG model. It can be clearly observed that BSIM-IMG, as well as extended range model, successfully passes the slope ratio test.

7.2.3 Volume Inversion Test In thin body devices with the lightly doped channel, the inversion layer can extend throughout the body. This effect is called volume inversion and it increases the drain current in the subthreshold region [8,9]. Thinner the body thickness, higher is the volume inversion. Note that in strong inversion, an inversion layer is formed close to the surface which masks the electric field, and therefore volume inversion vanishes. To test

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Figure 7.9 Slope ratio test: slope ratio smoothly varies from 1.3 in weak inversion to 1.0 in strong inversion at room temperature. L 5 1 μm, W 5 1 μm.

Figure 7.10 Drain current at different body thickness (parameter TSI). Current in subthreshold region increases due to volume inversion effect.

the BSIM-IMG model’s ability to capture this effect, drain current is plotted at different body thickness in Fig. 7.10. As observed from the figure, BSIM-IMG model qualitatively reproduces volume inversion effect.

7.3 TEST FOR SELF-HEATING EFFECT Semiconductor device properties are very sensitive to operating temperature. As the device dissipates power, device operating temperature changes (due to fluctuation in instantaneous temperature) and affects various parameters, such as mobility and band gap, which finally propagates to the

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terminal current. This is illustrated in Fig. 7.11. For the devices with very high power dissipation, self-heating effect (SHE) can have a significant impact on overall performance. We have discussed in Chapter 4, Leakage Current and Thermal Effects, that modeling SHE in FD-SOI devices is particularly important, owing to the relatively poor thermal conductivity of the buried oxide. We also discussed a subcircuit-based model for SHE. The validity of the SHE model is tested in two steps as follows. Bias the device in strong inversion, switch-on the self-heating mode (set SHMOD 5 1) and sweep the thermal resistance parameter RTH0. Observe the drain current and device temperature. Now turn off the self-heating model (set SHMOD 5 0) and simulate the device at temperatures obtained in step 1, keeping the same bias conditions as before [6,10]. Drain current obtained from these two steps should be the same. Fig. 7.12A and B shows these the results obtained using BSIM-IMG model. It is clearly seen in

Figure 7.11 Illustration of the impact of self-heating effect. Semiconductor device properties are very sensitive to the operating temperature. The power dissipated by the transistor raises the local temperature, which in turn affects various parameters, such as threshold voltage, mobility, and carrier velocity [10].

Figure 7.12 Self-heating test. (A) Temperature and drain current versus RTH0 at Vg 5 Vd 5 2 V with self-heating module turned-on. (B) Drain current versus temperature with self-heating model turned-off, at temperatures obtained in (A) under same bias conditions. Drain current obtained from two methods is equal, validating the correct implementation of self-heating model.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Fig. 7.12B that the drain current obtained from temperature and RTH0 sweep is same, indicating the correctness of the SHE model.

7.4 MODEL VALIDATION WITH GERMANIUM ON INSULATOR FD-SOI TRANSISTOR Transistors have witnessed scaling for the last several decades as it brings benefits, such as higher on-current, small footprint per transistor to name few. However, scaling is very challenging in state-of-the-art technology, partly due to severe short channel effects and partly due to the fundamental limitations of the scaling. Interestingly, there is also an alternative path which can lead to higher on-current: material engineering, that is, identification of the channel material composition with high carrier mobility than silicon. Germanium (Ge) is one such material [11]. However, these efforts are thwarted by the inability to achieve similar performance improvement in both n- and p-type devices, which are required for CMOS circuit designs [12]. There are, therefore, efforts for cointegration of hybrid channel devices for optimum CMOS performance (such as Ge/ strained silicon PMOS and compound semiconductor/silicon-based NMOS) [13,14]. Recently, first experimental germanium on insulator (GeOI)-based CMOS circuits were demonstrated in Ref. [15]. To keep pace with the technology advancement, we test the BSIM-IMG model’s ability to model the alternate channel material-based FD-SOI transistors.

7.4.1 Modeling the Germanium on Insulator FD-SOI Fig. 7.13 illustrates the simplified view of the GeOI device. Germanium has higher carrier mobility, which can be easily captured by the low field

Figure 7.13 Schematic representation of the GeOI FD-SOI transistor. GeOI is modeled using the BSIM-IMG model. GeOI, Germanium on insulator.

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model parameter U0 of the BSIM-IMG model. There is, however, another subtle aspect of the Ge material which is important to consider. The low effective mass of the carriers in Ge can shift the charge centroid as compared to Si [16] as shown in Fig. 7.14, which compares the electron concentration profile for the two cases. The shifted centroid, in turn, modulates the “effective oxide thickness.” In the BSIM-IMG model, this can be captured using the quantum mechanical effect module

Figure 7.14 Charge centroid shift: electron concentration as a function of distance from the front interface. In Ge, the inversion layer is away from the front interface as compared to the Si counterpart. Ge, Germanium.

Figure 7.15 Normalized gate capacitance as a function of applied front gate voltage. The shifting of the charge centroid leads to higher effective oxide thickness, which is well modeled by the Quantum Mechanical Effects (QME) module of the BSIM-IMG model.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

(Chapter 3: Channel Current Model With Real Device Effects in BSIMIMG) as shown in Fig. 7.15. Another key impact of the charge centroid shift is on the mobility. We know that the surface mobility is lower than the bulk mobility, primarily due to the surface roughness scattering. Interestingly, with charge centroid farther away from the surface, it should be less prone to the surface roughness scattering in Ge. At this point, while more experimental studies are needed to investigate this, we observed that the vertical field dependence of the mobility in Ge channel is

Figure 7.16 BSIM-IMG model results: NMOS (A) drain current Ids and (B) transconductance gm versus gate voltage. L 5 50 nm, W 5 1 μm. Symbols: experimental GeOI data, lines: BSIM-IMG model.

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different from the Si counterpart [17]. The effective mobility is expressed as [18] μeff 5

11U

U0 EU2 1 U A2UEeff

EU1 A1UEeff

where U0 is the low field mobility and Eeff is the effective vertical electric field. UA1, UA2, EU1, and EU2 are taken as the model parameters.

Figure 7.17 BSIM-IMG model results: NMOS (A) drain current Ids and (B) output conductance gds versus drain voltage. L 5 50 nm, W 5 1 μm. Symbols: experimental GeOI data, lines: BSIM-IMG model.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

7.4.2 Model Results and Circuit Level Validation The BSIM-IMG model is tested with the experimental GeOI data reported in Ref. [15] for both the n- and p-channel devices. We will first discuss the individual transistor characteristics, followed by the circuit level simulations. Fig. 7.16 compares the drain current and transconductance (gm) for two drain biases, and Fig. 7.17 shows the output characteristics. The model shows good agreement with the experimental data, including current as well as derivatives. Note that the accurate modeling of the derivatives is crucial otherwise the circuit simulation results may not be correct.

Figure 7.18 BSIM-IMG model results: PMOS (A) drain current Ids and (B) transconductance gm versus gate voltage. L 5 50 nm, W 5 1 μm. Symbols: experimental GeOI data, lines: BSIM-IMG model.

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Figure 7.19 BSIM-IMG model results: (A) PMOS Ids 2 Vds for various gate voltages. (B) Model scalability test: single model card is used to emulate device characteristics for different gate lengths.

Fig. 7.18A shows the Ids and Fig. 7.18B compares the gm of the p-channel device. The model correctly captures the characteristics of the GeOI transistors. The output characteristics Ids 2 Vds are shown in Fig. 7.19A. The model correctly captures the Ge-based FD-SOI transistor behavior. To test the BSIM-IMG scaling capability, the model is extracted for different gate lengths as well. Fig. 7.19B shows the model result, where a single model card can simultaneously fit multiple gate length devices.

7.4.3 Germanium on Insulator-Based CMOS Inverter After the accurate extraction of the DC parameters of the n- and p-channel GeOI transistors, CMOS inverter circuit is simulated.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 7.20 BSIM-IMG model validation with GeOI CMOS inverter: (A) Voltage transfer characteristics and (B) inverter gain versus input voltage. VDD is varied from 0.4 to 1.2 V. Inverter gain strongly depends on the modeling accuracy of the derivatives gm and gds. GeOI, Germanium on insulator.

Fig. 7.20A shows the voltage transfer characteristics of the inverter for different VDD 5 0.4
1.2 V in steps of 0.2 V. The BSIM-IMG model is able to correctly capture the transfer characteristics as well as its slope, as shown in Fig. 7.20B. The slope represents the gain of the CMOS inverter and strongly depends on the modeling accuracy of gm and gds.

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REFERENCES [1] Y. Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press, 2010. [2] C. McAndrew, H. Gummel, K. Singhal, Benchmarks for compact MOSFET models, in: Proc. SEMATECH Compact Models Workshop, 1995. [3] C. McAndrew, Validation of MOSFET model source
drain symmetry, IEEE Trans. Electron Devices 53 (9) (2006) 2202
2206. [4] Y.S. Chauhan, D.D. Lu, S. Venugopalan, S. Khandelwal, J.P. Duarte, N. Paydavosi, et al., FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard, New York, Academic, 2015. [5] K. Jordar, K.K. Gullapalli, C.C. McAndrew, M.E. Burnham, A. Wild, An improved MOSFET model for circuit simulation, IEEE Trans. Electron Devices 45 (1) (1998) 134
148. [6] G. Gildenblat, Compact Modeling: Principles, Techniques and Applications, Springer, 2010. [7] P. Bendix, P. Rakers, P. Wagh, L. Lemaitre, W. Grabinski, C.C. McAndrew, et al., RF distortion analysis with compact MOSFET models, in: IEEE Custom Integrated Circuits Conferenc, 2004, pp. 9
12. [8] D. Lu, Compact Models for Future Generation CMOS (Ph.D. thesis), UC Berkeley, 2011. [9] Y. Taur, An analytical solution to a double-gate MOSFET with undoped body, IEEE Electron Device Lett. 21 (5) (2000) 245
247. [10] H. Agarwal, S. Venugopalan, M.-A. Chalkiadaki, N. Paydavosi, J.P. Duarte, S. Agnihotri, et al., Recent enhancements in BSIM6 bulk MOSFET model, in: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2013. [11] R. Pillarisetty, Academic and industry research progress in germanium nano devices, Nature 479 (7373) (2011) 324
328. [12] P.S. Goley, M.K. Hudait, Germanium based field-effect transistors: challenges and opportunities, Materials 7 (2014) 2301
2339. [13] P. Nguyen, et al., Dual-channel CMOS co-integration with Si channel NFET and strained-SiGe channel PFET in nanowire device architecture featuring 15nm gate length, in: IEEE Electron Devices Meeting (IEDM), December 2014, pp. 16.2.1
16.2.4. [14] L. Czornomaz, et al., Co-integration of InGaAs n- and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates, in: IEEE Electron Devices Meeting (IEDM), December 2013, pp. 2.8.1
2.8.4. [15] H. Wu, N. Conrad, W. Luo, P.D. Ye, First experimental demonstration of Ge CMOS circuits, in: IEEE Electron Devices Meeting (IEDM), December 2014, pp. 9.3.1
9.3.4. [16] A. Lubow, S. Ismail-Beigi, T.P. Ma, Comparison of drive currents in metal oxide semiconductor field-effect transistors made of Si, Ge, GaAs, InGaAs, and InAs channels, Appl. Phys. Lett. 96 (12) (2010) 122105-1
122105-3. [17] S. Khandelwal, J. Duarte, Y. Chauhan, C. Hu, Modeling 20-nm germanium FinFET with the industry standard FinFET model, IEEE Electron Device Lett. 35 (7) (2014) 711
713. [18] H. Agarwal, P. Kushwaha, S. Khandelwal, J.P. Duarte, Y. Lin, H. Chang, et al., Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIMIMG industry standard model, in: IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2016, pp. 444
447.

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CHAPTER 8

High-Frequency and Noise Models in BSIM-IMG Pragya Kushwaha1 and Yogesh Singh Chauhan2 1

Postdoctoral Researcher, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, United States 2 Associate Professor, Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India

Radio-frequency (RF) market is seeing exponential growth due to increased demand for wireless applications. High-frequency (HF) modeling of transistors is key to develop reliable RF circuits. The substrates on which RF integrated circuits (ICs) are manufactured have significant impact on circuit performance. RF silicon-on-insulator (SOI) (RF-SOI) MOSFETs on highresistivity (HR) substrates have emerged as the best substrate choice over other substrates for low-cost RF solutions [1] (see Fig. 8.1). Mixed-signal system-on-chip devices and integration of complex, highpower devices are now possible because of RF-SOI’s high-linearity substrate, electrical isolation, and low insertion loss over a wide frequency range [2]. These technologies have offered us to integrate multiple RF/analog functions (e.g., the RF switches, multimode and multiband

Figure 8.1 Schematic of a FD-SOI transistor with the HR substrate without trap rich layer below BOX. BOX, Buried oxide; FD-SOI, fully depleted silicon-on-insulator; HR, high resistivity. Industry Standard FDSOI Compact Model BSIM-IMG for IC Design DOI: https://doi.org/10.1016/B978-0-08-102401-0.00008-X

© 2019 Elsevier Ltd. All rights reserved.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

power amplifiers, antenna tuners, and power controllers) in a smaller space [2]. For battery-life limited wireless applications, fully depleted SOI (FDSOI) has emerged as a promising candidate for advanced technology nodes due to better control over short-channel effects [3
5], performance enhancement capability via back bias tuning [6], better thermal properties [7], and reduced random dopant fluctuations [8]. With continuous channel length scaling, FD-SOI
based CMOS transistors are now becoming an appropriate choice in the millimeter wave range due to the achievement of higher transconductance and cutoff frequency (fT ) with the additional advantage of area and cost over III
V technology [9]. To achieve higher fT by scaling the RF-SOI MOSFET is a challenging task because of increased fringing capacitance between the gate and the source/drain contacts [10]. Optimized multifingered transistor layouts are widely used to reduce gate resistance and to increase the maximum frequency of oscillation (fmax ). RF-SOI’s market trends for production designs show that there is an urgent requirement for a robust, compact model which can capture FDSOI transistor behavior accurately at HF ranges [11]. FD-SOI transistors’ characteristics have frequency dependence via several inherent phenomena like self-heating effect (SHE) [12], substrate effect [13], and gate resistance effect [14]. The DC compact model is not sufficient to predict correct device behavior of measured data over a wide frequency range [15
18]. To capture the HF behavior of FD-SOI transistor, we have enhanced the BSIM-IMG model for RF applications by incorporating parasitic components like gate resistance, substrate resistance, and thermal resistance networks. We will start this chapter with the discussion on RF characterization, followed by the RF modeling and a parameter extraction procedure.

8.1 RADIO-FREQUENCY CHARACTERIZATION The major difference between low versus HF characteristics is the impact of each distributed R
C (i.e., time constant) on frequency behavior of the device. At high frequencies the dielectric (or any material) starts behaving like a transmission line. The assumption of lumped component may fail or may need to be modeled as distributed component from the understanding of transmission line behavior. Additional parasitics, such as inductances, may also affect device behavior at high frequencies. The goal of this chapter is to model the linear (small signal) behavior of a device subject to a HF test signal. Such behavior is typically summarized by the N-port network parameters of the device that

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Figure 8.2 Setup picture for N-channel MOSFETs for two-port RF characterization. RF, Radio frequency.

is, impedance parameters (Z-parameters), admittance parameters (Yparameters), hybrid parameters (H-parameters), and scattering parameters (S-parameters). S-parameters are preferred because they are based on the concept of incident, reflected, and transmitted waves that are more easily measured at high frequencies in terms of amplitude and phase angle of the various waves. Our focus will be on using two-port network, which we can be easily measured with typical lab equipment such as vector network analyzer. Typically, RF measurements are performed on the ground
signal
ground (G
S
G) pad set as shown in Fig. 8.2. The transistor’s gate terminal is assigned as port-1, while drain terminal is assigned as port-2. Source terminal is common and connected to the ground. In our work, Keysight’s E5071C vector network analyzer with the capability of measuring frequencies from 100 kHz to 8.5 GHz is used to measure the two-port S-parameters (see Fig. 8.3). The DC measurements are performed using Keysight’s B1500 parameter analyzer (see Figs. 8.4 and 8.5). HF characterization is a complicated task where attention should be paid on each and every component appearing in the measurements. Two important steps in the RF characterization are calibration and deembedding as discussed next. • Calibration: In this process the equipment is calibrated with known standards. Before we start calibration, we should make sure that tips of RF probes are planaraized. Calibration is done by measuring known

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Figure 8.3 Photograph of experimental setup used to perform RF measurements under different bias conditions. Wafer is visible on chuck along with RF probes. RF, Radio frequency. (B)

(A)

30

Ids (mA)

12 9 6

Symbols: Experimental data Lines: Model N-channel

gm (mA/V)

15

Vbg = 0.0 V Vds = 50 mV Vds = 1.1 mV

3 0 0.0

25

Symbols: Experimental data Lines: Model

20

N-channel Vbg = 0.0 V

15

Vds = 50 mV 10

Vds = 1.1 mV

5

0.2

0.4

0.6

0.8

Front-gate voltage (V)

1.0

0 0.0

0.2

0.4

0.6

0.8

1.0

Front-gate voltage (V)

Figure 8.4 (A) Drain current (Ids ) versus front-gate voltage Vfg characteristics. (B) Transconductance (gm ) versus front-gate voltage Vfg characteristics for Lg 5 100 nm. Bias conditions are Vds 5 50 mV and 1.1 V, substrate is grounded Vbg 5 0 V. Symbols: experimental data, Lines: the BSIM-IMG model.

standards [such as standards on Keysight’s Impedance Standard Substrate (ISS)] located at DUT reference planes (probe tips for on-wafer measurements, and applying algorithms to determine the error terms).

High-Frequency and Noise Models in BSIM-IMG

(A)

(B) 18

N-channel N-channel

Symbols: Measured data Lines : Model

gds (mA/V)

15 12

Ids (mA)

149

10

9

Vfg = 0.9–1.1 V

6

Vfg = 0.9–1.1 V

Symbols: Measured data Lines : Model

3 0 0.0

0.5

1.0

1 0.0

Drain voltage (V)

0.5

1.0

Drain voltage (V)

Figure 8.5 (A) Ids versus drain voltage Vds characteristics. (B) Output conductance gds versus drain voltage Vds characteristics for Lg 5 100 nm. Bias conditions are Vfg 5 0:9 2 1:1 V in steps of 0.1 V, substrate is grounded Vbg 5 0 V. Thermal resistance Rth value extracted from step 2 shown in Fig. 8.20 is used here. Symbols: experimental data, Lines: the BSIM-IMG model.

Figure 8.6 SOLT calibration. SOLT, Short-Open-Load-Thru.

•

Several calibration techniques are available in the literature. • Open-Short • SOLT (Short-Open-Load-Thru) • SOLR (Short-Open-Load-Reciprocal) • TRL (Thru-Reflect-Line) • LRM/LRRM (Line-Reflect-Match/Line-Reflect-Reflect-Match) Different standards are required for different techniques, but, in general, standards must be precise with very low and known parasitics. A special ISS with precisely defined standards is used for calibration purpose. Typically SOLT calibration (see Fig. 8.6) is accurate for most of the frequency range of interest for MOSFET characterization.

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De-embedding: All the probe and wire parasitics are removed using ISS substrate in the calibration step. Even with calibration, reference planes are still not at the boundaries of the intrinsic device due to on-wafer test structure interconnects (probe pads, metal layers, transmission lines, ground planes, etc.). We must measure additional on-wafer test structures to calibrate out (de-embed) the remaining parasitics. De-embedding is the process to remove parasitics from pads up to the device. Most common on-wafer de-embedding technique is OPEN-SHORT de-embedding method, where OPEN test structure is designed to represent the parallel (G) parasitics, and SHORT test structure is designed to represent the series (Z) parasitics as shown in Fig. 8.7. De-embedding results are valid if OPEN, SHORT, and DUT are linear and time invariant in nature. The power level must be chosen such that DUT behaves linearly with applied power for S-parameter measurements.

8.2 RADIO-FREQUENCY MODELING AND PARAMETER EXTRACTION To capture the HF behavior of FD-SOI transistor, we have enhanced the surface potential based BSIM-IMG model [19
23] for RF applications. First, we have extracted DC parameters like series resistance, mobility using DC measured data. Fig. 8.29A and B shows drain current behavior with the gate voltage and drain voltage, respectively, for a device with channel length of 100 nm with channel width of Wg 5 0:5 μm and number of fingers noise figure (NF) 5 60. The model shows good agreement with experimental data in all regions of operation, which implies accurate modeling of submodules like mobility degradation, current saturation etc. FD-SOI transistors have severe SHE at low-frequency levels, which affects device’s electrical characteristic such as output conductance gds . We have extracted the frequency-dependent parameters (i.e., gds , gate capacitance CGG and gate resistance Rg ), which affect device’s Analog/RF figure of merit (FoM). The frequency response of gds and CGG are obtained from the real part of Y22 and imaginary part of Y11 , respectively. In this section, we have discussed the variation of Real Y22 , CGG , and Rg in a wide frequency range and their impact on Analog/RF FoM.

8.2.1 Thermal Resistance Network In Chapter 4, Leakage Current and Thermal Effects, we have discussed that AC drain output conductance (gds ) measurement is good for accurate

Figure 8.7 (A) Illustration of parasitics from pads up to the device, (B) OPEN test structure, and (C) SHORT test structure.

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extraction of thermal network for SOI MOSFETs [24]. As frequency of the small signal increases, the device temperature gradually loses its ability to follow the applied signal. At high enough frequency relative to the time constant(s) of the device, the device temperature remains effectively constant. This isothermal frequency can be used to determine the device thermal time constants [24,25]. In advanced MOSFETs, this frequency is so high that substrate and gate resistance network come into picture [26], and gds does not show any plateau in the frequency range of interest, which makes self-heating time constant characterization difficult using most of the existing methods. Here we systematically explain the procedure to choose the frequency range of interest for thermal network extraction. Fig. 8.8 shows the imaginary part of Y22 (referred as Imag (Y22 )) for 100 nm channel length device. The device is biased at saturation and strong inversion where the effect of self-heating is large and can be measured accurately. Increasing the gate to source bias (Vfg ) from 1.2 to 1.4 V, keeping drain to source bias (Vds ) constant at 1.4 V, increases the drain current (Ids ) and hence the SHE. Since thermal contribution dominates over electrical contribution (substrate and/or gate resistance network) at low-frequency region of the spectrum due to SHE, Imag(Y22 ) at Vfg 5 1:4 V is proportional to Imag(Y22 ) at Vfg 5 1:2 V, where the proportionality constant depends on the ratio of currents, IdsjVfg51:4 V =IdsjVfg51:2 V . Around isothermal frequency, electrical contribution dominates over thermal contribution to Imag(Y22 ), and this proportionality relationship becomes invalid. This situation can be realized through the splitting of Imag(Y22 ) at Vfg 5 1:4 V and constant multiplied Imag(Y22 ) at Vfg 5 1:2 V curves. The frequency at which this splitting happens is the isothermal frequency [27].

Figure 8.8 Measured imaginary part of Y 22 for 100 nm channel length device. Vfg 5 1:2 and 1:4 V, and Vds 5 1:4 V.

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From [28], Y22 can be written as Y22 5 Y22T 1 Zth C20 ðV1 Y12T 1 V2 Y22T 1 I2 Þ

(8.1)

where Y12 5

@I1 jV2 ; T @V2

(8.2)

Y22 5

@I2 jV1 ; T @V2

(8.3)

Y12 and Y22 are the admittances for the isothermal case, that is, the temperature does not vary with the AC signal and remains fixed at the value determined by the DC bias. The parameters Y12T and Y22T are affected only by DC self-heating, while parameters Y12 and Y22 are also affected by AC self-heating. C20 5

@I2 C2 5 @TAmb 1 2 Zth ðC1 V1 1 C2 V2 Þ

(8.4)

C1 5

@I1 jV1 ; V2 @T

(8.5)

C2 5

@I2 jV1 ; V2 @T

(8.6)

Combining these equations, we get Y22 5 Y22T 1 Zth

Y22 5

C2 ðV1 Y12T 1 V2 Y22T 1 I2 Þ (8.7) 1 2 Zth ðC1 V1 1 C2 V2 Þ

Y22T 2 Zth Y22T ðC1 V1 1 C2 V2 Þ 1 Zth C2 ðV1 Y12T 1 V2 Y22T 1 I2 Þ 1 2 Zth ðC1 V1 1 C2 V2 Þ (8.8) Y22 5

Y22T 2 Zth Y22T C1 V1 1 Zth C2 ðV1 Y12T 1 I2 Þ 1 2 Zth ðC1 V1 1 C2 V2 Þ

(8.9)

Y22 5

Y22T 1 Zth ðC2 V1 Y12T 2 C1 V1 Y22T 1 C2 I2 Þ 1 2 Zth ðC1 V1 1 C2 V2 Þ

(8.10)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Assuming gate current component to be negligible, we can ignore C1 and Y12 in (8.10), which yields Y22 5

Y22T 1 Zth C2 I2 1 2 Zth C2 V2

Y22 2 Y22T 5 Zth C2 ðI2 1 V2 Y22 Þ Zth 5

Zth 5

Y22 2 Y22T C2 ðI2 1 V2 Y22 Þ

iso Y22 2 Y22

dIDS =dTamb ðI2 1 VDS UY22 Þ

(8.11) (8.12) (8.13)

(8.14)

Here, Tamb is the ambient temperature. Far above isothermal frequency, device temperature does not respond to the applied small signal. iso Taking only the thermal contribution into account, Imag(Y22 ) can be set to zero, that is, no phase shift between small signal drain current and voltiso age. Therefore Y22 is a real number. From Eq. (8.15), Imag(Y22 ) can be expressed as (separating real and imaginary components and taking only imaginary components) ImagðZth Þ½RealðDn Þ2 1 ImagðDn Þ2 Þ RealðDn Þ iso ImagðDn Þ½RealðY22 Þ 2 ðY22 Þ 1 RealðDn Þ

ImagðY22 Þ 5

(8.15)

where Dn 5

dIDS ðIDS 1 VDS UY22 Þ dTamb

(8.16)

A self-consistent Imag(Y22 ) and Real(Y22 ) fitting recipe is used to produce the results of Fig. 8.9. Fig. 8.10 shows the fitting of Imag(Y22 ) to measured data using (8.15), which leads to the extraction of Zth . Since we are interested in the thermal contribution only, Imag(Y22 ) is fitted such that it gives good match at low-frequency region and becomes close to zero at isothermal frequency. Extracted Zth is plugged back to 1.14 to calculate Real(Y22 ). Calculated Real(Y22 ) is then compared with measured data. Imag(Y22 ) is refitted over low-to isothermal frequency range until Real(Y22 ) shows good match with measured data over the same spectrum.

High-Frequency and Noise Models in BSIM-IMG

155

Figure 8.9 Measured and extracted real part of Y 22 for 100-nm-channel-length devices. Vfg 5 1:2 and 1:4 V and Vds 5 1:4 V.

Figure 8.10 Measured and extracted imaginary parts of Y 22 for 100-nm-channellength devices. Vfg 5 1:2 and 1:4 V and Vds 5 1:4 V.

8.2.2 Substrate Parasitic Network Fig. 8.11 shows that the model has a deviation from measured data above 100 MHz even after using self-heating (SHE) network. Because after 40
50 MHz, dynamic self-heating reduces or disappears [27]. The substrate-related transition in the real part of Y 22 occurs at frequencies between 100 MHz and few GHz [13,29] as shown in Fig. 8.12A. This effect comes into picture due to the majority carrier relaxation time of the silicon substrate which is nothing but the silicon resistivity (ρ0 ) multiplied by its permittivity (ε0 Uεsi ). Substrate under buried oxide (BOX) has resistivity around 20 Ω cm. The relaxation frequency for silicon substrate is 1=ð2πUρUε0 UεSi Þ. The relaxation frequency is in the order of 100 MHz for HR substrate. For frequencies lower than B100 MHz the substrate

156

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

(A) 3.4

Real (Y22), mS

(B)

Exp.data 1st order thermal N/W

3.2 3.0 2.8

ΔT

P = Ids*Vds Rth

Thermal N/W

Cth

2.6 ΔGSHE

2.4 105

DC value of gDS

106

107

108

109

1010

f (Hz) Figure 8.11 (A) Measured and extracted real part of Y 22 for Lg 5 100 nm. First-order thermal network is used for fitting till 20 MHz range. Bias conditions are Vfg 5 Vds 5 1:1 V and Vbg 5 0 V. Symbols: experimental data, Lines: the BSIM-IMG model. (B) R
C network for self-heating calculation.

Figure 8.12 (A) Measured and extracted real part of Y22 for Lg 5 100 nm. Five resistor
capacitor substrate networks are used to validate the BSIM-IMG model in the medium frequency range. Bias conditions are Vfg 5 Vds 5 1:1 V and Vbg 5 0 V. Symbols: experimental data, Lines: the BSIM-IMG model. (B) Substrate network: Five Rs and five Cs along with three capacitances (Csbox =Cdbox are capacitances between source/drain to BOX, and Cox2 is BOX capacitance.) are used to validate the model for the wide frequency range. We have neglected deep well junction capacitances. Gate parasitic network: Two resistors (gate resistance Rg , gate terminal to contactpad resistance Rc ) in the series along with front-gate capacitance Cox1 are used to validate the model above GHz range.

will behave as a conductor and can be modeled by a resistor. But for frequencies higher than 100 MHz the substrate will behave as a dielectric and is modeled by a capacitor. Hence, the substrate-related transition occurs corresponding to its dielectric cutoff frequency around 100 MHz.

High-Frequency and Noise Models in BSIM-IMG

157

Figure 8.13 Measured and simulated S-parameter: (A) Smith chart validation for S11 and S22 for channel lengths Lg 5 30 nm, 100 nm. (B) The phase of S11 and S22 for Lg 5 100 nm. Bias conditions are Vfg 5 Vds 5 1:1 V and Vbg 5 0 V. Symbols: experimental data, Lines: the BSIM-IMG model.

In the GHz range, distributed substrate resistance and capacitances start affecting two-port parameter behavior of MOSFET [30]. Literature [31,32] shows that a single resistor substrate network is sufficient to predict correctly Real Y22 behavior till few GHz. The proposed substrate network shown in Fig. 8.12B is used to validate the BSIM-IMG model. Fig. 8.12B shows that the addition of substrate network in the model enhances model accuracy up to several GHz frequency ranges. The substrate network shown in Fig. 8.12B is important for accurate fitting of S22 in all bias ranges [33]. Fig. 8.13A shows the S11 [the input impedance when the output port (drain) is terminated with 50 Ω] and S22 [the output impedance when the input port (gate) is terminated with 50 Ω] on the Smith chart as final validation of an RF model for a wide frequency range. The phase of S11 and S22 are shown in Fig. 8.13B. The model has shown good agreement with phase data, which implies that the input port components (i.e., gate resistance and gate capacitance) and the output port components (i.e., substrate network resistance and substrate capacitance) have been optimized well. Fig. 8.14 shows the current gain (jH21 j) versus frequency, where model has good fitting with the measured data at Vbg 5 0 V. By extrapolating jH21 j characteristic, we can get fT [34].

8.2.3 Gate Parasitic Network High-k metal gate transistors are gaining momentum for RF applications due to the high transient frequency achievement [10,35]. High-k metal gate transistors suffer from gate resistance which reduces maximum frequency of

158

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 8.14 Current gain jH21 j variation with frequency for Lg 5 100 nm. Current

gain reduces as frequency increases ( iL =iin 5 gm =ðwT 3 CGG Þ,wT 5 2 3 π 3 freq ). Here iL =iin are output/input currents. Bias conditions are Vfg 5 Vds 5 1:1 V and Vbg 5 0 V. Symbols: experimental data, Lines: the BSIM-IMG model.

Figure 8.15 (A) Measured and extracted imaginary part of Y11 =ð2πUfreq Þ versus frontgate voltage characteristic for Lg 5 100 nm. Note that CGG can also be measured using C
V measurements of large area devices, which is not shown here. Bias conditions are Vds 5 0 V and Vbg 5 0 V. (B) Measured and extracted imaginary part of Y11 for Lg 5 100 nm. Low-frequency measured data is not shown here. Bias conditions are Vfg 5 Vds 5 1:1 V and Vbg 5 0 V. Symbols: experimental data, Lines: the BSIM-IMG model.

oscillation [36,37]. At high frequencies, parasitic resistances/capacitances start playing an important role and affect the HF performance of the device. We will discuss here gate capacitance and resistance extraction in detail. 8.2.3.1 Gate Capacitance Network Fig. 8.15A shows CGG 5 ImagðY11 Þ=2πfreq versus front-gate voltage at low frequency. Fig. 8.15B shows Imag (Y11 ) versus frequency characteristic. It

High-Frequency and Noise Models in BSIM-IMG

159

Figure 8.16 Measured and extracted real part of H11 (gate resistance) versus frequency characteristic for Lg 5 100 nm. Symbols: experimental data, Lines: the BSIMIMG model.

shows the frequency behavior of Imag (Y11 ) for high gate and drain voltages (Vfg 5 Vds 5 1:1 V), where the model shows excellent fit. 8.2.3.2 Gate Resistance Network Gate resistance consists of distributed gate resistance (Rg ) and distributed contact resistance (Rc ). In strong inversion, contribution from source/ drain series resistance (Rs =Rd ) can be neglected; hence, contribution from gate resistance becomes dominant [38,39]. Thus effective gate resistance (Rg ) is extracted from real part of H11 ð 5 1=realðY11 ÞÞ as shown in Fig. 8.16. As described earlier, at low and medium frequency ranges, thermal and substrate networks come into the picture, while at very HF, gate resistor network plays important role due to its lower time constant [14] as shown in Fig. 8.17. We have also compared the model results for short-channel length Lg 5 30 nm data in Figs. 8.18 and 8.19. Fig. 8.13A also shows S11 and S22 for channel lengths Lg 5 30 nm, 100 nm. Fig. 8.18A shows the impact of gate and the substrate network on Real Y22 . Higher fT (jH21 j intercept on frequency axis) is achieved from Lg 5 30 nm transistor due to higher drain current as shown in Fig. 8.19B. The complete RF parameter extraction flow is shown in Fig. 8.20.

8.3 NOISE MODELS As RF devices are becoming pervasive in today’s market, it is vital to improve the performance of RF CMOS circuits. New architectures like

160

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

3.4 Exp. data First-order thermal N/W Gate N/W Substrate resistor N/W Gate parasitic N/W

Real (Y22), mS

3.2 3.0 2.8

Substrate N/W Thermal N/W

2.6 ΔGSHE

2.4 105

DC value of gDS

106

107

108 f (Hz)

109

1010

Figure 8.17 Measured and extracted real part of Y22 for Lg 5 100 nm. Above the GHz range, gate resistor plays major role in predicting device behavior correctly due to its lower time constant. Excellent fitting with experimental data shows the importance of thermal, substrate, and gate networks. Bias conditions are Vfg 5 Vds 5 1:1 V and Vbg 5 0 V. Symbols: experimental data, Lines: the BSIM-IMG model.

Figure 8.18 The BSIM-IMG model validation against measurement data for two channel lengths, named as devices A and B. Device A dimensions are Lg 5 30 nm, Wg 5 1 μm, NF 5 30; and Device B dimensions are Lg 5 100 nm, Wg 5 0:5 μm, NF 5 60. Both devices have similar front/back-gate oxide thickness and channel thickness as follows: Tox 5 1:2 nm, Tbox 5 10 nm, Tsi 5 8 nm. (A) Real Y22 versus frequency characteristic. (B) The imaginary part of Y11 =ð2πUfreq Þ versus frequency characteristic. Symbols: experimental data, Lines: the BSIM-IMG model.

FinFETs, FD-SOI, etc. are of great significance in supporting continuous downscaling of semiconductor devices in order to achieve superior performance in high-speed electronic circuits. Ultrathin body and BOX FD-SOI MOSFET offers excellent electrostatic control and reduced variability [40
43] along with an efficient back bias effect, which results in dynamic

High-Frequency and Noise Models in BSIM-IMG

161

DC parameter extraction

Figure 8.19 The BSIM-IMG model validation against measurement data for two channel lengths, named as devices A and B. Device A dimensions are Lg 5 30 nm, Wg 5 1 μm, NF 5 30; and Device B dimensions are Lg 5 100 nm, Wg 5 0:5 μm, NF 5 60. Both devices have similar front/back-gate oxide thickness and channel thickness as follows: Tox 5 1:2 nm, Tbox 5 10 nm, Tsi 5 8 nm. (A) Real H11 versus frequency characteristic. (B) jH21 j versus frequency characteristic. Symbols: experimental data, Lines: the BSIM-IMG model.

Step1: CGG vs Vfg characteristic Step2: Ids vs Vfg @ Vds = 50 mV, Ids vs Vfg @ Vds = 1.1 V, Ids vs Vds characteristic

RF parameter extraction

Step 3: Thermal network Real Y22 vs frequency Step 4: Substrate network Substrate resistance (RSUB) extraction, S22 vs frequency Step 5: Gate network Rg vs frequency, CGG vs frequency, S11 vs frequency Step 6: RF figure of merit Current gain vs frequency

Figure 8.20 An illustration of RF parameter extraction flow in FD-SOI MOSFETs. FDSOI, Fully depleted silicon-on-insulator; RF, radio frequency.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

modulation of the performance-power requirements of a circuit [44
47]. FD-SOI technology is also a preferred candidate for HF applications due to its high isolation and integration capabilities [48]. Thermal noise is a dominant noise source in HF range [49]. In order to reduce the minimum level of the signal, with tolerable quality, that can be processed in analog and RF circuits, good noise performance becomes one of the prime requirements [50]. In modern technology, power supply voltage is being reduced for low power and mobile wireless applications. Under these circumstances, thermal noise becomes an increasingly important issue as signal levels are becoming comparable to noise levels. A compact model capable of emulating precise noise behavior of FD-SOI MOSFETs at such frequencies is discussed in Section 8.3.1. At high frequencies the capacitive coupling between the gate and the channel results in significant induced noise at the gate [51]. Gateinduced noise is described in Section 8.6. Besides thermal noise, low-frequency noise (1/f noise) is another important noise for MOS transistor as it sets a lower limit on the level of signal that can be processed by a low-power RFIC [52,53]. In Section 8.6.1, we have discussed flicker noise model implemented in the BSIM-IMG model [54
58]. The BSIM-IMG model includes contribution from all noise components [59] like flicker (1/f noise), thermal noise from channel as well as from each parasitic resistors and shot noise. All these noise components are described in detail from Sections 8.3.1 to 8.6.2.

8.3.1 Thermal Noise Model Channel thermal noise in MOSFETs is a function of conductivity (i.e., total inversion charge) of channel. As a general case drain current (Ids ) in FD-SOI MOSFETs is given by

gðV Þ dV =dy



Ids 5 (8.17) 1 1 1=Esat dV =dy where denominator term represents current degradation due to velocity saturation effect, gðV Þ is channel conductance without velocity saturation, Esat is saturation electric field, and V is channel voltage. Addition of thermal noise source in in channel causes a small fluctuation Ids in current and v in channel voltage. Note that v; Ids and V are function of position along channel yUy 5 0 and L represent source and drain ends, respectively. Modified current in the presence of thermal noise is given as [60,61]

High-Frequency and Noise Models in BSIM-IMG

Ids 1 Ids 5

gðV 1 vÞ d



U ðV 1 vÞ 1 in 1 1 1=Esat U d=dy ðV 1 vÞ dy

Rearranging (8.18), we get   1 d d ½Ids 1 Ids 2 in U 1 1 U ðV 1 vÞ 5 gðV 1 vÞU ðV 1 vÞ Esat dy dy

163

(8.18)

(8.19)

Simplifying and considering terms up to first order, we get     1 dV Ids dv 1 dV Ids 1 1 U U 1 ðIds 2 in ÞU 1 1 U 1 Esat dy Esat dy Esat dy (8.20) dðV 1 vÞ 5 gðV 1 vÞU dy

In (8.20), RHS gðV 1 vÞU ðdðV 1 vÞÞ=dy can be simplified using Taylor series approximation as (refer Appendix for details)   Ids dv 1 dV d (8.21) U 1 ðIds 2 in ÞU 1 1 U 5 ðvUgðV ÞÞ Esat dy dy Esat dy Integrating (8.21) from source (y 5 0) to drain (y 5 L) with boundary conditions vð0Þ 5 0 5 vðLÞ (as source and drain ends are defined at constant potentials) gives  ð  1 L 1 dV Ids 5 in 1 1 U dy (8.22) Lvsat 0 Esat dy



ÐL where Lvsat 5 0 ½1 1 1=Esat U dV =dy dy. Using autocorrelation of (8.22) with Wiener
Khintchine theorem [62], we get power spectral density (PSD) for channel noise as [60,61]     ð ð 1 L L 1 dV 1 dV 0 Si2d ðf Þ 5 2 Sn ðf Þ 1 1 U U U 11 dydy0 (8.23) Lvsat 0 0 Esat dy Esat dy where V and V0 are channel potentials corresponding to y and y0 , respectively. Assuming thermal noise at different points in channel is uncorrelated Sn ðf Þ is expressed as [60,61] Sn ðf Þ 5 4kT U

gðyÞ



Uδðy0 2 yÞ ½1 1 1=Esat U dV =dy 

Using (8.24) in (8.23), we arrive at

(8.24)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

1 Si2d ðf Þ 5 2 Lvsat

Ðb

# ðL ðL " gðyÞ



 Uδðy0 2 yÞ 4kT U  U dV =dy 1 1 1=E sat 0 0     1 dV 1 dV 0 U U U 11 dydy0 3 11 Esat dy Esat dy

f ðtÞUδðt 2 cÞdt 5 f ðcÞ in (8.25)   ð ð 4kB T L 1 dV 4kB T Vd 2 Si2d 5 2 gðV Þ 1 1 U g ðV ÞdV dx 5 2 Lvsat 0 Esat dy Ids Lvsat Vs

Using

(8.25)

a

(8.26)

Above relation is known as Klaassen
Prins equation [63], where Lvsat 5 Leff 3 Dvsat . Here Leff is channel length, while Dvsat is the current degradation factor due to velocity saturation [64]. Conductance of a MOSFET in general can be expressed as gðV Þ 5 μeff WQinv ðV Þ

(8.27)

where μeff is the effective mobility which includes all mobility degradation effects, W is channel width, and Qinv ðV Þð 5 jQs;intrinsic 1 Qd;intrinsic jÞ is the total inversion charge per unit area. Qs;intrinsic ; Qd;intrinsic are intrinsic charges at source/drain ends. Using (8.27) in (8.26), the final expression for noise current can be expressed as (8.28). 8 4kT Δf > < NTNOIU Rds ðV Þ 1 L2 =μ Qinv

=& if RDSMOD 5 0 eff eff Si2d 5 (8.28) 4kT Δf > NTNOIU L2 Uμeff Qinv if RDSMOD 5 1 : eff

where the parameter NTNOI is introduced for more accurate fitting of short-channel devices. Rds ðV Þ is the bias-dependent source/drain resistance. The internal Rds ðV Þ option can be invoked by setting the model selector RDSMOD 5 0 (internal) and the external one for source resistance Rs ðV Þ and drain resistance Rd ðV Þ are invoked by setting RDSMOD 5 1 (external). In independent double-gate field effect transistor (FETs), total inversion charge Qð 5 Qf 1 Qb Þ will have contributions Qf and Qb from the front and the back gates, respectively. Moreover, interface quality and vertical field will be different at the front and the back gates in FD-SOI MOSFETs. So, to maintain generality, we have considered two different effective mobilities μf and μb at front and back interfaces, respectively [65]. Thus the modified conductivity becomes gðV Þ 5 W ðμf Qf ðV Þ 1 μb Qb ðV ÞÞ

(8.29)

High-Frequency and Noise Models in BSIM-IMG

165

Effective mobilities at the front and the back interfaces are taken using standard relation from [65,66]. Normalizing Qf and Qb by Cox1 Vt and Cox2 Vt , respectively, we get gðV Þ 5 WCox1 Vt ðμf qf ðV Þ 1 μb Kqb ðV ÞÞ

(8.30)

where Cox1 and Cox2 are front and back-gate oxide capacitances, respectively, and K 5 Cox2 =Cox1 . Using (8.30) in (8.26), we get ð 2 4kTW 2 Cox Vt2 Vd 2 2 Si2d 5 ðμf qf 1 K 2 μ2b q2b 1 2Kμf μb qf qb ÞdV (8.31) 2 Ids Lvsat Vs 3 2 7 6ð ð Vd ð Vd 7 Vd 2 4kTW 2 Cox Vt2 6 7 6 2 2 2 2 2 μ q dV 1 K μ q dV 1 2Kμ μ q q dV Si2d 5 7 6 f b f b b b 2 7 6 Vs f f Ids Lvsat Vs Vs 4|fflfflfflfflfflfflffl{zfflfflfflfflfflfflffl} |fflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflffl} |fflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflffl}5 A

B

C

(8.32) In (8.32) the first term (A) represents the thermal noise contribution due to front gate (similar to bulk MOSFET). Second term (B) represents the contribution of back gate, and the third term (C) represents the coupled effect of front and back gates. Since in (8.32) the integrals are with respect to channel voltage, to perform the integrations with respect to Gopt and Γ opt , we use dqf =dV and dqb =dV that are obtained by using Poisson’s equation, Gauss’s law, and the boundary conditions for FD-SOI MOSFET. Detailed derivation of dqf =dV and dqb =dV is given in the Appendix. Integration of part A:
 ð Vd ð qfd
qf 1 ηf 2 2 2 2 μf qf dV 5 μf q f 2 Vt dqf qf Vs qfs " # (8.33) q3 2 q3fd q2fs 2 q2fd 2 fs 5 Vt μf 1 ηf 3 2 Similarly integrating part B:  3  ð Vd 3 q2bs 2 q2bd 2 2 2 2 2 qbs 2 qbd K μb qb dV 5 K Vt μb 1 ηb 3 2 Vs

(8.34)

To simplify the integral in part C, we have assumed that for FD-SOI MOSFETs, BOX thickness will be more than that of front oxide

166

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

thickness. So variation in charge density at the back gate will be smaller as compared to the variation at the front gate. Hence, we replace qb by its average value ðqbav Þ at the source and the drain side and take it out of integral. The integral becomes " # ð Vd q2fs 2 q2fd 1 ηf ðqfs 2 qfd Þ 2Kμf μb qf qb dV 5 2KVt μf μb qbav (8.35) 2 Vs This gives us the final expression for Si2d as Si2d 5 α

2 4kTW 2 Cox Vt3 ½A1 1 B1 1 C1  2 I Lvsat ds

(8.36)

where α is a model parameter similar to NTNOI used in standard BSIM models [64,66], and A, B, C are " # 2 2 q 1 q q 1 q q 1 q fs fd fs fd fs fd A1 5 μ2f ðqfs 2 βqfd Þ 1 ηf 3 2 " # q2bs 1 qbs qbd 1 q2bd qbs 1 qbd 2 2 B1 5 K μb ðqbs 2 βqbd Þ 1 ηb 3 2 " # qfs 1 qfd C1 5 2Kμf μb qbav ðqfs 2 βqfd Þ 1 ηf 2 where β 5 0:99 is used to avoid any convergence issue at Vds 5 0 V . Channel length modulation is included by replacing channel length L by actual reduced channel length Leff [49,65]. In short-channel devices, drain induced barrier lowering (DIBL) reduces threshold voltage as Vds increases, which results in higher channel conductance and thermal noise [67]. DIBL is automatically included via threshold voltage shift in BSIMIMG core during surface potential calculation [5,64,68]. To verify this, we have simulated model for different values of DIBL parameter ETA0 as shown in Fig. 8.21. As ETA0 increases, DIBL is increased, which results in higher thermal noise.

8.4 THERMAL NOISE CHARACTERIZATION Thermal noise measurement setup is shown in Fig. 8.22. Setup includes an NF meter (NFM), vector network analyzer, a source-pull tuner to

High-Frequency and Noise Models in BSIM-IMG

167

Figure 8.21 Plot showing simulation of normalized PSD from the proposed model for different values of ETA0. As ETA0 increases from 0 to 1, DIBL increases resulting in higher thermal noise. ETAB and DSUB are BSIM-IMG model parameters, and λ is scale length as defined in Ref. [64]. ΔVth;DIBL is threshold voltage shift due to DIBL effect. PSD, Power spectral density.

Figure 8.22 Radio-frequency NFM setup. NFM, Noise figure meter.

vary the impedance observed by the DUT and a noise source. The setup is controlled by Keysight’s ICCAP tool. Measurement accuracy is increased by using low-noise amplifier before the NFM to boost the weak noise signal [69]. By keeping a fixed source impedance of 50 Ω0, NF is measured. We received DUTs from CEA-LETI 28 nm technology node. Device under test has effective oxide thickness Tox 5 1:2 nm, channel width Wg 5 1 μm, back-gate oxide thickness Tbox 5 25 nm, number of fingers NF 5 40 and silicon channel thickness Tsi 5 8 nm.

168

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

8.4.1 Thermal Noise Parameters NF parameter is the ratio of the signal-to-noise ratio (SNR) at the input port to that at the output port. Here, NF50 is the noise figure measurement performed with a source impedance of 50 Ω [see (8.37)]. NFmin is the minimum achievable NF [see (8.38)] for a device under fixed bias condition. NFmin and NF50 are given by [70
72].
2 Si22 f d NF50 5 1 1 Gs Rn 1 fT U (8.37) ð4kB T Þ2 gm2 Gs Rn 

h 

2 

2  NFmin 5112 ωCgg Rgs Rn 2Rgs 1r 2r Rgs ωCgs 1ωCgg Rn Rn 2Rgs 

2  

2 2 i1=2 1r2r Rgs ωCgs 2 Rn2Rgs2r Rgs ωCgs (8.38) here Rgs 5 Rg 1 Rs , where Rg and Rs are the gate and the source resistances, respectively. r 5 δ=5gm , gm is the transconductance, δ 5 4=3, and ω denotes frequency in radians. We have extracted Rgs , Cgg and Cgs form Y-parameters. Gate capacitance is Cgg 5 Cgs 1 Cgd , here Cgs is the gate-to-source capacitance, and Cgd denotes the gate-to-drain capacitance. Gs 5 ð1=50Þ Ω21 is the source admittance, kB denotes the Boltzmann constant, T is the temperature, Si2d denotes the noise PSD, and fT denotes the cutoff frequency. The equations used for NF50 and NFmin do not have the induced gate noise (IGN) as IGN is not as significant as the channel thermal noise for the frequency range studied here [69]. The noise resistance (Rn ) is the channel thermal noise which is extracted from NF50 as [70]

ðNF50 2 1Þ 2 ðωCgg Þ2 r 2 Rgs 2 rðRgs ωCgs Þ2 RA

Rn 5 (8.39) ðωCgg Þ2 2Rgs 1 1=Gs 1 Gs

here R A 5 2Rgs 1 source side reflection coefficient,

1=Gs . The

Γ opt 5 Zopt 2 Zo = Zopt 1 Zo is another important parameter. Zo is the characteristic impedance of the system. Zopt 5 1=Yopt denotes the optimum source impedance. Zopt 5 Gopt 1 j Bopt denotes the optimum source admittance, it results in minimum NF [69]. Gopt and Bopt are as follows [69]:
 

2  

2 2 1=2 ωCgg Gopt 5 Rn Rn2Rgs1r2r Rgs ωCgs 2 Rn2Rgs2r Rgs ωCgs Rn (8.40)

High-Frequency and Noise Models in BSIM-IMG

169

Figure 8.23 (A) Measured NF50 versus frequency characteristics for different frontgate voltages Vfg 5 0:8; 1; 1:2; 1:4 V. Frequency sweep is from 1 to 18 GHz, step size 5 1 GHz. Inset figure demonstrates the NF50 versus Vfg plots for two channel lengths Lg 5 50; 100 nm. (B) NF50 versus frequency characteristics for different backgate voltages Vbg 5 2 3; 0; 3 V. Inset figure demonstrates the NF50 versus Vbg characteristics for channel length Lg 5 100 nm. (C) NF50 versus frequency characteristics for different drain voltages Vds 5 1; 1:2; 1:4 V. Inset figure demonstrates the NF50 versus Vds characteristic for Lg 5 100 nm. Device details are as follows: Tsi 5 8 nm, Wg 5 1 μm, Tox 5 1:2 nm, Tbox 5 25 nm, NF 5 40.

Bopt 52

ωCgg Rn 2Rgs 2rðRgs ωCgs Þ2 Rn

(8.41)

Fig. 8.23 illustrates the frequency dependence of parameter NF50 for different biases. The NF50 demonstrated from Fig. 8.23A
C is nearly constant with frequency, while (8.37) predicts a parabolic dependence [73,74]. The reason behind this discrepancy is the smaller frequencydependent term (i.e., ðf =fT Þ2 ðSi22 =16k2B T 2 gm2 Rn Gs Þ) than 1 1 Rn Gs for the d measured device for the frequency range studied here. Fig. 8.23A inset shows NF50 as a function of the front-gate voltage (Vfg ). As Vfg increases,

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 8.24 (A) Ids versus front-gate voltage Vfg characteristics for different back-gate voltages (Vbg ) from the measurement as well as calibrated TCAD data. Lines: TCAD data, symbols: measured data. (B) Minimum NF NFmin versus frequency characteristics from TCAD simulations. (C) Minimum NF NFmin versus frequency characteristics extracted from S-parameter data (Lg 5 100 nm). Frequency sweep is from 1 to 18 GHz, step size 5 0.5 GHz. Bias conditions are Vfg 5 1:2 V and Vds 5 1:2 V. Cgs 5 Cgg 2 Cgd , where Cgg and Cgd are shown in Fig. 8.28B. Parameter values used to calculate NFmin are Rgs 5 37:47 Ω, Rn 5 1:7; 2:02; 2:35 kΩ for Vbg 5 2 3; 0; 3 V, respectively.

the total number of charge carriers in the device increases, which increases drain current. As a result, more carrier collisions occur in the channel which ultimately increases the overall noise (i.e., higher NFmin ) [75]. Fig. 8.24A demonstrates that, by increasing positive back-gate voltage (Vbg ), the threshold voltage (Vth ) decreases [76] and results in higher drain current, and as a result, we get higher thermal noise. This increased thermal noise increases the NF which is demonstrated in the inset of Fig. 8.23B. Fig. 8.23C inset shows that NF50 is nearly constant with drain voltage (Vds ) because the noise does not change with Vds in the saturation region due to the effect of velocity saturation [77,78].

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NF50 measurements along with the S-parameter measured data is used to extract the noise parameters like Rn , NFmin , Bopt , Gopt , and Γ opt as defined earlier from (8.37)
(8.41) [57]. Fig. 8.24B demonstrates the frequency dependence of NFmin for Vfg 5 1:2 V and Vds 5 1:2 V for different back-gate voltages Vbg 5 2 3; 0; 3 V. Fig. 8.24C demonstrates that the NFmin extracted from S-parameter measurements increases with frequency [74,79]. From (8.40) and (8.41), we can see that Gopt ð ~ f Þ and Bopt ð ~ 2 f Þ are proportional to frequency. As a result the top part of Fig. 8.25 demonstrates an increase in the magnitude of Gopt with positive slope, while bottom part of Fig. 8.25 shows an increase in the magnitude of Bopt with negative slope. Fig. 8.26 demonstrates the variation in the magnitude and the phase of Γ opt by changing frequency. These characteristics of NFmin , Gopt , Bopt , and Γ opt (magnitude and phase) are in good agreement with TCAD data [69,73,74]. Fig. 8.27A demonstrates the behavior of the noise resistance with front-gate voltage for three different back-gate voltages. The extracted Rn does not change significantly with frequency as it depends on gm and Cgg . Here, gm and Cgg are independent of frequency (see Fig. 8.28A and B). Noise resistance Rn can also be written as (8.42) [69]: Rn 5 Rgs 1

Si2d 4kB T UjY21 j2

5 Rgs 1

Si2d 4kB T Ugm2

(8.42)

From Fig. 8.28A, we see that for higher Vfg (51.2 V), the transconductance, gm ð 5 RealðY21 ÞÞ, does not change much with back-gate voltage, while Fig. 8.27A demonstrates large variation of Rn with back-gate voltage. From (8.42), this larger sensitivity of Rn with back-gate voltage can be reflected to the significant change in Si22 with Vbg [75] as shown by d TCAD data in Fig. 8.27B.

8.5 MODEL VALIDATION Derived model for thermal noise PSD is implemented and tested using the industry standard BSIM-IMG model [64]. To obtain qf and qb , total charge calculated by the core model is distributed between the front and the back gates using charge repartition, details of which are given in the Appendix. Validation of the proposed model is done against noise PSD obtained from TCAD simulations and experimentally measured HF noise parameters for a wide range of back biases (Vbg ). Finally standard

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 8.25 (A) The top figure demonstrates Gopt versus frequency characteristics from TCAD simulations. The bottom figure demonstrates Bopt versus frequency characteristics from TCAD simulations. (B) The top figure demonstrates Gopt versus frequency characteristics from S-parameter measurements. The bottom figure demonstrates Bopt versus frequency characteristics extracted from S-parameter measurements. Cgs 5 Cgg 2 Cgd , where Cgg and Cgd are shown in Fig. 8.28B. Bias conditions are Vds 5 1:2 V, Vfg 5 1:2 V. Parameter values used for the noise parameters calculation: Rgs 5 37:47 Ω and Rn 5 1:7; 2:02; 2:35 kΩ for Vbg 5 2 3; 0; 3 V, respectively.

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Figure 8.26 (A) Γ opt versus frequency characteristics from TCAD simulations. (B) Γ opt versus frequency characteristics extracted from S-parameter measurements. Cgs 5 Cgg 2 Cgd , where Cgg and Cgd are shown in Fig. 8.28B. Bias conditions are Vds 5 1:2 V, Vfg 5 1:2 V. Parameter values used for Γ opt calculation are Rgs 5 37:47 Ω and Rn 5 1:7; 2:02; 2:35 kΩ for Vbg 5 2 3; 0; 3 V, respectively.

benchmark tests are performed to validate the asymptotic behavior of the proposed model.

8.5.1 Experimental Validation of High-Frequency Noise Parameters As discussed in Section 8.4, in the area of circuit design, noise performance is characterized in terms of HF noise parameters. These parameters

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 8.27 (A) Rn versus Vfg characteristics for different back-gate voltages: Vbg 5 2 3; 0; 3 V. (B) Noise PSD Sid2 from TCAD data versus frequency characteristics for different back-gate voltages: Vbg 5 2 3; 0; 3 V. Vfg 5 1:2 V and Vds 5 1:2 V. Device details are as follows: Tsi 5 8 nm, Lg 5 100 nm, Tox 5 1:2 nm, Tbox 5 25 nm, Wg 5 1 μm, NF 5 40. PSD, Power spectral density.

represent various figures of merit for a circuit working in HF regime which necessitates accurate prediction of these parameters. These HF noise parameters can be either measured separately or extracted from NF50 (NF measured with 50 Ω source impedance) and S-parameter measurements. We have followed later approach (see details in Section 8.4) to obtain experimental values of HF noise parameters [72,80].

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Figure 8.28 (A) Real part of Y21 extracted from S-parameter measurements versus frequency for different back-gate voltages: Vbg 5 2 3; 0; 3 V. Inset figure demonstrates gm (DC measured data) versus Vfg characteristics for different back-gate voltages: Vbg 5 2 3; 0; 3 V. (B) Cgg , Cgd extracted from S-parameter measurements versus frequency characteristics for different back-gate voltages: Vbg 5 2 3; 0; 3 V. Vfg 5 1:2 V, Vds 5 1:2 V.

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 8.29 DC calibration of BSIM-IMG compact model with experimental data. (A) Ids 2 Vfg calibration with experimental measurements for different back bias values (Vbg 5 2 3; 0; 3 V). (B) Ids 2 Vds calibration with experimental measurements for different back bias values (Vbg 5 2 3; 0; 3 V). Symbols: measurement data. Lines: BSIMIMG model simulation.

DC calibration of BSIM-IMG model with experimental data is shown in Fig. 8.29A and B. NF measured at 8 GHz versus Vfg , and Vds is shown in Fig. 8.30A and B, respectively. The extracted Rn at 8 GHz is plotted with respect to Vfg and Vds in Fig. 8.31A and B, respectively. Variation of NF with Vfg (Fig. 8.30A) depends on the ratio of noise PSD and gm [see (8.30A)]. In strong inversion, NF increases with Vfg due to increase in noise PSD. At smaller Vfg , gm and correspondingly fT fall rapidly resulting in strong increase of NF. Similarly Rn also depends on the ratio of noise PSD and gm and follows a similar trend as NF (see Fig. 8.31A). Positive Vbg increases noise PSD and degrades SNR at output port of MOSFET which in turn increases NF. While, on other hand, negative Vbg have just opposite effect and hence lower NF. In Fig. 8.30A, as we move towards lower Vfg , gm for negative Vbg starts decreasing rapidly first and hence NF increases. Similar trend is then observed for zero and positive values of Vbg . Figs. 8.30B and 8.31B show NF and Rn variation with Vds . As current and noise PSD are constant in the considered Vds range (saturation), a constant behavior of NF and Rn is expected. At lower Vds , NF and Rn curves are showing increasing trend which is due to increasing noise PSD for smaller Vds values. Validation of NF50 and NFmin versus frequency is shown in Fig. 8.32A and B, respectively.

8.5.2 Asymptotic Behavior of Model Thermal noise factor γ ( 5 Si2d =4kB Tgd0 ), where gd0 is conductance at (Vds 5 0 V) is often used to describe behavior for thermal noise model [81]. At Vds 5 0 V the channel acts like a resistor of conductance gd0 and

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Figure 8.30 Validation of NF50 with experimental data. (A) NF50 versus Vfg for different back bias values (Vbg 5 2 3; 0; 3 V). (B) NF50 versus Vds for different back bias values (Vbg 5 2 3; 0; 3 V). A relatively constant behavior is obtained due constant current and noise PSD for considered Vds values. Symbols: measured NF50 data. Lines: simulation using (8.37) and (8.42). PSD, Power spectral density.

exhibits full thermal noise and γ 5 1 [82]. For long-channel devices, γ reduces to 2=3 as MOSFET enters into saturation. As shown in Fig. 8.33A, for weak inversion, γ goes from 1 to 0:5 as Vds is varied from linear to saturation region of operation. Similarly for strong inversion, γ goes from 1 in linear region to 2=3 for saturation values of Vds . This behavior of γ for proposed model is consistent with literature implying

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 8.31 Validation of Rn with experimental data. (A) Rn versus Vfg for different back bias values (Vbg 5 2 3; 0; 3 V). (B) Rn versus Vds for different back bias values (Vds 5 2 3; 0; 3 V). A relatively constant behavior is obtained due constant current and noise PSD for considered Vds values. Symbols: extracted Rn values using NF50 data [80]. Lines: Simulation using (8.42). PSD, Power spectral density.

correct asymptotic behavior of thermal noise model [81]. In weak inversion the cause of white noise is disputed [49], it is considered either as shot noise or thermal noise. So both thermal and shot noise PSD should give the same result in weak inversion. To verify this, PSD from shot noise and proposed model are compared in Fig. 8.33B that shows proposed model reduces to shot noise PSD ( 5 2qIds ) in weak inversion.

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179

Figure 8.32 Validation of noise figure versus frequency (f ). (A) Validation of NF50 versus f using (8.37) for different back bias values (Vbg 5 2 3; 0; 3 V). (B) Validation of minimum noise figure (NFmin ) versus frequency (f ) for different back bias values (Vbg 5 2 3; 0; 3 V). Symbols: extracted/ measured values. Lines: model simulation.

8.6 INDUCED GATE THERMAL NOISE MODEL Channel charge fluctuation causes a redistribution of the channel potential, which results in a charge redistribution across the gate capacitor. This fluctuation is capacitively coupled to the gate charge at the RF and result in a noise current (rate of change of charge) at the gate terminal, the physical source of it being the channel thermal noise fluctuation. This is called

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Figure 8.33 Verification of asymptotic behavior of noise PSD. (A) Variation of γ versus Vfg in strong and weak inversion region for long-channel MOSFET(L 5 10 μm). (B) PSD of shot noise and from model to show that model reduces to shot noise PSD in weak inversion region. PSD, Power spectral density.

the induced gate thermal noise. Bias dependence and the capacitive nature of this coupling make the induced noise bias and frequency dependent. In BSIM-IMG-induced gate thermal noise model [83], the analytical expression of induced noise is derived by taking the Klassen-Prince equation [63] as the starting point. Induced noise PSD and cross-correlation PSD are given by

High-Frequency and Noise Models in BSIM-IMG

Sig2 5 PSig2

ð Vd

Sig;id 5 PSig;id

ð Vd 2 g0 ðvÞ ðQðuÞ2QðvÞÞg0 ðuÞdu dv 2

Vs

181

(8.43)

Vs

ð Vd

g0 ðvÞ 2

Vs

ð Vd

g0 ðuÞðQðuÞ 2 QðvÞÞdudv

(8.44)

Vs

where PSig2 5 16π2 kTf 2 W 2 =Ids 5 Leff 2 , PSig;id 5 2 j8πkTfW =Ids 3 Leff 2 ; Vs and Vd are source and drain side potentials; kB is the Boltzmann constant, T denotes the temperature, and f is the frequency of operation. g0 is channel conductance without velocity saturation, Leff is channel length after including channel length modulation, W is channel width, Ids is drain current. The integration can be performed for an FD-SOI transistor if the total charge density can be given as [84]

Q 5 Cox1 Vt qf 1 Kqb (8.45) where qf and qb are the charge densities normalized by Cox1 Vt and Cox2 Vt at the front and the back gates, respectively. Vt is the thermal voltage, Cox1 and Cox2 are the front and the back-gate oxide capacitances, respectively, and K 5 Cox2 =Cox1 . The integrations yield the final expression for the induced noise and cross-correlation PSDs as in (8.47)
(8.48), where AI , BI , CI , and DI are defined as in (8.49)
(8.52), mid 5 μf Qf 2 1 Kμb Qb2 , μf ðbÞ denotes the front (back) gate mobility, and Qf ðbÞN is defined as Qf ðbÞN 5

N qN f ðbÞs 2 qf ðbÞd

N

1 ηf ðbÞ

N21 qN21 f ðbÞs 2 qf ðbÞd

N 21

(8.46)

where N 5 2; 3; 4; 5. For an ideal device θ 5 2. However, for compact modeling purposes, BSIM-IMG uses θ as a parameter. Effects of channel length modulation, drain-induced barrier lowering, and velocity saturation are incorporated in the same manner as in thermal noise model of BSIM-IMG. 16π2 qf θ Lvsat 3 Sig2 5 ðAI 2 BI 1 CI Þ (8.47) WCox 3 Vt 9 mid 5
 2 j8πqfLvsat 2AI 2 BI Sig;id 5 Cox Vt 3 mid 3 2DI where

  AI 5 PI 2 μf 2 Qf 3 1 2μf μb qav Qf 2 1 μb 2 Qb3

(8.48)

(8.49)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

BI 5 2PI WCox 2 Vt 3 ðμf Qf 2 1 μb KQb2 Þ½μf 2 Qf 4 1 ðμf qav Qf 3 Þðμf K 1 2μb Þ 1 ðμb qav 2 Qf 2 Þð2μf K 1 μb Þ 1 μb 2 Kqav 3 Qf 1 1 ηf ðlogðqfs Þ 2 logðqfd ÞÞ (8.50) h i2 CI 5 WCox 2 Vt 3 ðμf Qf 2 1μb KQb2 Þ ½μf 2 Qf 5 1 2qav μf Qf 4 ðμb 1 μf KÞ 1 qav 2 Qf 3 ðμb 2 1 4μf Kμb 1 K 2 μf 2 Þ 1 2μf μb K 2 qav Qf 2 ð1 1 qav Þ (8.51) h i DI 5 WCox 2 Vt 3 μf Q f 3 1 K 2 μb Qb3 1 Kqav ðμf 1 μb ÞQ f 2

(8.52)

Finally, the correlation coefficient is calculated as [84] iig;id Sig;id ffi 5 pffiffiffiffiffiffiffiffiffiffiffiffiffi C 5 pffiffiffiffiffiffiffiffiffi 2 2 Sid2 Sig2 id ig

(8.53)

The model is validated with calibrated TCAD simulations. Experimental measurements from an FD-SOI device [58] with L 5 100 nm W 5 40 μm, tbox 5 25 nm, tsi 5 8 nm, and EOT 5 1:2 nm are used to calibrate the TCAD device parameters. This calibrated TCAD setup is used for all the noise simulations. Fig. 8.34A and B shows the drain current as a function of the gate and drain voltages, respectively, for different back-gate biases. Fig. 8.35B shows the variation of the IGN PSD with front-gate voltage for different back-gate biases. The trend of the noise PSD with

Figure 8.34 Drain current variation with increasing (A) front-gate voltage and (B) drain voltage for different back-gate biases. This validation is used to extract the model parameters that are used for all the other noise simulations performed with the model. Device details are as follows: L 5 100 nm, W 5 40 μm, tbox 5 25 nm, tsi 5 8 nm, and EOT 5 1:2 nm.

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183

Figure 8.35 (A) Induced gate noise PSD as a function of front-gate bias for Vds 5 1:4 V and back biasing of Vbg 5 (0.1, 0, 20.1 V). An increase in the back bias reduces threshold voltage and also leads to higher channel conductivity and hence more induced gate thermal noise. Model agrees with TCAD data fairly well. (B) Induced gate noise PSD as a function of front-gate bias for Vds 5 1:4 V. Increase in front-gate bias increases channel conductivity, and it results in more induced noise PSD. Model shows a good agreement with TCAD extracted induced noise data. Parameters used are as follows: U0 5 44:67 3 1023 m2 =V s, UA 5 59:7 3 1023 V21 , vsat 5 0:67 3 105 m=s, θ 5 1.775. PSD, Power spectral density.

increasing front-gate voltage is as expected [85]. The increase in frontgate voltage increases channel conductivity resulting in the increase of the channel thermal noise PSD (proportional to channel conductivity). This is reflected on the gate terminal through the gate-to-channel coupling from gate capacitance, resulting in an increase in the IGN as well. Increasing the back-gate bias reduces threshold voltage and leads to higher channel

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

conductivity due to increase in charge density as well as the mobility [86], resulting in higher IGN. For the fixed V ds and V bg the decrease in gate-to-source capacitance with increasing front-gate voltage results in the reduction of the effective gate-to-channel coupling. This causes the induced noise PSD to decrease at higher front-gate voltage. Fig. 8.35B shows the dependence of the induced noise PSD on the front-gate voltage for different frequencies. As the frequency increases, the impedance of the effective capacitance coupling between the gate and the channel brings in a frequency dependence as shown in (8.47) and (8.48), which increases the IGN PSD at higher frequency [87]. This is further illustrated in plots (A
C) of Fig. 8.36. Plot (A) shows the increase in

Figure 8.36 (A) Induced noise PSD as a function of frequency. Sig2 is quadratically dependent on frequency. The model is in good agreement with TCAD-induced noise PSD. (B) cross-correlation PSD as a function of frequency. Sig;id is directly proportional to frequency. (C) cross-correlation coefficient as a function of frequency. Increase in frequency will result in to more gate
channel coupling capacitance, which in turn increases jCj at higher frequency. Parameters used are as follows: U0 5 44:67 3 1023 m2 =V s, UA 5 59:7 3 1023 V21 , vsat 5 0:67 3 105 m=s, θ 5 1.775. PSD, Power spectral density.

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IGN PSD with increasing frequency, while plots (B) and (C) clearly illustrate that the effective gate
channel coupling increases with frequency, by showing the increasing trend of the cross-correlation noise PSD and the correlation coefficient. All the plots show excellent agreement between the model and the TCAD simulations.

8.6.1 Flicker Noise Model Flicker noise is a dominant noise source in lower frequency range. It is also called as 1=f noise as its PSD is inversely proportional to frequency. In bulk MOSFETs, flicker noise results from carrier trapping de-trapping in traps present at Si 2 SiO2 interface [88]. Thus FD-SOI transistor faces more carrier fluctuations due to the presence of the front and back interfaces [89
98]. Charge trapping/de-trapping results in the fluctuations of both mobile carrier numbers and mobility in the channel. McWhorter stated that flicker noise arises due to random fluctuation in number of free carriers due traps present at Si 2 SiO2 interface [99]. 1=f spectrum of flicker noise is obtained by superimposing spectrum of individual traps with randomly distributed time constants. From [88], PSD is given as ð τ2 1 4τ 1 1 2 1 U for {ω{ S1=f ð f Þ ~ ðΔNÞ2 2 5 ðΔNÞ U f τ2 τ1 τ 1 τ 1 1 ðωτÞ (8.54) Hooge proposed that “the fluctuations in the conductivity are due to fluctuations in mobility and not in the number of charge carriers” [100,101]. Noise PSD from Hooge’s model is given by S1=f ðf Þ 5

αH UIds2 f γ Ntotal

(8.55)

where f is the frequency, Ids is the mean current flowing through the sample, and Ntotal is total number of free carriers in the sample. αH is Hooge’s parameter, while γ is a fitting parameter. The unified flicker noise model [102] accounts both carrier number and mobility fluctuation theories. The BSIMIMG model uses the same unified flicker noise model as implemented in BSIM4 [59]. In this section, we will discuss the derivation of unified noise model in detail. The drain current in FD-SOI transistor can be expressed as Ids 5 W μeff qNEx

(8.56)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

where N is the total number of channel carriers per unit area, and Ex is the horizontal channel field. Fluctuations in the occupancy of the front oxide traps induce correlated fluctuations in the channel carrier number (N), and surface mobility (μeff ) results as fluctuations in the drain current [102]. 1 δIds 1 δΔN 1 δμeff 5 6 Ids δΔNt ΔN δΔNt μeff δΔNt

(8.57)

where ΔN 5 NW Δx; ΔNt 5 Nt W Δx. N and Nt are the numbers of channel carriers and occupied traps per unit area at the front interface. ΔN and ΔNt are considered in a section of the transistor channel with width W and length Δx. These fluctuations in the drain current give rise to Sid in the channel. To solve the first right term in (8.57), we can relate ΔN and ΔNt , considering that the fluctuation in δΔQt (i.e., ΔQt 5 2 qΔNt ) of the trapped charge density causes a variation in the front surface potential, which results in change of all the charges that depend on surface potential [103]. Thus capacitive coupling between δΔN and δΔNt at the front interface is given as R5

δΔN Cinv N 5 52 δΔNt Cinv 1 Cox 1 CIT N 1 N

(8.58)

2

q where Cinv ( 5 kT N) is the inversion layer capacitance; N  5 kT q2 (Cox 1 CIT); CIT is the model parameter for the silicon
oxide interface trap coupling capacitance. To evaluate the second right term in (8.57), we have used Matthiessen’s mobility model to acknowledge the dependence of the carrier mobility on the front oxide charge densities as

1 1 1 1 5 1 5 1 αNt μeff μn μox μn

(8.59)

where μox is the mobility limited by the front oxide charge scattering [104], and μn is the mobility limited by other scattering mechanisms. α is the scattering coefficient to capture the influence of the front oxide trap charges on channel mobility. Differentiating (8.59) with respect to ΔNt , we get αμ2eff δμeff 52 δΔNt W UΔx

(8.60)

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187

Using (8.58) and (8.60) in (8.57) for front interface, we can write δIds =Ids for front interface as follows:
 δIds R δΔNt 5 6 αμeff (8.61) N Ids W UΔx Thus the power spectrum density of the local current fluctuation at the front interface becomes 2
2
Ids R SΔId ðx; f Þ 5 (8.62) 6 αf μeff SΔNt ðx; f Þ N W UΔx where SΔNt ðx; f Þ is the PSD of the mean square fluctuations in the number of occupied traps at the front interface [102,105] over the area W UΔx. Following similar methodology, as discussed in [102], we get the noise spectral density, Sid , as ð ð kTqIds μeff Vds  1 L R2 dV (8.63) N ðE Þ Sid ðf Þ 5 2 SΔId ðx; f ÞΔxUdx 5 fn t L 0 γ f EF L 2 0 N where Nt ðEfn Þ 5 NOIA 1 NOIB 3 N 1 NOIC 3 N 2 . Parameter EF is used to capture the process-induced variability in flicker noise behavior [90]. NOIA, NOIB, and NOIC are the technology-dependent model parameters. V is the channel potential (i.e., 0 V at the source end, while Vds at the drain end). By integrating (8.63), drain noise spectral density expression for linear region becomes " ! kTq2 μ0 ðT ÞIds N0 1 N Sid 5 U NOIAUln 1 NOIBUðN0 2 Nl Þ 2 Nl 1 N Cox Leff ;noi Uγ # NOIC 2 2 ðN0 2 Nl Þ 1 2 (8.64) where Leff ;noi 5 Leff 2 2ULINTNOI. μ0 ðT Þ is the effective mobility at the given bias condition, LINTNOI is a parameter. Leff and Weff are the effective channel length and width, respectively. γ is the exponential coefficient for the position dependence of trapping time constant. N0 is the charge density at the source side given by N0 5

Cox Uqis q

(8.65)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Nl is the charge density at the drain end given by Nl 5

Cox Uqid q

(8.66)

where qis and qid are the channel charges at source and drain ends, respectively. In the pinch-off region, we integrate (8.63) only at x 5 L and substitute dx with ΔLclm . The expression becomes   kTIds2 ΔLclm NOIA 1 NOIBUNl 1 NOICUNl2 U (8.67) Sid 5 2 Weff UNFULeff ðNl 1N  Þ2 ;noi Uγ where ΔLclm is the channel length reduction due to channel length modulation and given by 
 Vds 2 Vdseff 1 ΔLclm 5 lUln U 1 EM (8.68) Esat;noi l where EM is a BSIM-IMG model parameter for channel length modulation, and Esat;noi is the saturation electric field. Thus in the strong inversion region, the noise density is written as Ssi 5

kTq2 μ0 ðT ÞIds kTIds2 ΔLclm UFN1 1 10 10 UFN2 2 2 Cox1 Leff Weff UNFULeff ;noi U10 ;noi U10

(8.69)

where terms FN1 and FN2 are expressed as
 N0 1 N NOIC 2 FN1 5 NOIAUln ðN0 2 Nl2 Þ 1 NOIBUðN0 2 Nl Þ 1 Nl 1 N 2 (8.70) FN2 5

NOIA 1 NOIBUNl 1 NOICUNl2 ðNl 1NÞ2

(8.71)

In the subthreshold region the

noise density is derived from (8.63) using relation dN=dV 5 2 q=kT as Swi 5

NOIAUkT UIds2 Weff UNFULeff ;noi UγUN 2

(8.72)

The unified physical flicker noise model is smooth over all bias regions. The total flicker noise density is Sid;flicker 5

Swi Ssi Swi 1 Ssi

(8.73)

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189

The expression (8.73) is implemented in the BSIM-IMG model for flicker noise calculation.

8.6.2 Other Noise Components Gate current shot noise: Shot noise originates due to the randomness of charge carriers in crossing potential barrier [49]. It is associated with every semiconductor device forming a p
n junction. Current flowing through a p
n junction requires crossing a potential barrier and number of carriers having enough energy to cross barrier varies randomly with time resulting in shot noise. In MOSFETs, current flowing from source to drain requires overcoming potential barrier at source end. In weak inversion, barrier is large enough to result in significant shot noise in drain current. With higher gate voltage, barrier at source becomes very small resulting in large number of carriers in channel and averaging out shot noise [88]. PSD of shot noise associated with drain current Ids is given by Sshot ðf Þ 5 2UqUIds

(8.74)

where q is the electron charge. Shot noise is assumed to be independent of temperature and is very difficult to measure owing to very small current in weak inversion. In BSIM-IMG model, we have modeled shot noise corresponding to each gate current component as i2gs 5 2qðIgcs 1 Igs 1 Igbs Þ

(8.75)

i2gd 5 2qðIgcd 1 Igd 1 Igbd Þ

(8.76)

where Igcs and Igcd are gate-to-channel current components. Igs and Igd are gate-to-source/drain current components. Igbs and Igbd are gate-to-body current components. Resistor noise model: As parasitic resistors contribute in channel thermal noise, it is important to capture their contribution in total thermal noise. The noise associated with each parasitic resistor in the BSIM-IMG model is calculated as follows: When RDSMOD 5 1, the source and drain resistances can be modeled as resistor elements. The noise associated with Rsource and Rdrain are given as i2RS 1 5 4kT U Rsource Δf

(8.77)

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Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

i2RD 1 5 4kT U Rdrain Δf

(8.78)

where i2RS and i2RD are the noise current sources in parallel with Rsource and Rdrain , respectively. Similarly, when RGATEMOD 5 1, the gate electrode resistance can be modeled as a resistor element (Rgeltd ), and we have i2RG 1 5 4kT U Rgeltd Δf

(8.79)

where i2RG is the noise current source in parallel with Rgeltd .

8.7 APPENDIX

8.7.1 Simplification of gðV 1 vÞU ðdðV 1 vÞÞ=dy Expanding gðV 1 vÞ around V by Taylor series [106] up to first term, we get   dðV 1 vÞ dgðV Þ dV dðV 1 vÞ 5 gðV Þ 1 U Uðv 2 V Þ (8.80) gðV 1 vÞU dy dV dv dy Considering only first-order terms, we get gðV 1 vÞU

dðV 1 vÞ dV dv gðV Þ dV 5 gðV Þ 1 gðV Þ 1 vU U dy dy dy dV dy

gðV 1 vÞU

dðV 1 vÞ dV d 5 gðV Þ 1 ðvUgðV ÞÞ dy dy dy

(8.81)

(8.82)

8.7.2 Derivation for Relation Between dqf and dV For FD-SOI MOSFETs, solution of Poisson’s equation and boundary conditions are given by [61] [107] 

 2qNc Vt ψ1 2 V ψ2 2 V 2 2 Es1 2 Es2 5 exp 2 exp (8.83) Vt Vt εsi where Es1 and Es2 are vertical fields at front and back interfaces, respectively. q is electronic charge, Nc is the effective density of states of conduction band, and εsi is the permittivity of silicon. Boundary conditions for FD-SOI MOSFETs are given by

High-Frequency and Noise Models in BSIM-IMG

191

Cox1 ðVfg 2 Δφ1 2 ψ1 Þ 5 εsi Es1

(8.84)

Cox2 ðVbg 2 Δφ2 2 ψ2 Þ 5 εsi Es2

(8.85)

Here VfgðbgÞ are voltage applied at front (back) gate terminal, and Δφ1ð2Þ are work function difference between front (back) gates and source terminal. From Gauss’s law, inversion charge is given by Q 5 εsi ðEs1 2 Es2 Þ

(8.86)

Since we are considering charge from front gate, so we neglect the second exponential in (8.83) and use it with (8.86) to get sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 ψ 2V 1 ðεsi Es2 Þ2 2 εsi Es2 Qf 5 2qεsi Nc Vt exp 1 Vt

(8.87)

Differentiate (8.87) w.r.t. channel position y, we get

  dQf 1 ψ1 2 V dψ1 dV U 5 2qεsi Nc Vt exp 2 2ðQf 1 εsi Es2 Þ Vt dy Vt dy Vt dy (8.88) Simplifying (8.88) dQf ðQ f 1 2εsi Es2 Þ Qf dψ1 dV 5 U U 2 dy 2ðQf 1 εsi Es2 Þ Vt dy dy

! (8.89)

Defining ηf as [61] ηf 5 2 Using ηf in (8.89)

ðQf 1 εsi Es2 Þ ðQf 1 2εsi Es2 Þ


 dQf Qf dψ1 dV 5 2 dy dy ηf Vt dy

(8.90)

(8.91)

Using qf 5 Qf =Cox1 Vt dqf ηf Vt dV dψ 52 1 1 dy dy qf dy

(8.92)

192

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Using (8.84) dqf ηf Vt dqf dV 2 Vt 52 dy dy qf dy
 q f 1 ηf dqf dV 5 2 Vt qf

(8.93) (8.94)

8.7.3 Derivation for Relation Between dqb and dV Similar to Section 8.7.2, here we will consider charge due to back gate only, so we neglect the first exponential in (8.83) and use it with (8.86) to get sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 ψ2 2 V 2 Qb 5 εsi Es1 2 ðεsi Es1 Þ 1 2qεsi Nc Vt exp (8.95) Vt Differentiate (8.95) w.r.t. channel position y, we get

  dQb 1 ψ2 2 V dψ2 dV 52 2qεsi Nc Vt exp 2 U 2ðεsi Es1 2 Qb Þ Vt dy Vt dy Vt dy (8.96) Simplifying (8.96)

!

Qb 2εsi Es1 2 Qb dQb dψ2 dV

U 5 2 dy Vt dy Vt dy 2 εsi Es1 2 Qb

(8.97)

Defining ηb as ηb 5

2ðεsi Es1 2 Qb Þ 2εsi Es1 2 Qb

(8.98)

Using ηb in (8.96), we get dQb ηb Vt dψ dV 5 22 dy dy Qb dy

(8.99)

Using qb 5 Qb =Cox2 Vt and (8.85) and following similar steps as in part 1, we get
 q b 1 ηb dV 5 2 Vt dqb (8.100) qb

High-Frequency and Noise Models in BSIM-IMG

193

8.7.4 Charge Partition Between Front and Back Gates BSIM-IMG produces total inversion charge which includes the contribution of both front and back gates. For the purpose of our model validation, we need individual contribution from each gate. Inversion charge contribution from front (back) gate will be directly proportional to oxide capacitance (Cox1ðox2Þ ) and voltage applied to gate (VfgðbgÞ ). Based on this assumption, we have defined following two quantities that represent the ratio of inversion charge at front and back interfaces. rs1 5

rs2 5

Cox1 UV 0fg Cox1 UV 0fg 1 Cox2 UV 0bg

(8.101)

Cox2 UV 0bg

(8.102) Cox1 UV 0fg 1 Cox2 UV 0bg h qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffii 2 where V 0fgðbgÞ 5 0:5U VfgðbgÞ 1 VfgðbgÞ 1 4c 2 and c 5 0:1. V 0fgðbgÞ ensures that only positive values of VfgðbgÞ will contribute to the inversion charge at front (back) gate. Sum of rs1 and rs2 is always unity implying charge conservation, and these ratios satisfy all asymptotic conditions. For larger Vfg , almost all the charge will be at front gate and vice versa for back gate. For symmetrical gate operation (FinFETs) that is, Cox1 5 Cox2 and Vfg 5 Vbg , rs1 and rs2 will be 1=2 representing equal contribution from both sides.

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39.

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INDEX Note: Page numbers followed by “f” and “t” refer to figures and tables, respectively.

A AC symmetry test, 128
129, 129f Accumulation to weak-inversion region, 119 Admittance parameters (Y-parameters), 146
147 Ambient temperature impact on thermal resistance, 83
84, 84f Asymptotic behavior of thermal noise model, 176
178

B Back bias effect, 159
162 on threshold voltage, 112
113, 113f Back gate, 15
19 charge partition between front and, 193 Backplane region, 45
46 Bandgap temperature dependence, 77 BG0SUB parameter, 77 Bias-dependent capacitor, 90
91, 90f, 92f source/drain resistance, 61
62 Bias-independent capacitances, 103 capacitor, 90
91, 90f resistance, 61 Body doping effect, 45 Body effect, 3 Body-bias effect, 98
99 Body-doping effect, 98
99 Boltzmann distribution, 65
66, 66f Boltzmann tyranny. See Boltzmann distribution BOX. See Buried oxide (BOX) BSIM-IMG model, 10
11, 30
33, 35, 66, 71
72, 89, 92
93 channel current expression, 62 charge partition between front and back gates, 193 compact model, 23

extraction of large-sized device parameters, 109
113 extraction of temperature dependence parameters, 120
123 first step of parameter extraction, 108
109, 108t global parameter, 107
108 leakage current extraction, 116
120 local parameter, 107
108 short-channel device extraction and length scaling, 114
116 dqb and dV relation, 192 dqf and dV relation, 190
192 drain saturation voltage, 51
55 extrinsic capacitance model in, 102
105 FDSOI compact model, 13 g(V 1 v)  ((d(V 1 v))/dy) simplification, 190 intrinsic terminal charge model in, 93
98 lateral nonuniform doping model, 57 output conductance model, 57
59 quality model validation with germanium on insulator FD-SOI transistor, 136
142 symmetry tests, 125
130 test for self-heating effect, 134
136 weak and strong inversion test, 130
134 quantum mechanical effects, 56 series resistance model, 60
62 threshold voltage, 39
51 velocity saturation effect, 59
60 vertical field dependence of carrier mobility, 35
39 Buried oxide (BOX), 72, 104
105, 105f, 155
156

201

202

Index

C Calibration, 147
148 Capacitance(s) calculation from terminal charges, 90
93 reciprocity test, 130, 132f Carrier mobility, vertical field dependence of, 35
39 Carrier velocity saturation, 51
53 Channel charge fluctuation, 179
182 Channel current expression, 62 Channel doping concentration, 108t Channel length modulation, 166 Channel thermal noise in MOSFETs, 162
163 Channel-length modulation effect, 57
58, 101
102 Characteristic length, 41
42 Charge conservation principle, 91 CMOS transistor, 1
3 pre-2010 SOI scaling, 3
5 Compact models, 10
13, 15, 15f, 125, 130 Conductance of MOSFET, 164 test, 130
132, 133f Conduction band density of states (Nc), 77
78 Core model for independent multigate MOSFETs, 18
26 analytical solution, 26
28 extended range model, 23
26 fast, 19
23 model variables, 25t Coulomb scattering effect, 35
37, 110
111 CTH0 model parameter, 72
73

D De-embedding, 148
149 DIBL. See Drain-induced barrier lowering (DIBL) Digital circuits, 65 DITS. See Drain-induced threshold voltage shift (DITS) Drain current IDS vs. VGS at small VDS, 109
111 strong-inversion region, 110
111

subthreshold region, 109
110 IDS vs. VGS at VDS 5 VDD strong-inversion region, 111
112 subthreshold region, 111 Drain current model for independent-gate MOSFETs, 28
30 Drain leakage model, 66
68 Drain saturation electric field, 101
102 Drain saturation voltage, 51
55. See also Threshold voltage (Vt) MEXP parameter, 54f RDSMOD, 55 Drain-channel junction, 66
67 Drain-induced barrier lowering (DIBL), 42
43, 66, 89
90, 98
99, 166 output conductance to, 58
59 temperature dependence, 81 Drain-induced threshold voltage shift (DITS), 44
45

E Effective drain
source voltage models (Vdseff), 100
101 Energy bandgap, 77 Extended range core model, 96
98, 98f Extended range model for independent multigate MOSFETs, 23
26 Extraction of large-sized device parameters, 109
113 back bias effect on threshold voltage, 112
113 drain current IDS vs. VGS at small VDS, 109
111 drain current IDS vs. VGS at VDS 5 VDD, 111
112 gate capacitance CGG vs. VGS, 109 IDS and gDS vs. VDS, 112 of Rth, Cth, 85 of temperature dependence parameters, 120
123 Extrinsic capacitance model in BSIM-IMG, 102
105 outer fringe capacitance, 102
103 overlap capacitance model, 103
104 source/drain to substrate fringe capacitance, 104
105

Index

F Fast core model for independent multigate MOSFETs, 19
23 surface potential in, 20
23 terminal charges in, 93
96 FDSOI. See Fully depleted silicon-oninsulator (FDSOI) Fermi potentials at body (ɸB), 77
78 at substrate regions (ɸSUB), 77
78 Field penetration length, 39
41, 47 Figure of merit (FoM), 149
151 FinFET, 9
10 First silicon success, 12
13 First-order thermal network, 84
85, 85f Flicker noise model, 185
189 FoM. See Figure of merit (FoM) Frequency dependence of self-heating effect, 84
85 extraction of Rth, Cth, 85 frequency-domain circuit simulations, 89 Front gates, 16
19, 193 capacitance, 98, 99f charge partition between back and, 193 Fully depleted silicon-on-insulator (FDSOI), 1
3, 18, 65, 72f, 112
113, 125
126, 145
146, 145f based CMOS transistors, 145
146 characteristics, 146 compact model, 12
13 comparison with other ultrathin-body transistors, 9
10 model validation with Ge on insulator, 136
142 MOSFETs, 35 real-device-phenomena model equations, 13

G Gate capacitance CGG vs. VGS, 109, 110f Gate current shot noise, 189 Gate leakage current, 119
120 accumulation to weak-inversion region, 119 weak to strong-inversion region, 120

203

Gate oxide leakage, 68
72 gate-to-body tunneling current, 69
70 gate-to-channel tunneling current, 70
71 gate-to-source (drain) tunneling current, 71
72 Gate parasitic network, 157
159 gate capacitance network, 158
159 gate resistance network, 159 Gate-induced drain leakage (GIDL), 66
67, 82, 116
118, 119f Gate-induced source, 66
68 band-to-band tunneling at drain junction, 67f Gate-induced source leakage (GISL), 68, 82 Ge. See Germanium (Ge) GeOI-FD-SOI. See Germanium on insulator-FD-SOI (GeOI-FD-SOI) Geometrical dependence of thermal resistance, 73
75 Germanium (Ge), 136 Germanium on insulator-FD-SOI (GeOIFD-SOI), 136, 136f. See also Fully depleted silicon-on-insulator (FDSOI) germanium on insulator-based CMOS inverter, 141
142 model results and circuit level validation, 140
141 modeling, 136
139 GIDL. See Gate-induced drain leakage (GIDL) GISL. See Gate-induced source leakage (GISL) GlobalFoundries 22FDX technology, 13 Graphene nanowires, 10 Ground
signal
ground pad set (G
S
G pad set), 146
147 Gummel symmetry test, 126
127, 126f, 127f

H H-parameters. See Hybrid parameters (Hparameters) Halley’s method of numerical calculation, 50

204

Index

Halo region, 43
44 Harmonic balance test, 130, 131f Harmonic distortion, 130 Heat flow plane, 75 High-frequency (HF). See also Radiofrequency (RF) experimental validation of highfrequency noise parameters, 173
176 modelling of transistors, 145 High-k metal gate transistors, 157
158 High-resistivity (HR), 145 Hooge’s model, noise PSD from, 185
187 Hot chuck measurement, 85, 86f HR. See High-resistivity (HR) Hybrid parameters (H-parameters), 146
147

I ICs. See Integrated circuits (ICs) IGN. See Induced gate noise (IGN) IMG. See Independent-multigate (IMG) Impedance parameters (Z-parameters), 146
147 Impedance Standard Substrate (ISS), 147
148 Independent-multigate (IMG), 10
11 MOSFETs, 16
18 core model, 18
26 core model analytical solution, 26
28 drain current model, 28
30 terminal charge model, 30
33 3D schematic of ultrathin-body silicon-on-insulator device, 16f Induced gate noise (IGN), 168
169 Induced gate thermal noise model, 179
190. See also Thermal noise model Flicker noise model, 185
189 noise components, 189
190 Integrated circuits (ICs), 145 Intrinsic carrier concentration, temperature dependence of, 77 Intrinsic charge model in extended range core model, 96
98 Intrinsic terminal charge model in BSIMIMG, 93
98

in extended range core model, 96
98 in fast core model, 93
96 Inversion charge, 22 density, 92
94 at threshold condition, 49 Ioff current, 65
66 Isothermal frequency, 84
85 ISS. See Impedance Standard Substrate (ISS)

K K1RSCE model, 43
44 Klaassen
Prins equation, 164, 179
182

L Large-sized device parameters, extraction OF, 109
113 Lateral nonuniform doping model, 57 Leakage currents extraction gate leakage current, 119
120 GIDL, 116
118 and modeling gate oxide leakage, 68
72 gate-induced source and drain leakage model, 66
68 subthreshold leakage, 65
66 temperature dependence, 82 Length scaling of temperature parameters, 122
123, 122f Long channel DIBL, 44
45 Low-frequency noise, 162

M Mobility degradation, 99
102 temperature dependence, 78
81, 80f MoS2 films, 10 MOSFET, 65
66, 69f BSIM, 10
11 channel thermal noise in, 162
163 drain current model for independentgate, 28
30 single-digit-nm, 4

Index

205

N

Q

Narrow-width effects, 109 Newton’s method, 27 Noise figure (NF), 149
151 Noise figure meter (NFM), 166
167 Noise models, 159
166 Nonmonotonic back-gate bias dependence of mobility, 37
39

Quantum mechanical effects, 56, 89
90

O One-dimensional Poisson’s equation, 19, 24 1/f noise. See Flicker noise model OPEN-SHORT de-embedding method, 148
149, 150f Operating point threshold voltage, 48
51 Outer fringe capacitance, 102
103, 103f Output conductance model, 57
59. See also Series resistance model channel-length modulation effect, 57
58 DIBL effect, 58
59 Overlap capacitance model, 103
104 Oxide
semiconductor interface, 35
37

P Parameter extraction with BSIM-IMG compact model first step of parameter extraction, 108
109, 108t global parameter, 107
108 large-sized device parameters, 109
113 leakage current extraction, 116
120 local parameter, 107
108 short-channel device extraction and length scaling, 114
116 temperature dependence parameters, 120
123 Parasitic source/drain resistances, 82
83 Partial depletion, 1
3 Partially depleted SOI (PDSOI), 1
3 Phonon scattering, 35
37 Pinch-off, 51
54 effects, 100
101, 101f Planar bulk MOSFET, 3
4 PMOS, 38
39, 69
70, 136 Power spectral density (PSD), 163 Pre-2010 SOI CMOS transistor, 1
3

R Radio-frequency (RF), 145 characterization, 146
149 experimental setup, 148f modeling and parameter extraction, 149
159 N-channel MOSFETs for two-port RF characterization, 147f NFM, 167f parameter extraction flow in FD-SOI MOSFETs, 161f Radio-frequency-silicon-on-insulator (RFSOI), 145 MOSFET, 145
146 Real device effects, 35 impact of channel-length modulation, 101
102 of mobility degradation, 99
100 of pinch-off and velocity saturation, 100
101 on terminal charges, 98
102, 100f Resistor noise model, 189 Reverse short-channel effect (RSCE), 43
44, 98
99. See also Shortchannel effects (SCEs) of threshold voltage, 43
44 RF. See Radio-frequency (RF) RF-SOI. See Radio-frequency-silicon-oninsulator (RF-SOI) RSCE. See Reverse short-channel effect (RSCE)

S Scattering parameters (S-parameters), 146
147, 171 SCEs. See Short-channel effects (SCEs) SD. See Second derivative (SD) Second derivative (SD), 50 Self-heating effect (SHE), 72
75, 73f, 134
135, 146 frequency dependence, 84
85 impact, 135f

206

Index

Self-heating effect (SHE) (Continued) parameter RTHL in Rth, 75f Rth variation with channel length, 74f Rth vs. channel length, 74f, 76f SHE-induced temperature rise, 72
73, 76
77 test for, 134
136, 135f Series resistance model, 60
62. See also Output conductance model bias-dependent source/drain resistance, 61
62 bias-independent resistance, 61 SHE. See Self-heating effect (SHE) Short-channel device extraction and length scaling, 114
116 first and second derivative of transconductance, 117f IDS vs. VGS characteristics, 117f, 118f threshold voltage vs. gate length characteristics, 114f Short-channel effects (SCEs), 39, 89
90, 98
99, 109 formulation, 66 of threshold voltage, 41
42, 42f Short-Open-Load-Thru calibration (SOLT calibration), 148, 149f Signal-to-noise ratio (SNR), 168
169 Silicon body capacitance, 93
94 Silicon on oxide (SOI), 1
3 transistors, 2f wafer, 1, 2f Silicon-on-insulator (SOI), 145 Single-digit-nm MOSFET, 4 Slope ratio test (SR test), 132
133, 134f Small-signal AC conductance technique, 85 voltage gain, 84
85 SNR. See Signal-to-noise ratio (SNR) SOI. See Silicon on oxide (SOI)Silicon-oninsulator (SOI) SOLT calibration. See Short-Open-LoadThru calibration (SOLT calibration) Source/drain to substrate fringe capacitance, 104
105 Source
drain built-in potential (Vbi), 77
78 SPICE model. See Compact model

Strong-inversion region, 110
112 Substrate depletion effect on threshold voltage, 45
48 Substrate parasitic network, 155
157. See also Gate parasitic network Subthreshold drain-to-source leakage current, 65
66 leakage, 65
66 region, 109
111 Surface potential in fast core model, 20
23 Symmetry tests, 125
130 AC, 128
129, 129f capacitances reciprocity test, 130, 132f Gummel, 126
127, 126f, 127f harmonic balance test, 130, 131f

T TBGASUB temperature coefficient, 77 TBGBSUB temperature coefficient, 77 Technology Computer Aided Design simulations (TCAD simulations), 27
28, 95, 96f Temperature dependence of parameters, 76
83 bandgap temperature dependence, 77 of drain-induced barrier lowering, 81 extraction, 120
123 length scaling of temperature parameters, 122
123 of intrinsic carrier concentration, 77 of leakage currents, 82 of mobility, 78
81 of parasitic source/drain resistances, 82
83 of threshold voltage, 78 of velocity saturation, 81 Terminal charge and capacitances in BSIM-IMG calculation from terminal charges, 90
93 extrinsic capacitance model, 102
105 intrinsic terminal charge model, 93
98 impact of real device effects, 98
102 model, 30
33 Thermal effects and modeling, 72
85

Index

impact of ambient temperature on thermal resistance, 83
84 frequency dependence of self-heating effect, 84
85 modeling of self-heating effect, 72
75 temperature dependence of parameters, 76
83 Thermal noise model, 159
166. See also Induced gate thermal noise model asymptotic behavior of model, 176
178 characterization, 166
171 experimental validation of highfrequency noise parameters, 173
176 parameters, 168
171 validation, 171
178 Thermal resistance, 72
73 ambient temperature impact on, 83
84 network, 151
154 Threshold voltage (Vt), 39
51. See also Drain saturation voltage back bias effect on, 112
113 body doping effect, 45 channel length vs., 44f DIBL, 42
43 operating point, 48
51 roll-off, 41
42 at moderate channel length, 44
45 RSCE of threshold voltage, 43
44 shift, 47 for short-channel device, 50 short-channel effects, 41
42, 42f substrate depletion effect on, 45
48 temperature dependence of, 78, 79f Total back-gate charge, 95 Total gate-to-body current, 70 Transistors, 136 Tunneling current, 69 density, 67
68 Two-dimensional Poisson’s equation in silicon body, 39
40 Two-port network, 146
147

207

U Ultrathin-body fully depleted SOI (UTB (FD)SOI), 5, 9 Ultrathin-body scaling concept (UTB scaling concept), 5
9 comparison of FDSOI with other ultrathin-body transistors, 9
10 UTB-SOI transistor, 6
7, 18f

V Velocity saturation, 100
101 effect, 59
60 temperature dependence, 81 Vertical field dependence of carrier mobility, 35
39 nonmonotonic back-gate bias dependence of mobility, 37
39 Volume inversion test, 133
134

W Ward
Dutton partitioning scheme, 95 Weak and strong inversion test, 120, 130
134. See also Symmetry tests conductance test, 130
132, 133f drain current at different body thickness, 134f slope ratio test, 132
133, 134f volume inversion test, 133
134 Weak-inversion region, accumulation to, 119 Wiener
Khintchine theorem, 163 WSe2 films, 10

Y Y-parameters. See Admittance parameters (Y-parameters)

Z Z-parameters. See Impedance parameters (Z-parameters)