Polynomial Formal Verification of Approximate Functions (BestMasters) 3658418877, 9783658418878

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BestMasters

Martha Schnieber

Polynomial Formal Verification of Approximate Functions

BestMasters

Mit „BestMasters“ zeichnet Springer die besten Masterarbeiten aus, die an renommierten Hochschulen in Deutschland, Österreich und der Schweiz entstanden sind. Die mit Höchstnote ausgezeichneten Arbeiten wurden durch Gutachter zur Veröffentlichung empfohlen und behandeln aktuelle Themen aus unterschiedlichen Fachgebieten der Naturwissenschaften, Psychologie, Technik und Wirtschaftswissenschaften. Die Reihe wendet sich an Praktiker und Wissenschaftler gleichermaßen und soll insbesondere auch Nachwuchswissenschaftlern Orientierung geben. Springer awards “BestMasters” to the best master’s theses which have been completed at renowned Universities in Germany, Austria, and Switzerland. The studies received highest marks and were recommended for publication by supervisors. They address current issues from various fields of research in natural sciences, psychology, technology, and economics. The series addresses practitioners as well as scientists and, in particular, offers guidance for early stage researchers.

Martha Schnieber

Polynomial Formal Verification of Approximate Functions

Martha Schnieber Bremen, Germany

ISSN 2625-3577 ISSN 2625-3615 (electronic) BestMasters ISBN 978-3-658-41887-8 ISBN 978-3-658-41888-5 (eBook) https://doi.org/10.1007/978-3-658-41888-5 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer Vieweg imprint is published by the registered company Springer Fachmedien Wiesbaden GmbH, part of Springer Nature. The registered company address is: Abraham-Lincoln-Str. 46, 65189 Wiesbaden, Germany

Foreword

The complexity of modern circuits has grown tremendously over the last decades. While the first processors in the early 70s consisted of a few thousand components, todays’ high-end devices are composed of more than 50 billion elements. On top of this, in the context of designing Cyber-Physical Systems (CPS) also the interaction with the environment has to be taken into account. In the past 30 years an impressive improvement in these methods can be observed resulting in fully automated design tools that are provided by EDA companies these days. While in the early years of EDA the overall process was purely design centered, i.e., how to realize a given specification with few components (small area) and short depth (high speed), in recent years the quality of the resulting circuit after production, but throughout the entire lifetime became more important. This is motivated by the fact that electronic is used in many safety critical scenarios, like in cars and planes. In this context methods and tools are needed that allow to efficiently verify the correctness of components. The early approaches were based on simulation on emulation, but todays’ complexity can only be handled by formal methods that allow to prove the correctness in a mathematical sense. However, formal verification methods can have an exponential time and space complexity and by this often fail for complex designs. To overcome this problem, recently the concept of Polynomial Formal Verification (PFV) has been introduced. Here, efficient upper bounds on the complexity of the proof process are provided allowing efficient verification of complete designs. This book makes a significant contribution to the ongoing research activities. It is based on the master thesis of Martha Schnieber, which she has written as a student in the Group of Computer Architecture (AGRA) at the University of Bremen, Germany.

v

vi

Foreword

In her thesis she studied the class of approximate circuits that are used in error-tolerant applications, such as image processing. Here, the area or the depth of the circuits is reduced and the approximation can be evaluated using error metrics. It is shown that several state of-the-art approximate circuits are verifiable in polynomial time and space. Apart from the theoretical proofs, the presented methods are implemented and evaluated, further showing the correctness and significance of the results. The quality of her findings is also confirmed by two publications at international conferences in the field, that resulted from the thesis: • “Polynomial Formal Verification of Approximate Functions”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2022, Pafos, Cyprus. • “Polynomial Formal Verification of Approximate Adders”, Euromicro Conference on Digital System Design (DSD) 2022, Gran Canaria, Spain. I hope you will enjoy reading this book. Bremen March 2023

Prof. Dr. Rolf Drechsler [email protected]

Parts of this work have already been published in: • © 2022 IEEE. Reprinted, with permission, from [1]: M. Schnieber, S. Froehlich, and R. Drechsler, “Polynomial formal verification of approximate functions,” in 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022, pp. 92–97. • © 2022 IEEE. Reprinted, with permission, from [2]: M. Schnieber, S. Froehlich, and R. Drechsler, “Polynomial formal verification of approximate adders,” in 2022 25th Euromicro Conference on Digital System Design (DSD), 2022, pp. 761–768.

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

2 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Boolean Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Symmetric Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Adder Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Ripple Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Conditional Sum Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Carry Look Ahead Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Approximate Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Error Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Bit Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Average-Case Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 Mean-squared Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Binary Decision Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 ITE-Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 3 4 4 4 5 6 7 8 9 9 9 10 10 11 13 14

3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

4 Polynomial Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 General Approximate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Polynomially Verifiable Multiplexer Circuit . . . . . . . . . . . . . 4.1.2 Polynomially Verifiable XOR Circuit . . . . . . . . . . . . . . . . . . 4.1.3 Error Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 17 21 24 26

ix

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Contents

4.2 Approximate Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 ETAII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 GDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 ACAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 ACAII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 GeAr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Altered Ripple Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 Altered Conditional Sum Adder . . . . . . . . . . . . . . . . . . . . . . . 4.2.8 Altered Carry Look Ahead Adder . . . . . . . . . . . . . . . . . . . . .

29 29 31 33 34 35 36 41 46

5 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 General Approximate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Approximate Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

51 51 51 53 57 57 58

6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

75

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

77

1

Introduction

Digital circuits play a significant role in modern systems, as they are responsible for a numerous amount of calculations. They can be found in a variety of applications such as smartphones or smartwatches, but also in safety-critical systems like airplanes, cars or medical equipment. Thus, ensuring the correctness and safety of these circuits has become a very important task. Specifically, ensuring that the designed circuit correctly implements the specified function is critical. One possibility to check the correctness of the circuit is through thorough testing, meaning checking the output of the circuit for a variety of inputs. However, unless the circuit is tested for every possible input, the correctness of the circuit cannot be proven with this method. As there exist an exponential amount of possible inputs to a circuit, testing every input is not feasible. Thus, formal verification methods have been established to prove the correctness of a circuit [3] [4]. This can be done using multiple formal methods, such as SMT, SAT, BDDs [5] or other kinds of decision diagrams such as *BMDs [6]. Here, the circuit correctly implements the specification if e.g. the BDDs for the circuit and the specification are equal. Hence, the BDD for the circuit has to be constructed. However, during the computation of the formal representation of the function realized by the circuit, the formal representation can reach an exponential size and therefore, the verification can fail due to time or space constraints [7]. Predicting the time and space complexity of the verification process of specific circuits is a challenge that has not been focussed by research yet. Nonetheless, in the past years, it has been shown for several circuits that they can be verified efficiently in polynomial time and space, such as various adder circuits [7] [8] [9] or Wallacetree like multipliers [10]. Here, the formal representation of the functions has a major impact as well, e.g. for the Wallace-tree like multipliers, the verification using BDDs has an exponential complexity [11], whereas the verification using *BMDs is feasible in polynomial time and space [10]. © The Author(s), under exclusive license to Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 M. Schnieber, Polynomial Formal Verification of Approximate Functions, BestMasters, https://doi.org/10.1007/978-3-658-41888-5_1

1

2

1

Introduction

Apart from proving the polynomial verifiability of existing circuits, a related challenge is the construction of a polynomially verifiable circuit for a specific function. In [12], it has been shown that a circuit which is verifiable in polynomial time and space can be constructed for every symmetric function. For some applications which have hardware or time restrictions, the exact output of a specific function is not necessary but an approximate output is sufficient. For these applications, the function can be approximated, resulting in a similar function which computes a different output in some cases. In return, the circuit for the approximate function is more area-efficient or has a lower delay, which is benefitting if there exist area or time restrictions [13] [14]. No research has yet focused on proving the polynomial verifiability of such approximate functions. Thus, this thesis provides methods to prove the polynomial verifiability of circuits for several approximate functions. Firstly, we show that there exists a polynomially verifiable circuit for a function g if g is an approximation of a function f for which a polynomially verifiable circuit is known and where g and f differ for a polynomial amount of input assignments. Here, we present two synthesis strategies for the generation of polynomially verifiable circuits for g and give upper bounds for the size of the BDDs during the verification process of these circuits. Furthermore, we give an upper bound for both the time and space complexity of the verification process. As approximate functions are typically evaluated using error metrics, we also explore the correlation of the error between f and g and the BDD sizes during the verification process for several error metrics. As a specific kind of approximate function, we also prove the polynomial verifiability of several state-of-the-art approximate adders, where we give upper bounds for the sizes of the BDDs during the verification process, as well as upper bounds for the time and space complexity of the verification process. The remainder of this thesis is structured as follows: In Chapter 2, the relevant preliminaries for this thesis are explained, followed by a presentation of related work in Chapter 3. Subsequently, in Chapter 4, we prove the polynomial verifiability of several circuits. This chapter is divided into two parts: In Section 4.1, we construct polynomially verifiable circuits for functions which differ from another function with a polynomially verifiable circuit in a polynomial amount of cases. Then, in Section 4.2, we show the polynomial verifiability of several approximate adders, including handcrafted and automatically generated approximate adders. Afterwards, in Chapter 5, we evaluate the methods described in Chapter 4 by comparing the given upper bounds for the BDD sizes to the sizes of the actual BDDs during the verification process. Finally, Chapter 6 summarizes this thesis and the results.

2

Preliminaries

In this chapter, relevant definitions and concepts are explained. These include general Boolean Functions, including some specific functions, as well as several adder architectures. Furthermore, the concepts of approximate adders and error metrics are described, followed by the basics of BDDs and formal verification.

2.1

Boolean Functions

Let f : {0, 1}n → {0, 1}m be a Boolean function with n inputs and m outputs. Then, α = (α1 , . . . , αn ) ∈ {0, 1}n is an assignment for the function f , meaning a truth value is assigned to every input variable. α( f ) is the assignment applied to f , where every input variable xi is replaced by αi . As every input variable can be either 1 or 0, there exist 2n different assignments for f . For each assignment α, there exists a minterm m α which is defined as α

n−1 m α = x1α1 · x2α2 · · · · · xn−1 · xnαn

Here, xi1 = xi and xi0 = x i . Therefore, m α is a conjunction of all input variables, where every variable is either a positive or a negated literal, depending on the assignment α [15]. In the following sections, we give a detailed overview over symmetric and adder functions, which are relevant for this thesis.

© The Author(s), under exclusive license to Springer Fachmedien Wiesbaden GmbH, part of Springer Nature 2023 M. Schnieber, Polynomial Formal Verification of Approximate Functions, BestMasters, https://doi.org/10.1007/978-3-658-41888-5_2

3

4

2.1.1

2

Preliminaries

Symmetric Functions

A Boolean function f is symmetric if it is invariant under all possible input permutations σ and consequently its output depends only on the number of inputs set to 1 and not their positions: f (x1 , x2 , . . . , xn ) = f (xσ (1) , xσ (2) , . . . , xσ (n) ) A symmetric Boolean function S n (A) with n inputs and A ⊆ {0, 1, . . . , n} evaluates to 1 for an assignment α if and only if α sets exactly Ai inputs to 1, where Ai ∈ A [16][17].

2.1.2

Adder Function

The adder function takes an incoming carry bit c−1 as input, as well as two input numbers a and b with n bits respectively. Thus, it has 2n + 1 input bits: (an−1 , . . . , a0 , bn−1 , . . . , b0 , c−1 ). Its output is the sum of a, b and c−1 , which has n + 1 bits: (cn−1 , sn−1 , . . . , s0 ). Here, cn−1 is the carry output bit and sn−1 , . . . , s0 are the sum bits. The sum and carry bits can be calculated as follows: ci = ai bi + ai ci−1 + bi ci−1 si = ai ⊕ bi ⊕ ci−1 Thus, the carry bit ci , as well as the sum bit si can be calculated using ai , bi and ci−1 [18].

2.2

Adders

Several state-of-the-art adder architectures exist, of which we present the three most prominent ones in this section. Two of these adder architectures are based on Full Adders (FAs), which are shown in Figure 2.1. Here, the circuit for a FA is shown, as well as the corresponding symbol. A FA has three inputs ai , bi and ci−1 and two outputs si and ci , which represent the calculated sum of the three inputs. Here, ci−1 is the carry-in signal and ci is the carry-out signal [18].

2.2 Adders

2.2.1

5

Ripple Carry Adder

The Ripple Carry Adder (RCA) consists of n FAs, which are connected through a carry chain. The general structure of a RCA is shown in Figure 2.2: The i-th FA has the inputs ai ,bi and ci−1 and the computed carry-out ci is passed on to the next FA. The carry-out cn−1 of the final FA is the carry-out of the entire sum. Furthermore, the i-th FA also computes the sum bit si . The RCA has O (n) gates and a depth of O (n). Therefore, it is very area-efficient but has a high delay [18].

Figure 2.1 Circuit and symbol for a FA

Figure 2.2 Ripple Carry Adder

6

2

Preliminaries

Figure 2.3 Conditional Sum Adder ©2022 IEEE. (Reprinted, with permission, from [2])

2.2.2

Conditional Sum Adder

The Conditional Sum Adder (CSA) is defined recursively as shown in Figure 2.3. The lower halfs of the inputs are added by a CSA, whereas the higher halfs of the inputs are added by two CSAs in parallel: One CSA has its input carry bit set to 1 whereas the other CSA has its input carry bit set to 0. The higher half of the sum is then determined using a multiplexer which has the outputs of both CSAs as inputs, whereas the select input is set to the carry-out of the lower half of input bits. Thus, the select input is computed by the CSA which computes the sum of the lower input halfs. If this computed select input is 1, the higher half of the sum is the sum computed by the CSA with 1 as input carry bit and otherwise, it is the sum computed by the CSA with 0 as input carry bit. In the last recursive step, the CSAs are 1-bit adders, which are realized as FAs. Thus, a CSA with inputs of bitwidth n consists of one layer of FAs and log n layers of multiplexers. The CSA has an area of O (n · log n) and a depth of O (log n), making it less area-efficient than the RCA while having a lower delay [18].

2.2 Adders

7

Figure 2.4 Carry Look Ahead Adder ©2022 IEEE. (Reprinted, with permission, from [2])

2.2.3

Carry Look Ahead Adder

The Carry Look Ahead Adder (CLA) first computes all carry bits using a prefix computation. If all carry bits are calculated, the sum bits can be calculated as follows: si = ai ⊕ bi ⊕ ci−1 To compute the carry bits, two functions are calculated: the propagate function p and the generate function g. If 0 ≤ i ≤ k < j < n, p and g are defined as follows: pi,i = ai ⊕ bi gi,i = ai · bi p j,i = p j,k+1 · pk,i g j,i = g j,k+1 + p j,k+i · gk,i

8

2

Preliminaries

The carry bit ci can then be computed with ci = gi,0 + pi,0 · c−1 The structure of the CLA is shown in Figure 2.4, where the propagate function and generate function are shown as well. First, all gi,i and pi,i are computed and then, using the prefix computation, all gi,0 and pi,0 are computed, from which the carry bits and subsequently the sum bits are computed. The CLA has an area of O (n) and a depth of O (log n) and thus it is area-efficient and has a low delay [18].

2.3

Approximate Adders

Approximate Computing is often applied if the exact output of a function is not required, but an approximate output is sufficient, which is benificial in applications with e.g. hardware or time restrictions [13]. Approximate adders calculate the sum of two numbers with the possibility of some output bits being approximated. A common method for constructing approximate adders is the division into several subadders and the cutting of the carry chain between these subadders in order to reduce the depth and therefore the runtime. There exist several state-ofthe-art approximate adders which utilize this method, e.g. the approximate adders ETAII [19], GDA [20], ACAI [21], ACAII [22] and GeAr [23]. Another possibility for the reduction of area or delay is the alteration of regular adders by removing or changing the type of gates. Here, an algorithm is used to determine a set of gates which are to be altered such that the area or delay is reduced while keeping the error low [24] [25]. If a gate is removed, the output of this gate is replaced by one of its inputs. If the type of a gate is altered, it is changed from e.g. an AND gate to an OR gate. This alteration can be done with every type of regular adder, e.g. the RCA, CSA or CLA. Example 1 Figure 2.5 shows an example of an alteration, where Figure 2.5(a) shows the adder before the alteration. Here, the part of a RCA with n = 3 which calculates the output bit s2 is shown, where the individual FAs are framed for clarity. Figure 2.5(b) shows an arbitrarily altered version of Figure 2.5(a). Here, all gates in the first FA were removed and the carry-out of this FA was replaced with a0 . Furthermore, in the second FA, one AND gate is removed of which the output is replaced with a1 and the other AND gate is changed into an OR gate. Lastly, one of the XOR gates in the third FA is changed into an AND gate.

2.4 Error Metrics

9

Figure 2.5 Regular and altered RCA for the output s2 with n = 3

2.4

Error Metrics

Several error metrics have been proposed to evaluate an approximation by measuring the difference between two given functions. In this section, we give an overview of the error metrics which are relevant for this thesis. Here, f and g are functions with n inputs and m outputs and α is an assignment of the inputs.

2.4.1

Bit Threshold

The bit threshold is defined as

 

bt( f , g) =

α

i