Multi-MHz High Frequency Resonant DC-DC Power Converter [1st ed.] 9789811574238, 9789811574245

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CPSS Power Electronics Series

Dianguo Xu Yueshi Guan Yijie Wang Xiangjun Zhang

Multi-MHz High Frequency Resonant DC-DC Power Converter

CPSS Power Electronics Series Series Editors Wei Chen, Fuzhou University, Fuzhou, Fujian, China Yongzheng Chen, Liaoning University of Technology, Jinzhou, Liaoning, China Xiangning He, Zhejiang University, Hangzhou, Zhejiang, China Yongdong Li, Tsinghua University, Beijing, China Jingjun Liu, Xi’an Jiaotong University, Xi’an, Shaanxi, China An Luo, Hunan University, Changsha, Hunan, China Xikui Ma, Xi’an Jiaotong University, Xi’an, Shaanxi, China Xinbo Ruan, Nanjing University of Aeronautics and Astronautics, Nanjing Shi, Jiangsu, China Kuang Shen, Zhejiang University, Hangzhou, Zhejiang, China Dianguo Xu, Harbin Institute of Technology, Haerbin Shi, Heilongjiang, China Jianping Xu, Xinan Jiaotong University, Chengdu, Sichuan, China Mark Dehong Xu, Zhejiang University, Hangzhou, Zhejiang, China Xiaoming Zha, Wuhan University, Wuhan, Hubei, China Bo Zhang, South China University of Technology, Guangzhou Shi, Guangdong, China Lei Zhang, China Power Supply Society, Tianjin, China Xin Zhang, Hefei University of Technology, Heifei Shi, Anhui, China Zhengming Zhao, Tsinghua University, Haidian Qu, Beijing, China Qionglin Zheng, Beijing Jiaotong University, Haidian, Beijing, China Luowei Zhou, Chongqing University, Chongqing, Sichuan, China

This series comprises advanced textbooks, research monographs, professional books, and reference works covering different aspects of power electronics, such as Variable Frequency Power Supply, DC Power Supply, Magnetic Technology, New Energy Power Conversion, Electromagnetic Compatibility as well as Wireless Power Transfer Technology and Equipment. The series features leading Chinese scholars and researchers and publishes authored books as well as edited compilations. It aims to provide critical reviews of important subjects in the field, publish new discoveries and significant progress that has been made in development of applications and the advancement of principles, theories and designs, and report cutting-edge research and relevant technologies. The CPSS Power Electronics series has an editorial board with members from the China Power Supply Society and a consulting editor from Springer. Readership: Research scientists in universities, research institutions and the industry, graduate students, and senior undergraduates.

More information about this series at http://www.springer.com/series/15422

Dianguo Xu Yueshi Guan Yijie Wang Xiangjun Zhang •

•

•

Multi-MHz High Frequency Resonant DC-DC Power Converter

123

Dianguo Xu Harbin Institute of Technology Harbin, Heilongjiang, China

Yueshi Guan Harbin Institute of Technology Harbin, Heilongjiang, China

Yijie Wang Harbin Institute of Technology Harbin, Heilongjiang, China

Xiangjun Zhang Harbin Institute of Technology Harbin, Heilongjiang, China

ISSN 2520-8853 ISSN 2520-8861 (electronic) CPSS Power Electronics Series ISBN 978-981-15-7423-8 ISBN 978-981-15-7424-5 (eBook) https://doi.org/10.1007/978-981-15-7424-5 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

About This Book

This book analyzes multi-MHz high frequency resonant DC-DC power converters with operating frequencies ranging from several MHz to tens of MHz in detail, aiming to support researchers and engineers with a focus on multi-MHz high frequency converters. The inverter stage, rectifier stage, matching network stage are analyzed in detail. Based on the three basic stages, typical non-isolated and isolated resonant DC-DC converters are depicted. To reduce the high driving loss under multi-MHz, resonant driving methods are introduced and improved. Also, the design and selection methods of passive and active component under multi-MHz frequency are described, especially for aircore inductor and transformer. Furthermore, multi-MHz resonant converter provides an approach for achieving flexible system.

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Development of Multi-MHz Resonant Converter 1.2 Research of Multi-MHz Resonant Converter . . . 1.3 Contents of the Book . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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2 Resonant Inverter in Multi-MHz DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Infinite Inductor Resonant Inverter . . . . 2.2 Full Resonant Inverter Stage . . . . . . . . 2.2.1 Class E Inverter Stage . . . . . . . 2.2.2 Class U2 Inverter Stage . . . . . .

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3 Resonant Rectifier in Multi-MHz DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Floating Type Current-Driven Class E Rectifier . . . . . . . . . . . . . . 3.2 Ground Type Current-Driven Class E Rectifier . . . . . . . . . . . . . . .

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4 Matching Network in Multi-MHz DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction of Matching Network . . . . . . . . . . 4.2 L Type Matching Network . . . . . . . . . . . . . . . 4.2.1 Design of L Type Matching Network . . 4.2.2 Influence of L Type Matching Network 4.3 T Type Matching Network . . . . . . . . . . . . . . . 4.4 p Type Matching Network . . . . . . . . . . . . . . . 4.5 Example Based on T Type Matching Network .

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Contents

5 Typical Multi-MHz DC–DC Converter . . . . . . . . . . 5.1 Non-isolated DC–DC Converter . . . . . . . . . . . . 5.2 Isolated DC–DC Converter . . . . . . . . . . . . . . . . 5.3 Example of Low Voltage Stress Isolated DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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6 Resonant Driving Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Basic Resonant Driving Circuit . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Resonant Driving Based on Paralleled Branch . . . . . . . . . . . . . 6.3 Self-driven Resonant Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Basic Self-driven Resonant Circuit . . . . . . . . . . . . . . . . 6.3.2 Self-driven Resonant Circuit Based on Paralleled Branch Between Gate and Source . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Self-driven Resonant Circuit Based on Paralleled Branch Between Drain and Gate . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Example of Self-driven Circuit . . . . . . . . . . . . . . . . . . .

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7 Air-Core Planar Inductors and Transformers on PCB . . 7.1 Constant Width Planar Inductors . . . . . . . . . . . . . . . . 7.1.1 Calculation of Planar Circular Inductor . . . . . . 7.1.2 Calculation of Planar Square Spiral Winding . . 7.2 Variable Width Planar Inductors . . . . . . . . . . . . . . . . 7.2.1 Calculation of Variable Width Winding Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Optimal of Variable Width Winding Structure . 7.3 Variable Width Planar Transformer . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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8 Passive and Active Components in Multi-MHz Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Multi-MHz Magnetic Components . . . . . . . . 8.2 Multi-MHz Active Devices . . . . . . . . . . . . . 8.3 Testing Method . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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9 Flexible Multi-MHz DC—DC Converter . 9.1 Flexible Planar Air-Core Inductor . . . 9.2 Design of Matching Network . . . . . . 9.3 Experimental Results . . . . . . . . . . . . 9.4 Conclusion . . . . . . . . . . . . . . . . . . . .

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About the Authors

Dianguo Xu received the M.S. and Ph.D. degrees in electrical engineering from Harbin Institute of Technology (HIT), Harbin, China, in 1984 and 1989, respectively. In 1989, he joined the Department of Electrical Engineering, HIT, as an Assistant Professor, where he has been a Professor since 1994. He was the Dean of School of Electrical Engineering and Automation HIT, from 2000 to 2010. He is currently the Vice President of HIT. His current research interests include renewable energy power conversion technology, multi-terminal HVDC system based on MMC, power quality mitigation, speed sensorless vector-controlled motor drives, and high performance PMSM servo system. Prof. Xu is the winner of 2018 IEEE Industry Applications Society Outstanding Achievement Award. He was promoted as a fellow of IEEE for the contribution to control of electrical drives and power electronic converters. He was general chair of ICEMS 2019 and IEEE ITEC Asia-Pacific 2017, TPC chair of IPEMC 2012-ECCE Asia and VPPC 2008. He has published over 600 journal papers, 4 book chapters, and held 63 patents. He received the prize paper awards from IEEE Transactions on Power Electronics in 2018 and 2019, and best papers awards from the conferences of ICEMS 2019, ITEC Asia-Pacific 2018, ITEC Asia-Pacific 2017, ICEMS 2014, PCIM Asia 2014, IPEMC 2012-ECCE Asia and LSMS and ICSEE 2010. He is an Associate Editor for the IEEE Transactions on Industrial Electronics, IEEE Transactions on Power Electronics and IEEE Journal of Emerging and Selected Topics in Power Electronics. He is the Chairman of the IEEE Harbin Section, the vice president of China Electrotechnical Society (CES). Yueshi Guan was born in Heilongjiang Province, China, in 1990. He received the B.S., M.S. and Ph.D. degrees in electrical engineering from Harbin Institute of Technology, China, in 2013, 2015 and 2019, respectively. Since 2019, he has been an associate professor with the Department of Electrical and Electronics Engineering, Harbin Institute of Technology. His research interests are in the areas of high frequency and very high frequency converters, high step-up/step down ix

x

About the Authors

converters, single-stage AC/DC converter, and LED lighting systems. Prof. Guan has authored more than 50 conference and journal papers. He received Nomination Award of Young Engineer Award of PCIM Asia Conference in 2019, the Second Prize Paper Award from IEEE Transactions on Power Electronics, as well as Best Paper awards of ICEMS 2019, SPEED 2019, ITEC Asia-Pacific 2017. Dr. Guan is an Associate Editor of IET The Journal of Engineering, and Guest Editor of IEEE Journal of Emerging and Selected Topics in Industrial Electronics. Yijie Wang was born in Heilongjiang Province, China, in 1982. He received the B.S., M.S. and Ph.D. degrees in electrical engineering from Harbin Institute of Technology, China, in 2005, 2007 and 2012, respectively. From 2012 to 2017, he was a lecturer and associate professor with the Department of Electrical and Electronics Engineering, Harbin Institute of Technology. Since 2017, he has been a professor with the Department of Electrical and Electronics Engineering, Harbin Institute of Technology. His interests include DC-DC converters, soft-switching power converters, power factor correction circuits, digital control electronic ballasts, LED lighting systems. He received prize paper awards from IEEE Transactions on Power Electronics in 2018 and 2019, and best paper awards of ITEC Asia-Pacific 2017, ITEC Asia-Pacific 2018, ICEMS 2018 and 2019. Dr. Wang is an Associate Editor of the IEEE Transactions on Industrial Electronics, IEEE Journal of Emerging and Selected Topics in Power Electronics, IEEE Access, IET Power Electronics and Journal of Power Electronics. Xiangjun Zhang was born in Shandong Province, China, in 1971. He received the B.S. degree in welding from Xi’an Jiaotong University, Xian, China, in 1993; the M.S. degree in welding from the Harbin Welding Institute, Harbin, China, in 1999; and the Ph.D. degree in electrical engineering from the Harbin Institute of Technology, Harbin, in 2006. From 2006 to 2013, he was a Lecturer in the Department of Electrical and Electronics Engineering, Harbin Institute of Technology, where he has been an Associate Professor since 2013. His research interests include the areas of electronic ballast, power factor correction circuits, high-power converters, and light emitting diode lighting systems.

Chapter 1

Introduction

1.1 Development of Multi-MHz Resonant Converter The continuous development of power electronics technology has imposed increasingly strict requirements on the size, weight, power density and efficiency of power converters. For switching mode power supply, passive components such as inductors, transformers and electrolytic capacitors occupy most of the converter’s volume, which greatly limits the improvement of system power density. As the operating frequency increases, the energy stored in passive components decreases during each switching cycle, which can effectively reduce the value and volume of passive components [1–4]. Thus, to achieve small volume and high power density, the operating frequency of power converters keeps increasing. In recent years for low power converters, the operating frequency has been improved to multi-MHz, from several MHz to even tens of MHz. They have been gradually adopted in aerospace, consumer electronics, solid-state lighting and many other fields. However, the switching loss, driving loss and magnetic component loss increase rapidly with the increment of the switching frequency. Therefore, high loss under high-frequency conditions has become a bottleneck for the development of multi-MHz high-frequency converters. For switching loss, it is mainly determined by the working state of the switch and the diode. With the continuous development of soft-switching technology, resonant converters have attracted great attention. Resonant converters own zero voltage switching (ZVS) or zero current switching (ZVS) characteristics, which can effectively reduce switching loss caused by voltage and current overlap during switching transitions. On the other hand, the switching loss is also related to the characteristics of the switch and the diode. With the improvement of Si material semiconductor device technology, its on-resistance and input/output capacitance characteristics become smaller and smaller. Also, with the continuous development of new wide bandgap semiconductor such as GaN and SiC, the performance of devices has been greatly improved, further reducing the switching loss. At the same time, its switching characteristics are also different. For example, compared with the Si switch, the GaN FET © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_1

1

2

1 Introduction

has no reverse recovery loss, but it has a higher reverse conduction loss. Therefore, in the research of multi-MHz resonant power converters, it is necessary to comprehensively consider the coupling relationships of device–topology–control and other aspects in order to achieve a comprehensive improvement in its efficiency and power density. At present, the problems and challenges faced by the development of multi-MHz power converters mainly include the improvement of resonant converter topology, the optimization of driving methods and the design of passive and active components.

1.2 Research of Multi-MHz Resonant Converter The multi-MHz power electronic resonant systems can be classified by the energy conversion type, namely DC to AC (inverter), AC to DC (rectifier), and DC to DC. For the AC to AC conversion, it can be realized by cascading the rectifier circuit and inverter circuit, which seldom appears in existing literatures and applications. The research of multi-MHz resonant systems in power electronic fields begins from the inverter, which draws lots of inspirations from the RF amplifier. In the research of RF amplifier, the Class D inverter, Class E inverter and Class F inverter have been researched for several decades. There are also many derivate circuit topologies. Some of them have been directly used in the multi-MHz resonant inverters. Based on the duality principle, the rectifier circuit can be achieved with similar topologies. The topologies of inverter and rectifier will be introduced in Chaps. 2 and 3. One of the topology features of these RF amplifiers or rectifiers is that the inductors in the circuit are a choke one, where the input can be seen as a constant current. However, in multi-MHz power electronics systems, the choke inductors still lead to large volume, weight and loss. For the DC–DC conversion, it can be realized by cascading the inverter stage and rectifier stage. A typical diagram of multi-MHz DC–DC converters is shown in Fig. 1.1, besides the inverter and rectifier stage, a matching network is usually adopted to bridge the inverter stage and rectifier stage, it can be used to adjust the equivalent impedance of the rectifier to meet the impedance requirement of the inverter stage. Also, a transformer can be used in the matching network stage to achieve isolation. The matching network stage will be discussed in Chap. 4. Based on different inverter stages, rectifier stages and matching network stages, many DC–DC converters with

DC

Vin

AC DC

AC Inverter Stage

Matching Network

Fig. 1.1 Typical diagram of multi-MHz DC-DC power converters

Rectifier Stage

Vout

1.2 Research of Multi-MHz Resonant Converter

3

different characteristics can be built, including non-isolated and isolated ones, which will be depicted in Chap. 5. For these topologies, the realization of soft-switching characteristics within a wide load range is expected. Besides the switching loss, the driving loss and magnetic component loss are also greatly increased under multi-MHz situations. For the low-frequency driving method, the energy stored in the switch input capacitor is dissipated during every period, which forms a proportional relationship with switching frequency. To solve this problem, the resonant driving method is proposed to take advantage of the energy of the input capacitor by making the input capacitor resonating with an inductor in the driving loop. Thus, how to design an efficient resonant driving method is a key point to improve the system efficiency. Also, under multi-MHz situations, the inductance can be greatly reduced with the increment of operating frequency; thus, the air-core magnetic components can be used which can avoid the use of magnetic core and corresponding core loss. However, the winding AC resistance greatly increases under multi-MHz situations because of skin effect and proximity effect. There are different types of air-core magnetic components, such as solenoid ones, planar ones and 3D printed ones. Within them, the planar air-core magnetic components based on copper tracks on PCB as windings are the most widely used one. Thus, how to design and optimize the winding shape and width on PCB in order to reduce the resistance is a research hot spot, which is essential to improve the system efficiency.

1.3 Contents of the Book From Chaps. 2 to 5, the topologies of multi-MHz DC–DC converters are analyzed. The basic stages, namely inverter stage, rectifier stage and matching network stage, will be discussed in Chaps. 3–5, respectively. Their mathematical models and design methods are derived comprehensively. In Chap. 5, the typical non-isolated and isolated topologies are introduced by combining the inverter stage, rectifier stage and matching network stage, whose characteristics are discussed. In Chap. 6, the efficient resonant driving method for multi-MHz converters will be introduced, including the driving method based on external oscillator method and self-driving method. The parameter design method and power loss are analyzed. The passive and active components should also be carefully designed and chosen under multi-MHz situations. In Chap. 7, the air-core magnetic component design method will be discussed, including the air-core inductor and air-core transformer. The inductance, resistance and quality factor will be derived. The advanced winding structure will be introduced to improve the quality factor of the inductor under multiMHz situations. In Chap. 8, the characteristics of switches and diodes under multi-MHz situations will be introduced. The FOM of the switch and the model including parasitic capacitance are discussed. The testing and measurement tips of voltage and current in multi-MHz situations are given.

4

1 Introduction

In Chap. 9, the flexible DC–DC converter is designed based on above content under multi-MHz frequency situations, and characteristics of the bending inductor and optimized design method of matching network are analyzed. The flexible converter owns very low profile and bending ability, which can be used in wearable, lighting and other applications.

References 1. Hertel JC, Nour Y, Knott A (2018) Integrated very-high-frequency switch mode power supplies: design considerations. IEEE J Emer Select Topics Power Electron 6(2):526–538 2. Perreault DJ, Hu J, Rivas J et al (2009) Opportunities and challenges in very high frequency power conversion. In: Twenty-fourth annual IEEE applied power electronics conference and exposition, pp 1–14 3. Knott A, Andersen TM, Kamby P et al (2013) On the ongoing evolution of very high frequency power supplies. In: Twenty-eighth annual IEEE applied power electronics conference and exposition (APEC), pp 2514–2519 4. Knott A, Andersen TM, Kamby P et al (2014) Evolution of very high frequency power supplies. IEEE J Emer Sel Topics Power Electron 2(3):386–394

Chapter 2

Resonant Inverter in Multi-MHz DC–DC Converter

2.1 Infinite Inductor Resonant Inverter For high-frequency resonant inverters, many topologies have been proposed in the field of RF amplifier. Class E amplifier is a very common topology to realize DC to AC transmission. The circuit is shown in Fig. 2.1, where L F is an infinite inductor through which the input current can be seen as a constant value. Inductor L S and capacitor C S form a high quality factor LC branch at the switching frequency to guarantee a sinusoidal output voltage. A resonant capacitor C F is paralleled between the switch drain and source. The switch can operate under zero voltage switching (ZVS) situation to reduce switching loss. Also, the switch is also designed to operate at zero derivative voltage switching (ZdVS) situation which means the derivative value of the drain–source voltage at the turn-on instant is zero, which can help to reduce the effect of time error during the turn-on process. From the topology, it can be seen that the output capacitance of the switch can be fully absorbed by the resonant capacitor. The Class E inverter can be easily driven by the ground reference structure. One shortcoming of the Class E inverter is that the switch voltage stress is high, which is usually 3.6 times of the input voltage. To solve the high switch voltage stress problem, Class F resonant inverter is proposed by adding LC branch resonating at odd/even harmonic frequencies, as Fig. 2.2 shows. However, the switch output capacitance will affect the performance of the Class F inverter. Based on Class E and Class F inverter, the Class EFn or Class Fn inverter is proposed to tune specific n-th harmonic component of the resonant tank impedance. With this method, the switch can operate at low voltage stress situation as well as adopt the output capacitance. The simplest impedance adjustment is to adjust the second harmonic, and the corresponding topology is named as Class F2 inverter. The circuit is shown in Fig. 2.3, and the inductor L M and capacitor C M resonate at the frequency of second harmonic. In this circuit, the switch voltage stress is about 2.5 times of the input voltage. However, there is one major shortcoming of aforementioned topologies, which is that there is a choke inductor in these topologies. To solve this problem, some © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_2

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2 Resonant Inverter in Multi-MHz DC–DC Converter

LF

Fig. 2.1 Circuit of Class E resonant inverter

LS

Sctrl

Vin

Vin

RL

CF

LH1

LHn

CH1

CHn

LF

CS

Sctrl

RL

Fig. 2.2 Circuit of Class F resonant inverter

LF

Fig. 2.3 The circuit of Class 2 type resonant inverter stage

LS LM

Vin

Sctrl

CF

CS

RL

CM

topologies have been proposed to replace the infinite inductor by a finite one, and the soft-switching characteristics can still be achieved. For the inverter stage in DC/DC applications, another shortcoming is that there must be a high quality factor LC branch to guarantee sinusoidal output. However, for the inverter stage in DC/DC converter, the output voltage does not always need a pure sinusoidal output waveform. Thus, the high quality factor LC branch can be saved, and the volume of the inverter stage can be further reduced. In the following part, the design method of two typical inverter stages in DC–DC converter will be analyzed.

2.2 Full Resonant Inverter Stage 2.2.1 Class E Inverter Stage Figure 2.4 shows the diagram of Class E resonant inverter stage which can be applied in DC–DC converter. The inductor L F , capacitor C F constitute the Class E inverter

2.2 Full Resonant Inverter Stage

7

LF

Fig. 2.4 The circuit of the Class E inverter stage in DC–DC converter

iS

iL Vin

S

iC

iR CF

Rinv

network. It should be noted that C F is the sum of the output parasitic capacitor of the switch and the parallel discrete capacitor. When the switch is off, inductor L F and capacitor C F resonate. To reduce the switching loss under multi-MHz situations, the switch should operate at ZVS and ZdVS situations. In the following part, a mathematical design method of the Class E inverter stage will be introduced. It is assumed that the system adopts ideal components and the process of switching on and off is completed instantaneously. Also, the ESR of passive components is not considered. Figure 2.5 shows the main voltage and current waveforms of Class E inverter when the duty cycle D of the switch is 0.5. When 0 ≤ t < (1 − D)t, the switch is turned off, and L F and C F are resonant. According to laws of KCL and KVL, the following differential equation can be obtained:

vGS t

vC (vDS)

t

vL

t iC t iL iR 0

t (1-D)T

T

Fig. 2.5 Voltage and current waveform of Class E inverter

t

8

2 Resonant Inverter in Multi-MHz DC–DC Converter

d2 vC 1 dvC Vin vC + = + dt 2 Rinv CF dt L F CF L F CF

(2.1)

The general solution of Eq. (2.1) is as follows: vC (t)=eαt [A1 cos(βt) + A2 sin(βt)] + A3

(2.2)

Here, α and β meet the following requirements: ⎧ 1 ⎪ ⎪ α=− ⎪ ⎨ 2Rinv CF  2 ⎪ 4Rinv CF 1 ⎪ ⎪ −1 ⎩β = 2Rinv CF LF

(2.3)

In order to find the specific expression of Eq. (2.2), it is necessary to find the relevant conditions of the system. In order to make the switch have ZVS and ZDVS characteristics, it can be obtained that: ⎧ vC (0) = 0 ⎪ ⎪ ⎪ ⎨ v ((1 − D)T ) = 0 C   ⎪ dv ⎪ ⎪ C =0 ⎩ dt t=(1−D)T

(2.4)

At the moment of switching on and off, the current of inductance L F meets the following equations: ⎧ i L ((1 − D)T ) = i C ((1 − D)T ) + i R ((1 − D)T ) = 0 ⎪ ⎪ ⎪ ⎨ T DT Vin 1 ⎪ vL dt = i L (0) = i L (T ) = i L ((1 − D)T ) + ⎪ ⎪ LF LF ⎩

(2.5)

(1−D)T

On the other hand, the current of the inductance L F also meets the following equation:  ⎧ dvC  ⎪ ⎪ i L (0) = i C (0) + i R (0) = CF ⎪ ⎪ ⎪ dt t=0 ⎨ (1−D)T  ⎪ T Vin 1 1 ⎪ ⎪ i L ((1 − D)T ) = i L (0) + vL dt = − ⎪ ⎪ ⎩ LF LF LF 0

(1−D)T 

(2.6) vC dt

0

By combining (2.5) and (2.6), the following equation can be obtained:

2.2 Full Resonant Inverter Stage

9

 ⎧ dvC  DT Vin ⎪ ⎪ ⎪  = L C ⎪ ⎪ dt F F ⎨ t=0 (1−D)T  ⎪ ⎪ ⎪ vC dt = T Vin ⎪ ⎪ ⎩

(2.7)

0

Substituting (2.2) into constraint conditions (2.4) and (2.7), the following equations can be obtained:

T

T M A1 A2 = T Vin 0 D 0 1

(2.8)

where M is a 4 × 2 matrix, the specific expression is as follows: ⎡

eα(1−D)T sin(β(1 − D)T ) eα(1−D)T cos(β(1 − D)T ) − 1 ⎢ β α ⎢ α 2 +β 2 α 2 +β 2 ⎢ ⎢ ⎢ α cos(β(1 − D)T ) − β sin(β(1 − D)T ) α sin(β(1 − D)T ) + β cos(β(1 − D)T ) ⎣ α(1−D)T e eα(1−D)T [α sin(β(1−D)T )−β cos(β(1−D)T )]+β [α cos(β(1−D)T )+β sin(β(1−D)T )]−α − − D)T (1 2 2 2 2 α +β

α +β

⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦

(2.9)

In order to make A1 and A2 in (2.8) have unique solutions, matrix M should be of full rank, from which (2.10) should be satisfied: ⎧ α(1−D)T βe − [α sin(β(1 − D)T ) + β cos(β(1 − D)T )] = 0 ⎪ ⎪ ⎪ ⎡ α sin(β(1 − D)T ) + (2D − 1)β cos(β(1 − D)T ) ⎤ ⎪ ⎪ ⎪ 2α(1−D)T ⎪ ⎨ Dβe ⎦eα(1−D)T α2 + β 2 −⎣ 2 + β2 α ⎪ +D(1 − D)T sin(β(1 − D)T ) ⎪ ⎪ ⎪ ⎪ ⎪ − D)β (1 ⎪ ⎩− =0 α2 + β 2 (2.10) Solving (2.10), the expression of α and β is as follows: ⎧ x fs fs ⎪ ⎪ ⎨α = − − D tan x 1 − D x fs ⎪ ⎪ ⎩β = 1− D

(2.11)

where x is an intermediate variable, and x satisfies the following equation: xe−(x/ tan x+(1−D)/D) +

1− D sin x = 0 D

(2.12)

When (2.3) and (2.11) are combined, the resonant parameters of Class E inverter can be obtained as (2.13) shows.

10

2 Resonant Inverter in Multi-MHz DC–DC Converter

Table 2.1 Numerical solution of (2.12) D

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

x

5.3005

5.0080

4.7829

4.5972

4.4340

4.2813

4.1700

3.9480

⎧ 2Rinv D 2 (1 − D)x tan x + D[(1 − D) tan x]2 ⎪ ⎪ ⎨ LF = f s [(1 − D) tan x + Dx]2 + (Dx tan x)2 ⎪ D(1 − D) tan x 1 ⎪ ⎩ CF = 2 f s Rinv Dx + (1 − D) tan x

(2.13)

The coefficients of Eq. (2.2) can be obtained by combining (2.8), (2.9) and (2.11): ⎧ A1 = −Vin ⎪ ⎪ ⎪   ⎨ x 1 D Vin + A2 = ⎪ 1 − D sin2 x tan x ⎪ ⎪ ⎩ A3 = Vin

(2.14)

It can be seen that the solution of Eq. (2.12) is only related to the duty ratio D of the switch. Table 2.1 gives the numerical solution of Eq. (2.12) under different duty ratio D. Therefore, for Class E inverter, when the switching frequency f S , duty cycle D and the equivalent resistance Rinv of the later stage are given, the resonance parameters can be solved by (2.13). Based on above equations, the switch voltage stress can be calculated to be about 3.5 times of the input voltage, which is similar as infinite inductor Class E inverter and quite high.

2.2.2 Class Φ 2 Inverter Stage To further reduce the switch voltage stress, the Class F2 inverter stage can be adopted by using harmonics. As Fig. 2.6 shows, the peak voltage across the switch can be effectively reduced by superimposing the fundamental and third harmonic voltages. Figure 2.7 shows the circuit of the Class F2 inverter stage, which is derived from Class E inverter stage. The input resonant network consists of L F , C F , L 2F and C 2F . In parameter design process, to make the switch drain–source waveform present a low impedance at the second harmonic frequency, the resonant frequency of L 2F and C 2F is set to be close to twice of the switching frequency. Then, the resonant tank should be adjusted to exhibit high impedance at the fundamental and third harmonic frequency. Since the superposition of fundamental component and third harmonic component, the switch voltage waveform is in approximately trapezoidal form, and the voltage stress of switch can be reduced. Meanwhile, the switch is still expected to operate under ZVS and ZdVS soft-switching conditions. Figure 2.8 shows the current and voltage waveforms of the inverter. The parameter

2.2 Full Resonant Inverter Stage Fig. 2.6 Desired voltage waveform with the addition of third harmonic

11 voltage

1st harmonic

1st+3rd harmonic (desired voltage waveform)

time

3rd harmonic

Fig. 2.7 Circuit of the Class F2 inverter stage

LF

iin

iS S

Vin

iCF

L2F

CF

iR

iC2F R

C2F

derivation process of Class 2 inverter stage is similar to that of Class E inverter stage. When (1 − D)T ≤ t ≤ T, the switch is in on state, vLF = V in , vL2F + vC2F = 0, that is to say the inductor L F is charged by the input voltage source during this period, and thus, its voltage increases linearly. Meanwhile, assuming L 2F and C 2F resonate in series, the differential equation for vC2F can be derived as: 1 d2 vC2F + vC2F = 0 2 dt L 2F C2F

(2.15)

and its general solution can be obtained. vC2F = H1 cos √

t L 2F C2F

+ H2 sin √

t L 2F C2F

(2.16)

However, if L 2F and C 2F resonate when the switch is on, there will be large current flowing through the switch, which causes large conduction loss. Thus, the series resonance between L 2F and C 2F should be avoided when the switch is on. To ensure that the series resonance does not occur, the following conditions should be satisfied:  ⎧ ⎨ vC2F (t)t=(1−D)T = 0 (2.17)  ⎩ C2F dvC2F (t) t=(1−D)T = 0 dt

12

2 Resonant Inverter in Multi-MHz DC–DC Converter

vGS

S off

S on t

vCF (vDS)

t

vLF

t vC2F

t

vL2F

t iin t iS t iCF t

iC2F 0

(1-D)T

T

t

Fig. 2.8 Voltage and current waveform of Class F2 inverter

Combining (2.16) and (2.17), it can be obtained that H 1 = H 2 = 0, which means that vC2F is always zero during the on period, and there is no reactive current in the branch, avoiding additional loss. When 0 ≤ t ≤ (1 − D)T, the switch is in off state, according to KCL and KVL, the following equation can be obtained: i in = i CF + i C2F + i R

(2.18)

The inductor L F of the Class 2 inverter operates in resonant state, so the current iin flows in positive and negative directions as Fig. 2.8 shows. A paralleled capacitor on the input side of the Class 2 inverter is usually used which buffers the energy and stabilizes the input voltage. Since the derivatives of these current equations satisfy:

2.2 Full Resonant Inverter Stage

13

⎧ di V − vCF ⎪ ⎪ in = in ⎪ ⎪ dt LF ⎪ ⎪ ⎪   ⎪ ⎪ di dvCF d2 vCF d ⎪ CF ⎪ = C = C ⎪ F F ⎨ dt dt dt dt 2   ⎪ d di C2F dvC2F d2 vC2F ⎪ ⎪ = C2F = C2F ⎪ ⎪ dt dt dt dt 2 ⎪ ⎪ ⎪   ⎪ ⎪ 1 dvCF d vCF di R ⎪ ⎪ = = ⎩ dt dt Rinv Rinv dt

(2.19)

It can be derived that d2 vCF d2 vC2F 1 dvCF Vin − vCF = CF + C + 2F LF dt 2 dt 2 Rinv dt

(2.20)

Besides, the voltage of C F can be expressed as: vCF = v L2F + vC2F = L 2F

di C2F d2 vC2F + vC2F = L 2F C2F + vC2F dt dt 2

(2.21)

Combining (2.20) and (2.21), the following differential equation (2.22) can be obtained: ⎧ 2 2 ⎪ ⎪ C2F d vC2F + CF d vCF + 1 dvCF + vCF = Vin ⎨ dt 2 dt 2 R dt LF LF (2.22) 2 ⎪ d v ⎪ C2F ⎩ L 2F C2F + vC2F − vCF = 0 dt 2 where vF and v2F are the instantaneous voltages of C F and C 2F , respectively. A fourth-order differential equation (2.23) can be obtained according to (2.22). d4 vC2F L F CF C2F d3 v C2F + + dt 4 R dt 3 2 L F dvC2F d vC2F + vC2F = Vin + (L F C2F + L F CF + L 2F C2F ) 2 dt R dt L F CF L 2F C2F

(2.23)

A series of intermediate variables α 1 , β 1 , α 2 , β 2 and coefficients A1 , A2 , A3 , A4 , A5 are adopted to help to express and calculate the circuit resonant parameters. Here, the characteristic roots of the Eq. (2.23) can be expressed by (2.24), and the solution of (2.23) can be expressed by (2.25). r1,2 =

α1 ± jβ1 α2 ± jβ2 , r3,4 = (1 − D)T (1 − D)T

(2.24)

14

2 Resonant Inverter in Multi-MHz DC–DC Converter

  ⎧ α1 β1 β1 ⎪ (1−D)T t ⎪ v A t + A t cos sin = e (t) C2F 1 2 ⎪ ⎪ (1 − D)T (1 − D)T ⎪ ⎪   ⎪ ⎨ α2 β2 β2 t + A4 sin t + A5 0 ≤ t ≤ (1 − D)T + e (1−D)T t A3 cos (1 − D)T (1 − D)T ⎪ ⎪ ⎪ ⎪ 2 2 2 ⎪ ⎪ ⎪ vCF (t) = (α1 + α2)(1 − D) T  d vC2F + vC2F 0 ≤ t ≤ (1 − D)T ⎩ α1 α22 + β22 + α2 α12 + β12 dt 2 (2.25) In the following, the conditions of the system are presented and used to solve the intermediate parameters A1 –A5 and α 1 , β 1 , α 2 , β 2 . Firstly, based on previous analysis, since L2F and C2F do not resonate with each other during the on period, vC2F and iC2F are always zero. Thus, it can be known that vC2F (0) = vC2F (T ) = 0 and iC2F (0) = iC2F (T ) = 0. Taking iC2F = C2F (dvC2F /dt) into consideration, the following two conditions can be obtained: ⎧ ⎨ vC2F (0) = 0 ⎩ dvC2F |t=0 = 0 dt

(2.26)

Meanwhile, for the switch, its voltage vds (vCF ) starts to change from zero at the moment when switch is turned off. And vds resonates to zero and satisfies dvds /dt = 0 when switch is just turned on so that the switch can achieve ZVS and ZdVS characteristics. The characteristics can be expressed as: ⎧ vCF (0) = 0 ⎪ ⎪  ⎨ vCF (t)t=(1−D)T = 0 ⎪ ⎪ dvCF  ⎩ t=(1−D)T = 0 dt

(2.27)

In addition, the input current of the system iin can be expressed as follows during the on and off period: ⎧ ⎨ i (0) = i (0) + i (0) + i (0) = C dvCF | in CF C2F R F t=0 dt ⎩  i in ((1 − D)T ) = [i CF (t) + i C2F (t) + i R (t)] t=(1−D)T = 0 ⎧ ⎪ ⎪ 1 ⎪ ⎪ i in (0) = i in (T ) = i in ((1 − D)T ) + ⎪ ⎪ ⎪ L F ⎨ ⎪ ⎪ ⎪ 1 ⎪ ⎪ ⎪ i in ((1 − D)T ) = i in (0) + ⎪ ⎩ LF

(1−D)T 

0

T vLF dt = (1−D)T

(2.28)

DT Vin LF

T Vin 1 v LF dt = − LF LF

(2.29)

(1−D)T 

vCF dt 0

2.2 Full Resonant Inverter Stage

15

Solving (2.28) and (2.29), the following two conditions of the system can be obtained: ⎧ dv DT Vin CF ⎪ ⎪ ⎪ dt |t=0 = L C ⎪ F F ⎨ (1−D)T  ⎪ ⎪ ⎪ vCF dt = T Vin ⎪ ⎩

(2.30)

0

Substituting nine conditions included by (2.17), (2.26), (2.27) and (2.30) into (2.15), the following formula can be obtained:

M A1 A2 A3 A4

T

   2

T α1 + β12 α22 + β22 Vin = 000000D1 1− D

(2.31)

where M = [M 1 | M 2 ], M 1 and M 2 satisfy (2.32). As seen from (2.31), there are only eight equations because A5 = −A1 –A3 according to vC2F (0) = 0, thus, A5 is replaced by −A1 –A3 to reduce the order of the equations and simplify the form of (2.31). In fact, (2.32) is a set of equations about α 1 , β 1 , α 2 ,β 2 and A1 –A4 synthesized by various conditions. ⎡ ⎤ ⎧ eα1 cos β1 − 1 eα1 sin β1 ⎪ ⎪ ⎪ ⎢ ⎥ ⎪ ⎪ α1 β1 ⎢ ⎥ ⎪ ⎪ ⎢ ⎥ ⎪ α1 α cos β − β sin β  α1 α sin β + α cos β  ⎪ ⎢ ⎥ ⎪ e e ⎪ 1 1 1 1 1 1 1 1 ⎢ ⎥ ⎪ ⎪ ⎢ ⎥ ⎪ 2 2 ⎪ α1 − β1 2α1 β1 ⎢ ⎥ ⎪ ⎪        ⎢ ⎥ ⎪ ⎪ α α 2 2 2 2 M = ⎢ ⎥ ⎪ 1 1 1 e α − β cos β − 2α β sin β e 2α β cos β + α − β sin β ⎪ 1 1 1 1 1 1 1 1 ⎢ ⎪ 1 1  1 ⎪   1        ⎥ ⎢ ⎥ ⎪ ⎪ α α 2 2 2 2 2 2 2 2 ⎢ ⎪ 1 1 e α1 α1 − 3β1 cos β1 − β1 3α1 − β1 sin β1 e β1 3α1 − β1 cos β1 + α1 α1 − 3β1 sin β1 ⎥ ⎪ ⎢ ⎥ ⎪ ⎪     ⎢ ⎥ ⎪ ⎪ ⎢ ⎥ ⎪ α1 α12 − 3β12 β1 3α12 − β12 ⎪ ⎣ ⎦ ⎪ ⎪      ⎪   α  

⎪ α 2 2 2 2 2 2 ⎪ α2 + β2 e 1 α1 cos β1 + β1 sin β1 − α1 − α1 + β1 α2 + β2 e 1 α1 sin β1 − β1 cos β1 + β1 ⎨ ⎡ ⎤ ⎪ ⎪ eα2 cos β2 − 1 eα2 sin β2 ⎪ ⎪ ⎪ ⎪ ⎢ ⎥ ⎪ α2 β2 ⎪ ⎢ ⎥ ⎪ ⎪ ⎢ ⎥ ⎪ a2 α cos β − β sin β  α2 α sin β + β cos β  ⎪ ⎢ ⎥ e e ⎪ 2 2 2 2 2 2 2 2 ⎪ ⎢ ⎥ ⎪ ⎪ ⎢ ⎥ 2 − β2 ⎪ α 2α β ⎪ ⎢ ⎥ 2 2 ⎪ 2 2       ⎪ ⎢ ⎥ ⎪ α α ⎪ 2 2 2 2 M = ⎢ ⎥ ⎪ 2 ⎢ e 2 α2 − β2 cos β2 − 2α2 β2 sin β2 e 2 2α2 β2 cos β2 + α2 − β2 sin β2 ⎪ ⎪   ⎥          ⎪ ⎢ ⎪ α2 α α 2 − 3β 2 cos β − β 3α 2 − β 2 sin β α2 β 3α 2 − β 2 cos β + α α 2 − 3β 2 sin β ⎥ ⎪ ⎢ ⎥ ⎪ e e ⎪ 2 2 2 ⎥ 2 2 2 2 2 2 ⎢ 2 2  2 2 2 2  2 ⎪ ⎪ ⎢ ⎥ ⎪ ⎪ 2 − 3β 2 2 − β2 ⎢ ⎥ ⎪ α α β 3α ⎪ 2 2 2 ⎣ ⎦ 2 2 2 ⎪      ⎪ 

   ⎩ α α 2 2 2 2 2 2 α1 + β1 e 2 α2 cos β2 + β2 sin β2 − α2 − α2 + β2 α1 + β1 e 2 α2 sin β2 − β2 cos β2 + β2

(2.32) There are eight equations in (2.31), and the number of unknowns is exactly 8, so the equations can be solved. In order to obtain the specific values of the eight intermediate variables, we first divide α 1 , β 1 , α 2 , β 2 and A1 –A4 into two groups, that is, when solving A1 –A4 , we take α 1 , β 1 , α 2 , β 2 as known variables, then (2.31) can be regarded as an eighth-order non-homogeneous linear system of equations for A1 , A2 , A3 and A4 . According to the method of solving linear equations mathematically, if there is a unique solution for A1 , A2 , A3 , A4 , the rank of the coefficient matrix M and the augmented matrix M AU should be four. Since M is an 8 × 4 matrix, its

16

2 Resonant Inverter in Multi-MHz DC–DC Converter

rank is determined to be four. M AU is shown in (2.33), and mxy is the element of the xth row and yth column of the matrix M. For M AU , in order to make the rank to be four, its fifth-order sub-forms should be zero. According to these requirements, the following Eq. (2.34) for α 1 , β 1 , α 2 , β 2 can be obtained: ⎡

MAU

m 11 ⎢ m 21 ⎢ ⎢m ⎢ 31 ⎢ ⎢ m 41 =⎢ ⎢ m 51 ⎢ ⎢ m 61 ⎢ ⎢m ⎣ 71 m 81

m 12 m 22 m 32 m 42 m 52 m 62

m 13 m 23 m 33 m 43 m 53 m 63

m 14 m 24 m 34 m 44 m 54 m 64

m 72 m 73 m 74

0 0 0 0 0 0

⎤

⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ 2 2 2 2 (α1 +β1 )(α2 +β2 )Vin D ⎥ ⎦ 1−D (α12 +β12 )(α22 +β22 )Vin

m 82 m 83 m 84 1−D ⎧ m 34 P − m 31 P1 − m 32 P2 − m 33 P3 = 0 ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ m 44 P − m 41 P1 − m 42 P2 − m 43 P3 = 0 m 64 P − m 61 P1 − m 62 P2 − m 63 P3 = 0 ⎪ ⎪ ⎪ ⎪ (Dm 84 − m 74 )P − (Dm 81 − m 71 )P1 − ⎪ ⎪ ⎩ (Dm 82 − m 72 )P2 − (Dm 83 − m 73 )P3 = 0

(2.33)

(2.34)

where the matrices P, P1 , P2 and P3 are: ⎡

⎡ ⎡ ⎤ ⎤ ⎤ m 11 m 12 m 13 m 14 m 12 m 13 m 11 m 14 m 13 P = ⎣ m 21 m 22 m 23 ⎦, P1 = ⎣ m 24 m 22 m 23 ⎦, P2 = ⎣ m 21 m 24 m 23 ⎦, m 51 m 52 m 53 m 54 m 52 m 53 m 51 m 54 m 53 ⎤ ⎡ m 11 m 12 m 14 P3 = ⎣ m 21 m 22 m 24 ⎦ m 51 m 52 m 54 By solving (2.34), the values of α 1 , β 1 , α 2 , β 2 can be obtained. Then, (2.31) can be simplified as (2.35), taking α 1 , β 1 , α 2 , β 2 into (2.35), A1 –A4 can be calculated easily. ⎡

m 31 ⎢ m 41 ⎢ ⎣ m 61 m 81

m 32 m 42 m 62 m 82

m 33 m 43 m 63 m 83

⎡ ⎤ ⎤⎡ ⎤ 0 m 34 A1    2 ⎢ A2 ⎥ α1 + β12 α22 + β22 Vin ⎢ 0 ⎥ m 44 ⎥ ⎢ ⎥ ⎥⎢ ⎥ = ⎣0⎦ m 64 ⎦⎣ A3 ⎦ 1− D m 84 A4 1

(2.35)

It can be seen from (2.34) that the solutions of α 1 , β 1 , α 2 , β 2 are only related to the duty cycle D of the switch. Due to the complexity of (2.34), its algebraic solution is difficult to find. Luckily, the numerical solution with higher precision can be easily

2.2 Full Resonant Inverter Stage

17

gotten by MATLAB and can meet the requirements of practical engineering. The numerical solutions of (2.34) with different duty cycles are given in Table 2.2. Then, the unknownsA1 , A2 , A3 and A4 in (2.31) can be expressed as: ⎡

⎤ ⎡ A1 m 31 m 32    2 ⎢ A2 ⎥ α1 + β12 α22 + β22 Vin ⎢ m 41 m 42 ⎢ ⎥= ⎢ ⎣ A3 ⎦ ⎣ m 61 m 62 1− D A4 m 81 m 82

m 33 m 43 m 63 m 83

⎤−1 ⎡ ⎤ m 34 0 ⎢0⎥ m 44 ⎥ ⎥ ⎢ ⎥ m 64 ⎦ ⎣ 0 ⎦ m 84

(2.36)

1

It can be concluded that α 1 , β 1 , α 2 and β 2 are only determined by the duty cycle D of the switch, and A1 –A5 are only determined by the duty cycle D and the input voltage V in . When D = 0.5, the solution of (2.31) is shown in Table 2.3. According to the duty cycle D, period T and load R of the inverter, by substituting intermediate variables α1 , β1 , α2 , β2 into (2.31) and (2.32), the resonant parameters of the inverter can be solved as (2.37). Table 2.2 Numerical solutions of (2.33) D

α1

α2

β1

β2

0.1

−0.1567

−0.4714

5.7099

11.6284

0.2

−0.4654

−1.0670

5.3005

11.2506

0.3

−0.8081

−1.5590

5.0080

11.0654

0.4

−1.1621

−1.9890

4.7829

10.9510

0.5

−1.5321

−2.3940

4.5971

10.8680

0.6

−1.9340

−2.8042

4.4340

10.8002

0.7

−2.3971

−3.2542

4.2813

10.7382

0.8

−2.9860

−3.8067

4.1270

10.6739

0.9

−3.5078

−4.2734

3.9885

10.6113

Table 2.3 Numerical solution of (2.31) when D = 0.5

Label

Value

Label

Value

A1

−1.746V in

α1

−1.5321

A2

5.910V in

α2

−2.3940

A3

0.746V in

β1

4.5971

A4

−2.581V in

β2

10.8680

A5

V in

18

2 Resonant Inverter in Multi-MHz DC–DC Converter

    ⎧ 2α1 α22 + β22 + 2α2 α12 + β12 ⎪ ⎪ ⎪ C F = − (1−D)T ⎪    L (1 − D)T R = − ⎪ F 2 α1 +α2 R ⎪ 2 + β 2 α2 + β 2 ⎪ α ⎪ ⎪ 1 1 2 2 ⎪ ⎪ ⎪      ⎪ ⎪ ⎪ 2(α1 + α2 )2 α1 α22 + β22 + α2 α12 + β12 ⎪ ⎪ ⎨L  2F = − 2    (1 − D)T R   α1 α2 α12 + β12 − α22 − β22 + 4(α1 + α2 ) α1 α22 + β22 + α2 α12 + β12 ⎪ ⎪ ⎪ ⎪ ⎪ ⎪  ⎪ 2      ⎪ ⎪ ⎪ α1 α2 α12 + β12 − α22 − β22 + 4(α1 + α2 ) α1 α22 + β22 + α2 α12 + β12 ⎪ ⎪ ⎪ ⎪ ⎪ C2F = − (1 − D)T ⎪     2 ⎪ ⎩ 2(α1 + α2 ) α1 α22 + β22 + α2 α12 + β12 R

(2.37)

Based on above equatons, the switch voltage stress can be calculated to be about 2.5 times of the input voltage, which is greatly reduced than the Class E inverter stage in DC–DC converter.

Chapter 3

Resonant Rectifier in Multi-MHz DC–DC Converter

The rectifier plays the role of transferring AC component into DC component in the multi-MHz DC–DC converter. Based on the duality principle, the resonant rectifier circuit can be derived from the inverter circuit. For the resonant rectifier stage, the Class E type rectifiers are mostly adopted. Figure 3.1 shows four different types of Class E resonant rectifier stage in DC–DC converter. When the input source is directly connected to the output load through a diode or a inductor, the input source can be seen as current source. When the input source is connected to the output load by a series branch of inductor and diode, the input source can be seen as voltage source. In the following content, two types of current driven rectifier stages are taken as examples to be analyzed.

3.1 Floating Type Current-Driven Class E Rectifier For the rectifier stage in multi-MHz DC–DC converter, the voltage and current in the input side is expected in the same phase, which can help to reduce the reactive current. Under this condition, the equivalent impedance of the rectifier stage can be represented by a resistor. In the existing analysis process, the resonant rectifier stage is often designed based on the parameter sweeping method. By changing the parameters in simulation, the input current and voltage can be adjusted to be in the same phase. However, the resonant parameters are coupled with each other, and multiple parameter adjustments and simulations are required at the same time, which is time-consuming and of low accuracy. Therefore, this section takes the floating current-driven Class E resonant rectifier stage as an example to establish its mathematical model, in order to quickly and accurately guide the parameter design. At the same time, the system characteristic such as the diode voltage stress and input impedance can be obtained. Figure 3.2a illustrates the diagram of the rectifier circuit, and the analysis are based on the following assumptions:

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_3

19

20

3 Resonant Rectifier in Multi-MHz DC–DC Converter Cr

Lr

D1 iS

Lr

+

+ CO

RL

VO iS

D1

CO

Cr

RL

(a) current driven floating type

VO -

-

(b) current driven ground type

Cr Lr vS

D1 CO

+ RL

VO vS

Lr

D1 Cr

CO

VO -

-

(c) voltage driven series type

+ RL

(d) voltage driven T type

Fig. 3.1 Different types of class E resonant rectifier

(1) The threshold voltage and forward voltage drop of D1 are zero. In addition, the leakage current and the reverse recovery current are neglected. (2) The intrinsic capacitance of the diode is absorbed as a part of the total capacitance Cr . (3) The output filter capacitor C O is sufficiently large so that the output voltage ripple is negligible. Figure 3.2 also shows the main voltage and current waveforms of the system. Here T = (2π /ω) is the period of the AC current source and the duty cycle D is defined as the ratio between the diode on-time and operating period. The input source is represented by i S (t) = IIN sin(ωt + ϕ) where I IN is the amplitude of the input current, ω is its angular frequency and ϕ is its phase. When the current through the diode iD reaches zero at t = 0, the diode turns off. Then, the capacitor begins to resonate with the input inductor. The voltage across the capacitor uC decreases and thus the diode’s reverse blocking voltage increases. The reverse diode voltage has a maximum value at the point when the capacitor current iC crosses zero. Then, the current through C r turns positive, so uC gradually rises. When uC increases to zero at t = (1 − D)T, the diode D1 turns on. During the period when diode is on, the voltage of the inductor equals to V O ; thus, the current iL increases linearly. The difference between source current iS and inductor current iL flows through the diode and the diode turns off in ZCS mode naturally at the instant that iD reaches zero. The analysis starts at t = 0, when the diode is turned off. When the diode stays off (0 < t < (1 − D) T ), according to Kirchhoff voltage law (KVL), the capacitor voltage uC can be calculated by a second-order differential equation as shown in (3.1).

3.1 Floating Type Current-Driven Class E Rectifier

21

du C (t)2 u C (t) di S (t) VO + = − dt 2 L r Cr Cr dt L r Cr

(3.1)

The general solution to this equation can be obtained by u C (t) = A1 e

√ jt L r Cr

+ A2 e

− √ Ljt C

r r

+

IIN ωL r cos(ωt + ϕ) − VO 1 − ω2 /ωr2

(3.2)

√ Here,ωr = 1/ L r Cr , A1 and A2 are constant values. For uC (t), two constraints should be satisfied during the operating period of the rectifier stage.

+ uC

Fig. 3.2 Circuit and main current and voltage waveforms

iL iS

-

iC

Cr

iD

D1

+ CO

Lr

RL

VO -

(a) Circuit of current driven Class E resonant rectifier

iS Diode off

t

0 T

(1-D)T Diode on

(b) Input current iS iC 0 (1-D)T

(c) Capacitor current iC

T t

22 Fig. 3.2 (continued)

3 Resonant Rectifier in Multi-MHz DC–DC Converter

uC 0 (1-D)T

T

t

UC-max

(d) Capacitor voltage uC

iD 0 (1-D)T

T t

(e) Diode current iD

iL 0 (1-D)T

T t

(f) Inductor current iL

(1) The diode turns off at t = 0, so the capacitor voltage is zero. It is the same case with the instant when t = (1 − D)T, which means that  u C (t)|t=0 =u C (t)t=(1−D)T =0

(3.3)

(2) According to the previous analysis, the current difference between iS and iL is zero at t = 0, so the current through C r is zero at this instant, namely

i C (t)|t=0 = Cr

 du C (t)  =0 dt t=0

(3.4)

3.1 Floating Type Current-Driven Class E Rectifier

23

Substituting (3.3) and (3.4) into (3.2), the expression of uC can be obtained as (3.5) shows. Two equations, (3.6) and (3.7), which satisfy the constraints are also obtained as follows.  ⎧ IIN ωL r ⎪ ⎨ VO − 1−ω2 /ωr2 cos ϕ cos(ωr t) r (3.5) u C (t)= + IIN ωL 0 ≤ t < (1 − D)T 2 2 cos(ωt + ϕ) − VO ⎪ ⎩ 1−ω /ωr 0 (1 − D)T ≤ t ≤ T VO [cos(ωr (1 − D)T ) − 1]+ =

IIN ωL r cos ϕ cos(ωDT ) 1 − ω2 /ωr2

(3.6)

IIN ωL r cos ϕ cos(ωr (1 − D)T ) 1 − ω2 /ωr2 sin ϕ = 0

(3.7)

Meanwhile, an expression for the current of the inductor L r should be developed. According to the circuit analysis, when the diode is off (0 < t < (1 − D) T ), the inductor current iL can be calculated as: IIN ωL r i L ,off (t) = IIN sin(ωt + ϕ) + Cr ω sin(ωt + ϕ) 1 − ω2 /ωr2

IIN ωL r + VO − cos ϕ Cr ωr sin(ωr t) 1 − ω2 /ωr2

(3.8)

When the diode is on (1 − D) T < t < T ), the inductor current is shown as:  VO i L ,on (t) = i L ,off (t)t=(1−D)T + [t − (1 − D)T ] Lr

(3.9)

For inductor voltage and current, there are also two constraints that should be satisfied. The first constraint is that the average voltage of the inductor must be equal to zero on the base of the voltage-second balance principle. The second constraint is that the average current of inductor iL must be equal to the opposite of the output current because the average current of the current source is zero within one period. Here the current direction has been taken into consideration. Thus, Eqs. (3.10) and (3.11) can be obtained: 1 T

T u L (t)dt = 0

(3.10)

0

1 T

T i L (t)dt = − 0

PO VO

(3.11)

24

3 Resonant Rectifier in Multi-MHz DC–DC Converter

By substituting (3.10) and (3.11) into inductor current expressions (3.8) and (3.9), two nonlinear equations can be obtained as follows:

IIN ωL r 1 VO − cos ϕ sin(ωr (1 − D)T ) 1 − ω2 /ωr2 ωr II N Lr + VO DT − sin(ωDT ) cos ϕ = 0 1 − ω2 /ωr2

VO D 2 T 2 IIN PO cos(ϕ)[1 − cos(ωDT )] − +T =0 ω 2L r VO

(3.12)

(3.13)

From (3.6), (3.7), (3.12) and (3.13), it can be seen that there are seven variables D, PO , I IN , ω, V O , L r , and C r in total. With three determined parameters, these four equations can be adopted to calculate the corresponding parameters and design the resonant rectifier. According to (3.6), (3.7), and (3.12), the value of ωr /ω is determined only by the specific value of diode duty cycle D. The relationship between them is shown as follows.  ω    ωr   ωr r cos 2π (1 − D) − cos(2π D) − sin 2π (1 − D) + 2Dπ ω ω   ω     ωω ωr r r sin(2π D) cos 2π (1 − D) − 1 = 0 sin 2π (1 − D) cos(2π D) − ω ω ω (3.14) Meanwhile, Eq. (3.15) can also be obtained based on above equations, where K is an intermediate variable that helps to simplify the expressions of equations. K =



sin 2π ωr (1 − D) + 2Dπ ωωr IIN cos ϕωL r

= ωr ω

ωr VO 1 − ω2 /ωr2 sin 2π ω (1 − D) + ω sin(2π D)

(3.15)

Based on (3.14) and (3.15), the value of L r and I IN can be calculated as

K VO2 1 − ω2 /ωr2 (1 − cos(2π D)) + 2π 2 VO2 D 2 Lr = 2π PO ω IIN =

2π 2 VO2 D 2 − 2π PO ωL r 1 · cos ϕωL r VO (cos(2π D) − 1)

(3.16)

(3.17)

Then the resonant capacitor C r can be calculated according to the resonant frequency. From the preceding analysis, it can be derived that with the specification of the operating frequency and output voltage, the parameters of the rectifier can be calculated by the diode duty cycle and the output power. Figure 3.3 depicts the relationship between the inductance and the rated output power. It can be seen that the inductance increases rapidly with increment of duty

3.1 Floating Type Current-Driven Class E Rectifier

25

0.12

Fig. 3.3 Curves of inductor L r with varying duty cycle and output power

Po=5W Po=7W Po=10W Po=15W Po=20W Po=25W

0.1

Lr (uH)

0.08 0.06 0.04 0.02 0 0.2

0.3

0.4

0.5

D

0.6

0.7

0.8

0.9

cycle especially when the output power is not high. Figure 3.4 shows the curves of C r when the duty cycle and the output power vary within the same range. C r increases with the decrease of duty cycle especially when the output power is high. The trend is opposite to that of the inductance curve. Figure 3.5 shows the relationship between the current source amplitude, the duty cycle and output power. In the design process of the rectifier stage, the current source amplitude should not be too large. Large input current is not conducive to improving system efficiency. As can be seen in Fig. 3.5, small or large duty cycle causes large input current, which is not expected. For a certain D, the input current rises with the increment of the output power. Meanwhile, the normalized values can also provide general information about the system characteristics. For inductor, capacitor and input current, the definitions of normalized values can be expressed as (3.18)–(3.20) show. 60

Fig. 3.4 Curves of capacitor C r with varying duty cycle and output power

Po=5W Po=10W Po=15W Po=20W Po=25W

50

Cr (nF)

40 30 20 10 0 0.2

0.3

0.4

0.5

D

0.6

0.7

0.8

0.9

26

3 Resonant Rectifier in Multi-MHz DC–DC Converter 30

Fig. 3.5 Amplitude of the source with varying duty cycle and output power capacitor

Po=5W Po=10W Po=15W Po=20W Po=25W

25

Iin (A)

20 15 10 5 0 0.2

0.3

0.4

0.5

D

0.6

0.7

0.8

2π ω2 Cr 1 

= ωr2 K 1 − ω2 /ωr2 (1 − cos(2π D)) + 2π 2 D 2 PO 2π f VO2

K 1 − ω2 /ωr2 (1 − cos(2π D)) + 2π 2 D 2 Lr = Ln = 2  2π VO (PO 2π f )

K 1 − ω2 /ωr2 2π Iin 

In = = PO VO cos ϕ K 1 − ω2 /ωr2 (1 − cos(2π D)) + 2π 2 D 2

Cn =

0.9

(3.18)

(3.19)

(3.20)

It can be seen from the above equations that the normalized value of each parameter has nothing to do with the output voltage and output power, only determined by the diode duty cycle. Figure 3.6 shows the relationship between the normal7

Fig. 3.6 Curves of normalized inductor L n , C n and current I n in different D conditions

6

Normalized inductance Ln Normalized capacitance Cn Normalized input current In

Ln Cn In

5 4 3 2 1 0 0.2

0.3

0.4

0.5

D

0.6

0.7

0.8

0.9

Fig. 3.7 Peak diode reverse voltage with varying duty cycle

Normalized reverse voltage stress.UC,n

3.1 Floating Type Current-Driven Class E Rectifier

27

20 18 16 14 12 10 8 6 4 2 0

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

D

ized parameters and the duty cycle D. As can be seen from the figure, as the duty cycle gradually increasing, the normalized inductance gradually increases, and the capacitance gradually decreases. The current source amplitude basically reaches a minimum value when the duty cycle is around 0.6. When design the rectifier, the reverse voltage of the diode is also an important aspect to be considered. The normalized peak diode reverse voltage is defined as UC,n =

UC−max = max(|(1 − K ) cos(ωr t) + K cos(ωt) − 1|) VO

(3.21)

where U C-max is the peak reverse voltage of the diode, and can be calculated according to (3.5). It can be seen that the voltage stress of the diode depends on the selection of duty cycle. Figure 3.7 shows the curve of normalized diode voltage stress according to (3.21). It can be seen that with the increment of D, the normalized voltage stress significantly increases. Thus, in the optimal design method, a proper D should be first selected to avoid a high diode voltage stress. The input impedance Z rec of the rectifier stage plays an important role of designing the parameters of inverter stage and affects the power transmission characteristics of the system. Its expression is shown in Eq. (3.22), Rrec represents its resistive components, and X rec represents its inductive or capacitive components. Z r ec = Rr ec + j X r ec

(3.22)

Assuming the passive components and diode are ideal. With 100% efficiency, the power received by RL is identical to that transferred to Rrec . Here RL is the load and satisfies RL = V O2 /PO . Thus, Rrec can be obtained by

28

3 Resonant Rectifier in Multi-MHz DC–DC Converter

Rr ec =

 RL

VO2 2PO √ 2 = 2 II N II N 2

(3.23)

At the same time, the reactance component of the input impedance can be obtained by (3.24). In this formula, only the fundamental component is calculated. X r ec =

1 2π

2π 0

=−

u c (t) + V O cos(ωt + ϕ)d(ωt) II N

V O cos(ϕ) 2π I I N

· sin(2π · (1 − D))+ +

V O cos(ϕ) 1 − K · 2π I I N 2



sin((1 + ωr /ω) · (1 − D) · 2π ) sin((ωr /ω − 1) · (1 − D) · 2π ) + 1 + ωr /ω ωr /ω − 1

V O cos(ϕ) K · ((1 − D) · 4π + sin(4π · (1 − D))) 2π I I N 4



(3.24)

Based on the above two formulas, the input impedance angle of the rectifier stage can be obtained. Figure 3.8 shows the curve of equivalent impedance angle. It can be seen that with a certain duty cycle range, a small impedance angle can be achieved on the basis of the optimal parameter values. The phase angle varies within 20 degrees when D varies from 0.4 to 0.8. This means the circuit can maintain quasi-resistive characteristics. The small input impedance angle of the rectifier is beneficial to improving system efficiency with a small circulating current. Figure 3.9 shows the curves of equivalent resistance Rrec based on (3.22). It can be seen that at a certain output power, the equivalent resistance varies with the change in duty cycle D. The small duty cycle helps to realize a small equivalent resistance. However, a small duty cycle will increase the impedance angle as shown in Fig. 3.9, which leads to large loss and reduces system efficiency. 50

Fig. 3.8 The angle of input impedance with varying duty cycle

Input impedance angle (°)

45 40 35 30 25 20 15 10 5 0 0.2

0.3

0.4

0.5

D

0.6

0.7

0.8

0.9

3.1 Floating Type Current-Driven Class E Rectifier

29

8

Fig. 3.9 Equivalent resistance with varying duty cycle and output power

Po=5W Po=10W Po=15W Po=20W Po=25W

Equivalent resistance Rrec

7 6 5 4 3 2 1 0

0.2

0.3

0.4

0.5

D

0.6

0.7

0.8

0.9

Here, the role of D in the rectifier should be clarified. The parameter D represents only the ratio between the diode on-time and operating period. In addition, the ontime of the diode and duty cycle are both determined by the output power, output voltage, and values of components. The duty cycle D is not a controllable variation, and is adopted here to help with the parameter calculation and system design. In the resonant rectifier, the diode is parallel with the discrete resonant capacitor. Thus, the impact of the nonlinear capacitance of the diode must be taken into consideration. The capacitance is highly nonlinear and varies with the diode reverse voltage. In general, the capacitance C diode can be approximately expressed as: Cdiode = 

C jo 1+

Vdiode Vj

M

(3.25)

where C jo , V j , and M are device-specific parameters. Here the diode STPS3L40UF is taken as an example to be analyzed. From the values obtained by the device datasheet and experimental testing, the fitting curve of the diode junction capacitance under different reverse voltage conditions can be obtained as shown in Fig. 3.10. The plot corresponds to the parameters C jo = 679.493pF, V j = 0.257 V, and M = 0.456. During the design process, the established model is adopted to analyze the effects of nonlinear capacitance. The maximum reverse voltage stress is approximately 25 V in the ideal simulation condition as shown in Fig. 3.11. However, in the design procedure, the nonlinear capacitance must be equivalent to a constant value. Simulations are conducted with three different equivalent capacitance values, which are taken at three typical reverse voltage points. From the simulation results, it can be seen that these diode voltage waveforms are similar. The small differences are that with the increment of C diode equivalent value, the maximum diode reverse voltage also

30

3 Resonant Rectifier in Multi-MHz DC–DC Converter 350

Junction capacitance Cdiode (pF)

Fig. 3.10 Diode capacitance versus reverse voltage

300 250 200 150 100 50

0

5

15

10

20

30

25

35

40

Reverse voltage(V)

Discrete Cr=550pF

Discrete Cr=510pF

Discrete Cr=460pF

Reverse voltage 24.5V

Reverse voltage 25.4V

Reverse voltage 27.1V

Fig. 3.11 Diode voltage waveforms at different simulation condition

increases a little. When the equivalent capacitance value is taken around the diode average voltage (12 V), the simulation result is quite close to the ideal voltage waveform. Thus, in the design procedure, the capacitance at the diode average voltage can be chosen as the equivalent diode junction capacitance.

3.2 Ground Type Current-Driven Class E Rectifier Figure 3.12 shows the circuit of ground type Class E resonant rectifier, which is driven by current source with iin (t) = I in sin(ωt + ϕ), where I in , ω and ϕ represent the current magnitude, angular frequency and initial phase angle, respectively. In order to simplify the analysis of this stage, we also follow the assumptions in floating type.

3.2 Ground Type Current-Driven Class E Rectifier Fig. 3.12 Circuit of ground type class E rectifier stage

31

iCd

iD iin

D

vD

iLd

Ld

Cd

Vo

Co

RL

The key waveforms of the rectifier are shown in Fig. 3.13, it can be seen the current of the diode iD resonates to zero at the turn-off instant, achieving zero current switching (ZCS) characteristic. When 0 ≤ t ≤ (1 − Dd )T, the diode is in off state, according to KCL and KVL, the following differential equation can be obtained: 1 ωL d Iin cos(ωt + ϕ) − Vo d2 v D + · vD − =0 dt 2 L d Cd L d Cd

(3.26)

Then the voltage of the diode vD can be solved:

vD

t iin t iD t

iCd t

iLd 0

(1-D d)T

T

Fig. 3.13 Main waveform diagram of rectifier stage in DC-DC converter

t

32

3 Resonant Rectifier in Multi-MHz DC–DC Converter

⎡ ⎤ ⎧ (ω sin ωt − ωd sin ωd t) sin ϕ + ω(cos ωd t − cos ωt) cos ϕ ⎪ ⎪ ⎪ ⎥ ⎪ Ii n ⎢ ω2 − ω2d ⎪ ⎢ ⎥ ⎪ ⎪ ⎦ ⎨ C d ⎣ sin ωd t sin ϕ − v D (t) = ωd ⎪ ⎪ ⎪ ⎪ ⎪ + V − cos ωd t), 0 ≤ t ≤ (1 − Dd )T (1 o ⎪ ⎪ ⎩ 0 (1 − Dd )T ≤ t ≤ T (3.27) √ L d C d . Meanwhile, the current of the inductor L d is derived as: where ωd = 1

⎧ 2 ω cos ωd t − ω2d cos ωt sin ϕ + ωωd (sin ωd t − sin ωt) cos ϕ ⎪ ⎪ ⎪ Ii n ⎪ ⎪ ω2 − ω2d ⎪ ⎨ 0 ≤ t ≤ (1 − Dd )T i Ld (t) = −Vo ωd C d sin ωd t, ⎪ ⎪ ⎪ i Ld ((1 − Dd )T ) − Vo ω2 C d [t − (1 − Dd )T ], ⎪ ⎪ d ⎪ ⎩ (1 − Dd )T ≤ t ≤ T (3.28) According to the volt-second balance of the inductor L d and the amp-second balance of the capacitor C d , (3.29) can be obtained: ⎧ T ⎪ ⎪ 1 ⎪ ⎪ v D (t)dt = Vo ⎪ ⎪ ⎪ ⎨T 0

⎪ T ⎪ ⎪ 1 Po ⎪ ⎪ i Ld (t)dt = ⎪ ⎪ ⎩T Vo

(3.29)

0

Besides, the diode voltage is zero when t = (1 − Dd )T, that is vD ((1 − Dd )T ) = 0. Substituting these three constraints into (3.28) and (3.29), (3.30) can be derived.

3.2 Ground Type Current-Driven Class E Rectifier ⎧ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨

33

⎡ ⎤



ω sin ωToff − ωd sin ωd Toff sin ϕ + ω cos ωd Toff − cos ωToff cos ϕ sin ωd Toff sin ϕ Iin ⎣ ⎦ − Cd ωd ω2 − ωd2   + Vo 1 − cos ωd To f f = 0 



 Iin  ωd cos ωd Toff − cos ωToff sin ϕ + ω sin ωd Toff − ωd sin ωToff cos ϕ ω2 − ωd2 ωd Cd



I 1 − cos ωd Toff sin ϕ Vo ωd Toff − sin ωd Toff −off in = T Vo + ωd ωd2 Cd    ⎤ ⎡ ω3 sin ωd Toff − ωd3 sin ωToff sin ϕ ω2 cos ωToff − ω2 cos ωd Toff cos ϕ Iin ⎣ d   + cos ϕ ⎦ + ω ω2 − ωd2 ωd ω2 − ωd2 ⎛ ⎞ 2 ω2 Ton ⎠ − Vo Cd ⎝1 − cos ωd Toff + d 2 

(3.30)

⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪  ⎤ ⎡ ⎪

⎪ ⎪ ω2 cos ωd Toff − ωd2 cos ωToff sin ϕ + ωd ω sin ωd Toff − ωd sin ωToff cos ϕ ⎪ ⎪ ⎪ ⎥ ⎢ ⎪ I T Po ⎪ in ⎥ ⎪ ⎪ + Ton ⎢ ⎥= ⎢ ω2 − ωd2 ⎪ ⎪ ⎦ ⎣ Vo ⎪ ⎪ ⎩ −Vo ωd Cd sin ωd Toff

where T on = Dd T and T off = (1 − Dd )T, Dd is the conduction ratio of the diode. It can be seen the variables of Eq. (3.30) are C d , ωd and ϕ, the numerical solution of them can be calculated by MATLAB when ω, Po , V o , I in and Dd are known. Compared with the floating type Class E rectifier stage, the initial phase angle is variable. Actually, the change of I in and Dd can significantly affect the voltage stress of the diode and the phase angle of the equivalent input impedance of the rectifier. Figure 3.14 shows the relationship among the diode voltage stress V Dmax , the output voltage V o and the duty cycle Dd . It can be seen that V Dmax /V o increases sharply as Dd increases, thus resulting in an increment of voltage stress. For diode, the forward conduction voltage usually forms a proportional relationship with the rated voltage. Hence, higher voltage stress leads to higher diode conduction loss. From the diode 20

Fig. 3.14 Relationship between diode voltage stress and Dd

18 16

VDmax/Vo

14 12 10 8 6 4 2

0

0.1

0.2

0.3

0.4

0.5

Dd

0.6

0.7

0.8

0.9

1

34

3 Resonant Rectifier in Multi-MHz DC–DC Converter

voltage stress, it can be seen that the normalized voltage stress is the same as that of the floating diode type rectifier circuit under the same diode duty cycle situation. In addition, for the purpose of analyzing the input impedance characteristics of the rectifier, Fourier analysis of Eq. (3.31) can be obtained: v D (t) = Vo +

∞ 

V Dn sin(nωt + ϕn )

(3.31)

n=1

where the amplitude V Dn and the phase angle ϕ n of the nth harmonic satisfy: ⎧   T

2  T

2 ⎪ ⎪ 2 ⎪ ⎪ v D (t) cos(nωt)dt + v D (t) sin(nωt)dt ⎨ V Dn = T 0 0  T  T

⎪ ⎪ ⎪ ⎪ v D (t) cos(nωt)dt v D (t) sin(nωt)dt ⎩ ϕn = arctan 0

(3.32)

0

Then the input impedance of the rectifier can be written as Z rec = (V D1 /I in )∠(ϕ 1 − ϕ) considering the fundamental component. Figure 3.15 shows the relationship between the phase angle ϕ rec = (ϕ 1 − ϕ), I in and Dd when Po = 5 W and V o = 5 V. It can be seen ϕ rec increases as I in or Dd increases. Also, the impedance angle is larger than the floating type Class E rectifier. Figure 3.16 shows the parameter curves of L d and C d with different I in and Dd , which provides a reference for the selection of resonant parameters. The trend is similar as those of the floating type Class E rectifier. One feature of the ground type rectifier is that the diode can be easily replaced by a synchronous switch, especially in the non-isolated DC–DC converters. Under high 60

Fig. 3.15 Relationship between phase angle of equivalent input impedance and Dd and

Phase angle/°

50

Iin=1.2Io Iin=1.3Io Iin=1.4Io Iin=1.6Io Iin=1.8Io

40

30

20 10 0.1

0.2

0.3

0.4

0.5

Dd

0.6

0.7

0.8

0.9

1

3.2 Ground Type Current-Driven Class E Rectifier 10

3

10

2

10

1

10

0

Ld/nH

Fig. 3.16 Values of resonance parameters L d and Cd

35

0.2

Iin=1.2Io Iin=1.3Io Iin=1.4Io Iin=1.6Io Iin=1.8Io 0.3

0.4

0.5

Dd

0.6

0.7

0.8

0.9

Cd/pF

(a) Relation between resonance inductance value and Dd and Iin 10

4

10

3

10

2

10

1

10

0

0.2

Iin=1.2Io Iin=1.3Io Iin=1.4Io Iin=1.6Io Iin=1.8Io 0.3

0.4

0.5

0.6

0.7

0.8

0.9

Dd

(b) Relation between Resonance Capacitance and Dd and Iin

output current situations, the synchronous rectification method can help to reduce conduction loss. Figure 3.17a shows the circuit of current driven ground type rectifier. By changing the position of the diode, Fig. 3.17b shows the circuit of voltage driven series type rectifier based on synchronous switch, which is suitable to be used in isolated situation.

36

3 Resonant Rectifier in Multi-MHz DC–DC Converter

Lr

Fig. 3.17 Class E rectifier stage based on synchronous switch

+ iS

S

Cr

CO

RL

VO -

(a) current driven ground type

Lr vS

Cr

+ CO

S (b) voltage driven series type

RL

VO -

Chapter 4

Matching Network in Multi-MHz DC–DC Converter

4.1 Introduction of Matching Network Matching network is the intermediate stage connecting inverter stage and rectifier stage in the multi-MHz DC–DC converter. It plays the role of impedance transformation, adjusting the equivalent resistance of rectifier stage to meet the requirement of the inverter circuit, which is usually composed of passive components, such as inductor, capacitor and transformer. The matching network can be classified as isolated matching network and non-isolated matching network. The isolated matching network is based on transformer, which can achieve electrical isolation besides impedance transformation. However, transformer increases the complexity of circuit and causes unexpected parasitic inductance and capacitance. Thus, non-isolated matching networks based on inductors and capacitors are widely used. This chapter will focus on the non-isolated matching network. Figure 4.1 shows six basic types of non-isolated matching network composed of two or three passive components. For these different types of non-isolated matching networks, they can also be divides into high-pass type and low-pass type. They can be used to enhance or suppress the impact of harmonics on the working state of the circuit. There is a capacitor in series between the matching network input side and output side in the structures of (b), (d) and (f) in Fig. 4.1, which can naturally play the role of DC blocking. At a certain frequency, the non-isolated matching network usually play the role of resistive to resistive transformation and the parameters can be designed according to relationship between the input side resistance and output side resistance. When a matching network is selected, its impedance conversion rate often varies with the equivalent impedance of rectifier when the system operates under different power conditions. In the following content, we will analyze the design methods of different type of matching networks, investigate the transformation characteristics, as well as their influence on the system soft-switching characteristics under different output power conditions. © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_4

37

38

4 Matching Network in Multi-MHz DC–DC Converter LS

CS CS

LS

ZR

ZR

ZL

ZL

(a) L type low-pass matching network

(b) L type high-pass matching network

LS C1

CS

CS

L1

ZR

LS

ZR

ZL

ZL

(c) π type low-pass matching network

(d) π type high-pass matching network

LS

L1

C1

CS

ZR

ZL

LS

CS

ZR

ZL

(e) T type low-pass matching network

(f) T type high-pass matching network

Fig. 4.1 Diagram of the different types matching network

4.2 L Type Matching Network L type low-pass matching network in Fig. 4.1a and L type high-pass matching network in Fig. 4.1b are the simplest non-isolated matching network which can be built only by one capacitor and one inductor. In the following content, the parameters of low-pass and the high-pass structures will be calculated.

4.2.1 Design of L Type Matching Network For the design of the L type low-pass matching network parameters in Fig. 4.1a, the expression of the input impedance Z L of the matching network can be calculated as: ZL =

s2 L SCS Z R + s L S + Z R 1 + sC S Z R

(4.1)

where Z R is the equivalent impedance of the rectifier circuit. Equation (4.2) can be obtained by substituting the complex frequency s = jω into (4.1). ZL =

−ω2 L S C S Z R + Z R + jωL S 1 + jωC S Z R

(4.2)

4.2 L Type Matching Network

39

As mentioned above, both the input and output impedance are expected to be resistive. Thus, when Z L is resistive, the ratio of the real part in the numerator and the denominator needs to be equal to the ratio of the imaginary part in the numerator and the denominator. Equations (4.3) and (4.4) can be calculated as: Z L = −ω2 L S C S Z R + Z R ZL =

LS CS Z R

(4.3) (4.4)

Based on the (4.3) and (4.4), the values of C S and L S at the operating frequency can be calculated as:  ZR − ZL 1 (4.5) C1 = ωZ R ZL Ls =

1 Z L (Z R − Z L ) ω

(4.6)

From Eq. (4.6), it can be seen that the low-pass matching network is a low-tohigh L type matching network, here Z L has to be smaller than Z R . For example, at 20 MHz, the equivalent impedance of the rectifier circuit Z R is 10  and the expected impedance Z L is 5 , which can be transferred through the low-pass matching network. According to Eqs. (4.5) and (4.6), the values of C S and L S can be calculated as 795.8 pF and 39.8 nH. The value of equivalent impedance Z R changes with the load changed. When Z R is taken as 10 , 15  and 20  respectively, it can be seen from the Bode diagram in Fig. 4.2 that the magnitudes of impedance Z L do not change, but the phases gradually change into capacitive region with the increase of

Magnitude (dB)

30

20

10

Phase (deg)

90 45

ZR=10

0 -45 10

ZR=20 ZR=15 20

Fig. 4.2 Effect of Z R change on Z L at 20 MHz

100

40

4 Matching Network in Multi-MHz DC–DC Converter

Z R . The result means that the matching network cannot always maintain the resistive to resistive transformation characteristic when the impedance Z R changes. The unexpected inductive or capacitive component in Z L will affect the operating mode of the inverter stage. For the L type high-pass matching network shown in Fig. 4.1b, the parameters can be calculated with the similar method as abovementioned. At a certain operating angle frequency ω, the parameters C S and L S can be calculated as (4.7) shown.  ⎧ ⎪ ZL Z R ⎪ ⎪ ⎨ Ls = ω ZR − ZL ⎪ ⎪ 1 ⎪ ⎩ Cs = √ ω Z L (Z R − Z L )

(4.7)

Also, according to (4.7), it can be seen that the high-pass L type matching network is also a low-to-high structure which means input impedance Z L has to be smaller than Z R .

4.2.2 Influence of L Type Matching Network Figure 4.3 shows the circuit of the Class E resonant inverter stage with L type highpass matching network where rectifier stage is represented by the equivalent resistor Z R . To achieve desired output power  Po , the output impedance of the inverter stage 2 Po assuming the efficiency is 100%. can be calculated to be Z L = VDS When the switch turns off, the impedance Z DS between the switch source and drain can be represented as Fig. 4.4 shows, and the impedance Z DS determines the switch drain-source voltage waveforms. When Z L is resistive, the resonant frequency of the inverter stage can be calculated as

LF

Vin

Cs S

Inverter Stage

CF

ZL

Ls

Matching network

Fig. 4.3 Class E resonant inverter with L type matching network

ZR

4.2 L Type Matching Network

41

Fig. 4.4 Impedance diagram when the switch turns off

CF

ZDS

fF =

2π

√

LF

ZL

1 L F CF

(4.8)

However, with the change of equivalent resistance Z R under different output power conditions, the transferred impedance Z L cannot remain resistive in the L type matching network. The impedance angle of Z L can be calculated as 

θ Z L = arctan Im(Z L ) Re(Z L )

(4.9)

Figure 4.5 showsthe curve of θ Z L when the equivalent resistance Z R changes. The parameter A = Z R Z L represents the transfer ratio at the rated operating point, and at this point the impedance Z L is designed to be resistive as Fig. 4.5 shows. It can be seen 0.6

impedance angle of Z L(rad/s)

0.5 0.4 A=1.7 A=4.25 A=8.5

0.3 0.2 0.1 0 -0.1

Nominal Operating point

-0.2 -0.3 12

14

16

18

20

22

24

26

28

30

equivalent resistance Z R ( Ω)

Fig. 4.5 Impedance angle of Z L with change of Z R in L type matching network

32

42

4 Matching Network in Multi-MHz DC–DC Converter

that with the increment of Z R , the angle of Z L becomes larger than zero which means Z L changes to be inductive. On the contrary, the impedance Z L behaves capacitive. The trend is different from the L type low-pass matching network. The non-resistive characteristics of Z L induces extra inductance or capacitance components in the resonant tank, which affects the resonant frequency and operating characteristics of the high frequency converter. Figure 4.6 shows the switch drain-source voltage of the high frequency resonant circuit shown in Fig. 4.3 under different Z R conditions. Figure 4.6a shows the waveform of vDS at the rated operating point. It can be seen that at the turn-on point the voltage vDS just resonates to be zero, which means the switch can achieve ZVS turn-on characteristic. However, as shown in Fig. 4.6b, when the equivalent rectifier load Z R doubles, the switch drain-source voltage reaches zero before the coming of driving signal, thus the current reversely flows through the switch body diode. The reverse conduction causes large reverse conduction losses in high frequency condition. According to Eq. (4.8) and Fig. 4.5, it can be concluded that the resonant period 40

Voltage/V

30 20 ZVS

10 0 -10

0

40

80 Time/ns

120

(a) ZR=17Ω 40

Voltage/V

30 20 10 0 -10

Reverse conduction 0

40

80 Time/ns

120

(b) ZR=34Ω Fig. 4.6 Drain-source voltage waveforms under different equivalent load conditions

160

4.2 L Type Matching Network

43

decreases because of the extra inductive component of transferred impedance Z L . Thus, to guarantee the switch operating in the efficient situation within a large load variation range, it is necessary to adopt and design matching networks with resistive to resistive transferring characteristics when the equivalent resistance Z R changes.

4.3 T Type Matching Network In the following discussion, a T type matching network is adopted and analyzed to solve this problem. Figure 4.7 shows a diagram of the T type matching network, which is composed of two capacitors and one inductor. In the frequency domain, the transferred impedance of the T type matching network can be calculated as ZL =

s 3 Z R C1 L s Cs + s 2 (L s C1 +L s Cs ) + sCs Z R + 1 s 3 C1 L s Cs + s 2 C1 Cs Z R + sC1

(4.10)

The basic requirement of the matching network is to guarantee the transferred impedance Z L to be resistive at the operating angular frequency ω. Based on the above requirement, in the numerator and denominator of (4.10), the coefficients of the imaginary and real components must be in proportion and satisfy

C s Z R 1 − ω2 C 1 L s 1 − ω2 (L s C1 +L s Cs )

=Z L = −ω2 C1 Cs Z R C 1 1 − ω2 L s C s

(4.11)

Assuming C1 = kCs , then (4.12) and (4.13) can be obtained according to (4.11). ω2 C s L s =

ZR − k ZL k(Z R − Z L )

(4.12)

Fig. 4.7 Diagram of the T type matching network

C1 ZL

Cs Ls

Matching Network

ZR

44

4 Matching Network in Multi-MHz DC–DC Converter

ZL Z R=

ω2 L s Cs (k + 1) − 1 kω2 Cs2

(4.13)

Based on these equations, the final values of C 1 , C s , and L s can be calculated as ⎧  ⎪ Z L k2 − Z R 1 ⎪ ⎪ ⎪ Cs = ⎪ ⎪ ωk Z L Z R (Z L − Z R ) ⎪ ⎪ ⎪  ⎨ Z L k2 − Z R 1 C1 = ⎪ ⎪ ⎪ ω Z L Z R (Z L − Z R ) ⎪ ⎪ ⎪ ⎪ ZR − k ZL 1 ⎪ ⎪ ⎩ Ls = 2 ω Cs k(Z R − Z L )

(4.14)

The T matching network can achieve two resistance transformation cases: one is low-to-high case (Z L < Z R ), and the other is high-to-low case (Z L > Z R ). For these two different cases, the restrictions of k are quite different. For the low-to-high case, according to (4.12)–(4.14), (4.15) should be satisfied. ⎧ ⎪ ⎨ ZR − ZL > 0 ZR − k ZL > 0 ⎪ ⎩ Z R − k2 Z L > 0

(4.15)

From (4.15), the variation range of k in the low-to-high matching case can be calculated as:   (4.16) 0 < k < ZR ZL In the high-to-low matching case, the restrictions can be obtained as: ⎧ ⎪ ⎨ ZR − ZL < 0 ZR − k ZL < 0 ⎪ ⎩ Z R − k2 Z L < 0

(4.17)

Based on (4.17), the variation range of k in the high-to-low case can be calculated as 

 ZR ZL < k

(4.18)

Taking the low-to-high case as an example, in different k values and rated operating conditions, the parameter values are calculated as Table 4.1 shows. It can be seen  that at the same transfer ratio A = Z R Z L , with the increment of k, the values of capacitors C s and C 1 decrease. The minimum value of inductor L s is achieved when k

4.3 T Type Matching Network

45

Table 4.1 Parameters in different nominal operating conditions (f = 20 MHz) ZR

ZL

k

C s (pF)

C 1 (pF)

L s (nH)

17

5

0.5

1977.7

988.85

77.38

17

5

1

863.14

863.14

73.37

17

5

1.3

560.44

728.57

76.05

17

5

1.5

398.32

597.48

83.91

878.42

123.58

17

10

0.5

17

10

1

17

10

1.3

1756.8 610.33

610.33

103.76

72.95

56.11

496.05

= 1. On the other hand, at the same k, with the decrease in transfer ratio A, the values of the two capacitors also decrease while the value of the inductor L s increases. From the preceding analysis and parameters at the rated point, Fig. 4.8 shows the impedance angle of Z L when the equivalent resistance Z R changes. It can be seen that when k is smaller than 1, the impedance Z L becomes inductive with the increment of impedance Z R . The trend is similar to that of the L type high-pass matching network. However, when k is larger than 1, the impedance Z L becomes capacitive with the increment of impedance Z R , which is similar to that of the L type low-pass matching network. The expected characteristic appears when k = 1. In this condition the impedance angle of Z L always remains zero, it means Z L is resistive no matter how the equivalent resistance Z R changes. The same conclusion 0.4

impedance angle of ZL (rad/s)

0.3 0.2

Nominal Operating point 0.1 0 -0.1 -0.2 k=0.5 k=1 k=1.5

-0.3 -0.4 -0.5 12

14

16

18

20

22

24

26

28

30

equivalent resistance Z R (Ω)

Fig. 4.8 Impedance angle of Z L with change of Z R in T type matching network

32

46

4 Matching Network in Multi-MHz DC–DC Converter

LF

C1 CF

Vin

Inverter Stage

ZL

Cs Ls

ZR

Matching Stage

Fig. 4.9 Diagram of high frequency converter with T type matching network

can also be drawn after substituting the corresponding parameters into (4.10), where the imaginary parts are zero. Based on Class E inverter stage, Fig. 4.9 shows the circuit of a high frequency converter with the T type matching network at k = 1 which replaces the L type matching network in the above resonant converter. Figure 4.10 shows the simulation results at Z R = 17  and Z R = 34  condition respectively. From Fig. 4.10a it can be seen that the switch can turn on in ZVS condition at the rated operating point and the drain-source voltage waveform is the same as that in Fig. 4.6a. Figure 4.10b shows the voltage waveform when the equivalent rectifier load Z R doubles, the waveform is similar to that at the nominal operating point. Except that at the turn-on point, the drain-source voltage is a little bit higher than zero which is caused by the magnitude change of the transferred impedance Z L . The resistive T type matching network leads to small changes to the resonant tank of inverter stage because of no extra inductive or capacitive components. Comparing with the reverse conduction loss in L type matching network, T type matching network can guarantee well switching characteristics and small switching loss.

4.4 π Type Matching Network At the same time, because of the duality characteristics, a similar π type matching network can also be proposed as Fig. 4.11 shows. With a similar design procedure to that of the T type matching network, the parameter expressions of the π type matching network can be obtained:

4.4 π Type Matching Network

47

40

Voltage/V

30 20 10 0 -10

0

40

80 Time/ns

120

160

120

160

(a) ZR=17Ω 40

Voltage/V

30 20 10 0 -10

0

40

80 Time/ns (b) ZR=34Ω

Fig. 4.10 Drain-source voltage waveforms of high frequency converter with T type matching network Fig. 4.11 Diagram of the π type matching network

Ls

ZL

C1

Matching Stage

Cs

ZR

48

4 Matching Network in Multi-MHz DC–DC Converter

 ⎧ ZL − ZR 1 ⎪ ⎪ ⎪

⎪ Cs = ω ⎪ Z L Z R k2 Z L − Z R ⎪ ⎪ ⎪ ⎪  ⎪ ⎨ ZL − ZR k

C1 = ⎪ ω Z L Z R k2 Z L − Z R ⎪ ⎪ ⎪  ⎪

⎪ ⎪ ⎪ Z L Z R Z R − k 2 Z L (Z R − Z L ) ⎪ ⎪ ⎩ Ls= ω(Z R − k Z L )

(4.19)

where C1 = kCs . Under different situations, the parameters of π type matching network can be calculates as Table 4.2 shows. Figure 4.12 shows the angle curves Table 4.2 Parameters of π type matching network (f = 20 MHz) ZR

ZL

k

C s (pF)

C 1 (pF)

L s (nH)

17

5

0.5

753.41

376.7

69.56

17

5

1

863.14

863.14

73.37

17

5

1.3

1022.6

1329.3

70.78

17

5

1.5

1246.9

1870.4

64.15

17

10

0.5

17

10

1

17

10

1.3

424.06 610.33 5106.4

212.03

87.11

610.33

103.76

6638.3

21.7

0.5

impedance angle of Z L (rad/s)

0.4 k=0.5 k=1 k=1.5

0.3 0.2 0.1 0 -0.1

Nominal Operating point

-0.2 -0.3 -0.4 12

14

16

18

20

22

24

26

28

30

32

equivalent resistance ZR (Ω)

Fig. 4.12 Angle curves of impedance Z L with change of Z R in π type matching network

4.4 π Type Matching Network

49

of impedance Z L when the equivalent resistance Z R changes. Similar to the T type matching network when k = 1, the impedance angle of Z L always remains at zero, which means that Z L is resistive no matter how the equivalent resistance Z R changes. Compared with the parameters in Tables 4.1 and 4.2, when k = 1, the capacitance and inductance of T type matching network and π type matching network are the same under the same condition. It means that the two structures can be replaced by each other. One difference is that in T type structure, capacitor C s and C 1 is series with the load which can achieve DC blocking function naturally. The selection of matching network structure should consider the rectifier structure and input/output characteristics comprehensively.

4.5 Example Based on T Type Matching Network Based on the above analysis, a 20 MHz high frequency resonant converter with 10 W output power is designed and built in the laboratory. The circuit is shown in Fig. 4.13 and the picture of the prototype is shown in Fig. 4.14. Figure 4.15 shows the waveforms of the switch and driving signal under full load condition. It can be seen that the switch turns on in ZVS condition, and the driving signal is in sinusoidal form, which can reduce the driving loss. The driving method will be introduced in Chap. 6. Figure 4.16 and Fig. 4.17 show main voltage waveforms under the 90% load and 50% load conditions respectively. It can be seen that with the proposed T type matching network, the switch can always turn on in ZVS or quasi-ZVS condition within a wide load variation range. And the ON–OFF control method is adopted in the converter. Figure 4.18 and Fig. 4.19 show the switch and driving signal voltage waveforms during the turn-on and turn-off transitions respectively. It can be seen that because

Drec

MOSFET

LF Vgate

C1

S Cds Cext CF

CD CDext

Cs Ls

Vo

Lrec

Cout Rout

Crec

Lg Lp CB

PWM Controller

Fig. 4.13 Prototype of 20 MHz high frequency converter with T type matching network

50

4 Matching Network in Multi-MHz DC–DC Converter

Fig. 4.14 Photograph of the 20 MHz DC–DC prototype

vGS(10V/div) vDS(20V/div)

Time(20ns/div) Fig. 4.15 Waveforms of switch drain-source voltage and driving voltage under rated load

4.5 Example Based on T Type Matching Network

51

Time(2us/div)

vGS(10V/div)

vDS(20V/div)

Time(20ns/div) (a) switch drain-source voltage and driving voltage

vout(500mV/div)

Time(2us/div) (b) output voltage (AC coupled)

Enable(10V/div)

Time(2us/div) (c) enable signal of the PWM controller Fig. 4.16 Main voltage waveforms in 90% load condition

52

4 Matching Network in Multi-MHz DC–DC Converter

Time(2us/div)

vGS(10V/div) vDS(20V/div)

Time(20ns/div) (a) switch drain-source voltage and driving voltage

vout(500mV/div)

Time(2us/div) (b) output voltage (AC coupled)

Enable(10V/div)

Time(2us/div) (c) enable signal of the PWM controller Fig. 4.17 Main voltage waveforms in 50% load condition

4.5 Example Based on T Type Matching Network

53

vDS(20V/div)

vGS(10V/div)

Time(200ns/div) Fig. 4.18 Switch and driving voltage waveforms during the turn-on transition

vDS(20V/div)

vGS(10V/div)

Time(200ns/div) Fig. 4.19 Switch and driving voltage waveforms during the turn-off transition

there is no bulk inductor in the proposed high frequency converter, the transition time is short and it can achieve very fast dynamic response. Figure 4.20 shows the efficiency curves of prototypes based on different matching network. Comparing the efficiency of high frequency converter with the T type matching network and L type matching network, it can be seen that in the full load condition, their efficiencies are approximately the same. However, with decreasing output power, the converter based on T type matching network is more efficient because of the good soft-switching characteristics in light load condition.

54

4 Matching Network in Multi-MHz DC–DC Converter 82 81.5

efficiency (%)

81 80.5 80 79.5 79 Resistive T type matching network L type matching network

78.5 78 50

55

60

65

70

75

80

85

90

95

100

output power ratio (%)

Fig. 4.20 Efficiency of 20 MHz DC–DC converter with different matching networks

Chapter 5

Typical Multi-MHz DC–DC Converter

Based on the research of resonant inverter stage in Chap. 2, resonant rectifier stage in Chap. 3 and matching network in Chap. 4, many different kinds of multi-MHz DC–DC converters can be derived. In this Chapter, some typical DC–DC converters with different characteristics will be described.

5.1 Non-isolated DC–DC Converter As the circuit diagram introduced in Chap. 1, the simplest DC–DC converter can be composed only by inverter stage and rectifier stage, which realizes DC-to-AC transformation and AC-to-DC transformation, respectively. Figure 5.1 shows the circuit of resonant Boost converter which is composed by Class E inverter stage and voltage-driven Class E rectifier stage [1]. Based on the similar idea, the resonant boost converter based on Class 2 inverter stage can also be built as Fig. 5.2 shown [2]. The operating modes of the two topologies are similar. For both topologies, the equivalent impedance of the rectifier meets the inverter requirement. Thus, the matching network is not added in the circuits. As can be noticed from the topologies, there are only inductors and diode in series between the input voltage and output voltage. The average voltage of the inductor during one period is zero, and the average voltage of the diode during one period is negative. Thus, for this kind of topologies, they can only provide step-up voltage conversion ability. If the step-down voltage conversion ability is needed, there must be a DC blocking capacitor in series between the input port and output port. The main difference is that the resonant boost circuit based on Class 2 inverter stage owns lower switch voltage stress which is suitable to be applied in high input voltage applications. When the impedance of rectifier stage and inverter stage is not matched, the matching network is needed to be added between these two stages. Figure 5.3 shows the circuit of the SEPIC converter [3], the inverter stage is Class E topology, the rectifier stage is current-driven resonant topology, and the matching network is L-type © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_5

55

56

5 Typical Multi-MHz DC-DC Converter LR

LF VIN

S

CIN

D CR

CE

COUT

RL

Fig. 5.1 Circuit of resonant boost converter based on Class E inverter

Lrect

LF L2F VIN

Smain

CIN

D

CF

Crect

COUT

RL

C2F

Fig. 5.2 Circuit of resonant boost converter based on Class 2 inverter

CEX2 LF VIN

CIN

S

CEX

+

D1

CS LRS

COUT

VOUT

-

Fig. 5.3 Circuit of SEPIC converter

high-pass network. The inductance L RS is the paralleled inductance of the matching network and the rectifier stage. Here, C S also plays the role of DC blocking capacitor; thus, this converter owns both step-up or step-down voltage conversion ability. Here, the diode in the resonant stage can be placed in the ground referenced position to achieve easy driving method. However, with this method, the input voltage and output voltage cannot share the same ground. To further improve converter performance under the light load situation, the T-type matching network can be used to replace the L-type matching network in abovementioned SEPIC converter, and the circuit of SEPIC-derived is shown in Fig. 5.4 [4].

5.1 Non-Isolated DC-DC Converter

57

CEX2 LF VIN

CS

C1 S

CIN

D1

LS

CEX

LR

RL

COUT

Fig. 5.4 Circuit of SEPIC-derived converter

As introduced in Chap. 4, with the adoption of T-type matching network, the switch of the inverter stage can own soft-switching characteristics within a wide load range, especially for the light load situation. Also, the converter can still realize step-up and step-down voltage conversion. Based on the aforementioned typical topologies, some scholars begin to propose some new topologies, such as interleaved converters [5] and bidirectional converters [6], as Figs. 5.5 and 5.6 show. Similar to the application of the interleaved technology in low-frequency condition, the input current ripple of multi-MHz power converter can be reduced when CR1 LI1

vDS1

S1

CI1

LR1

D1

+ CR2

VIN LI2

VOUT -

vDS2 S2

COUT

CI2

Fig. 5.5 Schematic of the interleaved class E converter

LR2

58

5 Typical Multi-MHz DC-DC Converter

LRex

Lin Vin

Cin

S1

Cext1

CRex S2

+

Lout

Cext2

Cout

Vout

Fig. 5.6 Schematic diagram of bidirectional synchronous DC–DC converter

two complementary signals are applied to drive two interleaved circuit modules. The circuit of the interleaved converter based on the SEPIC circuit is shown in Fig. 5.5. In article [5], this prototype is used as the LED driver operating at 120 MHz. The output power is 3–9 W, and the efficiency is 80–89%. The application of the interleaved technology can effectively reduce the input and output ripple, so that this converter can be applied in high power fields. However, the tiny deviations of the two circuit modules may result in the offset of the system’s optimal operating point. In such high frequency condition, the differences of two modules would greatly affect the system optimal operating mode. As seen in Fig. 5.6, the diode in the rectifier stage is replaced by a switch, and then a bidirectional converter is obtained [6]. This converter is composed of Class E inverter and Class E synchronous rectifier. When the circuit operates in forward mode, S 1 acts as the power switch and S 2 acts as the synchronous rectifier diode. When the circuit runs in reverse mode, the roles of the switches are opposite to the former. Besides the ability of conducting bidirectionally, this converter can also effectively reduce the conduction loss of the rectifier stage by adopting the synchronous switch. However, this topology requires an extra driving circuit, and the two driving signals must satisfy a specific logical relationship under multi-MHz, which is a great challenge for the design of driving circuit. Based on the half-bridge inverter stage or rectifier stage, the voltage stress across the switch and the diode can be further reduced, such as Class DE inverter or rectifier. The switch is directly connected with the input port; thus, the stress is equal to input voltage. Based on Class DE half-bridge inverter stage and Class E rectifier stage, the half-bridge circuit is shown in Fig. 5.7 [7]. With similar method, the rectifier stage can be replaced by Class DE structure, and the circuit is shown in Fig. 5.8 [8]. Besides low device voltage stress, compared with the other topologies mentioned above, the half-bridge converters in Figs. 5.7 and 5.8 only contain one inductor, which is beneficial to improving the power density of the system. For half-bridge structure, great attention should be paid to the parasitic components in the half-bridge structure, which significantly affect the operation of the multi-MHz converters. The half-bridge circuits are very suitable for the applications where high input voltage or output voltage is required.

5.2 Isolated DC-DC Converter

59

S1

VIN

CS1

CIN

CR

S2

D

Lr

Cr

LR

CS1

COUT

RL

Fig. 5.7 Circuit of a half-bridge converter based on class DE inverter and Class E rectifier

+ S1

VIN

CR1

CO1

VOUT

CIN S2

D1

CS1

Cr CS1

Lr D2

CR2

CO2

Fig. 5.8 Circuit of a half-bridge converter based on class DE inverter and Class DE rectifier

5.2 Isolated DC–DC Converter Besides the non-isolation structure, the isolation function is expected in many application fields. As shown in Fig. 5.9, a DC–DC converter based on class 2 inverter stage is achieved with the capacitive isolation barrier method. With similar method, the circuit based on Class E inverter and Class DE rectifier is shown in Fig. 5.10 [9]. With an additional capacitor in the return loop, the isolation function can be effectively achieved. Under operating frequencies of hundreds of kHz, the value and volume of isolation capacitor must be very large. However, in multi-MHz conditions with reduced energy requirement, the value and volume can be significantly decreased. Also, the parasitic resistance and volume of ceramic capacitor is usually

60

5 Typical Multi-MHz DC-DC Converter

LF

CRES1

+

LREC

LRES

L2F S1

VIN

CREC

CEXT

C2F

D1

COUT

CRES2

VOUT

-

Fig. 5.9 Circuit of Class 2 inverter with capacitive isolation barrier

+ D1

CD1

CRES1

LRES

CO

LIN VIN

CIN

S

CS

D2 CRES2

VOUT

CD2

-

Fig. 5.10 Circuit of Class E inverter with capacitive isolation barrier

quite lower than its magnetic component counterpart, which helps to improve the system efficiency and power density. However, for higher voltage isolation requirement, significant problems exist in the capacitive isolation method. One problem is that with the increment of rated voltage, the volume of capacitor greatly increases which is not conducive to reducing the converter volume. Furthermore, with large capacitor size, the parasitic inductance caused by leads also greatly affects the high frequency operation. It should be mentioned that in Fig. 5.10, the parasitic inductance of C RES1 can be absorbed by L RES ; however, the parasitic inductance of C RES2 leads to great impact. Another problem is that for kV isolation applications there are almost no high-quality-factor capacitors which are available to operate at such high switching frequency. With a low-quality factor, the system suffers significant loss. Similar to the low-frequency conditions, magnetic isolation based on transformer is the most common method. It can be applied to both the low-voltage and highvoltage applications. For transformer-based solutions, the effect of leakage inductance and magnetizing inductance on the operation of multi-MHz converters cannot

5.2 Isolated DC-DC Converter

61

be ignored. To solve this problem, one effective way is to consider the leakage inductance and magnetizing inductance as resonant components through the optimal topology design. The isolated converter can be achieved by adding the transformer between the inverter stage and rectifier stage. The Class E inverter-based and Class 2 inverterbased isolated converters are shown in Fig. 5.11 [10] and Fig. 5.12 [11], respectively. Meanwhile, the Class E rectifier is realized based on the synchronous rectification. The synchronous rectifier can reduce the conduction loss because of small switch onresistance, but it is noteworthy that the corresponding driving circuit in the secondary side is needed, which causes additional driving loss. Therefore, a trade-off between conduction loss and driving loss must be implemented. Another great challenge for synchronous rectification is precision of control signal. Under multi-MHz situations, the time difference between primary side and secondary side is very small; thus, small time delay leads to the change of operating mode. The number of inductors in these topologies can be further reduced. Figure 5.13 shows an example of optimizing the topology of an isolated multi-MHz converter [12]. An isolated DC–DC converter based on Class 2 inverter stage and Class E rectifier stage is illustrated in Fig. 5.13a, where one transformer is added between these two stages. The leakage inductance in the secondary side can be combined

LF VIN

Sctrl

CIN

+

C1 * NP

Lm

COUT

* NS

RL

VOUT

Sr

Fig. 5.11 Circuit of isolated converter based on Class E inverter

LF LM VIN

CIN

Sctrl

CF

+

Lr

CS * NP

* NS

CM

COUT Cr

RL

VOUT

Sr

Fig. 5.12 Circuit of isolated converter based on Class 2 inverter

62

5 Typical Multi-MHz DC-DC Converter LF

CRES

LI2

LI1

L2F VIN

+

D1

* *

S1

CIN

LREC

LU1

CEXT

CREC

COUT

VOUT

C2F NP : NS

(a) LI2

LI1

+

D1

* LU1

CREC

COUT

VOUT

* NP : NS LF L2F S1

VIN

CEXT

C2F

(b) LI2

LI1

+

D1

* LU1

CREC

COUT

VOUT

* NP : NS

VIN

L2F S1

CF

C2F

(c)

Fig. 5.13 Transformation from non-isolated converter to isolated converter, a non-optimal structure, b combining two inductors, c optimal structure [12]

with the resonant inductor. From the perspective of AC analysis, the DC input source can be seen as short circuit; thus, one port of the transformer primary side can be adjusted to the input side as shown in Fig. 5.13b. Also, the resonant inductor L F can be combined with the transformer primary-side leakage inductance. Finally, as shown in Fig. 5.13c, the magnetizing inductance is merged with input inductance. Therefore,

5.2 Isolated DC-DC Converter

63

this example shows the approach of adopting the leakage inductance and magnetizing inductance into the multi-MHz isolated converter. It should be mentioned that in Fig. 5.13a, capacitor C RES plays the role of blocking DC voltage. Thus, its value is much larger than the resonant capacitor. The voltage across C RES can be seen as constant, and therefore, this capacitor can behave as a voltage source. In Fig. 5.13b, there is no need for DC voltage blocking and CRES does not exist. Compared with Figs. 5.13a, c, two resonant inductors are saved, which can help to reduce the count and volume of the components, in order to improve the power density. Based on the aforementioned converter, the diode in the secondary side can be replaced by a synchronous switch as shown in Fig. 5.14 [13]. Also, the LLC-type topology can also be applied in the multi-MHz converter [14]. (Fig. 5.15)

VIN

+

LO2

LO1 * NP

LM1

CIN

NS *

COUT

RL

Cr

VOUT

L2F

CF

Sctrl

Sr

C2F

Fig. 5.14 Isolated circuit based on transformer integration + S3

S1 Cr VIN

CIN

C1

Lr Lm

LP

S2

CO

LS S4

VOUT

C2

-

Fig. 5.15 LLC-type isolated multi-MHz converter

64

5 Typical Multi-MHz DC-DC Converter

5.3 Example of Low Voltage Stress Isolated DC-DC Converter A low voltage stress isolated converter is shown in Fig. 5.16. Different circuits can be used as the rectifier stage, such as Class E resonant rectifier circuit, half-bridge rectifier circuit and so on. The circuit takes full advantage of the primary-side and secondary-side leakage inductance, and the impedance across the switch can be optimized which can help the switch to operate under soft-switching and low-stress conditions by adopting the high-order harmonic components. The equivalent network of impedance ZDS in the isolated topology is shown in Fig. 5.17 in which the corresponding parameters are transferred to the primary side. C B represents a DC blocking capacitor with large capacitance; thus, the voltage can be seen as a constant value. n represents the turns ratio in the ideal transformer model. Z rec is the equivalent impedance of the rectifier stage, which can be ignored in the resonant tank with a high-quality factor. Then, the switch impedance Z DS can be derived as: Z DS =

N1 s 3 + N2 s K1s4 + K2s2 + K3

LF CB S

Lr

(5.1)

n:1

Lrec

Crec

Lm

CF

Zrec T

Fig. 5.16 Circuit of proposed single-switch isolated resonant converter

Fig. 5.17 Impedance of switch drain-to-source

Lr CF ZDS

LF

CB Lm

n2Lrec n2Zrec

Crec/n2

5.3 Example of Low Voltage Stress Isolated DC-DC Converter

65

where

 2 L rec = L r n , N1 = (L r L rec + L m L rec + L m L r /n 2 )L F Crec , N2 = (L m + L r )L F , K 1 = (L r L rec + L m L rec + L m L r /n 2 )L F CF Crec , K 3 = L F + L m + L r ,

K 2 = [(L m + L r )CF + (L m /n 2 + L rec )Crec ]L F + (L r L rec + L m L rec + L m L r /n 2 )Crec . To reduce the switch voltage stress, the switch impedance between the drain and source is expected to be similar as that of the Class 2 inverter stage. According to the aforementioned analysis, there should be a zero at the second harmonic in the switch impedance Z DS . Thus, C rec can be calculated as: Crec =

n 2 (L m + L r ) 4ω2 (L 2r + 2L m L r )

(5.2)

Moreover, there should be two poles in the switch impedance Z DS at fundamental frequency and third harmonic frequency. The phase angle of the impedance can be adjusted to be slightly larger than zero which helps to achieve ZVS turn-on. Thus, one pole is located slightly higher than ω and the other is slightly lower than 3ω. Here, the locations of the two poles are represented by m1 ω and m2 ω, where m1 is slightly higher than 1 (1 < m1 < 2) and m2 is slightly lower than 3 (2 < m2 < 3). Thus, the denominator of (5.1) is yielded to be zero when s = jm1 ω and s = jm2 ω. Thus, the relationship among m1 , m2 , and the resonant components can be obtained as (5.3) and (5.4) show. ⎧ K2 ⎪ 2 2 2 ⎪ ⎨ (m 1 + m 2 )ω = K1 K ⎪ ⎪ ⎩ m 21 m 22 ω4 = 3 K1

⎧ 4 L 2m ⎪ ⎪   2

 C = · F ⎪ ⎨ 4 m 1 + m 22 − 4 − m 21 m 22 ω2 L 2r + 2L m L r (L m + L r )

   2 ⎪ 4 m 1 + m 22 − 4 − m 21 m 22 L 2r + 2L m L r (L m + L r ) ⎪ ⎪   ⎩ LF = 2 2 m 1 m 2 (L m + L r )2 − 4 m 21 + m 22 − 4 L 2r + 2L m L r

(5.3)

(5.4)

By substituting the coupling coefficient of the transformer k = L m /(L m + L r ) into the above equations, (5.5) to (5.7) can be obtained: Crec =

n2 4ω2 (1 + k)L r

4 k2

CF =   2 · 4 m 1 + m 22 − 4 − m 21 m 22 ω2 (1 + k)L r

  (1 + k) 4 m 21 + m 22 − 4 − m 21 m 22 · Lr   LF = 2 2 m 1 m 2 − 4 m 21 + m 22 − 4 1 − k 2

(5.5)

(5.6)

(5.7)

66

5 Typical Multi-MHz DC-DC Converter

Lr

n2Lrec

Crec/n2

Lm

Vinv1

+ n2Zrec

nVrec1

Fig. 5.18 Equivalent circuit of transformer and rectifier stage

In the expression of L F , it can be seen that the denominator should be greater than zero to guarantee the value of L F is positive. By solving the inequation, the value range of the coupling coefficient k can be obtained: 

m2m2 = k0 < k 1 −  2 1 22 4 m1 + m2 − 4

(5.8)

Here, k 0 represents the critical value. As indicated by (5.8), the coupling coefficient must be larger than the critical value. Figure 5.18 shows the equivalent circuit of the transformer and rectifier stage. V inv1 represents the fundamental component of the transformer primary-side voltage, and V rec1 represents the voltage of the rectifier stage. During one duty cycle, the equivalent rectifier impedance can be calculated as the ratio of the fundamental voltage to the fundamental current. Then, the voltage of the rectifier stage transferred to the primary side can be approximately calculated as (5.9): nVrec1

n 2 Z rec k = Vinv1 · − jω(3 + 3k)L + n 2 Z r

rec



(5.9)

Also, the output power can be expressed as follows:

Pout =

nVrec1

√  2 2

n 2 Z rec

=

8Vin2 n 2 k 2 Z rec 

2 π 2 9ω2 (1 + k)2 L 2r + n 4 Z rec

(5.10)

Using the above equations, the relationship between the output power and system components can be investigated. Figure 5.19 shows the output power curves with variable inductor L r and coupling coefficient k. The output power forms a proportional relationship with the coupling coefficient and forms an approximately inversely proportional relationship with the transformer leakage inductance of primary side. These results indicate that the parameters of the transformer can be determined by the voltage gain and output power requirements.

5.3 Example of Low Voltage Stress Isolated DC-DC Converter Fig. 5.19 Output power curves under different Lr and k conditions

67

16

Pout (W)

12 8 4 0 8

12

16

20

24

28

0.7

32 0.6

0.8

1

0.9

As indicated by (5.5) to (5.7), it can be seen that the values of the other resonant elements can be calculated once the parameters of the transformer are determined. Thus, the effect of the transformer parameters must be investigated in detail. Figure 5.20a shows the curves of the critical coupling coefficient value k 0 with the variation of m1 and m2 . It can be seen that the critical coupling coefficient forms a proportional relationship with m2 and an inversely proportional relationship with m1 . 500

0.8

400

Crec (pF)

k0

0.75 0.7 0.65 0.6 1

300 200 100

1.1

1.2

1.3 2.7

2.8

2.9

0 5 10 15 20 25 30 0.6

3

0.9

1

20 k=1

LF / Lr

CF / Crec

0.8

(b) curves of resonant capacitance Crec

(a) curves of coupling coefficient 9 8 7 6 5 4 3 2 1

0.7

1.2

1.3 2.7

2.8

10

k=k0+0.1

5

k=k0 1.1

k=k0+0.05

15

2.9

3

(c) curves of resonant capacitance CF/Crec

0 1

k=1 1.1

1.2

1.3 2.7

2.8

2.9

(d) curves of inductance ratio LF/Lr

Fig. 5.20 Parameter value curves with different coefficients of pole locations

3

68

5 Typical Multi-MHz DC-DC Converter

Also, the coupling coefficient of the transformer must be larger than k 0 . The specific design method for the air-core PCB transformer will be presented in the next section. Figure 5.20b illustrates the curves of the capacitor C rec with the variation of the primary leakage inductance L r and coupling coefficient k. It can be seen that the capacitance forms an inversely proportional relationship with the resonant inductor L r and coupling coefficient k. Figure 5.20c shows the curves of C F /C rec with the variation of m1 and m2 for different values of k. For a certain C rec , the value of C F increases with a larger transformer coupling coefficient. Figure 5.20d shows the curves of L F /L r with the variation of m1 and m2 for different values of k. As indicated by Fig. 5.20d and (5.7), L F /L r is quite high if k is very close to k 0 . This means that the value of L F must be very large, which is not expected in high-frequency converters. Inductor with a large value increases the system volume and reduces the system efficiency. It can be seen that the ratio of L F to L r decreases as k increases. Thus, large L F can be avoided by increasing the coupling coefficient of the transformer. According to the obtained equations, the capacitance and inductance of the isolated converter can be calculated. These corresponding parameters should be slightly tuned according to simulation results because of the effects of non-ideal characteristics and high-order harmonics. Then, the switch impedance can be optimized with the proper locations of zeros and poles. Here, m1 and m2 are selected to be 1.3 and 2.7, respectively. The simulation parameters are as follows: Resonant inductor L F is 27 nH, L S is 72 nH, self-inductance of primary side is 52.8 nH, self-inductance of secondary side is 195.9 nH, and the coupling coefficient is 0.81. Capacitor C rec is 330 pF, C F is 1150 pF and C S is 450 pF. The SPICE-based simulation result of the switch voltage waveform U DS is shown in Fig. 5.21 where the input voltage is 12 V. It can be seen the switch voltage stress is tuned to about 2.5 times the input voltage, and there is no reverse conduction. Thus, it can be seen that the isolated high-frequency converter can achieve a low voltage stress and ZVS without the introduction of an additional branch. Figure 5.22 shows the Bode diagram of the switch drain–source impedance based on the above parameters. The switch impedance is consistent with the calculation results.

UDS/V

30 20 10 0 0

20

60

40

Time/ns Fig. 5.21 Simulation waveform of switch drain–source voltage

80

5.3 Example of Low Voltage Stress Isolated DC-DC Converter

69

Magnitude (dB)

60 40 20 0

Phase (deg)

-20 90 45 0

26MHz

-45 -90 106

54MHz 40MHz

107

Frequency (Hz)

108

Fig. 5.22 Bode plot of the switch drain–source impedance

In order to verify the feasibility of the isolated high-frequency converter and the corresponding design method, a 20 MHz experimental prototype is constructed, wherein the resonant rectifier is adopted. The input voltage is 12 V, the output voltage is 5 V, and rated power is 10 W. The picture of the prototype is shown in Fig. 5.23. Figure 5.24 shows the drain–source voltage and gate voltage waveforms of the switch. It can be seen that the switch realizes ZVS, and the peak voltage of U DS is about 31 V, which is 2.58 times the input voltage. Compared with traditional Class E topology, the voltage stress of the switch is effectively reduced. Based on the resonance between the inductor and the switch input capacitor, the resonant driving method can use the energy stored in the switch input capacitance during each switching period, which reduces the driving circuit losses under high-frequency conditions. Thus, it can be seen that the switch gate voltage is in a sinusoidal form. This driving method will be introduced in the next chapter. Figure 5.25 shows the waveforms of the drain–source voltage U DS and gate voltage U GS of the switch at 50% load. It can be seen that the duty cycle of the PWM signal is reduced to 0.4. With the ON–OFF control method, the output voltage V OUT can be regulated.

70

5 Typical Multi-MHz DC-DC Converter

(a) Top view

(b) Side view Fig. 5.23 Photograph of the proposed prototype

UDS(10V/div)

UGS(10V/div)

Time(40ns/div) Fig. 5.24 Switch drain–source voltage and driving voltage

5.3 Example of Low Voltage Stress Isolated DC-DC Converter

71

UDS(10V/div)

1.16us

Time(2us/div)

2.9us

UGS(10V/div)

Fig. 5.25 Switch drain–source voltage and driving voltage in light load condition

References 1. Burkhart JM, Korsunsky R, Perreault DJ (2013) Design methodology for a very high frequency resonant boost converter. IEEE Trans Power Electron 28(4):1929–1937 2. Pilawa-Podgurski RCN, Sagneri AD, Rivas JM, Anderson DI, Perreault DJ (2009) Very-highfrequency resonant boost converters. IEEE Trans Power Electron 24(6):1654–1665 3. Hu J, Sagneri AD, Rivas JM et al (2012) High-frequency resonant SEPIC converter with wide input and output voltage ranges. IEEE Trans Power Electron 27(1):189–200 4. Guan Y, Bian Q, Wang Y et al (2018) Analysis and design of high-frequency converter with resistive matching network and spiral inductor. IEEE Trans Power Electron 33(6):5062–5075 5. Kovacevic M, Knott A, Andersen MAE (2013) Very high frequency interleaved self-oscillating resonant SEPIC converter. In: 2013 15th European conference on power electronics and applications (EPE), 2013, pp 1–9 6. Pedersen JA (2013) Bidirectional very high frequency converter. Technology University of Denmark, Lyngby 7. Madsen MP, Knott A, Andersen MAE (2013) Very high frequency resonant DC/DC converters for LED lighting. In: 2013 twenty-eighth annual IEEE applied power electronics conference and exposition (APEC), pp 835–839 8. Madsen MP, Knott A, Andersen MAE (2014) Very high frequency half-bridge DC/DC converter. In: 2014 IEEE applied power electronics conference and exposition, 2014, pp 1409–1414 9. Pedersen JA, Madsen MP, Mønster JD, Andersen T, Knott A, Andersen MAE (2016) US mains stacked very high frequency self-oscillating resonant power converter with unified rectifier. In: 2016 IEEE applied power electronics conference and exposition (APEC), 2016, pp 1842–1846 10. Xu Z, Zhang Z, Xu K, Dong Z, Ren X (2017) 2-MHz GaN PWM isolated SEPIC converters. In: 2017 IEEE applied power electronics conference and exposition (APEC), 2017, pp 149–156 11. Zhang Z, Zou XW, Dong Z, Zhou Y, Ren X (2017) A 10-MHz eGaN Isolated Class-2 DCX. IEEE Trans Power Electron 32(3):2029–2040

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5 Typical Multi-MHz DC-DC Converter

12. Sagneri AD (2008) Design of miniaturized radio frequency dc-dc power converters. Massachusetts Institute of Technology, Cambridge 13. Zhang ZL, Dong Z, Zou XW, Ren X (2017) A digital adaptive driving scheme for eGaN HEMTs in VHF converters. IEEE Trans Power Electron 32(8):6197–6205 14. Thummala P, Yelaverthi DB, Zane RA, Ouyang Z, Andersen MAE (2019) A 10-MHz GaNFETbased-isolated high step-down DC–DC converter: design and magnetics investigation. IEEE Trans Ind Appl 55(4):3889–3900

Chapter 6

Resonant Driving Method

6.1 Basic Resonant Driving Circuit Under multi-MHz high-frequency conditions, in addition to higher switching loss, the loss of the driving circuit also increases rapidly with the increment of the switching frequency. Figure 6.1 shows the main parasitic parameter diagram of the power MOSFET device. This lumped parameter model ignores the parasitic inductor caused by the device packaging and other factors. Rg is the gate input resistance. C gs represents the gate–source parasitic capacitance, C gd represents the drain–gate parasitic capacitance, and C ds represents the output parasitic capacitance. Under low-frequency conditions, square-wave driving (hard driving) is usually used to control on and off of switches. The circuit often uses the totem pole structure shown in Fig. 6.2. When the main switch S main needs to be turned on, the switch S top is turned on, and the parasitic capacitance C gs is charged until the voltage reaches V g . When the main switch S main needs to be turned off, the switch S top is turned off, and the switch S bottom is turned on. Then, the parasitic capacitance C gs is discharged. When the gate voltage is lower than the threshold voltage, the main switch is turned off. Generally, at low-frequency conditions, the duty cycle is much larger than the time constant C gs Rg , and the gate driving voltage can be approximated seen as a square wave. From its operating mode, it can be seen that the energy of the gate–source capacitance in the square-wave driving method is completely exhausted during the period. Therefore, as the operating frequency increasing, the power loss of the squarewave driving method will increase rapidly. In addition, as the switching frequency increases, the system expects the driving circuit to provide larger driving current to achieve the fast turn-on/turn-off of the switch. However, the maximum driving current of the square-wave driving circuit is proportional to the driving voltage. Increasing the voltage can increase the driving current, but it will further increase the driving loss of the system. In order to solve the abovementioned shortcomings of the square-wave driving circuit, the concept of a resonant driving method has been proposed in recent years. © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_6

73

74

6 Resonant Driving Method

Fig. 6.1 Lumped parameter model of power MOSFET

Drain Cgd Rg

S

Cds

Gate Cgs Source

Vg

Fig. 6.2 Circuit diagram of square-wave driving (hard driving) method

Stop

Vbus

Rg Smain Cgs Sbottom

Fig. 6.3 Circuit diagram of basic resonant driving method

Vg Stop

Vbus LG

Rg

Smain

Cgs Sbottom

The most obvious difference between a resonant driving circuit and a square-wave driving circuit is that the driving voltage is sinusoidal or approximately sinusoidal form. The idea of the resonant driving method is to use the energy of the input parasitic capacitance through resonance to reduce the power loss. The simplest resonant driving circuit is shown in Fig. 6.3. A series resonant inductor is added in the driving

6.1 Basic Resonant Driving Circuit

75

circuit. Figure 6.4 shows the equivalent circuit of the resonant driving circuit, where RI represents the parasitic resistance of the voltage source and the resonant inductor. According to the structure of the driving circuit, the transfer function describing its driving ability can be obtained as (6.1) shows. The Bode diagram based on the transfer function is drawn as Fig. 6.5 shows. Since the parasitic capacitance C GS is fixed for a certain switch, the driving voltage can only be adjusted by adjusting the resonant inductor L G . As can be seen from the Bode diagram, when L G and C GS resonate around the switching frequency, the amplitude of the transfer function, V G /V T , reaches the maximum value. The amplitude of driving voltage can be adjusted by changing the value of the inductor L G at certain operating frequency. VG 1+RG CGS S = VT L S CGS S 2 + RG CGS S + 1

(6.1)

Fig. 6.4 Basic sinusoidal resonant driving circuit

VT

LG VG RG VG1

RI

CGS

Magnitude (dB)

40

20

LG=72nH

0

-20

LG=180nH

LG=120nH

Phase (deg)

-40 0 -45 -90

-135 -180 7 10

Frequency (MHz)

Fig. 6.5 Effect of L S change on driving ability

8

10

SMAIN

76

6 Resonant Driving Method

The basic resonant driving circuit reduces the loss by taking advantage of the energy stored in the input capacitor, but during the resonance, the current flowing through the resistor RG and RI causes large loss. The loss PG of the basic resonant driving circuit at operating frequency f can be calculated as (6.2) shows:  PG =

√ 2 VM / 2 (RG + RI ) = 2 · (πCGS VM f )2 (RG + RI ) 1/2π f CGS

(6.2)

where V M represents the peak value of the driving waveform V G . The loss of squarewave driving method can be calculated as (6.3) shows. Pgate_hard = CGS Vg2 f

(6.3)

where V g is amplitude of the square waveform. The switch SI7454 is taken as an example, and its parasitic capacitance C GS is 520 pF. According to (6.2) and (6.3), the comparison between the loss of the two driving methods when the switching frequency f is from 0 to 60 MHz is shown in Fig. 6.6. It can be seen from the figure that the resonant driving method can effectively reduce the loss. However, as the switching frequency increases, the loss of the resonant driving circuit tends to exceed that of the square-wave driving method. It is because that the loss on RG and RI forms a proportional relationship with the f 2 ; thus, it creases faster than the 0.8 0.7 0.6

Loss (W)

0.5

Square-wave driving

0.4 0.3 0.2

Resonant driving

0.1 0

0

10

20

30 40 Frequency (MHz)

50

Fig. 6.6 Loss comparison of square-wave driving and resonant driving methods

60

6.1 Basic Resonant Driving Circuit

77

square-wave driving method. The method to reduce the loss on RG and RI will be introduced in the following content.

6.2 Resonant Driving Based on Paralleled Branch In order to reduce the loss of the basic resonant driving circuit, a method by adding a paralleled branch in the resonant driving circuit is researched. Figure 6.7 shows the equivalent circuit of the improved resonant driving circuit based on paralleled branch. The added parallel branch is composed of a resonant inductor L P and a DC blocking capacitor C P . The above branch can effectively reduce the current flowing through the voltage source and resonant inductor parasitic resistance RI , thereby reducing the loss of the driving circuit. Figure 6.8 shows a simplified AC schematic diagram of the resonant driving circuit based on parallel branch, where RLP represents the parasitic resistance of the parallel branch inductor L P and vgs represents the driving voltage of the switch. Compared with the parasitic capacitance C iss , the impedance of the gate resistance RG of the switch is negligible. The voltage across it can be expressed as: vCiss (t) = vgs_ac (t) = Vgs sin(2π f t)

Vbus

Fig. 6.7 Diagram of resonant driving circuit based on parallel branch

RI

LG

RG Ciss

LP

+ -

Fig. 6.8 Simplified AC circuit of above resonant driving circuit

(6.4)

Smain

CP

RLG iLG RVB

RG

LG vLp

LP

iLP

RLP vgs CP

iRG Ciss

78

6 Resonant Driving Method

where vgs_ac represents the AC component of the driving voltage. The current flowing through the resistor RG and its loss can be obtained from Eqs. (6.5) and (6.6): i RG (t) = i Ciss (t) = Ciss

dvCiss (t) = 2π f Vgs Ciss cos(2π f t) dt

2 PRG = I R2G RG = 2π 2 f 2 Vgs2 Ciss RG

(6.5) (6.6)

Compared with the inductance L P , the impedance of the parasitic resistance is quite small, so the voltage drop across the resistance RLP is ignored. Then, the voltage across the inductor L P can be expressed as: v L p (t) = vgs_ac (t) = Vgs sin(2π f t)

(6.7)

Then, the current flowing through inductor L P is i L p (t) =

1 LP

 v L p (t)dt = −

Vgs cos(2π f t) 2π f L P

(6.8)

Thus, the losses in the ESR of L P can be calculated. PR L P = I L2P R L P =

Vgs2 2 8π 2 f 2 Ciss

RLP

(6.9)

The current flowing through the inductor L G and bias voltage source can be obtained as i L G (t) = i RG (t) + i L P (t) = 2π f Vgs Ciss cos(2π f t) −

Vgs cos(2π f t) 2π f L P

(6.10)

Therefore, the loss at RI can be obtained from Eq. (6.11) 2 PRI = ILG RI =

2  √ Vgs 2π f Vgs Ciss − √ RI 2 2π f L P

(6.11)

Based on the above analysis, the overall loss of the driving circuit can be expressed by the sum of the above loss: PP = PRG + PR L P + PRI

(6.12)

Figure 6.9 shows the loss curve of the resonant driving circuit under different parallel inductance L P conditions. It can be seen that the loss of the improved resonant driving circuit changes with the variation of the parallel inductance. By adjusting the inductance, the loss of the improved resonant driving method can be smaller than

6.2 Resonant Driving Based on Paralleled Branch Fig. 6.9 Loss comparison between basic driving circuit and improved driving circuit

79

1.4

1.2

Losses (W)

1

PP PBasic

Critical point

0.8

0.6

94% decrement

0.4

Optimal point

0.2

0 60

80

100

120

140

160

180

200

Parallel inductor LP (nH)

that of the basic resonant driving circuit. At the optimized point where the driving loss is the smallest, the driving circuit loss can be reduced by 90%. Although the resonant driving circuit can effectively reduce the driving loss, compared with the square-wave driving method, the rising and falling edges of the driving voltage are slower, resulting in an increment of conduction loss. Therefore, under different driving voltage amplitudes and system power conditions, a detailed analysis of the overall switch loss (including the driving loss and the conduction loss) will be analyzed in Chap. 8.

6.3 Self-driven Resonant Circuit 6.3.1 Basic Self-driven Resonant Circuit According to analysis of the resonant inverter in Chap. 2, the drain–source voltage of the switch is usually in half-sinusoidal form. Thus, the self-driven characteristics may be realized by feeding back the drain–source voltage to the gate and source terminal. Figure 6.10 shows the circuit of the basic self-driven circuit. It can be seen that a series resonant inductor and a DC bias voltage source are added in driving circuits which is similar to the basic resonant driving circuit based on high-frequency oscillator. Figure 6.11 shows the voltage waveform when the bias voltage V bias is the same as switch threshold voltage V th . It can be seen that when gate voltage vgs is higher than the threshold voltage vth , the switch turns on and the drain–source voltage vds keeps zero. When gate voltage vgs is lower than the threshold voltage vth , the switch turns off and the drain–source voltage vds begins to resonate. Thus, to realize self-driven ability, the relationship between switch gate voltage vgs and switch drain–source voltage vds should satisfy the following rules:

80

6 Resonant Driving Method

MOSFET

RG LG VBias

vgs

vds

CGD CDS CGS

Fig. 6.10 Circuit of the basic self-driven circuit

v vgs

vds

Vth

tt Fig. 6.11 Waveform of switch drain–source voltage and gate voltage

(1) There should be an almost 180° phase difference between the gate voltage vgs and drain–source voltage vds . (2) The amplitude of vgs should be within the proper driving voltage range of the selected switch. The switch gate voltage can be obtained by the sum of DC component vgs_dc and AC component vgs_ac , which is represented as (6.13) shown: vgs (t) = vgs_dc + vgs_ac (t) = VBias + Vgs sin(2π f t)

(6.13)

where V gs is the amplitude of AC component and f is the operating frequency. Let voltage V bias be zero, the basic self-driven circuit can be equivalent to the feedback network shown in Fig. 6.12. The relationship between gate voltage and drain–source voltage can be represented as (6.14) shows. Because of the high-quality factor, the parasitic resistances of inductor and capacitor are neglected.

6.3 Self-driven Resonant Circuit

81

Fig. 6.12 Feedback network of the basic self-driven circuit when bias voltage is zero

CGD RG

Vgs

LG

Vds

CGS

Vgs s 2 L G CGD = 2 Vds s L G (CGS + CGD ) + s RG (CGS + CGD ) + 1

(6.14)

Based on (6.14), the Bode plot of the voltage transfer function can be obtained. Figure 6.13 shows the Bode plot with different values of resonant inductor L G . Substituting s = jω into (6.14), this equation can be represented as: Vgs −ω2 L G CGD = Vds 1 − ω2 L G (CGS + CGD ) + jω RG (CGS + CGD )

(6.15)

20

Magnitude (dB)

0

12nH 39nH

-20

72nH

-40 -60

LG decreasing

-80 -100 180

Upper limit frequency Phase (deg)

135 90 45 0 6

10

7

8

10

10

Frequency (Hz)

Fig. 6.13 Bode plots of voltage transfer function with a different resonant inductor L G

9

10

82

6 Resonant Driving Method

It can be seen that when the real part in denominator is zero, the phase at this frequency is just 90°, which is named as upper limit frequency ωmax in the following part, as shown in (6.16): ωmax = √

1 L G (CGS + CGD )

(6.16)

Figure 6.13 shows that within a certain range lower than ωmax , the phase is almost 180°, which satisfies the phase requirement of self-driven circuit. It means that the operating frequency of the self-driven circuit cannot be higher than ωmax . The parasitic capacitance C GS and C GD is determined by the switch characteristics. Thus, for a certain switch, the only way to adjust the frequency ωmax is to change the value of resonant inductor L G . Meanwhile, Fig. 6.13 shows that the magnitude can also be adjusted by changing the value of resonant inductor L G . With the decrement of resonant inductor L G , the curve moves to the right side. In the case of the same amplitude requirement, the operating frequency can be improved and vice versa. Also, the phase of voltage transfer function (6.14) can be calculated as (6.17) shows:   ω RG (CGS + CGD ) (6.17) θ = π − atan 1 − ω2 L G (CGS + CGD ) From (6.17), it can be seen that the value of RG greatly affects the phase characteristics of self-driven system. From Fig. 6.14, it can be seen that with the increment 180 0.2 1 3

Phase (deg)

135

RG increasing 90

45

0 6

10

7

10

10

8

9

10

Frequency (Hz)

Fig. 6.14 Phase curves of voltage transfer function with a different gate resistance RG

6.3 Self-driven Resonant Circuit

83

of RG , the phase drops faster. Thus, during the procedure of selecting switch, the switch with small gate resistance can operate within a wide frequency range. Assuming the amplitude of driving voltage for a certain switch is set to be within the range of [V gsmin V gsmax ]. Thus, the voltage gain of the transfer function should satisfy (6.18): K min

      Vgs   −ω2 L G CGD   ≤ K max (6.18)   = ≤ Vds   1 − ω2 L G (CGS + CGD ) + jω RG (CGS + CGD ) 

where K min equals to V gsmin /V DS and K max equals to V gsmax /V DS . Meanwhile, to achieve self-driven characteristics, the phase should satisfy (6.19):  Pmin ≤ π − atan

ω RG (CGS + CGD ) 1 − ω2 L G (CGS + CGD )

 ≤π

(6.19)

In the following analysis, the SEPIC-type high-frequency converter based on Class E inverter is taken as an example. Based on the simulation and experimental results, it can be seen that the voltage gain is usually between −30 and −15 dB, and the minimum phase value Pmin is around 175°. With above magnitude and phase limitation, Fig. 6.15 shows the zoomed-in figure of transfer function with a different LG . From Fig. 6.15, it can be seen that the operating frequency range is between the magnitude limitation f min1 and phase limitation f max2 . With decrease in L G , the minimum operating frequency f min1 and maximum operating frequency f max2 both increase. It means that the maximum operating frequency can be improved by reducing the value of L G . However, as shown in Fig. 6.15c, when the value of L G is very small, the self-driven circuit cannot operate because f min1 is higher than f max2 is in this condition. Thus, the maximum operating frequency is limited by the switch parasitic parameters. During the design procedure, the switch should be carefully selected to achieve the desired operating frequency. In the basic self-driven resonant circuit, the degree of the freedom is only one. Also, a similar problem exists that the loss on the parasitic resistance in the driving loop is as high as the resonant driving method based on oscillator.

6.3.2 Self-driven Resonant Circuit Based on Paralleled Branch Between Gate and Source To reduce loss and increase the degree of freedom, a self-driven circuit with additional parallel branch is proposed. Figure 6.16 shows the self-driven circuit with a parallel branch between switch gate and source. Here, Z represents the impedance of the branch. At the beginning, the magnitude and phase characteristics of the feedback

84

Magnitude (dB)

-15

-20

-25

fmin1

fmax1

-30 180

operating frequency range

Phase (deg)

179 178 177

fmax2

176 175

7

8

10

9

10

10

Frequency (Hz)

(a) LG =72n

Magnitude (dB)

-15

-20

-25

fmin1

fmax1

Phase (deg)

-30 180

operating frequency range

179 178 177

fmax2

176 175

7

8

10

9

10

10

Frequency (Hz)

(b) LG =39nH

Magnitude (dB)

-15

-20

-25

fmin1

fmax1

-30 180

Phase (deg)

Fig. 6.15 Zoomed Bode plots of voltage transfer function with a different inductor L G

6 Resonant Driving Method

fm in1>fmax 2

179 178 177

fmax2

176 175

7

10

8

10

Frequency (Hz)

(c) LG =12nH

9

10

6.3 Self-driven Resonant Circuit

85

RG LG VBias

Vgs

Z

Vds

CGD CDS CGS

Fig. 6.16 Self-resonant driving circuit with parallel branch between gate and source

network should also be analyzed in order to meet the requirements of self-driven circuit. As shown in Fig. 6.17, by adding a LC branch between switch gate and source, the voltage transfer function can be calculated by (6.20). Here, because of the highquality factor, the parasitic resistances of inductor and capacitor are neglected. Vgs s 4 L G CGD L P CP + s 2 L G CGD ⎞ = ⎛ Vds s 4 L G L P CP (CGS + CGD ) + s 3 RG CP (CGS + CGD )(L G + L P ) ⎝ ⎠

 + s 2 L G (CGS + CGD ) + CP (L G + L P ) + s RG (CGS + CGD ) + 1

(6.20)

Then, under different parameter conditions, the Bode plots of the structure with LC branch can be obtained as Fig. 6.18 shows. Here, C P can also play the role of a DC blocking capacitor. From Fig. 6.18, it can be seen that the Bode plot of the self-driven circuit with parallel branch between gate and source is similar to that of the basic self-driven circuit within a certain range. Such as in the shadow region, the phase is also almost 180°, which meets the requirement of self-driven circuit. Figure 6.18 also shows that there is a resonant frequency f r1 in the Bode curve. For f r1 , it is the resonant frequency Fig. 6.17 Proposed feedback network with an additional LC branch between gate and source

CGD RG CP Vgs

LG

LP

Vds CGS

86

6 Resonant Driving Method 100

Magnitude (dB)

0 -100

Self-driven circuit in this section -200

fr1

-300 -400 180

Phase (deg)

135

Basic self-driven circuit

90 45 0 -45 6

7

10

8

10

10

9

10

Frequency (Hz)

(a) LP=56 nH CP=10 nF

Magnitude (dB)

100 0 -100

Self-driven circuit in this section -200

fr1

-300 -400 180

Phase (deg)

135

Basic self-driven circuit

90 45 0 -45 6

10

8

7

10

10

9

10

Frequency (Hz)

(b) LP=56 nH CP=100 nF Fig. 6.18 Bode curves of self-driven circuit with parallel branch between gate and source

6.3 Self-driven Resonant Circuit

87

Z Rg LG VBias

Vds

CGD CDS CGS

Vgs

Fig. 6.19 Self-resonant driving circuit with parallel branch between drain and gate

of L P and C P . On this condition, the switch gate is short with source. Thus, amplitude of Bode plot is quite small. When the value of C P is large enough, the voltage of the capacitor is almost constant. Thus, within the operating frequency range, the impedance of the LC branch can be approximately equivalent to L p . Therefore, the upper limit frequency of proposed circuit can be calculated by (6.21): ωmax = 

1 =  L eq (CGS + CGD )

1  LG LP (CGS + CGD ) L G +L P

(6.21)

Based on the above analysis, it can be concluded that the self-driven circuit based on parallel branch can achieve the similar characteristics when the equivalent inductor L eq equals to the resonant inductor in basic self-driven circuit. The loss of the driving circuit can be reduced with an additional parallel branched as analyzed in Sect. 6.2.

6.3.3 Self-driven Resonant Circuit Based on Paralleled Branch Between Drain and Gate Based on the similar idea, a LC branch can also be added between the drain and gate. At the beginning, it is still necessary to test whether the voltage transfer function satisfies the requirements of self-driven circuits. To obtain the transfer function, the circuit of Fig. 6.20a can be equivalently simplified by using Y transformation, as Fig. 6.20b shows. The results of elements of the Y network can be represented as follows: Z1 =

sCGD RG Z Z RG  = sC Z + RG + 1 (sCGD ) GD (Z + RG ) + 1

(6.22)

88

6 Resonant Driving Method

Fig. 6.20 Circuits of the self-driven circuit with parallel branch between drain and gate

Z

RG Vgs

Z2

CGD

LG CGS

(a) The circuit in Δ network form

Vds

Z1

Vds

Vgs

LG

Z3 CGS

(b) The circuit in Y network form

 Z (sCGD ) Z  = Z2 = sCGD (Z + RG ) + 1 Z + RG + 1 (sCGD )  RG (sCGD ) RG  Z2 = = sC + RG ) + 1 (Z Z + RG + 1 (sCGD ) GD

(6.23)

(6.24)

 Substituting Z = s L P + 1 (sCP ) into Fig. 6.20b, the system transfer function can be obtained as (6.25) shows Vgs b6 s 6 + b5 s 5 + b4 s 4 + b3 s 3 + b2 s 2 = 6 Vds a6 s + a5 s 5 + a4 s 4 + a3 s 3 + a2 s 2 + a1 s + a0

(6.25)

where b6 = L G A2 , b5 = AN + 2 AB L G , b4 = B N + 2L G AM + L G B 2 , b3 = M N + 2L G B M, b2 = L G M 2 . a6 = L G CGS AL P CP + A2 L G , a5 = L P CP CGS E + B L G CGS L P CP + AE + AN + 2 AB L G , a4 = AL P CP + L G CS (M L P CP + A) + RG CP CGS E + B E + B N + (2 AM + B 2 )L G , a3 = B L P CP +2ECGS + B L G CGS +L P CP2 CGS RG + ACGD RG +E M +M N + 2B L G M, a2 = A + L P CP M + M L G CGS + CP CGS CGD RG2 + BC G D RG + M 2 L G , a1 = B + CGS CGD RG + CGS CP RG + MCGD RG , a0 = M. Figure 6.21 shows the Bode plots of the self-driven circuits. From Fig. 6.21, it can be seen that the Bode plot of the self-driven circuit with parallel branch between drain and gate is similar to that of the basic self-driven circuit within a certain range. It means that this kind of self-driven circuit can also meet the requirements of selfdriven circuits. Figure 6.21 also shows that there is a resonant frequency f r2 in the Bode curve. For f r2 , it is the resonant frequency of L P and C P . In this condition, the switch gate is short with drain. Thus, amplitude of Bode plot is around zero. According to these figures, the resonant frequency of L p and C p between drain and gate should be designed to be higher than the desired operating range. Thus, in the operating frequency, the parallel branch behaves as a capacitor, which means

6.3 Self-driven Resonant Circuit

89

20

fr2

Magnitude (dB)

0 -20 -40

Proposed self-driven circuit

-60 -80 180

Phase (deg)

Basic self-driven circuit 90 0 -90 -180 6

10

9

8

7

10

10

10

Frequency (Hz)

Magnitude (dB)

20

fr2

0 -20 -40

Proposed self-driven circuit

-60

Phase (deg)

-80 180

Basic self-driven circuit

90

0

-90 6

10

8

7

10

10

9

10

Frequency (Hz)

(a) LP=56 nH CP=0.1 nF

(b) LP=56 nH CP=0.01 nF

Fig. 6.21 Bode curves of self-driven circuit with parallel branch between drain and gate

the current flowing through bias voltage source will be increased. Therefore, the self-driven circuit with parallel branch between drain and gate is not conducive to improving the system efficiency.

90

6 Resonant Driving Method

6.3.4 Example of Self-driven Circuit From the preceding analysis, a 13 MHz high-frequency resonant converter with the self-driven circuit is designed and built in the laboratory. The circuit is shown in Fig. 6.22. The input voltage is 8 V, the output voltage is 5 V, and the output power is 10 W. Figure 6.23 shows the switch gate and drain–source voltage of the self-driven circuit with a branch between the drain and gate. It can be seen that the switch turns on in ZVS condition, which can reduce the switching loss in high-frequency conditions. The operating frequency is almost 13 MHz. Here, C P is designed to be 100 nF and L P is designed to be 250 nH. It can be seen the waveform of vGS is in approximate sinusoidal form, where the nonlinear characteristic of input capacitance and the high-order harmonics also affect the shape of the driving signal. Drec LF

Cs Crec vgs

LG

Vin Regular

U1

S

CF

Cout

Ls

LP CP

Fig. 6.22 High-frequency converter with self-driven circuit in Sect. 6.3.2

Proposed self-driven circuit (gate-source)

f = 13MHz

vgs(5V/div)

vds(10V/div)

Time(50ns/div) Fig. 6.23 Switch gate and drain–source voltages of the circuit

Rout

Chapter 7

Air-Core Planar Inductors and Transformers on PCB

Under multi-MHz frequency conditions, the inductances are usually within tens or hundreds of nanohenries; thus, the air-core magnetic components without magnetic core can be adopted. These components can be divided into several different categories, such as solenoid ones and planar ones. Commercial air-core inductors are usually in solenoid form which needs to occupy extra vertical space of the system. For planar inductors and transformers, the copper tracks on PCB can be used as the windings. As a result, the air-core planar magnetic components do not take extra vertical space. Thus, this chapter focuses on air-core planar inductors and transformers on PCB.

7.1 Constant Width Planar Inductors For various PCB inductors, the multiple-layer structure and single-layer structure can be adopted. Though multiple-layer structure can further reduce the area of PCB inductors, large parasitic capacitance and complex structure are the main problems of multiple-layer PCB inductors. There are no such problems in single-layer PCB inductors. Among them, the planar square spirals and the planar circular spirals are two basic and widely used winding structures. In order to determine the inductor’s structural parameters and obtain the required inductance, an effective design method should be analyzed and established, which can give an insight view and make the design procedure clear and convenient. The simplified winding structures of the circular spiral inductors and square spiral inductors are shown in Fig. 7.1a, b respectively, which are employed to simplify the derivation of the inductance with acceptable error. Here, start from the planar circular PCB inductor.

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_7

91

92

7 Air-Core Planar Inductors and Transformers on PCB

(a) circular spiral winding

(b) square spiral windings

Fig. 7.1 Structures of planar circular spirals and planar square spirals

7.1.1 Calculation of Planar Circular Inductor The total inductance of a planar circular spiral winding comprises self-inductance as well as mutual inductance. As shown in Fig. 7.1a, the circular winding is simplified as a series of concentric circles. To further simplify the structure and ensure the inductance of the equivalent model is close to the inductance of the original structure as much as possible, each circle can be equivalent to a quasi-regular octagon as depicted in Fig. 7.2. Fig. 7.2 Equivalent quasi-regular octagon structure of circular windings

l1k l2k

l2k

l2k 8k-5 (k-th turn)

8k-1 (k-th turn)

l1k

8k-7 (k-th turn)

8k-3 (k-th turn)

l1k

l2k

l1k

7.1 Constant Width Planar Inductors

93

The quasi-regular octagon belonging to the kth turn has two different edges with length of l1k and l2k , which locate alternately and intersect at 135 degrees. The perimeter of the octagon in the kth turn should be almost equal to that of the circle. Thus, l1k and l2k can be calculated as (7.1) shows. 

l1k = 0.5346[riw + (k − 0.5)w + (k − 1)d] l2k = 1.0362[riw + (k − 0.5)w + (k − 1)d]

(7.1)

where r iw is the inner radius of the circular winding, w is the width of the track, and d represents the clearance distance between adjacent turns. For the octagonal winding, the self-inductance of the planar circular spiral winding is the sum of that in the planar conductors. The exact self-inductance for a straight conductor can be calculated as (7.2) shows [1]:   L = 0.2l ln

l w+t



w+t + +U 3l

 (7.2)

where L is the inductance in nanohenries, and l, w and t are in millimeters and represent the length, the width and the thickness of the conductor, respectively. U is the frequency-correction parameter. Then, the self-inductance of a planar circular spiral winding with N-turns can be expressed as follows. L c = 0.8

      N     l1k l2k w+t w+t l1k ln + + + U + l2k ln +U w+t 3l1k w+t 3l2k k=1 (7.3)

The total mutual inductance is the sum of each mutual inductance which is inducted through the coupling between two conductors, and it can be calculated as:  Mx y (7.4) M= x= y

where M represents the mutual inductance and M xy represents the mutual inductance between conductor x and conductor y. Here, the conductor number changes from 1 to 8 N as shown in Fig. 7.2. For the purpose of reducing the mutual inductance calculation complexity, only the mutual inductance between parallel conductors and the connected conductors with a certain angle is taken into consideration. Compared with the former types of mutual inductance, the mutual inductance between conductors with other locations is extremely little; thus, they can be neglected without causing significant error [2]. As shown in Fig. 7.3), the mutual inductance between two parallel conductors

94

7 Air-Core Planar Inductors and Transformers on PCB

lx l1

conductor x

l2

θ l

conductor y

ly (b)

(a)

Fig. 7.3 Two major types of mutual inductance in windings. a Two parallel conductors. b Two connected conductors with a certain angle θ

with a different length lx and ly can be calculated as (7.5) shows, which is affected by the corresponding conductor length and the geometric mean distance (GMD) between them. ⎞ ⎡ ⎛     lx + l y ⎣ ⎝ lx + l y lx + l y 2 ⎠ + 1+ Mparallel_x y = 0.2 ln 2 2GMD 2GMD ⎤

  2GMD 2 2GMD ⎦ − 1+ + lx + l y lx + l y ⎞ ⎡ ⎛

  lx − l y ⎣ ⎝ lx − l y lx − l y 2 ⎠ − 0.2 + 1+ ln 2 2GMD 2GMD ⎤

  2GMD 2 2GMD ⎦ − 1+ + (7.5) lx − l y lx − l y where assuming lx is larger than ly . Mutual inductance is positive for parallel conductors whose currents are in the same direction and is negative for conductors whose currents are in opposite directions. According to the abovementioned expressions, the mutual inductance of parallel conductors in a planar circular spiral winding can be calculated by Mparallel =



Mparallel_x y

(7.6)

Figure 7.3b illustrates two connected conductors with a certain angle θ , and the mutual inductance of the two conductors in this condition can be calculated by (7.7).   Mθ = 0.1 cos θl1 ln

1+ 1−

l2 l1 l2 l1

+ +

l l1 l l1



l2 + ln l1

l

2

l1 l2 l1

+ +

l l1 l l1

+1 −1

 (7.7)

7.1 Constant Width Planar Inductors

95

where Mθ is in nanohenries, the unit of length is millimeters, and l is calculated by 

the law of cosines l = l12 + l22 − 2l1l2 cos θ . Then, the mutual inductance of the conductors with 135° intersection from 1 to N-turn can be obtained as follows √  N  2 0.1 M135◦ = 16 [(l1k + l2k ) ln(l1k + l2k + lk )] 2 k=1 √  N  2 − 16 0.1 (7.8) [l1k ln(l1k − l2k + lk )+l2k ln(l2k − l1k + lk )] 2 k=1 where lk can be calculated as above analyzed. Thus, the total inductances of a N-turn circular winding can be calculated by (7.9). L total_circle =L c + Mparallel + M135◦

(7.9)

7.1.2 Calculation of Planar Square Spiral Winding The inductance calculation method of square windings is similar to that of the circular windings. In the simplified model as shown in Fig. 7.1b, the mean length of edge in the kth turn can be calculated as follows lsk = 2[riw + (k − 0.5)w + (k − 1)d]

(7.10)

Thus, the expression of self-inductance in square winding is shown in (7.11). L s = 0.8

    w+t lsk + lsk ln +U w+t 3lsk k=1

N 

(7.11)

As for the mutual inductance, according to Eq. (7.7), the result of M θ can be solved and the value is zero due to θ = 90°. Meanwhile, the mutual inductance M parallel_s between parallel conductors can be solved by (7.5), and then the total inductance of the square winding can be calculated. The expression is presented in (7.12). L total_square = L s + Mparallel_s

(7.12)

In order to test the accuracy of the aforementioned inductance formulas, multiple planar square and circular spiral inductors with various parameters are designed. Meanwhile, the relationship between the winding parameters and inductance is investigated. The inductance with different structure parameters, such as the width w, the

96

7 Air-Core Planar Inductors and Transformers on PCB

clearance distance d, the turns N and the inner radius r iw , is calculated based on above formulas. Meanwhile, the 3D models corresponding to these structure parameters are established and simulated in the FEA software to verify the validity and feasibility of above analysis, and the simulation results are shown in Fig. 7.4. From inductance curves in Fig. 7.5, it can be seen that the calculating values of circular windings and square windings keep good consistency with simulation values. These results verify the correctness of the above analysis. With the increasing turn number, the inductance also increases. Also, as shown in Fig. 7.5, with the same structure parameters, the square windings own higher inductance than the circular ones. Here, the circular winding structure is taken as an example to analyze the impact of the structure parameters as Fig. 7.6 shows. The turn number N plays a remarkable role in determining its inductance. As shown in Fig. 7.6a, the ratio of inductance L

(a) circular windings

(b) square windings

Fig. 7.4 Simulation results of different winding structures by Maxwell

Fig. 7.5 Inductance curves of square and circular windings by calculation and simulation (w = 1 mm, d = 0.5 mm, r iw = 1 mm)

L/nH

theoretical L_circle theoretical L_square simulation L_circle simulation L_square

900 750 600 450 300 150 0 2

3

4

5 N

6

7

8

theoretical L_circle simulation L_circle L_circle/N^2

500

97

7

400 300

6

200

5

100 0

L_circle/nH

8 L_circle/N^2

L_circle (nH)

7.1 Constant Width Planar Inductors

4 2

3

4

N

5

6

7

8

500 400 300 200 100 0

(a) w=1mm, d=0.5mm, riw=1mm 750 L_circle/nH

theoretical value: N=8 N=6 N=4 simulation value: N=4 N=6 N=8

600 450

500

100 0 30 40 d (mil)

50

(c)w=1mm, riw=1mm

30 w (mil)

40

50

theoretical value: N=4 N=6 N=8 simulation value: N=4 N=6 N=8

L_circle (nH)

300

150

20

20

400

200

10

10

(b) d=0.5mm, riw =1mm

300

0

theoretical value: N=4 N=6 N=8 simulation value: N=4 N=6 N=8

600

10

20

30 40 riw (mil)

(d) w=1mm, d=0.5mm

Fig. 7.6 Inductance curves at different winding parameters

and N 2 forms an approximately proportional relationship with N. From Fig. 7.6b, d, it is noticed that there is also a clear proportional relationship between inductance and their width w, clearance d and inner radius r iw . Based on the above results, it can be concluded that when an inductor with certain inductance is needed, Eqs. (7.9) and (7.12) can be adopted to effectively decide the corresponding parameters. Meanwhile for high-frequency inductors, a significant property is quality factor Q. Higher Q means lower AC resistance at the same inductance, which helps to reduce the conduction loss. When the frequency increases to several MHz or tens of MHz, because of the skin and proximity effects, the current density is no longer uniform across the conductor cross section, and AC resistance cannot be calculated accurately by specific formulas. Based on the simulation results shown in Fig. 7.7, it can be seen that the circular winding structure always keeps a higher-quality factor than the square winding structure, which can help to achieve small loss and high efficiency.

7.2 Variable Width Planar Inductors To further reduce the parasitic resistance and improve quality factor of air-core inductor under multi-MHz situations, the variable width winding structure shows

Fig. 7.7 Curves of AC resistance and quality factor for circular and square windings (w = 1 mm, d = 0.5 mm, r iw = 1 mm)

7 Air-Core Planar Inductors and Transformers on PCB

Rac(mOhm) or Q@20MHz

98

400 350 300 250 200 150 Rac_square Rac_circle Q_square Q_circle

100 50 0 0

100

200

300

400

500

600

700

L (nH)

smaller resistance characteristic compared with the constant width structure. Based on this structure, an optimal structure of planar circular winding is designed to further reduce winding resistance and achieve higher-quality factor.

7.2.1 Calculation of Variable Width Winding Structure Figure 7.8 shows the simplified diagram of the planar circular winding with various track widths. In this diagram, the inner radius, outer radius and width of the kth turn are denoted as r ik , r ok and wk , respectively. The labels N, r iw , r ow and s represent turn number of the winding, inner radius of the structure, outer radius of the structure and the space between the turns, respectively. Fig. 7.8 Diagram of the variable width winding structure

7.2 Variable Width Planar Inductors

99

Fig. 7.9 Polygonal structure diagram of the winding

l1k

A B

k

l1

135°

C

current 1

D j k

E F

N

To analyze the relationship between the inductance and structural parameters, an approximate polygonal structure as aforementioned is adopted as shown in Fig. 7.9. From Fig. 7.8, the expression of width wk in the kth turn can be obtained from (7.13), where radius ratio a is defined as r ok /r ik . wk = a k−1

(a − 1)(row − riw + s) −s aN − 1

(7.13)

Once the width is determined, the inductance can be derived in the same way as Sect. 7.1, where the edges l1k and l 2k in the kth turn can be obtained by (7.1), and the self-inductance can be calculated by (7.2). As shown in Fig. 7.9, mutual inductance between parallel conductors, such as conductors A and B or C and D, can be calculated using (7.5), where l and GMD are in millimeters. The mutual inductance between conductors connected at an angle of 135°, such as conductors E and F, can be obtained according to (7.8). Based on aforementioned analysis, inductance of the windings with different structure parameters can be calculated with the help of MATLAB. As shown in Fig. 7.10, the calculation results match well with the FEA simulation results.

7.2.2 Optimal of Variable Width Winding Structure The winding resistance is also related to several parameters. One important issue is how to design the radius ratio a. Here, start from the DC resistance. Based on an intuitive hypothesis, the radius ratios r ok /r ik in a certain winding should maintain a constant value, which may help to achieve the minimum resistance. Here, two simple structures with 2 and 3 turns are tested. For the 2-turn condition, the radius ratio of first track is assumed to be a. Therefore, the inner radius of the second track can be

100

7 Air-Core Planar Inductors and Transformers on PCB

Fig. 7.10 Inductance in different structure parameter conditions

700 600

theoretical: simulation:

N=3 N=5 N=7

L/nH

500

N=3 N=5 N=7

400 300 200 100 0

2 2.5 riw/mm

1.5

1

0.5

3

3.5

4

L/nH

(a) row=8mm, s=0.2mm, t=0.072mm with various riw 500 450 400 350 300 250 200 150 100 50 0 6

theoretical: simulation:

N=3 N=5 N=7

6.5

7

N=3 N=5 N=7

7.5 8 8.5 row/mm

9

9.5 10

(b) riw=2mm, s=0.2mm, t=0.072mm with various r 450 360 L/nH

theoretical: simulation:

N=3 N=5 N=7

270

N=3 N=5 N=7

180 90 0 0.1

0.2

0.3

0.4 0.5 s/mm

0.6

0.7

(c) riw=2mm, row=8mm, t=0.072mm with various s calculated to be ar iw + s and the system resistance can be calculated as (7.14) shows. R2turn

  1 2π ρ 1  +   = t ln a ln row (ariw + s)

(7.14)

According to (7.14), the resistance is calculated as shown in Fig. 7.11. Here, r iw is chosen to be 2 mm and r ow is chosen to be 8 mm. The figure indicates that the

7.2 Variable Width Planar Inductors Fig. 7.11 Resistance under various radius ratio conditions (2 turns)

101 18 s=0.1mm s=0.2mm s=0.3mm

16

Resistance/m

14 12 10 8 6 4

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

Radius ratio

resistance reaches its minimum value when the value of a is approximately 2. Further, it can be calculated that the radius ratio of the second track is also 2 which is the same as that of first track. For the 3-turn condition, the radius ratio of the first track is assumed to be a1 and the radius ratio of the second track is assumed to be a2 . Thus, the inner radius of the third track can be calculated to be a1 a2 r iw + a2 s + s and the system resistance can be calculated as (7.15) shows. R3turn

  1 2π ρ 1 1  = + +   t ln a1 ln a2 ln row (a2 a1riw + a2 s + s)

(7.15)

According to (7.15), resistance of three turns is calculated as Fig. 7.12 shows. Here, r iw is chosen to be 2 mm and r ow is chosen to be 8 mm. It is identified that Fig. 7.12 Resistance under various radius ratio conditions (3 turns) Resistance/m

35 30 25 20 15 10 1.8 1.6

1.8 1.6

1.4

1.4

1.2

a2

1.2 1

1

a1

102

7 Air-Core Planar Inductors and Transformers on PCB

when a1 is 1.57 and a2 is 1.56, the resistance reaches its minimum value. In this condition, the radius ratio of the third track is calculated to be 1.56. It shows that a constant radius ratio can help to achieve the smallest winding resistance, which complies with the previous assumption. Based on above analysis, the radius ratio in different tracks is selected as the same value. In N-turn situation, the optimal radius ratio can be calculated by (7.16). a N + a N −1

s s s row + · · · + a2 +a − =0 riw riw riw riw

(7.16)

Usually, the effect  ofparameter s can be ignored and a can be approximately calculated by a = N row riw . The above analysis is based on the usage of a simplified structure in an ideal condition. In actual situations, a transition straight conductor is needed to connect the adjacent turns. As shown in Fig. 7.13, the corresponding angle of the straight conductor is set to be a constant value β (0 < β < π). Here, an optimal value β should be calculated to achieve the minimum winding resistance. Through integral calculation, it can be derived that the DC resistance of the arc in kth turn is Rk_(2π −β) =

(2π − β)ρ t ln a

(7.17)

where ρ is the resistivity of the conductor and t is thickness of the winding. The DC resistance of the straight conductor in kth turn can be calculated by (7.18). Fig. 7.13 Winding structure with transition straight conductor

7.2 Variable Width Planar Inductors

Rk_β

103

 ρ 1 + (a + as )2 − 2(a + as ) cos β   = t ln a+1 2

(7.18)

where as = s/r iw . Based on (7.17) and (7.18), the DC resistance of the whole winding can be calculated. Ouyang and Andersen [3] give an empirical formula for calculating highfrequency resistance of the windings caused by the skin effect, and the AC resistance is derived as    2π − β 1 + (a + as )2 − 2(a + as ) cos β ξ sinh ξ + sin ξ Nρ   · · + Rac = · 2 cosh ξ − cos ξ t ln a ln a+1 2 (7.19) √ where ξ = t π f μσ , f is the frequency of the AC current, and μ and σ are the permeability and the conductivity of the conductor, respectively. To optimize the design of β and minimize the winding resistance, the derivative of (7.19) is calculated. Setting the derivative value be zero, the extreme points are obtained as (7.20). !  ⎧  "  #  ⎪ ⎪ ln2 a+1 + ln4 a+1 − ln2 a ln2 a+1 − ln2 a (a + as )2 + ln2 a+1 ⎪ 2 2 2 2 ⎪ ⎪ ⎪ ⎪ ⎨ β1 = arccos (a + as ) ln2 a !   "  #  ⎪ ⎪ a+1 a+1 ⎪ 2 2 4 ⎪ − ln − ln a ln2 a+1 − ln2 a (a + as )2 + ln2 a+1 ln ⎪ 2 2 2 2 ⎪ ⎪ ⎩ β2 = arccos (a + as ) ln2 a

(7.20)

It can be proved that Rac reaches its minimum in β 1 and maximum in β 2 . It implies that β 1 is the best design choice. Figure 7.14 also shows the value of the resistance 115

Fig. 7.14 Curve of winding AC resistance in different β conditions

theoretical result

R ac /mΩ

110

simulation result

105 100 95 90

0 β1 0.5

1

1.5

2 β2 2.5

β/rad

3

3.5

104

7 Air-Core Planar Inductors and Transformers on PCB

Fig. 7.15 Curves of β 1 related to a and as

0.35 0.3

β1

0.25 0.2 0.15

as=0.1 as=0.2 as=0.3 as=0.4 as=0.5

0.1 0.05 0

1

1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 a

with various values of β when r iw = 2 mm, r ow = 6 mm, N = 5 and s = 0.2 mm (a = 1.1886, as = 0.1) to verify the correctness of the above analysis. From Fig. 7.14, it is evident that the winding resistance increases with increment of angle when it is between β 1 and β 2 . The resistance achieves the minimum value at β 1 which is consistent with above analysis, which agrees with simulation results. Figure 7.15 shows the curves of β 1 with different a and as . It can be seen that β 1 forms an approximately proportional relationship with a, and β 1 also increases with the increment of as . Based on the optimal a and β, the air-core inductor with the expected value and small AC resistance can be designed.

7.3 Variable Width Planar Transformer Besides inductor, in this section, a mathematical analysis and effective design method of the planar air-core transformer are presented. Three factors must be considered in designing a transformer: the turns ratio n, primary leakage inductance L r and the coupling coefficient k. Figure 7.16 shows two typical equivalent models of transLr

n: 1

L rec

Lm

Fig. 7.16 Typical equivalent models of transformers

M

L 11

L 22

np

ns

7.3 Variable Width Planar Transformer

105

formers, where L 11 and L 22 are the self-inductance, M is the mutual inductance, and np and ns are the turns of the primary and secondary windings, respectively. The relationship between the two models is presented as follows: 

L m /n Lr + Lm L m /n L rec + L m /n 2



 =

L 11 M M L 22

 (7.21)

According to (7.22), the relationship among the self-inductance, mutual inductance, turns ratio and coupling coefficient can be represented as. ⎧ 2 ⎨ L 11 /L 22 = n M ⎩k = √ L 11 L 22

(7.22)

As previously mentioned, the turn number of the primary side and secondary side significantly affects the values of self-inductance L 11 and L 22 . The value of the primary leakage inductance L r can be represented by the coupling coefficient k(L r = (1 − k)L 11 ), which can be used as resonant inductor in optimized circuit. Thus, the turns ratio and coupling coefficient play a dominant role in determining the values of its electrical parameters. Figure 7.17 shows the simplified model of a planar air-core transformer example with a two-layer structure. The symbols in the figure such as r iw , r ow , d and s represent the inner radius of the windings, outer radius of the windings, distance between the primary and secondary windings, and space between the tracks, respectively. To reduce the resistances of the windings, the abovementioned variable width winding structure is adopted in the air-core transformer. The self-inductance of the primary side winding can be approximately calculated as follows:

primary winding

riw

wp1

L11

wp2 s

row

d riw secondary winding

ws1 ws2 s

M ws4

ws3 s

row

Fig. 7.17 Simplified model of the planar transformer with two-layer structure

s

L22

106

7 Air-Core Planar Inductors and Transformers on PCB

L=

np 

  0.2Ck ln

k=1

a k−1 ·



lk

(a−1)(row −riw +s) a N −1 (a−1)(row −riw +s) −s+t a N −1

a k−1 ·

3lk

−s+t

+ 

(7.23)

+ 0.94315

where t is the copper thickness and lk is the length of a small segment of the winding conductor. C k is the circumference of the kth turn. During the calculation, lk is set as 1/8 of the circumference. In (7.23), only the self-inductance effect of the segments is considered. Additionally, there is mutual inductance effect caused by the adjacent different segments. The mutual part can be calculated using (7.24). Thus, the self-inductance can be obtained as the sum of (7.23) and (7.24). Mself =

⎧ np np ⎨ 1   

(−1) P

$ $ $ $ $lu + (−1) P lr $Cu

⎩ 10lu u=1 r =1 P=0 ' ⎤⎫ ⎡ ⎛ ⎞ ' ( $ $ ( $ ⎞2 ⎪ ⎞2 ⎛ $$ ⎛ ( ⎪ $ ⎬ ⎥⎪ ⎢ ⎜ $$lu + (−1) P lr $$ ( ⎟ ( ( $lu + (−1) P lr $ | | 2|r − r 2|r − r ( u r u r ⎢ ⎜ ⎟ ⎠ ⎟−( $⎠ + $ $⎥ + )1 + ⎝ ⎥ ⎢ln⎜ )1 + ⎝ $$ $ $ ⎦⎪ $ ⎣ ⎝ 2|ru − rr | ⎠ 2|ru − rr | P P $lu + (−1) lr $ $lu + (−1) lr $ ⎪ ⎪ ⎭ −

⎧ np np ⎨ 1   

(−1) P

$ $ $ $ $lu + (−1) P lr $Cu

⎩ 10li u=1 r =1 P=0 ' ⎤⎫ ⎡ ⎛ ⎞ ' ( $ ( $ $ ⎞2 ( ⎪ ⎞2 ⎛ ⎛ $$ ⎪ $ $ $ ⎬ ⎥⎪ ⎢ ⎜ $l ⎟ ( + (−1) P lr $ ( $lu + (−1) P lr $ ( 2(r + r 2(r + r ) ) ( u r u r ⎢ ⎜ u ⎟ ( ⎠ ⎟ − )1 + ⎝ $ $⎠ + $ $⎥ + )1 + ⎝ ⎥ ⎢ln⎜ $ $ ⎦⎪ $ $ ⎣ ⎝ 2(ru + rr ) ⎠ 2(ru + rr ) P P $lu + (−1) lr $ $lu + (−1) lr $ ⎪ ⎪ ⎭

+

 ⎛   ⎞ 2 + 2 − 2 cos (Cu − 2lu )π Cu    ⎠ 0.4Cu cos (Cu − 2lu )π Cu ln⎝     2 − 2 cos (Cu − 2lu )π Cu u=1 np 

(7.24)

With a similar method, the self-inductance of the secondary side winding can be obtained. The mutual inductance between the primary winding and secondary winding can be calculated using (7.25). Here, l i is the segment length of the primary side winding conductor, and lj is the segment length of the secondary side winding conductor. r i and r j represent the corresponding radius, respectively. ⎧ np ns ⎨ 1 1   

$ $ $li + (−1) P l j $Ci M= (−1) ⎩ 10li i=1 j=1 P=0 Q=0 ' ⎡ ⎛ ⎞⎤⎫ ( ⎞2 ⎛ ⎪ $ $ $ $ ( ⎪ P P $li + (−1) l j $ $li + (−1) l j $ ( ⎢ ⎜ ⎟⎥⎬ ( ⎢ln⎜  ⎟ ⎥ ⎠ ⎝  + 1 + ⎣ ⎝ 2 ) 2 ⎠⎦⎪   ⎪ ⎭ 2 d 2 + ri + (−1) Q r j 2 d 2 + ri + (−1) Q r j ⎧ $ $ np ns ⎨ 1 1 P $ $    P+Q+1 li + (−1) l j C i − (−1) ⎩ 10li i=1 j=1 P=0 Q=0 P+Q+1

7.3 Variable Width Planar Transformer

107

Fig. 7.18 Relationships among k, d and s

⎤⎫ ⎡' (  ⎪ ⎞2 ⎛  ⎪ (     2 2 ⎪ ⎬ ⎢( 2 d 2 + ri + (−1) Q r j 2 d 2 + ri + (−1) Q r j ⎥ ⎥ ⎢( ⎠ ⎝ $ $ $ $ − ⎥ ⎢)1 + $li + (−1) P l j $ $li + (−1) P l j $ ⎦⎪ ⎣ ⎪ ⎪ ⎭ (7.25) Using the above equations, the transformer coupling coefficient can be obtained. The curves of the coupling coefficient with variable transformer parameters are plotted in Figs. 7.18 and 7.19. As shown in Fig. 7.18, the coupling coefficient decreases with the increment of d or s. This is because the longer distance causes greater leakage of the magnetic flux. Figure 7.19a–c shows that with a certain r ow and d, the coupling coefficient reaches a peak value as the inner radius r iw increases. The larger hollow area provides a wider path for the magnetic flux and reduces flux shielding. However, it decreases the copper area and generates less magnetic flux. When r iw is small, the hollow area is dominant, which leads to the increment of the coupling coefficient with a larger r iw . After k reaches its peak value, the copper area plays a leading role and k starts to decrease with the increment of r iw . The above analysis of the planar air-core transformer parameters indicates that the transformer can be effectively designed according to mathematical analysis and the equations. Finally, within a small range, it can be tuned using the FEA software to achieve more precise properties. Above design method can be used to design the air-core transformer of isolated converter in Sect. 5.3.

108

7 Air-Core Planar Inductors and Transformers on PCB

Fig. 7.19 Relationships among k, r iw , r ow and d

0.7

0.6

k

0.5

0.4 row=3mm row=6mm row=9mm row=12mm row=15mm

0.3

0.2 0.15

0

2

4

6 8 riw / mm

10

12

14

(a) d=1.6mm 0.7

0.6

k

0.5

0.4

row=3mm row=6mm row=9mm row=12mm row=15mm

0.3

0.2

0

2

4

6 8 riw / mm

10

12

14

(b) d=1.3mm 0.75 0.7

k

0.6

0.5 row=3mm row=6mm row=9mm row=12mm row=15mm

0.4

0.3

0

2

4

6 8 riw / mm

(c) d=1.0mm

10

12

14

References

109

References 1. Grover FW (1962) Inductance calculations. Van Nostrand, Princeton, 1946, reprinted by, Dover, New York, 1962 2. yGreenhouse HM (1974) Design of planar rectangular microelectronic inductors. IEEE Trans Parts Hybrids Packag 10(2):101–1094 3. Ouyang Z, Andersen MAE (2014) Overview of planar magnetic technology—fundamental properties. IEEE Trans Power Electron 29(9):4888–4900

Chapter 8

Passive and Active Components in Multi-MHz Converter

When operating frequency comes to multi-MHz, there are some different characteristics for both passive and active components, especially for magnetic components, switches and diodes. Besides the air-core PCB magnetic components in Chap. 7, a more general description of multi-MHz magnetic components is presented in this chapter. The switches and diodes characteristics under multi-MHz frequency are also introduced.

8.1 Multi-MHz Magnetic Components The magnetic components, such as inductor and transformer, take a large part of the volume of power converters. In general, the value of inductors and transformers forms an inverse proportional relationship with the operating frequency. However, the volumes do not reduce continuously with the increment of operating frequency because the loss, heat dissipation and temperature rising must be taken into consideration. Thus, the small volume and low profile magnetic components are deeply researched in multi-MHz conditions. To reduce the magnetic core loss, many high-performance magnetic materials are developed. Taking the product of Ferroxcube as an example, the characteristics of magnetic materials suitable for different frequencies are shown in Table 8.1. The magnetic permeability of magnetic materials decreases rapidly with the increment of the operating frequency. The materials such as 3F4, 3F5 and 4F1 are suitable for working at multi-MHz frequencies. The suitable operating frequency range of high-frequency magnetic material keeps improving. Besides the normal magnetic core structure, to reduce the profile, PCB magnetic components based on magnetic sheet can also be used. Based on the very thin magnetic sheet, the profile of the magnetic components can achieve the similar value of the capacitors and even lower. Table 8.2 shows some available magnetic sheet. Also, nano-granular thin-film magnetic material can also be used which can be deposited on both sides and on beveled cuts to form a fully linked closed core. © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_8

111

112

8 Passive and Active Components in Multi-MHz Converter

Table 8.1 Characteristics list of high-frequency magnetic materials Type

Frequency (MHz)

μi (25 °C)

Bsat (mT) (25 °C)

Material

3F4

1–2

900

≈410

MnZn

3F45

1–2

900

≈420

MnZn

3F5

2–4

650

≈380

MnZn

4F1

4–10

80

≈320

NiZn

Type

Permeability

Manufacturer

EFF

130

KEMET

EFX

100

KEMET

IFL12

180

TDK

IFL16

220

TDK

Table 8.2 Typical magnetic sheet

Also, under multi-MHz situations, the low temperature co-fired ceramic (LTCC) technology is beginning to be adopted, which can help to achieve a 3D integration system. LTCC materials have the same temperature expansion coefficient with silicon (Si), so hybrid integration could be realized through semiconductor wire bonding. Besides advantages stated above, high-thermal conductivity metal or ceramic substrates (e.g., AlN) could be co-fired together with LTCC tapes, helping to dissipate heat generated by power loss. To reduce core loss, air-core magnetic components have been widely adopted in multi-MHz conditions. There are different winding structures for air-core magnetic components, such as spiral, solenoid and toroidal. Compare with cored components, air-core components usually need more turn number to achieve same inductance. For different winding structures, planar spiral winding structure takes a large area, toroidal air-core structure and solenoid air-core structure can achieve a certain inductance within a quite smaller area compared with spiral geometry, which helps to achieve high power density. However, there are many vias which cause certain loss. Thus, the spiral winding structure is still the mostly used one, where the windings can be in circular, square, racetrack and many other shapes. For air-core inductor, the parasitic capacitance is expected to be reduced in order to improve the self-resonant frequency, which helps to broaden the operating range of the air-core inductor. The parasitic capacitance is even larger in the multi-layer structure, where the faced copper in different layers will cause large parasitic capacitance. Also, some 3D printed air-core inductors with different shaped are proposed to achieve low weight. Thus, for choosing multi-MHz magnetic components, there should be a trade-off between the cored structure and air-core structure in terms of magnetic loss, copper loss, volume and magnetic shielding requirement.

8.2 Multi-MHz Active Devices

113

8.2 Multi-MHz Active Devices Under multi-MHz situations, it is also very important to choose proper active devices, such as switches and diodes. The performance of Si devices keeps improved. Also, with fast development of material and manufacturing process, GaN and SiC devices have been widely adopted in multi-MHz resonant converters. Especially for GaN devices, it has been widely adopted in low-power and low-voltage situations. However, for these devices, how to compare the device performance and choose proper devices is very important to improve system efficiency. Figures of Merit (FOM) is an important factor to describe the loss performance of power devices. For multi-MHz devices, the FOM under hard-switching situations is similar as traditional one, which can be represented by (8.1): FOM = (Q GD + Q GS2 )Rds(on)

(8.1)

The equation shows that the device loss in hard-switching condition is mainly caused by turn-on loss and conduction loss. The power loss forms a proportional relationship with square root of FOM. Also, the part of turn-on loss is affected by parasitic components related with the transition time. However, for resonant soft-switching condition under multi-MHz, the output capacitance C OSS usually affects the output capacitor discharging time in order to change the effective conduction time of the switch. Especially for the half bridge structure, the large output capacitance will length the deadtime, which increases the RMS current value. Thus, the FOM under soft-switching situation can be defined as (8.2) shows. FOM = (Q G + Q OSS )Rds(on)

(8.2)

The equation shows that the output capacitance charge is also taken into consideration. With the increment of system current and power, the conduction loss would occupy the most important part. With the increment of switch voltage, the output charge QOSS will also increase, and this loss will play the important part of the total device loss. In general, GaN FETs usually can achieve a 2–2.5 times reduction in FOM than the Si MOSFETs. With above FOM, the preliminary selection of high-performance switch under high-frequency resonant soft-switching situations can be determined. With several certain devices, the loss can be calculated in detail. Here, we take the single-switch resonant DC--DC converter for example. For the soft-switching characteristics, ignoring the switching loss, only the conduction loss is taken into consideration as (8.3) shown. 2 · RDS, on PS = Irms

(8.3)

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8 Passive and Active Components in Multi-MHz Converter

where I rms is the RMS value of switch current and RDS, on is the on-resistance of the switch. The resonant driving method can take advantage of the energy stored in switch input capacitance, which greatly reduces the loss in the driving circuit. The loss of the basic resonant driving circuit can be approximately calculated by 2 Vgs2 Pgate = 2Rg π 2 f 2 Ciss

(8.4)

where Rg represents the switch gate resistance, C iss represents the switch input capacitance, and V gs is the amplitude of the driving voltage. It can be seen that the driving circuit loss forms a proportional relationship with the gate resistance and input capacitance. Though the resonant driving method can reduce the driving loss by taking advantage of the input capacitance energy, the rising and falling edges of driving voltage change slowly which increases the conduction loss. To analyze the conduction loss under resonant driving circuit, Fig. 8.1 shows the resonant driving waveform. At t 1 , the driving voltage reaches the threshold voltage vth and the switch turns on. At t 2 , the driving voltage reaches the critical voltage vcv , then the switch is fully turned on. As shown in the switch datasheets, when the driving voltage is between the threshold voltage and critical voltage, the switch on-resistance is in a high value condition. When the driving voltage is higher than the critical voltage, the switch on-resistance significantly reduces and also remains constant. Compared with the square-wave driving method, the transition time between threshold voltage and critical voltage is longer in resonant driving method. Here, the switch average current within time t 1 –t 4 is defined as I avg , on-resistance between transition times t 1 –t 2 and t 3 –t 4 is defined as Rtra , and on-resistance between fully turned-on time t 2 –t 3 is defined as Ron . The period is represented by T. The switch conduction loss of the square-wave driving method can be approximately calculated as (8.5): 2 Ron Pon_square = Iavg

(t4 − t1 ) T

(8.5)

Fig. 8.1 Diagram of the resonant driving voltage waveform

Vcv Vth VDC

t1 t2

t3 t4

t

8.2 Multi-MHz Active Devices

115

The switch conduction loss of the resonant driving method can be approximately calculated as: 2 Pon_resonant = Iavg Rtra

2(t2 − t1 ) 2 (t3 − t2 ) +Iavg Ron T T

(8.6)

Switch SI7454 is taken as an example, and the peak value of square-wave driving voltage and resonant driving voltage are both 5 V. According to datasheet, the threshold voltage is 3 V, and the critical voltage is 4 V, Rtra is about 150 m and Ron is about 30 m. Under 20 MHz condition, the sum of switch conduction loss and driving loss under different switch average current conditions is shown in Fig. 8.2. It can be seen that there is a cross point for these two driving methods. It can be concluded that when system current and system power are small, resonant driving method is conducive to improving system efficiency. On the other hand, when system is in high current and power condition, the square-wave driving method should be adopted. Figure 8.3 shows the curve under 30 MHz condition, it can be seen that the current amplitude of cross point increases. It means that the resonant driving circuit is suitable to be applied under higher frequency conditions. For GaN FET, another characteristic needed to be payed attention is the dynamic resistance, which has been studied and reported recently. The dynamic resistance means that the on-resistance after immediately turn-on is significantly higher than its normal DC resistance value, which can be approximately highlighted by the shadow in Fig. 8.4. 2 square waveform driving method resonant driving method

Conduction loss + Switching loss (W)

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0

0

1

2

3 4 5 Switch average current (A)

6

Fig. 8.2 Conduction and driving loss with two driving methods (20 MHz)

7

8

116

8 Passive and Active Components in Multi-MHz Converter 2 square waveform driving method resonant driving method

Conduction loss + Switching loss (W)

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0

0

1

2

3 4 5 Switch average current (A)

6

7

8

Fig. 8.3 Conduction and driving loss with two driving methods (30 MHz)

Fig. 8.4 Diagram of the resonant driving voltage waveform

Dynamic resistance region

Vcv Vth VDC

t1 t2

t3 t4

t

Dynamic resistance of GaN FETs is a serious problem which causes high conduction loss than expected. Besides this dynamic resistance problem, another unexpected loss is off state loss, by the experimental testing results shown in [1], the measured off state loss is significantly higher than the predicted value. The loss is unaccounted for by the manufacturer provided SPICE model when these devices are used at such high frequency. Under ideal soft-switching condition, the output capacitor resonates with inductor without loss. Thus, the loss can be seen as the output capacitance loss at high-frequency operating situation. Based on above analysis, the switch under high-frequency situation can be modeled as Fig. 8.5 shows.

8.2 Multi-MHz Active Devices

117

D

Fig. 8.5 Simplified switch model in a lumped form

IDISP

ICOND ROSS

RISS CISS

RDS-ON

G

COSS

S

Figure 8.5 illustrates the simplified switch model in a lumped form, which consists of the parasitic capacitances and resistances. Here, RDS-ON , ROSS and RISS represent the parasitic resistances in the switch, RDS-ON can be adjusted to take the dynamic resistance into consideration. C ISS and C OSS represent the input capacitance and output capacitance, respectively. It should be pointed out that in multi-MHz condition, Ross varies under different temperature or voltage conditions. With the lumped switch model, the switching loss and conduction loss can be analyzed, and their relationship with operating frequency can be investigated. The conduction loss is mostly dependent on duty cycle, and the corresponding current and is independent of operating frequency. However, the loss caused by RG and ROSS is affected by the operating frequency. It is noteworthy that smaller input and output capacitance can also help to reduce the corresponding loss, which forms a proportional relationship with the square of output capacitance. The total loss can be approximately calculated by (8.7)  2 2 Vgs2 + Irms × RDS, on + Ploss = 2Rg π 2 f 2 Ciss

IDISP Coss + Cext

2 2 Coss Ross

(8.7)

Similar phenomenon also exists for the Si and SiC Schottky diode, experimental results in [2] and [3] show that under multi-MHz high-frequency situations, there are unexpected loss and significant de-rating for Schottky diode. The unexpected loss and significant de-rating are even more serious under high dv/dt situation. Based on above analysis, we can see that under multi-MHz situations, the operating characteristics may be different from that under low-frequency situations. And there are unexpected loss and device de-rating phenomenon, which may be caused by dynamic on-resistance, junction capacitance, especially at high-frequency and high-voltage situations. Thus, the loss mechanism should be further investigated. When selecting devices, comparison of device loss should be conducted at specific situations.

118

8 Passive and Active Components in Multi-MHz Converter

8.3 Testing Method The increasing operating frequency brings more stringent requirements on the accuracy and response speed of the measurement system. Under multi-MHz situations, active devices require good measurement technology, as well as good techniques to capture details of high-speed waveforms. The following content will discuss the measurement methods of multi-MHz waveforms. The bandwidth of the combination of oscilloscope and probe can be calculated by (8.8): BW−3 dB = 

1 1 BW2−3 dB, Scope

+

1

(8.8)

BW2−3 dB, Probe

where BW-3 dB , BW-3dB, Scope , BW-3Db, Probe are bandwidths corresponding to the measurement system, oscilloscope and probe, respectively. In general, take Tek’s products for example, the bandwidth of oscilloscope is 300 MHz–3.3 GHz, while the bandwidth of probe is 50 MHz –1 GHz. The bandwidth of the probe plays an important role in the performance of the measurement system. In general, the higher the measurement frequency f r is, the less accurate the captured waveform is. In this case, the measurement system is acting like a low-pass filter, attenuating the high frequency content. Narrow bandwidth would prolong the rise and fall time of waveforms, the relationship between system bandwidth and the rise or fall time can be calculated from (8.9). trise(10−90%) ≈

0.35 BW−3 dB

(8.9)

The 0.35 value is for oscilloscopes with Gaussian frequency response. The value may be different for oscilloscopes with difference frequency response profiles and can vary between 0.35 and 0.45. The parasitic inductance in the testing loop interacts with the probe input capacitance causing rings at a certain frequency, as (8.10) shows. f ring =



1

2π L loop Cprobe

(8.10)

The inductance increases with its length, which leads to the decrement of ringing frequency and low-frequency oscillation in the waveform, which greatly affect the accuracy of measurement. Therefore, it is important to minimize the effects of the probe’s input capacitance and loop length. The measurement point should be as close to the power device as possible to reduce the loop inductance.

References

119

References 1. Surakitbovorn K, Davila JR (2017) Evaluation of GaN transistor losses at MHz frequencies in soft switching converters. In: 2017 IEEE 18th workshop on control and modeling for power electronics (COMPEL). Stanford, CA, 1–6 2. Santiago-González JA, Elbaggari KM, Afridi KK et al (2015) Design of class E resonant rectifiers and diode evaluation for VHF power conversion. IEEE Trans Power Electron 30(9):4960–4972 3. Raymond LC, Liang W, Rivas JM (2014) Performance evaluation of diodes in 27.12 MHz Class-D resonant rectifiers under high voltage and high slew rate conditions. In: 2014 IEEE 15th workshop on control and modeling for power electronics (COMPEL), 1–9

Chapter 9

Flexible Multi-MHz DC-DC Converter

With development of advanced material, flexible power electronic systems are gradually needed in PV, lighting and other wearable applications. Multi-MHz power converters can greatly reduce the volume and profile, which is suitable for the flexible application. In this Chapter, a flexible DC-DC converter for OLED application is analyzed.

9.1 Flexible Planar Air-Core Inductor In a flexible converter, the bendable inductor is a very important part, and this section analyzes the inductance variation situation. A circular spiral coil with an inner diameter of R1 , an outer diameter of RN and a number of turns of N is taken as an example. The line width is w, the line spacing is d, and the copper thickness is δ. When the coil is bent along the x-axis with a bending angle θ, the projection of the coil on the xy plane and the yz plane is shown in Fig. 9.1. For the convenience of analysis, as shown in Fig. 9.1, the coil is divided into two parts along the x-axis. The ith turn conductor in the area where x > 0 is expressed as i+ , and the ith turn conductor in the area where x < 0 is expressed as i- . Then, the coordinates of each conductor segment can be expressed as: ⎤ ⎡  ⎧ 2 ⎪  y ⎪ ⎪ ⎪ i + (x, y, z) = ⎣ Ai 1 − , y, M 2 − y 2 − M cos θ 2⎦ y ∈ [−Bi , Bi ] ⎪ ⎪ Bi ⎨ ⎤ ⎡  2 ⎪ ⎪  ⎪ y ⎪ θ ⎦ 2 2 ⎣ ⎪ ⎪ ⎩ i − (x, y, z) = Ai 1 − Bi , −y, − M − y + M cos 2 y ∈ [−Bi , Bi ] (9.1)

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 D. Xu et al., Multi-MHz High Frequency Resonant DC-DC Power Converter, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-15-7424-5_9

121

122

9 Flexible Multi-MHz DC-DC Converter

z

10

2r

z

2RN 5

y RN/θ

0

B

i-

10

i+

A

0

x

-10

-10

θ

-5

5

0

10

y

Fig. 9.1 Bending view of the planar spiral coil

Among them, M, Ai , Bi are intermediate variables which are represented by (9.2), and RN is the radius of the outermost coil. ⎧ 2R N ⎪ ⎪ M= ⎪ ⎪ θ ⎨ Ai = ri ⎪ ⎪ ⎪ ri θ 2R N ⎪ ⎩ Bi = sin θ 2R N

(9.2)

According to (9.1), the partial derivative of the coordinates can be obtained as: ⎡ ⎤ ⎧ ⎪ ⎪ ⎪ ⎥ ⎪ ∂i + (x, y, z) ⎢ −y ⎪ ⎢ −Ai  y ⎥ y ∈ [−Bi , Bi ] ⎪  = , 1, ⎪ 2 ⎣  2 ⎪ 2 − y2 ⎦ ∂y Bi ⎪ M ⎪ y ⎪ 1 − Bi ⎨ ⎤ ⎡ ⎪ ⎪ ⎪ ⎪ ⎥ ⎪ ∂i (x, y, z) ⎢ −Ai y y ⎪ ⎥ y ∈ [−Bi , Bi ] ⎪ − =⎢ , −1,   ⎪ 2 ⎦ ⎣ ⎪   2 2 2 ∂ y B ⎪ M − y i ⎪ ⎩ 1 − Byi

(9.3)

Equation (9.4) shows the method of calculating the inductance according to Neumann’s formula and Rosa’s equation.

9.1 Flexible Planar Air-Core Inductor

L=

⎧ N N  ⎪ ⎪ μ ⎪ ⎪ ⎪ ⎪ ⎨ 4π i=1 j=1



123



dl · dl j  i  li − l j 

(i = j)

(9.4)

  N N  ⎪  ⎪ 0.2235(α + β) 2l ⎪ i ⎪ ⎪ + 0.5 + (10−6 ) (i = j) 2li log ⎪ ⎩ α + β l i i=1 j=1

Substituting the coordinate vector in (9.1) and partial derivative in (9.3) into (9.4), the mutual inductance between the ith and jth conductors can be expressed as (9.5) shows. ⎧ −B −B ⎪ i j ⎪ μ ⎪ L = dy f 1 (y1 , y2 )dy2 ⎪ 1 j−) (i+, 4π ⎪ ⎪ Bi Bj ⎪ ⎪ ⎪ −B ⎪ −B i j ⎪ ⎪ μ ⎨ L (i+, j+) = 4π dy1 f 2 (y1 , y2 )dy2 (i = j) (9.5) Bi Bj   ⎪ ⎪ y1 y1 −B i ⎪    ⎪ μ ⎪ L (i+, j+) = 4π dy1 f 2 (y1 , y2 )dy2 + f 2 (y1 , y2 )dy2 ⎪ ⎪ ⎪ Bi Bj ⎪ ⎪   Bj ⎪   ⎪ ⎩ +2πri log 2πri + 0.5 + 0.2235(w+δ) (10)−6 (i = j) w+δ πri In (9.5), intermediate functions f 1 (y1 , y2 ) and f 2 (y1 , y2 ) are used to simplify the calculation, and their expressions are as (9.6) shows. ⎧ ⎪ ⎪ ⎪ ⎪ ⎪ f 1 (y1 , y2 ) = ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ f 2 (y1 , y2 ) = ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎩

Ai A j Bi B j

⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣

⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣

√

y1 y2 Bi2 −y12 · B 2j −y22

−1+ √

√

y1 y2 M 2 −y12 · M 2 −y22

⎤ 21 

2  Ai A j 2⎥ 2 2 2 2 Bi − y1 − B j − y2 + (y1 − y2 ) ⎥ ⎥ Bi B j ⎥

2  ⎥  ⎥ ⎦ + M 2 − y12 − M 2 − y22 Ai A j Bi B j

⎡

√



√

√

y1 y2 Bi2 −y12 · B 2j −y22

+1− √

√

y1 y2 M 2 −y12 · M 2 −y22

2

(9.6) ⎤ 21

 Ai A j Bi2 − y12 − B 2j − y22 + (y1 − y2 )2 ⎥ ⎥ ⎥ Bi B j ⎥

2  ⎥  ⎥ ⎦ 2 2 + M 2 − y1 − M 2 − y2

Then, the self-inductance of the N-turns coils can be solved as follows. L coil =

N  N  i=1 j=1

L (i+, j+) + L (i+, j−)

!

(9.7)

124

9 Flexible Multi-MHz DC-DC Converter

0.56 Inductance [μH]

Fig. 9.2 Relationship between coil bending angle and inductance value

0.54 0.52 0.5 Calculate Measure

0.48 0.46

0

50 100 Bending angle θ [°]

150

According to the above analysis and derivation, the coil inductance can be calculated by MATLAB. The comparison between the measurement and calculation of the inductance value is shown in Fig. 9.2, where the bending angle θ is shown as the angle in Fig. 9.1.

9.2 Design of Matching Network For a bendable DC/DC converter, the most important task is to eliminate the influence of the inductance variation in the matching network, which is mainly reflected in the impedance angle. The T-type matching network is adopted in this converter, and the circuit is shown in Fig. 9.3. According to Kirchhoff’s voltage and current law, the voltage and current can be expressed as (9.8): ⎧ ⎪ ⎨ u L = i L · Z 1 + (i L − i R ) · Z 3 u L = iL · Z1 + i R · Z2 + u R ⎪ ⎩ uR = iR · ZR

(9.8)

The simplified output to input voltage ratio can be obtained from (9.9): Fig. 9.3 Circuit of T-matching network

+

uL

iL

Z1

Z2 Z3

-

iR + uR ZR -

9.2 Design of Matching Network

125

⎧ uR Z3 ⎪ ⎪ ⎨ G = u = (Z Z + Z Z + Z Z ) Z + (Z + Z ) L 1 2 2 3 1 3 R 1 3 ⎪ ⎪ ⎩ Z L = u L = (Z 1 Z 2 + Z 2 Z 3 + Z 1 Z 3 ) + (Z 1 + Z 3 )Z R iL Z2 + Z3 + Z R

(9.9)

Additionally, the impedance angle of the matching network can be expressed as: tan ϕ L =

(Z 1 + Z 3 )Z 2R − (Z 1 Z 2 + Z 2 Z 3 + Z 1 Z 3 )(Z 2 + Z 3 ) Z 32 Z R

(9.10)

As analyzed by the above section when the coil is bent, its inductance decreases accordingly. The design principle of the matching network is to ensure that its input side impedance is purely resistive or weakly inductive when the inductance is changed. In this way, the inverter stage can work in the soft-switching state. First, under normal conditions (the inductor is not bent), the input side impedance of the matching network should be purely resistive, that is, tanϕ L = 0, then according to (9.10), Z 1 can be expressed as: Z1 =

(Z 2 + Z 3 )Z 2 Z 3 − Z 2R Z 3 −(Z 2 + Z 3 )2 + Z 2R

(9.11)

To simplify the analysis and calculation, let Z 2 = -mZ 3 , Z1 can be expressed as: ⎧ 3 2 ⎪ ⎨ Z 1 = (1 − m)m Z 3 + Z R Z 3 (1 − m)2 Z 32 − Z 2R ⎪ ⎩ Z 2 = −m Z 3

(9.12)

Substituting (9.12) into (9.9), the ratio of output voltage to input voltage G = U R /U L is only related to m, Z 3 and Z R . That is:  G=

Z 2R − (m − 1)2 Z 32 Z3

(9.13)

Then, the expression of Z 3 can be obtained from (9.14). Z3 = 

j ZR G 2 − (m − 1)2

1−G