MT6631 GNSS L1+L5 RF Design Application [1.1 ed.]

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GNSS L1+L5 RF Design Application

Revision History Version

Date

V1.0

2020.03.20

Initial release

Jerome Shiu

V1.1

2020.04.27

Update the Co-TMS check list table

Jerome Shiu

CONFIDENTIAL A

Description

Author

Outlines 1. GNSS L1+L5 Introduction 2. GNSS L1+L5 RF Design Guidelines 2.1 GNSS L1 and L5 PCB Design and Hardware Checklist 2.2 GNSS L1 and L5 RF Design Guidelines 2.3 Co-existence Solution of GNSS and RF

3. GNSS Co-clock Design Guidelines

CONFIDENTIAL A

1. GNSS L1+L5 INTRODUCTION

CONFIDENTIAL A

GNSS Frequency Allocation & L1+L5 Improvement  L1 + L5 Dual Frequency – GPS L5, Galileo E5a, Beidou3 B2a  10x bandwidth  10x code rate  ionospheric delay compensation

– L1+L5 Improvement:

GPS L1

GPS L5

Center Freq. (MHz)

1575.42

1176.45

Band-width (MHz)

2

20

Code Length

1023

10230

Modulation

BPSK(1)

BPSK(10)

Data

Data + Pilot

Signal Component

 Accuracy  Multipath mitigation  Band diversity for blocker avoidance

L5 band

L1 Slow Code Rate: The constructive interference for a reflected ray 150m delayed direct path 150 m

300 m

B2a B2b

L5 High Code Rate: For L5 signal, there is no interference for relative delay > 60m CONFIDENTIAL A

30 m

L1 band

True L5 – Support Beidou B2A L5 constellation from Spirent

 Currently, only MTK HW can supports B2A  In China, with B2A, we have more L1+L5 satellites than other dual frequency GNSS receivers Average visible L5 Satellite numbers in Beijing

40 20

L5 with B2A

L5 without B2A GPS L5

CONFIDENTIAL A

Beidou B2A

GPS L5-Band Benefit - Urban (5m/s) for Multipath Evaluation  Multipath Mitigation – Improves accuracy (more resistant to long delay reflections due to 10x higher chipping rate)

33.7 m

Golden path Position by using L1 signals, error ~33.7 meter Position by using L5 signals, error ~1.0 meter

Note: The scenario is created by the L1/L5 simulator with 5 SVs that have multipath at 0.25 L1 C/A chip with 0.01Hz Doppler difference on 3dB lower reflected path.

CONFIDENTIAL A

Urban Field Trial – L5 Antenna Efficiency Comparison (L1 30% vs L5 20% & 10%) At least 6 SVs and CNR 18dB-Hz of L5-band signal could ensure improvement on urban field trial from L5 benefits. GPS L5-Band Antenna Average Efficiency

L5-Band SV Number >6 Rate in Critical Route

20%

91.54%

10%

74.64%

Whole Route

SV Number

35 30 25 20

Critical Route

15 10

5

Get ~17% L5 signal available rate by improving antenna efficiency from 10% to 20%.

0 790000

890000

L1天線效益30%

Critical Route (Urban case)

Critical Route

990000

1090000

L5 天線效益20%

1190000

L5 天線效益10%

SV Number

35 30 25 20 15 10 5 0 960000

L5 no benefit 970000

980000

L1天線效益30%

990000 1000000 1010000 1020000 1030000 L5 天線效益20% 2020/4/29

L5 天線效益10% 7

Field Trial Performance Comparison of GPS L1 and L5 L1 with multipath exclusion : 25m L1+L5 with multipath exclusion : 9m

L1 with multipath exclusion : 17m L1+L5 with multipath exclusion : 6m

Note: GPS L1 and L5 antennas average efficiency are 30%. The multipath exclusion is MTK GPS position algorithm.

2. GNSS L1+L5 RF DESIGN GUIDELINES

CONFIDENTIAL A

2.1 GNSS L1 AND L5 PCB DESIGN AND HARDWARE CHECKLIST

CONFIDENTIAL A

Copyright © MediaTek Inc. All rights reserved.

2020/4/29

10

GNSS L1 and L5 PCB Design Checklist Item

Description

Pass/Fail

Please use the multi-plexer+pre-SAW filter, external GNSS LNA, and post-SAW for RF/GPS co-existence. Do RF traces impedance control, well-shielding, and good isolation from noisy source for all GNSS traces and components. Schematic and layout

Place eLNA as close to the GNSS antenna as possible, and minimize RF loss between the antenna and LNA input. GNSS I/Q traces must have solid GND shielding. Place all decoupling capacitors close to IC power input and enable pins. Place post-SAW filter and chip input matching close to GNSS chip input. Do the well thermal and mechanical stress isolation for crystal and PMIC DCXO.

Crystal and clock buffer

All crystal traces should be protected with ground, and do impedance control for RF clock buffer traces. Keep all baseband and RF clock/data/power/TX control traces and vias with well-shielding, and keep it far away from GNSS RF and antennas and PCB edge.

De-sense

Separate GNSS RF, cellular RF, and baseband components in different shielding cases. Reserve the decoupling capacitors position in data and clock pin of noisy sources. CONFIDENTIAL A

Copyright © MediaTek Inc. All rights reserved.

2020/4/29

11

GNSS L1/L5 Hardware Performance Minimum Requirement Test Item Test Spec. Note Conductive CNR Conductive L1/L5 CNR @-130dBm Static in room temperature Extreme TMS Compensated Clock Drift Rate WiFi Max. Power RF Max. Power

≧40.5 for TMO AGPS, ATT AGPS, A-BD certification, and high performance application Flight mode and LCM on -> GPS fix 30 sec. -> Start measuring clock drift ≦2.5 ppb/s rate 10 min. -> Record Max. clock drift rate Test flow: GPS fix -> Temp. chamber for GPS learning -> GPS restart -> ≦10 ppb/s (5~50oC) Temp. chamber for GPS test -> Record Max. clock drift rate ≦20 ppb/s (50oC)Temp. chamber setting: 25->-20->55->25oC, and Temp. rate: 1~3°C/min

≧39.5 dB-Hz

GPS fix 30 sec. -> Start measuring clock drift rate -> wait 20 sec. -> Turn on PA 10sec. -> Turn off PA -> Record Max. clock drift rate

≦10 ppb/s

GPS fix 30 sec. -> Start measuring clock drift rate -> Play 3D -> Record Max. clock drift rate Use a golden phone to check chamber loss, and let LCM be turned on.

Play 3D Wireless CNR @-130dBm

L1/L5 CNR (θ=0/45/60o)

≧39 dB-Hz

L1-band total efficiency ≧30% Antenna L5-band total efficiency ≧20% Pattern Uniform LCM on (L1/L5-band) ≦1 dB Wireless deRF Tx Max. Power (L1/L5-band)≦1 dB sense Play 3D (L1/L5-band) ≦3 dB GPS L1 B13/14 L-C notch filter -> band-pass filter -> LNA -> GNSS chip  GPS L1 antenna: antenna Isolation > 15dB between B13/14 TX and GPS L1 RX  B13/14 notch filter + BPF: attenuation > 65dB in B13/14 band, and loss < 1.5dB in GPS L1 band  LNA: B13/14 2nd harmonic < - 42dBm in GPS L1 band (Pin = -25dBm at 787/788 MHz), and LNA gain < 0dB in B13/14 band LTE B13/14 TX RF front-end:  Transceiver -> PA -> Duplexer -> Low-pass filter -> TXM (or ASM) -> RF antenna  PA: B13/14 2nd harmonic < -13dBm (Pout=27dBm, 10MHz, FRB)  Duplexer + Low-pass filter: attenuation >75dB in GPS L1 band  TXM (or ASM): B13/14 2nd harmonic 1

Units Note

f1 = 1575 MHz dBm f2 = f1 +/-1 MHz Input power = -30 dBm f1 = 824.6 MHz dBm f2 = 2400 MHz Input power = -25 dBm f1 = 1712.7 MHz dBm f2 = 1850 MHz Input power = -20 dBm fin = 787/788 MHz Pin = -25 dBm dBm f2H = 1574/1576 MHz (NF Max. can loose to 1.3dB) uS off->on and on->off f = 20 MHz ... 10 GHz

Copyright © MediaTek Inc. All rights reserved.

2020-04-29

24

GNSS L5 Band LNA Spec. Parameter Operating temperature Frequency Supply voltage Vcc Supply current (ON) Supply current (OFF) Power On voltage (ON) Gain Noise figure Impedance (in/out) Input return loss |S11| Output return loss |S22| Reverse isolation Inband input 1dBcompression point

GNSS L5 Band LNA Spec. Min. Typ. Max. -40 85 1164 1189 1.5 1.8/2.8 3.6 7 5 0.8 14 16 18 -15 1 50 10 10 20

-15

Inband input 3rd-order intercept point

-5

Out-of-band input 2ndorder intercept point

-40

Out-of-band input 3rdorder intercept point

-4

Settling time Stability

CONFIDENTIAL A

°C MHz V mA Vcc 1.8V must meet this spec. uA V dB GPS L5 band dB > 5GHz dB ohm dB dB dB

dBm f = 1176 MHz

10 >1

Units Note

f1 = 1176 MHz dBm f2 = f1 +/-1 MHz Input power = -30 dBm f1 = 824.6 MHz dBm f2 = 2400 MHz Input power = -25 dBm f1 = 1785 MHz dBm f2 = 2401 MHz Input power = -25 dBm uS off->on and on->off f = 20 MHz ... 10 GHz

Copyright © MediaTek Inc. All rights reserved.

2020-04-29

25

Co-existence Test Setup GNSS Ant.

antenna isolation

DUT

RF Ant.



GNSS simulator or Signal generator

Power divider

Attenuator

Power divider

Base station simulator

CNR de-sense and jamming scan test: 1. 2. 3. 4. 5. 6.

Let GNSS Ant. receive -130dBm signal by adjusting power level of “GNSS simulator” to do CNR de-sense test or “signal generator” to do jamming scan test. Adjust “Attenuator” to let total RF loss equal to antenna isolation (>10dB normally). Record the baseline (flight mode) CNR or jamming scan result. Let “DUT” transmit Max. power each band that DUT supported by “base station simulator”. Record this CNR or jamming scan result and compare it with baseline results. Please refer the appendix for more AGPS hardware performance minimum requirement.

CONFIDENTIAL B

3. GNSS CO-CLOCK DESIGN GUIDELINES

CONFIDENTIAL B

Placement and Layout Guidelines 

Design Concept – –



Keep crystal and traces far away noise source(Buck, NCP, Class-D… or other toggling signals), and stress area. This section is for thermal impact reduction and clock calibration for crystal. Please reserve enough area for crystal routing and keep-out region. The clock stability is very important for RF performance.

Placement 1.

2. 3.



Keep the crystal and PMIC DCXO area far away from the heat sources and stress area: 1. Keep crystal > 10mm away from the ~0.8W heat sources (i.e., RF and WiFi PAs 1Tx, RF transceiver 2Tx, or other high thermal components), and > 20mm away from the ~1.6W heat sources (i.e., RF and WiFi PAs 2Tx, or other high thermal components). 2. Keep crystal away from heat sources: >15mm for AP, >10mm for DDR, > 5mm for wide width > 0.5mm traces, > 4mm for PMIC, >10mm for 1A charger, and > 20mm from 2A charger. 3. Suggest to keep PMIC DCXO area >10mm away from any heat sources. 4. The crystal and PMIC DCXO placement rules are the same as above description for placing the heat sources on the backside. 5. Keep-out at least the first two inner layers and > 0.25mm away from the surrounding metal for all crystal components . 6. Place the crystal and traces inside the shielding case, and keep > 20 mm away from any have mechanical force area to avoid PCB deformation risk such as PCB edge, USB, headphones, vibrators, screw hole and huge component (opposite side). Please use the TIM (thermal interface material) between PMIC and shielding case metal for reducing the thermal transient, and other heat sources also can use TIM for it. Place DCXO LDO capacitors close to PMIC ball within 1mm such as VXO22, and VRFCK.

Layout 1. 2.

3. 4.

5.

For thermal consideration, do not connect crystal and PMIC DCXO GND to main GND directly, use AVSS18_AUXADC island as crystal reference GND, decrease the GND via number surrounding the crystal area, and minimum width traces (≤ 3 mil) to do all crystal routing. Recommend to place the crystal and PMIC into one shielding case, and route all traces on the TOP layer for clock stability consideration. The XTAL1 and XTAL2 traces routing should be smoothly and directly, and outside of the crystal. Besides, the traces length are 4.4~10.0mm and the length difference 2 times trace width), and traces impedance should be continuous. Make sure AUXADC signal traces with well-ground shielding by GND or AVSS18_AUXADC for precise temperature measurement, and keep all crystal routing away from high-speed and power traces. Clock output buffer traces are often sensitivity and noisy, so routing these traces in inner layer is a good choice for avoiding any unwanted coupling. And, keep away from RF traces for avoiding de-sense. CONFIDENTIAL B

PMIC Co-TMS Layout Recommendation

CONFIDENTIAL B

Co-TMS Placement Recommendation Check List Table Distance Suggestion (units: mm)

TMS

Note

DCXO

>4

H

Sub PMIC for CPU

> 15

L

> 10

Sub PMIC for GPU and cellular RF

> 10

L

> 10

WiFi IC 1Tx

> 10

H

> 10

WiFi IC 2Tx

> 20

M

> 10

Cellular RF PA 1Tx

> 10

H

> 10

Cellular RF PA 2Tx

> 20

M

> 10

Cellular RF Transceiver 1Tx

>5

H

>5

Cellular RF Transceiver 2Tx

> 10

M

> 10

AP

> 15

M

> 10

DDR

> 10

M

> 10

Charger 1A

> 10

M

Charger 2A

> 20

L

>5

H

PCB edge, and screws

> 20

L

USB, headphones, and vibrators

> 20

H

Other Suggestion

PCB

Keep-out TMS layers XO1/XO2 traces: length 4.4~10mm and Diff. buck pins to DCXO pins •

Risk

Main PMIC

Wide width > 0.5mm traces

•

Priority

Priority

≥2

H

Y

H

Y

L

It can adjust the speed of charging current for reducing the thermal impact in the beginning

> 10 > 10

It need to confirm no any PCB deformation or bending risk around TMS and TMS traces area Risk

Note Use TMS GND island on 3rd layer The XTAL1 and XTAL2 traces mutual capacitance should be