Introduction to LabVIEW, FPGA for RF, Radar and Electronic Warfare Applications

Table of contents :
Introduction to LabVIEW™ FPGA for RF, Radar, and Electronic\rWarfare Applications......Page p0002.djvu
Preface......Page p0012.djvu
Acknowledgments......Page p0016.djvu
1.1 What Is an FPGA?......Page p0020.djvu
1.2 History of FPGAs......Page p0021.djvu
1.3 Selecting an FPGA......Page p0022.djvu
1.3.1 Build Your Own Board Approach......Page p0023.djvu
1.3.3 Selecting FPGA Pros and Cons......Page p0024.djvu
1.4.1 LabVIEW FPGA Hardware......Page p0025.djvu
1.4.2 LabVIEW FPGA Math and Logic......Page p0026.djvu
1.5 The Development Process......Page p0028.djvu
1.5.1 Risk Analysis......Page p0030.djvu
1.5.4 Source Code Control......Page p0031.djvu
1.5.5 Bug and Task Tracking......Page p0032.djvu
1.5.6 Document Management......Page p0033.djvu
1.5.8 Technical Debt......Page p0034.djvu
1.5.9 Laboratory Information Management System......Page p0035.djvu
1.6 Book Overview......Page p0036.djvu
1.6.5 Chapter 6: Looking Ahead......Page p0037.djvu
References......Page p0038.djvu
Chapter 2\rHow to Learn LabVIEW FPGA......Page p0042.djvu
2.1 Learning LabVIEW FPGA Versus VHDL/Verilog......Page p0043.djvu
2.2 Preconceived Notions......Page p0044.djvu
2.4.1 Have a Problem to Solve......Page p0046.djvu
2.4.3 Software Engineering......Page p0048.djvu
2.4.5 FPGA Knowledge......Page p0049.djvu
2.5.1 Existing LabVIEW Developer......Page p0050.djvu
2.5.2 Non-LabVIEW Software Developer......Page p0051.djvu
2.5.3 VHDL/Verilog Developer......Page p0052.djvu
2.5.6 Management......Page p0053.djvu
References......Page p0054.djvu
3.1 Introduction......Page p0058.djvu
3.2.2 Earlier FPGAs......Page p0059.djvu
3.2.4 The Specialization of FPGAs......Page p0060.djvu
3.3.1 Electronics Kit Analogy......Page p0062.djvu
3.3.4 I/O......Page p0064.djvu
3.3.6 Math on an FPGA......Page p0065.djvu
3.4 Benefits of FPGAs......Page p0066.djvu
3.4.2 Low Latency......Page p0067.djvu
3.5 Industries and Applications......Page p0068.djvu
3.6.2 CPUs......Page p0072.djvu
3.6.3 GPUs......Page p0074.djvu
References......Page p0075.djvu
4.1 Overview......Page p0080.djvu
4.2 A Systems Engineering Approach......Page p0081.djvu
4.2.1 Development Models......Page p0082.djvu
4.2.2 Requirements Gathering......Page p0083.djvu
4.2.3 Design......Page p0084.djvu
4.2.5 Risk Analysis......Page p0086.djvu
4.3 Generic LabVIEW FPGA Systems View......Page p0087.djvu
4.4 LabVIEW Environment......Page p0088.djvu
4.4.1 Setting Up LabVIEW......Page p0089.djvu
4.4.2 LabVIEW File Types......Page p0090.djvu
4.4.3 Example Finder......Page p0093.djvu
4.4.5 Tools >> Options......Page p0095.djvu
4.4.7 LabVIEW Bookmarks......Page p0096.djvu
4.4.9 Reentrancy in LabVIEW VIs......Page p0097.djvu
4.4.12 Object-Oriented Design in LabVIEW......Page p0098.djvu
4.5.1 Host to or from the FPGA......Page p0099.djvu
4.5.3 P2P Configurations......Page p0112.djvu
4.5.4 MGT Configurations......Page p0113.djvu
4.5.5 Disk Interfacing......Page p0114.djvu
4.5.6 Interfacing to Many FPGA Cards......Page p0116.djvu
4.6 Inside the FPGA......Page p0118.djvu
4.6.1 To and From the FPGA......Page p0119.djvu
4.6.2 Inside the FPGA......Page p0131.djvu
4.7 Simulating the Design......Page p0148.djvu
4.7.1 Simulation Modes......Page p0149.djvu
4.7.3 Simulation Summary......Page p0151.djvu
4.8.1 Compiling an FPGA......Page p0152.djvu
4.8.2 LabVIEW FPGA Compile Steps......Page p0153.djvu
4.8.3 Xilinx Compile Tools......Page p0154.djvu
4.8.5 Compilation Hardware Considerations......Page p0155.djvu
4.8.7 Multiple Compiles of the Same FPGA VI......Page p0156.djvu
4.8.8 Compile Failures......Page p0157.djvu
4.8.9 Periodic Compile Checks......Page p0160.djvu
4.9.1 Streaming......Page p0161.djvu
4.9.3 Interactive Front Panel Communication......Page p0162.djvu
4.10.2 LabVIEW FPGA IP Export......Page p0163.djvu
4.11 Summary......Page p0164.djvu
References......Page p0165.djvu
5.1 Overview......Page p0170.djvu
5.2 Problem Definition......Page p0171.djvu
5.3 NI Platform ......Page p0172.djvu
5.4 Common NI FPGA Architectures......Page p0176.djvu
5.4.1 Summary......Page p0178.djvu
5.5 Components of an RF Test System......Page p0179.djvu
5.5.1 Front End......Page p0180.djvu
5.5.2 FPGA DSP......Page p0184.djvu
5.5.4 Storage......Page p0193.djvu
5.6.1 NI VST......Page p0194.djvu
5.6.2 RTSA......Page p0204.djvu
5.6.3 Multichannel Phased Array Systems......Page p0210.djvu
References......Page p0214.djvu
6.1 FPGA Overlays......Page p0218.djvu
6.1.1 NI VST as an FPGA Overlay......Page p0219.djvu
6.1.2 Xilinx PYNQ......Page p0220.djvu
6.2 SoC Architectures......Page p0221.djvu
6.3 FPGA Platforms......Page p0222.djvu
6.4 RISC-V......Page p0223.djvu
6.6 How to Stay Current......Page p0224.djvu
6.6.1 Publications and Online Resources......Page p0226.djvu
References......Page p0227.djvu
LabVIEW High Performance FPGA Developer’s Guide......Page p0230.djvu
NI Center of Excellence......Page p0231.djvu
NI Training......Page p0232.djvu
RF, EW, and Radar Books......Page p0233.djvu
Management Books......Page p0234.djvu
Online Videos......Page p0235.djvu
Online RF, Radar, and EW Resources......Page p0236.djvu
Summary......Page p0237.djvu
About the Author......Page p0238.djvu
Index......Page p0240.djvu