Intel® Virtualization Technology FlexMigration Application Note

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Intel® Virtualization Technology FlexMigration Application Note This document is intended only for VMM or hypervisor software developers and not for application developers or end-customers. Readers are expected to be knowledgeable about Intel® Architecture and Intel® Virtualization Technology.

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INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION I NFORMATI ON I N THI S DOCUMENT I S PROVI DED I N CONNECTI ON WI TH I NTEL PRODUCTS. NO LI CENSE, EXPRESS OR I MPLI ED, BY ESTOPPEL OR OTHERWI SE, TO ANY I NTELLECTUAL PROPERTY RI GHTS I S GRANTED BY THI S DOCUMENT. EXCEPT AS PROVI DED I N I NTEL'S TERMS AND CONDI TI ONS OF SALE FOR SUCH PRODUCTS, I NTEL ASSUMES NO LI ABI LI TY WHATSOEVER AND I NTEL DI SCLAI MS ANY EXPRESS OR I MPLI ED WARRANTY, RELATI NG TO SALE AND/ OR USE OF I NTEL PRODUCTS I NCLUDI NG LI ABI LI TY OR WARRANTI ES RELATI NG TO FI TNESS FOR A PARTI CULAR PURPOSE, MERCHANTABI LI TY, OR I NFRI NGEMENT OF ANY PATENT, COPYRI GHT OR OTHER I NTELLECTUAL PROPERTY RI GHT. A " Mission Cr it ical Applicat ion" is any applicat ion in w hich failure of t he I nt el Pr oduct could r esult , dir ect ly or indirect ly, in per sonal inj ur y or deat h. SHOULD YOU PURCHASE OR USE I NTEL'S PRODUCTS FOR ANY SUCH MI SSI ON CRI TI CAL APPLI CATI ON, YOU SHALL I NDEMNI FY AND HOLD I NTEL AND I TS SUBSI DI ARI ES, SUBCONTRACTORS AND AFFI LI ATES, AND THE DI RECTORS, OFFI CERS, AND EMPLOYEES OF EACH, HARMLESS AGAI NST ALL CLAI MS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARI SI NG OUT OF, DI RECTLY OR I NDI RECTLY, ANY CLAI M OF PRODUCT LI ABI LI TY, PERSONAL I NJURY, OR DEATH ARI SI NG I N ANY WAY OUT OF SUCH MI SSI ON CRI TI CAL APPLI CATI ON, WHETHER OR NOT I NTEL OR I TS SUBCONTRACTOR WAS NEGLI GENT I N THE DESI GN, MANUFACTURE, OR WARNI NG OF THE I NTEL PRODUCT OR ANY OF I TS PARTS. I nt el m ay m ake changes t o specificat ions and pr oduct descript ions at any t im e, w it hout not ice. Designer s m ust not r ely on t he absence or charact er ist ics of any feat ur es or inst r uct ions m arked " r eserved" or " undefined" . I nt el r eserves t hese for fut ur e definit ion and shall have no responsibilit y w hat soever for conflict s or incom pat ibilit ies ar ising fr om fut ure changes t o t hem . The inform at ion her e is subj ect t o change w it hout not ice. Do not finalize a design w it h t his inform at ion. The product s descr ibed in t his docum ent m ay cont ain design defect s or er r or s k now n as er rat a w hich m ay cause t he pr oduct t o dev iat e fr om published specificat ions. Cur r ent charact er ized er rat a ar e available on r equest . Cont act your local I nt el sales office or your dist ribut or t o obt ain t he lat est specificat ions and befor e placing your pr oduct or der. Copies of docum ent s w hich have an order num ber and ar e r efer enced in t his docum ent , or ot her I nt el lit erat ur e, m ay be obt ained by calling 1- 800- 548- 4725, or go t o: ht t p: / / www.int el.com / design/ lit erat ure.ht m % 20 I nt el ® 64 ar chit ect ur e r equir es a sy st em w it h a 64- bit enabled pr ocessor, chipset , BI OS and soft war e. Per form ance w ill vary depending on t he specific har dware and soft war e you use. Consult your PC m anufact urer for m or e inform at ion. For m or e inform at ion, v isit ht t p: / / w w w.int el.com / info/ em 64t I nt el® Vir t ualizat ion Technology requir es a com put er sy st em w it h an enabled I nt el® pr ocessor, BI OS, and v ir t ual m achine m onit or ( VMM) . Funct ionalit y, perform ance or ot her benefit s w ill vary depending on har dwar e and soft war e configurat ions. Soft ware applicat ions m ay not be com pat ible w it h all operat ing sy st em s. Consult your PC m anufact ur er. For m or e inform at ion, v isit ht t p: / / w w w.int el.com / go/ v ir t ualizat ion I nt el and t he I nt el logo ar e t radem ar k s of I nt el Cor porat ion in t he U.S. and/ or ot her count r ies. * Ot her nam es and brands m ay be claim ed as t he pr oper t y of ot her s.

Copy r ight © 2010- 2012 I nt el Corporat ion. All right s r eser ved.

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CHAPTER 1 INTRODUCTION 1.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 CHAPTER 2 INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION AND CPUID VIRTUALIZATION 2.1 CPUID VIRTUALIZATION AND A LIVE-MIGRATION COMPATIBILITY POOL. . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION FOR VMS THAT OPERATE IN VMX NON-ROOT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION FOR VMS THAT DO NOT OPERATE IN VMX NONROOT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3.1 CPUID Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3.1.1 Virtualization of CPUID Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.2 CPUID Faulting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4 EXAMPLE USE OF INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION . . . . . . . . . . . . . . . . . . . . . . 2-9 FIGURES Figure 2-1. Figure 2-2.

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Feature Information Returned by CPUID.01H.ECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Feature Information Returned by CPUID.01H.EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

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CHAPTER 1 INTRODUCTION 1.1

OVERVIEW ®

I nt e l Vir t u a liz a t ion Te ch n ology ( I nt e l ® VT) refers t o a suit e of hardware assist s in I nt el silicon ( t he processors, chipset s and net working devices) t hat m ake virt ualizat ion soft ware sim pler and robust and enable it t o deliver bet t er perform ance. I nt e l® Vir t ua liza t ion Te ch nology Fle x M igr a t ion ( I nt e l® V T Fle x M igr a t ion) is a part of I nt el VT t hat allows a vir t u a l- m a chin e m on it or ( VM M ) t o report a consist ent set of available processor feat ures t o guest soft ware running in a vir t ua l m a ch in e ( VM ) , t hereby broadening t he live- m igrat ion com pat ibilit y pool across generat ions of I nt el ® processors. The event ual live- m igrat ion solut ion built across servers using different generat ions of I nt el processors is defined by t he VMM vendor and validat ed by t he VMM provider. I nt el prim arily provides t he hardware hooks t o enable t he VMM vendors t o im plem ent such a solut ion. Hence I nt el VT FlexMigrat ion, com bined wit h support from a virt ualizat ion- soft ware provider, allows I T t o m axim ize flexibilit y across a single pool of virt ualizat ion resources using m ult iple generat ions of I nt el server product s.

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CHAPTER 2 INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION AND CPUID VIRTUALIZATION Soft ware discovers t he processor ident ificat ion and feat ure inform at ion using t he CPUI D inst ruct ion. I nt el VT FlexMigrat ion is an um brella t erm t hat refers t o processor feat ures t hat allow a VMM t o vir t ua lize t he CPUI D inst ruct ion. That is, t hese feat ures give a VMM cont rol over t he values report ed by CPUI D t o guest soft ware running in a VM.

2.1

CPUID VIRTUALIZATION AND A LIVE-MIGRATION COMPATIBILITY POOL

Wit hout CPUI D virt ualizat ion, a VMM m ay be challenged in it s abilit y t o support a live- m igrat ion com pat ibilit y pool t hat includes processors t hat support different feat ures. Suppose, for exam ple, t hat such a pool cont ains processor P1, which support s feat ure X, and processor P2, which does not . I f guest soft ware begins operat ing in a VM running on processor P1, t he CPUI D inst ruct ion will report feat ure X ( which is support ed on processor P1) . I f t he VM is lat er m igrat ed t o processor P2, guest soft ware will not operat e correct ly if it at t em pt s t o use feat ure X ( which is not support ed on processor P2) . A VMM can avoid t his problem wit h appropriat e CPUI D virt ualizat ion. Specifically, a VMM can virt ualize t he CPUI D inst ruct ion so as not t o report any feat ure t hat is not support ed by every processor in t he live- m igrat ion com pat ibilit y pool. I n t he exam ple above, t he VMM would virt ualize t he execut ion of CPUI D on processor P1 so as n ot t o report feat ure X. ( I t would do so, despit e t he fact t hat processor P1 does support feat ure X, because processor P2 does not .) As a result , guest soft ware will not at t em pt t o use feat ure X and will t hus cont inue t o operat e correct ly aft er being m igrat ed t o processor P2. Support for a live- m igrat ion com pat ibilit y pool does not require arbit rary CPUI D virt ualizat ion. As not ed in t he previous paragraph, it is sufficient t o conceal feat ures t hat are not support ed by all processors in t he live- m igrat ion com pat ibilit y pool. I t is not necessary change t he report ing of ot her processor capabilit ies ( e.g., cache sizes) . I nt el VT FlexMigrat ion provides feat ures t hat enable CPUI D virt ualizat ion so as t o support a live- m igrat ion com pat ibilit y pool t hat includes processors t hat support different feat ures. I t includes feat ures bot h for VMs t hat operat e in VMX non- root operat ion and t hose t hat do not . 1 I nt el VT FlexMigrat ion support s CPUI D - in du ce d 1. VMX non-root operation is a feature of Intel VT for Intel® 64 and IA-32 Architectures (Intel® VT-x).

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VM e x it s for VMs t hat operat e in VMX non- root operat ion. On cert ain processors, I nt el VT FlexMigrat ion m ay support eit her of t wo ot her feat ures for VMs t hat do not operat e in VMX non- root operat ion: CPUI D m a sk ing and CPUI D fa ult ing. VMM providers can claim support of I nt el VT FlexMigrat ion if at least one of t hese feat ures is enabled t o im plem ent a cross- generat ion live- m igrat ion capabilit y.

2.2

INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION FOR VMS THAT OPERATE IN VMX NON-ROOT OPERATION

VM X n on - r oot ope r a t ion is a feat ure of I nt el VT for I nt el ® 64 and I A- 32 Archit ect ures ( I nt el ® VT- x) . VMs t hat are support ed by I nt el VT-x operat e in VMX non- root operat ion. I nt el VT- x is defined so t hat any execut ion of t he CPUI D inst ruct ion in VMX non- root operat ion causes a t ransit ion t o t he VMM. These t ransit ions are called CPUI D - in du ce d VM e x it s. The CPUI D inst ruct ion report s processor ident ificat ion and feat ure inform at ion t o soft ware by ret urning values in t he regist ers EAX, EBX, ECX, and EDX. A VMM handling CPUI D- induced VM exit s can em ulat e execut ion of t he CPUI D inst ruct ion by placing what ever values it chooses in t hose regist ers. When t he VMM ret urns cont rol t o t he VM, it will appear t o guest soft ware t hat t he CPUI D inst ruct ion ret urned t he values t hat were chosen by t he VMM. Because every execut ion of t he CPUI D inst ruct ion in VMX non- root operat ion causes a VM exit , and because t he VMM m ay put any values it want s in t he regist ers EAX, EBX, ECX, and EDX, a VMM has com plet e cont rol over execut ion of t he CPUI D inst ruct ion in any VM support ed by I nt el VT- x. I f t he VMM is support ing a live- m igrat ion com pat ibilit y pool, it can em ulat e t he CPUI D inst ruct ion in such VMs so as not t o report any feat ure t hat is not support ed by every processor in t he live- m igrat ion com pat ibilit y pool. As explained in Sect ion 2.1, t his approach support s correct guest operat ion even aft er live m igrat ion. CPUI D- induced VM exit s are an int egral part of I nt el VT-x and are an archit ect urally com m it t ed feat ure. They are and will be support ed on all I nt el processors t hat support I nt el VT- x. CPUI D- induced VM exit s are docum ent ed in I nt el ® 64 and I A- 32 Archit ect ures Soft ware Developer’s Manual ( SDM) in Volum e 3B, Chapt er “ VMX Non- Root Operat ion”, Sect ion “ I nst ruct ions That Cause VM Exit s Uncondit ionally”. This volum e m ay be downloaded at http://download.intel.com/design/processor/manuals/253669.pdf .

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INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION FOR VMS THAT DO NOT OPERATE IN VMX NON-ROOT OPERATION

A VMM m ight choose not t o use I nt el VT- x for som e or all of it s VMs. I t m ight inst ead support t hem using soft ware t echniques based on binary t ranslat ion or paravirt ual-

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izat ion. ( Such t echniques can also be used for VMs t hat are support ed by I nt el VT- x.) Because such VMs do not run in VMX non- root operat ion, t he VMM cannot use CPUI D- induced VM exit s t o em ulat e execut ions of t he CPUI D inst ruct ion in t hose VMs. To com pensat e for t his, cert ain I nt el processors support CPUI D m a sk ing, described in Sect ion 2.3.1. More recent processors m ay inst ead support CPUI D fa u lt in g, described in Sect ion 2.3.2.

2.3.1

CPUID Masking

CPUI D m asking is a hardware assist t hat enables such VMMs t o im plem ent a cross- generat ion live- m igrat ion capabilit y on plat form s based on support ing processors. Unlike CPUI D- induced VM exit s, CPUI D m asking does not give a VMM com plet e cont rol over guest execut ions of t he CPUI D inst ruct ion. I t does, however, allow part ial virt ualizat ion of t he CPUI D inst ruct ion so as t o prevent report ing any feat ure t hat is not support ed by every processor in t he live- m igrat ion com pat ibilit y pool. As not ed in Sect ion 2.1, t his abilit y is required t o im plem ent a cross- generat ion live- m igrat ion capabilit y. The CPUI D inst ruct ion report s inform at ion t o soft ware using a set of CPUI D fun ct ion s. Each funct ion report s four ( 4) 32- bit values, and t hese are report ed in t he regist ers EAX, EBX, ECX, and EDX. The value in t he EAX regist er at t he t im e t he CPUI D inst ruct ion is execut ed det erm ines t he funct ion t hat t he inst ruct ion report s. 1 The not at ion CPUI D.nn: reg refers t o t he value ret urned in regist er reg by CPUI D funct ion nn. For exam ple, CPUI D.01H: EDX is t he value t hat t he CPUI D inst ruct ion places in t he regist er EDX when t he regist er EAX cont ained t he value 01H at t he t im e t he inst ruct ion was execut ed. CPUI D funct ion 0DH report s inform at ion using m ult iple sub- funct ions t hat are select ed by t he value of ECX. The not at ion CPUI D.( EAX= 0DH,ECX= nn) : reg refers t o t he value ret urned in regist er reg by sub- funct ion nn of CPUI D funct ion 0DH. The CPUI D inst ruct ion ret urns inform at ion about I SA feat ures in t he following values: CPUI D.01H: ECX, CPUI D.01H: EDX, CPUI D.( EAX= 0DH,ECX= 01H) : EAX, CPUI D.80000001H: ECX, and CPUI D.80000001H: EDX. ( Not all of t he processors t hat support CPUI D m asking use all of t hese CPUI D funct ions.) Furt her det ails about t he CPUI D inst ruct ion are given in I nt el ® 64 and I A- 32 Archit ect ures Soft ware Developer’s Manual ( SDM) in Volum e 2A, Chapt er “ I nst ruct ion Set Reference, A- M”, Sect ion “ I nst ruct ions ( A- M) ”. This volum e m ay be downloaded at http://download.intel.com/design/processor/manuals/253666.pdf . As exam ples, Figure 2- 1 ident ifies t he feat ures report ed by CPUI D.01H: ECX, and Figure 2- 2 does t he sam e for CPUI D.01H: EDX. 1. For some CPUID functions, the ECX register at the time the CPUID instruction is executed selects a sub-function, determining with the EAX value the values returned in EAX, EBX, ECX, and EDX. There is no CPUID masking for such functions and, for that reason, the remainder of this document does not consider CPUID sub-functions.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4

3 2 1

0

ECX 0 AVX OSXSAVE XSAVE AES POPCNT MOVBE x2APIC SSE4_2 — SSE4.2 SSE4_1 — SSE4.1 DCA — Direct Cache Access PDCM — Perf/Debug Capability MSR xTPR Update Control CMPXCHG16B FMA — Fused Multiply Add CNXT-ID — L1 Context ID SSSE3 — SSSE3 Extensions TM2 — Thermal Monitor 2 EST — Enhanced Intel SpeedStep® Technology SMX — Safer Mode Extensions VMX — Virtual Machine Extensions DS-CPL — CPL Qualified Debug Store MONITOR — MONITOR/MWAIT DTES64 — 64-bit DS Area PCLMULQDQ — Carryless Multiplication SSE3 — SSE3 Extensions Reserved

OM16524b

Figure 2-1. Feature Information Returned by CPUID.01H:ECX CPUI D m asking allows VMM soft ware t o prevent t he processor from report ing select ed feat ures in t he values CPUI D.01H: ECX, CPUI D.01H: EDX, CPUI D.( EAX= 0DH,ECX= 1H) : EAX, CPUI D.80000001H: ECX, and CPUI D.80000001H: EDX. VMM soft ware cont rols CPUI D m asking by program m ing t he m odel- specific regist ers ( MSRs) . Specifically, t here are t hree CPUI D - m a sk ing M SRs:

•

CPUI D1_FEATURE_MASK MSR. This MSR is support ed by all processors t hat support CPUI D m asking. I t s cont ent s affect t he values report ed by CPUI D funct ion 01H: — The value loaded int o ECX is t he logical-AND of t he value t hat would norm ally be report ed for CPUI D.01H: ECX and bit s 31: 0 of t his MSR. — The value loaded int o EDX is t he logical-AND of t he value t hat would norm ally be report ed for CPUI D.01H: EDX and bit s 63: 32 of t his MSR.

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Figure 2-2. Feature Information Returned by CPUID.01H:EDX All processors t hat support CPUI D m asking support CPUI D1_FEATURE_MASK MSR.

•

CPUI DD_01_FEATURE_MASK MSR. This MSR is support ed by som e but not all processors t hat support CPUI D m asking. I t s cont ent s affect t he values report ed by sub- funct ion 01H: — The value loaded int o EAX is t he logical- AND of t he value t hat would norm ally be report ed for CPUI D.( EAX= 0DH,ECX= 01H) : EAX and bit s 31: 0 of t his MSR.

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— Bit s 63: 32 of t his MSR are reserved and soft ware should not change it s init ial value.

•

CPUI D80000001_FEATURE_MASK MSR. This MSR is support ed by som e but not all processors t hat support CPUI D m asking. I t s cont ent s affect t he values report ed by CPUI D funct ion 80000001H: — The value loaded int o ECX is t he logical-AND of t he value t hat would norm ally be report ed for CPUI D.80000001H: ECX and bit s 31: 0 of t his MSR. — The value loaded int o EDX is t he logical-AND of t he value t hat would norm ally be report ed for CPUI D.80000001H: EDX and bit s 63: 32 of t his MSR.

( The locat ions of t he CPUI D- m asking MSRs are m odel- specific; t hey are provided lat er for specific processors.) CPUI D m asking does not give VMM soft ware full cont rol over CPUI D virt ualizat ion. While it allows a VMM t o prevent t he processor from report ing a feat ure t hat is support ed by t he processor, it does not allow a VMM t o cause t he processor t o report a feat ure t hat is not support ed by t he processor. I n addit ion, a VMM cannot use CPUI D m asking t o prevent t he processor from report ing nat ive hardware capabilit ies t hat are report ed in ot her CPUI D funct ions ( e.g., cache sizes) . Even wit h t hese lim it at ions, CPUI D m asking provides t he capabilit y ident ified in Sect ion 2.1 as required t o im plem ent a cross- generat ion live- m igrat ion capabilit y. Soft ware can ident ify support for CPUI D m asking by consult ing CPUI D.01H: EAX, which report s t he following version inform at ion: ( 1) ext ended fam ily I D in bit s 27: 20; ( 2) fam ily I D in bit s 11: 8; ( 3) ext ended m odel I D in bit s 19: 16; ( 4) m odel in bit s 7: 4; and ( 5) st epping I D in bit s 3: 0. CPUI D m asking is support ed only on processors t hat report an ext ended fam ily I D of 00H and a fam ily I D of 6H. Those processors support CPUI D m asking as follows:

•

Ext ended m odel I D 1H and m odels 7H and DH ( for all values of st epping I D) : — These processors support t he CPUI D1_FEATURE_MASK MSR at MSR address 478H. I t s init ial value is FFFFFFFF_FFFFFFFFH, m asking no feat ures. — These processors do not support t he CPUI DD_01_FEATURE_MASK MSR. Feat ures report ed t hrough sub- funct ion 01H of CPUI D funct ion 0DH cannot be m asked. — These processors do not support t he CPUI D80000001_FEATURE_MASK MSR. Feat ures report ed t hrough CPUI D funct ion 80000001H cannot be m asked.

•

Ext ended m odel I D 1H and m odels AH, EH, and FH ( for all values of st epping I D) ; or ext ended m odel I D 2H and m odels 5H, CH, EH, and FH ( for all values of st epping I D) : — These processors support t he CPUI D1_FEATURE_MASK MSR at MSR address 130H. I t s init ial value is FFFFFFFF_FFFFFFFFH, m asking no feat ures. — These processors do not support t he CPUI DD_01_FEATURE_MASK MSR. Feat ures report ed t hrough sub- funct ion 01H of CPUI D funct ion 0DH cannot be m asked.

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— These processors support t he CPUI D80000001_FEATURE_MASK MSR at MSR address 131H. I t s init ial value is FFFFFFFF_FFFFFFFFH, m asking no feat ures.

•

Ext ended m odel I D 2H and m odels AH and DH ( for all values of st epping I D) : — These processors support t he CPUI D1_FEATURE_MASK MSR at MSR address 132H. I t s init ial value is FFFFFFFF_FFFFFFFFH, m asking no feat ures. — These processors support t he CPUI DD_01_FEATURE_MASK MSR at MSR address 134H. I t s init ial value is FFFFFFFF_FFFFFFFFH, m asking no feat ures. — These processors support t he CPUI D80000001_FEATURE_MASK MSR at MSR address 133H. I t s init ial value is FFFFFFFF_FFFFFFFFH, m asking no feat ures.

CPUI D m asking is not an archit ect urally com m it t ed feat ure. I nt el does not expect t o support it on any processor m odel ot her t han t hose ident ified above. For fut ure processors, I nt el plans t o support CPUI D fault ing ( Sect ion 2.3.2) as long as t here cont inues t o be a m arket need for a cross- generat ion live- m igrat ion capabilit y by VMMs t hat do not support all t heir VMs using I nt el VT-x.

2.3.1.1

Virtualization of CPUID Masking

I nt el does not expect t hat a VMM support ing live- m igrat ion com pat ibilit y pools will it self operat e in a VM. Thus, such soft ware should not find it self in a sit uat ion in which CPUI D m asking m ight be em ulat ed by anot her VMM. However, soft ware vendors m ay ident ify ot her usages of CPUI D m asking. ( I nt el does not advocat e such usages.) For t he sake of com plet eness, t his sect ion discusses when a VMM m ight decide t o virt ualize CPUI D m asking and how it m ight do so. A VMM m ay choose t o em ulat e CPUI D.01H: EAX ( fam ily, m odel, et c.) by ret urning t o guest soft ware t he sam e value t hat t he hardware report s. I f t his value im plies support for CPUI D m asking ( see Sect ion 2.3.1) , guest soft ware m ay seek t o use CPUI D m asking. A VMM m ay choose t o support such guest soft ware wit h appropriat e virt ualizat ion of t he CPUI D- m asking MSRs. Specifically, it m ay int ercept execut ions of t he WRMSR inst ruct ion and record t he values t hat guest soft ware at t em pt s t o writ e t o t he CPUI D- m asking MSRs. I t can t hen use t hose values in it s virt ualizat ion of t he CPUI D inst ruct ion. Det ails depend on how t he VMM is support ing t he VM in which t he guest soft ware operat es:

•

I f t he VM is operat ing in VMX non- root operat ion, t he VMM can use t he recorded values when det erm ining which values t o place in ECX and EDX when virt ualizing CPUI D funct ions 1 and 80000001H. Specifically, it can place in each regist er t he logical-AND of t he value it would have used ( in t he absence of CPUI D m asking) and t he value t hat guest soft ware at t em pt ed t o writ e t o t he corresponding CPUI D- m asking MSR.

•

I f t he VM is not operat ing in VMX non- root operat ion, t he VMM can writ e t o each CPUI D- m asking MSR t he logical-AND of t he value desired by t he VMM ( for it s own CPUI D virt ualizat ion) and t he value t hat guest soft ware at t em pt t o writ e t o t he MSR.

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A VMM m ight choose not t o virt ualize CPUI D m asking even t hough it em ulat es CPUI D.01H: EAX wit h a value t hat im plies support for t hat feat ure. Developers of soft ware using CPUI D m asking should consider t his fact .

2.3.2

CPUID Faulting

CPUI D fa ult in g is an alt ernat ive hardware assist t hat enables such VMMs t o im plem ent a cross- generat ion live- m igrat ion capabilit y on plat form s based on a support ing processors. Like CPUI D- induced VM exit s ( Sect ion 2.2) , CPUI D fault ing gives a VMM com plet e cont rol over guest execut ions of t he CPUI D inst ruct ion. ( This abilit y is sufficient t o im plem ent a cross- generat ion live- m igrat ion capabilit y.) Like CPUI D m asking ( Sect ion 2.3.1) , CPUI D fault ing does not require use of I nt el VT-x. When CPUI D fault ing is enabled, all execut ions of t he CPUI D inst ruct ion out side syst em - m anagem ent m ode ( SMM) cause a general- prot ect ion except ion ( # GP( 0) ) if t he current privilege level ( CPL) is great er t han 0. I f a VMM operat es at CPL 0 and all guest soft ware operat es wit h CPL > 0, CPUI D fault ing causes every execut ion of t he CPUI D inst ruct ion t o t ransit ion t o t he VMM ( via t he # GP( 0) ) . A VMM handling t he # GP( 0) can em ulat e execut ion of t he CPUI D inst ruct ion by placing what ever values it chooses in t he regist ers EAX, EBX, ECX, and EDX. When t he VMM ret urns cont rol t o t he VM, it will appear t o guest soft ware t hat t he CPUI D inst ruct ion ret urned t he values t hat were chosen by t he VMM. Because every execut ion of t he CPUI D inst ruct ion wit h CPL > 0 causes an except ion, and because t he VMM m ay put any values it want s in t he regist ers EAX, EBX, ECX, and EDX, a VMM has com plet e cont rol over execut ion of t he CPUI D inst ruct ion in any VM in which CPUI D fault ing is enabled. I f t he VMM is support ing a live- m igrat ion com pat ibilit y pool, it can em ulat e t he CPUI D inst ruct ion in such VMs so as not t o report any feat ure t hat is not support ed by every processor in t he live- m igrat ion com pat ibilit y pool. As explained in Sect ion 2.1, t his approach support s correct guest operat ion even aft er live m igrat ion. VMM soft ware enables CPUI D fault ing by program m ing t he MI SC_FEATURES_ENABLES m odel- specific regist er ( MSR) . This MSR is at MSR address 140H. CPUI D fault ing is enabled by set t ing bit 0 of t he MSR. This m eans t hat soft ware can enable CPUI D fault ing wit h an algorit hm such as t he following: MOV ECX, 140H

// access MISC_FEATURES_ENABLES MSR

RDMSR

// read current value of MSR into EDX:EAX

OR EAX, 00000001H

// set bit 0 of EAX

WRMSR

// write back MSR with original value with bit 0 set

All processors t hat support CPUI D fault ing support t he MI SC_FEATURES_ENABLES MSR. Soft ware can ident ify support for CPUI D fault ing by consult ing t he PLATFORM_I NFO MSR. This MSR is at MSR address CEH. Support for CPUI D fault ing is report ed in bit 31 of t he MSR. This m eans t hat soft ware can ident ify support for CPUI D fault ing wit h an algorit hm such as t he following: MOV ECX, CEH

2-8

// access PLATFORM_INFO MSR

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RDMSR

// read current value of MSR into EDX:EAX

AND EAX, 80000000H

// result is non-zero if bit 31 of MSR is 1

JNZ cpuid_faulting_supported

// falls through if CPUID faulting is not supported

CPUI D fault ing is not an archit ect urally com m it t ed feat ure. I nt el m ay rem ove t he feat ure on fut ure processor m odels if it is no longer needed by soft ware ( e.g., if all VMMs t hat im plem ent a cross- generat ion live- m igrat ion capabilit y support all t heir VMs using I nt el VT-x) . Alt hough CPUI D fault ing is non- archit ect ural, I nt el plans t o report presence or absence of t he feat ure in t he PLATFORM_I NFO MSR and, if support ed, t o enable it via t he MI SC_FEATURES_ENABLES MSR.

2.4

EXAMPLE USE OF INTEL® VIRTUALIZATION TECHNOLOGY FLEXMIGRATION

Consider t he POPCNT inst ruct ion. Processors report t he POPCNT inst ruct ion in CPUI D.01H: ECX.POPCNT [ bit 23] . A VMM m ay support a live- m igrat ion com pat ibilit y pool t hat includes som e processors t hat support t he POPCNT inst ruct ion and ot hers t hat do not . As not ed in Sect ion 2.1, t he VMM should virt ualize t he CPUI D inst ruct ion so as not t o report t he POPCNT inst ruct ion — even on processors t hat do support t he inst ruct ion. Suppose t hat a VM operat es in VMX non- root operat ion. As not ed in Sect ion 2.2, every execut ion of t he CPUI D inst ruct ion in t he VM causes a VM exit t o t he VMM. When handling such VM exit s, t he VMM can check t he value of EAX t o det erm ine when guest soft ware is using CPUI D funct ion 01H. I n such cases, t he VMM can ensure t hat support for t he POPCNT inst ruct ion is not report ed by ensuring t hat ECX[ bit 23] is 0 before ret urning t o t he VM. Suppose t hat a VM does not operat e in VMX non- root operat ion. I n t his case, t he VMM can ensure t hat support for t he POPCNT inst ruct ion is not report ed by ensuring t hat t he value of CPUI D1_FEATURE_MASK MSR[ bit 23] is 0 whenever t hat VM is running ( t he VMM can use t he WRMSR inst ruct ion t o do t his) . As not ed in Sect ion 2.3, t his ensures t hat , when t he VM is running, CPUI D funct ion 01H will report 0 in ECX[ bit 23] .

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