IEEE MTT-V054-I01 (2006-01) [54, 1 ed.]

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JANUARY 2006

VOLUME 54

NUMBER 1

IETMAB

(ISSN 0018-9480)

MINI-SPECIAL ISSUE ON RADIO FREQUENCY INTEGRATED CIRCUITS Editorial: Mini-Special Issue on Radio Frequency Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. B. Steer

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MINI-SPECIAL ISSUE PAPERS

IMD Reduction in CMOS Double-Balanced Mixer Using Multibias Dual-Gate Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.-F. Au-Yeung and K.-K. M. Cheng New Miniature 15–20-GHz Continuous-Phase/Amplitude Control MMICs Using 0.18- m CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P.-S. Wu, H.-Y. Chang, M.-D. Tsai, T.-H. Huang, and H. Wang Design and Analysis of CMOS Broad-Band Compact High-Linearity Modulators for Gigabit Microwave/Millimeter-Wave Applications . . . . . . . . . . . . . . . . . . . H.-Y. Chang, P.-S. Wu, T.-W. Huang, H. Wang, C.-L. Chang, and J. G. J. Chern Design and Analysis for a Miniature CMOS SPDT Switch Using Body-Floating Technique to Improve Power Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M.-C. Yeh, Z.-M. Tsai, R.-C. Liu, K.-Y. Lin, Y.-T. Chang, and H. Wang Development of Multiband Phase Shifters in 180-nm RF CMOS Technology With Active Loss Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Lu, A.-V. H. Pham, and D. Livezey Distortion in RF CMOS Short-Channel Low-Noise Amplifiers . . . . . . . .R. A. Baki, T. K. K. Tsang, and M. N. El-Gamal Millimeter-Wave Design Considerations for Power Amplifiers in an SiGe Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U. R. Pfeiffer and A. Valdes-Garcia Design of Low-Power Fast VCSEL Drivers for High-Density Links in 90-nm SOI CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G. Sialm, C. Kromer, F. Ellinger, T. Morf, D. Erni, and H. Jäckel Switched Resonators and Their Applications in a Dual-Band Monolithic CMOS -Tuned VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S.-M. Yim and K. K. O An Improved Model for Ground-Shielded CMOS Test Fixtures. . . . . . . . . . . . . . . . . . . . T. Kaija and E. O. Ristolainen A Low-Power Oscillator Mixer in 0.18- m CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T.-P. Wang, C.-C. Chang, R.-C. Liu, M.-D. Tsai, K.-J. Sun, Y.-T. Chang, L.-H. Lu, and H. Wang A Digitally Controlled Constant Envelope Phase-Shift Modulator for Low-Power Broad-Band Wireless Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X. Yang and J. Lin

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(Contents Continued from Front Cover) CONTRIBUTED PAPERS

A New Set of (curl)-Conforming Hierarchical Basis Functions for Tetrahedral Meshes . . . . . . . . . . . . . P. Ingelström Characteristic-Function Approach to Parameter Extraction for Asymmetric Equivalent Circuit of On-Chip Spiral Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F. Huang, N. Jiang, and E. Bian Design and Modeling of 4-bit Slow-Wave MEMS Phase Shifters . . . . . . . . . . . B. Lakshminarayanan and T. M. Weller A Full-Duplex Dual-Frequency Self-Steering Array Using Phase Detection and Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G. S. Shiroma, R. Y. Miyamoto, and W. A. Shiroma A Substrate for Small Patch Antennas Providing Tunable Miniaturization Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . K. Buell, H. Mosallaei, and K. Sarabandi Hybrid Rectenna and Monolithic Integrated Zero-Bias Microwave Rectifier. . . . . . J. Zbitou, M. Latrach, and S. Toutain On the Conception and Analysis of a 12-GHz Push–Push Phase-Locked DRO . . . . . . . . . . . J.-F. Gravel and J. S. Wight Compact Microstrip Dual-Band Bandpass Filters Design Using Genetic-Algorithm Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M.-I. Lai and S.-K. Jeng An Evaluation of Three Simple Scalable MIM Capacitor Models . . . . . . . . . . . . . . . . . . . A. Mellberg and J. Stenarson Full-Wave Nonlinear Analysis of Nonradiative Dielectric Guide Circuits Including Lumped Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N. P. Pathak, A. Basu, and S. K. Koul Dual-Band Planar Quadrature Hybrid With Enhanced Bandwidth Response. . . . . C. Collado, A. Grau, and F. De Flaviis An Integral-Equation Technique for Solving Thick Irises in Rectangular Waveguides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. Stevanovic´ , P. Crespo-Valero, and J. R. Mosig Quasi-TM MoL/MoM Approach for Computing the Transmission-Line Parameters of Lossy Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G. Plaza, R. Marqués, and F. Medina Analysis of 2-D Frequency Converter Utilizing Compound Nonlinear Photonic-Crystal Structure by Condensed Node Spatial Network Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .H. Satoh, N. Yoshida, S. Kitayama, and S. Konaka Singularity Subtraction for Evaluation of Green’s Functions for Multilayer Media . . . . E. S¸ ims¸ek, Q. H. Liu, and B. Wei BPSK to ASK Signal Conversion Using Injection-Locked Oscillators–Part II: Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. M. López-Villegas, J. G. Macías-Montero, J. A. Osorio, J. Cabanillas, N. Vidal, and J. Samitier Modeling of a Cavity Filled With a Plane Multilayered Dielectric Using the Method of Auxiliary Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V. Volski and G. A. E. Vandenbosch Wide-Band Electrooptic Intensity Modulator Frequency Response Measurement Using an Optical Heterodyne Down-Conversion Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A. K. M. Lam, M. Fairburn, and N. A. F. Jaeger A Simplified Design Approach for Radial Power Combiners. . . . . . . . . . . . . . . A. E. Fathy, S.-W. Lee, and D. Kalokitis Numerical Performance and Applications of the Envelope ADI–FDTD Method . . . . . . . . . .C. T. M. Choi and S.-H. Sun Novel Microstrip Bandpass Filters Based on Complementary Split-Ring Resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. Bonache, I. Gil, J. García-García, and F. Martín A Turnstile Junction Waveguide Orthomode Transducer . . . . . . . . . . . . . . . . . . . . . . . A. Navarrini and R. L. Plambeck A Dual-Frequency Wilkinson Power Divider . . . . . . . . . . . . . . . . . . . . . . . . . L. Wu, Z. Sun, H. Yilmaz, and M. Berroth On the Development of a Compact Sub-Nanosecond Tunable Monocycle Pulse Transmitter for UWB Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. Han and C. Nguyen -Band MMIC Phase Shifter Using a Parallel Resonator With 0.18- m CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.-W. Kang, H. D. Lee, C.-H. Kim, and S. Hong Design and Modeling of a Specific Microwave Applicator for the Treatment of Snoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P.-Y. Cresson, C. Ricard, N. Bernardin, L. Dubois, and J. Pribetich A Neural-Network Method for the Analysis of Multilayered Shielded Microwave Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. P. García, F. Q. Pereira, D. C. Rebenaque, J. L. G. Tornero, and A. A. Melcón IM3 and IM5 Phase Characterization and Analysis Based on a Simplified Newton Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Crespo-Cadenas, J. Reina-Tosina, and M. J. Madero-Ayora Domain Decomposition FDTD Algorithm Combined With Numerical TL Calibration Technique and Its Application in Parameter Extraction of Substrate Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . .F. Xu, K. Wu, and W. Hong Analysis of NRD Components Via the Order-Reduced Volume-Integral-Equation Method Combined With the Tracking of the Matrix Eigenvalues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Bozzi, D. Li, S. Germani, L. Perregrini, and K. Wu A Comparative Analysis of Behavioral Models for RF Power Amplifiers . . . . . . .M. Isaksson, D. Wisell, and D. Rönnow Properties of Mixed-Mode Parameters of Cascaded Balanced Networks and Their Applications in Modeling of Differential Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H. Shi, W. T. Beyene, J. Feng, B. Chia, and X. Yuan Electrical Soliton Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D. S. Ricketts, X. Li, and D. Ham

106 115 120 128 135 147 153 160 169 173 180 189 198 210 216 226 235 240 247 256 265 272 278 285 294 302 309 321 329 339 348 360 373

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(Contents Continued from Page 1) Modeling of Periodic Distributed MEMS—Application to the Design of Variable True-Time Delay Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. Perruisseau-Carrier, R. Fritschi, P. Crespo-Valero, and A. K. Skrivervik Extraction of Broad-Band Passive Lumped Equivalent Circuits of Microwave Discontinuities . . . . . . . . . . . . . R. Araneo Optical Multibeamforming Network Based on WDM and Dispersion Fiber in Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .S. Blanc, M. Alouini, K. Garenaux, M. Queguiner, and T. Merlet On-Board Calibration System for Millimeter-Wave Radiometers Based on Reference-Polarized Signal Injection . . . . . . . . . . . . . . . . . . . O. A. Peverini, R. Tascone, E. Carretti, G. Virone, A. Olivieri, R. Orta, S. Cortiglioni, and J. Monari Significant Contribution of Nonphysical Leaky Mode to the Field Excited by a Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Tsuji, S. Ueki, and H. Shigesawa In-Line Pseudoelliptic Band-Reject Filters With Nonresonating Nodes and/or Phase Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Amari, U. Rosenberg, and R. Wu A 3-D Spectral-Element Method Using Mixed-Order Curl Conforming Vector Basis Functions for Electromagnetic Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J.-H. Lee, T. Xiao, and Q. H. Liu Evaluation of ACPR in Mixers Based on a Parametric Harmonic-Balance Approach. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Crespo-Cadenas, J. Reina-Tosina, and M. J. Madero-Ayora A Novel Phase Measurement Technique for IM3 Components in RF Power Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S.-Y. Lee, Y.-S. Lee, and Y.-H. Jeong Generalized Mixed-Mode -Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Ferrero and M. Pirola Designs for Broad-Band Microstrip Vertical Transitions Using Cavity Couplers . . . . E. S. Li, J.-C. Cheng, and C. C. Lai Chirping Unit Cell Length to Increase Frozen-Mode Bandwidth in Nonreciprocal MPCs . . . . . R. A. Chilton and R. Lee Covariance-Based Uncertainty Analysis of the NIST Electrooptic Sampling System. . . . . . . . . . . . . . . . . . . . . . . . . . . D. F. Williams, A. Lewandowski, T. S. Clement, J. C. M. Wang, P. D. Hale, J. M. Morgan, D. A. Keenan, and A. Dienstfrey Reconstructing Stratified Permittivity Profiles Using Super-Resolution Techniques. . . . . . . O. A. M. Aly and A. S. Omar Novel Butler Matrix Using CPW Multilayer Technology . . . . . . . . . . . . . . . . . . . M. Nedil, T. A. Denidni, and L. Talbi Information for Authors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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CALLS FOR PAPERS

2006 International Conference on Ultra-Wideband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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IEEE MICROWAVE THEORY AND TECHNIQUES SOCIETY The Microwave Theory and Techniques Society is an organization, within the framework of the IEEE, of members with principal professional interests in the field of microwave theory and techniques. All members of the IEEE are eligible for membership in the Society upon payment of the annual Society membership fee of $14.00, plus an annual subscription fee of $16.00 per year for electronic media only or $32.00 per year for electronic and print media. For information on joining, write to the IEEE at the address below. Member copies of Transactions/Journals are for personal use only.

ADMINISTRATIVE COMMITTEE K. VARIAN, President J. S. KENNEY, Vice President W. CANTRELL, Secretary N. KOLIAS, Treasurer M. P. DELISIO D. HARVEY L. KATEHI N. KOLIAS D. LOVELACE V. J. NAIR K. VARIAN K. WU W. SHIROMA S. M. EL-GHAZALY J. HAUSNER S. KAWASAKI T. LEE J. MODELSKI B. PERLMAN R. WEIGEL R. YORK R. SNYDER M. HARRIS K. ITOH J. S. KENNEY J. LIN A. MORTAZAWI D. RUTLEDGE S. WETENKAMP R. SORRENTINO Honorary Life Members Distinguished Lecturers Past Presidents T. S. SAAD K. TOMIYASU L. E. DAVIS W. HOEFER J. LASKAR M. SHUR K. C. GUPTA (2005) T. ITOH A. A. OLINER P. STAECKER L. YOUNG R. J. TREW (2004) W. GWAREK T. ITOH J. C. RAUTIO P. SIEGEL W. HEINRICH B. KIM D. RYTTING R. J. TREW F. SCHINDLER (2003)

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IEEE Periodicals Transactions/Journals Department Staff Director: FRAN ZAPPULLA Editorial Director: DAWN MELLEY Production Director: ROBERT SMREK Managing Editor: MONA MITTRA Senior Editor: CHRISTINA M. REZES IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES (ISSN 0018-9480) is published monthly by the Institute of Electrical and Electronics Engineers, Inc. Responsibility for the contents rests upon the authors and not upon the IEEE, the Society/Council, or its members. IEEE Corporate Office: 3 Park Avenue, 17th Floor, New York, NY 10016-5997. IEEE Operations Center: 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. NJ Telephone: +1 732 981 0060. Price/Publication Information: Individual copies: IEEE Members $20.00 (first copy only), nonmember $77.00 per copy. (Note: Postage and handling charge not included.) Member and nonmember subscription prices available upon request. Available in microfiche and microfilm. Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy for private use of patrons, provided the per-copy fee indicated in the code at the bottom of the first page is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For all other copying, reprint, or republication permission, write to Copyrights and Permissions Department, IEEE Publications Administration, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. Copyright © 2006 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Periodicals Postage Paid at New York, NY and at additional mailing offices. Postmaster: Send address changes to IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, IEEE, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. GST Registration No. 125634188.

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

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Editorial: Mini-Special Issue on Radio Frequency Integrated Circuits

T

HIS TRANSACTIONS’ Mini-Special Issue contains papers on radio frequency integrated circuits (RFICs). In previous years, papers submitted to this TRANSACTIONS’ Mini-Special Issue were restricted to expanded works based on presentations at the IEEE RFIC Symposium. This year the issue was not so restricted. Several papers considered for this TRANSACTIONS’ Mini-Special Issue were ready for publication many months before this issue was assembled and were, therefore, published in 2005. The sophistication of RFICs continues to increase with many entire systems being realized in integrated form in silicon and silicon–germanium technologies. A significant development is the increasing sophistication of Asian activities in RFICs and papers in this TRANSACTIONS Mini-Special Issue reflect some of these contributions. As with all conference special issues, the editing was undertaken by the regular editors of this TRANSACTIONS to ensure that the quality of the papers matched that for which this TRANSACTIONS is known. This TRANSACTIONS maintains a website at http://www.mtt. org/publications/Transactions/transactions.htm where Calls for Papers for special issues and links to author tools are maintained. The site also contains a number of themed editorials, which prospective authors should read. One of these is on the relationship between conference and journal papers. In this TRANSACTIONS, we seek to publish only original material that has not been presented elsewhere in archival form. The contents of many conference are now available electronically, through IEEE Xplore, for example, and expanded papers must contain mostly new material. This TRANSACTIONS’ website also includes advice on “How to Get Your Article Published,” which presents a few steps authors can follow to increase their

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chances of receiving favorable reviews of their paper. There is also an enhanced guide to authors at http://www.mtt.org/publications/Transactions/for_authors_transactions.htm and the checklist will expedite the processing of manuscripts. Upcoming Special and Mini-Special Issues are as follows. • Special Issue on Microwave Photonics. Scheduled publication date: February 2006. • Special Issue on Ultra-Wideband. Scheduled publication date: April 2006. • Special Issue on the 35th (2005) European Microwave Conference. Scheduled publication date: June 2006. • Mini-Special Issue on the 2005 Asia–Pacific Microwave Conference. Scheduled publication date: August 2006. • Special Issue on the 2006 Radio and Wireless Symposium. Scheduled publication date: September 2006. • Mini-Special Issue on Measurements for Large-Signal Characterization and Modeling of Nonlinear Analog Devices, Circuits, and Systems. Scheduled publication date: September 2006. • Special Issue on the 2006 IEEE MTT-S International Microwave Symposium. Scheduled publication date: November 2006. • Special Issue on Applications of Ferroelectrics in Microwave Technology. Scheduled publication date: January 2007. Additional information about these Special and Mini-Special Issues can be obtained from this TRANSACTIONS’ website.

MICHAEL B. STEER, Editor-in-Chief North Carolina State University Department of Electrical and Computer Engineering Raleigh, NC 27606-7911 USA

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

IMD Reduction in CMOS Double-Balanced Mixer Using Multibias Dual-Gate Transistors Chung-Fai Au-Yeung, Student Member, IEEE, and Kwok-Keung M. Cheng, Senior Member, IEEE

Abstract—This paper presents a novel and simple linearization scheme for a CMOS double-balanced mixer based on the use of multibias dual-gate transistors. In this technique, intermodulation-distortion (IMD) components with proper phase relationship, generated by devices operating at different bias conditions, are combined together to improve the linearity of mixers. For experimental verification, the measured performance of a fabricated CMOS mixer is shown. Over 35 dB of IMD reduction is achieved by the proposed method under proper biasing condition. Index Terms—Double-balanced mixer, dual-gate transistor, linearization.

I. INTRODUCTION

A

LINEAR and low-power RF transceiver circuit is highly desirable for modern wireless applications as far as high data rate and reliable transmission are concerned. Since signal level increases gradually down the receiving path, the first down-conversion mixer, rather than the low-noise amplifier, is often the major limiting factor in achieving high linearity. As illustrated in Fig. 1, when the received RF signal is strong enough, intermodulation-distortion (IMD) components would appear at the IF output due to the presence of device nonlinearities. This phenomenon causes interference to the adjacent channels, as well as performance degradation such as increased bit error rate. Recently, much effort has been devoted to the design of high-linearity mixers [1]–[3]. These techniques offer various levels of IMD reduction at the expense of circuit complexity. In this paper, a novel approach for the cancellation of IMD components in CMOS double-balanced mixer is introduced. In Section II, the operating principle of the multibias dual-gate transistor (MBDGT) and its application to the design of highlinearity mixers are illustrated. In Section III, the proposed technique is verified experimentally by the measured performance of a fabricated 0.35- m CMOS mixer circuit. For sensitivity study, issue relating to the effect of process variation (e.g., threshold voltage) on the IMD reduction capability is also addressed. II. MBDGT-BASED DOUBLE-BALANCED MIXER DESIGN A dual-gate transistor was proposed for active mixer design to achieve conversion gain, as well as isolation between the RF and local oscillator (LO) ports [4]. Moreover, double-balanced Manuscript received October 15, 2004; revised July 21, 2005. The authors are with the Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong (e-mail: kkcheng@ ee.cuhk.edu.hk). Digital Object Identifier 10.1109/TMTT.2005.860899

Fig. 1. Output spectrum of practical mixer.

Fig. 2.

Typical I–V characteristics of dual-gate transistor.

mixer architecture has been widely adopted with differential input and output for the suppression of spurious signals. A. Operating Principle of MBDGT Fig. 2 shows the I–V curves of a typical dual-gate transistor [5], [6]. When the device is biased in the knee region, the LO signal (upper gate) modulates the drain voltage (floating node) of the lower field-effect transistor (FET), which causes the FET to swing in and out of the linear and half-saturated regime. This hard switching mode offers the highest mixing gain with the tradeoff of poor IMD performance. In [4], it was suggested that the nonlinear drain current might be represented by phasor, in which the magnitude and phase of the

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AU-YEUNG AND CHENG: IMD REDUCTION IN CMOS DOUBLE-BALANCED MIXER USING MBDGTs

TABLE I SIMULATED IMD3 COMPONENT: DUAL-GATE TRANSISTOR WITH gate width

5

= 60 m AND load impedance = 1 k

Fig. 3. Basic configuration of double-balanced mixer with MBDGT.

IMD components are under the control of the biasing voltages. It was also shown [7] that there exists a close relationship between the phases of IMD components from devices operating in different bias regions. For illustration, the third-order IMD component generated by a dual-gate transistor is simulated by using Cadence version 5.0-in conjunction with AMS Hit-Kit v3.51 library (0.35- m four-metal-layer CMOS process). In this simulation study, a two-tone signal centered at 2.45 GHz with a power level of 15 dBm and tone spacing of 1 MHz is injected into the lower gate of the device. For mixing purposes, a LO drive, with a power level of 5 dBm and frequency of 2.35 GHz, is then applied to the upper gate. Table I shows the variations of the simulated IMD currents (in both magnitude and phase) appearing at the IF output under different biasing conditions ( and ). Note that the phase of the IMD signal can even be reversed (boxed) by properly controlling the operating point of the device. B. Operating Principle of Double-Balanced Mixer Fig. 3 shows the basic structure of a double-balanced mixer configured with MBDGT. In this topology, half of the branches are biased at either or to give the required IMD behaviors (antiphase relationship). By neglecting all intermodula-

tion products higher than the third order, and with a two-tone input, the corresponding branch currents (IMD) can simply be described by the following expressions [8]: (1) (2) (3) (4) where is the transfer coefficient representing the intermodulation behavior of the dual-gate transistor as a function of the biasing voltages; is the signal level of the RF input. Subsequently, the total IMD current flowing through the IF load can thus be written as (5) In practice, the transfer function is often a complex parameter, as the device may introduce parasitic capacitance and inductance. Furthermore, the amplitude and phase errors associated with the differential inputs at both the RF and LO ports are usually not negligible. Hence, in order to take into account the

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Fig. 4. Simulated nonlinear transconductance (lower FET) versus biasing voltages.

gain and phase mismatches caused by these circuit imperfections, the above equation may be modified to give (6) It can be seen from the above expression that by proper biasing and layout design, optimal condition (both magnitude and phase) may be enforced to cause the complete cancellation of the IMD signal at the IF output. It is also known [8] that under low-level excitation, these transfer coefficients are closely related to the expanded Taylor series of the nonlinear device’s transconductance. Fig. 4 shows the simulated and values of a typical CMOS dual-gate transistor operating at various RF and LO biasing voltages. Fig. 4(a) and (b) may be used to predict the optimum biasing condition for maximum conversion gain, as well as the third-order IMD signal level. And to a first approximation, the IMD current in (6) can be reexpressed as

higher order

product (7)

where and are complex coefficients. It can be seen from (7) that with equal-bias operation, complete elimination of the IMD component is impossible and the reduction factor is limited by the unequal phases of the first (in bracket) and second vectors (higher order IMD product). However, with the multibias scheme, the three vectors may be combined to cancel each other by properly choosing the magnitude and sign of and . Fig. 4(b) also indicates that more than one biasing voltage V may be selected to provide the same value (and sign) of for IMD suppression. III. EXPERIMENTS AND RESULTS Fig. 5 shows the microphotograph of a double-balanced dualgate mixer fabricated using 0.35- m CMOS technology. The

Fig. 5.

Microphotograph of the fabricated mixer.

entire mixer occupies a die area of less than 0.18 mm . The chip was wire bonded to a standard printed circuit board with the RF, LO, and IF signals being fed differentially by using off-chip baluns. The mixer was designed to operate at a supply voltage of 2 V and LO power of 5 dBm. The measurement setup shown in Fig. 6 was adopted for the experimental verification of the proposed method. Two independent power supplies were used to provide the required biasing voltages ( and ). In the two-tone test, signal centered at 2.45 GHz with frequency separation of 100 kHz was applied to the RF input of the mixer. Fig. 7 shows the IF output spectrum (100 MHz) of the mixer operating at an RF power level of 15 dBm under equal-bias ( V for maximum conversion gain) or multibias ( V; V) situation. With multibias operation, an IMD reduction of almost 40 dB was found. Fig. 8 shows the variation of the measured IMD signals with RF input power ranging from 0 to 45 dBm at a fixed bias condition. These results indicate that more than 20 dB of IMD reduction can easily be obtained over a wide input power range even without readjustment of bias level. For a vector modulated signal test, both CDMA2000 (forward link of nine channels) and wide-band code division multiple access (WCDMA) (3.86 Mchip/s) formats are employed. Figs. 9 and 10 show the measured output spectrums and, in both modulation cases, the enhancement in adjacent channel power ratio (ACPR) was found to be well above 20 dB.

AU-YEUNG AND CHENG: IMD REDUCTION IN CMOS DOUBLE-BALANCED MIXER USING MBDGTs

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Fig. 6. Experimental setup.

Fig. 7. Measured two-tone test.

Fig. 9. Output spectrum: CDMA2000.

Fig. 8. Measured IMD level versus input RF power.

Fig. 10.

Output spectrum: WCDMA.

The proposed scheme was further studied by observing the output signal level (fundamental and IMD) versus different biasing condition. In the first experiment, equal bias

was applied to the mixer with the same set of test parameters (signal frequencies, LO and RF power level, etc.). In the second experiment, was kept constant, while

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Fig. 11.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Measured output power level with equal-bias scheme.

was varied from 0.75 to 2.25 V. Figs. 11 and 12 show the measured IMD performance as a function of the LO bias voltage. These results indicate that there exists more than one optimum point for IMD cancellation (as explained in Section II). For the first minima, the corresponding IMD level (degradation in conversion gain) for equal-bias V and multibias ( V; V) schemes are 55 dBm (5 dB) and 75 dBm (2 dB), respectively. In comparison, a further IMD reduction of almost 20 dB was achieved by the proposed scheme. In practice, the optimum biasing condition may drift with temperature, as well as device parameters. For example, the threshold voltage of CMOS transistor could change substantially due to process variation. For sensitivity study of multibias scheme, the measured IMD reduction factor as a function of biasing voltage offset (deviation from the optimum value) is depicted in Fig. 13. Under proper bias condition (zero offset), the achievable IMD reduction level was found to be 37 dB. However, the suppression factor degrades gradually with increasing voltage offset (drops to 20 dB with an offset voltage of 0.05 V). The sensitivity effect may be minimized using bias adaptation technique (part of the baseband circuitry in transceiver design). For reference purposes, the overall performance of the fabricated mixer is tabulated in Table II. Note that the MBDGT mixer was found to exhibit a conversion gain of 1.7 dB and port-to-port isolation of over 40 dB. The current consumption of the entire mixer is 4.4 mA (including output buffer). For comparison, the measured performance of the same mixer operating at equal-bias condition (maximum conversion gain) is also included. By applying the proposed scheme, the third-order intercept point was improved by almost 10 dB. IV. CONCLUSIONS The application of an MBDGT to IMD reduction in CMOS double-balanced mixer has been presented. The mechanism of IMD generation and cancellation in an MBDGT-based double-balanced mixer has been described and validated by computer simulation and experiments. Excellent IMD reduction has been demonstrated by performing measurements on a

Fig. 12.

Measured output power level with multibias scheme.

fabricated CMOS mixer. Adaptation circuitry may be required to compensate for the sensitivity problem caused by the process

AU-YEUNG AND CHENG: IMD REDUCTION IN CMOS DOUBLE-BALANCED MIXER USING MBDGTs

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[3] K. K. M. Cheng and C. F. Au-Yeung, “Novel difference-frequency dualsignal injection method for CMOS mixer linearization,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 7, pp. 358–360, Jul. 2004. [4] Y. Kwon and D. Pavlidis, “Phasor diagram analysis of millimeter-wave HEMT mixers,” IEEE Trans. Microw. Theory Tech, vol. 43, no. 9, pp. 2165–2167, Sep. 1995. [5] J. Gao and X. Y. Cao, “Characteristics and applications of dual-gate FET,” in Int. Microwave and Millimeter Wave Technology Conf., Aug. 1998, pp. 120–122. [6] P. J. Sullivan, B. A. Xavier, and W. H. Ku, “Doubly balanced dual-gate CMOS mixer,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 878–881, Jun. 1999. [7] J. Kim and Y. Kwon, “Intermodulation analysis of dual-gate FET mixers,” IEEE Trans. Microw. Theory Tech, vol. 50, no. 6, pp. 1544–1555, Jun. 2002. [8] S. A. Maas, Nonlinear Microwave Circuit. Norwood, MA: Artech House, 1988.

Fig. 13.

IMD reduction versus offset voltage. TABLE II SUMMARY OF MEASURED MIXER PERFORMANCE

variation. This scheme is simple to implement and is most suitable for monolithic integration. REFERENCES [1] T. J. Ellis, “A modified feed-forward technique for mixer linearization,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 1998, pp. 1423–1426. [2] Y. Kim, Y. Kim, and S. Lee, “Linearized mixer using predistortion technique,” IEEE Microw. Wireless Compon. Lett, vol. 12, no. 6, pp. 204–205, Jun. 2002.

Chung-Fai Au-Yeung (S’05) received the B.Eng. (with first-class honors) and M.Phil. degrees in electronic engineering from The Chinese University of Hong Kong, Shatin, Hong Kong, in 2001 and 2003, respectively, and is currently working toward the Ph.D. degree in electronic engineering at The Chinese University of Hong Kong. His research interests include RF integrated circuit (RFIC) design, device modeling, and linearization techniques.

Kwok-Keung M. Cheng (S’90–SM’91) received the B.Sc. degree (with first-class honors) in electronic engineering and Ph.D. degree from King’s College, University of London, London, U.K., in 1987 and 1993, respectively. In 1996, he became an Assistant Professor (then Associate Professor in 2001) with the Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong. He has authored or coauthored over 60 papers appearing in leading international journals and conferences. He contributed to MMIC Design (London, U.K.: IEE Press, 1995) and RFIC and MMIC Design and Technology (London, U.K.: IEE Press, 2001). His current research interests are mainly concerned with the design of RF integrated circuits (RFICs), microwave mixers, low-noise oscillators, and high-efficiency power amplifiers for wireless communication systems. Dr. Cheng was the recipient of the 1986 Siemens Prize, the 1987 Institution of Electrical Engineers (IEE) Prize, and the 1988 Convocation Sesquicentennial Prize in Engineering (University of London).

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New Miniature 15–20-GHz Continuous-Phase/Amplitude Control MMICs Using 0.18-m CMOS Technology Pei-Si Wu, Student Member, IEEE, Hong-Yeh Chang, Member, IEEE, Ming-Da Tsai, Member, IEEE, Tian-Wei Huang, Senior Member, IEEE, and Huei Wang, Fellow, IEEE

Abstract—The design and performance of two new miniature 360 continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18- m CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm 0.82 mm. To the best of the authors’ knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360 phase-control range above 5 GHz reported to date. Index Terms—CMOS, monolithic microwave integrated circuit (MMIC), phase shifter, vector sum method.

I. INTRODUCTION

P

HASE shifters are widely used in phase array systems as electronic beam-steering elements and in other systems such as modulators [1]. For these applications, relatively low-cost monolithic microwave integrated circuits (MMICs) using a CMOS process are preferable to realize phase shifters. Several techniques have been utilized to realize a MMIC phase shifter. The reflection-type phase shifter (RTPS), which utilizes a 3-dB hybrid coupler and a pair of reflective termination circuits with impedance transformers, is widely used due to its wide-band performance [2]–[5]. However, using bulk silicon processes, the low inductor/varactor values and the limited varactor capacitance range produce high losses and small phase control ranges [6]. Another way of realizing broad-band phase shifters is by switching between a low-pass filter and a high-pass filter. The low-resistivity substrate and large on-state resistance in CMOS process will degrade the performance of the switching-type phase shifters (STPSs) [7]. These two types of phase shifters can be cascaded for multibit operation, which will increase their insertion losses and phase errors [2]. On the other hand, active phase shifters using the vector sum method

Manuscript received May 13, 2005; revised Septempber 14, 2005. This work was supported in part by the National Science Council under Grant NSC 93-2752-E-002-002-PAE, Grant NSC 93-2213-E-002-033, and Grant NSC 93-2219-E-002-024. The authors are with the Graduate Institute of Communication Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2005.860896

can provide continuous phase shift or multibit operation with low loss or even gain [8]–[14]. In this paper, we propose the following two new -band monolithic phase shifters using 0.18- m CMOS technology. 1) The Cartesian phase shifter obtains a 360 phase shift by the vector sum of four orthogonal signals of which amplitudes can be varied over a wide dynamic range. Smaller chip size has been achieved by reducing the number of couplers and delay lines. This phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range between 15–20 GHz. The chip size is 0.95 mm 0.76 mm. 2) The hybrid polar phase shifter separates the input signal into two paths: one can be placed anywhere in the first quadrant, and the other can cover the whole third quadrant. Therefore, by linear combination of these two paths, this circuit has 360 continuous phase shift. This phase shifter demonstrates an insertion loss of 16.2 dB with a 38.8-dB dynamic range from 15 to 20 GHz. The chip size is only 0.71 mm 0.82 mm. These circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method. To the best of the authors’ knowledge, these circuits have the smallest chip size among all 360 phase-control range MMIC phase shifters above 5 GHz. II. PHASE/AMPLITUDE CONTROL TOPOLOGY A. Cartesian Phase Shifter The architecture of the first phase shifter, which is modified from [13] and [14], is shown in Fig. 1(a). The input power divider and 180 delay lines in the original designs are replaced with a 180 balun. The output Wilkinson power combiner is omitted by designing the output matching of the variable gain amplifiers (VGAs) to 100 . Therefore, the chip area can be reduced substantially. The four different VGAs are marked with VGA I, VGA II, VGA III, and VGA IV in Fig. 1(a), and , , , are variable gains of the corresponding amplifiers, respectively. Fig. 1(a) shows that the input signal is split by the 180 balun, so that VGA I and VGA III are excited with out-of-phase and equal magnitude inputs at a desired frequency. The outputs of the first-stage VGAs are then combined through the 3-dB quadrature coupler and amplified by the second-stage VGAs. Finally, the outputs of the second-stage VGAs are combined.

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WU et al.: NEW MINIATURE 15–20-GHz CONTINUOUS-PHASE/AMPLITUDE CONTROL MMICs USING 0.18- m CMOS TECHNOLOGY

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TABLE I ~ EXAMPLE OF RELATIONS BETWEEN OUTPUT VECTOR Z PHASE SHIFTER, AND VGA GAINS

, , tion (1) can also be derived as

, and

OF

CARTESIAN

. Equa-

where

(2) As described in (2), continuous magnitude and phase can be achieved by properly adjusting the gain of each VGA. For example, if the desired output vector is placed in the first quadrant and is 30 dB higher than , then can be approximated as , and the magnitude of is proportional to . By the assumption that the VGAs have more than 30 dB gain control, an example of relations between output vector and the four VGA gains is shown in Table I. B. Hybrid Polar Phase Shifter Fig. 1. (a) Architecture and (b) vector diagram at the output of second-stage VGAs of a Cartesian phase shifter. (c) Redrawn (b) with the gain of VGAs as axes, i.e. A A =2 2, A A =2 2, A A =2 2, and A A =2 2.

p

p

p

p

As shown in Fig. 1(b), the and represent the output vectors of the VGA II and VGA IV, respectively. is located in the second quadrant and is located in the fourth quadrant. From Fig. 1(b), the output vector can be expressed as

(1)

which is slightly different than those in [13] and [14]. Therefore, Fig. 1(b) can be redrawn as Fig. 1(c) by representing the output vector of the phase shifter as the sum of the four axes, i.e.

Fig. 2(a) shows the architecture of the second proposed phase shifter. At the desired frequency, the input signal is split into two paths with equal magnitude and 180 phase difference through the 180 balun. The two paths are delayed by RTPS sections with phase shift of and and amplified by the VGAs with gains of and , respectively. The 3-dB quadrature coupler with two terminating varactors, which provides 0 to 90 continuous-phase delay, is the RTPS section. The vector diagram of the output of the VGAs is shown in Fig. 2(b). The and represent the output vectors of VGA I and VGA II, respectively. The vector is placed in the first quadrant with the magnitude and phase controlled by the gain of VGA I and capacitances of the varactors. Similarly, the vector is placed in the third quadrant marked with magnitude and phase controlled by VGA II and capacitance . The output vector of the hybrid polar phase shifter, which is obtained by adding vector and and then multiplying by as shown in Fig. 2(b), can also cover four

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TABLE II ~ OF HYBRID POLAR PHASE RELATIONS BETWEEN OUTPUT VECTOR Z SHIFTER, VGA GAINS, AND PHASE SHIFTS

and the capacitances of the varactors. If the desired output vector is placed in the first or third quadrants, then and can be the same as the desired phase, and the magnitude of is proportional to the difference between and . For in the first quadrant, should be much higher than ; for in the third quadrant, should be much higher than gain . If the desired output vector is located in the second quadrant, and can be 90 and 0 , respectively; therefore, the magnitude of is proportional to . Similarly, and of 0 and 90 , respectively, lead the vector in the fourth quadrant. The relations between output vector of the hybrid polar phase shifter, gains of VGAs, and phase-shifter sections are summarized in Table II. III. BUILDING BLOCKS OF PHASE SHIFTERS

Fig. 2. (a) Architecture and (b) vector diagram at the output of the second-stage phase shifter sections of hybrid polar phase shifter.

quadrants. According to Fig. 2(b), the output vector expressed as

can be

(3) Equation (3) can also be derived as

The proposed active phase shifters were fabricated using TSMC’s 0.18- m MS/RF CMOS technology [15], [16] with one poly and six metal layers. High- inductors can be formed by using the top AlCu metallization layer of 2- m thickness without additional process steps. The substrate conductivity is approximately 10 S/m. With the optimized CMOS technology and a deep n-well, this technology provides a and of better than 60 and 55 GHz, respectively. Accumulation-mode varactors (using 32-Å gate oxide) are provided, giving sharp-transition in the – tuning range. The metal–insulator–metal (MIM) capacitors with 1 fF/mm were fabricated using oxide intermetal dielectric. Two types of polysilicon resistors, with several and k , are provided by choosing the individual dose of ion-implantation separately from the gate-electron doping process. The designs of the new phase shifters are composed of 180 baluns, 3-dB quadrature couplers, and VGAs. Each of them is described below.

where A. 180 Baluns

(4) As described in (4), continuous magnitude and phase control can be achieved by properly adjusting the gains of the two VGAs

The 180 baluns are realized using transformers, which can reduce chip sizes substantially. The transformers are based on a Marchand balun configuration [17]–[20] using a thin-film microstrip structure. The bottom metal (metal 1) is set to ground, and the top metal is the signal line. In order to reduce the size of the balun and utilize the full three-dimentional (3-D) potential

WU et al.: NEW MINIATURE 15–20-GHz CONTINUOUS-PHASE/AMPLITUDE CONTROL MMICs USING 0.18- m CMOS TECHNOLOGY

Fig. 3. (a) Simplified circuit diagram. (b) One-coil 3-D layout structure of the transformer balun. The z axis is scale larger for the clarity. (c) Chip photograph of the transformer balun test circuit.

of the six metal layers, a broadside coupled spiral structure is adopted to realize the balun. A simplified circuit diagram of the balun is shown in Fig. 3(a). Port 1 is connected through two coils to open the circuit; ports 2 and 3 are connected from the ground to the coil. At the center frequency, if port 1 excites the signal, it will couple to the righthand side coils, and ports 2 and 3 will be 180 out of phase. This transformer is divided into two coils; each coil can be employed as a quadrature coupler; therefore, this transformer is like a Marchand balun. Fig. 3(b) shows a one-coil 3-D layout structure of the transformer, the axis is drawn to a large scale purposely for the clarity. The coils are broadside coupled and meandered in spiral configuration. For size and coupling consideration, the line width and gap are both 3 m. The transformer balun was simulated by a full-wave EM simulator (Sonnet software) [21]. A chip photograph of the transformer balun test circuit is shown in Fig. 3(c); the center transformer size without pad is only 0.144 0.084 mm . The transformer was tested using on-wafer probing. We used an HP8510C network analyzer to measure the small-signal data up to 50 GHz. The three-port -parameters are extracted from the two-port measurements using a port-reduction method [22],

Fig. 4. Simulated and measured results. (a) Magnitude of jS j and jS (b) Amplitude and phase difference of S and S of the transformer.

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j

.

[23]. The simulated and measured insertion losses and phase differences between ports 2 and 3 of the transformer are shown in Fig. 4. The insertion loss is better than 8.5 dB from 14 to 45 GHz, and the major cause of the loss is the metal loss. The amplitude and phase imbalance is below 1.3 dB and 6 for the same frequency range. B. 3-dB Quadrature Couplers The 3-dB quadrature couplers are also implemented using thin-film microstrip structure. Broadside configurations are again utilized for higher coupling and reduced chip size. The substrate height of this thin-film structure is only about 5.2 m. For the 10- m gap meander broadside coupled line, there is small edge coupling effect. Therefore, the size of the couplers can be very compact. In these designs, the broadside meandered quarter-wave couplers are adopted for the 3-dB 90 directional couplers. To reduce the size of the couplers, the center frequency is set to 22.5 GHz. The 3-D layout structure of the coupler is illustrated in Fig. 5(a). The broadside coupled lines are composed of metals 6, 5, and 4. Because metal 6 is thicker than the other metals, metals 5 and 4 are connected together by

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Fig. 5. (a) 3-D layout structure and (b) simulated magnitude of jS j, jS j, and jS j of the 90 directional coupler. The z axis is scale larger for the clarity.

Fig. 6. (a) Simplified schematic of the VGA. (b) Chip photograph of the VGA test circuit.

via holes to balance the metal loss. The simulated results of the coupler are shown in Fig. 5(b). C. VGAs The critical components in the proposed phase shifters are VGAs, which adopt the distributed amplifier topology [24]. The cascode configuration has a higher maximum available gain and wider bandwidth than a single-ended device does, so it is utilized in our VGA circuits. Fig. 6(a) shows a simplified schematic of the VGA, which consists of input and output transmission lines coupled by the transconductance of the MOSFETs. The gate line is formed by lumped inductors and MOSFET gate–source capacitance and is terminated in its characteristic impedance at the end. To reduce the die size, the inductance of the artificial transmission line is realized utilizing helical inductors. The helical inductors have smaller sizes than those of planar spiral inductors since the turns are expanded vertically [25]. The number of gain cells is two for minimum size consideration. The gain of the VGA is controlled by the adjusting transconductance of the upper device in the cascode cell. The chip photograph of the VGA test circuit is shown in Fig. 6(b) with the core VGA size of 0.23 0.38 mm excluding testing pads.

Fig. 7. Variation of simulated and measured gains versus control voltage (V ) of the VGA test circuit.

The gain of the VGA test circuit can be varied from 6 to 39.5 dB between 5–21 GHz through on-wafer measurement. The simulated and measured variation of gain with frequency for different control voltages are shown in Fig. 7. The chip is biased at V and varied from 0.3 to 2.5 V, with

WU et al.: NEW MINIATURE 15–20-GHz CONTINUOUS-PHASE/AMPLITUDE CONTROL MMICs USING 0.18- m CMOS TECHNOLOGY

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Fig. 8. Chip photograph of the Cartesian phase shifter with a chip size of 0.95 0.76 mm .

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the drain current varying from 0 to 28 mA. Compared with previously published broad-band designs using a 0.18- m CMOS process, this amplifier has comparable gain and bandwidth with the smallest chip area, therefore, it is suitable for our active phase-shifter designs. IV. EXPERIMENTAL RESULTS A. Cartesian Phase Shifter The chip photograph of the Cartesian phase shifter with a size of 0.95 0.76 mm is shown in Fig. 8. Fig. 9(a) shows the measured small-signal gain corresponding to eight-phase status from 2 to 30 GHz. The controlling method using two gain states in [13] and [14] is used to control the VGAs to realize the eight phase states. The minimum loss at 15 GHz is 0.7 dB and the maximum is 6.5 dB. The measured phase results of eight-phase status are shown in Fig. 9(b). The maximum phase error of the phase state at 15 GHz is 15 , while the minimum one is 0.1 . The causes of amplitude and phase errors are the mismatches of the four VGAs, amplitude and phase imbalances of the 3-dB quadrature coupler, and the 180 transformer balun. In order to obtain the minimum imbalance of the Cartesian phase shifter, we can use the static constellation diagram measurement [26] to extract the best phase and amplitude states. The static constellation diagrams were obtained from continuous-wave (CW) mode -parameter measurement with a computer-controlled setup. The forward transmission coefficients are plotted in Fig. 10(a) with a linear polar format, where the control voltages of four VGAs have been swept from 0.7 to 1.7 V in steps of 0.125 V. The ideal of the Cartesian phase shifter should look like a square and the center should be the origin point of the polar chart in Fig. 10(a). However, from Fig. 10(a), all continuous phase and an insertion loss of 8 dB with 37-dB dynamic ranges can be still achieved. Based on the forward transmission coefficient, the control voltages of the best amplitude and phase states are extracted. The static constellation diagrams of quaternary phase-shift keying (QPSK) or higher order quadrature amplitude modulation (QAM) modulations can be generated. The 16-QAM was used as an example to plot the extracted constellation diagram in Fig. 10(b), which

Fig. 9. Measured small-signal: (a) gain and (b) phase for eight states of the Cartesian phase shifter.

features a minimum insertion loss of 6.2 dB, an amplitude imbalance of 0.26 dB, and a phase imbalance of 3 . Using the static constellation diagram, the Cartesian phase shifter can achieve good amplitude and phase states from 15 to 20 GHz. B. Hybrid Polar Phase Shifter The chip photograph of the hybrid polar phase shifter with a size of 0.71 0.82 mm is shown in Fig. 11. Fig. 12(a) shows the measured small-signal gain corresponding to 16-phase status from 2 to 30 GHz. The 16-phase control voltage is obtained by (4). The minimum loss at 15 GHz is 10.9 dB, and the maximum is 14.2 dB. The measured phase results of 16-phase status are shown in Fig. 12(b). The maximum phase error of the phase state at 15 GHz is 12.5 , while the minimum is 0 . The amplitude and phase errors are due to the mismatches of the two VGAs and the amplitude and phase imbalances of the 180 transformer balun and phase-shifter sections. To reduce the practical mismatches and imbalances of the VGAs and passive elements, the static constellation diagram measurement was also used to extract the best phase and am-

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Fig. 12. Measured small-signal: (a) gain and (b) phase for 16 states of the hybrid polar phase shifter.

Fig. 10. Measured static constellation diagram of the Cartesian phase shifter at 15 GHz. (a) Sweep control voltages of four VGAs from 0.7 to 1.7 V with a step of 0.125 V. (b) Extracted 16-QAM.

Fig. 11. Chip photograph of the hybrid polar phase shifter with a chip size of 0.71 0.82 mm .

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plitude states. Fig. 13(a) shows the forward transmission coefficients with a linear polar format, where the control voltage of two VGAs and varactors have been swept from 0.7 to 1.9 V and 0 to 1.2 V in steps of 0.1 and 0.2 V, respectively. In the ideal case, the first and third quadrants should be square and the second and fourth quadrants should be quarter circle. However, from Fig. 13(a), the phase shifter can still achieve 360 phase shift and an insertion loss of 16.2 dB with a 38.8-dB dynamic range. Based on Fig. 13(a), we generate 32-PSK as an example, and the results are plotted in Fig. 13(b), featuring an average insertion loss of 16.2 dB, an amplitude imbalance of 0.2 dB, and a phase imbalance of 1.71 Using the static constellation diagram, the hybrid polar phase shifter can also achieve good amplitude and phase states from 15 to 20 GHz. These two circuits have the same frequency range. The Cartesian phase shifter has four VGAs, so it has a lower insertion loss with higher dc power consumption and larger chip size. On the other hand, the hybrid polar phase shifter has only two VGAs, so it has a higher insertion loss, lower dc power consumption, and smaller chip size. The hybrid polar phase shifter can achieve better insertion loss by adding an additional amplifier at the output. For QAM modulation, the Cartesian phase shifter is more suitable due to its square-like constellation. The hpolar phase shifter is preferable for the PSK modulation because of its circle-like constellation.

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TABLE III COMPARISON OF MONOLITHIC PHASE SHIFTERS FROM 10 TO 20 GHz

Fig. 13. Measured static constellation diagram of the hybrid polar phase shifter at 20 GHz. (a) Sweep control voltages of two VGAs and varactors from 0.7 to 1.9 V at 0 to 1.2 V in steps of 0.1 and 0.2 V, respectively. (b) Extracted 32-PSK.

V. DISCUSSIONS These two circuits demonstrate continuous-phase/amplitude control from 15 to 20 GHz using commercial 0.18- m CMOS process. Although amplifiers using the same process provide gains at the same or higher frequency range [24], [25], our phase shifters have losses instead of gains for the following reasons. We use a one-stage amplifier as the VGA to reduce the chip size, which limits the gain performance. Also, the passive couplers and baluns have high losses in silicon substrate. As a component of the transmitter, the insertion loss of the phase shifter will limit the output power of the system. An amplifier can be added after the phase shifter to increase the output power. For receiver applications, the insertion loss degrades the noise figure, and thus a low-noise amplifier is needed in front of the phase shifter. The nonlinearity is another problem of these phase shifters. Since the varators and transistors are nonlinear devices, all continuous-phase shifters have the nonlinearity problems. Static

constellation diagrams measurement can be used to extract the phase and amplitude states and calibrate the mismatches of the devices and imbalances of the passive couplers and baluns. However, this method needs good resolution of bias control circuits to find the exact state and requires small phase variation over frequency. Modern digital signal processing (DSP) and predistortion techniques may possibly solve the bias resolution problems and nonlinearity; moreover, using a CMOS process, digital circuits can be easily integrated with the phase shifters. The phase flatness over frequency may not be as severe because the bandwidths used in modern communication systems are usually below 500 MHz. Our circuits demonstrate small phase variation over frequency. The Cartesian phase shifter has a maximum root mean square (rms) phase error of 1.13 for 3-b phase control (45 ) with 500-MHz bandwidth from 15 to 20 GHz. The hybrid polar phase shifter achieves a maximum rms phase error of 0.17 for 4-bit phase control (22.5 ) with 2-GHz bandwidth at the same frequency range. Table III summarizes published monolithic phase shifters from 10 to 20 GHz. Comparing with published monolithic

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phase shifters for digital 5-bit phase-shift operation, the smallest insertion loss is 5.3 dB with 8 phase error [30], the others’ insertion losses are all above 10 dB [4], [29], [30], [32]. For analog 360 continuous-phase shifts, the insertion losses are 20 dB [6] (cascade four chips) and 7.2 dB [28] (cascade two chips). It is observed that these two CMOS phase shifters have the smallest chip size with comparable performance and can be attractive for the system integration in a single chip. VI. CONCLUSION Two new miniature MMIC phase shifters using the vector sum method have been presented in this paper. These MMIC circuits are designed for 15–20 GHz using a 0.18- m CMOS process. Continuous 0 –360 phase and 8–45-dB and 16.2–55-dB constant insertion losses can be achieved for the first and second phase shifter, respectively. There two phase shifters can be further applied to -QAM and -PSK modulations with good phase/amplitude matches in microwave applications. ACKNOWLEDGMENT The authors would like to thank M.-F. Lei, Dr. C.-H. Tseng, and Dr. K.-Y. Lin, all of National Taiwan University, Taiwan, R.O.C., and P.-Y. Chen, Airoha Technology Corporation, Taiwan, R.O.C., for their helpful suggestions. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, R.O.C., through the Chip Implementation Center of Taiwan, Taiwan, R.O.C. REFERENCES [1] K. M. Simon, M. J. Schindler, V. A. Mieczkowski, P. F. Newman, M. E. Goldfarb, E. Reese, and B. A. Small, “A production-ready, 6–18-GHz, 5-b phase shifter with integrated CMOS-compatible digital interface circuitry,” IEEE J. Solid-State Circuits, vol. 27, no. 10, pp. 1452–1456, Oct. 1992. [2] S. Lee, J.-H. Park, H.-T. Kim, J.-M. Kim, Y.-K. Kim, and Y. Kwon, “Low-loss analog and digital reflection-type MEMS phase shifters with 1 : 3 bandwidth,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 1, pp. 211–219, Jan. 2004. [3] K. Miyaguchi, M. Hieda, K. Nakahara, H. Kurusu, M. Nii, M. Kasahara, T. Takagi, and S. Urasaki, “An ultra-broad-band reflection-type phase shifter MMIC with series and parallel LC circuits,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 12, pp. 2446–2452, Dec. 2001. [4] D. C. Boire, G. S. Onge, C. Barratt, G. B. Norris, and A. Moysenko, “4 : 1 bandwidth digital five bit MMIC phase shifters,” in Microwave Millimeter-Wave Monolithic Circuit Symp. Dig., Jun. 1989, pp. 69–73. [5] H. Hayashi, T. Nakagawa, and K. Araki, “A miniaturized MMIC analog phase shifter using two quarter-wave-length transmission lines,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 150–154, Jan. 2001. [6] H. Zarei and D. J. Allstot, “A low-loss phase shifter in 180 nm CMOS for multiple-antenna receivers,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., vol. 1, Feb. 2004, pp. 392–393. [7] H. D. Lee and D. W. Kang, “A Ku-band MOSFET phase shifter MMIC,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2004, pp. 191–194. [8] M. Kumar, R. J. Menna, and H. Huang, “Broad-band active phase shifters using dual gate MESFET,” IEEE Trans. Microw. Theory Tech., vol. MTT-29, no. 10, pp. 1098–1101, Oct. 1981. [9] Y. Gazit and H. C. Johnson, “A continuously-variable Ku-band phase/amplitude control module,” in IEEE MTT-S Int. Microwave Symp. Dig., 1981, pp. 436–438. [10] J. Grajal, J. Gismero, M. Mahfoudi, and F. A. Petz, “A 1.4–2.7-GHz analog MMIC vector modulator for a crossbar beamforming network,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 10, pp. 1705–1714, Oct. 1997. [11] J. R. Selin, “Continuously variable L-band monolithic GaAs phase shifter,” Microwave J., vol. 30, pp. 211–218, Sep. 1987.

[12] D. K. Paul and P. Gardner, “Microwave quadrature active phase shifter using MESFETs,” Microwave Opt. Technol. Lett., vol. 15, pp. 359–360, Aug. 1997. [13] S. J. Kim and N. H. Myung, “A new active phase shifter using a vector sum method,” IEEE Microw. Guided Wave Lett., vol. 10, no. 6, pp. 233–235, Jun. 2000. [14] P.-Y. Chen, T.-W. Huang, H. Wang, Y.-C. Wang, C.-H. Chen, and P.-C. Chao, “K -band HBT and HEMT monolithic active phase shifters using vector sum method,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1414–1424, May 2004. [15] H.-M. Hsu, J.-Y. Chang, J.-G. Su, C.-C. Tsai, S.-C. Wong, C.-W. Chen, K.-R. Peng, S.-P. Ma, C.-N. Chen, T.-H. Yeh, C.-H. Lin, Y.-C. Sun, and C.-Y. Chang, “A 0.18-m foundry RF CMOS technology with 70-GHz ft for single chip system solutions,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2001, pp. 1869–1872. [16] C.-H. Diaz, K.-L. Young, J.-H. Hsu, J. C. H. Lin, C.-S. Hou, C.-T. Lin, J.-J. Liaw, C.-C. Wu, C.-W. Su, C.-H. Wang, J.-K. Ting, S.-S. Yang, K.-Y. Lee, S.-Y. Wu, C.-C. Tsai, H.-J. Tao, S.-M. Jang, S.-L. Shue, H.-C. Hsieh, Y.-Y. Wang, C.-C. Chen, S.-C. Yang, S. Fu, S.-Z. Chang, T.-C. Lo, J.-Y. Wu, J.-S. Shy, C.-W. Liu, S.-H. Chen, B.-L. Lin, B.-K. Liew, T. Yen, C.-H. Yu, Y.-C. Chao, M.-S. Liang, C. Wang, and J. Y. C. Sun, “A 0.18-m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications,” in IEEE VLSI Tech. Symp., Jun. 1999, pp. 11–12. [17] K. S. Ang, S. B. Economides, S. Nam, and I. D. Robertson, “A compact MMIC balun using spiral transformers,” in Asia–Pacific Microwave Conf., vol. 3, Dec. 1999, pp. 655–658. [18] Y. J. Yoon, Y. Lu, R. C. Frye, M. Y. Lau, P. R. Smith, L. Ahlquist, and D. P. Kossives, “Design and characterization of multilayer spiral transmission-line baluns,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 9, pp. 1841–1847, Sep. 1999. [19] Y. Fujiki, “Chip type transformer,” U.S. Patent 5 497 137, Mar. 5, 1996. [20] P.-S. Wu, C.-H. Wang, T.-W. Huang, and H. Wang, “Compact and broadband millimeter-wave monolithic transformer balanced mixers,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 10, pp. 3106–3114, Oct. 2005. [21] Sonnet User’s Manual, Release 8.53, Liverpool, New York, Dec. 2002. [22] M. Davidovitz, “Reconstruction of the S -matrix for a 3-port using measurements at only two ports,” IEEE Microw. Guided Wave Lett., vol. 5, pp. 349–350, Oct. 1995. [23] H.-C. Lu and T.-H. Chu, “Port reduction methods for scattering matrix measurement of an n-port network,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 6, pp. 959–967, Jun. 2000. [24] R.-C. Liu, C.-S. Lin, K.-L. Deng, and H. Wang, “Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode distributed amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1370–1374, Aug. 2004. [25] M.-D. Tsai, K.-L. Deng, H. Wang, C.-H. Chen, C.-S. Chang, and J. G. J. Chern, “A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 12, pp. 554–556, Dec. 2004. [26] A. Ashtiani, S.-I. Nam, A. d’Espona, S. Lucyszyn, and I. D. Robertson, “Direct multilevel carrier modulation using millimeter-wave balanced vector modulators,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2611–2619, Dec. 1998. [27] K. Miyaguchi, M. Hieda, K. Nakahara, H. Kurusu, M. Nii, M. Kasahara, T. Takagi, and S. Urasaki, “An ultra-broad-band reflection-type phase shifter MMIC with series and parallel LC circuits,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 12, pp. 2446–2452, Dec. 2001. [28] H. Hayashi, T. Nakagawa, and K. Araki, “A miniaturized MMIC analog phase shifter using two quarter-wave-length transmission lines,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 150–154, Jan. 2002. [29] K. M. Simon, M. J. Schindler, V. A. Mieczkowski, P. F. Newman, M. E. Goldfarb, E. Reese, and B. A. Small, “A production-ready, 6–18-GHz, 5-b phase shifter with integrated CMOS-compatible digital interface circuitry,” IEEE J. Solid-State Circuits, vol. 27, no. 10, pp. 1452–1456, Oct. 1992. [30] C. F. Campbell and S. A. Brown, “A compact 5-bit phase-shifter MMIC for K -band satellite communication systems,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2652–2656, Dec. 2000. [31] J. Wallace, H. Redd, and R. Furlow, “Low cost MMIC DBS chip sets for phased array applications,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 1999, pp. 677–680. [32] Y.-S. Dai, X.-J. Chen, T.-S. Chen, T.-F. Yu, L. Lin, L.-J. Yang, S.-P. Gao, and J.-T. Lin, “A novel multi-octave five-bit monolithic phase shifter,” in Proc. Int. Conf. Microwave and Millimeter Wave Technology, Sep. 2000, pp. 215–218. [33] T. M. Hancock and G. M. Rebeiz, “A 12-GHz SiGe phase shifter with integrated LNA,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 977–983, Mar. 2005.

WU et al.: NEW MINIATURE 15–20-GHz CONTINUOUS-PHASE/AMPLITUDE CONTROL MMICs USING 0.18- m CMOS TECHNOLOGY

Pei-Si Wu (S’02) was born in Changhua, Taiwan, R.O.C., in 1980. He received the B.S. degree in electric engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2002, and is currently working toward the Ph.D. degree at National Taiwan University. His research interests include microwave and millimeter-wave circuit designs.

Hong-Yeh Chang (S’02–M’05) was born in Kinmen, Taiwan, R.O.C., in 1973. He received the B.S. and M.S. degrees in electric engineering from National Central University, Chung-Li, Taiwan, R.O.C., in 1996 and 1998 respectively, and the Ph.D. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2004. In 1998, he joined Chunghwa Telecom Laboratories, Taoyuan, Taiwan, R.O.C., where he was involved in the research and development of code-division multiple-access (CDMA) cellular phone systems. From 1999 to 2000, he was with Syncomm Inc., Taoyuan, Taiwan, R.O.C., where he was involved with the personal access communications system (PACS) radio port and handset design. He is currently a Post-Doctoral Research Fellow with the Graduate Institute of Communication Engineering, National Taiwan University. His research interests include monolithic microwave and millimeter-wave integrated circuit designs, transceiver and power-amplifier linearization, and RF signal measurement.

Ming-Da Tsai (S’03–M’06) was born in Miaoli, Taiwan, R.O.C., on August 31, 1979. He received the B.S. degree in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2001, and the M.S. and Ph.D. degree from the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2003 and 2005, respectively. His research interests are in the areas of RF and millimeter-wave integrated circuits in CMOS, SiGe BiCMOS, and compound semiconductor technologies.

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Tian-Wei Huang (S’91–M’98–SM’02) received the B.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1987, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Los Angeles (UCLA), in 1990 and 1993, respectively. In 1993, he joined the TRW RF Product Center, Redondo Beach, CA. His research has focused on the design and testing of monolithic microwave integrated circuits (MMICs) and RF integrated circuits (RFICs). From 1998 to 1999, he was with Lucent Technologies, where he was involved with local multipoint distribution system (LMDS) fixed wireless systems. From 1999 to 2002, he was involved with RF/wireless system testing with Cisco Systems. In August 2002, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are MMIC/RFIC design, packaging, and RF system-on-chip integration.

Huei Wang (S’83–M’87–SM’95–F’06) was born in Tainan, Taiwan, R.O.C., on March 9, 1958. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, MI, in 1984 and 1987, respectively. During his graduate study, he was engaged in research on theoretical and numerical analysis of electromagnetic radiation and scattering problems. He was also involved in the development of microwave remote detecting/sensing systems. In 1987, he joined the Electronic Systems and Technology Division, TRW Inc. (now Northrop Grumman), Redondo Beach, CA. He has been an MTS and Staff Engineer responsible for MMIC modeling of computer-aided design (CAD) tools, and MMIC testing evaluation and design, and became the Senior Section Manager of the Millimeter-Wave Sensor Product Section, RF Product Center. In 1993, he visited the Institute of Electronics, National Chiao-Tung University, Hsinchu City, Taiwan, R.O.C., where he taught MMIC-related topics. In 1994, he returned to TRW Inc. In February 1998, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., where he is currently a Professor. Dr. Wang is a member of Phi Kappa Phi and Tau Beta Pi. He was the recipient of the Distinguished Research Award presented by the National Science Council, R.O.C. (2003–2006). He was also elected as the first Richard M. Hong Endowed Chair Professor of National Taiwan University in 2005.

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Design and Analysis of CMOS Broad-Band Compact High-Linearity Modulators for Gigabit Microwave/Millimeter-Wave Applications Hong-Yeh Chang, Member, IEEE, Pei-Si Wu, Student Member, IEEE, Tian-Wei Huang, Senior Member, IEEE, Huei Wang, Fellow, IEEE, Chung-Long Chang, and John G. J. Chern

Abstract—CMOS broad-band compact high-linearity binary phase-shift keying (BPSK) and IQ modulators are proposed and analyzed in this paper. The modulators are constructed utilizing a modified reflection-type topology with the transmission lines implemented on the thick SiO2 layer to avoid the lossy silicon substrate. The monolithic microwave integrated circuit (MMIC) chips were fabricated using standard bulk 0.13- m MS/RF CMOS process and demonstrated an ultracompact layout with more than 80% chip size reduction. The broadside couplers and 180 hybrid for the modulators in the CMOS process are broad-band designs with low phase/amplitude errors. The dc offset and imbalance for the proposed topology are investigated and compared with the conventional reflection-type modulators. The measured dc offset was improved by more than 10 dB. Both BPSK and IQ modulators feature a conversion loss of 13 dB, a modulation bandwidth of wider than 1 GHz, and second- and third-order spur suppressions of better than 30 dBc. The IQ modulator shows good sideband suppression with high local-oscillator suppression from 20 to 40 GHz. The modulators are also evaluated with a digital modulation signal and demonstrate excellent modulator quality and adjacent channel power ratio. Index Terms—Binary phase-shift keying (BPSK), CMOS, coupler, millimeter wave (MMW), quadrature amplitude modulator (QAM).

I. INTRODUCTION

C

MOS and SiGe direct-conversion modulators are commonly used in cellular phone and wireless local area network (WLAN) transmitters due to the low complexity and cost [1]–[6]. For high-level modulations, such as orthogonal frequency division multiplexing (OFDM) or n-quadrature amplitude modulation (n-QAM), high-linearity and low dc-offset binary phase-shift keying (BPSK) or IQ modulators are essential for the communication systems, and their performances have significant effects on the modulation quality [or signal-to-noise ratio (SNR)]. Generally, most of them employ ring-mixer or Gilbert-cell mixer configurations because of high local oscillator Manuscript received May 23, 2005; revised September 6, 2005. This work was supported in part by the NTU-TSMC Joint-Development Project and the National Science Council of Taiwan, R.O.C., under Grant NSC 93-2752-E-002002-PAE, Grant NSC 93-2219-E-002-016, Grant NSC 93-2219-E-002-025, and Grant NSC 93-2213-E-002-033. H.-Y. Chang, P.-S. Wu, T.-W. Huang, and H. Wang are with the Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, 106 Taiwan, R.O.C. (e-mail: [email protected]). C.-L. Chang and J. G. J. Chern are with the Taiwan Semiconductor Manufacturing Company, Hsinchu City, 300, Taiwan, R.O.C. Digital Object Identifier 10.1109/TMTT.2005.860900

(LO)-to-RF isolation and good spurious suppression [7]. The CMOS Gilbert-cell-based modulators demonstrated excellent performance, but they are mostly below 10 GHz. Conventional refection-type BPSK modulators, that consist of two bi-phase reflection-type modulators and two Lange couplers, were reported using InP- or GaAs-based high-electron mobility transistor (HEMT), and heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) processes for the millimeter-wave (MMW) applications [8]–[12]. These modulators are usually broad-band with low LO drive and good amplitude/phase matches. However, the chip sizes of conventional reflection-type modulators are directly affected by the operation frequency. The conventional approach is relatively suitable for MMW MMIC designs. The other drawback of conventional reflection-type modulators is low LO-to-RF isolation (or high dc offset) due to the mismatch of components. From the previously reported results, the dc offset is severe in the constellation diagram and results a seriously LO leakage [10], but the LO leakage can be further improved with the additional dc-offset compensations [11]. To show the operation principle of the reflection-type BPSK and IQ modulators without imbalances and nonlinearity, the simplified time varying output voltage equations can be obtained from [11] and expressed as (1) and (2) for BPSK and IQ modulators, respectively, where is modulation gain, is the angular frequency of the carrier signal, and , , and are baseband signals. From (1), the BPSK modulation can be performed by sweeping from 1 to 1 (or 1 to 1) based on the baseband waveform. For the IQ modulator, the phase and amplitude of the carrier can be modulated by sweeping and simultaneously, and the modulation schemes can be n-PSK or n-QAM based on the vector sum of the baseband inputs. In [13], we proposed an innovative topology for the reflection-type BPSK modulator and implemented it using a 0.13- m CMOS process, which utilized a 180 hybrid and a Wilkinson power combiner to replace the input and output 90 hybrids. This modified reflection-type BPSK modulator features low dc offset, amplitude, and phase imbalances. In order to enhance the modulation bandwidth, the small inductors are used for RF

0018-9480/$20.00 © 2006 IEEE

CHANG et al.: DESIGN AND ANALYSIS OF CMOS BROAD-BAND COMPACT HIGH-LINEARITY MODULATORS

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choke at the gates of the NMOS devices and the small capacitors are used for RF bypass at the baseband input ports. In this paper, the proposed BPSK modulator is further applied to an IQ modulator design, and the quadrature LO signals are generated from a low-imbalance broadside coupler. The IQ modulator demonstrates a good modulation quality with wide modulation bandwidth. The broadside 90 coupler and a very compact transformer with low amplitude and phase errors are also developed in the CMOS technology for the 90 and 180 hybrids used in the proposed reflection-type BPSK and IQ modulators. All passive elements are designed in thin-film microstrip line (or called microstrip-on-die in [14]). The layout of the thin-film microstrip line is very compact with low loss due to the thick SiO layer and the avoidance of the silicon substrate loss. The imbalance analysis of the conventional reflection-type modulators presented the investigations of the phenomena versus the imbalances [11]. In this paper, we further analyze the dc offset and imbalance of the proposed reflection-type modulators. As compared with conventional reflection-type modulators, the proposed topology is less sensitive to the mismatch of the hybrids and device characteristics, as well as the amplitude and phase imbalances in the BPSK modulator. The couplers design of the proposed reflection-type modulator is more flexible, and the compact layouts are easily achieved with the tradeoff between the imbalances in the two 90 couplers using CMOS technology. According to the experimental results, the BPSK and IQ modulators feature low conversion loss and high linearity with ultra compact chip sizes. To the best of our knowledge, this is the first attempt to use CMOS technology to demonstrate BPSK and IQ modulators by using the modified reflection-type topology in the MMW regime with much smaller sizes (0.5 0.35 mm , 0.65 0.58 mm ) and gigabit modulation bandwidth. II. OPERATION PRINCIPLE AND ANALYSIS A. BPSK Modulator From our prior work, the conventional reflection-type BPSK modulator using GaAs HBT technology was reported in [11], and it is configured in a balanced structure similar to that of the balanced amplifiers. Based on the reflection-type topology, the block diagram of the proposed modified reflection-type BPSK modulator is shown in Fig. 1(a), which comprises a transformer, an in-phase combiner, and two bi-phase reflection modulators. and are differential input ports for the baseband signal. The bi-phase reflection modulator consists of a 90 hybrid and two NMOS devices. Assuming that the 90 hybrid has a phase error of and an amplitude error of , the transformer has a phase error of and an amplitude error of , and the in-phase combiner has a phase error of and an amplitude error of ( , , and , while , , and for the ideal case). The transmission coefficients of the modified reflection-type BPSK modulator can be expressed as

Fig. 1. Block diagram of the modified reflection-type modulators. (a) BPSK modulator. (b) IQ modulator.

(3)

is the magnitude difference between and where and is the phase difference between and ( , for ideal case). For the conventional reflection-type BPSK modulator, the transmission coefficients with imbalances can be found in [11]. Similarly, we assume that the Lange coupler has an amplitude error of (3 dB) and a phase error

is the input reflection coefficient looking into the where drain of the NMOS at the port (device is turned on or off), and is at the port (device is turned off or on). There are two phase states for the BPSK operation: the devices

at port is off and the devices at port is on for the state-0, while the devices at port is on and the devices at port is off for the state-1. Assuming that the amplitude error and are (3 dB), and the phase error and are 5 ( rad). Since the in-phase combiner is a symmetric architecture, we suppose that the amplitude imbalance is 1 and the phase error is 0. The state-0 transmission coefficient of the BPSK modulator can be expressed as (4) and the state-1 transmission coefficient

can be expressed as (5)

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Fig. 2. DC offset contours versus the magnitude difference M and the phase difference  . (a) Modified reflection-type BPSK modulator. (b) Conventional reflection-type BPSK modulator.

of 5 . The state-0 transmission coefficient of the conventional reflection-type BPSK modulator can be expressed as (6) and the state-1 transmission coefficient as

can be expressed (7)

The dc offset of the BPSK modulator can be expressed as (8) and the dc offset is zero for ideal case. The dc offset contours in decibel versus the magnitude difference and the phase difference are plotted in Fig. 2 for the modified and the conventional reflection-type BPSK modulators. The magnitude difference is swept from 0 to 1, and the phase difference is swept from 0 to 180 . As can be observed, the dc offset of the proposed topology is less sensitive to the mismatch of the device characteristics. In most of the area of Fig. 2(a), the dc offset is

Fig. 3. Imbalances versus the magnitude difference M and the phase difference  for the modified reflection-type BPSK modulator. (a) Amplitude imbalance contours. (b) Phase imbalance contours between states 0 and 1 (A = 3 dB, A = 1 dB,  = 5 , and  = 5 ).

better than 15 dB. From the EM simulation and the experimental results of the 180 hybrid, the amplitude error is within 1.122 (1 dB), therefore, the dc offset should be better than 20 dB. On the contrary, the dc offset of the conventional reflection-type BPSK modulator is only about 10 dB, as shown in Fig. 2(b). It can be observed that the proposed reflection-type BPSK modulator is easier to match to the device and can be further used for broad-band circuit designs with low dc offset. For the imbalance analysis of the modified reflection-type BPSK modulator, the imbalance contours between states 0 and 1 are plotted in Fig. 3 for amplitude and phase imbalances. In most of the area of the charts, the amplitude imbalance is within 1.5 dB and the phase imbalance is within 5 . From (3) and the imbalance investigation, the insertion losses of the modified BPSK modulator degrade with the amplitude imbalance increasing, but the phase error causes only phase delay without any degradation. In the case where the magnitude difference is within 0.5 and the phase difference is greater than 170 , the amplitude and phase imbalances of the modified reflection-type

CHANG et al.: DESIGN AND ANALYSIS OF CMOS BROAD-BAND COMPACT HIGH-LINEARITY MODULATORS

TABLE I COMPARISON OF MAXIMUM AMPLITUDE AND PHASE IMBALANCES FOR THE MODIFIED AND CONVENTIONAL BPSK MODULATORS 0:5,  170 ) (M

BPSK modulator are almost within 2 dB and 5 , when the amplitude errors and are (3 dB) and the phase errors and are 20 . Comparing with the conventional reflection-type BPSK modulator, the maximum amplitude and phase imbalances are listed in Table I. The modified reflection-type BPSK modulator obviously features lower amplitude/phase imbalances, even when the amplitude error is up 8 (18 dB) and the phase error is up to 50 . Therefore, the modified reflection-type modulator also has better robustness to the amplitude/phase errors of the hybrids. When the amplitude errors is greater than (3 dB), the phase error is greater than 20 , and the phase difference is smaller than 170 , the errors ( and ) of the 180 hybrid will be strongly related to the amplitude/phase imbalances of the modulator, and the imbalances also can be obtained from the imbalance calculation in (3). From above discussions, we can summarize that i) the insertion losses of the modulator are affected by the magnitude/phase of the input reflection coefficient, the amplitude imbalance of the 90 hybrid (coupler 1), and the losses of the passive components; ii) the imbalances of the modulator will be dominated by the performance of the 180 hybrid. B. IQ Modulator The block diagram of the IQ modulator is shown in Fig. 1(b), which employs two modified reflection-type BPSK modulators, a 90 hybrid (coupler 2), and an in-phase combiner. IP/IN and QP/QN are differential baseband signal input ports for BPSK I and Q channels, respectively. Since the imbalances of coupler 2 seriously affect the quadrature error and amplitude imbalance of the IQ modulator, we assume that coupler 2 has an amplitude imbalance of and a phase error of ; these notations are different from the imbalances of coupler 1 discussed in the previous section on the BPSK modulator. The transmission coefficients of the modified reflection-type IQ modulator can be expressed as

(9) and are the input reflection coefficients where looking into the drain of the NMOS at the I- and Q-channel BPSK modulators, respectively. From (9), we can see that the

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insertion loss is affected by the amplitude imbalance of coupler 1, and some phase delay without any distortion is caused by the phase error . These phenomena are similar to the results discussed for the BPSK modulator. For the imbalances of coupler 2 and the in-phase combiner, the quadrature error degrades with increasing the phase imbalances of and , and the I/Q channel imbalance increases with increasing the amplitude imbalances of and . Generally, the amplitude/phase errors of the in-phase combiner are very low due to its symmetric structure, and therefore they can be neglected for these investigations. For the case of low mismatch among the devices, coupler 2, and the in-phase combiner, the insertion loss of the IQ modulator increases as the amplitude imbalance of the 180 hybrid deteriorates, while the phase error also causes only phase delay without any distortion. Otherwise, the imbalances of the 180 hybrid affect quadrature error, I/Q channel amplitude, and dc offset of the IQ modulator. From the above-mentioned discussion, the 180 hybrid and the 90 coupler are strongly related to the performances of the IQ modulator. In order to reduce the distortion and imbalances of the IQ modulator, the imbalances of the 180 hybrid and coupler 2 should be minimized. III. CIRCUIT DESIGN The broad-band modulators were designed using a TSMC commercial standard bulk 0.13- m 1P8M CMOS process, which provides one poly layer for the gates of CMOS transistors and eight metal layers for interconnections. The metal–insulator–metal (MIM) capacitor, spiral inductor, and polysilicon resistors with several and k are available in this process. The active device (NMOS) exhibits a unit current gain frequency of 90 GHz and a maximum oscillation frequency of 106 GHz with a 1.2-V supply. In order to avoid the silicon substrate loss, the metal 1 (bottom layer) in the 1P8M CMOS process is used for ground plane, and the metal 8 (top layer) is used for the microstrip line with the thick SiO layer as substrate. The internal metal layers (metals 2–7) are used for broadside-coupler design and interconnections. A. Compact 90 and 180 Couplers in the CMOS Process The 90 hybrids used for bi-phase reflection modulator are implemented using broadside-coupled lines, because the gap of the edge coupler is too small to fabricate for the required coupling. They are meandered to achieve a compact layout, which is another advantage of the broadside coupler compared with the Lange coupler. The layout and cross section of coupler 1 is shown in Fig. 4(a) with an area of m . The space and width of the striplines first can be obtained from the required even- and odd-mode characteristic impedances, and then the coupling coefficients are calculated using the full-wave EM simulator SONNET [15]. Metal layers 7and 8 are used for the coupled lines of the broadside coupler due to the thick dielectric layer, and metal 1 is also used for the ground plane to keep away from the Si substrate. The line width is 4 m with a line length of approximately 300 m. The thickness of the SiO layer between metals 1 and 7 is represented by with a dielectric constant of and between metals 7 and 8 is represented by with a dielectric constant of . From the analysis in Section II, the imbalances of coupler 1 has little effect on the

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Fig. 4. Coupler 1. (a) Layout and cross section with an area of 196 (b) Simulated results.

2 40 m .

performance of the modified reflection-type BPSK modulator (except for the insertion loss), and thus the center frequency of the coupler can be designed higher to make the coupler compact. The simulated results of coupler 1 are plotted in Fig. 4(b) from 1 to 100 GHz. The coupled port has a maximum coupling of 2.7 dB at a center frequency (100 GHz). The average coupling for the direct and coupled ports is 3.5 dB between 50–100 GHz. The phase difference between the direct and coupled ports is approximately 90 with an error within 3 in the entire band. The layout and cross-sectional view of coupler 2 is illustrated in Fig. 5(a) with an area of m . The broadside coupled lines are composed of metals 7 and 8, and the line width is 4 m with a line length of approximately 850 m. From Section II, the performance of the IQ modulator is seriously degraded by the imbalances of coupler 2, and coupler 2 should be carefully designed. To obtain the appropriate coupling, we add an additional offset distance ( of 1 m) between metals 7 and 8 to reduce the coupling coefficient. The coupling can be reduced by decreasing the line width, but the insertion loss will increase due to the metal loss and mismatch. The simulated results of coupler 2 are plotted in Fig. 5(b), which features a maximum coupling of 2.7 dB at a center frequency of 45 GHz, an amplitude imbalance of within 2 dB, and a phase imbalance of within 2 between 20–70 GHz. The average coupling coefficient for the direct and coupled ports is about 3.7 dB. In the design of the 180 hybrid, a Marchand balun [7] is used as the 180 hybrid due to its excellent amplitude/phase match and broad-band response. The layout and cross section of the 180 hybrid is shown in Fig. 6. Two coupled lines in the Marc-

Fig. 5. Coupler 2. (a) Layout and cross section with an area of 340 (b) Simulated results.

2 65 m .

Fig. 6. Layout and cross section of the 180 hybrid with an area of 120

65 m .

2

hand balun are also constructed of broadside-coupled lines with the space and width of the transmission lines obtained from the

CHANG et al.: DESIGN AND ANALYSIS OF CMOS BROAD-BAND COMPACT HIGH-LINEARITY MODULATORS

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Fig. 8. Schematic of the modified reflection-type BPSK modulator.

Fig. 7. Measured and simulated results of the 180 hybrid. (a) Insertion losses. (b) Amplitude and phase imbalance (simulation: solid line; measurement: symbols).

required even- and odd-mode characteristic impedances. These two coupled lines are wound into a very compact area of m , and the structure is similar to the spiral broadside coupled striplines (SBCSs) using low-temperature co-fired ceramic (LTCC) [16] and GaAs processes [17]. The line width and gap are both 3 m. The measured (symbol) and simulated (solid line) insertion losses of the 180 hybrid are plotted in Fig. 7(a), which features a simulated insertion loss of better than 8 dB between 15–80 GHz. The measured results are obtained from the port reduction method [18] that extracts the three-port -parameters from multiple sets of two-port measurement results. The measured and simulated amplitude/phase imbalances versus frequency are plotted in Fig. 7(b). It is observed that the measured amplitude imbalance is within 1 dB, the measured phase imbalance is within 5 from 15 to 50 GHz, and the measured results agree with the simulated results. B. BPSK and IQ Modulators The schematic of the modified reflection-type BPSK modulator is shown in Fig. 8, and the photograph of the modified reflection-type BPSK modulator was shown in [13] with a chip size of mm . For optimal design of the modulator, the device size of the NMOS is properly selected based on the

on- and off-state reflection coefficients. A Wilkinson combiner is used for the in-phase combiner, and the quarter-wave transmission lines in the combiner are also meandered to achieve a compact layout. In order to enhance the modulation bandwidth, small inductors and capacitors are used for a low-pass network at the baseband input ports. The biases are 1 V at and 0 V at for state 0; the biases are 0 V at and 1 V at for state 1. For the state OFF of the modulator, the biases at and are both 0.5 V. The simulated results of the modified reflection-type BPSK modulator will be shown in Section IV and compared with the measured results. Between 18–80 GHz, the simulated insertion losses for states 0 and 1 are better than 12 dB with an amplitude imbalance of within 1 dB and a phase imbalance of within 5 , and the simulated insertion loss for state OFF is better than 35 dB. The conversion loss versus the LO frequency for the modulator is also simulated from 10 to 50 GHz when it performs as a double-sideband up-converter mixer. The simulated conversion loss is better than 10 dB with an output of higher than 5 dBm from 20 to 50 GHz. The baseband signal is a 5-MHz single-tone signal with a power of 8 dBm, and the LO drive power is 5 dBm. The schematic of the modified reflection-type IQ modulator is shown in Fig. 9, which utilizes a 90 coupler (coupler 2) to generate the quadrature-phase signals for the I and Q paths and uses an in-phase combiner to combine the I/Q modulated signals. The photograph of the modulator is shown in Fig. 10 with a chip size of mm . The metal 2 is used for the interconnection between baseband input pads and the nodes of IP, IN, QP, and QN. The baseband interconnections are properly routed to keep away from the RF or LO signal. The nodes of IP, IN, QP, and QN are usually biased with a dc voltage of 0.5 V to enhance the LO-to-RF isolation, when the circuit is performed as a mixer or modulator. The conversion loss versus LO frequency for the IQ modulator is simulated and presented in Section IV from 15 to 40 GHz when it is performed as an image-rejection up-converter mixer. The IF (baseband) input is a 5-MHz single-tone signal with a power of 10 dBm, and the LO drive power is 10 dBm. Between 20 to 40 GHz, the simulated conversion loss is better 11 dB, the sideband suppression is higher than 20 dB, and the output is also higher than 5 dBm.

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Fig. 9.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Schematic of the modified reflection-type IQ modulator.

Fig. 11. Measured and simulated results of the modified reflection-type BPSK modulator. (a) Insertion losses of states 0, 1, and OFF. (b) Amplitude and phase imbalances between states 0 and 1 (simulation: solid line; measurement: symbol with line). Fig. 10. Photograph of the modified reflection-type IQ modulator with a chip size of 0:65 0:58 mm .

2

IV. EXPERIMENTAL RESULTS A. BPSK Modulator The measurements of the modulator chips are performed via on-wafer probing. The -parameters of the chips were measured by using an Agilent 8510C network analyzer. The measured insertion losses of three states (states 0, 1, and OFF) between 1 to 80 GHz for the modified reflection-type BPSK modulator are plotted in Fig. 11(a), and the amplitude and phase imbalances between states 0 and 1 are plotted in Fig. 11(b). The measured results agree well with the simulated results. From 15 to 75 GHz, the measured insertion losses are less than 13 dB and the isolation in the OFF state is better than 40 dB, the amplitude imbalance is within 0.5 dB, and the phase imbalance is with 3 . The worst case input and output return losses are better than 8 dB. For the conversion loss measurement of the BPSK modulator, an Agilent 83 650L signal generator with a broad-band amplifier is used for the LO, an Agilent E4438C microwave signal generator with a 180 hybrid is used for baseband inputs, and the RF

Fig. 12. Measured output spectrum of the BPSK modulator with the LO frequency of 49 GHz and the baseband frequency of 5 MHz.

output signal is measured with an Agilent E4448A spectrum analyzer. The measured output spectrum of the BPSK modulator is plotted in Fig. 12, the LO source is 49 GHz with a power

CHANG et al.: DESIGN AND ANALYSIS OF CMOS BROAD-BAND COMPACT HIGH-LINEARITY MODULATORS

Fig. 13. Measured and simulated conversion loss and intermodulation versus the LO frequency from 10 to 50 GHz for the BPSK modulator.

Fig. 14. Measured conversion loss versus the baseband frequency from 1 MHz to 6 GHz with an LO frequency of 40 GHz for the BPSK modulator.

of 5 dBm, and the baseband signal is 5 MHz with a power of 8 dBm. The measured output is higher than 5 dBm and is obtained from sweeping the baseband input power. The measured and simulated conversion loss and intermodulation ( and spurs) versus the LO frequency from 10 to 50 GHz for the BPSK modulator is plotted in Fig. 13. It shows good agreement between measurement and simulation. Between 15 and 50 GHz, the measured conversion loss is better than 15 dB, the second-order intermodulation components are less than 35 dBc referred to the upper or lower sideband output power, and the third-order intermodulation components are less than 30 dBc. The measured conversion loss versus the baseband frequency from 1 MHz to 6 GHz with an LO frequency of 40 GHz for the BPSK modulator is plotted in Fig. 14, which features a modulation bandwidth of greater than 1 GHz. Therefore, this modulator is suitable for wide-band digital modulation applications. The modulation quality of the BPSK modulation is also measured and shown in [16], which demonstrates an error vector magnitude (EVM) of better than 3.5% and 7% for data rates of 1 and 10 Mb/s, respectively, an adjacent channel power ratio

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Fig. 15. Measured output spectrum of the BPSK modulator at 60 GHz with 1and 2.4488-Gb/s (OC-48) data rates in PRBS.

Fig. 16. Measured output spectrum of the IQ modulator with an LO frequency of 30 GHz and a baseband frequency of 5 MHz.

(ACPR) of less than 40 dBc, and an output channel power of higher than 15 dBm. The BPSK modulator has also been evaluated by a bi-phase multilevel modulation, and the result shows good modulation quality, linearity, and ACPR. For wideband applications, the BPSK modulator is evaluated with 1- and 2.4488-Gb/s (OC-48 standard) data rates in a pseudorandom bit stream (PRBS). The differential baseband signals are generated from an Agilent pattern generator (N4901B series BERT), and the voltage swing of the baseband signal is from 0.2 to 0.8 V. The LO is generated from an Agilent E8247C with an Agilent 83557A MMW source module, and the diver LO power is about 0 dBm. The measured output spectrum of the BPSK at 60 GHz is plotted in Fig. 15, which features good LO suppression and a channel power of higher than 20 dBm for both data rates. The spectrum is spread out due to the unfiltered baseband signals, resulting in a sinc-like spectrum. B. IQ Modulator Fig. 16 shows the measured output spectrum of the IQ modulator with an LO frequency of 30 GHz and a baseband frequency

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Fig. 17. Measured and simulated conversion loss, sideband, and LO suppressions versus the LO frequency from 15 to 40 GHz for the IQ modulator. Fig. 18. Measured intermodulation versus the LO frequency from 15 to 40 GHz for the IQ modulator.

of 5 MHz, where the desired output is the lower sideband (LSB) component and the image output is the upper sideband (USB) component. The measured output power of the modulator signal is 19 dBm when the baseband input of 10 dBm and the LO drive power of 10 dBm are applied to the IQ modulator. The measured image suppression is 39 dBc and the measured LO suppression is 25 dBc. The second-order intermodulation components are less than 33 dBc referring to the desired output power (LSB), and the third-order intermodulation components are less than 44 dBc. The measured output is higher than 10 dBm with a sideband suppression of better than 38 dBc and an LO suppression of better than 25 dBc. The spurs ( and ) suppressions are less than 30 dBc when the modulator is operated at output . The measured and simulated conversion loss, sideband, and LO suppressions versus the LO frequency from 15 to 40 GHz is plotted in Fig. 17 for the IQ modulator. The measured results also agree with the simulated results. Between 20 and 40 GHz, the measured sideband suppression is better than 20 dBc and the measured LO suppression is better than 15 dBc. Since the low-imbalance (amplitude imbalance 0.5 dB and phase imbalance ) band of coupler 2 is narrow, the high sideband suppression ( 40 dBc) occurs only from 27 to 30 GHz. The measured intermodulation ( and ) versus the LO frequency for the IQ modulator is plotted in Fig. 18, which demonstrates a second-order intermodulation of 31 dBc and a third-order intermodulation of 38 dBc from 20 to 40 GHz. For the measurement of the modulation quality, an Agilent E8247C signal generator is used for the LO source because a good phase-noise source is required for the high-level modulation. An Agilent E4448A spectrum analyzer and an Agilent 86 410A vector signal analyzer are used for the vector signal characterization. The baseband signals are generated using Agilent ADS software and downloaded into an Agilent E4438C arbitrary waveform generator. The data frame is also constructed with a PRBS, and some additional digital filters are also utilized to minimize the spectrum spread. The LO drive power is about 10 dBm and the baseband overall input power, including IP, IN, QP, and QN, is about 10 dBm. At an LO frequency of 30 GHz,

Fig. 19. Measured constellation diagram of the IQ modulator at 30 GHz with a 54-Mb/s OFDM modulation (reference constellations: , recovery symbols: , EVM , data: 64-QAM, pilot: BPSK).



< 3%

Fig. 20. Measured output spectrum of the IQ modulator at 30 GHz with a 54-Mb/s OFDM modulation; the channel power is about 18 dBm with a channel bandwidth of 20 MHz.

0

the IQ modulator is evaluated by a 64-QAM modulation with a data rate of 6 Mb/s. The measured modulation quality (EVM) of

CHANG et al.: DESIGN AND ANALYSIS OF CMOS BROAD-BAND COMPACT HIGH-LINEARITY MODULATORS

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TABLE II COMPARISON OF PREVIOUSLY REPORTED CONVENTIONAL REFLECTION-TYPE BPSK/IQ MODULATORS AND THIS WORK

64-QAM is less than 1.8% with a phase error of within 1 and an amplitude error of within 1%. The measured ACPR is better than 50 dBc with a channel power of higher than 18 dBm. For wide-band applications, the IQ modulator is also evaluated with a 54-Mb/s OFDM modulation signal. The measured constellation diagram of the IQ modulator at 30 GHz is plotted in Fig. 19, which shows a 64-QAM constellation for data signals and a BPSK constellation for pilot signals. The measured EVM of the OFDM modulation is within 3%. The measured output spectrum of the IQ modulator with a 54-Mb/s OFDM modulation is plotted in Fig. 20, which demonstrated a channel power of higher than 18 dBm with a channel bandwidth of 20 MHz and an ACPR of better than 40 dBc. The comparison of previously reported conventional reflection-type BPSK/IQ modulators and this work are summarized in Table II. The modified reflection-type modulators in this paper demonstrate broad RF bandwidth, gigabit modulation bandwidth, good LO-to-RF isolation, high linearity, and ultracompact chip sizes. Compared to the prior work based on GaAs HBT technology [11], this work exhibits better modulation bandwidth, conversion loss, LO-to-RF isolation, and secondand third-order intermodulations and smaller chip size due to the innovative topology and CMOS characteristics. V. CONCLUSION An innovative topology for the reflection-type modulator is proposed and analyzed in this paper, and the modified reflection-type BPSK and IQ modulators are successfully implemented using standard bulk 0.13- m CMOS process with ultra compact chip size. Compared with the conventional reflection-type modulators, these modulators demonstrated low amplitude/phase imbalances and high LO-to-RF isolation (or low dc offset) with broad bandwidth due to the proposed topology. The BPSK modulator demonstrates an RF frequency of 15–75 GHz with good amplitude/phase match. For the IQ modulator, the RF frequency is from 20 to 40 GHz, and it features good sideband, LO, and spur suppressions. The modulators also achieve low conversion loss, gigabit modulation bandwidth, and high linearity. Therefore, they can be further applied to ultrawide-band transmitter applications. Due to

low cost and mass production of the standard bulk CMOS process, it is very attractive for the system integration including digital signal process and front-end RF circuits in a single chip. From this demonstration, the CMOS technology has potential applications in the MMW regime. ACKNOWLEDGMENT The authors gratefully acknowledge the Taiwan Semiconductor Manufacturing Company, Hsinchu City, Taiwan, R.O.C., for the chips fabrication. The authors would also to like to thank Prof. G. D. Vendelin and M.-F. Lei, National Taiwan University, Taipei, Taiwan, R.O.C., for the discussions, and P. Lin, Taiwan Agilent, Taipei, Taiwan, R.O.C., for help with the high-speed data rate measurement. REFERENCES [1] C.-Y. Wu and H.-S. Kao, “A 2-V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator and RF amplifier for GHz RF transmitter applications,” IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 49, pp. 123–134, Feb. 2002. [2] N. Sornin, M. Massel, L. Perraud, and C. Pinatel, “A robust Cartesian feedback loop for a 802.11 a/b/g CMOS transmitter,” in IEEE RFIC Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 145–148. [3] K.-Y. Lee, S.-W. Lee, Y. Koo, H.-K. Huh, H.-Y. Nam, J.-W. Lee, J. Park, K. Lww, D.-K. Jeong, and W. Kim, “Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 43–53, Jan. 2003. [4] P. Zhang, T. Nguyen, C. Lam, D. Gambetta, C. Soorapanth, B. Cheng, S. Hart, I. Sever, T. Bourdl, A. Tham, and B. Razavi, “A direct conversion CMOS transceiver for IEEE 802.11a WLANs,” in IEEE ISSCC Dig., Feb. 2003, pp. 354–355. [5] R. Ahola, A. Aktas, J. Wilson, K. R. Rao, F. Jonsson, H. Isto, A. Brolin, T. Hakala, A. Friman, M. Tuula, J. Hanze, S. Martin, D. Wallner, Y. Guo, T. Lagerstam, L. Noguer, T. Knuuttila, P. Olofsson, and M. Ismail, “A single-chip CMOS transceiver for 802.11 a/b/g wireless LANs,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2250–2258, Dec. 2004. [6] K. Nakajima, T. Sugano, and N. Suematsu, “A 5 GHz-band SiGe-MMIC direct quadrature modulator using a doubly stacked polyphase filter,” in IEEE RFIC Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 409–412. [7] S. A. Maas, The RF and Microwave Circuit Design Cookbook. Boston, MA: Artech House, 1998. [8] D. C. W. Lo, H. Wang, B. R. Allen, G. S. Dow, K. W. Chang, M. Biedenbender, R. Lai, S. Chen, and D. Yang, “Novel monolithic multifunctional balanced switching low-noise amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp. 2629–2634, Dec. 1994.

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[9] T. Lodhi, D. L. Edgar, H. McLelland, S. Ferguson, K. Elgaid, C. R. Stanley, and I. G. Thayne, “A 77 GHz coplanar waveguide MMIC BPSK vector modulator realized using InP technology,” in IEEE Gallium Arsenide Integrated Circuit Symp. Dig., 2000, pp. 183–186. [10] D. S. McPherson and S. Lucyszyn, “Vector modulator for W -band software radar techniques,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 8, pp. 1451–1461, Aug. 2001. [11] H.-Y. Chang, T.-W. Huang, H. Wang, Y.-C. Wang, P.-C. Chao, and C.-H. Chen, “Broad-band HBT BPSK and IQ modulator MMICs and millimeter-wave vector signal characterization,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 3, pp. 908–919, Mar. 2004. [12] Y. Sun and A. P. Freundorfer, “A new overlay coupler for direct digital modulator in GaAs HBT,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 8, pp. 1830–1835, Aug. 2004. [13] H.-Y. Chang, P.-S. Wu, T.-W. Huang, H. Wang, Y.-C. Tsai, and C.-H. Chen, “An ultra compact and broadband 15–75 GHz BPSK modulator using 0.13-m CMOS process,” in IEEE MTT-S Int. Microwave Symp. Dig., Long Beach, CA, Jun. 2005, pp. 41–44. [14] L. M. Franca-Neto, R. E. Bishop, and B. A. Bloechel, “64 GHz and 100 GHz VCO’s in 90 nm CMOS using optimum pumping method,” in IEEE ISSCC Dig., Feb. 2003, pp. 444–445. [15] Sonnet User’s Manual, Release 9.0, Sonnet Software Inc., North Syracuse, NY, May 2003. [16] Y. Fujiki, H. Mandai, and T. Morikawa, “Chip type spiral broadside coupled directional couplers and baluns using low temperature co-fired ceramic,” in Electric Components and Technology Conf., Jun. 1999, pp. 105–110. [17] P.-S. Wu, C.-H. Wang, T.-W. Huang, and H. Wang, “Compact and broadband millimeter-wave monolithic transformer balanced mixers,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 10, pp. 3106–3114, Oct. 2005. [18] H.-C. Lu and T.-H. Chu, “Port reduction methods for scattering matrix measurement of an n-port network,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 6, pp. 959–968, Jun. 2000.

Hong-Yeh Chang (S’02–M’05) was born in Kinmen, Taiwan, R.O.C., in 1973. He received the B.S. and M.S. degrees in electric engineering from National Central University, Chung-Li, Taiwan, R.O.C., in 1996 and 1998 respectively, and the Ph.D. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2004. In 1998, he joined Chunghwa Telecom Laboratories, Taoyuan, Taiwan, R.O.C., where he was involved with the research and development of code-division multiple-access (CDMA) cellular phone systems. From 1999 to 2000, he was with Syncomm Inc., Taoyuan, where he was invovled with the personal access communications system (PACS) radio port and handset design. He is currently a Post-Doctoral Research Fellow with the Graduate Institute of Communication Engineering, National Taiwan University. His research interests include monolithic microwave and millimeter-wave integrated circuit designs, transceiver and power amplifier linearization, and RF signal measurement.

Pei-Si Wu (S’02) was born in Changhua, Taiwan, R.O.C., in 1980. He received the B.S. degree in electric engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2002, where he is currently working toward the Ph.D. degree. His research interests include microwave and millimeter-wave circuit designs.

Tian-Wei Huang (S’91–M’98–SM’02) received the B.S. degree from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1987, and the M.S. and Ph.D. degrees from the University of California at Los Angeles (UCLA), in 1990 and 1993, respectively, all in electrical engineering. In 1993, he joined the TRW RF Product Center, Redondo Beach, CA. His research has focused on the design and testing of monolithic microwave integrated circuits (MMICs) and RF integrated circuits (RFICs). During 1998–1999, he was with Lucent Technologies, working on the local multipoint distribution system fixed wireless systems. From 1999 to 2002, he was involved with the RF/wireless system testing at Cisco Systems. In August 2002, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are MMIC/RFIC design, packaging, and RF system-on-chip integration.

Huei Wang (S’83–M’87–SM’95–F’06) was born in Tainan, Taiwan, R.O.C., on March 9, 1958. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, MI, in 1984 and 1987, respectively. During his graduate study, he was engaged in research on theoretical and numerical analysis of electromagnetic radiation and scattering problems. He was also involved in the development of microwave remote detecting/sensing systems. In 1987, he joined the Electronic Systems and Technology Division, TRW Inc. (now Northrop Grumman), Redondo Beach, CA. He has been an MTS and Staff Engineer responsible for MMIC modeling of computer-aided design (CAD) tools, and MMIC testing evaluation and design, and became the Senior Section Manager of the Millimeter-Wave Sensor Product Section, RF Product Center. In 1993, he visited the Institute of Electronics, National Chiao-Tung University, Hsinchu City, Taiwan, R.O.C., where he taught MMIC-related topics. In 1994, he returned to TRW Inc. In February 1998, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., where he is currently a Professor. Dr. Wang is a member of Phi Kappa Phi and Tau Beta Pi. He was the recipient of the Distinguished Research Award presented by the National Science Council, R.O.C. (2003–2006). He was also elected as the first Richard M. Hong Endowed Chair Professor of National Taiwan University in 2005.

Chung-Long Chang received the B.S. degree in electrical engineering from the Feng-Chia University, Taichong, Taiwan, R.O.C., in 1995. He joined the Taiwan Semiconductor Manufacturing Company, Hsinchu City, Taiwan, R.O.C., in 1995. From 1995 to early 2000, he was involved with the Advanced Module Division’s Dielectric & CMP Department. In early 2000, he joined the Logic Technology Division, where he was invovled with mixed-mode RF groups, and he is now a Section Manager of the Communication Technology Department. He is the champion for MIM/MOM capacitors development including the coordination of RD and FAB module teams, process and product qualification, and technology transfer.

John G. J. Chern received the B.S. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., in 1975, and the M.S. and Ph.D. degrees from the University of California, Berkeley, in 1979 and 1984, respectively, all in electrical engineering. He has been involved with the IC industry throughout his career. His experiences include CMOS and BiCMOS process development, process/device simulation tools development, and EPROM/DRAM/SRAM device design and process development. He joined Taiwan Semiconductor Manufacturing Company, Hsinchu City, Taiwan, R.O.C., in 1993 and is now a Director in Research and Development to lead the development of communication technology including mixed-signal RF CMOS and SiGe BiCMOS.

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Design and Analysis for a Miniature CMOS SPDT Switch Using Body-Floating Technique to Improve Power Performance Mei-Chao Yeh, Student Member, IEEE, Zuo-Min Tsai, Student Member, IEEE, Ren-Chieh Liu, Member, IEEE, Kun-You Lin, Member, IEEE, Ying-Tang Chang, and Huei Wang, Fellow, IEEE

Abstract—A low insertion-loss single-pole double-throw switch in a standard 0.18- m complementary metal–oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the 1dB , the bodyfloating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured 1dB of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured 1dB of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm2 . The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches. Index Terms—Body-floating technique, complementary metal–oxide semiconductor (CMOS) switches, nonlinear model, single-pole double-throw (SPDT).

I. INTRODUCTION

I

N RECENT years, wireless communication systems have undergone explosive growth in complementary metal–oxide semiconductor (CMOS) technology. CMOS technology has been able to meet the more stringent cost constraints inherent in these more diverse mainstream applications. The advantages of silicon CMOS technology for RF and microwave control functions over GaAs are its low-cost structure and its integration potential with RF and silicon MOS-based mixed-signal circuitry. A high-quality microwave switch is a key building block of a RF front end for time-division duplexing (TDD) communication systems. Key figures-of-merit of a transmit/receive (T/R)

Manuscript received May 31, 2005; revised August 31, 2005. The work was supported in part by the Sunplus Technology Company Ltd. and the National Science Council of Taiwan, R.O.C. under Grant NSC 93-2752-E-002-002-PAE, Grant NSC 93-2219-E-002-016, Grant NSC 93-2219-E-002-024, and Grant NSC 93-2213-E-002-033. M.-C. Yeh was with the Graduate Institute of Communication Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C. She is now with the Realtek Semiconductor Corporation, Hsinchu City, Taiwan 300, R.O.C. (e-mail: [email protected]). Z.-M. Tsai and H. Wang are with the Graduate Institute of Communication Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C. (e-mail: [email protected]). R.-C. Liu is with the Realtek Technology Company, Hsinchu City, Taiwan 300, R.O.C. (e-mail: [email protected]). K.-Y. Lin and Y.-T. Chang are with the Sunplus Technology Company Ltd., Hsinchu City, Taiwan 300, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2005.860894

Fig. 1.

Dynamic load line of the: (a) on- and (b) off-state passive FET.

switch include insertion loss, isolation, and power-handling capability measured by the power 1-dB compression point . Recent publications show a trend of implementing T/R switches using the CMOS process [1]–[4]. Switches using high and low substrate resistances in a 0.18- m CMOS process have demonstrated good insertion loss [5], but required a large area of substrate contact to implement a low substrate resistance switch. To achieve such performance, an LC-tuned substrate bias was used [6]. However, the bias network improving the large-signal handling capability increased the chip size significantly. In the meanwhile, the LC-tuned substrate bias network limited the switch in a narrow frequency range. For 2.4- and 5.2-GHz applications, two different switches were designed and the LC-tuned substrate bias networks were needed to be

0018-9480/$20.00 © 2006 IEEE

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Fig. 2. (a) Circuit schematic of a series transistor. (b) The equivalent model in the on state. The simplified equivalent circuit models: (c) without and (d) with body-floating technique.

devised, respectively. An impedance-matching technique was used to improve the of the switch [7], but the matching network also resulted in a large die size. Switch realized by depletion-layer-extended transistors (DETs) obtained high power handling [8]. Nevertheless, the DETs were formed with additional mask steps compared with the standard CMOS process. In order to avoid latching up, the pMOS and n-well must also be placed sufficiently far away from the DETs and, thus, results in a large chip size. An accurate nonlinear CMOS model is needed to predict the power performance. A CMOS RF model for gigahertz communication integrated circuits (ICs) was proposed [9], but it described the power characteristics mainly in the active region of the transistor. A large-signal field-effect transistor (FET) model of a passive high electron-mobility transistor (HEMT) for the switch circuit was presented [10], and the power performance of the series-shunt switch can be predicted accurately in the heterojunction field-effect transistor (HJFET) monolithic-microwave integrated-circuit (MMIC) process. In this paper, the body-floating technique is used to improve the power performance of the switch. To implement this technique in a CMOS switch, the body of the device is connected to ground with a 5-k resistor. This simple implementation can increase the power-handling capability in a wide-band frequency range with a small chip size [11]. An RF single-pole doublethrow (SPDT) switch in a standard 0.18- m CMOS process is presented. In order to investigate the power limitation of the transistors, a nonlinear CMOS model is developed to predict the power performance of the SPDT switch. This SPDT switch exhibits 0.7-dB insertion loss, 35-dB isolation, and 21.3-dBm input at 2.4 GHz and 1.1-dB insertion loss, 27-dB isolation, and 20-dBm input at 5.8 GHz. Compared with the previously published CMOS switches [1]–[8], this chip accomplished low insertion loss, high isolation, good power performance, and smallest chip size simultaneously. II. BODY-FLOATING TECHNIQUE In order to increase the power performance of the switch, the reasons for power limitation of CMOS devices are first investigated. Fig. 1(a) and (b) shows the dynamic load lines of a shunt passive FET in the on and off states, respectively. The equivalent-circuit model of an on-state transistor is a small resistor, which has the dynamic load line along the I–V curve, as shown in Fig. 1(a). The larger swing range of the dynamic load line

follows the large input power. The input impedance is changed when the dynamic load line approaches the maximum current, and limits the power-handling capability. For the off-state transistor, it is represented as a small capacitor series with a small resistor. For small input power, the drain-to-source current is almost zero when the transistor turns off. The dynamic load line is shown in Fig. 1(b). When the input power increases, the dynamic load line approaches the breakdown voltage and, thus, the input impedance is changed and power performance is degraded. In order to improve the power performance of the CMOS switch, the body-floating technique is used. Fig. 2(a) shows the circuit schematic of a series transistor, and the equivalent-circuit model in the on state is presented in Fig. 2(b). For a conventional switch, the body of the transistor is connected to the source, and the equivalent-circuit model is shown as Fig. 2(c). When the input power increases, the drain-to-source voltage is so negative as to turn on the diode between drain and body, and the input impedance of the transistor is lower. Using the body-floating technique, the body of the transistor is connected to ground with a 5-k resistor, and the equivalent-circuit model is illustrated in Fig. 2(d). Since the resistance connected to ground is very high compared to , the input impedance of the transistor still remains the same as . Fig. 3(a) shows the circuit schematic of a shunt transistor, and the equivalent-circuit model in the off state is shown in Fig. 3(b). Without the body-floating technique, the high input power will turn on the diode between body and drain, and the current from ground to drain increases quickly. The high current will change the input impedance of the transistor, and degrade the power performance, as shown in Fig. 3(c). Fig. 3(d) demonstrates the equivalent-circuit model of the off-state transistor with the body floating. When the input power is high, the diode between drain and body still turns on. Since the resistance between body and ground is very high, the current from ground to drain increases smoothly. Fig. 4 presents the measured dc–IV curves of a 60- m transistor with and without using the body-floating technique. As can be observed, the negative drain current occurs much later in the off state when the body-floating technique is applied. That means the input impedance of the transistor with the body-floating technique is barely influenced with the high input power, and the power-handling capability is improved. On the other hand, the power performance is limited by the maximum

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Fig. 3. (a) Circuit schematic of a shunt transistor. (b) The equivalent model in the off state. The simplified equivalent circuit models: (c) without and (d) with body-floating technique.

Fig. 4. DC–IV curves of a 60-m transistor with and without using body-floating technique.

current when the device is in the on state. In the case of a 60- m device, the differences between the dc–IV curves are not obvious in the positive drain-to-source voltage region. Therefore, when the power performance of the switch is limited by the shunt transistor, which is in the off state, the body-floating technique can increase the power-handling capability of the switch effectively. This will be explained using the load-line analysis in Section III. The SPDT switch is fabricated in a 0.18- m CMOS process. To implement the body-floating technique, the body is connected to ground with a 5-k resistor, as shown in Fig. 5. A deep n-well (DNW) is offered as default in the 0.18- m mixed-signal process for better substrate isolation with an additional PN junction [12]. In this study, the DNW is used to completely separate the body of the transistor with a p-substrate using the body-floating technique. Due to the DNW, there are no parasitic bipolar junction transistors (BJTs) and, thus, the switch can get rid of latching up. III. SPDT SWITCH DESIGN By using the body-floating technique, the performances of the CMOS switch can be improved. Fig. 6 is the schematic of the series-shunt CMOS RF SPDT switch, which comprises two series and two shunt transistors. The series transistors M1 and M2 perform the main switching function, and the shunt transistors M3 and M4 increase the isolation of the switch. It is observed that the ratio of the size for the series to shunt transistor significantly

Fig. 5. Simple structure of DNW.

Fig. 6. Series-shunt switch schematic diagram.

influences the performances of the switch, especially for the insertion loss. Fig. 7(a) presents the simulated relations between the insertion loss (in decibels) and the gatewidth of series and shunt transistors, while the relations between isolation (in decibels) and the sizes are shown in Fig. 7(b). As can be observed, the sizes of the series and shunt transistors must be selected properly. In order to achieve a low insertion loss, there are two options: one is to use a large size for the series transistor and a small size for the shunt one, and the other is simply the opposite, i.e., to select a small size for the series device and a large size for the shunt one. Since the insertion losses of the two cases are similar, isolation and power-handling capability will be taken into consideration. Fig. 8 illustrates the dc–IV curves of a 60and a 180- m transistor. As can be observed, in the on state, the larger device has the higher maximum current and, thus,

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Fig. 7. Relationships between the sizes of the transistors and: (a) insertion loss and (b) isolation of the SPDT switch. Fig. 9. DC–IV curves and dynamic load lines of a: (a) 180-m series on-state and (b) 60-m shunt off-state transistor.

power is 19 dBm, the dynamic load line of the 180- m series on-state transistor is still within the linear region of the dc–IV curve [see Fig. 9(a)], while the dynamic load line of the 60- m shunt off-state transistor has been clamped by the nonlinear portion of the dc–IV curve [see Fig. 9(b)]. This explains that the shunt transistor limits the power performance of the switch. IV. NONLINEAR RESISTIVE CMOS MODEL

Fig. 8.

DC–IV curves of a 60- and a 180-m transistor.

the power-handling capability is better. On the other hand, in the off state, the smaller device has less negative current, which leads to a better power-handling capability. For the concern of power-handling capability, large devices are used for series transistors, while a small size is used for the shunt ones. Since there are tradeoffs in device size selection for the insertion loss, isolation, and power-handling capability, large devices of 180- m gatewidth are selected for series transistors M1 and M2, while the sizes of shunt transistors M3 and M4 are both 60 m in the design. The gate bias resistors , , , and are 5 k to improve the dc-bias isolation. The simulated dynamic load lines are illustrated in Fig. 9. The dynamic load lines are plotted along the dc–IV curves for a 180- m series on-state and a 60- m shunt off-state transistor, respectively. When the input

The resistive CMOS model is nonlinear model operating at zero drain-to-source voltage and suitable for the passive CMOS switches. The maximum power for the switching operation would be expressed by the CMOS parameters such as the saturation drain current at V and the drain breakdown voltage in the pinched-off state. In the large-signal operation, the drain voltage swings to the negative region. Therefore, the characteristics of the negative drain–voltage region must be included in the nonlinear model for the switch applications. A large-signal CMOS model for the switch circuit is presented in Fig. 10. In the model, the FET can be expressed as the parallel combination of a capacitor series with a small resistor and a current source. The current equations of the current source describe saturation current, knee voltage, and breakdown voltage. The model is based on the Angelov model [13]. To study the two-port model easily, a simple hyperbolic tangent current model is employed. Four main current source equations are used to describe the on- and off-state transistors. In the on state with V, the drain current is described as (1)–(4)

YEH et al.: DESIGN AND ANALYSIS FOR MINIATURE CMOS SPDT SWITCH

Fig. 10.

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Nonlinear model of the FET. TABLE I PARAMETER VALUES FOR LARGE-SIGNAL MODEL

Fig. 11. device.

DC–IV curves comparison of measurement and model for a 60-m

Fig. 12. Measured phase of S conditions in on state.

of a shunt 60-m device for the different bias

(3) (4) (5) (6) (7)

and, in the off state, with V, the drain current is as shown in (5)–(7). Two series of parameters of a 180- and 60- m transistors are extracted. The values of the parameters of the CMOS nonlinear model are listed in Table I. In order to simplify the nonlinear model, some coefficients such as , , etc. are omitted. It is observed the simplified nonlinear model still can describe the power performance of the device accurately as follows:

(1) (2)

When the input power varies, the gate-to-source voltage of the transistor changes simultaneously. The dc–IV curves of different from 1.4 to 2 V in the on state and 2.2 to 1.4 V in the off state are described in the nonlinear model. Fig. 11 demonstrates the dc–IV curves of a 60- m transistor. The lines with markers are the calculated results of the nonlinear model, while the solid lines present the measurements. The measured and calculated results are in good agreement. The capacitance for is the combination of the parasitic capacitances between drain, gate, source, and body. In the on state, the input impedance is dominated by , and is almost the same in different bias conditions. Fig. 12 shows the measured phase of of a shunt 60- m transistor with different values of and . As can be observed, when the gate voltage and the drain-to-source voltage change, the phases of of the device are similar. In the off state, changes when the drain-to-source voltage swings. However, in the low-frequency

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Fig. 13. Measured phase of condition in off state.

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S

of a shunt 60-m device for different bias

Fig. 15. Die photograph of 0.18-m CMOS switch. The effective circuit area without pads is only 0.03 mm .

Fig. 16. Simulated and measured insertion loss and isolation of the 0.18-m CMOS switch. It achieves a 1.1-dB insertion loss and 27-dB isolation at 5.8 GHz.

V. MEASUREMENT RESULTS

Fig. 14. S of measurement and simulation by nonlinear model for a shunt 60-m transistor. In the on state, V is 1.8 V, while V is 1.8 V in the off state.

0

range, the difference is not obvious. Fig. 13 demonstrates the measured phase of of a shunt 60- m transistor with different drain-to-source voltages at 5.8 GHz. The variations of phases between different bias conditions are less than 3 with gate voltage fixed at 1.8 V. In order to simplify the nonlinear model, the capacitor of the model is assumed not to vary with the dc bias of the transistor. In the TSMC 0.18- m CMOS process, the values of are 0.15 and 0.05 pF for 180- and 60- m devices, respectively, with an of 5 . Fig. 14 shows the of measurement and simulation with the nonlinear model for a shunt 60- m transistor in the on and off states from dc to 50 GHz. The simulated results by the nonlinear model agree with the measurements very well.

This CMOS SPDT switch is implemented using commercial standard 0.18- m MS/RF CMOS technology, which provides one poly layer for the gate of the MOS and six metal layers for inter-connection [14], [15]. The substrate conductivity is approximately 10 S/m. With optimized CMOS technology and DNW, this technology provides and of higher than 60 and 55 GHz, respectively. The die micrograph of the series-shunt SPDT switch using a 0.18- m CMOS process is shown in Fig. 15. The chip size is 0.53 0.37 mm and the effective circuit area without pads is only 0.2 0.15 mm . The circuit was tested via on-wafer probing. As shown in Fig. 16, the series-shunt switch achieves an insertion loss of 0.7 dB and an isolation of 35 dB at 2.4 GHz. It also achieves an insertion loss of 1.1 dB and an isolation of 27 dB at 5.8 GHz. Fig. 17 shows the simulated and measured I/O return losses of the switch versus frequency. The I/O return losses are both better than 10 dB below 6 GHz. Fig. 18 presents the measured insertion losses versus input power of the switches with/without body-floating technique at 2.4 and 5.8 GHz. When the dc bias of the Tx and Rx nodes shown in Fig. 6 is 0 V, and is 1.8 and 1.8 V, respectively, the switch using a 0.18- m device achieves a of 21.3 dBm at 2.4 GHz

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Fig. 17. switch.

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Simulated and measured I/O return losses of the 0.18-m CMOS

Fig. 19. Simulated and measured P versus P of the SPDT switch at: (a) 2.4 and (b) 5.8 GHz. The simulation is performed by using the nonlinear model introduced in Section IV.

TABLE II MEASURED PERFORMANCE SUMMARY OF THE SPDT SWITCH

Fig. 18. Insertion loss versus P of the 0.18-m CMOS switch at: (a) 2.4 and (b) 5.8 GHz. Using the body-floating technique, the P of the switch is improved 2 dB.

and a of 20 dBm at 5.8 GHz. Using devices of the same sizes, another SPDT switch without the body-floating technique achieves a of 19 dBm at 2.4 GHz and a of 18 dBm at 5.8 GHz. The of the switch is improved 2 dB by using the body-floating technique. Fig. 19 shows the simulated and measured versus of the SPDT CMOS switch with the body-floating technique. The simulated input of the switch is 21 dBm with the nonlinear model described in Section IV at 2.4 GHz, while the simulated input is 24.5 dBm with the BSIM3 models [12]. At 5.8 GHz, by using the nonlinear model described in Section IV, the simulated input of the switch

is 21 dBm, compared with the 25-dBm simulated input with the BSIM3 models, the nonlinear model can predict the power performance more accurately. High power performances of the switches in [6] and [8] are achieved by using the large transistors and asymmetric topologies at the cost of the higher insertion loss and lower isolation in the receive path. This switch with the body-floating technique attains low insertion loss, high

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TABLE III RECENTLY REPORTED PERFORMANCES OF 5–6-GHz CMOS SWITCHES

isolation, and good power performance in the transmit and receive paths simultaneously. Table II summaries the measured performances of the SPDT switch at 2.4 and 5.8 GHz.

VI. CONCLUSIONS The body-floating technique has been used to increase the power-handling capability of the CMOS switch. In order to investigate the power performance of the switch, a nonlinear CMOS model for describing the power-handling capability has been developed. Based on the nonlinear model, the transistor size can be properly selected for high-power performance. An SPDT switch using a 0.18- m CMOS process was designed, fabricated, and measured. The series-shunt switch achieves an insertion loss of 0.7 dB, an isolation of 35 dB, and a of 21.3 dBm at 2.4 GHz. This switch also exhibits 1.1-dB insertion loss, 27-dB isolation, and 20-dBm input at 5.8 GHz. Table III presents the recently reported performances of 5–6-GHz CMOS switches. The switch with the body-floating technique accomplishes low insertion loss, high isolation, good power performance, and smallest chip size simultaneously. Moreover, the newly developed nonlinear model can predict the power performance of the switch more accurately than the BSIM3 model.

ACKNOWLEDGMENT The authors would like to thank Dr. H.-Y. Chang and C.-S. Lin, both with the National Taiwan University, Taipei, Taiwan, R.O.C., for their valuable suggestions.

REFERENCES [1] F.-J. Huang and K. O, “A 0.5-m CMOS T/R switch for 900-MHz wireless applications,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 486–492, May 2000.

[2] A. Ajjikuttira, C. Lrung, E.-S. Khoo, M. Choke, and R. Singh, “A fullyintegrated CMOS RFIC Bluetooth application,” in IEEE Int. Solid-State Circuits Conf. Dig., San Franciso, CA, Feb. 2001, pp. 198–199. [3] K. K. O, X. Li, F.-J. Huang, and W. Foley, “CMOS components for 802.11b wireless LAN applications,” in IEEE RFIC Symp., Seattle, WA, Jun. 2002, pp. 103–106. [4] M. Madihian, L. Desclos, and T. Drenski, “CMOS RF IC’s for 900 MHz–2.4 GHz band wireless communication networks,” in IEEE RFIC Symp., Anaheim, CA, Jun. 1999, pp. 13–16. [5] Z. Li, H. Yoon, F.-J. Huang, and K. K. O, “5.8-GHz CMOS T/R switches with high and low substrate resistances in a 0.18-m CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 13, no. 1, pp. 1–3, Jan. 2003. [6] N. A. Talwalkar, C. P. Yue, H. Gan, and S. S. Wong, “Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 863–870, Jun. 2004. [7] F.-J. Huang and K. K. O, “Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p-silicon substrates,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 35–41, Jan. 2004. [8] T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. T. H. Ueda, N. Suematsu, and T. Oomori, “21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs),” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 577–584, Jan. 2004. [9] J.-J. Ou, X. Jin, I. Ma, C. Hu, and P. R. Gray, “CMOS RF modeling for GHz communication IC’s,” in VLSI Circuits Symp. Dig., Honolulu, HI, Jun. 1998, pp. 94–95. [10] H. Mizutani, M. Funabashi, M. Kuzuhara, and Y. Takayama, “Compact DC–60-GHz HJFET MMIC switches using ohmic electrode-sharing technology,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 11, pp. 1597–1603, Nov. 1998. [11] M.-C. Yeh, R.-C. Liu, Z.-M. Tsai, and H. Wang, “A miniature low-insertion-loss, high-power CMOS SPDT switch using floating-body technique for 2.4- and 5.8-GHz applications,” in IEEE RFIC Symp., Long Beach, CA, Jun. 2005, pp. 451–454. [12] “0.18 m mixed signal 1P6M MIM salicide 1.8 V/3.3 V design guideline,” TSMC, Hsinchu City, Taiwan, R.O.C., 2000. [13] I. Angelov, H. Zirath, and N. Rorsman, “A new empirical model for HEMT and MESFET devices,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 12, pp. 2258–2268, Dec. 1992. [14] H. M. Hsu, J. Y. Chang, J. G. Su, C. C. Tsai, S. C. Wong, C. W. Chen, K. R. Peng, S. P. Ma, C. H. Chen, T. H. Yeh, C. H. Lin, Y. C. Sun, and C. Y. Chang, “A 0.18-m foundry RF CMOS technology with 70-GHz ft for single chip system solutions,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, May 2001, pp. 1869–1872. [15] C. H. Diaz et al., “A 0.18-m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications,” in IEEE VLSI Tech. Symp., Kyoto, Japan, Jun. 1999, pp. 11–12.

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YEH et al.: DESIGN AND ANALYSIS FOR MINIATURE CMOS SPDT SWITCH

Mei-Chao Yeh (S’03) was born in Kaohsiung, Taiwan, R.O.C., on January 10, 1981. She received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2003, and the M.S. degree from the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2005. She is currently an Engineer with the Realtek Semiconductor Corporation, Hsinchu City, Taiwan, R.O.C. Her research interests are in the areas of RF and millimeter-wave ICs in CMOS technologies.

Zuo-Min Tsai (S’01) was born in Mailo, Taiwan, R.O.C., in 1979. He received the B.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, R.O.C., 2001, and is currently working toward the Ph.D. degree at National Taiwan University. His research interests are the theory of microwave circuits.

Ren-Chieh Liu (S’01–M’05) was born in ChangHua, Taiwan, R.O.C., on September 2, 1975. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, R.O.C., in 1997, 2000 and 2004, respectively. He is currently an Engineer with the Realtek Semiconductor Corporation, Hsinchu City, Taiwan, R.O.C. His research interests include CMOS RF ICs, microwave monolithic ICs, and communication system circuits.

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Kun-You Lin (S’00–M’04) was born in Taipei, Taiwan, R.O.C., in 1975. He received the B.S. degree in communication engineering from National Chiao Tung University, Hsinchu City, Taiwan, R.O.C., in 1998, and the Ph.D. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2003. From August 2003 to March 2005, he was a Post-Doctoral Research Fellow with the Graduate Institute of Communication Engineering, National Taiwan University. He is currently an Advanced Engineer with the Sunplus Technology Company Ltd., Hsinchu City, Taiwan, R.O.C. His research interests include the design and analysis of microwave/RF circuits. Dr. Lin is a member of Phi Tau Phi.

Ying-Tang Chang was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. degree in communication engineering from National Chiao Tung University, Hsinchu City, Taiwan, R.O.C., in 1999, and the M.S. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. Since October 2001, he has been with the Sunplus Technology Company Ltd., Hsinchu City, Taiwan, R.O.C., where he is an Advanced Engineer engaging in CMOS/BiCMOS RFIC design.

Huei Wang (S’83–M’87–SM’95–F”06) was born in Tainan, Taiwan, R.O.C., on March 9, 1958. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, MI, in 1984 and 1987, respectively. During his graduate study, he was engaged in research on theoretical and numerical analysis of electromagnetic radiation and scattering problems. He was also involved in the development of microwave remote detecting/sensing systems. In 1987, he joined the Electronic Systems and Technology Division, TRW Inc. He has been an MTS and Staff Engineer responsible for MMIC modeling of computer-aided design (CAD) tools, and MMIC testing evaluation and design, and became the Senior Section Manager of the Millimeter-Wave Sensor Product Section, RF Product Center. In 1993, he visited the Institute of Electronics, National Chiao-Tung University, Hsinchu City, Taiwan, R.O.C., where he taught MMIC-related topics. In 1994, he returned to TRW Inc. In February 1998, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., where he is currently a Professor. Dr. Wang is a member of Phi Kappa Phi and Tau Beta Pi. He was the recipient of the Distinguished Research Award presented by the National Science Council, R.O.C. (2003–2006). He was also elected as the first Richard M. Hong Endowed Chair Professor of National Taiwan University in 2005.

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Development of Multiband Phase Shifters in 180-nm RF CMOS Technology With Active Loss Compensation Chao Lu, Student Member, IEEE, Anh-Vu H. Pham, Senior Member, IEEE, and Darrell Livezey

Abstract—We present the design and development of a novel integrated multiband phase shifter that has an embedded distributed amplifier for loss compensation in 0.18- m RF CMOS technology. The phase shifter achieves a measured 180 phase tuning range in a 2.4-GHz band and a measured 360 phase tuning range in both 3.5- and 5.8-GHz bands. The gain in the 2.4-GHz band varies from 0.14 to 6.6 dB during phase tuning. The insertion loss varies from 3.7 dB to 5.4-dB gain and 4.5 dB to 2.1-dB gain in the 3.5- and 5.8-GHz bands, respectively. The gain variation can be calibrated by adaptively tuning the bias condition of the embedded amplifier to yield a flat gain during phase tuning. The return loss is less than 10 dB at all conditions. The chip size is 1200 m 2300 m including pads. Index Terms—CMOS analog integrated circuits distributed amplifiers, phase shifters, phased arrays.

(ICs),

I. INTRODUCTION

M

ULTIPLE input and multiple output (MIMO) transceivers have recently gained attention for the development of broad-band wireless applications. As a special case of MIMO, adaptive phased-array antennas can effectively combat co-channel interferences and deal with multipath fading [1]. By controlling the time delay and gain of the signal in each antenna independently, phased-array antennas can form beams and nulls in desired directions. This kind of beamforming improves antenna gain to yield higher signal-to-noise ratio and provides spatial diversity for higher data rate transmission. RF phase shifters are key elements of analog phased-array antennas and have been mostly implemented in GaAs integrated circuits (ICs). Recently, Si-based RF phase shifters have emerged as a new platform for wireless integrated transceivers [2]–[5]. Both digital and analog phase shifters have been demonstrated in RF silicon ICs. A 6-bit digital phase shifter was reported in SiGe technology over a 7–11-GHz frequency band [2]. A dual-band 5.2/2.4-GHz 4-bit phase shifter designed by combining two single-band phase shifters was reported in [3]. Low- factor passive devices and a small tuning ratio of varactor capacitance (typically 2 4) in CMOS represent challenges in the implementation of multiband continuous phase Manuscript received April 22, 2005; revised August 30, 2005. This work was supported in part by UC MICRO, by Tahoe RF Semiconductor Inc., and by the National Science Foundation under Contract ECS-0401375. C. Lu and A.-V. H. Pham are with the Department of Electrical and Computer Engineering, University of California at Davis, Davis, CA 95616 USA (e-mail: [email protected]; [email protected]). D. Livezey is with Tahoe RF Semiconductors Inc., Auburn, CA 95602 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2005.860892

Fig. 1. Circuit topology of a multiband phase shifter with broad-band active loss compensation.

shifters with low loss and large phase tuning ranges. A continuous phase shifter with a 105 phase tuning range at 2.4 GHz has recently been reported in 0.18- m CMOS technology [4]. A 360 phase shifter at 8 GHz consuming 170 mW of power was proposed in [5] by embedding a varactor-tuned LC ladder network between driving amplifiers. In this paper, we present the development of a multiband RF CMOS phase shifter that employs a distributed amplifier for loss compensation since the conventional loss compensation methods, such as negative resistance [4], become ineffective for broad-band and multiband applications. In this phase shifter, two varactor-tuned LC networks have been designed to provide both phase shifting and broad-band impedance matching. The impedance-matching networks allow the distributed amplifier to have high input and output impedance for the reduction of power consumption. The distributed amplifier compensates loss from 2.4 to 6 GHz and provides the calibration of gain variation. The phase shifter achieves a measured continuous 180 and 360 phase tuning at 2.4- and 3.5/5.8-GHz bands, respectively. The gain is as high as 6.6 dB without calibration and the return loss is less than 10 dB from 2.4 to 6 GHz. The phase shifter requires only one phase control bias and, therefore, one digital-to-analog converter (DAC). To the best of our knowledge, this is the first multiband continuous phase shifter reported in RF CMOS. Section II describes the architecture of the proposed embedded amplifier topology. The detailed analysis of distributed amplifiers and phase transmission functions are presented. Section III describes the prototype implementation and measurements of the multiband phase shifter. II. PHASE-SHIFTER CIRCUIT TOPOLOGY Fig. 1 illustrates the multiband phase shifter that has a distributed amplifier for broad-band loss compensation. The proposed topology in this design yields significant loss compensation with less power consumption by increasing the characteristic impedance of gate and drain lines of the distributed amplifier to be above 50 . Varactor-tuned LC networks are employed

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LU et al.: DEVELOPMENT OF MULTIBAND PHASE SHIFTERS IN 180-nm RF CMOS TECHNOLOGY

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Fig. 2. Cascaded single-stage distributed amplifier.

to achieve a compact chip size and to provide broad-band 50matching and phase tuning. Though the internal characteristic impedance of the distributed amplifier is , the input and output impedances of the whole phase-shifter circuit are maintained to be around 50 during phase tuning. A. Distributed Amplifiers In distributed amplifiers, gain stages are connected so that output currents are combined coherently while their capacitances are synthesized in parallel to form artificial transmission lines, namely, gate and drain lines. The artificial transmission-line topology gives distributed amplifiers a wide bandwidth. Due to its gain advantage over conventional distributed amplifiers, a cascaded single-stage distributed amplifier [6]–[8] is employed in this design. When the operation frequency is far below the cutoff frequency, the gain of a distributed amplifier with cascaded single stages is simplified as [6]

Fig. 3. Schematic diagram of varactor-tuned LC network.

B. Varactor-Tuned LC Network Fig. 3(a) shows a conventional varactor-loaded transmissionline phase shifter, where several lumped-element -sections are cascaded to implement an equivalent transmission line for the compact chip size. Similar to that in [9], the transmission phase of a single -section can be derived as

(2)

When tions is

, the transmission phase of

-sec-

(1) (3) is the transconductance of each stage, and and where are the characteristic impedances of gate and drain artificial transmission lines, respectively. To enhance gain, the number of stages ( ) or the transconductance of each stage can be increased with a penalty of more power consumption. Furthermore, the gain can also be increased by designing high interstage impedances, but significantly sacrificing bandwidth [8]. Our strategy is to increase the characteristic impedances ( ) of gate and drain lines at the input and output of the amplifier to achieve high gain, while the inter-stage impedances are maintained at the intermediate level, i.e., 100 . If we define the impedance transformation ratio , the power consumption of distributed amplifiers can be theoretically reduced by times for the same gain compared with for design. We have chosen for both and to balance power consumption and bandwidth. Fig. 2 shows a three-stage cascaded single-stage distributed amplifier where the gate/drain characteristic impedances are designed to be equally 100 and the gate/drain parasitic capacitances of transistors are adopted into the artificial transmission lines. The simulated results show that the distributed amplifier can yield 14–15-dB gain up to 8 GHz. The distributed amplifier draws maximum 25-mA current from 1.8-V power supply and, therefore, the maximum power consumption is 45 mW.

where

is the operation frequency. The group delay is then (4)

This group delay is independent on frequency and is referred as a true time delay, and this delay can be adjusted by changing inductance or capacitance or both. Therefore, varactor-load transmission-line phase shifters are also suitable for broad-band applications [10]. For a given capacitance tuning ratio , which is defined to be , the relative phase shifting is controlled by varying the capacitance . The relative transmission phase tuning range is

(5) We can see that the phase tuning range increases with the section number . For a typical silicon-based varactor, the capacitance tuning ratio is typically 2 4. To reach a symmetrical variation, we specify [11]

(6)

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Fig. 4. Peak Q frequency of spiral inductors and cutoff frequency of  -sections in 180-nm RF CMOS technology.

Assuming

, we obtain

(7)

parameter variations resulting from device mismatching. Each varactor-tuned LC network in Fig. 1 is composed of the circuit shown in Fig. 3(b). The input varactor-tuned LC network transforms 50 to , and the output one transforms to 50 . These two varactor-tuned LC networks employ an identical architecture and can share one control voltage because of the symmetry. C. Hyperabrupt (HA) Varactor

At these worst conditions, the return loss is calculated as dB

Fig. 5. Tuning capacitance of MOS varactors and HA varactors at 3 GHz.

(8)

This indicates that the phase shifter can achieve a good impedance matching through the full phase tuning range. From (5), we can also see that the phase tuning range will increase as the inductance value increases in each section. However, a larger nominal capacitance value of varactors is required to maintain the characteristic impedance around and, therefore, the cutoff frequency of the -sections is degraded, as shown in Fig. 4. This figure also indicates the peak quality factor ( ) frequency of spiral inductors drops as the inductance increases. To alleviate the effect of parasitic capacitance related with spiral inductors and satisfy the condition of , we chose the inductance nH and, therefore, pF. At these conditions, pF and pF. The desired phase tuning range can be achieved by appropriately designing section number . The section number should be at least 20 to yield 360 phase tuning range at 3.5 GHz. One contribution of this study is to design a varactor-tuned LC network that provides both phase shifting and broad-band matching. To provide broad-band impedance matching, three-section Chebyshev impedance transformers [12] [see Fig. 3(b)] have been designed, and each section is composed of an equal “length” lumped varactor-loaded transmission line [see Fig. 3(a)]. Each section has a different characteristic impedance, i.e., 57.4, 70.7, and 87.1 , which are determined by Chebyshev polynomials. Since the frequency band of interest is 2–6 GHz, we chose GHz in the design of multisection Chebyshev transformers. The three-section Chebyshev transformer has 12 lumped -sections and, therefore, 12 inductors. All inductors are kept uniformly to be 1.0 nH, and all capacitors are comprised of the same unit varactor with different multipliers. Therefore, the circuit is insensitive to

RF CMOS technology typically offers two options for varactor implementation: MOS accumulation varactors and HA junction varactors. The HA varactor utilizes a retrograde implant to modify a standard pn junction that results in a nonlinear n-type dopant across the depletion region. As the reverse bias is increased, the nonlinear doping profile causes a greater capacitance change in the HA junction diode and greatly enhances the tunability and linearity [13]. HA varactors have a larger tuning ratio and better capacitance–voltage (CV) linearity compared with MOS varactors, as shown in Fig. 5. The linear capacitance control property relaxes the resolution requirement on DACs. The tuning ratio of HA varactors is as high as 5 with the control voltage changing from 0 to 7 V. However, as the control voltage approaches at a high value, the linearity of capacitance versus control voltage is degraded. In this design, the control voltage from 0 to 4.5 V is chosen to result in a tuning ratio of 4. D. Gain Variation Calibration to yield difAs varactors are tuned and controlled by ferent phases, the quality factor of the varactors and the cutoff frequency of varactor-tuned LC networks will vary and cause changes in the insertion loss of the phase shifter. Generally, this kind of gain shift, as well as that resulting from temperature drifting needs to be calibrated in most applications [14], and the calibration is conventionally performed through a variable attenuator. Our proposed architecture provides an option for gain calibration by adaptively adjusting the bias condition of the embedded amplifier, as indicated by (1). For the operation frequencies far less than the cutoff frequency of the artificial gate and drain transmission lines, the transmission phase of the distributed amplifier is independent on the bias condition, as long as all transistors are maintained in the saturation region. Therefore, the gain (loss) calibration will not impact the transmission phase of the phase shifter. The calibration can be conducted to yield a flat gain by using a simple lookup table [3].

LU et al.: DEVELOPMENT OF MULTIBAND PHASE SHIFTERS IN 180-nm RF CMOS TECHNOLOGY

Fig. 6.

Die photograph of the multiband phase shifter in 0.18-m RF CMOS.

Fig. 8.

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Measured transmission phase at 2.4, 3.5, and 5.8 GHz.

TABLE I COMPARISON OF PHASE TUNING RANGE WITH V

Fig. 7.

FROM 0 TO 4.5 V

Measured: (a) input return loss and (b) output return loss.

III. MEASUREMENT RESULTS OF PHASE SHIFTERS The novel phase shifter was implemented in IBM 180-nm RF CMOS. The varactor-tuned LC networks are on the left- and right-hand sides, while the embedded distributed amplifier is in the middle of the chip. The chip size is 2.3 mm 1.2 mm including pads. As shown in Fig. 6, the grounding path and all biases are connected onto an evaluation board using bond wires. A.

-Parameter Measurements

-parameter measurements were conducted at room temperature using a Cascade Microtech probe station and an Agilent E8364B Performance Network Analyzer. Fig. 7 shows that the measured return loss is less than 10 dB from 2.4 to 6 GHz with control voltage tuning from 0 to 4.5 V. The measurements are focused on three frequency bands, i.e., 2.4–2.48, 3.4–3.5, and 5.73–5.83 GHz, and the measured relative phase tuning ranges with from 0 to 4.5 V are 220 , 360 , and 660 , respectively (Fig. 8). The measured

Fig. 9.

Measured S

in 2.4-GHz frequency band.

phase tuning ranges are consistent with those in the simulation, as compared in Table I. Fig. 8 indicates a nearly linear relationship between the relative phase shifting and , as predicted in Section II. For narrow-band applications, the phase variation at a given control voltage versus operation frequency is an important specification for continuous phase shifters. The phase variation versus frequency determines the achievable resolution and, therefore, the performance of phased array antennas. The -parameter measurements show that the phase variation for 20-MHz bandwidth is 3 , and the gain ripple within the same bandwidth is less than 0.1 dB, as shown in Figs. 9–11. The results shown below are based on the measurements with the 180 and 360 continuous phase tuning ranges in 2.4- and 3.5/5.8-GHz bands, respectively.

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Fig. 10.

Fig. 11.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006

Measured S

Measured S

Fig. 12.

Calibration results at 2.4 GHz.

Fig. 13.

Calibration results at 3.5 GHz.

Fig. 14.

Calibration results at 5.8 GHz.

in 3.5-GHz frequency band.

in 5.8-GHz frequency band.

Fig. 9 shows that the relative phase tuning range is 180 in the 2.4-GHz band as changes from 0.1 to 3.0 V, and the gain varies from 0.1 to 6.6 dB. This result indicates that the insertions loss caused by lossy CMOS passive devices has been significantly compensated. The phase tuning range in the 3.5-GHz band is 360 as changes from 0 to 4.0 V, and the insertion loss is reduced from 3.7- to 5.4-dB gain, as shown in Fig. 10. The phase tuning range in the 5.8-GHz band is 360 as changes from 1.0 to 4.5 V. The insertion loss is also compensated to vary from 4.5 dB to 2.1-dB gain during the phase tuning, as illustrated by Fig. 11. The distributed amplifier provides a constant gain of 14 dB up to 8 GHz. However, the loss of the phase shifter and matching

networks increases significantly at 5.8 GHz and up to 18 dB. Hence, the compensated gain at 5.8 GHz is less than that at 2.4 and 3.5 GHz. B. Gain Variation Calibration As we can see from the -parameter measurement results, the gain (loss) of the phase shifter varies as changes for different phase conditions. The gain variation of the phase shifter can be calibrated by adaptively adjusting the gate bias of the distributed amplifier through a lookup table. The calibration results at 2.4 GHz is shown in Fig. 12. We can see that a flat gain around 0 dB is achieved compared with the gain shifting from 0 to 6.6 dB before the calibration. On the other hand, the phase tuning versus control voltage curve with the calibration is almost identical as that without the calibration through the whole 180 tuning range.

LU et al.: DEVELOPMENT OF MULTIBAND PHASE SHIFTERS IN 180-nm RF CMOS TECHNOLOGY

The gain variation calibration has been also conducted at 3.5 and 5.8 GHz, as shown in Figs. 13 and 14, respectively. A flat insertion loss is achieved at 3.7 and 4.5 dB, respectively, across the 360 phase tuning range. Similar to that at 2.4 GHz, the transmission phase is almost unaffected through the calibration process. The independence of phase tuning on gain calibration simplifies the design of control (calibration) algorithms. IV. CONCLUSION This paper has presented the development of a multiband phase shifter in 180-nm CMOS technology. The phase shifter requires only one control voltage for phase tuning. The proposed novel topology yields significant loss compensation with moderate power consumption [5], [15], [16]. The measurement results have shown that the phase shifter can achieve more than 180 tuning range over 2.4- to 6-GHz bands. The phase variation within 20-MHz bandwidth is 3 , and the time-delay nature also makes this phase shifter suitable for wide-band applications. The gain can be as high as 6.6 dB without calibration. The gain variation during phase tuning can be calibrated by adaptively adjusting the bias condition of the embedded amplifier. The calibration through a lookup table has been conducted to yield a flat gain through the whole phase tuning range.

[11] F. Ellinger, H. Jackel, and W. Bachtold, “Varactor-loaded transmissionline phase shifter at C -band using lumped elements,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 4, pp. 1135–1140, Apr. 2003. [12] D. M. Pozar, “Impedance matching and tuning,” in Microwave Engineering, 3rd ed. Hoboken, NJ: Wiley, 2005, ch. 5, pp. 250–255. [13] J. S. Dunn, D. C. Ahlgren, D. D. Coolbaugh, N. B. Feilchenfeld, G. Freeman, D. R. Greenberg, R. A. Groves, F. J. Guarin, Y. Hammad, A. J. Joseph, L. D. Lanzerotti, S. A. St. Onge, B. A. Orner, J.-S. Rieh, K. J. Stein, S. H. Voldman, P.-C. Wang, M. J. Zierak, S. Subbanna, D. L. Harame, D. A. Herman, Jr., and B. S. Meyerson, “Foundation of RF CMOS and SiGe BiCMOS technologies,” IBM J. Res. Dev., vol. 47, no. 2/3, pp. 101–138, Mar./May 2003. [14] G. Tsoulos and M. Beach, “Calibration and linearity issues for an adaptive antenna system,” in Proc. Vehicular Technology Conf., vol. 3, Phoenix, AZ, May 1997, pp. 1597–1600. [15] H. Hayashi and M. Mauraguchi, “An MMIC active phase shifter using a variable resonant circuit (and MESFETs),” IEEE Trans. Microw. Theory Tech., vol. 47, no. 10, pp. 2021–2026, Oct. 1999. [16] D. Viveiros, Jr., D. Consonni, and A. K. Jastrzebski, “A tunable all-pass MMIC active phase shifter,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 8, pp. 1885–1889, Aug. 2002.

Chao Lu (S’05) received the B.E. and M.S. degrees in electronic engineering from Tsinghua University, Beijing, China, in 1999 and 2002, respectively, and is currently working toward the Ph.D. degree at the University of California at Davis. From 2002 to 2003, he was also a Design Engineer with Intel Technology Ltd., Shanghai, China, where he developed mixed-signal ICs. His current research interests include advanced communication architectures, wide-band/multiband RF integrated circuits (RFICs), and mixed-signal ICs.

ACKNOWLEDGMENT The authors wish to acknowledge the IBM Corporation, Essex Junction, VT, for the chip fabrication. REFERENCES [1] R. A. Soni and R. D. Benning, “Intelligent antenna system for cdma2000,” IEEE Signal Process. Mag., vol. 19, no. 4, pp. 54–67, Jul. 2002. [2] M. Teshiba, R. Van Leeuwen, G. Sakamoto, and T. Cisco, “A SiGe MMIC 6-bit PIN diode phase shifter,” IEEE Microw. Wireless Compon. Lett., vol. 12, no. 12, pp. 500–501, Dec. 2002. [3] D. R. Banbury, N. Fayyaz, S. Safavi-Naeini, and S. Nikneshan, “A CMOS 5.5/2.4 GHz dual-band smart-antenna transceiver with a novel RF dual-band phase shifter for WLAN 802.11a/b/g,” in IEEE RFIC Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 157–160. [4] H. Zarei and D. J. Allstot, “A low-loss phase shifter in 180 nm CMOS for multiple-antenna receivers,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., vol. 1, San Francisco, CA, Jan. 2004, pp. 392–393. [5] S. Hamedi-Hagh and C. A. T. Salama, “A novel C -band CMOS phase shifter for communication systems,” in Proc. Int. Circuits Systems Symp., vol. 2, Bangkok, Thailand, May 2003, pp. II316–II319. [6] J. Y. Liang and C. S. Aitchison, “A proposal of a broad-band high gain block using cascaded single-stage distributed amplifiers,” in IEEE High Performance Electron Devices for Microwave and Optoelectronic Applications Workshop, London, U.K., Nov. 1995, pp. 173–178. [7] K. Deng, T. Huang, and H. Wang, “Design and analysis of novel highgain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 11, pp. 2188–2196, Nov. 2003. [8] A. Worapishet, S. Srisathit, and M. Chongcheawchamnan, “On the feasibility of cascaded single-stage distributed amplifier topology in digital CMOS technology,” in Proc. 45th Midwest Circuits Systems Symp., vol. 2, Tulsa, OK, Aug. 2002, pp. II254–II257. [9] R. V. Garver, “Broad-band diode phase shifters,” IEEE Trans. Microw. Theory Tech., vol. MTT-20, no. 5, pp. 314–323, May 1972. [10] W. M. Zhang, R. P. Hsia, C. Liang, G. Song, C. W. Domier, and N. C. Luhmann, Jr., “Novel low loss delay line for broad-band phased antenna array applications,” IEEE Microw. Guided Wave Lett., vol. 6, no. 11, pp. 395–397, Nov. 1996.

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Anh-Vu H. Pham (SM’03) received the B.E.E. (with highest honors), M.S., and Ph.D. degrees from the Georgia Institute of Technology, Atlanta, in 1995, 1997, and 1999, respectively. In 1997, he co-founded RF Solutions, LLC, an RFIC company that was acquired by Anadigics in 2003. He has held faculty positions with Clemson University and the University of California at Davis, where he is currently an Associate Professor. He is also active as a consultant to the industry. He has authored or coauthored over 50 technical journal and conference papers. His research interests are in the area of RF and high-speed packaging and signal integrity, RFIC design, and wireless sensors. Dr. Pham serves as a member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) Technical Program Committee (TPC) on Power Amplifiers and Integrated Circuits. He has been the chair of the IEEE MTT-12 Microwave and Millimeter Wave Packaging and Manufacturing Technical Committee of the IEEE MTT-S. He was the recipient of the 2001 National Science Foundation CAREER Award on millimeter-wave organic packaging.

Darrell Livezey received the B.S.E.E./C.S. degree from the University of Colorado at Boulder, in 1986. In 1986, he joined the Boeing Company, where he designed electrooptic systems for aircraft. In 1996, he joined CommQuest (an IBM company) and developed several RF and mixed-signal ICs for telecommunication applications. Since 2003, he has been a Senior Engineer with Tahoe RF Semiconductor Inc., Auburn, CA, where he currently develops RF and mixed-signal ICs for telecommunication, satellite, and automatic test equipment (ATE) applications.

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Distortion in RF CMOS Short-Channel Low-Noise Amplifiers Rola A. Baki, Member, IEEE, Tommy K. K. Tsang, Student Member, IEEE, and Mourad N. El-Gamal, Member, IEEE

Abstract—An approach to estimate the distortion in CMOS short-channel (e.g. 0.18- m gate length) RF low-noise amplifiers (LNAs), based on Volterra’s series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18- m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate–source capacitance gs of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper. Index Terms—Closed-form expressions, intermodulation distortion, RF low-noise amplifier (LNA), second-order distortion (HD2), short-channel CMOS, third-order harmonic distortion (HD3), Volterra series.

I. INTRODUCTION

T

HE DESIGN and analysis of integrated RF and microwave circuits is receiving a considerable interest by the research community due to the continuous growth in the wireless telecommunication market (e.g., [1]–[15]). In particular, many ongoing efforts are focused on the integration of RF receivers in standard CMOS technologies [3]–[8]. This is necessary in order to allow the implementation of RF front-ends with digital signal processors and enable low-cost single-chip fully integrated solutions. The evolution of CMOS technologies and the high level of integration they offer have made it an attractive candidate for RF applications. State-of-the-art CMOS technologies offer competitive performance in terms of noise and cutoff frequencies. With an 0.18- m gate-length standard CMOS process, a minimum noise figure (NF) of less than 0.5 dB has been measured at 5.1 GHz with an associated of 150 GHz were obtained 16-dB gain [16], and an of more by careful layout techniques [17]. Also, an Manuscript received January 20, 2005; revised May 5, 2005. This work was supported by the National Science and Engineering Research Council of Canada, by the Canadian Microelectronic Corporation, and by ReSMiQ, Canada. The authors are with the Microelectronics and Computer Systems Laboratory, McGill University, Montreal, QC, Canada H3A 2A7 (e-mail: [email protected]; [email protected]; [email protected]. mcgill.ca). Digital Object Identifier 10.1109/TMTT.2005.860897

than 150 GHz with a 0.8-dB NF at 6 GHz [18], and 64- and 100-GHz oscillating frequencies [19] have been achieved using a CMOS 90-nm gate-length process. These performances are sufficient to allow the integration of circuits operating in the lower gigahertz range and to cover most of today’s consumer wireless applications. LNAs are widely used in telecommunication systems (e.g. [2]–[15]). Their linearity is becoming of high importance for modern RF receivers. Even-order harmonics generate dc offsets in homodyne receivers, while third-order intermodulation distortions, resulting from mixing with interferers in adjacent channels, can corrupt the desired downconverted signal channels. Several studies of the effects of the CMOS transistors characteristics on the linearity of RF LNAs have already been reported, e.g., by Kang et al. [20], Toole et al. [21], Wambaq et al. [22], and Kim et al. [23]. The analysis reported in [20] discusses the third-order distortion behavior of CMOS transistors for RF applications. The results presented are based on empirical coefficients obtained from measurements of specific devices. It focused mainly on the effect of the output transconductance of the transistors on distortion. The analysis in [21] attempted to exploit a “sweet-spot” in the third-order distortion response, without providing practical detailed analytical equations relating specific transistor parameters to distortion. In Section II, we will discuss this work, which is the latest distortion analysis reported in the literature for RF CMOS amplifiers. The analysis in [22] provides models to compute the distortion in CMOS LNAs, without providing closed-form simple expressions describing the effect of specific transistor parameters and, thus, without suggesting design guidelines to enhance the distortion behavior. The analysis in [23] proposes a technique to enhance the third-order input intercept point (IIP3) of RF amplifiers by using multiple gated transistors, without focusing much on the fundamental behavior of distortion in the transistor itself. Besides, only the transconductance nonidealities were discussed in detail. The effects of technology variations and of technology scaling were investigated in [24] and [25]. A model was proposed in [26] for large-signal distortion analysis and was applied to RF CMOS power amplifiers. Linearity analysis of switching pairs operating in the weak inversion region was presented in [27]. Distortion analysis for long-channel RF CMOS amplifiers was reported in [28]. In that was considered. The studies in analysis, only the effect of [20]–[23] do not provide closed-form frequency-dependent expressions describing the second-order harmonic distortion in CMOS short-channel-based LNAs, which is becoming a major

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Fig. 1. (a) Common-source LNA. (b) Folded-cascode LNA.

Fig. 2. OIP3 simulations of a single transistor amplifier: (i) without degeneration and input matching, (ii) with a degeneration resistor, and (iii) with a degeneration resistor and input impedance matching. Note that varying the overdrive voltage is equivalent to biasing the transistor at different current bias points.

problematic issue in modern homodyne receivers.1 Studies of second-order distortions in MESFET and HBT devices have already been reported (e.g., [29], [30]). In this paper, a complete method to estimate the distortion in RF LNAs is presented [31]. Compact equations relating distortion to the CMOS transistors’ design parameters are derived. The approach used is based on the theory of Volterra’s series [32]–[38]. Volterra’s series are time-dependent power series which can be used to describe systems with memory, i.e., employing capacitors and inductors. The CMOS transistors characteristics considered in this work include the , the output resistance , the parasitic source resistance , gate-to-source , and drain-to-source gate-to-drain capacitances [39]. For simplicity, the substrates of the MOS transistors are assumed to be connected to the sources, and substrate leakage currents are not included, since they do not produce considerable amount of distortion [20]. The analysis is performed on a common-source RF amplifier and on a folded-cascode amplifier (Fig. 1). This paper is organized as follows. Section II gives an overview of the limitations of the use of the sweet-spot point for RF applications. The procedure to obtain closed-form expressions describing the distortion in nonlinear circuits using Volterra’s series is briefly introduced in Section III. Distortion analysis of a single-transistor amplifier and of a folded-cascode amplifier is then discussed in detail in Section IV. Distortion-aware design guidelines for RF LNAs are provided in Section V. The paper concludes with a verification of the analytical results proposed here through a comparison with measured results from an LNA chip prototype. 1In this work, the approach used to obtain closed-form expressions for the second-order harmonic dependency on the combined CMOS transistor characteristics for RF LNAs is explained in detail. Readers can follow it to generate the full expressions, if needed. However, the derived equations are pages long and too complex and provide no valuable design/analysis insights. Thus, only the dependency of second-order harmonic distortion (HD2) on each individual transistor nonideality alone is reported herein.

II. LIMITATIONS OF USING THE DISTORTION SWEET-SPOT POINT FOR RF APPLICATIONS A summary of the work presented in [21] is discussed in this section. To the best of our knowledge, it is the most recent distortion analysis of RF CMOS amplifiers reported in the literature. In short-channel CMOS transistors, the main source of distortion comes from the nonlinear behavior of the transconductance. Assuming that the output transconductance is linear and the cross modulation between the transconductances is negligible, the ac current in a MOS transistor can be modeled as (1) The second-order transconductance equals 0 A/V at zero and then increases before reaching a maximum value at a small overdrive voltage . Further increase in results in decreasing . As a result, , which is obtained by differentiating with respect to , decreases to zero at a very small overdrive voltage, i.e., when the transistor is still operating in the moderate inversion region. Therefore, theoretically, if the transistor is biased at this operating point, which is known as the “sweet-spot” point [21], the third-order harmonic distortion would tend to be zero, which would result in an infinite third-order output intercept point (OIP3). It is an attractive line of thought to follow for analog circuit designs in general. The low-noise RF amplifiers shown in Fig. 1 are used in the following discussion. For simulation purposes, the tank impedances were set such that the LNA’s mid-band gains are maximized at around 5 GHz. First, the circuit was simulated without using any degeneration impedances or input-matching inductors. The output intercept point was then obtained from transient simulations based on the BSIM transistor models in HSPICE. As expected and obtained in [21], the OIP3 is maximized at the biasing point where the third-order transconductance reaches zero (Fig. 2). The circuit was then simulated after adding a small degeneration resistor (20 ). As demonstrated in the plot, the

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where is a function of the circuit’s parameters in the frequency domain, and is the number of transistors. Dividing through by and taking the Laplace transform, the column vector on the left-hand side becomes

(3) where is the th-order transfer function between the input voltage and the gate–source voltage of the th transistor. Using Kramer’s rule, we can then solve for and for up to . 2) To obtain the second nonlinear response, the circuit is then analyzed as in step 1) with the nonlinear inputs placed in parallel with each nonlinear element and with the linear input short circuited [Fig. 3(b)]. The value of the second-order nonlinear current source is given by Fig. 3. Small-signal equivalent circuit of the LNA in Fig. 1(a). (a) Circuit used for the first-order kernel analysis. (b) Circuit used for the second-order kernel analysis.

OIP3 behavior changed—the maximum OIP3 in the moderate inversion region has decreased by 5 dB and shifted to a lower bias current value. In a practical LNA, the input impedance of the LNA should be matched to the characteristic impedance of the system, which is typically 50 . Hence, an input-matching inductor with a of 5 was added to the circuits, and the degeneration resistor was replaced by an inductor . As shown in Fig. 2, by adding , the OIP3 in the moderate inversion region decreased by about 15 dB from its original peak. It can be shown that the OIP3 decreases with the addition of the input impedance matching and of the degeneration impedance due to the feedback path created between the output voltage across the tank and the fundamental tone of the input signal. A more detailed analysis of this is reported by Aparin et al. in [40]. Thus, the use of the “sweet-spot” point in the moderate inversion region for CMOS short-channel transistors might not be easily applicable for RF LNA designs. However, it can be greatly appreciated in amplifiers operating at lower frequencies. III. BASICS OF VOLTERRA’S SERIES—A BRIEF A method based on Volterra’s series to study the nonlinear effects of transistors in continuous-time analog circuits was presented in [32] and is adopted for our analysis. It can be summarized as follows. 1) A small-signal nodal analysis is initially performed to obtain the first-order response of the circuit [e.g. Fig. 3(a)]. The set of transfer functions relating the input voltage to the nonlinear internal voltages (the gate–source voltages ) is then derived. The equations obtained can be arranged in a matrix format

(4) where is the second coefficient in the Taylor expansion of the relationship between the voltage and the current in a CMOS transistor. For the derivation of the th nonlinear response, the terms can then be obtained by deriving times the expression of the current with respect to [31], [41]. Note that it is possible to write the system’s equations such that the resulting square matrix and its determinant have the same format as that of (2). In fact, only the input vector [matrix in (2)] becomes a function of the nonlinear current sources . 3) With the frequency variable replaced by in the matrix and using Kramer’s rule, the second-order output response of the circuit can be calculated as follows: (5) where is the determinant of the square matrix in (2) when the first column is replaced by the nonlinear input vector. In order to calculate the magnitude of the second-order harmonic distortion for a sinusoidal input with amplitude , it is sufficient to evaluate the magnitude of HD2

(6)

is the linear transfer function of the where circuit. 4) The third-harmonic distortion is calculated by following a similar procedure to that described in the previous steps, with replaced by , and with given by

(2)

(7)

BAKI et al.: DISTORTION IN RF CMOS SHORT-CHANNEL LNAs

For

49

, (7) simplifies to (8)

where the second term of the right-hand side represents the intermodulation effect of the first- and second-order harmonics on the third-order one. The third-order response of the circuit can be evaluated as is the second response of the circuit, with the frequency variables replaced by . It is thus given by (9) Although it will not be done in this paper, this method can be extended to calculate the th kernel of the Volterra series [22]. This would require using nonlinear current sources of the th order and repeating the process described in the previous two steps. For LNAs, the input signal is usually small, and thus the small-signal current in the MOSFET transistor [(1)] normally converges within the first few terms. Moreover, the transfer functions of LNAs typically have low-pass or bandpass responses, which helps to filter out high-order frequency terms generated in the transistors. It is therefore sufficient to describe the distortion behavior in LNAs with only the second- and third-order responses. The remainder of this paper studies the second- and thirdorder harmonic distortions in RF CMOS short-channel LNAs operating in the deep inversion region. The analysis is based on Volterra’s series and shows the effects of transistor parasitics, such as the source resistance , the output transconductance (modeled by a linear resistor ), the parasitic gate-to-drain , gate-to-source , and drain-to-source capacitances, and the transconductance nonidealities on distortion. Distortion-aware design guidelines are suggested throughout.

is the transconductance of M1, where , and is the parallel combination of , , and . All capacitors in Fig. 3 are assumed to be linear [39]. Equations (10)–(13) were first rearranged in a matrix format, and then expressions for the second- and third-order harmonic responses were obtained, as explained in steps 2)–4) in Section III. The same analysis was performed for the folded-cascode LNA shown in Fig. 1(b) and, interestingly, yielded equivalent results. Expressions describing the third-order intermodulation distortion in the LNA were also derived. The third-order intermodulation distortion can be evaluated using

(14)

where

(15)

(16)

and

(17)

where IV. DISTORTION ANALYSIS OF RF CMOS LNAS USING VOLTERRA’S SERIES As explained earlier, small-signal analysis of the circuit of interest has to be performed first in order to obtain the th-order behavior. The equivalent circuit for the common-source RF amplifier in Fig. 1(a) with degeneration is shown in Fig. 3(a). The following set of equations are obtained for this circuit by performing nodal analysis: (10)

(11)

(18)

(19)

(20)

(12) and

(13)

(21)

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where and are the second and third coefficients of the Taylor expansion of , and and are the frequencies of a two-tone input test signal with equal amplitudes. Finally, the IIP3 is given by

IIP3

IM3

(22)

is the amplitude of the output signal at the or where frequencies and can be estimated by . Although exact and complete closed-form expressions for the second- and third-order distortion, and for the intermodulation distortion, dependencies on the combined CMOS transistor characteristics were obtained using the mathematical tool Maple and were verified experimentally (Section VI), they were many pages long and very complex, and provided no insight or value for hand analysis. In order to provide the readers with practical design guidelines, we derived compact analytical expressions for distortion, taking into account only one CMOS parameter at a time.2 Fig. 4. Effect of (b) HD3. [W=L =

A. Effect of the CMOS Transconductance Considering the effect of alone, the following HD2 and HD3 expressions were derived:

HD2

(23)

HD3

(24)

g

: analytical and simulated distortions (a) HD2 and = 300 ].

50 m=0:18 m, and R

B. Effect of the Gate–Source Capacitance Expressions for HD2 and HD3 caused by using Maple and are given by

were obtained

HD2 and are the second and third coefficients where of the Taylor expansion of , as explained in Section III, and are constant for a given bias point. Note that, since the terms depend on the biasing current, for every value, the terms have to be, and are, reevaluated. By increasing the transconductance of transistor M1, the harmonic distortions can be significantly decreased3 (Fig. 4). For example, an increase of 30% in results in a 9-dB decrease in HD2. It can be shown that both and are proportional to [31], and, therefore, the second- and third-order harmonic distortions due to are independent of the ratio and are only inversely proportional to . In a distortion-aware design context, this translates to a preference of selecting a relatively small transistor size that is capable of providing the necessary when biased at the highest possible overdrive voltage , in order to decrease the effect of on distortion. 2Due to the fact that the system is nonlinear, one could argue that superposition cannot be used, in theory. However, since the circuit is actually weakly nonlinear, and it normally handles relatively very small signals, the cross-modulation terms resulting from the interactions between the different CMOS nonidealities were found to always be very small, compared to the other distortion terms considered and reported in this paper. Thus, these cross-modulation terms could be neglected, and a superposition-like-based analysis could safely be carried out, as supported by numerous simulations and measurements presented here. 3Note that, for all simulation results presented in this section, v = 1 mV unless otherwise specified.

(25) HD3

(26)

was set to a typical value (i.e., 2 ). The source resistance GHz, fF, and From (25) and (26), setting m m, we have . It will almost have can therefore be concluded that increasing no effect on HD2 or HD3. This statement was verified using HSPICE and Maple, for different transistor sizes and bias currents (Fig. 5). This suggests that it is possible to decrease the size of the input-matching inductor of an LNA, while maintaining the same resonant frequency at the input by simply adding a ca, all without affecting the linearity of pacitor in parallel with has no impact on HD2 the circuit. Fig. 5 also suggests that and HD3, for different transistor sizings and bias currents. This work did not address the effect of phase changes due to varying on distortion.

BAKI et al.: DISTORTION IN RF CMOS SHORT-CHANNEL LNAs

Fig. 5. Analytical and simulated distortions: effect of transistor sizings.

C. Effects of Parasitic Capacitances When considering

C

51

for two different

and

alone, HD2 and HD3 were found to

be HD2

(27)

HD3

(28)

Similar expressions were obtained for

and are given by

HD2 (29) HD3 (30) in the denominator of HD2(s) and of The term HD3(s) in the above equations represents the feedback that the parasitic capacitor introduces between the input and the output of a single-transistor LNA. As the increases and gets closer in value to , the term decreases, which results in an increase in the second- and third-order distortions. Theoretically, the above equations imply that, for a specific biasing condition, the distortion generated due to the feedback through can be infinite. However, when the transistor is operating in the saturation region, as generally is the case in LNA designs, the parasitic capacitor is mainly due to the lateral diffusion of the drain region below the gate oxide, giving rise to an overlap region between them. This capacitor is linearly dependent on the width of the CMOS transistor and is given by , where is the width of the overlap. The value of this overlap is relatively small. For example, for a 100- m-width 0.18- m-length transistor, with frequencies up

Fig. 6. Effect of C : analytical and simulated distortions (a) HD2 and = 300 ]. (b) HD3 [W=L = 50 m=0:18 m and R

is always smaller than . Therefore, to 10 GHz, the term practically, the distortion in RF LNAs due to is limited. Fig. 6 suggests that the effect of on distortion is higher than that of (Fig. 5), but it remains relatively weak, compared to, for an example, the effect of . By varying from 0 to 200 fF, the distortion deteriorates only by about 4 dB. D. Effects of the Output Resistance Resistance

and of the Source

The output resistance of the MOSFET transistor is modeled as in Fig. 3. It is assumed to be linear, in order to keep the analysis simple [21]. It introduces a certain amount of distortion, since it creates a signal path between the source and the drain of the transistor [40]. Note that, without including in this analysis, would appear between and , in parallel with the tank impedance, and we would not be able to derive its parasitic effect on the circuit. In reality, the parasitic resistance at the source of a MOSFET is typically around 2 . When considering , HD2(s) and HD3(s) were found to be HD2 (31) HD3 (32) where (33) Analytical and simulation results demonstrating the effect of the output resistance are shown in Fig. 7. As expected, the distortion decreases when increasing the output resistance.

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Fig. 8. Effect of r : analytical and simulated distortions (a) HD2 and (b) HD3 [W=L = 50 m=0:18 m, I = 2 mA, and R = 300 ].

Fig. 7. Analytical and simulated distortions: effect of r on (a) HD2 and (b) HD3 [W=L = 50 m=0:18 m and R = 300 ].

Taking only

into account, HD2 and HD3 are given by

HD2

(34)

and HD3 (35)

Equation (34) suggests that HD2 is almost inversely proportional to the square of the degeneration resistor , while (35) shows an inversely proportional cubic relationship between HD3 and . The LNA in Fig. 1(a) was simulated with a bias current of 2 mA and a gain of 15 dB, while was varied from 2 to 80 . As shown in Fig. 8, a source resistance of only 20 can decrease HD2 and HD3 by 6 and 10 dB, respectively. This asserts the common knowledge that, in a distortion-aware design, adding a degeneration impedance to the source of the input transistor significantly decreases distortion, since the latter is square/cubic inversely proportional to it. This can practically be achieved using a small resistance or inductor. While both elements will have the same effect in terms of distortion, inductors are invariably the elements of choice, due to their minimal effects on the NFs of LNAs.

V. PRACTICAL CONSIDERATIONS IN DISTORTION-AWARE LNA DESIGN From the analysis presented earlier, it is possible to summarize distortion-aware design guidelines for RF CMOS LNAs as follows: 1) Select the smallest possible transistor which will provide the necessary when biased at the highest possible overdrive voltage : A small transistor will minimize the effects of and (Section IV-C), while a large will decrease the distortion caused by (Section IV-A). 2) Add a capacitor in parallel with the of the input transistor: This is to mitigate the use of a small transistor. The addition of would lower the input impedance and ease input matching, without having any effect on distortion (Section IV-B). 3) Add a degeneration impedance to the source of the input transistor: Only a small degeneration impedance will significantly decrease distortion, since the latter is square/cubic inversely proportional to it (Section IV-D). To demonstrate the value of the above design considerations, three LNAs were designed and simulated. Their respective parameters are shown in Fig. 9 and Table I. They were chosen such that all circuits provide similar gains, using similar degeneration impedances and resonant LC tanks. However, the sizes of the transistors were varied. Similar gains were obtained by only tuning the gate-to-source voltage . For example, a 10-dB gain was achieved by setting to 0.55 V in design 1, 0.5 V in design 2, and 0.475 V in design 3. To mitigate the use of small transistors while ensuring a reasonable size of the input-matching inductor, a capacitor was added in parallel to

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Fig. 9. Schematic of a cascode LNA with different design parameters, used to demonstrate the effect of different transistor sizings on distortion. Also shown in Table I, for a 16-dB gain, the OIP3, V , the power consumption, and the NF.

TABLE I THREE LNA DESIGN PARAMETERS

Fig. 10. (a) IIP3 and (b) OIP3 for three LNAs with different transistor sizes.

for the LNAs with smaller transistor sizes (designs 1 and 2), such that similar parameters were obtained for the three circuits. Fig. 10 shows the distortion behaviors in terms of IIP3 and OIP3 for the three amplifiers with respect to their gains. As can be seen, for all gain values, the distortion was minimum for the smallest transistor LNA (i.e., m). For higher gains, even greater than 12 dB, the smallest transistors amplifier surpassed the distortion performances of the other two designs (i.e., higher IIP3). With the gain set to 16 dB, OIP3s of 14, 4.5, and 1.5 dBm were measured for the 75-, 150-, and 300- m transistor widths, respectively. It should be noted that, by using a small transistor, the 10-dB enhancement in distortion came at the cost of increasing the overall power consumption to 9.8 mW for the 75- m/0.18- m LNA, compared to 7.2 and 5.8 mW. These results demonstrate that, for a given acceptable LNA gain, the distortion can be minimized by using smaller transistors

Fig. 11.

Photomicrograph of the folded-cascode LNA [42].

driven by large overdrive voltages while employing degeneration impedances, at a moderate increase of power consumption. Note that similar results were observed for the folded-cascode LNA operating from a 1-V power supply [see Fig. 1(b)]. VI. EXPERIMENTAL RESULTS The folded-cascode LNA structure in Fig. 1(b) was implemented in a standard CMOS 0.18- m process [42]. A specific

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Fig. 13. Experimental, analytical, and simulation results of the 5.8-GHz LNAs’ third-order intermodulation distortion.

and analytical distortions, for two different biasing currents, namely mA [see Fig. 12(a)] and mA [see Fig. 12(b)], is 3 dB. Also, a good agreement regarding trends and slopes between all corresponding curves is evident. Finally, Fig. 13 compares the in-band third-order intermodulation distortion obtained from measurements and simulations to the analytical results computed by Maple. Once again, the good agreement between all curves supports the validity of the entire analysis procedure proposed in this paper. Fig. 12. Comparisons of experimental, analytical, and simulation results of HD2 and HD3 of the 5.8-GHz folded-cascode LNA with different bias currents of (a) I = 11:3 mA and (b) I = 5:8 mA.

layout implementation is shown in Fig. 11. It operates from a 1-V power supply. The LNA exhibits 13.2 dB of gain at 5.8 GHz. Including the output stage, the circuit consumes 22 mW of power and has an NF of 2.5 dB. The measured input and output reflection coefficients were less than 5 and 10 dB, respectively. The layout occupies 0.9 mm , including the bonding pads. Harmonic and intermodulation distortions were measured on wafer using Cascade GSG probes. Fig. 12 shows the measured and simulated results for HD2 and HD3 and compares them to the values computed analytically using Maple. For the simulations, HSPICE was used: a transient analysis was performed over 50 periods, and only the last period was considered to avoid transients. The second- and third-order harmonics were then estimated through post-processing using the fast Fourier transform algorithm of MATLAB. Coherent testing conditions were observed all along in order to ensure maximum accuracy. The analytical results were obtained by modeling the distortion following the approach described in Section III using Maple, while taking into account all of the CMOS transistor parameters affecting distortion. The validity of this analytical approach is well demonstrated by the results in Fig. 12: the maximum deviation between the experimental, simulated,

VII. CONCLUSION Nonlinearity equations in terms of Volterra’s series have been derived, allowing the investigation of the distortion in shortchannel CMOS RF LNAs. Closed-form and frequency-dependent equations describing distortion were derived and compared to simulation and experimental results. Simple practical design considerations were suggested and verified by comparing the distortion behavior of three LNA setups. Results showed that the distortion is lowered for LNA designs using smaller transistors while operating with larger overdrive voltages, without impacting much the power consumption. To the best of our knowledge, this is the first time this design approach is proposed and demonstrated along with simple closed-form equations demonstrating the effect of on distortion in LNAs. REFERENCES [1] R. Mukhopadhyay, Y. Park, P. Sen, N. Srirattana, J. Lee, C.-H. Lee, S. Nuttinck, A. Joseph, J. D. Cressler, and J. Laskar, “Reconfigurable RFIC’s in Si-based technologies for a compact intelligent RF front-end,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 81–93, Jan. 2005. [2] M. A. Copeland, S. P. Voinigescu, D. Marchesan, P. Popescu, and M. C. Maliepaard, “5-GHz SiGe HBT monolithic radio transceiver with tunable filtering,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 2, pp. 170–181, Feb. 2000. [3] C. Y. Wu and C. Y. Chou, “A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 519–521, Mar. 2004. [4] X. Guan and A. Hajimiri, “A 24-GHz CMOS front-end,” IEEE J. SolidState Circuits, vol. 39, no. 2, pp. 368–373, Feb. 2004.

BAKI et al.: DISTORTION IN RF CMOS SHORT-CHANNEL LNAs

[5] T. H. Lee, H. Samavati, and H. R. Rategh, “5-GHz CMOS wireless LANs,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 268–280, Jan. 2002. [6] F. Gatta, D. Manstretta, D. Rossi, and F. Svelto, “A fully integrated 0.18 m CMOS direct conversion receiver front-end with on-chip LO for UMTS,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 15–23, Jan. 2004. [7] S. W. Yue, D. K. Ma, and J. R. Long, “A 17.1–17.3-GHz image-reject downconverter with phase-tunable lo using 3 times subharmonic injection locking,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2321–2332, Dec. 2004. [8] M. N. El-Gamal, K. H. Lee, and T. K. Tsang, “Very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications,” Proc. Inst. Elect. Eng. Circuits Devices Syst., pp. 355–362, Oct.–Dec. 2002. [9] T. K. Adiseno, M. Ismail, and H. Olsson, “A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1162–1168, Sep. 2002. [10] A. Tasic, W. A. Serdijin, and J. R. Long, “Optimal distribution of the RF front-end system specifications to the RF front-end circuit blocks,” in Proc. IEEE ISCAS, 2004, pp. 889–892. [11] I. M. Filanovsky, “On design of narrow-band low-noise amplifiers with inductive source degeneration,” in Proc. IEEE MWSCAS, 2000, pp. 64–67. [12] A. N. Moheldin, E. Sanchez-Sinencio, and J. Silva-Martinez, “A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1172–1181, Jul. 2003. [13] J. W. M. Rogers and C. Plett, “A 5 GHz radio front-end with automatically Q tuned notch filter,” in Proc. IEEE BCTM, 2002, pp. 69–72. , “A completely integrated 1.8 volt 5 GHz tunable image reject [14] notch filter,” in Proc. IEEE RFIC Symp., 2000, pp. 75–78. [15] T. Taris, J. B. Begueret, H. Lapuyade, and Y. Deval, “A 0.9 V body effect feedback 2 GHz low-noise amplifier,” in Proc. ESSCIRC, 2003, pp. 659–662. [16] J. N. Burghartz, M. Hargrove, C. S. Webster, R. A. Groves, M. Keene, K. A. Jenkins, R. Logan, and E. Nowak, “RF potential of a 0.18 m CMOS logic device technology,” IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 864–870, Apr. 2000. [17] L. F. Tiemeijer, H. M. J. Boots, R. J. Havens, A. J. Scholten, P. H. W. de Vreede, P. H. Woerlee, A. Heringa, and D. B. M. Klaassen, “A realized at 0.18 m gate length in an inrecord high 150 GHz f dustrial RF-CMOS technology,” in IEEE IEDM Tech. Dig., 2001, pp. 10.4.1–10.4.4. [18] M. Vanmackelberg, S. Boret, D. Gloria, O. Rozeau, R. Gwoziecki, C. Raynaud, S. Lepilliet, and G. Dambrine, “90 nm SOI-CMOS of 150 and 0.8 dB NF @ 6 GHz for SOC,” in Proc. IEEE Int. GHz f SOI Conf., 2002, pp. 153–154. [19] L. M. Franca-Neto, R. E. Bishop, and B. A. Bloechel, “64 GHz and 100 GHz VCO’s in 90 nm CMOS using optimum pumping method,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 444–538. [20] S. Kang, B. Choi, and B. Kim, “Linearity analysis of CMOS for RF applications,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 972–977, Mar. 2003. [21] B. Toole, C. Plett, and M. Cloutier, “RF circuit implications of moderate inversion enhanced linear region in MOSFETs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 319–328, Feb. 2004. [22] P. Wambacq, P. Dobrovolny, S. Donnay, M. Engels, and I. Bolsens, “Compact modeling of nonlinear distortion in analog communication circuits,” in Proc. Design, Automation Test Europe Conf. Exhibit., 2000, pp. 350–354. [23] T. W. Kim, B. Kim, and K. Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223–229, Jan. 2004. [24] R. van Langevelde, L. F. Tiemeijer, R. J. Havens, M. J. Knitel, R. F. M. Ores, P. H. Woerlee, and D. B. M. Klaassen, “RF-distortion in deepsubmicron CMOS technologies,” in IEEE IEDM Tech. Dig., 2000, pp. 807–810. [25] C. H. Choi, Z. Yu, and R. W. Dutton, “Impact of poly-gate depletion on MOS RF linearity,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 330–332, May 2003. [26] C. Fager, J. C. Pedro, N. B. de Carvalho, H. Zirath, F. Fortes, and M. J. Rosario, “A comprehensive analysis of IMD behavior in RF CMOS power amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 24–34, Jan. 2004. [27] M. T. Terrovitis and R. G. Meyer, “Intermodulation distortion in currentcommutating CMOS mixers,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1461–1473, Oct. 2000.

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[28] C. H. Feng, F. Jonsson, M. Ismail, and H. Osson, “Analysis of nonidealities in RF CMOS amplifiers,” in Proc. IEEE ICECS, 1999, pp. 137–140. [29] S. S. Islam and A. F. M. Anwar, “Nonlinear analysis of GaN MESFET’s with Volterra series using large-signal models including trapping effects,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 11, pp. 2474–2479, Nov. 2002. [30] W. Kim, S. Kang, K. Lee, M. Chung, J. Kang, and B. Kim, “Analysis of nonlinear behavior of power HBT’s,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 7, pp. 1714–1722, Jul. 2002. [31] R. A. Baki, T. K. K. Tsang, and M. N. El-Gamal, “Distortion in RF CMOS short-channel low noise amplifiers,” in Proc. IEEE NEWCAS, 2005, pp. 41–44. [32] P. Wambacq, G. E. Gielen, and P. R. Kinget, “High-frequency distortion analysis of analog integrated circuits,” IEEE Trans. Circuits Syst. II, Exp. Briefs, no. 3, pp. 335–345, Mar. 1999. [33] R. A. Baki, M. N. El-Gamal, and C. Beainy, “Distortion analysis of highfrequency log-domain filters using Volterra series,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 50, no. 1, pp. 1–11, Jan. 2003. [34] A. Gothenberg and H. Tenhunen, “Performance analysis of sampling switches in voltage and frequency domains using Volterra series,” in Proc. IEEE ISCAS, 2004, pp. 765–768. [35] J. Vuolevi and T. Rahkonen, “Analysis of third-order intermodulation distortion in common-emitter BJT and HBT amplifiers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 50, pp. 994–1001, Dec. 2003. [36] K. L. Fong and R. G. Meyer, “High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages,” IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 548–555, Apr. 1998. [37] C. C. Huang, H. T. Pai, and K. Y. Chen, “Analysis of microwave MESFET power amplifiers for digital wireless communications systems,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 4, pp. 1284–1291, Apr. 2004. [38] A. Heiskanen, J. Aikio, and T. Rahkonen, “A 5th order Volterra study of a 30 W LDMOS power amplifier,” in Proc. IEEE ISCAS, 2003, pp. 616–619. [39] S. A. Mass, “FET Models for Volterra Series Analysis,” Applied Wave Research Inc., El Segundo, CA, Press release, 1999. [40] V. Aparin and L. E. Larson, “Modified derivative superposition method for linearizing FET low noise amplifiers,” in Proc. IEEE RFIC Symp., 2004, pp. 105–108. [41] W. Lu et al., “BSIM3v3.2.2 MOSFET Model,” Univ. California, Berkeley, 1999. [42] T. K. Tsang and M. N. El-Gamal, “Gain and frequency controllable sub-1V 5.8 GHz CMOS LNA,” in Proc. IEEE ISCAS, 2002, pp. 795–798.

Rola A. Baki (S’00–M’05) was born in Beirut, Lebanon. She received the B.Eng. and M. Eng. (with honors) degrees from McGill University, Montreal, QC, Canada, in 1999 and 2001, respectively, both in electrical engineering, and is currently working toward the Ph.D. degree at McGill University. She has been with the RFIC Laboratory, McGill University, since January 2000. Her Ph.D. research focuses on RF circuits and systems, with special emphasis on microwave filters. She was an Assistant Professor with the University of Quebec, Montreal, for the 2004–2005 academic year. She recently joined Murandi Communications Inc., Calgary, AB, Canada, as a Senior RF Engineer. Ms. Baki was the recipient of the Strategic Microelectronics Council Industrial Collaboration Award and is a scholarship recipient of the Natural Sciences and Engineering Council of Canada (NSERC) Award and of the “Fonds Québécois de la Recherche sur la Nature et les Technologies” (FCAR) Award at the doctoral level. For her first semester as a Faculty Lecturer on microelectronic circuits at McGill, she was the recipient of the Best Teacher Award for the academic year 2001–2002.

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Tommy K. K. Tsang (S’99) was born in Hong Kong on February 16, 1977. He received the B.Eng and M.Eng degrees (with honors) from McGill University, Montreal, QC, Canada, in 1999 and 2002, respectively, and is currently working toward the Ph.D. degree at McGill University. His earlier research focused on low-voltage bipolar and CMOS RF low-noise amplifiers for wireless applications. Currently, he is a member of the RFIC Group at McGill University, where his research focuses on novel low-power RFIC architectures and designs. He has published more than 15 papers in the area of low-voltage and high-performance integrated circuits and MEMS for RF applications and coauthored one chapter on CMOS RFIC front-ends for 5 GHz and beyond. Mr. Tsang was the corecipient of the 2002 IEEE Midwest Symposium on Circuits and Systems Best Student Paper Award for work on MEMS variable capacitors for RF applications and recipient of the Natural Sciences and Engineering Research Council—eMPOWR Canada Innovation Platform Award in 2003 and the Microelectronics Strategic Alliance of Québec (ReSMIQ) Scholarship in 2005.

Mourad N. El-Gamal (S’92–M’99) received the B.Sc. degree (with honors) from Ain-Shams University, Cairo, Egypt, in 1987, the M.Sc. degree from Vanderbilt University, Nashville, TN, in 1993, and the Ph.D. degree from McGill University, Montreal, QC, Canada, in 1998, all in electrical engineering. He is currently an Associate Professor and William Dawson Scholar at McGill University. His research interests include integrated circuits and MEMS for communications applications, on which he has published many papers and, most recently, contributed to a chapter on low-voltage 5-GHz RFIC front-ends. He was a on leave of absence from McGill in 2002 to assume the role of Director of Engineering, then Vice President, of the Wireless Business Unit of MEMSCAP, which is headquartered in France and is a 165-employee publicly traded company specializing in MEMS. He oversaw all of the business and technical aspects in different sites around the world related to RF-MEMS devices, RFICs, and millimeter-wave passive circuits. Earlier, he worked for the French telecommunications company ALCATEL and was a Member of the Technical Staff at IBM. He regularly serves as a consultant for leading microelectronics companies in North America and in Europe and holds one patent. Dr. El-Gamal is a member of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems (CAS) Society and is the chairman of the analog/digital committee of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM). He served as Guest Editor for the October 2004 issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and for the Journal on Wireless Communications and Networking. He was the corecipient of several research awards, the most recent being the Myril B. Reed Best Paper Award of the IEEE International Midwest Symposium on Circuits and Systems for his work on frequency synthesizer covering the lower and upper bands of 5-GHz WLANs. He was also the recipient of several teaching awards and recognitions.

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Millimeter-Wave Design Considerations for Power Amplifiers in an SiGe Process Technology Ullrich R. Pfeiffer, Member, IEEE, and Alberto Valdes-Garcia, Student Member, IEEE

Abstract—This paper describes a number of significant modeling considerations for SiGe heterojunction bipolar transistor power amplifiers operating at millimeter-wave frequencies. Smalland large-signal model-to-hardware correlation is presented for single transistor amplifiers, as well as for a combined dual-stage amplifier up to 65 GHz. The relevant parasitic effects are described along with the proposed modeling approach for each of them. The limits of the standard Vertical Bipolar Inter-Company device model at high-injection and their effect on the prediction of the achievable large-signal compression and power-added efficiency are also discussed. Index Terms—Millimeter wave, model-to-hardware correlation, power amplifier (PA), silicon germanium (SiGe).

I. INTRODUCTION

A

DVANCED silicon germanium (SiGe) bipolar technologies have demonstrated operation at millimeter-wave frequencies due to continued improvement in their cutoff frequencies . It has been shown that SiGe can meet the demands of relatively high output powers while maintaining high integration levels at low cost [1]–[4]. However, to achieve first-pass design hardware at millimeter-wave frequencies, it is necessary to use excellent parasitic models in combination with accurate device models. These requirements are difficult to meet even at microwave frequencies, where SiGe power amplifiers (PAs) still show discrepancies between simulated/expected and experimental results [5]. Current design techniques for millimeter-wave PAs with III–V semiconductors include extensive full-wave electromagnetic simulations for passive devices and interconnections [6] and custom-made transistor models obtained through a comprehensive set of RF measurements [7]. In addition to these modeling considerations, standard practice at millimeter-wave frequencies is to implement multiple design variances to account for possible model inaccuracies, e.g., a shift in the optimum frequency of operation. For example, the optimization of prototype designs has been done by cutting shorting bars of the back-end of the line [8], by connecting tuning islands through e-beam write and gate metallization process to adjust the matching circuits [9], or by breaking air bridges to find the optimum match for maximum power-added efficiency (PAE) [10]. Such design techniques, however, are getting rapidly Manuscript received February 15, 2005; revised May 24, 2005. This work was supported in part by the National Aeronautics and Space Administration under Grant NAS3-03070. U. R. Pfeiffer is with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). A. Valdes-Garcia is with the Analog and Mixed-Signal Center, Department of Electrical Engineering, Texas A&M University, College Station, TX 77843 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2005.860898

inefficient if one aims for highly integrated circuits. It is, therefore, desirable to use design techniques similar to traditional silicon-based circuit design; exclusively based on sophisticated pre-defined libraries and including scalable parasitic elements. To attain this quality of design automation at millimeter-wave frequencies is an open problem that demands further research. The focus of this paper is on the model-to-hardware correlation in a pre-production SiGe process technology for PA applications. The purpose is to introduce a set of modeling considerations and to analyze their limitations in the context of experimental results. The PA concept used is described in Section III. Model-to-hardware correlations are shown in Section IV for single-stage and dual-stage transistor amplifiers, including an outline of the parasitic modeling approach that has been developed. A discussion on large-signal SiGe heterojunction bipolar transistor (HBT) device modeling limitations at high injection is given in Section V. The performance of a standard Vertical Bipolar Inter-Company (VBIC) model is compared to a more physics-based high current model (HICUM), which can remove some of the modeling shortcomings known for HBT devices [11], [12]. This paper presents conclusions in Section VI. II. SiGe TECHNOLOGY USED The PAs described in this paper were designed on an IBM preproduction bipolar process SiGe8T [13]. It is a 0.12- m SiGe technology with a cutoff frequency GHz and GHz. The four-layer back end of the line has three copper layers with thick aluminum as the last metal for low-loss interconnects. The breakdown voltages are V and V. III. SINGLE-STAGE PA CONCEPT The measured performance of a dual-stage 60-GHz PA has been reported in [1] and the results have been compared to a similar amplifier topology designed for operation at 77 GHz in [2]. All of the circuits are balanced PAs designed to operate from a 2.5-V supply and employed to feed a differential antenna structure providing a 100- differential impedance at the input and output. This study presents the model-to-hardware correlation for the dual-stage 60-GHz PA and its single-stage breakouts (fabricated separately) equivalent in size to the first transistor stage (T1) and second transistor stage (T2), respectively. Fig. 1 shows a simplified schematic diagram of such single-stage class-AB biased balanced amplifier breakouts. Each amplifier uses the same bias circuit [14] to compensate for process and temperature variations, as well as to smooth bias and gain control. The scaling of the SiGe processes to smaller dimensions leads to lower breakdown voltages

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Fig. 1. Simplified schematic diagram of the balanced single-stage PAs. In case of T1, the amplifier is dc coupled at the input, as shown in this figure. In case of T2 (twice as large as T1), the amplifier is ac coupled with a series MIM cap at the input (not shown in this figure).

are balanced to increase the total output power by 3 dB. In both cases, the circuit halves are symmetric and well isolated from each other and, therefore, a common- to differential-mode conversion can be neglected. It has been found that adding 3 dB to single-ended measurements give rise to the same results as described in [2] and [18]. All large-signal measurements presented in this paper have been measured on-wafer, single ended into 50 , and are representative for a differential operation of the PA since 3 dB has been added to its input and output power. The input power was generated using an Anritsu synthesizer (69347B) in combination with an external 60-GHz driver amplifier (Spacek) mounted closely to the probe. For on-wafer probing of the device, 67-GHz Picoprobes in a ground–signal–ground–signal–ground (GSGSG) configuration have been used and the output power was detected with a calibrated Anritsu power sensor (SC6230). Similarly, small-signal -parameters have been measured single-ended for improved vector network analyzer (VNA) sensitivity. Swept power gain compression measurements at 60 GHz require accurate calibration and deembedding techniques at each power level in order to remove nonlinear effects of the driver amplifier and the frequency synthesizer. The available input power from the source has been calibrated with a through measurement on a 50- calibration substrate including deembedding of cable and probe losses. All small-signal measurements used a standard short-open-load-thru (SOLT) calibration technique. IV. MODEL-TO-HARDWARE CORRELATIONS

Fig. 2. Chip micrograph of the balanced single-stage (T1) PA. The size of the PA is 2.1 0.82 mm .

2

Fig. 3. Chip micrograph of the balanced single-stage (T2) PA. The size of the PA is 2.1 0.65 mm .

2

. The breakdown limit, caused by impact ionization, can be overcome to a certain extent if the bias circuit provides a low enough external resistance seen from the transistor’s base [15]–[17]. Each bias circuit provides an impedance of approximately 300 . This allows the collector–emitter voltage to swing 1.5 V around the 2.5-V dc-bias voltage V without causing the device to break down. Note that this voltage is well above . Fig. 2 shows a chip micrograph of the first amplifier and Fig. 3 shows a chip micrograph of the second amplifier. Transistor T1 has half the size of transistor T2, which sets a dc-bias current ratio of 1 : 2 between the two. Both circuits

The differences between a silicon-based millimeter-wave circuit design approach and its III–V counterpart are manifold. With respect to parasitics, the main difference is the superior performance of III–V substrates compared to those of silicon bulk materials, which tend to be rather lossy for standard low-resistivity silicon (e.g., 10 cm). In GaAs designs, for example, microstrip lines are defined between the top metallization and a backside ground leaving the GaAs bulk material in between. A similar approach in silicon would be futile. However, the superior manufacturability of interconnects within the back end of the line where 4–6 metal layers are offered routinely affects the design approach that can be taken. The silicon back end of the line stack height is in the order of 10 m with copper layers interleaved with silicon dioxide as isolation material and thick aluminum as last metal. Dielectric losses due to SiO can be neglected and a wide enough ground shield can effectively prevent stray fields from penetrating the lossy silicon substrate. The excellent performance of such transmission lines and their associated scalable models have been reported in [19]–[21] and they have been used in the designs described here for signal transmission and matching purposes. In the following, the parasitic effects within the back end of the line that have been considered are described. This includes a summary of the device model considerations and their effect on the large-signal performance of the amplifier. A. Modeling Considerations Transmission lines have been widely used for the design of the amplifiers, e.g., for the RF chokes and the input/output match. They are implemented as microstrip lines on a

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Fig. 4. Small-signal S -parameter for single-stage amplifier T1. Measured data is compared with SpectreRF and RFDE simulations results.

4- m-thick analog metal (AM) having the ground return path on the lower metal layer. Most of them are 10- m wide with side shields on either sides to minimize coupling to adjacent structures. They are designed for a characteristic impedance of 50 and comply with current density and electro-migration design rules. Good model-to-hardware correlation has been achieved by the use of a scalable seven-segment lumped ladder network up to 110 GHz [19]. However, transmission lines do have ends and require additional models at boundaries. In the current design approach, via models or short transmission-line sections have been added to a parasitic representation of the design in order to account for such boundaries. Most of the designs use 0.3- m-thick copper ground planes (MT) to avoid electromagnetic fields to reach into the lossy silicon substrate, to minimize coupling, and to limit the loss of the on-chip impedance transformation. Areas with no ground shield, e.g., lowest metal interconnects on M1, have been avoided wherever possible to reduce additional losses or modeling shortcomings. The following considerations have been taken into account for the modeling of the amplifiers. 1) Bondpad to Microstrip Transition: The bondpad design includes a deep trench (DT) layer underneath the pad to minimize pad losses. The pad design rules do not allow a metal shield

directly below, which would slightly increase the pad capacitance, but lower its loss. The absence of a ground plane below the pad represents an abrupt transition from the ground of the microstrip line to the DT of the pad. The spacing between the end of the microstrip line and the pad has, therefore, been modeled as an additional microstrip section to account for the phase shift across the transition. 2) Microstrip to Lower Level Metal Interconnect (Signal Via): The connection from the top-layer metal (AM) down to the transistor device requires the use of a 10- m-high via field. The height seems to be small, but can have a relevant effect on the impedance match of the amplifier if it is not taken into account. The vias have been modeled in a three-dimensional (3-D) electromagnetic simulator and their associated inductance has been lumped into a 4–6-pH inductor. Such an inductance is in agreement with a phase shift along a 10- m-long conductor and with the Greenhouse formula given in [22]. 3) Parasitic Extraction of the Device Interconnects: The npn bipolar transistors are parallel instances with parasitic capacitance, resistance, and inductance associated with their wiring. Transistor T1 consists of four and T2 of eight parallel instances, each 5 0.12 m. The parasitic elements are extracted for each wiring segment to form a distributed interconnection

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Fig. 5. Small-signal S -parameter for single-stage amplifier T2. Measured data is compared with SpectreRF and RFDE simulations results.

model. The use of a distributed model instead of single parasitic elements for each terminal of the overall transistor array is important (especially for the connection of the transistor bases) to accurately predict gain losses, as well as variations in the input and output reflection coefficients of the active device. 4) Microstrip to MIM Capacitor Interconnect: Parasitic capacitance, resistance, and via inductance have been extracted and added to the design to account for additional wiring effects as part of the shunt metal–insulator–metal (MIM) capacitors. 5) Transmission-Line T-Sections: T-sections are present in the layout at microstrip crossovers. The RF-choke, npn collector contact, and output microstrip line intersect are examples. These sections have been modeled by additional transmission lines to account for an extra phase shift. 6) Pad Model: On a lossy silicon substrate, the physical size of the I/O pads has a significant impact on the amplifiers matching network and requires specific attention. An equivalent lumped-circuit model should not only be able to account for its parasitic capacitance, moreover, it is required to account for the evoked phase shift from the point where a probe tip or wirebond would touch down on the pad and the edge where the signal is finally fed into a microstrip line. Distributed models that can account for such a phase shift have been used in the

past [23] for calibration purposes and have been used here to model the two-port characteristic of the pad. Based on 3-D electromagnetic simulations, an additional 2.5 phase shift has been identified and included based on an ideal 50- transmission-line segment with a length of 35 m. In general, the use of lumped circuit or distributed models are preferred over -parameter data where insufficient out-of-band information is available for large-signal simulators to converge. 7) Transistor Device Model: Active devices are included based on the VBIC bipolar junction transistor model, which has been fit to dc and small-signal -parameter measurements. Such models have shown reasonable good results, but have known shortcomings specifically if accurate large-signal responses are required [11]. Better models for high-performance SiGe HBTs have been reported, as will be outlined in more detail in Section V, but have not been available during the design process. B. Single-Transistor Amplifier Correlations Based on the above modeling considerations, the following section compares the small- and large-signal simulation results to on-wafer measurements. Two simulation engines, Cadence SpecrteRF and Agilent RFDE, have been used for comparative

PFEIFFER AND VALDES-GARCIA: MILLIMETER-WAVE DESIGN CONSIDERATIONS FOR PAs IN SiGe PROCESS TECHNOLOGY

Fig. 6. Compression at 1 dB versus transducer power gain for different simulators compared to measured results. Both transistor amplifiers (T1 and T2) are shown.

purposes. Note, Agilent’s RFDE requires its own set of technology libraries, which should ideally lead to identical results. At this point, however, the latest technology update for RFDE was not available, which can cause some minor differences. Figs. 4 and 5 show the simulated and measured small-signal -parameters from 40 up to 65 GHz for transistor amplifiers T1 and T2, respectively. The reverse isolation is predicted very accurately for both hardware, whereas the input match shows an optimum match approximately 5 GHz lower. The rolloff of the small-signal gain is faster for the measured hardware T1 than predicted by either simulator with a maximum 3-dB difference at 65 GHz. The small-signal gain for the T2 hardware is approximately 2 dB higher below 60 GHz and slightly lower above. Overall, the matching is broad-band and allows an operation over a wide frequency range. The input match is below 10 dB from 45 to 56 GHz for the first (T1) amplifier and from 55 to 64 GHz for the second amplifier (T2). The output match is better than -10 dB up to 59 GHz for T1 and up to 57 GHz for T2. The difference in the input match can be explained in part by the fact that the amplifier T2 is ac coupled at the input with a series MIM cap, whereas amplifier T1 is only dc coupled. The additional size of the MIM cap reduces the required transmission-line length and affect the effective electrical length of the input transmission line. The large-signal characteristic of both amplifiers is compared in a scatter plot, as shown in Fig. 6. A scatter plot is preferred for comparative purposes instead of output power versus input power curves. This figure plots the 1-dB compression point (1 dBCP) versus the amplifiers transducer power gain. This figure includes an additional 3-dB power pick-up, which is possible in a differential mode of operation even though the data was measured single ended, as pointed out earlier. This figure shows a 8-dB lower compression point in case of hardware T1 and a 6-dB lower compression point in case of T2. The transducer power gain plotted on the -axis is similar for both amplifiers even though T1 is half the size of T2. This can be understood since the transducer power gain includes the effect of the mismatched input of T1 where T2 has a very good match at 61.5 GHz. This

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Fig. 7. Peak PAE versus corresponding input power delivered to the amplifier.

Fig. 8. Close-up view of one-half of a balanced dual-stage amplifier using an open-stub tuned circuit case. The input, inter-stage, and output matching sections are shown.

figure shows the apparent shortcomings of the standard VBIC model to predict the large-signal compression of the device. See Section V for a further discussion of this effect. A similar plot is shown in Fig. 7 for the peak PAE versus the corresponding input power. The plot correlates measured data for the two amplifiers with simulation results. For amplifier T1, the simulated PAE is approximately 11%–12% higher than measured and, for the larger transistor amplifier T2, the simulation result is approximately 6% higher. Similarly, the simulated input power at peak efficiency is shifted upwards by 3 and 4 dB. The simulators, however, differ only by approximately 1 dB. Note that the input power is the power delivered to the amplifier and removes the effect of the input mismatch from the PAE. C. Dual-Stage PA Correlations During the design phase of the amplifiers published in [1] and [2], simulation results were only available for lower bias point conditions (e.g., for V) where convergence issues related to the operation above breakdown could be avoided. Updated device models have been made available, which, in conjunction with other simulators, such as harmonic balance, have led to new results that can be used here for comparative purposes.

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Fig. 9. Measured and simulated small-signal respectively.

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S -parameters of the dual-stage amplifier. Simulated curves are shown for VBIC and HICUM device models,

Fig. 8 shows a close-up view of one-half of a balanced dualstage 60-GHz SiGe amplifier published in [1]. The circuit uses open-stub tuning for input and output matching. Note that the transistor sizes are the same and some layout aspects are similar to the previously shown single-transistor amplifiers. At 60 GHz, a quarter-wavelength is 600 m; hence, transmission lines can be used as open stubs for impedance matching. Instead of shunt MIM capacitors, the dual-stage amplifier uses open-stub microstrip lines as part of the (LC) resonant matching networks to provide the necessary impedance transformation from the external 50 (half-circuit) to approximately 7 at the collector of the output transistors. A comparison of -parameter simulation results with measured hardware is shown in Fig. 9. Good correlations have been achieved for the input and output match, as well as for the return isolation. The amplifiers small-signal gain , which is going down from 16 dB at 40 GHz to 7.5 dB at 65 GHz, is predicted approximately 5 dB higher at frequencies between 50–55 GHz. Note that a PA design for maximum power delivered to a load and optimum operation within breakdown limits requires a nonconjugated match at the output and does not necessarily has an output match for minimum return loss.

Fig. 10. Output power (P out) and transducer power gain (P gain) versus input power delivered to the dual-stage PA at 61.5 GHz. Simulated curves are shown for VBIC and HICUM device models, respectively.

Fig. 10 shows the measured output power and transducer power gain versus input power at 61.5 GHz and a

PFEIFFER AND VALDES-GARCIA: MILLIMETER-WAVE DESIGN CONSIDERATIONS FOR PAs IN SiGe PROCESS TECHNOLOGY

Fig. 11. PAE versus corresponding input power delivered to the amplifier at 61.5 GHz. Simulated curves are shown for VBIC and HICUM device models, respectively.

supply voltage of 2.5 V. A transducer power gain of 10.8 dB has been achieved and the output power at 1-dB compression was 11.2 dBm. The saturated output power was measured at 16.2 dBm (two outputs) and 13.2 dBm single ended. The data is compared to an RFDE harmonic-balance simulation. The results show very good agreement for low-input power levels, but the large-signal compression occurs approximately 5 dB later than in the measured data. The SpectreRF simulation converged only for low input power levels under liberal conditions even though the single transistor amplifiers could be simulated at saturation. The results also agree well for low-input power levels, but show a significant over-prediction of the PAE as the input power increases. Fig. 11 shows a comparison between the measured and simulated PAE curve. The measured PAE is only 4.5%, whereas the RFDE simulation predicts a peak efficiency of 14%. The poor PAE model-to-hardware correlation can be understood by the fact that the large-signal compression occurs approximately 5 dB earlier and causes the gain at peak efficiency to drop faster and, therefore, limit the achievable efficiency. V. DISCUSSION OF RESULTS The achievable large-signal model-to-hardware correlation is largely being affected by device model shortcomings. All SiGe HBTs described in this paper are biased at a current density close to their peak or to provide sufficient gain at millimeter-wave frequencies. Such operation points can be very well modeled in case of small-signal operation. At large-signal operation, however, the dc current through the device can easily increase by a factor of two or more, which moves the device bias point over the peak of the curve into high injection [24]. High-performance SiGe devices inherently have a steep rolloff at high injection due to the high germanium content and larger germanium gradient in the neutral base employed to achieve their high beta and [25]. Rolloff at high-injection depends also on the device size and is known to be a weakness of the VBIC model [11], [12]. Therefore, it is not surprising that

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model-to-hardware discrepancies exist in PA designs. Other scalable and more physics-based bipolar device models like Most Exquisite Transistor Model (MEXTRAM) or HICUM are currently under development and have shown promising results for HBT devices [26]–[28]. To support such observations, the dual-stage amplifier design has been converted into an updated device library where HICUM models have been made available. The updated design library uses the same SiGe process generation with the same peak and cutoff frequencies. Although the HICUM device models are created for a collector–base–emitter–base–collector (CBEBC) configuration, they have been used here for comparative purposes to show their improved correlation with the measured large-signal compression characteristic. Note that the measured amplifier was laid out in an emitter–base–collector (EBC) topology, which will cause a slight shift in device parasitics and, consequently, a shift in the simulated small-signal -parameters. The -parameters of the HICUM models are shown in Fig. 9 for reference only. It is to be understood that the large-signal compression is not going to be affected by a slight shift in -parameters. The simulation results of the HICUM model are obtained using a harmonic-balance simulator and are shown in Fig. 10 for comparative purposes. It can be clearly seen that the HICUM model predicts an earlier compression of the HBT devices, which correlates well with the measured data. The large-signal compression directly affects the maximum achievable PAE, as can be seen in Fig. 11. The correlation of the available PAE is poor in case of the standard VBIC model, where as the HICUM model shows better results. VI. CONCLUSIONS AND OUTLOOK It has been demonstrated that reasonable good model-tohardware correlation based on the VBIC bipolar device model can be achieved in an SiGe processes technology without the need for extensive 3-D electromagnetic modeling. It has also been shown that single transistor PAs with high output powers are possible if the device breakdown and parasitic effects are carefully considered during the design process. Measurement results indicate that SiGe based transistors in common emitter bias configuration are able to generate 11.2 dBm at their 1-dB compression point and 16.2 dBm at saturation. However, to accurately predict the amplifiers compression point, saturated output power, and PAE, the specific characteristics of advanced SiGe HBTs have to be taken into account by the device models. This is especially true if transistors are operated at high injection and close to their device breakdown and current density limits. In agreement to recent research on modeling HBTs [11], it has been observed that, at peak efficiency, the dc-bias current through the common emitter device is increased up to a point beyond the peak of the curve and the device happens to be biased at a collector current density, which heavily compresses the amplifier gain and, therefore, limits the available efficiency. Future work will include the investigation of other, more physics-based, device models in conjunction with more sophisticated simulators. Improved parasitic models can include more layout details specifically at interconnect boundaries. Beside those improvements, future research will also focus on other circuit and bias conditions such as common base stages and cascode amplifiers.

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ACKNOWLEDGMENT The authors would like to thank all who contributed to the fabrication of the chip. Especially W. Ansley and the SiGe Technology Group, IBM, Burlington, VT, for providing the HICUM HBT device model. The authors extend special thanks to T. Zwick, B. Floyd, S. Reynolds, T. Beukema, and B. Gaucher, all of the IBM T. J. Watson Research Center, Yorktown Heights, NY, for helpful discussions.

[21] [22] [23]

[24]

REFERENCES [1] S. Reynolds, B. Floyd, U. R. Pfeiffer, and T. Zwick, “60 GHz transceiver circuits in SiGe bipolar technology,” in IEEE Int. Solid-State Circuits Conf., Feb. 2004, pp. 442–443. [2] U. Pfeiffer, S. Reynolds, and B. Floyd, “A 77 GHz SiGe power amplifier for potential applications in automotive radar systems,” in Radio Frequency Integrated Circuits Symp., Jun. 2004, pp. 91–94. [3] P. Wennekers and R. Reuter, “SiGe technology requirements for millimeter-wave applications,” in Proc. IEEE Bipolar/BiCMOS Circuits Technology Meeting, Sep. 2004, pp. 97–83. [4] B. Floyd, S. Reynolds, U. R. Pfeiffer, T. Zwick, T. Beukema, and B. Gaucher, “SiGe bipolar transceiver circuits operating at 60 GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 156–167, Jan. 2005. [5] W. Bakalski, W. Simburger, R. Thuringer, A. Vasylyev, and A. Scholtz, “A fully integrated 5.3-GHz 2.4-V 0.3-W SiGe bipolar power amplifier with 50 ohms output,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1006–1014, Jul. 2004. [6] J. C. Vaz and J. C. Freire, “Millimeter-wave monolithic power amplifier for mobile broad-band systems,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 6, pp. 1211–1215, Jun. 2001. [7] A. K. Sharma, G. P. Onak, R. Lai, and K. L. Tan, “A V -band high-efficiency pseudomorphic HEMT monolithic power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp. 2603–2609, Dec. 1994. [8] H. Li, H.-M. Rein, T. Suttorp, and J. Böck, “Fully integrated SiGe VCO’s with powerful output buffer for 77-GHz automotive radar systems and applications around 100 GHz,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1650–1658, Oct. 2004. [9] H.-L. A. Hung, G. M. Hegazi, T. T. Lee, F. R. Phelleps, J. L. Singer, and H. Huang, “V -band GaAs MMIC low-noise and power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 12, pp. 1966–1975, Dec. 1988. [10] O. S. A. Tang, J. Liu, P. C. Chao, W. M. T. Kong, K. C. Hwang, K. Nichols, and J. Heaton, “Design and fabrication of a wide-band 56- to 63-GHz monolithic power amplifier with very high power-added efficiency,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1298–1306, Sep. 2000. [11] C.-J. Wei, J. Gering, and Y. Tkachenko, “Enhanced high-current VBIC model,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1235–1243, Apr. 2005. [12] S. V. Cherepko and J. Hwang, “VBIC model applicability and extraction procedure for InGap/GaAs HBT,” in Proc. Asia–Pacific Microwave Conf., Dec. 2001, pp. 716–721. [13] B. J. Jagannathan et al., “Self-aligned SiGe NPN transistors with 285 and 207 GHz f in a manufacturable technology,” IEEE GHz f Electron Device Lett., vol. 23, no. 5, pp. 258–260, May 2002. [14] E. Järvinen, S. Kalajo, and M. Matilainen, “Bias circuit for GaAs HBT power amplifiers,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, May 2001, pp. 507–510. [15] M. Rickelt, H.-M. Rein, and E. Rose, “Influence of impact-ionizationinduced instabilities on the maximum usable output voltage of Si-bipolar transistors,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 774–783, Apr. 2001. [16] M. Rickelt and H.-M. Rein, “A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits,” IEEE J. Solid-State Circuits, vol. 37, no. 9, pp. 1184–1197, Sep. 2002. [17] R. Singh, D. L. Harame, and M. M. Oprysko, Silicon Germanium: Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2003. [18] T. Zwick and U. R. Pfeiffer, “Pure-mode network analyzer concept for on-wafer measurements of differential circuits at millimeter wave frequencies,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 934–937, Mar. 2005. [19] T. Zwick, Y. Tretiakov, and D. Goren, “On-chip SiGe transmission line measurements and model verification up to 110 GHz,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 2, pp. 65–67, Feb. 2005. [20] D. Goren, R. Gordin, and M. Zelikson, “Modeling methodology for on-chip coplanar transmission lines over the lossy silicon substrate,” in Proc. 7th IEEE Signal Propagation on Interconnects Workshop, May 2003, pp. 11–14.

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, “On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices,” in Proc. 41st IEEE Design Automation Conf. Workshop, Jun. 2003, pp. 724–727. H. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Trans. Parts, Hybrids, Packag., vol. PHP-0, no. 2, pp. 101–109, Jun. 1974. T.-M. Winkel, M. Ktata, T. Ludwig, H. Schettler, H. Grabinski, and E. Klink, “Determination of frequency dependent transmission line parameters on product related on chip test line structures using S -parameter measurements,” in Proc. IEEE Topical Electrical Performance of Electronic Packaging Meeting, Oct. 2003, pp. 97–100. J. Pan, G. Niu, A. Joseph, and D. L. Harame, “Impact of profile design and scaling on large signal performance of SiGe HBTs,” in Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Sep. 2004, pp. 209–212. D. Harame, J. Comfort, J. Cressler, E. Crabbe, J.-C. Sun, B. Meyerson, and T. Tice, “Si/SiGe epitaxial-base transistors—Part I: Materials, physics, and circuits,” IEEE Trans. Electron Devices, vol. 42, no. 3, pp. 455–468, Mar. 1995. Q. Liang, J. Cressler, G. Niu, R. Malladi, K. Newton, and D. Harame, “A physics-based high-injection transit-time model applied to barrier effects in SiGe HBTs,” IEEE Trans. Electron Devices, vol. 49, no. 10, pp. 1807–1813, Oct. 2002. J. Paasschens, W. Kloosterman, R. Havens, and H. de Graaff, “Improved compact modeling of output conductance and cutoff frequency of bipolar transistors,” IEEE J. Solid-State Circuits, vol. 36, no. 9, pp. 1390–1398, Sep. 2001. M. Schroter, H.-M. Rein, W. Rabe, R. Reimann, H.-J. Wassener, and A. Koldehoff, “Physics- and process-based bipolar transistor modeling for integrated circuit design,” IEEE J. Solid-State Circuits, vol. 34, no. 8, pp. 1136–1149, Aug. 1999.

Ullrich R. Pfeiffer (M’02) received the Diploma degree in physics and Ph.D. degree in physics from the University of Heidelberg, Heidelberg, Germany, in 1996 and 1999, respectively. In 1997, he was a Research Fellow with the Rutherford Appleton Laboratory, Oxfordshire, U.K., where he developed high-speed multichip modules. In 2000, his research was based on high-integrated real-time electronics for a particle physics experiment with the European Organization for Nuclear Research (CERN), Geneva, Switzerland. In 2001, he joined IBM and is currently a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. His current research involves RF circuit design, power-amplifier design at 60 and 77 GHz, high-frequency modeling, and packaging for millimeter-wave communication systems. Dr. Pfeiffer is a member of the German Physical Society (DPG). He was the recipient of the 2004 Lewis Winner Award for Outstanding Paper presented at the 2005 IEEE International Solid-State Circuit Conference

Alberto Valdes-Garcia (S’00) was born in 1978 and grew up in San Mateo Atenco, Mexico. He received the B.S. degree in electronic systems engineering (highest honors) from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico, in 1999, and is currently working toward the Ph.D. degree in electrical engineering at the Analog and Mixed-Signal Center (AMSC), Texas A&M University, College Station. In 2000, he was a Design Engineer with the Broadband Communications Sector, Motorola. From 2001 to 2004, he was a Semiconductor Research Corporation (SRC) Research Assistant at the AMSC working on the development of analog and RF built-in testing techniques. In the summer of 2002, he was with the Read Channel Design Group, Agere Systems, where he investigated wide tuning range gigahertz LC voltage-controlled oscillators (VCOs) for mass storage applications. During the summer of 2004, he was with the Mixed-Signal Communications IC Design Group, IBM T. J. Watson Research Center, where was involved with the design and analysis of millimeter-wave SiGe PAs. His current research involves system-level and RF circuit design for ultra-wideband (UWB) communications. Mr. Valdes-Garcia has been the recipient of a scholarship presented by the Mexican National Council for Science and Technology (CONACYT) since the Fall 2000. In 2005, he was the recipient of the Doctoral Thesis Award presented by the IEEE Test Technology Technical Council (TTTC).

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Design of Low-Power Fast VCSEL Drivers for High-Density Links in 90-nm SOI CMOS Gion Sialm, Christian Kromer, Student Member, IEEE, Frank Ellinger, Member, IEEE, Thomas Morf, Member, IEEE, Daniel Erni, Member, IEEE, and Heinz Jäckel, Member, IEEE

Abstract—The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50- load. The required chip area is only 140 m 140 m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than 10 12 to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model.

TABLE I COMPARISON OF LOW-POWER HIGH-SPEED DRIVERS



Index Terms—Common source (CS), modeling, optical interconnects, parasitics, source follower (SF), vertical-cavity surface-emitting laser (VCSEL).

I. INTRODUCTION

V

ERTICAL-CAVITY surface-emitting lasers (VCSELs) [1], [2] usually are the lasers of choice for short-distance single or high-density optical links [3]–[6]. The reasons are the possibility to manufacture them as two-dimensional arrays, which increases link density, their moderate power consumption at high data rates, and their low price. A critical block in an optical link is the VCSEL driver. A VCSEL driver consists of two blocks, i.e., the pre- and maindriver. Their tasks are as follows. The pre-driver steps down the capacitance of the VCSEL, and the main driver supplies the necessary output modulation current at a given bandwidth (BW). Signal preshaping, which might be necessary to improve the eye opening, can be performed in either block. Latency, an important parameter in communication systems, is usually minimized for drivers, which means that each stage bears the same delay [7]. Table I shows a comparison of recently published VCSEL drivers. As one can see, many of today’s high-speed VCSEL Manuscript received March 10, 2005; revised July 8, 2005. This work was supported by the Swiss Federal Office for Professional Education under Contract KTI 4900.1. G. Sialm, C. Kromer, F. Ellinger, and H. Jäckel are with the Electronics Laboratory, Swiss Federal Institute of Technology, 8092 Zürich, Switzerland (e-mail: [email protected]). T. Morf is with the Zürich Research Laboratory, IBM Research GmbH, 8803 Rüschlikon, Switzerland. D. Erni is with the Laboratory for Electromagnetic Fields and Microwave Electronics, Swiss Federal Institute of Technology, 8092 Zürich, Switzerland. Digital Object Identifier 10.1109/TMTT.2005.860893

drivers are implemented in SiGe technology. The reason is the larger supply voltage of more than 3 V and the better current drive capability of a bipolar process. In contrast, deep-submicrometer-CMOS technologies with gate lengths smaller than 0.1 m allow a maximum supply voltage of only approximately 1 V due to the thin gate oxide. This decreases the power consumption per BW, which is a key figure-of-merit (FOM) in high-density optical links because of the limited system power budgets. On the other hand, such a small supply voltage and the large modulation voltage required for driving a VCSEL make the development of CMOS drivers a challenging task. Thus, it is crucial to investigate which of the basic driver architectures, i.e., the common source (CS) or current mode logic (CML) driver, the common source with degenerated source (CSD), or the common drain [source follower (SF)], is able to perform the aforementioned tasks of a driver best for this low supply voltage and the required output modulation voltage for the VCSEL. Therefore, an analysis methodology including short channel transistor effects is developed, which allows the investigation of multistage drivers with respect to the aforementioned tasks of a driver and power consumption. In Section II, the driver specifications are evaluated. The methodology for the driver analysis and comparison is then explained in Section III. Based on this analysis, two driver topologies optimized with respect to the chip area and power consumption have been implemented in a 90-nm silicon-on-insulator (SOI) CMOS technology. Small- and large-signal electrical measurements, as well as optical measurements of the complete laser-driver are performed and compared with the results of the analysis in Section IV. II. DRIVER SPECIFICATIONS The driver specifications are derived from the VCSEL model described in [13] and [14]. The substrate of the VCSEL is un-

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TABLE III DRIVER SPECIFICATIONS FOR A BER

< 10

@ 12.5 Gb/s

Fig. 1. Measured optical (black) and simulated (white solid lines) VCSEL output at an operating current of 6 mA with a 50- driver and an ER of 6 dB at 12.5 Gb/s. The timescale is 20 ps/div.

TABLE II VCSEL PARAMETERS

Fig. 3.

Simplified small-signal equivalent circuit of MOSFET for

f < 40 GHz.

TABLE IV PARAMETERS OF n-FET

Fig. 2. Calculated relative eye opening with respect to an ideal square versus the electrical BW including driver, packaging, and VCSEL parasitics.

6.5 GHz corresponds to an overall BW of the transmitter of 8.5 GHz. The higher BW results from the resonance peak of the VCSEL at 6.7 GHz and corresponds well with 0.7 12.5 GHz. The VCSEL driver specifications are summarized in Table III. III. DRIVER ANALYSIS METHODOLOGY

doped because this type of VCSEL is superior in terms of speed compared with n- and p-substrate VCSELs. Fig. 1 demonstrates the accuracy of the laser model for an eye diagram at a data rate of 12.5 Gb/s and an optical extinction ratio (ER) of 6 dB (according to the Optical Internetworking Forum VSR-3 standard). The operating current was chosen to be 6 mA, which is a good tradeoff between power consumption and BW. The key parameters of the VCSELs at this operating current, which are used for the driver specifications, are listed in Table II. They have been extracted from the modulation transfer function (MTF) and the reflection coefficient of the VCSEL. The minimum electrical BW, including driver, packaging, and VCSEL parasitics for a data rate of 12.5 Gb/s, is determined numerically by calculating the relative optical eye opening. Fig. 2 shows the result. As one can see, the lower limit of the electrical BW is approximately 6.5 GHz because, for smaller BWs, the eye opening deteriorates significantly. An electrical BW of

Based on the parameters of the driver specification, we propose the following methodology to analyze and compare the two stage drivers in Fig. 4 in terms of the power consumption and the driver tasks, namely, the capability of stepping down the load capacitance and providing the necessary BW: First, we derive the small- and large-signal models for this short-channel CMOS technology and the parameters required for the driver analysis. Second, in the driver analysis, we calculate the input capacitance and the power consumption dependent on the output modulation voltage , which is due to the fixed VCSEL load proportional to the output modulation current . Capacitance allows the stepping-down ratio to be determined. Third, the power consumption and capability of stepping down the load capacitance of these three drivers are compared. This is done for different output modulation voltages and under the condition that all drivers have the same BWs and output resistances .

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Fig. 4. Schematics of two stage drivers analyzed. (a) CS main and pre-driver. (b) CSD main and pre-driver. (c) SF main driver with CS pre-driver with Z dummy load with the same electrical characteristics as the VCSEL.

as

A. SOI Technology SOI CMOS technology was chosen for the drivers because SOI transistors outperform bulk transistors having the same channel length in terms of speed. The n-field-effect transistors (n-FETs) of the 90-nm SOI technology can be modeled with the small-signal equivalent circuit depicted in Fig. 3. The relevant parameter values are listed in Table IV. The large-signal transistor model comprises only the expression for the saturation, as in the driver analysis, the transistors are kept in saturation. According to [16] and [17], velocity saturation must be taken into account for short channel transistors. This can be done with the following model:

The transconductance is equal to , where . Parameter represents the unused headroom normalized to , and is the total load, which includes and the internal resistor of the CS. Parameter corresponds to the difference between and the maximum output voltage normalized to , where is the voltage common mode at the output of the CS. The effective voltage overdrive can be obtained by eliminating the transconductance in the expression for and . The expression is relegated to the Appendix. The expression for can be derived from (1) as follows:

(1) where , denotes the large-signal transconductance, denotes the effective gate overdrive voltage, denotes the voltage at which the velocity of the electrons starts to saturate, denotes the short channel parameter, and denotes the channel length modulation parameter. For long channel transistors, . The extracted values for and are 0.35 V and 1.3 , respectively. B. Driver Analysis Here, we explain the analysis procedure required to investigate a single driver stage. The procedure is valid independent of the stage architecture and, therefore, only explained at the example of the CS. The input parameters for the analysis procedure of the main driver are the following. The VCSEL resistance and capacitance (Table II), the operating current , the output modulation voltage and the BW from the driver specifications (Table III), the technology parameters such as the intrinsic gain (Table IV), and the drain–source voltage of the current source used in a differential stage. is determined by a tradeoff between the voltage headroom of the driving transistors and the width of the current source. The larger is, the smaller are both the transistor width and headroom. In the first step of the procedure, the transistor parameters , , and are determined using the aforementioned parameters. This can be done in the following way.

(2) with The remaining parameter values to be defined in the expressions for , and are the unused headroom , the total load , and the voltage gain . Parameter is chosen to be 0 for the CS main drivers. According to (2), this allows one to achieve the minimum width for a given and and, thus, the maximum speed. This means that the supply voltage of the VCSEL in Fig. 4(a) and (b) is , where is the operating voltage of the VCSEL. The difference between of the VCSEL and of the CS is assumed to be provided by a separate current source. The additional capacitance of the current source is neglected in the analysis because this capacitance is small compared with the one of the VCSEL. The total load includes and the internal resistor of the CS. is required to improve the BW because the BW, which corresponds to the RC constant of the VCSEL, is only 3.7 GHz. Resistor can be determined with the condition that all main drivers architectures have the same output resistance . The voltage gain can be determined from the four boundaries in Table V, which are illustrated in Fig. 5. This can be done by inserting into the four boundaries and solving for . The second condition is only used for the CS. Applying this boundary means that the CS works uniquely in saturation even in the worst case, which occurs when the input voltage reaches

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TABLE V CONDITIONS FOR THE CALCULATION OF THE VOLTAGE GAIN

nant pole at the output can be estimated according to [17] with the following equation:

A

(4) is required to calAs one can see, the input resistance culate the BW. Knowing the BW of one stage, therefore, allows to be determined. The BW of one stage can be derived from the overall BW in the driver specifications (6.5 GHz) while keeping the latency minimal. This means that each stage has the same BW. Deriving the BW of a single driver stage with a dominant pole for the two-stage drivers analyzed yields a value of 10.1 GHz for the specified 6.5 GHz. The same equations can be derived for the SF. They are relegated to the Appendix. Three main differences exist between the is determined by the required voltage CS and the SF. First, gain, intrinsic gain, and load resistance and cannot be chosen arbitrarily as for the CS. Second, the way the unused headroom is determined; whereas for the CS, the value was chosen to be 0 because of the speed, the unused headroom of the SF is chosen in such a way that the common mode current is just of the VCSEL. This yields the maximum gain required for the modulation of the VCSEL and a small , allowing a high speed. Third, only condition 1 in Table V is used to determine , as the SF is always in saturation as long as the maximum gate voltage is smaller than . The analysis procedure of the pre-drivers in Fig. 4 is the same as the one of the main drivers. The input parameters whose values differ from those of the main driver are , , the load resistance , and the load capacitance . and correspond to the input resistance and capacitance of the main driver, respectively. Based on these values, the required voltage gain can be calculated, which, in turn, allows the remaining transistor parameters of the pre-driver to be determined. Fig. 5. Overlapped qualitative input and output characteristics of a transistor with the boundaries listed in Table V. The solid and dashed lines belong to (lower axis) and (upper axis), respectively. The dashed black line denotes is + the load line of a CS. For the CS main and pre-driver ( 2) and , respectively.

1v = 0 V

V

V 0 x 1 1v 0 V

V

V

V

V 0

its maximum and the output voltage its minimum. This enables superior speed and linearity. In the second step of the procedure, the transistor capacitances and the input capacitance are estimated. Assuming that transistor capacitances scale with the transistor width, they can be determined with . The reason is that is proportional to the transistor width as long as the channel lengths are the same. Based on the transistor capacitances, the input capacitance can be estimated with the following equation: (3) In the third step of the procedure, the BW is calculated. The BW of the CS with a large load capacitance and, thus, a domi-

C. Driver Comparison The main parameters of the drivers analyzed in Fig. 4 with the same output resistance and BW are plotted versus in Fig. 6. As the transconductance is optimized in a digital technology for , is chosen to be 0.15 V yielding V. This is close to . The results for V are summarized in Table VI. The lower and upper boundaries of in Fig. 6 are 0.3 V (for lower values, the necessary BW cannot be achieved) and the maximum achievable V of the SF. This corresponds to a between 4.8–9 mA. For the CS, a small load (e.g., VCSEL resistance or ) especially increases the transistor width and power consumption yielding a small BW. The CSD depicted in Fig. 4(b) is a CS driver with a shunt resistor between the sources of the driving transistors. The advantage of this resistor is a reduced sensitivity of the gain and BW to process variations and an increased linearity due to a smaller voltage gain. The parameters of a CS and CSD stage are the same, except for a higher output resistance, smaller voltage

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Fig. 6. Driver comparison. Main driver: (a) common total output load, (b) voltage gain, and (c) input capacitance for different output modulation voltages. Pre-driver: (d) voltage gain and (e) input capacitance. (f) Power consumption of complete driver.

gain, and lower because of the reduced Miller effect and . According to Fig. 6(b) and (c), the shunt resistor has only a small influence and, thus, is small. There are three reasons, i.e., first, the little voltage headroom due to the small supply voltage; second, the small intrinsic gain; and third, the small output resistance. A small , however, is not desirable, as the increase of the linearity and the decrease of the sensitivity to process variations become too small. Increasing the voltage gain by lowering will increase only moderately. As a result, this topology is especially suited if the is large and is higher than the one calculated with condition 2. The SF has a maximum of 0.57 V because, for higher , the minimum calculated with condition 1 is larger than the maximum allowed determined by condition 3. Table VI reveals that the SF features a low output resistance at a relative small width yielding small capacitances and, thus, allowing a high input resistance. Moreover, the SF shows small power consumption and allows one to modulate VCSEL arrays with a common cathode. A drawback might be the need of a negative power supply. IV. IMPLEMENTATION AND MEASUREMENTS Based on the results of the driver comparison, we implement an optimized CSD and SF topology as the main driver. These topologies were chosen because of the reduced sensitivity to process variations of the CSD compared with that of the CS and the lower power consumption of the SF. Both drivers are further optimized with respect to power consumption, chip area, and speed. Their schematics are shown in Fig. 7.

The CSD topology is implemented as a differential to single-end (DSE) driver. This increases the voltage gain and lowers the power consumption, as no dummy load is required. The SF driver has three stages. The second pre-driver is a DSE driver with the advantages explained above. The resistor at the output increases the drain–source current, which improves the voltage gain and lowers of the main driver. The first stage of the pre-driver is a CS because the CS in addition improves the voltage gain and, according to the analysis, has a smaller input capacitance than a CSD stage. To compensate manufacturing variations or temperature changes, can be adjusted in two ways, i.e., either by varying the voltage or by adding an additional current source in parallel to the SF, which, however, will deteriorate the BW. Both drivers were connected with the VCSELs by bonding wires having a length of approximately 0.8 mm. Fig. 8 shows small- and large-signal measurements of the drivers in Fig. 7. The small-signal measurements in Fig. 8(a) and (d) are single-ended measurements used to verify the largesignal SOI Berkley short channel insulated gate FET model (BSIM). The deviation in Fig. 8(a) results from the somewhat too optimistically modeled p-FET devices. The differential BW calculated with SOI BSIM models is, according to Fig. 8(b) and (e) 22 and 18 GHz for the DSE and SF drivers, respectively. As expected, the gain is approximately doubled compared with the single-end measurements. The measurements confirm that the voltage gain of the SF is higher than that of the DSE driver because of the first stage in the pre-driver. Fig. 8(c) and (f) clearly show open eyes at a data rate of 12.5 Gb/s for both drivers.

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TABLE VI COMPARISON OF THE ANALYZED PRE- AND MAIN DRIVER TOPOLOGIES IN FIG. 4

Fig. 7. Simplified schematics of the drivers implemented. The first number indicates the width in micrometers and the second number indicates the gate length in nanometers.

Table VII summarizes the parameters measured and those calculated with the analysis methodology discussed. The output re-

sistance and BW (including the VCSEL parasitics) in the simulation are the same as in the measurements.

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Fig. 8. (a) and (d) Measured and simulated electrical single-ended S . The BW of the DSE driver and of the SF is 13 and 18 GHz, respectively. The power consumption is always 14 and 17 mA for the DSE and SF driver, respectively. (b) and (e) Simulated differential S -parameters. The BW of the DSE driver and of the SF is 22 and 18 GHz, respectively. (c) and (f) Measured electrical eyes at 12.5 Gb/s with an output modulation voltage of 0.4 V on a 50- load. TABLE VII CALCULATED VERSUS MEASURED KEY PARAMETERS

Fig. 9. Measured optical eyes when driving VCSELs at 12.5 Gb/s at an operating current of I = 6 mA and an ER = 6 dB. (a) The DSE driver. (b) The SF architecture.

Simulations have shown that by substituting the passive load in the CSD main driver shown in Fig. 4(b) with an active one according to Fig. 7(a), one can improve BW and decrease power consumption. The reason for the higher BW is that the active load yields a current peaking and, in addition, improves the voltage gain, which requires smaller driving transistors. The power consumption could be reduced by 35%. For the SF, the BW (including the VCSEL parasitics) is the same as in the measurements. , however, is calculated. As one can see, the deviation between the calculated and measured values is less than 15%. The BW of the total driver is smaller than the measured one because the BW of one stage was chosen to be minimal, which corresponds to 16.9 GHz for a three-stage driver. Substituting the VCSEL load with a 50- load increases the BW of the main driver. However, the BWs of the two stages in the pre-driver still are the same, yielding a pre-driver BW of 11 GHz. The power consumption could be reduced by 45% using a DSE pre-driver instead of the conventional CSD driver shown in Fig. 4(b). The optical measurements of the drivers with a VCSEL are shown in Fig. 9. The SF driver exhibits a larger overshoot than the DSE driver. This can be explained by the higher BW of the

SF, which confirms the calculations of the analysis. The higher overshoot and steeper falling edge decrease the eye opening. This can be seen in the larger deterministic jitter in the upper middle of the optical eye. In contrast, the smaller BW of the DSE driver shows minimal overshoot and minimal deterministic timing jitter. Comparing Fig. 1 with Fig. 9 reveals that an appropriate driver topology can equalize overshoot and nonlinearity, resulting in an improved eye opening (15% for SF and 30% for DSE). In summary, the SF is a suitable topology for driving a VCSEL because of the low power consumption. However, the ongoing decrease of the power supply voltage will make it difficult to reach the necessary output modulation current or voltage in future CMOS technologies. The DSE driver has a smaller BW, yielding a minimal overshoot and accordingly a small deterministic jitter. V. CONCLUSION Using an analysis methodology that allows one to investigate multistage drivers, we have explored the capability of stepping down the load capacitance and the power consumption of two-stage drivers with the same output resistance and BW. The

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TABLE VIII EQUATIONS USED FOR THE DRIVER ANALYSIS

main drivers are a CS, a CSD, and an SF topology. The result of the analysis has demonstrated that the SF is well suited for driving VCSELs at high data rates, as the power consumption is small and VCSELs in a common cathode configuration can be modulated. Two different power-optimized CMOS driver architectures have been implemented: a DSE and an SF driver. Applying a 10-Gb/s VCSEL yielded clearly open eyes even at a data rate of 12.5 Gb/s. The chip area used is only 140 m 140 m, which is small compared with that of a peaking transformer, whose size can be as large as 95 m 95 m [12]. An accurate VCSEL model was applied to develop and optimize the driver. The implementation of a DSE driver allowed a reduction of the power consumption by approximately 30% compared with a conventional CS driver. The SF had the same DSE driver as pre-driver, which enabled a 45% reduction of the power consumption. The measurement results exhibited clearly open optical eyes for both drivers. These VCSEL drivers with a BW of 18 GHz have, to the best of our knowledge, the lowest power consumption per gigabit per second to date and a small chip size. APPENDIX Table VIII shows the equation used in the driver analysis for all three kinds of driver architectures. ACKNOWLEDGMENT The authors would like to thank S. Hunziker, Avalon Photonics Ltd., Zürich, Switzerland, for supplying the VCSELs [18], [19]. REFERENCES [1] K. Iga, “Vertical-cavity surface-emitting laser: Introduction and review,” in Vertical-Cavity Surface-Emitting Laser Devices. Berlin, Germany: Springer-Verlag, 2003, pp. 1–27. [2] W. W. Chow, K. D. Choquette, and S. W. Koch, “Physics of the gain medium in vertical-cavity surface-emitting semiconductor lasers,” in Vertical-Cavity Surface-Emitting Laser Devices. Berlin, Germany: Springer-Verlag, 2003, pp. 31–51.

[3] J. Ahadian, M. Englekirk, M. Wong, T. Li, R. Hagan, R. Pommer, and C. Kuznia, “A quad 2.7 Gb/s parallel optical transceiver,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 13–16. [4] D. M. Kuchta, Y. Kwark, C. Schuster, C. Baks, C. Haymes, J. Schaub, P. Pepeljugoski, L. Shan, R. John, D. Kucharski, D. Rogers, M. Ritter, J. Jewell, L. Graham, K. Schrödinger, A. Schild, and H.-M. Rein, “120Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station,” J. Lightw. Technol., vol. 22, no. 9, pp. 2200–2212, Sep. 2004. [5] J. Simon, L. Windower, S. Rosenau, K. Giboney, B. Law, G. Flower, L. Mirkarimi, A. Grot, C.-K. Lin, A. Tandon, G. Rankin, R. Gruhlke, and D. Dolfi, “Parallel optical interconnect at 10 Gb/s per channel,” in IEEE Electronic Components and Technology Conf., Orlando, FL, 2004, pp. 1016–1023. [6] C. Kromer, G. Sialm, C. Berger, T. Morf, M. L. Schmatz, F. Ellinger, D. Erni, G.-L. Bona, and H. Jäckel, “A 100 mW 4 10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects,” in IEEE Int. Solid-State Circuit Conf., San Francisco, CA, Feb. 2005, pp. 334–335. [7] I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. San Francisco, CA: Morgan Kaufmann, 1999. [8] Y. Ohtomo, T. Yoshida, M. Nishisaka, K. Nishimura, and M. Shimaya, “A single-chip 3.5 Gb/s CMOS/SIMOX transceiver with automatic gain control and automatic-power-control circuits,” in IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 2000, pp. 58–59. [9] B. Madhavan and A. F. H. Levi, “Low-power 2.5 Gbit/s VCSEL driver in 0.5 m CMOS-technology,” Electron. Lett., vol. 34, pp. 178–179, 1998. [10] A. A. Ciubotaru and J. S. Garcia, “An integrated direct-coupled 10 Gb/s driver for common-cathode VCSELs,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 426–433, Mar. 2004. [11] D. M. Kuchta, P. Pepelijugoski, and Y. Kwark, “VCSEL modulation at 20 Gb/s over 200 m of multimode fiber using a 3.3 v SiGe laser driver IC,” presented at the LEOS Summer Topical Meeting Tech. Dig., 2001, Paper WA2.1. [12] D. Kucharski, Y. Kwark, D. Kuchta, D. Guckenberger, K. Kornegay, M. Tan, C. Lin, and A. Tandon, “A 20 Gb/s VCSEL driver with preemphasis and regulated output impedance in 0.13 m CMOS,” in Int. Solid-State Cicuits Conf., 2005, pp. 222–224. [13] G. Sialm, D. Erni, D. Vez, G. L. Bona, T. Morf, C. Kromer, F. Ellinger, and H. Jäckel, “Trade-offs of VCSEL modeling for the development of driver circuits in short distance optical links,” Opt. Eng., vol. 44, no. 10, pp. 105 401-1–105 401-15, Oct. 2005. [14] M. Jungo, D. Erni, and W. Bächtold, “VISTAS: A comprehensive system-oriented spatiotemporal VCSEL-model,” IEEE J. Sel. Topics Quantum Electron., vol. 9, no. 3, pp. 939–948, May/Jun. 2003. [15] F. Ellinger, T. Morf, G. von Büren, C. Kromer, G. Sialm, L. Rodoni, M. Schmatz, and H. Jäckel, “60 GHz VCO with high tuning range fabricated on VLSI SOI CMOS technology,” in IEEE MTT-S Int. Microwave Symp. Dig., Fort Worth, TX, Jun. 2004, pp. 1329–1332.

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[16] Y. Cheng and C. Hu, MOSFET Modeling and BSIM3 User’s Guide. Boston, MA: Kluwer Academic, 1999. [17] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998. [18] D. Vez, S. Eitel, S. G. Hunziker, G. Knight, M. Moser, R. Hoevel, H.-P. Gauggel, M. Brunner, A. Hold, and K. H. Gulden, “10 Gbit/s VCSEL’s for datacom: Devices and applications,” Proc. SPIE–Int. Soc. Opt. Eng., vol. 4942, pp. 29–43, 2003. [19] S. Eitel, S. G. Hunziker, D. Vez, M. Moser, R. Hoevel, H.-P. Gauggel, M. Brunner, and K. H. Gulden, “Multimode VCSEL’s for high bit-rate and transparent low-cost fiber-optic links,” Proc. SPIE–Int. Soc. Opt. Eng., vol. 4649, pp. 183–190, 2002.

Gion Sialm received the M.S. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 1995, and is currently working toward the Ph.D. degree at the ETH in collaboration with the IBM Zürich Research Laboratory, Rüschlikon, Switzerland. He was an Information Technology (IT) Manager with a company involved in worldwide activities, where he built up the IT and telecommunication infrastructure. In 2000, he joined the IT Department, Swiss Federal Institute of Technology, where he both headed, as well as implemented high-availability projects for database and e-mail applications. His research interests include networking, optical interconnects, and CMOS analog RF circuit design.

Christian Kromer (S’98) received the M.S. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 1996, and is currently working toward the Ph.D. degree at the ETH in collaboration with the IBM Research Laboratory, Zürich, Switzerland. In 1997, he joined the LSI Logic Corporation, Milpitas, CA, where he was engaged in printed circuit board design for a quadrature phase-shift keying (QPSK) receiver system integrated-circuit (IC) design for an eight-phase-shift keying (8-PSK) demodulator and discrete RF circuit design. His research interests are in optical interconnects and CMOS analog RF circuit design.

Frank Ellinger (S’97–M’01) was born in Friedrichshafen, Germany, in 1972. He received the M.S. degree in electrical engineering from the University of Ulm, Ulm, Germany, in 1996, both the Masters degree in business and administration (MBA) and Ph.D. degree in electrical engineering, and both the Habilitation (post-doctoral) degree in electrical engineering, and Venia Legendi (university teaching degree) in circuit design from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 2001 and 2005, respectively. In 2001, he was with the Wireless Marketing Division, Infineon, Munich, Germany. Since 2001, he has been Head of the RFIC Design Group of the Electronics Laboratory, ETH, and Project Leader of the IBM/ETH Competence Center for Advanced Silicon Electronics, Rüschlikon, Switzerland. He also lectures at the ETH. His main interests are the design of integrated circuits for high-speed wireless and optical communication. He has authored as primary author over 40 refereed papers, most of them IEEE journal contributions. He holds three patents. Dr. Ellinger was program chair of the Workshop on Compound Semiconductor Devices and Integrated Circuits Europe in 2003. In 2005, he became an associate editor of the IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS. One of his recent publications has been among the third most-read (downloaded) IEEE JOURNAL OF SOLID-STATE CIRCUITS papers in May 2004. He was the recipient of several awards including the Rohde & Schwarz/Agilent/Gerotron EEEfCOM Award, the Denzler Award of the Swiss Electrotechnical Association (SEV), the ETH Medal, and the Young Ph.D. Award of the ETH (Bonus 29).

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Thomas Morf (S’89–M’97) was born on April 4, 1961, in Zürich, Switzerland. He received the B.S. degree from the Winterthur Polytechnic Switzerland, Winterthur, Switzerland, in 1987, the M.S. degree in electrical engineering from the University of California at Santa Barbara (UCSB), in 1991, and the Ph.D. degree from the Eidgenössische Technische Hochschule (ETH), Zürich, Switzerland, in 1996. His doctoral research concerned circuit design and processing for high-speed optical links on GaAs using epitaxial liftoff techniques. In 1996, he joined the Electronics Laboratory, ETH where he led a research group in the area of InP–HBT circuit design and technology. Since Fall 1999, he has been with the Zürich Research Laboratory, IBM Research GmbH, Rüschlikon, Switzerland. His current research interests include all aspects of electrical and optical high-speed high-density interconnects and high-speed and microwave circuit design.

Daniel Erni (S’88–M’93) was born in Lugano, Switzerland, in 1961. He received the El.-Ing. HTL degree from the Interkantonales Technikum Rapperswil HTL, Switzerland, in 1986, and the Dipl. El.-Ing. degree and Ph.D. degree for the investigation of nonperiodic waveguide gratings and nonperiodic coupled cavity laser concepts from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 1990 and 1996, respectively. Since 1990, he has been with the Laboratory for Electromagnetic Fields and Microwave Electronics, ETH, where he is involved with nonlinear wave propagation, laser diode modeling (multisection distributed feedback (DFB) and distributed Bragg reflector (DBR) lasers, and VCSELs), computational electromagnetics, and the design of nonperiodic optical waveguide gratings, e.g., by means of evolutionary algorithms. He is the Head of the Communication Photonics Group, ETH. His current research interests includes highly multimode optical signal transmission in optical interconnects (i.e., in optical backplanes with extremely large waveguide cross sections), as well as alternative waveguiding concepts for dense integrated optical devices such as photonic crystal devices, couplers, and wavelength division multiplexing (WDM) filter structures. Dr. Erni is a member of the Swiss Physical Society (SPS), the German Physical Society (DPG), and the Optical Society of America (OSA). He was the recipient of the 2000 Outstanding Journal Paper Award presented by the Applied Computational Electromagnetics Society for a contribution on the application of evolutionary optimization algorithms in computational optics.

Heinz Jäckel (M’82) received the Doctorate degree in electrical engineering from the Eidgenössische Technische Hochschule (ETH), Zürich, Switzerland, in 1979. In 1980, he joined IBM, where he held scientific and management positions for 13 years in the research laboratories of IBM, Rüschlikon, Switzerland, and Yorktown Heights, New York. During this time, he carried out research projects in the field of device and circuit design for superconducting Josephson junction computers, GaAs–MESFET logic, and memory integrated circuits (ICs) and opto-electronics. In 1988, he was instrumental in the establishment of the opto-electronic project at IBM, where he subsequently managed optical storage device activities. Since 1993, he has been a Full Professor of analog electronics with the Electronics Laboratory, ETH. The research activities of his High Speed Electronics and Photonics Group, ETH, concentrate on the following topics: technology, design and characterization of ultrafast transistors (mainly InP-based heterojunction bipolar transistors), and circuits for multi-10 gigabit electronics, integrated-circuit (IC) design of RF circuits for mobile communication, and CMOS application-specific integrated circuits (ASICs) for sensory technology. In the area of lightwave communication, the group pursues research on photonic devices and integrated optical circuits for data transmission, particularly InP-based all-optical devices for all optical signal processing at terabit/s data rates.

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Switched Resonators and Their Applications in a Dual-Band Monolithic CMOS LC -Tuned VCO Seong-Mo Yim and Kenneth K. O

Abstract—A switched resonator concept, which can be used to reduce the size of multiple-band RF systems and which allows better tradeoff between phase noise and power consumption, is demonstrated using a dual-band voltage-controlled oscillator of the (VCO) in a 0.18- m CMOS process. To maximize switched resonator when the switch is on, the mutual inductance between the inductors should be kept low and the switch transistor factor of switched resonators is size should be optimized. The 30% lower than that of a standalone inductor. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of 125 and 123 dBc Hz at a 600-kHz offset and 16-mW power consumption. Compared to a single-band 1.8-GHz VCO, the dual-band VCO has almost the same phase noise and power consumption, while occupying 37% smaller area. Index Terms—Dual band, multiband, phase noise, power consumption, RF receivers, switched inductors, switched resonators, variable inductors, voltage-controlled oscillator (VCO).

I. INTRODUCTION

T

HE proliferation of wireless applications is rapidly increasing the demand for low-cost communication terminals, which can support multiple standards and frequency bands. In response to this, multiband terminals using multiple RF transceivers have been reported [1], [2]. This, however, increases die area or chip count in a radio, which, in turn, increases cost and complexity of radios. A way to mitigate this is the use of a tunable/programmable transceiver consisting of a tunable low-noise amplifier [3], [4], buffers and mixers, and a voltage-controlled oscillator (VCO) with a wide tuning range. To realize the tunable RF blocks, the variable inductor concept has been previously reported [5]–[8] and utilized first in a VCO [6]. The VCO partially relies on the changes in series resistance of an inductor to attain continuous variations of effective inductance. This resistance, however, significantly degrades of the resonator and phase noise of the VCO. To reduce the degradation of phase noise, a switched resonator concept (dotted rectangle in Fig. 1) is proposed and demonstrated in a dual-band VCO, and a VCO with a tuning range greater than 50% and excellent phase-noise performance [8]–[11]. In fact, the VCO in [11] achieves the lowest phase noise among CMOS VCOs operating near 2.4 and 5.2 GHz. In this paper, the Manuscript received July 20, 2004; revised January 11, 2005 and May 25, 2005. This work was supported by Jazz Semiconductor under a grant. S.-M. Yim was with the Department of Electrical and Computer Engineering, Silicon Microwave Integrated Circuits and Systems Research Group, University of Florida, Gainesville, FL 32611 USA. He is now with Micro Devices, Greensboro, NC 27409 USA (e-mail: [email protected]). K. K. O is with the Department of Electrical and Computer Engineering, Silicon Microwave Integrated Circuits and Systems Research Group, University of Florida, Gainesville, FL 32611 USA. Digital Object Identifier 10.1109/TMTT.2005.856102

Fig. 1.

Schematic of a dual-band VCO.

measured and simulated characteristics of switched resonators including the quality factor are reported. Analytical expressions, which explain the behaviors of switched resonators, as well as the design considerations and approaches to improve their properties are presented. Lastly, this paper suggests that a dual-band VCO using switched resonators can have the same phase noise and power consumption while occupying a smaller area than that for two VCOs needed to cover the two bands. II. NEED FOR A SWITCHED RESONATOR A possible way to achieve a wide tuning range is to use a switched capacitor bank in a resonator [12]. To qualitatively discuss the need for a switched resonator over a switched capacitor bank, consider the – VCO shown in Fig. 1. Since the quality factor of the on-chip spiral inductor is significantly lower than that of the capacitances in the resonator, especially at frequencies between 1–2 GHz, the equivalent total parallel resistance can be approximated by the equivalent parallel resistance of the inductor . For an inductor with series resistance of and inductance of , the is approximately or , where is the desired oscillation frequency. To sustain oscillation, the loop gain (1) is the effective transconductance of the VCO core where transistors. With the assumption that, for a given process technology, when inductance changes, its series resistance also changes with approximately the same ratio, i.e., is approximately constant, if or is larger, then can be smaller or power consumption of the VCO can be reduced since

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-TUNED VCO

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. Due to this, if is reduced by increasing only the capacitance, then must be increased as ( ). This results in significantly higher power consumption and core transistor size than would be needed if both and were to be increased. At the same time, increasing only arbitrarily high will increase the series resistance . When the core voltage swing is near the maximum, which is how VCOs are typically designed to operate, this will limit the phase-noise performance. This is also undesirable and points to the need for a switched resonator in which both and can be tuned. The phase-noise limitation imposed by arbitrarily increasing can be explained using the Leeson–Cutler phase-noise equation [13]–[15] as follows:

(2) where is the Boltzmann’s constant, is the absolute temperature, is the noise factor of core transistors/amplifiers, is the average power dissipated in the tank, is the oscillation frequency, is the quality factor of the total tank, and is the offset from the carrier. is where is the root mean square voltage across the tank. As mentioned, since , and the total parallel resistance ( ) of the tank is , when the voltage swing is near the maximum, for given , phase noise is only determined by the noise factor and . Due to this, to reduce phase noise, should be lowered. These mean if is chosen for the higher frequency band and the same is used for the lower frequency band using a large switched capacitor bank, the power consumption at the lower frequency band may be higher than needed. Since the core transistor size should be made larger to support the larger power consumption, this will also reduce the VCO tuning range especially at the higher band. On the other hand, if is chosen for the lower frequency band, then phase-noise performance at the higher frequency band will be compromised. Due to these, an element in which both and can be simultaneously tuned provides a greater flexibility to trade off phase noise, power consumption, and tuning range due to greater flexibility for choosing , and enables implementation of a VCO with given phase noise over a large frequency range at lower power consumption. Lastly, for VCOs implemented in deep submicrometer CMOS processes, another contributor to of a tank is the output resistance of the transistors. As will be discussed, this can reduce the impact of lower of switched resonators. III. SWITCHED RESONATOR CONCEPT Fig. 2(a) and (b) shows switched resonators including mutual inductance ( ). The inductance seen between ports 1 and 2 are changed by turning the switch transistor on and off. The equivalent circuit of the switched resonator is shown in Fig. 2(c). In the case that port 2 is grounded and that and have no mutual effect ( ), the resonator is simplified into the circuit in

Fig. 2. (a) and (b) Two-use configurations of a switched resonator. (c) An equivalent circuit of a switched resonator in (a). (d) The equivalent circuit when port 2 is ac grounded and the switch is on. (e) The equivalent circuit when the switch is off.

Fig. 2(d) when the switch is on, and into the circuit in Fig. 2(e) when off. When the switch is off, the inductance of switched resonator is largely determined by the two inductors while the capacitance is determined by the parasitic capacitances ( ’s and ) of the inductors and the capacitances ( and ) at the drainoftheswitchtransistor.The extractedinductance usingmeasurements and the simple inductor model is lower due to the effects of in series with , and of the switch transistor ( ) [16]. When the switch is on, the channel resistance is close to zero. The inductance and capacitance of the switched resonator are switched by shorting out , the capacitances associated with , , and theswitch transistor.The inductance isapproximately and the capacitance is , thus, leading to simultaneous decreases of inductance and capacitance. IV. DESIGN AND EXTRACTED PARAMETERS OF THE SWITCHED RESONATORS Fig. 3 shows the test structures used to develop better understanding of the characteristics and limitations of switched resonators. The structures were fabricated in a 0.18- m CMOS

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TABLE I SWITCHED RESONATOR IN FIG. 3(a)

Fig. 3. Photomicrographs of switched resonators with parallel and offset topologies. (a) An offset structure with W=L of NMOS = 2 mm=0:18 m. (b) A parallel structure with W=L of NMOS = 2 mm=0:18 m. The current directions of i and i are shown on the inductors.

process. and [see Fig. 2(a) and (b)] have 3.25 turns with a metal linewidth of 19 m, and 4.25 turns with a metal width of 10 m, respectively. The inductors are formed by shunting metal 3–5 layers. The total metal thickness is 4 m. The switch transistor is 0.18- m long. This small channel length is required to minimize the channel resistance and to minimize the quality-factor reduction when the switch is on. Due to uses of short gate fingers, the gate resistance is sufficiently low and its impact is negligible. In Fig. 3(a), and are separated and offset to reduce the impact of mutual inductance between the inductors. The structure in Fig. 3(a) has an nMOS switch transistor ( ) with a width of 2 mm. Though not shown, another structure similar to that in Fig. 3(a) with a transistor width of 1 mm also has been fabricated. The simulated ’s with of 2.7 V ( of V), which can be generated using a voltage doubler [17] are 0.4 and 0.8 compared to 2.1 and 2.9 low-frequency series resistances of and . Although low, this finite decreases of . For the structure in Fig. 3(b), and are located in parallel. This increases the mutual inductance ( ) between the structures to 0.26 nH. This, however, is still significantly smaller than and . In addition to these, and are separately fabricated to study the impact of using the inductors in switched resonator structures. The extracted inductances ( ) of and from measurements using an HP8510C two-port network analyzer are 4.7 and 6.1 nH, the series resistances ( ) are 1.7 and 3.1 , and the parasitic capacitances ( ) are 500 and 360 fF, respectively (Table I). and are measured at 45 MHz. is measured at 300 MHz. The equivalent-circuit model and plots for the model parameters and [18] versus frequency are shown in Fig. 4. increases more rapidly with frequency than that expected from the skin and proximity effects and, at frequencies above 3 GHz, it decreases. These are due to modeling the inductor using a simple lumped model [see Fig. 4(a)] rather than using a distributed model [16]. Figs. 5 and 6 show the measured , , , and [see Fig. 5(e)] for the switched resonator when the switch is on and off, respectively. The dc voltage of 0.9 V is applied to ports 1 and 2. The threshold voltage of the switching

Fig. 4. (a) Lumped-element model for a planar spiral inductor. (b) Measured L, (c) R , (d) C , and (e) Q versus frequency plots for L and L .

transistor is increased due to the body effect, which slightly increases the on resistance. and have stronger frequency dependence than and and can even become negative. The stronger frequency dependence of and and negative are due to the fact that, in the presence of additional parasitic capacitances

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When the switch is on, assuming the channel resistance ( is zero, and are expressed by

)

(3) and (4) When the switch is off, assuming , are are

and

(5) and

(6) where

Fig. 5. Plots of: (a) L , (b) R , (c) C , and (d) R versus frequency when the switch is on. (e) The lumped-element model for a switched resonator.

Fig. 6. Plots of measured and simulated: (a) L , (b) R (d) R versus frequency when the switch is off.

, (c) C

, and

( (630 fF) and (790 fF), the effects of modeling a distributed structure using a simple lumped section become stronger [16]. The structure resonates at the frequencies near . The self-resonant frequencies of structures are significantly reduced compared to that for and . However, the structures are still useful at frequencies below 2.5 GHz when the switch is on and below 1.5 GHz when the switch is off.

(7) The mutual inductance, when positive, increases the ratio between inductances when the switch is off and on. This, however, also reduces the quality factor when the switch is on because of lower inductance. Referring to Fig. 5(a) and (b), the nonnegligible on-resistance ( ) increases and to be greater than and of when the switch is on. Figs. 5 and 6 also show simulated , , , and . The models for individual inductors and transistor are used for the simulations. The measured and simulated results are in qualitative agreement, especially within the intended operating frequency range between 1–2 GHz. Except for , when the switch is on, the simulation results below 2 GHz are within 30% of the measured results. Fig. 7 shows , , , and [see Fig. 5(e)] versus the gate-to-source voltage ( ) of the switch for the structures shown in Fig. 3. As the transistor in Fig. 3(a) is switched from off to on, , , and decrease, but increases, as shown in Fig. 7(a)–(d) and Table I. This increase is due to the channel resistance and resistances in series with and . Due to the frequency dependences, and are specified at the lowest measurement frequency, and to avoid measurement errors, and are extracted at higher frequency, but significantly lower than the self-resonant frequency. Comparing the characteristics of the structures in Fig. 3(a) and (b), when the switch is on, the mutual inductance effect slightly reduces of the structure in Fig. 3(b), while increasing and of the structure. These slightly reduce [see Fig. 8(b)]. When the switch is off, the mutual effect makes become slightly greater [see Fig. 5(a)] than

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V V

Fig. 7. Plots of: (a) L , (b) R , (c) C for switched resonators, and plots of: (e) L switched resonators at 0.9 and 1.8 GHz.

, and (d) R , and (f) C

versus V versus V for

the sum of and , but negligibly affects and . is approximately the sum of and , respectively. The structures in Fig. 3(a) and (b) have comparable [see Fig. 8(a)]. The effects of mutual inductance is small because is only 0.26 nH. This indicates that offsetting inductors and is not critical. Referring to the structures in Fig. 3(a) and (c), when the width of the switching transistor is larger, the on-resistance is smaller. However, because the parasitic capacitances are bigger, the current and loss through the substrate becomes larger. Therefore, [18] is lowered when the transistor width is too large [see Fig. 8(a) and (b)]. On the other hand, if the width is too small, then the on resistance can be too high and this also lowers . This means there is an optimal size for the switching transistor to maximize similar to the insertion-loss dependence on transistor width in MOS T/R switches [19]. Fig. 8(c) and (d) shows the maximum quality factor ( ) [18] over the measurement frequency range and quality factor ( ) versus the gate-to-source voltage plot of the switch at 900 and 1800 MHz. Among the structures, the switched resonator with a 1-mm-wide transistor has the highest at the intended operating frequencies of 0.9 and 1.8 GHz. When the switch is on and off, the ’s are 6.5 and 6.9, respectively, and the ’s are 5.2 and 6.9, respectively for the structure with offset and 2-mm width (see Fig. 3(a) and Table I). The ’s are 6.5 and 7.4 and the ’s are 5.7 and 7.3 for the structure with offset and 1-mm width when the switch is on

0

versus frequency: (a) when V = 0:9 V and (b) when versus V and (d) a plot of Q versus at 0.9 and 1.8 GHz when the switch is on and off.

Fig. 8.

Plots of Q

= 3:6 V. (c) A plot of Q

beyond 1.8 V has an almost negligible and off. Increasing effect on . When the switch is on, for the structure with offset and 1-mm width is reduced by 34% compared to of by itself. When the switch is on, compared to and , and are increased by 0.5 nH and 0.9 , respectively, due to the nonnegligible on resistance [see Fig. 5(a) and (b)]. This increase of and the increase of [see Fig. 7(d)] reduce . The transitions of and in Fig. 7(a) and (b) are sharp primarily due to the low on resistance ( ) of . Since the switch transistor is wide, its contribution to is significant. When the mutual inductance is large, the slope of transition of will be more gradual. This combination of inductance and capacitance changes results in a large frequency tuning range, and can provide a better tradeoff between power consumption and phase noise in VCOs. The measured results for the switched resonator in Fig. 3(a) are summarized in Table I. Lastly, the extracted parameters are frequency dependent due to the simple model that was used to represent the switched resonators. Clearly, more research is needed to develop a better model. V. DESIGN OF THE DUAL-BAND VCO To evaluate the usefulness of switched resonators, a dualband VCO shown in Fig. 1 was fabricated. In the dual-band VCO, on top of the conventional pMOS VCO core composed of and , and buffers composed of and [20], there are transistors and and inductors and . By controlling the gate voltage ( ) of and , the inductance of the tanks can be controlled. and are 4.7 nH and and are 6.1 nH. is set to be 2 of . When and are off, the inductance of tanks is 7.9 nH and is 2.9 pF, and the VCO operates in the 0.9-GHz band [see Fig. 7(e) and (f)]. When and are on, the inductance is 3.2 nH and is 1.5 pF, which is around half of that for the 0.9-GHz operation, and the VCO operates in the

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TABLE II VCO CHARACTERISTICS AT V

79

= 1:8 V

Fig. 9. Measured tuning ranges of a dual-band VCO and that for a single-band VCO.

1.8-GHz band. The simultaneous reduction of and increases the resonant frequency. Fine tuning of the VCO is accomplished using p -n well varactor diodes. This lowers VCO gains in each band, which should lower phase noise [9] and provide added immunity from the phase-locked loop (PLL) instability and noise pick-up problems. VI. EXPERIMENTAL RESULTS OF THE DUAL-BAND VCO In Fig. 9, the tuning range for the 0.8-GHz band is between 0.753–0.867 GHz over the range between 0.5–3.6 V, which corresponds to a 13% tuning range. However, the phase noise is flat and low only for frequencies between 0.823–0.867 GHz, which corresponds to a 5% tuning range. The tuning range for the 1.8-GHz band is 1.381–1.814 GHz over the range between 0.4–3.6 V, which corresponds to a 24% tuning range. However, once again, phase noise is flat and low only for frequencies between 1.640–1.814 GHz, which corresponds to a 9% tuning range. These reductions in the usable tuning range are due to the forward-biasing of p-n varactors, and this problem can be alleviated by using a MOS varactor [21]–[23]. In fact, a switched resonator has been used in conjunction with MOS varactors to realize VCOs with a wide tuning range while achieving comparable phase-noise performance [9], [10]. Fig. 9 also shows the simulated tuning ranges, which are in reasonable agreement with the measurements. The measured phase noise for the low band is 125 dBc Hz at a 600-kHz offset from a 0.865-GHz carrier and 123 dBc Hz at a 600-kHz offset from a 1.812-GHz carrier for the high band. In addition, a 1.8-GHz VCO without a switched resonator has been fabricated for performance comparison. The measured results are summarized in Table II. The phase noise of this single-band VCO is 123 dBc Hz at a 600-kHz offset from a 1.894-GHz carrier, which is almost the same as the phase noise of the dual-band VCO at the high band. The power consumption of both the single and dual-band VCOs with a 1.8-V supply is 16 mW. The similar phase noise and power consumption for the dual- and single-band VCOs near 1.8 GHz are surprising, given the lower of the switched resonator of the dual-band VCO. A plausible explanation for this is that the parallel resistance of the resonator is not solely determined by the equivalent parallel resistance of inductor . Instead, it could be determined or significantly affected by the output resistance of the amplifiers

Fig. 10. Measured quality factors of a switched resonator and the phase noise at 600-kHz offset from carriers around 0.9 and 1.8 GHz versus V in a dual-band VCO when V = 0:6 V and I = 8:8 mA and when V = 0:9 V and 3:3 mA.

in the VCO core. Especially for deep submicrometer transistors with channel lengths of 0.18 m and below, the effects of output resistances will not be negligible. During the portions of an oscillation cycle when the core amplifier is on, the output resistances vary from 1000 to 250 compared to 300parallel resistance of the tank (excluding the transistor output resistance). The phase noise at a 600-kHz offset from around a 900-MHz and 1.8-GHz carrier and versus the gate-to-source voltage ( ) of the switching transistor are measured and shown in Fig. 10. The maximum output swing and minimum phase noise in the VCO occur when the measured dc voltage at the source of the tail transistor ( of ) is 0.6 V or of 8.8 mA. Phase noise is high around the threshold voltage due to the low [see Fig. 9(d)]. In fact, the oscillation is lost near the threshold voltage once the phase noise becomes higher than 112 dBc Hz at the 600-kHz offset. The figure-of-merit (FOM) [24] in Table III is the widely used FOM for the VCO, which is defined as mW (8) is the measured phase noise at offset frequency from the carrier frequency . is the VCO power consumption in milliwatts. The FOMs of VCOs presented in this paper

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PERFORMANCE

OF

TABLE III VCO’S USING EITHER A VARIABLE INDUCTOR OR A SWITCHED RESONATOR

The model parameters of switched resonators have stronger frequency dependence than those for inductors. Compared to the resonators that can be constructed using on-chip inductors, of switched resonators is 30% lower. The dependences of model parameters for switched resonators on the parameters of their subcomponents are explained. The effects of mutual inductance between the switched inductors have been investigated and shown to be insignificant. There are optimal sizes for the transistors in switched resonators to maximize when the transistors are on. By comparing a dual-band VCO using switched resonators operating near 0.9 and 1.8 GHz, and a single-band 1.8-GHz VCO, it has been shown that the dual-band VCO with switched resonators can have the same phase noise and power consumption while occupying a smaller area than that for two VCOs needed to cover the two bands. ACKNOWLEDGMENT The authors are grateful to Dr. J. Zheng, P. N. Sherman, B. Krieger, and P. Kempf, all with Jazz Semiconductor, Newport Beach, CA, for their help. Fig. 11. Photomicrographs of a dual- and single-band VCO.

range between 176 and 182 dBc Hz. These are not the best, but are competitive. This indicates that the VCOs are reasonable test vehicles for studying the impact of switch resonators on the VCO performance. The chip micrograph for the dual-band VCO is shown in Fig. 11. and are offset. The area increase due to and is small. The die sizes of the dual- and the single-band VCO are 1.3 0.7 mm and 0.86 0.68 mm including the output buffers, respectively. The dual-band VCO excluding the output buffers and pads is 0.598 mm and is increased by 41 compared to that of the single-band 1.8-GHz VCO, which is 0.351 mm . This increase is due to the areas of , , , and in Fig. 11. Compared to two single-band VCO core areas, this dual-band VCO should occupy 37% smaller area. VII. CONCLUSIONS The dependences of characteristics for switched resonators, which provide greater flexibility to trade off phase noise, tuning range, and power consumption of VCOs on frequency and the gate-to-source voltage of switch transistors has been presented.

REFERENCES [1] A. Molnar, R. Magoon, G. Hatcher, J. Zachan, W. Rhee, M. Damgaard, W. Domino, and N. Vakilian, “A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCO’s and fractional-N synthesizer,” in Int. Solid-State Circuits Conf. Tech. Dig., 2002, pp. 232–233. [2] J. Ryynanen, K. Kivekas, J. Jussila, A. Parssinen, and K. Halonen, “A dual-band RF front-end for WCDMA and GSM applications,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1198–1204, Aug. 2001. [3] T. K. K. Tsang and M. N. El-Gamal, “Dual-band sub-1 V CMOS LNA for 802.11A/B WLAN applications,” in IEEE Int. Circuits Systems Symp., May 2003, pp. I-217–I-220. [4] Z. B. Li, R. Quintal, and K. K. O, “A dual-band CMOS front-end with two gain modes for wireless LAN applications,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2069–2073, Nov. 2004. [5] C. Aden, “Variable inductors implemented in a 0.8-m CMOS process,” M.S. thesis, Univ. Florida, Gainesville, FL, 1998. [6] F. Herzel, H. Erzgraber, and N. Ilkov, “A new approach to fully integrated CMOS LC -oscillator with a very large tuning range,” in Proc. Custom Integrated Circuits Conf., Orlando, FL, May 2000, pp. 573–576. [7] P. Park, C.-S. Kim, M.-Y. Park, S.-D. Kim, and H.-K. Yu, “Variable inductance multilayer inductor with MOSFET switch control,” IEEE Electron Device Lett., vol. 25, no. 3, pp. 144–146, Mar. 2004. [8] S.-M. Yim and K. K. O, “Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC -tuned VCO,” in Proc. Custom Integrated Circuits Conf., San Diego, CA, May 2001, pp. 205–208. [9] Z. Li and K. K. O, “A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range,” IEEE Microw. Wireless Compon. Lett., vol. 13, no. 4, pp. 137–139, Apr. 2003.

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[10] M. Tiebout, “A CMOS fully integrated 1 GHz and 2 GHz dual band VCO with a voltage controlled inductor,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2002, pp. 799–802. [11] Z. Li and K. K. O, “A 1-V low phase noise multi-band CMOS voltage controlled oscillator with switching inductors and capacitors,” in RFIC Symp., Fort Worth, TX, Jun. 2004, pp. 467–470. [12] J.-M. Mourant, J. Imbornonr, and T. Tewksbury, “A low phase noise monolithic VCO in SiGe BiCMOS,” in IEEE Radio Frequency Integrated Circuits Symp., Boston, MA, Jun. 2000, pp. 65–68. [13] E. J. Baghdady, R. N. Lincoln, and B. D. Nelin, “Short-term frequency stability: Characterization, theory, and measurement,” Proc. IEEE, vol. 53, no. 7, pp. 704–722, Jul. 1965. [14] L. S. Cutler and C. L. Searle, “Some aspects of the theory and measurement of frequency fluctuations in frequency standards,” Proc. IEEE, vol. 54, no. 2, pp. 136–154, Feb. 1966. [15] D. B. Leeson, “A simple model of feedback oscillator noises spectrum,” Proc. IEEE, vol. 54, no. 2, pp. 329–330, Feb. 1966. [16] S.-M. Yim, T. Chen, and K. K. O, “The effects of a ground shield on the characteristics and performance of spiral inductors,” IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 237–244, Feb. 2002. [17] C.-M. Hung and K. K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 521–525, Apr. 2002. [18] K. K. O, “Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies,” IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1249–1252, Aug. 1998. [19] F.-J. Huang and K. K. O, “A 0.5-m CMOS T/R switch for 900-MHz wireless applications,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 486–492, Mar. 2001. [20] C. M. Hung, B. Floyd, and K. K. O, “A fully integrated 5.35-GHz CMOS VCO and a prescaler,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 17–22, Jan. 2001. [21] J. N. Burghartz, M. Soyuer, and K. A. Jenkins, “Microwave inductors and capacitors in standard multilevel interconnect silicon technology,” IEEE Trans. Microw. Theory Tech., vol. 44, no. 1, pp. 100–104, Jan. 1996. [22] C.-M. Hung, Y.-C. Ho, I.-C. Wu, and K. K. O, “High-Q capacitors implemented in a CMOS process for low-power wireless applications,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 505–511, May 1998. [23] T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. H. Lee, and S. S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” in VLSI Circuits Symp. Tech. Dig., Jun. 1998, pp. 32–33. [24] P. Kinget, “Integrated GHz voltage controlled oscillators,” in Analog Circuit Design: (X)DSL and Other Communication Systems; RF MOST Models; Integrated Filters and Oscillators, W. Sansen, J. Huijsing, and R. van de Plassche, Eds. Boston, MA: Kluwer, 1999, pp. 353–381.

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Seong-Mo Yim was born in Shinan, Korea, in 1967. He received the B.S. degree in electrical engineering and M.S. degree in micro-machining from Korea University, Seoul, Korea, in 1989 and 1998, respectively, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Florida, Gainesville, in 2003. From 1989 to 1996, he was a Micro-controller Design Engineer with Samsung Electronics, Ki-Heung, Korea. In 2000, he was with Conexant Systems (now Jazz Semiconductor), Newport Beach, CA, where he was a Summer Intern involved in the area of semiconductor BiCMOS process development. Since 2004, he has been with RF Micro Devices, Greensboro, NC. Dr. Yim was the recipient of the 1997 Prize of the Semiconductor Design Contest held by LG Semiconductor. He was also the recipient of a 2001 and 2002 Texas Instruments Incorporated Fellowship.

Kenneth K. O received the S.B., S.M., and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology (MIT), Cambridge, in 1984, 1984, and 1989, respectively. From 1989 to 1994, he was with Analog Devices Inc., where he developed submicrometer CMOS processes for mixed-signal applications and high-speed bipolar and BiCMOS processes for RF and mixed-signal applications. He is currently a Professor with the Department of Electrical and Computer Engineering, University of Florida, Gainesville. He has authored or coauthored approximately 130 journal and conference publications. He holds four patents. His research group (Silicon Microwave Integrated Circuits and Systems Research Group) develops circuits and components required to implement analog and digital systems operating from 1 GHz to 1 THz using silicon integrated-circuit (IC) technologies. Dr. O was the general chair of the 2001 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM). He was an associate editor for the IEEE TRANSACTIONS ON ELECTRON DEVICES from 1999 to 2001. He also served as the publication chairman of the 1999 International Electron Device Meeting. He was the recipient of the 1995, 1997, and 2000 IBM Faculty Development Awards and the 1996 National Science Foundation (NSF) Early CAREER Development Award.

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An Improved Model for Ground-Shielded CMOS Test Fixtures Tero Kaija and Eero O. Ristolainen

Abstract—An improved model for ground-shielded (GS) test fixtures is proposed. The proposed model provides more accurate device-under-test gap behavioral model than previous test-fixture models and takes into account the impedance of the ground return path. The new model is validated up to 25 GHz by comparing the model simulations with experimental measurements. The proposed model is applied to bulk-silicon- and sapphire-based GS test fixtures with different layouts. Furthermore, a large phase shift in the shield-based test-fixture forward transmission is reported in this study. Based on the results achieved, suggestions for deembedding method selection are given. Test fixtures were fabricated using a 0.35- m CMOS process and 0.5- m silicon-on-sapphire CMOS process. Index Terms—Microwave measurements, modeling, RF CMOS, semiconductor device measurements, silicon-on-insulator (SOI) technology.

I. INTRODUCTION

T

HE DEVICE simulation models for RF integrated-circuit design are frequently based on scattering parameters measured directly on a semiconductor wafer. A test fixture is needed around the device-under-test (DUT) in order to connect the probe tips of the probe station to the terminals of the DUT on the semiconductor wafer. The test fixture itself causes severe parasitics to the measurement environment. These parasitics have to be deembedded in order to obtain pure DUT data. Consistent deembedding requires that the employed test fixtures have clear and evident parasitics [1]. Ground-shielded (GS) test fixtures were introduced for microwave on-wafer measurements in [1] and later expanded upon in [2] and [3]. A simple lumped-element model for GS test fixtures is developed and validated up to 12 GHz in [1] and [3]. This lumped-element model was applied to a GS test-fixture scaling method in [4]. Since the operating frequencies of the RF CMOS integrated devices show an increasing trend, valid simulation models for passive and active components beyond 12 GHz are required. In this study, we investigate GS test-fixture parasitics and the current GS test-fixture model validity above 12 GHz. It is important to know the measurement environment and to determine if significant parasitics appear after 12 GHz or if major changes appear in the test-fixture parasitics. Several different

Manuscript received May 18, 2005; revised July 16, 2005. This work was supported by the Nokia Foundation and by the Finnish Foundation for Advancement of Technology. T. Kaija is with the Institute of Electronics, Tampere University of Technology, FIN-33720 Tampere, Finland (e-mail: [email protected]). E. O. Ristolainen, deceased, was with the Institute of Electronics, Tampere University of Technology, FIN-33720 Tampere, Finland. Digital Object Identifier 10.1109/TMTT.2005.860895

Fig. 1. (a) GS test fixture with ground bars filled with vias (dots in upper bar) on bulk-silicon substrate. (b) GS test fixture with solid ground pads connected to ground-shield on insulating sapphire. The slots in the ground shields are not shown (to be discussed later).

deembedding methods are available [5]–[9] and knowledge of the test-fixture parasitics helps in choosing the most suitable deembedding method. This paper is organized as follows. Section II describes the test fixtures studied. Section III discusses the limitations of the current GS test-fixture model above 12 GHz. Furthermore, an improved model for GS test fixtures is proposed. A comparison is made between the current test-fixture model and the proposed test-fixture model. The model simulations are validated using experimental measurements. The proposed improved model is applied to silicon-on-sapphire (SOS)-based GS test-fixture modeling in Section IV. A discussion of the results is given in Section V. Finally, conclusions are drawn in Section VI. II. FABRICATED GS TEST FIXTURES The layout of a GS test fixture may vary, depending on the employed process technology. The number of metal layers may be different or the size and the structure of the probing pad may have design rule constraints. However, one common factor is that the lowest metal layer is used below the pads to shield the fixture from substrate. GS test fixtures were studied with two different substrate materials: low resistive bulk silicon and insulating sapphire. Furthermore, the layouts of the studied test fixtures are not identical. This assists in achieving generalized results, i.e., if the proposed model is suitable for different kinds of test fixtures based on shielding. The top and cross-sectional views of the fabricated test fixture on top of bulk-silicon and sapphire substrate are shown in Fig. 1(a) and (b), respectively.

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TABLE I GS- AND IGS-MODEL PARAMETERS FOR BULK-SILICON- AND SAPPHIRE SUBSTRATE-BASED GS TEST FIXTURES

Fig. 2.

Conventional GS test-fixture model [3].

The employed bulk-silicon CMOS process has four metal layers, while the SOS process has three metal layers. Furthermore, the ground pad sizes are 70 m 70 m and 103.6 m 103.6 m for bulk and SOS test fixtures, respectively. The size of the signal pads of the bulk-silicon test fixture is 60 m 60 m, while in the SOS-based fixture, the signal pad size is identical with the size of the ground pads of the fixture due to process design rule constraints. The signal pad stacks contain three and two metal layers, as shown in Fig. 1(a) and (b), respectively. The greatest difference between the fixtures in Fig. 1(a) and (b) is that the bulk CMOS fixture has ground bars between the ground pads. These bars contain all four metal layers and they are completely connected to the ground-shield plane by employing via arrays between every metal layer. The SOS-based test fixture does not have these bars. Only the large ground pads are connected to the ground-shield plane using wide via arrays between every metal layer inside the ground pad. The SOS-based test fixture also has a wider signal lead than the bulk-silicon test fixture. Moreover, the outer dimensions of the test fixtures are not similar; the fixture in Fig. 1(a) is 50 m shorter than that in Fig. 1(b). In addition, the thicknesses of the metal layers are different due to different process technologies. In summary, the two introduced shield-based test fixtures studied have typical process- and design-induced layout differences, but they are categorized as GS test fixtures. III. IMPROVED TEST-FIXTURE MODEL A brief experimental introduction on how the validity of the current GS test-fixture model starts to decline above 9 GHz is presented here. The limitations of the current model are pointed out and the proposed improved model is described. A. Present GS Test-Fixture Model The current GS test-fixture model is shown in Fig. 2 [3]. It includes resistances and inductances to take into account the series parasitics of the signal lead. Parallel parasitics are modeled as capacitors . Moreover, is added between signal lead tips (inside the dashed box) to represent the coupling capacitance. The parallel capacitance and signal lead resistance can be calculated from the process parameters or extract from measured data. The includes the contact resistance of probing in addition to signal lead resistance. Contact resistance can be measured by employing a simple short in-fixture [6]. The signal lead inductance is extracted from measured thru in-fixture data. The coupling capacitance is extracted from measured open in-fixture data. In order to test the current model capabilities, the bulk-silicon test fixture shown in Fig. 1(a) was measured on a frequency range from 45 MHz to 25 GHz and the lumped elements of the

Fig. 3. Simulated GS-model bulk-silicon test fixture.

Y

-parameter versus measured data from GS

GS model were fitted to the measured data on a frequency range from 45 MHz to 12 GHz. The fitted GS-model lumped-element values are listed in Table I, which also contains the lumped-element values for the SOS-based test-fixture model and the values of the additional lumped-element components of the proposed improved test-fixture model. However, these values will be discussed later. To verify if the GS model is valid above 12 GHz, it was simulated over the whole frequency range from 45 MHz to 25 GHz and simulation data was compared to measured test-fixture data, as shown in Figs. 3 and 4. The GS model gives a good match in test fixture , as shown in Fig. 3, but fails to match with measured , as shown in Fig. 4. The imaginary part of changes direction at 12 GHz and cannot be modeled with a plain capacitor. The capacitive susceptance starts to decrease and it transforms into inductive susceptance at 18 GHz. Moreover, this means that the phase encounters a large phase shift. It is emphasized that the fabricated test fixture is not the same size and it does not have identical layout with the fixtures proposed in [1]–[3]. Still, 12 GHz is a “turning point” for the imaginary part of . Moreover, the measured real part starts to branch off from zero after 9 GHz, which the GS model does not take into account. Thus, the real part of becomes frequency dependent, as shown in Fig. 4. The GS model was found valid up to 12 GHz in [1] and [3]. Based on our measurements, the model validity starts to decline after 9 GHz. Therefore, an improved ground-shielded (IGS) model is required.

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Fig. 4. Simulated GS-model bulk-silicon test fixture.

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Y

-parameter versus measured data from GS

Fig. 5. Proposed IGS model.

B. Proposed Improved Test-Fixture Model The DUT gap of the GS test fixture recalls a gap discontinuity in a microstrip structure. A frequency-independent lumped-element model for microstrip gap discontinuity up to 25 GHz has been proposed in [10]. Since there is a slot in the ground plane (place for the DUT), the structure is not identical with the discontinuity presented in [10]. However, the series circuit between the reference planes in the microstrip gap discontinuity model is adopted and applied to the proposed IGS model. The IGS model is shown in Fig. 5. An inductor and resistor have been added inside the dashed square to form the aforementioned circuit. The resistor takes into account the radiation and surface wave losses [10]. The lumped element forms the positive susceptance by increasing the phase shift. In addition, the microstrip gap discontinuity model has an circuit in parallel with the strip and ground plane [10]. This was not included in the IGS model since the measured data shown in Fig. 3 emphasizes that the capacitance between signal lead and ground plane dominates, i.e., the imaginary part of is positive, increasing linearly with frequency. Furthermore, a simple test-fixture model was preferred. However, adding the and elements is itself not enough to model the test-fixture behavior above 12 GHz. It is easy to conclude that the magnitude of will start to decrease since the impedance of the lumped element increases as the frequency grows. However, it can be seen from data shown in Fig. 4 that measured forward coupling shows an increasing trend. Thus, an additional lumped element required to model this behavior is justified and described below.

Fig. 6.

Measured ground-lead impedance.

A small ( 0.2 pH) ground-lead inductance is reported for GS test fixtures in [1]. The effect of this inductor was assumed negligible and it was not included in the GS model [1]. We extracted the ground-lead impedance from a measured short in-fixture by employing a four-step deembedding method [6]. The resulting ground-lead impedance real and imaginary parts are shown in Fig. 6. The real part of the ground-lead impedance is approximately 0 over the measured frequency range. It has small variation along the 0-axis, but it does not show any trend to change from the average 0- value. The imaginary part has a clear increasing trend, which indicates a small inductor in the ground lead. The inductance value can be calculated from the imaginary part, resulting in an average of 1.5 pH. Thus, our measurements show significantly larger inductance values for ground lead compared to the previously published 0.2 pH. Therefore, in our IGS model. we have included an inductor The authors believe that the ground return path impedance is due to certain test-fixture layout factors. The process design rules generally require chopping holes in the ground shield (wide metal areas stress release rule) in order to ensure successful processing. This means that large solid metal planes are not allowed. The test fixtures shown in Fig. 1(a) and (b) have slots in their ground planes. These slots are oriented in parallel with the signal lead, as shown in detail in Fig. 7. The shield below the signal lead and pad is solid. The impedance of the ground return path is increased since the ground return current is forced to flow around these slots in order to reach the ground pads. The ground return current path is coarsely indicated with dashed arrows in Fig. 7. Furthermore, the roughness of the ground-shield surface increases the ground return current path distance. Therefore, we propose that the ground-lead impedance would be modeled with an inductor. Moreover, it cannot be maintained as a general rule that the ground-lead inductance is always below 0.2 pH (or negligible) since the layout of the GS test fixture affects the ground-lead impedance. On the basis of these arguments, the use of a small inductor to model the impedance of the ground return path is justified.

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Fig. 7. Detailed view of the slotted test-fixture ground plane. Minimum slot size accepted by the employed process technology is used.

Fig. 9. Y real and imaginary parts. Measured data (solid lines) are compared with IGS-model simulation data.

Fig. 8. Y real and imaginary parts. Measured data (solid lines) are compared with simulated IGS model (triangles).

The proposed IGS model is now introduced. After that, the performance of the proposed model will be validated. The IGS model was imported to the ADS simulator of Agilent Technologies, Palo Alto, CA, and an optimization routine was used to find the values for and in order to fit the IGS-model simulations to measured data. The value of was fixed at the measured average value of 1.5 pH. All other parameters were kept the same as in the GS model. The resulting values for and were 8 k and 55 nH, respectively. The lumped element has a quite large value. However, it does not represent a physical component; instead, it models the behavior of the gap. It increases the phase shift. The inductor gives nonlinear phase behavior, as described in [10]. Finally, the IGS model employing the “bulk-silicon fixture” values from Table I was simulated and compared with measurements. The results of the comparison are shown in Figs. 8 and 9. The IGS model gives a satisfactory match with measured and . The measured data in Figs. 8 and 9 is the same as in Figs. 3 and 4. It is seen that IGS model succeeds in modeling the GS over the whole measured frequency range.

Fig. 10. Measured bulk CMOS GS test fixture simulated data included for comparison.

S

. IGS- and GS-model

To emphasize the great phase shift in the GS test-fixture forward coupling, the measured is shown in a polar plot in Fig. 10. The simulated data from the IGS and GS models is also included. Again, the IGS model shows good agreement with the measurements. The simulated GS-model data starts to branch off after 9 GHz from measured data. However, a more important observation is that the GS-model simulated data does not provide a phase shift similar to that provided by the measured data. In Fig. 10, the “branch-off” frequency point 9 GHz and the frequency range end value 25 GHz are marked with solid and dashed arrows for IGS- and GS-model simulated data, respectively.

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was a similar agreement between the simulations and measurements as that already shown in Fig. 8. To sum up, the proposed IGS model was found valid for GS test fixtures in the frequency range 45 MHz to 25 GHz. V. DISCUSSION

Fig. 11. (left) Polar plot in frequency range 45 MHz to 25 GHz. Measured test fixture S on bulk silicon (solid line). Simulated GS- and IGS-model S data is marked with circles and triangles, respectively. (right) Measured test fixture S on SOS substrate (solid line). Simulated results from GS and IGS models are marked with circles and triangles, respectively. Measured S data of unshielded test fixture on SOS substrate is illustrated with dashed line.

IV. IGS MODEL APPLIED TO SOS-BASED TEST FIXTURE The applicability of the proposed IGS model for modeling different shield-based test fixtures was studied next. The IGS model was used to model the SOS-based test fixture shown in Fig. 1(b). A similar modeling sequence was carried out as previously described for bulk-silicon test fixture. The resulting values for lumped elements are collected in Table I. The differences between bulk-silicon- and SOS-based test fixture are due to different layouts and process parameters. For example, the SOS-based shielded test fixture has a wider signal lead and a larger signal pad, resulting in a greater value than for the bulk-silicon test fixture. The signal lead is made of thicker metal, which increases the value compared to the bulk-silicon test fixture. The wide signal lead decreases the series inductance value in the SOS-based fixture. A different process and increased DUT gap size affects the values of and . An interesting thing is that the ground-lead inductance is increased compared to the bulk-silicon test fixture. The SOS-based test fixture has a slotted ground plane. The number of slots and the slot placement differ from those in the bulk-silicon test fixture, but the orientation of the slots is the same. Furthermore, the SOS-based test-fixture layout does not contain ground bars, as indicated in Fig. 1(b). Therefore, it is assumed that the differences on the ground-plane layout and the lack of ground bars cause the small increment in ground-lead impedance. It is emphasized that the SOS-based test fixture is also wider than the bulk-silicon test fixture. A similar comparison with IGS-model simulated data and measured SOS-based test-fixture data was carried out as was done for the bulk-silicon test fixture in Fig. 10. The results are shown in Fig. 11. The phase shift in the SOS-based GS test fixture is larger than in the bulk-silicon GS test fixture. On the left-hand side of Fig. 11, there is an enlarged detailed view of the center of the polar plot. The IGS-model simulated data gives a satisfactory match with measured data. The GS model simulations start to branch off from measured data in a way similar to that previously described. The GS-model matching declines rapidly above 12-GHz frequency. Furthermore, the match between simulated IGS-model and SOS-based test-fixture measured data was checked. This figure is not included since there

The phase shift in is large in both bulk-silicon- and SOS-based GS test fixtures, as shown in Figs. 10 and 11. To demonstrate that this is not a result of unsuccessful measurements, an example of measured for a completely unshielded test fixture (no ground shield) is shown in Fig. 11 (dashed line). The measured phase shift is significantly smaller than in GS fixtures. To verify the above result, all these test fixtures were measured in two different laboratories with two different probe stations and vector network analyzers. Furthermore, the probe stations were calibrated employing short-open-load-thru (SOLT) and load-reflect-reflect-match (LRRM) calibration methods. After the calibration, the probe tips were lifted in the air and the separation between probe tips was adjusted to match the separation when probing a test fixture. A weak capacitive coupling was found. The phase of the started at 90 and was nearly constant (slightly decreasing) over the whole measured frequency range, as expected in theory. After all these verification procedures. the measurement results were still consistent in all cases; the bulk-silicon- and SOS-based GS fixtures had a large phase shift, while a small phase shift was measured for unshielded fixtures. The authors believe that this is the first time a significant difference in phase shift has been reported between a GS and unshielded test fixture. The aforementioned test-fixture layout factors were assumed to cause the impedance in the ground lead. It remains for the future to study the effect of slot orientation, shape, and placement in order to minimize ground return path impedance. The modeled test fixtures are open in-fixtures in this study. Open in-fixture is a test fixture without an actual device embedded into the DUT gap. Therefore, the possible influence of the embedded device on the coupling parameters , , and of the IGS model is left for further study. However, if one is unsure about how the presence of the actual device affects the fixture coupling characteristics (in our case, the parameters , , and ), it is possible to place a dummy device into the DUT gap of the open in-fixture, as was proposed in [1]. This dummy device is identical with the actual DUT (e.g., an RF nMOS transistor), but it is left unconnected in the case of the open in-fixture. However, the difference between the plain open in-fixture and open in-fixture with an embedded dummy device should be verified experimentally. At the time of writing this paper, such open in-fixtures were not yet available for a comparison. VI. CONCLUSIONS An improved model for GS test fixtures has been proposed and the model has been validated up to 25 GHz. Based on the results presented in this study, it is suggested that a deembedding method having the capability to take into account the groundlead parasitics should be used with GS test fixtures. This means that the selected deembedding method has to be able to remove the ground-lead parasitics.

KAIJA AND RISTOLAINEN: IMPROVED MODEL FOR GS CMOS TEST FIXTURES

ACKNOWLEDGMENT The authors would like to thank J. Saijets and H. Hakojärvi, both with VTT Information Technology, Espoo, Finland, for carrying out the on-wafer measurements. REFERENCES [1] T. E. Kolding, “On-wafer measuring techniques for characterizing RF CMOS devices,” Ph.D. dissertation, Aalborg Univ., Aalborg, Denmark, Aug. 1999. [2] T. E. Kolding, O. K. Jensen, and T. Larsen, “Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices,” in Proc. IEEE Int. Microelectron. Test Structures Conf., 2000, pp. 106–111. [3] T. E. Kolding, “Shield-based microwave on-wafer device measurements,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 6, pp. 1039–1044, Jun. 2001. [4] T. Kaija and E. O. Ristolainen, “An experimental study of scalability in shield-based on-wafer CMOS test fixtures,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 3, pp. 945–953, Mar. 2004. [5] M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, “An improved de-embedding technique for on-wafer high-frequency characterization,” in Proc. IEEE Bipolar Circuits and Technology Meeting, 1991, pp. 188–191. [6] T. E. Kolding, “A four-step method for de-embedding gigahertz on-wafer CMOS measurements,” IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 734–740, Apr. 2000. [7] A. Cho and D. E. Burk, “A three-step method for the deembedding of high frequency S -parameter measurements,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1371–1375, Jun. 1991. [8] E. P. Vandamme, M. M.-P. Schreurs, and C. Van Dinther, “Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test structures,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 737–742, Apr. 2001. [9] T. E. Kolding, “On-wafer calibration techniques for gigahertz CMOS measurements,” in Proc. IEEE Int. Microelectronic Test Structures Conf., 1999, pp. 105–110.

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[10] N. G. Alexopoulos and S.-C. Wu, “Frequency-independent equivalent circuit model for microstrip open-end and gap discontinuities,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 7, pp. 1268–1272, Jul. 1994.

Tero Kaija was born in Turku, Finland, in 1977. He received the M.Sc. degree in electrical engineering from Tampere University of Technology (TUT), Tampere, Finland, in 2002, and is currently working toward the Ph.D. degree at the Institute of Electronics, TUT. He is also a graduate student with The Graduate School in Electronics, Telecommunications and Automation (GETA), Helsinki, Finland. His research interests include high-frequency on-wafer measurements on bulk-silicon and silicon-on-insulator (SOI) wafers and RF CMOS device modeling.

Eero O. Ristolainen passed away January 3, 2005. He received the M.Sc. and Dr.Tech. at Helsinki University of Technology, Helsinki Finland, in 1972 and 1989, respectively. During the 1980s and 1990s, he was a Visiting Professor with the Michigan Technological University, Houghton, and the Department of Material Science and Surface Engineering, University of Florida, Gainesville. He authored or coauthored over 100 papers. From 1997 to January 2005, he was with the Department of Electronics, Tampere University of Technology, Tampere, Finland, where he was a Professor of microelectronics. His research interests have included integrated-circuit design, ultrahigh-speed electronic circuits [SiGe/Si heterostructures and heterojunction bipolar transistors (HBTs)] and SOI devices, RF integrated-circuit design, integrated analog and mixed circuits, new electronic materials, modeling (finite-element methods and nanoscale simulations), and the microelectronics three-dimensional (3-D) system-in-package (SiP).

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A Low-Power Oscillator Mixer in 0.18-m CMOS Technology To-Po Wang, Student Member, IEEE, Chia-Chi Chang, Ren-Chieh Liu, Ming-Da Tsai, Student Member, IEEE, Kuo-Jung Sun, Ying-Tang Chang, Liang-Hung Lu, Member, IEEE, and Huei Wang, Fellow, IEEE

Abstract—A downconversion double-balanced oscillator mixer using 0.18- m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers. Index Terms—Oscillator mixer, self-oscillating mixer (SOM), voltage-controlled oscillator (VCO).

I. INTRODUCTION

T

HE DEMAND for high bit-rate wireless systems is driven by the growing popularity of consumer products. Lowvoltage, low-power, and highly integrated circuits (ICs) are always the trends for IC design, especially crucial in mobile wireless communication systems due to the limitation of battery capacity. Circuits combining oscillator and mixer using GaAs, BiCMOS, and CMOS processes were designed for the purpose of a high degree of integration [1]–[5] and reducing power dissipation [1], [4], [5]. Therefore, an oscillator-mixer design is attractive for highly integrated ICs with low power consumption.

Manuscript received May 18, 2005; revised October 19, 2005. This work was supported in part by Sunplus and by the National Science Council under Contract NSC 93-2752-E-002-002-PAE, Contract NSC 93-2219-E-002-024, and Contract NSC 93-2213-E-002-033. T.-P. Wang, M.-D. Tsai, K.-J. Sun, L.-H. Lu, and H. Wang are with the Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. (e-mail: [email protected]). C.-C. Chang was with the Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. He is now with VIA Technologies Inc., Taipei, Taiwan 23141, R.O.C. R.-C. Liu was with the Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. He is now with the Realtek Semiconductor Corporation, Hsinchu, Taiwan 30075, R.O.C. Y.-T. Chang is with the Sunplus Technology Company Ltd., Hsinchu, Taiwan 300, R.O.C. Digital Object Identifier 10.1109/TMTT.2005.861671

A 0.9–2.2-GHz quadrature mixer oscillator (QMO), fully integrating quadrature current-controlled oscillator (QCCO), converter with a band-switch circuit quadrature mixer, and GHz) was realized for using the BiCMOS process ( low-cost purposes [3]. The quadrature mixer was stacked above a current-controlled oscillator, and this circuit topology has demonstrated good isolation between RF inputs and the local oscillator (LO). However, it needs a 3-V supply voltage because the mixers are directly connected on top of the oscillators, and the phase noise of the QCCO is limited because of the lack of a resonator. For power dissipation consideration in a phase-locked loop (PLL), a circuit using a 0.6- m BiCMOS process merged the oscillator and mixer into one stage and exhibited low power consumption [4]. However, the level shift, inductive peaking, and speed-up current sources were needed to be included in the voltage-controlled oscillator (VCO)/mixer combined stage. The circuit needs a 3-V supply voltage due to at least three stacked active devices and the substantial phase noise is limited in the free-running VCO. Another quadrature self-oscillating mixer (SOM) in a 0.6- m CMOS technology claimed its SOM resulted in reduced area, as well as reduced power dissipation since the mixer and oscillator functions share the same current [5]. The LO output component of each of the four mixer stages connects to the LO input port of the subsequent stage in order to form a self-oscillating ring mixer with quadrature outputs. However, this structure operates at a supply voltage of 3.3 V since two nMOS and two resistors are directly stacked. The noise figure is also limited due to the switching transistor not completely turned on and off. This paper demonstrates a low-power LC-tank double-balanced oscillator mixer. This oscillator mixer stacks the discrete mixer on the VCO to fulfill the total current consumption reduction by using the current reuse topology. In this topology, the mixer current flows into VCO cross-coupled pair directly. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer operates at low supply voltage of 1.0 V. This paper is organized as follows. In Section II, the circuit topology is presented and the design methods are also analyzed in detail. Section III gives experiment results and characterization. Section IV compares the published SOMs, mixer oscillators (MOs), and mixers with this study and also presents the conclusions of this paper.

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Fig. 2. Functional representation of the proposed oscillator mixer.

Fig. 1. Schematics of: (a) the regular downconversion double-balanced mixer and (b) the regular differential VCO.

II. CIRCUIT DESIGN AND ANALYSIS A. Principle of Circuit Operation Fig. 1 shows the schematics of a regular down-conversion double-balanced mixer and regular differential VCO. For simplicity in analyzing the minimum supply voltages of the regular mixer, the regular VCO, and this oscillator mixer, the body effect is neglected, all the transistors are assumed identical, and all devices are in the saturation region. The transconductances of the nMOS transistors ( and ) are used to convert input RF voltage signals to currents. The nMOS devices ( – ) are the time-variant section to mix the RF signals with the LO signals to generate the IF signals. There are three levels of active devices ( , , and ) and a resistor ( ) stack directly, and the minimum supply voltage ( ) for the mixer is

(1) is the curFor a regular VCO shown in Fig. 1(b), device rent source, and devices ( – ) are the negativecrosscoupled pair. The oscillating frequency is determined by the LC tank. These two active devices ( and ) stack directly, and the minimum supply voltage ( ) for the VCO is (2)

Fig. 3. Circuit schematic of the down-conversion double-balanced oscillator mixer.

In order to reduce these supply voltages ( and ) and power consumptions, the regular mixer and regular VCO are merged. Fig. 2 shows the functional representation for the merged topology. In Fig. 2, the VCO core generates the differential voltage signals for the switching function to turn on and off the mixer section ( , , , and ) by changing their source voltages. The mixer section plays the role to convert the input RF voltage signal to output current, and is switched on and off by the differential-LO signals to produce differential-IF signals. The schematic of this down-conversion double-balanced oscillator mixer is shown in Fig. 3 with each nMOS ( – ) of 32 fingers and total gatewidth of 80 m. The nMOS ( – ) serve as LO buffers for testing purpose and ports 1 and 1 are the input ports for differential RF signals. While nMOS ( – ) operating as transconductances ( – ), the devices ( – ) simultaneous serve as the oscillator and switch. nMOS devices ( – ) operating in the saturation region are used to increase the conversion gain. In other words,

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for – . The differential-LO signals can turn on and off the nMOS ( – ) by changing their source voltages. To achieve low supply voltage, the tail current source of the regular mixer topology introduced by Gilbert is avoided [6]. The supply voltage and are for the mixer and VCO, respectively. The minimum supply voltage ( ) for the VCO is

. Due to the differential relation where of and , shown in Fig. 2, the overall differential IF output voltage is (10)

(3)

. Neglect of the body efwhere fect and channel length modulation in all devices, the transconductance ( ) for nMOS ( - ) can be expressed as

This supply voltage is lower than that of a regular VCO (2) by if the processes are the same. The minimum supply voltage ( ) for the mixer is

(11)

(4) is the amplitude of the oscillating signal from the where cross-coupled pair ( – ). However, is equivalent to for the large oscillating signal. Therefore, (5) which is lower than that of regular mixer (1) by if the are the same. For the QMO in [3], the minimum supply voltage is . As mentioned in [4], the compact low-power topology in [4] suffers from an important limitation: a minimum supply voltage of . Considering the SOM in [5], the minimum supply voltage is . If the process and voltage drop by the resister are the same for [3]–[5] and this study (e.g., 0.18- m SiGe BiCMOS [7]), the minimum supply voltages for [3] and [4] approximate and 1.6 V, respectively. These voltages are higher than the highest supply voltage (1.0-V ) in this study. The supply voltage ( ) is also lower than that of [5] by . B. Oscillator-Mixer Conversion-Gain Analysis As shown in Fig. 2, the differential RF currents are associated with the transconductances ( – ) and the RF input signal ( ). Since is small, the relationship of them can be approximated as (6) (7) where and are the bias current of the transconductors ( and ). After the switching function provided by the VCO, the IF generated from and can be written as (8) where produced from

and

. For the same reason, the IF current is (9)

is the amplitude of the oscillating signal. If the sinuwhere soidal oscillating signal has a 50% duty cycle, the voltage conversion gain of the oscillator mixer can be derived as (12) Thus, it can be seen that the voltage gain can be increased by increasing the oscillating amplitude ( ) or the loading resistor ( ) or the voltage ( ) if other parameters are constant. In (12), the is approximately 320 for this oscillator mixer. cannot be too large since it will reduce the voltage headroom of the mixer. In order to achieve competitive conversion gain at low supply voltage, the supply voltage ( ) of the VCO is 630 mV biased at only a little higher than the threshold voltage ( mV), and the overdrive voltage ( ) is approximately mV . In this design, the oscillating amplitude ( ) from the cross-coupled pair ( – ) will increase the conversion gain. C. Noise Figure of the Oscillator Mixer For the regular double-balanced mixer shown in Fig. 1(a), the thermal noise of the active devices are generated from the time-variant section ( – ), transconductance section ( – ), and tail current source ( ). The single-sideband (SSB) noise figure can be modified from [8] and approximately written as (13), shown at the bottom of the following page, where the transconductance, noise factor, and gate resistance of the transconductance section ( – ) are denoted by , , and , respectively. The corresponding properties of the time-variant section ( – ) and tail current source ( ) are denoted by , , and , , and , respectively. is the signal-source resistance used for noise-figure evaluation, represents the conversion gain of the switching pair, and approaches one for large LO amplitude [8]. During the time interval near zero-crossing of the LO voltage, the MOS ( – ) of the time-variant section will conduct, and there will be a noise current path direct to the IF output port. A significant noise current will occur at the IF frequency during this time interval [8]. For the proposed double-balanced oscillator mixer shown in Fig. 2, the thermal noise introduced by the switch and oscillator section ( – ) results in a common-mode noise current

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TABLE I VOLTAGE GAIN, IIP3, AND PHASE NOISE OF THE OSCILLATOR MIXER WITH ) RESPECT TO DIFFERENT MIXER CURRENT CONSUMPTION (I

at the IF output port. The noise current will cancel because of the differential-IF output voltage. Therefore, the noise currents mainly come from the mixer section ( – ), and the SSB noise figure of this oscillator mixer can be derived as Fig. 4. Direct current (dc) path of the oscillator mixer.

(14) where , , and represent the transconductance, noise factor, and gate resistance of the mixer section shown in Fig. 2, respectively. is the signal-source resistance used for noisefigure evaluation. From (13) and (14), the noise figure of the proposed oscillator mixer is lower than that of the regular mixer if the transconductance ( ) of the oscillator mixer is the same as that ( ) of the regular mixer, and other parameters are the same. The simulated SSB noise figure of the proposed oscillator mixer is 14.2 dB, which is approximately 3.2 dB lower than that of a regular mixer with the same conversion gain. D. Linearity of the Oscillator Mixer The principle source of the distortion in active mixers is the nonlinearity of the input RF voltage to current conversion. The input third-order intercept point (IIP3) of a mixer is used to represents its linearity. Typically, the mixer section ( – ) with larger gatewidth device results in higher IIP3; however, this will come at cost of higher current consumption and higher power consumption. Therefore, the linearity is a tradeoff with the current consumption. This phenomenon can be observed from the experiment data shown in Table I. For the proposed low-power oscillator mixer, the mixer current consumption is limited to achieve a minimal power dissipation. E. VCO Topology The oscillator core of the oscillator mixer is the negativecross-coupled pair with each nMOS ( – ) of gatewidth of 80 m. The VCO supply voltage ( ) is via the inductors, the negative resistance is generated from the cross-coupled pair,

and the fundamental frequency is determined by the LC-tank ( , , , and VC). Each inductor is 0.4 nH and the simulated quality factor of the inductor is 15. In order to achieve accurate VCO frequency, the capacitors in this LC tank consists of a capacitor and a varactor. The fine-tuned frequency is determined by the bias of the varactor from the node ( ). The nMOS ( – ) are source followers placed after the VCO so as to drive the external lowimpedance load (50 ) of the instrument for testing purpose. Removing the tail current source makes it more difficult to adjust the dc current consumption through the feedback and increases the current sensitivity to the power supply. However, the tail current source in this low-voltage and low-power circuit design is omitted to achieve the low supply voltages ( and ) and to eliminate its flicker noise and thermal noise contribution to the VCO phase noise [9] and mixer noise figure. The total VCO current ( ) shown in the Fig. 4 is controlled by the supply voltage ( ), and the mixer current ( ) is related to the supply voltage ( ). In practical applications, the voltage regulators and bandgap-reference circuits for the supply voltages ( and ) can be used to alleviate the inconvenience. F. Current Reuse in Oscillator Mixer Fig. 4 shows the dc paths of the oscillator mixer. The dc currents from and are defined as and , respectively. With the applied to the drain and gate of the VCO cross-coupled pair ( – ), the dc current consumption for the VCO ( – ) is defined as . From simulation, the dc current ( ) from the highest supply voltage ( V) goes through the mixer ( – ),

(13)

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flows only into the cross-coupled pair ( – ), and finally sink into ground. The dc current ( ) does not flow into the supply voltage ( V). This is also verified by experiment. For example, the measured is 0.54 mA, is 4.12 mA, and is 4.66 mA. Therefore, the dc current ( ) can be written as (15) From simulation and experiment, increasing the mixer supply voltage ( ) with a constant supply voltage ( ), the mixer current ( ) from is increased and the current ( ) from is reduced with the same amount. Moreover, the total currents flow through the VCO devices ( ) is constant. In other words, the total current consumption ( ) of the oscillator mixer is constant and entire mixer current ( ) can be reused by the VCO cross-coupled pair ( – ). For the same bias conditions, the total current consumption ( ) of the stacked topology combing mixer and oscillator will be lower than that of the discrete counterpart. This is because the mixer current ( ) can be reused by the VCO cross-coupled pair ( – ) in the stacked topology so as to reduce the total current consumption. The dc power consumptions of the mixer and VCO shown in Fig. 4 are defined as and , respectively. For the current reuse topology, the mixer differential pairs stacked on top of the VCO cross-coupled pair ( – ) can be considered as an external loading of the LC-tank VCO. The VCO phase noise depends on the LC tank and the input impedance looking into the sources of the differential pairs ( and ) if the parasitic capacitors are ignored. In this design, the bias voltages ( ) of the differential pairs ( and ) are approximately equal to the threshold voltage, and these result in low transconductances ( , , , and ) and high impedances ( and ). From the measured results in Table I, while mixer voltage conversion gain increases by 7.3 dB (becomes 16.1 dB), the VCO core phase noise degrades slightly by 1.9 dB (becomes 111.5 dBc Hz at 1-MHz offset). Therefore, the differential pairs do not have a serious impact on the tank factor and VCO performance. III. CIRCUIT PERFORMANCE This oscillator mixer was fabricated using a standard 0.18- m bulk RF CMOS technology. Fig. 5 shows the photograph of the fabricated chip. This oscillator mixer was mounted on an FR4 test board containing one rat-race hybrid, dc blocking capacitors, and subminiature version A (SMA) connectors. The IF frequency is fixed at 55 MHz. The output powers of IF signals were measured with the spectrum analyzer by tuning the RF frequency from 4.1 to 4.6 GHz. Fig. 6 shows the measured and simulated conversion gain of this chip with respect to RF frequency with the supply voltages V and mV, and the gate bias ( ) is 1.2 V. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO excluding buffers, respectively. The output voltages of IF signals were

Fig. 5. Chip photograph of the oscillator mixer with a chip size 0.72 mm 1.34 mm.

2

Fig. 6. Measured and simulated results of the conversion gain for the oscillator mixer with RF input power of 35 dBm.

0

Fig. 7. Measured and simulated conversion gains of the oscillator mixer with ). respect to mixer current consumption (I

measured with the 1-M load oscilloscope by tuning the RF frequency from 4.1 to 4.6 GHz. The measured voltage conversion gain is 10.9 dB at 4.2-GHz RF signal. The measured results agree with the simulated data. The operating frequency range of this oscillator mixer is limited by the VCO tuning range. Fig. 7 depicts the measured and simulated conversion gains of the oscillator mixer with respect to different mixer current ( ). Fig. 8 shows the measured fundamental output power and third-order intermodulation (IM3) with respect to the RF input frequency spacing of 5 MHz, and the IIP3 is 11.8 dBm. The IM3 was measured using two HP 83650L continuous wave (CW) generators and an Agilent E4448A spectrum analyzer. The tuning range of this oscillator mixer is 11.5% and the VCO

WANG et al.: LOW-POWER OSCILLATOR MIXER IN 0.18- m CMOS TECHNOLOGY

Fig. 8. Measured results of fundamental output power and IM3 for the oscillator mixer with RF input frequency spacing of 5 MHz.

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Fig. 10.

Measured IF time-domain differential signals of the oscillator mixer.

Fig. 11.

Measured phase noise of the VCO.

Fig. 9. Measured results of the oscillating power at IF port and RF port for the oscillator mixer.

gain ( ) is 440 MHz/V. The measured VCO oscillating power at the RF and IF ports of this oscillator mixer from 4.0 to 4.6 GHz are shown in Fig. 9. The oscillating power at IF port is lower than 35 dBm. The measured leaky oscillating power at RF port is 37 dBm around 4.2 GHz. The isolation between LO and RF cannot be measured directly because the VCO is embedded in the oscillator mixer, but the simulated LO to RF isolation is 31.4 dB. However, the VCO oscillating power at the RF port can be measured correctly. Fig. 10 shows the measured IF time-domain differential signals, the frequency of the IF signal is 55 MHz. The measured SSB noise figure of the oscillator mixer is 14.5 dB. This noise figure was measured using the Agilent N8975A NFA noise-figure analyzer. Fig. 11 shows the measured phase noise of the VCO from source followers ( , ). The measured phase noise is 107.1 dBc Hz at 1-MHz offset from the carrier. However, these source followers in this oscillator mixer are just for testing purposes, and the source followers also serve as the loads of the VCO tank. If the source followers ( , ) are omitted, the simulated phase noise of the VCO core improves 6 dB, and the phase noise will be 113.1 dBc Hz at 1-MHz offset from the carrier. The performance of an VCO core can be evaluated by the figure-of-merit (FOM) including the phase noise , carrier frequency ( ), offset frequency ( ), and dc power consumption ( ) [10] mW (16)

which results in an FOM of 175 dBc Hz with the source followers and 180.9 dBc Hz without the source followers. The measured voltage conversion gain, IIP3, and VCO phase noise without source followers of the oscillator mixer with respect to different mixer current consumption ( ) are shown in Table I. The higher voltage conversion gain and higher IIP3 can be obtained by increasing the mixer current. IV. CONCLUSION This oscillator mixer achieves lower supply voltage, higher operating frequency, and better phase noise at free running among recently reported Si-based SOMs and MOs [3]–[5]. Table II compares the recently reported low-power mixers in the CMOS process with this chip. The mixer in this oscillator mixer operates at a higher frequency and achieves lower power consumption with competitive conversion gain compared to other mixers. The total power consumption (VCO and mixer) of the oscillator mixer is 3.14 mW, which is also lower than the power consumption of a low-power mixer using a 0.18- m CMOS process [11]–[13]. Note that this oscillator mixer does not need an external VCO to operate in a communication system. The supply voltage of the VCO in an oscillator mixer is only a little higher than the threshold voltage. The low supply voltage and low-power consumption is obtained by using the individual supply voltages and current reuse topology. The phase noise is improved from previous reported

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COMPARISON

OF

TABLE II RECENTLY REPORTED LOW-POWER MIXERS WITH THIS STUDY

[7] M. Racanelli and P. Kempf, “SiGe BiCMOS technology for RF circuit applications,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1259–1270, Jul. 2005. [8] M. T. Terrovitis and R. G. Meyer, “Noise in current-commutating CMOS mixers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 772–783, Jun. 1999. [9] P. Andreani and H. Sjöland, “Tail current noise suppression in RF CMOS VCOs,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 342–348, Mar. 2002. [10] N. Fong, J. Plouchart, N. Zamdmer, D. Liu, L. Wagner, C. Plett, and N. Tarr, “Design of wide-band CMOS VCO for multiband wireless LAN applications,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1333–1342, Aug. 2003. [11] C. G. Tan, “A high-performance low-power CMOS double-balanced IQ down-conversion mixer for 2.45-GHz ISM band application,” in IEEE RFIC Symp., 2003, pp. 457–460. [12] V. Vidojkovic, J. V. D. Tang, A. Leeuwenburgh, and A. V. Roermund, “A high gain, low voltage folded-switching mixer with current-reuse in 0.18-m CMOS,” in IEEE RFIC Symp., 2004, pp. 31–34. [13] V. Vidojkovic, J. V. D. Tang, A. Leeuwenburgh, and A. H. M. V. Roermund, “A low-voltage folded-switching mixer in 0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1259–1264, Jun. 2005. [14] C. Hermann, M. Tiebout, and H. Klar, “A 0.6 V 1.6-mW transformerbased 2.5-GHz downconversion mixer with 5.4-dB gain and 2.8-dBm IIP3 in 0.13-m CMOS,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 488–495, Feb. 2005.

0

SOMs and MOs by using the LC tank in this chip. As a result, the oscillator mixer combines the individual mixer and VCO to achieve low supply voltage, low current consumption, and low power consumption with competitive conversion gain. The supply voltage and power consumption of this proposed topology can be further reduced by using more advanced CMOS technology.

To-Po Wang (S’05) was born in Hsinchu, Taiwan, R.O.C., in 1975. He received two B.S. degrees (one in mechanical engineering and the other in electrical engineering) from National Sun Yat-Sen University, Taiwan, R.O.C., in 1998, the M.S. degree in communication engineering from National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 2000, and is currently working toward the Ph.D. degree at the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. From 2000 to 2003, he was with the BENQ Corporation, Taipei, Taiwan, R.O.C., where he was engaged in mobile phone research. His research interests are in the areas of RF and millimeter-wave ICs in CMOS, SiGe BiCMOS, and compound semiconductor technologies.

ACKNOWLEDGMENT The authors would also like to thank J.-H. Tsai, H.-Y. Chang, M.-F. Lei, and C.-S. Lin, all of National Taiwan University, Taipei, Taiwan, R.O.C., for useful discussions.

REFERENCES [1] M. J. Roberts, S. Iezekiel, and C. M. Snowden, “A W -band self-oscillating subharmonic MMIC mixer,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2104–2018, Dec. 1998. [2] N. Bourhill, S. Iezekiel, and D. P. Steenson, “A millimeter-wave fiber-radio downlink based on optically controlled MMIC self-oscillating mixers,” in Proc. 33rd Eur. Microwave Conf., 2003, pp. 607–610. [3] J. V. D. Tang and D. Kasperkovitz, “A 0.9–2.2-GHz monolithic quadrature mixer oscillator for direct-conversion satellite receiver,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 1997, pp. 88–89. [4] B. Razavi, “A 2-GHz 1.6-mW phase-locked loop,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 730–735, May 1997. [5] M. B. Bendak, B. A. Xavier, and P. M. Chau, “A 1.2-GHz CMOS quadrature self-oscillating mixer,” in IEEE Int. Circuits Systems Symp., Jun. 1999, pp. 434–437. [6] G. Fraello and G. Palmisano, “Low voltage folded-mirror mixer,” Electron. Lett., vol. 33, no. 21, pp. 1780–1781, Oct. 1997.

Chia-Chi Chang received the B.S. and M.S. degrees in electronic engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2002 and 2004, respectively. In 2005, he joined VIA Technologies Inc., Taipei, Taiwan, R.O.C., as an RF Integrated Circuit Designer. His research interests include the design of high-speed frequency synthesizers and broad-band CMOS circuits for wireless communication.

Ren-Chieh Liu was born in ChangHua, Taiwan, R.O.C., on September 2, 1975. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, R.O.C., in 1997, 2000 and 2004, respectively. Upon graduation, he joined the Realtek Semiconductor Corporation, Hsinchu, Taiwan, R.O.C., where he has been involved with CMOS RF ICs, microwave monolithic ICs, and communication system circuit designs.

WANG et al.: LOW-POWER OSCILLATOR MIXER IN 0.18- m CMOS TECHNOLOGY

Ming-Da Tsai (S’03) was born in Miaoli, Taiwan, R.O.C., on August 31, 1979. He received the B.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2001, and the M.S. and Ph.D. degrees from the Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2003 and 2005, respectively. His research interests are in the areas of RF and millimeter-wave ICs in CMOS, SiGe BiCMOS, and compound semiconductor technologies.

Kuo-Jung Sun was born in Tainan, Taiwan, R.O.C. He received the B.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, R.O.C., in 1991, and the M.S. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2005. His research interests include the design of RF ICs (RFICs)/monolithic microwave integrated circuits (MMICs), CMOS sensors, and data converters.

Ying-Tang Chang was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. degree in communication engineering from National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1999, and the M.S. degree in the communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. Since October 2001, he has been with the Sunplus Technology Company Ltd., Hsinchu, Taiwan, R.O.C., where he is currently an Advanced Engineer engaged in CMOS/BiCMOS RFIC design.

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Liang-Hung Lu (M’02) was born in Taipei, Taiwan, R.O.C., in 1968. He received the B.S. and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1991 and 1993, respectively, and the Ph.D. degree in electrical engineering from The University of Michigan at Ann Arbor, in 2001. During his graduate study, he was involved in SiGe HBT technology and monolithic microwave integrated circuit (MMIC) applications. In 2001, he joined the Semiconductor Research and Development Center (SRDC), IBM, Hopewell Junction, NY, where he was engaged in low-power and RF project for silicon-on-insulator (SOI) technology. In the August 2002, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., as an Assistant Professor. His research interests include CMOS/BiCMOS RF and mixed-signal integrated-circuit designs.

Huei Wang (S’83–M’87–SM’95–F’06) was born in Tainan, Taiwan, R.O.C., on March 9, 1958. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, MI, in 1984 and 1987, respectively. During his graduate study, he was engaged in research on theoretical and numerical analysis of electromagnetic radiation and scattering problems. He was also involved in the development of microwave remote detecting/sensing systems. In 1987, he joined the Electronic Systems and Technology Division, TRW Inc. He has been a Member of Technical Staff (MTS) and Staff Engineer responsible for MMIC modeling of computer-aided design (CAD) tools, and MMIC testing evaluation and design, and became the Senior Section Manager of the Millimeter-Wave Sensor Product Section, RF Product Center. In 1993, he visited the Institute of Electronics, National Chiao-Tung University, Hsinchu City, Taiwan, R.O.C., where he taught MMIC-related topics. In 1994, he returned to TRW Inc. In February 1998, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., where he is currently a Professor. Dr. Wang is a member of Phi Kappa Phi and Tau Beta Pi. He was the recipient of the Distinguished Research Award presented by the National Science Council, R.O.C. (2003–2006). He was also elected as the first Richard M. Hong Endowed Chair Professor of National Taiwan University in 2005.

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A Digitally Controlled Constant Envelope Phase-Shift Modulator for Low-Power Broad-Band Wireless Applications Xiuge Yang, Student Member, IEEE, and Jenshan Lin, Senior Member, IEEE

Abstract—A low-power constant envelope phase-shift modulator is presented. The circuit switches the phase of a constant amplitude carrier at output according to the input digital data. Design issues and their impact on the performance of the modulator are discussed. A test chip was fabricated in a 0.18- m CMOS process. Experiment results verified the design principle of the modulator. The modulator consumes 2 mA and is suitable for low-power wireless applications like sensor network and personal area network. Since the circuit is implemented mostly by digital circuit, has broad-band frequency response, and supports high data rate, the modulator can be used at various wireless bands. The measured operating range of carrier frequency is 1.75 to 3.5 GHz, and the modulation data rate can go up to 500 Mb/s. In addition, the modulator can be modified to generate different modulations by digitally controlling both the phase and amplitude of the output signal from a phasor-combining circuit. Therefore, the modulator can potentially be used for software configurable radios. Index Terms—Constant envelope, low power, phase modulation, software configurable radio, wireless.

I. INTRODUCTION

M

ANY wireless mobile products use nonlinear saturated power amplifiers (PAs) because they have higher efficiency than linear amplifiers. A nonlinear amplifier changes the signal amplitude by different amounts depending on the instantaneous amplitude of the signal. The more the amplitude of a signal varies, the more nonlinear amplification occurs, which will result in a distorted signal. Therefore, modulated signals with constant envelope are often preferred in wireless communications. In constant envelope modulations, only phase information is employed to carry the user data, with the carrier amplitude being constant. Two examples of constant envelope modulations are minimum shift keying (MSK) and Gaussian minimum shift keying (GMSK) [1]. Compared to MSK, GMSK has the advantage of a more compact power spectrum with lower sidelobes due to baseband filtering [2], but MSK [3] does not generate inter-symbol interference (ISI) because the shaping sinusoidal pulse is confined in a bit duration. In either type of modulation, data information is contained only in the carrier’s phase. Thus, both modulations can be viewed as phase modulation. MSK, as well as GMSK, has a conventional quadrature scheme

Manuscript received June 8, 2005; revised September 14, 2005. The authors are with the Radio Frequency System on Chip Group, Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2005.861669

Fig. 1. MSK modulation example and the modulated signal’s constellation. (a) MSK modulation is I –Q modulation with half sinusoidal pulse shaping. (b) The modulated signal presents a constant envelope constellation.

origin, but this paper will present a different approach to implement it other than the conventional approach. If seen from the constellation of a phase modulation signal, the signal vector or the phasor changes angle according to the transmitted bits with the magnitude of the vector maintaining the same, which results in a point moving on a constant–radius circle and changing direction from time to time. This is exemplified in Fig. 1, which shows an MSK modulation and its constellation of an 8-bit interval. The baseband channel data bits are shaped into sinusoidal pulses and, respectively, modulated onto two carriers with quadrature phases. The resulting signals of the two channels are then summed up, and the modulated signal becomes a constant envelope carrier with changing phase. It can be seen that, on the resulting constellation, the phasor moves on a circle and changes direction based on the bit pattern. It goes over a quadrant for a 1-bit interval. Different modulations will produce different phasor movements on the constellation. As long as the phase changes along the constellation circle corresponding to actual data bits can be generated in integrated circuits (ICs), MSK, GMSK, and potentially any other constant envelope modulations can be implemented. Fig. 2 [4] illustrates how, in any particular quadrant,

0018-9480/$20.00 © 2006 IEEE

YANG AND LIN: DIGITALLY CONTROLLED CONSTANT ENVELOPE PHASE-SHIFT MODULATOR

Fig. 2. Illustration of how a phasor can be generated from two phasors in quadrature.

constant envelope signals with different phases ’s can be generated from two local-oscillator (LO) carriers in quadrature. By maneuvering the values of and , which can be seen as the weights of the two quadrature LOs and , can be changed while maintains constant. It should be noted that this method can even be extended for nonconstant envelope modulations such as quadrature amplitude modulation (QAM), which utilize amplitude variations as well. In that case, both the magnitude and angle of the phasor need to be changed, although it will make nonlinear amplification difficult. However, even if only nonlinear PAs are to be used, making use of techniques such as linear amplification with nonlinear components (LINC) [5], nonconstant envelope modulations can still be realized with the combination of two sets of constant envelope modulators and nonlinear PAs. This brings broad application prospects for modulators designed based on this principle, which essentially is just changing the phase, and possibly amplitude as well, of a carrier according to the modulation. For example, a software defined radio (SDR) can use such modulators to accommodate different modulations. The modulator to be discussed in this paper is one that follows this implementation approach. It was designed for personal area networks ready for the ZigBee technology [6] or other types of low-power wireless networks. The design approach and comparisons to conventional modulators of similar functions are discussed in Section II. The modulator adopts an MSK-based scheme, but the phase change over any bit interval, which corresponds to a quadrant on the constellation, was implemented in a limited number of discrete steps, four in this particular design, in order to simplify the circuit architecture without compromising the performance of the modulator significantly. This is explained in Section III together with some other issue associated with the modulator design. Section IV describes the modulator circuit design in detail, and measurement results are presented in Section V. Section VI presents a conclusion. II. CONSTANT ENVELOPE PHASE-SHIFT MODULATOR USING THE PHASOR-COMBINING APPROACH The approach of generating an in-between phasor from two phasors in quadrature can be realized by a phasor-combining circuit, or a summing circuit, whose simplified schematic can be seen in Fig. 3. In this circuit, and are at carrier frequency and have a 90 difference in phase. and weigh and , respectively, and the sum of the two weighted LOs will be the generated phasor that falls between the two input phasors. In

Fig. 3.

Simplified schematic of a phasor-combining circuit.

Fig. 4.

Conceptual block diagram of a conventional I=Q modulator.

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other words, can be interpreted as a carrier signal whose phase is being changed. The amplitude of , or the magnitude of the generated phasor, also depends on the values of and . If the sum of and remains constant, the modulated signal will have a constant envelope. By choosing pairs of quadrature LOs of different phases according to the actual data, the correct quadrant on the constellation can be guaranteed. As we know, modulations, or quadrature modulations, play an important role in many telecommunication applications and wireless standards. The modulator designed using the phasor-combining approach is capable of generating most of the widely used modulations such as quadrature phase-shift keying (QPSK), MSK, and GMSK, but it is not exactly the same as a conventional modulator. Fig. 4 shows a conceptual block diagram [7] for conventional modulators. It can be seen that a conventional modulator takes two baseband data sequences and and varies the amplitude and phase of the two quadrature sinusoidal carrier signals in response to the instantaneous and channel voltages [8]. Many modulators designed based on the quadrature scheme have been reported such as in [9]–[11]. However, different quadrature modulation schemes require different baseband processings such as pulse shaping and filtering, which imposes challenges on the baseband circuit, especially if multiple modulation schemes are to be generated, such as for an SDR [12], [13]. The phasor-combining approach, on the contrary, does not require baseband processing. In principle, it directly changes the phase and/or amplitude of the carrier, according to the designated phasor movement on the constellation. Different modulation schemes and, hence, the different baseband processings they need, result in different phasor movements on the modulated signal’s constellation. Therefore, in a sense, the phasor-combining approach skips the baseband processing, the analog mixing or multiplication, and the summation, and tries to create the final vector signal directly. This is done by selecting the pairs of and (see Fig. 3) for correct

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Fig. 6.

Fig. 5. Comparison of PSD with respect to the number of phase shifts per bit period. Normalized frequency is used in this figure.

quadrants and by controlling the weighing currents and for correct signal phase/amplitude. The circuitry can be much simplified in this way. Another major difference between the two types of modulators lies in that the proposed modulator is “linear” in the sense that carrier phase and/or amplitude are changed linearly by the bias currents ( and ) of the phasor combining circuit, whereas conventional modulators usually make use of devices’ nonlinearity to realize “mixing” or “multiplication.” This difference brings forth an important advantage of the phasor-combining approach over the conventional modulators. Channel filtering, which is necessary for cleaning up a nonlinear modulator’s output spectrum [14]–[16], would not be necessary for the phasor-combining modulator, making it more suitable for higher level of integration. III. DESIGN ISSUES ASSOCIATED WITH THE CONSTANT ENVELOPE PHASE-SHIFT MODULATOR In this study, the discrete step phase-shift modulation is a little different than the MSK modulation in that MSKs continuous phase change over a bit period is approximated by a relatively small number of phase steps here. Meanwhile, it can be related to MSK or even offset quadrature phase-shift keying (OQPSK), depending on the number of discrete phase shifts employed in every quadrant. However, neither a perfectly constant envelope, nor a constant phase-shift step size is easy to realize in practice. Therefore, the effect this may have on the modulator’s performance needs to be investigated. A. Theoretical Power Spectral Density (PSD) With Respect to the Number of Phase Shifts Per Bit Period A good means for checking the performance of a modulator is the modulated signal’s power spectral density (PSD). Ideal MSK modulation with randomly distributed input bits would give us a normalized PSD, as shown by the solid line in Fig. 5 [17], which also shows the different PSDs generated from the phase-shift modulation by using different numbers of phase shifts within every quadrant, starting from the axis points. It can be seen that with one phase shift per quadrant, the PSD is the same as that of an OQPSK modulation, and as the

Ideal constellation of the modulator output.

number of phase-shift steps per quadrant increases, the discrete phase-shift modulation approaches MSK and the spectrum eventually becomes an MSK spectrum. As shown in Fig. 5, the highest normalized sidelobe level for the cases of one step, two steps, and four steps per quadrant are 14, 18, and 22 dBc, respectively. With four phase shifts per quadrant, the discrete phase-shift modulator has a very similar spectrum to an MSK spectrum, which has a 23 dBc highest sidelobe level. A quadrant on the constellation corresponds to a bit period. Therefore, we chose four phase-shift steps for every bit period for the design to simplify the circuit architecture. With four phase shifts per quadrant, the output of the modulator should generate a constellation like the one in Fig. 6, where the modulated signal moves sequentially on the circle in discrete steps and changes direction only on the or axis points. B. Impact of Variations in the Modulated Signal’s Amplitude and Phase-Shift Step The results in Fig. 5 were simulated by assuming an ideal modulator that produces constant amplitude and constant phaseshift step size. However, due to a summing circuit’s gate-todrain RF feedthrough of the two quadrature input signals, which exists even when one of the two summing weights is set to zero, perfect constant amplitude within each quadrant of the modulated signal’s constellation cannot be achieved by real circuits. The size of the phase-shift steps also varies across the constellation. The variation in the modulated signal’s amplitude and phase-shift step will lead to deviation of the signal point from the ideal symbol point on a constellation, which will increase the error vector magnitude (EVM) of the modulator. The EVM is the difference between the ideal vector convergence point and the transmitted point on a signal constellation. It is defined as the rms value of the error vectors in relation to the magnitude of an ideal symbol. It is obvious that the bigger the amplitude/phase-shift variations are, the worse the modulator will perform in terms of EVM. Meanwhile, we also need to investigate the impact on the output spectrum. In order to take into account more and different variations of the modulated signal, the effect of the variance of variations in the output signal’s amplitude, or in its phase shift among the four steps within each quadrant, was further studied, i.e., we treated the variation as a random variable with a mean of zero and an approximated variance based on the data from simulation results, and studied the relationship between the modulator’s performance, in terms of sidelobe level, and the variance of the variation (VOV). We denoted VOV as .

YANG AND LIN: DIGITALLY CONTROLLED CONSTANT ENVELOPE PHASE-SHIFT MODULATOR

Fig. 8.

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Block diagram of the constant envelope phase-shift modulator.

Fig. 7. Normalized sidelobe level (referenced to mainlobe level) versus variations in amplitude and phase shift. (The horizontal axis has the unit of radians for phase-shift variation, whereas the unit of percentage is used for amplitude variation.).

For example, based on probability theory, the VOV in phase shift can be approximated as (1) and ’s are actual values where of implemented phases. To simulate the effect, four normally distributed random values with zero mean and variance of were generated to represent the variations from the four ideal phase points in a quadrant. Fig. 5 plots the first sidelobe level normalized to mainlobe level (in decibels relative to a carrier) versus the different values of in phase shift. For the modulator design, maximum angle deviation from the ideal phasor can be looked up in Fig. 5 as the worst case scenario in terms of phase-shift variation to see how the performance will be affected. The results shown in Fig. 7 indicate that if is less than 0.1 rad (5.73 ), the increase of the sidelobe level from the ideal case is less than 1 dB. Fig. 7 also plots the effect of amplitude variation on the PSD’s sidelobe increase. The effect appears to be similar to that of phase-shift variation. Note that the horizontal axis has the unit of radians for phase-shift variation, and it indicates percentage for amplitude variation. Therefore, when in the amplitude of the modulation is less than 10%, or when in the phase-shift step is less than 0.1 rad, the modulator’s performance will not be degraded significantly. It should be pointed out, however, that the variation in the amplitude of the modulated signal is likely to disappear after the signal is amplified by a nonlinear and saturated PA. Therefore, it should not be a critical factor for the performance of the modulator when integrated in a transmitter with a nonlinear PA. IV. CIRCUIT DESCRIPTION A block diagram of the constant envelope phase-shift modulator circuit is shown in Fig. 8. The circuit is mainly composed of a 2 : 1 divider, two 4 : 1 differential multiplexers (MUXs), a phasor combining circuit (summing circuit), output buffers, and a digital circuit section to control these blocks. It should be noted

Fig. 9. (a) Block diagram of a 2 : 1 static frequency divider. (b) A detailed divider schematic.

that the digital control circuit is not included in Fig. 8 for the purpose of clarifying the modulator circuit’s main architecture. A. Divider From a differential 2 LO (twice the LO frequency) input signal, a 2 : 1 current mode logic static frequency divider, as shown in Fig. 9, generates four signals with phases that are equally separated over 360 , as indicated by the four crosses on the -axes in Fig. 6. The divider has a differential master–slave configuration [18]. The inverted slave outputs are connected to the master inputs. The cross connection between the slave and master generates an output frequency at half of the input ( and ) frequency. The differential output from the master ( and ) is in quadrature with that of the slave ( and ). Therefore, with a differential input at a frequency twice the designated LO frequency for the modulation, the divider will provide four LO signals whose phases are 90 apart from one another. Both the master and slave consist of two input transistors (M1 and M2), two latch transistors (M3 and M4), two drive transistors (M5 and M6), and two load

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Fig. 11.

Fig. 10.

Schematic of a 2 : 1 differential current-steering MUX.

transistors (M7 and M8). The self-oscillation frequency of a divider increases as the sizes of the transistors are reduced, although driver transistor size has less effect than the sizes of other transistors [19]. However, at a given drive transistor size, the smaller the latch transistors’ size is, the lower the output voltage amplitude will be [19]. In addition, increasing the transistor’s size will also increase power consumption. Due to these tradeoffs, and since the divider must be designed based on the acceptable power consumption and output signal level, the chosen transistor sizes will set a limit on the operating frequency of the divider. The operating frequency range of the divider will determine the modulator’s operating bandwidth to a great extent. B. MUXs From the four LO signals generated by the divider, two 4 : 1 differential MUXs are used to select the current state and the next state. The two states correspond to the two boundary points of a quadrant on the -plane, whereby the modulated signal phase would change by 90 during any bit interval. The selected pair of the two states holds for a bit interval before being changed by the two 4 : 1 MUXs for the next bit interval. Each 4 : 1 MUX is designed to consist of two stages of 2 : 1 differential MUXs. The two stages are controlled by two clocks, Clock1 and Clock2, respectively, as can be seen from Fig. 8. One of the two clocks, Clock1 in this design, controls the bit rate, and the other clock embeds the digital data bits. Fig. 10 shows the schematic of a 2 : 1 current-steering MUX [20] used in the design. This structure allows for a reduced voltage swing. Simulations also indicate that switching of the current can be performed at a speed higher than switching of the voltage [20]. Therefore, this type of MUX can increase the operating speed of the circuit, which allows for higher data rates, especially if the same circuitry is to be used for implementing different modulation schemes. Compared to a one-stage 4 : 1 MUX [21], the two-stage configuration, although more complex, suffers less speed penalty

Schematic of the phasor-combining circuit.

and maintains fully differential signals better [22]. Both configurations require at least two inputs, one for the clocks, and the other for data, which will decide what to select from the four LO signals. The simulation result also showed that, for this modulator design, the power consumption of using two-stage MUXs was not significantly higher than using one-stage ones. C. Phasor-Combining Circuit After passing through buffers, the current state signal and the next stage signal are fed into a phasor-combining circuit, which is shown in Fig. 11. The phasor-combining circuit sums the input signals to produce a signal with a phase shifting between those of the two inputs. Different intermediate phases can be generated by applying different bias currents ( and ) as summing weights, which can be realized by using digital logic circuits to switch the current sources. As can be seen from Fig. 9, three switches, which turn on or off the three bias current sources , , and , are controlled by digital circuit to generate four different combinations of and values within a bit interval in order to implement the four intermediate phase shifts within any particular quadrant period. The digital control signals for switches 1 and 3 are differential and, thus, neither , nor will contribute to and at the same time, while always contributes to only. The controls of the switches are designed such that the four combinations of and are as follows. , generate a 0 phase shift relative to the current state). 2) , generate a 22.5 phase shift). 3) , generate a 45 phase shift). 4) , generate a 67.5 phase shift).

1)

(to (to (to (to

and weigh the current state signal and the next state signal, respectively, and is the sum of the two weighted signals with an in-between phase. In the meantime, constant amplitude of can be maintained by keeping the sum of and constant ( ).

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Fig. 13. Schematic of a flip-flop latch. Fig. 12. Schematic of the buffer.

D. Buffers The last stage of the modulator design is an output buffer/amplifier to drive 50- single-ended loads for the purpose of testing with 50- instruments. Three buffers similar to the one in Fig. 12 are cascaded to serve as the driver. The buffers use resistor loads to achieve a broad-band response. There is also a buffer stage between the MUXs and the phasor-combining circuit. E. Digital Circuit Section As introduced earlier, the modulator circuit needs many clock signals (e.g., for the MUXs) and control signals (e.g., for controlling the switches of the phasor-combining circuit). For testing purpose, the modulator chip is designed with only one clock input, and all the clocks and controls are generated by digital circuitry on the chip. Since these signals are of relatively lower frequencies, a CMOS logic digital circuit is used for lower power consumption. The digital circuit section mainly consists of two sets of the combination of master–slave flip-flops and XOR gates with one set generating the control signals for the switches and the other generating the clocks for the MUXs. The two sets are separately configured and connected according to the desired waveforms of the clocks and controls. In both sets, the masters and slaves use the same type of flip-flop latch as shown in Fig. 13 [23]. Latches are also used to line up the correct edges of the generated clocks and controls. V. EXPERIMENT RESULT

Fig. 14. Die microphotograph of the modulator.

constellation. The purpose was twofold, i.e., to reduce the spectrum bandwidth of the output signal so that it can be measured by equipment with limited bandwidth and to simplify testing the IC without the need for a high-speed data pattern generating instrument or multiple high-frequency clock signal sources. In this design, only an RF signal input, for the divider to generate the four phased LO signals, and a single clock input, for controlling the MUXs and timing the internal digital circuits, are needed. To derive the mathematical description of a signal modulated in such a way, assume that the carrier is in the form of , where is the amplitude of the carrier, is the carrier frequency, and is the initial phase of the carrier. Without loss of generality, can be assumed to be zero. A modulated signal moving clockwise on the constellation circle continuously means that the carrier’s phase decreases continuously with time. Denote the bit rate as and, therefore, the bit interval . Since the phase change of an MSK signal within a bit interval is , the modulated signal can be expressed as

The modulator IC was designed and fabricated in the TSMC 0.18- m mixed-signal CMOS process with a supply voltage of 1.8 V. The chip occupies an area of 0.5 mm . Its microphotograph is shown in Fig. 14. A. Fixed Data Pattern and Output Spectrum In designing this particular modulator testing chip, repetitive data pattern was internally generated and translated into the MUXs, creating a modulated signal that moves clockwise in circles at a constant speed, determined by the data rate, on the

(2)

Therefore, frequency is

is still a single tone sinusoidal signal, but its lower than the original carrier frequency.

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EVM = 2 8%).

Fig. 17. Measured constellation of the modulated signal ( The signal moved sequentially and repetitively in full circles. Fig. 15.

:

Simulated output power spectrum for the fixed repetitive data pattern.

Fig. 18.

Fig. 16. Measured output power spectrum. The signal’s frequency is 25 MHz, or one fourth of the 100 MHz bit rate, lower than the 2.5-GHz carrier frequency.

Since in this design the continuous phase change is implemented in four discrete steps, the mathematical expression for the actual signal should instead be

Measured I =Q-plane diagram of the modulated signal.

new “current” and “next” states. Therefore, the data rate of the fixed pattern data still signifies the bit rate that the modulator can manage for arbitrary data patterns. As observed in the measurement, as the data rate increased (the signal vector rotated clockwise faster), the frequency shift in the output spectrum also increased. B. Constellation and

(3)

is the floor operator, which gives the largest integer where less than or equal to the operand. MATLAB simulation was performed to estimate the output spectrum of , which is shown in Fig. 15. The modulator IC was tested using an Agilent 89600 series Vector Signal Analyzer (VSA) with an external PA connected to the output of the chip. The VSA has a bandwidth of 36 MHz. From the measured spectrum of the modulator’s output signal in Fig. 16, it can be seen that it matches the theoretical estimation. The bit rate was set to 100 Mb/s in the measurement, the carrier frequency was 2.5 GHz, and the spectrum shows a single tone with the center frequency at 2.475 GHz, which is exactly 25 MHz lower than the carrier frequency. It should be pointed out that, although fixed data pattern was designed and used to simplify the measurement, at the end of every bit interval the MUXs always re-select two LOs in quadrature as the

Plane Diagram

Fig. 17 shows the measured constellation using the Agilent 89600s VSA. This test was used to verify the correctness of the phase shifts. The -plane diagram in Fig. 18 demonstrates the constant envelope feature of the modulator. The bit rate was still set to 100 Mb/s in the measurement, and the carrier frequency was 2.5 GHz. The measurement result showed an EVM of 2.8%. The IEEE 802.15.4 Standard [24], which a ZigBee-ready transceiver should be compliant to, specifies a transmitter EVM of 35% with a 2-Mchips/s chip rate. If this modulator is to be used in a ZigBee-ready CMOS transmitter, the EVM requirement should be easily met. With one of the differential outputs terminated by 50 , the test chip delivered a signal level of 2 dBm to a 50- load. The modulator was designed for low-power applications, and the measured current dissipation was 2 mA with the supply voltage being 1.8 V. It should be noted that this current dissipation did not include that of the three cascaded output buffers, which, although consumed 10-mA total current, are not necessarily an integral part of the modulator, if the modulator is integrated in a transmitter chain and only needs to drive the input impedance of the next stage circuit such as a mixer or a PA.

YANG AND LIN: DIGITALLY CONTROLLED CONSTANT ENVELOPE PHASE-SHIFT MODULATOR

Fig. 21.

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Constellation (

EVM = 6%) at bit rate greater than 500 Mb/s.

Fig. 19. Measured EVM versus carrier frequency. At 100-Mb/s bit rate, for EVMs lower than 5.5%, the modulator can operate at a carrier frequency between 1.75–3.5 GHz.

Fig. 22. When the error vector is perpendicular to the ideal phasor, the phase variation is the biggest.

Fig. 23. When the error vector is in the same direction as the ideal phasor (or in the exactly opposite direction), the amplitude variation is the biggest.

TABLE I SUMMARY OF MODULATOR PERFORMANCE Fig. 20. Measured EVM versus bit rate. At 2.5-GHz carrier frequency, for EVMs lower than 5%, the bit rate of the modulator ranges from dc to 500 Mb/s.

C. Operating Frequency and Bit Rate The frequency range of the carrier was also measured. The measurement was performed by keeping the clock frequency for bit rate fixed at 100 MHz and monitoring the signal constellation and EVM, while changing the RF input frequency, which is twice the LO carrier frequency. As can be seen from Fig. 19, within the carrier frequency range of 1.75–3.5 GHz, the modulator works fine with lower than 5.5% EVMs (The IEEE 802.11a Standard specifies a maximum EVM of 25 dB, or 5.62%, for the peak data rate of 54 Mb/s [25].) Another measurement was performed to find out the highest bit rate that the modulator circuit can handle with a 2.5-GHz carrier. The resulting EVMs at different bit rates are plotted in Fig. 20. Although a 500-Mb/s bit rate can turn in a decent EVM of 5%, measurement showed that higher bit rate would result in blurry constellation (see Fig. 21) and degraded EVM (greater than 6%) if the carrier frequency remained the same. As discussed earlier, the divider has a limit on its output signal’s frequency, which, in turn, will limit the modulator’s operating bandwidth. Considering the circuit did not use any inductor load, it can be estimated that the modulator’s actual bandwidth is larger than the measured results if the quadrature LO signals are provided externally. Since the circuit

is inherently broad-band, the modulator can easily support high data rate. EVM is a direct measure of the accuracy of a modulator. The contributors to the degradation in EVM could include variations in phase and amplitude, phase noise, poor frequency response at any stage of the system, poor return loss, and virtually any other RF system-related problems. At a certain EVM value, the maximum possible phase variation occurs in the case of Fig. 22, where the error vector is perpendicular to the ideal phasor. For , approximately equals 0.085 rad. According to Fig. 5, this variation will not affect the PSD significantly. Same analysis can be applied to the amplitude variation, where the worst case scenario is as shown in Fig. 23. Again, at a 6% EVM, the variation in amplitude has little impact on the modulator’s output PSD, especially considering that the signal will be amplified through an amplifier in saturation.

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TABLE II COMPARISON OF BANDWIDTH AND BIT RATE

D. Performance Summary and Comparison A brief performance summary for the modulator is listed in Table I. It can be seen that, in addition to the functionality and the low power consumption, the modulator also works at a big range of operating frequency and high data rates. Table II compares this study to some of the reported modulators of similar functions. VI. CONCLUSION A constant envelope phase-shift modulator has been demonstrated to work for an MSK-like modulation. It consumes very low power and has good modulation accuracy. The modulator has a broad-band response and can operate at high data rates. The modulator is most appealing and promising in that the concept behind it, which has been verified by experiment results, can be utilized to generate different modulation schemes. For example, GMSK modulation generates a signal whose phase change also follows a pattern more complicated than MSK. Thus, it is possible to implement the phase change pattern of GMSK so that the conventional baseband circuit for Gaussian filtering or pulse shaping will no longer be required. Moreover, for any arbitrary modulations, only limited numbers of steps between phase changes are necessary, as long as the output power spectrum can meet the application-specific requirements. Therefore, as mentioned earlier, the modulator has a broad application prospect. It can be used in low-power transmitters, especially those integrated with wireless sensors. It is also a good choice for a personal area network. More importantly, due to its digital control nature and potential for implementing different modulations such as GMSK or even QAM, the modulator would be well suited for a software-configurable radio. ACKNOWLEDGMENT The authors would like to thank MOSIS, Marina del Ray, CA, and TSMC, Hsinchu, Taiwan,R.O.C., for fabricating the chips and Agilent Technologies, Palo Alto, CA, for providing testing equipment. The authors also thank Prof. K. K. O and Prof. J. Brewer, both with the University of Florida, Gainesville, and Dr. F. Martin and Dr. P. Gorday, both with Motorola, Plantation, FL, for technical discussions.

REFERENCES [1] J. Proakis, Digital Communications, 4th ed. New York: McGraw-Hill, 2000. [2] K. Murota and K. Hirade, “GMSK modulation for digital mobile radio telephony,” IEEE Trans. Commun., vol. COM-29, no. 7, pp. 1044–1050, Jul. 1981. [3] S. Pasupathy, “Minimum shift keying: A spectrally efficient modulation,” IEEE Commun. Mag., vol. 17, no. 4, pp. 14–22, Jul. 1979. [4] X. Yang, C. Cao, J. Lin, K. O, and J. Brewer, “A 2.5 GHz constant envelope phase shift modulator for low-power wireless applications,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Jun. 2005, pp. 667–670. [5] D. C. Cox, “Linear amplification with nonlinear components,” IEEE Trans. Commun., vol. COM-22, no. 12, pp. 1942–1945, Dec. 1974. [6] E. H. Callaway, Jr., Wireless Sensor Networks: Architectures and Protocols. New York, NY: Auerbach, 2003. [7] R. Sorace, “Digital-to-RF conversion for a vector modulator,” IEEE Trans. Commun., vol. 48, no. 4, pp. 540–542, Apr. 2000. [8] J. Wholey, “Vector modulator IC’s for use in wireless communications,” in Proc. RF Expo West, 1993, pp. 232–240. [9] M. Borremans, M. Steyaert, and T. Yoshitomi, “A 1.5 V, wide band 3 GHz, CMOS quadrature direct up-converter for multi-mode wireless communications,” in Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 79–82. [10] T. P. Liu, E. Westerwick, N. Rohani, and R. H. Yan, “5 GHz CMOS radio transceiver front-end chipset,” in Proc. Int. Solid-State Circuits Conf. Tech. Dig, Feb. 2000, pp. 320–321. [11] B. Razavi, “A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 573–579, May 1999. [12] M. Chongcheawchamnan, K. S. Ang, D. Kpogla, S. Nam, S. Lucyszyn, and I. D. Robertson, “Low-cost millimeter-wave transmitter using software radio techniques,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2000, pp. 1949–1952. [13] S. Rajagopal, S. Rixner, and J. R. Cavallaro, “A programmable baseband processor design for software defined radios,” in Midwest Circuits Systems Symp., Aug. 2002, pp. III-413–III-416. [14] G. Vigil, D. C. Malocha, and M. A. Belkerdid, “Design of saw FIR filters for quadrature binary modulators,” in Proc. IEEE Ultrasonics Symp., Dec. 1991, pp. 123–127. [15] P.-U. Su and J.-M. H. Hsu, “A quadrature modulator with enhanced harmonic rejection filter,” in Proc. IEEE Asia–Pacific Conf., Aug. 2002, pp. 319–322. [16] J. A. Weldon, R. S. Narayanaswami, J. C. Rudell, L. Lin, M. Otsuka, S. Dedieu, L. Tee, K.-C. Tsai, C.-W. Lee, and P. R. Gray, “A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers,” IEEE J. Solid-State Circuits, vol. 36, pp. 2003–2015, Dec. 2001. [17] X. Yang, J. Lin, K. K. O, and J. Brewer, “Design and analysis of a lowpower constant envelope phase shift modulator,” in Proc. IEEE Radio Wireless Conf., Sep. 2004, pp. 363–366. [18] K. Ware, H. Lee, and C. G. Sodini, “A 200-MHz CMOS phase-locked loop with dual phase detectors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1560–1568, Dec. 1989. [19] U. Singh and M. Green, “Dynamics of high-frequency CMOS dividers,” in IEEE Int. Circuits Systems Symp., vol. 5, 2002, pp. V-421–V-424. [20] J. Savoj and B. Razavi, High-Speed CMOS Circuits for Optical Receivers. Norwell, MA: Kluwer, 2001. [21] D. Kehrer and H. Wohlmuth, “20-Gb/s 82 mW one-stage 4 : 1 multiplexer in 0.13 m CMOS,” in Eur. Solid-State Circuits Conf., 2003, pp. 385–388. [22] D. Kehrer, “High speed wireless building blocks,” presented at the IEEE Radio Frequency Integrated Circuits Symp. Workshop, 2004. [23] G. Gerosa, S. Gary, C. Dietz, P. Dac, K. Hoover, J. Sanchez, P. Ippolito, N. Tai, S. Litch, J. Eno, J. Golab, N. Vanderschaaf, and J. Kahle, “A 2.2 W, 80 MHz superscalar RISC microprocessor,” IEEE J. Solid-State Circuits, vol. 29, pp. 1440–1454, Dec. 1994. [24] Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR_WPAN’s), IEEE Standard 802.15.4, 2003. [25] High-Speed Physical Layer in the 5 GHz Band, Table 90, IEEE Standard 802.11a, 1999. [26] W. Kong, C. Ye, and H. C. Lin, “A 2.4 GHz fully CMOS integrated RF transceiver for 802.11b wireless LAN application,” in Proc. IEEE Radio Wireless Conf., Sep. 2004, pp. 475–478. [27] Y. Zhou and J. Yuan, “A 1 GHz CMOS current-folded direct digital RF quadrature modulator,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Jun. 2005, pp. 25–28.

YANG AND LIN: DIGITALLY CONTROLLED CONSTANT ENVELOPE PHASE-SHIFT MODULATOR

Xiuge Yang (S’05) was born in Beijing, China. She received the B.S. degree in electronic engineering from the Tsinghua University of China, Beijing, China, in 1999, the M.S. degree in electrical and computer engineering and M.S. degree in management from the University of Florida, Gainesville, in 2001 and 2003, respectively, and is currently working toward the Ph.D. degree in electrical and computer engineering at the University of Florida. Since 2003, she has been with the Radio Frequency System on a Chip (RFSOC) Research Group, Department of Electrical and Computer Engineering, University of Florid. Her research interests include RF and mixed-signal integrated-circuit design in CMOS technology, wireless communications, digital modulations, and software-defined radio.

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Jenshan Lin (S’91–M’94–SM’00) received the B.S. degree from National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1987, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Los Angeles (UCLA), in 1991 and 1994, respectively. In 1994, he joined AT&T Bell Laboratories (later Lucent Bell Laboratories), Murray Hill, NJ, as a Member of Technical Staff, and in 2000, became the Technical Manager of RF and High Speed Circuit Design Research. Since joining Bell Laboratories, he has been involved with ICs using different technologies for different applications, He led the Base Station Radio Frequency Integrated Circuit (RFIC) Team, Bell Laboratories, to demonstrate the first low-cost high-performance silicon CMOS RFIC solution for wireless base stations, which was press released at the International Solid-State Circuits Conference (ISSCC 2001). In September 2001, he joined Agere Systems, a spin-off from Lucent Bell Laboratories, and was involved with high-speed CMOS circuit design for 10-G/40-G broad-band communications. In July 2003, he joined the University of Florida, Gainesville, as an Associate Professor. He has authored or coauthored over 90 technical publications in referred journals and conferences proceedings. He holds five patents. His current research interests include RF system-on-chip integration, high-speed broad-band circuits, high-efficiency transmitters, wireless sensors, biomedical applications of microwave and millimeter-wave technologies, and software-configurable radios. Dr. Lin has been active in the IEEE Microwave Theory and Techniques Society (MTT-S). He is an elected Administrative Committee (AdCom) member serving the term of 2006–2008, and a member of the Wireless Technology Technical Committee. He also serves on several conference Steering Committees and Technical Program Committees including the IEEE MTT-S International Microwave Symposium (IMS), the Radio Frequency Integrated Circuits Symposium (RFIC), the Radio and Wireless Symposium (RWS), and the Wireless and Microwave Technology Conference (WAMICON). He is currently the Technical Program co-chair of the 2006 RFIC Symposium and Workshop co-chair of the 2006 RWS. He was the recipient of the 1994 UCLA Outstanding Ph.D. Award and the 1997 ETA Kappa Nu Outstanding Young Electrical Engineer Honorable Mention Award. He was a co-author/advisor of several IMS Best Student Paper Awards (Dawson—Second Place 1997, Droitcour—Honorable Mention 2001, Droitcour—First Place 2003) and advisor of an IEEE MTT-S Undergraduate/Pre-Graduate Scholarship Award (2004).

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H

A New Set of (curl)-Conforming Hierarchical Basis Functions for Tetrahedral Meshes Pär Ingelström

Abstract—A new set of (curl)-conforming hierarchical basis functions for tetrahedral meshes is presented. Contrary to previous bases, this one is designed such that higher order basis functions vanish when they are projected onto a lower order finite-element space using the interpolation operator defined by Nédélec. Consequently, to increase the polynomial order and improve the accuracy of the interpolated field, only additional degrees of freedom (DOFs) of higher order are added, whereas the original DOFs (the coefficients for the basis functions) remain unchanged. This makes this basis very well suited for use with efficient multilevel solvers and goal-oriented hierarchical error estimators, which is demonstrated through numerical examples. Index Terms—Edge elements, error estimation, hierarchical bases, Nédélec interpolation, Schwarz methods.

I. INTRODUCTION

H

IGHER order curl -conforming finite elements (FEs) have become more and more popular during recent years. This is due to the demand for more accurate and efficient solvers for electromagnetic-field problems. For problems with smooth solutions, higher order elements give higher convergence rates (i.e., the errors decrease more rapidly as the mesh is refined and more degrees of freedom (DOFs) are added) and they are, therefore, generally more economical to use than the common first-order elements (which are often referred to as edge elements since the DOFs are associated with the edges). Further, higher order elements also cause much less numerical dispersion than the first-order edge elements. Therefore, they are also attractive for large or resonant problems where the waves propagate long distances and large phase errors would be accumulated if first-order elements were used. On the other hand, for problems with singular solutions, we find that the convergence rate is independent of the order of the basis functions if elements with uniform size and polynomial order are used. Therefore, it is particularly important to use adaptive mesh refinement for schemes with higher order elements. As one of the applications of the presented basis functions, we consider -adaptivity guided by goal-oriented error estimates. This can be used to localize the effect of singularities and improve the convergence rate significantly. -adaptivity [1], [2] is an even more flexible approach, where both and may vary from element to element. Even though -adaptivity is not considered in this paper, we stress that the presented basis functions are well suited for use in -adaptive schemes as well. Manuscript received September 14, 2004; revised July 1, 2005. The author is with the School of Electrical Engineering, Chalmers University of Technology, SE-412 96 Göteborg, Sweden (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2005.860295

curl -conforming spaces Numerous bases for higher order have been presented in the literature during recent years. These can be divided into interpolatory bases (e.g., [3]) and hierarchical bases (e.g., [4]). The main advantage of interpolatory bases is that they may lead to better conditioned matrices and that the values of the basis functions are more easily interpreted (typically the field strength in a point associated with the basis function). However, hierarchical bases are more popular for several reasons. They can, for example, be used for the following: • schemes with -adaptivity [5] and -adaptivity [1], [2]; • hierarchical error estimation [6]; • efficient multilevel/Schwarz solvers [7], [8] where the two latter applications will be demonstrated in this paper. FE spaces can also be classified by the shape of the elements, e.g., bases for tetrahedral meshes and bases for hexahedral meshes. If we limit ourselves to tetrahedral meshes and hierarchical basis functions, there are still many bases to chose between, e.g., see [4] and [9]–[12] and the references therein. We may ask: “What are the differences between the different bases, and what characterizes a ‘good’ basis?” Firstly, we note that different bases span slightly different spaces. As pointed out in [4], the space spanned by some of the earlier sets of basis functions could actually change by just reordering the nodes of the mesh. However, as pointed out in [13], many of the more recent sets of basis functions (e.g., [4], [11], and [21]) also span slightly different spaces than those defined by Nédélec in [14]. Therefore, different bases may lead to slightly different solutions. However, the most important difference probably concerns how well the bases are suited for use with iterative solvers, and in [10], it was shown that the number of conjugate gradient (CG) iterations required to achieve a certain accuracy varied considerably depending on the choice of basis functions. The ultimate choice of basis functions would be orthogonal with respect to the bilinear form in the weak formulation of the problem we want to solve. However, such basis functions are not possible to design (unless a global eigenvalue problem is solved). Instead, we have to settle for basis functions that are “nearly orthogonal” or orthogonal in some other sense. One strategy for creating nearly orthogonal basis functions was presented in [4]. There the idea was to make the basis functions orthogonal with respect to the inner product , where is the regular tetrahedron. A similar strategy was also used in [11], but there the curl of the basis functions was also considered. Common for both of these strategies is that the orthogonality properties only hold for regular tetrahedra.

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INGELSTRÖM: NEW SET OF

(curl)-CONFORMING HIERARCHICAL BASIS FUNCTIONS

In this paper, we propose a different criterion for the construction of the basis functions. Instead of making the basis functions orthogonal with respect to some inner product, we design higher order basis functions such that they vanish when they are projected onto a lower order FE space by the interpolation operators defined by Nédélec [14], [15]. An advantage of this strategy is that no assumption of the shapes of the elements is required, and it also implies some orthogonality in the standard inner products. In Section II, the FE spaces, the DOFs and the interpolation operator defined by Nédélec in [14] are reviewed. In Section III, explicit expressions for basis functions up to complete order 4 are given and some of their properties are discussed. In Section IV, it is demonstrated how the basis functions can be used to compute accurate goal-oriented error estimates in an efficient way and how they can be used to construct efficient multilevel preconditioners. Some concluding remarks and suggestions for future research are given in Section V and, finally, there is an Appendix that concerns the construction of basis functions of any order. II. FE SPACES Nédélec has presented two families of curl -conforming FE spaces [14], [15] that are the foundation for much of the research on FEs in electromagnetics. Common for the two families are that the DOFs are associated with the edges, triangular faces, and interior of the tetrahedra and that they are constructed such that tangential continuity of the field across element boundaries is ensured. The normal component may, however, be discontinuous. The first family consists of incomplete-order polynomial spaces where some polynomials that do not affect the range space of the curl operator (i.e., gradients of scalar functions) are excluded such that the fields themselves and their curl are approximated to the same order. The corresponding spaces in the second family, which are of complete polynomial order, contain additional curl-free functions. While these additional functions lead to larger matrices, they do not generally improve the order of convergence. Therefore, the incomplete-order spaces are more popular. In this paper, we present basis functions that can be used to span both incomplete- and complete-order spaces, but in order to save space, we will focus the discussion on bases for the incomplete-order spaces. Before we define the FE spaces, we recall some polynomial spaces used by Nédélec as follows: polynomials of degree ; homogeneous polynomials of degree (exactly) ; ; where

is the coordinate vector. We also define the spaces

curl

(1)

An FE in the incomplete th-order space is defined by the following. • A domain, which, in this case, is a tetrahedron . • A space of polynomials defined on , in this case, . • A set of DOFs, as many as the dimension of . In this case, the DOFs are moments over the edges, triangular faces, and interior of (3) (4)

(5)

Here, , , and refer to an edge, a face, and the volume of , respectively. The “test function” is parallel to edge , lies in the plane of the face , and is defined in the entire tetrahedron. We note that the DOFs are equivalent to, but generally not the same as, the unknowns of the linear system of equations that results from an FE discretization. Much of the research in this paper is based on the interpolation operator , which is defined by requiring that the DOFs are the same for the original and the interpolated fields and

(6)

In practice, if we want to compute from a given field , we first have to find a suitable basis for the test functions ( , , ). We then first solve for the edge DOFs, then the face DOFs, and finally the interior DOFs. We stress that this can be done locally on each element. For the corresponding definitions of the complete-order FE spaces and interpolation operators , we refer to [15]. III. HIERARCHICAL BASIS FUNCTIONS The new basis functions are given in Tables I and II. They are expressed using simplex coordinates ( is the continuous function that is linear in each tetrahedron, one at node and zero at all other nodes) and they are associated with the nodes , edges , faces , and individual elements of the tetrahedral mesh. In Table I, scalar-valued basis functions, which span the spaces – , are given (the tilde sign is used to denote incremental spaces and corresponding vectors). In Table II, vector-valued rotational basis functions, which span the spaces – , are given. A basis for the scalar continuous ( -conforming) FE space of order can be constructed from the basis functions in Table I as follows: (7)

(2)

which we will use below.

107

(

Bases for the tangentially continuous vector-valued curl -conforming) FE spaces are constructed in a similar

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is not used explicitly in the construction of We note that the FE spaces. However, it is well known that include (see, e.g., [16]). Thus, it is easy to see that . The construction of the basis functions is inspired by [4], but we have added the following constraints:

TABLE I SCALAR BASIS FUNCTIONS

for all

with

for all

with on each element

(11) (12) (13)

We omit the details of the construction here, but a brief discussion is given in the Appendix. The key property of the new basis follows from (11) and (12): for all

with

(14)

whereas (13) ensure that the bases span the same spaces as those defined by Nédélec in [14]. To explain the implications of (14), we consider the Nédélec interpolation of a (known) field onto . The interpolated field can be written as a linear combination of basis functions in as follows:

TABLE II ROTATIONAL BASIS FUNCTIONS

(15) is a basis for and where plex) coefficients. Similarly, we have

are (com-

(16) is a basis for the incremental space (i.e., the additional basis functions in ) and are coefficients. Now, since (14) states that for and , we easily see that for . This means that if we want to increase the order of an interpolated field, we do not have to recompute the original coefficients since they remain unchanged. Further, if we want to compute the Nédélec interpolation of a discrete field, we simply set the higher order coefficients to zero. Regarding orthogonality in the standard inner products, we have the following important property:

where

(17) , , and if (14) will be shown in the Appendix. manner. Let us denote the incomplete-order curl -conforming FE spaces of order by . We have the following decomposition: (8) where the incremental spaces are defined by (9) (10)

. How this follows from

IV. APPLICATIONS As a model problem, we consider the computation of the scattering parameters for a waveguide cavity resonator (see Fig. 1). How the scattering parameter can be computed is well known, but we describe it here mainly to introduce some equations and notations that we need in Sections IV-A and B. First we need the solution to the following boundary value problem: in

(18)

INGELSTRÖM: NEW SET OF

(curl)-CONFORMING HIERARCHICAL BASIS FUNCTIONS

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The FE formulation is obtained from (22) by replacing curl with [we also require that satisfy the such that boundary condition (20)]. It reads: Find (24) The approximate FE solution leads to the approximate scattering parameter (25) Fig. 1. Drawing of the waveguide cavity resonator that is used as a model problem. The height (in the z -direction) is 10 mm.

in on

(19) (20) on

A. Efficient Multilevel Preconditioner (21)

is the electric field when the waveguide is excited Here, through port , is the magnetic permeability, is the electric permittivity, is the angular frequency, is the imaginary unit, the index refers to port number, is the (imaginary) propagation constant of the dominant mode at port , is the transverse field of the same dominant mode, is the computational domain, is the Kronecker delta function, is the outward normal unit vector on the boundary, is the part of the boundary with perfect electric conductivity (metal), and denotes the artificial boundary at port . We note that (19) follows from (18) if and it is, therefore, in some sense redundant. The boundary condition for the ports were derived assuming that only the dominant mode propagates at the ports and that the ports are placed sufficiently far from any discontinuities in the waveguide such that all evanescent modes can be neglected. A weak formulation is derived from (18), (20), and (21) using the standard Galerkin approach. It reads: Find curl such that curl where

and

In the Sections IV-A and B, we describe how the presented hierarchical basis functions can be used to compute using an efficient multilevel preconditioner and goal-oriented error estimates for , respectively.

(22)

are defined as

The efficiency of multilevel preconditioners that are based on hierarchical basis functions has been reported in many papers (see, e.g., [7] and [8]). However, these papers do not treat schemes with third-order or higher order elements. The method presented here is similar to that in [8], but we show that, with the proposed basis functions, it also performs well with thirdand fourth-order elements. We expect this method to also perform well with other bases, e.g., those in [4] and [11], but we have not made any comparison. To describe the preconditioner, we introduce some notations. Let be the matrix corresponding to with test functions in and basis functions in . Similarly, let be the vector corresponding to with test functions in and be the vector with DOFs associated to . Equation (24) can then be written in the following matrix form: .. .

..

.

.. .

.. .

.. .

(26)

. The coefficient vector corresponds to the field vector The algorithm for the preconditioner is given in Table III. The inputs and are the (sparse) lower and upper triangular matrices from the decomposition of the first-order matrix . The “ ” call refers to one or a few iterations with the symmetric successive over-relaxation (SSOR) method. The action of the preconditioner is to approximately solve the system by solving the similar system . We stress that the preconditioning matrix is complex and symmetric. For example, if , we get (27)

and curl is the subspace of curl that satisfy the boundary condition (20). The amplitudes of the transverse modal fields can be chosen such that (23)

where is the matrix corresponding to the SSOR preconditioner for . If we ignore the treatment of the first-order system and assume that only one SSOR iteration is made on the diagonal blocks, we find that the computational cost for applying the preconditioner is roughly the same as the cost for a matrix–vector multiplication involving the total matrix . Since the SSOR preconditioner is used for the higher order matrices

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TABLE III ALGORITHM FOR THE MULTILEVEL PRECONDITIONER

Fig. 3. Number of CG iterations required for schemes of different order to 10 . reach the stopping criteria

kA e 0 b k