High-speed VLSI interconnections [2nd ed] 9780471780465, 0471780464

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High-Speed VLSI Interconnections Second Edition

Ashok K. Goel Department of Electrical Engineering Michigan Technological University

WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION

High-Speed VLSI Interconnections

High-Speed VLSI Interconnections Second Edition

Ashok K. Goel Department of Electrical Engineering Michigan Technological University

WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION

Copyright ß 2007 by John Wiley & Sons, Inc. All rights reserved Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400, fax 978-750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, 201-748-6011, fax 201-748-6008, or online at http://www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at 877-762-2974, outside the United States at 317-572-3993 or fax 317-572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Wiley Bicentennial Logo: Richard J. Pacifico Library of Congress Cataloging-in-Publication Data: Goel, Ashok K., 1953High-speed VLSI interconnections / by Ashok K. Goel. – 2nd ed. p. cm. Includes bibliographical references. ISBN 978-0-471-78046-5 (cloth) 1. Very high speed integrated circuits–Mathematical models. 2. Very high speed integrated circuits–Defects–Mathematical models. 3. Integrated circuits–Very large scale integration–Computer simulation. 4. Semiconductors– Junctions. I. Title. TK7874.7.G63 2007 621.390 5–dc22 2007001710 Printed in the United States of America 10 9 8 7 6 5 4 3 2 1

In loving memory of my father

Shri D. N. Goel

Contents PREFACE 1

xv

Preliminary Concepts and More

1

1.1 Interconnections for VLSI Applications 1.1.1 Metallic Interconnections: Multilevel, Multilayer, and Multipath Configurations 1.1.2 Optical Interconnections 1.1.3 Superconducting Interconnections

2

1.2 Copper Interconnections 1.2.1 Advantages of Copper Interconnects 1.2.2 Challenges Posed by Copper Interconnects 1.2.3 Fabrication Processes for Copper Interconnects 1.2.4 Damascene Processing of Copper Interconnects

5 6 6 7 9

2 5 5

1.3 Method of Images

10

1.4 Method of Moments

15

1.5 Even- and Odd-Mode Capacitances 1.5.1 Two Coupled Conductors 1.5.2 Three Coupled Conductors

17 17 19

1.6 Transmission Line Equations

21

1.7 Miller’s Theorem

23

1.8 Inverse Laplace Transformation

25

1.9 Resistive Interconnection as Ladder Network 1.9.1 Open-Circuit Interconnection

27 27 vii

viii

CONTENTS

1.9.2 1.9.3

2

Short-Circuited Interconnection Application of Ladder Approximation to Multipath Interconnection

29 31

1.10 Propagation Modes in Microstrip Interconnection

31

1.11 Slow-Wave Mode Propagation 1.11.1 Quasi-TEM Analysis 1.11.2 Comparison with Experimental Results

32 33 37

1.12 Propagation Delays

41

Exercises

41

References

42

Parasitic Resistances, Capacitances, and Inductances

46

2.1

Parasitic Resistances: General Considerations

47

2.2

Parasitic Capacitances: General Considerations 2.2.1 Parallel-Plate Capacitance 2.2.2 Fringing Capacitances 2.2.3 Coupling Capacitances

50 51 51 52

2.3

Parasitic Inductances: General Considerations 2.3.1 Self and Mutual Inductances 2.3.2 Partial Inductances 2.3.3 Methods for Inductance Extraction 2.3.4 Effect of Inductances on Interconnection Delays

52 53 55 55 57

2.4

Approximate Formulas for Capacitances 2.4.1 Single Line on a Ground Plane 2.4.2 Two Lines on a Ground Plane 2.4.3 Three Lines on a Ground Plane 2.4.4 Single Plate with Finite Dimensions on a Ground Plane

57 58 58 59

Green’s Function Method: Using Method of Images 2.5.1 Green’s Function Matrix for Interconnections Printed on Substrate 2.5.2 Green’s Function Matrix for Interconnections Embedded in Substrate 2.5.3 Application of Method of Moments 2.5.4 Even- and Odd-Mode Capacitances 2.5.5 Ground and Coupling Capacitances

60

2.5

59

60 67 72 73 76

CONTENTS

2.5.6 2.5.7

The Program IPCSGV Parametric Dependence of Interconnection Capacitances

ix

76 77

2.6

Green’s Function Method: Fourier Integral Approach 2.6.1 Green’s Function for Multilevel Interconnections 2.6.2 Multiconductor Interconnection Capacitances 2.6.3 Piecewise Linear Charge Distribution Function 2.6.4 Calculation of Interconnection Capacitances

84 84 87 89 90

2.7

Network Analog Method 2.7.1 Representation of Subregions by Network Analogs 2.7.2 Diagonalized System for Single-Level Interconnections 2.7.3 Diagonalized System for Multilevel Interconnections 2.7.4 Interconnection Capacitances and Inductances 2.7.5 The Program ICIMPGV 2.7.6 Parametric Dependence of Interconnection Capacitances 2.7.7 Parametric Dependence of Interconnection Inductances

91 92 93 97 97 99 99 104

Simplified Formulas for Interconnection Capacitances and Inductances on Silicon and GaAs Substrates 2.8.1 Line Capacitances and Inductances 2.8.2 Coupling Capacitances and Inductances

109 112 113

Inductance Extraction Using FastHenry 2.9.1 The Program FastHenry 2.9.2 Extraction Results Using FastHenry

114 115 116

2.8

2.9

2.10 Copper Interconnections: Resistance Modeling 2.10.1 Effect of Surface/Interface Scattering on Interconnection Resistivity 2.10.2 Effect of Diffusion Barrier on Interconnection Resistivity 2.11 Electrode Capacitances in GaAs MESFET: Application of Program IPCSGV 2.11.1 Ground and Coupling Capacitances 2.11.2 The Program EPCSGM 2.11.3 Dependence on MESFET Dimensions 2.11.4 Comparison with Internal MESFET Capacitances

119 120 121 122 122 123 127 132

Exercises

132

References

133

x

3

CONTENTS

Interconnection Delays

136

3.1 Metal–Insulator–Semiconductor Microstripline Model of an Interconnection 3.1.1 The Model 3.1.2 Simulation Results

138 138 140

3.2 Transmission Line Analysis of Single-Level Interconnections 3.2.1 The Model 3.2.2 The Program PDSIGV 3.2.3 Dependence on Interconnection Parameters

145 145 150 150

3.3 Transmission Line Analysis of Parallel Multilevel Interconnections 3.3.1 The Model 3.3.2 Numerical Simulation Results

154 154 158

3.4 Analysis of Crossing Interconnections 3.4.1 Simplified Analysis of Crossing Interconnections 3.4.2 Comprehensive Analysis of Crossing Interconnections 3.4.3 The Program SPBIGV 3.4.4 Simulation Results Using SPBIGV

168 169 174 178 178

3.5 Parallel Interconnections Modeled as Multiple Coupled Microstrips 3.5.1 The Model 3.5.2 Simulation Results

190 190 193

3.6 Modeling of Lossy Parallel and Crossing Interconnections as Coupled Lumped Distributed Systems 3.6.1 The Model 3.6.2 Simulation Results

195 195 197

3.7 Very High Frequency Losses in Microstrip Interconnection 3.7.1 The Model 3.7.2 Simulation Results 3.7.3 Interconnection Delays with High-Frequency Effects

203 203 207 213

3.8 Compact Expressions for Interconnection Delays 3.8.1 The RC Interconnection Model 3.8.2 The RLC Interconnection Model: Single Semi-Infinite Line 3.8.3 The RLC Interconnection Model: Single Finite Line

216 217 219 221

CONTENTS

3.8.4 3.8.5 3.9

4

Single RLC Interconnection: Delay Time Two and Three Coupled RLC Interconnections: Delay Times

xi

223 224

Interconnection Delays in Multilayer Integrated Circuits 3.9.1 The Simplified Model 3.9.2 Simulation Results and Discussion

226 226 228

3.10 Active Interconnections 3.10.1 Interconnection Delay Model 3.10.2 Active Interconnection Driven by Minimum-Size Inverters 3.10.3 Active Interconnection Driven by Optimum-Size Inverters 3.10.4 Active Interconnection Driven by Cascaded Inverters 3.10.5 Dependence of Propagation Time on Interconnection Driving Mechanism

230 230 231 232 234 235

Exercises

236

References

237

Crosstalk Analysis

242

4.1

Lumped-Capacitance Approximation

243

4.2

Coupled Multiconductor MIS Microstripline Model of Single-Level Interconnections

245

4.2.1 4.2.2 4.2.3

245 248 251

4.3

4.4

The Model Numerical Simulations Crosstalk Reduction

Frequency-Domain Modal Analysis of Single-Level Interconnections 4.3.1 General Technique 4.3.2 Two-Line System 4.3.3 Three-Line System 4.3.4 Four-Line System 4.3.5 Simulation Results

253 254 255 257 258 260

Transmission Line Analysis of Parallel Multilevel Interconnections 4.4.1 The Model 4.4.2 The Program DCMPVI 4.4.3 Numerical Simulations Using DCMPVI

264 264 268 268

xii

CONTENTS

4.5 Analysis of Crossing Interconnections 4.5.1 Mathematical Analysis 4.5.2 Simulation Results

280 280 284

4.6 Compact Expressions for Crosstalk Analysis 4.6.1 Distributed RC Model for Two Coupled Interconnections 4.6.2 Distributed RLC Model for Two Coupled Interconnections 4.6.3 Distributed RLC Model for Three Coupled Interconnections

293

4.7 Multiconductor Buses in GaAs High-Speed Logic Circuits 4.7.1 The Model 4.7.2 Lossless MBUS with Cyclic Boundary Conditions 4.7.3 Simulation Results

5

294 296 299 302 303 305 306

Exercises

309

References

310

Electromigration-Induced Failure Analysis

313

5.1 Electromigration in VLSI Interconnection Metallizations: Overview 5.1.1 Problems Caused by Electromigration 5.1.2 Electromigration Mechanism and Factors 5.1.3 Electromigration Under Pulsed DC and AC Conditions 5.1.4 Testing and Monitoring of Electromigration 5.1.5 General Guidelines for Testing Electromigration 5.1.6 Reduction of Electromigration

314 314 315 323 323 325 327

5.2 Models of IC Reliability 5.2.1 Arrhenius Model 5.2.2 Mil-Hdbk-217D Model 5.2.3 Series Model 5.2.4 Series–Parallel Model

328 329 329 330 330

5.3 Modeling of Electromigration Due to Repetitive Pulsed Currents 5.3.1 Modeling of Physical Processes 5.3.2 First-Order Model Development 5.3.3 Modeling Results for Direct Currents 5.3.4 Modeling Results for Pulsed Currents

331 332 333 337 340

CONTENTS

6

xiii

5.4 Electromigration in Copper Interconnections 5.4.1 Electromigration under DC Conditions 5.4.2 Electromigration under Pulsed DC Condition 5.4.3 Electromigration under Bipolar AC Conditions

341 341 342 342

5.5 Failure Analysis of VLSI Interconnection Components 5.5.1 Reduction of Components into Straight Segments 5.5.2 Calculation of MTF and Lognormal Standard Deviation 5.5.3 The Program EMVIC 5.5.4 Simulation Results Using EMVIC

344 344 348 349 350

5.6 Computer-Aided Failure Analysis 5.6.1 RELIANT for Reliability of VLSI Interconnections 5.6.2 SPIDER for Checking Current Density and Voltage Drops in Interconnection Metallizations

356 357 358

Exercises

360

References

362

Future Interconnections

371

6.1 Optical Interconnections 6.1.1 Advantages of Optical Interconnections 6.1.2 Systems Issues and Challenges 6.1.3 Material Processing Issues and Challenges 6.1.4 Design Issues and Challenges

371 372 373 374 374

6.2 Transmission Line Models of Lossy Optical Waveguide Interconnections 6.2.1 Lossy Waveguide with Single Propagating Wave 6.2.2 Equivalent Circuits for Waveguide Drivers and Loads 6.2.3 Lossy Waveguide in Inhomogenous Medium

375 375 378 379

6.3 Superconducting Interconnections 6.3.1 Advantages of Superconducting Interconnections 6.3.2 Propagation Characteristics of Superconducting Interconnections 6.3.3 Comparison with Normal Metal Interconnections

386 386

6.4 Nanotechnology Circuit Interconnections: Potential Technologies 6.4.1 Silicon Nanowires and Metallic Interconnections 6.4.2 Nanotube Interconnections 6.4.3 Quantum-Cell-Based Wireless Interconnections Exercises References

390 391 392 399 400 400

386 388

xiv

CONTENTS

APPENDICES

(ftp://ftp.wiley.com/public/sci_tech_med/ high_speed_VLSI)

Appendix 2.1

The Program IPCSGV for Calculating the Parasitic Capacitances for Single-Level Interconnections on GaAs-Based Using the Green’s Function Method

Appendix 2.2

The Program ICIMPGV for Calculating the Parasitic Capacitances and Inductances for Multilevel Interconnections on GaAs-Based (ftp://ftp.wiley.com/public/ sci_tech_med/high_speed_VLSI) Using the Network Analog Method

Appendix 2.3

The Program EPCSGM for Calculating the Electrode Parasitic Capacitances in a Single-Gate GaAs MESFET

Appendix 3.1

The Program PDSIGV for Calculating the Propagation Delays in the Single-Level Interconnections on GaAs-Based (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI)

Appendix 3.2

The Program IPDMSR for Calculating the Propagation Delays in an Interconnection Driven by Minimum-Size Repeaters

Appendix 3.3

The Program IPDOSR for Calculating the Propagation Delays in an Interconnection Driven by Optimum-Size Repeaters

Appendix 3.4

The Program IPDCR for Calculating the Propagation Delays in an Interconnection Driven by Cascaded Repeaters

Appendix 4.1

The Program DCMPVI for Delay and Crosstalk Analysis of Multilevel Parallel (ftp://ftp.wiley.com/public/sci_tech_med/ high_speed_VLSI) Interconnections

Appendix 4.2

The Program SPBIGV for Signal Propagation Analysis of Bilevel Crossing Interconnections on GaAs-Based (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI)

Appendix 5.1

The Program EMVIC for Electromigration-Induced Failure Analysis of (ftp://ftp.wiley.com/public/sci_tech_med/ high_speed_VLSI) Interconnection Components

INDEX

405

Preface Continuous advances in very large scale integrated (VLSI) circuit technology have resulted in complex chips that have millions of interconnections that integrate the components on the integrated circuit (IC) chip. Customer demand for higher speeds and smaller chips has led to the use of interconnections in multilevel and multilayer configurations. At present, the interconnections play the most significant role in determining the size, power consumption, and clock frequency of a digital system. Parasitic capacitances, resistances, and inductances and their effects on the crosstalk and propagation delays associated with interconnections in high-density environments have become the major factors in the evolution of very high speed IC technology. It has been over 10 years since the first edition of this book was published. During this period, several developments have taken place in the field of VLSI interconnections such as the introduction of copper interconnections for VLSI applications, realization of the importance of including inductances in the delay and crosstalk models for very high speed circuits, further research on optical interconnections, and the possibility of realizing nanotechnology ICs using nanowires, nanotubes, and wireless interconnections. An attempt has been made to include these developments in the present second edition. This book focuses on the various issues associated with VLSI interconnections used for high-speed applications. These include parasitic capacitances and inductances, propagation delays, crosstalk, and electromigration-induced failure. It has been written as a textbook for a graduate-level course and as a reference book for practicing professionals who want to gain a better understanding of the several factors associated with high-speed interconnections. The reader is expected to have a basic understanding of electromagnetic wave propagation. The chapters in this book are designed such that they can be read independently of one another while, at the same time, being parts of one coherent unit. To maintain independence among the chapters, some material has been intentionally repeated. Several appropriate exercises are provided at the end of each chapter which are designed to be challenging as well as help the student gain further insight into the xv

xvi

PREFACE

contents of the chapter. The six chapters in this book can be described briefly as follows. In Chapter 1, a few basic techniques and some advanced concepts regarding wave propagation in an interconnection are presented. Various types of interconnections employed in VLSI applications, including multilevel, multilayer, and multipath interconnections, are discussed. Advantages of copper interconnections and their fabrication techniques are reviewed. The method of images used to find the Green’s function matrix is presented, and the method of moments, which can be used to determine the interconnection capacitances, is discussed. The even- and odd-mode capacitances for two and three coupled conductors are discussed, and the transmission line equations are derived. Miller’s theorem, which can be used to uncouple the coupled interconnections, is presented. An efficient numerical inverse Laplace transformation technique is described. A resistive interconnection has been modeled as a ladder network. The various modes that can exist in a microstrip interconnection are described, and a quasi–transverse electromagnetic (TEM) analysis of slow-wave mode propagation in the interconnections is presented. The various measures of propagation delays, including delay time and rise time, are defined. In Chapter 2, numerical techniques that can be used to determine the interconnection resistances, capacitances, and inductances on a high-density VLSI chip are discussed as well as the dependence of these parasitic elements on the various interconnection design parameters. Approximate formulas for calculating the parasitic capacitances for a few interconnection structures are presented. An algorithm to obtain the interconnection capacitances by the Green’s function method, where the Green’s function is calculated using the method of images, is presented. The Green’s function is also calculated by using the Fourier integral approach, and a numerical technique to determine the capacitances for a multilevel interconnection structure in the Si–SiO2 composite is presented. An improved network analog method to determine the parasitic capacitances and inductances associated with the high-density multilevel interconnections on the GaAs-based ICs is presented. Simplified formulas for the interconnection capacitances and inductances on the oxide-passivated silicon and semi-insulating gallium arsenide substrates are provided. A program called FastHenry, which can be used to determine the inductances associated with an interconnection structure, is described. A model for understanding the resistances for copper interconnections is presented. Source codes of a few computer programs to compute the parasitic capacitances and inductances are given in the appendices on the accompanying Ftp site. One of these programs has been extended to determine the electrode parasitic capacitances in a GaAs metal–semiconductor field effect transistor (MESFET). In Chapter 3, numerical algorithms that can be used to calculate the propagation delays in the single and multilevel parallel and crossing interconnections are presented, and the dependence of the interconnection delays on the various interconnection design parameters is discussed. An analysis of interconnection

PREFACE

xvii

delays on very high speed VLSI chips using a metal–insulator–semiconductor microstripline model is presented. A computer-efficient model based on the transmission line analysis of the high-density single-level interconnections on GaAs-based ICs is presented. The signal propagation in the single-, bi-, and trilevel high-density interconnections on GaAs-based ICs is studied, and a computerefficient model of the propagation delays in the bilevel parallel and crossing interconnections on GaAs-based ICs is presented. A SPICE model for the lossless parallel interconnections modeled as multiple coupled microstrips is presented, and this model is extended to include lossy parallel and crossing interconnections. The high-frequency effects such as conductor loss, dielectric loss, skin effect, and frequency-dependent effective dielectric constant are studied for a microstrip interconnection. Compact expressions of propagation delays for the single and coupled interconnections modeled as RC and RLC circuits are provided. The active interconnections driven by several mechanisms are analyzed and a simplified model of the interconnection delays in multilayer ICs is presented. The source codes of a few computer programs used to determine the propagation delays in the normal and active interconnections are included in the appendices. In Chapter 4, the mathematical algorithms which can be used to study the crosstalk effects in the single and multilevel parallel and crossing interconnections are discussed and the dependence of the crosstalk effects on the various interconnection design parameters is studied. Crosstalk among neighboring interconnections is calculated by using a lumped-capacitance approximation. Crosstalk in very high speed VLSI circuits is analyzed by using a coupled multiconductor metal–insulator– semiconductor microstripline model for the interconnections. Single-level interconnections are investigated by the frequency-domain modal analysis, and a transmission line model of the crosstalk effects in the single-, bi-, and trilevel highdensity interconnections on the GaAs-based ICs is presented. This is followed by an analysis of the crossing bilevel interconnections on the GaAs-based ICs. Compact expressions for studying the crosstalk effects in the interconnections modeled as RC and RLC circuits are provided. The crosstalk effects in the multiconductor buses in the high-speed GaAs logic circuits are analyzed. The source codes of a few computer programs used to analyze the crosstalk effects are included in the appendices. In Chapter 5, the degradation of the reliability of an interconnection due to electromigration is discussed. First, several factors related to electromigration in the VLSI interconnections are reviewed. The basic problems that cause electromigration are outlined, the mechanisms and dependence of electromigration on several factors are discussed, testing and monitoring techniques and guidelines are presented, and the methods of reducing electromigration in the VLSI interconnections are briefly discussed. Electromigration in copper interconnections is studied. The various models of IC reliability including the series model of failure mechanism in the VLSI interconnections are presented. A model of electromigration due to repetitive pulsed currents is developed. The series model has been used to analyze the electromigration-induced failure in the several VLSI interconnection components. The several computer programs available for studying electromigration in VLSI

xviii

PREFACE

interconnections are discussed briefly. The source code of a computer program used to study electromigration-induced failure effects in the various interconnection components is included as an appendix. In Chapter 6, a few interconnection technologies that seem promising for future ICs are discussed. The advantages, issues, and challenges associated with the optical interconnections are discussed and a lossy waveguide interconnection is modeled as a transmission line. The propagation characteristics and the comparison of superconducting interconnections with the normal metal interconnections are presented. Various technologies that seem promising for nanotechnology circuits, including nanowires, nanotubes, and quantum-cell-based wireless interconnections, are briefly discussed. The appendices for this book containing source codes can be found at: ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI. It should be noted that the various computer models presented in this book may not have been validated by experimental measurements and therefore should be used in computer-aided design programs with caution. In addition, the computer programs provided in the appendices are written for different computer systems and may need modifications to become suitable for the user’s system. Finally, in the Internet-based information age, it is necessary to give references to certain websites. Though these websites were active at the time of preparation of this manuscript, it is possible that they may become inactive in the future.

ACKNOWLEDGMENTS I would like to thank several individuals for their help and encouragement during the preparation of this book. I am grateful to Professor Kai Chang of Texas A&M University and editor of Microwave and Optical Technology Letters for inviting me to write this book. I am also thankful to Professor Martha Sloan of Michigan Technological University for her support. I also would like to thank my graduate students Yiren R. Huang, P. Joy Prabhakaran, Manish K. Mathur, Wei Xu, Matthew M. Leipnitz, and Jaikumar K. Parambil for their assistance with developing the computer programs and for obtaining the simulation results presented at several instances in this book. I am thankful to the Institute of Electrical and Electronics Engineers (United States) and the Institution of Electrical Engineers (United Kingdom) for their permission to use copyrighted material from over 30 papers published in IEEE Transactions, IEE Proceedings, and their other publications and I would like to take this opportunity to thank the authors of these papers whose work has been showcased in this book. I also owe special thanks to my wife, Sangita, for her constant love and encouragement. Finally, I express my deep appreciation to my son, Sumeet, and daughter, Rachna, for their patience and understanding during the preparation of this book.

PREFACE

xix

DISCLAIMER The information presented in this book is believed to be accurate and great care has been taken to ensure its accuracy. However, no responsibility is assumed by the author for its use and for any infringement of patents or other rights of third parties that may result from its use. Further, no license is granted by implication or otherwise under any patent, patent rights, or other rights. A. K. G. Houghton, Michigan

CHAPTER ONE

Preliminary Concepts and More In this chapter, some of the basic concepts and techniques used in this book are presented. The chapter is organized as follows:  Various types of interconnections employed in very large scale integration (VLSI) applications are discussed in Section 1.1.  Advantages and challenges posed by the copper interconnections and the techniques used for their fabrication are presented in Section 1.2.  Method of images used to find the Green’s function matrix in Chapter 2 is presented in Section 1.3.  Method of moments used to determine the various interconnection capacitances in Chapter 2 is discussed in Section 1.4.  Even- and odd-mode capacitances for two and three coupled conductors are discussed in Section 1.5.  Transmission line equations are derived and coupled transmission lines are discussed in Section 1.6.  Miller’s theorem used to uncouple the coupled interconnections in Chapter 3 is presented in Section 1.7.  A computer-efficient numerical inverse Laplace transformation technique used at several instances in this book is described in Section 1.8.  A resistive interconnection has been modeled as a ladder network in Section 1.9.  Various propagation modes that can exist in a microstrip interconnection are described in Section 1.10.  A quasi–transverse electromagnetic (TEM) analysis of slow-wave mode propagation in interconnections is presented in Section 1.11. High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

1

2

PRELIMINARY CONCEPTS AND MORE

 Definitions of propagation delays used in the literature, including delay time and rise time, are presented in Section 1.12.

1.1

INTERCONNECTIONS FOR VLSI APPLICATIONS

Continuous advances in integrated circuit (IC) technology have resulted in smaller device dimensions, larger chip sizes, and increased complexity. There is an increasing demand for circuits with higher speeds and higher component densities. In recent years, growth of GaAs on silicon (Si) substrate has met with a great deal of interest because of its potential application in new hybrid technologies [1–11]. GaAs-on-Si unites the high-speed and optoelectronic capability of GaAs circuits with the low material cost and superior mechanical properties of the Si substrate. The heat sinking of such devices is better since the thermal conductivity of Si is three times more than that of GaAs. This technology is expanding rapidly from research to device and circuit development [12–15]. So far, the various IC technologies have employed metallic interconnections, and there is a possibility of using optical interconnections in the near future. Recently, the possibility of using superconducting interconnections is also being explored. Optical and superconducting interconnections are discussed in Chapter 6. 1.1.1

Metallic Interconnections: Multilevel, Multilayer, and Multipath Configurations

The VLSI chips require millions of closely spaced interconnection lines that integrate the components on a chip. As VLSI technology advanced to meet the needs of customers, it became necessary to use multilayer interconnections in two or more levels to achieve higher packing densities, shorter transit delays, and smaller chips. In this book, the term level will be used to describe conductors which are separated by an insulator and the term layer to describe different conductors tiered together in one level of interconnection, as shown in Fig. 1.1.1. In most cases, because of its low resistivity and silicon compatibility as shown in Table 1.1.1 [16], aluminum has been used to form metal interconnections. However, as device dimensions are decreased, current density increases, resulting in decreased reliability due to electromigration and hillock formation causing electrical shorts between successive levels of Al [17–20]. Tungsten has also been used for interconnects [21–23] and, sometimes, Al/Cu is used to solve problems characteristic of pure Al [1.24] though this choice has not been without problems [25, 26]. There have been several studies [27–34] aimed at reducing electromigration. All these studies have used layers of two or more metals in the same level of the interconnection. Some of the multilayer structures studied so far have been Al/Ti/Cu [28], Al/Ta/Al [30], Al/Ni [31], Al/Cr [32], Al/Mg [33], and Al/Ti/Si [34]. Coevaporation of Al–Cu–Ti, Al–Cu–Ti, Al–Cu–Co, and Al–Co has also been shown to decrease electromigration [27]. There

INTERCONNECTIONS FOR VLSI APPLICATIONS

3

FIGURE 1.1.1 Schematic of layered interconnection structures using (a) Ti layer used to match aluminum and silicon expansion coefficients; (b) Ti or W layer on top of aluminum to constrain hillocks; (c, d) multiple layers of Ti or W alternated with aluminum.

have been many studies on the problem of hillock formation as well [16, 35–44]. One method of reducing these hillocks on silicon-based circuits has been to deposit a film of WSi [36] or MoSi between Al and the silicon substrate. Complete elimination of hillocks is reported in studies where the VLSI interconnections were fabricated by layering alternately Al and a refractory metal (Ti or W) [16, 42–44]. Recently, in an attempt to solve the ‘‘interconnect problem,’’ that is, the problem of unprecedented high density of interconnections operating at extremely high speeds and carrying high current densities, a modified version of the traditional metallic interconnection called the ‘‘multipath interconnect’’ has been proposed [45]. The modified interconnection consists of using the concept of parallel processing by providing two or more paths between the driving gate and the loading

4

PRELIMINARY CONCEPTS AND MORE

TABLE 1.1.1 Resistivity and Expansion Coefficients Material

Resistivity (m
cm)

Pure aluminum (bulk) Sputtered Al and Al/Si Sputtered Al/2% Cu/1% Si LPCVD aluminum Pure tungsten (bulk) CVD tungsten Evaporated/sputtered tungsten Ti (bulk) TiAl3 (bulk) CuAl2 (bulk–y phase) WAl12 Si SiO2

2.65 2.9–3.4 3.9 3.4 5.65 7–15 14–20 42.0 17–22 5–6 — — —

Thermal Expansion Coefficient ( C 1) 25.0  10 25.0  10 25.0  10 25.0  10 4.5  10 4.5  10 4.5  10 8.5  10 — — — 3.3  10 0.5  10

6 6 6 6 6 6 6 6

6 6

Melting Point ( C) 660 660 660 660 3410 3410 3410 1660 1340 591 647 — —

Source: From [16]. # 1985, by IEEE.

gate. A schematic of a three-section multipath interconnect (side view) connecting the driver and the load is shown in Fig. 1.1.2. These paths are stacked vertically isolated from one another by insulating layers between any two consecutive paths thereby taking the same area on the chip as a single-path interconnect. Depending on the number of paths, an array of such multipath interconnects could carry much higher currents on the chip. Furthermore, this interconnect structure could be built by an extension of the available microelectronics fabrication techniques.

FIGURE 1.1.2 Schematic of three-path multipath interconnection (side view) connecting driver and load on (a) semi-insulating substrate such as GaAs and (b) silicon substrate.

COPPER INTERCONNECTIONS

1.1.2

5

Optical Interconnections

As an alternative to electrical interconnections, optical interconnections have emerged in recent years which offer fast, reliable, and noise-free data transmission [46–50]. So far, they have been used for computer-to-computer communications and processor-to-processor interconnections. At this time, however, their applicability at lower levels of the packaging hierarchy, such as for module-to-module connections at the board level, chip-to-chip connections at the module level, and gate-to-gate connections at the chip level, is still under investigation. The principal advantages of optical interconnections over electrical connections are higher bandwidth, lower dispersion, and lower attenuation. Some of the problems with optical interconnections under investigation are size incompatibility with ICs, high power consumption, and tight alignment requirements.

1.1.3

Superconducting Interconnections

In recent years, the advent of high-critical-temperature superconductors has opened up the possibility of realizing high-density and very fast interconnections on siliconas well as GaAs-based high-performance ICs. The major advantages of superconducting interconnections over normal metal interconnections can be summarized as follows: (a) Signal propagation time on a superconducting interconnection will be much smaller as compared to that on a normal metal interconnection, (b) the packing density of the IC can be increased without suffering from the high losses associated with high-density normal metal interconnections, and (c) there is virtually no signal dispersion on superconducting interconnections for frequencies up to several tens of gigahertz.

1.2

COPPER INTERCONNECTIONS

To be able to produce high-speed ICs, it is always desirable to use interconnections that would allow rapid transmission of information, that is, signals among the various components on the chip. For the last 40 years, aluminum has been used almost exclusively to make metallic interconnection lines on ICs. More recently, aluminum–copper alloys have been used because they have been shown to provide better reliability than pure aluminum. In December 1997, in order to lower the resistance of metallic interconnections, IBM announced plans to replace aluminum with copper, a metal with lower resistivity of less than 2 m
cm compared to that of about 3 m
cm for aluminum. It is worth mentioning that while copper interconnections have been a hot topic in the semiconductor industry since the IBM announcement, the race to improve the aluminum interconnect technology has not slowed down. In fact, semiconductor companies are exploring new technologies for aluminum-based interconnections. These include ionized plasma deposition, hot aluminum physical vapor deposition (PVD), and aluminum damascene structures. It is expected that while advanced microprocessors and fast memory circuits may

6

PRELIMINARY CONCEPTS AND MORE

switch to copper interconnections, aluminum-based interconnections deposited by using the latest techniques will continue to coexist at least in the near future. While the semiconductor industry has known the potential advantages of using copper interconnects since the 1960s, it took over 30 years for it to overcome the associated challenges until it was announced in a paper on the complementary metal–oxide–semiconductor (CMOS) 7S technology presented at the Institute of Electrical and Electronics Engineers’ IEDM conference by IBM in December 1997. Following is a summary of the advantages of copper interconnects and the challenges in implementing this technology: 1.2.1

Advantages of Copper Interconnects

1. An obvious advantage of copper is its lower electrical resistivity compared with aluminum. In fact, copper interconnects offer 40% less resistance to electrical conduction than the corresponding aluminum interconnects, which results in speed advantages of as much as 15% in microprocessor circuits employing copper interconnects. 2. The phenomenon of electromigration that results in the movement of atoms and molecules in the interconnects under high-stress conditions of high temperatures and high current densities causing open- and short-circuit failures of interconnects through the formation of voids and hillocks is known to occur much less frequently in copper interconnects than in aluminum interconnects. That is why aluminum–copper alloys have been preferred over pure aluminum as the interconnect material. 3. Copper interconnects can be fabricated with widths in the range of 0.2 mm while it has been difficult to reduce dimensions below 0.35 mm with aluminum interconnects. This reduction in interconnection dimensions allows much higher packing densities of the order of 200 million transistors per chip. 4. It has been claimed that the deposition of copper interconnects can be achieved with a potential cost saving of up to 30%, which translates into a saving of about 10–15% for the full wafer [51]. 1.2.2

Challenges Posed by Copper Interconnects

In the United States, a consortium of 10 leading chip-making semiconductor companies known as SEMATECH (Semiconductor Manufacturing Technology) has worked hard to overcome the challenges posed by the replacement of aluminum interconnects by copper interconnects. Following is a list of technical challenges that must be addressed and met within acceptable standards to fabricate copper-based IC chips [52]: 1. Copper is considered poisonous for silicon-based circuits. It diffuses rapidly into the active source, drain, and gate regions of transistors built on the silicon

COPPER INTERCONNECTIONS

7

substrate and alters their electrical properties affecting the functionality of the transistors. 2. In order to meet the above challenge alone, an entirely new fabrication process is required for implementation of copper interconnects. 3. Fabrication of copper interconnects requires the production and use of a large amount of ultrapure water, which is rather expensive. 4. The release of waste discharges containing copper to the environment must be handled very carefully. 1.2.3

Fabrication Processes for Copper Interconnects

As shown in Fig. 1.2.1, a conventional photolithographic process for depositing aluminum interconnects on the silicon substrate involves the following steps: 1. 2. 3. 4.

Deposit a layer of silicon dioxide insulator on the silicon wafer. Deposit a layer of metal on the silicon dioxide layer. Cover the metal layer by depositing a layer of photoresist on it. Project a shadow of the interconnect pattern (drawn on a reticle) on the photoresist layer by using ultraviolet rays and an optical projection system. 5. Develop the photoresist that was exposed to the ultraviolet light.

FIGURE 1.2.1 Conventional photolithographic process steps for depositing aluminum metallization on silicon substrate.

8

PRELIMINARY CONCEPTS AND MORE

6. Using proper chemicals, etch away parts of the metal layer that are not covered by the hardened photoresist. 7. Finally, remove the hardened photoresist, leaving the interconnect metal in the desired pattern on the silicon dioxide layer. Since copper can contaminate the silicon substrate and the silicon dioxide dielectric layer of an IC resulting in increased junction leakages and threshold voltage instabilities, barrier layers are required to isolate the copper interconnects from the substrate and the dielectric layer. The barrier layer, usually made from tungsten or titanium nitride, should be as thin as possible to minimize the resistance and to maximize the reliability of the copper interconnects. It is applied after the interconnect channels have been etched out in the dielectric layer by photolithography. The barrier layer is covered by a microscopic seed layer of copper to ease further deposition of copper on the entire wafer by electroplating. Finally, the excess copper is removed by a chemical–mechanical polishing process leaving the desired pattern of copper interconnects on the wafer. The various steps are shown in Fig. 1.2.2. Various techniques have been studied for deposition of copper interconnects on silicon-based circuits. These include chemical vapor deposition (CVD), electroless plating, and electrolytic plating [51]. In each case, the objective was to deposit very thin and even layers of copper interconnects in the horizontal direction and vias in

FIGURE 1.2.2 Various steps involved in depositing copper metallizations.

COPPER INTERCONNECTIONS

9

FIGURE 1.2.3 Schematic of (a) voids and (b) seams that may be formed during late stages of copper deposition.

the vertical direction for connecting interconnects in different levels. It was found that the CVD and electroless plating techniques encountered several problems during fabrication whereas electrolytic plating worked satisfactorily, resulting in even copper films with a faster rate of deposition. 1.2.4

Damascene Processing of Copper Interconnects

At present, the damascene electroplating process is used frequently to make copper on-chip interconnects. The term ‘‘damascene’’ originates from the fact that a

FIGURE 1.2.4 Steps involved in depositing copper interconnections and vias using singledamascene process.

10

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.2.5 Steps involved in depositing copper interconnections and vias using dualdamascene process.

somewhat similar technique was used by the metallurgists of old Damascus to produce sharpest polished swords in the medieval era. In the world of semiconductor processing, this technique was initially used to form vias that are used to connect interconnects at different levels of an IC. In damascene processing, the patterns of interconnects or vias are formed first by etching the oxide on the substrate. Then the seed layer is deposited on the patterned substrate/oxide. This is followed by copper electroplating which deposits inside and outside the patterned features. Special care is taken to avoid the formation of voids and seams (shown in Fig. 1.2.3) during the late stages of copper deposition. The excess copper is finally removed by the chemical– mechanical planarization process. The steps involved in making copper interconnects using the damascene process are shown in Fig. 1.2.4. This process is repeated several times to form interconnects and vias for a multilevel interconnect structure required on an IC chip. The process described above is called the ‘‘single’’ damascene process because it differs from the more widely used ‘‘dual’’ damascene process in which both the interconnects and the vias are first patterned by etching of the substrate/oxide before the seed layer is formed and copper is deposited. It reduces the number of processing steps by avoiding one copper deposition step and one planarization step for each level of the interconnect structure. The steps involved in making copper interconnects using the dual damascene process are shown in Fig. 1.2.5.

1.3

METHOD OF IMAGES

The method of images can be used to find the potential due to a given electric charge in the presence of conducting planes and dielectric surfaces. To illustrate this

METHOD OF IMAGES

11

FIGURE 1.3.1 Line charge r lying in medium of dielectric constant e1 at distance d above second medium of dielectric constant e2 .

method, let us consider a line charge r lying in a medium of dielectric constant e1 and at a distance d above a second medium of dielectric constant e2 , as shown in Fig. 1.3.1. At the interface of the two media, the following two boundary conditions must be satisfied: 1. The normal component of the electric flux density (Dn ) is the same on the two sides of the interface. 2. The tangential component of the electric field (Et ) is also the same across the interface. Using the coordinate system of Fig. 1.3.1, it means that at y ¼ 0 Dn1 ¼ Dn2

or

e1 Ey1 ¼ e2 Ey2

ð1:3:1Þ

and Ex1 ¼ Ex2

ð1:3:2Þ

The potential V due to an infinite line charge ( r) in a medium of dielectric constant e at a distance r is given by V¼

r lnðr 2 Þ 4pe

ð1:3:3Þ

When a second dielectric is present, the real charge r produces image charges across the dielectric interface. If the observation point P is above the interface, that is, on the same side as the real line charge (see Fig. 1.3.2a), an image charge r1 will be at a distance d below the interface. With the real line charge at x ¼ 0 and y ¼ d,

12

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.3.2 (a) Observation point P on same side as real line charge. (b) Observation point P below dielectric interface.

the distance between the real charge and the observation point is given by qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi x2 þ ðy dÞ2

r¼

and with the image charge at x ¼ 0 and y ¼ charge and the observation point is given by ri ¼

d, the distance between the image

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi x2 þ ðy þ dÞ2

Using Eq. (1.3.3), the potential at all points above the interface, that is, for y  0, will be V1 ¼

1 ½r lnðr 2 Þ þ r1 lnðri2 ފ 4pe1

Now since Ex1 ¼

@V1 @x

METHOD OF IMAGES

13

for y  0 Ex1 ¼

1 @ fr ln½x2 þ ðy 4pe1 @x

dÞ2 Š þ r1 ln½x2 þ ðy þ dÞ2 Šg

or " # 1 2x 2x r þ r1 Ex1 ¼ 4pe1 x2 þ ðy dÞ2 x2 þ ðy þ dÞ2

ð1:3:4Þ

Similarly Ey1 ¼

@V1 @y

Therefore, for y  0 Ey1 ¼

1 @ fr ln½x2 þ ðy 4pe1 @y

dÞ2 Š þ r1 ln½x2 þ ðy þ dÞ2 Šg

or " # 1 2ðy dÞ 2ðy þ dÞ þ r1 r Ey1 ¼ 4pe1 x2 þ ðy dÞ2 x2 þ ðy þ dÞ2

ð1:3:5Þ

If the observation point P lies below the dielectric interface, that is, in the medium with dielectric constant e2 (see Fig. 1.3.2b), then the real line charge r must be modified to take care of the effect of the dielectric interface. This modified charge, say r2, can be found in terms of r as shown below. The distance between the observation point and the charge r is again given by

r¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi x2 þ ðy dÞ2

The potential V2 below the interface is then given by V2 ¼

1 ½r lnðr 2 ފ 4pe2 2

Now, since Ex2 ¼

@V2 @x

14

PRELIMINARY CONCEPTS AND MORE

for y  0 Ex2 ¼

1 @ fr ln½x2 þ ðy 4pe2 @x 2

dÞ2 Šg

or " # 1 2x r Ex2 ¼ 4pe2 2 x2 þ ðy dÞ2

ð1:3:6Þ

Similarly Ey2 ¼

@V2 @y

Therefore, for y  0 Ey2 ¼

1 @ fr ln½x2 þ ðy 4pe2 @y 2

dÞ2 Šg

or " # 1 2ðy dÞ r Ey2 ¼ 4pe2 2 x2 þ ðy dÞ2

ð1:3:7Þ

Applying the continuity condition (1.3.2) to Eqs. (1.3.4) and (1.3.6), we get     1 2x r2 2x ¼ ½r þ r1 Š 2 4pe2 x2 þ d 2 4pe1 x þ d2 From this, it follows that r þ r1 r2 ¼ e1 e2

ð1:3:8Þ

Applying the continuity condition (1.3.1) to Eqs. (1.3.5) and (1.3.6), we find that     e1 2d e2 r2 2d ¼ ð r þ r1 Þ 2 4pe1 4pe2 x2 þ d2 x þ d2 from which it follows that r þ r1 ¼

r2

ð1:3:9Þ

METHOD OF MOMENTS

15

Combining Eqs. (1.3.8) and (1.3.9), we get r þ r1 r r1 ¼ e1 e2 from which the image charges r1 and r2 can be found in terms of the real charge r and the dielectric constants e1 and e2 to be r1 ¼ r

  e1 e2 e1 þ e2

ð1:3:10Þ

r2 ¼ r



ð1:3:11Þ

2e2 e1 þ e2



To find the image of a charge in a grounded conducting plane, it is well known that the image charge has the same magnitude as the real charge but an opposite sign and that it lies as much below the ground plane as the real charge is above it.

1.4

METHOD OF MOMENTS

The method of moments is a basic mathematical technique for reducing functional equations to the matrix equations [53]. Consider the inhomogenous equation Lðf Þ ¼ g

ð1:4:1Þ

where L is a linear operator, f is a field or response (the unknown function to be determined), and g is a source or excitation (a known function). We assume that the problem is deterministic, that is, there is only one solution function f associated with a given excitation g. Let us expand the function f in a series of basis functions f1 ; f2 ; f3 ; . . . ; fn in the domain of L as f ¼

X

an fn

n

ð1:4:2Þ

where the an are constants. The functions fn are called expansion functions or the basis functions. For exact solutions, Eq. (1.4.2) is usually an infinite summation and the functions fn form a complete set of basis functions. For approximate solutions, Eq. (1.4.2) is usually a finite summation. Substituting Eq. (1.4.2) into Eq. (1.4.1) and using the linearity of the operator L, we have X n

an Lðfn Þ ¼ g

ð1:4:3Þ

16

PRELIMINARY CONCEPTS AND MORE

Now, defining a set of weighting functions or testing functions w1 , w2 , w3 ; . . . in the range of L and taking the inner product with each wm , the result is X n

an hwm ; Lfn i ¼ hwm ; gi

m ¼ 1; 2; 3; . . .

This set of equations can be written in matrix form as ½lmn Š½an Š ¼ ½gm Š where ½lmn Š ¼ ½hwm; Lfn iŠ and ½an Š and ½gm Š are column vectors. If the matrix ½lmn Š is nonsingular, then the matrix ½lmn Š 1 exists. The constants an are then given by ½an Š ¼ ½lmn Š 1 ½gm Š and the solution function f is given by Eq. (1.4.2) as f ¼

X n

an fn ¼ ½lmn Š 1 ½gm Š½fn Š

This solution may be exact or approximate depending upon the choice of functions fn and weighting functions wn . The particular choice wn ¼ fn is known as the Galerkin method. If the matrix ½lmn Š is of infinite order, it can be solved only in special cases, for example, if it is diagonal. If the sets fn and wn are finite, then the matrix ½lmn Š is of finite order and can be inverted by known methods such as the Gauss–Jordan reduction method. In most problems of practical interest, the integration involved in evaluating lmn ¼ hwm ; Lfn i is usually difficult to perform. A simple way to obtain approximate solutions is to require that Eq. (1.4.3) be satisfied at certain discrete points in the region of interest. This process is called a point-matching method. In terms of the method of moments, it is equivalent to using Dirac delta functions as the weighting functions. Another approximation useful for practical problems involves dividing the region of interest into several small subsections and requiring that the basis functions fn are constant over the areas of the subsections. This procedure, called the method of subsections, often simplifies the evaluation of the matrix ½1mn Š. Sometimes, it is more convenient to use the method of subsections in conjunction with the point-matching method. One of the most important tasks in any particular problem is the proper choice of the functions fn and wn . The functions fn should be linearly independent and chosen so that some superposition (1.4.3) can approximate the function f reasonably accurately. The functions wn should also be linearly independent and chosen so that

EVEN- AND ODD-MODE CAPACITANCES

17

the products hwn ; gi depend on the relative independent properties of g. Some additional considerations while choosing the functions fn and wn are accuracy of the solution desired, ease of evaluation of the matrix elements, size of the matrix that can be inverted, and realization of a well-conditioned matrix.

1.5

EVEN- AND ODD-MODE CAPACITANCES

In this section, the even- and odd-mode capacitances associated with systems of two or three coupled conductors are discussed. 1.5.1

Two Coupled Conductors

Two coupled conductors of different dimensions lying in the same plane at a distance d above the ground plane are shown in Fig. 1.5.1. We are interested in finding the self and mutual (or coupling) capacitances for this system. In other words, we want to find the capacitances between each conductor and the ground (denoted by C11 and C22 ) and the capacitance between the two conductors (denoted by C12 ). To simplify the analysis, the problem can be split into the even and odd modes. In the even mode, each conductor is assumed to be at 1 V potential with the same sign for each conductor. In the odd mode, the first conductor is assumed to be at a þ1 V potential while the second conductor is kept at a 1 V potential. First, we will determine the even- and odd-mode capacitances for each conductor separately. In the even mode shown in Fig. 1.5.2, there are no electric field lines at the center between the two conductors. Therefore, this plane can be treated as a magnetic wall which represents an open circuit to any mutual capacitance between the two

FIGURE 1.5.1 Two coupled conductors of different dimensions lying in same plane at distance d above ground plane.

18

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.5.2 (a) Electric field lines for two conductors in even mode. (b) Equivalent circuit for two conductors in even mode.

conductors. Therefore, we can say that ðeÞ

ð1:5:1Þ

ðeÞ

ð1:5:2Þ

C1 ¼ C11 C2 ¼ C22 ðeÞ

ðeÞ

where C1 is the even-mode capacitance for the first conductor while C2 is that for the second conductor. In the odd mode shown in Fig. 1.5.3, the plane of symmetry between the two conductors can be treated as a grounded electric wall. This represents a short circuit to the mutual capacitance C12 . Therefore, in this case ðoÞ

ð1:5:3Þ

ðoÞ

ð1:5:4Þ

C1 ¼ C11 þ 2C12 C2 ¼ C22 þ 2C12

EVEN- AND ODD-MODE CAPACITANCES

19

FIGURE 1.5.3 (a) Electric field lines for two conductors in odd mode. (b) Equivalent circuit for two conductors in odd mode.

ðoÞ

ðoÞ

where C1 and C2 are the odd-mode capacitances for the first and second conductors, respectively. The mutual capacitance C12 can be expressed in terms of ðoÞ ðeÞ C1 and C1 using Eqs. (1.5.1) and (1.5.3) as h ðoÞ C12 ¼ 12 C1

ðeÞ

C1

i

while the self-capacitances are given by Eqs. (1.5.1) and (1.5.2). 1.5.2

Three Coupled Conductors

As in the case of two conductors, the three-conductor case can also be treated by splitting it into the even and odd modes. In the even mode, each conductor is again assumed to be at a þ1 V potential. In the odd mode, one conductor is kept at a þ1 V potential while the other two conductors are assumed to be at 1 V potential. This means that when finding the odd-mode charge on the first conductor, for example, the potentials on the second and third conductors are of the opposite sign to that on

20

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.5.4 Self- and mutual capacitances for three conductors.

the first conductor. Figure 1.5.4 shows the self and mutual capacitances for the three conductors. These capacitances can be found in terms of the even- and odd-mode capacitances of the three conductors. In the even mode, ðeÞ

ðeÞ

C1 ¼ C11

ðeÞ

C2 ¼ C22

C3 ¼ C33

ð1:5:5Þ

In the odd mode, ðoÞ

C1 ¼ C11 þ 2C12 þ 2C13 ðoÞ

ð1:5:6Þ

C2 ¼ C22 þ 2C12 þ 2C23 ðoÞ

C3 ¼ C33 þ 2C13 þ 2C23 Solving these equations, we can find that the mutual capacitances are given by ðeÞ

C12 ¼ 14 ½ C1

ðeÞ

ðeÞ

ðeÞ

C13 ¼ 14 ½ C1 þ C2 ðeÞ

C23 ¼ 14 ½C1

ðeÞ

ðoÞ

ðeÞ

ðoÞ

ðoÞ

C3 Š

ðoÞ

ðoÞ

C2 þ C3 þ C1 þ C2

ðeÞ

C2

ðoÞ

C3 þ C1

C2 þ C3 Š

ðeÞ

ðoÞ

C3

ðoÞ

ðoÞ

C1 þ C2 þ C3 Š

The self-capacitances are given by Eqs. (1.5.5).

ð1:5:7Þ

TRANSMISSION LINE EQUATIONS

1.6

21

TRANSMISSION LINE EQUATIONS

A transmission line can be treated as a repeated array of small resistors, inductors, and capacitors. In fact, the transmission line theory can be developed in terms of alternating current (AC) circuit analysis, but the equations become extremely complicated for all but the simple cases [54]. It is more convenient to treat such lines in terms of differential equations which lead naturally to a wave equation which is of fundamental importance to electromagnetic theory in general. We can develop the differential equations for a uniform transmission line by a simple circuit analysis of its equivalent circuit, shown in Fig. 1.6.1, consisting of several incremental lengths and then taking the limit as the length of the increment approaches zero. The notations of voltage and current at some general points x and x þ
x along the line are shown in Fig. 1.6.1. The parameters R, L, G, and C are the resistance, inductance, conductance, and capacitance values per unit length of the line, respectively. As
x is changed, these values remain the same. We assume that the voltage and current are sinusoidal and that at any point x along the line the time variation of voltage is given by vx ¼ v0 ejot Now, if we apply Kirchhoff’s voltage law around the first incremental loop in Fig. 1.6.1, we obtain vx ¼ ix R
x þ ix ðjoLÞ
x þ vxþ
x or vxþ
x

FIGURE 1.6.1

vx ¼

ix ðR þ joLÞ
x

Equivalent circuit for uniform transmission line.

ð1:6:1Þ

22

PRELIMINARY CONCEPTS AND MORE

In the above equations, R and L have been multiplied by
x to get the actual values of resistance and inductance for an incremental section of length
x. Now, the total current ix into the first incremental section at x minus the total current ixþ
x into the next section at x þ
x must be equal to the total current through the shunt capacitance C and the parallel resistance Rp , that is, ix

ixþ
x ¼

vx vx þ Rp =
x 1=ðjoC
xÞ

or, setting 1=Rp ¼ G, the conductance per unit length, we get ixþ
x

ix ¼

vx ðG þ joCÞ
x

ð1:6:2Þ

In Eq. (1.6.1), the left-hand side represents the incremental voltage drop along the line denoted by
vx. Dividing both sides of Eq. (1.6.1), we get
vx ¼
x

ix ðR þ joLÞ

Similarly, Eq. (1.6.2) can be expressed as
ix ¼
x

vx ðG þ joCÞ

Now, if
x is made very very small, then the incremental voltage or current change per incremental distance becomes the corresponding derivative. Thus we get the two fundamental differential equations for a uniform transmission line, dvx ¼ dx

ðR þ joLÞix

ð1:6:3Þ

dix ¼ dx

ðG þ joCÞvx

ð1:6:4Þ

where all line parameters are per unit distance. These equations can be solved if they can be written in terms of one unknown (vx or ix ). An equation in terms of vx can be written by first taking the derivative of Eq. (1.6.3) with respect to x to yield d2 vx ¼ dx2

ðR þ joLÞ

dix dx

ð1:6:5Þ

and then substituting Eq. (1.6.4) in Eq. (1.6.5) to get d 2 vx ¼ ðR þ joLÞðG þ joCÞvx ¼ g2 vx dx2

ð1:6:6Þ

MILLER’S THEOREM

23

where g2 ¼ ðR þ joLÞðG þ joCÞ

ð1:6:7Þ

Similarly, an equation in terms of ix can be obtained by first differentiating Eq. (1.6.4) and then substituting Eq. (1.6.3) to yield d2 ix ¼ ðR þ joLÞðG þ joCÞix ¼ g2 ix dx2

ð1:6:8Þ

Equations (1.6.6) and (1.6.8) are the fundamental relationships governing wave propagation along a uniform transmission line. The symbol g as defined by Eq. (1.6.7) is known as the propagation constant, that is, pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi g ¼ ðR þ joLÞðG þ joCÞ In general, g is a complex number. The real part of g gives the reduction in voltage or current along the line. This quantity, when expressed per unit length of the line, is referred to as the attenuation constant a given by a ¼ Re

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðR þ joLÞðG þ joCÞ

For a transmission line with no losses, a ¼ 0, that is, a line with no losses has no attenuation. The imaginary part of g, when expressed per unit length of the line, is known as the phase constant b given by b ¼ Im

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðR þ joLÞðG þ joCÞ

For a lossless line where R ¼ G ¼ 0, the phase constant becomes pffiffiffiffiffiffi b ¼ o LC

with dimensions of radians per meter in rationalized meter–kilogram–second (RMKS) units. Phase shift per unit length along the line is a measure of the velocity of propagation of a wave along the line, that is, v¼

1.7

o 1 ¼ pffiffiffiffiffiffi b LC

MILLER’S THEOREM

Miller’s theorem is an important theorem which can be used to uncouple nodes in electric circuits. Consider a circuit configuration with N distinct nodes 1, 2, 3,. . ., N

24

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.7.1 (a) Circuit configuration with N distinct nodes. (b) Circuit configuration equivalent to that shown in Fig. 1.7.1a.

as shown in Fig. 1.7.1a. The node voltages can be denoted by V1, V2 , V3 ,. . ., VN , where VN is zero because N is the reference node. Nodes 1 and 2 are connected by an impedance Zc . We assume that the ratio V2 =V1 is known or can be determined by some means. Let us denote this ratio by K, which, in general, can be a complex number. It can be shown that the configuration shown in Fig. 1.7.1a is equivalent to that shown in Fig. 1.7.1b provided Z1 and Z2 have certain specific values. These values of Z1 and Z2 can be found by equating the currents leaving nodes 1 and 2 in the two configurations. The current I1 leaving node 1 through impedance Zc in configuration (a) is given by I1 ¼

V1

V2 Zc

¼ V1

1

K Zc

¼

V1 Zc =ð1 KÞ

while the current leaving node 1 through impedance Z1 in configuration (b) is given by V1 =Z1. Therefore, we conclude that Z1 ¼

Zc 1

K

In a similar manner, the current I2 leaving node 2 through impedance Zc in configuration (a) is given by I2 ¼

V2

V1 Zc

¼ V2

1

ð1=KÞ V2 ¼ Zc =ð1 1=KÞ Zc

while the current leaving node 2 in configuration (b) is V2 =Z2 . Therefore, the value of impedance Z2 should be Z2 ¼

1

Zc K ¼ Zc 1=K K 1

INVERSE LAPLACE TRANSFORMATION

25

Since configurations (a) and (b) have identical nodal equations, these are identical. However, we note that Miller’s theorem is useful only if the value of the ratio K can be determined by some independent means.

1.8

INVERSE LAPLACE TRANSFORMATION

In several cases, it is more convenient to solve the equations in the frequency domain, that is, the s domain, and then obtain the time-domain solution by an inverse Laplace transformation of the s-domain solution. Various techniques for numerical inverse Laplace transformation are available in the literature. The technique presented in this section is simple yet efficient and can be easily incorporated in computer programs. It uses the Pade´ approximation and does not require the computation of poles and residues [55, 56]. The inverse Laplace transform of VðsÞ is given by vðtÞ ¼

1 2pjt

cþj1

Z

VðsÞest ds

c j1

ð1:8:1Þ

The variable t can be removed from est by the transformation z ¼ st

ð1:8:2Þ

and then using an approximation for ez. Substituting Eq. (1.8.2) in Eq. (1.8.1), we obtain 1 vðtÞ ¼ 2pjt

Z

c0 þj1

VðsÞez dz

c0 j1

ð1:8:3Þ

According to the Pade´ approximation, the function ez can be approximated by a rational function RN;M ðzÞ ¼

PN ðzÞ QM ðzÞ

ð1:8:4Þ

where PN ðzÞ and QM ðzÞ are polynomials of order N and M, respectively. Inserting Eq. (1.8.4) in Eq. (1.8.3), we obtain 1 ^vðtÞ ¼ 2pj

Z

c0 þj1

c0 j1

V

z RN;M ðzÞ dz t

ð1:8:5Þ

where ^vðtÞ is the approximation for vðtÞ. The integral (1.8.5) can be evaluated by using residue calculus and choosing the path of integration along the infinite arc

26

PRELIMINARY CONCEPTS AND MORE

either to the left or to the right. To ensure that the path along the infinite arc does not contribute to the integral, M and N are chosen such that the function FðzÞ ¼ V

 z RN;M ðzÞ t

ð1:8:6Þ

has at least two more poles than zeros. This gives Z C

FðzÞ dz ¼ 2pj

X

ðresidue at poles inside closed pathÞ

ð1:8:7Þ

where the positive sign is used when the path C is closed in the left-half plane and the negative sign is applied when C is closed in the right-half plane. For N < M, we have M X Ki z zi i¼1

RN;M ðzÞ

ð1:8:8Þ

where zi are the poles of RN;M ðzÞ and Ki are the corresponding residues. Closing the path of integration around the poles of RN;M ðzÞ in the right-half plane, we get the basic inversion formula ^vðtÞ ¼

M z  1X i Ki V t t i¼1

ð1:8:9Þ

When M is even, we can write 0

^vðtÞ ¼

M h z i 1X i Re Ki0 V t t i¼1

ð1:8:10Þ

where M 0 ¼ M=2 and Ki0 ¼ 2Ki . When M is odd, M 0 ¼ ðM þ 1Þ=2 and Ki0 ¼ Ki for the residue corresponding to the real poles. The poles zi and residues Ki0 have been calculated with high precision and are used in the programs in this book. To summarize, for a given function VðsÞ in the s domain, the response vðtÞ at any time t can be obtained by the following steps: 1. Select appropriate values of N and M and take values of zi and Ki0 from the computed tables [55, 56]. 2. Divide each zi by t and substitute ðzi =tÞ for each s in VðsÞ. 3. Multiply each Vðzi =tÞ by the corresponding Ki0 and add the products. 4. Retain only the real part of the result in step 3 and divide by t.

RESISTIVE INTERCONNECTION AS LADDER NETWORK

27

Note that, because of division by t, the value of vðtÞ at t ¼ 0 cannot be calculated by the above procedure. However, either this value can be obtained by using the initial-value theorem or an approximate value can be found by selecting a very small initial value of t. The technique described above is suitable for the calculation of the system response to a nonperiodic excitation such as a step or an impulse.

1.9

RESISTIVE INTERCONNECTION AS LADDER NETWORK

It is well known that interconnections made of high-resistivity materials such as polycrystalline silicon (poly-Si) result in much higher signal delays than the lowresistivity metallic interconnections. However, in the past, poly-Si has remained a principal material for the second-level interconnections. In order to analyze highspeed signal propagation in resistive interconnections, it is important to understand their transmission characteristics. In this section, it will be shown that resistive interconnections can be modeled as ladder RC networks under open-circuit, shortcircuit, as well as capacitive loading conditions [57, 58]. Finally, the ladder approximation has been applied to a multipath interconnect to perform a first-order analysis of the dependence of the propagation delays expected in such an interconnect on the number of paths. 1.9.1

Open-Circuit Interconnection

From transmission line theory [59], the open-circuit voltage transfer function of a resistive transmission line is given by V2 1 pffiffiffiffiffiffiffiffiffi ¼ V1 cosh sRC

ð1:9:1Þ

where R is the total line resistance and C is the total line capacitance including the capacitance due to the fringing fields as described by Ruehli and Brennan [60]. Using infinite partial-fraction expansions [61], Eq. (1.9.1) can be written as " 1 V2 1 4X pffiffiffiffiffiffiffiffiffi ¼ ¼ ð 1Þðkþ1Þ V1 cosh sRC p k¼1 ð2k

2k

1

1Þ2 þ sRCð4=p2 Þ

#

ð1:9:2Þ

If v1 ðtÞ is a Dirac pulse, then the voltage v2 ðtÞ can be found easily by finding the inverse Laplace transforms of the terms on the right side of Eq. (1.9.2). If v1 ðtÞ is a unit step voltage, then V1 ¼ V0 =s (with V0 ¼ 1) and v2 ðtÞ can be obtained after a simple integration to be

v2 ðtÞ ¼ L

1



"  X 1 1=s 4 ðkþ1Þ pffiffiffiffiffiffiffiffiffi ¼ 1 ð 1Þ pð2k 1Þ cosh sRC k¼1

exp

ð2k

1Þ2 p2 t 4RC

!#

28

PRELIMINARY CONCEPTS AND MORE

or  4 1 v2 ðtÞ ¼ p ¼1

1 1 þ 3 5

1:273 e

1 þ


7

p2 t=ð4RCÞ



 4 e p

þ 0:424 e

1 e 3

p2 t=ð4RCÞ

9p2 t=ð4RCÞ

9p2 t=ð4RCÞ

0:254 e

 þ




25p2 t=ð4RCÞ

þ


ð1:9:3Þ

It should be noted that the expression (1.9.3) differs from the corresponding approximate expression in reference [57], vout ðtÞ ¼ 1

1:172 e

p2 t=ð4RCÞ

þ 0:195 e

9p2 t=ð4RCÞ

0:023 e

25p2 t=ð4RCÞ

ð1:9:4Þ

which was obtained by a finite partial-fraction expansion of an infinite expansion of Eq. (1.9.1). It can be seen that the terms of second and higher orders in Eq. (1.9.4), which are particularly important at low values of time, are far from correct. A T network and the corresponding n-stage ladder network for an interconnection line are shown in Figs. 1.9.1a and b, respectively. In Fig. 1.9.1b, ri ¼ R=ðn þ 1Þ and ci ¼ C=n. Now, we need to determine the number of ladder stages required to generate the output voltage based on the transmission line model given by Eq. (1.9.3). Assuming unit step input, a comparison of the plots of the output voltage versus time for an open-circuited interconnection obtained by using Eq. (1.9.3), obtained by a numerical simulation of the T network and those obtained by

FIGURE 1.9.1 Representation of interconnection line as (a) T network and (b) n-stage ladder network. (From [54]. # 1983 by IEEE.)

RESISTIVE INTERCONNECTION AS LADDER NETWORK

29

FIGURE 1.9.2 Output voltage versus time for open resistive transmission line for unit step input voltage. (From [55]. # 1983 by IEEE.)

numerical simulations of the ladder network with different number of stages, is shown in Fig. 1.9.2. For the sake of comparison, the output voltage plot obtained by using the approximate expression (1.9.4) is also included in Fig. 1.9.2. It can be seen that the plot obtained by using Eq. (1.9.3) almost coincides with that obtained for the ladder network with 5 stages. In fact, there is negligible difference between the results for the 5- and 10-stage ladder networks. For an interconnection line loaded with a capacitance CL , the voltage transfer function can be easily obtained in the s domain, but its analytical inverse Laplace transformation is not possible. Therefore, lumped-circuit approximations have to be used. It can be shown that, for a wide range of CL =C values, a five-stage ladder network yields sufficient accuracy. Thus, the conclusion for an open-circuit interconnection also holds for a capacitively loaded interconnection. 1.9.2

Short-Circuited Interconnection

For a short-circuited RC transmission line, the output current for a step input voltage V0 =s is given by 1 pffiffiffiffiffiffiffiffiffi I ¼ CV0 pffiffiffiffiffiffiffiffiffi sRC sinh sRC

ð1:9:5Þ

Using infinite partial-fraction expansion [61], Eq. (1.9.5) can be written as "

1 1 2 X 1 ð 1Þk I ¼ CV0 þ sRC RC k¼1 s þ ½p2 k2 Š=ðRCÞ

#

ð1:9:6Þ

30

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.9.3 Output current versus time for short-circuited resistive transmission line for unit step input voltage. (From [55]. # 1983 by IEEE.)

The output current in the time domain can then be easily obtained by finding the inverse Laplace transforms of the terms on the right side of Eq. (1.9.6) to be iðtÞ ¼

V0 ½1 R

2e

p2 t=ðRCÞ

þ 2e

p2 4t=ðRCÞ

2e

p2 9t=ðRCÞ

þ


Š

ð1:9:7Þ

Assuming unit step input, a comparison of the plots of the output current versus time for a short-circuited interconnection obtained by using Eq. (1.9.7), obtained by a numerical simulation of the T network and those obtained by numerical simulations of the ladder network with different number of stages, is shown in Fig. 1.9.3. It can be seen that, for a short-circuited interconnection, at least 10 stages

FIGURE 1.9.4 Ten-stage RC ladder network approximation applied to each path of multipath interconnection.

PROPAGATION MODES IN MICROSTRIP INTERCONNECTION

31

FIGURE 1.9.5 Dependence of propagation delay on number of paths of multipath interconnection included in SPICE model of Fig. 1.9.4. Results obtained by simulation of multipath interconnection by semiconductor TCAD tool also shown.

are required in the ladder network to obtain good agreement with the analytical solution.

1.9.3

Application of Ladder Approximation to Multipath Interconnection

For this analysis, an n-path multipath interconnection on the GaAs substrate is considered and the 10-stage ladder network approximation is used for each path of the multipath interconnection. In other words, each path is represented by a ladder of RC combinations as shown in Fig. 1.9.4. As shown in this figure, the interconnection is driven by a 50- voltage source and is terminated by a 50- load. The symbols R1 , R2 , and Rn represent the total resistances of the first, second, and nth paths of the interconnection whereas C1, C2 and Cn represent the total ground capacitances (including the fringing fields) of the first, second, and the nth paths. In this analysis, the coupling capacitances between the consecutive paths have been ignored because essentially the same voltage signal is propagating along the different paths of the same interconnection. The dependence of the propagation delay on the number of paths included in the above model using SPICE is shown in Fig. 1.9.5. For the sake of comparison, this figure also includes the results obtained by simulation of the multipath interconnection by a semiconductor technological computer-aided design (TCAD) tool.

1.10

PROPAGATION MODES IN MICROSTRIP INTERCONNECTION

A resistivity–frequency mode chart of the metal–insulator–semiconductor (MIS) microstripline [62] is shown in Fig. 1.10.1, where d is the skin depth and r is the semiconductor resistivity. It can be seen from this figure that the propagation mode

32

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.10.1 Resistivity-frequency mode chart of MIS microstripline. (From [62]. # 1984 by IEEE.)

in the microstrip depends on the substrate resistivity and the frequency of operation. Figure 1.10.1 shows the following: 1. When the substrate resistivity is low (less than approximately 10 3
cm), the substrate acts like an imperfect metal wall having a large skin effect resulting in the skin effect mode. 2. When the substrate resistivity is high (greater than approximately 104
cm) then the substrate acts like an insulator and the dielectric quasi-TEM mode propagates. 3. For an MIS waveguide, the slow-wave mode propagates when the substrate is semiconducting and the frequency is low. The slow-wave mode results because, in the low-frequency limit (note that this frequency limit extends into the gigahertz range at certain substrate resistivities), the electric field lines do not penetrate into the semiconductor whereas the magnetic field lines can fully penetrate into it causing spatially separated storage of electric and magnetic energies. 1.11

SLOW-WAVE MODE PROPAGATION

In this section, a quasi-TEM analysis of slow-wave mode propagation in the micrometer-size coplanar MIS transmission lines on heavily doped semiconductors [63] is presented. The analysis includes metal losses as well as semiconductor losses. The quantities derived from the quasi-TEM analysis are compared with those

SLOW-WAVE MODE PROPAGATION

33

FIGURE 1.11.1 (a) Cross-sectional view and (b) plan view of micrometer-size coplanar MIS transmission lines. (From [63]. # 1986 by IEEE.)

measured experimentally for a system of four micrometer-size coplanar MIS transmission lines fabricated on Nþ silicon. 1.11.1

Quasi-TEM Analysis

The geometry of the microstructure MIS transmission lines used in this analysis is shown in Fig. 1.11.1. For the experimental results presented below, these structures consist of coplanar aluminum strips (fabricated by evaporating Al on SiO2) separated from antimony-doped Nþ silicon substrate of doping density Nd  3  1018 cm 3 and electrical conductivity 80 (
cm) 1 by a thin SiO2 layer. For the four transmission lines used in the experimental results, the wafer thickness d is 530 mm, the length l is 2500 mm, and the metal thickness t is 1 mm. The values of the other dimensions shown in Fig. 1.11.1 and the capacitance scaling factor used later in this analysis for each of the four lines are listed in Table 1.11.1. Because of the low impedance of the Nþ semiconductor, most of the electrical energy is confined to the insulating layer immediately below the center conductor. However, because the semiconductor is a nonmagnetic material, the magnetic field freely penetrates the Nþ substrate. This separation of the electric and magnetic energies results in the slow-wave mode propagation. For quasi-TEM propagation of the slow-wave mode of coplanar microstructure MIS transmission line, its equivalent circuit used in this analysis is shown in

34

PRELIMINARY CONCEPTS AND MORE

TABLE 1.11.1 Dimensions S, W, and h and Capacitance Scaling Factor K of Experimental lines Line 1 2 3 4

S

W

h

K

4.2 4.2 8.7 4.7

6.0 14.0 9.5 13.5

0.53 0.53 0.28 0.28

1.3 1.3 1.1 1.2

Source: From [65]. # 1987 by IEEE. Note: All dimensions are in micrometers.

Fig. 1.11.2. The inductance per unit length, L, is given by L¼

1 c2 C

ð1:11:1Þ

air

where c is the phase velocity in vacuum and Cair is the capacitance per unit length of an equivalent air-filled transmission line. Here, Cair can be determined by conformal mapping [64] leading to the following expression for L: L¼

1 4c2 e0 F

ð1:11:2Þ

where e0 is the permittivity of free space and F is a geometric factor given approximately by [64]

F¼

8 pffiffiffi > ln½2ð1 þ kÞ=ð1 > > > < p > > > > :

p pffiffiffiffi ln½2ð1 þ k0 Þ=ð1

pffiffiffi kފ pffiffiffiffi k0 ފ

0:707  k  1 0  k  0:707

ð1:11:3Þ

FIGURE 1.11.2 ‘‘Slow-wave’’ mode equivalent circuit of micrometer-size coplanar MIS transmission line used in quasi-TEM analysis. (From [63]. # 1986 by IEEE.)

SLOW-WAVE MODE PROPAGATION

35

with k¼

S S þ 2W

ð1:11:4Þ

k0 ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffi 1 k2

ð1:11:5Þ

In Fig. 1.11.2, the resistance Rm in series with L represents the correction due to the metal conductive losses. Its value in ohms per unit length is approximately equal to the effective resistance of the center conductor given by

Rm ¼

8 1 > > > > < sm tS > > > > :

for t  dm

1 for t  dm s m dm S

ð1:11:6Þ

where sm and dm are the conductivity and skin depth of aluminum, respectively. The ground-plane contribution to Rm can be ignored because the current densities in it are much smaller than those in the center conductor. The resistance RL is inserted in the equivalent circuit of Fig. 1.11.2 to account for the loss caused by the longitudinal current flowing in the Nþ semiconductor parallel to the current in the center conductor. Since the longitudinal semiconductor current flows in addition to the longitudinal current in the metal, a parallel connection has been used. The value of RL is given by

RL ¼

1 s S dS S

ð1:11:7Þ

where sS and dS are the conductivity and skin depth of the Nþ semiconductor, respectively. Equation (1.11.7) is based on the assumption that the longitudinal electric field under the center conductor decays exponentially in the vertical direction with decay constant dS . To account for the energy storage and loss associated with the transverse electric field and current, the transverse capacitance Ct and transverse resistance Rt have been included in Fig. 1.11.2. The transverse capacitance per unit length is given approximately by

Ct ¼

ei e0 SK h

ð1:11:8Þ

36

PRELIMINARY CONCEPTS AND MORE

where ei is the dielectric constant of SiO2 and K is a geometric factor listed in Table 1.11.1 introduced to account for the capacitance associated with the fringing fields. Equation (1.11.8) is based on the assumption that most of the electric energy is stored in the dielectric layer under the center conductor. The value of the transverse resistance is given approximately by

Rt ¼

1 2sS F

ð1:11:9Þ

where F is the geometric factor given by Eq. (1.11.3). In this analysis, we have ignored the finite transverse capacitance through the air because its susceptance is very small compared with that of Ct and Rt in series. For a transmission line consisting of the circuit elements of Fig. 1.11.2, the complex propagation constant g and the complex characteristic impedance Z0 are given by g ¼ a þ jb ¼

Z0 ¼

Z00

þ

jZ000

pffiffiffiffiffiffi ZY

ð1:11:10Þ

rffiffiffiffi Z ¼ Y

ð1:11:11Þ

where

Z¼

1 1=RL þ 1=ðRm þ joLÞ

ð1:11:12Þ

Y¼

1 Rt þ 1=ðjoCt Þ

ð1:11:13Þ

and the quality factor Q and the ‘‘slowing factor’’ l0 =lg are given by

Q¼

b 2a

l0 b ¼ pffiffiffiffiffiffiffiffiffi lg o m0 e0

ð1:11:14Þ

ð1:11:15Þ

SLOW-WAVE MODE PROPAGATION

37

FIGURE 1.11.3 Contours of constant Q for transmission line 2. Dashed line corresponds to experiment parameters. (From [63]. # 1986 by IEEE.)

The quasi-TEM mode analysis presented above is valid only at frequencies which satisfy both f  f1 and f  f2 , where f1 ¼ f2 ¼

1 psS m0 ðW þ S=2Þ2 sS 2pe0 eS

ð1:11:16Þ ð1:11:17Þ

The contours of constant Q for the transmission line 2 are shown in Fig. 1.11.3. This figure shows that, at frequencies satisfying f  f1 and f  f2 , the mode of propagation is the ‘‘slow-wave’’ mode because, in this region, the magnetic field freely penetrates the substrate while the electric field does not. When f2 < f < f1 , both transverse electric and magnetic fields freely penetrate the semiconductor substrate and the ‘‘dielectric quasi-TEM’’ is the mode of propagation. On the other hand, when f1 < f < f2 , neither field penetrates the substrate and the mode of propagation is the ‘‘skin effect mode.’’ Using worstcase parameters for the four transmissions lines studied in this section, we can determine that f1 ¼ 120 GHz and f2 ¼ 12; 000 GHz. Therefore, all four lines satisfy the criteria for the slow-wave mode propagation and for validity of the quasi-TEM analysis.

1.11.2

Comparison with Experimental Results

The experimental results presented below are obtained by measuring the S parameters over the frequency range 1.0–12.4 GHz [63]. The attenuations of the

38

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.11.4 Dependence of attenuation on frequency for (a) line 1, (b) line 2, (c) line 3, and (d) line 4. Solid lines represent theoretical values obtained from quasi-TEM analysis. Symbols are experimental values. [63]. # 1986 by IEEE.)

four lines versus frequency are shown in Figs. 1.11.4a–d. Solid lines represent theoretical values obtained from the quasi-TEM analysis presented above. The real (Z00 ) and imaginary (Z000 ) parts of the characteristic impedance as functions of frequency for the four lines are shown in Figs. 1.11.5a–d. It can be seen that the characteristic impedances of all four lines are nearly real, of the order of 50 , and almost independent of frequency. The dependences of the ‘‘slowing factors’’ (l0 =lg ) on frequency for the four lines are shown in Figs. 1.11.6a–d, which also display the quality factor Q versus frequency. It can be seen that each of the four quality factors increases with frequency, reaching values in the range 3.6–4.3 at 12.4 GHz. It is obvious that there is excellent agreement between theory and experiments over the full frequency range from 1.0 to 12.4 GHz for all four transmission lines. It can be concluded from this close agreement that the slow-wave mode propagating on these micrometer-size MIS transmission lines is, in fact, a quasi-TEM mode and can therefore be analyzed by elementary techniques.

SLOW-WAVE MODE PROPAGATION

39

FIGURE 1.11.5 Dependence of real and imaginary parts of characteristic impedance on frequency for (a) line 1, (b) line 2, (c) line 3, and (d) line 4. Solid lines represent theoretical values obtained from quasi-TEM analysis. Symbols are experimental values. (From [63]. # by 1986 IEEE.)

In this analysis, we have included three loss mechanisms, namely metal loss, longitudinal semiconductor loss, and transverse semiconductor loss. It can be shown that the relative contribution of each loss mechanism in the above model can be approximately (within 1%) calculated by keeping the corresponding resistance in the circuit of Fig. 1.11.2 while setting the other two resistances to zero. The results for transmission line 2 are shown in Fig. 1.11.7. It can be seen that the metal loss contribution is dominant at frequencies below 25 GHz and decreases with increasing frequency though, even at 100 GHz, it accounts for nearly 20% of the total loss. It can also be noted that both the transverse and the longitudinal semiconductor losses increase with frequency though the transverse loss component is very small.

40

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.11.6 Dependence of quality and slow-wave factors on frequency for (a) line 1, (b) line 2, (c) line 3, and (d) line 4. Solid lines represent theoretical values obtained from quasi-TEM analysis. Symbols are experimental values. (From [63]. # 1986 by IEEE.)

FIGURE 1.11.7 Relative contributions of three loss mechanisms for transmission line 2. (From [63]. # 1986 by IEEE.)

EXERCISES

1.12

41

PROPAGATION DELAYS

In the literature, three measures of propagation delays in an electric circuit are defined [65]: Delay Time. The time required by the output signal (current or voltage) to reach 50% of its steady-state value. Rise Time. The time required by the output signal (current or voltage) to rise from 10 to 90% of its steady state value. Propagation Time. The time required by the output signal (current or voltage) to reach 90% of its steady-state value. EXERCISES E1.1 In the circuit shown below using an ideal voltage amplifier of gain 0.5, determine the input resistance Rin .

E1.2 In the circuit shown below using an ideal voltage amplifier of gain determine the input capacitance Cin .

10,

E1.3 Following the steps in Section 1.5, write the expressions for the even- and odd-mode capacitances for a system of four coupled conductors and solve them for the self and mutual capacitances for the four conductors. Comment on the accuracy of your results.

42

PRELIMINARY CONCEPTS AND MORE

E1.4 Following the steps in Section 1.5, write the expressions for the even- and odd-mode capacitances for a system of five coupled conductors and solve them for the self and mutual capacitances for the five conductors. Comment on the accuracy of your results. E1.5 Suggest situations where it will be preferable to model an interconnection as a lumped circuit or as a transmission line.

REFERENCES 1. R. M. Lum and J. K. Klingert, ‘‘Improvements in the Heteroepitaxy of GaAs on Si,’’ Appl. Phys. Lett., vol. 51, July 1987. 2. J. Varrio, H. Asonen, A. Salokatve, and M. Pessa, ‘‘New Approach to Growth of High Quality GaAs Layers on Si Substrates,’’ Appl. Phys. Lett., vol. 51, no. 22, Nov. 1987. 3. P. C. Zalm, C. W. T. Bulle-Lieuwma, and P. M. J. Maree, ‘‘Silicon Molecular Beam Epitaxy on GaP and GaAs,’’ Phillips Tech. Rev., vol. 43, May 1987. 4. N. Yokoyama, T. Ohnishi, H. Onodera, T. Shinoki, A. Shibatomi, and H. Ishikawa, ‘‘A GaAs 1K Static RAM Using Tungsten Silicide Gate Self-Aligned Technology,’’ IEEE J. Solid-State Circuits, Oct. 1983. 5. H. K. Choi, G. W. Turner, T. H. Windhorn, and B. Y. Tsaur, ‘‘Monolithic Integration of GaAs/AlGaAs Double-Heterostructure LED’s and Si MOSFET’s,’’ IEEE Electron Device Lett., Sept. 1986. 6. M. I. Aksun, H. Morkoc, L. F. Lester, K. H. G. Duh, P. M. Smith, P. C. Chao, M. Longerbone, and L. P. Erickson, ‘‘Performance of Quarter-Micron GaAs MOSFETs on Si Substrates,’’ Appl. Phys. Lett., vol. 49, Dec. 1986. 7. T. C. Chong and C. G. Fonstad, ‘‘Low-Threshold Operation of AlGaAs/GaAs Multiple Quantum Lasers Grown on Si Substrates by Molecular Beam Epitaxy,’’ Appl. Phys. Lett., vol. 27, July 1987. 8. W. Dobbelaere, D. Huang, M. S. Unlu, and H. Morkoc, ‘‘AlGaAs/GaAs Multiple Quantum Well Reflection Modulators Grown on Si Substrates,’’ Appl. Phys. Lett., July 1988. 9. W. T. Masselink, T. Henderson, J. Klem, R. Fischer, P. Pearah, H. Morkoc, M. Hafich, P. D. Wang and G. Y. Robinson, ‘‘Optical Properties of GaAs on (100) Si Using Molecular Beam Epitaxy,’’ Appl. Phys. Lett., vol. 45, no. 12, Dec. 1984. 10. J. B. Posthill, J. C. L. Tran, K. Das, T. P. Humphreys, and N. R. Parikh, ‘‘Observation of Antiphase Domains Boundaries in GaAs on Silicon by Transmission Electron Microscopy,’’ Appl. Phys. Lett., Sept. 1988. 11. R. Fischer, H. Morkoc, D. A. Neuman, H. Zabel, C. Choi, N. Otsuka, M. Longerbone, and L. P. Erickson, ‘‘Material Properties of High-Quality GaAs Epitaxial Layers Grown on Si Substrates,’’ J. Appl. Phys., vol. 60, no. 5, Sept. 1986. 12. L. T. Tran, J. W. Lee, H. Schichijo, and H. T. Yuan, ‘‘GaAs/AlGaAs Heterojunction Emitter-Down Bipolar Transistors Fabricated on GaAs-on-Si Substrate,’’ IEEE Electron Devices Lett., vol. EDL-8, no. 2, Feb. 1987. 13. N. El-masry, J. C. Tarn, T. P. Humphreys, N. Hamaguchi, N. H. Karam, and S. M. Bedair, ‘‘Effectiveness of Strained-Layer Superlattices in Reducing Defects in GaAs Epilayers Grown on Silicon Substrates,’’ Appl. Phys. Lett., vol. 51, no. 20, Nov. 1987.

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14. J. H. Kim, A. Nouhi, G. Radhakrishnan, J. K. Liu, R. J. Lang, and J. Katz, ‘‘High-Peak-Power Low-Threshold AlGaAs/GaAs Stripe Laser Diodes on Si Substrate Grown by Migration-Enhanced Molecular Beam Epitaxy,’’ Appl. Phys. Lett., Oct. 1988. 15. S. Sakai, S. S. Chang, R. V. Ramaswamy, J. H. Kim, G. Radhakrishnan, J. K. Liu, and J. Katz, ‘‘AlGaAs/AlGaAs Light-Emitting Diodes on GaAs-Coated Si Substrates Grown by Liquid Phase Epitaxy,’’ Appl. Phys. Lett., Sept. 26, 1988. 16. D. S. Gardner et al., ‘‘Layered and Homogeneous Films of Aluminum and Aluminum/ Silicon with Titanium and Tungsten for Multilevel Interconnects,’’ IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 174–183, Feb. 1985. 17. K. C. Saraswat and F. Mohammadi, ‘‘Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits,’’ IEEE Trans. Electron Devices, vol. ED-29, no. 4, p. 645, Apr. 1982. 18. M. H. Woods, ‘‘The Implications of Scaling on VLSI Reliability,’’ Seminar Notes from 22 Int. Reliability Physics Seminar. 19. E. Philofsky and E. L. Hall, ‘‘A Review of the Limitations of Aluminum Thin Films on Semiconductor Devices,’’ Trans. Parts Hybrids Packaging, vol. PHP-11, no. 4, p. 281, Dec. 1975. 20. R. A. Levy and M. L. Green. ‘‘Characterization of LPCVD Aluminum for VLSI Processing,’’ Proc. 1984 Symp. on VLSI Technology, The Japan Society of Applied Physics and the IEEE Electron Devices Society, p. 32, Sept. 1984. 21. K. C. Saraswat, S. Swirhun, and J. P. McVittie, ‘‘Selective CVD of Tungsten for VLSI Technology,’’ Proc. Symp. on VLSI Science and Technol., The Electrochemical Society, May 1984. 22. J. P. Roland, N. E. Handrickson, D. D. Kessler, D. E. Novy, Jr., and D. W. Quint, ‘‘TwoLayer Refractory Metal IC Process,’’ Hewlett-Packard J., vol. 34, no. 8, pp. 30–32, Aug. 1983. 23. D. L. Brors, K. A. Monnig, J. A. Fair, W. Coney and K. Saraswat, ‘‘CVD Tungsten—A Solution for the Poor Step Coverage and High Contact Resistance of Aluminum,’’ Solid State Technol., vol. 27, no. 4, p. 313, Apr. 1984. 24. F. M. d’Heurle, ‘‘The Effect of Copper Additions on Electromigration in Aluminum Thin Films,’’ Metallurg. Trans., vol. 2, pp. 693–689, Mar. 1971. 25. R. Rosenberg, M. J. Sullivan, and J. K. Howard, ‘‘Effect of Thin Film Interactions on Silicon Device Technology,’’ in Thin Films Interdiffusion and Reactions, J. M. Poeate, K. N. Tu, and J. W. Mayer, Eds., Electrochemical Society, New York: Wiley, 1978, pp. 48–54. 26. J. McBrayer, ‘‘Diffusion of Metals in Silicon Dioxide,’’ Ph. D. Dissertation, Stanford University, Stanford, CA, Dec. 1983. 27. J. K. Howard, J. F. White, and P. S. Ho, ‘‘Intermetallic Compounds of Al and Transitions Metals: Effect of Electromigration in 1–2 mm Wide Lines,’’ J. Appl. Phys., vol. 49, no. 7, p. 4083, July 1978. 28. S. S. Iyer and C. Y. Ting, ‘‘Electromigration study of the Al-Cu/Ti/Al-Cu Systems,’’ Proc. 1984 Int. Reliability Physics Symp., Apr. 1984. 29. J. P. Tardy and K. N. Tu, ‘‘Interdiffusion and Marker Analysis in Aluminum Titanium Thin Film Bilayers,’’ in Proceedings of the Electronic Materials Conference, T. C. Harman, Ed., Metallurgical Society of AIME, June 1984, p. 12.

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30. K. Hinode, S. Iwata, and M. Ogirima, ‘‘Electromigration Capacity and Microstructure of Layered Al/Ta Film Conductor,’’ Extended Abstr., Electrochem. Soc., vol. 83–1, p. 678, May 1983. 31. F. M. d’Heurle, A. Gangulee, C. F. Aliotta, and V. A. Ranieri, ‘‘Electromigration of Ni in Al Thin-Film Conductors,’’ J. Appl. Phys., vol. 46, no. 11, p. 4845, Nov. 1975. 32. F. M. d’Heurle and A. Gangulee, ‘‘Solute Effects on Grain Boundary Electromigration and Diffusion,’’ in The Nature and Behavior of Grain Boundaries, H. Hu, Ed., New York: Plenum, 1972, p. 339. 33. F. M. d’Heurle, A. Gangulee, C. F. Aliotta, and V. A. Ranieri, ‘‘Effects of Mg Additions on the Electromigration Behavior of Al Thin Film Conductors,’’ J. Electron. Mat., vol. 4, no. 3, p. 497, 1975. 34. F. Fishcher and F. Neppl, ‘‘Sputtered Ti-Doped Al-Si for Enhanced Interconnect Reliability,’’ Proc. 1984 Int. Reliability Physics Symp., IEEE Electron Devices and Reliability Societies, 1984. 35. C. J. Santoro, ‘‘Thermal Cycling and Surface Reconstruction in Aluminum Thin Films,’’ J. Electrochem. Soc., vol. 116, no. 3, p. 361, Mar. 1969. 36. K. C. Cadien and D. L. Losee, ‘‘A Method for Eliminating Hillocks in Integrated-Circuit Metallizations,’’ J. Vac. Sci. Technol., pp. 82–83, Jan.–Mar. 1984. 37. A. Rev, P. Noel, and P. Jeuch, ‘‘Influence of Temperature and Cu Doping on Hillock Formation in Thin Aluminum Film Deposited on Ti:W,’’ Proc. First Int. IEEE VLSI Multilevel Interconnection Conf., IEEE Electron Devices Society and Components, Hybrids, and Manufacturing Society, p. 139, June 1984. 38. P. B. Ghate and J. C. Blair, ‘‘Electromigration Testing of Ti:W/Al and Ti:W/Al-Cu Film Conductors,’’ Thin Solid Films, vol. 55, p. 113, Nov. 1978. 39. W. Barbee, Jr., in ‘‘Synthesis of Metastable Materials by Sputter Deposition Techniques,’’ in Synthesis and Properties of Metastable Phases, E. S. Machlin, and T. J. Rowland, Eds., The Metallurgical Society of AIME, Oct. 1980, p. 93. 40. T. W. Barbee, Jr., ‘‘Synthesis of Multilayer Structures by Physical Vapor Deposition Techniques,’’ in Multilayer Structures, G. Chang, Ed., New York: Academic, 1984. 41. W. Barbee, Jr., ‘‘Multilayers for X-ray Optical Applications,’’ in Springer Series in Optical Sciences, vol. 43: X-Ray Microscopy, G. Schmahl and D. Rudolph, Eds., Berlin, Heidelberg: Springer-Verlag, 1984, p. 144. 42. D. S. Gardner, T. L. Michalka, T. W. Barbee, Jr., K. C. Saraswat, J. P. McVittie, and J. D. Meindl, ‘‘Aluminum Alloys with Titanium, Tungsten, and Copper for Multilayer Interconnections,’’ Proc. 42nd Annual Device Res. Conf., The IEEE Electron Devices Society, p. IIB-3, June 1984. 43. D. S. Gardner, T. L. Michalka, T. W. Barbee, Jr., K. C. Saraswat, J. P. McVittie, and J. D. Meindl, ‘‘Aluminum Alloys with Titanium, Tungsten, and Copper for Multilayer Interconnections,’’ 1984 Proc. First Int. IEEE VLSI Multilevel Interconnection Conf., IEEE Electron Devices Society and Components, Hybrids, and Manufacturing Society, p. 68, June 1984. 44. D. S. Gardner, R. B. Beyers, T. L. Michalka, K. C. Saraswat, T. W. Barbee, Jr., and J. D. Meindl, ‘‘Layered and Homogeneous Films of Aluminum and Aluminum/Silicon with Titanium, Zirconium, and Tungsten for Multilevel Interconnects,’’ IEDM Tech. Dig., Dec. 1984.

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45. A. K. Goel, ‘‘Nanotechnology Circuit Design: The Interconnect Problem’’, Proc. IEEE NANO- 2001, Maui, Hawaii, Oct. 27–30, 2001. 46. J. W. Goodman, F. I. Leonberger, S. Y. Kung, and R. A. Athale, ‘‘Optical Interconnections for VLSI Systems,’’ Proc. IEEE, vol. 72, no. 7, pp. 850–866, July 1984. 47. L. D. Hutcheson, P. Haugen, and A. Hussain, ‘‘Optical Interconnects Replace Hardwire,’’ IEEE Spectrum, pp. 30–35, Mar. 1987. 48. J. W. Goodman, R. K. Kostuk, and B. Clymer, ‘‘Optical Interconnects: An Overview,’’ Proc. IEEE VLSI Multilevel Interconnection Conference, Santa Clara, CA, pp. 219–224, June 1985. 49. T. Bell, ‘‘Optical Computing: A Field in Flux,’’ IEEE Spectrum, Aug. 1986. 50. Special Issue on Optical Interconnections, Opt. Eng., Oct. 1986. 51. ‘‘Back to the Future: Copper Comes of Age.’’ Available: http://domino.research.ibm.com/ comm/wwwr_thinkresearch.nsf/pages/copper397.html. 52. ‘‘Meeting the Challenge of Making Semiconductor Chips with Copper Interconnects.’’ Available: http://www. ornl.gov/sci/nuclear_science_technology/cscp/rd/copper.htm. 53. R. F. Harrington, ‘‘Matrix Methods for Field Problems,’’ Proc. IEEE, vol. 55, no. 2, pp. 136–149, Feb. 1967. 54. L. V. Kantorovich and V. I. Krylov, Approximate Methods of Higher Analysis, 4th ed. translated by C. D. Benster, New York: Wiley, 1959, Chapter 4. 55. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, New York: Van Nostrand Reinhold, 1983, Chapter 10. 56. K. Singhal and J. Vlach, ‘‘Computation of Time Domain Response by Numerical Inversion of the Laplace Transform,’’ J. Franklin Inst., vol. 299, no. 2, pp. 109–126, Feb. 1975. 57. R. J. Antinone and G. W. Brown, ‘‘The Modeling of Resistive Interconnects for Integrated Circuits,’’ IEEE. J. Solid State Circuits, vol. SC-18, no. 2, pp. 200–203, Apr. 1983. 58. G. D. Mey, ‘‘A Comment on ‘The Modeling of Resistive Interconnects for Integrated Circuits,’’ IEEE J. Solid State Circuits, vol. SC-19, no. 4, pp. 542–543, Aug. 1984. 59. L. N. Dworsky, Modern Transmission Line Theory and Applications. New York: Wiley, 1979. 60. A. E. Ruehli and P. A. Brennan, ‘‘Accurate Metallization Capacitances for Integrated Circuits and Packages,’’ IEEE J. Solid State Circuits, vol. SC-8, pp. 289–290, Aug. 1973. 61. I. Gradshteyn and I. Ryzhik, Tables of Integrals, Series and Products, New York: Academic, 1980, p. 36. 62. H. Hasegawa and S. Seki, ‘‘Analysis of Interconnection Delay on Very High-Speed LSI/ VLSI Chips Using a MIS Microstrip Line Model,’’ IEEE Trans. Electron Devices, vol. ED-31, pp. 1954–1960, Dec. 1984. 63. Y. R. Kwon, V. M. Hietala, and K. S. Champlin, ‘‘Quasi-TEM Analysis of ‘Slow-Wave’ Mode Propagation on Coplanar Microstructure MIS Transmission Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-35, no. 6, pp. 545–551, June 1987. 64. K. C. Gupta, R. Garg, and I. J. Bahl, Microstrip Lines and Slotlines. Dedham, MA: Artech House, 1979. 65. H. E. Kallman and R. E. Spencer, ‘‘Transient Response,’’ Proc. IRE, vol. 33, pp. 169–195, 1945.

CHAPTER TWO

Parasitic Resistances, Capacitances, and Inductances An electrical interconnection is characterized by three parameters: resistance, capacitance, and inductance. Series resistance is an important parameter and can be rather easily determined by the material and dimensions of the interconnection. Parasitic capacitances and inductances associated with interconnections in the highdensity environment of ICs have become the primary factors in the evolution of the very high speed IC technology. This chapter is organized as follows:  A few general considerations regarding parasitic interconnection resistances are presented in Section 2.1.  A few general considerations regarding parasitic interconnection capacitances are presented in Section 2.2.  A few general considerations regarding parasitic interconnection inductances are presented in Section 2.3.  Approximate formulas for calculating the parasitic capacitances for a few interconnection structures are presented in Section 2.4.  An algorithm to obtain the interconnection capacitances by the Green’s function method which employs the method of moments in conjunction with a Green’s function appropriate for the geometry of the interconnections is presented in Section 2.5. The Green’s function is calculated using the method of multiple images.  Green’s function is calculated using the Fourier integral approach and a numerical technique to determine the capacitances for a multilevel interconnection structure on the Si–SiO2 composite is presented in Section 2.6.

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

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PARASITIC RESISTANCES: GENERAL CONSIDERATIONS

47

 An improved network analog method to determine the parasitic capacitances and inductances associated with the high-density multilevel interconnections on GaAs-based ICs is presented in Section 2.7.  A few simplified formulas for calculating the interconnection capacitances on oxide-passivated silicon and semi-insulating gallium arsenide substrates are given in Section 2.8.  A program called FastHenry for inductance extraction is discussed in Section 2.9.  A resistance model for copper interconnections is presented in Section 2.10.  In Section 2.11, the electrode parasitic capacitances in a GaAs metal– semiconductor field effect transistor (MESFET) have been determined by an application of the program IPCSGV developed earlier in the chapter.

2.1

PARASITIC RESISTANCES: GENERAL CONSIDERATIONS

Resistance is a material property by which the metal resists the flow of current. It is fairly easy to predict or calculate the resistance of a material once its dimensions are known. The following formula is used for the calculation of resistance for a slab of any conducting material: R¼r



L Wt



¼ RS

  L W

ð2:1:1Þ

where L ¼ length of slab W ¼ width of slab t ¼ thickness of slab r ¼ resistivity of slab’s material The parameter Rs is called the sheet resistance of the material and is measured in ohms per square. The sheet resistance of any metal is a function of its thickness and the resistivity of the material. The material resistivity is a function of the chemical composition of the material and the density of impurities in that material. The process of resistance extraction may be a fairly simple task. With prior knowledge of the interconnection layout of a circuit, any circuit simulator may be able to calculate the overall resistance with very little error. However, there are important considerations that need to be kept in mind for reducing and managing the onchip resistances: 1. The use of copper interconnections will certainly complicate the resistance calculation process. This is because, as discussed in Chapter 1 and shown in Fig. 2.1.1, it is necessary for copper to have a shielding metal to prevent it from poisoning the silicon substrate. The shield material is however not laid evenly as it is required to be thicker at some circuit locations than at others,

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FIGURE 2.1.1

Shielding layer in copper interconnection structure.

such as at contacts and vias. Accurate extraction must take this shield or seed layer into account. 2. When the frequency of operation is increased, metals display a phenomenon known as skin effect. Skin effect is a tendency for the alternating current to flow near the outer surface of a solid electrical conductor such as metal wire at frequencies above the audio range. The effect becomes more and more pronounced as the frequency is increased. The skin effect increases the effective resistance of a wire at moderate to high frequencies, as shown in Fig. 2.1.2. Skin effect becomes crucial only when the width and thickness of the conductor exceed twice the material’s skin depth. The skin effect must be modeled into the resistance extraction tools for the high-frequency circuits. 3. Full scaling, that is, reducing all dimensions of an interconnection, increases the metal’s sheet resistance mainly due to the reduction in its thickness. The only solution for this is to try and use selective scaling or keep the thickness constant. However, this makes the process of scaling more complex and would increase the fringe capacitances as well as the interwire capacitances.

FIGURE 2.1.2 Approximate frequency dependence of rise of interconnection resistance due skin effect.

PARASITIC RESISTANCES: GENERAL CONSIDERATIONS

49

Another option would be to find materials with lower sheet resistance such as copper or some silicides. 4. The resistance of local interconnections grows linearly with the scaling factor. This is more so with global interconnections which actually grow longer with the scaling process. One solution is to use multilevel interconnections, which tend to reduce the wire lengths and allow straight connections between interconnections on two levels. Another important consideration is to use thicker and wider upper layers for global interconnections. 5. It is also necessary to reduce the contact resistances by avoiding the use of an excessive number of contacts and vias by making larger holes. Making holes tends to encourage current crowding around the perimeters of the holes. 6. The current densities at different points in an interconnection may be different due to a phenomenon called electromigration, discussed in Chapter 5. This phenomenon refers to the transport of metal ions and molecules in a metal line due to a direct current running through it for long periods of time, especially under high-stress conditions such as high current densities and high temperature. Electromigration can cause the interconnection to break open or to short circuit with another neighboring interconnection. The formation of voids and hillocks due to electromigration can be observed using scanning electron microscopy of an interconnection line subjected to high currents for long periods of time. The growth of a void formed by electromigration in an interconnection line with time is shown schematically in Fig. 2.1.3. The rate of electromigration in an interconnection depends on various material properties such as crystal structure in addition to temperature and current density. Overall, electromigration is the result of a vicious cycle in the sense that

FIGURE 2.1.3

Growth of electromigration-induced void in interconnection line with time.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

high current density speeds up the electromigration process, which further increases current density due to an effective decrease of line width due to the formation of voids. This process also increases the overall resistance of the interconnection line.

2.2

PARASITIC CAPACITANCES: GENERAL CONSIDERATIONS

The dynamic response of a chip is a strong function of the capacitances associated with the transistors and gates in the circuit and the parasitic resistances and capacitances associated with the interconnection lines present in the circuit layout. Until the recent past, the circuit delay was mostly due to the transistor design characteristics and, for this reason, much effort has been put into the scaling of devices. At present, the propagation delays in an IC result primarily from the interconnection capacitances and the device and interconnection resistances. These are usually referred to as RC delays. An accurate model of the capacitances must include the contribution of the fringing fields as well as the shielding effects due to the presence of neighboring conductors. In the literature, several numerical techniques have been presented that can be used to characterize the interconnection lines though with limited applications. For example, the Schwarz–Christoffel conformal mapping technique [1] can be used to obtain exact results in terms of elliptic integrals for a symmetric two-strip conductor; for more than two strip conductors or for asymmetric two-strip conductors, the method becomes very cumbersome and significant results cannot be obtained. The technique employing Galerkin’s method [2] in the spectral domain uses a Fourier series which becomes quite complicated for mixed or inhomogenous dielectric multiconductor structures. The Green’s function integral equation technique [3] is suitable for conductors of rectangular or annular shapes but becomes extremely difficult for irregular geometric shapes. The finite-element method [4] and the finitedifference method [5] involve determination of the charge distributions on the conductor surfaces and can be applied to several conductor geometries. The network analog method, evolved from the finite-difference representation of partial differential equations [6], has been used for finite substrates in two dimensions [7], open substrates in three dimensions [8, 9], and lossy, anisotropic and layered structures [10–14]. In the past, capacitance models have been developed for IC metallization wires [15–17], and the system of equations for infinite printed conductors has been solved [18–20]. There has also been reported work on systems of conductors with finite dimensions [21–27]. According to the semiconductor industry association’s roadmap, the RC wiring delay will increase by over 900% from the 0.35- to the 0.l-mm-generation ICs. During the same time interval, gate delays are expected to drop from about 70 ps to about 20 ps while the clock period will reduce by nearly 70%. As the interconnection is scaled with each technology generation, several trade-offs are made. In order to reduce the interconnection resistance and improve its electromigration properties, the thickness of the metal is kept fairly constant, that is, it is not scaled with its pitch.

PARASITIC CAPACITANCES: GENERAL CONSIDERATIONS

51

FIGURE 2.2.1 Electric field lines that result in parallel-plate capacitance of interconnection line on silicon substrate (side view).

The increasing aspect ratio (thickness/width) results in larger coupling capacitances and more crosstalk among the interconnections (see Chapter 4 for a discussion of crosstalk). This problem worsens as the number of interconnection levels is increased with almost every new generation. It is obvious that interconnection capacitance characterization is an important aspect of current and future process development as well as circuit design. In order to give the circuit designers an accurate assessment of the speed and crosstalk issues, parasitic capacitances associated with interconnections must be understood very well. In general, there are three types of capacitances observed in an interconnection layout and all of these are important to the overall capacitance extraction. 2.2.1

Parallel-Plate Capacitance

It is known that most of the total interconnection capacitance is accounted for by parallel-plate capacitances though their relative contribution to the total capacitance decreases as the interconnection dimensions are scaled down. In silicon-based circuits, as shown in Fig. 2.2.1 the interconnection layout usually forms a parallelplate structure with the underlying silicon substrate separated by a dielectric layer usually made of silicon dioxide, and the parallel-plate capacitance is given by   WL ð2:2:1Þ CPP ¼ eox tox where L and W are the length and width of the interconnection line, respectively, whereas tox and eox are the thickness and dielectric constant of the oxide layer, respectively. For circuits built on a resistive substrate such as GaAs (which is several thousand times more resistive than silicon), an oxide layer is not required and tox and eox are replaced by the thickness and dielectric constant of the GaAs substrate itself. 2.2.2

Fringing Capacitances

For any parallel-plate interconnection structure, there are always electric field lines that emerge from the edges of the interconnection to form the so-called fringing

52

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.2.2

Fringing field lines of interconnection line on silicon substrate (side view).

fields as shown in Fig. 2.2.2. These fringing fields increase with the circumference and thickness of the interconnection line and add to the overall capacitance of an interconnection structure. Relative contribution of the fringing fields to the total interconnection capacitance increases as the interconnection dimensions are scaled down. 2.2.3

Coupling Capacitances

In an interconnection layout consisting of two or more interconnections, as shown in Fig. 2.2.3, there are eletric field lines and hence capacitances that exist among the interconnections. These capacitances that exist between any pair of interconnections are called coupling or mutual capacitances. These coupling capacitances are the major cause of crosstalk among the interconnections due to which the signal integrity is severely distorted due to an increase in noise.

2.3

PARASITIC INDUCTANCES: GENERAL CONSIDERATIONS

The CMOS and other circuits consist of both active and passive devices. Active devices are the transistors while passive devices are the interconnection structures that connect the transistors and gates in the circuit. These interconnections are mostly made of a metal such as aluminum and copper. In addition to its resistance, each interconnection has capacitances to the substrate and to the neighboring

FIGURE 2.2.3 Electric field lines resulting in coupling capacitances among interconnection lines on same level or different levels (side view).

PARASITIC INDUCTANCES: GENERAL CONSIDERATIONS

53

interconnections in the same level as well as to the interconnections in other levels. Furthermore, each interconnection also has self-inductance and mutual inductance caused by magnetic couplings of the interconnections. Until a few years ago, the gate parasitics of transistors were much larger than the interconnection parasitic impedances due to their relatively large sizes. The interconnection could be modeled as a short circuit and its impedance was ignored. Over the years, continuous scaling of the minimum gate feature size has increased the chip performance tremendously and reduced the cost of production. At the same time, it has reduced the gate capacitances, making the interconnection capacitances more comparable. Furthermore, decreasing cross-sectional areas and increasing lengths of the interconnection wires have significantly increased their resistances. The design methodologies used to reduce the time delays on the chip have concentrated on reducing the RC time constants of the interconnection lines. More recently, this has been achieved fairly successfully by replacing aluminum with copper as the interconnection material to reduce the line resistance, and breakthroughs in the use of ultra low-k dielectrics in the place of silicon dioxide have helped reduce the interconnection capacitance. So far, on-chip inductances have largely been ignored in the interconnection models. Currently ICs are designed for high clock frequencies with much faster signal rise and fall times. Considering the use of wider interconnections for power/ ground buses and with faster rise times, the on-chip inductances can no longer be ignored [28–32]. These inductances lead to several undesirable effects, such as increased ringing, increased crosstalk, and worse power/ground bounce. In order to optimize the circuit performance, it is important to understand the dependences of these inductances on the various interconnection design parameters. 2.3.1

Self and Mutual Inductances

Each interconnection line has an associated self-inductance as well as a mutual inductance with respect to each of the surrounding interconnection lines. Both self and mutual inductances are loop quantities and can be determined only if the current loop is known exactly. The self-inductance of a loop is defined as the ratio of the magnetic flux passing through the loop to the value of the loop current. The mutual or coupling inductance of a (victim) loop with respect to another (aggressor) loop is defined as the ratio of the magnetic flux passing through the victim loop caused by the current in the aggressor loop to the aggressor current. These magnetic fluxes that give rise to the self and mutual inductances are shown in Fig. 2.3.1. The magnetic interactions that takes place among the current-carrying conductors can be decomposed into three effects that take place concurrently: 1. Currents flowing through conductors create magnetic fields (Ampere’ law).

54

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.3.1 Magnetic fields that result in self and mutual inductances for two coupled loops.

2. Time-varying magnetic fields create induced electric fields (Faraday’ law). 3. Induced electric fields exert forces on the electrons in the conductors and cause electric voltage drops. These three effects may be combined to state that a voltage drop is produced in the victim loop b due to a time-variant current flowing in a loop a as shown in Fig. 2.3.2. It can be shown that the resulting induced voltage in loop b is given by

Vb ¼ Lba

  dIa dt

ð2:3:1Þ

where Lba is the mutual inductance between loops a and b and Ia is the current flowing through loop a. For the special case where loops a and b are the same, the coefficient Laa becomes the self-inductance of loop a.

FIGURE 2.3.2

Voltage induced in loop b by time-variant current in loop a.

PARASITIC INDUCTANCES: GENERAL CONSIDERATIONS

2.3.2

55

Partial Inductances

Calculation of the loop inductances for large-scale ICs can prove to be cumbersome and uneconomical in several ways. Two most significant problems in the calculations are as follows: 1. Need to know the current loops, that is, the return paths of the currents a priori, especially since these return paths have not been defined in the VLSI circuits. 2. The fact that a current can take several return paths. To overcome these problems, the concept of partial inductances was developed by Rosa and was introduced to the circuit-modeling and analysis community by Ruehli. Since the actual current loops are not known, partial inductance is defined in terms of the magnetic flux created by the current of one aggressor segment through the virtual loop that the victim segment forms with infinity, as shown in Fig. 2.3.3. It can be shown that the total self and mutual loop inductances are equivalent to the sums of the partial self and mutual inductances of the segments that form all the loops in the system. In other words, the relationship between the loop and partial inductances is given by Lab;loop ¼

XX i

sij Lij;partial

j

ð2:3:2Þ

where i and j represent segments of loops a and b, respectively. In Eq. (2.3.2), the coefficients sij are 1 if one of the currents in segments i and j is flowing opposite to the direction assumed when the coupling partial inductance Lij;partial was computed and is þ1 otherwise. Thus, by defining each current segment as forming its own return loop with infinity, partial inductances are used to represent the total loop interactions without prior knowledge of the actual current loops. 2.3.3

Methods for Inductance Extraction

Over the years, several models have been developed to calculate the self and mutual inductances. All models make a trade-off between computational efficiency and

FIGURE 2.3.3

Illustration of partial inductances.

56

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

accuracy and choose between specific two-dimensional (2D) models versus the general three-dimensional (3D) inductance models. Advocates of the 2D models insist that the return currents are equal and opposite to the interconnection currents and the inductances can therefore be extracted by using simpler 2D models which greatly limit the complexity of the problem by using several approximations and hence are more computer efficient though less accurate. The users of the 2D models assert that the sensitivity of a signal waveform is rather low to errors in the inductance values, particularly for the propagation delay and rise time analyses. It is claimed that the errors in propagation delay and rise times are below 9.4 and 5.9%, respectively, assuming a 30% relative error in the extracted inductance values and that this level of error may be acceptable when compared to the corresponding errors of 51 and 71% in propagation delay and rise times when using an RC model, that is, without using the inductances at all. On the other hand, the 3D model advocates claim that the return current paths in ICs are fundamentally unknown and employ sophisticated analysis methods to cope with the increased complexity of these models which are more accurate though less computer efficient. The biggest advantage of 3D modeling techniques lies in the fact that they provide a way to go around the need to know the current return paths a priori. The 3D field solvers employ finite-difference or finite-element methods to the governing Maxwell equations which represent one of the most elegant and concise ways to state the fundamentals of electricity and magnetism. Starting from the Maxwell equations, one can develop the working relationships in terms of the electric and magnetic fields or the current density distributions in a complex IC interconnection layout. This approach generates a global 3D mesh for all parts of the interconnection structure and the surrounding space, causing the number of unknowns to increase dramatically. There are many commercially available 3D field solvers for inductance extraction in the market. The exact analysis and extraction methods employed in these solvers may vary widely, but the underlying principles are almost always based on the steps mentioned above.

FIGURE 2.3.4 Dependence of propagation delays on interconnection lengths in range 50 nm–10 mm using RC and RLC delay models [33].

APPROXIMATE FORMULAS FOR CAPACITANCES

57

FIGURE 2.3.5 Dependence of propagation delays on interconnection widths in range 50 nm–1 mm using RC and RLC delay models [33].

2.3.4

Effect of Inductances on Interconnection Delays

The relative effects of including inductances in the interconnection delay models have been studied recently for a system of five single-level interconnections [33]. Propagation delays obtained by using the approximate RC and RLC models have been compared as functions of the interconnection lengths, interconnection widths, and interconnection separations, as shown in Figs. 2.3.4, 2.3.5, and 2.3.6, respectively. It is clear from these figures that the RLC delays significantly exceed the RC delays in all cases. These results further demonstrate the importance of including on-chip inductances in the chip design models. 2.4

APPROXIMATE FORMULAS FOR CAPACITANCES

In order to accurately determine the interconnection capacitances on the VLSI circuits, 2D and 3D effects must be taken into account. This requires rigorous

FIGURE 2.3.6 Dependence of propagation delays on interconnection separations in range 50 nm–1.25 mm using RC and RLC delay models [33].

58

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.4.1 Schematic of (a) single line on conducting ground plane, (b) two lines on ground plane, (c) three lines on ground plane, and (d) single plate of finite dimensions on ground plane. (From [23]. # 1983 by IEEE.)

numerical analysis which can be too time consuming when used in the computeraided design (CAD) programs. Therefore, approximate formulas to estimate the interconnection capacitances are sometimes desirable. This section presents such empirical formulas suggested by Sakurai and Tamaru [23] for a few interconnection structures. 2.4.1

Single Line on a Ground Plane

A schematic of a single interconnection line placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1a. The capacitance C1 per unit length in terms of the various dimensions shown in Fig. 2.4.1a can be estimated from the approximate formula C1 ¼ eox

"

   0:222 # W T þ 2:80 1:15 H H

ð2:4:1Þ

where eox is the dielectric constant of the insulator such as SiO2 for which eox ¼ 3:9  8:855  10 14 F=cm. The relative error of formula (2.4.1) is within 6% for 0:3 < W=H < 30 and 0:3 < T=H < 30. 2.4.2

Two Lines on a Ground Plane

A schematic of two interconnection lines placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1b. In this case, the total capacitance C2 of one line per unit length includes the ground capacitance C10 and the coupling

APPROXIMATE FORMULAS FOR CAPACITANCES

59

capacitance C12 between the lines, that is, C2 ¼ C10 þ C12 . In terms of the various dimensions shown in Fig. 2.4.1b, C2 can be estimated from the approximate formula C2 ¼ C1 þ eox

"

    W T þ 0:83 0:03 H H

 0:222 #  T S 0:07 H H

1:34

ð2:4:2Þ

The relative error of formula (2.4.2) is less than 10% for 0:3 < W=H < 10, 0:3 < T=H < 10, and 0:5 < S=H < 10. It should be noted that formula (2.4.2) tends to the single-line formula (2.4.1) as the line separation S approaches infinity. 2.4.3

Three Lines on a Ground Plane

A schematic of three interconnection lines placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1c. In this case, the total capacitance of one line includes the ground capacitance C20 and the coupling capacitance C21 between the lines. For example, the total capacitance C3 of the middle line per unit length is equal to C20 þ 2C21 . In terms of the various dimensions shown in Fig. 2.4.1c, C3 can be estimated from the approximate formula C3 ¼ C1 þ 2eox

"

    W T 0:03 þ 0:83 H H

 0:222 #  T S 0:07 H H

1:34

ð2:4:3Þ

The relative error of formula (2.4.3) is less than 10% for 0:3 < W=H < 10, 0:3 < T=H < 10, and 0:5 < S=H < 10. It should be noted that formula (2.4.3) tends to the single-line formula (2.4.1) as the line separation S approaches infinity.

2.4.4

Single Plate with Finite Dimensions on a Ground Plane

A schematic of a single plate with finite dimensions placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1d. In this case, the capacitance Cp between the plate and the ground includes the 3D effects. In terms of the various dimension parameters shown in Fig. 2.4.1d, Cp can be estimated from the approximate formula Cp ¼ eox

"

   0:222  0:728 # plate area T T 1:15 ðplate circumferenceÞþ4:12 H þ1:40 H H H ð2:4:4Þ

Compared to the data published by Ruehli et al. [17], the relative error of formula (2.4.4) is within 10% for 0 < W=L < 1, 0:5 < W=H < 40, and 0:4 < T=H < 10. It should be noted that formula (2.4.4) tends to formula (2.4.1) as the plate length approaches infinity.

60

2.5

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

In this section, the parasitic capacitances for a system of closely spaced conducting interconnection lines printed on the GaAs substrate which in turn is placed on a conducting ground plane are determined by using the method of moments [34] in conjunction with a Green’s function appropriate for the geometry of the interconnections. The Green’s function is obtained by using the method of multiple images [3, 35]. It is assumed that the interconnections are of negligible thickness. 2.5.1

Green’s Function Matrix for Interconnections Printed on Substrate

The Green’s function is a solution of a partial differential equation for a unit charge and with specified boundary conditions. To find the Green’s function, the first step is to determine the potential due to the source charge everywhere in the region of interest. In this section, the problem will be solved in two dimensions and then it will be extended to the 3D case in the next section. Consider the case of charged interconnections printed on a dielectric substrate which in turn is placed on a conducting ground plane as shown in Fig. 2.5.1. Obviously, there are more than one interface and we need to consider the formation of image charges about the dielectric interface and about the ground plane by a process known as multiple imaging. Each image of the real charge also images across all other interfaces. For example, the real charge r will form an image across the dielectric interface as rðe1 e2 Þ=ðe1 þ e2 Þ. This image will then form another image about the bottom ground plane as ð rÞðe1 e2 Þ=ðe1 þ e2 Þ. This new image will in turn image back across the dielectric interface with its magnitude changed by a factor of ðe2 e1 Þ=ðe1 þ e2 Þ, and so on. Also, the real charge will image about the bottom ground plane as r. This image charge itself will image back across the

FIGURE 2.5.1 Schematic of few interconnections printed on top of substrate, which in turn is placed on conducting ground plane.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

61

FIGURE 2.5.2 Magnitudes and locations of images formed when line charge r lies in medium of dielectric constant e0 above medium of dielectric constant e with conducting ground plane under it.

dielectric interface modified by a factor of ðe2 e1 Þ=ðe1 þ e2 Þ. This process will continue to infinity and produce an infinite number of image charges. For the 2D case of a line charge r lying in a medium of dielectric constant e0 above a medium of dielectric constant e with a conducting ground plane under it, the magnitudes and locations of a number of images are shown in Fig. 2.5.2. First, the real charge reflects across the dielectric interface. Then both the real charge and this first image reflect across the ground plane changing in sign. These two new images then reflect back across the dielectric interface changing by a factor k where k¼

e e0 e þ e0

and the process continues to infinity. Now, the potential at any field point ðxi ; yi Þ due to a line charge r at the location ðxj ; yj Þ can be determined. In general, if r is the distance from the source charge to the field point, then Vðxi ; yi Þ ¼

r lnðr 2 Þ 4pe0

62

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

However, the distance between the source charge and the field point will be different for each image, that is, the potential due to the nth image is given by r lnðrn2 Þ 4pe0

Vn ðxi ; yi Þ ¼

and the total potential at the field point is given by Vðxi ; yi Þ ¼

1 X

Vn

n¼1

Therefore, it follows from Fig. 2.5.2 that, for yi  T and yj  T, Vðxi ; yi Þ ¼

r f 4pe0

xj Þ2 þ ðyi

ln½ðxi

yj Þ2 Š

xj Þ2 þ ðyi

þ k ln½ðxi

xj Þ2 þ ðyi

k2 ln½ðxi

yj yj

xj Þ2 þ ðyi þ yj

þ k ln½ðxi

xj Þ2 þ ðyi þ yj

k2 ln½ðxi

xj Þ2 þ ðyi þ yj

þ k3 ln½ðxi

xj Þ2 þ ðyi

k ln½ðxi

xj Þ2 þ ðyi

þ k2 ln½ðxi

k3 ln½ðxi

xj Þ2 þ ðyi

2TÞ2 Š

4TÞ2 Š þ




2TÞ2 Š

4TÞ2 Š

6TÞ2 Š þ




yj þ 2TÞ2 Š

yj þ 4TÞ2 Š

yj þ 6TÞ2 Š þ




xj Þ2 þ ðyi þ yj Þ2 Š

þ ln½ðxi k ln½ðxi þ k2 ln½ðxi

xj Þ2 þ ðyi þ yj þ 2TÞ2 Š

xj Þ2 þ ðyi þ yj þ 4TÞ2 Š þ


g

ð2:5:1Þ

The Green’s function Gðxi ; yi ; xj ; yj Þ for the real charge at ðxj ; yj Þ and the field point at ðxi ; yi Þ can now be determined from Eq. (2.5.1) by setting r ¼ 1. Therefore

Gðxi ; yi ; xj ; yj Þ ¼

1 1 X ðð 1Þn kn 4pe0 n¼1

1

lnfðxi

þ ð 1Þnþ1 kn ln½ðxi ð 1Þnþ1 kn ln½ðxi

ð 1Þn kn

1

lnfðxi

xj Þ2 þ ½yi

2ðn

yj

xj Þ2 þ ðyi þ yj

xj Þ2 þ ðyi

1ÞTŠ2 g

2nTÞ2 Š

yj þ 2nTÞ2 Š

xj Þ2 þ ½yi þ yj þ 2ðn

1ÞTŠ2 gÞ

ð2:5:2Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

63

If all the interconnections are printed in the same plane on the substrate, then yi ¼ yj ¼ T. Then Eq. (2.5.2) becomes Gðxi ; T; xj ; TÞ ¼

1 1 X ðð 1Þn kn 4pe0 n¼1

1

xj Þ2 þ ½2ðn

lnfðxi

xj Þ2 þ ½2ðn

þ ð 1Þnþ1 kn lnfðxi

xj Þ2 þ ð2nTÞ2 Š

ð 1Þnþ1 kn ln½ðxi ð 1Þn kn

1

1ÞTŠ2 g 1ÞTŠ2 g

xj Þ2 þ ð2nTÞ2 ŠÞ

ln½ðxi

or Gðxi ; T; xj ; TÞ ¼

1 1 X ð½ð 1Þn kn 4pe0 n¼1

1

þ ð 1Þnþ1 kn Š lnfðxi

xj Þ2 þ ½2ðn

½ð 1Þnþ1 kn þ ð 1Þn kn 1 Š ln½ðxi

1ÞTŠ2 g

xj Þ2 þ ð2nTÞ2 ŠÞ

or Gðxi ; T; xj ; TÞ ¼



X 1 1 ð1 4pe0 n¼1

kÞ½ð 1Þnþ1 kn 1 Š

 ðlnfðxi ln½ðxi

xj Þ2 þ ½2ðn

1ÞTŠ2 g

xj Þ2 þ ð2nTÞ2 ŠÞ

Since 1

k¼1

e e0 2e0 ¼ e þ e0 e þ e0

Therefore Gðxi ; T; xj ; TÞ ¼

1 X 1 ½ð 1Þnþ1 kn 1 Š 2pðe þ e0 Þ n¼1

 ðln½ðxi lnfðxi

xj Þ2 þ ð2nTÞ2 Š

xj Þ2 þ ½2ðn

1ÞTŠ2 gÞ

We can rewrite this expression for the 2D Green’s function element as Gðxi ; T; xj ; TÞ ¼

1 X n¼1

An ½gijn1

gijn2 Š

where An ¼

1 ½ð 1Þnþ1 kn 1 Š 2pðe þ e0 Þ

ð2:5:3Þ

64

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

gijn1 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2nT from the field point, and gijn2 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2ðn 1ÞT from the field point. Now, we can extend Eq. (2.5.3) to the case when the charge is limited to a finite length and a finite width. First, we need to find the expression for the free-space potential due to a charge in three dimensions. Consider a conductor on the surface of a dielectric which is divided into a large number of rectangular subsections. Consider a subsection of length
xj , width
yj , and area
sj located at the source point ðxj ; yj ; zj Þ. For this rectangular subsection in free space (i.e., without the dielectric present) the potential at a field point ðxi ; yi ; zi Þ can be determined by integration over the surface of the subsection, that is, for a unit charge density,

1 Vðxi ; yi ; zi Þ ¼ 4pe0

Zx2 Zy2

x1

y1

1 ½ðxi

2

xj Þ þ ðyi

yj Þ2 þ ðzi

zj Þ2 Š1=2

dx dy

where x1 ¼ xj

1 2
xj

x2 ¼ xj þ 12
xj

y1 ¼ yj

1 2
yj

y2 ¼ yj þ 12
yj

After the integration is performed, we get  1 ðxj Vðxi ; yi ; zi Þ ¼ 4pe0

  ðc þ A1 Þðd þ B1 Þ xi Þ ln ðd þ C1 Þðc þ D1 Þ    
xj ðd þ B1 Þðd þ C1 Þ þ ln ðc þ D1 Þðc þ A1 Þ 2   ða þ A1 Þðb þ B1 Þ þ ðyj yi Þ ln ðb þ D1 Þða þ C1 Þ   
yj ðb þ B1 Þðb þ D1 Þ þ ln 2 ða þ C1 Þða þ A1 Þ      ac bd þ atan h atan hA1 hB1      ad bc þ h atan þ atan hC1 hD1

ð2:5:4Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

65

where h ¼ zj

zi

a ¼ xj

xi

c ¼ yj yi 12
yj pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A1 ¼ a 2 þ c 2 þ h2 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi C1 ¼ a2 þ d 2 þ h2

1 2
xj

b ¼ xj

xi þ 12
xj

d ¼ yj yi þ 12
yj pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi B 1 ¼ b2 þ d 2 þ h 2 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi D1 ¼ b2 þ c2 þ h2

Extension of Eq. (2.5.3) to the three dimensions is accomplished by multiplying this equation by 4pe0, by replacing the term gijn1 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2nT from the field point, and by replacing the term gijn2 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2ðn 1ÞT from the field point. The new expressions for gijn1 and gijn2 will become    1 ðc þ A2 Þðd þ B2 Þ gijn1 ¼ ðxj xi Þ ln 4pe0 ðd þ C2 Þðc þ D2 Þ    
xj ðd þ B2 Þðd þ C2 Þ þ ln 2 ðc þ D2 Þðc þ A2 Þ   ða þ A2 Þðb þ B2 Þ þ ðyj yi Þ ln ðb þ D2 Þða þ C2 Þ    
yj ðb þ B2 Þðb þ D2 Þ þ ln 2 ða þ C2 Þða þ A2 Þ      ac bd 2 nT atan þ atan 2nTA2 2nTB2      ad bc þ 2 nT atan þ atan ð2:5:5Þ 2nTC2 2nTD2 where qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2 ¼ a2 þ c2 þ ð2nTÞ2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi C2 ¼ a2 þ d 2 þ ð2nTÞ2

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi B2 ¼ b2 þ d 2 þ ð2nTÞ2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi D2 ¼ b2 þ c2 þ ð2nTÞ2

and gijn2 ¼

      ðc þ A3 Þðd þ B3 Þ
xj ðd þ B3 Þðd þ C3 Þ ln þ xi Þ ln 2 ðd þ C3 Þðc þ D3 Þ ðc þ D3 Þðc þ A3 Þ       ða þ A3 Þðb þ B3 Þ
yj ðb þ B3 Þðb þ D3 Þ þ ðyj yi Þ ln ln þ 2 ðb þ D3 Þða þ C3 Þ ða þ C3 Þða þ A3 Þ      ac bd 2ðn 1ÞT atan þ atan 2ðn 1ÞTA3 2ðn 1ÞTB3      ad bc þ 2ðn 1ÞT atan þ atan ð2:5:6Þ 2ðn 1ÞTC3 2ðn 1ÞTD3

 1 ðxj 4pe0

66

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where A3 ¼ C3 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a2 þ c2 þ ð2ðn 1ÞTÞ2

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a2 þ d2 þ ð2ðn 1ÞTÞ2

B3 ¼ D3 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b2 þ d 2 þ ð2ðn 1ÞTÞ2

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b2 þ c2 þ ð2ðn 1ÞTÞ2

Substituting for gijn1 and gijn2 from Eqs. (2.5.5) and (2.5.6) in Eq. (2.5.3) and multiplying by the factor 4pe0 and simplifying, we get for the Green’s function element in three dimensions Gij ¼ Gðxi ; T; xj ; TÞ ¼

1 X 1 ð 1Þnþ1 kn 1 ðT1 þ T2 þ T3 þ T4 2pðe þ e0 Þ n¼1

T5 þ T6 þ T7

T8 Þ ð2:5:7Þ

where T1 ¼ ðxj T2 ¼

xi Þ ln



ðc þ A3 Þðd þ B3 Þðd þ C2 Þðc þ D2 Þ ðd þ C3 Þðc þ D3 Þðc þ A2 Þðd þ B2 Þ



   
xj ðd þ B3 Þðd þ C3 Þðc þ D2 Þðc þ A2 Þ ln ðc þ D3 Þðc þ A3 Þðd þ B2 Þðd þ C2 Þ 2

T3 ¼ ðyj



ða þ A3 Þðb þ B3 Þðb þ D2 Þða þ C2 Þ yi Þ ln ðb þ D3 Þða þ C3 Þða þ A2 Þðb þ B2 Þ



   
yj ðb þ B3 Þðb þ D3 Þða þ C2 Þða þ A2 Þ ln T4 ¼ 2 ða þ C3 Þða þ A3 Þðb þ B2 Þðb þ D2 Þ T5 ¼ 2ðn

  1ÞT atan

ac 2ðn 1ÞTA3



þ atan

T6 ¼ 2ðn

  1ÞT atan

ad 2ðn 1ÞTC3



þ atan

     ac bd þ atan T7 ¼ 2nT atan 2nTA2 2nTB2      ad bc þ atan T8 ¼ 2nT atan 2nTC2 2nTD2 and T is the substrate thickness.



bd 2ðn 1ÞTB3





bc 2ðn 1ÞTD3



GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

2.5.2

67

Green’s Function Matrix for Interconnections Embedded in Substrate

If all the interconnections are embedded in the substrate, then their heights above the bottom ground plane denoted by H will be less than the thickness of the substrate denoted by T. First, as in the previous section, the Green’s function for a line charge r in two dimensions will be found by using the method of images and, next, the expression for the Green’s function will be extended to the 3D case. The results can be checked for accuracy by reducing them to the case when the interconnections are printed on the substrate by setting H ¼ T and ensuring that the resulting expression for the Green’s function agrees with Eq. (2.5.7). First, we find the magnitudes and locations of the image charges when a real line charge is placed at a height HðH < TÞ above the bottom ground plane. The real charge will first reflect up across the dielectric interface and give rise to an image charge equal to kr. This first image and the real charge will then both reflect across the ground plane changing in signs. These two new images will then reflect back across the dielectric interface and so on. The process will continue to infinity giving rise to the images shown in Fig. 2.5.3. To find the potential at a point ðxi ; yi Þ inside the dielectric, we need to find the sum of all the potentials at this point due to the real charge and all its image charges, that is,   1 X r lnðrn2 Þ Vn ¼ Vðxi ; yi Þ ¼ 4pe 0 n¼1

FIGURE 2.5.3 Magnitudes and locations of images formed when line charge r is embedded in medium of dielectric constant e with conducting ground plane under it and surrounded by another medium of dielectric constant e0 .

68

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where e ¼ e0 er . It follows from Fig. 2.5.3 that, for yi  T and yj  T, r f ln½ðxi xj Þ2 þ ðyi HÞ2 Š Vðxi ; yi Þ ¼ 4pe þ k ln½ðxi xj Þ2 þ ðyi H 2TÞ2 Š xj Þ2 þ ðyi

k2 ln½ðxi

xj Þ2 þ ðyi þ H

k ln½ðxi

2TÞ2 Š

xj Þ2 þ ðyi þ H

þ k2 ln½ðxi

xj Þ2 þ ðyi þ H

k3 ln½ðxi

þ ln½ðxi

4TÞ2 Š þ




H

4TÞ2 Š

xj Þ2 þ ðyi þ HÞ2 Š

k ln½ðxi þ k2 ln½ðxi þ k ln½ðxi

k2 ln½ðxi

6TÞ2 Š þ




xj Þ2 þ ðyi þ H þ 2TÞ2 Š

xj Þ2 þ ðyi þ H þ 4TÞ2 Š þ




xj Þ2 þ ðyi

H þ 2TÞ2 Š

xj Þ2 þ ðyi

H þ 4TÞ2 Š

xj Þ2 þ ðyi

þ k3 ln½ðxi

H þ 6TÞ2 Š þ


g

ð2:5:8Þ

The Green’s function Gðxi ; yi ; xj ; yj Þ for the real charge at ðxj ; yj Þ and the field point at ðxi ; yi Þ can now be determined from Eq. (2.5.8) by setting r ¼ 1. Therefore Gðxi ; yi ; xj ; yj Þ ¼

1 1 X ð ð 1Þnþ1 kn 4pe n¼1

1

lnfðxi

þ ð 1Þn kn ln½ðxi

ð 1Þn kn ln½ðxi ð 1Þnþ1 kn

1

xj Þ2 þ ½yi

xj Þ2 þ ðyi þ H xj Þ2 þ ðyi

lnfðxi

H

2ðn

1ÞTŠ2 g

2nTÞ2 Š

H þ 2nTÞ2 Š

xj Þ2 þ ½yi þ H þ 2ðn

1ÞTŠ2 gÞ

ð2:5:9Þ

If all the interconnections are in the same plane, then yi ¼ yj ¼ H and Eq. (2.5.9) becomes 1 1 X ðð 1Þn kn ln½ðxi xj Þ2 þ ð2H 2nTÞ2 Š Gðxi ; H; xj ; HÞ ¼ 4pe n¼1 ð 1Þn kn ln½ðxi

þ ð 1Þnþ1 kn

ð 1Þnþ1 kn

xj Þ2 þ ð2nTÞ2 Š

1

lnfðxi

1

lnfðxi

xj Þ2 þ ½2H þ 2ðn xj Þ2 þ ½2ðn

1ÞT 2 gÞ

We can rewrite this expression for the 2D Green’s function element as 1 X ½An ðgijn1 gijn2 Þ þ Bn ðgijn3 gijn4 ފ Gðxi ; H; xj ; HÞ ¼ n¼1

1ÞTŠ2 g

ð2:5:10Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

69

where An ¼ ð 1Þn kn

Bn ¼ ð 1Þnþ1 kn

1

gijn1 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2H 2nT from the field point, gijn2 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2nT from the field point, gijn3 is the freespace Green’s function for the nth image at a distance yj yi ¼ 2H þ 2ðn 1ÞT from the field point, and gijn4 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2ðn 1ÞT from the field point. Extension of Eq. (2.5.10) to the three dimensions is accomplished by replacing the term gijn1 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2H 2nT from the field point, replacing the term gijn2 by the freespace Green’s function for the nth image at a distance h ¼ zj zi ¼ 2nT from the field point, replacing the term gijn3 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2H 2ðn 1ÞT from the field point, and replacing the term gijn4 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2ðn 1ÞT from the field point. The new expressions for gijn1 , gijn2 , gijn3 , and gijn4 become        1 ðc þ A4 Þðd þ B4 Þ
xj ðd þ B4 Þðd þ C4 Þ gijn1 ¼ ln þ ðxj xi Þ ln 2 4pe ðd þ C4 Þðc þ D4 Þ ðc þ D4 Þðc þ A4 Þ       ða þ A4 Þðb þ B4 Þ
yj ðb þ B4 Þðb þ D4 Þ þ ðyj yi Þ ln ln þ 2 ðb þ D4 Þða þ C4 Þ ða þ C4 Þða þ A4 Þ      ac bd ð2H 2nTÞ atan þ atan ð2H 2nTÞA4 ð2H 2nTÞB4      ad bc þð2H 2nTÞ atan þ atan ð2H 2nTÞC4 ð2H 2nTÞD4

ð2:5:11Þ

where qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a2 þ c2 þ ð2H 2nTÞ2 B4 ¼ b2 þ d 2 þ ð2H 2nTÞ2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 2 C4 ¼ a þ d þ ð2H 2nTÞ D4 ¼ b2 þ c2 þ ð2H 2nTÞ2        1 ðc þ A5 Þðd þ B5 Þ
xj ðd þ B5 Þðd þ C5 Þ ln þ ðxj xi Þ ln ¼ 2 4pe ðd þ C5 Þðc þ D5 Þ ðc þ D5 ÞðC þ A5 Þ       ða þ A5 Þðb þ B5 Þ
yj ðb þ B5 Þðb þ D5 Þ þ ðyj yi Þ ln ln þ 2 ðb þ D5 Þða þ C5 Þ ða þ C5 Þða þ A5 Þ      ac bd 2nT atan þ atan 2nTA5 2nTB5      ad bc þ2nT atan þ atan ð2:5:12Þ 2nTC5 2nTD5 A4 ¼

gijn2

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where

gijn3

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 2 B5 ¼ b2 þ d 2 þ ð2nTÞ2 A5 ¼ a þ c þ ð2nTÞ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi D5 ¼ b2 þ c2 þ ð2nTÞ2 C5 ¼ a2 þ d 2 þ ð2nTÞ2    1 ðc þ A6 Þðd þ B6 Þ ðxj xi Þ ln ¼ 4pe ðd þ C6 Þðc þ D6 Þ      
xj ðd þ B6 Þðd þ C6 Þ ða þ A6 Þðb þ B6 Þ þ ln þ ðyj yi Þ ln 2 ðc þ D6 Þðc þ A6 Þ ðb þ D6 Þða þ C6 Þ    
yj ðb þ B6 Þðb þ D6 Þ þ ln ð2H þ 2ðn 1ÞTÞ 2 ða þ C6 Þða þ A6 Þ      ac bd  atan þ atan ½2H þ 2ðn 1ÞTŠA6 ½2H þ 2ðn 1ÞTŠB6    ad þ ½2H þ 2ðn 1ÞTŠ atan ½2H þ 2ðn 1ÞTŠC6   bc ð2:5:13Þ þ atan ½2H þ 2ðn 1ÞTŠD6

where A6 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a2 þ c2 þ ð2H þ 2ðn 1ÞTÞ2

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi C6 ¼ a2 þ d2 þ ð2H þ 2ðn 1ÞTÞ2

B6 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b2 þ d 2 þ ð2H þ 2ðn 1ÞTÞ2

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi D6 ¼ b2 þ c2 þ ð2H þ 2ðn 1ÞTÞ2

and gijn4

 1 ðxj ¼ 4pe

  ðc þ A7 Þðd þ B7 Þ xi Þ ln ðd þ C7 Þðc þ D7 Þ    
xj ðd þ B7 Þðd þ C7 Þ þ ln 2 ðc þ D7 Þðc þ A7 Þ   ða þ A7 Þðb þ B7 Þ þ ðyj yi Þ ln ðb þ D7 Þða þ C7 Þ    
yj ðb þ B7 Þðb þ D7 Þ þ ln 2 ða þ C7 Þða þ A7 Þ      ac bd 2ðn 1ÞT atan þ atan 2ðn 1ÞTA7 2ðn 1ÞTB7      ad bc þ 2ðn 1ÞT atan þ atan 2ðn 1ÞTC7 2ðn 1ÞTD7

ð2:5:14Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

71

where A7 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a2 þ c2 þ ½2ðn 1ÞTŠ2

B7 ¼

C7 ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a2 þ d 2 þ ð2ðn 1ÞT 2 Þ

D7 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b2 þ d2 þ ð2ðn 1ÞTÞ2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b2 þ c2 þ ð2ðn 1ÞTÞ2

Substituting for gijn1, gijn2 , gijn3 , and gijn4 from Eqs. (2.5.11)–(2.5.14) in Eq. (2.5.10) and simplifying, we get for the Green’s function element in three dimensions Gij ¼ Gðxi ; H; xj ; HÞ 1 1 X ¼ ð½ 1Šn 1 kn ½T9 þ T10 þ T11 þ T12 4pe n¼1

T13 þ T14 þ T15

þ ½ 1Šn kn 1 ½T17 þ T18 þ T19 þ T20

T16 Š

T21 þ T22 þ T23

T24 ŠÞ

ð2:5:15Þ

where   ðc þ A4 Þðd þ B4 Þðd þ C5 Þðc þ D5 Þ xi Þ ln ðd þ C4 Þðc þ D4 Þðc þ A5 Þðd þ B5 Þ    
xj ðd þ B4 Þðd þ C4 Þðc þ D5 Þðc þ A5 Þ ln ¼ 2 ðc þ D4 Þðc þ A4 Þðd þ B5 Þðd þ C5 Þ   ða þ A4 Þðb þ B4 Þðb þ D5 Þða þ C5 Þ ¼ ðyj yi Þ ln ðb þ D4 Þða þ C4 Þða þ A5 Þðb þ B5 Þ    
yj ðb þ B4 Þðb þ D4 Þða þ C5 Þða þ A5 Þ ln ¼ 2 ða þ C4 Þða þ A4 Þðb þ B5 Þðb þ D5 Þ      ac bd þ atan ¼ ð2H 2nTÞ atan ð2H 2nTÞA4 ð2H 2nTÞB4      ad bc þ atan ¼ ð2H 2nTÞ atan ð2H 2nTÞC4 ð2H 2nTÞD4      ac bd þ atan ¼ 2nT atan 2nTA5 2nTB5      ad bc þ atan ¼ 2nT atan 2nTC5 2nTD5   ðc þ A6 Þðd þ B6 Þðd þ C7 Þðc þ D7 Þ ¼ ðxj xi Þ ln ðd þ C6 Þðc þ D6 Þðc þ A7 Þðd þ B7 Þ

T9 ¼ ðxj T10

T11 T12 T13

T14 T15 T16

T17

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

   
xj ðd þ B6 Þðd þ C6 Þðc þ D7 Þðc þ A7 Þ ln 2 ðc þ D6 Þðc þ A6 Þðd þ B7 Þðd þ C7 Þ   ða þ A6 Þðb þ B6 Þðb þ D7 Þða þ C7 Þ ¼ ðyj yi Þ ln ðb þ D6 Þða þ C6 Þða þ A7 Þðb þ B7 Þ    
yj ðb þ B6 Þðb þ D6 Þða þ C7 Þða þ A7 Þ ln ¼ 2 ða þ C6 Þða þ A6 Þðb þ B7 Þðb þ D7 Þ      ac bd þ atan ¼ ½2H þ2ðn 1ÞTŠ atan ½2H þ 2ðn 1ÞTŠA6 ½2H þ 2ðn 1ÞTŠB6      ad bc þ atan ¼ ½2H þ2ðn 1ÞTŠ atan ½2H þ 2ðn 1ÞTŠC6 ½2H þ 2ðn 1ÞTŠD6      ac bd ¼ 2ðn 1ÞT atan þ atan 2ðn 1ÞTA7 2ðn 1ÞTB7      ad bc þ atan ¼ 2ðn 1ÞT atan 2ðn 1ÞTC7 2ðn 1ÞTD7

T18 ¼ T19 T20 T21 T22 T23 T24

2.5.3

Application of Method of Moments

The algorithm presented below is suitable for a system of four interconnection lines and can be easily modified for a different number of lines. For a system of four conducting lines, the known potential Vi on the ith ði ¼ 1; 2; 3; 4Þ conductor is related to the unknown surface charge density sj on each conductor by the following system of integral equations: Vi ¼

4 Z X j¼1

Sj

Gðxi ; yi ; xj ; yj ; zÞsj ðxj ; yj Þdxj dyj

where G is the Green’s function and Sj is the area of the jth conductor. If the conductors are divided into a total of N subsections with areas dsj , then the potential Vi of the ith subsection is given by Vi ¼

4 X

sj Gij

j¼1

where sj is now the unknown surface charge density of the jth subsection and Gij is the element of the Green’s function pertinent to the problem. If the subsections are made small enough so that the charge density can be assumed constant over the area of each subsection, then the method of moments can be used to convert this equation into its matrix form ½VŠ ¼ ½sj Š½GŠ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

73

Then, by matrix inversion, the unknown sj can be determined from ½sj Š ¼ ½GŠ 1 ½VŠ where ½sj Š and ½VŠ are two N-dimensional column matrices and ½GŠ is the N-dimensional square matrix. The total charge on the jth conductor is given by

Qj ¼

Nj X

sj dsj

j¼1

j ¼ 1; 2; 3; 4

where Nj is the number of subsections on the jth conductor. 2.5.4

Even- and Odd-Mode Capacitances

For the system of four interconnection lines, an even- and odd-mode excitation can be used to calculate the even- and odd-mode capacitances of each line separately. For the even-mode excitation, each line is assumed to be þ1 V potential with respect to the conducting ground plane. For the odd-mode excitation, one line is kept at þ1 V while the other three lines are kept at 1 V potential. This means that when finding the odd-mode charge on the first line, the potential on the first line is kept at þ1 V while the potentials on each of the second, third, and fourth lines are kept at 1 V, and so on. First, the four lines are divided into N1 , N2 , N3 , and N4 number of subsections. Thus, the total number of subsections becomes N ¼ N1 þ N2 þ N3 þ N4 Then, the voltage excitation for the even mode of each interconnection line is an N-row unit column matrix, that is,

½VŠeven

2 3 1 6 .. 7 6.7 6 7 617 6 7 617 6.7 .7 ¼6 6.7 617 6 7 617 6 7 6 .. 7 4.5 1

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

while the odd-mode excitation for the first line is represented by the matrix 3 1 .. 7 . 7 17 7 17 7 .. 7 .7 7 17 7 17 .. 7 7 .7 7 17 7 17 .. 7 .5

2

½VŠodd;1

6 6 6 6 6 6 6 6 6 6 ¼6 6 6 6 6 6 6 6 6 6 4

1

and similarly for ½VŠodd;2, ½VŠodd;3 , and ½VŠodd;4 . If the inverse of the Green’s function matrix is denoted by ½RŠ, then we can define the following 16 quantities by summing the ijth elements in the 16 submatrices of the matrix ½RŠ: R1 ¼

N1 N1 X X

R2 ¼

N1 NX 1 þN2 X

R3 ¼

N1 X

R4 ¼

N1 X

R5 ¼

NX 1 þN2

R6 ¼

Rij

i¼1 j¼1

Rij

i¼1 j¼N1 þ1 N1 þN 2 þN3 X

Rij

i¼1 j¼N1 þN2 þ1 N X

Rij

i¼1 j¼N1 þN2 þN3 þ1 N X

Rij

i¼N1 þ1 j¼1

NX 1 þN2 1 þN2 NX

i¼N1 þ1 j¼N1 þ1

Rij

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

R7 ¼ R8 ¼ R9 ¼ R10 ¼ R11 ¼ R12 ¼ R13 ¼ R14 ¼ R15 ¼ R16 ¼

NX 2 þN3 1 þN2 N1 þN X

75

Rij

i¼N1 þ1 j¼N1 þN2 þ1 NX 1 þN2

N X

Rij

i¼N1 þ1 j¼N1 þN2 þN3 þ1 N1 þN 2 þN3 X

N1 X

Rij

i¼N1 þN2 þ1 j¼1

N1 þN 2 þN3 NX 1 þN2 X

Rij

i¼N1 þN2 þ1 j¼N1 þ1 N1 þN 2 þN3 2 þN3 N1 þN X X

Rij

i¼N1 þN2 þ1 j¼N1 þN2 þ1 N1 þN 2 þN3 X

N X

Rij

i¼N1 þN2 þ1 j¼N1 þN2 þN3 þ1 N X

N1 X

N X

NX 1 þN2

N X

N1 þN 2 þN3 X

N X

N X

Rij

i¼N N4 þ1 j¼1

Rij

i¼N N4 þ1 j¼N1 þ1

Rij

i¼N N4 þ1 j¼N1 þN2 þ1

Rij

i¼N N4 þ1 j¼N N4 þ1

The even- and odd-mode capacitances for each of the four lines can be determined from the relations ðe;oÞ

Cj

¼

ðe;oÞ

Qj

ðe;oÞ

Vj

j ¼ 1; 2; 3; 4

Since ½sŠ ¼ ½GŠ 1 ½VŠ

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

the even- and odd-mode capacitances for the four lines can be expressed as C1e ¼ ðR1 þ R2 þ R3 þ R4 Þ
s1

C2e ¼ ðR5 þ R6 þ R7 þ R8 Þ
s2

C3e ¼ ðR9 þ R10 þ R11 þ R12 Þ
s3

C4e ¼ ðR13 þ R14 þ R15 þ R16 Þ
s4

C1o ¼ ðR1

C2o C3o C4o

2.5.5

¼ ðR6

¼ ðR11

¼ ðR16

R2

R3

R5

R7

R9 R13

R10 R14

R4 Þ
s1

R8 Þ
s2

R12 Þ
s3

R15 Þ
s4

Ground and Coupling Capacitances

The ground and coupling interconnection capacitances can be obtained by solving the following set of equations: C1e ¼ C11 C2e ¼ C22

C3e ¼ C33

C4e ¼ C44

C1o ¼ C11 þ 2C12 þ 2C13 þ 2C14

C2o C3o C4o

¼ C22 þ 2C12 þ 2C23 þ 2C24

ð2:5:16Þ

¼ C33 þ 2C13 þ 2C23 þ 2C34

¼ C44 þ 2C14 þ 2C24 þ 2C34

Since the number of unknowns is greater than the number of equations, Eqs. (2.5.16) cannot be solved exactly. One way is to use the method of unconstrained multivariable optimization to solve the equations. 2.5.6

The Program IPCSGV

The source code of a program called IPCSGV developed to determine the interconnection parasitic capacitances on the GaAs-based VLSI is presented in Appendix 2.1, which can be found at the ftp site: ftp://ftp.wiley.com/public/ sci_tech_med/high_speed_VLSI. It is based on the various calculation steps presented above and is written in FORTRAN. The program can be modified to include more interconnections though the relative precision of the results will be

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

77

affected. One can utilize the method of unconstrained multivariable optimization to solve Eqs. (2.5.16) for an interconnection configuration consisting of four interconnections, three on the top plane and one embedded in the substrate, as shown in Fig. 2.5.4.

2.5.7

Parametric Dependence of Interconnection Capacitances

The program IPCSGV can be used to study the dependences of the ground and coupling interconnection capacitances on the various interconnection parameters shown in Fig. 2.5.4. In the following results, one of the parameters is varied in a specific range while the others are kept fixed at their selected typical values. These typical values are chosen to be the following: interconnection lengths 100 mm each, widths 1 mm each, separations 2 mm, interlevel distances 2 mm, and thickness of GaAs substrate 200 mm. The dependences of the ground and coupling capacitances on the lengths of the bilevel interconnections are shown in Figs. 2.5.5 and 2.5.6, respectively. Figure 2.5.5 shows that C22 is always less than C11 and C33 . This is due to larger shielding of the electric field lines that constitute the capacitance C22 by those that constitute the capacitances C12 and C23 . This figure also shows that for the interconnection lengths above about 10 mm the ground capacitances vary almost linearly with length. Departure from linearity for smaller lengths is due to a more dominant role played by the fringing fields for smaller interconnection dimensions. The dependences of the ground and coupling capacitances on the widths of the interconnection lines are shown in Figs. 2.5.7 and 2.5.8, respectively. As functions of the interconnection separation, the ground and coupling capacitances are shown in Figs. 2.5.9 and 2.5.10, respectively. The dependences of the ground and coupling capacitances on the interlevel separation of the interconnection lines are shown in Figs. 2.5.11 and 2.5.12, respectively. As functions of the thickness of the GaAs substrate, the ground and coupling capacitances are shown in Figs. 2.5.13 and 2.5.14, respectively. Figures 2.5.15 and 2.5.16 show the effects of changing the relative angle of the

FIGURE 2.5.4 IPCSGV.

Schematic of four interconnections in bilevel configuration used in program

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.5.5 Dependence of ground capacitances for four bilevel interconnections on interconnection lengths.

FIGURE 2.5.6 Dependence of coupling capacitances for four bilevel interconnections on interconnection lengths.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

79

FIGURE 2.5.7 Dependence of ground capacitances for four bilevel interconnections on interconnection widths.

FIGURE 2.5.8 Dependence of coupling capacitances for four bilevel interconnections on interconnection widths.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.5.9 Dependence of ground capacitances for four bilevel interconnections on interconnection separations.

FIGURE 2.5.10 Dependence of coupling capacitances for four bilevel interconnections on interconnection separations.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

81

FIGURE 2.5.11 Dependence of ground capacitances for four bilevel interconnections on interlevel separation.

FIGURE 2.5.12 Dependence of coupling capacitances for four bilevel interconnections on interlevel separation.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.5.13 Dependence of ground capacitances for four bilevel interconnections on substrate thickness.

FIGURE 2.5.14 Dependence of coupling capacitances for four bilevel interconnections on substrate thickness.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

83

FIGURE 2.5.15 Dependence of ground capacitances for four bilevel interconnections on relative angle of fourth interconnection.

FIGURE 2.5.16 Dependence of coupling capacitances for four bilevel interconnections on relative angle of fourth interconnection.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

fourth line in the bilevel configuration on the various ground and coupling capacitances. Figure 2.5.16 shows that C14 , C24 , and C34 decrease sharply while C12 , C23 , and C13 increase when the angle is increased.

2.6

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

The parasitic capacitances for a system of multilevel conducting interconnections can also be determined by the Green’s function method obtained by the Fourier integral approach and by using a piecewise linear approximation for the charge density distributions [24] on the conducting interconnections. This method reduces the order of integration and the number of equations needed, thereby reducing the computation time and the memory required. In this section, the Green’s function for the Si–SiO2 system is derived by using the Fourier integral approach and the integral equations are solved for a multilevel interconnection structure using a piecewise linear approximation for the charge density distributions [24]. 2.6.1

Green’s Function for Multilevel Interconnections

A representation of three multilevel conducting interconnections in the Si–SiO2 composite is shown in Fig. 2.6.1. The solution of the Laplace equation governing the potentials on the conductors can be written as ðpÞ ¼

Z

Gðp; qÞsðqÞdq

all charge

ð2:6:1Þ

where sðqÞ is the charge density at point qðx0 ; y0 ; z0 Þ in Fig. 2.6.1 and Gðp; qÞ is the appropriate Green’s function describing the potential induced at point pðx; y; zÞ by a unit point charge at point qðx0 ; y0 ; z0 Þ. For a system of N conductors, the potential on the jth conductor is given by

j ðpÞ ¼

N Z X i¼1

Si

Gðp; qÞsi ðqÞdsi ðqÞ

j ¼ 1; 2; . . . ; N

ð2:6:2Þ

where si ðqÞ denotes the charge density on the surface Si of the ith conductor. The Green’s function Gðp; qÞ can be expressed as a Fourier integral [36] as Gðp; qÞ ¼

1 4pe1

Z

1 0

J0 ðmrÞe

mjz1 j

dm

ð2:6:3Þ

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

85

FIGURE 2.6.1 Representation of three multilevel interconnections in Si–SiO2 composite. (From [24]. # 1987 by IEEE.)

where e1 is the dielectric constant of SiO2, J0 is the Bessel function of first kind and zero order, m is the variable of integration, z1 ¼ z z0 , and r¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðx x0 Þ2 þ ðy y0 Þ2

The Green’s function in region 1 ð0 < z  dÞ shown in Fig. 2.6.1 can now be written as Z 1 1 J0 ðmrÞ½e mjz1 j þ 1 ðmÞemz1 þ 2 ðmÞe mz1 Šdm ð2:6:4Þ G1 ðp; qÞ ¼ 4pe1 0 and that in region 2 ðd  z < 1Þ is given by Z 1 1 J0 ðmrÞ½ 1 ðmÞe G2 ðp; qÞ ¼ 4pe1 0

mz1

þ 2 ðmÞemz1 Šdm

ð2:6:5Þ

where the unknown functions 1 , 2 , 1 , and 2 are determined by using the boundary conditions G1 ðp; qÞ ¼ G2 ðp; qÞ at z ¼ d @G1 @G2 e1 ¼ e2 at z ¼ d ð2:6:6Þ @z1 @z1 G1 ðp; qÞ ¼ 0 at z ¼ 0 at z ¼ 1 G2 ðp; qÞ ¼ 0

86

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

to be given by 3 2 3 0 1 bKðae2mz 1Þ 6 2 7 6 ðbK 1Þe 2mz0 bKa 7 6 7 6 7 0 4 1 5 ¼ 4 5 bgða e 2mz Þ 2 0 2

ð2:6:7Þ

with e1 e2 e1 þ e2 1 b¼ K þ e2md

K¼

a¼e

m½ðjd z0 jÞ ðd z0 ފ

g ¼ ð1 þ KÞe2md

Substituting Eq. (2.6.7) into Eqs. (2.6.4) and (2.6.5) and solving the resulting integrals, we can find that the Green’s function for the case when points p and q are both in region 1 is given by 2   1 X 1 6 1 1 ffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi þ ð 1Þn K nþ1 G11 ðp; qÞ ¼ 4pffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4pe1 2 z21 þ r2 0 2 n¼0 ð2z þ z1 Þ þ r 0

1 B  @qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½2ðn þ 1Þd ð2z0 þ z1 ފ2 þ r2

1 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½2ðn þ 1Þd þ z1 Š2 þ r2 13

1 1 C7 þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiA5 2 2 0 2 2 ½2ðnþ1Þdþð2z þz1 ފ þr ½2ðnþ1Þd z1 Š þ r

ð2:6:8Þ

the Green’s functions for the cases when points p and q are located in different regions are given by 2   1 6 1 1 ffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi G12 ðp; qÞ ¼ 4pffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4pe1 z21 þ r2 ð2z0 þ z1 Þ2 þ r2 0 1 X 1 1 B ð 1Þn K nþ1  @qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi þ n¼0 ð2nd z1 Þ2 þ r2 ð2nd þ 2z0 þ z1 Þ2 þ r2 13 1 þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½2ðn þ 1Þd þ 2z0 þ z1 Š2 þ r2

1 C7 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiA5 2 ½2ðn þ 1Þd z1 Š þ r2

ð2:6:9Þ

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

G21 ðp; qÞ ¼

  1þK 4pe1 0 2 1 1 BX 6 @ ð 1Þn K n 4qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi n¼0 ð2nd þ z1 Þ2 þ r2

87

31

1 7C qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5A 2 0 2 ð2nd þ 2z þ z1 Þ þ r ð2:6:10Þ

and the Green’s function for the case when points p and q are both in region 2 is given by 0   X 1 1þK B B G22 ðp; qÞ ¼ ð 1Þn K n 4pe1 @ n¼0 2

1 6 4qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½2ðn 1Þd þ 2z0 þ z1 Š2 þ r2

2.6.2

31

1 7C qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5A 2 ð2nd þ 2z0 þ z1 Þ þ r2

ð2:6:11Þ

Multiconductor Interconnection Capacitances

For the three-conductor problem shown in Fig. 2.6.2a, the total charges Qi ði ¼ 1; 2; 3Þ on the three conductors are given in terms of the ground and coupling capacitances shown in Fig. 2.6.2b and the potentials j ðj ¼ 1; 2; 3Þ of the three conductors by the equations

Q1 ¼ C11 1 þ C12 ð1

2 Þ þ C13 ð1

3 Þ

Q2 ¼ C21 ð2

1 Þ þ C22 2 þ C23 ð2

3 Þ

Q3 ¼ C31 ð3

1 Þ þ C32 ð3

ð2:6:12Þ

2 Þ þ C33 3

For a system of N conductors, Eqs. (2.6.12) can be written as

Qi ¼ Cii i þ

N X j¼0

Cij ði

j Þ

i ¼ 1; 2; . . . ; N

ð2:6:13Þ

88

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.6.2 (a) Three finite interconnection metallization lines. (b) Equivalent circuit showing ground and coupling capacitances. (From [24]. # 1987 by IEEE.)

which can be rewritten in terms of the short-circuit capacitances Csij as

Qi ¼

N X

Csij j

j¼1

i ¼ 1; 2; . . . ; N

ð2:6:14Þ

Comparing Eqs. (2.6.13) and (2.6.14), the ground and coupling interconnection capacitances can be obtained from the short-circuit capacitances by using the relations

Cii ¼ Cij ¼

N X

Csij

j¼1

Csij

i ¼ 1; 2; . . . ; N i 6¼ j

ð2:6:15Þ ð2:6:16Þ

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

89

FIGURE 2.6.3 (a) Division of conductor into discrete elements. (b) Shape of piecewise linear charge function on each element. (From [24]. # 1987 by IEEE.)

which in turn require determination of the charge on each conductor for known values of the potentials j .

2.6.3

Piecewise Linear Charge Distribution Function

For a system of N conductors, each conductor is divided into a number of discrete elements as shown in Fig. 2.6.3a and, on each of these elements, the charge density is approximately expressed by a linear combination of four piecewise linear functions. Thus, the charge density si ðqÞ on the ith element is given by si ðqÞ ¼

4 X l¼1

ail fil ðqÞ

ð2:6:17Þ

where fil ðqÞ is the lth of the four charge shape functions used to describe the charge distribution on the ith element and ail are the unknown coefficients which need to be determined. If the ith conductor is divided into Ni elements, then the total charge on this conductor is given by

Qi ¼

Ni Z X j¼1

mth element

sm ðqÞdsm ðqÞ

ð2:6:18Þ

90

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where m¼jþ

i X

Nk

1

k¼2

For a single conductor having a rectangular cross section, the charge shape function is shown in Fig. 2.6.3b and is given by

fqi2

8 > < Aðs ¼ Bðs > : 0

ai Þ

for qi2  s < qi3

bi Þ

for qi1 < s  qi2

for qi4  s  qi1

or qi3  s  qi4

ð2:6:19Þ

where 2 wi ðwi þ ti Þ 2 ti ðwi þ ti Þ

A¼ B¼

ai ¼ six0 þ wi

2.6.4

bi ¼ siz0 þ ti

Calculation of Interconnection Capacitances

In order to determine the interconnection capacitances, we need to find the 4N unknown coefficients ða11 ; . . . ; a14 ; a21 ; . . . ; aN4 Þ. Substituting for charge density from Eq. (2.6.17) in Eq. (2.6.2), we get

j ðpÞ ¼

N X 4 X i¼1 l¼1

ail Fil ðpÞ

j ¼ 1; 2; . . . ; N

ð2:6:20Þ

where Fil ðpÞ ¼

Z

ith element

Gðp; qÞfil ðqÞ dsi ðqÞ

ð2:6:21Þ

Following the Ritz–Rayleigh method [37], both sides of Eq. (2.6.20) are projected onto the space spanned by the original charge shape functions. Using the following

NETWORK ANALOG METHOD

91

equations for the jth element:

ðj ðpÞ; fil ðpÞÞ ¼



0 j

when i 6¼ j when i ¼ j

we get from Eq. (2.6.20) N X 4 X i¼1 l¼1

ail Pijl ¼ ðj ðpÞ; fjl ðpÞÞ

j ¼ 1; 2; . . . ; N

ð2:6:22Þ

Gðp; qÞfjl ðpÞfil ðqÞdsj ðpÞdsi ðqÞ

ð2:6:23Þ

where

Pijl ¼

Z

ith element

Z

jth element

Equation (2.6.22) can be written in matrix form as ½PŠ½AŠ ¼ ½FŠ½Š

ð2:6:24Þ

where A ¼ ða11 ; . . . ; a14 ; a21 ; . . . ; aN4 ÞT is the vector of 4N unknown coefficients, P is the 4N  4N matrix of the evaluated double integrals,  ¼ ð1 ; 2 ; . . . ; N ÞT is the vector of N known potentials of the N conductors, and F is a 4N  N incidence matrix of elements and conductors. Using any standard technique, Eq. (2.6.24) can be solved for the unknown coefficients. Then the charge densities can be obtained using Eq. (2.6.17) and the charges on each conductor can be found from Eq. (2.6.18). Finally, the short-circuit capacitances required for the determination of the interconnection capacitances can be obtained using Eqs. (2.6.14) and (2.6.18) or can be found directly using Cs ¼ ½FŠT ½PŠ 1 ½FŠ

2.7

ð2:6:25Þ

NETWORK ANALOG METHOD

In this section, the parasitic capacitances and inductances associated with the single-, bi-, and trilevel interconnections on GaAs-based ICs are determined by a network analog method [25]. The developed algorithm is suitable for open

92

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

substrates and finite interconnection dimensions in single or multilevels. Furthermore, the algorithm allows greater flexibility in the choice of the spatial domains, thereby reducing the number of nodes and hence the computer processing time. In principle, the method allows for any number of lines in the interconnection configurations. However, the amount of computation time as well as the memory size required for solving the problem will increase with an increase in the number of interconnection lines. The method involves division of the interconnection lines and the underlying substrate into subregions, representation of each subregion by an appropriate network analog, diagonalization of the network analog system and calculation of the parasitic capacitances for the diagonalized system using a recursive scheme, and finally determination of the parasitic capacitances for the system of interconnection lines.

2.7.1

Representation of Subregions by Network Analogs

For the semi-insulating and nonmagnetic GaAs substrate, Maxwell’s equations in the quasi-static case (i.e., ð@=@tÞB ¼ 0) reduce to =E¼0

ð2:7:1Þ

and

=  H ¼ sE þ e

@ E @t

ð2:7:2Þ

Defining a potential V such that E¼

rV

and using the identity ==H¼0 we obtain from Eq. (2.7.2)   @ r sþe V¼0 @t 2

ð2:7:3Þ

93

NETWORK ANALOG METHOD

In 3D rectangular coordinates, the finite-difference form of Eq. (2.7.3) can be written as   @ Vðx þ
xÞ Vðx
xÞ s þ ex @t ð
xÞ2     @ Vðyþ
yÞ Vðy
yÞ @ Vðz þ
zÞ Vðz þ sþe þ sþ ey z @t @t ð
yÞ2 ð
zÞ2


zÞ

¼0

ð2:7:4Þ

where ex , ey , and ez and are the permittivities along the x, y, and z directions, respectively. Multiplying each term of Eq. (2.7.4) by 2ð
xÞð
yÞð
zÞ, it becomes   @ Vðx þ
xÞ Vðx 2ð
yÞð
zÞ s þ ex @t
x


xÞ



 @ Vðy þ
yÞ Vðy þ 2ð
xÞð
zÞ s þ ey @t
y


yÞ

  @ Vðz þ
zÞ Vðz þ 2ð
xÞð
yÞ s þ ez @t
z


zÞ

¼0

ð2:7:5Þ

Equation (2.7.5) implies that the entire region consisting of the lower substrate (GaAs) placed on a conducting ground plane, metallic lines, and the upper open substrate can be divided into subregions each of dimensions
x,
y, and
z consisting of circuit elements whose values depend on the conductivity s and the permittivity e.

2.7.2

Diagonalized System for Single-Level Interconnections

A schematic of the three single-level interconnections printed on the GaAs substrate is shown in Fig. 2.7.1a. In this case, the total admittance matrix G for the nodes in the plane of the interconnection lines is given by G ¼ Gu þ Gl

ð2:7:6Þ

where Gu and Gl are the admittance matrices for the upper and lower substrates, respectively. The matrix G can be determined by first determining the impedance

94

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.1 Schematic of (a) three single-level, (b) six bilevel, and (c) six trilevel interconnections printed on or embedded in GaAs substrate.

matrix Zk for the kth layer ðk ¼ 1; 2; . . . ; L1 Þ using a recurrence formula Zk ¼ zk

1

þ ½Gk

1

þ ½Zk 1 Š 1 Š

1

ð2:7:7Þ

where Gk , the admittance matrix for the network analog of the kth layer, is given by

Gk ¼

2

ð1Þ

4 Gk

ð2Þ Gk

h

i ð2Þ T

Gk

ð1Þ Gk

3 5

NETWORK ANALOG METHOD

95

where 2

ð1Þ

Gk

ð2Þ

Gk

2ða þ bÞ 6 a 6 6 6 0 ¼6 6 .. 6 . 4 0 2

6 6 6 ¼6 6 6 4

a 2ða þ bÞ a .. . 0

b

0

0

0 0 .. . 0

b 0 .. . 0

0 b .. . 0












.. .




0 a









2ða þ bÞ


.. .. . . 0


a

0 0 0 .. . 2ða þ bÞ

3

3 7 7 7 7 7 7 7 5

ð2:7:8Þ

0 7 7 7 0 7 7 .. 7 . 5 b

and the values of a and b are determined by the dimensions, conductivity and permittivity of the subsections on the kth layer as given by   ð
yÞð
zk Þ ð
yÞð
zkþ1 Þ þ
x
x   ð
xÞð
zk Þ ð
xÞð
zkþ1 Þ 1 þ b ¼ 2ðjoer e0 þ sÞ
y
y a ¼ 12ðjoer e0 þ sÞ

ð2:7:9Þ

In Eq. (2.7.7) zk is the impedance of each element on the kth layer and is given by zk ¼


zk ðjoer e0 þ sÞð
xÞð
yÞ

ð2:7:10Þ

Gl ¼ ½ZLl Š 1 þGLl

ð2:7:11Þ

Then, for the lower substrate

Similarly, for the upper substrate Gu ¼ ½ZLu Š 1 þGLu In the past, the network analog method has been restricted to the case when
x ¼
y. However, greater flexibility can be introduced if
x is not necessarily equal to
y. Furthermore, computer processing time can be lowered if
z is increased as the distance of the layer from the interconnections increases. With these modifications, the admittance matrix Gk has a special band form as shown in Eq. (2.7.8) and can be diagonalized. If Nði; jÞ denotes the node number corresponding to

96

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

the ith row ði ¼ 1; 2; . . . ; Nx Þ and the jth column ðj ¼ 1; 2; . . . ; Ny Þ, then the eigenvalue corresponding to this node is given by 

l½Nði; jފ ¼ 2a 1



ip cos Nx þ 1



 þ 2b 1



jp cos Ny þ 1



ð2:7:12Þ

and an element of the corresponding orthonormal eigenvector matrix E is given by     2 imp jnp E½Nðm; nÞ; Nði; jފ ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffipffiffiffiffiffiffiffiffiffiffiffiffiffiffi sin sin Nx þ 1 Ny þ 1 Nx þ 1 Ny þ 1

ð2:7:13Þ

where Nx and Ny are the number of subdivisions along the x and the y directions, respectively. It can be proved that the eigenvector E in Eq. (2.7.13) is orthonormal, that is, ET ¼ E 1 . The diagonalized admittance matrix can now be written as

 GD k ¼ Diag l1 ; l2; . . . ; lNx
Ny

and is related to the matrix Gk by

T Gk ¼ EGD kE

Similarly, the diagonalized impedance matrix ZkD is related to the matrix Zk by Zk ¼ EZkD ET and the recurrence formula for the diagonalized system becomes h D 1i þ Zk 1 ZkD ¼ zk 1 I þ GD k 1

1

k ¼ 1; 2; . . . ; Lu;l

ð2:7:14Þ

and then, for the upper and lower substrates, h i D GD u;l ¼ Zu;l

1

ð2:7:15Þ

The representation of the node Nði; jÞ due to the lower substrate in the diagonalized system is shown in Fig. 2.7.2a. The corresponding representation due to the upper substrate can be obtained on the same lines. First, the matrices GD u and GD l are obtained and then the total impedance matrix Z is obtained by

D 1 T Z ¼ E GD E u þ Gl

ð2:7:16Þ

NETWORK ANALOG METHOD

97

FIGURE 2.7.2 (a) Representation of node on single-level interconnections in diagonalized system. (b) Representation of node between any two levels of multilevel interconnections in diagonalized system.

2.7.3

Diagonalized System for Multilevel Interconnections

Schematics of the interconnections in the bi- and trilevel configurations are shown in Figs. 2.7.1b and c, respectively. In this case, the network analogs for the upper open substrate and for the substrate between the lowest interconnection level and the bottom ground plane can be reduced by the technique used for the single-level interconnections. However, the substrate between the successive levels needs to be considered. The diagonalized system for a node in the x–y plane on a layer between any two levels can be shown as in Fig. 2.7.2b. The values of the elements z1 ; z2 ; . . . ; zL and l1 ; l2 ; . . . ; lL are determined by the dielectric permittivity, conductance, and dimensions of the subsections at the node. In order to save the computation time, the substrate between the two successive interconnection levels can be divided into two symmetric halves and then the reduced network for the upper half can be combined with the equivalent network for the lower half.

2.7.4

Interconnection Capacitances and Inductances

It can be shown that only the nodes located on the interconnection lines determine the interconnection characteristics. For multilevel interconnections, the total impedance matrix contains submatrices which connect nodes on the interconnection

98

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

lines on all levels. For example, for three interconnection lines in any configuration, the impedance matrix is given by 2

½Zi11 Š ½ZŠ ¼ 4 ½Zi21 Š ½Zi31 Š

3 ½Zi13 Š ½Zi23 Š 5 ½Zi33 Š

½Zi12 Š ½Zi22 Š ½Zi32 Š

where the matrix ½Zi12 Š represents coupling between the nodes on the first and second interconnections and so on. The ground and coupling capacitances associated with the multilevel interconnections can then be determined as follows: Let

½YŠ ¼ ½ZŠ

1

2

½Yi11 Š ¼ 4 ½Yi21 Š ½Yi31 Š

½Yi12 Š ½Yi22 Š ½Yi32 Š

3 ½Yi13 Š ½Yi23 Š 5 ½Yi33 Š

s denote the sum of the elements of the submatrix ½Yixy Š, that is, Further, let Yixy s ¼ Yixy

M X N X m¼1 n¼1

Yixy ðm; nÞ

Then the ground interconnection capacitances are given by X s s Cxx ¼ Yixx Yixy þ x6¼y

and the coupling interconnection capacitances are given by Cxy ¼

s Yixy

x 6¼ y

ð2:7:17Þ

The inductance matrix can be computed from the capacitance matrix for the corresponding two-dimensional interconnection configuration (consisting of infinite-length interconnections) in free space by the matrix inversion. The telegraphist’s equations for the lossless case in free space are @V ¼ @x

L

@I @t

C0

@V @t

and @I ¼ @x or @2V @2V ¼ LC 0 @x2 @t2

NETWORK ANALOG METHOD

99

In free space, the wave should travel with the speed of light, that is,   @2V 1 @2V ¼ @x2 v2 @t2 Therefore LC0 ¼

1 ¼ m0 e0 v2

In matrix form ½LŠ ¼ m0 e0 ½C0 Š

1

ð2:7:18Þ

In Eq. (2.7.18), m0 and e0 are the permeability and permittivity for free space and ½C0 Š is the capacitance matrix for the 2D interconnection configuration in free space. 2.7.5

The Program ICIMPGV

The listing of a computer program called ICIMPGV used to compute the parasitic capacitances and inductances for the multilevel parallel interconnections on the GaAs-based high-density ICs and based on the numerical technique presented above is included in Appendix 2.2 on the accompanying ftp site. In the next two sections, the program ICIMPGV has been used to study the dependences of the interconnection capacitances and inductances on the various interconnection parameters. 2.7.6

Parametric Dependence of Interconnection Capacitances

For the single-level interconnections, the capacitance results are compared to those obtained by using the Green’s function method and an excellent agreement can be seen. For example, as a function of the interconnection length, the dependences of the ground and coupling capacitances as determined by using the two methods are shown in Figs. 2.7.3 and 2.7.4, respectively, and the same comparisons as functions of the interconnection width are shown in Figs. 2.7.5 and 2.7.6, respectively. For a system of more than four interconnections, the results obtained by the Green’s function method can be only approximate at best. Therefore, the results for the bilevel and trilevel configurations as shown below are obtained by the network analog method only. For the bilevel interconnections shown in Fig. 2.7.1b, the dependences of the various ground and coupling capacitances on the lengths of the interconnection lines in the range 20–2000 mm keeping the other parameters at their fixed typical values are shown in Figs. 2.7.7 and 2.7.8, respectively. As functions of the interlevel distance in the range 1–20 mm, the ground and coupling capacitances for the same bilevel configuration are shown in Figs. 2.7.9 and 2.7.10, respectively.

100

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.3 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1a on interconnection lengths as determined by Green’s function and network analog methods.

FIGURE 2.7.4 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1a on interconnection lengths as determined by Green’s function and network analog methods.

NETWORK ANALOG METHOD

101

FIGURE 2.7.5 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1a on interconnection widths as determined by Green’s function and network analog methods.

FIGURE 2.7.6 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1a on interconnection widths as determined by Green’s function and network analog methods.

102

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.7 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1b on interconnection lengths.

FIGURE 2.7.8 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1b on interconnection lengths.

NETWORK ANALOG METHOD

103

FIGURE 2.7.9 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1b on interlevel distance T12 .

FIGURE 2.7.10 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1b on interlevel distance T12 .

104

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.11 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1c on interconnection widths.

For the trilevel interconnections shown in Fig. 2.7.1c, the dependences of the ground and coupling capacitances on the widths of the interconnection lines in the range 0.5–5 mm are shown in Figs. 2.7.11 and 2.7.12, respectively. The values of the fixed parameters are also shown in the figures. As functions of the interconnection separation in the range 0.5–10 mm, the ground and coupling capacitances for the trilevel interconnections are shown in Figs. 2.7.13 and 2.7.14, respectively. Figures 2.7.15 and 2.7.16 show the variation of the various ground and coupling capacitances for the trilevel configuration on the interlevel distance T23 in the range 2–50 mm.

2.7.7

Parametric Dependence of Interconnection Inductances

While modeling the interconnections for very high speed signal propagations, the inductances coupling the various interconnection lines should also be considered. The program ICIMPGV can be used to study the dependences of the various coupling inductances for the single-, bi-, and trilevel interconnection configurations shown in Fig. 2.7.1 on the various interconnection parameters. For example, for the three single-level interconnections, Fig. 2.7.17 shows the dependences of the

NETWORK ANALOG METHOD

105

FIGURE 2.7.12 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1c on interconnection widths.

FIGURE 2.7.13 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1c on interconnection separations.

106

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.14 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1c on interconnection separations.

FIGURE 2.7.15 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1c on interlevel distance T23 .

NETWORK ANALOG METHOD

107

FIGURE 2.7.16 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1c on interlevel distance T23 .

FIGURE 2.7.17 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1a on interconnection widths.

108

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.18 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1a on interconnection separations.

FIGURE 2.7.19 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1b on interconnection widths.

SIMPLIFIED FORMULAS FOR INTERCONNECTION CAPACITANCES

109

FIGURE 2.7.20 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1b on interconnection separations.

coupling inductances in nanohenrys per centimeter on the interconnection widths in the range 0.5–5 mm while Fig. 2.7.18 shows those on the interconnection separations in the range 0.5–10 mm. For the bilevel configuration, the dependences of the various coupling inductances on the interconnection widths are shown in Fig. 2.7.19 while those on the interconnection separations are shown in Fig. 2.7.20. For the bilevel configuration, the dependences of the various coupling inductances on the thickness of the GaAs substrate in the range 3–200 mm are shown in Fig. 2.7.21 while those on the interlevel distance T12 in the range 1–50 mm are shown in Fig. 2.7.22. For the trilevel interconnections, the various coupling inductances as functions of the interconnection widths in the range 0.5–4 mm are shown in Fig. 2.7.23, those as functions of the interconnection separations in the range 0.5–5 mm are shown in Fig. 2.7.24, and those as functions of the interlevel distance T23 are shown in Fig. 2.7.25.

2.8

SIMPLIFIED FORMULAS FOR INTERCONNECTION CAPACITANCES AND INDUCTANCES ON SILICON AND GaAs SUBSTRATES

In recent years, insulating substrates such as Cr-doped semi-insulating gallium arsenide (GaAs) have emerged as alternatives to silicon. This is partially because of the argument that interconnections fabricated on these substrates offer considerably

110

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.21 Dependences of the coupling inductances for interconnections shown in Fig. 2.7.1b on substrate thickness.

FIGURE 2.7.22 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1b on interlevel distance T12 .

SIMPLIFIED FORMULAS FOR INTERCONNECTION CAPACITANCES

111

FIGURE 2.7.23 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1c on interconnection widths.

FIGURE 2.7.24 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1c on interconnection separations.

112

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.25 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1c on interlevel distance T23 .

lower capacitances than those fabricated on silicon. In this section, simplified formulas for finding the line and coupling capacitances and inductances for interconnections fabricated on the oxide-passivated silicon and semi-insulating GaAs substrates are presented [26]. 2.8.1

Line Capacitances and Inductances

The cross section of an interconnection fabricated on an insulating substrate is shown in Fig. 2.8.1a. It is defined by its width ðwÞ, height of the substrate ðhÞ, and relative dielectric constant of the material of the substrate ðer Þ. It is assumed that the thickness of the interconnection line is negligibly small. The approximate values of

FIGURE 2.8.1 Schematic of cross section of typical interconnection on (a) insulating substrate and (b) oxide-passivated silicon substrate. (From [26]. # 1982 by IEEE.)

113

SIMPLIFIED FORMULAS FOR INTERCONNECTION CAPACITANCES

the line capacitance and inductance of the interconnection can be determined by using the formulas [26] 2pe0 eeff ln½8h=w þ w=ð4hފ   m 8h w þ L ¼ 0 ln w 4h 2p

C¼

wh ð2:8:1Þ

where eeff is the effective dielectric constant of the substrate material given by eeff ¼

  er þ 1 er 1 h þ 1 þ 10 2 2 w

0:5

The cross section of an interconnection fabricated on an oxide-passivated silicon substrate is shown in Fig. 2.8.1b. In this figure, tox is the oxide thickness and tSi is the thickness of the silicon substrate. For frequencies below 1 GHz, the approximate values of the line capacitance and inductance of the interconnection on an oxidepassivated silicon substrate can be determined by using the formulas 2pe0 eeff ln½8h=w þ w=ð4hފ C¼ h > : e e w þ 2:42 0:44 tox þ 1 0 r tox w   m 8h w h ¼ tox þ tSi þ L ¼ 0 ln 2p w 4h 8 >
> > < > > > :

  60 8h w þ pffiffiffiffiffiffiffi  ln eeff w 4h 120p

½w=h þ 2:42

0:44h=w þ ð1

w h h=wÞ6 Š eeff

ð3:7:4Þ

The maximum relative error in expressions (3.7.3) and (3.7.4) is less than 2%; however, corrections [52] are required for t=h > 0:005. The expression for eeff at high frequencies has been derived by Yamashita et al [53] and is given by pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi er eeff ð0Þ eeff ð f Þ ¼ eeff ð0Þ þ 1 þ 4F 1:5

ð3:7:5Þ

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

205

where   n  4fh pffiffiffiffiffiffiffiffiffiffiffiffi wo2 er 1 0:5 þ 1 þ 2 log 1 þ F c h f is the frequency, and c is the speed of light in a vacuum. The error in the expression (3.7.5) is less than 1%. For a lossless material, the propagation constant b0 is given by b0 ¼

pffiffiffiffiffiffiffi 2pf eeff c

ð3:7:6Þ

However, for a conductor of finite resistivity and substrate material of finite conductivity, the attenuation should be considered. At low frequencies where the current distribution in the conductor can be considered uniform, the conductor loss factor ac is given in nepers as rc ac ¼ ð3:7:7Þ 2wtZ0 where rc is the resistivity of the metal. However, at high frequencies where the current distribution is not uniform due to the skin effect, the conductor loss is given by [54] 8 "  0  2 #  > R w h hflnð4pw=tÞ þ t=wg w 1 s > > 1 < 1þ 0þ > > 0 > 2pZ h 4h w pw h 2p 0 > > > > > > > >   0 2 #  " > > R w h hflnð4h=tÞ t=hg 1 w > s > > 1 < < 2pZ0 h 4h w pw0 2p h : ac ¼ > >   > > Rs =ðZ0 hÞ w0 w0 =ðphÞ > > > þ  > 2 > 0 0 h 0:94 þ w0 =ð2hÞ > ½w =h þ ð2=pÞ lnf2pe½0:94 þ w =ð2hÞgŠ > > > > > >   > > h hflnð2h=tÞ t=hg w > > :  1þ 0þ >2 0 w pw h where m is the permeability of the metal, Rs 

pffiffiffiffiffiffiffiffiffiffiffiffi pf mrc , and

8    t 4pw w 1 > > < > < w þ p 1 þ ln t h 2p w0 ¼    > t 2h w 1 > > > : w þ 1 þ ln p t h 2p

ð3:7:8Þ

206

INTERCONNECTION DELAYS

FIGURE 3.7.2 Dependences of conductor loss, dielectric loss, and line loss on frequency [49].

The dielectric loss ad caused by the nonzero conductivity of the substrate has been derived by Welch and Pratt [55] and is given by ad ¼

60pss ðeeff 1Þ pffiffiffiffiffiffiffi ðer 1Þ eeff

ð3:7:9Þ

where ss is the conductivity of the substrate. For a 50- , 0.5-mm-thick aluminum microstripline on a 450-mm-thick Si wafer of resistivity 100
cm, the dependences of the conductor loss, dielectric loss, and line loss on frequency in the range 108–1013 Hz are shown in Fig. 3.7.2. The circuit diagram and circuit equations for the transmission line model of the microstrip interconnection are given in Fig. 3.7.3, where L and C denote

FIGURE 3.7.3 Circuit diagram and circuit equations for transmission line model of microstrip interconnection [49].

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

207

the inductance and capacitance per unit length for the lossless line and Rc and Rd denote the resistances per unit length introduced by the conductor resistance and the substrate conductance. The circuit equations can be solved to yield the following expressions for the general attenuation constant a and propagation constant b: qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi ffi 1 ð f þ f2 Þ 1 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi b ¼ 12ðf1 þ f2 Þ

ð3:7:10aÞ

a¼

where

ð3:7:10bÞ

Rc Rd  2 #"  2 # Rc Z0 2 2 f2 ¼ o LC þ o LC þ Z0 Rd f1 ¼ o2 LC "

ð3:7:11Þ

with Z0 ¼ ðL=CÞ0:5 . For low-loss conditions, the circuit model of Fig. 3.7.3 yields ac ¼

Rc 2Z0

ad ¼

pffiffiffiffiffiffi b0 ¼ o LC

Z0 2Rd

ð3:7:12Þ

Equations (3.7.11) and (3.7.12) can be combined to rewrite f1 and f2 in terms of, b0 , ac , and ad as f1 ¼ b20 4ac ad



 f2 ¼ b20 þ 4a2c b20 þ 4a2d

ð3:7:13Þ

Then Eqs. (3.7.6)–(3.7.9) can be combined with Eqs. (3.7.10) and (3.7.13) to obtain a and b for all loss conditions. If ac and ad are small as compared to b0 , as will be the case under low-loss conditions, then a and b are given by

a ¼ ac þ ad

3.7.2

b¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðac ad Þ2 þ b20

ð3:7:14Þ

Simulation Results

The simulation results are obtained for two input high-speed logic waveforms consisting of square-wave and exponential pulses. The input square-wave pulses are of 50 ps duration with 12 ps rise and fall times. The input exponential pulses are of the form vðtÞ ¼ e

ðt=t1 Þ

½1

eð

t=t2 Þ

Š

ð3:7:15Þ

208

INTERCONNECTION DELAYS

FIGURE 3.7.4 Circuits used to produce (a) exponential and (b) square-wave input pulses for simulation results presented in this section [49].

Input pulses vsw ð0; tÞ and vex ð0; tÞ with finite rise and fall times can be produced by applying ideal square-wave and exponential pulses to the circuits shown in Fig. 3.7.4. By choosing the circuit parameters in Fig. 3.7.4, a variety of pulses can be obtained. The Fourier transforms of the input square-wave pulses are given by 

Vsw ð0; f Þ ¼

1

e jot1 jo



1 1 þ jot2

o2 =o21



ð3:7:16Þ

where o21 ¼

1 LC

t2 ¼

L Z0

The Fourier transforms of the input exponential pulses are given by Vex ð0; f Þ ¼



1 jo þ 1=t1



1 1 þ jot2 þ t2 =t1



ð3:7:17Þ

where t1 ¼ Z0 C

t2 ¼ RC

As stated earlier, the voltage response vðz; tÞ at a distance z along the microstripline are obtained by multiplying the Fourier transform of the input waveform (at z ¼ 0) by the propagation factor exp½ða þ jbÞzŠ and then taking the inverse Fourier transform. The dependences of the characteristic impedance on frequency for two microstrips of widths 10 and 300 mm on a Si wafer of thickness 450 mm are shown in Fig. 3.7.5. This figure shows that the region of geometric dispersion extends from 10 to 300 GHz and that this effect is more pronounced for the narrow line width of 10 mm. Figure 3.7.6 shows the line losses versus frequency for microstriplines made

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

209

FIGURE 3.7.5 Characteristic impedance versus frequency for two microstrip interconnections of widths 10 and 300 mm [49].

FIGURE 3.7.6 Plots of line loss versus frequency for interconnection materials of Al (r ¼ 2:7 m
cm), W (r ¼ 10 m
cm), WSi2 (r ¼ 30 m
cm), and poly-Si (r ¼ 500 m
cm) on 450-mm-thick Si wafer [49].

210

INTERCONNECTION DELAYS

FIGURE 3.7.7 Plots of phase velocity versus frequency for interconnection materials of Al (r ¼ 2:7 m
cm), W (r ¼ 10 m
cm), WSi2 (r ¼ 30 m
cm), and poly-Si (r ¼ 500 m
cm) on 450-mm-thick Si wafer [49].

of aluminum, tungsten, WSi2, and poly-Si of widths 10 and 300 mm on two substrates with resistivities of 10 and 100
cm. The dependences of the phase velocity on frequency for the same set of parameters as in Fig. 3.7.6 are shown in Fig. 3.7.7. For exponential input pulse (with t1 ¼ 15 ps and t2 ¼ 1 ps) and square-wave input pulse (with t1 ¼ 50 ps, t2 ¼ 5 ps, and o1 ¼ 1012 Hz), the time-domain waveforms for aluminum interconnections of widths 10 and 300 mm on two substrates with resistivities of 10 and 100
cm at z values of 3 and 6 mm are shown in Figs. 3.7.8 and 3.7.9. It should be noted that for the substrate resistivity of 10
cm the signal is severely attenuated by 6 mm whereas for the substrate resistivity of 100
cm it is not affected as much. Thus, it can be concluded that high-resistivity substrates are more appropriate when designing microstrip interconnections for high-frequency ICs. For interconnection materials of tungsten, WSi2, and poly-Si and for the squarewave input pulses, the time-domain waveforms at a few locations on the microstrip interconnection on two substrates with resistivities of 10 and 100
cm are shown in Figs. 3.7.10–3.7.12. It should be noted that the conductor loss becomes increasingly significant from aluminum to tungsten to WSi2 lines but the changes are not

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

211

FIGURE 3.7.8 Plots of time-domain exponential pulses after 0, 3, and 6 mm of propagation on Al microstriplines on 450-mm-thick Si wafer [49].

FIGURE 3.7.9 Plots of time-domain square-wave pulses after 0, 3, and 6 mm of propagation on Al microstriplines on 450-mm-thick Si wafer [49].

212

INTERCONNECTION DELAYS

FIGURE 3.7.10 Plots of time-domain square-wave pulses after 0, 3, and 6 mm of propagation on W microstriplines on 450-mm-thick Si wafer [49].

FIGURE 3.7.11 Plots of time-domain square-wave pulses after 0, 1.5, and 3 mm of propagation on WSi2 microstriplines on 450-mm-thick Si wafer [49].

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

213

FIGURE 3.7.12 Plots of time-domain square-wave pulses after 0, 1.5, and 3 mm of propagation on poly-Si microstriplines on 450-mm-thick Si wafer [49].

dramatic. Figure 3.7.12 shows that, for poly-Si lines, the loss becomes very large for very high speed pulses though significant improvement is achieved by choosing higher resistivity substrates, as is the case with other lines as well. 3.7.3

Interconnection Delays with High-Frequency Effects

The transmission line model for the single-level interconnections presented in Section 3.2 can be modified to include the high-frequency losses described above. Then each section of the transmission line will be modified to that shown in Fig. 3.7.13. The propagation constant for the interconnection line will be given by vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi " !#ffi u 4 X u 1 þ s Ci þ Yi g ¼ tðRc þ sLi Þ Rd i¼1

ð3:7:18Þ

FIGURE 3.7.13 One section of transmission line including very high frequency effects [56].

214

INTERCONNECTION DELAYS

and the characteristic impedance will be given by vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u Rc þ sLi u ! Z0 ¼ u 4 u1 X t þs C þ Yi i Rd i¼1

ð3:7:19Þ

where the Yi ’s are defined in Section 3.2. The rest of the analysis can be completed following the steps outlined in Section 3.2. In the following simulation results [56], one of the parameters is changed while the others are set as follows: frequency f ¼ 10 GHz, interconnection widths 1 mm each, interconnection lengths 1 mm each, source resistance Rs ¼ 700 , load capacitance CL ¼ 100 fF, substrate thickness 200 mm, and interconnection material resistivity 2.82 m
cm for aluminum. Figure 3.7.14 shows the dependence of the delay time on the frequency of the input signal. It can be seen that the dependence of propagation delay on the frequency is minimal until it is near and above the 1-MHz range when the propagation delay becomes quite responsive to a change in the frequency. After 1 GHz, the delay suggests significant skin effect and dielectric losses. Figure 3.7.15 shows the delay time as a function of the interconnection width at f ¼ 10 GHz. It shows that the delay time increases steadily as the width and hence the interconnection capacitance are increased. Decreasing the line resistance with increasing width does not seem to play an important role because of the dominant skin effect at high frequencies.

FIGURE 3.7.14 Dependence of delay time on frequency of input signal [56].

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

215

FIGURE 3.7.15 Dependence of delay time on width of interconnection line at 10 GHz [56].

Delay time as a function of the interconnection material resistivity is shown in Fig. 3.7.16. Figure 3.7.17 displays the dependence of delay time on load capacitance, which corresponds to the input capacitance of the gate loading the interconnection. Figure 3.7.18 shows the dependence of delay time on source resistance, which corresponds to the output resistance of the gate/transistor driving the interconnection line.

FIGURE 3.7.16 10 GHz [56].

Dependence of delay time on resistivity of interconnection material at

216

INTERCONNECTION DELAYS

FIGURE 3.7.17 Dependence of delay time on load capacitance at 10 GHz [56].

FIGURE 3.7.18 Dependence of delay time on driving source resistance at 10 GHz [56].

3.8

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

In this section, compact, that is, closed-form, expressions for the voltage waveforms and the coresponding delays at the load end of an interconnection are presented. First, the interconnection will be modeled as a distributed RC network [57] and then

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

217

it will be treated as an RLC network [19]. The expressions are useful for obtaining quick estimates of the interconnection delays though at the cost of some accuracy. 3.8.1

The RC Interconnection Model

Consider a single-level interconnection of length ‘ driven by a transistor or a gate and connected to another transistor or gate at its load end, as shown in Fig. 3.8.1. It can be modeled as an interconnection line driven by a voltage source of internal resistance RS and loaded by a capacitor CL. Inductive effects are neglected in this treatment. Voltage wave propagation along this line is represented by the differential equation     1 @2V @V ¼ c r @x2 @t

ð3:8:1Þ

where r and c are the resistance and capacitance of the interconnection line per unit length, respectively. The voltage waveform Vð‘; tÞ at the interconnection load can be expressed as a series [58]: 1 X Vð‘; tÞ ¼1þ Kk e VS k¼1

sk
t=RC

 1 þ K1 e

s1
t=RC

ð3:8:2Þ

where R and C are the total resistance and capacitance of the interconnection line, respectively, that is, R ¼ ðrÞð‘Þ and C ¼ ðcÞð‘Þ. The sk ’s are the roots of the equation [57]

subject to the condition

pffiffiffiffiffiffi 1 RT CT sk tan sk ¼ pffiffiffiffiffiffi ðRT þ CT Þ sk

k



3 2

p
0:1RC and therefore K1 and s1 are the most important coefficients. The approximate values of these two coefficients are given by K1 ¼ s1 ¼



RT þ C T þ 1 1:01 RT þ CT þ p=4



ð3:8:5Þ

1:04

ð3:8:6Þ

RT CT þ RT þ CT þ ð2=pÞ2

The relative errors of the above functions are less than 3% for K1 and less than 4% for s1 for any values of RT and CT . It should be noted that the exact value of K1 is 4=p and that of s1 is ðp=2Þ2 for RT ¼ CT ¼ 0. When RT ¼ CT  1, the exact value of K1 is 1 and that of s1 is 1=½ðRT þ 1ÞðCT þ 1ފ. Both these asymptotic values are correctly produced by expressions (3.8.5) and (3.8.6). The voltage waveform at the load end of the interconnection can be expressed as Vð‘; tÞ ¼1 VS

exp



t=ðRCÞ 0:1 RT CT þ RT þ CT þ 0:4



ð3:8:7Þ

Equation (3.8.7) can be solved for t in terms of Vð‘Þ. The time t taken by the load voltage to reach v ¼ V=VS is given by     1 ðRT CT þ RT þ CT þ 0:4Þ t ¼ RC 0:1 þ ln 1 v

ð3:8:8Þ

Equation (3.8.8) can be further solved to find the times t0:5 and t0:9 for v ¼ 0:5 and v ¼ 0:9, respectively, as t0:5 ¼ RC½0:377 þ 0:693ðRT CT þ RT þ CT ފ t0:9 ¼ RC½1:02 þ 2:3ðRT CT þ RT þ CT ފ

ð3:8:9Þ ð3:8:10Þ

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

219

Comparisons of the load voltage waveforms and the corresponding delays obtained using the compact expressions (3.8.9) and (3.8.10) with those obtained using the exact analysis show that the error in Eq. (3.8.8) is less than 3.5% of RC [57]. The accuracy of this equation is better than that given by the widely used Elmore’s delay expression [59]. 3.8.2

The RLC Interconnection Model: Single Semi-Infinite Line

A single semi-infinite interconnection line modeled as a distributed RLC network driven by a step input voltage source VS with a source resistance RS is shown in Fig. 3.8.2. The voltage Vinf ðx; tÞ along this line is described by the partial differential equation @2 @2 @ Vinf ðx; tÞ ¼ lc 2 Vinf ðx; tÞ þ rc Vinf ðx; tÞ 2 @x @t @t

ð3:8:11Þ

where r, l, and c are the distributed resistance, inductance, and capacitance per unit length of the interconnection line, respectively. Assuming that the voltage and current along the line are zero at t ¼ 0, Laplace transformation of Eq. (3.8.11) yields the differential equation  @2 r V ðx; sÞ ¼ lcs s þ ð3:8:12Þ Vinf ðx; sÞ inf @x2 l In the Laplace (s) domain, a general solution of Eq. (3.8.12) can be written as ffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi   pffiffiffiffi  pffiffiffiffi  r r Vinf ðx; sÞ ¼ A exp þ B exp x lc s s þ ð3:8:13Þ x lc s s þ l l

FIGURE 3.8.2 Single semi-infinite interconnection line (a) modeled as distributed RLC network and (b) driven by input voltage source VS with source resistance RS .

220

INTERCONNECTION DELAYS

The coeficient A can be determined from applying the known boundary condition at x ¼ 0 that Vinf ð0; sÞ is equal to the input source voltage VS ðsÞ minus the voltage drop across the source impedance in the s domain while B can be determined from the requirement that at x ¼ 1 the voltage must be finite and well behaved, resulting in B ¼ 0. Then the voltage along the line in the s domain is given by ffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  pffiffiffiffi  ZðsÞ r exp x lc s s þ Vinf ðx; sÞ ¼ VS ðsÞ ð3:8:14Þ ZðsÞ þ RS l where ZðsÞ is the characteristic impedance of the lossy interconnection given by rffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffi r þ sl s þ r=l ¼ Z0 ZðsÞ ¼ sc s

ð3:8:15Þ

pffiffiffiffiffiffi where Z0 is the characteristic impedance of the lossless line given by Z0 ¼ l=c. The voltage along the semi-infinite line in the time domain can be obtained by an inverse Laplace transformation of Eq. (3.8.14) to be [19]   qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi Z0 r=ð2lÞt e  I0 s t2 ðx lcÞ2 Vinf ðx; tÞ ¼ VS Z0 þ RS pffiffiffiffi!k=2 h  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 pffiffiffiffi 2 1 X t x lc 2 pffiffiffiffi 4 Ik s t ðx lcÞ þ 1 t þ x lc k¼1 

 u0 ðt

pffiffiffiffi x lcÞ

ð1 þ Þ2

k 1

i

ð3:8:16Þ

where s ¼ r=ð2lÞ, Ik is the kth-order modified Bessel function, u0 is a unit step function, and is the reflection coefficient defined by ¼

RS Z0 RS þ Z0

The voltage along the lossless semi-infinite line can be obtained from Eq. (3.8.16) after substituting r ¼ 0 to be Vinf ðx; tÞ ¼ VS



 Z0 u0 ðt Z0 þ RS

pffiffiffiffi x lcÞ

ð3:8:17Þ

because the zero-order modified Bessel function has a value of unity and all higher order modified Bessel functions become zero. pffiffiffiffi It is interesting to note from Eq. (3.8.16) that at t ¼ x lc the voltage wavefront traveling down the lossy semi-infinite line is given by Vinf ðx; tÞ ¼ VS



 Z0 e Z0 þ RS

r=ð2Z0 Þx

ð3:8:18Þ

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

221

FIGURE 3.8.3 Single interconnection of finite length modeled as distributed RLC network driven by input voltage source VS with a source resistance RS and terminated by open circuit.

3.8.3

The RLC Interconnection Model: Single Finite Line

A global interconnection for gigascale integration can be represented by a finite line of length ‘ driven by a source with an arbitrary source impedance and terminated by an open circuit [60] as shown in Fig. 3.8.3. The reflection diagram for a line of finite length is shown in Fig. 3.8.4. In the s domain, the voltage at the end of the line is given by

Vfin ð‘; sÞ ¼ 2Vinf ð‘; sÞ þ 2

q  X RS n¼1

ZðsÞ RS þ ZðsÞ

n

Vinf ½ð2n þ 1Þ‘; sŠ

ð3:8:19Þ

where n is the reflection number, q is the maximum reflection number shown in Fig. 3.8.4, and ZðsÞ is defined by Eq. (3.8.15). In the time domain, the voltage at the

FIGURE 3.8.4 Reflection diagram for single interconnection of finite length. (From [19]. # 2000 by IEEE.)

222

INTERCONNECTION DELAYS

end of the finite line is given by [19]   q X n X 1 X Z0 nðn 1þ jÞ! Vfin ð‘; tÞ ¼ 2Vinf ð‘; tÞ þ 2VS e r=ð2lÞt ð 1Þi n iþj Z0 þ RS i!j!ðn iÞ! n¼1 i¼0 j¼0 ( ! pffiffiffiffi ðiþjÞ=2  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi t ð2n þ 1Þ‘ lc 1 pffiffiffiffi  Iiþj s t2 ½ð2n þ 1Þ‘ lcŠ2 þ 1 t þ ð2n þ 1Þ‘ lc pffiffiffiffi!ðiþjþkÞ=2  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 X pffiffiffiffi t ð2n þ 1Þ‘ lc p ffiffiffiffi  Iiþjþk s t2 ½ð2n þ 1Þ‘ lcŠ2 t þ 2n þ 1Þ‘ lc k¼1 ) pffiffiffiffi ½4 ð1 þ Þ2 k 1 Š  u0 ½t ð2n þ 1Þ‘ lcŠ ð3:8:20Þ where q, defined earlier as the maximum reflection number for a given time, can be written as a function of time as    t 1:0 ð3:8:21Þ q ¼ 0:5 pffiffiffiffi þ 1:0 x lc with the notation hxi representing the decimal truncation of x, that is, h2:3i ¼ h2:8i ¼ 2:

For the special case when the driving source resistance RS is equal to the characteristic impedance of the lossless line Z0 and the reflection coefficient becomes zero, the voltage at the end of the finite line is given by q X Vfin ð‘; tÞ ¼ 2Vinf ð‘; tÞ þ VS e r=ð2lÞt ð 1Þn n¼1

pffiffiffiffi!n=2  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi t ð2n þ 1Þ‘ lc pffiffiffiffi  In s t2 ½ð2n þ 1Þ‘ lcŠ2 t þ ð2n þ 1Þ‘ lc pffiffiffiffi!ðnþkÞ=2 1 X t ð2n þ 1Þ‘ lc pffiffiffiffi : þ t þ ð2n þ 1Þ‘ lc k¼1 )  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi n pffiffiffiffi o pffiffiffiffi 2 k 1 2 Inþk s t ½ð2n þ 1Þ‘ lcŠ ð4 0 Þ u0 ½t ð2n þ 1Þ‘ lcŠ (

ð3:8:22Þ

Comparisons of the normalized end-of-line voltages obtained by the compact expression (3.8.20) with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements are shown in Fig. 3.8.5 [19]. For these comparisons, the interconnection metal is assumed to be copper surrounded by a low-k dielectric. The various interconnection parameters are as follows: Interconnection length 3.6 cm Interconnection cross section 2.1 mm  2.1 mm Resistance per unit length 37.9 /cm

1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0

0.0e+00

Normalized End of Line Voltage, V(L,t)/Vdd

HSPICE Simulation New Compact Expressions

2.0e–00

4.0e–10 6.0e–10 Time [sec] (a)

8.0e–10

Normalized End of Line Voltage, V(L,t)/Vdd

1.5 1.4 1.3

1.0e–09

1.5 1.4 1.3 1.2 1.1 1.0 0.9 HSPICE Simulation 0.8 New Compact Expressions 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0e+00 2.0e–00 4.0e–10 6.0e–10 8.0e–10 1.0e–09 Time [sec] (c)

Normalized End of Line Voltage, V(L,t)/Vdd

Normalized End of Line Voltage, V(L,t)/Vdd

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

223

1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6

HSPICE Simulation New Compact Expressions

0.5 0.4 0.3 0.2 0.1 0.0

0.0e+00

2.0e–00

4.0e–10 6.0e–10 Time [sec] (b)

8.0e–10

1.0e–09

1.5 1.4 1.3 1.2 1.1 1.0 0.9 HSPICE Simulation 0.8 New Compact Expressions 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0e+00 2.0e–00 4.0e–10 6.0e–10 8.0e–10 1.0e–09 Time [sec] (d)

FIGURE 3.8.5 Comparisons of normalized end-of-line voltages obtained by compact expression (3.8.20) with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements. (From [19]. # 2000 by IEEE.)

Driving source resistance 133.2

Lossless characteristic impedance 266.5

Figure 3.8.5 shows that the HSPICE waveforms approach the compact expression waveform as the number of RLC elements is increased in the HSPICE simulation. For the typical values of the interconnection and driving source parameters chosen in these comparisons, there is virtually complete agreement between the two waveforms for 500 or more RLC elements, lending excellent support to the compact expression (3.8.20). 3.8.4

Single RLC Interconnection: Delay Time

For a distributed RC interconnection line, Sakurai [57] has derived the following compact expression for the delay time defined as the time taken by the load voltage to reach 50% of its steady-state value: Td;RC ¼ 0:693RS c‘ þ 0:377rc‘2

ð3:8:23Þ

224

INTERCONNECTION DELAYS

For a distributed RLC interconnection line, this expression has been extended by Davis and Meindl as follows [19]: 8   ‘ R 4Z0 > > > pffiffiffiffi and RS < 3Z0 ð3:8:24Þ for  ln < RS þ Z0 Z0 lc   Td;RLC ¼ > R 4Z0 > 2 > or RS > 3Z0 ð3:8:25Þ :0:693RS c‘ þ 0:377rc‘ for  2 ln RS þ Z0 Z0

A comparison of the time delay obtained by the above closed-form expressions with that obtained from the compact RLC expression shows that the error in the simplified expression is less than 5% when RS =Z0 < 0:2 or when R=Z0 > 2:3. Outside this region, more accurate delay time can be obtained by using the compact distributed RLC expressions. 3.8.5

Two and Three Coupled RLC Interconnects: Delay Times

An analysis of two and three coupled RLC interconnects with open-circuit terminations [20] is presented in Chapter 4. For a system of two coupled distributed RLC interconnects A (active) and Q (quiet) shown in Fig. 3.8.6, the worst-case time delay occurs when the mutual capacitance between the lines is the highest, that is, when the two lines are switching with opposite polarities. The solution for the voltage in this case is given by V , which is effectively the solution for a single finite line with inductance l ¼ ðls lm Þ and capacitance c ¼ cs þ 2cm . It is given by VA ð‘; tÞ ¼ Vfin ð‘; t; l ¼ ls

lm ; c ¼ cgnd þ 2cm Þ

ð3:8:26Þ

For a system of three parallel coupled interconnects, each driven by a voltage source VS having an internal source resistance RS sandwiched between two virtual ground planes as shown in Fig. 3.8.7, the worst-case time delay occurs when the inner interconnection is active and the two outer lines simultaneously switch with an opposite polarity. After adjusting the initial and boundary conditions (see detailed analysis in Chapter 4), the load voltage waveform on the inner (active) interconnection is given by   4 1 ; c ¼ 2c þ 3c VA ð‘; tÞ ¼ Vfin ‘; t; l ¼ gnd m 3 ð2cgnd þ 3cm Þv2   1 1 ð3:8:27Þ Vfin ‘; t; l ¼ ; c ¼ 2c gnd 3 2cgnd v2

FIGURE 3.8.6 Two coupled distributed RLC interconnects A (active) and Q (quiet). (From [20]. # 2000 by IEEE.)

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

225

FIGURE 3.8.7 Three parallel coupled interconnects sandwiched between two virtual ground planes. (From [20]. # 2000 by IEEE.)

In Eqs. (3.8.26) and (3.8.27), Vfin ðx; tÞ represents the voltage waveform along a single interconnection line given by Vfin ð‘; tÞ ¼ 2Vinf ðx ¼ ‘; t; m ¼ 0Þ q X n X 1 X þ 2e r=ð2lÞt ð 1Þi

ðn iþjÞ

n¼1 i¼0 j¼0

Vinf ðx ¼ ð2n þ 1Þ‘; t; m ¼ iþ jÞ

nðn 1 þ jÞ! i!j!ðn iÞ! ð3:8:28Þ

where Vinf ðx; t; mÞ denotes the voltage waveform along the semi-infinite line given by pffiffiffiffi!m=2  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  pffiffiffiffi Z0 t x lc r pffiffiffiffi e r=ð2lÞt I0 t2 ðx lcÞ2 Vinf ðx; t; mÞ ¼ VS Z0 þ R S 2l t þ x lc !ðkþmÞ=2 p ffiffiffiffi 1 1X t x lc pffiffiffiffi þ e r=ð2lÞt ½4 ð1 þ Þ2 k 1 Š 2 k¼1 t þ x lc  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi r t2 ðx lcÞ2 uðt x lcÞ ð3:8:29Þ  IðkþmÞ 2l 

In the above analysis, we have assumed that the interconnects are open circuited at the load ends and the capacitance of the driving source has been neglected. It has been shown [21] that, for an interconnection driven by a large driver, neglecting the source capacitance causes about 5% error in the 50% delay time whereas neglecting both the driver and load capacitances results in an error of about 14%. For a detailed treatment of capacitively terminated single and coupled distributed RLC interconnects, readers are referred to [21].

226

3.9

INTERCONNECTION DELAYS

INTERCONNECTION DELAYS IN MULTILAYER INTEGRATED CIRCUITS

There has always been an interest in extending the concept of multilevel interconnections to 3D integrated circuits with active devices such as transistors, gates, cells, and so on, on several planes. The potential for fabricating IC chips with multiple planes of almost independent circuits [61–66] has been demonstrated by researchers by using silicon-on-insulator (SOI) techniques [67], and this can be called multilayer circuit (MLC) technology. In this section, a simplified model of interconnection delays in multilayer ICs [68] is presented. The interconnection delay in an MLC chip is normalized to that in an equivalent single-plane chip. This is followed by a study of the dependences of these interconnection delays on several parameters of the MLC chip, such as the number of devices on the chip, the number of circuit planes, the interconnection complexity, and the characteristics of the interconnection material. 3.9.1

The Simplified Model

For this analysis, a multilayer circuit is defined as one consisting of independent circuits on more than one plane; that is, an MLC chip looks like a stack of two or more independent chips with vertical interconnections between them. In other words, the placement of transistors and interconnections on each plane does not depend on the fabrication and other characteristics on other planes. An example of a four-layer MLC is shown in Fig. 3.9.1. Generally, aluminum is considered to be a suitable interconnection material for the top plane of an MLC chip while, for the other planes, the interconnection material is chosen from refractory metals, silicides, and polysilicon.

FIGURE 3.9.1 Schematic of four-layer MLC structure. (From [68]. # 1986 by IEEE.)

INTERCONNECTION DELAYS IN MULTILAYER INTEGRATED CIRCUITS

227

In this analysis, several simplifying assumptions are made. First, it is assumed that each plane of the MLC chip uses the same basis technology and that it is the same as that for the single-plane chip used for normalization. Next, it is assumed that the various devices are evenly divided among all planes of the MLC chip; that is, if n is the number of devices and p is the number of planes, then the number of devices on each plane is equal to n=p. It is further assumed that there exists an interconnection complexity factor m which represents the degree to which the interconnection complexity influences the circuit area and that m is the same for each plane. If k represents a technology-dependent normalization constant, then the chip area A is modeled as  m n ð3:9:1Þ A¼k p Therefore, when m ¼ 1, the total area required for constructing the MLC chip will be the same as that of the corresponding single-plane chip and, when m > 1, it will be less than that for the single-plane chip because of the reduction in fractional area required for the interconnections. A simple model for the interconnection delay t can be constructed in terms of the RC time constant associated with the interconnection line. For an interconnection of length L and width W, t can be written as   L ð3:9:2Þ ðcLWÞ ¼ rp cL2 t ¼ RC ¼ rp W where rp is the thin-film resistivity of the interconnection material and c is its capacitance per unit area. The fringing fields as well as the coupling capacitances with the neighboring conductors have been neglected. Obviously, the maximum interconnection delay is associated with the longest interconnection line, and an estimate of the maximum interconnection length Lp on any one plane of the MLC chip of area A is given by [62] pffiffiffi Lp ¼ 12 A ð3:9:3Þ Assuming that all planes of the MLC chip are equal in area, each plane can have interconnections of maximum length given by Eq. (3.9.3). If f is the number of planes that have interconnection lines to be driven by the same device, then the effective total length of the interconnection is given by Ltot, where Ltot ¼ fLp

1f p

ð3:9:4Þ

Combining Eqs. (3.9.1)–(3.9.4), an estimate of the maximum interconnection delay for the MLC chip is given by  m n tp ¼ rp cL2tot ¼ rp cf 2 L2p ¼ 14rp cf 2 A ¼ 14rp cf 2 k ð3:9:5Þ p

228

INTERCONNECTION DELAYS

TABLE 3.9.1 Thin-Film Resistivities of Interconnection Materials Thin-Film Resistivity (m
cm)

Material Aluminum Refractory metals Silicides Polysilicon

2 5–10 15–100 1000

r 1.0 2.5–5 7.5–50 500

Source: From [68]. # 1986 IEEE.

On the other hand, the time constant for the corresponding single-plane chip (p ¼ 1) is given by t1 ¼ 14r1 ckðnÞm1

ð3:9:6Þ

where r1 and m1 are the thin-film resistivity of the interconnection material and the interconnection complexity factor for the single-plane chip. Then, assuming that the capacitance per unit area c is the same for the single-plane and MLC chips, the ratio Rr of the maximum interconnection delay on the MLC chip to that on the singleplane chip becomes Rr ¼

m tp f 2 ðn=pÞ rp ¼ rf 2 ðpÞ ¼ ðnÞm1 r1 t1

m

ðnÞm

m1

ð3:9:7Þ

where r ¼ rp =r1 . Assuming that the single-plane chip uses aluminum interconnections, the thin-film resistivities [63] and the corresponding r values for aluminum, refractory metals, silicides, and polysilicon are listed in Table 3.9.1. 3.9.2

Simulation Results and Discussion

The dependences of the normalized interconnection delays on the interconnection complexity factor for several values of the number of circuit planes keeping r ¼ 1 and f ¼ 1 are shown in Fig. 3.9.2. The normalized interconnection delays as functions of the circuit size for several values of the interconnection complexity factor keeping r ¼ 3, f ¼ 1, m1 ¼ 1:2, and p ¼ 4 are shown in Fig. 3.9.3. Based on the discussion of MLC circuits presented in this section and from the results presented in Figs. 3.9.2 and 3.9.3, the following comments can be made: 1. Partitioning of the IC into virtually independent subcircuits fabricated on separate planes reduces the lengths of interconnection lines on any one plane, thereby reducing the interconnection delays. 2. When the availability of the third dimension in an MLC circuit permits the reduction of interconnection complexity factor m compared to m1 for a single-plane chip, the area per plane is reduced by a factor of p m nm m1 with a proportional reduction in the normalized interconnection delay Rr.

INTERCONNECTION DELAYS IN MULTILAYER INTEGRATED CIRCUITS

229

FIGURE 3.9.2 Dependences of normalized interconnection delays on interconnection complexity factor for several values of number of circuit planes. Fixed parameters: r ¼ 1 and f ¼ 1. (From [68]. # 1986 by IEEE.)

3. An important factor in maximizing the speed of an MLC is partitioning the original IC such that a device on a given plane drives a maximum-length interconnection on one plane only. This will minimize f and hence Rr because Rr / f 2 . 4. The assumptions made in the above analysis can be considered extrapolations of the best-case MLC technology. If these assumptions are modified to account for more realistic MLCs, the resulting interconnection delay will increase.

FIGURE 3.9.3 Dependences of normalized interconnection delays on circuit size for several values of interconnection complexity factor. Fixed parameters: r ¼ 3, f ¼ 1, m1 ¼ 1:2, and p ¼ 4. (from [68]. # 1986 by IEEE.)

230

3.10

INTERCONNECTION DELAYS

ACTIVE INTERCONNECTIONS

It has been known for some time that transistors can be scaled down in size in such a way that the device propagation delay decreases in direct proportion to the device dimensions. However, if the interconnections are scaled down, it results in RC delays that begin to dominate the IC chip performance at submicrometer dimensions. In other words, for the high-density, high-speed submicrometer geometry chips, it is mostly the interconnection rather than the device performance that determines the chip performance. So far, the interconnection delays have been reduced by using higher conductivity materials such as replacing aluminum with copper to lower the interconnection resistance, replacing silicon dioxide with a lowdielectric-constant material to lower the interconnection capacitance, and keeping the interconnection thickness almost constant irrespective of the scaling of devices. For example, in scaling from the 10- to the 1-mm design rules, the interconnection thicknesses were reduced by a factor of 2 or less. Now, because of the limitations of the optical lithography systems, it is essential that other approaches be developed to lower the interconnection delays. One way of solving this problem is to replace the passive interconnections on a chip by the active interconnections, that is, by inserting inverters or ‘‘repeaters’’ at appropriate spacings depending on the preferred driving mechanism. However, this technique does require more area on the chip and results in higher power consumption. In the literature [69, 70], several methods have been discussed for the reduction of transit delays in an interconnection. These include driving the interconnection using minimum-size inverters, optimum-size inverters, and cascaded inverters. An analysis of these driving methods for the silicon-based ICs is presented in [69]. In this section, these methods have been examined for the GaAs-based ICs [70]. Propagation times (time taken by the output signal to go from 0 to 90% of its steadystate value) have been calculated for each of these three methods for several interconnection dimensions and have been compared with each other and with the case when the interconnection is driven by a single typical GaAs MESFET. Results are given for two interconnection materials: aluminum with resistivity ðrÞ ¼ 3 m
cm and WSi2 with r ¼ 30 m
cm. 3.10.1

Interconnection Delay Model

An interconnection having total resistance Ri and capacitance Ci driven by a transistor of resistance Rs and driving a load capacitance CL is shown in Fig. 3.10.1. Assuming a unit step voltage source, the propagation times in distributed and lumped RC networks can be approximated as 1.0RC and 2:3RC, respectively [71]. Therefore, an approximate expression for the total delay in the interconnection shown in Fig. 3.10.1 will be T90% ¼ 1:0Ri Ci þ 2:3ðRs CL þ Rs Ci þ Ri CL Þ

ð3:10:1Þ

Ignoring the terms containing the load capacitance CL , we have T90%  Ri Ci þ 2:3Rs Ci

ð3:10:2Þ

ACTIVE INTERCONNECTIONS

231

FIGURE 3.10.1 Interconnection delay model. (From [69]. # 1985 by IEEE.)

This expression is in agreement with that derived by Sakurai [72]. Since both interconnection resistance and capacitance increase linearly with length, the propagation time expressed by Eq. (3.10.2) will increase nearly as the square of the interconnection length. It can be shown that this dependence can be made linear if the entire interconnection length is divided into smaller sections and each section is driven by a repeater. 3.10.2

Active Interconnection Driven by Minimum-Size Inverters

A schematic of an active interconnection driven by minimum-size inverters as repeaters is shown in Fig. 3.10.2. As shown in the figure, the use of inverters divides the interconnection into smaller subsections. The symbols used in the figure are: Ri ¼ total resistance of interconnection line Ci ¼ total capacitance of interconnection line Rr ¼ output resistance of minimum-size inverter Cr ¼ input capacitance of minimum-size inverter

FIGURE 3.10.2 Schematic of interconnection driven by minimum-size inverters. (From [69]. # 1985 by IEEE.)

232

INTERCONNECTION DELAYS

Rs ¼ resistance of GaAs MESFET CL ¼ load capacitance n ¼ number of inverters To achieve the shortest total propagation time using minimum-size inverters, the optimum number of inverters can be found using calculus to be [69] rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Ri C i n¼ 2:3Rr Cr

ð3:10:3Þ

The propagation time for each subsection driven by the minimum-size inverters can be determined using the algorithm presented in Section 3.2, whereas the additional delay caused by the first stage can be found by the approximate expression for lumped RC networks given by Wilnai [71] to be 2:3Rs Cr . The computer program IPDMSR for determining the propagation time in an active interconnection driven by minimum-size repeaters is given in Appendix 3.2 on the accompanying ftp site. The results using aluminum as the interconnection material are listed in Tables 3.10.1 and 3.10.2 whereas those using WSi2 as the interconnection material are listed in Tables 3.10.3 and 3.10.4. 3.10.3

Active Interconnection Driven by Optimum-Size Inverters

Propagation times can be improved by increasing the size of the inverters by a factor of k, where k is given by [69] k¼

rffiffiffiffiffiffiffiffiffi Rr Ci Ri Cr

ð3:10:4Þ

TABLE 3.10.1 Propagation Times in Four Driving Methods for Selected Interconnection Lengths Interconnection Length 1 mm 2 mm 5 mm 1 cm 2 cm 5 cm 10 cm

GaAs MESFET (ns) 0.05 0.08 0.17 0.33 0.80 3.5 15.1

Minimum-Size Repeaters (ns)

Optimum-Size Repeaters (ns)

—a —a 2.31 4.16 7.87 18.98 37.51

—a —a 0.11 0.20 0.29 0.54 0.97

Cascaded Drivers (ns) 0.24 0.27 0.34 0.46 0.76 2.79 11.49

Note: Interconnection material aluminum (r ¼ 3 m
cm). Interconnection width ¼ interconnection separation ¼ 1 mm; load ¼ 100 fF; source resistance ¼ 700 . a

For interconnect lengths below 2 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

233

ACTIVE INTERCONNECTIONS

TABLE 3.10.2 Propagation Times in Four Driving Methods for Selected Interconnection Widths Interconnection Width (mm) 0.1 0.2 0.5 1.0 2.0 5.0 10.0

GaAs MESFET (ns) 0.98 0.50 0.39 0.33 0.31 0.25 0.27

Minimum-Size Repeaters (ns) 3.01 3.10 3.56 4.03 4.5 —a —a

Optimum-Size Repeaters (ns)

Cascaded Drivers (ns)

0.04 0.08 0.15 0.20 0.35 —a —a

0.85 0.52 0.38 0.46 0.70 1.38 2.39

Note: Interconnection material aluminum (r ¼ 3 m
cm). Interconnection length ¼ 1 cm; load ¼ 100 fF; source resistance ¼ 700 . a

For interconnect widths above 5.0 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

This is because the current driving capability of the inverter is directly proportional to its width–length ratio. When this ratio is increased by a factor of k, the output resistance of the inverter becomes Rr =k and the input capacitance of the inverter becomes kCr . A schematic of an active interconnection driven by optimum-size inverters is shown in Fig. 3.10.3. In this case, the additional delay caused by the first stage will be approximately 2:3kRs Cr. The computer program IPDOSR for determining the propagation time in an active interconnection driven by optimum-size repeaters is given in Appendix 3.3 on the accompanying ftp site. The total propagation times for this case are also listed in Tables 3.10.1–3.10.4.

TABLE 3.10.3 Propagation Times in Four Driving Methods for Selected Interconnection Lengths Interconnection Length 1 mm 2 mm 5 mm 1 cm 2 cm 5 cm 10 cm

GaAs MESFET (ns) 0.07 0.14 0.41 1.35 4.62 9.6 19.98

Minimum-Size Repeaters (ns)

Optimum-Size Repeaters (ns)

Cascaded Drivers (ns)

—a 1.11 2.14 3.85 7.28 17.55 34.69

—a 0.13 0.23 0.39 0.71 1.67 3.26

0.27 0.34 0.62 1.42 4.49 22.3 80.28

Note: Interconnection material WSi2 (r ¼ 30 m
cm). Interconnection width ¼ interconnection separation ¼ 1 mm; load ¼ 100 fF; source resistance ¼ 700 . a

For interconnect lengths below 2 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

234

INTERCONNECTION DELAYS

TABLE 3.10.4 Propagation Times in Four Driving Methods for Selected Interconnection Widths Interconnection Length (mm) 0.1 0.2 0.5 1.0 2.0 5.0 10.0

GaAs MESFET (ns)

Minimum-Size Repeaters (ns)

Optimum-Size Repeaters (ns)

8.9 5.0 2.21 1.35 0.8 0.52 0.36

2.79 2.99 3.5 3.82 4.34 5.23 6.34a

0.05 0.09 0.38 0.39 0.42 0.56 0.82a

Cascaded Drivers (ns) 10.6 5.85 2.18 1.42 1.19 1.59 2.48

Note: Interconnection material WSi2 (r ¼ 30 m
cm). Interconnection width ¼ interconnection separation ¼ 1 mm; load ¼ 100 fF; source resistance ¼ 700 .

a For interconnect widths above 10 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

3.10.4

Active Interconnection Driven by Cascaded Inverters

A schematic of an active interconnection driven by cascaded inverters is shown in Fig. 3.10.4. In this case, instead of a single driver, a chain of inverters is used that increase in size until the last inverter is large enough to drive the interconnection. The optimal delay is obtained using a sequence of n inverters that increase gradually in size (each by a factor of 2.71828 over the previous one). The optimum value of n is given by [69]   Ci n ¼ ln Cr

ð3:10:5Þ

FIGURE 3.10.3 Schematic of interconnection driven by optimum-size inverters. (From [69]. # 1985 by IEEE.)

ACTIVE INTERCONNECTIONS

235

FIGURE 3.10.4 Schematic of interconnection driven by cascaded drivers. (From [69]. # 1985 by IEEE.)

In this case, the additional delay caused by the first stage and the first n is given approximately by 2:3Rs Cr þ 2:3ð2:71828Þðn

1ÞRr Cr

1 inverters

ð3:10:6Þ

and the propagation time in the interconnection driven by the last inverter can be found using the algorithm presented in Section 3.2. The program IPDCR for determining the propagation time in an active interconnection driven by cascaded repeaters is given in Appendix 3.4 on the accompanying ftp site. The results for this case are listed in Tables 3.10.1–3.10.4. 3.10.5

Dependence of Propagation Time on Interconnection Driving Mechanism

A comparison of the propagation times for each of the four methods of driving an interconnection—that is, using a single GaAs MESFET, minimum-size inverters, optimum-size inverters, and cascaded inverters—for several values of the interconnection lengths in the range 1 mm–10 cm is shown in Table 3.10.1. For these results, the interconnection material is taken to be aluminum and the other parameters are shown in the table. This table shows that minimum- and optimumsize inverters cannot be used to drive interconnections of lengths 2 mm and below. Otherwise, among the four methods, using optimum-size inverters yields the lowest propagation times. For interconnection lengths of 1 and 2 mm, using a single GaAs MESFET results in lower propagation times than using cascaded inverters. Table 3.10.2 shows the propagation times for each of the four methods for several interconnection widths in the range 0.1–10.0 mm. This table shows that the methods of using minimum- and optimum-size inverters are not suitable for interconnection widths of 5 mm and above. Otherwise, for interconnection widths below about 1 mm, using optimum-size inverters results in the lowest propagation times among the four

236

INTERCONNECTION DELAYS

methods. For interconnection widths between 2 and 10 mm, using a single GaAs MESFET yields the lowest propagation times. When the interconnection material is changed to WSi2, propagation times for the four methods of driving an interconnection for several values of interconnection length and interconnection width are shown in the Tables 3.10.3 and 3.10.4, respectively. These tables show that, in this case, minimum- and optimum-size inverters cannot be used for interconnection lengths of 1 mm and below and for interconnection widths above 10 mm. Using optimum-size inverters is found to result in the lowest propagation times for all interconnection lengths (see Table 3.10.3) and for interconnection widths below 5 mm (see Table 3.10.4). For interconnection widths above 5 mm, driving the interconnection with a single GaAs MESFET results in the lowest propagation times. EXERCISES E3.1 List and discuss the desirable characteristics of a numerical model that make it more suitable for inclusion in a CAD tool. Review the techniques presented in this chapter from the point of view of their suitability for inclusion in a CAD tool. E3.2 Comment on the validity of the assumptions and approximations used in the analysis of crossing interconnections in Section 3.4. E3.3 Refering to Section 3.7, comment on the relative significance of the highfrequency losses in an aluminum interconnection on GaAs in the following frequency ranges: (a) below 10 MHz; (b) 10 MHz–1 GHz; (c) 1–10 GHz; (d) 10– 100 GHz; and (e) above 100 GHz. E3.4 Show that for the shortest total propagation time using minimum-size inverters the optimum number of inverters is given by the expression (symbols are defined in Section 3.10.2) rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Ri C i n¼ 2:3Rr Cr E3.5 Show that the value of k for optimum-size inverters is given by the expression (symbols defined in Section 3.10.3) rffiffiffiffiffiffiffiffiffi Rr Ci k¼ Ri Cr E3.6 Show that the optimal delay is obtained by using a sequence of n inverters that increase gradually in size (each by a factor of 2.71828 over the previous one), where n is given by the expression (symbols defined in Section 3.10.4)   Ci n ¼ ln Cr

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16. A. K. Goel, ‘‘Transit Times in the High-Density Interconnections on GaAs-Based VHSIC,’’ IEE Proc., vol. 135, pt. I, no. 5, pp. 129–135, Oct. 1988. 17. A. K. Goel and Y. R. Huang, ‘‘Efficient Characterization of Multilevel Interconnections on the GaAs-Based VLSIC’s,’’ Microwave Opt. Tech. Lett., vol. 1, no. 7, pp. 252–257, 1988. 18. K. W. Goossen and R. B. Hammond, ‘‘Modeling of Picosecond Pulse Propagation in Microstrip Interconnections on Integrated Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. 37, no. 3, pp. 469–478, Mar. 1989. 19. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part I: Single Line Transient, Time Delay and Overshoot Expressions,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2068–2077, Nov. 2000. 20. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multivel Networks,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2078–2087, Nov. 2000. 21. R. Venkatesaran, J. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part III: Transients in Single and Coupled Lines with Capacitive Load Termination,’’ IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1081–1093, Apr. 2003. 22. R. Venkatesan, J. A. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part IV: Unified Models for Time Delay, Crosstalk and Repeater Insertion,’’ IEEE Trans. Electron Devices, vol. 50, pp. 1094–1102, Apr. 2003. 23. F. Y. Chang, ‘‘Transient Simulation of Nonuniform Coupled Lossy Transmission Lines Characterized with Frequency-Dependent Parameters—Part I: Waveform Relaxation Analysis,’’ IEEE Trans. Circuits Syst., vol. 39, pp. 585–603, Aug. 1992. 24. F. Y. Chang, ‘‘Transient Simulation of Nonuniform Coupled Lossy Transmission Lines Characterized with Frequency-Dependent Parameters—Part II: Discrete-Time Analysis,’’ IEEE Trans. Circuits Syst. I, vol. 39, pp. 907–927, Nov. 1992. 25. J. E. Bracken, V. Raghavan, and R. A. Rohrer, ‘‘Interconnect Simulation with Asymptotic Waveform Evaluation (AWE),’’ IEEE Trans. Circuits Syst. I, vol. 39, pp. 869–878, Nov. 1992. 26. L. M. Silveira, I. M. Elfadel, J. K. White, M. Chilukuri, and K. S. Kundert, ‘‘Efficient Frequency-Domain Modeling and Circuit Simulation of Transmission Lines,’’ IEEE Trans. Comp. Packag. Manufact. Technol. B, vol. 17, pp. 505–513, Nov. 1994. 27. D. B. Kuznetsov and J. E. Schutt-Aine, ‘‘Optimal Transient Simulation of Transmission Lines,’’ IEEE Trans. Circuits Syst. I, vol. 43, pp. 110– 121, Feb. 1996. 28. J. S. Roychowdhury, A. R. Newton, and D. O. Pederson, ‘‘Algorithms for the Transient Simulation of Lossy Interconnect,’’ IEEE Trans. Computer Aided Design, vol. 13, pp. 96– 104, Jan. 1994. 29. Y. I. Ismail and E. G. Friedman, ‘‘Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits,’’ IEEE Trans. VLSI Syst., vol. 8, pp. 195–206, Apr. 2000. 30. Y. Cao, X. Huang, D. Sylvester, N. Chang, and C. Hu, ‘‘A New Analytical Delay and Noise Model for On-Chip RLC Interconnect,’’ Proc. IEDM, San Francisco, CA, 2000, pp. 823– 826.

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49. K. W. Goossen and R. B. Hammond, ‘‘Modeling of Picosecond Pulse Propagation in Microstrip Interconnections on Integrated Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. 37, no. 3, pp. 469–478, Mar. 1989. 50. D. G. Corr and J. B. Davies, ‘‘Computer Analysis of Fundamental and Higher Order Modes in Single and Coupled Microstrip,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-20, pp. 669–678, 1972. 51. M. V. Schneider, ‘‘Microstrip Lines for Microwave Integrated Circuits,’’ Bell Syst. Tech. J., vol. 48, p. 1421, 1969. 52. K. C. Gupta, R. Garg, and R. Chadha, Computer-Aided Design of Microwave Circuits, Dedham, MA: Artech House, 1981, p. 62. 53. E. Yamashita, K. Atsuki, and T. Ueda, ‘‘An Approximate Dispersion Formula of Microstrip Lines for Computer-Aided Design of Microwave Integrated Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-27, p. 1036, 1979. 54. R. A. Pucel, D. J. Masse and C. P. Hartwig, ‘‘Losses in Microstrip,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-16, p. 342, 1968. 55. J. D. Welch and H. J. Pratt, ‘‘Losses in Microstrip Transmission Systems for Integrated Microwave Circuits,’’ NEREM Rec., vol. 8, p. 100, 1966. 56. A. K. Goel and S. Weitemeyer, ‘‘Modeling of Very High-Frequency Effects in the VLSI Interconnections,’’ Microwave Opt. Tech. Lett., vol. 31, no. 3, pp. 229–233, Nov. 2001. 57. T. Sakurai, ‘‘Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI’s,’’ IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118–124, Jan. 1993. 58. T. Sakurai, ‘‘Approximation of Wiring Delay in MOSFET LSI,’’ IEEE J. Solid-State Circuits, vol. SC-18, no. 4, pp. 418–426, Aug. 1983. 59. W. C. Elmore, ‘‘The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,’’ J. Appl. Phys., vol. 19, pp. 55–63, Jan. 1948. 60. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Reading, MA: Addison-Wesley, 1990. 61. S. Kawamura et al., ‘‘Three-Dimensional CMOS IC’s Fabricated by Using Beam Recrystallization,’’ IEEE Electron Devices Lett., vol. EDL-4, p. 366, 1983. 62. S. Akiyama et al., ‘‘Multilayer CMOS Device Fabricated on Laser Recrystallized Silicon Islands,’’ IEDM Tech. Dig., p. 352, 1983. 63. Y. Akasaka et al., ‘‘Integrated MOS Devices in Double Active Layers,’’ Proc. Symp. VLSI Technol., p. 90, 1984. 64. M. Nakano, ‘‘3-D SOI/CMOS,’’ IEDM Tech. Dig., p. 792, 1984. 65. S. Kataoka, ‘‘An Attempt Towards an Artificial Retina: 3-D Technology for an Intelligent Image Sensor,’’ Proc. Int. Conf. Solid State Sensors and Actuators, p. 440, 1985. 66. K. Sugahara et al., ‘‘SOI/SOI/Bulk-Si Triple-Level Structure for Three-Dimensional Devices,’’ IEEE Electron Devices Lett., vol. EDL-7, p. 193, 1986. 67. D. A. Antoniadis, ‘‘Three-Dimensional Integrated Circuit Technology,’’ Proc. Materials Res. Soc. Meeting, Nov. 1983. 68. A. L. Robinson, L. A. Glasser, and D. A. Antoniadis, ‘‘A Simple Interconnect Delay Model for Multilayer Integrated Circuits,’’ Proc. IEEE VLSI Multilevel Interconnection Conf., pp. 267–273, 1986.

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CHAPTER FOUR

Crosstalk Analysis Continuous advancements in the field of very large scale integrated circuits (VLSICs) and very high speed integrated circuits (VHSICs) have resulted in smaller chip sizes, smaller device geometries, and millions of closely spaced interconnections in one or more levels that connect the various components on the chip. There are continuous customer demands for higher speeds in the areas of signal processing, high-speed computation, data links, and related instrumentation. Crosstalk among the interconnections in single as well as multilevel configurations has become a major problem in the development of the next-generation high-speed integrated circuits. In the literature, modeling and analysis of coupled interconnections have received considerable attention. Several authors have used multiconductor transmission line theory [1–7] and the analysis of coupled lossy transmission lines has also been reported [8–10]. Nonlinearity of the source and load networks has been addressed by several workers [6, 9, 11]. Plenty of effort has been made to get closed-form expressions for the signal waveforms on two or three coupled interconnections. For example, the analytical solutions valid for weak-coupling cases (because they ignore the second-degree coupling) are reported [10, 12, 13] and formulas for voltage transfer functions for a two-line system without the weak-coupling assumption are presented [14]. Closed-form solutions for a system of N lossless lines using cyclic boundary conditions are developed [15] and a general crosstalk analysis technique without making the weak coupling or cyclic boundary condition assumption is presented [16]. Crosstalk analysis of parallel multilevel interconnections on GaAsbased ICs is presented [17, 18], and an analysis of bilevel crossing interconnections has been carried out [19, 20]. Recently, attention has focused on developing compact models for the transient analysis of distributed RLC interconnections [21–24]. This chapter is organized as follows:

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

242

LUMPED-CAPACITANCE APPROXIMATION

243

 Crosstalk among the neighboring interconnections is studied using a lumpedcapacitance approximation in Section 4.1.  Crosstalk in very high-speed VLSICs is analyzed using a coupled multiconductor MIS microstripline model for the interconnections in Section 4.2.  Single-level interconnections have been investigated by the frequency-domain modal analysis in Section 4.3.  A transmission line model of crosstalk effects in single-, bi-, and trilevel highdensity interconnections on GaAs-based VHSICs is presented in Section 4.4.  An analysis of crossing bilevel interconnections on GaAs-based ICs is presented in Section 4.5.  Closed-form expressions for crosstalk waveforms using distributed RC and RLC interconnection models are presented in Section 4.6.  Crosstalk effects in multiconductor buses in high-speed GaAs logic circuits are analyzed in Section 4.7.

4.1

LUMPED-CAPACITANCE APPROXIMATION

The lumped-capacitance model of two interconnections coupled by the capacitance Cc is shown in Fig. 4.1.1, where C denotes the ground capacitance of each interconnection. The first interconnection is driven by the unit voltage source of resistance Rs on the left and terminated by the load capacitance CL on the right. The second interconnection is terminated by the resistance Rs on the left and the load capacitance CL on the right. Crosstalk voltage is defined as the voltage V2 ðtÞ induced across the load CL on the second interconnection. It can be shown that the amplitude of the crosstalk voltage at time t is given by V2 ðtÞ ¼ 12½e

t=t1

e

t=t2

Š

ð4:1:1Þ

FIGURE 4.1.1 Lumped-capacitance model of two interconnections coupled by capacitance Cc . (From [5]. # 1984 by IEEE.)

244

CROSSTALK ANALYSIS

where t1 ¼ RðC þ CL Þ

t2 ¼ Rð2Cc þ C þ CL Þ

ð4:1:2Þ

Using calculus, it can be shown that the maximum value of the crosstalk voltage is given by V2;max

     1 nc 1 1 þ nc ln ¼ exp 1 nc 2 2nc

exp



   nc þ 1 1 þ nc ln 1 nc 2nc

ð4:1:3Þ

where the capacitance coupling coefficient nc is given by nc ¼

Cc C þ Cc þ CL

ð4:1:4Þ

Based on the lumped-capacitance model, the dependences of the crosstalk voltage V2 on time in the range 0–500 ps for interconnections of widths and separation equal to 2 mm and lengths of 1 and 3 mm are shown in Fig. 4.1.2. Figure 4.1.2 also shows the dependence of the maximum crosstalk voltage on the coupling coefficient nc in the range 0–1. It will be shown in the next section that the ‘‘lumped-capacitance’’ approximation becomes inadequate in high-speed circuits. In fact, it can be shown that this approximation is applicable for interconnections which are at least a few millimeters long and the circuit rise time is above 200–300 ps.

FIGURE 4.1.2 Crosstalk waveform and amplitude derived from lumped-capacitance approximation. (From [5]. # 1984 by IEEE.)

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

4.2

245

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL OF SINGLE-LEVEL INTERCONNECTIONS

In this section, a system of parallel single-level interconnections is modeled as a coupled multiconductor MIS microstripline system having many conductors [5]. Interconnections are formed on a surface-passivated semiconductor substrate with a metallized back. This model is particularly suitable for situations where many closely spaced interconnections run parallel for a long time, such as in the semicustom gate array shown in Fig. 4.2.1. For simplicity, losses in the semiconductor substrate are ignored, making the model specially applicable to interconnections on semi-insulating GaAs or InP or silicon-on-sapphire substrates. 4.2.1

The Model

The MIS microstripline model for a system of n strip conductors is shown in Fig. 4.2.2a. To incorporate the boundary conditions existing on both sides of the stripline system, a periodic boundary condition is adopted where it is assumed that the same system of n stripline conductors is repeated indefinitely, as shown in

FIGURE 4.2.1

Schematic of semicustom gate array. (From [5]. # 1984 by IEEE.)

246

CROSSTALK ANALYSIS

FIGURE 4.2.2 (a) Coupled multiconductor MIS microstripline model having n conductors. (b) Periodic boundary condition applied to model. (From [5]. # 1984 by IEEE.)

Fig. 4.2.2b. This periodic boundary condition is quite useful for providing a firstorder estimate of crosstalk without going into the specific layout design details. Now, on this n-conductor stripline system, there exist n quasi-TEM modes. Consider a mode, called the y mode, where the phase angle difference of voltage and current between two adjacent conductors is constant and equal to y. Possible values of y that satisfy the periodic boundary condition are given by y ¼ 0;

2p 2kp 2ðn 1Þp ;...; ;...; n n n

ð4:2:1Þ

Then the characteristic impedance Z0y and the phase velocity vy of the y mode are given by 1 vy Cy  1=2 Cy0 vy ¼ c 0 Cy

Z0y ¼

ð4:2:2aÞ ð4:2:2bÞ

where c0 is the velocity of light in a vacuum and Cy and cy0 are the static capacitances of the y mode per conductor per unit length with and without the dielectric loadings, respectively. The static mode capacitances can be found by the Green’s function method. The Green’s function on the strip plane (y ¼ 0 in Fig. 4.2.2b) for the y mode,

247

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

denoted by Gy ðx; x0 Þ, is defined as the potential at a point x on the strip plane when a unit charge with a phase factor of e jmy is placed at points x0 þ mp, where m ¼ 0; 1; 2; . . . ; 1 and p is the pitch in Fig. 4.2.2b. Yamashita et al. have determined Gy ðx; x0 Þ by making a Fourier transformation of the 2D Laplace equation and solving the resultant equation with respect to y, resulting in Gy ðx; x0 Þ ¼

1 X e

m¼ 1



jbm ðx x0 Þ

pjbm j

e1 cothðb1 bm Þ þ e2 cothðb2 bm Þ  ½e2 cothðb2 bm ފ½e0 þ e1 cothðb1 bm ފ þ e1 ½e1 þ e1 cothðb1 bm ފ

 ð4:2:3Þ

where bm ¼

2mp þ y p

Then, the potential on the strip under consideration, denoted by V0, can be found from the charge density function ry ðxÞ for the y mode at point x on the strip conductor by solving the following equation numerically: V0 ¼

Z

a=2 a=2

Gy ðx; x0 Þry ðx0 Þ dx0

ð4:2:4Þ

Then, the static capacitance of the y mode per conductor will be given by Cy ¼

1 V0

Z

a=2 a=2

ry ðxÞ dx

ð4:2:5Þ

The voltage and current on the kth conductor can be expressed in terms of the normal modes defined above by the equations X Vk ðzÞ ¼ Ayf e

jðk 1Þy jo½t ðz=vy ފ

e

y

Ik ðzÞ ¼

X Ayf y

Z0y

e

jðk 1Þy jo½t z=vy ފ

e

þ Ayr e Ayr e Z0y

jðk 1Þy joðtþz=vy Þ

e



ð4:2:6Þ



ð4:2:7Þ

jðk 1Þy joðtþz=vy Þ

e

where z denotes the position on the conductor, o is the angular frequency, and Ayf and Ayr are the amplitudes of the forward and backward voltage waves in the y mode. The mode wave amplitudes Ayf and Ayr can be determined using the known terminal conditions at both ends of each strip conductor. The values of voltage and current in the time domain can be found by an inverse Laplace transformation of the above equations.

248

CROSSTALK ANALYSIS

FIGURE 4.2.3 Calculated characteristic impedance Z0y of various modes. (From [5]. # 1984 by IEEE.)

4.2.2

Numerical Simulations

In the following results [5], unless otherwise specified, it is assumed that the interconnections are of width a ¼ 2 mm, the substrate is of thickness b2 ¼ 200 mm and relative permittivity e2 ¼ 12, and the insulator is of thickness b1 ¼ 1 mm and relative permittivity e1 ¼ 4. First, for the case of b1 ¼ 0 and b2 ¼ 1, the dependences of the characteristic impedance Z0y on the width-to-pitch ratio (a=p) for various values of y are shown in Fig. 4.2.3. It is interesting to note the high-impedance nature of the interconnection system even for a typical practical case when a ¼ 2 mm, p ¼ 4 mm, and b2 ¼ 200 mm. This is because of the relatively small value of a=b2 (which leads to a smaller value of the ground capacitance). For a system of 10 semi-infinite interconnections with a unit step voltage applied to the input end of the first interconnection and the input ends of other interconnections open circuited, the induced voltage Vi on the ith interconnection is plotted versus i in Fig. 4.2.4. It can be seen that the voltage applied to one line tends to have its effect over a long range. This is because of the small shielding effect of the metallized back plane, which in turn is due to a small value of the a=b2 ratio. For a system of five semi-infinite interconnections, the dependence of the induced voltage at an adjacent strip on the interconnection spacing s ð¼ p aÞ is shown in Fig. 4.2.5. The long-range nature of the induced voltage can again be noted.

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

249

FIGURE 4.2.4 Calculated crosstalk amplitude at ith interconnection for system of 10 semiinfinite interconnections. (From [5]. # 1984 by IEEE.)

For a system of five finite-length interconnections with the excitation and loading conditions shown in the inset of Fig. 4.2.6, the crosstalk voltage waveform across the load capacitance of interconnection 4 is shown in Fig. 4.2.6. The waveform shows an initial time delay (due to the propagation of wavefront) followed by ringing-type decaying oscillation superposed by ripplelike smaller oscillations. These small oscillations are caused by the velocity mismatches among the various modes involved. For the sake of comparison, the corresponding waveform calculated by the lumped-capacitance approximation (using the network shown in the inset) is also

FIGURE 4.2.5 Crosstalk amplitude at adjacent interconnection versus spacing for system of 5 semi-infinite interconnections. (From [5]. # 1984 by IEEE.)

250

CROSSTALK ANALYSIS

FIGURE 4.2.6 Calculated step response waveforms. The dashed curve is the waveform using the lumped-capacitance approximation. (From [5]. # 1984 by IEEE.)

included in Fig. 4.2.6, which shows that, as stated earlier, this approximation is not adequate for high-speed circuits. Figure 4.2.7 shows the dependences of the amplitudes of the crosstalk waveforms on the interconnection lengths for two sets of terminal conditions shown in the insets. This figure shows that the presence of floating interconnections increases the crosstalk amplitude because it effectively increases mutual coupling by reducing the line capacitances. For a system of five finite-length interconnections, the crosstalk voltage waveforms for signal source resistance Rs of 5 k , 700 , and 10 are shown in

FIGURE 4.2.7 Crosstalk amplitude versus interconnection length for two systems of five interconnections with different terminal conditions. (From [5]. # 1984 by IEEE.)

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

251

FIGURE 4.2.8 (a) Crosstalk waveforms for different values of signal source resistance Rs . (b) Crosstalk amplitude versus Rs . (From [5]. # 1984 by IEEE.)

Fig. 4.2.8a. The dependence of the maximum crosstalk voltage on the source resistance in the range 10–10,000 is shown in Fig. 4.2.8b. These figures show that the oscillations become more dominant and determine the crosstalk amplitude as the signal source resistance is reduced. As Rs is reduced down to a few tens of ohms, multiple reflections of the wavefront appear at the initial times, and the first negative peak of this transient determines the amplitude of the crosstalk waveform. The result calculated using the lumped-capacitance approximation is also included in Fig. 4.2.8b, which shows that this approximation is valid when Rs is above 2– 3 k and the response is slow. 4.2.3

Crosstalk Reduction

The above results suggest that for reliable operation of very high speed VLSI circuits with sufficient noise margins, it is very important to consider methods of reducing crosstalk. One method of reducing crosstalk is to reduce the substrate thickness in

252

CROSSTALK ANALYSIS

FIGURE 4.2.9 Crosstalk coupling coefficient versus spacing for several values of substrate thickness. (From [5]. # 1984 by IEEE.)

order to provide a solid shielding ground plane in close vicinity to the interconnections. However, this method will be effective only if the substrate thickness is reduced below 10 mm. This is clear from Fig. 4.2.9, which shows the dependence of the crosstalk coupling coefficient on spacing for several values of substrate thickness. Reducing substrate thickness below 10 mm may not be practically possible unless a new technology, such as silicon on insulator (SOI) is used. Crosstalk can also be reduced by providing shielding ground lines adjacent to the active interconnections. This is a very effective method, as shown by Fig. 4.2.10, which gives the dependences of the crosstalk voltage on spacing for two systems of five interconnections with and without the shielding ground lines between the

FIGURE 4.2.10 Effect of shielding lines on crosstalk. (From [5]. # 1984 by IEEE.)

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

253

FIGURE 4.2.11 Waveforms at centers of adjacent line ðV2 Þ, shielding line ðVS Þ, and active line ðV3 Þ. (From [5]. # 1984 by IEEE.)

interconnections. The drawback of this method is that it significantly reduces the wiring channel capacity, particularly when the availability of interconnection capacity is itself a big problem in the design of VLSI circuits. It is interesting to note that the potential on a narrow shielding line is not zero all along the line even if it is grounded on both ends. This is clear from Fig. 4.2.11, which shows the waveforms at the centers of the adjacent line, the shielding line, and the active line.

4.3

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

In this section, a general technique for analyzing crosstalk in coupled single-level lossless interconnections [16] is presented. The analysis is carried out without

254

CROSSTALK ANALYSIS

FIGURE 4.3.1 Schematic of system of N coupled interconnection lines. (From [16]. # 1990 by IEEE.)

making the weak-coupling or cyclic boundary condition assumption. First, modal analysis has been done in the frequency domain to obtain the closedform expressions for the voltage and current transfer functions. Then the transfer function is expanded into its Taylor series and the inverse Fourier transformation is applied to the terms considered significant depending on the accuracy desired in the solution. 4.3.1

General Technique

Consider the system of N interconnection lines shown in Fig. 4.3.1. Let ½CŠ, ½LŠ, and ½RŠ denote the capacitance, inductance, and resistance matrices of the system. Further, let En ðtÞ, ZGn , and ZLn denote the input signal, the source impedance, and the load impedance for the nth line, where n ¼ 1; 2; . . . ; N. Let ‘ be the length of each interconnection line. We define the series impedance matrix ½ZŠ and the parallel admittance matrix ½YŠ as ½ZŠ ¼ ½RŠ þ jo½LŠ and ½YŠ ¼ jo½CŠ. The N propagation modes that exist in a system of N conductors are defined by N complex modal propagation constants gn ¼ an þ jobn , where n ¼ 1; 2; . . . ; N. Then elements of the voltage eigenvector matrix ½Sv Š are solutions of the eigenvalue equation ðg2 ½IŠ þ ½ZŠ½YŠÞ½Sv Š ¼ ½0Š

ð4:3:1Þ

and the current eigenvector matrix ½SI Š is given by ½SI Š ¼ ½ZŠ 1 ½Sv Š½ Š

ð4:3:2Þ

where ½IŠ is the identity matrix and ½ Š ¼ diagfg1 ; g2 ; . . . ; gn g. The characteristic impedance matrix ½Zc Š is given by ½Sv Š½SI Š 1 and the characteristic admittance matrix ½Yc Š is equal to ½Zc Š 1 . Then the voltage and current vectors on the interconnection

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

255

line can be expressed in terms of ½Sv Š and ½SI Š as ½Vðxފ ¼ ½Sv Šð½Wi ðxފ þ ½Wr ðxފ ½Iðxފ ¼ ½Yc Š½Sv Šð½Wi ðxފ

ð4:3:3Þ

½Wr ðxފÞ

ð4:3:4Þ

where ½Wi ðxފ ¼ ½Wi;n ð0Þðe

gn x

½Wr ðxފ ¼ ½Wr;n ð0Þðegn x ފ

ފ

ð4:3:4aÞ

and Wi;n and Wr;n are the amplitudes of the incident and reflected components of the nth mode. The voltage and current vectors satisfy the boundary conditions ½ZG Š½Ið0ފ

½Vð0ފ ¼ ½EŠ

½Vð‘ފ ¼ ½ZL Š½Ið‘ފ

ð4:3:5Þ

where ½EŠ ¼ ½En Š, ½ZG Š ¼ diagfZG1 ; ZG2 ; . . . ; ZGN g, ½ZL Š ¼ diagfZL1 ; ZL2 ; . . . ; ZLN g, En is the input voltage signal applied to the nth line, ZGn is the internal impedance of the nth input signal source, and ZLn is the load impedance of the nth line. Substituting Eqs. (4.3.3) and (4.3.4) into Eq. (4.3.5), we obtain the following linear equations for ½Wi ð0ފ and ½Wr ð0ފ: "

½Sv Š þ ½ZG Š½SI Š ð½Sv Š

½Sv Š

½ZG Š½SI Š

½ZL Š½SI Š½PŠ ð½Sv Š þ ½ZL Š½SI ŠÞ½PŠ

1

#"

½Wi ð0ފ ½Wr ð0ފ

#

¼

"

½EŠ ½0Š

#

ð4:3:6Þ

where ½PŠ ¼ diagfexpð gnl Þg. After solving Eq. (4.3.6) for ½Wi ð0ފ and ½Wr ð0ފ, the voltage and current transfer functions can be determined from the voltage and current spectra obtained from Eq. (4.3.3). In general, first, the voltage and current are calculated at a finite number of discrete frequencies and then the time-domain waveforms are obtained using the fast Fourier transform (FFT) technique. If the lines can be considered lossless and are terminated at one or both ends by the line characteristic impedances, then analytical inverse Fourier transformation can be used to obtain the closed-form expressions for the time-domain waveforms as shown below for two-, three-, and four-line systems. 4.3.2

Two-Line System

The capacitance and inductance matrices for a two-line system can be written as ½CŠ ¼



C11 C21

C12 C22





L11 ½LŠ ¼ L21

L12 L22



ð4:3:7Þ

with C11 ¼ C22 , C12 ¼ C21 , L11 ¼ L22 , and L12 ¼ L21 . The propagation modes gn ¼ jobn ðn ¼ 1; 2Þ of the two modes can be obtained by solving Eqs. (4.3.1)

256

CROSSTALK ANALYSIS

and (4.3.2) to be g1 ¼ jo

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðL11 þ L12 ÞðC11 C12 Þ

g2 ¼ jo

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðL11 L12 ÞðC11 þ C12 Þ ð4:3:8Þ

Then, the voltage and current eigenvector matrices and the characteristic impedance matrix are given by   1 1 ½Sv Š ¼ 1 1 2 3 1 1 6 Z1 Z2 7 7 ½SI Š ¼ 6 ð4:3:9Þ 41 15 Z Z2 1  1 Z1 þ Z2 Z1 Z2 ½Zc Š ¼ 2 Z1 Z2 Z1 þ Z2 where 

L11 þ L12 Z1 ¼ C11 C12

1=2



L11 L12 Z2 ¼ C11 þ C12

1=2

ð4:3:10Þ

Suppose that the load impedances of the two lines are the same, that is, ZL1 ¼ ZL2 ¼ ZL ; the source impedances of the two lines are the same, that is, ZG1 ¼ ZG2 ¼ ZG ; and the signal source E1 ðtÞ is applied to line 1. Then the voltage transfer functions can be obtained to be      V1;2 ðx; oÞ 1 1 e g1 x þ rL1 e g1 ð2‘ xÞ 1 e g2 x þ rL2 e g2 ð2‘ xÞ ¼  E1 ðoÞ 2 P1 P2 1 rL1 rG1 e 2g1 ‘ 1 rL2 rG2 e 2g2 ‘

ð4:3:11Þ

where rLn ¼

ZL Zn ZL þ Zn

n ¼ 1; 2

rGn ¼

ZG Zn ZG þ Zn

n ¼ 1; 2

and Pn ¼ 1 þ

ZG Zn

n ¼ 1; 2

ð4:3:12Þ

If the source impedances applied to the two interconnection lines are each equal to Zcc defined as the characteristic impedance of an isolated line, that is, ZG  Zcc ,

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

257

then rGn  0 ðn ¼ 1; 2Þ and Eq. (4.3.11) becomes  V1;2 ðx; oÞ 1 1 ¼ ðe E1 ðoÞ 2 P1

g1 x

þ rL1 e

g1 ð2‘ xÞ

1 Þ  ðe P2

g2 x

þ rL2 e

g2 ð2‘ xÞ

 Þ ð4:3:13Þ

Further, if the load impedances of the two lines are each equal to Zcc , then Eq. (4.3.13) still holds but with rLn  0 ðn ¼ 1; 2Þ. The closed-form expressions in the time domain can now be determined by the inverse Fourier transformations of the voltage transfer functions given by Eq. (4.3.13) to be      1 1 x 1 x  E1 t E1 t 2 P1 v1 P2 v2       rL1 2‘ x rL2 2‘ x  E1 t E1 t þ P1 P2 v1 v2

V1;2 ðx; tÞ ¼

ð4:3:14Þ

where vn ¼ jo=gn ¼ 1=bn ðn ¼ 1; 2Þ are the two propagation velocities. It is clear from Eq. (4.3.14) that one source of crosstalk noise is the mismatch between the propagation velocities of different modes. In addition, Eq. (4.3.13) indicates that the coupling of the active line with its neighbors degrades the input signal as it travels along the active line. 4.3.3

Three-Line System

Consider a system of three interconnection lines with matched loads having three propagation modes. If the matrix ½AŠ denotes the product of the matrices ½LŠ and ½CŠ, that is, ½AŠ ¼ ½LŠ½CŠ, then the propagation constants of the three modes will be given by g1 ¼ joðA11 A13 Þ  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi0:5 1 g2 ¼ pffiffiffi jo A11 þ A13 þ A22 þ ðA11 þ A13 A22 Þ2 þ 8A12 A21 2  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi0:5 1 g3 ¼ pffiffiffi jo A11 þ A13 þ A22 ðA11 þ A13 A22 Þ2 þ 8A12 A21 2

ð4:3:15Þ

and the voltage eigenvector matrix is given by 2

1 ½Sv Š ¼ 4 0 1

1 Z2 1

3 1 Z3 5 1

ð4:3:16Þ

258

CROSSTALK ANALYSIS

where Z2 ¼ Z3 ¼

ðA22

A11

ðA22

A11

A13 Þ þ A13 Þ

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðA22 A11 A13 Þ2 þ 8A12 A21 2A12 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi ðA22 A11 A13 Þ2 þ 8A12 A21

ð4:3:17Þ

2A12

If the input signal E1 ðtÞ is applied to line 1 (the active line), source impedances are much smaller as compared to the line characteristic impedances Zcc , that is, ZGn ¼ 0, and if the load impedances are each equal to Zcc , that is, ZLn ¼ Zcc ðn ¼ 1; 2; 3Þ, then the closed-form expressions for the line voltage waveforms can be determined by following the same steps as for the two-line system to be        1 x Z3 x Z2 x þ E1 t E1 t V1 ðx; tÞ ¼ E1 t Z2 Z3 Z2 Z3 2 v1 v2 v3       1 Z2 Z3 x x E1 t þ E1 t V2 ðx; tÞ ¼ 2 Z2 Z3 v2 v3        1 x Z3 x Z2 x E1 t þ E1 t E1 t V3 ðx; tÞ ¼ 2 v1 v2 v3 Z2 Z3 Z2 Z3 ð4:3:18Þ

4.3.4

Four-Line System

Consider a system of four interconnection lines with matched loads having four propagation modes. If the matrix ½AŠ denotes the product of the matrices ½LŠ and ½CŠ, that is, ½AŠ ¼ ½LŠ½CŠ, then the propagation constants of the four modes will be given by  jo g1 ¼ pffiffiffi ðA11 þ A14 þ A22 þ A23 Þ 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi0:5 þ ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31 Þ  jo g2 ¼ pffiffiffi ðA11 þ A14 þ A22 þ A23 Þ 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi0:5 ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31 Þ ð4:3:19Þ  jo g3 ¼ pffiffiffi ð A11 þ A14 þ A22 A23 Þ 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi0:5 þ ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ  jo g4 ¼ pffiffiffi ð A11 þ A14 þ A22 A23 Þ 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi0:5 ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

259

and the voltage eigenvector is given by 2

1 6 Z1 ½Sv Š ¼ 6 4 Z1 1

1 Z2 Z2 1

1 Z3 Z3 1

3 1 Z4 7 7 Z4 5 1

ð4:3:20Þ

where Z1 ¼ ð A11 A14 þ A22 þ A23 Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31Þ þ 2ðA12 þ A13 Þ

Z2 ¼ ð A11 A14 þ A22 þ A23 Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31 Þ 2ðA12 þ A13 Þ

ð4:3:21Þ

Z3 ¼ ð A11 þ A14 þ A22 A23 Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ þ 2ðA12 A13 Þ

Z4 ¼ ð A11 þ A14 þ A22 A23 Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ 2ðA12

A13 Þ

If the input signal E1 ðtÞ is applied to line 1 (the active line), source impedances are much smaller as compared to the line characteristic impedances Zcc , that is, ZGn ¼ 0, and if the load impedances are each equal to Zcc , that is, ZLn ¼ Zcc ðn ¼ 1; 2; 3; 4Þ, then the closed-form expressions for the line voltage waveforms can be determined by following the same steps as for the two-line system to be          1 x x x x V1 ðx; tÞ ¼ a2 E1 t þ a1 E1 t a4 E1 t þ a3 E1 t 2 v1 v2 v3 v4             1 x x x x E1 t E1 t þ E1 t þ b2 þ E1 t V2 ðx; tÞ ¼ b1 2 v1 v2 v3 v4             1 x x x x V3 ðx; tÞ ¼ b1 E1 t E1 t þ E1 t b2 þ E1 t 2 v1 v2 v3 v4          1 x x x x V4 ðx; tÞ ¼ a2 E1 t þ a1 E1 t þ a4 E1 t a3 E1 t 2 v1 v2 v3 v4 ð4:3:22Þ

260

CROSSTALK ANALYSIS

where vn ¼ a1 ¼

Z1 Z1

Z2

a2 ¼

jo gn

Z2 Z1

Z2

n ¼ 1; 2; 3; 4 a3 ¼

Z3 Z3

b1 ¼ a1 Z2 ¼ a2 Z1

4.3.5

Z4

a4 ¼

Z4 Z3

Z4

ð4:3:23Þ

b2 ¼ a3 Z4 ¼ a4 Z3

Simulation Results

A schematic of the coupled interconnections in high-speed circuits and systems is shown in Fig. 4.3.1 and the layout of the N uniformly coupled 50- interconnections used in the simulations given below [16] is shown in Fig. 4.3.2. Referring to Fig. 4.3.1, we have set ZGn ¼ 0 and ZLn ¼ 50 , where n ¼ 1; 2; . . . ; N. In Fig. 4.3.2, unless otherwise stated, the interconnections are assumed to be of negligible thickness, the substrate is aluminum with permittivity er ¼ 10, the width of each interconnection ðWÞ is equal to the substrate thickness ðHÞ, the distance between any two adjacent conductors ðSÞ is 1.5 H, the length of each coupled line is 20 cm, and a ramp signal having amplitude of 1 V and rise time of 100 ps is applied to line 1 (the active line). For a system of two interconnection lines, the time-domain voltage waveforms at the load ends of the active line and the neighboring line determined by Eq. (4.3.14) are shown in Fig. 4.3.3. The capacitance and inductance matrices used in these results were determined by the Green’s function method and are ½CŠ ¼



½LŠ ¼



1:737 0:073 4:276 0:529

0:073 1:737  0:529 4:276



pF=cm

nH=cm

FIGURE 4.3.2 Layout of N uniformly coupled 50- interconnections on aluminum substrate. (From [16]. # 1990 by IEEE.)

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

261

FIGURE 4.3.3 Signal waveforms at load ends for two-line system in Fig. 4.3.2 with N ¼ 2. (From [16]. # 1990 by IEEE.)

For the sake of comparison, Fig. 4.3.3 also shows the analysis results from [12], where weak coupling was assumed. It is clear that the weak-coupling approximation can result in significant errors in crosstalk calculations. For the two-line system, the amplitude of the coupling noise at the load end as a function of the layout parameter S=W is plotted in Figure 4.3.4. Fig. 4.3.5 shows the influences of the length of the coupled lines and the rise time of the input signal on the amplitude of the coupling noise. For a system of three interconnection lines, the time-domain voltage waveforms at the load ends of the active line and the neighboring lines determined by Eq. (4.3.18) are shown in Fig. 4.3.6. The capacitance and inductance

FIGURE 4.3.4 Amplitude of load-end coupling noise as function of layout parameter S=W for two-line system in Fig. 4.3.2 with N ¼ 2. (From [16]. # 1990 by IEEE.)

262

CROSSTALK ANALYSIS

FIGURE 4.3.5 Dependences of peak coupling noise on length (‘) of coupled lines of two-line system for different values of rise time ðTr Þ of signal source. (From [16]. # 1990 by IEEE.)

FIGURE 4.3.6 Signal waveforms at load ends for three-line system in Fig. 4.3.2 with N ¼ 3. (From [16]. # 1990 by IEEE.)

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

263

matrices used in these results were determined by the Green’s function method and are 3 2 1:737 0:073 0:005 7 6 pF=cm ½CŠ ¼ 4 0:073 1:741 0:073 5 0:005 0:073 1:737 2 3 4:276 0:527 0:159 6 7 ½LŠ ¼ 4 0:527 4:269 0:527 5 nH=cm 0:159 0:527 4:276 The results assuming weak coupling from [12] are also included in Fig. 4.3.6 and indicate that this approximation is not satisfactory for typical interconnection configurations. For a system of four interconnection lines, the time-domain voltage waveforms at the load ends of the active line and the disturbed lines determined by Eq. (4.3.22) are shown in Fig. 4.3.7. The capacitance and inductance matrices used in these results were determined by the Green’s function method and are 1:737

0:073

0:004

0:002

6 0:073 6 ½CŠ ¼ 6 4 0:004

1:742 0:073

0:073 1:742

0:004

0:073

0:004 7 7 7 0:073 5

2

0:002

4:276 6 0:527 6 ½LŠ ¼ 6 4 0:158 2

0:072

3

pF=cm

1:737 3

0:527

0:158

0:072

4:269 0:526

0:526 4:269

0:158

0:527

0:158 7 7 7 0:527 5

nH=cm

4:276

FIGURE 4.3.7 Signal waveforms at load ends for four-line system in Fig. 4.3.2 with N ¼ 4. (From [16]. # 1990 by IEEE.)

264

CROSSTALK ANALYSIS

FIGURE 4.3.8 Load waveforms for signal–signal (S–S), signal–ground–signal (S–G–S) and ground–signal–ground–signal–ground (G–S–G–S–G) configurations. (From [16]. # 1990 by IEEE.)

The reduction of crosstalk by placing grounded conductors between the signal lines is demonstrated in Fig. 4.3.8, which shows the load voltage waveforms on line 2 when a ramp signal having amplitude of 1 V and rise time of 80 ps is applied to line 1 for the cases of two signal lines only (S–S), two signal lines with a grounded shield conductor in between (S–G–S), and two signal lines with grounded shield conductors in between as well as on both sides (G–S–G–S–G). It is clear from the simulation results that the grounded conductors should be placed on both sides of each signal line to significantly reduce crosstalk. However, it should be noted that the insertion of ground conductors not only increases the complexity of the circuit but also causes waveform distortion for the signal on the active line.

4.4

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

In this section, the crosstalk among the parallel multilevel interconnections including the single-, bi-, and trilevel configurations is studied by modeling the interconnections as transmission lines. The model has been utilized to study the dependences of crosstalk voltage on interconnection parameters such as length, width, separation, interlevel distance, driving transistor resistance, and load capacitance. 4.4.1

The Model

As shown in Fig. 4.4.1, the interconnection line can be modeled as a transmission line driven by a unit step voltage source having resistance Rs , loaded by the capacitance CL , and coupled to the neighboring interconnection lines by the mutual capacitances and inductances (not shown in the figure). The resistance Rs is determined by the dimensions of the driving transistor and the capacitance CL is determined by the parasitic capacitances of the transistor loading the interconnection line. For the interconnection lines printed on or embedded in the semi-insulating

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

265

FIGURE 4.4.1 Interconnection driven by unit step voltage source Vs of resistance Rs and terminated by load capacitance CL . The terminal endings on the neighboring interconnections are also shown. Interconnection capacitances as well as capacitive and inductive couplings between interconnections not shown.

GaAs substrate, quasi-TEM is the dominant mode of wave propagation and the transmission line equations are given as @ Vðx; tÞ ¼ @x @ Iðx; tÞ ¼ @x



 @ Iðx; tÞ @t   @ GþC Vðx; tÞ @t RþL

ð4:4:1Þ ð4:4:2Þ

where L and C are the inductance and capacitance matrices per unit length of the interconnections, R is determined by the resistance per unit length of the interconnections, and G is the conductance matrix determined by the conductivity of the substrate. For semi-insulating GaAs substrate, G can be neglected. The matrices L and C can be determined by the network analog method developed in Chapter 2. In the s domain, Eqs. (4.4.1) and (4.4.2) can be written as d Vðx; sÞ ¼ dx d Iðx; sÞ ¼ dx

½R þ sLŠIðx; sÞ

ð4:4:3Þ

½G þ sCŠVðx; sÞ

ð4:4:4Þ

Defining Z ¼ R þ sL

Y ¼ G þ sC

Eqs. (4.4.3) and (4.4.4) can be solved in the s domain, yielding pffiffiffiffi pffiffiffiffi Vðx; sÞ ¼ e ZY ðxÞ Vi ðsÞ þ e ZY ð‘ xÞ Vr ðsÞ rffiffiffiffi pffiffiffiffi Y pffiffiffiffi Iðx; sÞ ¼ ½e ZY ðxÞ Vi ðsÞ e ZY ð‘ xÞ Vr ðsފ Z

ð4:4:5Þ ð4:4:6Þ

266

CROSSTALK ANALYSIS

In Eqs. (4.4.5) and (4.4.6), ‘ is the total length of the transmission line, Vi ðsÞ is the voltage vector of the incident wave at x ¼ 0, and Vr ðsÞ is that of the reflected wave at x ¼ ‘. At the end points x ¼ 0 and x ¼ ‘, Eqs. (4.4.5) and (4.4.6) yield pffiffiffiffi Vð0; sÞ ¼ Vi ðsÞ þ e ZY ‘ Vr ðsÞ rffiffiffiffi pffiffiffiffi Y Ið0; sÞ ¼ ½Vi ðsÞ e ZY ‘ Vr ðsފ Z pffiffiffiffi Vð‘; sÞ ¼ e ZY ‘ Vi ðsÞ þ Vr ðsÞ rffiffiffiffi Y pffiffiffiffi Ið‘; sÞ ¼ ½e ZY ‘ Vi ðsÞ Vr ðsފ Z

ð4:4:7Þ ð4:4:8Þ ð4:4:9Þ ð4:4:10Þ

Incorporating the boundary conditions determined by the lumped circuit elements connected to the interconnection line, that is, Vð0; sÞ ¼ Vs ðsÞ Rs Ið0; sÞ 1 Vð‘; sÞ ¼ Ið‘; sÞ sCL

ð4:4:11Þ ð4:4:12Þ

we have rffiffiffiffi pffiffiffiffi Y Vi ðsÞ þ e Vr ðsÞ ¼ ð Rs Þ ½Vi ðsÞ e ZY ‘ Vr ðsފ þ Vs ðsÞ Z  rffiffiffiffi pffiffiffiffi pffiffiffiffi 1 Y ½e ZY ‘ Vi ðsÞ Vr ðsފ e ZY ‘ Vi ðsÞ þ Vr ðsÞ ¼ sCL Z ð

pffiffiffiffi ZY Þ‘

ð4:4:13Þ ð4:4:14Þ

which can be solved to yield, for Vi ðsÞ and Vr ðsÞ, 8 "
R¼0 ð6:2:18Þ < b for Q¼ > b > : for L ¼ 0 ð6:2:19Þ a and, if G ¼ 0 or C ¼ 0, then Eq. (6.2.13) yields 8 a > > < b for G ¼ 0 Q¼ > b > : for C ¼ 0 a

ð6:2:20Þ ð6:2:21Þ

Conversely, it can be stated that if the power quotient of a waveguide is given approximately by the ratio ða=bÞ or its inverse, then it can be modeled approximately by a three-parameter transmission line. 6.2.2

Equivalent Circuits for Waveguide Drivers and Loads

Now, we need to find the transmission line load impedance and the Thevenin voltage source (or Norton current source) equivalent circuit for the waveguide driver in terms of the known waveguide parameters. To accomplish these objectives, we note that z dependences of both the transverse electric field in the waveguide and the voltage in the equivalent transmission line are given by the function VðzÞ ¼ Ae

gz

þ Begz

ð6:2:22Þ

where A and B are the forward and reflected wave amplitudes determined by the driver and the load. Similarly, the z dependences of both the transverse magnetic field in the waveguide and the current in the equivalent transmission line are given by the function IðzÞ ¼

1 ½Ae Z0

gz

Begz Š

ð6:2:23Þ

Now, the reflection coefficient L looking toward the load is the quantity characteristic of the waveguide termination and is defined as L

¼

B A

ð6:2:24Þ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

379

The load impedance ZL for the equivalent transmission line can now be determined by requiring that it result in the same L as exists in the waveguide. Therefore, if ‘ is the length of the transmission line, then Eqs. (6.2.22) and (6.2.23) yield, at z ¼ ‘, ZL 

 Vð‘Þ 1þ ¼ Z0 Ið‘Þ 1

Le

ð2g‘Þ

Le

ð2g‘Þ



ð6:2:25Þ

Since both L and g are fixed by the wave behavior in the waveguide and Z0 is determined by conditions (6.2.14)–(6.2.17) and the requirement of agreement with a low-frequency circuit, the load ZL can be determined from Eq. (6.2.25). For the waveguide driver, the Thevenin voltage source equivalent circuit (input voltage Vin and impedance Zin ) for the corresponding transmission line can be determined by requiring that the equivalent circuit result in the correct complex input power Pin and the correct reflection coefficient from the driver ð D Þ. The input power is given by   1 1 Vin  Pin ¼ Vin Ið0Þ ¼ Vin Zin þ Zi 2 2

ð6:2:26Þ

where Zi is the line input impedance, which can be determined from Eqs. (6.2.22) and (6.2.23) to be  Vð0Þ 1þ ¼ Z0 Zi  1 Ið0Þ

L L



ð6:2:27Þ

The impedance Zin is given by Zin ¼ Z0

 1þ 1

D D



ð6:2:28Þ

Then, using Eqs. (6.2.27) and (6.2.28), Eq. (6.2.26) becomes  1 2 1 ð1 Pin ¼ jVin j  4 Z0 1

D Þð1 D L

LÞ



ð6:2:29Þ

Knowing the power input to the waveguide and the two reflection coefficients D and, L , jVin j can be determined. The reflection coefficients can be determined from standing-wave measurements in the waveguide or by calculations in certain special cases. 6.2.3

Lossy Waveguide in Inhomogenous Medium

In this section, the transmission line parameters R, L, G, and C for a transmission line equivalent to a lossy waveguide in an inhomogenous medium are derived from

380

FUTURE INTERCONNECTIONS

Maxwell’s equations. In this case, the material parameters of the waveguide medium are taken as complex and dependent on the transverse position. In other words, if the z direction is the direction of propagation, then the dielectric permittivity e and magnetic permeability m are given by sðx; yÞ jo m ¼ m1 ðx; yÞ þ jm2 ðx; yÞ e ¼ e0 kðx; yÞ þ

ð6:2:30Þ ð6:2:31Þ

where k is the dielectric constant and s is the conductivity of the medium. The electric and magnetic fields at any angular frequency o are also considered to be complex and are given by Eðx; y; zÞ ¼ Et ðx; yÞVðzÞ þ ZEl ðx; yÞIðzÞ 1 Hðx; y; zÞ ¼ Ht ðx; yÞIðzÞ þ Hl ðx; yÞVðzÞ Z

ð6:2:32Þ ð6:2:33Þ

where the subscript t denotes the transverse vector with x and y components, the subscript l denotes a longitudinal component in the z direction, and Z is the intrinsic impedance of empty space given by s ffiffiffiffiffiffiffiffiffiffiffiffi  m0  376:7

Z¼ e0

ð6:2:34Þ

It should be noted that the electric and magnetic fields given by Eqs. (6.2.32) and (6.2.33) represent one mode of propagation only; a general solution of Maxwell’s equations will be given by summations over all propagation modes. 6.2.3.1 Separation of Longitudinal and Transverse Components Assuming a single traveling wave, we will now derive a few basic equations by substituting Eqs. (6.2.32) and (6.2.33) into Maxwell’s equations and separating the longitudinal and transverse components. Substituting Eqs. (6.2.32) and (6.2.33) into the Maxwell equation rE ¼

jomH

ð6:2:35Þ

we get d VðzÞ r  Et ðx; yÞ þ VðzÞ^k  Et ðx; yÞ þ IðzÞZ r  E1 ðx; yÞ dz   1 ¼ jom IðzÞHt ðx; yÞ þ VðzÞ Hl ðx; yÞ Z

ð6:2:36Þ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

381

where ^k is a unit vector in the z direction. Taking the z components of Eq. (6.2.36), we get   jom Hl ðx; yÞ ¼ 0 VðzÞ r  Et ðx; yÞ þ Z

ð6:2:37Þ

Since VðzÞ is nonzero, we get r  Et ðx; yÞ þ

jom Hl ðx; yÞ ¼ 0 Z

ð6:2:38Þ

Now, taking the transverse components of Eq. (6.2.36), we get Z r  El ðx; yÞ þ jomHt ðx; yÞ ¼

^k  Et ðx; yÞ



1 d VðzÞ IðzÞ dz



ð6:2:39Þ

Since the left side of Eq. (6.2.39) is independent of z, it follows that 

 1 d VðzÞ ¼ const ¼ c1 IðzÞ dz

ð6:2:40Þ

Substituting (6.2.32) and (6.2.33) into the Maxwell equation r  H ¼ joeE

ð6:2:41Þ

and following the above steps, we get from the z components IðzÞ½r  Ht ðx; yÞ

joeZEl Š ¼ 0

ð6:2:42Þ

and, since IðzÞ is nonzero, we get r  Ht

joeZEl ¼ 0

ð6:2:43Þ

Taking the transverse components, we get 1 r  Hl ðx; yÞ Z

joeEt ðx; yÞ ¼

^k  Ht ðx; yÞ



1 d IðzÞ VðzÞ dz



ð6:2:44Þ

Since the left side of Eq. (6.2.44) is independent of z, it follows that 

 1 d IðzÞ ¼ const ¼ c2 VðzÞ dz

ð6:2:45Þ

382

FUTURE INTERCONNECTIONS

Equations (6.2.40) and (6.2.45) can be written in the form of transmission line equations by choosing the arbitrary constants c1 and c2 as c1 ¼ c2 ¼

gZ0 g Z0

ð6:2:46Þ ð6:2:47Þ

Substituting Eqs. (6.2.32) and (6.2.33) into the Maxwell equation r  ½eðx; yÞEðx; y; zފ ¼ 0

ð6:2:48Þ

we get VðzÞr  ½eðx; yÞEt ðx; yފ þ

d IðzÞeðx; yÞZ^k  El ðx; yÞ ¼ 0 dz

ð6:2:49Þ

Using Eqs. (6.2.45) and (6.2.47) in Eq. (6.2.49), we get  VðzÞ r  ½eðx; yÞEt ðx; yފ

 g ½eðx; yÞZ^k  El ðx; yފ ¼ 0 Z0

ð6:2:50Þ

and, since VðzÞ is nonzero, we get r  ½eEt Š

g ðeZ^k  El Þ ¼ 0 Z0

ð6:2:51Þ

Substituting Eqs. (6.2.32) and (6.2.33) into the Maxwell equation r  ½mðx; yÞHðx; y; zފ ¼ 0

ð6:2:52Þ

we get IðzÞr  ½mðx; yÞHt ðx; yފ þ

1 d mðx; yÞ^k  Hl ðx; yÞ VðzÞ ¼ 0 Z dz

ð6:2:53Þ

which, when combined with Eqs. (6.2.40) and (6.2.46), leads to  IðzÞ r  ½mðx; yÞHt ðx; yފ

gZ0

 1 mðx; yÞ^k  Hl ðx; yÞ ¼ 0 Z

ð6:2:54Þ

and, since IðzÞ is nonzero, we get r  ½mHt Š

gZ0

1 ^ mk  Hl ¼ 0 Z

ð6:2:55Þ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

383

Using Eqs. (6.2.46) and (6.2.47) in Eq. (6.2.39), we get gZ0 ^k  Et

Zr  El ¼ 0

jomHt

ð6:2:56Þ

and using Eqs. (6.2.46) and (6.2.47) in Eq. (6.2.44), we get g^ k  Ht þ joeEt Z0

1 r  Hl ¼ 0 Z

ð6:2:57Þ

In addition, using Eqs. (6.2.46) and (6.2.47) in Eqs. (6.2.40) and (6.2.45), we get the transmission line equations d VðzÞ ¼ dz d IðzÞ ¼ dz

gZ0 IðzÞ

ð6:2:58Þ

g VðzÞ Z0

ð6:2:59Þ

whose general solutions are known to be given by VðzÞ ¼ Ae gz þ Begz 1 IðzÞ ¼ ½Ae gz Begz Š Z0

ð6:2:60Þ ð6:2:61Þ

where A and B are the complex amplitudes of the forward and reverse traveling waves whose values can be determined by the characteristics of the driver and load of the line. Eigenvalue Equation for g. Divide Eq. (6.2.38) by m and take the curl of the resulting equation. Next divide Eq. (6.2.51) by e and take the gradient of the resulting equation. Then, subtracting the second equation from the first, we get mr 



1 ðr  Et Þ m



   1 g^ r r  ðeEt Þ ¼ jom k  Ht e Z0

joeEt



g Z rð^k  El Þ Z0 ð6:2:62Þ

Now, taking the cross product of Eq. (6.2.56) with ^k, we get jomð^k  Ht Þ ¼

gZ0 Et

Z rð^k  El Þ

ð6:2:63Þ

Substituting Eq. (6.2.63) in Eq. (6.2.62), we get the eigenvalue equation for g:       1 1 2 2 ð6:2:64Þ m r  ðr  Et Þ r r  ðeEt Þ þ ðg þ o emÞEt ¼ 0 m e The eigenvalues of Eq. (6.2.64) can be discrete, continuous, or a combination of both depending upon the functions e and m.

384

FUTURE INTERCONNECTIONS

6.2.3.2 Power Using Poynting’s vector, the average power at position z in the waveguide is given by 1 PðzÞ ¼ 2

Z

dx

Z

Ety Htx ŠVðzÞIðzÞ

dy½Etx Hty

ð6:2:65Þ

Since we require that the equivalent transmission line carry the same average as the waveguide, we get PðzÞ ¼ 12 VðzÞIðzÞ

ð6:2:66Þ

Combining Eqs. (6.2.65) and (6.2.66), we get the condition Z

dx

Z

dy½Etx Hty

Ety Htx Š ¼ 1

ð6:2:67Þ

Using Eqs. (6.2.62) and (6.2.51), we can eliminate Ht and condition (6.2.67) can be expressed in terms of Et alone as Z

dx

Z

dy Et 



   Z0 1 r r  Et jog m

o2 eEt

 

¼1

ð6:2:68Þ

Integrating Eq. (6.2.68) by parts and assuming that the fields vanish at the waveguide boundaries (or at infinity), we get Z

dx

Z



1 dy ðr  Et Þ  ðr  Et Þ m

2

2

o ejEt j



¼

jog Z0

ð6:2:69Þ

If we now eliminate Et in Eq. (6.2.67), the condition can be expressed in terms of Ht alone as Z

dx

Z

 1 dy ðr  Ht Þ  ðr  Ht Þ e

2

2

o mjHt j



¼ jogZ0

ð6:2:70Þ

The conditions (6.2.69) and (6.2.70) normalize the transverse fields to ensure that both the waveguide power and the transmission line power are given by Eq. (6.2.66). 6.2.3.3 Expressions for R, L, G, and C Using the customary expressions defining g and Z0, that is, g2 ¼ ðR þ joLÞðG þ joCÞ R þ joL Z02 ¼ G þ joC

½Eq:ð6:2:4ފ ½Eq:ð6:2:9ފ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

385

we can write g Z0 R þ joL ¼ gZ0

ð6:2:71Þ

G þ joC ¼

ð6:2:72Þ

Using Eq. (6.2.71) and the normalization condition (6.2.69), we can find the following expressions for G and C:

G¼

Z

C¼

Z

dx

Z

dx

Z

"

dy sjEt j

om2 jHl j2 Z2

2

"

dy ke0 jEt j

#

ð6:2:73Þ

#

ð6:2:74Þ

m1 jHl j2 Z2

2

Similarly, using Eq. (6.2.72) and the normalization condition (6.2.70), we can find the following expressions for R and L: R¼ L¼

Z

dx

Z

dx

Z

Z

dy½sZ2 jEl j2 dy½m1 jHt j2

om2 jHt j2 Š

ð6:2:75Þ

ke0 Z2 jEl j2 Š

ð6:2:76Þ

For the case of a homogeneous medium, the corresponding expressions can be found by replacing the transverse and longitudinal field quantities with the field components in Eqs. (6.2.32) and (6.2.33) to yield G¼ C¼ R¼ L¼

1 jVðzÞj2 1

jVðzÞj

2

1

jIðzÞj

2

1

jIðzÞj2

Z Z

dx

Z

dy½sjEn ðx; y; zÞj2

dx

Z

dy½ke0 jEn ðx; y; zÞj2

om2 jHz ðx; y; zÞj2 Š

ð6:2:77Þ

m1 jHz ðx; y; zÞj2 Š

ð6:2:78Þ

Z

dx

Z

dy½sjEz ðx; y; zÞj2

om2 jHn ðx; y; zÞj2 Š

ð6:2:79Þ

Z

dx

Z

dy½m1 jHn ðx; y; zÞj2

ke0 jEz ðx; y; zÞj2 Š

ð6:2:80Þ

where the subscript n denotes the component of the field normal to the direction of propagation. After some manipulation, it can be proved that expressions (6.2.73)– (6.2.76) result in the same values of the ratios in Eqs. (6.2.14) and (6.2.15).

386

6.3 6.3.1

FUTURE INTERCONNECTIONS

SUPERCONDUCTING INTERCONNECTIONS Advantages of Superconducting Interconnections

The signal propagation characteristics, including transit delays of the chip-to-chip interconnection lines, have a major effect on the total performance of an electronic system. An attempt to reduce the interconnection delays by scaling down its dimensions results in increased signal losses in the interconnection [11]. This is due to the increased series resistance and higher dispersion of the interconnection. This adverse effect can be almost eliminated by replacing normal metallic interconnections by superconducting interconnections which have very low series resistance at frequencies up to the energy gap frequency of the material [12, 13]. In fact, in recent years, the advent of high-critical-temperature superconductors [14–16] has opened up the possibility of realizing high-density and very fast interconnections on silicon as well as GaAs-based high-performance ICs. The major advantages of superconducting interconnections over normal metal interconnections can be summarized as follows: 1. The signal propagation time on a superconducting interconnection will be much smaller as compared to that on a normal metal interconnection. 2. The packing density of the IC can be increased without suffering from the high losses associated with high-density normal metal interconnections. 3. There is virtually no signal dispersion on superconducting interconnections for frequencies up to several tens of gigahertz. 6.3.2

Propagation Characteristics of Superconducting Interconnections

In this section, an analysis of propagation characteristics [17] on a superconducting microstripline with dielectric thickness td , stripline thickness tc , ground-plane thickness tg , and penetration depth lL shown in Fig. 6.3.1 is presented. In the structure shown in Fig. 6.3.1, material 1 is air with er ¼ 1:0; material 2 is Ba–Y–Cu–O with critical temperature Tc ¼ 92:5 K, normal-state resistivity ðrn Þ ¼ 200 m
cm, ˚ material 3 is SiO2 with er ¼ 3:9; material 4 is Ba–Y–Cu–O with and lL ð0Þ ¼ 1400 A; ˚ and material 5 is SiO2 with Tc ¼ 92:5 K, rn ¼ 200 m
cm, and lL ð0Þ ¼ 1400 A; er ¼ 3:9. It is assumed that the permeability of each medium is that of free space m0 , the loss tangent of dielectrics is negligible, the fringing field effects at the edges of the line can be neglected, and high-Tc superconductors have standard superconducting behavior below Jc, Hc1 , Tc , and energy gap frequency. It can be further assumed that the only nonzero component of magnetic field is Hy and that all fields are independent of y. In other words, in addition to the time dependence given by ejot, the nonzero field components in rectangular coordinates are Hy ðxÞe gz , Ex ðxÞe gz , and Ez ðxÞe gz . Using the two-fluid model [18, 19], the total current JT in a superconductor consists of normal current Jn and a supercurrent Js , that is, J T ¼ Jn þ Js

ð6:3:1Þ

SUPERCONDUCTING INTERCONNECTIONS

387

FIGURE 6.3.1 Schematic of superconducting microstrip structure analyzed in this section. (From [17]. # 1987 by IEEE.)

where the supercurrent component obeys London’s equations E ¼ jom0 l2L Js

H¼

l2L =  Js

ð6:3:2Þ

where lL is the penetration depth of the superconductor. The boundary value problem presented in Fig. 6.3.1 can be solved using Eqs. (6.3.1) and (6.3.2) and Maxwell’s equations to obtain the propagation constant g which is valid for frequencies up to several gigahertz (note that the normal-current component is negligible for these frequencies):      lL;2 tc lL;4 tg 2 2 þ ð6:3:3Þ coth coth g ¼ m0 e3 o 1 þ td lL;2 td lL;4 According to Eq. (6.3.3), g is purely imaginary, indicating that the propagation characteristics of a superconducting microstripline are lossless and dispersionless. The phase velocity of propagation for the superconducting microstrip is given by o ¼ vp ¼ ImðgÞ

(sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi     ffi) lL;2 tc lL;4 tg þ coth coth m0 e3 1 þ td lL;2 td lL;4

1

ð6:3:4Þ

Equation (6.3.4) indicates that the phase velocity depends strongly on the superconducting layer thickness, penetration depth of the superconducting layers, and dielectric constants of the dielectric layers. Since the penetration depth is a function of temperature given by lL ð0Þ lL ðTÞ ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 ðT=Tc Þ4

ð6:3:5Þ

388

FUTURE INTERCONNECTIONS

the phase velocity also depends on temperature, particularly for temperatures near the critical temperature Tc . It can also be seen from Eq. (6.3.4) that the phase velocity is a function of the dielectric constant only when the dielectric thickness and the superconducting layer thickness are much larger than the penetration depth. Using the two-fluid model, the conductivity of a superconductor is given by [19] "  4 T 1 j 1 s ¼ snormal Tc m0 o½lL;2 ð0ފ2

 4 # T Tc

ð6:3:6Þ

where snormal is the normal-state conductivity of the superconductor at a temperature just above Tc . 6.3.3

Comparison with Normal Metal Interconnections

In this section, a comparison of the propagation characteristics of the superconducting and normal aluminum interconnections at 77 K [17] is presented. The interconnection dimensions and other transmission line parameters for the aluminum line are chosen to be the following: Width of microstrip line ðWÞ 2 mm Thickness of microstrip ðtc Þ 0:5 mm Interdielectric thickness ðtd Þ 1 mm Ground-plane thickness ðtg Þ 1 mm Relative dielectric constant for interdielectric 3.9 Relative dielectric constant for substrate 3.9 Conductivity of 0.5-mm-thick aluminum at 77 K 1:5  106 S/cm Capacitance of line 1.54 pF/cm The inductance of the line for frequencies up to 10 GHz is 2.95 nH/cm (decreasing to 2.25 nH/cm for frequencies above 100 GHz, due to skin effect). The series resistance of the line for frequencies up to 10 GHz is 77.6 /cm (increases as the frequency increases above 10 GHz, due to skin effect) A comparison of the phase velocities at 77 K for the superconducting line and the aluminum line for frequencies up to 1012 Hz is shown in Fig. 6.3.2 and a comparison of the attenuation for the two lines in the frequency range 106–1012 Hz is shown in Fig. 6.3.3. First, for the normal aluminum interconnection line, it can be seen that its phase velocity is much less than that of the superconducting line for frequencies up to 100 MHz. Further, its phase velocity depends very strongly on frequency, indicating that the line is very dispersive. Figure 6.3.3 indicates that, for a normal aluminum line, its maximum useful length (attenuation < 3 dB) is limited by attenuation to be 2 cm at 100 MHz and only 2 mm at 10 GHz. For the superconducting interconnection line, it can be seen from Fig. 6.3.2 that its phase velocity is nearly constant at frequencies up to 1 THz at 77 K; that is, the

SUPERCONDUCTING INTERCONNECTIONS

389

FIGURE 6.3.2 Comparison of phase velocities at 77 K for superconducting and normal aluminum lines. (From [17]. # 1987 by IEEE.)

line is virtually nondispersive. However, as shown in Fig. 6.3.3, the attenuation of the superconducting line is a function of frequency and temperature; it is very small for frequencies up to 10 GHz and increases with increasing frequency. Therefore, superconducting interconnections can operate with negligible dispersion and low loss at frequencies of several gigahertz for lengths exceeding several meters.

FIGURE 6.3.3 Comparison of attenuations at 77 K for superconducting and normal aluminum lines. (From [17]. # 1987 by IEEE.)

390

6.4

FUTURE INTERCONNECTIONS

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

As progress along the International Technology Roadmap for Semiconductors (ITRS) continues, physical and electromagnetic limitations make scaling of silicon CMOS FETs increasingly difficult. One long-term solution is to replace Si FETs by completely new structures such as nanoscale molecular, biological, or quantum devices. Before considering this changeover, an interconnection technology must be developed that is suitable for these new device concepts. To connect ultrasmall devices, interconnections must be less than 10 nm in diameter. However, they still must be easy to fabricate, have low resistance and high maximum current-carrying capacity, and be isolated by low-k dielectric materials for applications in nanotechnology circuits requiring ultrahigh density of the devices and interconnections. This implies that, in addition to the development of the various nanodevices, interconnections that will be used to connect these devices in nanotechnology circuits should be given a very special attention. It is extremely important to gain an understanding of the parasitic elements such as capacitances and inductances and interconnection performance parameters such as propagation delays, crosstalk, and current-carrying capacities for almost electromigration-free operation for the various interconnection technologies in the nanoscale regime. In the past, such models have been developed for microscale metallic interconnections [20]. In future development of nanoscale ICs, interconnections will play a crucial role. As the sizes of the active devices approach the nanometer dimensions, the wires that connect them must also be scaled down. Several IC manufacturers are in the process of commercializing 100-nm CMOS-based IC technologies and the research and development work for the 70- and 50-nm devices is well underway. Successful IC development below these feature sizes faces the fundamental challenges imposed by the basic lays of quantum physics. In addition, as the diameters of conventional metallic interconnection wires reach the mean free path for electrons, surface scattering from the boundaries of ultranarrow conductors as well as grain boundary scattering would inhibit electronic conduction in the wires to an unacceptable level. Nanotechnology circuits [21–27] with devices on the sub-100-nm scale will require interconnections with sizes from 50 nm down to molecular and atomic dimensions. If metallic conducting lines such as copper are used for the interconnections, then the miniaturization process will result in a rise in copper resistivity because the dimensions of the conducting lines will be of the same order of magnitude as the mean free path of electrons, which is 39.3 nm in copper at room temperature. This rise in resistivity may dramatically slow the circuit’s functioning and as a result jeopardize the ability to improve the circuit speed expected from miniaturization. Electromigration which is the result of momentum transfer from electrons moving under an applied electric field to ions making up the lattice structure of the interconnection material imposes another serious problem. Continuing miniaturization of thin-film metallic interconnections results in increasingly high current densities leading to the open- and/or short-circuit electrical failures of interconnections in a relatively short time. The higher the

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temperature, the higher the electromigration-induced failure of metallic interconnections. In this context, it is important to note that lots of electrons and electron scattering are required for electromigration to take place. It does not occur in semiconductors unless they are so heavily doped that they exhibit metallic conduction. In this section, the various potential interconnection technologies suitable for nanoscale ICs, including metallic interconnections, nanowires, carbon nanotubes, and quantum wires, are reviewed. 6.4.1

Silicon Nanowires and Metallic Interconnections

A nanowire is simply a solid, cylindrical wire with a diameter on the scale of a few nanometers. These can be fabricated from a variety of materials (silicon, germanium, gallium nitride, metals, oxides, etc.) to a length of several micrometers. Semiconductor nanowires are 1D structures with unique electrical and optical properties that are used as building blocks in nanoscale circuit design. Their low dimensionality means that they exhibit quantum confinement effects. One of the challenges lies in understanding the electron conduction and transport properties of these nanowires and how these can be used as interconnections for integrating various nanoscale devices such as single electron transistors and quantum cellular automata. These issues are relevant to the ultimate design of a nanoscale IC regardless of the nature of the active element. As such these issues represent a fundamental element of the road map leading to nanoscale integration. According to C. M. Lieber of Harvard, nanowires ‘‘represent the smallest dimension for efficient transport of electrons and excitons, and thus will be used as interconnections and critical devices in nanoelectronics and nano-optoelectronics.’’ Silicon nanowires, a class of nanowires, are good candidates for nanoscale interconnections [28]. Metal interconnections which are used to connect transistors on an IC chip have become the major bottleneck in furthering chip miniaturization. On-chip interconnections contribute much more to the chip’s overall delay than that caused by the once dominant gate capacitances in transistors. This delay in interconnections is due to the presence of parasitic impedances characteristically seen in metal lines. These impedances are seen in the form of capacitances between an interconnection line and the substrate as well as between interconnection lines in different levels, line resistances, and inductances, both self and mutual, due to induced magnetic fields. Over the years, researchers have been trying to reduce this delay by reducing the interconnection’s RC time constant. For the 130-nm technology chips, this has been achieved to some extent with the replacement of aluminum with copper to reduce the line’s resistance and by using low-k dielectric materials in the place of the industry standard silicon dioxide to reduce capacitances. However, with ever-increasing frequencies, scaling of minimum feature sizes, the reduction of resistances and capacitances, as well as larger die sizes have all led to a growing dominance of on-chip inductances. These inductances have been largely ignored in the past. However, this trend cannot continue into the future [29, 30]. Inductance effects include ringing and reflections which can distort the signals severely. If not considered, further scaling of devices and the use of higher frequencies will increase

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these effects, leading to false switching in transistors and resulting in the chip’s failure. To sum up, it is crucial to understand the effects of interconnection inductances on various signal and design parameters such as signal rise and fall times, power dissipation, repeater insertion processes, and signal propagation. It is particularly true for nanoscale interconnections which are expected to be used for the 65-nm technology chips and onward. ‘‘Multipath interconnection,’’ a modified version of the traditional metallic interconnection proposed as a possible solution of the interconnection problem for some nanoscale circuits [31, 32], is discussed in Chapter 1. The modification consists of using the concept of parallel processing by providing two or more paths between the driver and the load to carry the signal, as shown in Fig. 1.1.2. These paths are stacked vertically isolated from one another by insulating layers between them, thereby taking the same area on the chip as a standard single-path interconnection. Such a structure can carry much larger currents on the chip, and this interconnection structure can be built by an extension of the existing microelectronics fabrication infrastructure. Computer simulations of the propagation delays expected in a multipath interconnection indicate that the overall interconnection delay would decrease as the number of paths is increased [31]. An analysis of the electromigration-induced failure of a multipath interconnection suggests that the MTF increases as the number of paths is increased [31]. Clearly the multipath interconnection shows great promise for microelectronic circuits or hybrid circuits consisting of both microelectronic and nanotechnology devices. 6.4.2

Nanotube Interconnections

Nanotubes are tiny tubes about 10,000 times thinner than a human hair and consist of rolled-up sheets of carbon hexagons. Discovered in 1991 by researchers at NEC, they have the potential for use as minuscule wires in ultrasmall electronic devices. As shown in Fig. 6.4.1, there are two main types of carbon nanotubes (CNTs) that can have high structural perfection. Single-walled nanotubes (SWNTs) consist of a single graphite sheet seamlessly wrapped into a cylindrical tube. Multiwalled

FIGURE 6.4.1 (a) Single-walled CNT. (b) Multiwalled CNT. (From [39]. # 2004 by IEEE.)

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nanotubes (MWNTs) comprise an array of such nanotubes that are concentrically nested like rings of a tree trunk [33]. Multiwall nanotubes are generally in the range of 1–25 nm in diameter while SWNTs have diameters in the range of 1–2 nm. Both SWNTs and MWNTs are usually many micrometers long and hence can fit well as components in sub-micrometer-scale devices and nanocomposite structures that may play an important role in emerging technologies. IBM has recently been able to manipulate the nanotubes in a controlled way. It has developed the capability of changing a nanotube’s position, shape, and orientation as well as cutting it by using an atomic force microscope. NASA researchers have reported a new method for producing ICs using CNTs instead of copper for interconnections. This technology may extend the life of the silicon chip industry by 10 years. The electrical properties of CNTs are fascinating because they can exhibit metallic or semiconducting behavior depending on their structure and dimensions. This has made CNTs a unique candidate material for potential nanotechnology applications as nanoscale electronic devices and interconnections [34–36]. To a large extent, the unique electrical properties of CNTs such as their extremely low electric resistance are derived from their 1D character and the unique electronic structure of graphite. Resistance primarily occurs due to defects in crystal structure, impurity atoms, or an atom vibrating about its position in the crystal. In the case of a CNT, the electrons are not so easily scattered. Due to their small diameter and huge aspect ratio (length to width), nanotubes are essentially 1D systems and therefore electrons have a low chance of scattering, giving rise to very low resistance. The electronic properties of perfect MWNTs are rather similar to those of perfect SWNTs because the coupling between the cylinders is weak in MWNTs. Electrical transport in metallic SWNTs and MWNTs is ballistic, that is, without scattering over long nanotube lengths, enabling them to carry high currents with essentially no heating. In contrast, electrons in copper travel only 40–50 nm before they scatter. Phonons also propagate easily along the nanotube. Superconductivity has also been observed at low temperatures with transition temperatures of nearly 0.55 K for 1.4-nm-diameter SWNTs and nearly 5 K for 0.5-nm SWNTs. The low resistance ensures that the energy dissipated in CNTs is very small, thereby solving the problem of dissipated power density that adversely affects silicon circuits. Current densities of more than 1010 A/cm2 have been reported for the metallic configuration of CNTs. Since CNTs do not have any leftover bonds, there is no need to grow a film on the surface in order to tie up the free bonds and there is no need to restrict the gate insulator to silicon dioxide. This fact implies the use of other superior materials to insulate the gate terminal in a transistor which can result in a much faster device. The properties of CNTs can be summarized as follows: 1. The carrier transport is 1D, resulting in ballistic transport with no scattering and much less power dissipation. Scattering-free current transport allows high current densities and improved signal delays.

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2. All chemical bonds of the carbon atoms are satisfied and there is no need for chemical passivation of free bonds as in silicon. 3. The strong C–C covalent bonding gives the CNTs high mechanical and thermal stability and resistance to electromigration. Current densities as high as 1010 A/cm2 can be sustained in metallic CNTs. 4. The diameter of a CNT is controlled by chemistry, not by fabrication. 5. Both active devices and interconnections can be made of semiconducting and metallic nanotubes. 6. Thermal conductivity along the axis is roughly twice that of diamond. Carbon nanotubes have shown great promise for use as interconnections in nanotechnology circuit applications. This is particularly because they can conduct large currents of the order of a 106 A/cm2 without any deterioration, thus avoiding the electromigration problems characteristic of metallic interconnections. The scatteringfree transport of electrons possible in defect-free CNTs is a very attractive feature of CNTs for microelectronic applications. The reduction in the thickness of conventional metallic or polycrystalline interconnections leads to additional scattering at the surfaces and grain boundaries, thereby deteriorating the interconnection resistance. Carbon nanotudes provide undistributed quasi-crystalline wirelike structure where pulses can travel uninterrupted by length-dependent ohmic scattering. The approximate estimation of signal delays with a simple model proves that nanotubes would surpass classical wires with respect to signal delays. Plenty of work on using CNTs for building ICs is in progress [37–40]. Researchers are also trying to develop complex gates and circuits by fabricating devices along the length of a single CNT. 6.4.2.1 Nanotube Vias The ability to grow nanotubes at specific sites has helped researchers to design CNT vias [41]. Vias are defined as interconnections between wiring layers in chips and are prone to deterioration due to current crowding and electromigration. Carbon nanotubes have been proposed as the alternative for metal plugs to overcome these problems. Ultra-large-scale integrated (ULSI) circuits have problems that originate from stress and electromigration of copper interconnections, particularly the vias. One proposed solution for this problem is to use CNTs with large migration tolerance as vias. Bundles of CNTs must be used as vias to get enough current for large-scale integrated (LSI) interconnections. Hot-filament chemical vapor phase deposition (HF-CVD) can be used to grow CNT bundles in the via holes. Mechanical polishing with diamond slurry can be done to control the length of the CNT vias after their growth. Figure 6.4.2a suggests that the total resistance of the CNT via is about three orders of magnitude lower than that of a single CNT and that there is no visible degradation of the via current with time as shown in Fig. 6.4.2b. Such measurements show that the current flows in parallel through the thousands of nanotubes used in the vias which are end bonded to the upper and lower electrodes [41]. The total resistance of a CNT via with about 5000 nanotubes has been shown to be about 1 , and this resistance can be

(a)

Current (mA)

(b)

Total resistance (Ω)

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

108 107 106 105 104 103 102 10 1

395

One CNT bridge Three CNT bridge CNT via

10 102 103 Number of CNTs

1

104

20 15 10 2 × 106 A/cm2 5 0

0

20

40

60

80

100

120

Time (hour) FIGURE 6.4.2 (a) Dependence of resistance of CNT bundle on number of CNTs in bundle. Resistances of one-CNT bridge, three-CNT bridge, and typical CNT via also shown. (b) Dependence of current in CNT via on time. (From [41]. # 2004 by IEEE.)

further reduced by improvements in nanotube quality. The density of CNTs needs to be increased and the diameters of nanotubes need to be decreased for fabricating more effective CNT vias. It is expected that CNT bundle vias will prove to be effective replacements for copper vias for future ULSI interconnections. 6.4.2.2 Comparison of Nanotubes and Copper Interconnections The potential performance of CNT interconnections and their relative comparison to copper interconnections can be studied using physical models [42]. Nanotube bundles offer better performance than single nanotubes in which wave propagation is relatively slower. As the interconnection size decreases, the performance of copper interconnections goes down due to the increased resistivity as well as electromigration problems, and CNTs have been proposed to be effective replacements due to the ballistic flow of electrons with electron mean free path of several micrometers. Latencies of ideal CNT and copper interconnections are plotted in Fig 6.4.3. A singlewall nanotube results in a very high contact resistance and high characteristic impedance, and hence a bundle of closely packed parallel CNTs is preferably used above a ground plane. The properties of the desired nanotube bundle include: 1. Good connections to all nanotubes within the bundle. 2. Distance between nanotubes within the bundle should be as small as possible to have the largest nanotube density. 3. Quantum coupling between the nanotubes should be nearly zero.

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80

W

SWCNTs Above a Ground Plane Copper Wires Bundle of SWCNs

2d0 d0

dg 0

10

20

30

40

50

8

60

0.25

6

Latency, τ (ps)

d0 = Inm, dg = 2d0

0.3

W

0.2

T

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0.15 0.1

2

H

0.05 0 0

2

4

6

8

0 10

W 20

T

H W = T = H = 27nm 0

0

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Interconnect Length, L (µm)

FIGURE 6.4.3 Dependence of latency on interconnect length for ideal single-layered carbon nanotubes above ground plane, 22-nm node copper wires (expected in 2016), and bundles of ideal SWCNTs for n > 100. (From [42]. # 2005 by IEEE.)

The ITRS predicts that the latency for carbon nanotube bundles will be given by [42] tbundle ¼ 0:7Rtr ðcbundle L þ CL Þ where Rtr is the driver resistance, CL is the load capacitance, and L is the interconnection length. The diameters of the SWCNs can be less than 1 nm and a bundle of, for instance, 400 SWCNs can be as narrow as 20 nm. Assuming that the SWCNT resistance increases exponentially with length, Fig. 6.4.4 shows the latencies of SWCNT bundles and copper interconnections (implemented at 22-nm node) versus the interconnection length for electron mean free path, for L0 ¼ 5 mm and L0 ¼ 10 mm. This figure suggests that there is a length beyond which the latency of SWCNT bundles becomes larger than that of copper wires. This critical length is roughly 10 times the electron mean free path in SWCNTs. From Fig. 6.4.4, one can infer that compared to the 22-nm copper node, the bundles are about 30% faster for a mean free path of 5 mm while they can be nearly 80% faster if a mean free path of 10 mm is achieved. Assuming that the SWCNT resistance increases linearly with length, dependences of the latency on the interconnect length for a 22-nm node copper wire and bundles of SWCNTs with electron mean free paths of 0.1, 1, and 10 mm are shown in Fig. 6.4.5.

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200 Copper Interconnects SWCT-Bundles, L0=5.0 µm SWCN-Bundles, L0=10 µm

Latency, τ (ps)

150

22nm Node, Year 2016

100

50

0 0

50 100 Interconnect Length, L (µm)

150

FIGURE 6.4.4 Dependence of latency on interconnect length for 22-nm node copper wire and bundles of SWCNTs with electron mean free paths of 5 and 10 mm. It is assumed that SWCNT resistance increases exponentially with length. (From [42]. # 2005 by IEEE.)

6.4.2.3 Carbon Nanotubes for High-Frequency Applications In the near future, CNTs are expected to be used for high-frequency applications. Models of the AC properties of CNTs are still in developing stages. Concepts such as quantum capacitance and AC impedance of 1D quantum systems are discussed only in theory. Little data are available to validate high-frequency device models for nano scale devices [43]. A proposed circuit model for understanding the AC impedance of a single-walled nanotube with DC contacts on both sides is shown in

100 CNT Bundles, L0 = 0.1µm Copper Interconnects CNT Bundles, L0 = 1µm CNT Bundles, L0 = 10µm

Latency, τ (ps)

75

50

25

0

0

20

40 60 80 Interconnect Length, L (µm)

100

FIGURE 6.4.5 Dependence of latency on interconnect length for 22-nm node copper wire and bundles of SWCNTs with electron mean free paths of 0.1, 1, and 10 mm. It is assumed that SWCNT resistance increases linearly with length. (From [42]. # 2005 by IEEE.)

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FIGURE 6.4.6 (a) Proposed RF circuit model for single-wall carbon nanotube with DC electrical contacts at both ends. (b) Simplified equivalent circuit. (From [43]. # 2002 by IEEE.)

Fig. 6.4.6a and its simplified equivalent circuit is shown in Fig. 6.4.6b. In this model, Lk is the kinetic inductance per unit length (approximately 10 nH/mm), CQ is the quantum capacitance per unit length, and CES is the electrostatic capacitance per unit length. Other high-frequency applications of CNTs are in the active mode of operation such as in nanotube transistors. While detailed theoretical models for the highfrequency properties of CNT transistors are not available at present, the device performance can be estimated using the following equation for cut-off frequency [44]: fT ¼

gm 2pCgs

where gm is the transconductance and Cgs is the gate–source capacitance. Predictions of the maximum frequency at which current gain can be achieved can be done assuming values of 20 mS for the transconductance. The predictions for fT versus gate length for a nanotube transistor are shown in Fig. 6.4.7. This figure indicates that nanotubes will surpass existing semiconductor devices and achieve cutoff frequencies in the terahertz range.

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FIGURE 6.4.7 Speculative prediction of fT versus gate length for CNT transistor compared to other semiconductor device technologies. (Derived from [44].)

6.4.3

Quantum-Cell-Based Wireless Interconnections

A digital signal can be propagated down a series of quantum cells by using what may be called ‘‘quantum wires.’’ These are wireless interconnections; that is, there is no actual contact between the cells. As shown in Fig. 6.4.8, the coulomb repulsion forces the adjacent cells to align in the same ‘‘1’’ or ‘‘0’’ orientation for the lowenergy state, that is, the ground state [45–49]. Hence, one can achieve wireless logic for propagation of signals. Based on this principle, quantum wires designed as a straight interconnection, to achieve a 90 bend and to obtain a fanout of 2 are shown in Fig. 6.4.9. In addition, quantum wires can be designed to carry crossover signals in the same plane. This kind of wireless connection eliminates the usual electromigration problems associated with metallic interconnections in conventional ICs. This also results in chip area saving and a much higher packing density. Quantum-cell-based interconnections form a part of a quantum cellular automata (QCA), which refers to an array of quantum cells that is fabricated at the nanometer scale and can be used to implement binary logic. These quantum cells can be arranged in principle to get all levels of circuit complexities from the basic logic gates such as inverters and adders to a complete nanocomputer. Though the current QCA-based circuit designs are limited to a single plane, it is possible that bilevel, trilevel, or even higher level circuits and interconnections will be used in future QCA designs.

FIGURE 6.4.8 cells.

Ground state resulting from coulomb interaction between two quantum

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FIGURE 6.4.9 Layouts of quantum cells used to (a) design straight wireless interconnection, (b) achieve a 90 bend, and (c) obtain a fanout of 2.

EXERCISES E6.1 List the problems that need to be solved before optical interconnections can be used for on-chip and chip-to-chip communications. E6.2 List the problems that need to be solved before superconducting interconnections can be used for on-chip and chip-to-chip communications. E6.3 Equation (6.2.29) can be used to determine the magnitude of Vin only and not its phase. Comment on the relative significance of the phase of Vin . E6.4 Based on the discussion in Section 6.2, show that VðzÞ and IðzÞ can be expressed as the weighted averages of the transverse electric and magnetic fields over the cross section of the waveguide. In particular, prove that      Z0 1 2 r o eEt r  Et VðzÞ ¼ dx dy Eðx; y; zÞ  jog m       Z Z 1 1 2 o mHt r  Ht IðzÞ ¼ dx dy Hðx; y; zÞ  r jogZ0 e Z

Z



E6.5 Prove that Eqs. (6.2.73)–(6.2.76) for R, L, G, and C result in the same values of the ratios in Eqs. (6.2.14) and (6.2.15). E6.6 List the problems that need to be solved before nanotube, nanowire, multipath, and quantum-cell-based wireless interconnections can become a reality for nanotechnology circuits.

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43. P. Burke, ‘‘Luttinger Liquid Theory as a Model of the Gigahertz Electrical Properties of Carbon Nanotubes,’’ IEEE Trans. Nanotechnol., vol. 1, no. 3, pp. 129–144, Sept. 2002. 44. P. Burke, ‘‘Carbon Nanotube Devices for GHz to THz Applications,’’ Proc. International Semiconductor Device Research Symposium, 2003. 45. C. Lent and P. Tougaw, ‘‘A Device Architecture for Computing with Quantum Dots,’’ Proc. IEEE, vol. 85, p. 541, 1997. 46. C. Lent, P. Tougaw, W. Porod, and G. Bernstein, ‘‘Quantum Cellular Automata,’’ Nanotechnology, vol. 4, p. 49, 1993. 47. C. Lent and P. Tougaw, ‘‘Lines of Interacting Quantum Cell Dots: A Binary Wire,’’ J. Appl. Phys., vol. 74, p. 6227, 1993. 48. J. Lusth, ‘‘Symmetric versus Asymmetric Charge Neutralization in Quantum-Dot Cellular Automata,’’ Nanotechnology Proceedings, 2001. 49. G. To´th and C. Lent, ‘‘Quasi-Adiabatic Switching for Metal-Island Quantum-Dot Cellular Automata,’’ J. Appl. Phys., vol. 85, no. 5, pp. 2977–2984, 1999.

Index Activation energy, 318, 322 Active interconnection(s), 230 driven by cascaded repeaters, 234 driven by minimum size repeaters, 231 driven by optimum size repeaters, 232 propagation delays in, 232, 235 Arrhenius plot, 326 Attenuation, 38 Bend, 345 CAD tools, 356 Capacitance(s), 46, 50 approximate formulas for, 57, 109 matrix, 263 parametric dependence of, 77, 99 Carbon nanotubes, 397 Characteristic impedance, 36, 39, 209 Compact expression(s), 216, 292 Copper interconnection(s), 5, 47, 119, 395 advantages, 6 challenges, 6 damascene processing, 9 electromigration, 341 fabrication, 7 resistance modeling, 119 Crossing interconnections, 168, 195, 280 Crosstalk, 242 compact expression(s), 292

dependence on interconnection parameters, 248, 260, 268, 284 reduction of, 251 Current crowding, 315 Current density, 318, 320 Delays, 136, 226, 230 compact expression(s), 216 dependence on interconnection parameters, 150, 158, 178, 214 Delay time, 41 Electromigration, 2, 49, 313 due to repetitive pulsed currents, 331 due to thermal effects, 320 effect of activation energy, 322 effect of current density, 320 effect of line length, 321 effect of line width, 321 in copper interconnections, 341 guidelines for testing, 325 mechanism, 316 problems caused by, 314 reduction of by alloying, 327 by substrate overcoating, 327 under AC conditions, 323 under direct currents, 337 under pulsed DC conditions, 323, 340 Encapsulation, 327

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

405

406

INDEX

Even-mode capacitances, 17, 73 for three coupled conductors, 19 for two coupled conductors, 17 FastHenry, 114 Fourier integral method, 84 Fourier transformation, 157 Frequency domain modal analysis, 253 GaAs, 2, 109, 302 GaAs-on-Si, 2 Galerkin method, 16 Gold interconnections, 328 Green’s function, 60, 84 matrix, 67 method, 60, 84 Ground bus, 347, 356 High-frequency effect(s), 203, 213 conductor loss, 205 dielectric loss, 206 effective dielectric constant, 204 model of, 203 skin-effect, 205 Hillocks, 2 Inductance(s), 52 matrix, 263 parametric dependence of, 104 simplified formulas for, 109 Inductance extraction, 55, 114 Interconnection(s), 2 active, 230 between logic gates, 141 copper, 5, 47 crossing, 168, 195 metallic, 391 MIS model of, 138 multilayer, 2 multilevel, 2, 84, 154 multipath, 2, 4, 30 nanotechnology, 390 nanotube, 392 nanowire, 391 optical, 5, 371 semi-infinite, 140, 219 single-level, 145 superconducting, 5 wireless, 399

Interconnection component(s), 344 bend, 345 ground bus, 347, 356 multipath(section) interconnection, 347, 355 overflow, 346, 355 plug, 345, 353 power bus, 347, 356 reduction into straight segments, 344 step, 345, 353 straight segment, 351 via, 347, 354 Inverse Laplace transformation, 25, 157 Joule heat, 315 Ladder network, 27 Lognormal distribution, 326 of failure times, 326 standard deviation, 348 Lumped-capacitance approximation, 243 Median-time-to-failure (MTF), 318, 348 effect of current density, 352 effect of line length, 351 effect of line width, 351 effect of temperature, 352 of interconnection components, 34 Metal loss, 40 Method of images, 10, 60, 67 Method of moments, 15 Miller’s theorem, 23 MIS model, 243 Multiconductor bus(es), 302 Multilayer interconnections, 2 Multilevel interconnections, 2, 84, 154, 264 Multipath interconnection(s), 2, 4, 30, 347 Nanotechnology interconnects, 390 Nanotube interconnection, 392, 397 comparison with copper interconnection, 395 Nanotube via, 394 Nanowire, 391 Nernst–Einstein equation, 317 Network analog method, 91 Noise measurement, 324

INDEX

Odd-mode capacitances, 17, 73 Optical waveguide, 375 Optical interconnection(s), 5, 371 advantages, 372 design issues, 374 material issues, 374 system issues, 373 Pade’ approximation, 25 Power bus, 347, 356 Propagation constant, 23, 36 Propagation delays, 41. See also Delays in active interconnections, 235 dependence on driving mechanism, 235 in multilayer IC, 226 Propagation mode(s), 31 quasi-TEM, 32 skin-effect, 32 slow-wave, 32 Propagation time, 41, 235 Quantum cell, 399 Quasi TEM mode, 32 RC models, 217, 294 Reliability, 328 Arrhenius model of, 329 Mil-Hbdk-217D model of, 329

407

series model of, 330 series-parallel model of, 330 RELIANT, 357 RF circuit model, 398 Repeaters, see Inverters Resistance(s), 46, 47 Resistance measurement, 323 Resistivity, 4, 228 Resistivity-frequency mode chart, 32 Rise time, 41 RLC models, 219, 221, 223, 224, 296, 299 Schwarz–Christoffel conformal mapping, 50, 139 Semiconductor loss, 40 Skin-effect, 48, 198 mode, 32, 34 Slow-wave mode, 32, 34 SPIDER, 358 Superconducting interconnections, 5, 386 Thermal effects, 320 Transmission line analysis, 154, 264 Transmission line theory, 21 Via, 347, 354, 394 Voids, 49

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