High-Performance Integrated Charge Pumps: Design and Novel Solutions 3031435966, 9783031435966

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Andrea Ballo Alfio Dario Grasso Gaetano Palumbo

High-Performance Integrated Charge Pumps Design and Novel Solutions

High-Performance Integrated Charge Pumps

Andrea Ballo • Alfio Dario Grasso • Gaetano Palumbo

High-Performance Integrated Charge Pumps Design and Novel Solutions

Andrea Ballo University of Catania Catania, Italy

Alfio Dario Grasso University of Catania Catania, Italy

Gaetano Palumbo University of Catania Catania, Italy

ISBN 978-3-031-43596-6 ISBN 978-3-031-43597-3 https://doi.org/10.1007/978-3-031-43597-3

(eBook)

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland Paper in this product is recyclable.

Preface

A Charge Pump (CP) is an electronic circuit that converts the input power supply voltage to a DC output voltage higher than the power supply (even several times). However, unlike the other traditional step-up or boost DC-DC converters, which rely on inductors, CPs are a class of voltage multipliers made up of capacitors and diodes or switches only. This kind of circuit has been extensively analyzed, designed, and used since the early days of electronics. Indeed, a patent on the first voltage multiplier with discrete capacitors and valve diodes was lodged by Schenkel in 1919, while in 1932 Cockcroft and Walton introduced a new voltage multiplier realized with discrete components, generating voltages up to millions of volts, which was generally used first in physical experiments to produce high-velocity ions and, later, in TV receivers. Thanks to their inherent feature of not requiring inductors, CPs are particularly appealing whenever a voltage value higher than the input power supply is required in the design of an Integrated Circuit (IC). Originally this design domain was limited to non-volatile memories, indeed the first integrated CP was presented in 1972 by Dickson. In his famous paper, a novel topology CP, suitable for full on-chip implementation, was designed to provide the voltage, higher than the power supply, to program an EEPROM. From the historical point of view, it is surely interesting that, to minimize the parasitic effects due to integrated implementation, the novel topology proposed by Dickson was not based on the Cockcroft and Walton one, but took inspiration (or was rediscovered) from the much older topology suggested by Schenkel. The ability to realize a voltage higher than the power supply fully inside an IC was found advantageous in the smart power ICs and, since the 1990s, CPs were also commonly used in that domain. CPs inside an IC became then much more common, since they have been used in a vast variety of integrated systems such as switched capacitor circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. For this reason, CPs have been extensively studied in the past and a significant effort has been devoted to the identification of new circuital solutions.

v

vi

Preface

Fig. 1 IEEE journals concerning charge pump circuits over the years

More recently, a further booster on the use of CPs was due to the relentless and increasing interest in the design of energy-autonomous microsystems, whose power supply relies on the scavenging of energy from the ambient by using different kinds of transducers, such as photovoltaic cells, thermoelectric generators, and piezoelectric devices. In this emerging context, which includes ultra-low-power nodes for the Internet of Things (IoT) and the Wireless Sensor Networks (WSNs), CPs are becoming essential building blocks. The increasing interest in the analysis and design of CPs and their application is clearly demonstrated by the exponential trend in the number of scientific papers dealing with CPs in the IEEE journal collection shown in Fig. 1. The main focus of this book is to provide readers with an in-depth understanding of the challenges involved in the design of a CP. Analysis, modeling, design strategies, and topologies are treated in detail. All the authors’ results in terms of novel and high-performance CP topologies and related design are organized in a coherent manner. Moreover, particular care is also devoted to ultra-low power and harvesting applications, which include many of the recent results by the authors. Indeed, since 1990 the authors have dedicated a lot of effort to the development of this topic. In recent years, many novel original results have been obtained, many of them devoted to the area of ultra-low power applications and energy harvesting systems. The basic theoretical foundations are provided to set the stage for the comprehension of analyses and results. Exhaustive methodologies are presented, and analytical

Preface

vii

derivations are included, thus allowing the reader to gain an insight into the main dependencies among the relevant circuit parameters. Although the material is presented in a formal and theoretical manner, much emphasis is spent on the design perspective with many practical examples and measured results. The book can be used as a reference for engineers and also for undergraduate, graduate, and postgraduate students, who are already familiar with basic electronic circuits and are willing to extend their knowledge of this specific field. The outline of the book is as follows. Chapter 1 discusses the basic topology of the Dickson CP, its simplified equivalent model, and key design parameters, along with optimal design procedures for different load conditions and performance targets. Chapter 2 is about the different implementations of CPs which vary according to the switch topology and their connection with the pumping capacitors. The chapter also includes a discussion and a comparison of the different regulation techniques. Chapter 3 deals with the time domain response and speed performance of a Dickson CP and introduces design techniques and innovative topologies to reduce the settling time. Chapter 4 is focused on integrated power management applications and discusses design strategies to increase the power conversion efficiency. Chapter 5 deals with the design strategies that allow the use of a Dickson CP in very-low voltage application, like energy harvesting systems. In particular, two novel topologies are introduced, analyzed, and discussed. Finally, Chap. 6 introduces an unconventional use of the Dickson CP as a signal amplifier which paves the way to a new field of applications for this widespread circuit. Catania, Italy

Andrea Ballo Alfio Dario Grasso Gaetano Palumbo

Acknowledgments

This work was partially funded by the European Union (NextGeneration EU), through the MUR PNRR project SAMOTHRACE (ECS00000022).

ix

Contents

1

Integrated Charge Pump Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Simplified Analysis of the Dickson CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Ideal One-Stage Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Ideal N -Stage Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 Node Voltage Values of a Dickson CP . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Dickson CP Parameters and Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Design of the Dickson CP with a Current Load . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Silicon Area Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Current (Power) Consumption Minimization . . . . . . . . . . . . . . . . . 1.3.3 Design Strategies Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Design of the Dickson CP with a Pure Capacitive Load . . . . . . . . . . . . . . 1.4.1 Silicon Area Occupation and Rise Time Minimization . . . . . . . 1.4.2 Charge Consumption Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Design Strategies Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Dickson Charge Pump Accurate Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 First-Order Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Model with Charge Loss Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 1 3 5 7 10 11 12 12 14 15 16 17 19 19 22 34

2

Variants and Evolutions of the Dickson CP Topology . . . . . . . . . . . . . . . . . . . 2.1 The Traditional Dickson CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Dickson CP with Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 The Charge Transfer Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 CTS Gate Biasing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 One-Transistor CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 CTS with an Auxiliary Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Double CPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 The Voltage Doubler and the Latched CP . . . . . . . . . . . . . . . . . . . . . 2.4 Adiabatic CPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Charge Pumps with an Adaptive Number of Stages. . . . . . . . . . . . . . . . . . . 2.6 CP Topologies: Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35 35 35 36 38 38 39 42 44 46 47 49 xi

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Contents

2.7 Regulation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.1 Output Resistance Modulation Schemes . . . . . . . . . . . . . . . . . . . . . . 2.7.2 Clock Amplitude Modulation Schemes . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53 54 58 61

3

Design Strategies High-Speed Dickson CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Optimized CP with Clock Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Rise Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Silicon Area Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Simulated Results and Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 CP with Linear Distribution of Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Simulated Results and Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

67 67 68 68 73 74 77 77 81 87

4

Design Strategies for Low-Power Dickson CP Applications . . . . . . . . . . . . 89 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.2 Clock Voltage Amplitude Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2.1 Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2.2 Validation and Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.3 Node Pre-charging Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.1 Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.2 Transistor Level Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3.3 Validation and Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5

Design Strategies for Very-Low-Voltage Dickson CPS. . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Very-Low-Voltage Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 CTS On-Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Very-Low-Voltage Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Modified Very-Low-Voltage Topology . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Remarks on the VLV and MVLV CP Topologies . . . . . . . . . . . . . 5.2.5 Validation and Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Hybrid Latched CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 CTS in Subthreshold Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Hybrid Latched Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Validation and Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Current-Mode Body-Biased CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Validation and Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

An Unconventional Application: The CP as a Signal Amplifier . . . . . . . . 141 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.2 DC and Small-Signal Modeling of the CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

105 105 106 106 107 109 111 112 118 118 121 123 129 129 134 137

Contents

6.2.1 DC Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 AC Behavior in SSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 AC Behavior in FSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Dickson CP as Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Large-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Validation of the Dickson CP as Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Transistor Level Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Experimental Results of a 4-Stage CP in 130-nm CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Experimental Results with 65-nm CMOS Technology . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiii

143 144 146 147 147 149 150 152 152 153 158 160

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Acronyms

Lists of abbreviations MOS CMOS MOSFET NMOS PMOS CP CTD SSL FSL PCE VCE D-SSL HV-CMOS CTS EEPROM DRAM SRAM FBB BBB DBB WL PMU TEG MIM TDDB CMBB VLV MVLV

Metal-Oxide-Semiconductor Complementary Metal-Oxide-Semiconductor MOS Field Effect Transistor N-type MOSFET P-type MOSFET Charge Pump Charge Transfer Device Slow Switching Limit Fast Switching Limit Power Conversion Efficiency Voltage Conversion Efficiency Deep Slow Switching Limit High Voltage-CMOS Charge Transfer Switch Electrically Erasable and Programmable Read-Only Memory Dynamic Random Access Memory Static Random Access Memory Forward Body Biasing Backward Body Biasing Dynamic Body Biasing Word Line Power Management Unit Termo-Electric Generator Metal-Insulator-Metal Time-Dependent Dielectric Breakdown Current Mode Body Biasing Very Low Voltage Modified Very Low Voltage xv

xvi

DIBL GBW SR THD IC LCD RF IoT WSN PCN

Acronyms

Drain-Induced Barrier Lowering Gain-BandWidth Slew Rate Total Harmonic Distortion Integrated Circuit Liquid Crystal Display Radio Frequency Internet of Things Wireless Sensor Network Printed Circuit Board

Chapter 1

Integrated Charge Pump Basics

1.1 Simplified Analysis of the Dickson CP 1.1.1 Ideal One-Stage Topology To show the behavior of an ideal CP, let us consider the one-stage topology in Fig. 1.1a, which comprises a single pumping capacitance, C, its related stage switch, .S1 , a switch .SOU T , needed to properly connect the output load to the CP stage, a clock signal with two complementary phases, whose amplitude is equal to the power supply .VI N (Fig. 1.1b), and a load modeled with a current generator .IL and a capacitor .CL . During the first half period, from 0 to .T /2, .S1 and .SOU T are, respectively, closed and open, and C, being connected to the power supply, is charged to .VI N (Fig. 1.2a); meanwhile, the output node is discharged by the current load, .IL , which sinks a charge .IL T /2. In the second half period, from .T /2 to T , the switches change their state (see Fig. 1.1b), the clock signal now equals .VI N , and part of the charge stored in C is both transferred to the capacitive load, .CL , and, for the amount of .IL T /2, again sunk by the current load. Hence, as shown in Appendix, VOU T |Steady−State = 2VI N −

.

IL T C

(1.1)

Several cycles are needed to approach the asymptotic value, and as shown in Fig. 1.3 where the output voltage of a one-stage charge pump is plotted,1 the step increment of the output voltage in each successive clock period becomes smaller.

case of study has the following parameters: .VI N = 1 V, .T = 1 ms, .C = 100 nF, and = 1 μ F.

1 The .CL

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 A. Ballo et al., High-Performance Integrated Charge Pumps, https://doi.org/10.1007/978-3-031-43597-3_1

1

2

1 Integrated Charge Pump Basics

Fig. 1.1 Ideal one-stage CP: (a) Circuit model; (b) Clock signal, .VCK

Fig. 1.2 Ideal one-stage CP: (a) first half period; (b) second half period

Indeed, the output voltage will steeply increase in the first part of the transient and will slowly tend to its final value. Following the above description, as the same name suggests, a Dickson CP takes charges from the power supply via the capacitor C, pumps these charges into the

1.1 Simplified Analysis of the Dickson CP

3

Fig. 1.3 Output voltage of the one-stage Dickson CP for different values of the output current

output load, and, thanks to the memory effect of the output capacitor .CL , increases the output voltage up to an ideal value that, neglecting the loss due to the current load, is ideally twice the power supply.

1.1.2 Ideal N-Stage Topology The one-stage Dickson CP can be generalized by including additional cascaded stages as shown in Fig. 1.4, where a generic N-stage CP is reported. Each stage is made of a pumping capacitor C and a switch .Si , with .i = 1, 2, 3, ..., N. Moreover, the N-stage CP needs a two-phase clock and, again, a switch .SOU T to connect the last CP stage to the output load. The behavior of a N-stage CP is of course a generalization of the one-stage CP behavior. In particular, during the first half clock period, .VCK is low and, according to Fig. 1.4, only the odd switches are closed. The first pumping capacitor is thus charged to .VI N , and all the other pumping capacitors of the odd stages receive the charge from the capacitor of the previous stage (this happens also for the load capacitor when the number of stages is even). During the other half clock period, the clock signal .VCK is equal to .VI N and only the even switches are closed. Then, all the capacitors of the odd stages transfer the charge to the capacitor of the subsequent stage (the load capacitor is maintained separated from the CP if the number of stages is even, since the switch .SOU T is open). In summary, in a complete clock period, each CP capacitor takes an amount of charge from the capacitor at its left side and transfers a part of this charge to the

4

1 Integrated Charge Pump Basics

Fig. 1.4 Ideal N-stage Dickson CP

capacitor at its right side. Thus, considering the CP in steady state during each period, there is a charge transfer from the power supply to the output load. In particular, from a quantitative point of view, the amount of charge exchanged in each half period between two adjacent capacitors is equal to .IL T , given that a CP has to provide such an amount of charge in each time period. Consider, for example, a two-stage CP with a current load, as shown in Fig. 1.5. During the first half period (in the steady state), the first capacitor is connected to the power supply and is recharged by .Q, which is the same amount of charge provided by the CP to the output (Fig. 1.5b). In the next half period, when the first and second pumping capacitors are connected together (Fig. 1.5c) since switch .S2 is closed, they exchange the same amount of charge, .Q, and the highest node voltage results to be V1 |VCK =VI N = V2 |VCKn =0 = V1 |VCKn =0 + VCK −

.

IL T IL T = 2VI N − C C

(1.2)

Finally, in the subsequent first half period, when the switches .S1 and .SOU T are closed (Fig. 1.5b), the output voltage is VOU T = V2 |VCKn =VI N = V2 |VCKn =0 + VCK −

.

IL T IL T = 3VI N − 2 C C

(1.3)

Extending the analysis to an N-stage CP, we get the asymptotic output voltage value as VOU T |Steady−State = (N + 1) VI N − N

.

IL T C

(1.4)

It is worth noting that, assuming the switches almost ideal (i.e., almost zero ONresistance), the charge transfer occurs in a very short time (zero for ideal switch). Thus, when .SOU T closes, the output voltage suddenly reaches its maximum value, and then, due to the presence of the current load .IL , during all the time period, it slightly decreases. This effect results in an output voltage ripple, .Vr , which, assuming C much smaller than .CL , is equal to Vr =

.

IL T CL

(1.5)

1.1 Simplified Analysis of the Dickson CP

5

Fig. 1.5 Ideal two-stage CP: (a) first half period; (b) second half period

1.1.3 Node Voltage Values of a Dickson CP Since the voltages in the CP nodes are higher than the power supply, to evaluate the voltage stress on each CP component, it is useful to compute the voltage on each CP node and across each switch. At this purpose, let us consider the voltage at the generic node j and analyze its value at the beginning and at the end of each half period. Without loss of generality, we can assume that in the first half period the capacitor of the stage j (with the clock signal low) is connected to the previous stage through the closed switch .Sj . Hence, during this half period, it receives a charge .Q from the capacitor in the stage (.j − 1). Denoting with .V the voltage variation on the CP capacitors due to the charge transfer .Q, the voltages at the beginning and the end of this half period are, respectively, expressed by Vi,start−lef t−sharing = j (VI N − V )

(1.6)

Vi,end−lef t−sharing = j (VI N − V ) + V

(1.7)

.

.

During the subsequent half period, when the switch .Sj is open and the switch Sj +1 is closed, the clock signal driving the stage j is high (i.e., there is a charge sharing with the capacitor in the stage .j + 1), and the voltages at the beginning and the end of the half period are, respectively, equal to

.

Vi,start−right−sharing = j (VI N − V ) + V + VI N

(1.8)

Vi,end−lef t−sharing = j (VI N − V ) + VI N

(1.9)

.

.

6

1 Integrated Charge Pump Basics

Fig. 1.6 Voltages of the nodes j and .j − 1 (above) and voltage across the switch .Sj (below)

Let us consider the switch .Sj , which connects capacitors at nodes .j − 1 and j , and evaluate the voltage across it, .Vj,j −1 = Vj − Vj −1 . This voltage is plotted in Fig. 1.6. At the end of the first half period, .Sj is closed, and consequently, the voltage across the switch is zero (point 2 in Fig. 1.6). At the beginning of the subsequent half period (.Sj open), the clock signal changes and the voltages at nodes j and .j − 1 fall and rise, respectively, by the clock amplitude. Hence, the voltage across the switch is equal to .Vj,j −1 = 2VI N (point 3 in Fig. 1.6). At the end of this half period, the capacitor at node j (.j − 1) gives (receives) charge .Q. Thus, as seen from point 4 in Fig. 1.6, the voltage at node j (.j − 1) reduces (increases) by .V and .Vj,j −1 = 2VI N − 2V . Finally, when .Sj is closed again and the charge transfer between capacitors at nodes .j − 1 and j begins, the clock signal changes, and the voltage across the switch is .Vj,j −1 = −2V (point 1 in Fig. 1.6). These voltage values are equal for all the CP switches and are summarized in Table 1.1. It is worth noting that the voltage across the switches depends on the clock amplitude (assumed, as usual, equal to the power supply) and on the voltage step, .V , which is given by V = VI N +

.

VI N − VOU T N

(1.10)

1.2 Dickson CP Parameters and Models Table 1.1 Switch voltages at various times

Time Beginning .Sj closed End .Sj closed Beginning .Sj open End .Sj open

7 Switch voltages .Vj,j −1 .−2V 0 .2VI N .2VI N − 2V

1.2 Dickson CP Parameters and Models The key design parameters of a CP are the number of stages, the silicon area occupation, and the current consumption. Moreover, especially for CPs with only a purely capacitive load, also the rise time and the charge consumption during the transient rise time are of importance. Concerning the clock frequency, despite it may appear as a design parameter, often it is set at the value of the clock used inside the system where the CP is used. The number of stages, N , is strictly related to the required output voltage, .VOU T , given by (1.4), and in the case of a pure capacitive load, it simplifies into .VOU T = (N + 1) VI N . Physical implementation of an integrated CP requires usually a not negligible silicon area, .AT OT , which is mainly due to the stage capacitors. Thus, the silicon area need to implement an integrated CP, .AT OT , can be simply approximated with the area required to implement the CP capacitors. Hence, defining with k the process parameter that links the silicon area needed to realize the kind of capacitors used and naming .CT OT the sum of the pumping capacitors, .NC, we get AT OT = kN C = kCT OT

.

(1.11)

Then, substituting (1.4) into (1.11), the area of a Dickson CP with a current load is equal to AT OT = k

.

IL N2 (N + 1) VI N − VOU T f

(1.12)

By inspection of (1.12), the Dickson CP area, as expected, is expanded increasing the load current and decreasing the clock frequency. Indeed, in both cases, to provide the required amount of charge, higher values of the pumping capacitors are needed. Moreover, as will be shown in Sect. 1.2 where the optimum number of stages is evaluated, the CP area also increases with the increase of the output voltage and with the reduction of the power supply value. In particular, while a linear dependence on 2 .VOU T holds, a dependence .1/V I N is observed regarding the power supply. The current consumption, .IVI N , can be considered as constituted by two contributions [1], namely a term due to the ideal CP behavior, .II N , and a term that accounts for the parasitic effects, .IP AR , thus yielding IVI N = II N + IP AR

.

(1.13)

8

1 Integrated Charge Pump Basics

Fig. 1.7 N -stage CP with bottom-side parasitic capacitive effects

The current .II N can be evaluated by considering that the amount of charge, .Q, delivered to the load and provided by the power supply, is transferred from one capacitor to another during each period and is expressed by II N = (N + 1)

.

Q = (N + 1) IL T

(1.14)

The same result can be achieved by using the transformation factor of the CP. We amplify the power supply of an .N + 1 factor and, in an ideal case without energy waste (i.e., by transferring all the power taken from the power supply to the output load), the current sunk by the CP is .N + 1 times higher than the load current. Without loss of generality and neglecting for the moment the cross conduction currents that arise when two adjacent switches provide a conductive path during commutation, the current .IP AR is mainly due to the charge and discharge in each time period, T , of the sum of the parasitic capacitance, .CP , shown in Fig. 1.7. Thus, we can write IP AR = N

.

CP VI N = αNCVI N f T

(1.15)

where the bottom plate parasitic capacitance, .CP , is assumed proportional to the pumping capacitance C through a factor .α. From (1.14), (1.15), and using (1.4) to express the total pumping capacitance, the total current consumption during the steady state is given by  IVI N = (N + 1) + α

.

 N2 VI N IL (N + 1) VI N − VOU T

(1.16)

where it can be observed that the current consumption, and hence the power consumption, depends neither on the clock frequency nor on the total Dickson CP capacitance, but it is linearly related to the current load, .IL . The rise time, .tr , which is the time required to achieve a defined output value .VOU T (tr ), is a parameter particularly useful for charge pump with purely capacitive load. Thus, by adopting the dynamic models of a CP with purely capacitive load

1.2 Dickson CP Parameters and Models

9

Fig. 1.8 Equivalent model of a CP

developed in [2–4], the CP rise time can be approximated with the relationship     CL (N + 1) VI N − VOU T (0) .tr = T N + 0.3N + 0.6 ln C (N + 1) VI N − VOU T (tr )

(1.17)

which for N much higher than 1 and normalizing the output voltage to the power supply as vx =

VOU T (tr ) VI N

(1.18)

vx0 =

VOU T (0) VI N

(1.19)

.

.

can be rewritten as tr = T N

.

  + CEQ N + 1 − vx0 ln CT OT N + 1 − vx

2 CL

(1.20)

where capacitance .CEQ is equal to .CT OT /3. As expected, to reach the output steady-state voltage, .(N + 1) VI N , (1.20) shows an infinite rise time. Moreover, it is apparent that .tr is affected by the load capacitance and the total CP capacitance, .CT OT . From (1.20), we can write VOU T (tr ) = (N + 1) VI N − [(N + 1) VI N − VOU T (0)] e

.

−

tr N Cf CL +CEQ

(

)

(1.21)

Hence, the dynamic behavior of a Dickson CP with purely capacitive load is equivalent to that of a simple RC circuit [3]. More specifically, the CP model is shown in Fig. 1.8 where REQ =

.

N Cf

(1.22)

and .VOU T (∞) is the output voltage in the steady state, given by (1.11). Again, for CP with purely capacitive load, it may be useful to evaluate the charge consumption, which is only delivered by the power supply to the CP during its rise time, and can be divided into three main contributions

10

1 Integrated Charge Pump Basics

QT = QL + QP U MP + QP AR

.

(1.23)

The charge .QL is the contribution given to the load, the charge .QP U MP is required during the transient by the pumping capacitors, and the charge .QP AR is the contribution wasted in the parasitic elements shown in Fig. 1.7 (note that the parasitic capacitance at the bottom plate, .CP , is generally more than one order of magnitude higher than that of the other plate). Taking into account the equivalent RC circuit in Fig. 1.8, we get   QL (tr ) + QP U MP (tr ) = (N + 1) CL + CEQ [VOU T (tr ) − VOU T (0)] (1.24)

.

During each clock period, the charge loss due to parasitic effects (required to charge and discharge the bottom plate parasitic capacitances of the pumping capacitor) can be modeled by .NCP VI N , and the contribution during the rise time is equal to QP AR (tr ) = NCP VI N

.

tr tr = αCT OT VI N T T

(1.25)

where the bottom plate parasitic capacitance, .CP , is assumed proportional to the pumping capacitance C through a factor .α. Substituting each contribution into (1.23), we get the expression of the total charge delivered by the power supply during the rise time as    N + 1 − vx0  CL + CEQ VI N QT OT (tr ) = (N + 1) (vx − vxo ) + αN 2 ln N + 1 − vx (1.26)

.

1.3 Design of the Dickson CP with a Current Load The typical design parameters for a CP with a current load are summarized in Table 1.2. Among the unknown entries (highlighted in bold characters), two of them can be evaluated by using (1.12) and (1.16). Then, starting the design of the Dickson CP by finding parameter N , we can follow two possible strategies: one minimizing the area and the other minimizing the power consumption. Indeed, as shown in Fig. 1.9 (which exemplifies the case in which .VI N = 1V , .VOU T = 4V , and .α = 0.1)2 area and current consumption are minimized for different values of N. 2 It

is worth noting that the normalized values of (1.12) and (1.16) are independent from some parameters as the clock frequency, f , the technology dependent coefficient, k, and the current load, .IL .

1.3 Design of the Dickson CP with a Current Load Table 1.2 CP design parameters with a current load

11 Parameter .VI N .IVI N .VOU T .IOU T .f = 1/T .CT OT ∝ AT OT N .α = CP /C

Comment Technology dependent Not known a priori Design constraint Design constraint System dependent Not known a priori Not known a priori Technology dependent

Fig. 1.9 Dickson CP current consumption and silicon area normalized to their minimum values versus N

1.3.1 Silicon Area Minimization To find the optimum N minimizing the silicon area, we must set to zero the derivative of (1.12) with respect to N. On the other hand, if we want to maximize the current provided to the load, we have to set to zero the derivative of current .IL evaluated from (1.4). In both cases, we get {2N [(N + 1) VI N − VOU T ] − N 2 VI N }

.

IL =0 f

(1.27)

which, solved for N, gives [5]  NAOP T = 2

.

 VOU T −1 VI N

(1.28)

12

1 Integrated Charge Pump Basics

And after solving (1.4) for C yields C=N

.

IL T (N + 1) VI N − VOU T

(1.29)

Then substituting .NAOP T in (1.29), we find the stage capacitor C.

1.3.2 Current (Power) Consumption Minimization The optimum N that minimizes current consumption is obtained by setting to zero the derivative of (1.16) with respect to N 1 + αNVI N

.

[(N + 2) VI N − 2VOU T ] [(N + 1) VI N − VOU T ]2

=0

(1.30)

Hence, solving for N , we get [1]     VOU T α −1 NIOP T = 1 + VI N α+1

.

(1.31)

Finally, substituting the optimum value of (1.31) in (1.29), we get the required value of C for the optimized design.

1.3.3 Design Strategies Comparison In order to compare the two considered design strategies, let us start evaluating the increase in silicon area of the minimum power consumption design, compared to the minimum silicon area design [1]. From (1.29) and using the values .NAOP T and .NIOP T , we obtain the Dickson CP total capacitance for minimization of silicon area and power consumption, respectively, as 

CT ,AOP T

.

CT ,IOP T

.

 VOU T IL T =4 −1 VI N VI N

2

α   1 + α+1 VOU T IL T

= −1 α VI N VI N α+1

from which the increase of silicon area is given by

(1.32)

(1.33)

1.3 Design of the Dickson CP with a Current Load

13

Fig. 1.10 Increment of capacitance (i.e., silicon area) in the case of power consumption optimization with respect to the case of area minimization

2

α 1 + α+1 CT ,IOP T − CT ,AOP T

. −1 = α CT ,AOP T 4 α+1

(1.34)

Relationship (1.34), which is plotted in Fig. 1.10, is a decreasing function of .α, and it is about equal to 0.4 and 0.2 (i.e., an area increase equal to 40% and 20%) for .α equal to 0.1 and 0.2, respectively. For .α much lower than 0.1 (not plotted), the minimum power consumption strategy requires a huge amount of silicon area. Let us now evaluate the incurred increase in current consumption with the minimum area design. Substituting (1.28) or (1.31) into (1.16), we find the expression of .IVI N for the minimum area and minimum current design strategies IVI N ,AOP T

.

IVI N ,IOP T =

.



    VOU T − 1 + 1 IL = 2 (1 + 2α) VI N

   V OU T − 1 + 1 IL 1 + 2α + 2 α + α 2 VI N

(1.35)

(1.36)

Then, the current increase is results

.

IVI N ,AOP T − IVI N ,IOP T IVI N ,IOP T

 T 2 (1 + 2α) VVOU − 1 +1 IN   −1 = √ T 1 + 2α + 2 α + α 2 VVOU − 1 + 1 IN

(1.37)

14

1 Integrated Charge Pump Basics

Fig. 1.11 Increment of current consumption (i.e., power consumption) in the case of silicon area minimization with respect to the case of minimum current consumption

By inspection of Fig. 1.11, where (1.37) is plotted, we see that the increment in .IVI N is a decreasing function of .α and an increasing function of the ratio .VOU T /VI N . In particular, for an ideal one-stage CP, the current consumption increase is, for the optimum area design, not higher than 20%. On the other hand, for .VOU T /VI N higher than 4, the current consumption increase is higher than 20%, provided that .α is lower than 0.15. Similar results that take into consideration CP efficiency instead of current consumption are found in [1].

1.4 Design of the Dickson CP with a Pure Capacitive Load The design parameters involved in the design of a CP with purely capacitive load are summarized in Table 1.3 and can be obtained from relationships (1.11), (1.20), and (1.26). The first parameter to be set is the number of stages. However, even if (1.10) relates N and the steady-state output voltage in a simple way, it cannot be practically used, since this value is ideally reached after an infinite time. Again, as for the case of current load discussed above, we can follow different design strategies. Indeed, analyzing the plot in Fig. 1.12, where normalized (to their minimum values) .QT OT and .CT OT are plotted versus N, two different minima appear. Hence, before starting the design procedure, we have to clearly identify the main design target, in order to use the design approach that allows to optimize the chosen performance.

1.4 Design of the Dickson CP with a Pure Capacitive Load Table 1.3 CP design parameters with a pure capacitive load

Parameter .VI N .QT OT .VOU T (tr ) .tr .f = 1/T .CT OT ∝ AT OT N .α = CP /C

15 Comment Technology dependent Not known a priori Design constraint Design constraint System dependent Not known a priori Not known a priori Technology dependent

Fig. 1.12 .QT OT and .CT OT normalized to their minimum values versus N

1.4.1 Silicon Area Occupation and Rise Time Minimization To find the optimum number of stages that minimizes the silicon area, we must evaluate .CT OT through (1.20) and set to zero its derivative with respect to N . Similarly, the optimum N that minimizes the rise time is found by directly setting to zero the derivative of (1.20). In both cases, we get .

− 2 ln

  1 1 N + 1 − vx − +N =0 N + 1 − vx N + 1 − vx0 N + 1 − vx0

(1.38)

The above expression can be simplified using the empirical approximation (very accurate for x ranging from 0.3 to 1 [3]) .

ln x ≈

2x 2 − x − 1 3x

(1.39)

16

1 Integrated Charge Pump Basics

And, after some algebraic simplifications, (1.38) becomes .

(vx − vx0 ) [4vx + 2vx0 − 3 (N + 2)] =0 [(N + 1) − vx ] [(N + 1) − vx0 ]

(1.40)

from which the optimum N minimizing both total capacitance and rise time is NAOP T =

.

4 2 vx + vx0 − 2 3 3

(1.41)

4 (vx − 1) 3

(1.42)

Being .vx0 often equal to 1, we get NAOP T =

.

Once .NAOP T is defined, we can use the rise time constraint, given by (1.20), to evaluate the required total pumping capacitance and, hence, the value of C.

1.4.2 Charge Consumption Minimization To find the optimum number of stages that minimizes charge consumption, we take the derivative of (1.26) and set it to zero .

(vx − vx0 ) + 2αN ln

vx − vx0 (N + 1) − vx0 =0 − αN 2 (N + 1) − vx [(N + 1) − vx ] [(N + 1) − vx0 ] (1.43)

To solve (1.43), we again approximate the logarithmic term. We now use the linear approximation that minimizes the error in the range 0 to 1 [3] .

ln x ≈ 2 (x − 1)

(1.44)

Thus (1.43) becomes 1+

.

4αN αN 2 =0 − (N + 1) − vx0 [(N + 1) − vx ] [(N + 1) − vx0 ]

(1.45)

or equivalently .

(1 + 3α) N 2 − [vx + vx0 + 4α (vx − 1) − 2] N + (vx − 1) (vx0 − 1) = 0 (1.46)

Since .vx0 is often equal to 1, the optimum number of stages minimizing charge consumption is expressed by

1.4 Design of the Dickson CP with a Pure Capacitive Load

NQOP T =

.

17

1 + 4α (vx − 1) 1 + 3α

(1.47)

Again, once .NQOP T is calculated, we find the pumping capacitor, C, for the required rise time by using relationship (1.20).

1.4.3 Design Strategies Comparison To perform a comparison of the design strategies discussed above, we evaluate the area overhead caused by the minimum power consumption design and the charge consumption overhead caused by the minimum silicon area design [3]. As already stated, the silicon area can be directly derived from the CP total capacitance; hence, evaluating (1.20) for each design strategy, we get tr,AOP T = T

.

tr,QOP T = T

.

CL + CEQ CT ,QOP T

CL + CEQ CT ,AOP T 



4 (vx − 1) 3

1 + 4α (vx − 1) 1 + 3α

2

2

 ln

ln 4  1 +4 α

(1.48)

(1.49)

where .CT ,AOP T and .CT ,QOP T are the pumping total capacitances in the cases of area and charge consumption minimization, respectively. Assuming a given rise time to be achieved by both design strategies, by equating (1.48) and (1.49), we can evaluate the increased total CP capacitance for the optimized power consumption design with respect to the minimum area design. It results to be

.

CT ,QOP T − CT ,AOP T = CT ,AOP T



 3 1 + 4α 2 ln 4 1 + 3α



1 α

 +4

ln 4

−1

(1.50)

Relationship (1.50) is a decreasing function of .α as can be seen from its plot in Fig. 1.13. It is apparent that the area increases by 25% to 5% for .α ranging from 0.1 to 0.5. To compare the charge consumption of the two design strategies, we substitute N from (1.42) and (1.47) into relationship (1.27) (assuming as usual .vx0 equal to 1), and we get

QT ,AOP T =

.

4 (vx − 1)2 + α 3

  2   4 2 (vx − 1) ln 4 CL + CEQ VI N 3

for the area minimization design, and

(1.51)

18

1 Integrated Charge Pump Basics

Fig. 1.13 Increase on total CP capacitance of the minimum power consumption design with respect to the minimum area design

Fig. 1.14 Increase on charge consumption (i.e., power consumption) of the minimum silicon area design with respect to the minimum consumption design

QT ,QOP T

.

  1 + 4α 1 + 4α 2 2 = (vx − 1)2 (vx − 1) + α 1 + 3α 1 + 3α     1 +4 CL + CEQ VI N × ln α

(1.52)

for the charge consumption minimization design. Hence, the increase of the charge consumption incurred by the minimum area design is given by

1.5 Dickson Charge Pump Accurate Modeling

.

QT ,AOP T − QT ,QOP T = QT ,AOP T

 1 + α 34 ln 4   − 1 1 1 + α 1+4α ln + 4 1+3α α 3 4

1+4α 1+3α

19

(1.53)

By inspection of Fig. 1.14 where relationship (1.53) is plotted, we can see that (1.53) is a decreasing function of .α and is always lower than 15% for typical .α values.

1.5 Dickson Charge Pump Accurate Modeling In this section, we present a more accurate model than the one shown in the previous Sect. 1.2 in order to take into account the effect of charge loss nonidealities, thus including the limits of the charge transfer between the stages [6]. Moreover, for completeness, the validation of the analytical results (through both SPICE simulations and measurements) will be also included.

1.5.1 First-Order Model Let us consider the simplified block diagram of a N-stage Dickson CP in Fig. 1.15, and assume each switch as a two-terminal building block that will be named charge transfer device (CTD) [7–9]. The CTD, whose implementation and behavior will be better and in-depth treated in the next chapter, aims to unidirectionally transfer the charge from one stage to the following one. Moreover, assume the amplitudes of the clock signals, .VCK and .VCKn , equal to the input voltage, .VI N . Under this condition and the usual assumption of equal capacitance for each stage, the charge losses can be considered the same for each CTD device. Of course, according to Fig. 1.15, the load is represented by capacitance .CL and current .IOU T . Under the assumption that the CP works in slow switching limit (SSL), which means the charge in each clock semi-period is totally transferred from one pumping capacitor to the following, we can model it with the RC-equivalent circuit in Fig. 1.16. In particular, in the model in Fig. 1.16, .VI N and .VOU T represent the steady-state input and the output voltage increments, respectively. The ideal transformer models the power conversion, whose ideal conversion factor, .GCP ,i , is

Fig. 1.15 Generic N -stage Dickson CP

20

1 Integrated Charge Pump Basics

Fig. 1.16 First-order Dickson CP model

equal to .N + 1, and .ROU T ,i and .CEQ,i are, respectively, the ideal output resistance and self-capacitance expressed by N . fC

(1.54a)

A (N) C N +1

(1.54b)

ROU T ,i =

.

CEQ,i =

where f is the clock frequency and .A(N), function of the number N, is defined in [10] as   N 4N 2 + 3N + 2 . .A (N) = 12 (N + 1)   N 4N 2 − N − 3 A (N) = 12

(1.55a) (1.55b)

Equations 1.55a and 1.55b are valid for N even and odd integers, respectively. According to the model in Fig. 1.16, the CP time-domain dynamic (within the SSL) is only characterized by the time constant   τCP ,i = ROU T ,i CEQ,i + CL

.

(1.56)

in which the product .ROU T ,i · CEQ,i represents the ideal intrinsic time constant of the CP. In a more realistic case, the finite resistance of the CTD, .RD , and the top stray capacitances of the pumping capacitors, .CT , limit the charge transfer, and a more accurate model of the output resistance was proposed in [11] ROU T =

.

RD δ



δ τf

     δ δ + cosh−1 N coth τf τf

(1.57)

where .δ ≤ 0.5 is the duty cycle of the clock signal, and the time constant .τ = RD (C + CT ) leads the inter-stage conduction transient. By inspection of (1.57), .ROU T shows the same behavior of (1.54a) when .δ/f >> τ , i.e., when the clock frequency is enough small to allow the total charge transfer (i.e., SSL). When .δ/f ≤ τ , the charge is only partially transferred from one stage to the other and .ROU T approaches its minimum .RD (N + 1)/δ. Thus, in this regime, which is

1.5 Dickson Charge Pump Accurate Modeling

21

referred to as fast switching limit (FSL), the voltage multiplier shows an output resistance given by the effective resistance of the single CTD, .RD /δ, times their number N+1, thus according the established knowledge acquired on the domain of the switched capacitor converters [12]. Note also that the factor .1/δ comes from the fact that the charge transfer through each switching device is limited by the minimum conduction time window .δ/f . We can generalize the expression of the intrinsic time constant in (1.56) according to   τCP = ROU T CEQ + CL

.

(1.58)

where .CEQ includes also parasitic effects of the top stray capacitances CEQ =

.

A (N ) (C + CT ) N +1

(1.59)

Another effect due to the parasitic capacitance .CT is to decrease the effective gain of the CP, since it determines a charge partition with C (also affected by a possible drop voltage, .VD , due to nonidealities of the charge transfer device). In particular, the gain from its ideal maximum value, .N + 1, reduces to  GCP =

.



N 1+

CT C

+1

1−

VD VI N



 =

  N VD +1 1− 1 + αT VI N

(1.60)

The parameter .αT is the ratio between top stray capacitance and the pumping capacitance and only depends on the adopted technology. In conclusion, the complete expression of the output voltage, including an output demanded current, .IOU T , and assuming the output initial voltage equal to zero, is given results VOU T = VI N GCP

.

  t 1 − exp − − ROU T IOU T τCP

(1.61)

To have a complete overview of the Dickson CP, it is useful to represent the power conversion efficiency (P CE), defined as the ratio between output and input power (i.e., .P CE = POU T /PI N ). By inspection of Fig. 1.16, P CE can be simply derived since we have   IOU T 1 + GCP ROU T .PI N = POU T (1.62) VOU T From relationship (1.62), as expected, it is apparent that to increase the CP efficiency, which means to make .PI N closer to .POU T , the CP output resistance should be made as small as possible, which in other terms means to increase the pumping capacitance or the clock frequency and to lower the CTD on-resistance.

22

1 Integrated Charge Pump Basics

In practical cases, a further term should be added to the relationship (1.62) in order to take into account the switching power losses of the stray capacitances tied to the bottom plate of each pumping capacitor. Indeed, like for digital circuits, the switching power losses are due to continuous commutations on the switched nodes. In particular, in the CP, the commuted nodes are connected to the pumping capacitors plates, and considering the steady-state behavior, where all nodes experience the same voltage variation (equal to the clock amplitude, .VCK ), naming .CB the contribute of the bottom plate capacitance of each CP capacitor, the total switching power losses are given by PLOSS,SW = N (CB + CT ) f VI2N

.

(1.63)

Thus adding Eq. (1.63) to the second term of (1.62), we get the whole power conversion efficiency as  −1 N (CB + CT ) f VI2N IOU T POU T = 1 + GCP ROU T + .P CE = PI N VOU T VOU T IOU T

(1.64)

1.5.2 Model with Charge Loss Nonidealities To consider and analyze a more realistic scenario, charge loss nonidealities should be accounted in a CP model [6]. At this purpose, let us consider the generic single-stage equivalent circuit shown in Fig. 1.17a. In the model of a CTD, we have to account for the voltage drop .VD , the charge partition between C and .CT , already considered as voltage losses, the switching-resistance .RD /δ, and, as shown in Fig. 1.17b, also four current sinks and the leakage resistances of the pumping capacitors. The current sinks .IDi+1,L and .IDi+1,R model constant charge leakages seen at the left (input) and the right (output) terminal of the CTD, respectively. Their sizes can be different, like for a diode, or, at the least of any asymmetries, be the same as for a diode-connected MOSFET where the charge losses coincide, as first approximation, with the reverse saturation current of the reverse biased diffusion S/D to substrate junctions. However, it is worth noting that in the stage cascade the right terminal of the i-th and the left terminal of the (.i + 1)-th CTD, where .i = 1, 2 . . . , N , are electrically connected together and, assuming the current losses be the same for all CTDs, their effect results in a whole output referred current loss .ISU B = ID,L + ID,R , so considered hereinafter. Concerning the currents that reversely flow through the interdicted CTDs (i.e., .IDi+1,REV and .IDi+2,REV in Fig. 1.17b), being in steady state the voltages that turn off the CTDs equal to 2.VI N [3], the two generators can be assumed equally sized. And this allows to consider the value of both generators equals to .IREV . Consider, however, that such currents act differently on the capacitors involved

1.5 Dickson Charge Pump Accurate Modeling

23

Fig. 1.17 Single-stage CP: (a) generic block scheme; (b) equivalent model with parasitics current loss; (c) and the simplified model used in the analytical explanation

in the charge path during the single clock semi-cycle. In particular, looking at Fig. 1.17c, the leftmost current generator effectively sinks charge from the nearest pumping capacitor. From the point of view of the simplified model, a current .IREV is subtracted to the transferred one and apparently lost but, excluding the first stage where the turned-off CTD sees the input voltage source tied to its left side, the current provides a charge injection to the pumping capacitor of the previous stage. This mode described above characterizes the working principle of the rightmost current generator, which instead increases the level of charge in its nearest capacitor. Intuitively, it is apparent that such current is not lost. However, analysis results, as confirmed by the validation ones, show that reverse currents determine self-power consumptions and functional limitations of the CP. As last, leakage resistance, .RC , models nonideality of the dielectric of the pumping capacitor, while .CB represents its bottom plate stray capacitance. It is worth noting that .CB does not considerably affect the CP open-circuit output transient response if the driving capability of the clock drivers is high enough. This condition is satisfied almost always, and, for this reason, such contribute is neglected in the following. Similarly, the effect of .RC can be neglected if the intrinsic inter-

24

1 Integrated Charge Pump Basics

Fig. 1.18 Charge transferring time slot in the steady state for: (a) first stage, (b) intermediate stage, and (c) last stage

stage time constant .τ is sufficiently lower than .τC = CRC , which is equivalent to assume .RC >> RD . This assumption is accounted in the following analytical explanation also. Extending the switch-resistance-aware Dickson CP model already presented in [11], the equation between .VOU T and .IOU T is carried out including the reverse and substrate current losses and assuming the charges not fully transferred due to the resistance .RD of the CTD. Without loss in consistence, the effect of the constant voltage drop, .VD , of the CTDs and the parasitic capacitance .CT are neglected in this following. In Fig. 1.18, it shows several combinations among the voltage multiplier in steady state. The period when the switch turns on, .δT , is assumed to be equal to the period when the switch turns off and .T (=1/f ) is the period of the clock. Let us indicate as .Vi = Vi (t) the voltage at node i (.1 ≤ i ≤ N ), with .Vi,i the initial voltage of .Vi in the first half of the period and with .Vi,f the final voltage of .Vi in the same half period. Additionally, let us indicate with .V˜i,i(f ) the initial (final) voltage of .Vi in the second half of the period.

1.5 Dickson Charge Pump Accurate Modeling

25

Although the CTD on-resistance varies with the node voltages, it is assumed that RD is constant and represents the averaged value during .δT . From Fig. 1.18, during .δT , the below relationships hold .

C

.



VI N − V1 dV1 = + (IREV − ISU B ) . dt RD 2i −C dV dt = 2i+1 C dVdt

−C

=

V2i −V2i+1 RD V2i −V2i+1 RD

+ (IREV + ISU B ) + (IREV − ISU B )

(1.65a)

.

VN − VOU T dVN = + (IREV + ISU B ) RD dt

(1.65b)

(1.65c)

The initial and final voltages at each capacitor node in each half period are related to one another according to .

V˜2i−1,f − VI N = V2i−1,i .

(1.66a)

V˜2i−1,i = V2i−1,f + VI N .

(1.66b)

V˜2i,f + VI N = V2i,i .

(1.66c)

V˜2i,i = V2i,f − VI N

(1.66d)

And the steady state indicates the following relations for each pumping capacitor: . .

  C V1,f − V1,i = [IOU T + (N + 1) ISU B + IREV ] T − ISU B (1 − δ) T (1.67a) ⎧   ⎪ ⎪ ⎪C V2i,f − V2i,i = − [IOU T + (N + 2 − 2i) ISU B + IREV ] T ⎪ ⎨ +ISU B (1 − δ) T (1.67b) .   ⎪ C V2i+1,f − V2i+1,i = [IOU T + (N + 1 − 2i) ISU B + IREV ] T ⎪ ⎪ ⎪ ⎩ −ISU B (1 − δ) T   C VN,f − VN,i = − [IOU T + 2ISU B + IREV ] T + ISU B (1 − δ) T (1.67c)

where .(IOU T + ISU B )T is the charge transferred to the output terminal in a period and .ISU B (1 − δ)T is the part of the charge not transferred during the conduction phase. From the conditions .V1 (0) = .V1,i and .V1 (δT ) = .V1,f , (1.65a), we get V1,f = [VI N − RD (ISU B − IREV )] (1 − ζ ) + V1,i ζ

.

(1.68)

26

1 Integrated Charge Pump Basics

where .ζ is equal to .exp (−δT /CRD ). The first and second parts of (1.65b) have to be combined to obtain differential and common mode equations (i.e., .d (V2i − V2i+1 ) /dt and .d (V2i + V2i+1 ) /dt, respectively). Thus singularly solving and using them to obtain the final node voltage values yield   1 V2i,i 1 + ζ 2 + V2i+1,i 1 − ζ 2 2   δT −RD IREV 1 − ζ 2 − 2 ISU B . C    1 V2i+1,i 1 + ζ 2 + V2i,i 1 − ζ 2 = 2   δT 2 +RD IREV 1 − ζ − 2 ISU B C

V2i,f =

.

V2i+1,f

(1.69a)

(1.69b)

Finally, (1.65c) results in VOU T =

.

VN,f − VN,i ζ RD (ISU B + IREV ) 1−ζ

(1.70)

Let us calculate the final voltage at each node whose sum will give the output voltage. From (1.68) and (1.67a), .V1,f is calculated as V1,f = VI N − [IOU T + (N + δ) ISU B + IREV ]

.

T ζ − RD (ISU B − IREV ) C 1−ζ (1.71)

From the first to the last stage, the exact solution of voltage in each intermediate node needs the knowledge of the voltage value of the node itself, its previous and its following ones in an entire clock period. This is allowed considering that during the second half period, equations that describe the node voltage of stages that transfer charge, superscripted with “.˜·,” show the same form of (1.65b), which results in (1.69a) and (1.69). Therefore, from (1.69a) and using conditions (1.66a), (1.66b), and (1.66d), voltage of the odd-order nodes at the end of a complete cycle results V2i−1,i = .

  1 V2i−1,f 1 + ζ 2 + V2i,f 1 − ζ 2 2     δT RD IREV ISU B 1 − ζ2 + − VI N + C 2

(1.72)

which is completed by replacing the bottom-placed relationship of (1.67b) V2i,f = V2i−1,f + A2i.

.

(1.73a)

1.5 Dickson Charge Pump Accurate Modeling

27

A2i = 2VI N − [IOU T + (N − 2i + 2δ) ISU B + IREV ]

2 T + RD IREV C 1 − ζ2 (1.73b)

Similarly, from (1.69b) and (1.67b), V2i+1,f = V2i,f + B2i+1.

(1.74a)

.

B2i+1 = − [IOU T + (N + δ − 2i + 1/2) ISU B + IREV ] −

T 2ζ 2 C 1 − ζ2

T ISU B 2δ − 1 + RD IREV C 1 − ζ2

(1.74b)

Summarizing, from (1.73a) and (1.74a), the following relationship is given V2,f = V1,f + A2 V3,f = V2,f + B3 V4,f = V3,f + A4 V5,f = V4,f + B5 .

...

(1.75)

VN,f = VN −1,f + AN

VN,f = V1,f +

N/2  i=1

A2i +

N/2−1 

B2i+1

i=1

Therefore, replacing (1.71), (1.73b), (1.74b) in the last of (1.75) yields VN,f .

  1 + ζ2 ζ T N = (N + 1) VI N + NRD IREV − (IOU T + IREV ) + C 1 − ζ2 1 − ζ2     1 + ζ2 2ζ T (1 + δ) ζ ISU B N + RD − − [(N + 1) /2 + δ] + 2 2 1−ζ C 1−ζ 1−ζ (1.76)

From (1.70) and (1.67c), we get VOU T = VN,f + RD (IREV + ISU B ) − [IOU T + (1 + δ) ISU B + IREB ]

.

and, finally, from (1.76) and (1.77) yield

ζ 1−ζ (1.77)

28

1 Integrated Charge Pump Basics

VOU T = (N + 1) (VI N + RD IREV ) .

− {IOU T + [(N + 1) /2 + δ] ISU B

T + IREV } C

  1 + ζ2 2ζ N + 1 − ζ2 1 − ζ2 (1.78)

Equation (1.78) can be rewritten in a more compact form as VOU T = GCP ,i (VI N + RD IREV ) − {IOU T + [(N + 1) /2 + δ] ISU B + IREV }

.

ROU T (1.79) where .ROU T is the CP output resistance given by (1.57), in which the exponential terms have been replaced with the hyperbolic functions. By inspection of (1.79), it is straight evident as the various current sources weigh on the CP output behavior. In particular, the effect of each single type of current is measured by the coefficient for that it is multiplied. For simplicity, each single coefficient is reported in the following: .

−

T ∂VOU T = ∂IOU T C

  1 + ζ2 2ζ = ROU T N + 1 − ζ2 1 − ζ2

∂VOU T T .− = [(N + 1) /2 + δ] C ∂ISU B ∂VOU T T .− = ∂IREV C

(1.80)

  1 + ζ2 2ζ = [(N + 1) /2 + δ] ROU T N + 1 − ζ2 1 − ζ2 (1.81)

  1 + ζ2 2ζ N − (N + 1) RD = ROU T − (N + 1) RD + 1 − ζ2 1 − ζ2 (1.82)

i.e., the coefficients in (1.80)–(1.82) have the same meaning of equivalent resistive contributions that weight the effect of the single current on the steady-state output voltage. It is worth noting that when .IREV = ISU B = 0, (1.79) differs from (1.61) only for the factor .GCP that gathers the effect of the top stray capacitance of the pumping capacitors and the CTD voltage drop. For completeness, another effect of the capacitance .CT is the increase of the total capacitive contribution of the single charge path, which is equivalent to have (.C + CT ) instead of C in all the equations reported in this section. Relationship (1.79) is here validated by the first three plots reported in Fig. 1.19 where, more specifically, (1.80), (1.81) and (1.82) are compared with SPICE simulation results as a function of the normalized clock frequency for CPs with various numbers of stages. In these plots, .RD has been set to 10 .k, .C = 100 pF, .δ = 0.5 and .CT = 0.

1.5 Dickson Charge Pump Accurate Modeling Fig. 1.19 Comparison between SPICE simulations and: (a) Eq. (1.80), (b) Eq. (1.81), and (c) Eq. (1.82)

29

30

1 Integrated Charge Pump Basics

Fig. 1.20 Voltage gain versus the different current losses

Fig. 1.21 Advanced Dickson CP model

As it can be noted, there is a very good accuracy between simulations and the compared equations, with a maximum relative percentage error of about 5%. Effects of the two losses on the voltage gains are also shown in Fig. 1.20, where output-toinput voltage ratio is plotted for 2-, 4-, and 8-stage CPs when the CP works in the two extremes of SSL and FSL. The last term of equations (1.80)–(1.82) shows as the parameter is in relationship with the CP output resistance .ROU T . This comparison allows to introduce an advanced equivalent model that accounts for charge loss nonidealities. In particular, the current sinks, functions of .IREV and .ISU B , are added as compared to the conventional model, according to the model shown in Fig. 1.21, where .VI N and .VOU T are replaced to their increments. It is worth noting that nullifying the output current, for the proposed model the CP open-circuit output voltage depends on the clock frequency. In fact, two drawbacks caused by current losses are: • Reduction of the maximum open-circuit output voltage • Introduction of an undesired like-pole behavior in the voltage gain, as can be seen in Fig. 1.22

1.5 Dickson Charge Pump Accurate Modeling

31

Fig. 1.22 Simulation results of open-circuit voltage gain vs. normalized frequency for a different number of stages (.IREV = ISU B = 100 nA)

This point is not predicted by previous models. Figure 1.23a and b shows as the voltage gain curves change for different values of current .ISU B and .IREV , distinctly. As can be seen, output nodes reach their maximum values as slow as the current increases. In that figure, the output voltage of a sub-group of CPs (to be precise, only the CPs with an even number of stages) has been reported, but we assure that the results are independent by the order of N. An analytical expression for the general poles is found by searching the clock frequency at which the output voltage approaches its halved maximum value, which is equivalent to the definition of the root at .−3 dB in a Bode magnitude diagram. Thus, from (1.79), assuming these frequencies fall in SSL dominion, we obtain .

fp,ISU B =

1 (GCP − 1) (GCP + 1) ISU B . 2π C [GCP VI N + 0.5GCP (GCP + 1) RD ISU B ]

(1.83a)

fp,IREV =

2IREV 1 GCP − 1 2π GCP C (VI N + 3RD IREV )

(1.83b)

The presence of these poles, which effectively limit the response of the Dickson CP when exploited in low-power applications, suggests the introduction of a new limit, which we refer to as Deep-SSL (D-SSL). Finally, the charge loss nonidealities determine self-power dissipation for the CP, which must be accounted in the evaluation of PCE. Such power losses can be calculated starting from the coefficients expressed in (1.80)–(1.82) and are given by

32

1 Integrated Charge Pump Basics

Fig. 1.23 Simulation results of open-circuit voltage gain vs. normalized frequency for the evenorder Dickson CPs at various: (a) .ISU B and (b) .IREV

 PLOSS,ISU B = ROU T

.

N +2 ISU B 2

2 .

2 PLOSS,IREV = [ROU T − (N + 1) RD ] IREV

(1.84a) (1.84b)

Relations (1.84) have to be added to (1.62) and (1.63) to completely compute the input power. A further and in-depth validation of the accurate model also on experimental results carried out with a different number of stages and implemented by using two different technology nodes (a 130-nm HV-CMOS and a 65-nm standard CMOS) can be found in [6].

Appendix: Output Voltage of the One-Stage Dickson CP

33

Appendix: Output Voltage of the One-Stage Dickson CP Let us start by considering the CP in Fig. 1.2 without the current load. During the first half period (with .S1 closed and .SOU T open), C is charged up to .VI N , while .CL holds its charge. In the second half period (with .S1 open and .SOU T closed), there is a charge redistribution between C and .CL , and during a generic period, j , we get VOU T (j ) = V2 (j ) =

.

C · 2VI N + CL · VOU T (j − 1) C + CL

(1.85)

Assuming that in the initial state .VOU T (0) = VI N , we get C VI N C + CL   CL C VI N 1+ + C + CL C + CL

VOU T (1) = VI N +

.

VOU T (2) = VI N

.

(1.86)

(1.87)

after one and two clock periods, respectively. Hence, relationship (1.85) can be rewritten as [13–15] VOU T (j ) = VI N +

.

i j −1   CL C VI N C + CL C + CL

(1.88)

i=0

which, by using the property of power series,3 becomes

VOU T (j ) = VI N + 1 +

.



CL C + CL

j  (1.89)

VI N

whose limit for .j → ∞ is .2VI N . If the CP has also a current load (as shown in Fig. 1.3), relationship (1.85) still holds. Indeed, with .CL much higher than C, the discharge due to .IL can be assumed equal in both the half periods. However, we have now a different initial condition, since (1.86) is now reduced by a factor .(IL T )/CL . Thus, (1.88) changes into  VOU T (j ) = VI N +

.

3 Remember

IL T C VI N − CL C + CL

j −1 that, for .x < 1, one has that . i=0 x =

1−x i 1−x

 j −1  i=0

.

CL C + CL

i (1.90)

34

1 Integrated Charge Pump Basics

which is equivalent to

VOU T (j ) = VI N + 1 +

.



CL C + CL

j  

 VI N −

1 1 + C CL



 IL T

(1.91)

whose limit for .j → ∞ (with .CL much higher than C) is relationship (1.1).

References 1. Palumbo, G., Pappalardo, D., & Gaibotti, M. (2002). Charge-pump circuits: powerconsumption optimization. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 49(11), 1535–1542. https://doi.org/10.1109/TCSI.2002.804544 2. Tanzawa, T., & Tanaka, T. (1997). A dynamic analysis of the Dickson charge pump circuit. IEEE Journal of Solid-State Circuits, 32(8), 1231–1240. https://doi.org/10.1109/4.604079 3. Palumbo, G., Barniol, N., & Bethaoui, M. (2000). Improved behavioral and design model of an n-th order charge pump. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 47(2), 264–268. 4. Palumbo, G., & Pappalardo, D. (2006). Charge pump circuits with only capacitive loads: Optimized design. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(2), 128– 132. 5. DiCataldo, G., & Palumbo, G. (1996). Optimized design of an n-th order dickson voltage multiplier. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(5), 414–418. 6. Ballo, A., Grasso, A. D., Palumbo, G., & Tanzawa, T. (2022). A charge loss aware advanced model of Dickson voltage multipliers. IEEE Access, 10, 118082–118092. 7. D’Arrigo, S., et al. (1989). A 5 V-only 256 kbit CMOS flash EEPROM. In IEEE International Solid-State Circuits Conference (pp. 132–133). 8. Nakagome, Y., et al. (1991). An experimental 1.5-V 64-Mb DRAM. IEEE Journal of SolidState Circuits, 26(4), 465–472. 9. Gariboldi, R., & Pulvirenti, F. (1994). A monolithic quad line driver for industrial applications. IEEE Journal of Solid-State Circuits, 29(8), 957–962. 10. Tanzawa, T., Tanaka, T. (1997). A dynamic analysis of the Dickson charge pump circuit. IEEE Journal of Solid-State Circuits, 32(8), 1231–1240. 11. Tanzawa, T. (2011). A switch-resistance-aware Dickson charge pump model for optimizing clock frequency. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(6), 336– 340. 12. Seeman, M. D., & Sanders, S. R. (2008). Analysis and optimization of switched-capacitor DC–DC converters. IEEE Transactions on Power Electronics, 23(2), 841–851. 13. Tanzawa, T., & Atsumi, S. (1999). Optimization of word-line booster circuits for low-voltage flash memories IEEE Journal of Solid-State Circuits, 34(8), 1091–1098. 14. Tanzawa, T., Tanaka, T., Takeuchi, K., & Nakamura, H. (2002). Circuit techniques for a 1.8-Vonly NAND flash memory. IEEE Journal of Solid-State Circuits, 37(1), 84–89. 15. Di Cataldo, G., & Palumbo, G. (1993). Double and triple charge pump for power IC: Ideal dynamical models to an optimized design. IEE Proceedings G (Circuits, Devices and Systems), 140(2), 33–37.

Chapter 2

Variants and Evolutions of the Dickson CP Topology

2.1 The Traditional Dickson CP 2.1.1 Dickson CP with Diodes The first integrated realization of a CP was the Dickson’s one in 1976 [1]. Like previous CPs realized in discrete implementations, such as the Crockcroft and Walton topology proposed in 1932 [2], the original Dickson CP makes use of diodes instead of switches, as shown in Fig. 2.1. A similar CP topology to the original Dickson’s one, but implemented with MOSFET diodes, as shown in Fig. 2.2, was also implemented on silicon [3]. The main advantage provided by diodes is the absence of the switch control signals. The main drawback is the reduction of the CP output voltage. Indeed, when a diode is forward biased (i.e., when the corresponding switch must be closed), it causes a voltage loss equal to the diode threshold voltage, .Vγ (regardless the diode is bipolar or MOS), which reduces the output voltage of a factor .(N + 1) Vγ . This reduction is particularly critical under low-power supplies, since relationship (1.4) becomes now   IL T VOU T ,Steady−State = (N + 1) VI N − Vγ − N C

.

(2.1)

and determines also a loss in the CP efficiency. For this reason, the Dickson CP is seldom adopted in integrated applications.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 A. Ballo et al., High-Performance Integrated Charge Pumps, https://doi.org/10.1007/978-3-031-43597-3_2

35

36

2 Variants and Evolutions of the Dickson CP Topology

Fig. 2.1 Original Dickson CP

Fig. 2.2 Dickson CP with MOSFET diodes

Fig. 2.3 Generic N-stage Dickson CP

2.1.2 The Charge Transfer Switch For the reasons discussed in the previous subsection, the typical Dickson CP implementation is based on the scheme where switches are used instead of diodes, such as the circuit schemes in the previous chapter. More specifically, considering an N-stage Dickson CP as in Fig. 2.3, we can consider each i-th stage made up of a pumping capacitor, C, and a charge transfer a switch (CTS). Of course, an adjoined CTS is needed to provide the output charge at the load. The acronym CTS was first introduced by Wu and Chang [4] to emphasize the main goal of this block, which is to irreversibly transfer charge from the input to the output. The circuit topology of the CTS constitutes the main diversification factor among the various proposed Dickson CP topologies and, hence, is an important key aspect to consider. In general, the CTS is constituted by one or two main transistors, acting as a switch, and whose gates are properly driven by other CP nodes or auxiliary circuits inside the CTS block. Indeed, even if the implementation of a switch is conceptually simple, in a CP the voltage at the switch terminals is higher than the power supply.

2.1 The Traditional Dickson CP

37

Fig. 2.4 N -stage CP patented by Dickson in 1980 [5]

Fig. 2.5 N-stage CP whit PMOS diode

As a consequence, the MOS transistors used to implement the CP switches have to be switched ON by applying suitable gate voltages higher than their source terminal voltages. For example, an evolution of the traditional Dickson topology was proposed and patented by Dickson himself in 1980 [5] (Fig. 2.4) and discussed more in detail in the next chapter section. A more performing variant of the Dickson CP patented in 1980 can be obtained by simply replacing the single NMOS transistor with a PMOS transistor whose bulk is connected to the source, as shown in Fig. 2.5. Such solution allows to equalize the threshold voltages along the CP, otherwise made different by the various source to bulk voltages. Moreover, its value is increased during turn-off, since source-body junction is reverse biased, thus reducing the reverse current. This implementation is effective when the available technology is a standard double well and the bulk of each NMOS transistor cannot be independently controlled. The basic idea exploited in the topologies depicted in Figs. 2.4 and 2.5 can be adopted to reduce the adverse effect of threshold voltage of the main CTS transistor by adopting auxiliary circuits to drive the two control terminals of the transistor as switch, i.e., the gate or the body terminal. Indeed, gate biasing and body (or bulk) biasing techniques, as shown in Figs. 2.6 and 2.7, respectively, can be applied to better manage the main CTS transistor during on and off phases and to improve its electrical properties, such as threshold voltage and on/off resistance. These techniques are further analyzed in the following paragraphs.

38

2 Variants and Evolutions of the Dickson CP Topology

Fig. 2.6 Dickson CP with CTS exploiting gate biasing

Fig. 2.7 Dickson CP with CTS exploiting body biasing

2.2 CTS Gate Biasing Techniques CTS gate biasing techniques can be classified into: • One-transistor CTS • CTS with an auxiliary circuit The one-transistor CTS solutions have the gate of the transistors connected to specific nodes of the CP. On the other hand, in the CTS with an auxiliary circuit, the CTS is made up by the main transistor, which works as a switch, plus a dedicated control circuit that provides a proper signal to the gate of the main transistor.

2.2.1 One-Transistor CTS A one-transistor CTS topology is again represented by the topology patented by Dickson in 1980 [5] and reported in Fig. 2.4. As shown in Fig. 2.4, the CTS switch is made up by NMOS transistor only, whose bulk is connected to ground, while the gate is connected to a forward node in order to increase the overdrive voltage and decrease the loss due to the transistor threshold voltage, thus allowing a reduction of the minimum supply voltage.

2.2 CTS Gate Biasing Techniques

39

Despite surely interesting, the main drawback of the topology in Fig. 2.4 is due to the not totally turned-off CTS, causing a non-negligible reverse current that flows from the output to the input, resulting in a worst power conversion efficiency. Another example of one-transistor CTS has been recently proposed by authors [6], and since for its feature it is particularly suited for low-voltage application, it will be treated in detail in Sect. 5.2.

2.2.2 CTS with an Auxiliary Circuit The first CP having a CTS with an auxiliary circuit was applied on memories and proposed by D’Arrigo et al. [7]. After, a complementary version able to generate both negative and positive voltages for erasing and program operation of EEPROM was presented by Umezawa et al. [8]. These kinds of topologies, named Bootstrap CPs, were attractive and widely adopted. The simplified schematic of a bootstrap CP and the required four-phase non-overlapped clock signals are shown in Figs. 2.8 and 2.9, respectively. Considering the CP in Fig. 2.8, the required high gate voltages of the main CTS transistor are obtained for each stage thanks to a bootstrap circuit, which is realized by adding (for each stage) another capacitor and MOS transistor, which represent the (small) auxiliary circuit. In the bootstrap CP during the boosting phase, the gate voltages of the main CTS transistors are maintained constant and independent from other CP voltages. Consequently, the main transistor works in triode region as long as its gate-to-source voltage is greater than the threshold voltage. Despite the circuit in Fig. 2.8 allows reducing the voltage drop across the switch, its drawback is that during steady state (i.e., when the pumping capacitors are charged near their maximum voltage) the transistors work in the subthreshold region

Fig. 2.8 Bootstrap CP [7]

40

2 Variants and Evolutions of the Dickson CP Topology

Fig. 2.9 Clock (.Fi ) and control (.FBi ) signals of the Bootstrap CP in Fig. 2.8

Fig. 2.10 Modified clock (.Fi ) and control (.FBi ) signals of the Bootstrap CP in Fig. 2.8

where their conduction properties abruptly deteriorate. To overcome this drawback, the use of a boosted clock signal as in Fig. 2.10 was introduced in [9]. To better understand the working principle of a Bootstrap CP, let us analyze the generic stage (with an auxiliary capacitor) depicted in Fig. 2.11. During the half period in which there is no charge transfer (i.e., .MP ASS is open), signal .FB1 is low and the added transistor .MB is closed, since the voltage at its gate is higher of a threshold voltage (.VGS,MB =2.VI N ) than the other two nodes. The capacitor .CB is then charged up to a voltage equal to .Vj −1 = (j − 1) VI N −(j − 2) V , see (1.37). During the subsequent half period, the clock signals .F1 and .F2 change their value, and, after another small time slot (see Fig. 2.10), .F B1 goes high to 2.VI N . Now the transistor MB is open, while the pass transistor .MP ASS is closed. Indeed,

2.2 CTS Gate Biasing Techniques

41

Fig. 2.11 Generic CTS of a Bootstrap CP (with an auxiliary capacitor)

the gate voltage of .MP ASS is equal to .(j + 1) VI N −(j − 2) V , which is higher than the voltage at its source (i.e., the node j ) by .VI N + 2V . Besides, during this half period, the gate–source of .MP ASS is sufficiently high to keep this transistor closed (the gate–source voltage is always not lower than .VI N + V ). It is apparent that the ingenious behavior of this topology is obtained at the price of a more complex clocking and control section (requiring four phases and 2.VI N amplitude). More recently, Fuketa et al. [10] introduced a modified bootstrap CP in which phases .F1a and .F1b are switched between 0 and the output voltage to further increase performance. Note, however, that start-up phase can be slowed down or completely fail in the topologies that reuse CP node voltages, especially the output one. This is caused by the initial voltage levels of the nodes, which could be too low in the start-up phase. To overcome this drawback, auxiliary circuits are required to start and support the CP charge transient (kick starters). The bootstrap strategy can be also adopted to better turn off the main transistor, rather than to improve its conduction features. This is the case of the topology introduced by Ansari et al. [11], shown in Fig. 2.12, which was improved by Mondal and Paily [12, 13] by the adoption of the scheme depicted in Fig. 2.13. These topologies were presented in the literature as single clock CPs, since the counterphase clock signal is locally generated for each pair of stages. Another topology that can be considered a dynamic version of the basic topology in Fig. 2.14, but having a CTS with auxiliary circuit, was introduced by Wu and Chang in [4]. A simplified schematic of this topology is depicted in Fig. 2.14. The topology of the CTS commutes from diode-connection, during the off state, to the classical static connection during the on state. The drawback of this topology, like for the one in Fig. 2.4, is due to the last switch. Indeed, it strongly limits the CP’s performance because it cannot be bootstrapped, unless extra circuitry is implemented [14].

42

2 Variants and Evolutions of the Dickson CP Topology

Fig. 2.12 The Bootstrap CP with single clock signal [11]

Fig. 2.13 The improved Bootstrap CP with single clock signal [12, 13]

Fig. 2.14 CP proposed by Wu and Chang in [4]

2.3 Double CPs Double CPs were conceived to reduce the output ripple by using the same total CP capacitance, .CT OT . As depicted in Fig. 2.15, each half part, which has a total capacitance .CT OT /2, feeds the load in a different half period. Hence, the charge .Q pumped at the output is divided into two equal parts, each for half period. The

2.3 Double CPs

43

Fig. 2.15 Simplified schematic of a double CP

Fig. 2.16 Double bootstrap CP

output voltage is the same as the simple CP, but the ripple is now Vr =

.

IL · T 1 Q = 2 CL 2CL

(2.2)

Indeed, for this topology, the time interval between two charge transfers into .CL when the output voltage is reduced due to the current load .IL is now only .T /2. In principle, any kind of Dickson CP can be transformed in a Double Dickson CP, such as the Double Bootstrap CP shown in Fig. 2.16.

44

2 Variants and Evolutions of the Dickson CP Topology

2.3.1 The Voltage Doubler and the Latched CP A very interesting and efficient CP, which is inherently double since exploits the complementary structure of a double topology, is the Latched CP (also named dualbranch cross-coupled CP). The simplified schematic of the Latched CP, originally proposed in [15–17], is shown in Fig. 2.17. It includes a latch in each stage and gained a high level of popularity since it is suitable for very high clock frequencies and because, unlike the Bootstrap CP, needs only a two-phase clock. Before treating the latched CPs, it is useful to introduce a specific 2-stage CP, shown in Fig. 2.18, often employed as voltage shifter or voltage doubler and used as a feedback CP for DRAM word-line drivers [15]. In particular, the topology in Fig. 2.18a is commonly adopted to generate differential doubled output voltage with zero drop across its transistors, while if it is coupled to dual series-connected PMOS switches, as the topology in Fig. 2.18b, a single output is obtained.

Fig. 2.17 Latched CP

Fig. 2.18 Nakagome’s cell block scheme (a) without and (b) with PMOS switches

2.3 Double CPs

45

Fig. 2.19 Cross-coupled CP with bulk switching [22]

The topology in Fig. 2.18b (more than 10 years later successively re-introduced in [18]) represents the basic cell of the cross-coupled CP independently proposed by Gariboldi and Pulvirenti, which was used in their quad monolithic line driver [16, 17]. As the dual-branch structure, the latched CP configuration allows to halve the ripple, enhancing the charge transfer, and, moreover, it can take profit of gate and body biasing techniques. Unfortunately, the employment of the series-connected PMOS and NMOS should entail some limitations on the conduction level given by series of their channel resistances, since an inevitably increase in the CTS equivalent on-resistance arises. In the literature, many variants have been proposed for the basic topology of the Latched CP, such as the solution proposed by Luo et al. [19], where PMOS transistors are bootstrapped to improve power efficiency (up to 69%, with an output current of 3.5 mA and a voltage of 10.5 V). In the same year, Tsuji et al. [20] suggested a low-leakage driver for the main complementary MOS of a latched CP to improve current drivability with a low input voltage (as low as 100 mV). Another high-performance latched CP was proposed by Peng et al. in [21], where bodies and gates are dynamically biased to lower the minimum supply voltage (at value as low as 320 mV). However, its weakness stays in the need for extra stages and in the complexity of the general circuit. More effective solutions are given by Favrat et al. [22], which used two auxiliary transistors to apply the principle of bulk switching to improve the current drive of the PMOS and the power efficiency of the Nakagome’s cell, as depicted in Fig. 2.19. Finally, a further improved cross-coupled CP was introduced by Chen et al. [23], who for the first time applied FBB on a three-stage CP, and by Kim et al. [24],

46

2 Variants and Evolutions of the Dickson CP Topology

who applied the dynamic body biasing on both transistors, thus allowing a very low start-up voltage as low as 150 mV and a high efficiency of 72.5%.

2.4 Adiabatic CPs In order to lower power consumption, adiabatic principle has been applied to CPs. The strategy is focused on the slow charging condition in order to reduce the energy that is not transferred to the load. In particular, the adiabatic strategy, which was originally exploited in a digital domain [25, 26], is applied following two strategies. In the first one, two-time step charge sharing and a particular clock scheme are used [27]. This strategy is adopted by Ulaganathan et al. [28] on a linear CP for energy harvesting applications. The three-stage CP proposed in [28] is depicted in Fig. 2.20, where two-step waveform applied on node .VG allows to transfer the charge in two times, characterized by two different voltage levels. Therefore, the total transferred energy .ET is given by   2 2  Vf Vf 1 1 C − Vi + C Vf − − Vi .ET = 2 2 2 2 2  2 Vf 1  =C − Vi < C Vf − Vi 2 2

(2.3)

where .Vi and .Vf are the initial and final capacitor voltage levels, respectively. The second strategy exploits the recycling of charges collected and the realization of auxiliary ground and .VDD nodes, as shown in Fig. 2.21, where the working

Fig. 2.20 Adiabatic CPs, two-time step charge sharing [20]

2.5 Charge Pumps with an Adaptive Number of Stages

47

Fig. 2.21 Adiabatic CPs, charge recycling block scheme [28]

principle used by Keung et al. in [29] is reported. During a first time slot, thanks to the virtual ground, the charges consumed by a source logic block are collected in the capacitor. Meanwhile, the supply voltage feeds the target logic block. Then, when the auxiliary ground node is high, the circuits are switched and the collected charge is pumped up by the CP to the right-side capacitor in order to generate the auxiliary .VDD , which supplies the target logic block. This approach allows about 10% of power consumption reduction, with only 1–2% of area penalty.

2.5 Charge Pumps with an Adaptive Number of Stages Adaptive CPs, also known as reconfigurable CPs, are designed to be able to change their number of stages [18, 19] or change their voltage conversion ratio [30–34] in order to satisfy to the varying load condition (for example, the CP current driving capability). They are useful, for example, in IC applications where more than one CP with a different number of stages is required at different times. Thus, when the CPs are used in non-overlapping time periods, it can be useful to implement only one CP that dynamically adapts its number of stages, as the two-stage to a four-stage CP topology in [30]. Adaptive CPs are also used to improve very low-voltage start-up operation [23], such as the CPs devoted to microscale energy harvesting [36], and to the energy reduction in the sleep to active transition [37]. In general, reconfigurable CPs can be applied for different kinds of scenarios. They can allow a constant output voltage

48

2 Variants and Evolutions of the Dickson CP Topology

Fig. 2.22 Block scheme of the adaptive CP in [31]

for a wide dynamic input voltage range or permit a higher power conversion factor for an extended input range. As an example, the solution in [38] where for defined input and output voltages the CP can work into two different states, one at low power consumption but low speed, and the other one with higher speed but higher power consumption. For all the reasons discussed above, the interest on the reconfigurable CPs is highly increasing [39–44], especially in the last years, and an interesting review on this topic can be found in [45]. An example of an adaptive CP with a number of stages dynamically set by rearranging the whole set of capacitors, so that the required output voltage could be reached by maximizing the CP’s efficiency, is shown in [31]. In this topology for a defined number of stages, the whole CP capacitance (i.e., silicon area used by the CP) always remains equal. A version of the topology proposed in [31], which adapts its number of stages from 1 to 3, is shown in Fig. 2.22, where, without loss of generality, the CTS is with diodes with the phase arrangement for the three different cases summarized in Table 2.1 (of course in a practical implementation any CTS can be used instead of diodes, as in [31] where switches with bootstrap are used).

2.6 CP Topologies: Performance Comparison

49

Table 2.1 Clock phases for the CP in Fig. 2.22 FX FN

One-stage CP

Two-stage CP

Three-stage CP

.F1 , .F2 , .F3 , .F4 , .F5 , .F6

.F1 , .F3 , .F5

.F1 , .F3 , .F4 , .F6

–

.F2 , .F4 , .F6

.F2 , .F5

Referring to Fig. 2.22, it is worth noting that, in order to provide adaptability, each capacitor is connected through a diode both to the power supply (.DAi and .DDi ) and to the output node (.DCi and .DEi ). Moreover, there are diodes that connect couple of capacitors (.DBi and .DF i ). To understand the behavior of the CP in Fig. 2.22, let us consider each single case starting from the single-stage one. In this configuration, all the capacitors have to be connected in parallel to form a single capacitor. In other words, this means that all the capacitors have to be driven by the same phase signal and all the diodes connecting couple of capacitors (.DBi and .DF i ) are always reverse biased (see Table 2.1). In the case in which a two-stage topology is needed, the CP in Fig. 2.22 works like three parallel two-stage topologies. Hence, it can be simply inferred that the set of phases .F1 , .F3 , and .F5 must be complementary to the other set .F2 , .F4 , and .F6 (see Table 2.1). Under this condition, the diodes .DF i are always reverse biased. Moreover, since at steady state .V2i > VDD and .V2i + 1 < VOut , the diodes .DDi and .DEi are also reverse biased. Finally, a three-stage CP can be obtained by configuring the CP like two parallel three-stage CPs. This condition is obtained by driving the input phases .F1 , .F3 , .F4 , and .F6 together, and the input phases .F2 and .F5 by the complementary phase (see Table 2.1). Thus, the two three-stage CPs have the two main paths constituted by internal nodes 1, 2, and 4 with the set of phases .F1 , .F2 , and .F4 , and internal nodes 3, 5, and 6 with the set of phases .F3 , .F5 , and .F6 . It can be simply verified that at the steady state the diodes .DDi , .DEi , .DC1 , .DB2 , and .DA3 are reverse biased.

2.6 CP Topologies: Performance Comparison The adoption of a specific topology among those reported and briefly described in the previous sections is not so simple and typically depends upon the specific application, the adopted technology, and design constraints. In general, in low-supply-voltage applications, such as energy scavenging from TEGs, gate and body control schemes could represent a good choice since they allow for lowering the minimum input voltage. In applications requiring low power consumption, energy recycling or active/idle mode transition offered by adiabatic CPs or adaptive CPs could represent an efficient solution, but at the expense of higher settling time and area overhead. Analysis of the reported experimental measurements of the different topologies represents an important step in the

50

2 Variants and Evolutions of the Dickson CP Topology

assessment of the state of the art. Indeed, it may reveal additional and sometimes unexpected benefits of a particular topology. At this purpose, in [46], authors collected in a spreadsheet performance metrics of different previously reported solutions and made it available online to allow independent exploration. Moreover, for the sake of conciseness, a selection of 11 solutions, out of 27 in [46], targeted for energy harvesting applications, is reported in Table 2.2. In particular, they refer to the topologies in [10, 13, 14, 21, 24, 47–50] and [27]. Except for the CP in [13], where large pumping capacitors were used to drive high current loads, in energy harvesting applications output power levels of CPs fall down in the range of tens of microwatts. Defining the power efficiency as η=

.

POU T PI N−CP + PAU X

(2.4)

where .PI N −CP is the input power of the CP only and .PAU X is the power consumption of the auxiliary circuits, by inspection of Table 2.2, .η ranges from 10% to 79% (this latter value achieved by Wang et al. [49]) and typically most of the examined topologies (bootstrap or cross-coupled) exhibit a .η in the range 30%– 60%, despite that they should be inherently highly efficient. These low .η values are due to the auxiliary circuits (in particular the clock generators and drivers) that can heavily affect the overall power consumption since .PAU X could be comparable to .PI N −CP . From the above comments, it becomes apparent that particular attention must be given to the design of auxiliary circuits, in particular the clock generator and drivers, whose power consumption may seriously degrade the power conversion efficiency of the overall CP. Analysis of data reported in Table 2.1 reveals also that the lowest minimum supply voltage is achieved by the cross-coupled topology in [48], thanks to the adoption of an auxiliary CP for start-up. Unexpectedly, solutions adopting gate and body control schemes, as in [10, 13, 21, 24] (as in [51–53], see [46]), exhibit higher minimum supply voltages, thus showing that the comparison among the different designs is not straightforward because of the different functionality and constraints required by the various applications. A better comparison can be carried out by considering more than one parameter at the same time. Such a comparison is reported in Fig. 2.23 where, for all the solutions in [46], V CE and .η are plotted versus the output power density, being V CE defined as V CE =

.

VOU T VOU T = VOU T ,id (N + 1) VI N

(2.5)

where .VOU T and .VOU T ,id are the actual and ideal CP output voltages, respectively. By inspection of Fig. 2.23a, it is apparent that the solution reported in [48] achieves the lowest value of minimum supply voltage (75 mV), but with one of the lowest values of V CE (50%). Consequently, its overall performance appears lower than

30 1.74 1.5 80 38.8 0.032

46.08

10000.b 12 15 50 58 0.6

Total Cap. (pF )

Load Cap. (pF ) Load current (.μA) Max power (.μW ) Peak V CE (.%) Peak .η (.%) Area (.mm2 ) 100 0.76 6.6 76 33 1.32

1001

[10] BS 10 CKB 2x 65 100 10 400 10 4.7 96 66 0.17

160

[14] Dickson 4 DGB 65 550 1.8 50.7 .− .− 89 .− 0.14

288

[21] C-C 6 BGB 180 320 0.45

21 10.5 86 34.c 0.066.b

36000.b 10000.b

[24] C-C 3 DBB 130 150 0.25 500 5 7 65 58 0.42

150

[47] BS 3 .− 130 270 0.8 800 30 75 93 78.6.c 0.98

310

[49] BS 5 S-M 130 500 2.5

Acronyms in the Table: C-C Cross-coupled, BS Bootstrap, CkB Clock Booster, DGB Dynamic Gate Biasing, BGB Backward Gate Biasing, DBB Dynamic Body Biasing, S-M Split–Merge, LVT Low-Voltage Threshold Notes in the Table: .a simulation; .b off-chip capacitors; .c external clock generator

22.5

[48] C-C .6 × 24 Start-up 130 70 0.04

Ref. Topology No. of Stages Aux. Circuit Technology (nm) Min. Supply (mV ) Frequency (MH z)

[50] C-C 3 CKB 3x 65 150 15.2

Table 2.2 Comparison of different charge pumps

4000.b 620 620 93 76 0.48

500

[13] BS 1 .− 180 390 23 100 0.1 0.061 70 59 0.15

96

0.035 80 62 0.1

224

[27].a Adiabatic 3 7 LVT diodes 130 125 0.36

3.9 3 58 38.8 0.78

.−

286

[35] Adaptive 10 .− 65 120 1

2.6 CP Topologies: Performance Comparison 51

52

2 Variants and Evolutions of the Dickson CP Topology

Fig. 2.23 Performance comparison, (a) V CE versus minimum input voltage and (b) .η versus output power density

[50] and [24] (also lower than [54], see [46]) that, while exhibiting higher values of minimum supply voltage (100 mV, 150 mV, and 150 mV, respectively), show much higher values of V CE (91%, 86%, and 80%, respectively). Additional information can be gathered from Fig. 2.23b. Indeed, considering the example analyzed above, it becomes apparent that [48] present better performance for the higher value of .η and the output power density, while occupying much more area than [50]. Moreover, Fig. 2.23b shows that, from the power efficiency and power density point of view, the best performance is achieved by the solutions in [13, 14], and [49] (note, however, that [49] adopt an external clock generator and,

2.7 Regulation Techniques

53

consequently, the evaluation of the .η does not take into account its additional power consumption).

2.7 Regulation Techniques In order to set a stable output voltage with constraints imposed by the load, the voltage at the output of the CP has to be regulated. Of course, the need of regulation depends on the specific application and the supplied circuit type (i.e., purely capacitive, purely resistive, or mixed). As examples, in nonvolatile memory applications, such as NOR Flash or the more recent 3D NAND memories [55, 56], where CPs are used to drive a single or multiple word lines (WLs), a purely capacitive load can be assumed, and the main design specs are settling time and voltage conversion efficiency (V CE). On the other hand, in energy-autonomous wireless nodes, the equipped sockets, such as sensors, actuators, communication, and data-storage sub-systems, consume both static and dynamic power. In this context, the load is both capacitive and resistive, and an efficient managing of the gathered energy assumes the primary importance (i.e., power conversion is the main target) [57, 58]. As a final design context example, when the CP is used in the cold start of energy harvesting circuits based on thermoelectric generators, the load is both capacitive and resistive, but the main specifications are V CE and settling time [59–62]. For a conventional regulated N -stage CP, the output voltage can be adjusted from .VI N to (N + 1) .VI N by changing one or more CP parameters according to the reference voltage, .VT ARG . Based on the parameter on which they act, regulation schemes could be typically classified into two schemes, namely [63]: • Output resistance modulation • Clock amplitude modulation More specifically, in the output resistance modulation schemes, the clock frequency or the duty cycle is properly changed to adapt the CP output resistance to the load, thus pursuing to achieve the targeted output power or to maintain the maximum power transfer. In the clock amplitude modulation schemes, it is adjusted the clock amplitude, .VCK (different in type of regulation from the input voltage, .VI N ) in order to reduce switching power losses or to speed up the output transient response. Each of these techniques is briefly discussed in the following subsections. From one point of view, we could also consider CP with adaptive stage another way to regulate the charge pump, but this case was treated in a previous section.

54

2 Variants and Evolutions of the Dickson CP Topology

2.7.1 Output Resistance Modulation Schemes The output resistance modulation is a widely adopted regulation scheme to set the output voltage under different output load conditions. This kind of feedback is commonly used in various application fields, and, as shown in Fig. 2.24, it is made up of the N-stage CP, a voltage divider, a voltage comparator, and, depending on the controlled parameter (i.e., clock frequency or duty cycle), a voltage controlled oscillator (VCO) [64–67] or a pulse width modulator (PWM) [68]. Focusing on the frequency-based modulation, the clock frequency acts on the CP output impedance to regulate the output voltage and to tune it according to the reference voltage. However, as discussed in [63], the output impedance value can be changed only if the CP works within SSL. This condition limits the maximum operative frequency and, therefore, the regulation range. Anyway, the regulation range can be increased by proper pumping capacitance and CP transistors re-sizing. The remaining limits are given by the minimum and maximum VCO frequencies, .fmin and .fMAX , respectively, which define the absolute limits of the regulation range. Since the regulation acts at the steady state, a proportional control of the CP output resistance can be assumed, and we can write .

Neff = RSSL,MAX [1 + AV CO (kV D VOU T − VT ARG )] fC

(2.6)

where .RSSL,MAX = Neff /(fmin C) is the maximum CP output resistance, .AV CO , expressed in .V −1 ), is the gain of the cascade between OP and VCO, and .kV D is the voltage partition coefficient of the voltage divider. Thus, within the control range, the closed-loop function for the output voltage is given by  VOU T =

.

   Neff + 1 VI N − RSSL,MAX IL + AV CO RSSL,MAX IL VT ARG   1 + kV D AV CO RSSL,MAX IL (2.7)

Fig. 2.24 Output resistance modulation scheme

2.7 Regulation Techniques

55

Fig. 2.25 Closed-loop response: (a) output voltage and clock frequency for .fmin and .fMAX set to 100 and 10 MHz, respectively, versus the output current and (b) the input voltage (.IL = 10 .μA)

and, assuming .AV CO kV D >> 1, the output voltage in (2.7) approaches the value VT ARGET /kV D . Note that the variation of the clock frequency is proportional to the difference between the scaled CP output voltage and the reference voltage. Furthermore, the frequency range can be set from .fmin to .fMAX . As an example, the closed-loop output voltage and the controlled clock frequency of the 8-stage CP regulated with the output resistance modulation scheme as response to an output current and an input voltage variation are shown in Fig. 2.25. It is apparent that the output voltage follows the target one with a restrained error

.

56

2 Variants and Evolutions of the Dickson CP Topology

theoretically expressed by

ε = kV D

.

1−



  IN R IL − SSL,MAX Neff + 1 VTVARG VT ARG   1 + kV D AV CO RSSL,MAX IL

(2.8)

With the aim of comparing the regulation schemes, two performance parameters commonly adopted for voltage regulators have been considered, namely line and load regulation. In particular, line regulation is defined as the ability of the output voltage to maintain its specified output voltage over changes in the input voltage and is expressed by LineR =

.

Neff + 1 δVOU T   = δVI N 1 + kV D AV CO RSSL,MAX IL

(2.9)

The load regulation is referred to the output current variation rather than the input voltage variation, and it is defined as LoadR =

.

   AV CO kV D Neff + 1 VI N − VT ARG − 1 δVOU T = RSSL,MAX    2 δIL 1 + kV D AV CO RSSL,MAX IL (2.10)

Assuming a high gain .AV CO = 1000 .V−1 and a partition coefficient .kV D = 0.1 , with an output current of .10 μA. The error, line, and load regulations of relationships (2.8)–(2.10) are equal to 0.14%, 0.011, and 185.8 ., respectively. Differently from the frequency-based type, the duty cycle-based modulation schemes act on the CP output impedance when it works in FSL, where the output impedance value changes as a function of the duty cycle (i.e., .ROU T ,F SL = .(N eff + 1) R/δ). This limits the minimum operative frequency, which can be extended by a proper stage components re-sizing. Other limits are due by the minimum and the maximum duty cycle of the pulse width modulator, .δmin > 0 and .δMAX ≤ 0.5, respectively. Like the frequency-based scheme, a proportional control of the CP output resistance can be assumed, and we can write 

 Neff + 1 R = RF SL,MAX [1 + AP W M (kV D VI N − VT ARG )] . (2.11) δ   where .RF SL,MAX = Neff + 1 R/δmin is the maximum output resistance offered by the CP in FSL, .AP W M , expressed in (.V −1 ), is the gain of the cascade between OP and PWM, .kV D is the voltage partition of the voltage divider, and .δmin is the minimum duty cycle. Within the control range, the closed-loop function for the output voltage results

2.7 Regulation Techniques

57

Fig. 2.26 Closed-loop response: output voltage and duty cycle for .δmin and .δMAX set to 0.01 and 0.49, respectively, versus: (a) output current; (b) input voltage

VOU T

.

    Neff + 1 VI N − RF SL,MAX IL + AP W L RF SL,MAX IL VT ARG   = 1 + kV D AP W L RF SL,MAX IL (2.12)

which has a similar expression of (2.7). And, of course, assuming .AP W M kV D >> 1, the output voltage in (2.12) approaches .VT ARGET /kV D . The closed-loop output voltage of the whole system, assuming a 4-stage CP, has the response to an output load and an input voltage variation shown in Fig. 2.26.

58

2 Variants and Evolutions of the Dickson CP Topology

As expected, assuming a high gain .AP W M = 1000 V−1 , the output voltage follows the target one with a restrained error even lower than 1%, while line and load regulations, valued as given in (2.9) and (2.10), respectively, are 0.1 and 1.05 ..

2.7.2 Clock Amplitude Modulation Schemes Although rarely adopted, regulation schemes based on clock amplitude modulation offer a good compromise between circuit complexity and overall performances. In these schemes, the amplitude of the clock signals is adjusted to target a specific output voltage. This kind of feedback is made up at least of the N-stage CP, a voltage divider, a linear comparator, and an auxiliary DC–DC converter, which, depending on the targeted application, can reduce or boost the input voltage .VI N to feed the buffers that provide the clock signals (Fig. 2.27). The clock amplitude affects the maximum CP output voltage (i.e., .VOU T ,MAX = Neff VCK + VI N ), and, specifically, it tends to tune the CP output voltage according to the target voltage value. Therefore, the control is apparently independent from the CP working zone, SSL or FSL. However, it is worth nothing that the CP output resistance limits the CP output current capability; therefore, the regulation range could be limited mainly when CP works in the deep-SSL zone. Moreover, input current caused by switching losses can be decreased, making .VCK < VI N [69]; vice versa, a boosting of the clock amplitude with respect to the input voltage (.VCK > VI N ) can lead to a settling time reduction [70]. Since the two action affects the CP performance in an opposite way, for these control schemes’ application, field can be divided into low-power and high-speed applications, for the earlier and the latter approaches, respectively. Assuming a linear modulation of the controlled parameter within the control range, we can write

Fig. 2.27 Clock amplitude modulation scheme

2.7 Regulation Techniques

59

Fig. 2.28 Closed-loop response: (a) output voltage and (b) clock amplitude versus the output current and the input voltage for .0 ≤ VCK ≤ VI N

VCK = AV M VI N (VT ARG − kV D VOU T )

.

(2.13)

where .AV M , expressed in (.V −1 ), is the gain of the cascade between comparator and auxiliary DC–DC converter (here re-called voltage modulator), and .kV D is the voltage partition coefficient of the voltage divider, previously defined. Then, closedloop function for the output voltage is simply expressed by

60

2 Variants and Evolutions of the Dickson CP Topology

Fig. 2.29 Closed-loop response: (a) output voltage and (b) clock amplitude versus the output current and the input voltage for .VI N ≤ VCK ≤ 2VI N

VOU T

.

  Neff AV M VT ARG + 1 VI N − RCP IL   = 1 + kV D Neff AV M VI N

(2.14)

Of course, assuming .AV M kV D >> 1, we see that the output voltage in (2.14) approaches that of .VT ARGET /kV D . The closed-loop output voltage of the system versus the output current and input voltage variations is depicted in Fig. 2.28a and b, for the reduced mode, .0 ≤ VCK ≤ VI N , and Fig. 2.29a and b for the boosted mode, .VI N ≤ VCK ≤ 2VI N . As expected,

References

61

for a high gain .AV M kV D = 100, the output voltage approaches the target one with an average error equal to 0.1%. It is worth noting that line and load regulations have different expressions with respect to the output resistance modulation schemes, and, in particular results LineR =

.

Neff AV M (VT ARGET + kV D RCP IL ) + 1 δVOU T =  2 δIL 1 + Neff AV M kV D VI N LoadR =

.

δVOU T RCP = 1 + Neff AV M kV D VI N δVI N

(2.15)

(2.16)

The numerical values for the simulated case are 0.15 and 112.2 ., respectively. Note also that as compared to the output resistance modulation scheme the number of stages further increases the open-loop gain of the feedback, improving line and load regulations.

References 1. Dickson, J. F. (1976). On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique. IEEE Journal of Solid-State Circuits, 11(3), 374–378. https://doi.org/10.1109/JSSC.1976.1050739. 2. Crockcroft, J., & Walton, E. (1932). Production of High Velocity Positive Ions. Proceedings of the Royal Society A, 136, 619–630. 3. Witters, J., Groeseneken, G., & Maes, H. (1989). Analysis and modeling of on-chip highvoltage generator circuits for use in EEPROM Circuits. IEEE Journal of Solid-State Circuits, 24(5), 1372–1380. 4. Wu, J.-T., & Chang, K.-L. (1998). MOS charge pumps for low-voltage operation. IEEE Journal of Solid-State Circuits, 33(4), 592–597. 5. Dickson, J. F. (1980). Voltage multiplier employing clock gated transistor chain. US Patent US4 214 174A. https://patents.google.com/patent/US4214174A/en16 6. Ballo, A., Grasso, A. D., & Palumbo, G. (2020). A high-performance charge pump topology for very-low-voltage applications. IEEE Transactions on CAS Part II, 67(7), 1304–1308. 7. D’Arrigo, S., Imondi, G., Santin, G., Gill, M., Cleavelin, R., Spagliccia, S., Tomassetti, E., Lin, S., Nguyen, A., Shah, P., Savarese, G., & McElroy, D. (1989). A 5 V-only 256 kbit CMOS flash EEPROM. In IEEE international solid state circuits conference (1989). ISSCC. Digest of Technical Papers (pp. 132–133). 8. Umezawa, A., Atsumi, S., Kuriyama, M., Banba, H., Imamiya, K., Naruke, K., Yamada, S., Obi, E., Oshikiri, M., Suzuki, T., & Tanaka, S. (1992). A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triplewell structure. IEEE Journal of Solid-State Circuits, 27(11), 1540–1546. 9. Atsumi, S., Kuriyama, M., Umezawa, A., Banba, H., Naruke, K., Yamada, S., Ohshima, Y., Oshikiri, M., Hiura, Y., Yamane, T., & Yoshikawa, K. (1994). A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. IEEE Journal of Solid-State Circuits, 29(4), 461–469. 10. Fuketa, H., O’uchi, S., & Matsukawa, T. (2017). Fully integrated, 100-mV minimum input voltage converter with gate-boosted charge pump KickStarted by LC oscillator for energy harvesting. IEEE Transactions on Circuits and Systems II: Express Briefs, 64(4), 392–396.

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11. Ansari, M. A., Ahmad, W., & Signell, S. R. (2011). Single clock charge pump designed in 0.35 μm technology. In Proceedings of the 18th international conference mixed design of integrated circuits and systems—MIXDES 2011 (pp. 552–556). 12. Mondal, S., & Paily, R. P. (2013). A strategy to enhance the output voltage of a charge pump circuit suitable for energy harvesting. In 2013 Annual international conference on emerging research areas and 2013 international conference on microelectronics, communications and renewable energy (pp. 1–5). 13. Mondal, S., & Paily, R. (2016). An efficient on-chip switched-capacitor-based power converter for a microscale energy transducer. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(3), 254–258. 14. Mahmoud, A., Alhawari, M., Mohammad, B., Saleh, H., & Ismail, M. (2018). A charge pump based power management unit with 66% -efficiency in 65 nm CMOS. In 2018 IEEE international symposium on circuits and systems (ISCAS) (pp. 1–4). 15. Nakagome, Y., et al. (1991). An experimental 1.5-V 64-Mb DRAM. IEEE Journal of SolidState Circuits, 26(4), 465–472. https://doi.org/10.1109/4.75040. 16. Gariboldi, R., & Pulvirenti, F. (1994). A monolithic quad line driver for industrial applications. IEEE Journal of Solid-State Circuits, 29(8), 957–962. https://doi.org/10.1109/4.297702. 17. Gariboldi, R., & Pulvirenti, F. (1996). A 70 m/spl Omega/ intelligent high side switch with full diagnostics. IEEE Journal of Solid-State Circuits, 31(7), 915–923. https://doi.org/10.1109/4. 508203. 18. Ker, M.-D., Chen, S.-L., & Tsai, C.-S. (2006). Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. IEEE Journal of Solid-State Circuits, 41(5), 1100–1107. 19. Luo, Z., Ker, M., Cheng, W., & Yen, T. (2017). Regulated charge pump with new clocking scheme for smoothing the charging current in low voltage CMOS process. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(3), 528–536. 20. Tsuji, Y., Hirose, T., Ozaki, T., Asano, H., Kuroki, N., & Numa, M., (2017). A 0.1–0.6 V input range voltage boost converter with low-leakage driver for lowvoltage energy harvesting. In 2017 24th IEEE international conference on electronics, circuits and systems (ICECS) (pp. 502–505). 21. Peng, H., Tang, N., Yang, Y., & Heo, D. (2014). CMOS startup charge pump with body bias and backward control for energy harvesting step-up converters. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(6), 1618–1628. 22. Favrat, P., Deval, P., & Declercq, M. J. (1998). A high-efficiency CMOS voltage doubler. IEEE Journal of Solid-State Circuits, 33(3), 410–416. 23. Chen, P.-H., Ishida, K., Zhang, X., Okuma, Y., Ryu, Y., Takamiya, M., & Sakurai, T. (2010). 0.18-V input charge pump with forward body biasing in startup circuit using 65 nm CMOS. In IEEE custom integrated circuits conference 2010 (pp. 1–4) 24. Kim, J., Mok, P. K. T., & Kim, C. (2015). A 0.15 V input energy harvesting charge pump with dynamic body biasing and adaptive dead-time for efficiency improvement. IEEE Journal of Solid-State Circuits, 50(2), 414–425. 25. Athas, W., Svensson, L., Koller, J., Tzartzanis, N., & Ying-Chin Chou, E. (1994). Low-power digital systems based on adiabatic-switching principles. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4), 398–407. 26. Alioto, M., & Palumbo, G. (2000). Performance evaluation of adiabatic gates. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 47(9), 1297–1308. 27. Lauterbach, C., Weber, W., & Romer, D. (2000). Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps. IEEE Journal of Solid-State Circuits, 35(5), 719–723. 28. Ulaganathan, C., Blalock, B. J., Holleman, J., & Britton, C. L. (2012). An ultralow voltage self-startup charge pump for energy harvesting applications. In 2012 IEEE 55th international midwest symposium on circuits and systems (MWSCAS) (pp. 206–209) 29. Keung, K., Manne, V., & Tyagi, A. (2007). A novel charge recycling design scheme based on adiabatic charge pump. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(7), 733–745.

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47. Shih, Y., & Otis, B. P. (2011). An inductorless DC–DC converter for energy harvesting with a 1.2-μW Bandgap-Referenced output controller. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(12), 832–836. 48. Goeppert, J., & Manoli, Y. (2016). Fully integrated startup at 70 mV of boost converters for thermoelectric energy harvesting. IEEE Journal of SolidState Circuits, 51(7), 1716–1726. 49. Wang, Y., Yan, N., Min, H., & Shi, C.-R. (2017). A high-efficiency split-merge charge pump for solar energy harvesting. IEEE Transactions on Circuits and Systems II: Express Briefs, 64(5), 545–549. 50. Yi, H., Yin, J., Mak, P., & Martins, R. P. (2018). A 0.032-mm20.15-V ThreeStage charge-pump scheme using a differential bootstrapped Ring-VCO for energy-harvesting applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(2), 146–150. 51. Sawada, K., Sugawara, Y., & Masui, S. (1995). An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V. In Digest of technical papers, symposium on VLSI circuits (pp. 75–76) 52. Bloch, M., Lauterbauch, C., & Weber, W. (1998). High efficiency charge pump circuit for negative high voltage generation at 2 V supply voltage. In Proceedings of the 24th European solid-state circuits conference (pp. 100–103) 53. Zhang, X., & Lee, H. (2013). Gain-Enhanced monolithic charge pump with simultaneous dynamic gate and substrate control. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(3), 593–596. 54. Tsuji, Y., Hirose, T., Ozaki, T., Asano, H., Kuroki, N., & Numa, M. (2017). A 0.1–0.6 V input range voltage boost converter with low-leakage driver for low voltage energy harvesting. In 24th IEEE international conference on electronics, circuits and systems (ICECS) 2017 (pp. 502–505) 55. Tanzawa, T., & Atsumi, S. (1999). Optimization of word-line booster circuits for low-voltage flash memories. IEEE Journal of Solid-State Circuits, 34(8), 1091–1098. 56. Tanzawa, T., Murakoshi, T., Kamijo, T., Tanaka, T., McNeil, J. J., Duesman, K. (2016). Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20 V charge pump using tier capacitors. In Proceedings of the IEEE Asian solid-state circuits conference (ASSCC) 2016, Toyama, Japan (pp. 165–168). 57. Vraˇcar, L., Priji´c, A., Neši´c, D., Devi´c, S., & Priji´c, Z. (2016). Photovoltaic energy harvesting wireless sensor node for telemetry applications optimized for low illumination levels. Electronics, 5(2), 26. 58. Mondal, S., & Paily, R. (2016). An efficient on-chip switched-capacitor-based power converter for a Microscale Energy Transducer. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(3), 254–258. 59. Rozgi´c, D., & Markovi´c, D. (2017). A miniaturized 0.78-mW/cm2 autonomous thermoelectric energy-harvesting platform for biomedical sensors. IEEE Transactions on Biomedical Circuits and Systems, 11(4), 773–783. 60. Dezyani, M., Ghafoorifard, H., Sheikhaei, S., & Serdijn, W. A. (2018). A 60 mV input voltage, process tolerant start-up system for thermoelectric energy harvesting. IEEE Transactions on Circuits and Systems Part I: Regular Papers, 65(10), 3568–3577. 61. Doms, I., Merken, P., Van Hoof, C., & Mertens, R. P. (2009). Capacitive power management circuit for micropower thermoelectric generators with a 1.4 μ a controller. IEEE Journal of Solid-State Circuits, 44(10), 2824–2833. 62. Bose, S., Anand, T., & Johnston, M. L. (2019). Integrated cold start of a boost converter at 57 mV using cross-coupled complementary charge pumps and ultra-low-voltage ring oscillator. IEEE Journal of Solid-State Circuits, 54(10), 2867–2878. 63. Ballo, A., Bottaro, M., Grasso, A. D., & Palumbo, G. (2020). Regulated charge pumps: a comparative study by means of Verilog-AMS. Electronics, 9(6), 998. 64. Zhu, W., Jiang, J., Lin, D., Xiao, J., Yang, G., Li, X., & Zou, S. A. (2019). Charge pump system with new regulation and clocking scheme. IEICE Electronics Express Letters, 16(4), 1–5.

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Chapter 3

Design Strategies High-Speed Dickson CP

3.1 Introduction As for any electronic circuit, the speed performance of a CP is an important design metric. Indeed, in some applications, such as nonvolatile memories, CP speed performance (measured by the time needed to achieve the output steady-state voltage, known as settling or rise time) represents a key CP feature [1]. In all the applications where the loading effect can be modeled by a capacitor only, the output current in steady state is very small. To give some numerical examples, in nonvolatile memory applications, such as NOR Flash memories [1], the word line (WL) has a capacitance in the order of 10 pF, while in recent 3D NAND [2], the capacitance is 2.× and 4.× higher for a selected WL and deselected WLs, respectively. Some papers have dealt with the analysis and modeling of the time-domain response of a Dickson CP [3–6], and some of these also include design strategies to optimize it [7, 8]. In this chapter, two different solutions, mainly devoted to reducing the settling time assuming the same silicon area, are presented and discussed. The first solution makes use of a clock booster that doubles the CP clock amplitude [9, 10]. The second approach relies on an unconventional pumping capacitors sizing, which set them not equal, but following a linear distribution [11]. A third solution based on node pre-charging will be treated in the next chapter. Indeed, this technique leads also to the reduction of the energy consumed during the wake-up time of the CP that is a key aspect in energy harvesting systems of energy-autonomous nodes [12]. It is worth noting that, since the speed performance is, in general, strictly related to the total CP capacitance or, in other words, to the CP silicon area, the strategy used to improve the settling time assuming the same area can also be adopted to reduce the silicon area assuming the same speed performance.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 A. Ballo et al., High-Performance Integrated Charge Pumps, https://doi.org/10.1007/978-3-031-43597-3_3

67

68

3 Design Strategies High-Speed Dickson CP

3.2 Optimized CP with Clock Booster 3.2.1 Rise Time Reduction According to the model discussed in Chap. 1 (Sect. 1.2), reported in Fig. 3.1 for a better readability, a Dickson CP can be modeled with an RC circuit whose input and output are the output voltage variation (i.e., the output voltage increment), .Vout , and its steady-state value .Vout (∞), and the equivalent resistance and capacitance are given by [5, 6] N T N2 = CT CDCP

(3.1)

CDCP N 2C ≈ 3 (N + 1) 3

(3.2)

REQ =

.

CEQ =

.

Consequently, the corresponding time constant is expressed by  τEQ =

.

CL 1 + 3 CDCP

 T N2

(3.3)

The total CP capacitance, i.e., .CCP = NC, is used in the rightmost term of (3.1) and (3.1). From (3.3), it is apparent that the reduction of the number of stages, N , can improve the speed performance by square factor. However, the reduction of N reduces in turn the CP steady-state output voltage. Hence, considering that Vout (∞) = NVCK + VI N

.

(3.4)

we can increase the clock amplitude while maintaining the same maximum voltage increment and reducing the number of stages. To further understand how the rise time changes when increasing the clock amplitude and reducing the number of stages, let us consider the widely adopted and accurate model introduced in [5]. Combining it with the above model [4], we can write that the rise time of an (N/K) (N ) .N/k-stage CP, .T , normalized to the rise time of a N-stage CP, .TR , can be R expressed as Fig. 3.1 CP equivalent model

3.2 Optimized CP with Clock Booster

69

Fig. 3.2 Schematic diagram of a CP with clock booster

(N/K) TR . (N ) TR

  C ln 1 + N CeqL 1 ≈ 2 =  k 2 Ceq k ln 1 + N CL

(3.5)

where .k = VCK /VI N . Analysis of (3.5)1 shows that rise time can be heavily reduced with a proper choice of the k coefficient. Indeed, setting .k = 2 (which means halving (N/K) reduction. the number of stages), we can ideally achieve a 75% rise time .TR From the above considerations, we can reduce the CP settling time by using a clock amplitude higher than the power supply and reducing N while maintaining unchanged the CP steady-state output voltage. Thus, according to Fig. 3.2,2 we can implement a CP topology combining a Dickson CP with a clock booster (CKB) [13, 14], which doubles the clock voltage amplitude (i.e., .k = 2 and, therefore, .VCK = 2VI N ). The CP topology with a double clock booster and halved number of stages, which maintains equal the total CP capacitance, has a time constant that is theoretically four times lower than the original CP without a double clock amplitude. However, due to the actual driving capability of the CKB, in real implementations, such reduction is surely lower. To evaluate this reduction, we can model the finite level of current that the CKB can provide to the CP in the model of Fig. 3.1 to obtain the actual equivalent RC time constant of the CP with CKB. Since the CKB without an output load reaches its steady-state output voltage (i.e., a voltage twice the power supply) in one period only, we can assume that its equivalent capacitance is equal to zero and only an equivalent resistance, .RCKB , has to be considered to model the CKB. Then, the whole equivalent RC circuit for the CP with CKB can be assumed the one in Fig. 3.3.

1 The

approximation in (3.5) is given by applying Taylor’s expansion. the symbolism introduced in Chap. 2, the CTS in Fig. 3.2 assumes the model of a diode to recall the unidirectionality that the switch should have. However, also in this solution the CTS can have any other topology.

2 Unlike

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3 Design Strategies High-Speed Dickson CP

Fig. 3.3 Equivalent model of a CP with CKB

Like for a CP, the current given by CKB is limited by its capacitor value and, hence, it is reasonable to assume as equivalent resistance of the CKB the same equivalent resistance of a CP in (3.1). Thus, naming the total CKB capacitance and the halved number of stages of the CP with CKB with .CCKB and .NCP −CKB (i.e., .NCP −CKB = N/2), respectively, we get RCKB =

.

2 NCP −CKB T

CCKB

(3.6)

By using relationships (3.1), (3.2), and (3.6), and defining .CCP −CKB as the total capacitance of the CP without the CKB, the time constant of the whole CP yields  τCP =

.

CL 1 + 3 CCP −CKB

  CCP −CKB 2 1+ NCP −CKB T CCKB

(3.7)

Of course, the limited driving capability of the CKB reduces the potential speed advantage of a CP with CKB, see (3.7). Indeed, comparing (3.7) with the ideal case in which the CKB has infinite driving capability (i.e., .RCKB = 0), we find that the relative increase in the time constant is τ =

.

τCP − τCP i CCP −CKB = τCP i CCKB

(3.8)

This means that the reduction of the speed is exactly equal to the ratio between the total capacitance of the CP, deprived of the CKB, and the CKB capacitance. In other words, in a CP which a double CKB to get a speed advantage the CKB capacitance, .CCKB , must be comparable or higher than .CCP −CKB . Remembering that .NCP −CKB = N/2, note that the advantage becomes zero when .CCKB = CCP −CKB /3, since (3.7) becomes equal to (3.3). The requirements on the CKB capacitance mean that the reduced rise time is paid by increased silicon area. In any case, an advantageous design is achieved when the silicon area of the CP with CKB is almost equal to that of the traditional CP topology. In particular, naming .CT the whole capacitance of the CP with CKB, CT = CCP −CKB + CCKB

.

(3.9)

3.2 Optimized CP with Clock Booster

71

Fig. 3.4 .αT ,opt versus .CL /CT

and introducing a distribution factor, .α, CCP −CKB = αCT

(3.10)

CCKB = (1 − α) CT

(3.11)

.

.

relationship (3.7) becomes  τCP =

.



1 CL + 3 αCT

2 NCP −CKB T

1−α

(3.12)

From (3.12), the optimum value of .α that minimizes the rise time is found, as usual, setting to zero the first derivative of (3.12) that yields α 2 + 6α

.

CL CL −3 =0 CT CT

(3.13)

whose solution is αT ,opt

.

CL =3 CT

 1+

1 CL 3C T

 −1

(3.14)

Relationship (3.14) versus the ratio .CL /CT is plot in Fig. 3.4 and shows that the optimum value of .α typically ranges from 0.3 to 0.5.

72

3 Design Strategies High-Speed Dickson CP

By inspection of Fig. 3.4, it also appears that for load capacitor values much higher than the total CP capacitance, the optimum CP capacitance distribution, .αT ,opt , is obtained for values close to 0.5 (i.e., when the capacitance of the CP is equal to that of the clock booster). To compare the speed performance of the traditional Dickson CP with the topology with CKB, let us evaluate the relative reduction with respect to the traditional CP, which rewriting (3.12) as τCP −CKB

.

1 = 4



1 CL + 3 αCT



N 2T 1−α

(3.15)

yields τ  =

.

τCP −CKB − τDCP 1/4 = 1 − αT ,opt τDCP

1 3

CL αT ,opt CT CL 1 3 + CT

+

−1

(3.16)

Consider first the load equal or higher than the total CP capacitance, .CL ≥ CT and set .αT ,opt = 0.5 that allows to simplify (3.16) into τ  ≈ −

.

1 1 2 1 + 3 CL

(3.17)

CT

Relationship (3.17) shows that .τ  is lower than 1/8 and reduces increasing the ratio .CL /CT above 1. This means that the CP with CKB when .CL = CT provides a potential advantage in terms of rise time of only about 10%, and this advantage is even reduced when the load is higher than the total CP capacitance, an advantage that seems too limited under this condition. Let us consider now the cases when the CP capacitance is higher than the load capacitance, i.e., .CL /CT < 1, which is a common condition in nonvolatile memories applications [15, 16]. Under this condition, assuming .αT ,opt = 0.4 in (3.16) yields τ  ≈ −

.

3/5 CL 1 + 3C T

(3.18)

showing that the rise time advantage is at least 20% when .CL /CT = 2/3. Moreover, reducing the ratio .CL /CT , the advantage increases up to a maximum value higher than 60% when .CL /CT is negligible with respect to the value 1/3. Note also that despite (3.17) gives a maximum absolute value of 0.6 (i.e., a maximum rise time increase of 60%), it is a simplification of (3.15) with .αT ,opt = 0.4, while for .CL /CT much lower than 1, the .αT ,opt is close to 0.3 and a higher rise time advantage can be achieved. The ideal reduction of rise time versus the ratio of output load capacitance and total CP capacitance, according to Eq. (3.16), is plotted in Fig. 3.8.

3.2 Optimized CP with Clock Booster

73

Fig. 3.5 .αA,opt versus .CL /CCP for silicon area minimization

3.2.2 Silicon Area Reduction The speed performance advantages provided by the CP with CKB can be exchanged with silicon area (mainly fixed by the total capacitance of the stages since the transistors’ silicon area is usually negligible). This means that for equal rise time (i.e., equal time constant) the CP with a double CKB can also be used to reduce the silicon area as compared with the traditional CP topology. In particular, combining relationships (3.3) and (3.15) and assuming equal the time constant of both the CP with CKB and the traditional CP, we can write CT =

.

3CL

  L −1 α 4 (1 + α) 1 + 3 CCCP

(3.19)

Setting to zero the first derivative of (3.19), we obtain the optimum value of parameter .αA that defines the distribution of capacitance between the CP and the CKB. In particular, αA,opt =

.

1 1

− 2 8 1 + 3 CL CCP

(3.20)

is plot in Fig. 3.5 where it appears that the optimum value ranges from 0.4 to 0.5. Plotting and analyzing the ratio between the total area of the CP with CKB, and the area of traditional CP, .ADCP , versus .CL /CCP , as shown in Fig. 3.6, it can be noted marginal advantages when .CL is close to or greater than .CCP . On the contrary,

74

3 Design Strategies High-Speed Dickson CP

Fig. 3.6 Silicon area reduction versus .CL /CCP

a considerable area saving is obtained when .CL is lower than .CCP , achieving values greater than 60%.

3.2.3 Simulated Results and Comparison Validation of the CP with CKB topology and its advantages is performed designing and simulating using SPICE both the CP with CKB and the traditional CP with a different number of stages and various output capacitance values. To highlight the contributions of capacitors to the main performance of the circuit, we initially considered a CP with switches having on and off resistance equal to 10 . and 10 .T , respectively. The circuit scheme of the adopted CKB is shown in the leftmost part of Fig. 3.7. Transient simulations were run considering a number of stages equal to 8, 10, 12, 14, and 16 for a classical CP, and a number of stages equal to 4, 5, 6, 7, and 8 for a CP with CKB. Moreover, for all the considered topologies, the load capacitance was varied from 0.1 to 10 times the total capacitance value. The comparison between every couple of CPs (with and without CKB) was carried out for equal steady-state output voltage and total capacitance, and the results found are summarized in Fig. 3.8, which shows the simulated relative reduction of rise time, evaluated at 90% of the steady-state output voltage, between the CP with CKB and the conventional CP versus the ratio .CL /CT . In the same figure, the theoretical ratio between CP with CKB rise time and that of the traditional CP (i.e., relationship (3.15) plus 1) has been included.

3.2 Optimized CP with Clock Booster

75

Fig. 3.7 Block scheme of the latched CP and CKB

Fig. 3.8 Simulated rise time ratio of CP with CKB and the conventional CP versus .CL /CT using ideal switches

76 Table 3.1 Design parameters

3 Design Strategies High-Speed Dickson CP Stages 8 10 12 14 16

.CT

240 300 360 420 480

(pF )

.TR (.μs)

@ .CL /CT = 0.1, 1, 10 67, 197, 1505 116, 328, 2493 168, 476, 3614 230, 651, 4914 302, 853, 6476

From Fig. 3.8, it can be noted that the errors between the theoretical analysis and the simulation are always lower than 6%, with higher errors for small values of .CL /CT . Indeed, high superposition of the simulated curves highlights a low dependence of the ratios by the number of stages of the CP. A more realistic validation has been carried out by comparing transistor level implementations of a classical latched CP [17, 18] and its improved version with CKB (see Fig. 3.7), using a standard CMOS 65-nm technology. It is worth noting that the latched CP represents an efficient implementation of the conventional CP. Table 3.1 reports the total capacitance and the rise time of the classical latched CP in the various scenarios. Aspect ratio of transistors Mni and Mpi is set equal to (0.8/0.28) and (1.2/0.28) for the classical CP and the CP with CKB, respectively. The clock booster has been sized in the same way for all simulations; in particular, aspect ratio of M1 and M2 is set equal to (8/0.28), while inverters are sized 3 times larger than a minimum inverter. Capacitors of the stages and the clock booster have been implemented using MIM capacitors having 1-fF/.μm.2 specific capacitance. The model of this component takes into account also the parasitic to ground. The switching frequency and the voltage supply were set to 1 MHz and 1.2 V, respectively. Maximum percentage error of the simulated classical latched CP rise time in comparison to its estimation by equation in [5] is lower than 12%. The relative reduction of rise time between the latched CP with CKB and the conventional latched CP versus the ratio .CL /CT is plotted in Fig. 3.9. Results show the advantage obtained by the topology with the double CKB and the accuracy with respect to the theoretical model described above. Indeed, the maximum percentage error of the simulated latched CP as compared to the analytical model is lower than 8.7%. The main performance parameters of the two compared topologies in the worstcase condition (.N = 16, .CL /CT = 10) are reported in Table 3.2. All the above results make double clock boosting technique attractive, mainly for applications in which small memories must be quickly erased/programmed or when area occupation must be reduced while maintaining the same rise time. Finally, it is worth noting that the solution with CKB entails a very slight increase of circuit complexity since only the clock booster shown in the leftmost inset of Fig. 3.7 has to be added to the conventional CP topology.

3.3 CP with Linear Distribution of Capacitance

77

Fig. 3.9 Simulated rise time ratio of transistor level latched CP with CKB versus .CL /CT Table 3.2 Performance parameters comparison (.N = 16, .CL /CT = 10)

Parameter Current consumption (.μA) Power efficiency % Output ripple (mV)

Latched 212.1 99.5 4.20

Proposed 216.5 94.6 1.46

3.3 CP with Linear Distribution of Capacitance 3.3.1 Design Strategy Consider a classical N-stage Dickson CP with a generic CTS (see Fig. 3.10) and evaluate the total amount of input charge during the transient considering the methodology originally presented in [5]. The total amount of input charge during the transient is due to the charge stored in the output capacitor, .CL , and the sum of the charge stored in the odd-, .C2k−1 , and the even-order, .C2k , capacitors, during a generic j -th semi-period, whose expressions are, respectively, given by [5, 6] Q (2k − 1, j ) = (2k − 1) C2k−1 Vg − 2 (k − 1) qout .

.

Q (2k, j ) = 2kC2k Vg − 2kqout

(3.21a) (3.21b)

where .Vg is the overdrive voltage in each stage (equal to .VI N when the CTS is an ideal switch) and .qout is the amount of charge transferred to the output stage during the start-up transient, whose relationship can be written as [5]

78

3 Design Strategies High-Speed Dickson CP

Fig. 3.10 Block scheme of the generic Dickson CP

qout = T

.

C [(N + 1) VI N − VOU T ] = [(N + 1) VI N − VOU T ] N Req

(3.22)

where .Req is the CP equivalent output resistance, given by (3.1) for the traditional Dickson topology with equal capacitors (i.e., equal to .N T /C) [19]. Assuming that odd-stages capacitors are pre-charged to .CVg [5], we can compute relationships (3.21) assuming a linear distribution for the capacitors values. In particular, to distribute the value of capacitances along the CP, we assume that the center of distribution is located near the center stages, i.e., (.N + 1)/2 and N /2 for an even and odd number of stages, respectively. Hence, for an even number of stages, evaluating the

through two points, the initial one

equation of a straight line passing (N +1) CT (1−a)CT , and the middle one . . 1, 2 N , yields N 

CT .Ck = N

k−1 (1 − a) + 2a N −1

(3.23)

Similarly, for an odd number of stages, we found Ck =

.



CT N

(1 − a) + 2a

k−1 N −2



The distribution (3.23) can be positive or negative. Note that to avoid negative values of (3.23) when .k = 1 and .k = N, relationship .|a| < 1 must be satisfied. To confirm the effectiveness of (3.23), observe that N

.

C k = CT

(3.24)

k=1

and when parameter a is assumed equal to 0, we find the common design assumption with all capacitances equal to C. To give an idea of the capacitor values distribution, the values normalized to the total capacitance, .CT , as a function of its position, k, are plotted in Fig. 3.11 for a 20-stage Dickson CP for different values of the slope parameter a. In order to estimate the rise time and the total current consumption in the start-up phase, let us evaluate the RC equivalent model in Fig. 3.1 [6] and [19] for an even number of stages, whose parameters are derived in the last Appendix for the linear distribution case (similar results can be obtained for an odd number of stages)

3.3 CP with Linear Distribution of Capacitance

79

Fig. 3.11 k-th normalized capacitor values for 20-stage Dickson CP and different slope parameter values

Req,L

.

  −1 N N 

Req,D T k−1 = 1+ 2 −1 a = N N −1 Ck k=1

(3.25)

k=1

 Ceq,L = Ceq,D 1 + a

.

3N 2 − 2 4N 2 + 3N + 2

(3.26)

where .Req,D and .Ceq,D are the parameter values for the conventional Dickson CP with equal stage capacitors given by (3.1) and (3.2), respectively. It is worth noting that (3.25) is a sum of positive terms where parameter a is at the denominator of each term, and the coefficient of a in each term is always lower than or equal to 1. Thus, terms are negligible for low values of a, and an equivalent resistance value close to the traditional Dickson CP given by (3.1) is obtained. On the other hand, relationship (3.26) is apparently linearly dependent of the slope parameter, a. To compare the performances of the topology with capacitance value distribution with the traditional one, the ratios between the parameters .Req,L /Req,D and .Ceq,L /Ceq,D have been evaluated and plotted in Fig. 3.12 versus different values of the slope parameter a and for a different number of stages. By inspection of Fig. 3.12, it is apparent that any arrangement of the total capacitance with differently sized stage capacitances leads to a higher output equivalent resistance, which means a worsening of the CP current drivability. Thus, to limit the increase of CP output resistance, the value of the slope parameter, a, should be in the range .−0.5 ÷ 0.5. This choice allows to restrain the worsening of the output equivalent resistance under about 13% for a 4-stage CPs, and it is also lower than this value for CP with a higher number of stages. Finally, from Fig. 3.12, it can be noted that a significant linear reduction of the equivalent CP self-capacitance is found when the

80

3 Design Strategies High-Speed Dickson CP

Fig. 3.12 Normalized equivalent parameters versus slope parameter a, for a different number of CP stages

slope parameter a is negative (i.e., when capacitor values decrease along the CP from the input to the output). A deeper insight of the CP behavior can be obtained through the evaluation of its intrinsic time constant, .τeq,L (i.e., .τeq in the (3.3) relationship), which characterizes the intrinsic transient response of the CP. It is worth noting that .τeq,L represents the dominant contribution on the transient response when .CL is sufficient lower than .Ceq , which, combining (3.2) with (3.26) for the linear distribution, can be approximated as Ceq,L ≈

.

CT 3

  3 1+a 4

(3.27)

By inspection of (3.25) and (3.26), we get that the intrinsic time constant is the product of a term equal to or slightly higher than (3.1) and a term that can be lower or higher than (3.2) (depending linearly with a). Hence, the intrinsic time constant of the linear distribution design for .a > 0 is surely higher than the intrinsic time constant of the traditional Dickson CP, while it can be lower for .a < 0 down to a value in which the increase of the resistance in (3.25) with respect to (3.1) becomes higher than the decrease of the capacitance in (3.26) with respect to (3.2). The intrinsic time constant value, normalized with respect to the intrinsic time constant of a Dickson CP in (3.3), is plotted in Fig. 3.13 versus different values of the slope parameter, a, for a different number of stages. From Fig. 3.13, it is apparent the intrinsic rise time improvement achieved by adopting the linear capacitance distribution at the cost of a slight increase of the equivalent output resistance .Req . Hence, this advantage can be gained in all the CPs where .Ceq > CL . By inspection of Fig. 3.13, it can also be noted that an optimum slope parameter value, .aT ,opt , exists that minimizes the intrinsic time constant. This value is close to

3.3 CP with Linear Distribution of Capacitance

81

Fig. 3.13 Normalized CP intrinsic time constant versus slope parameter a, for a different number of CP stages

−0.8 for .N >10. However, even if a significant reduction of the intrinsic rise time can be obtained with the optimum .aT ,opt value, it has the cost of a not negligible output resistance increase. Therefore, a moderate while effective choice for a is a value equal to or higher than .−0.5. Finally, it is worth noting that since the average input energy during the rise transient is given by

.

   EI N = QI N VI N = (N + 1) Ceq + CL Vout (TR ) − Vg VI N

.

(3.28)

where .Vout (TR ) is the output voltage at the end of the rise time, .TR , in CPs with Ceq > CL the adoption of the proposed capacitance sizing also determines a reduction of the demanded transient energy, due to the linear relation between the average input energy and the CP self-capacitance.

.

3.3.2 Simulated Results and Comparison Validation of the CP linear distribution sizing strategy has been done by using a 12stage and a 20-stage latched CP, both of them designed and simulated with linear distributed and equal stage capacitances, for equal total capacitance CT (which means equal area occupation). The circuits are designed using a CMOS 130-nm triple-well technology provided by STMicroelectronics, whose main parameters are summarized in Table 3.3. The simplified block diagram of the CP is depicted in the left side of Fig. 3.14, in which the single stage (dashed box) is shown in detail. It is worth noting that the symmetry of the distribution suggests designing near stages equidistant from the

82

3 Design Strategies High-Speed Dickson CP

Table 3.3 Process parameters and design constraints Parameter .Vtn0 .Vtp0 .μN COX .μP COX

BDV

Typical value 697 626 137 70 4.8

Unit mV mV 2 .μA/V. 2 .μA/V. V

Parameter = VCK frequency .CT .(W/L)N .(W/L)P .VI N

Value 1 4 240; 400 50/0.5 50/0.5

Unit V MHz pF .μm/.μm .μm/.μm

Fig. 3.14 Scheme of the latched CP with the single stage in detail Fig. 3.15 Layout of a 12-stage CP with .a = −0.5

center, for example (.N/2 − 1)-th with the (.N/2 + 1)-th and so on. Thus, the total area of each couple is equal, and a CP with regular shape can be obtained. As an example, see Fig. 3.15 where the layout of the 12-stage CP with .a = −0.5 is shown. The design constraints and the aspect ratio of the transistors used to implement each CTS are also summarized in Table 3.3. In order to emulate a more realistic implementation, the simulation setup is implemented by using as power supply a 1-V voltage generator with an output resistance, .RT H , equal to 100 ., and clock signals derived from the power supply thanks to real switches having .RON and .ROF F equal to 100 . and 1 .T , respectively. Moreover, to avoid short circuit currents of the clock generation system, non-overlapped clock signals are adopted. Pumping capacitors are implemented by

3.3 CP with Linear Distribution of Capacitance

83

Fig. 3.16 Transient output voltages for .a = −0.1 and .a = −0.5 without a load applied and, after the steady state is reached, with a load current .IL = 20 μA, for: (a) the proposed and traditional 12-stage CPs, and (b) 20-stage CPs

metal–insulator–metal (MiM) capacitors, which exhibit very low stray capacitances, high specific capacity, and a high breakdown voltage (about 20 V). The comparison between the proposed and classical CPs has been carried out using the same design parameters, transistors size, and total capacitance value. The metrics considered are the rise time ratio, defined as the ratio between the rise time of the proposed and traditional CPs, the average current consumption during their own rise time, the output resistance, and the V CE, defined in (2.5). Post-layout transient simulations are summarized in Fig. 3.16a and b for 12- and 20-stage topologies, respectively, considering the parameter distribution a equal to

84

3 Design Strategies High-Speed Dickson CP

Fig. 3.17 Voltage drop across the sixth CTS of the 12-stage charge pumps in start-up, no-loaded steady-state and loaded steady-state conditions

−0.5 and .−0.1. As expected, we found a rise time sensibly lower than the classical CP. The not significant drawback due to the current drivability reduction, originating from a small increase of the CP output resistance, is highlighted in the rightmost part of the graphs, where the output voltage of the proposed solutions reaches steadystate values lower than the classical ones when a current load (.IL = 20 μA) is applied. Time diagrams of the inter-stage voltage difference across the sixth CTS during the start-up, in no-loaded steady-state and loaded steady-state conditions, are shown in Fig. 3.17. This figure shows that the change of the charge transfer ratio between two adjacent stages produces a slight change of the voltage drop on the switches, which means that no further over-stress voltage arises under the considered distribution. The analytical and simulated rise time ratios are compared for different slopes and under different values of .CL /CT in Fig. 3.18. From this figure, it is apparent the advantage in terms of speed achieved with the linear distribution when the capacitive load does not dominate the time constant of the CP and the slope is negative. Furthermore, the proposed model is able to predict the advantage in terms of rise time with a maximum error less than 11.3% (.a = −0.5) with respect to the postlayout simulations, which decreases under 6.9% if compared to SPICE simulations by using ideal switches. Moreover, it is worth noting that the actual CP shows a better speed than that predicted by the model; hence, the model underestimates the benefits of the proposed solution. Table 3.4 summarizes the main simulation results for all different scenarios when the applied capacitive load is ten times lower than the total CP capacitance. As a

.

3.3 CP with Linear Distribution of Capacitance

85

Fig. 3.18 Comparisons between proposed vs. traditional CP rise time ratios for different slope values and for different values of .CL /CT Table 3.4 Simulation result summary Parameter CP Proposed .V CEMAX .EI N (nJ ) .Req (.k) Latched .V CEMAX .EI N (nJ ) .Req (.k)

12-stage = −0.1 0.97 14.14 144.5 0.97 14.74 144

.a

= −0.5 0.967 11.81 171.1

.a

20-stage = −0.1 0.97 63.47 240.5 0.97 66.02 239.5

.a

= −0.5 0.967 53.54 277.4

.a

6-stage = −0.1 0.965 1.31 103.2 0.97 1.85 75

.a

= −0.5 0.965 1.31 102.3

.a

proof of good sizing of the circuit, V CE values are near the unity for all the cases. The average input energy is decreased by 6% and 19% for .a = −0.1 and .a = −0.5, respectively, while the output resistance increase (18.8%) is the cost to pay for the rise time improvement, which is almost equal to 30%. Finally, a deeper analysis of [20], where a different kind of unequal capacitor sizing is reported, shows that its design strategy, despite the complex mathematical model adopted (numerically evaluated only for N up to 6), yields an almost linear capacitance distribution for .a = −0.69 and when .CL /CT is lower than 1. Hence, the same capacitor values of the above described approach for this slope parameter value are obtained, thus providing the same speed performance of the proposed topology, as summarized in Table 3.4.

86

3 Design Strategies High-Speed Dickson CP

Appendix: Equivalent Parameters Computation From relationships (3.21) and including the initial conditions, we can evaluate the total amount of charge injected from the power supply to the charge pump during the time j -th as the difference between the two following equations: N

  kCk kVg − Rk IOU T (j )

(3.29)

 T IOU T (j ) (2k − 1) C2k−1 Vg − C2k−1

(3.30)

.

k=1 N/2

.

k=1

Equation (3.30) represents the total charge demanded by the k-th stage, and it shows that the charging speed is related to the equivalent resistance seen by that stage, .Rk , given by k  k

T NT i − 1 −1 .Rk = = (1 − a) + 2a CT N −1 Ci i=1

(3.31)

i=1

Equation (3.30) is due to redistribution mechanism that holds in the CP, and, therefore, it gathers the amount of charges that must not be taken into account for the evaluation of the total current consumption. To compute the parameters of the CP equivalent model, .Req and .Ceq , as well as the intrinsic time constant .τeq , are enough to solve the total input charge increment between two consecutive instants j and .j + 1 given by the difference (3.29) and (3.30), in which the output current is given by the second term of (3.22), resulting in

.

=

VOU T

(N + 1) Ceq [VOU T (j + 1) − VOU T (j )] =  N N

(j + 1) − VOU T (j ) kCk Rk − (2k − 1) T Req k=1

(3.32)

k=1

Therefore, the intrinsic time constant is given by τeq = Req Ceq

.

⎤ ⎡  N/2  k−1 N

T ⎦ T 1 ⎣ = + kCk (2k) C2k Ci C2k N +1 k=1

i=1

(3.33)

k=1

from which the equivalent parameters are

Req

.

N

T = Ck k=1

and

Ceq

⎤ ⎡  N/2 N  Rk−1 T /C2k ⎦ 1 ⎣ kCk + = (2k) C2k N +1 Req Req k=1

k=1

(3.34)

References

87

Fig. 3.19 Charge pump equivalent lumped RC circuit

The achieved results suggest that a further and generalized equivalent circuit to model the Dickson CP can be the lumped RC circuit, reported in Fig. 3.19 for an even number of stages. The model can be validated calculating, by means of (3.34), the parameters for the classical Dickson CP and noting that they coincide with them. With the adopted distribution, the charge transfers from one stage to the following one are not equal (as shown by the ratio .Rk−1 /Req , which, unlike the classical distribution, is not equal to k). This makes the solution of (3.33) not trivial to pursue, and to achieve it, we approximate the ratio .Rk−1 /Req with (.k − 1). Despite the approximation done shows a maximum error with respect to the exact one as high as 40%, it allows to solve (3.33) and (3.34) that give the intrinsic time constant and the equivalent self-parameters, among which Ceq =

.





 CT 4N 2 + 3N + 2 + a 3N 2 − 2 12N (N + 1)

(3.35)

and shows an error with respect to simulation results lower than 7% (as apparent from Fig. 3.19).

References 1. Tanzawa, T., & Atsumi, S. (1999). Optimization of word-line booster circuits for low-voltage flash memories. IEEE Journal of Solid-State Circuits, 34(8), 1091–1098. 2. Tanzawa, T., Murakoshi, T., Kamijo, T., Tanaka, T., McNeil, J. J., & Duesman, K. (2016). Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors. In IEEE Asian Solid-State Circuits Conference 2016 (A-SSCC 2016) (pp. 165–168). 3. Cataldo, G. D., & Palumbo, G. (1993). Double and triple charge pump for power IC: Dynamic models which take parasitic effects into account. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 40(2), 92–101. 4. DiCataldo, G., & Palumbo, G. (1996). Optimized design of an n-th order Dickson voltage multiplier. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(5), 414–418. 5. Tanzawa, T., & Tanaka, T. (1997). A dynamic analysis of the Dickson charge pump circuit. IEEE Journal of Solid-State Circuits, 32(8), 1231–1240. 6. Palumbo, G., Barniol, N., & Bethaoui, M. (2000). Improved behavioral and design model of an n-th order charge pump. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 47(2), 264–268.

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7. Palumbo, G., Pappalardo, D., & Gaibotti, M. (2006). Charge pump with adaptive stages for non-volatile memories. IEE Proceedings-Circuits, Devices and Systems, 153(2), 136–142. 8. Saeed, A., Ibrahim, S., & Ragai, H. F. (2017). A sizing methodology for rise time minimization of Dickson charge pumps with capacitive loads. IEEE Transactions on Circuits and Systems II: Express Briefs, 64(10), 1202–1206. 9. Ballo, A., Giustolisi, G., Grasso, A. D., & Palumbo, G. (2018). A clock boosted charge pump with reduced rise time. In 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2018 (pp. 605–608). 10. Ballo, A., Grasso, A. D., Giustolisi, G., & Palumbo, G. (2019). Optimized charge pump with clock booster for reduced rise time or silicon area. IEEE Transactions on Circuits and Systems II: Express Briefs, 66(12), 1977–1981. 11. Ballo, A., Grasso, A. D., Palumbo, G., & Tanzawa, T. (2020). Linear distribution of capacitance in Dickson charge pumps to reduce rise time. International Journal of Circuit Theory and Applications, 48, 555–566. 12. Ballo, A., Grasso, A. D., & Palumbo, G. (2020). Charge pump improvement for energy harvesting applications by node pre-charging. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(12), 3312–3316. 13. Nakagome, Y., et al. (1991). Experimental 1.5V 64Mb DRAM. IEEE Journal of Solid-State Circuits, 26(4), 465–472. 14. Ying, T., et. al. (2003). Area-efficient CMOS charge pumps for LCD drivers. IEEE Journal of Solid-State Circuits, 38(10), 1721–1725. 15. Won, O. Y., et. al. (2012). A comparative study of charge pumping circuits for flash memory applications. Microelectronics Reliability, 52(4), 670–687. 16. Rumberg, B., et. al. (2017). A regulated charge pump for tunneling floating-gate transistors. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(3), 516–527. 17. Gariboldi, R., & Pulvirenti, F. (1994). A monolithic quad line driver for industrial application. IEEE Journal of Solid-State Circuits, 29(9), 957–962. 18. Gariboldi, R., & Pulvirenti, F. (1996). A 70 mW intelligent high side switch with full diagnostics. IEEE Journal of Solid-State Circuits, 31(7), 915–923. 19. Dickson, J. (1976). On-chip high-voltage generation MNOS integrated circuits using an improved voltage multiplier technique. IEEE Journal of Solid-State Circuits, SC-11(3), 374– 378. 20. Saeed, A., Ibrahim, S., & Ragai, H. F. (2017). A sizing methodology for rise-time minimization of Dickson charge pumps with capacitive loads. IEEE Transactions on Circuits and Systems II: Express Briefs, 64(11), 1202–1206.

Chapter 4

Design Strategies for Low-Power Dickson CP Applications

4.1 Introduction Among the strategies adopted at the architectural level, duty cycling is a very effective solution extensively implemented to meet the limited power budget of autonomous nodes [1] (Fig. 4.1). The power management unit (PMU) of a dutycycled system includes two different kinds of power converters (Fig. 4.2), namely always-on and duty-cycled converters, which are used to deliver power during the active and sleep modes, respectively, to the different building blocks of the node. The overall energy consumption of the system can be expressed as [2] Etotal = Pactive tact

.

  + Psleep tcycle − tact +



tw−up

Iw−up (t) Vact (t) dt

(4.1)

0

where .Pactive and .Psleep is the power during the active and sleep state, respectively, tw−up is the time necessary to the duty-cycled converter to generate its nominal output voltage, .tact is the time during which the node is activated, .tcycle is the interval between each activation, .Iw−up is the current absorbed by the node during .tw−up , and .Vact is the voltage at the output of the converter. The latter term in (4.1) represents the energy consumed by the duty-cycled converter during the wake-up time, and in some applications, it constitutes a significant percentage of the overall energy consumption [2–4]. A design strategy that reduces the current absorbed by the node during the wakeup or speeds up the dynamic behavior of the converters, maintaining the same input energy or even reducing it, can contribute to improve the power efficiency of the whole system. Indeed, the energy consumed by the duty-cycled converter during the wake-up time can be minimized by reducing its current consumption, .Iw−up , during .tw−up and/or .tw−up itself. With this in mind, this chapter gathers two different .

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 A. Ballo et al., High-Performance Integrated Charge Pumps, https://doi.org/10.1007/978-3-031-43597-3_4

89

90

4 Design Strategies for Low-Power Dickson CP Applications

Fig. 4.1 Block diagram of a duty-cycled system

Fig. 4.2 Original Dickson CP with parasitic capacitance contribute

solutions aimed to the reduction of the energy consumed by the converter during the wake-up phase. In particular, in the first section, a solution based on the reduction of the voltage amplitude of the clock signal is presented [5]. It represents a simple but very effective design strategy to increase power conversion efficiency. In the second section, it is shown that with node pre-charging, simply implemented by means of few auxiliary diodes and parasitic junctions, the CP retains the charges in the pumping capacitors when the harvesting power source is not able to feed the system, thereby reducing the input energy, and the rise time too, during the start-up phase [6].

4.2 Clock Voltage Amplitude Reduction

91

4.2 Clock Voltage Amplitude Reduction 4.2.1 Design Strategy Let us consider a generic Dickson CP in Fig. 4.3 with CTS implemented by diodes, as in the original topology proposed by Dickson [7], where stray capacitances at the top and bottom plates of C are also explicitly represented by .CT = αT C and .CB = αB C, respectively, being .αT and .αB technology-dependent parameters. The power consumption of the CP in steady-state condition can be expressed by (a more detailed expression can be found by substituting the exact expression of .VOU T as reported in [8]) PCP = IL VOU T + PLOSS

(4.2)

.

where .PLOSS takes into account the power needed to charge and discharge the top and the bottom parasitic capacitors, conduction losses due to the internal resistance of each CTS, and charge transfer losses due to the charge redistribution from two adjacent pumping capacitors. .PLOSS can represent a significant percentage contribution of (4.2), especially in ultra-low-power applications, and it can potentially determine a significant reduction of the power conversion efficiency [9]. Considering, as usual, that the main power loss contribution is given by charging/discharging of the bottom plate parasitic capacitor, .CB (remember that parasitic capacitor at the top plate of the pumping capacitors is usually enough distant from the substrate to consider .αT almost equal to zero), we can estimate the power loss as 2 PLOSS = αB Nf CVCK

(4.3)

.

which shows a quadratic dependence with the clock amplitude, .VCK . The quadratic dependence of .PLOSS suggests that we can strongly decrease it by lowering .VCK . Nonetheless, being the output voltage given by (1.4), reducing .VCK will cause a lowering of the output voltage. To compensate such reduction, we can increase the number of stages [5]. More specifically, writing the steady-state output voltage, including the parasitic capacitor effect, as VOU T = VI N

.

  − VT h + N VCK

1 1 + αT



IL − VT h − fC

 (4.4)

and considering .VCK = βVI N , with .β smaller than unity, we get VOU T ,β = VI N

.

  − VT h + Nβ βVI N

1 1 + αT



IL − VT h − fC

 (4.5)

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4 Design Strategies for Low-Power Dickson CP Applications

By equating (4.4) and (4.5), we can find the new number of stages, .Nβ , that leaves unaltered the output voltage versus the parameter .β



− VT h − fILC N

.Nβ = N ≈ 1 β − VT h − fILC βVI N 1+α T VI N

1 1+αT

(4.6)

The rightmost simplification of (4.6) holds neglecting the top plate parasitic capacitor, the diode threshold voltage, and assuming the ratio .IL /f C much lower than .VI N . Substituting (4.6) into (4.3), we find PLOSS = αB βNf CVI2N

.

(4.7)

that shows the feasibility of significantly reducing the switching power losses by decreasing the clock signal amplitude. Moreover, as positive collateral effects, the output voltage ripple is also reduced since the number of the stages is increased. As an example, setting .β = 0.5 (i.e., halving .VCK with respect to .VI N ), we can halve .PLOSS at the cost of doubling the number of stages, i.e., doubling the area occupation. To design the CP with a defined .β value and minimizing the power consumption, we can directly apply the results in (1.31), yielding [5]     VOU T αT −1 .Nβ = 1+ 1 + αT βVI N

(4.8)

Of course, additional circuitry is required to get an amplitude for .VCK lower than .VI N . However, it can be simply implemented using an unregulated switched capacitor converter whose power conversion efficiency can be as high as 99% [9]. In principle, also a linear voltage regulator could be adopted to generate .VCK lower than .VI N . Nonetheless, in this case, an additional power loss term, due to the voltage drop over the regulator, is added in (4.7), thus nullifying the advantage of the proposed strategy.

4.2.2 Validation and Comparison The above design strategy has been confirmed through extensive simulations carried out on 2-, 4-, 6-, and 8-stage latched CPs [10, 11] (elementary building block of the patched CP is reported in Fig. 4.3) implemented in a standard 65-nm CMOS technology. Assuming a load capacitor equal to 160 pF, stage capacitance has been set to 10 pF, and the NMOS and PMOS transistor aspect ratio has been set to

4.2 Clock Voltage Amplitude Reduction

93

Fig. 4.3 Circuit scheme of the elementary latched CP block

Fig. 4.4 Summary of the simulation results

10 .μm/120 nm (the value of the channel length was set twice the minimum value to minimize the reverse current loss). Different scenarios have been studied by adopting two different values of supply voltage (1 V and 0.8 V) and clock frequency (1 MHz and 2 MHz) and three different values of the technology parameter .αB (0.01, 0.1 and 0.2). Simulations for .αB = 0.01 have been carried out considering metal–insulator–metal (MIM) capacitors. The other two .αB values model actual parasitic effects of the other kind of capacitors typically available in the design kits. The simulated average power loss is summarized in Fig. 4.4. The results are normalized to the one of the corresponding 2-stage CP, for .Nβ equal to 4 (.VCK = 0.5.VI N ), 6 (.VCK = 0.33 .VI N ), and 8 (.VCK = 0.25 .VI N ), respectively.

94

4 Design Strategies for Low-Power Dickson CP Applications

Fig. 4.5 Transient output voltage comparison of the simulated CPs (.VI N = 1 V, .f = 2 MHz)

Data are also compared with CPs implemented with ideal switches and the theoretical model carried out in the previous subsection, and from Fig. 4.4, it is evident that the power loss reduction is well predicted by the theoretical model. In Fig. 4.5, the transient output voltages of the 2-, 4-, 6-, and 8-stage CP with no load applied until .2 ms and, subsequently, with a load current equal to 10 .μA are reported. Note that driving capability of 8-stage CP is heavily reduced due to the clock voltage amplitude (equal to 0.25 V) that forces the transistors working in subthreshold. As expected, the rise time increases with an increasing number of stages. In particular, as compared to the 2-stage CP, the rise time is increased by 89%, 227%, and 1741% for the 4-, 6-, and 8-stage CP, respectively. These results suggest that the 4-stage CP (.VCK = 0.5 .VI N ) represents the best compromise between settling time and power loss reduction (50%). Finally, in Fig. 4.6, the transient output voltage compared with the basic 2-stage CP and the 4-stage CP with .VCK = 0.5.VDD (clock frequency is equal to 1 MHz, .VI N = 1 V for all solutions) is reported. Again in these cases, the CPs start with no load, while a current load is applied at .0.5 ms. It can be observed that for the 4-state CP with halved pumping capacitors the settling time is increased by 273% and the driving capability is slightly decreased with respect to the basic 2-stage CP. These results suggest that a compromise between area occupation, settling time, driving capability, and power loss reduction must be found according to the specific application.

4.3 Node Pre-charging Technique

95

Fig. 4.6 Transient output voltage of the CP (.VI N = 1 V, .f = 2 MHz)

4.3 Node Pre-charging Technique 4.3.1 Design Strategy Let us analyze the behavior of the CP when each intermediate node is pre-charged to a voltage equal to .Vg that represents the maximum voltage increase given by each stage [6]. The value of .Vg depends upon the specific charge transfer switch adopted for the CP (for example, in the case of a simple diode-connected transistor, .Vg is equal to .V I N − VT , where VT is the device threshold voltage). Evaluation of the total input energy and the rise time, respectively, yields [12, 13]   EI N = (N + 1) CL VP P − Vg VI N

(4.9)



VP P −Vg ln 1 − (N +1)V −V g g .TR = T

−1 C ln 1 + N CL

(4.10)

.

where .VP P is the actual output voltage. In the case of fully discharged intermediate nodes (i.e., without pre-charging), the total input energy and rise time are given by EI N,N CP = (N + 1)2 CL αVg VI N

.

TR,N P C = T

.

ln [1 − α]

−1 ln 1 + NCCL

(4.11) (4.12)

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4 Design Strategies for Low-Power Dickson CP Applications

Fig. 4.7 Analytical input energy and rise time ratios versus .α

where coefficient .α is defined as α=

.

VP P (N + 1) Vg

(4.13)

and represents the ratio between the desired output voltage, which is typically set by a feedback loop [6], and the maximum achievable output voltage, which is a function of .Vg and the number of stages of the CP. To estimate the improvement of the performances for the CP with pre-charged intermediate nodes, the ratios of (4.9) over (4.11) and (4.10) over (4.12) are reported as a function of parameter .α and the number of stages, N, as .

EI N EI N,N CP

 =α α− ln

.

1 N +1

N +1 N

 (4.14)



TR +1 = TR,N P C ln (1 − α)

(4.15)

and are plotted in Figs. 4.7 and 4.8, respectively. By inspection of (4.14), the energy ratio is always lower than 1 and decreases decreasing .α and N. Almost the same behavior is provided by (4.15) and shown in Fig. 4.8. Thus, significant energy and speed improvements can be achieved by the proposed CP for .α