Electronic Components and Technology (Solutions, Instructor Solution Manual) Third Edition [3 ed.] 9780849374975, 9780863801891, 0849374979

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Instructors Manual for Electronic Components and Technology Stephen J. Sangwine November 28, 2006

Contents Chapter 1: Introduction

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Chapter 2: Interconnection technology

2

Chapter 3: Integrated circuits

2

Chapter 4: Power sources and power supplies

3

Chapter 5: Passive electronic components

4

Chapter 6: Instruments and measurement

6

Chapter 7: Heat management

7

Chapter 8: Parasitic electrical and electromagnetic effects

8

Chapter 9: Reliability and maintainability

10

Chapter 10: Environmental factors and testing

12

Chapter 11: Safety

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Preface This manual includes solutions and some supporting text and explanation for each Exercise and Problem included in the book. Exercises are short problems included in the body of a chapter, usually with a brief numerical answer given, but no working. This manual gives the working, and discusses points that could be used in class. Problems are listed at the end of most chapters and short answers are given at the end of the book. This manual gives a worked solution to show how the answer is arrived at. In addition, the book contains Worked Examples in most chapters. As the name suggests, these include working and answers, and they are therefore not covered in this manual. A note about calculations: in this manual some calculations are expressed in scientific notation, and some using engineering notation with SI prefixes. Students should, of course, become fluent in calculating with either system and should know all the commonly used SI prefixes in terms of powers of ten. Thus they should be able to calculate 17 mV/220 k without having to look up the definition of milli as 10−3 or kilo as 103 . Stephen J. Sangwine Colchester, UK Email: [email protected]

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Chapter 1: Introduction There are no exercises or problems in this short chapter.

Chapter 2: Interconnection technology There are no exercises in this chapter. Problem 2.1 The problem requires calculation of the cross-sectional area A of conductor, given the resistivity, the current and the maximum permitted voltage drop. The instruction to ignore heating effects is included because a rise in temperature of the conductor would change the resistivity. From Ohm’s Law, the voltage drop per unit length of conductor is given by V = I R where R is the resistance per unit length. The resistance per unit length of conductor is given by ρ/A where ρ is the resistivity in m (given in the problem), and A is the cross-sectional area in m2 (to be found). Hence, the required cross-sectional area is given by: ρI V

A= Substituting the numerical values given we get: A=

1.7 × 10−8 m × 10 A 0.050 Vm−1

= 3.4 × 10−6 m2 = 3.4 mm2

Note that the answer should be in square millimetres, not square metres, because this is a practical-sized unit for electrical and electronic wire cross-section (and one that is always used in practice in preference to the more scientific unit of square metres). Problem 2.2 This problem imagines a printed-circuit backplane which is used to interconnect a number of plug-in control cards, each in the form of a p.c.b. with a rear-edge connector. The diagram alongside the problem shows the setup. Let the resistance of each 50 mm of p.c.b. track be R. The voltage drop along one track is a maximum of 25 mV (25 mV in the 5 V rail, and 25 mV in the 0 V return). This is made up of four voltage drops across four 50mm lengths of conductor carrying 2 A, 1.5 A, 1 A and 0.5 A (the current decreases at each card, as 0.5 A is drawn off by the card). Thus: 25 mV = R × 2 A + R × 1.5 A + R × 1 A + R × 0.5 A = R × 5 A Therefore, R = 5 m by solving for R. Now we can solve for the cross-sectional area of track using A = ρl/R where l is the length of track, and the other terms are as in Problem 2.1. Substituting the numerical values: A=

1.7 × 10−8 m × 0.05 m = 1.7 × 10−7 m2 5 × 10−3 

Dividing this result for the cross-sectional area by the track thickness (35µm), we obtain the required width: 1.7 × 10−7 m2 /35 × 10−6 = 4.86 × 10−3 = 4.9 mm. Note that the final answer is expressed in millimetres and rounded (in fact it could be rounded to 5 mm in practice).

Chapter 3: Integrated circuits There are no exercises in this chapter.

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Problem 3.1 An approximate calculation is all that is needed here. 106 = 1000 × 1000, therefore laying out transistors in 1000 rows and 1000 columns, at 2 mm by 3 mm per transistor, we would need a p.c.b. 2 m by 3 m with an area of 6 m2 . The second calculation should not be calculated from scratch, of course. Since the number of transistors is 150 times that in the 1987 chip, all we need to do is scale up the answer above: 150 × 6 = 900 m2 . This area is the area of a square which is 30 m on a side. The point of this calculation could be discussed in class: miniaturization is an important aspect of IC technology and this calculation shows that a modern processor chip if implemented in discrete transistors would require a very large area of printed-circuit board indeed. Problem 3.2 The time period involved is 20 years to a good enough approximation. Dividing this by 1.5 (i.e. 18 months), there are about 13 doublings. (An important aspect of these calculations is to be able to make reasonable approximations, since the calculation of an exact answer from approximate data is rather pointless.) So: 213 = 8192, or approximately 8000. Therefore we might expect 8 × 109 or 8000 million transistors per chip in 2006. The actual number of transistors is around 2 × 108 , which is somewhat less. Discussion of the discrepancy might cover: (a) the difference made by assuming a doubling time of slightly more than 18 months; (b) technical factors which have lengthened the doubling time.

Chapter 4: Power sources and power supplies Exercise 4.1 The point of this exercise is to show that a fairly large capacitance is required to store the required charge even for a fraction of a second of operation. The calculation is as follows: 4 W/5 V = 0.8 A. This current, if sustained for 0.125 s gives a charge of 0.8 × 0.125 = 0.1 C. Using the formula Q = C V for the charge stored in a capacitor of capacitance C at a voltage V , and assuming 1 th of the charge stored in the capacitor is used to maintain the 0.8 A current (an that for a voltage drop of 0.1 V, 50 approximation, but good enough for this calculation), then we need the capacitor to hold a total charge of 5 coulombs (0.1 C times 50). Hence Q is 5 C and V is 5 V, therefore the capacitance required is 1 F. A useful supplementary exercise would be to look up data sheets for a 1 F capacitor with a rating of 6 V, particularly to check the physical dimensions. Problem 4.1 This is an approximate calculation, with assumptions that could be discussed. The calculation is as follows. The nominal capacity of the cell is 4 Ah × 1.25 V = 4 A × 3600 s × 1.25 V = 18 000 J. We now need to estimate the total energy supplied by the charging current over 12 hours. If we assume a cell voltage slightly less than the nominal voltage (e.g. 1.2 V), then the total energy supplied is 0.5 A × 12 h × 3600 s × 1.2 V ≈ 25 900 J. Taking the difference, we get about 8000 J, which over 12 hours, is 8000/(12 × 3600) ≈ 200 mW. Note that the assumptions in this calculation mean that an answer to more than one significant figure would not be reasonable. Problem 4.2 The point of this calculation is that the capacitance is huge. 30 Ah×12 V is 360 Wh, which is 360 Wh× 3600 s = 1.3×106 J (to 2 significant figures, which is sufficient). From the formula for the energy stored in a capacitor: 1 C = 1.3 × 106 / × 122 = 1.3 × 106 /72 ≈ 18 000 F 2 Problem 4.3 This is a discussion problem. Points that should arise from a discussion are that chemical reactions speed-up with increased temperature, and batteries stored at lower temperature will therefore suffer less internal selfdischarge due to chemical reactions. Sunlight will heat a battery, and therefore will also accelerate self-discharge.

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Problem 4.4 This problem should not require a complete new calculation. Students should be encouraged to find a solution without reworking the problem for the new frequency, and if they do rework the problem, they should be told that there is a much simpler method, which is this: the capacitor value is simply one eighth of that required at 50 Hz (400/50 = 8) because a cycle of the 400 Hz waveform is one eighth as long as a cycle of the 50 Hz waveform. The peak rectifier current is unchanged. This is harder to see but since the greatest rate of change of voltage is increased by a factor of 8 and the capacitor value is reduced by a factor of 8, there is no change in the peak rectifier current. Problem 4.5 (a) The maximum discharge rate is C/8 (easy, from the definition of the C rate). (b) The charging time is 16 hours (24 minus 8), and therefore the charging rate would be C/16 if all the energy supplied during charging were to be absorbed. The assumption stated is that only 2/3 of the energy is absorbed so a higher charging rate of 32 × C/16 is needed or 3C/32. Problem 4.6 (a) The power delivered to the load at maximum load current is 63 mA × 3.3 V = 210 mW. The power drawn from the source is 68 mA × 5 V = 340 mW. Dividing the former by the latter gives 62% efficiency. (b) At a load current of 5 mA, the power delivered to the load is 5 mA × 3.3 V = 17 mW and the power drawn from the source is the same (the unused load current now passes through the Zener diode), giving an efficiency of 17/340 or about 5%. Problem 4.7 The presence of the transistor means that the Zener diode current is constant at 5 mA. (a) For a load current of 63 mA as in the previous problem, the power supplied to the load is the same, and the power drawn from the source is the same (63 mA + 5 mA), therefore the efficiency is the same, without needing to perform the calculation. (b) For a load current of 5 mA the total current drawn from the source is now only 10 mA, since the transistor base current is to be neglected. Therefore the power drawn from the source is 10 mA × 5 V = 50 mW and the efficiency is therefore about 17/50 or about 35%. This is, of course, much higher than for the circuit in Problem 4.6 and the reason is that less power is wasted in the Zener diode at low load currents.

Chapter 5: Passive electronic components Exercise 5.1 This exercise is designed to stimulate thinking about non-ideal behaviour in the circuit. The ramp waveform must be good, and it should be clear that to obtain a ramp waveform that started from 0 V without some deviation from ideal would be very difficult. Possible reasons are that the FET switch does not switch ideally from conduction to non-conduction, that the capacitor is not perfectly discharged because the FET cannot be perfectly conducting while ‘on’ etc. Therefore, since it is hard to make the ramp waveform ideal at the start, the circuit is designed to start the ramp slightly below 0 V, and a comparator is used to detect when the ramp waveform passes 0 V, the assumption being that the ramp waveform by this point is fairly close to ideal. Exercise 5.2 The worst case values at 20o C, as in Worked Example 5.1, are 1.05 and 0.95. Using a negative temperature coefficient, at 0o C, the deviation from nominal value will be −20o C × (−200 ppm/o C) = +4000 ppm, giving a maximum resistance of 1.05 × (1 + 4000/106 ) = 1.054 or a deviation of 5.4%. At 70o C, the deviation from nominal value will be 50o C×(−200 ppm/o C) = −10 000 ppm, giving a minimum resistance of 0.95×(1−10 000/106 ) = 0.94 or -6%. Exercise 5.3 The inductance value is 90 nH. The inductive reactance of an inductor is given by jωL, but here we are interested in the modulus only, so ωL will suffice. Remembering the factor of 2π, we can consider a unit resistance (i.e. 1 ) and obtain the other results by scaling. Therefore we need to find the frequency f at which 2π f L equals 1. Hence f = 1/2π L = 1/2π90 × 10−9 = 1.8 × 106 Hz. For higher resistance values, this result can be scaled up, hence we get the answers as given of 18 MHz, 1.8 GHz etc.

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Exercise 5.4 The assumption here is that the sheets of mica are stacked as interleaved plates of a capacitor as shown in the marginal sketch. Using the formula given at the start of the section, C = 0 r A/d and substituting the values, remembering a factor of 10 to allow for the stacking (effectively 10 parallel capacitors), we get: C = 10 × 9 × 10−12 F/m × 6 × (30 × 10−3 m2 )2 /25 × 10−6 m = 20 × 10−9 F, or 20 nF. Exercise 5.5 This is a discussion exercise. Real capacitors depart from the ideal behaviour of a capacitance. In this case, the electrolytic capacitor, although it has a high capacitance, will not have a low reactance at high frequencies, because of its inherent series inductance (see Fig. 5.4). The ceramic capacitor, on the other hand, has a low capacitance value, but also low series inductance, because of its construction. At higher frequencies therefore it may well have a lower reactance than the much larger electrolytic capacitor. If this were not so, there would indeed be little point in including it in the circuit. Problem 5.1 Let the tolerance at 20o C be T , so that the actual value of each resistor with nominal value R is R(1 ± T ). Now the maximum gain of the amplifier will be given by: !    1 + 50 × 10−6 × 20 1.01 R2 1 + T G max = R1 1 − T 0.99 1 − 50 × 10−6 × 20 where R2 and R1 are the nominal values of the two resistors, the next term allows for the tolerances, the next for the temperature coefficients and the last for the stabilities, in each case the numerator giving the worst case maximum value, and the denonimator the worst case minimum value. (It is assumed here that both resistors have positive temperature coefficients as this gives the maximum gain.) Evaluating the numerical value of the rightmost two terms, and preserving as many significant figures as possible:   R2 1 + T G max = 1.022244467 R1 1 − T The maximum gain G max must be less than 1.025 RR21 . Hence, we must have: 1+T = X < 1.025/1.022244467 = 1.002695571 1−T Some simple algebra gives us T < (X − 1)/(X + 1), from which T < 1.35 × 10−3 . Thus the tolerance must be less than 0.13%, suggesting that we should choose 0.1% tolerance resistors. The minimum gain G min is the reciprocal of G max and a similar calculation shows that G min must be greater than 0.975 RR21 , leading to a value for T of less than 0.16%. Hence the choice of 0.1% tolerance resistors is satisfactory for this case. Students should be encouraged to verify that the chosen 0.1% tolerance does indeed give a gain within the specified limits – the result is as follows: !    1 + 50 × 10−6 .20 1.01 R2 R2 1.001 G max = = 1.0243 R1 0.999 0.99 R1 1 − 50 × 10−6 .20 which is within the 2.5% tolerance permitted. The minimum gain is the reciprocal of this result, and is again within the tolerance permitted. Problem 5.2 Equating the magnitude of the shunt reactance with ten times the resistance we get: 1 = 10 × R 2π f C Hence C = C=

1 π

1 20π f R .

Using the values given, f = 50 × 106 and R = 1000, we get C =

pF. Now 1/π ≈ 0.3, so the shunt capacitance must be less than about 0.3 pF. 5

1 20π50×109

=

1 π×1012

or

√ Problem 5.3 Use the formula in equation 5.4: vr ms = 4kT R B, where k = 1.38 × 10−23 JK−1 . Substituting this √ and the other numeric values: vr ms = 4 × 1.38 × 10−23 × 300 × 1012 × 104 = 13 mV. Practical capacitors are not noisy because this leakage resistance is in parallel with the capacitance. (Imagine the equivalent circuit to be a noiseless resistor in series with the noise source, shunted by the capacitance, and it is clear that the capacitance will shunt the noise. Equivalently, the noise source is coupled to an RC low-pass filter.)

Chapter 6: Instruments and measurement Exercise 6.1 This is a simple exercise in using Ohm’s Law, plus the fact that two resistances in series add. When the voltmeter is at f.s.d. the voltage across the series resistor and coil combination must be 1 V and the current passing through the resistor and coil must be 1 mA in order to deflect the meter to full scale. Therefore the total resistance must be 1 k. Subtracting the 75  resistance of the coil, the required resistor value is 925 . Problem 6.1 (a) The current must divide in the ratio 1:99 between the coil and the shunt resistor. (The idea of a current divider is sometimes less familiar to students than the idea of voltage division using a potential divider, but they should be encouraged to think in this way rather than reasoning out the answer by a longer method.) Thus the shunt resistor must have a value of R = 75 99  or 0.76  to 2 significant figures. (b) The two worst cases are when the coil and resistor have values at the opposite extremes of their tolerance range. The ratio of the currents in these two cases is: 75 99

× 0.99 = 0.0099 75 × 1.01 75 99

× 1.01 = 0.0103 75 × 0.99 Thus the current passing through the meter coil will be 99 mA or 103 mA, representing an error of -1% or +3%. Whether these errors are significant is a discussion point. A precision ammeter would not have an error as large as 3%, but a 1% error is probably acceptable. For comparison (and students should think of researching this themselves or be encouraged to do so) the Avometer Model 8 Mark 7 illustrated in Figure 6.5 is accurate to ±1% f.s.d. on d.c. ranges, rather less on a.c. Problem 6.2 This is a simple calculation using a potential divider. In the sketch below, the point P is indicated. To the left is the Th´evenin equivalent circuit being measured with resistance R and open-circuit voltage V . The resistance Rin on the right represents the input resistance of the oscilloscope (with or without the 10× probe). R  V

Pr 6 Vp



Ri

r Now, from the potential divider formula: Vp Rin = V R + Rin and this voltage ratio must be no less than 0.98 (for a 2% error). Taking 0.98 (worst case value) and solving for R, we get R = Rin (1 − 0.98)/0.98 = 2Rin /98. Calculating the value of R for each of the two values of Rin , we get: (a) Rin = 107  × 2/98 = 204 k (b) Rin = 106  × 2/98 = 20.4 k

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Chapter 7: Heat management Exercise 7.1 The required formula is R = l/k A where R is the thermal resistance in o C W−1 , l is the length of the bar (metres) and A is the cross-sectional area (m2 ), and k is the thermal conductivity (given in the text). This formula can be deduced from a simple dimensional analysis. The heat loss from the sides of the bar has to be ignored in order to simplify the exercise. Substituting the values given: R = 0.1/(170 × (0.01)2 ) ≈ 5.9o C W−1 Given the simplifying assumption made here, it makes sense to quote this as 6o C W−1 . Exercise 7.2 Use equation 7.5: θJ − θA = P(RJ-C + RC-S + RS-A ) and substitute the values on the right: P = 25 W, RJ-C = 1.7o C W−1 , RC-S = 0.3o C W−1 , and RS-A = 1.5o C W−1 . This gives a value on the right of 87.5o C. Adding the ambient temperature (θA = 25o C) gives a junction temperature of 112.5o C. Given the inherent approximations in this sort of calculation, it is more sensible to express this as 113o C (in fact the result is not likely to be accurate to within one degree). Exercise 7.3 Use equation 7.5 again, but re-arrange the equation to make RS-A the subject, and substitute the numerical values given: RS-A =

150o C − 50o C θJ − θA − (RJ-C + RC-S ) = − (1.5o C W−1 + 0.3Co W−1 ) = 2.2o C W−1 P 25 W

Problem 7.1 The thermal resistance junction-to-sink, per transistor, is 1.9o C W−1 (from adding the thermal resistance of the transistor to the thermal resistance of the mica washer and silicone grease). From the power dissipation, per transistor, and this thermal resistance, we can work out the temperature difference junction-to-sink: 1θJ-S = 15 W × 1.9o C W−1 = 28.5o C We are permitted a junction temperature 60o C above ambient, so, subtracting this result, we can allow no more than a temperature difference between heat sink and ambient of 31.5o C. (What we mean here of course, is the temperature difference between the part of the heat sink immediately under the mica washer and ambient, as this will be the hottest part). Remembering that we have two transistors, and therefore 30 W to dissipate, we can calculate the maximum thermal resistance of the heatsink as: 31.5o C RS-A = = 1o C W−1 30 W Problem 7.2 From the power dissipation derating curve, we can calculate the thermal resistance of the transistor package: it is the reciprocal of the slope of the derating curve. Therefore RJ-C = 1/20 mWo C−1 = 50o C W−1 . (a) The temperature of the transistor case can be represented by the equation: θC = 48o C W−1 × P + 25o C, where P is the power dissipation. The power dissipation allowed, from the derating curve, can be represented by the equation P = −0.02 × θC + 3.5 valid over the range of case temperatures 25o C − 175o C. (This latter equation requires the intercept on the y-axis to be computed, which is 3.5 W by the simple calculation of −0.02 × −25.) Substituting the first equation into the second, we get: P = −0.02(48P + 25) + 3.5 = −0.02 × 48P − 0.02 × 25 + 3.5 = −0.96P + 3 Hence P = 3/1.96 = 1.53 W. (b) This is simply computed from the thermal resistance of the dissipator and the power dissipation: 1.2 W × 48o C W−1 + 25o C = 82.6o C.

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Problem 7.3 From Worked Example 7.3, the volumetric flow rate in cubic metres per hour is: 3600P ρcθ Substituting the values given in the Problem, (the temperature difference permitted is 20o C) we get: 3600 × 150 = 20.8 m3 hour−1 1.3 × 1000 × 20 which should be rounded to 21 m3 hour−1 (the calculation cannot be accurate to 3 significant figures).

Chapter 8: Parasitic electrical and electromagnetic effects Exercise 8.1 (a)√Neglecting any loss in the cable, and therefore assuming R and G to be zero, the characteristic impedance, Z 0 = L/C, so L = Z 02 C, which gives 502 × 100 × 10−12 = 2.5 × 10−7 or 250 nH m−1 . √ (b) The propagation velocity is given by equation 8.4, therefore v = 1/ 2.5 × 10−7 × 100 × 10−12 = 2 × 108 ms−1 which is 200 mm ns−1 . (c) From equation 8.4, r = LCc2 = 2.5 × 10−7 × 100 × 10−12 × (3 × 108 )2 = 2.25. √ √ Exercise 8.2 From equation 8.4, v = c/ r = c/ 6 = 0.41c. Taking c to be 300 mm ns−1 , the velocity will be 300 × 0.41 ≈ 120 mm ns−1 . Exercise 8.3 As the text says, the exercise is a practical one. It is relatively simple to obtain oscilloscope waveforms as shown in the figure. The pulse generator must have a 50 output as stated in order to be matched to the cable. If this is not the case, reflected pulses arriving back at the pulse generator output will be reflected again and will cause confused waveforms. The oscilloscope should be triggered from a trigger output on the pulse generator if possible, as shown in the marginal sketch. Exercise 8.4 This is a discussion point designed to get students to think about the practical problem of leakage current. The important point to consider is not in fact whether there should be a solder resist coating on the PCB, but whether this coating, if present, should cover the guard ring or any of the PCB area near the guard ring. Considering the guard ring itself, this is conductive, so coating it with solder resist (which will have a high but not infinite resistance) will not have an adverse effect on the guard ring itself, since the leakage resistance of the solder resist coating is in parallel with the very low resistance of the copper making up the ring. Considering the insulated area of PCB inside the guard ring, solder resist may increase the leakage compared to a dry PCB laminate, but on the other hand, the solder resist may reduce moisture absorption, so compared to non-dry laminate the solder resist covered board might have a higher leakage resistance. The question is therefore not simple. Exercise 8.5 This is a straightforward exercise in algebra. The current through the device will be: I = k(V1 sin ω1 t + V2 sin ω2 t)2 Squaring the voltage term, we get: I = k(V12 sin2 ω1 t + V22 sin2 ω2 t + 2V1 V2 sin ω1 t sin ω2 t) and it is the third term inside the brackets that has the components at sum and difference frequencies. (Some students may need to be reminded that sin2 ω1 t has the same frequency as sin ω1 t.) The trigonometric formula needed is sin A sin B = − 12 (cos(A + B) − cos(A − B)).

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Exercise 8.6 The formula for the capacitance of a parallel plate capacitor is given in Chapter 5, Equation 5.5: C = 0 r A/d The dimensions given must be converted into metres, of course: C = 9 pF m−1 × 6 × 0.233 m × 0.16 m/0.3 × 10−3 m = 6.7 × 10−9 ≈ 7 nF Comment: this is a rather small capacitance for decoupling purposes, and, distributed as it is over the area of the board, it will have very little decoupling effect. Typical capacitor values for decoupling are in the region of 10–100 nF and a board of this size would have one capacitor per two ICs if the board contained TTL logic, rather less in the case of CMOS logic. Problem 8.1 This modelling is not valid for steady currents, of course! Consider the equivalent circuit as described, open circuit. The output will be 2Vi (t), thus modelling voltage doubling at an open-circuit. When connected to an impedance Z 0 , the voltage observed at the output of the equivalent circuit will be Vi (t), and if short-circuited, the output voltage will be zero. Problem 8.2 (a) In order for a lumped-parameter circuit model to be valid, we must have T < d/c (Equation 8.2). Here we have T < 100 mm/150 mm ns−1 , or T < 0.67 ns. The reciprocal of T is 1.5 GHz. (b) From Equation 8.1: 50 4 |vi | = q 1 Vp π 104 + 10−12 ×2π×10−7 ×n

where n is the harmonic number. Tabulating this ratio for each of the odd harmonics from 1 to 9 and using 20 log10 to express the voltage ratio in dB: |vi | Vp

n 1 3 5 7 9

0.004 12 × 10−3 20 × 10−3 28 × 10−3 35.9 × 10−3

|vi | Vp

dB -48 -38 -34 -31 -29

Problem 8.3 (a) This requires the solution of a simple pair of simultaneous equations. The two resistors must act as a voltage divider to give the open-circuit voltage of 3 V. This requires: R2 3 = R1 + R2 5 The other equation is the impedance: the parallel combination of the two resistors must have a value of 120. (This is because the dynamic impedance of the potential divider is obtained by the parallel combination of the two resistors, the power supply offering negligible dynamic impedance between the +5 V and 0 V rails.) This requires: R1 R2 = 120 R1 + R2 Dividing the second equation by the first we solve for R1 : R1 R2 R1 +R2 R2 R1 +R2

=

120 3 5

5 =⇒ R1 = 120 ×  = 200 3

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The simplest way to obtain the value of R2 is to observe that the values of the two resistors must be in the ratio 2:3 because of the voltages across them, thus R2 = 300, but this can also be obtained by substituting the value of R1 into either of the equations, and solving for R2 . √ √ (b) From Equation 8.4, the propagation velocity is given by c/ r = 3 × 108 / 6 = 1.2 × 108 ms−1 or about 120 mm ns−1 . The propagation delay from end to end of the bus is thus 3000/120 or 25 ns. Doubling this to allow for the acknowledgement gives 50 ns, and the reciprocal gives a data rate of 20 × 106 data items per second. Problem 8.4 (a) The instantaneous current demand per gate is 3 V/120 = 25 mA. Multiplying by 8, we get 200 mA. (b) We must double the distance to the power supply, because the signal must propagate from the bus buffer IC to the PSU and back, so the local capacitor must supply the current demand for 600 mm/200 mm ns−1 = 3 ns. The charge that has to be supplied is the current multiplied by this time, hence q = 200 mA×3 ns = 6×10−10 C. Dividing this by the change in voltage gives: 6 × 10−10 C/50 mV = 12 nF. (c) This is optimistic because it assumes the charge can be extracted instantly from the power-supply reservoir capacitor(s), which is not true, since they will have some parasitic inductance which will inhibit the sudden movement of charge.

Chapter 9: Reliability and maintainability Exercise 9.1 This is a trivial calculation, using Equation 9.2. Students should be encouraged to use the statistics functions on a calculator to enter the values given and then calculate the mean, rather than doing the whole operation manually. Exercise 9.2 This requires some knowledge of mathematical concepts such as proof by contradiction. In what follows, the argument is that if the slope was positive then a certain result would obtain which is demonstrably not possible: If the slope of R(t) > 0 then there exist t1 and t2 such that R(t1 ) > R(t2 ), t2 > t1 . This says that there is a higher probability of functioning without failure over the longer time interval t2 than the time interval t1 which is clearly invalid. Exercise 9.3 (This exercise requires knowledge of differential calculus.) From Equation 9.10: λ(t) = From the expression R(t) = exp(−kt), we have 9.10 we have: λ(t) =

dR(t) dt

−1 dR(t) R(t) dt

= −k exp(−kt) and substituting these expressions into Equation

−1 [−k exp(−kt)] = k exp(−kt)

Exercise 9.4 No solution required, as this is a simple exercise in plotting data. Exercise 9.5 This is a simple exercise, but it may take students a while to think of the solution. The overall reliability is the product of the individual reliabilities. The solution is to consider all components other than the least reliable component to be perfect, that is to have a reliability of 1. The system will then have an overall reliability equal to that of the least reliable component. Now, if any one of the other components is less than perfect, its reliability will be less than 1, and the overall system reliability will be reduced below that of the least reliable component. Therefore the overall reliability cannot be greater than the reliability of the least reliable component.

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Exercise 9.6 This is a simple exercise in algebra, but it is easy to make errors with signs. 1 − Fm3 − 3Fm2 Rm = 1 − Fm (Fm2 + 3Fm Rm ) and substituting Fm = 1 − Rm , we have: 1 − Fm (Fm2 + 3Fm Rm ) = 1 − (1 − Rm )((1 − Rm )2 + 3(1 − Rm )Rm ) 2 2 = 1 − (1 − Rm )(1 − 2Rm + Rm + 3Rm − 3Rm ) 2 = 1 − (1 − Rm )(1 + Rm − 2Rm ) 2 2 3 = 1 − (1 + Rm − 2Rm − Rm − Rm + 2Rm ) 2 3 = 1 − (1 − 3Rm + 2Rm ) 2 3 = 3Rm − 2Rm

Problem 9.1 (a) The availability is the fraction of time for which the system is operational. The number of hours in 6 months is 8760/2 = 4380. Subtracting the number of hours for which the system was ‘down’, which is 1 + 2 + 1.5 + 2 + 2 × 2 = 10.5 hours. The availability is therefore (4380 − 10.5)/4380 = 99.76% (b) The MTBF is simply the mean time between failures. There were four failures during the period, thus the MTBF is 4380/4 or about 1100 hours. (It is not necessary to calculate this accurately, since the concept is an approximation, and we can ignore the preventative maintenance time.) Problem 9.2 (a) Constant failure rate means that R(t) = exp(−kt) (Exercise 9.3). Setting t = 8760 × 2 (the number of hours in 2 years) we have: ln 0.8 = 1.27 × 10−5 hour−1 k= −8760 × 2 and the MTBF is the reciprocal of the failure rate, thus MTBF = 1/1.27 × 10−5 ≈ 79, 000 hours. (b) An MTBF of 50,000 hours corresponds to a failure rate of 2 × 10−5 hour−1 . Assuming constant failure rate, as in (a), R = exp(−2 × 10−5 × 8760 × 2) = 0.7044. The probability of failure F, within two years is 1 − R = 0.2955. Placing two of these power supplies in parallel, so that we have a redundant system (both must fail for the combination to be a failure), the probability of a double failure is F 2 = 0.29552 = 0.0874, giving an overall reliability of 1 − 0.0874 = 0.9126. We require an overall reliability of 0.8 taking the diodes into account, hence the diodes must have a reliability of 0.8/0.9126 = 0.8766 or approximately 0.88. Problem 9.3 The failure rates of the measuring channels are λm = 1/100, 000 = 10−5 hour−1 , and of the power supply λpsu = 1/150, 000 = 6.67 × 10−6 hour−1 . The probability of system failure is the probability that both measurement channels or the power supply have failed, and this is given by P = (1 − Fm × Fm )Rpsu , where Fm is the value of the lifetime distribution function for a measurement channel after 5 years, and Rpsu is the reliability of the power supply after 5 years. The reliability Rm of each measurement channel after 5 years is Rm = exp(−10−5 × 8760 × 5) = 0.6453, hence Fm = 0.3547. (A constant failure rate is assumed.) The reliability Rpsu of the power supply after 5 years is Rpsu = exp(−6.67×10−6 ×8760×5) = 0.7468. Thus the system reliability is R = (1−0.35472 )×0.7468 = 0.6528 or 0.65 or 65%. Problem 9.4 λ =

1 MTBF

= 10−5 hour−1 . We require 0.75 = exp(−λt) and we have to solve for t. Thus t=

ln 0.75 = 28, 768 hours −10−5

Dividing this by 8760, this represents about 3.3 years.

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Chapter 10: Environmental factors and testing Exercise 10.1 TTL logic is implemented with bipolar transistors, whereas CMOS logic is implemented with MOSFETs. Bipolar transistors have parameters, particularly β which are temperature dependent, and this is the most likely reason for the limited temperature range. However, TTL logic was available with a wider temperature range (see the 5400 series manufactured by Texas Instruments) which presumably had more complex circuitry (perhaps with compensating components) to give the wider operating temperature range (it is difficult to be sure because the 5400 series no longer seems to be available and access to data books and design guides is not easy). Exercise 10.2 From Equation 10.2, we can express the activation energy, E, in terms of the other parameters: E=

k ln λλ21 1 T1

−

1 T2



and substituting the numerical values (remembering to convert from Celsius to Kelvin temperatures) we have: E=

1.38 × 10−23 ln 120000 6000   = 1.03 × 10−19 J = 0.64 eV 1 1 273+40 − 273+85

To find the lifetime at 100o C we can use Equation 10.2 directly to find the ratio of lifetimes between 40o C and 100o C, and then use this ratio to scale the known lifetime at 40o C:  ! λ100 1.03 × 10−19 1 1 = exp − = 46.3 λ40 1.38 × 10−23 273 + 40 373 Therefore, dividing the lifetime at 40o C by this ratio, we get 120000/46.3 hours or about 2600 hours. Exercise 10.3 The RAM lining is shaped into cones in order to minimise the amount of reflected radio-frequency energy. If the RAM consisted of flat sheets, an impinging EM wave would hit an impedance discontinuity, and some of the radio-frequency energy would be reflected. The cone shape means that the impedance mismatch is gradual, and less energy is reflected. An analogy can be drawn here with the transmission line reflection effects discussed in Chapter 8. Problem 10.1 Use Equation 10.2 and find the activation energy, E (see the solution to Exercise 10.2 above where Equation 10.2 is rearranged to solve for E:   2×10−5 1.38 × 10−23 ln 8×10 −6   E= = 5.8 × 10−20 J 1 1 273+20 − 273+40 We now need to find the constant K in the Arrhenius equation (Equation 10.1). Rearranging the Arrhenius equation to solve for K we get: ! 5.8 × 10−20 −6 K = λ exp(E/kT ) = 8 × 10 exp = 13.6 1.38 × 10−23 × 293 (Notice that we get the same result using the lifetime at 40o C.) To obtain the required lifetimes at the two temperatures given we need only substitute the values into the Arrhenius equation: ! −5.8 × 10−20 (a) λ10 = 13.6 exp = 4.8 × 10−6 1.38 × 10−23 × 283 ! −5.8 × 10−20 (b) λ60 = 13.6 exp = 4.5 × 10−5 1.38 × 10−23 × 333

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Problem 10.2 (a) 1/6 × 10−9 = 1.67 × 108 hours, or dividing by 8760, about 19,000 years. We next need to find the constant K in the Arrhenius equation as in the previous Problem. Here we also have to convert eV into joules. ! −19 0.25 × 1.6 × 10 = 1.2 × 10−4 K = λ exp(E/kT ) = 6 × 10−9 exp 1.38 × 10−23 × 293 Now we can solve the Arrhenius equation for each of the temperatures given, to obtain the lifetimes: ! −0.25 × 1.6 × 10−19 −4 λ0 = 1.2 × 10 exp = 2.9 × 10−9 1.38 × 10−23 × 273 ! −0.25 × 1.6 × 10−19 −4 λ70 = 1.2 × 10 exp = 2.6 × 10−8 1.38 × 10−23 × 343 Taking the reciprocals of these lifetimes, we get (a) about 39,000 years, and (b) 4500 years (remembering to divide by 8760 to get the result in years, and rounding the result to 2 significant figures). Note that these MTTF figures are so long that they are questionable, as there may be many effects that are not properly modelled over such long time scales.

Chapter 11: Safety There are no exercises or problems in this chapter.

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