Digital Principles and Circuits [1 ed.] 9789350433195, 9788183184861

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DIGITAL PRINCIPLES AND CIRCUITS

Dr. C.B:AGARWAL, Ph. D. Former Reader and Head Department of Physics D.S. College, Aligarh, India Member, New York Academy of Sciences, U.S.A.

mal GJiimalaya GJlublishingGHouse MUMBAI • DELHI • NAG PUR • BANGALORE • HYDERABAD

© No part of this book shall be reproduced, reprinted or translated for any purpose whatsoever without prior permission ofthe publisher in writing.

ISBN: 97 8-81-83184-86-1 FIRST EDITION

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JUNE 2006

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CONTENTS Chapter 1 DIGITAL CONCEPTS

1-33

1.1 Analog vs Digital 12 Advantages of digital technology 1.3 Digital numbers 1.4 BCD vs Binary 1.5 Signal numbers and complements 1.6 Voltage representation of bits 1.7 Voltage levels and logic levels 1.8 Digital circuits vs logic circuits 1.9 Basic logic operations 1.10 Logic gate symbols 1.11 Active-low and active-high levels 1.12Multi-gate symbols 1.13 Timing diagrams 1.14 Serial and parallel transmission 1.15BJT 1.16 UJT 1.17 FET 1.18 MOSFET 1.19 Depletion MOSFET 1.20 Enhancement MOSFET 1.21 FAMOS 1.22 Basic MOSFET switch 1.23 Integrated circuits 1.24 Advantages and limitations of ICs 1.25 Classification of ICs 1.26 Construction of monolithic ICs 1.27 Fabrication of Components and circuits-diode, transistor, resistor, given circuit 1.28 MOS ICs 1.29 IC packages-24-pin DIP surface mount package, J-Iead surface-mount package 1.30 Computer memory 1.31 DigItal computer organisation 1.32 Data bussing 1.33 Microcomputer 1.34 Microprocessor.

Chapter 2 NUMBER SYSTEMS

34-70

2.1 Introduction 2.2 Decimal-number system-counting, maximum counts, disadvantages 2.3 Binary number system - binary formats, counting, maximum counts 2.4 Binary-to-decimal conversion 2.5 Decimal-to-binary conversion 2.6 Octal number system-counting, maximum counts 2.7 Binary-to-octal conversion 2.8 Octal-to-binary conversion 2.9 Octal-to-decimal conversion 2.10 Decimal-to-octal conversion 211 Hexadecimal number system 2.12 Binary-tohexadecimal conversion 2.13 Hexadecimal-to-binary conversion 2.14 Hexadecimal-to-decimal conversion 2.15 Decimal-to-hexadecimal conversion 2.16 Interconversion made easy 2.17 Comparison of number systems 2.18 Signed-number systems 2.19 Sign-magnitude system 2.20 I's Complement system-Obtaining 1's complement, Representing signed numbers in 1's Complement system 2.21 2's Complement system - other method, negation, remembering 2's complementation 2.22 9's Complement and 10's Complement systems 2.23 Binary addition 2.24 Binary subtraction 2.25 Binary multiplication 2.26 Binary division 2.27 Octal addition 2.28 Octal subtraction 2.29 Octal multiplication and division 2.30 Hex addition 2.31 Hex subtraction 2.32 Hex multiplication and division 2.33 2's Complement addition 2.34 2's Complement subtraction - minuend > subtrahend, minuend < subtrahend 2.35 2's Complement multiplication 2.36 2's Complement division 2.37 l's Complement addition and subtraction 2.38 l's complement multiplication and division 2.39 Summary. Problems Objective questions and Answers

Chapter 3 BINARY CODES

71-93

3.1 Introduction 3.2 Straight binary code 3.3 BCD (8421) code-natural BCD, disadvantages, Characteristics 3.4 Excess-3 Code-decodfng, self-complementing, addition, characteristics 3.5 Other BCD Codes 3.6 Gray Code 3.7 Binary-to-gray conversion 3.8 Gray-to-binary conversion 3.9 Code comparison 3.10 Error-detecting parity Codes-parity bit, code formation, Single-parity check, Double-parity check 3.11 Higher BCD Codes 312 51111 Code 313 543210

Code 3.14 5043210 (Biquinary Code) 315 9876543210 (Ring Counter) Code (alphameric) Code 3.17 6-Bit Internal Code 3.18 8-bit EBCDIC Code 3.20 Summary. Problems Objective questions and Answers

Chapter 4 LOGIC GATES AND IC FAMILIES

3.16 Alphanumeric 3.19 ASCII Code

94-157

4.1 Introdu .tion 42 AND gate 4.3 Diode AND gate 4.4 Transistor AND gate 4.5 OR gate 4.6 Diode OR gate 4.7 Transistor OR gate 4.8 Disadvantages of diode gates 4.9 Multi-inputs (Fan-in) 4.10 NOT gate (INVERTER)-complementation, double inversion, IC invertors 4.11 Loading effect (Fan-out)-buffer/driver 4.12 Representation of binary numbers as electrical signals-Positive and negative logic in dc and ac systems 4.13 Positive and negative gates 4.14 NAND gate-NAND as INVERTER 4.15 NOR gate-NOR as INVERTER 4.16 Bubbled gates-significance, bubbled NAN:Q bubbled NOR 4.17 NAND and NOR as universal gates-AND, OR, NOT realisation 4.18 xORand XNOR gates 4.19 Concise account of logic gates 420 Digital rcs 4.21 Levels of integration 4.22 Digital IC (logic) families-Bipolar families, MOS families 4.23 Characteristics of digital ICs-voltage and current parameters, Noise immunity, speed/propagation delay, power dissipation, fan in! Fan-out, Operating temperature. 4.24 DTL AND gate 4.25 DTL NAND gate 4.26 DTL NAND gate with load-circuit analysis, current sinking, noise, wired-AND connection 4.27 RTL NOR gate-current sourcing, RTL characteristics 4.28 TTL 4.29 TTL basic NAND gate 4.30 Standard TTL NAND gate with totempole output-low-state operation, high-state operation, loading considerations, output circuits, totem pole output, open collector output, tristate output, wired-ANDing 4.31 TTL series 7400 and 5400-high speed TTL, low power TTL, Schottky TTL, Low power Schottky TTL, Advanced Schottky TTL, Advanced low-power Schottkey TTL, Fast TTL 4.32 DCTL NOR gate-high and low state operations, disadvantages 4.33 ECL 4.34 ECL basic circuit 4.35 ECL OR/NOR gate-circuit operation, wired-O R connection, characteristics 4.36 J2 L NOR gate-current injector, circuit operation 4.37 Tristate logic 4.37 Tristate buffers-inverting and non-inverting tristate buffers 4.39 MOS-Iogic familiesNMOS INVERTER, CMOS INVERTER 4.40 Dynamic MOS INVERTER-Rationed dynamic INVERTER, Ratio less dynamic INVERTER 4.41 NMOS-NAND and NMOS-NOR gates 4.42 CMOS-NAND and CMOS NOR gates 4.43 CMOS transmission gate 4.44 CMOS series 4.45 MOS logic characteristics 4.46 BiCMOS logic 4.47 Comparison oflogic families 4.48 IC gates 4.49 Summary. Problems Objective questions and Answers

Chapter 5 BOOLEAN ALGEBRA

158-204

5.1 Introduction 52 Basic concepts of Boolean algebra 5.3 Boolean operations 5.4 Laws and theorems of Boolean algebra 5.5 Proof of Boolean Laws 5.6 DeMorgan's theorems 5.7 Proof of DeMorgan's theorems 5.8 Physical Significance of DeMorgan's theorems 5.9 Duality of Boolean algebra 5.10 Evaluation of Boolean expressions 5.11 Sequence of operations 5.12 Synthesis of Boolean expression-SOP and POS standard products and sums 5.13 Canonical expressions with two variables 5.14 Physical significance of SOP and POS 5.15 Three-variable canonical expression 5.16 Inter conversion of canonical forms 5.17 Other forms of logic expressions 5.18 Simplification of Boolean expression 519 Simplification by algebraic method 5.20 Simplification by Karnaugh map 5.21 Karnaugh map-to obtain simplified SOP and POS 5.22 Summarised procedure of K-map 5.23 Four-variable Karnaugh map 5.24 Don't care conditions 5.25 Code conversion by Karnaugh map-Gray-to-8421 5.26 Five-variable and sixvariable k-maps 5.27 Simplification by Q-M method 5.28 Analysis of logic circuits

5.29 Implementation of Boolean expressions 5.30 NANIYNOR implementation-first approach, second, approach, NAND-NAND gating, NOR-NOR gating 5.31 Summary. Problems Objective questions and Answers

Chapter 6 COMBINATIONAL CIRCUITS

205-259

6.1 Introduction 62 Exclusive OR gate-gate formation, multi-input XOR gate as controlled INVERTER, IC XOR gates 6.3 Exclusive NOR gate 6.4 Half adder 6.5 Full adder-NAND realisation of full adder 6.6 Half-subtractor 6.7 Full subtractor 6.8 Serial and parallel adder 6.9 Parallel adder-carry propagation delary 6.10 IC parallel adder 611 I's complement subtract or 6.12 2's complement adder/subtractor-S-Bit TTL adder/subtractor 6.13 BCD (8421) adder 6.14 Multidigit BCD adder 6.15 Excess-3 adder 616 Arithmetic overflow 617 Parity checker 6.1S Parity generator/checker 6.19 Parity generator/checker 741S0-8-bit parity checker, 9-bit parity generator, 10-bit parity generator, 9-bit parity checker. 6.20 Encoder 6.21 Decimal-to-BCD diode matrix encoder 6.22 Decimal-to-BCD priority encoder 74147 6.23 Octal-to-binary priorityencoder 7414S 6.24 Decoder 6.25 BCD-to-decimal decoder-expansion, 744217445 decoders, decoder! driver 6.26 BCD-to-7-Segment decoder-744617447 decoder!drivers, common anode and common cathode, LED and LCD. 6.27 Binary-to-octal decoder 74138 6.28 Multiplexer-enable input, expansion 6.29 Multiplexer tree 6.30 Word multiplexer 6.31 Demultiplexer 6.32 Demultiplexer tree 6.33 Decoder/Demulti-plexer 6.34 Mux applications 6.35 Digital comparators-I-bit, 2-bit and 4-bit compactors 6.36 Comparator applications 6.37 Serial adder 6.38 Binary-to-gray code converter 6.39 BCD-to-binary code converter 6.40 Other code converters 6.4 Arithmetic logic unit and arithmetic processing unit 6.42 Summary. Problems Objective questions and Answers

Chapter 7 FLIP-FLOPS AND REGISTERS

260-297

7.1 Sequential circuits 7.2 The flip-flop 7.3 Basic flip flop circuit-latch, RS latch 7.4 RS flip flop 7.5 The clock-rise and fall times, propagation delay 7.6 Level-clocking vs edge-triggeringRC circuit 7.7 Edge-detector circuit 7.8 Clocked RS flip-flop 7.9 JK flip-flop 7.10 Master-slave JK flip-flop 7.11 D flip-flop-Ievel triggered, Edge-triggered 712 T flip-flop 7.13 Asynchronous inputs 7.14 Flip-flop timing considerations-setup and hold times, maximum clocking-frequency, Clock-pulse lowlhigh times, asynchronous active pulse width 7.15 Flip-flop implementation 7.15 Flip-flop applications-data storage and transfer, frequency division and counting, denouncer switch. 7.17 IC Timer 555 7.18 IC flip-flops 7.19 Registers-controlled register 7.20 Shift registers 7.21 Serial shift register 7.22 Parallel controlled shift register 7.23 Serial/parallel shift register-SISO, PISO. and bidirectional shifting 7.24 Static and Dynamic shift registers 7.25 IC shift registers 7.26 Shift register applications 7.27 Summary. Problems Objective questions and Answers

Chapter 8 DIGITAL COUNTERS

298-342

8.1 Introduction 82 Basic flip-flop counter-frequency division 8.3 Modulus of a counter 8.4 Asynchronous (ripple) counter 8.5 Mod-8 ripple counter 8.6 Delay aspect of ripple counters 8.7 Ripple counters with modules of N < 27) 8.8 Mod-6 ripple counter 8.9 Asynchronous mod-8 Down counter 8.10 Asynchronous up/down counter 811 Asynchronous mod-l0 (decade) counter 8.12 Presettable asynchronous counter 8.13 Disadvantages of asynchronous counters

8.14 Synchronous counters 8.15 Synchronous mod-16 counter (serial carry) 8.16 Synchronous mod16 counter (parallel carry) 8.17 Synchronous mod-10 counter 8.18 Synchronous up/down counter 8.19 PreseUable synchronous counter 820 Decoding a counter-AND and NAND gate decoders 8.21 Strobing. 8.22 Ring counter 8.23 Twisted-ring counter 8.26 Designing a counter 8.27 IC counters 8.28 Asynchronous IC counters-7490 as divide-by-10, 7490 as divide-by-6, 949217493/ 74293 IC counters, 74176174177174196174197 IC counters, 74390174393174490 IC counters 8.29 Synchronous IC counters-74168174169, 74190174191 and 74192174193 IC counters 8.30 IC shift register counters 8.31 Counter applications 8.32 Digital clock 8.33 Summary Problems Objective questions and Answers

Chapter 9 MEMORY SYSTEMS

343-401

9.1 Introduction 92 Memory terminology 9.3 Basic memory 9.14 Memory organisation 9.5 Magnetic memones-core, drum, disk, tape, bubble memory 9.6 Semiconductor memories 9.7 Classification of semiconductor memones 9.8 Read-only memory 9.9 Maskprogrammed ROM-diode ROM organisation 9.10 Linear andX-Y selection 9.11 Bipolar and MOS ROMs 9.12 PROM 9.13 EPROM 9.14 EEPROM 9.15 Flash memory 9.16 IC ROMs/ PROMs 9.17 ROM applications 9.18 RAM 9.19 Static and dynamic RAMs 9.20 Bipolar static RAM-cell 9.21 Static MOS RAM cell 9.22 Dynamic MOS RAM cell 9.23 DRAM architecture 9.24 SRAM vs DRAM 9.25 IC RAMs 9.26 Capacity expansion-word-size, word capacity 9.27 Ultimate DRAMs-SDRAM, DDR-SDRAM. RDRAM, VRAM, WRAM, SGRAM, NRAM 9.28 CAM 9.29 Shift-register sequential memory 9.30 Dynamic shift-register memory cell 9.31 CCD memory 9.32 Cache memory 9.33 Programmable logic device. 9.34 PROM as PLD 9.35 PAL 9.36 PLA-erasable PLA, capacity expansion, IC PLAs 9.37 FPGA 9.38 Mass-storage devices-floppy disk, floptical, MO disk, mini disk, CD-ROM, DVD-ROM, Hard disk. Flash memory, Plastic memory 9.39 Summary. Problems Objective questions and Answers

Chapter 10 DI A CONVERTERS AND AID CONVERTERS

402-433

10.1 Introduction 10.2 Digital-to-analog converter 10.3 Weighted-resistor D/A converter (voltage) 10.4 Weighted-resister D/A converter (current) 10.5 R-2R ladder D/A converter 10.6 Inverted ladder DAC 10.7 Bipolar DAC-offset circuit 10.8 DAC characteristics 10.9 Monotonicity 10.10 Resolution 10.11 Accuracy-quantization error, offset error 10.12 Settling time 10.13 Compatibility of resolution and accuracy 10.14 Analog output of DAC 10.15 BCD inputs 10.16 Current DAC vs voltage DAC 10.17 IC D/A converters 10.18 Analog-to-digital converters 10.19 Counter-controlled ADC 1020 Successive-approximation ADC, 10.21 Flash ADC 10.22 Dual-slope ADC 10.23 Voltage-to-frequency ADC 10.24 Voltage-to-time ADC 10.25 Sample and hold circuit-acquisition and aperture times 10.26 Summary Problems Objective questions and Answers

APPENDIX A (Pinouts)

434-441

APPENDIX B (List of ICs)

442-444

APPENDIX C (Solutions to Odd-numbered Problems)

445-454

Index

455-461

CHAPTER

1

DIGITAL CONCEPTS Digital electronics is the field in which two-state switching circuits operate with signals in the form of electrical pulses. The inputs and the outputs in these circuits involve only two levels of voltage which are referred to as "low" and "high". The information or data to be processed in a digital system is usually presented in the form of binary strings of Os and Is. Because of many advantages of the digital technology, its use is growingly increasing in the design and development of modern devices. Digital calculators, computers, TV sets, video games, watches, robotes, telecommunication and control systems, and so many others, are the major fields in which digital techniques are extensively applied. Before we go into discussing various specific digital circuits and devices in this book, let us first introduce the reader with some basic concepts of digital techniques in the present Chapter. 1.1 ANALOG vs DIGITAL

There can be two ways-analog and digital, in which a quantity can be measured, observed, recorded, or monitored in a physical system. The system is accordingly termed as an analog system or the digital system. In the analog system, a quantity is represented in terms of a voltage or current, or the movement of a meter-needle. A few examples of analog systems are: a microphone producing an output voltage proportional to the input sound, an auto-speedometer whose needle moves according to the speed of auto a thermocouple in which the current varies with the junction temperature, or an analog watch whose needle records the time-intervals. The input and output quantities in an analog system are obviously termed as analog quantities whose main and common characteristic is that they vary in continuous manner and not in fixed or discrete steps. In the digital system, a quantity is represented only in definite or fixed amounts by means of digits. It does not vary in a continuous manner like the analog quantities. For example, a digital watch reads the time in steps of a minute or a second, or even its parts, whereas the analog watch reads the time continuously. Thus, a digital quantity is discrete and the analog quantity is continuous, although the two are convertible into eachother. Since most physical quantities in Nature are analog, their processing and manipulation can be eased if they are converted into digital formats.

DIGITAL PRINCIPLES AND CIRCUITS

2

1.2 ADVANTAGES OF DIGITAL nCHNOLOGY The distinct advantages of digital technology over the analog techniques are the following: 1. 2. 3. 4. 5. 6. 7. S.

Designing and fabrication of digital circuits is simpler and easier. Storage of information for any short or long periods is easier in digital systems. Digital operation is easily programmable. Digital devices are computer-compatible. Digital circuits are less affected by noise problems. Digital IC chips can be fabricated with more circuitry on smaller area. Digital data can be processed at a faster rate. Digital devices are more precise, reliable and accurate.

1.3 DIGITAL NUMBERS

Digital number is a group of digits whose relative positions determine their weight. The following four kinds of digital numbers are frequently used in digital systems. 1. 2. 3. 4.

Decimal numbers Binary numbers Octal numbers Hexadecimal numbers

A decimal number is formed by grouping any of the ten digits (0 through 9). For instance, 346, 436 and 643 are three different decimal numbers whose magnitudes are different depending on the relative positions of digits in each one. A binary number is formed by grouping any of the two digits (0 and 1) which are commonly termed as bits. For instance, 1001 (read as one-zero-zero-one) is a binary number which is formed with the two bits in four positions. In binary numbers also, the bitpositions determine the magnitude of the number. Natural binary numbers advance in a sequence by adding a 1 to the preceding number. An octal number is a group of any of the eight digits (0 through 7) whose magnitude depends on the relative positions of digits in it.

A hexadecimal number uses ten decimal digits (0 through 9) and six alphabets (A,B,C,D,E,F) whose positions determine the magnitude of the number.

1.4 BCD vs BINARY The term "BCD" is the abbreviation for binary-coded-decimal which means expressing a decimal number in binary digits. Note that a BCD number for a decimal is not the same as the equivalent binary. In BCD representation, each digit of a decimal number is expressed with a 4-bit group of equivalent binary, whereas in binary representation, whole of the decimal number is written in natural binary. Some of the decimal numbers given below are expressed both in natural binary and BCD formats.

3

DIGITAL CONCEPTS

Decimal

Natural binary

0 1 2 9 18 62 103

0 1 10 1001 10010 111110 1100111

BCD 0000 0001 0010 1001 10011000 01100010 000100000011

1.5 SIGNED NUMBERS AND COMPLEMENTS To represent a negative number, we normally use a minus (-) sign and to represent a positive number, we use a plus (+) sign before it. However, in binary numbers, instead of using these plus or minus signs, it is more convenient to put a 1 for the minus sign and a 0 for the plus sign. These bits of 1 and 0 are called as the sign bits, and the resulting number as the signed-magnitude binary number. For instance, the negative number -9 is expressed below in the signed-binary form with 1 as the sign-bit and 1001 as the magnitude bits . Decimal (-9) = 1 100 1 Signed binary

Signbit~

'----v---'

t

L ___

Magnitude bits

Representation of signed numbers in l's -complement form and 2 's-complement form is another way through which arithmetical manipulations can be done most conveniently. l's complement of a binary number is obtained by inverting each 0 into 1, and each 1 into 0 in the magnitude bits. 2's complement of a binary is obtained by adding a1 to the l's complement. Much about these complements and their arithmetical manipulations are given in Chapter 2.

1.6 VOLTAGE REPRESENTATION OF BITS Any digital device or circuit that receives binary signals (in terms of Os and Is) must operate only with two states, so that one state may represent binary 0 and the other state, binary 1. Also, there must be two particular voltage-levels that may represent the two bits of o and 1. However, instead of assigning two fixed levels of voltage for this purpose, it is convenient and customary to assign two voltage-ranges: usually, OV to 0.8 V range for binary 0, and 2V to 5V range for binary 1, as illustrated in Fig. 1.1. This implies that any voltage within the lower range would mean a binary 0 and any voltage within the upper range would mean a binary 1. This kind of representation is referred to as positive logic representation. However, if we adopt an opposite representation, in which aO is represented with the upper range and a1 is represented with the lower range of voltage, such a kind of representation would be referred to as negative-logic representation. Either of the two methods can be adopted in any digital circuit, but the same must be essentially specifi r rl with that circuit.

4

DIGITAL PRINCIPLES AND CIRCUITS Voltage

SV range (1) 2V

O.8V OV

Fig. 1.1 Positive-voltage representation of binary 0 and 1

1.7 VOLTAGE LEVELS AND LOGIC LEVELS

The two voltage-ranges repl-esenting the binary 0 and binary 1, in Fig. 1.1, are the voltage levels which we may call as "low" for binary 0 and «high" for binary 1 in the positive-logic representation or vice versa if the negative logic representation is adopted. Thus, the input and output of a circuit would be termed as low or high, depending on whether the voltage present there is within the prescribed lower or upper range. The low and high voltage levels are also referred to as "logic 0" and "logic 1" states, respectively. Also, the other terms used synonymously for these states are given in Table 1.1. Table 1.1 Logic 0

Logic 1

False Off No Low Open

True On Yes High Closed

1.8 DIGITAL CIRCUITS vs LOGIC CIRCUITS

A digital circuit is one that produces an output voltage within the prescribed voltage-ranges (low or high) in response to the inputs which also fall within the same prescribed voltageranges. In other words, a digital circuit responds to an input's binary level (0 or 1), and not to its actual voltage. Any digital circuit can be equally termed as a logic circuit. This is so because the operation of a digital circuit is based on a definite logic that governs the operating conditions (input-output relationships) in the circuit. For example, the circuit-logic of an INVERTER, stating "Output is high when input is low" governs the operations of inversion. In this way, the terms -digital and logic are synonym to each other, and either can be llsed in place of the other. Since a transistor is used as a key element in every digital circuit, these circuits may be classified into the following categories depending on the two operating states of the transistor:

DIGITAL CONCEPTS

1

2

3

5

Circuits in which one state of the transistor corresponds to the cut-off region (with both the junctions reverse-biased), while the other state corresponds to the saturation region (with both the junctions forward-biased). These circuits are referred to as saturating circuits. Circuits in which one state of the transistor corresponds to the cut-off region, but the other state lies in the forward active-region (with the emitter forward-biased and the collector reverse-biased). These circuits are referred to as non-saturating circuits. Circuits in which both the states of the transistor correspond to the forward activeregion.

The former two classes of circuits are most widely used in the digital systems. 1.9 BASIC LOGIC-OPERATIONS

There are three logic operations which are most basic and independent of eachother. These operations belong to the Boolean algebra, and are named as AND operation (logical multiplication), OR operation (logical addition) and NOT operation (logical inversion or complementation). Each of these operations is performed by the corresponding logic gate, such that the gate-output is the result of the logic operation performed on the gate-inputs.

AND operation AND operation is performed by an AND gate which produces a high output when all the inputs are high. The Boolean expression for AND operation uses a dot (.) sign between the variables to be ANDed. OR operation

OR operation is performed by an OR gate which produces a high output when any or all the inputs are high. The Boolean expression for OR operation uses a plus (+) sign between the variables'to be ORed.

NOT operation NOT operation is performed by an INVERTER which produces a high output when the input is low, and vice versa. This operation is termed as inversion or complementation. The Boolean expression for NOT operation uses an overbar (-) which is raised over the input variable to be complemented. 1.10 LOGIC-GATE SYMBOLS

To indicate the existence of a logic gate in the logic-circuit diagrams, a definite symbol has to be used for each gate, which is termed as the logic symbol of that gate. Though, these symbols are normally used in their standard shapes, however, their alternate forms are also found meaningful in many circuit diagrams. Fig. 1.2 shows the AND, OR, INVERTER, NAND and NOR gates in their standard and alternate forms, which are equivalent of eachother. Note that the small circles shown in these symbols, indicating the inversion, are called as inversion circles, or bubbles. The procedure to derive the alternate form from the standard form is explained in the following steps.

DIGITAL PRINCIPLES AND CIRCUITS

6

:=cr :~ :~ :~

AND

.., '?'

Operation symbol (OR) OR

.... '?~

A~='R

B~AD=A+B ~Operation symbol (AND)

NAND~,

A~

NOR ~, -'

A~ __

-'

NOT> Standard symbols

A~=-B A+ B=AB

B~A+B=AB

B

--d..-)

_ AB=A+B

A-4:>-A Alternate symbols

Fig. 1.2 Logic-gate symbols

1. Invert each input and output of the standard symbol, by putting bubbles wherever absent, and ·by removing them if present in both the input and output lines of the standard symbol. 2. Change the operation symbol from AND to f)R, or from OR to AND For example, the standard N~ symbol is an AND symbol with a bubble on its output, but no bubble on any input. Therefore we remove the output bubble and put a bubble on each input of an OR symbol. On the basis of symbolic representation, the NAND and NOR gates are termed as inverting gates, because a bubble is present on either the input or the output of both the standard and alternate symbols. On the hand, AND and OR gates are non-inverting gates because their standard symbols have no bubbles and each alternate symbol has bubbles on both the inputs and the output. The gate Bymbols shown in Fig. 1.2 are significant because they can interpret how a gate operates. For this purpose we explain below the meaning of active logic-levels. 1.11 ACTIVE-LOW AND ACTIVE-HIGH LEVELS

When an input- or output-line on a gate symbol has a bubble on it, that line is termed to be active-low. When the input- or output-line has no bubble on it, such line is termed as activehigh. Thus, the presence or absence of a bubble determines the active -low/active-high state of inputs and outputs in the circuit, and is used to describe the operation. Let us consider an example of a NAND gate whose symbols are shown in Figs. 1.3 (a) and (b). The operation of NAND gate can be stated in the following two different ways: 1. Output goes low when all inputs go high. 2. Output goes high when any input goes low. The NAND symbol in Fig. 1.3 (a) interprets the fIrst statement in which the word "all" is ' used for the AND symbol. The NAND symbol in Fig. 1.3 (b) interprets the second statement in which the word "any" is used for the OR symbol. Thus both the symbols interpret the same operation in two different ways.

DIGITAL CONCEPTS

7

P\

Active-high Inputs

ActIve-low output

Active-low inputs

Active-high output

Fig. 1.3 Active-low and active-high states in

NAND

symbols

1.12 MULTI-INPUT GATE SYMBOLS Logic gates having more than two inputs are called as multi-input gates. Fig. 1.4 shows the logic symbols for the multi-input AND and OR gates. One can note in these symbols as to how the edges for the 4 inputs and 5 inputs have been extended. This is the common practice to be followed while drafting the multi-inputs symbols for any gate.

DFig. 1.4 Logic symbols for multi-input gates

Note that the XOR (exclusive OR) and XNOR (exclusive NOR) gates basically have 2 inputs each. However, in their Ie versions more inputs are provided by fabricating several 2input units in sequence, as shown in Fig. 1.5 (a) in which the output of one unit is connected to one of the inputs of the next unit. The logic symbol for the 4-input XOR gate is also shown in Fig. 1.5 (b).

:> (a)

(b)

Fig. 1.5 (a) 4-input XOR gate (b) its logic symbol

1.13 TIMING DIAGRAM The switching of the output from low state to high, or vice versa, is termed as "transition" or change of "state" or "level". Timing diagram, is the graphical representation of occurrence, or non-occurrence of these transitions at regular time-intervals during the operation of the circuit.

DIGITAL PRINCIPLES AND CIRCUITS

8

1.4 SERIAL AND PARAWL TRANSMISSION

TJ:'ansmission of digital information from one place to the other in a computer is an important aspect. There are two methods: serial and parallel, through which the information can be transmitted between two places, either on the same chip, or within the same digital system, or even over a long distance of kilometers. In serial transmission, the information is transmitted bit -by-bit, i.e. one bit at a time, whereas in the parallel transmission, all the bits of information are transmitted simultaneously. The main difference between these two methods is that the parallel transmission goes faster, but it requires more connecting lines. 1.15 BJT ·BJT (bipolar junction transistor) is a three-terminal semiconductor device which consist of two p-n junctions joined back-to-back. The three sections (or regions) forming this device are named as emitter, base and collector. In other words, a BJT is simply a thin sandwich of one type of semiconductor material between two layers of other semiconductor material. Fig. 1.6 shows the BJT structures along with their circuit symbols. When a thin layer of n-type semiconductor material is sandwiched between two layers of p-type material the structure is named as pnp transistor (Fig. 1.6 (a). When a thin layer of p-type material is sandwiched between two layers of n-type material, the structure is named as npn transistor (Fig. 1.6 b).

E~

Emitter

P

Base

Collector

nip

~C

.-=E::..:m.::.:itt:::e::...r~-=Ba=se=--rCo=II:::;ect:::o:::..,r P ~c

Eo---1

1

1

B

B

,...---oC

Eo-----..

nip

Eo----.....

r---oC

B

B

(a)

(b)

Fig. 1.6 Structures and symbols of (a) pnp transistor and (b) npn transistor

The three terminals coming out of the emitter, base and collector regions, are labelled as E, B and C, re~pectively. The two junctions are named as emitter-base (EB)junction and collector-base (CB) junction. The emitter-base junction is forward-biased and the collector-base junction is reverse-biased. Emitter The left-hand region of transistor is named as emitter. It is heavily doped because it has to supply the majority carriers (elections or holes) to the base.

Base The middle region of transistor is named as base. It is very'thin (-10-6 m) and lightly doped compared with the emitter and the collector regions.

9

DIGITAL CONCEPTS

Collector The right-hand region of transistor is named as collector. It is moderately doped and its main function is to collect the majority carriers coming from the emitter through the base. Normally, the collector region is made physically larger than the emitter because it has to dissipate a greater amount of power. The, circuit symbols for pnp and npn transistors are also shown in Fig. 1.6. in which it can be noted that the arrow head is always attached to the emitter, which indicates the conventional direction of current flow. In pnp transistor the inward arrowhead indicates the flow of current from emitter to base, whereas in the npn transistor, the outward arrowhead indicates the flow of current from base to emitter.

1.16 UJT A UJT (unijunction transistor) is basically a 3- terminal semi-conductor diode which has only a single p-n junction. This device consists of a lightly doped n-type silicon bar with a heavily doped p-type material alloyed to its one side, so as to form a single p-n junction. As shown in Fig. 1.7 (a), the terminal leads drawn at the two ends of the silicon bar are called as base-1 (B 1 ) and base-2 (B 2 ), and the terminal coming out of the p-type material is called emitter (E). In the circuit symbol (Fig. 1.7 b), the arrow in the emitter is bent toward Bl which indicates the flow of current through the junction. 82 82

E

'!:

Silicon bar

n

E

81 81 (a) UJT structure

(b) UJT symbol

Fig. 1.7 UJT Structure and Symbol

A UJT differs from a diode in that it has three terminals. Although, a UJT cannot be used as an amplifier, its negative-resistance property makes it useful in making oscillators.

1.17 FET The FET (field-effect transistor) is a 3-terminal semiconductor device in which the current is controlled with the application of an electric field. Unlike a bipolar transistor, an FET is a unipolar device because only one kind of charge carriers, i.e. either electrons or holes, take part in the process of current conduction. Moreover, an FET has a much

DIGITAL PRINCIPLES AND CIRCUITS

10

greater input impedance (several megohms) and low noise as compared to the bipolar transistor. There are two kinds of FETs, namely:

,-r

1. Junction field-effect transistor (JFET), or simply FET 2. Metal-oxide semiconductor FET (MOSFET)

JFET A JEFT (junction field-effect transistor) can be made in both the n-channel and p-channel configurations. The n-channel JFET consist of n-type silicon bar (Fig. 1.8 a) whose opposite sides are diffused in the middle with a heavily doped p-type material. The middle Drain (D)

Drain (D) p

n-Channel Gate O-......,JP-J n (G)

·~

Internal : short

p-Charmel Gate (G)

· ·· ·

: Internal : short

··

I

(a)

(d)

o

0

n

1

G

Electrons

n

Depletion layer (VGS = 0) Go--I.n:a

.:-

p

•

'. •

I

'" +--Extended depletion layer (-VGS increased)

s (e)

o

0

GQ--.....

Go--i-I

s n-Channel FET

(I)

s p-Channel FET

Fig. 1.8 FET structure and circuit symbols

Depletion layer (VGS =0)

....

, I

S (b)

(e)

1

:'

I

Holes

Extended depletion layer (-VGS increased)

,

DIGITAL CONCEPTS

11

space in the bar acts as the path for the charge carriers, and is called as channel. The two diffused p-regions , each forming a p-n junction, are internally connected together and a common lead is taken out as the gate terminal (G). The other leads taken out from the two ends of the bar are called as source terminal (8) and drain terminal (D). Note that these two terminals are interchangeable depending on the polarity of the voltage applied between them. The current-input end of the bar is source, and the other end is drain. When a voltage is applied between the source and drain, drain current flows along the channel in terms of electrons as the charge carriers. The drain current is governed by the gate voltage Vas which is always kept negative to keep the gate reverse-biased. The above four constituents of the JFET are briefly defined as follows. Channel

IS the space between two gates through which majority carriers pass between

source and drain. Gate is the terminal which comes out from two internally connected p-n junctions which are formed at the opposite sides of the channel. is the terminal through ~hich majority carriers enter into the bar. It is socalled because the carriers originate from it. is the terminal through which majority carriers leave the bar. Drain Operations: The operation of n-channel JFET can be explained using Fig. 1.8 (b) as follows: (i) When V GS = 0, and VDS is applied between drain and source, the two p-n junctions form depletion layers (shaded areas). The electrons flow from source to drain in the channel between depletion layers. The width of depletion layers determines the width of the channel and hence its conductivity, or the amount of drain current.

V GS = -ue (gate is reverse-biased), the width of depletion layers increases Fig. 1.8 b), which reduces the width of conducting channel, and hence its conductivity. The drain current through the n-channel therefore decreases. If the reverse voltage on the gate is now decreased, the width of depletion layers would decrease and therefore the width of conducting channel would increase. This would increase the amount of drain current. In this way the drain current is controlled by varying the negative gate-village.

(ii) When

Ap-channel JFET (Fig. 1.8 d) is formed with ap-type bar and diffusing two n-type regions on opposite sides of its middle part. Its operation (as illustrated in Fig. 1.8 e) is similar to that of n-channel JFET except that the polarity of the voltage VDS and V GS are reversed. Note that the charge carriers in this case are holes instead of electrons. Fig. 1.8 (c) and (f) show the circuit symbols for the two kinds of JFET. The vertical line in each symbol indicates the bar (or channeD, and the gate-arrow is always directed toward the n-type material.

1.18 MOSFET A MOSFET(m¢tal-oxide semiconductor field-effect transistor) is the modified version of JFET in which the gate is insulated from the channel with a thin film of metal oxide, usually the silicon dioxide (Si0 2 ) deposited between them. This permits only a negligible gate current and therefore provides a very large input impedance (- 1012 ohms) to this

DIGITAL PRINCIPLES AND CIRCUITS

12

device. The insulation of gate also allows application of the positive as well as negative voltages to the gate, while only negative gate-voltages can be used in a JFET. Moreover, the diffusion of impurity material (n- or p-type) in the MOSFET is done only on one side of the silicon bar, instead of both sides. This diffused region is called as substrate, and is internally shorted to the source. Depending on the polarity of the applied gate-voltage, MOSFETs are constructed in the following two types: 1. Depletion MOSFET 2. Enhancement MOSFET 1.19 DEPLETION MOSFET

Depletion MOSFET can ,operate in either of the depletion and enhancement modes. To operate it in the depletion mode, we apply a negative voltage to the gate; and to operate it in the enhancement mode, the gate voltage is kept positive relati-:e to substrate. Fig. 1.9 (a) and (b) show the structures of n-channel and p-channel depleLion MOSFETs along with their circuit symbols. In each case, the impurity material (p- or n-type) diffused on one side of the bar is called substrate (88), and is internally connected to the source (8). In this structure, the gate and the channel act as two plates of a parallel-plate capacitor with the oxide film as dielectric. It is the formation of this capacitor which permits the application of both the positive and negative gate-voltages.

o n

p n-substrate

p-substrate

G

iSS

G

iSS

I

! ! i .......-.-....._...; S

i

:

i

_............_._-_..j S

+

o

o

G~ S (8) n-channel MOSFET

S (b) p-channel MOSFET

Fig. 1.9 Structure and symbols for depletion MOSFET

In the n-channel depletion MOSFET, when the gate voltage is VGS = 0, electrons flow freely from source to drain through the conducting n-channel. When the gate is given a\

DIGITAL CONCEPTS

13

negative voltage (Vas =-ve), the gate-capacitor induces positive charge in the channel (as the second plate of capacitor) which reduces the number of channel electrons. On increasing the negative gate-voltage, this effect increases, so that the channel conductivity and hence the drain current decreases. In fact, too much of negative voltage, denoted as Vas (om, would cutoff the channel completely. This negative-gate operation explains the depletion-mode operation. When a positive voltage is applied to the gate, the gate-capacitor creates free electrons in the n-channel which increases the channel conductivity or the drain current. This positive-gate operation is the enhancement-mode operation of the depletion MOSFET. It may be noted that the depletion MOSFETs are often taken to be as normallY-ON MOSFETs because the drain current flows in them even when Vas = o.

1.20

ENH~NCEMENT

MOSFECT

Enhancement MOSFET operates only in the enhancement mode, i.e. with the positive gate-voltages only. It cannot operate with a negative gate-voltage because it differs in structure from the depletion MOSFET. Fig. 1.10 shows the structure and circuit-symbols of n-channel and p-channel enhancement MOSFETs which are conventionally termed as NMOS and PMOS, respectively.

o n

.. .. .. .. .... ..···...... .... Go-......N

S

n-substrate extends upto Si02 1ayer

p-substrate extends upto Si02 1ayer

acts as virtual p-channel

o

I

J

G~9 S (8) NMOS

(b) PMOS

Fig. 1.10 Structure and symbols for enhancement MOSFETs

14

DIGITAL PRINCIPLES AND CIRCUITS

\

In the structure of NMOS device, as shown in Fig. 1.10 (a), thep-type substrate extends all the way upto the oxide layer, and thereby divides the n-channel, making it discontinuous between the source and drain. When we apply a negative voltage at the gate, the capacitor action induces positive charges in the space between the source and drain, which prevents the passage of electrons between the two. This explains why NMOS can never be operated with a negative gate-voltage. Also with a zero gate-voltage (VGS = 0), drain current does not flow because of the discontinuity of the channel. For this reason, enhancement MOSFETs are often termed as normally-oFF MOSFETs.

When we apply a sufficiently high positive gate-voltage, greater than a minimum threshold value VGS (th), a thin column of electrons is generated very close to the oxide layer (Fig. 1.10 a). The layer of p-substrate touching the oxide layer thus provides a channel for the electrons, and therefore acts as n-type material. It is then called as virtual n-channel which allows the flow of drain current. , Contrary to NMOS, the PMOS device operates only with the negative gate-voltages because it is fabricated by interchanging all the n- and p- regions of NMOS, as shown in Fig. 1.10 (b).

The circuit symbols for both the NMOS and PMOS devices are shown in Fig. 1.10 (a) and (b) in which the arrow on the substrate is always directed towards the n-type material. The broken vertical line indicates the non-conducting (discontinuous) channel. The shorting of substrate with the source, as shown in these symbols is made internally. NOTE Most of the MOS digital devices (Chapter 9) are fabricated exclusively in the enhancement MOSFET structure. 1~21

FAMOS

A FAMOS (floating-gate avalanche-injection MOSFET) is an improved version of MOSFET, in which the gate is kept floating, in addition to its being insulated from the oxide layer. More about this device and its use in the formation of EPROM memories is described in Chapter 9.

1.22 BASIC MOSFET SWITCH A MOSFET basically operates like an on-off switch that opens or closes between the source' and drain. The on or off state of this device is determined by the source-drain channel resistance which is controlled by the input gate-voltage VGS' In the n-channel MOSFET (NMOS) shown in Fig. 1.11 (a), when VGs=- 0 (or negative), there is no conducting channel between the source and' drain and the device is off. The channel resistance (ROFF ) in this OFF-state is typically - 1010 ohms, which forms almost an open circuit (Fig. 1.11 b) between source and drain. When V GS is made positive (equal to or greater than the threshold value ofVGS (th) = +1.5V), a conducting channel is formed between the source and drain, and the MOSFET starts conducting. The channel resistance falls to a value of RON = 1000 ohms (when Vas = +5V) which almost provides a short circuit between source and drain (Fig. 1.11c). In this way, the NMOS device switches from a very high resistance to a low resistance as the gate voltage changes from a low value to a high value.

15

DIGITAL CONCEPTS +5V

+5V

ROFF

-10 10 n

S

(a) NMOS

(b) OFF state (VGS =OV)

RoN = 1000n

S

(c) ON state (VGS = +5V)

Fig. 1.11 NMOS switching states

A PMOS device also operates in the same manner except that it uses voltages of opposite polarity. 1.23 INTEGRATED CIRCUITS (ICs)

In the earlier days, electronic circuits were used to be assembled by joining various discrete components with the help of connecting wires or leads. Later on, with the development of printed circuits, the inter-connections between the components were made by soldering them through short metal strips etched on an insulating sheet. However, the latest techniques today in vogue, are the integrated circuits in which we neither use any discrete components, nor any connecting wires, leads or strips. Instead, all the active components (such as transistors and FETs) and passive components (such as resistors and capacitors), as well as their interconnections are fabricated (integrated) on a single small wafer of silicon in a very compact from. Thus, an integrated circuit can be defined as a single tiny chip of the silicon crystal that contains all the active and passive components of the circuit along with their interconnections in the integrated form. 1.24 ADVANTAGES AND UMITATIONS OF ICs

ICs possess a large number of advantageous features which have made them so popular to be used widely. Some of the advantages, as also a few limitations, ofICs are listed below.

Advantages 1. Very small in size. 2. Very light in weight. 3. Very cheap in cost. 4. 5. 6. 7. 8.

Consuming a low power. Highly reliable. Can operate with high speeds. Huge packaging density. Easily replaceable.

DIGITAL PRINCIPLES AND CIRCUITS

16 Limitations 1. Coils and inductors cannot be fabricated. 2. Unable to withstand more heat and rough handling. 3. Not repairable.

1.25 . CLASSIFICATION OF ICs Classification of ICs can be done on several considerations such as packing density, their functioning, or the technique of fabrication. The first two types of classification are given below while the third one is discussed in Sec. 1.26. Classification by packing density Depending on the number of components/circuits integrated on a single chip, ICs have been classified into the following levels of integration.

(Small-scale integration) : When the number of circuits fabricated on the chip is less than 30. MSI (Medium-Scale integration) : When the number of circuits is between 30 and 100. IBI (Large-Scale integration) : When the number of circuits is between 100 and 10,000. VLSI (Very large-scale integration) : When the numbers of circuits is between 10,000 and 100,000. . UI.13I (Utra-large-scale integration): When the number of circuits exceeds 100,000. SSI

Classification by functioning On the basis of general functioning of the ICs, they are divided into the following groups: 1. Linear (analog) ICs 2. Nonlinear (digital) ICs

Linear lCs are so-called because the output in them is proportional to the input, as happens in the case of analog devices. Linear ICs are less used compared to the non-linear ICs, with their limited use in the military and industrial applications. Non-linear lCs, on the other hand, are widely used in digital devices and circuits in which the magnitude of output is not proportional to the input. All digital devices, such as gates, flip-flops, adders subtractors, counters, registers and various kinds of memories are fabricated as nonlinear ICs. These ICs are so popular and widely used that nearly 80% of the IC market is covered by them. 1.26 CONSTRUCnON OF MONOUTHIC ICs Monolithic lC is a tiny piece of silicon wafer on which all the active and passive components of a circuit are integrated. The monolithic technique involves the process of photolithography along with that of impurity diffusion. Monolithic ICs can be constructed either on bipolar, or on MOS technology, of which the former is described in the following steps.

DIGITAL CONCEPTS

17

Steps 1 Wafer preparation To prepare a wafer, we first take a p-type cylindrical bar of silicon crystal (about 2.5 cm in diameter) and cut it into many thin slices, called wafers, as shown in Fig. 1.12 (a). Each wafer has a thickness of about 200 pm and a diameter of 2.5 cm. It is then finely polished on one surface so as to remove any surface-imperfections. This wafer (Fig. 1.12 b) serves as the p-substrate.

silicon

I 0

bar

""~I'-__

p_-_s_ub_st_ra_te_---'I

Polished wafer

Water

(a)

I ~m 200

(b)

Fig. 1.12 Wafer preparation

Step 2 Epitaxial growth and oxidation In this step, we place the p-substrate wafer in a heating furnace at about 1200°C and pass over it a gas mixture of silicon and pentavalent atoms. This forms a thin layer of n-type silicon of about 10 pm thickness on the p- substrate, which is called as n-type epitaxial layer, as shown in Fig. 1.13 (a).

r

n-epitaxiallayer

n-epitaxial layer

--

::::::::::::::::::::::::::::::::;:::::::::::::::::::::::::::::::::::::::::::: 200~m

p-Substrate

Sio2layer~

.4 . ................................... .

:~:~: ~: ~ {:................................. ~ {{: ~:~:~: ~: ~: ~: ~: ~:~: ~:~: ~: ~{:~: ~:~ {{{:~:~:~: ...... ...................................... ::::::::::::::::::::::::::::::::::::::::::::::::::=:=:::::::::::::::::::::::: ... .............. ............... .. ..... :~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:~: p-Substrate

(a)

l

io.5~m 10 ~m

(b)

Fig. 1.13 Epitaxial growth and oxidation

Next, after cleaning and polishing the epitaxial layer, a thin layer of Si0 2 (0.5 pm thick) is grown over it for which the epitaxial layer is exposed to an oxidising agent at 1000°C. The oxygen atoms combining with the silicon atoms form the silicon dioxide layer, as shown in Fig. 1.13 (b) . This layer acts as a masking layer. Step 3 Isolation and Diffusion After completing step 2, the Si0 2 layer is etched away selectively at the places where impurity diffusion is required. The exposed portions of epitaxial layer (such as wI. W2, W3 in Fig. 1. 14 a) are called diffusion windows, and the remaining portions of Si0 2 layer, as masks.

DIGITAL PRINCIPLES AND CIRCUITS

18

n-type islands

n-type epitaxial layer

p-type impurity ", .1

p-Substrate

p-Substrate (a) Etched-away Si02 layer at

(b) p-type impurity diffused through w,. w2 • W3

locations w,. w2 • W3

Fig. 1.14 Isolation and diffusion

Now, the wafer is subjected to the process of impurity diffusion. In this process, the wafer is heated along with a p-type impurity, in such a way that this impurity diffuses into the epitaxial layer through the diffusion windows well upto the level of substrate , but not into the substrate. In this way, the n-type epitaxial layer below each window changes into a p- type region thereby isolating the adjacent n-type regions below the Si02 mask. These isolated regions are called as n-type "islands", as shown in Fig. 1.14 (b). Thus, each island is separated from the other by two back-to-back p-n junctions. More number of islands can be created by increasing the number of windows and diffusing through each window. Step 4 Metallization Metallization is the process which is meant for interconnecting various portions integrated in the wafer. In this process, the diffusion windows are closed by growing Si0 2 layer, and a new set of smaller windows is created at the points where contacts are to be made with the integrated portions (Fig. 1.15 a). A thin film of aluminium is then deposited over the entire wafer-surface by vacuum-deposition technique so that this metal may enter through the new windows and contact the parts.

New set of windows

~t~t P

AI-contacts

Etched-away regions

*~

L:J pTIp p-Substrate (a)

(b)

Fig. 1.15 Metallization process

Now, the undesired AI-film areas are etched away, leaving behind only the desired contacts, as shown in Fig. 1.15 (b).

19

DIGITAL CONaPTS Step 5 Separating into Chips

Because a wafer is fabricated with a large number of similar components or circuits on it, each chip containing an individual component or circuit is separated from the other by cutting the wafer into these chips. Each chip is then enclosed in a suitable package with the external pins coming out (see Sec. 1.29). 1.27. FABRICATION OF COMPONENTS AND CIRCUITS

The procedure to construct a monolithic Ie, as described in the foregoing Section, basically consists of three processes: etching of windows, creation of n- and p-islands, and interconnecting the integrated component parts. On this basis, how a transistor, a diode, a resistor, a capacitor, or a circuit is fabricated, is specifically described below for each one. (a) Formation of Diode

One or more diodes can be fabricated by diffusing one or more n-type impurities at appropriate locations over thep-substrate of the wafer. As described in steps 1,2 and 3 in the previous section, we prepare a p-substrate silicon wafer, deposit n-epitaxiallayer and Si02 layer on it, and then selectively etch away the Si02 layer at the desired locations, so as to create the diffusion-windows. This was shown in Fig. 1.14 (a) and is repeated here in Fig. 1.16 (a) with only two windows (wland W2) through which we diffuse p-type impurity into the epitaxial layer. This creates n-type island, as shown in Fig. 1.16 (b). These windows are then closed with a new layer of Si02 , as shown in Fig. 1.16 (c). Next, a new window (w) is created at the middle of this layer (Fig. 1.16 d) through which the n-type impurity is diffused into the n-epitaxiallayer, thus forming a p-type island, as shown in Fig. 1.16 (e). The entire surface of the wafer is again closed with Si02 layer, as shown in Fig. 1.16 (f). In this way, we get a p-n junction diode with p-island as anode and n-island as cathode.

p

p-Substrate (8)

p

.n.

p

p

p-Substrate

p-Substrate

(b)

(c) p-isJand

:1

: n: . p-Substrate (d)

p-Substrate (e)

Fig. 1.16 Formation of p-n junction

p

n·

I:

p-Substrate

(f)

DIGITAL PRINCIPLES AND CIRCUITS

20

Finally to attach the contact terminals (A, K), the Si02 layer is etched away at appropriate points so as to contact the p-island as anode (A) and the n-island as cathode (K) using the deposition of AI-metal film, as shown in Fig. 1.17.

p-Substrate

Fig. 1.17 Formation of junction diode (b)

Formation of Transistor

To integrate an npn transistor on the p-substrate wafer, a p-type island is created and sealed off with Si02 , as illustrated in Fig. 1.16 (f) in the case of diode formation. Now taking this wafer, we make a window (w) at the middle of Si02 layer (Fig. 1.18 a), and diffuse a p-type impurity into the epitaxial layer, This creates an n-type island, as shown in Fig. 1.18 (b). Now, an Si0 2 layer is finally grown over the entire surface for sealing it (Fig. 1.18 c). This provides the required integrated npn transistor in which contacts for emitter, base and collector terminals are made using the metallization technique as described earlier and illustrated in Fig. 1.18 (d) Si02 1ayer

. n. p-Substrate

p-Substrate

p-Substrate

(b)

(a)

< >

(c)

E~C

p-Substrate

(d)

Fig. 1.18 Formation of npn transistor

! 8

(e)

21

DIGITAL CONCEPTS (c) Formation of Resistor

The general procedure to fabricate an IC resistor is the same as that for the diode formation. However, while diffusing the doping p-impurity, its concentration as well as the depth of diffusion into the epitaxial layer are so adjusted that the resistance value of the dopedp-region changes from one point to the other. Fig. 1.19 shows two such points (1,2) on the p-island which differ in their resistance values. As a result, this portion of p-island between 1 and 2 acts as an integrated resistor.

p

>


8

2. Decimal product is (a) 4 Octal multiplicand---.... 4 Decimal x 2 Octal multiplier ---_JI X 2 Decimal

? Dividing the decimal product by 8, we have

8 Decimal product (= 8)

~ =1 Quotient, 0 Remainder Result Hence,

=~ 0 - 1

Octal product 48 x 28 = 108

(b)

25 Octal multiplicand ---_~ 21 Decimal x 3 Octal multiplier x 3 Decimal ? ffi Decimal product ( > 8) Dividing the decimal product by 8, we have

~ =7 Quotient, 7 Remainder Hence,

Result = ; 7 - 1 Octal product 258 x 38

= 778

NOTE D~vision with octal numbers can be perform!3d either through binary or by repeated subtraction of he divisor from the dividend.

DIGITAL PRINCIPLES AND CIRCUITS

60

2.30 HEX ADDITION Addition of hex numbers is similar to octal addition, except that the radix is 16 instead of 8. Consequently, after each sum of 16 in any column, a carry of 1 is raised to the next higher column. Remembering that the largest hex digit is F (decimal 15), this procedure is illustrated below. (i) -Carry (ii) 11 1 -Carry 1 Hex augend 2A.E6 Hex augend 94 +82 Hex addend +3BF.2D Hex addend -3E9.13 Hex sum 116 Hex sum ~Hex point In (i), LSB column

Second column Third column In (ii), LSB column Second column Third column Fourth column Fifth column

4 + 2 =6 (result), no carry 9 + 8 =17 - 16 =1 (result), 1 carry to third column. 1 carry = 1 (result). 6 + D (13) = 19-16 = 3 (result), 1 carry to second column. E (14) + 2 + 1 carry = 17 - 16 = 1 (result), 1 carry to third column A (10) + F(15) + 1 carry = 26 - 16 = 10 (A) result, 1 carry to fourth column. 2 + B (11) + 1 carry = 14 (E) result, no carry 3 (result).

2.31 HEX SUBTRACTION Subtraction with hex numbers is similar to octal subtraction, except that the borrow of 1 taken from the higher column is added as 16 (hex radix) to the borrow-demanding column. This is illustrated and explained below. (ii) (i) -Borrow

,,,

)~

3E.8A -2F.98 E.F2

Hex minuend Hex subtrahend Hex difference

In (i), LSB column Second column Third column Fourth column

2B6.5F -6A.EC 24B.73

Hex minuend Hexsubtrahend Hex difference

A(10) - 8 =2 (result) =, no borrow 8 - 9 + 16 = 15 = F (result) E(14) -1 borrow = 13 - F(15) + 16 =14 =E (result) 3 - 1 borrow =2 - 2 =0 (result)

Similarly, we can subtract in (ii)

2.32 HEX MULTIPUCATION AND DIVISION Hex multiplication is exactly similar to octal multiplication, except that the radix is 16 instead of 8. In this process, each hex number is converted into decimal and then we multiply them. If the decimal product is less than 16, it gives the result. If the decimal product is equal to or greater than 16, we divide it by 16, and use the remainder as the LSD,

NUMBER SYSTEMS

61

and the quotient as the MSD of the result. This procedure is illustrated below for a few cases.

(0

5 Hex x 3 Hex

.. 5 Decimal .. x 3 Decimal 15 Decimal « 16)

?

8 Hex---_.. 8 Decimal x 2 Hex .. x 2 Decimal ? 16 Decimal (=16) Dividing it by 16, we have (ii)

16 . 16 = 1 Q uotient, 0 Re.d mam er

l

I

J

Hex product = 1 0 Hence, r8-1-6-X-2-1-6-=-1-0-16'1

I

(iii)

A Hex---_.. 10 Decimal x B Hex .. x 11 Decimal

110 Decimal (> 16)

?

(iv) 5.2 Hex:---_.. 5.125 Decimal x 8.E Hex .. x 8.875 Decimal 45.484 Decimal (> 16)

?

Dividing 110 by 16, we have

Dividing it by 16, we have

;~o

45.484 W--

= 6 Quotient, 14 Remainder I

~r

Hex product = 6E Hence, --=-6E-'1 AxB

Ir-

2 Quotient, 13.484 Remainder

~ D.484----1

Hence, 15.2 x 8.E = 2D.484!

NOTE Division in hex can be performed either through binary, or by repeated subtraction of divisor from the dividend.

2'5-COMPLEMENT ARITHMETIC5 2's-complement system is the most convenient and commonly used system to carry out the arithmetical operations in digital computers. These operations, which are illustrated and explained in the following sections, slightly differ from those in the other systems. It may be pointed out that a particular digital machine is designed only for a particular complement system, and therefore it can deal only in that particular system, and no other. It must also be ensured that every 2's-complement number has the same number of bits as assigned for the particular machine.

2.33 2'5 COMPLEMENT ADDITION In 2's-complement system (0 A positive number is expressed by its signed binary equivalent and , (U) A negative number is expressed by the 2's complement of its signed binary. magnitude. Keeping this in mind, the procedure of addition in this system is described below under three cases depending on the polarity of the two numbers to be added. 1. When both the numbers are positive, we directly add their signed binary values. The sum is positive with a sign bit of O.

62

DIGITAL PRINCIPLES AND CIRCUITS 2. When both the numbers are negative, we add their 2's complements. Ignoring the extra carry appearing in the sum, the remaining bits are taken as the negative result with a sign bit of 1. 3. When both the numbers have opposite signs, we add 2's complement of the negative number to the signed biliary of the positive number. If the sum shows an extra carry, it is ignored and the remaining bits are taken as the positive result with a sign bit ofO. If the sum shows no extra carry, all the bits are taken as the negative result with a sign bit of 1.

Each of the above procedures is illustrated below, using 5 bits including the sign bit.

Case 1 Augend and Addend both Positive 9 Augend

01001 +00100 01101

+4 Addend 13 Sum

Signed binary of 9 --Sig:n.e.c:i binary of 4

Sum (no extra- carry) tL-___ Positive sign bit

Result (9 + 4) =01101 (13)

Case 2 Augend and Addend both negative (-9) + (-4)

Augend Addend

10111 + 11100

2's complement of -9 2's complement of -4

Sum Extra carry _ _---'tt'---__ Negative sign bit ignored Result (-9) + (-4) = 10011 (-13) -13

110011

Case 3 Augend and Addend have opposite signs (a) Augend> Addend: Result is positive

(9) + (-4)

Augend 01001 Signed binary of9 Addend +11100 2's complement of-4 5 Sum 100101 Sum Extra carry _ _---'tt'---__ "Positive sign bit ignored Result 9 + (-4) = 00101 (5)

(b) Augend < Addend: Result is negative

4 + (-9) -15

Augend Addend Sum Result

00100 Signed binary of 4 + 10111 2's complement of -9 1011 Sum (no extra carry)

tL-___ Negative sign bit 4 + (-9) =11011 (-5)

NOTE 2's complement adderlsubtractor circuits are discussed in Chapter 6.

NUMBER SYSTEMS

63

2.34 2'5 COMPLEMENT SUBTRACTION Subtraction in 2's-complement system is conveniently performed through addition, because the subtraction A - B can be expressed as the addition A + (-B). This means the addition of a positive number with a negative number, which has already been discussed in Case 3 of the foregoing Section 2.33. Naming the positive number as minuend and the negative number as subtrahend, we illustrate below this subtraction by adding the 2's complement of the subtrahend to that of the minuend (using 4 bits including the sign bit).

(a) Minuend> Subtrahend: Difference is positive 7 Minuend 0111 -3 Subtrahend + 1101

Signed binary of 7 2's complement of -3 Sum Positive sign bit

4 Differe_n_c_e_---lIQ100 Extra carry ignored Result = (7 - 3) = 0100 (4)

n

(b) Subtrahend> Minuend: Difference is Negative 3 Minuend 0011 Signed binary of 3 -7 Subtrahend + 1001 2's complement of-7 -4 Difference 1100 Sum (no extra carry) t Negative sign bit Results (3 -7) = 1100 (-4) NOTE Whenever the result (Difference) is a negative number, its magnitude can be obtained by its 2's complementation.

2.35 2'5 COMPLEMENT MULTIPUCATION Multiplication in 2's-complement system is performed like that in binary, for which the multiplier and the multiplicand both must be in their true binary forms. The procedure is explained and illustrated below.

(i) When the multiplier and the multiplicand both are positive, they are already in their true binary forms, and are multiplied as they are. The resulting product is a positive number which must be assigned a sign bit of o. 12 Multiplicand x7 Multiplier -84 Product

1100 x 0111 1100 1100 1100 0000

1010100

True binary of 12 Ttue binary of 7

}

Partial products Product magnitude of 8410

Attaching a sign bit of 0, the positive product is given by Product 12 x 7 = 01010100 (84) in 2's complement system

DIGITAL PRINCIPLES AND CIRCUITS

64

(ii) When the multiplier and multiplicand both are negative, each one is 2'scomplemented to obtain their true magnitudes. On multiplying these magnitudes, the resulting product is a positive number which must be assigned a sign bit of O. (-9: Multiplicand 1001 True binary of magnitude 9 + (+8) Multiplier x 1000 True binary of magnitude 8 72 Product 0000 0000 0000

} Partial products

1001 Product magnitude 72 1001000 Attaching a sign bit of 0, the positive product is given as Products (-9) x (-8) = 01001000 (72) in 2's-complement system (iii) When the multiplier and multiplicand have opposite signs, The negative number is

first 2's-complemented into its positive magnitude, as above. The product of the two magnitudes is a positive magnitude which is 2's-complemented and assigned a sign bit of 1 to pr0\1de the final negative result. True binary of 6 6 Multiplicand 0110 x (-2) Multiplier x 0010 True binary of magnitude 2 -12 Product 0000 0110 } Partial products 0000 . 0000

Product magnitude 12 0001100 2's complement of 1100 (12) 0100 Attaching a sign bit of 1, the final negative product is given as Product 6 x (-2) = 10100 (-12) in 2's-complement system

2.36 2'S-COMPLEMENT DIVISION Division in 2's complement system is normally performed through repeated subtraction of the divisor from the dividend. In this process, each subtraction is done as the addition of 2's complement of the subtrahend (negative divisor) to the minuend (positive dividend). This is illustrated below for 11000 (24) + 110 (6). Equalizing the number of bits, the signed numbers are: Dividend 24 = 011000, It's 2's complement = 011000 Divisor 6 000110, It's 2's complement = 000110 Negative divisor -6 = 100110, It's 2's complement = 111010 14 Dividend (Minuend) 011000 Signed bin~ of 24 -6 Divisor (Subtrahend) +111010 2's Complement of-6

=

18 " -6"

Ignoring 1 ~ 1010010 Signed binary of 18 +111010 2's Complement -6

Contd.

NUMBER SYSTEMS

65

-Contd. 12

-6 6

-6

o

Ignoring 1

~

Ignoring 1

~

Remainder Ignoring 1

~

" " " "

1001100 +111010 1000110 +111010 1000000

Signed binary of 12 2's Complement of -6 Signed binary of 6 2's Complement of -6 2's Complement of 0 (Remainder)

Thus, the final result can be written as: Quotient Remainder

= 4 (Number of times the above additions are made) = 000100 (4) = 000000 (0)

1 'S-COMPLEMENT ARITHMETICS 1's complement system of representing the signed numbers is less frequently used because of certain limitations involved in it. However, the procedures to carry out the arithmetical operations in this system are similar to those used in the 2's-complement system, except that l's-complement numbers are used instead of 2's-complement numbers. A few operations are illustrated below. 2.37 1 'S-COMPLEMENT ADDITION AND SUBTRACTION In 1's-complement addition, we add the augend and addend by writing the positive number in signed-binary form and the negative number in its 1's-complement form. In l'scomplement subtraction, we add the l's complement of the subtrahend to the minuend (in signed-binary form). In either of these operations, if an extra carry appears in the sum, it is removed and added as end-around carry (EAC) to the LSB of the sum to obtain the final result in l's-complement system. A few examples are illustrated below. Addition 5 Augend 0101 Signed bin. of 5 +2 Addend + 0010 Signed bin. of 2

7 Sum

0111 Sum (no extra Carry) Result (5 + 2) = 0111 (7)

(-5) Augend 1010 l' Comp't of -5 + (-2) Addend +1101 l' Comp't of-2

-7

Sum

r

10111 Sum (with extra carry)

~ +1 EAC added

1000 Result (-5-2) = 1000 (-7)

Subtraction 2 Minuend 0010 Signed bin. of 2 -5 Subtrahend +1010 1's Comp't. of -5

-3 Difference 1100 Sum (no extra carry) Result (2-5) = 1100 (-3) 5 Minuend 0101 Signed bin. of 5 -2 Subtrahend +1101 1's comp't. of-2 3 Difference [ 1~010 Sumn (with extra carry) +1 EAC 0011 Result (5-2)

=0011 (3)

2.38 1'S-COMPLEMENT MULTIPLICATION AND DIVISION In l's-complement multiplication, we multiply the two numbers by putting each one (positive or negative) in its true binary magnitude. The true-binary product so obtained is assigned a sign bit of 0 if the multiplier and multiplicand both are positive or b6th negative. But if they are of opposite polarity, the above signed binary product is 1's complemented to "get the result. This is illustrated below.

DIGITAL PRINCIPLES AND CIRCUITS

66

4 x2

100 True binary of 4 x 10 True binary of 2

8

000 100 1000 True binary product 8 01000 Signed binary product 8 Result 4 x 2 =01000 (8)

4 x (-2)

-8

100 True binary of 4 x 10 True binary of 2 000 100

1000 True binary magnitude 8 01000 Signed binary magnitude 8 10111 1's-complement of 8 Result 4 x (-2) = 10111 (-8)

NOTE Division in l's-complement system can be carried out by repeated subtraction of divisor from the dividend, as illustrated for 2's-complement system (Sec. 2.36).

2.39 SUMMARY •

• • •

• • • • • •

• • •

• •

Binary number system uses two digits (0 and 1), decimal uses ten digits (0 through 9), octal system uses eight digits (0 through 7) and the hex systrm uses sixteen digits i.e. ten decimals (0 through 9) and six alphabets (A, B, C, D, E, F). "Bit" is the shortened form of "binary digit'. "Nibble" is a 4-bit word. "Byte" is an 8bit string that represents a character. Each of the decimal, binary, octal and hex systems is a positional system, in which a number is expressed as the sum of positional values of the digits. In the conversion of decimal to binary/octallhex, we repeatedly divide/multiply the integer/fraction by base 1/8/16 accordingly. In the conversion of binary/octallhex to decimal, we sum up the positional values of digits using the weights of 2n / 8n/16n • In the conversion of binary to octal, or octal to binary, we use 3-bit grouping. In the conversion of binary to hex, or hex to binary, we use 4-bit grouping. BCD system differs from binary in that each decimal digit in it is expressed with the 4-bit binary equivalent. In binary addition, 1+1¢2, but 0 with a carry to the higher column. In binary subtraction, 0-1 ¢ -1, but a 1 with a borrow from the higher column. Signed binary has a sign bit of 0 for the positive numbers, and a sign bit of 1 for the negative numbers. 1's- complement of a binary is obtained by inverting each bit. 2's- complement of a binary is obtained by adding a~ to the 1's complement. In 2's-complement system, a positive number is expressed by its signed binary value with a 0 sign bit. Negative number is expressed by 2's-complementing the signed binary magnitude. Negation of a signed number is its 2's-complementation, which represents the same number with opposite polarity. Total number of values in 2's-complement system using N magnitude bits is 2N + 1 which range between the largest negative value _2N and the largest positive value 2N -

•

1.

Addition is the only operation through which subtraction, multiplication and division can also be performed in 2's-complement system.

67

NUMBER SYSTEMS PROBLEMS

NUMBER-SYSTEM CONVERSION 2.1 Convert the following binary numbers to decimal. (a) 101 (b) 11011 (e) 0.1001 (e) 100011.11001

(d) 110110.10

(f) 101.001

2.2 Convert the following decimal numbers to binary. (a) 5

(b) 39

(e) 0.84

(f) 24.328

(e)

78

2.3 Convert the following binary numbers to octal. (a) 110 (b) 10110 (e) 110111.101 2.4 Convert the following octal numbers to binary. (a) 345 (b) 32.2 (e) 3276.2 (e) 5250

(d) 1110.1110 (d) BB

(d) 7.C

(d) 32.2

(d) A7.2

(f) D276

2.12 Convert the following octal numbers to hexadecimal. (a) 32 (b) 565 (e) 24.45 (e) 4320

(d) 524

(f) 8492

2.11 Convert the following hexadecimal numbers to octal. (a) 18 (b) 8.A (e) CB (e) 64AC

(d) 326

(f) 235.215

2.7 Convert the following binary numbers to hexadecimal. (a) 10110111 (b) 101.0111110 (e) 0.101101 2.8 Convert the following hexadecimal numbers to binary. (a) 89 (b) AB2 (e) 4CA (e) 2DE.3 (f) AB2.234 2.9 Convert the following hexadecimal numbers to decimal. (a) 20 (b) AB2 (e) 32BF (e) A364 (f) 9.3A 2.10 Convert the following decimal numbers to hexadecimal (a) 18 (b) 518 (e) 0.54 (e) 4312

(d) 4242

(f) 2.561

2.6 Convert the following decimal numbers to octal. (a) 12 (b) 187 (e) 0.56 (e) 9.32

(d) 11.111

(f) 240.22

2.5 Convert the following octal numbers to decimal. (a) 12 (b) 124 (e) 16.2 (e) 2642.6

(d) 425

(f) 6006

(d) 472.02

68

DIGITAL PRINCIPLES AND CIRCUITS

BINARY ARITHMETICS 2.13 Perform the following binary additions and check them by converting the binary numbers to decimal. (a) 1110 + 1011

(b) 1011.10 + 11110.01 (c)

10101 + 0.110

(d) 111.1 + 111.1

2.14 Perform the following binary subtractions and check them by converting the binary numbers to decimal. (a) 1100 -1001

(b) 111.1- 111.11

(e)

10110 -1010.1 (d) 1011.1- 111.1

2.15 Perform the following multiplications in binary system (a) 15x9 (b) 23x2.5 (e) 22xB.25

(d) 3.2x B.6

2.16 Perform the following divisions in the binary system using subtraction of divisor. (a) 28+12

(b) 6+4

(e) 52.2+22.0

(d) 75+35

OCTAL AND HEX ARITHMETICS 2.17 Perform the following octal additions. (a) 7+4

(b) 26+6.2

(e) 512.3+22.7

2.18 Perform the following hex additions. (a) 9+B

(d) 3.04 + 6.1

~.

(b) 2A+6.2

(e)

B.~\ + 0.A4

(d) AB + C.F

2.19 Perform the following octal subtractions (a) 74-36

(b) 24.2 - 15.6

(e) 322-37.1

(d) 0.26 - 3.2

(e)

(d) AF-6D

2.20 Perform the following hex subtractions (a) 9-3

(b) 5D-3.2B

7C-C2.5

2.21 Perform the following octal multiplications (through binary). (a) 5x6 (b) 5.4x52 (e) 3.2x7 (d) 362x13.6 2.22 Perform the following hex Ililultiplications (through binary). (a) 3x7

(b) 7.3DkE2

.

(e) ABx7C

(d) F.Ax2B7

COMPLEMENT'S ARITHMETICS 2.23 Find the 2's complements of the following signed binaries and write down their decimal equivalents. (a) 11000 (b) 1101001 (e) 110100 (d) 0100100 (e) 01001011

(n

010100Q1

2.24 Represent each of the followin~ decimals in 2's-complement system (a) -2 (b) +26 (e) -B5 (d) +74 2.25 How many bits (including the sign bit) are required to represent the decimals ranging from 0 to 999 in 2's-complement system? 2.26 What are the largest negative apd largest positive numbers which can be expressed in 2's-complement system using 10 bits? 2.27 Perform the following decimal additions in 2's-complement system. (a) (+4) + (+7) (b) (-8) + (-6) (e) (-9) + (+5) (d) (+9) + (-5)

NUMBER SYSTEMS

69

2.28 Perform the following decimal subtractions in 2's-complement system. (a) 8-5

(b) 3-9

(d) 68-50 16-22 2.29 Multiply the decimals 12 and -6 in 2's-complement system. 2.30 Divide decimal 28 with decimal 6 using subtraction in 2's-complement system. (c)

OBJECTIVE QUESTIONS

1 Binary equivalent of decimal 60 is (a)

11111

(b) 111100

(c)

111011

(d) 101110

(c)

216

(d) 220

(c)

300

(d) 400

(c)

57

(d) 103

2 Octal equivalent of decimal 142 is (a) 210

(b) 212

3 Hexadecimal equivalent of decimal 256 is (b) 200 (a) 100 4 Decimal equivalent of binary 111001 is (a) 43

(b) 61

5 Octal equivalent of binary 1011.10 is 15.6 Hexadecimal equivalent of binary 11000.110 is (a) 8.C (b) C.16 (c) B.18 Binary equivalent of octal 57.4 is (c) 1100.01 (a) 101111.100 (b) 101101.1 Decimal equivalent of octal 25 is (c) 3] (a) 11 (b) 21 Hexadecimal equivalent of octal 176 is (c) 7E (b) 6F (a) 6E Binary equivalent of hexadecimal 7E is (c) 11110000 (a) 01111110 (b) 11111000 Decimal equivalent of hexadecimal 11A is (c) 282 (b) 272 (a) 262 Octal equivalent of hexadecimal 7E is (c) 176 (b) 146 (a) 126 1's Complement of 101101 is (c) 101100 (a) 010110 (b) 010010 9's complement of decimal 495 is (c) 509 (b) 504 (a) 505 Binary subtraction 1111-0111 yields (b) 0110 (c) 0100 (a) 0111 Binary division 11110 + 110 equals (c) 101 (b) 110 (a) 100 Value of (15 + 17)8 in decimal is (c) 15 (a) 32 (b) 28 (a) 11.2

6 7 8 9

10 11 12 13 14

15 16 17

(b) 13.4

(c)

(d) 17.8 (d) 18.C (d) 11001.00 (d) 41 (d) 7F (d) 11100000 (d) 292 (d) 196 (d) 110110 (d) 503 (d) 1000 (d) 111 (d) 35

DIGITAL PRINCIPLES AND CIRCUITS

70 18 Value of (28 + Ah6 in octal is (a) 42 (b) 52

(d) 62 19 Conversion of decimal to hex requires successive division by (a) 2 (b) 8 (c) 16 (d) m Conversion of decimal to octal requires successive division by (a) 2 (b) 8 (c) 16 (d) 21 2's-complement representation of decimal -6 is (a) 1010 (b) 0010 (c) 0110 (d) m 2's-complement representation of decimal 12 is (a) 11001

(b) 01100

(c)

(c)

10111

70

32 32 0111

(d) 11000

23 Total number of values (including the sign bit) in 2's complement system using N magnitude bits is (a) 2N+l

1 (b) 9 (c) 17 (b)

(b) 2 N - 1

2 (c) 10 (b) 18 (d)

3 (a) 11 (c) 19 (c)

(c) ~+1

ANSWERS 4 (c) 5 (b) 12 (c) 13 (b) 20 (b) 21 (b)

(d) 2N-1

7 (a)

8 (b)

14 (b)

15 (d)

16 (c)

2}. (b)

23 (a)

6 (d)

CHAPTER

3

BINARY CODES 3.1 INTRODUCTION

The data prior to be handled in the input/output units of a computer may be in different formats, such as numerals, alphabets, or some special symbols. It is therefore essential~y needed to convert these data into a single format of binary, which is the only format that a computer can understand. This binary format can be expressed in a number of different codes, called binary codes. Formation of binary codes can be done in a large number of different ways, but some of them are very important and used so frequently. In this Chapter, we discuss these codes, which include the straight-binary code, natural BCD (8421) code, excess-3 code, gray code, parity-check code, biquinary code, alphanumeric code and the ASCII code. 3.2 STRAIGHT-BINARY CODE

When a decimal number as a whole is expressed in the true binary format, it may be called as straight-binary code. For example, we can write the code 0001 for decimal 1, code 0010 for decimal 2, or code 1101 for decimal 13. This code is so named because it advances in a straight forward manner by adding a 1 in the preceding number. 3.3 BCD (8421) CODE

BCD is the abbreviation, for the term Binary-Coded-Decimal, which means the coding of a decimal into binary. In the BCD code, instead of converting the decimal number as a whole, we replace e a c h decimal digit by the equivalent 4-bit binary Sixteen group. Thus, the BCD code for decimal 34 is 0011 0100 whereas its binary code is 100010. possible 4-bit groups Formation of binary groups using four bits can be done in sixteen different ways. Out of these sixteen 4-bit groups, a~ given in Fig. 3.1, ~e can choose any ten groups to represent the ten decimal digits (0 through 9). Since there can be many ways to choose a particular set of ten groups, an equal number of BCD codes would arise.

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Ten Natural BCD codes

Six forbidden groups

Fig. 3.1 Sixteen possible 4-bit groups

DIGITAL PRINCIPLES AND CIRCUITS

72

NATURAL BCD CODE I:Natural BCD code, or simply termed "BCD", consists of the first ten groups of the sixteen ·4-bit groups given above. The remaining six groups (1010, 1011, 1100, 1101, 1110, 1111) are excluded from this code, as the forbidden groups. If a forbidden group appears in any BCD operation, the latter goes to an invalid result. BCD code with the lowest group of 0000 and the highest group of 1001 is identical to the straight binary code upto decimal 9. However, the two codes differ when the decimal number exceeds 9, as is shown in Table 3.1. in which each decinial digit is expressed by the corresponding 4-bit group. Table 3.1 BCD Codes Decimal

Natural BCD (8421) Code

Decimal

Natural BCD (8421) Code

0 1 2 3 4 5 6 7 8

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

10 11 12 : 25 26 : 375 376 :

00010000 00010001

9

00010010 : 00100101 00100110 : 0011 0111 0101 0011 0111 0110 :

Natural BCD code is a weighted code, and therefore it is also known as 8421 code, in which the bit-positions, from MSB toward LSB in each 4-bit group, are assigned with the fixed weights of 8,4,2,1 (23,22,2 1,20). Using these weights, the decimal digit represented by a particular 4-bit group can be realised by summing the weighted values of the bits. This is shown below for the 4-bit group of 1000 representing decimal 8. Given 4-bit group Weights Weighted values Decimal values Decimal digit

= = = = =

1 8. lx8 + 8 + 810

0 0 0 2 4 1 Ox4 + Ox2 + Ox1 0 + 0 + 0

NOTE BCD (8421) code is commonly used in the input and output operations of digit computers. It is also used to represent decimal digits in digital calculators, voltmeters and counters.

Example 3.1 Express the decimal 927 in BCD code Solution Replacing each decimal digit with the equivalent 4-bit group, we write as: 9 J, 1001 Hence,

2 J, 0010 92710

7 Decimal digits J, 0111 BCD code groups

= 10010010 0111BCD

BINARY CODES

73

Disadvantage

A problem arises in the addition of BCD numbers when the decimal sum exceeds 9. In all such additions, the BCD sum becomes invalid, either by the presence of a forbidden group in it, or otherwise. See Example 3.2. Example 3.2 Add decimal 12 with decimal 9 in binary and BCD codes. Explain the error arising in the BCD addition. Solution Binary addition Decimal addition BCD addition J2 00010010 1100 +1001 +9 +1001 21 Sum 0001 1011 = 10101 It can be noted here that the BCD sum of 00011011 does not represent the decimal sum of 21, because the 1011 group appearing in it is a forbidden group, which is not allowed to appear in any valid BCD code. Hence the BCD sum is taken to be erroneous whenever the decimal sum exceeds 9. Decoding

Converting a BCD (8421) code into decimal is called decoding. While decoding, we arrange the given BCD code in 4-bit groups and then replace each group by the corresponding decimal digit, as shown below for the 8421 code 1000 0101 0110 0011. 1000

0101

0110

0011

'-.,--J

'-.,--J

'-.,--J

'-.,--J

I

Thus,

I

\

\

1000

0101

0110

0011

+

+

+

+

8 1000

5 0101

Given 8421 code 4-Bit groups

6 3 Decimal digits 0110 OOllBCD = 856310

Characteristics of BCD (8421) Code 1. This code is convenient in converting to and from decimal. 2. This code is identical to straight binary code upto decimal 9, but differs beyond it, 3. This code is a weighted code that uses the binary weights of 8, 4, 2, 1. 4. This code is disadvantageous in that the BCD addition is invalid when the decimal sum exceeds 9, as explaineti in Example 3.2.

3.4 EXCESS - 3 CODE Excess-3 code is the modifjed BCD code in which the problem of adding 8421 numbers whose decimal sum exceeds 9, has been removed. To obtain this code, we add decimal 3 to each decimal digit and convert each sum into equivalent 4-bit-group. This procedure is illustrated below for the conversion of decimal 5 and decimal 29 into excess-3 codes.

74

DIGITAL PRINCIPLES AND CIRCUITS

(a)

5 +3 8

Given decimal Add 3 Sum

1000

Binary group

t

5 10

Thus,

(b)

=1000excess _ 3

+3 5

9 +3 12

0101

1100

2

t

2910

Thus,

Given decimal 29 Add 3 to each digit

t Excess-3 groups

= 01011100excess _ 3

In (b) above, it is worth noting that instead of raising a carry of 1 from the sum of 9 and 3 to the higher column, the sum of 12 is left intact and converted to binary group 1100. Table 3.2 Excess-3 code and Forbidden groups

Excess-3

Decimal

Forbidden groups

0000 0001 0010 /

0 1 2 3 ,4 5 6

7 8 9

I

0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

"

Table 3.2 shows the ten 4-bit groups used in the excess-3 code for the ten decimal digits (0 through 9), as obtained by using the foregoing procedure of adding 3 and converting to binary. Note that this set often groups is different from the 8421 code, because the groups included in it are the middle ten groups of the sixteen 4-bit groups. The six forbidden groups excluded from this code and given in the last column, are the first three and the last three groups. If any of these groups appears in any excess-3 operation, it would make the result invalid. Decoding To decode an excess-3 number back into decimal, we follow the reverse procedure, in which we subtract 0011 (3) from each 4-bit group of the given excess-3 number, and then

75

BINARY CODES

each obtained group is replaced by its equivalent decimal digit. Example 3.3. illustrates this procedure. Example 3.3 Decode the following excess-3 numbers into decimal. (a) 01101100 (b) 1011 00111000 Solution (a)

0110 -0011 0011

~

3 0110

Thus,

(b)

Thus,

1011 -0011 -1000

0011 -0011

~

~

8 1011

0 0011

-0000

1100 -0011 1001

~

~ l1OOexcess-a 1000 -0011 0101

~

5 1000excess-3

Given excess-3 group Subtract 3 Equivalent binary groups Converting to decimal Decimal digits =39 10 Given excess-3 group Subtract 3 Equivalent binary groups Converting to decimal Decimal digits =80510

Self-complementing Code

Excess-3 code is a self-complementing code. In such a code, we directly get the 9's complement (in excess-3 form) of the encoded decimal, simply by complementing the corresponding excess-3 code. For example, to obtain the 9's complement of decimal 2, we complement its excess-3 code 0101. This directly gives 1010 as the excess-3 code for the 9's complement of decimal 2. In the similar way, decimal 24 (excess-3 code 0101 0111) will have its 9's complement as 1010 1000 in the excess-3 code form. This is further illustrated in Example 3.4 along with decoding also. Example 3.4 Obtain 9's complement of decimal 35 using excess-3 code Solution First we convert 35 into excess-3 equivalent which is then complemented to obtain the 9's complement. 5 Given decimal digits 3 Add 3 +3 +3 Encoding to 6 8 excess-3 ~ ~ Converting to binary groups 0110 1000 Excess-3 for 35 ~ ~ Complementing excess-3 for 35 1001 0111 Excess-3 for 9's complement of 35 ~ ~ Converting to decimal Decoding to { 9 7 Equivalent decimal digits Decimal -3 -3 Subtract 3 6 4 9's complement of 25

Hence,

9's complement of 3510 = 1001 0111excess-a = 6410

76

DIGITAL PRINCIPLES AND CIRCUITS

Excess-3 Addition Excess-3 numbers are added exactly as we add in binary. There can be two cases: Case 1 When the sum 'of decimal digits is 9, or less (no carry): we add the excess-3 numbers in each column of decimal digits, and then subtract 9011 (decimal 3) from each sum, to get the result. This is illustrated below. (a) Adding 3 and 5 Decimal 3 0110 Excess-3 for decimal 3 Excess-3 for decimal 5 Decimal +5 +1000 8 1110 First sum Decimal -0011 Subtract decimal 3 1011 Excess-3 sum for decimal 8 (b) Adding 26 and 53 Excess-3 for decimal 26 Decimal 26 0101 1001 Excess-3 for decimal 53 Decimal +53 0110 +1000 1101 First sum Decimal 79 1111 -0011 -0011 Subtract decimal 3 in each column - - Excess-3 1010 sum for decimal 79 1100 Case2 When the sum of decimal digits exceeds 9 (a carry arises) : we add the excess-3 numbers raising a carry to the higher column wherever needed. Then, we add 0011 (3) to the first sum in the column raising a carry, and subtract 0011 (3) from the sum in the column not raising a carry. This is illustrated below for the addition of decimals 38 and 47. Clumn Column

A

B

011~ ta~~i1

Excess-3 for 38 + 0111 1010 Excess-3 for 47 1110 0101 First sum - 0011 + 0011 Subtract 3/add 3 1011 1000 .Excess-3 sum for 85 Hence, 3810 + 4710 =10111000excess-a It may be noted here that 0011 (3) is added to the first sum in column B because it raises a carry into column A, while 0011 (3) has been subtracted from the first sum in column A because it does not raise any carry. Decimal Decimal Decimal

38 +47 85

Example 3.5 Add decimals 245 and 378 in excess-3 codes, and verify the result by decoding the sum.

Solution Decimal 245 Decimal +378 Decimal 623

Hence,

I I + - Carry 0101 0111 1000 -Ij 0110 1010 1011 1100 0010 0011 - 0011 + 0011 + 0011 1001 0101 0110

24510 + 37810

Excess-3 for 245 Excess-3 for 378 First sum Subtract 3/add 3/add 3 Excess-3 sum for 623

= 62310 = 1001 0101 0110excess-3

71

BINARY CODES

To verify the above excess-3 sum, we decode it by subtracting 0011 (3) from it and converting to decimal? That is, Excess-3 sum for 623 1001 0101 0110 -0011 -0011 -0011 Subtract 3 -- -Equivalent binary groups 0\10 ~10

,11

6

3

2

Decimal digits

Characteristics ofExcess-3 Code 1. In excess-3 code. each 4-bit group is equivalent of a decimal which exceeds the encoded decimal by 3. 2. Excess-3 code is an unweighted code in whio-- F=A

OV

(a)

Fig. 4.7

B1D o

(b)

(e)

INVERTER circuit, (b) its truth table and (c) logic symbol.

When the input A is OV (low), there is no base current, and hence no collector current. This makes the transistor to become cutoff and the output to rise to 5V (high). When the input A is 5V (high), a sufficient base current flows through the properly chosen input resistor R, so that the transistor goes into saturation. This causes the output to fall to OV (low). Writing logic 0 for OV and logic 1 for 5V, the truth table can be realized as described earlier. NOTE NOT operation is sometimes termed as unary operation because it is performed on a single variable.

Example 4.6 Explain the electrical signal which is expressed with the binary 101101. If this signal is applied to a NOT gate, what would be the output signal? Solution The electrical signal as represented by the given binary is a train of pulses with 1 for high voltage and 0 for low voltage in the positive-logic representation. When this signal is applied as input to a NOT gate, it gets INVERTed (complemented) giving the output signal as 010010. Example 4.7 Write down the logic expression for the output Y in the logic circuit of Fig. E 4.7 given below. Evaluate Y when the input signals are: A =1, B =0, C =0 A B C -_______

A

Fig. E 4.7

Solution Logic expression for Y is obtained in the following steps: (i) ANDing the inputs A, B and C with the AND gate, gives ABC.

INVERTing the input A with the INVERTER, gives A. \ (iii) oRing the signals ABC ahd A by the OR gate, finally gives ~e output as (ii)

Y = ABC+A

LOGIC GATES AND IC FAMIUES

103

Putting the given values of A, Band C in this expression, we have Y = 1·0· 0+ 1 = 0+0 =0

Double Inversion When the output of a single INVERTER is applied to another INVERTER, the latter INVERTER also inverts the inverted signal, thereby generating the same signal that was applied to the first INVERTER. In this process of double inversion, the two successive inversions of a signal cancel out eachother's effect, and the original signal remains unaltered. This operation is equivalent to a nil operation. In other words, whenever two INVERTERs appear to be connected in series, they must be treated as cancelled, and the line connecting them be considered as a short-circuit (direct connection), as shown in Fig. 4.8.

A----------------~·------------------A Direct line

Fig. 4.8 Double inversion equals nil operation

IC INVERTERs Modern Ie technology has made it possible to fabricate several INVERTERS on a single package. Several such packages are commercially available. For example, the Hex 7404 package incorporates six INVERTERS. It has 14 pins including 2 pins each for power supply and ground. Another package is the Hex CD 4049 which also has six INVERTERs with 16 pins. The pin diagrams of these packages are given in Appendix A in Figs. 3 and 12, respectively. 4. 11 LOADING EFFECT ( FAN-OUT)

When several INVERTERs/gates are connected to the output of a single INVERTER/gate, as shown in Fig. 4.9, its voltage output no longer remains constant, but decreases, and- the corresponding output current increases. This effect, referred to as loading effect, increases with the increasing number of INVERTERs (or gates) connected as loads across the first INVERTER/gate referred to as driver. The cause of this situation is obviously the reducing value of effective impedance of all the loads which exist in parallel to eachother. To prevent the load current of driver stage from going beyond its prescribed limits, it therefore becomes necessary to impose a restriction on the number of loads to be connected across the driver. The maximum allowed number of loads that can be connected across a gate is referred to as "fan-out" of that gate. Its value is specified for each gate or INVERTER. For example, if a gate has a fan-out of 5, then not more than 5 load gates must be

104

DIGITAL PRINCIPLES AND CIRCUITS

Driver

Load

Driver

Driver Loads (b) Two loads

(8) Single load

Loads (c) Three loads

Fig. 4.9 Loading effect

connected to its output. Note that the increasing number of loads increases propagation delay of the circuit. Buffer I Driver A buffer, or driver, or buffer I driver is a single-input-single-output circuit which is designed to provide a larger output current and/or voltage than exists in a normal circuit. Such circuits are often needed to drive heavier loads, such as indicator LED or an incandescent lamp, that requires larger currents and lor voltage for their proper operation. To meet this requirement, buffers are designed with transistors of larger-thannormal size. Inverting and non-inverting buffers are discussed in Sec. 4.38. IC buffer units are available with totempole, open-collector and tristate outputs that allow heavy output currents. For example, the 7406 is a popular package of six INVERTERs with open-collector outputs. It can provide a current of 40 rnA and can handle voltages upto 30 V. The 7437 is a quad NAND buffer which has four 2-input NAND gates, each one optimised to provide an output current of 3 times as high as its input current. Another package is the Motorola MC789P which has six INVERTERs with active-low outputs. Each input pin has a load factor of 3, and each output pin can drive 16 loads, i.e.a maximum of 5 INVERTERs can be connected to each output pin (because 16/3 = 5.3 means maximum of 5 INVERTERs.

4.12 REPRESENTAnON OF BINARY NUMBERS AS ELECTRICAL SIGNALS Any digital information that moves in or out of a computer, consists of binary numbers which are formed using the bits 0 and 1. In the moving information, it is not these bits which move, but it is the two electrical signals that move along the circuits, representing the two bits. That is, one electrical signal represents a 0 and the other represents a 1. These signals are such as to be easily identified from eachother, and can be selected from the following types. In the dc logic systems, which usedc voltages, we can select any two of the three types of voltages (positive voltage, negative voltage and zero voltage) to represent the bits 0 and 1. In the ac logic systems, which use voltage pulses, we can select any two of the three types of pulses (positive pulse, negative pulse, and no pulse) to represent these bits. Positive and Negative Logic Representation Using the signals mentioned above the bits 0 and 1 can be represented in two ways-one is called positive-logic representation, and the other is called negative-logic representation.

LOGIC GATES AND IC FAMILIES

105

Either of these two representations can be adopted for a given digital circuit, which will be according-Iy called as a positive-logic circuit, or a negative-logic circuit. These two kinds of reprC:dcntations are explained below in the cases of dc and ac systems. DC Systems

In the positive-logic representation in a de system, a higher voltage level is used to represent a 1, and the lower voltage-level is used to represent a O. In the negative logic representation, we go the reverse way, i.e. a o o higher voltage-level is used for 0 and the lower +5V voltage level for 1. For example, if we use +5 V for 1 and OV for 0 in one case, or +5 V for 1 and OV 0 -5 V for 0 in another case, both are the examples of positive logic representation. But, if we use o -5V o V for 1 and +5 V for 0, or -5 V for 1 and + 5V for Negative Positive 0, they would come under negative-logic logic logic representation. These are also illustrated in Fig. 4.10 Positive and negative logics in a Fig. 4.10. dcsystem

ACSystems In a positive-logic ac system, we use a positive pulse to represent 1 and no-pulse to represent O. We can also use no-pulse for 1 and negative pulse for 0, as illustrated in Fig. 4.11 (a). In the negative-logic ac system, we use the reverse representation, as illustrated in Fig. 4.11 (b ). Positive edge Positive pulse

o

No pulse

Positive edge

o

Negative pulse

Negative edge Negative edge

(a) Positive logic Positive pulse

0

o

o

I---

No pulse

o

Negative pulse (b) Negative logic

Fig. 4.11 Positive and negative logics in an ac system

106

DIGITAL PRINCIPLES AND CIRCUITS

Instead of using the whole pulse, only its edges are frequently used to represent the bits o/'and 1. In the positive logic, the rising (or positive) edge of the pulse is used for 1, and the falling (or negative) edge is used for O. In the negative logic, we use the reverse representation, i.e. the rising edge for 0 and the falling edge for 1, as illustrated in Figs. 4.11(a) and (b). Table 4.1 summarises all the possible ways of positive logic representation in the de and ac systems each.

Table 4.1 Positive-logic representation (a) In a de system

Logic 1

Positive voltage

Zero voltage

More PosL voltage

Less Neg. voltage

Logic 0

Zero voltage

Neg. voltage

Less Posi. voltage

More Neg. voltage

(b) In an ac system

Logic 1

Positive pulse

No pulse

Rising (positive) edge

Logic 0

No pulse

Negative pulse

Falling (ne~~tive) eage

Example 4.8 Mention the kind of logic (positive or negative) to which each of the following voltage levels belong in a de system. (a) -2 V (1),3 V (0)

(c) -5 V (0), -1.5 V (1)

(b) 1.3 V (1), -1.3 V (0)

(d) -2.5 V (0), -8 V (1)

Solution Each of the given voltage-levels belong to the logic as given below. (a) Negative logic

(c) Positive logic

(b) Positive logic

(d) Negative logic

Example 4.9 Sketch the signal waveforms which represent the following binary numbers in a positive-logic de system using the voltage levels of +5 V and -5 V, and in a negativelogic ac system using the positive-pUlse and no-pulse signals : A =11010010 and B =19011101

Solution Since the de system uses positive logic, therefore, using +5V for logic 1 and -5 V for logic 0, the waveforms for the given binary numbers are sketched in Fig. E 4.9 (a). The ac system uses negative logic, therefore, we use no-pulse for logic 1, and positive pulse for logic o. The w~veforms thus obta1ned are sketched in Fig. E 4.9 (b).

LOGIC GATES AND IC FAMIUES

107

+5VI---';"'"

OV

------. -- ----- ---- ----------- ---- --------

o

-fN

o

Signal A= 11010010

o

o

+5V

OV

-5V

--- ---------- ---------------- ----- -------

o

Signal B.: 10011101

o

0

(a) Signal wave-forms in positive-logic de system

o

o

Positive pulse

o

o

No pulse )--_ _....1 Positive pulse No pulse

o

o

0

-----------'-----_......

Signal A= 11010010

Signal B = 10011101

(b) Signal waveforms in negative-logic ae system

Fig. E 4.9

4.13 POSITIVE AND NEGATIVE GATES A positive gate is one that uses positive logic. Similarly, a negative gate is one that uses negative logic. The performance of a logic gate, or INVERTER, or any other logic system essentially depends on which kind of logic (positive or negative) is being adopted for its operation. A gate/circuit using one kind of logic behaves in a different way with.the other kind of logic. For example, if we compare the truth tables of the positive AND-gate and a negative NOR-gate, the outputs produced by each gate for similar inputs are found to be identical. This means that a positive AND-gate acts as a negative NOR-gate. Its viceversa is also true, i.e. a negative AND-gate acts as a positive NOR-gate. In the same manner, a positive NAND-gate is equivalent to a negative OR-gate, and vice versa. Also, a positive INVERTER using pnp transistor behaves as a negative INVERTER using npn transistor.

This change of behaviour is also illustrated below : Positive AND gate Negative NOR gate Positive OR gate Negative NAND gate Positive NANn gate Negative OR gate

DIGITAL PRINCIPLES AND CIRCUITS

108

Positive NOR gate Positive INVERTER (PNP) Positive INVERTER (NPN)

Negative AND gate Negative INVERTER (NPN) Negative NAND (PNP)

Thus, it is not only these gates, or INVERTERs that change their performance but this is also true for every logic system when we change the logic. Hence, it becomes essential that every logic system must be labelled with the kind of logic (positive or negative), whichever is ar" opted for that system. Conversion of one kind of logic to the other, in a given logic system, is done by reversing the logic levels, for which several alterations, such as reversing of the polarity of circuitelements and interchanging of the power supply terminals have also to be made. Fig. 4.12 shows the conversion of a positive AND-gate and a positive OR-gate into the corresponding negative gates usiilg the negative logic: OV (1), 5V (0) in place of the positive logic: 0 V (0),5 V(1) for which the polarity of diodes is reversed and power supply terminals are interchanged. +5V

1

Ao--K 1-----1--0 F = AS

1

B

\'

.

o-~IC

~-......-QF=A+B

B

Logic levels

Logic levels

-= OV (b) Negative AND gate

(a) Positive AND gate

+5V

Ao---t

1.

~-

__--o F=A+B

o

1

B

Logic levels

-= OV (c) Positive OR gate

A o---fC I-~--O F= A B

Bo---K

Logic levels

(d) Negative OR gate

Fig. 4.12 Conversion of Positive gates into Negative gates

4.14 NAND GATE A NAND gate performs NAND (NOT-AND) operation, which is just inverse of the AND operation. That is, the output in this operation goes low when all the inputs are high. In other words, this equals the logical statement: "Output goes high when any or all the inputs are low". Like other gates, a NAND gate can also have two or more inputs, and a single

LOGIC GATES AND IC FAMIUES

109

output. Fig. 4.13 (a) shows the logic circuit of a 2-input NAND gate which is formed by connecting an INVERTER across an AND gate. In this circuit, inputs A and B are first ANDed into AB, and then INVERTed to provide the output AB. Because the output of a NAND gate is just the complement of the output AB of AND gate these two gates are referred to as complementary gates to each other. The logic symbol for NAND gate, shown in Fig. 4.13 (b), is just the symbol of AND gate with a small circle attached at its output which indicates inversion. The operation of this gate is described in the truth table of Fig. 4.13 (c).

A"

B

[t>-~-~1 I

I

I : , I I .... __ .......................... __ .. .

NAND (a) logic diagram

F=AB

=A+ B-

:~F Denotes inversion (b) Logic symbol

A

B

AB

-

-A+B-

0

0

1

1

0

1

1

1

1 1

0

1

1

0

1 0

(c) Truth table

Fig. 4.13 NAND gate logic diagram, logic symbol and truth table The Blooean equation fOr NAND operation can be written as F =- AB = X + jj

(using DeMorgan's theorem)

The former equation above is read as "F equals not (A and B), which means that the output F of NAND gate is equal to the INVERTed value of AB as a whole. From the second equation, - the output F also equals A + B according to DeMorgan's theorem. If we give 0 and 1 logic values to each variable A and B in both the above equations, the same value of F is obtained from each equation, as listed in the truth table.

NAND as INVERTER , A NAND gate turns into an INVERTER when ali its inputs are connected together into a single input. This result is obviously given in the first and fourth rows of the truth table. That is In the first row: A = B = 0, gives F = 1 (INVERTed value of A = B = 0) In the fourth row : A = B = 1, gives F = 0 (INVERTed value of A =B =1)

Thus, whenever a single-value input is applied to a NAND gate, it is INVERTed at the output. That is, a single-input NAND gate acts as an INVERTER. NOTE IC NAND gate circuits are discussed in detail under different logic families in the later part of this Chapter.

4.15 NOR GATE A NOR gate performs NOR (NOT-OR) operation, which is just inverse of OR operation. That is, the output in this operation goes low when any or all the inputs are high. This equals the logical statement "Output goes high when all the inputs are low". Like other gates, a NOR

110

DIGITAL PRINCIPLES AND CIRCUITS

gate also can have two or more inputs, and a single output. Fig. 4.14 (a) shows the logic circuit of a !2-input NOR gate which is obtained by connecting an INVERTER across an OR gate. In this circuit, the inputs A and B are first ORed into A + B which is then INVERTed to provide the output A + B. Because the output of a NOR gate is just the complement of the output of an OR gate, these two gates are sai.d to be complementary to eachother. The logic symbol for NOR gate, shown in Fig. 4.14 (b) is just the symbol for OR gate with the circle of inversion attached to its output. The truth table of this gate depicting its operation, is given in Fig. 4.14 (c). A

B

0

0

1

1

0

1

0

0

1

0

0

0

1

1

0

0

A+B

A+B

~--------------------.

A~' A • + B :• , F=AB ' --B L___________________ !, =A+

B

:~F Denotes inversion

NOR (8) Logic circuit

(b) Logic symbol

(c) Truth table

Fig. 4.14 NOR gate logic diagram, logic symbol and truth table The Boolean equation for NOR operation can be written as F =A+B =AB

(using DeMorgan's theorem)

The first equation above is read as "F equals not (A or B), which means that the output F of NOR gate is equal to the INVERTed value of (A + B) as a whole. From the second equation, the output F also equals AB according to the DeMorgan's theorem. If we give 0 and 1 logic values to each variable A and B in both the above equations, the same values of F are obtained from each equation, as listed in the truth table.

NOR AS INVERTER Like the NAND gate, a NOR gate also acts as INVERTER when all its inputs are connected together into single input. This behaviour can be observed in the first and fourth rows of truth table in Fig. 5.14 (c), in which the output is F = 1 when the inputs are 0 each, and the output is F = 0 when the inputs are 1 each. Thus, the similar inuts provide an opposite output. That is, a single-input NOR gate turns into an INVERTER. NOTE 1 The actual circuits for IC NOR gates under different logic families are discussed in the later part of this Chapter.

2 NAND and NOR gates are not complementary to eachother. Example 4.10 Draw the truth table for each of the 3-input NAND gate and the 3-input NOR gate.

Solution The required truth tables for the 3-input NAND and NOR gates are drawn below. Each truth table has 23=8 rows of input-combinations with the lowest word as ABC =000 and the highest as ABC = 111.

LOGIC GATES AND IC FAMIUES

111

NAND A

B

C

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

NOR

-F=ABC 1 1 1 1

1 1 1 0

A

B

C

F=A+B+C

1 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 0 0 0

1

Example 4.11 Evaluate the outputs in a NAND gate and a NOR gate when each one has the inputs: A = 0, B = 1, C = 1. Solution Output of NAND gate is given by F= ABC

= A+B+C = 0+ 1+ 1 = 1+0+0 =1

Output of NOR gate is given by F=A+B+C =A.B.C =0.1.1

= 1.0.0 =0

4.16 BUBBLED GATES A bubbled gate is a basic gate that accepts inputs in the INVERed form. Such a gate using an AND gate as the basic gate and an INVERTER to invert each input, is shown in Fig. 4. 15 (a), and is named as 2-input bubbled AND-gate. In this gate the inputs A and B are first INVERTed and then ANDed into A Ii as the output. In the logic symbol of this gate, given in Fig. 4.15 (b), the triangle of INVERTER is ignored, while its small circle (bubble) is shifted to each input of the basic gate. Each bubble in the symbols of bubbled gates indicates

:~AB ~ (a) Logic circuit (Bubbled AND-gate

=5ubbles

A

B

AS

A-f'....._ -

--

B~A+B=AB

(b) Logic symbol (Bubbled AND-gate

Fig. 4.15 Bubbled AND gate equals NOR gate

(c) NOR gate

112

DIGITAL PRINCIPLES AND CIRCUITS

inversion. The circuit and symbol for the bubbled OR-gate are similarly shown in Fig. 4.16.

A~B

_

Ubbles

__ A+B

B (a) Logic circuit (Bubbled OR-gate

- £=A

__

B

A+B

A~

__

_

_

B~AB=A+B (c) NAND gate

(b) Logic symbol (Bubbled OR-gate

Fig. 4.16 Bubbled OR-gate equals NAND gate As is obvious from Fig. 4.15, a bubbled AND-gate produces the same output A + B as that of a NOR gate, therefore these two gates are equivalent of eachother. Similarly, from Fig. 4.16, a bubbled OR-gate is equivalent to the NAND gate because they both produce the same output AB.

Significance Bubbled gates are significant because their formation is such that it directly applies the DeMorgan's theorems. For example, on applying the inputs A an~ B~o a bubbled AND-gate, we directly get the output A + B , as per the DeMorgan's theorem (A . B =A + B) without any need of extra INVERTERs. Similarly, the output AB produced by a bubbled OR-gate conforms to the other DeMorgan's theorem (A + ii = AB) . Bubbled gates are also significant because they can directly determine the active status of their inputs and output by the presence or absence of the bubble on the gate symbol. That is, when a bubble is present on the input or output of the gate symbol, the corresponding input or output signal is active-low, and when it is absent, the corresponding signal is activehigh, as illustrated in Fig. 4.17 for the NAND symbols in standard and bubbled forms.

4~ ! Active-low

Active-high (a) Standard NAND

Fig. 4.17

Active-~gh

M-

Active-low

Active-high

(b) Bubbled OR

and active-low status in NAND gates

Bubbled NAND and bubbled NOR gates

A bubbled NAND-gate with the inputs A and B produces an output of A

ii, i.e. A

+ B which is

the same as that of an OR gate, as shown in Fig. 4.18 (a). Thus, the bubbled NAND-gate is equivalent to an OR gate. Similarly, a bubbled NOR gate is equiValent to an AND gate because both of them produce the same outputAB, as shown in Fig. 4.18 (b).

LOGIC GATES AND IC FAMIUES

(a)

113

;=0--

AB=A+B

;=L)-A+B

Bubbled NAND

OR

;=D-

AB

AND

Bubbled NOR

Fig. 4.18 Bubbled NAND and NOR gates 4.11 NAND and NOR as UNIVERSAL GATES

The NAND and NOR gates are considered as universal gates because any other gate or Boolean expression can be realized by connecting only the NAND gates, or only the NOR gates. Realization of the basic AND, OR, NOT gates is described below, whereas that of the Boolean expressions is discussed in Chapter 5. (a) AND, OR, NOT realisation using NAND gates

How to form the AND, OR and NOT gates using only the NAND gates, is illustrated in Fig. 4.19, and explained below. To form an AND gate, we need two NANDs. The first NAND provides the output AB which is then INVERTed into AB by the second NAND acting as INVERER (with the inputs joined together into a single input). To form an OR gate, we need three NANDs. The inputs A and B are first INVERTed into X and Ii by the two NAND INVERTERs, which are then NANDed into A + B by the third NAND. To form a NOT gate or INVERTER, we join all the inputs of a NAND gate together into a single input. This single-input NAND gate INVERTs the input A into X. A

Fonnation of AND gate

B

D

AB

A

Formation of OR gate

D - - - A+B

B

Formation of NOT gate

Fig. 4.19 Formation of basic gates using NAND gates

114

DIGITAL PRINCIPLES AND CIRCUITS

, (b) AND, OR NOT realisation using NOR gates

Formation of each basic gate using only the NOR gates is illustrated in Fig. 4.20. To form an AND gate needs three NORs, of which two are used as INVERTERs for each input A and B, and the third one produces the outputAB. To form an OR gate requires two NORs, of which the first one turns the inputs A and B into A + B which is INVERTed by the second NOR into the output A + B . To form a NOT gate, a single NOR gate acts as an INVERTER by j-oining together its inputs.

Formation of AND gate

A--...--\

AB A---.----\

Formation of OR gate

;____DX+B

Q)---A+B

Formation of NOT gate

Fig. 4.20 Formation of basic gates using NOR gates

4.18 XOR and XNOR GATES An XOR (exclusive-OR) gate is basically a 2-input OR gate, which does not produce a high output when both the inputs are high. Because this gate operates under all the operating conditions of the OR gate, except (excluding) the one described above, it is named as exclusive OR gate. The resulting logical statement for this gate can therefore be written as : "The output goes high when both the inputs are dissimilar", i.e. both are neither high, nor low. An XNOR (exclusive-NOR) gate is basically a 2-input NOR gate which excludes the condition -in which a low output is produced when both the inputs are high. This leads to the logical statement as: "The output goes high when both the inputs are similar ," i.e. both high, or both low.

Note that the XOR and XNOR gates are complementary to eachother, because the output of one is complementary to that of the other. Detailed discussion of these gates is given in Chapter

6. 4.19 CONCISE ACCOUNT OF LOGIC GATES

A summarised account of all the logic gates discussed so far, containing the gate symbols, logic functions and truth tables for their comparison,_ is given in Fig. 4.21. for the basic gates, and in Fig. 4.22 for the bubbled gates.

LOGIC GATES AND IC FAMIUES Logic symbol

Gate

115 Logic function

AND

~=D-

F=A.B

OR

~=D-

F = A+B

NOT

A--{>-

F=A

NAND

~=D-

- F=A.B=A+B

NOR

~=D--

F=A+B=A.B

XOR

~=D-

r = AE!) B = AB+AB

XNOR

~=D-

F= A 0B

-

- -

-

= AB+AB

A 0 0 1 1 A 0 0 1 1 A 0 1A 0 0 1 1 A 0 0 1 1 A 0 0 1 1 A 0 0 1 1

Truth table B 0 1 0 1 B 0 1 0 1

B 0 1 0 1 B 0 1 0 1 B 0 1 0 1 B 0 1 0 1

F 0 0 0 1 F 0 1 1 1 F 1 0 F 1 1 1 0 F 1 0 0 0 F 0 1 1 0 F 1 0 0 1

Fig. 4.21 A concise account of basic gates Logic symbol

Gate

Bubbled

AND Bubbled

OR Bubbled

NAND Bubbled

NOR

Logic function

;=D-

F = A. B

~=D-

F= A+B

;=0-

F= A·B=A+B

~=V-

F=

- -

-

-

--

-A+B = AB

Fig. 4.22 A concise account of bubbled gates

Truth table A 0 0 1 1 A 0 0 1 1 A 0 0 1 1 A 0 0 1 1

B 0 1 0 1 B 0 1 0 1 B 0 1

0 1 B 0 1 0 1

F 1 0 0 0 F 1 1 1 0 F 0 1 1 1 F 0 0 0 1

116

DIGITAL PRINCIPLES AND CIRCUITS

4.20 DIGITAL ICs

A digital Ie (integrated circuit) is fabricated on the surface of a very small silicon chip using the advanced photographic techniques. These circuits are called as "integrated" because the elements, such as diodes, transistors, resistors and gates, etc. are fabricated as an integral part of the chip. These circuits are totally different from the discrete circuits which are made by assembling the lumped components connected with eachother. After fabrication, the IC chip is encapsuled in a plastic, or metal container, and external leads are taken out from the selected points in the circuit to connect it to the other devices. Digital ICs have found extensive practical applications because of the following main advantages over the discrete circuits. 1. 2. 3. 4. 5. 6. 7.

Reduced cost Reduced size Reduced complexity of wiring Increased reliability Increased speed of operation Lower power-consumption Trouble-free maintenance

4.21 LEVELS OF INTEGRATION

Depending on the number of gates and other elements on a single chip, the digital ICs are divided into several groups, or levels, which are termed as SSI, MSI, LSI, VLSI, and ULSI. The SSI (small-scale integration) level refers to those chips which contain less than 30 elements on a single chip. The term MSI (medium-scale integration) means the level of integration ranging from 30 to 100 elements per chip, while the LSI (large-scale integration) refers to the number of elements between 100 and 10,000 on a single chip. The chips having the number between 10,000 to 1,00,000 each comes under the VLSI (very largescale integration), while those with still more elements belong to the ULSI (ultra largescale integration) level. 4.22 DIGITAL-IC (LOGIC) FAMILIES

Digital integrated circuits have been designed and fabricated basically on two technologies-bipolar and unipolar. Accordingly, these circuits are classified into two categories which are referred to as bipolar logic family and unipolar (or MOS) logicfamily. The elements used in the bipolar- family ICs are the resistors, capacitors, diodes and transistors, whereas the Mos-family lea use only the MOSFETs in their integration. These two families have been further sub-divided as follows. (a) Bipolar families consist of the following groups: 1. 2. 3. 4.

DTL (Diode-transistor logic) RTL (Resistor-transistor logic) TTL (Transistor-transistor logic) DCTL (Direct-coupled transistor logic)

LOGIC GATES AND IC FAMIUES

117

5. ECL (Emitter- coupled logic) 6. 12L (Integrated-injection logic) (b) MOS families contain the following groups:

1. PMOS (p-channel MOSFETs) 2. NMOS (n-channel MOSFETS) 3. CMOS (complementary MOSFETs)

Before discussing the specific gate-circuits belonging to each logic family, let us explain the important characteristics of digital ICs.

4.23 CHARACTERISTICS OF DIGITAL ICs To determine and compare the performance of various digital ICs, it is essential to know the following common characteristics. 1. Voltage and current parameters 2. Noise immunity 3. Speed of operation 4. Power dissipation 5. Fan-in / Fan-out 6. Operating temperature Voltage and Current parameters The voltage and current parameters are specified for each gate for its normal operation. These parameters include four input and output voltages and four input and output currents. The input and output voltages are : V iL V iH

-

VoL -

VoH

-

Maximum value (upper limit) of input voltage for the low state Minimum value (lower limit) of input voltage for the high state Maximum value (upper limit) of output voltage for the low state Minimum value (lower limit) of output voltage for the high state

The four input and output currents are : liL - Input current in the low state 1m - Input current in the high state IoL - Output current in the low state lou: Output current in the high state

Noise Immunity Noise immunity of a digital gate determines its ability of tolerating noise voltages without going into false operation. These unwanted noise voltages which often enter into the gate circuit by way of induction from the stray electric and magnetic fields, adversely increase or decrease the applied voltage levels in the low and high states.

118

DIGITAL PRINCIPLES AND CIRCUITS

Quantitatively, the noise immunity is measured as the noise margins in the low and high states. Noise margins can be defined with the help of Fig. 4.23 (a) and (b) in a dc system. Fig. (a) shows the prescribed voltage ranges for the low and high states of the input, while those for the output are shown in Fig. (b).

In the input voltage ranges, ViLis the upper limit of low-state range, and V iH is the lower limit of high-state range. Any input voltage that may enter into the intermediate range (ViH - V iL ) would drive the circuit into false operation. Similarly, in the output voltage ranges, VoL is the upper limit of low-state range, and VaH is the lower limit of high-state range. Any output voltage that may enter into the intermediate range (VaH - VoL ) would drive the circuit into false operation.

-----.-_..... -- ... . :::::High:::::

-_ ............. _--.. ..... ... _- .....

------_ .... _----- - _ .. oo . . . . . . . . _ - - - -

-:-:-:-:-Higti-:-:-:-:-:-::::o8tate·::::: -_--------_ ........ _-_ ........ . .. _---

-:::::::::::::: -:::::::::::::: II~..........

Intermediate

V -------------

______________

IL

-:-:-:-:-:LOw..:-:-:-:-: -::::.state~-:::: -_.oo._------_ .... -----------_ .... __ .oo .. _------..... -------_ ...... (a) Input-voltate ranges

.-:-:-:-:-:stale.:-:-:~-: .................. _::::::::::-:::

Intermediate

4i

~, •• ~~~~~.,.. Vr --oo----------

::::::::::::::_

r---------------VaH a(1)

range

1------------------y. a(O)

-:-:-:-:-:£0\0;:-:-:-:-:-:-

-::::.state·::::: ...... ................ -.. _.. ___...... .. __.. ................

_-----

(b) Output-voltate ranges

Fig. 4.23 Noise margins in a de system

The high-state noise margin is, therefore, defined as the margin (VaH - YaH) by which the high-state range may come down The low-state-. noise margin is defined as the margin (ViL - VoL) by which the low state range may go up. That is, High-state noise margin _ Ll (1) = VaH - V iH Low-state noise margin Ll (0) =V iL - VoL Speed of operation/propagation delay

Movement of a signal from input to the output in a gate circuit is not instantaneous, but takes some finite time which is referred to as propagation delay. Speed of operation of the gate is therefore directly affected by the amount of this propagation delay, i.e. greater the delay, smaller is the speed of operation. To measure the propagation delay quantitatively, let us refer to Fig. 4.24 which shows the voltage-waveforms at the input and output of the gate circuit. We define here two delay intervals tHL and tLH between these waveforms. tHLis the time interval between the 50% values of the input and the output, when the output goes from the high state to the low state. tLH is the corresponding time interval when the output goes from low state to the high state. The average value of these two intervals gives the amount of propagation delay, i.e. Gate propagation delay

LOGIC GATES AND IC FAMIUES

119

_____________________________________ 50% Low state

Input voltage

High state

output voltage---"""

50%

Low state

Fig. 4.24 Input and output waveforms defining propagation delay

The amount of propagation delay (tp ) per gate ranges between 2 to 50 ns, which increases with the increasing number of gates, if connected in series. Speed of operation of a digital circuit, therefore can be increased by reducing the number of gates connected in series. Power dissipation

Power dissipation of a. gate is the amount of power that is dissipated at the gate when operating in the high and low states. Normally, its value ranges between a few microwatts to about 50 milliwatts. Note that higher speeds of operation require more power. As a result, the product of power dissipation and speed of operation (propagation delay) forms an important factor called Figure of merit of the gate, which is expressed as Figure of merit (pJ)

=Power dissipation x Propagation delay (mW)

(ns)

Fan-in I Fan-out Fan-in of a logic gate is the maximum number of inputs that can be allowed in that gate. Thus, the fan-in of a 3-input gate is 3. Fan-out of a logic gate is the maximum number of load gates that can be connected to its output without getting overloaded. Thus, a fan-out of 5 of a gate means that not more than 5 gates must be connected as loads to its output. Operatingtemperature

The temperature of a digital IC under operation is also an important factor for its proper functioning. For consumers and industrial applications, the operating temperatures must range between O°C and +70°C, whereas for military applications, they must range between -55°C and +125°C. 4.24 DTL AND-GATE

DTL (diode-transistor logic) circuits belong to the bipolar family of digital ICs. These circuits use diodes and transistors as the basic elements in them. To achieve higher fan-in and higher fan-out, DTL gates have been developed as an extension of the diode gates (Section 4.3) by adding a transistor amplifier in the output. The circuit for a 3-input DTL

DIGITAL PRINCIPLES AND CIRCUITS

120

AND-gate thus formed using a diode AND-gate and an emitter-follower, is shown in Fig. 4.25 along with its truth table. Its operation is explained below in terms of the voltage levels of +3 V (high) and 0 V (low).

+v

A ----...~.----......

B --ICa---+---I C--IC=:I----'

F=ABC

Diode AND-gate

-v Emitter-follower

A

B

C

F

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

Truth table

Fig. 4.25 A DTL AND-gate with truth table Circuit Operation

(i) When all the inputs are at 0 V, all the diodes conduct because of being forwardbiased through R l . This causes the transistor base to remain at 0 V (neglecting the diode drop). Because the emitter follows the base, the output also remains at F = 0 V. (ii) When any (but not all) inputs are at + 3 V, the corresponding diode/diodes do not conduct, but 'the others still conduct. This again keeps the base and emitter at 0 V, so that the output is again F = 0 V. (iii) When all the inputs are at +3V, neither diode conducts with no drop across Rl> The base, and therefore the emitter, rises to +3V, giving the output F =+3V. This operation of the AND gate is also depicted in the associated truth table interms of 0 and 1.

As given in Fig. 4.25, the emitter has to be negatively biased (with - V) relative to base, so that the positive drop across the diode may get compep.sated by the negative counter-part across the emitter-base junction of the transistor

The main advantage of DTL AND-gate is the high value of current gain - 30, which is caused by the low output impedance of the emitter-follower. This allows improved loading conditions, i.e. a higher fan-out for this gate.

4.25 DTL NAND-GATE A DTL NAND-gate formed with a 2-input diode AND-gate followed by an INVERTER, is shown in Fig. 4.26 along with its truth table. Its operation is described below using the positive logic-levels : Logic 1 = +5V Logic 0 = OV

·OGIC GATES AND IC FAMIUES

121 +5V

t---oF=AB A

A 0 0 1 1

B

F

0 1 0 1

1 1 1 0

Truth Table

B

AND-gate INVERTER Fig. 4.26 A DTL NAND-gate with truth table

Circuit operation

D2 ) conduct, and therefore point P comes at + 0.7 V relative to ground, because of the drop across these diodes. The series diodes (D3 and D 4 ) also conduct through RB with a total drop of +1.4 V across them, which makes the base voltage to become at - 0.7 V relative to ground. This negative biasing of the base-emitter junction keeps the transistor OFF, and therefore the output rises to + 5 V (high), as per the NAND function. (i) When either or both the inputs are at 0 V, the corresponding diodes (DI or / and

.

(ii) When both the inputs are at + 5 V (high), Dl and D2 get reverse- biased and the point P rises towards + 5 V. This produces a rising base current, which (when sufficiently large) drives the transistor into saturation. As a result, the output falls nearly to 0 V (low), as per the NAND function. The above functioning of the NAND gate is also given in the associated truth table in Fig. 4.26. Note that the use of series diodes D3 and D4 in this circuit is just to create a negative bias to the base-emitter junction during the operation under case (i), otherwise the positive voltage of + 0.7 V at the base would have undesirably turned the transistor ON and driven the circuit into false operation.

4.26 DTL NAND-GATE (with LOAD) The working of a DTL NAND-gate is considerably affected when it operates under loaded conditions. Fig. 4.27 shows a 2-input DTL NAND-gate that drives N similar gates connected as loads to its output. The analysis of this circuit is given below using the logic levels: Logic 0 = VCE, sat = 0.2 V Logic 1 = V CC = 5V and the circuit parameters as :

= R2 = 5K Rc = 22K

Rl

Diode drop VBE,on

=0.7 V =0.8 V

Diode cut-in Transistor cut-in

=0.6 V =0.5 V

~

= 30

122

DIGITAL PRINCIPLES AND CIRCUITS Vee (+5 V)

R

5K

A

03

04 Series diodes

B

O2

R8 5K

Input diodes

I1411",--------- Driver NAND-gate ----->1+- N Driven load-gates---.. Fig. 4.27 A DTL NAND-gate loaded with N similar gates

Circuit analysis

(i) When both the inputs are high (Output in low state): Under no-load conditions, the input diodes WI and D2 ) are reverse biased, but the series diodes (Da, D 4 ) and transistor T conduct. This gives the voltage at point Pas Vp = 0.7 + 0.7 + 0.8 = 2.2V The base current and the collector current of transistor T are : IB = 11-12 Vee - V. p. . ---==-= V BE on = ---'~-

R

= Ie

RB

5-2.2 0.8 _ 04mA 5K

= Vee -

5K -

.

VeE,sat _ 5 - 0.2 2.2 K

Re

=2.18 mA

Since this value of Ie (= 2.18 mA) < ~ IB ( =30 x 0.4 = 12mA), it confirms that the transistor is in saturation, and the output is in low state. Under loaded conditions, with N similar load gates connected at the driver output, the input diodes of the load gates conduct with a load current h that gets added to the unloaded collector current Ie flowing through T. In this way, the transistor acts as a current sink for the load current

Vee - VPl IL, -" Rl

_ -

5-0.9 - 082mA 5K - .

[VP1=0.2 + 0.7 = 0.9 V]

LOGIC GATES AND IC FAMIUES

123

when the gate operates in the low state. (ii)

When either or both the inputs are low (Output in high state) :

Under no-load conditions, the input diodes, whichever corresponds to a low input conduct, so that V p = 0.7 V. This voltage is insufficient to drive D 3 , D4 and T into conduction because it is less than the minimum required voltage of 0.6 + 0.6 + 0.5 = 1.7 V. The transistor T, thus being cutoff, causes the output to rise to the high state. Under loaded conditions, the output still remains high, but its value Slightly falls by the amount of drop across Re , which is caused by the reverse saturation-current through the load-diodes. Thus, the effect of loading causes the transistor to act as a current source for the reverse saturation-current when the gate operates in the high state. Current sinking As explained above, in the low-state of output, the current through the forward-biased load diodes is sinked into the transistor, and in the high-state of output, the reverse saturationcurrent through the load diodes is sourced (supplied) by the transistor, Because, the sinked current is much greater than the sourced current, the net effect is termed as current sinking.

Fan-out For one load gate, the load current is h = 0.82 rnA For N load-gates, it becomes I'L = Nh + Ie = 0.82 N + 2.18 rnA Also, I'L = PIB =12 rnA 0.82 N + 2.18 = 12 Therefore, which gives a fan-out of N=12

(Ie = unloaded collector current)

Noise Margins In the low-state of output, since V p = 2.2 V, the reverse-bias voltage for the input diodes is Vee - V p = 5 - 2.2 = 2.8 V . Since the diode's cut--in voltage is 0.6 V, therefore,

Low-state noise margin

a (0) = 2.8 - (- 0.6)

= 3.4 V

In the high-state of output, V p = 0.9 V, and the minimum voltage required for Dlo D2 and T to conduct is 1. 7 V, therefore,

High-state noise margin

a(1)

= 1.7 ~ 0.9 = 0.8 V

WtI-ed AND connection Connecting the outputs of two or more DTL gates together into a single output, is referred to as wired-AND connection. The main advantage of this type of direct connection consists in getting an ANDed value of all the individual outputs without requiring an additional AND gate. It also eliminates the need for an AND-OR-INVERT logic. Fig. 4.28 shows wired ANDing of two DTL NAND-gates using their symbols. The ANDed output is given by Y = Y 1 Y 2 for the individual outputs Y1 and Y 2 •

124

DIGITAL PRINCIPLES AND

CIRCUrt'~

Yl

Fig. 4.28 Wired-ANDing of DTL NAND-gates Besides the above advantages, the wired-AND connection of DTL gates adversely affects the power dissipation, speed of operation as well as the fan-out of the circuit. DTL characteristics

DTL gates have become obsolete these days, because of their slow speeds. The main cause of their slow speed are the charges at the base of transistor, which can leak-off only through RB because Da and D4 do not conduct when the transistor switches from saturation to cutoff. However, the DTL family of digitallCs is characterised with: 1. Lower speed 2. Better noise immunity 3. -Propagation delay - 30 ns 4. Fan-in of 8 5. Fan-out of 5

4.27 RTL NOR-GATE The RTL (resistor-transistor logic) is another group of digital ICs belonging to the bipolar family, in which the circuits use transistors and resistors. A NAND or NOR gate in this group can be formed by using two transistors and a few resistors. Fig. 4.29. shows a 2-input positive-logic RTL NOR-gate using transistors TI and T2 with their emitters grounded and collectors tied together to share a common load resistor R 2 • Each input (A and B) is applied to the different base through a resistor R 1• +3V

r-----------------~--oF=A+B

A 0 0 1 1

Fig. 4.29 An RTL NOR-gate with truth table

B

F

0 1 0 1

1 0 0 0

LOGIC GATES AND IC FAMIUES

125

The operation of this circuit under no-load conditions is explained below using the logic levels: low = OV and high =+ 3 V.

Circuit operation When both the inputs A and B are low, both the transistors are cutoff, and the output voltage is high, a little less than Vee = + 3 V, because of the small drop across R 2 • (ii) When either, or both the inputs A and B are high, the corresponding transistor goes into saturation, thereby driving the collector output to the low state. The above operation of NOR gate is also explained in the truth table associated with the circuit in Fig. 4.29. (i)

Current sourcing Under loaded conditions, when the gate output is low, the reverse saturation base current of the load transistors is sinked into T 1 and T 2' But in the high state of output, the current is supplied (sourced) by the gate to the load transistors. Because the source current is much greater than the sinked current , this action is termed as current sourcing. Other effects of loading are explained in Example 4.12. Example 4.12 Draw a circuit for RTL NOR-gate that drives N load gates. Analyse this

circuit to evaluate the following : 1. Output voltage of driver gate 2. Input current to all the load gates 3. Noise margins in the high and low states.

Solution Fig. E 4.12 (a) shows he circuit for a 2-input-RTL NOR gate that drives N load gates (G1 through G N ). The input circuit of driver is given in Fig. (b) and the output circuit of the driven loads is given in Fig. (c). 1. In Fig. E 4.12 (a), if R' is the effective load of N driven gates, then 1 1 1 N R' = Rl + Rl + ... = Rl . whi ch gIves

R' -- Rl N

...(1)

From Fig. E 4.12 (b), since the output current to all the N driven gates is ... (2)

the voltage across R' is cc VBE, on Rl V , -- IR' _- VR +-RI/N x N 2

, .. (3)

The required output voltage of driver gate is therefore, Vo

=

VBE,on

+ V'

= VBE,on + V ce - VBE. on X Rl R2+RI/N N

... (4)

126

DIGITAL PRINCIPLES AND CIRCUITS

n

Vee (3.5 V)

veer-l + ":" R2

R2 640

./C2

--1 Gt VCE;B8I

i

450

Vo

1 ,,, ,,,

450

+-- Driver NOR gate - : - - N driven loads -.. (a) RTL NOR gate circuit driving N loads

1 Vee

+

fJ, Rt

+

Effective load of driven gates

,, ,,

(b) Input circuit of driver : (c) Output circuit & driven loads G1

Fig. E 4.12

2. From Fig. E. 4.12 (c), the collector current IC2 for the load transistor in saturation, is given by Vcc - VCE, sat

IC2 =

...(5)

R2

Therefore, the base current at the input of each load transistor becomes ... (6)

3. High-state noise margin : !J. (1)

= High-state output -

High-state input

= Output voltage of driver - Base voltage of driver

= Vo -

(VBE , on + R1x I B2 )

Putting for Vo from Eq. (4) and IB2 from Eq. (6), we have on sQI!ing, !J. (1)

Vcc - VBE,on

= R2 + RI/N

Vcc - VBE,sat -

PR2/Rl

... (7)

LOGIC GATES AND IC FAMIUES

127

4. Low-state noise margin : /). (0) = Transistor cut-in -

... (8)

VCE, sat

Considering the following circuit parameters R1= 450 n R 2 =640n

VCC

=3.5V

VCE, sat

=0.2 V

Transistor cut-in

V BE , on

= 0.8 V = 30

f3 N = 4 load transistors

=0.5V

Using Eqs. (4), (6), (7) and (8), the required values are given below: Vo

=1.203 V,

IB2 =

0.17 rnA,

/).(1)

= 0.327 V, /). (0) = 0.3 V

RTL Characteristics

The RTL logic family has the following characteristics: 1. Slower speed of operation 2. Poor noise immunity

3. Low fan-in of 4 4. Fan-out of 6 5. More expensive due to fabrication of resistors.

4.28 nL The TTL (transistor-transistor logic) family is the most widely used. group of bipolar logic family since 1970s, because of its high speed, good fan-in and fan-out, and easier interface with the other digital circuitry. The unique feature of TTL lCs is that they use a multiemitter transistor at the input which saves much of space on the chip. This also results into lowering the capacitance to the substrate which helps in increasing the speed of operation. The TTL family has not only been prominent in the SSl and MSl designs in the past, but today also, it continues to playa leading role in the logic designs.

4.29 nL BASIC NAND-GATE NAND gate is the basic circuit of TTL family, although the AND, OR and NOR gate configurations have been currently developed in this family. The basic TTL NAND circuit using a multi-emitter transistor Tl at the input, and two other transistors T2 and Ta is shown in Fig. 4.30. Although this basic circuit has no practical importance, however, it is essential to know its operation, which is given below using the logic levels: High (1) = V cc = +5 V, and Low (0) =VCE, sat = .0.2 V.

Circuit operation

When both the inputs (A and B ) are high, T 1 is cutoff because both the EB junctions of T 1 are reverse-biased. However, the CB junction of Tl is forward-biased, and allows a current to flow from Vcc, viaR 1 , to the base ofT2 , which gets turned ON. Since Ta also gets turned ON by the drop across the emitter resistor R E , the output falls to F

= 0.2 V (low)

128

DIGITAL PRINCIPLES AND CIRCUITS

t - - - - o ( ) F= AB

A

Bo----' Multi-emitter Transistor

Fig. 4.30 TTL basic NAND gate

When either or both the inputs are low, the corresponding EB junction of T 1 is forwardbiased that allows a sufficient current to flow from Vee, viaR l and Tl'S emitter to ground. This causes a voltage of 0.7 V at the base of Th which is insufficient to forward-bias its CB junction. ConsequEtntly, T2 remains cutoff, as also T 3 , because it has no base current. The _ output thus rises to F = + 5 V (high)

Drawback The main drawback of the basic TTL circuit of Fig. 4.30 is the increased power dissipation when the output goes into low state, because then the transistor T3 conducts heavily around 40 mAo To avoid this drawback, modified circuits are preferred, in which the output is obtained either through a totempole stage, or in the open-collector mode, or in the tristate mode, as discussed in the following. 4.30 STANDARD nL NAND-GATE WITH TOTEMPOLE OUTPUT

Totempole output circuit is used to increase the speed of switching. In this circuit, an additional transistor is used in the output to act as emitter follower whose low outputimpedance (- 100 ohms) provides a shorter time constant for charging the output capacitance of the gate, and hence the greater speed of switching. Fig. 4.31 shows the standard circuit of a 2-input NAND gate using the totempole output, which is obtained from the basic TTL circuit by adding a transistor T 4 and a diode D in series with the transistor T 3 • Transistor T4 acts as emitter follower and the diode prevents T4 from conducting when the output is in the low state. The capacitance Co includes the output capacitance of T 3 , capacitance of driven gates, if any, and the wiring capacitance. The operation of this circuit is explained below using the logic levels : Logic 1

= Vcc=+5V

Logic 0

= VCE, sat =0.2 V

LOGIC GATES AND IC FAMIUES

129

r---------~----------~----------~V~(+5V)

A 0----"'" 80-------' Multi-emitter Transistor

RE 1K Totempole stage

Fig. 4.31 Standard TTL NAND-gate with totempoie output

Low·state operation When both the inputs (A and B) are high, the output goes low ( VoL)' because the emitters of are reverse-biased, but its collector conducts. This turns T2 ON, as also Ta. Because T4 and D are cutoff, therefore, the output goes low (VoL=0.2 V). This action is detailed below.

TI

The T 2'S collector voltage or T 4'S base voltage is given by V C2

=V B4 =V BE a, sat+ VCE, sat =0.8 + 0.2 =1.0 V

The voltage across T 4'S BE junction and diode D is given by

V BE4 =VB 4- VCEa,sat= 1.0 - 0.2 = 0.8 V Because this voltage V BE4 = 0.8 V is insufficient to forward-bias T4 and D, hence they are cutoff. The capacitance Co discharges through T 3 , and the output Vo falls to V oL = 0.2 V (low).

ffigh-state operation When either or both the ~nputs are low, the output switches to high state (VoH), because then, T1's emitter conducts but not the collector, so that T2 and hence Ta get cutoff. The base voltage of T 4 now, is V B4

=V BE4,sat + V D +VoL= 0.8 + 0.7 + 0.2 =1.7 V

so that the base current and collector current ofT4 are - VB4 _ 5 - 1. 7 _ 2 36 rnA I B 4 - V ccR2 - 1.4K - . IC4

=

VCC - VCE4.saC V D - VoL

Ra

5-0.2-0.7-0.2 _ 39rnA 100 -

130

DIGITAL PRINCIPLES AND CIRCUITS

Because fJIB4, (= 30 x 2.36 = 70.8 inA) > IC4 (= 39 rnA), therefore T4gets ON. During when T4, remains ON, it supplies a charging current to C(JJ which decreases toward zero. AP. a result, Voincreases toward Vcc, until finally, T4,gets cutoff when Vo reaches the steady value VoH

=V cc -

=5 -

V4,Ccut-inl- VDCcut-inl

0.5 - 0.6 =3.9 V (high)

Note that during the transition of output from low state to the high state, Ta turns off more slowly than T4 turns on i.e. they both remain in the conducting state for a very small period, and therefore draw a heavy current (lc4 + IB4 =41.4 rnA) from the Vcc supply in this period of transition. Loa~coxuriderations

When the standard TTL circuit of Fig. 4.31 is loaded by connecting similar load-gates to its output, its operation is affected as follows. In the high state of output, the gate acts as a current source, because it supplies the reverse-bias leakage current (liH ) of a few microamperes to the input of each load-gate through T4 and D, which is called sourcing current. Similarly, in the low state of output, the gate acts as a current sink, because it receives a current (liL) from the input of each load gate that flows through Ts to ground. This current is called sinking current. If N be the number ofload gates, then the total sourcing current to all the load-gates is given by loH

= NliH

Similarly, the total sinking current from the inputs of all the load gates is given by

Since these currents loH and loL increase with the increasing number of load-gates (N), the corresponding fan-outs in high and low states are given by .

(

Htgh-state fan-out N max

(max) = loH I ( ) iH max

)

loL (max) - liL (max)

Low-state fan-out N (max) -

-="-'---"-

where, loH (max), liH(max), loL (max) and liL (max) are the maximum currents as specified in the data-sheet of each gate. The lower value of the above two fan-outs is taken to be the fan-out of the gate. Example 4.13 Determine the fan-out for the TTL gate 74ALS 20 whose data sheet gives the following values.

=0.4 rnA loL (max) = 8.0 rnA loH (max)

=20 pA liL"(max) = 0.1 rnA liH (max)

LOGIC GATES AND IC FAMIUES

131

Solution IoH

(max)

400

High-state fan-out

= IiH (max) = al = 20

Low-state fan-out

(max) = IoL IiL (max)

8 = 80 0.1

= -

Thus, the required fan-out of the given and 30.

Ie is N = 20,being the lower of the two values of 20

Output circuits There are the following three kinds of circuits which are currently being used in the output of TTL gates. 1. Totempole output 2. Open-collector output 3. Tristate output Totempole output The totempole output stage as used in the standard TTL circuits of Fig. 4.31 possesses the following important features. 1. It reduces power dissipation when the gate output is in the low state, because the transistor T 4 remains OFF, and therefore no current flows through the collector resistance R 3 • 2. It improves the switching speed of the gate when its output is in the high state. This happens because of the smaller value of time-constant for charging the output capacitance, which is caused by the low output-impedance of the conducting transistor T4 acting as emitter-follower. 3. It causes a heavy current-flow (more power loss) from the Vee supply, when the output goes from low state to the high state. This happens, because in the low state, when T3 goes into saturation, excess charges flood into its base, and get collected there. Since the leaking of these base-charges is slow, a delay called turn-oft-time delay is caused to the switching of T3 from saturation to cutoff. That is, T4 turns-on earlier than T3 turns off, thereby both T3 and T4 remain conducting and hence a heavy current flows for the small period of delay. 4. Apart from the above, the totempole has the disadvantage in that wired-ANDing cannot be achieved in the outputs of two or more TTL gates, because when one gate's output is high and the other's is low, a large current would flow from the high terminal to the low terminal. Open. collector output

Open-collector configuration is the other kind of output circuit in the TTL gates, using which wired-ANDing' can be achieved by connecting together the gate outputs directly. In this configuration, the collector resistor R3 of the standard circuit of Fig. 4.31 is removed from the chip and the collector terminal of T4 is left open (unconnected). At the time of

132

DIGITAL PRINCIPLES AND CIRCUITS

using the gate, an external resistor R a, called pull-up resistor is connected to the open collector of T 4 from outside the chip. Vee

Common pull-up resistor (external) ~

~

~~::----------~--------"--=C>---o y=

Y, Y2

Open collectors - - - connected together

TTL gate G,

TTL gate G2

Fig. 4.32 Wired ANDing in open-collector TTL gates

To achieve wired-ANDing of two (or more) TTL gates, such as G 1 and G2 in Fig. 4.32, their open collectors are tied together and a common pull-up resistor (Ra) of appropriate value is connected to them externally. The outputs Y1 and Y2 of these gates are ANDed in this way into Y = Y1 Y2 without needing any AND gate separately. For calculation of the value of pull-up resistor, see Example E 4.13. Tristate output

Another kind of output configuration used in the TTL gates is the tristate logic circuit, which not only provides the high-speed operation of totempole, but also allows wiredANDing of the outputs (without a pull-up resistor). In this configuration, a tristate logic (TSL) circuit, as discussed in Section 4.38, is connected across the standard NAND of Fig. 4.31, which drives the output to go into a third state apart from the usual low and high states. In the third state, called high-impedance (hi-z) state, or open state, both the totempole transistors T a and T 4 of the standard TTL are cut-off, and the output terminal of the TSL circuit, instead of going low or high, remains floating with a high impedance of several megohms relative to ground and Vee . This high-z state is required for wired-ANDing.

Wired-ANDing The TSL circuit acts as a switch which allows, or does not allow the input to appear at its output, dependirig on whether it is closed or open. TTL gates using tristate (TSL) outputs are called tristate TTL gates. The outputs of two (or more) such gates can be connected together to get the ANDed output Y =Y1 Y 2 , as shown in Fig. 4.33. In this operation, if the output from.Jme gate is high and that from the other is low, one output is kept in the hi-z state using the enjlble signal (Sec. 4.38) until the other becomes similar to it. In this way the problem of heavy current from the high terminal to the low terminal is avoided.

LOGIC GATES AND IC FAMIUES

133

Besides the wired-ANDed output, Y can also reflect the output of only one of the tristate gates which may be selected by its enable signal with the other gates deselected. Note that only one gate can be selected at one time in this operation. TSL

TTL gate 1

Y,

switch

TSL

TTL gate 2

switch

Fig. 4.33 Wired-ANDing in tristate TTL gates

Example 4.13 Show how to connect the outputs of N open-collector TTL gates to obtain wired-ANDed output using a single pull-up resistor R L • If n TTL load gates are to be driven with this output, calculate the probable values of RL under these loaded conditions. Specifications for a normal 74 series TTL are given as :

Input:

ViL IiL

Output:

VoL IoL

= O.BV = 1.6 rnA = 0.4 V = 16rnA

ViH = 2.0V IiH VoH IoH

= 40pA = 2.4 V = 250 J1 A (sinked by gate output)

Solution The required wired-AND connection is shown in Fig. E 4.13, in which N opencollector outputs (V h V 2 , ••. , VN ) are tied together to a single pull-up resistor RL which is connected to the Vee (+5 V) supply, The tied output Va is connected to drive the inputs of n load gates. In wired-ANDing, when one or more of the open-collector outputs are at low, and the others are at high, the resulting tied output Va will remain low, which conforms to the AND operation.

The value of RL has to be carefully chosen to ensure that Va falls in the proper range, i.e. 0 - 0.4 V for logic 0 and 2.4 V - 5 V for logic 1. This would determine a range of R L , which can be calculated below using the given specifications. Vcd+5V)

V,

V2

VN

n:::::::::::--~-~~v.~o-=-V.-l,~V2-"-'v.-N---+--t

•

N open-collector gates

n Load gates

Fig. E 4.13

134

DIGITAL PRINCIPLES AND CIRCUITS

(i) When Vo is at low (i.e. one open-collector output is low and the others are at high): h+nliL ~ 16ma

Since

h=

V CC - VoL RL

=

5-0.4

4.6

RL

RL

4.6

Therefore

RL + 1.6n ~ 16

Or -

> 4.6 RL16 -1.6 n

k-ohms ...... (1)

(ii) When Vo is at high (i.e. all the open-collector outputs are at high):

h

~ N1oH+n1iJI

V CCiL VoH ;:: 0.25 N + 0.04n

2.6

RL ~ 0.25N + 0.04n

or

R

< L -

Thus,

2.6 0.25N + 0.04 n

RL (min)

k-ohms ...... (2)

= 16 ~·~.6 n 2.6

RL(max) = 0.25 N + 0.04 n

which shows that the minimum and maximum values of RL depend on the number of driver gates (N) and driven gates (n). RL (min) = 1.4 k-ohms

ForN=4 andn=8

RL (max) = 1.97 k-ohms

4.31 SERIES 7400 AND 5400 The TTL devices are manufactured under two series which are numbered as 7400 and 5400. Each series includes a large number of SSI and MSI chips which can be used to build all kinds of digital circuits and systems. The 7400-series devices are made for commercial applications, while those under the 5400 series are meant for military applications. These two series differ only in their temperature and power-supply ranges, as given in Table 4.1. Table 4.1 Temperature and power supply ranges of TTL series TTL Series

Power-supply range

Application

7400

Temp. range ODC to 70 DC

5V± 0.25 V

Commercial

5400

-55 DC to 125 DC

5V ± 0.5 V

Military

LOGIC GATES AND IC FAMIUES

135

The 7400 TTL series has several sub-series and the devices under each sub-series are the improved versions of the standard TTL circuit. The identification of these sub-series is done with the prefixes: 74H, 741., 748, 74LS, 74AS, 74ALS and 74F while the characteristics of each one are described in the following. (a)

High-speed TIT... (7411)

The high-speed TTL devices numbered as 74HOO, 74H01, 74H02, etc. have high speed of operation, which is achieved by decreasing the internal time-constant of the standard circuit, and thereby reducing the propagation delay to around 6 ns. However, the power dissipation increases upto 20 mW due to decrease in circuit-resistance. (b)

Low-power TIL (74L)

The low-power TTL devices, numbered as 74LOO, 74L01, 74L02, etc. are designed to have low-power dissipation by increasing the circuit resistance of the Standard TTL. However, these devices are slower due to increased value of time constant. (c)

Schottky TIL (74 S)

In the Schottky TTL devices, numbered as 74S00, 74S01, etc., a Schottky transistor is used in place of T3 of the standard TTL, to improve the switching speed by reducing the turn-offtime delay caused by the excess base-charges. A Schottky transistor is made by fabricating a Schottky diode (SD) across the base collector junction of a transistor, as shown in Fig. 4.34 along with the symbol.

(a) Schottky transistor

(b) Symbol

Fig. 4.34

Since the Schottky diode has much lower barrier potential (0.4 V) than that of the basecollector junction, it is sufficiently forward-biased so as to pass-on the excess base-charges through it. The turn-off-time delay is reduced in this way, to around 2 ns from 10 ns of the Standard TTL. (cl) Low-power Schottky TIL (74 LS)

The lower-power Schottky TTL devices, numbered as 74LSOO, 74LS01, etc. present the best compromise between low power and high speed. These devices are manufactured with

136

DIGITAL PRINCIPLES AND CIRCUITS

increased internal resistance using the Schottky diodes. A gate of this sub-series has power dissipation of as low as 2 mW, and propagation-delay of around 10 ns. Apart from the above, the digital devices of the following sub-series are the most improved versions which have been recently added into the TTL family. (e) Advanced Schottky TTL (74 AS)

This series is the advanced version of Schottky TTL (74S) regarding the speed and power considerations. Its characteristics are compared with the other sub-series in Table 4.2. (f) Advanced low power Schottky TTL (74 ALS)

This series is the advanced version oflow-power Schottky (74LS) as described in (d) above. Its characteristics are also compared in Table 4.2 with the other sub-series. (g) Fast 'ITL (74F)

This TTL sub-series is the most advanced recent entry that uses a new fabrication technique to reduce the inter-device capacitances, and hence the propagation delay. Its comparison is also given in Table 4.2, with the others sub-series. Comparison of Characteristics Table 4.2 gives at-a-glance comparison of the characteristics of various sub-series of the TTL family. Table 4.2 TTL sub-series characteristics 74AS

74ALS

74F

2

8

1.2

6

9.5

1.7

4

3

20

40

20

33

125

45

200

70

100

2.4

2.7

2.7

2.5

2.5

2.5

VoL (max)

0.4

0.5

0.5

0.5

0.4

0.5

V,H (min)

2.0

2.0

2.0

2.0

2.0

2.0

ViL (max)

0.8

0.8

0.8

0.8

0.8

0.8

74

74S

Power dissipation per gate (mW)

10

20

Propagation delay per gate (ns)

9

;3

Fan-out

10

20

Maximum clock rate (MHz)

35

VoH (min)

Gate performance

74LS

Voltage parameters

4.32 DCTL NOR-GATE DCTL (direct-coupled transistor logic) circuits have the same pattern as that of RTL, except that each input is directly applied to the base without connecting any resistor to it. Fig. 4.35 shows a 2-input DCTL NOR gate with the transistors Tl and T2 directly receiving the inputs A and B , and driving the load-gate transistors T3 and T 4 • Its operation is summarised in the associated truth table and described below using the logic levels: Logic 1 = VBE , on = 0.8 V (high) Logic 0 = VeE, sat = 0.2 V (low)

LOGIC GATES AND IC FAMIUES

137

VcC+

A , , B

' '

I

_ AB

:

, - - - - - - - - - - ...... ____ 1

NAND (a)

Fig. 5.2 Second theorem (A . B = A + B)

Complementing an expression Another importance of De Morgan's theorems consists in obtaining the complement of an expression directly. For example, we can complement the expression F = A . (B + C) as follows. Complement

F =A· (B + C)

Using Second theorem,

F =A+ B +C F = A + B E is the required complement.

U sing First theorem,

Example 5.1 Find the complement of the following expression using De Morgan's theorems. Simplify the complement expression and suggest the suitable logic circuit to implement the same. y =abc+a+bc Solution The required complement is written as

y

= abc + a + bc = (a b

c ) . a. bc

=

First theorem Second theorem, Law 8

On simplifying, we get -

which requires one the complementy.

AND

-

-

Law 8, Law 3

= aab+abb+abc+aac+abc+acc

Law 3

= abc+abc

Law 7

= a· (b c +bc)

Law 3

gate and one

XOR

gate, as shown connected in Fig. E 5.1 to realize

~y=albc+bCl

XOR a -------'-

AND

Fig. E 5.3

165

BOOLEAN ALGEBRA

5.9 DUALITY OF BOOLEAN ALGEBRA A dual of any Boolean expression can be obtained simply by interchanging the signs of (+ ) and (.) and also the Os and Is in it. Using this procedure, the dual of x . 0 would be x +1, and the dual of (1 + x) . (y + 0) would be O'x + y .1. As described earlier, each law and each theorem of Boolean algebra is expressed in dual forms, either of which can be converted into the other by interchanging the (+) and (.) signs, as well as the Os and Is. In this way, the entire Boolean algebra is characterised with this duality.

Complementing an expression The easiest way to obtain the complement of a Boolean expression is by using its dual. In this method, we first take the dual of the given expression and then complement each literal. For example, to complement the expression -

the dual of y is

y =abc+a+bc y = (a + b +e ). a . (b + c)

by interchanging the signs

Complementing each literal gives -

y

= (a + b + c), a ·(b + c)

y

=

which is simplified to -

-

-

a ab + a ae + bah + bae + cab + cae

=O+O+O+abC+abc+O

=a (be + b c) Note that this method of taking dual and complementing each literal is easier than that using the De Morgan's theorems as given earlier.

5.10 EVALUATION OF BOOLEAN EXPRESSION Constructing a truth table from a logical expression is called evaluation (or analysis) of that expression. Such a truth table is developed in several steps. First, all the possible binary values of the input variables are entered in the Table with one variable in one column. The total number of such entries would be 2 n for n variables. Next, in the subsequent columns are entered the values of each term (combination of variables or complements) of the expression. Finally, the complete expression is evaluated in the last column by writing its value in each row. For instance, let us evaluate the Boolean expression.

To form its truth table, we first write values of 8 possible combinations of the 3 variables (A, B, C) in the first three columns of the truth table, as shown in Table 5.3. Then, the values of C are written in the fourth column by complementing the values of C. The values of BC are then found by ANDing Band C, and entered in the fifth column. Finally, A and Be are oRed, and the resulting values are entered in the last column, thus completing the truth table for the given function.

DIGITAL PRINCIPLES AND CIRCUITS

166

Table 5.3 Evaluating Y =A + BC A

B

C

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

C 1 0 1 0 1 0 1 0

BC

Y=A+BC

0 0 1 0 0 0 1 0

0 0 1 0 1 1 1 1

I I

S.11 SEQUENCE OF OPERATIONS In the evaluation of a Boolean expression, various operations must be performed in the following sequence. 1. 2. 3. 4. 5.

First perform all inversions of the single terms. Then perform all operations within the parentheses. Perform all the AND operations in the order. Then perform all the OR operations in the order In an expressiull with inversion bar over it, perform all the operations within it, and then invert the result.

Besides the above, the following tips are also of much help in the quicker evaluation of the expressions. ANDing with itself ~Ring with itself Anything ANDed with 1 Anything ORed with 0 Anything ANDed with 0 Anything ORed with 1

= itself = itself = itself = itself = 0 =1

(x· x = x) (x + x = x) (x· 1 = x) (x + 0 = x) (x· 0 = 0) (x+ 1 = 1)

where x = a variable, or a term/expression with more variables.

Example 5.2 Evaluate (construct the truth table for) the logical function y= A+B M 2 , M 3 , M 7 )

5. 15 Convert the following to the other canonical form. (a) F(A,B,C)=L(1,3,7)

(b) F (X, Y, Z) = IT (1, 2, 4, 5)

5. 16 Distinguish between the canonical and noncanonical forms. Which form ie obtained when reading a function from a truth table? 5. 17 Prove that the sum of all minterms of a 3-variable Boolean function is 1. 5. 18 Prove that the product of all maxterms of a 3-variable function is O. 5. 19 Implement the Boolean function F=AB+AB+BC (a) using AND, OR and NOT gates only (b) using NAND gates only.

5.20 Draw Karnaugh map for each of the following expressions (a) AB +AB (b) A C +AC (d) AB +AB (c) A +AB 5.21 Simplify the following Boolean function by using K-map. F =ABC + AB C + ABC +ABC 5.22 Draw the K-map for a truth table of four variables in which the first eight outputs are o each, and the last eight outputs are 1 each.

203

--aOOLEAN ALGEBRA

5.23 In a logic system, the output is 1 for the inputs of ABeD = 0111, 0110, 1111 and 1110 each. Write down its Boolean equation and solve it using K-map. 5.24 Implement the following function with NAND gates. F (X, Y, Z ) =L m (0, 6)

5.25 Form a K-map to convert decimal digits expressed in 8421 code into Gray code. 5.26 Suggest a suitable circuit using K-map to generate even parity bit for the decimal digits expressed in 8421 code. 5.27 Simplify the following Boolean functions using the Q-M map method. (a)

{(Xl> X2, X3, X4)

=L (1,5,6,7,9,10,14,15)

(b) {(Xl> X2, X3, X4, X5) =

L (5,8,11,16,20,24,27,30) OBJECTIVE QUESTIONS

1 In Boolean algebra, Y is a (a) variable (c) literal

word (d) expression (b)

2 The Boolean expression A + B + 1 equals ~)A+l

(c)

~)B+l

A+B

(d) 1

3 To say, "logical sum equals a binary sum" is (a) False (b) True 4 "A logical sum can be converted into a logical product simply by exchanging (+) and (.) signs. This statement is (a) False (b) True 5 The expression A + A equals (a) A (c) 1

(b)

A

(d) 0

6 The expression A + B + Ii can be written as ~)A+B

(c)

B+l

~)A+l

(d)

A+Ii

7 The expression AB + A Ii can be simpllfied to ~)A

(c)

AB

8 The Boolean function F (a) 4 minterms (c) 12 minterms

~)B

(d)

A Ii

=A Ii + ACD has 8 minterms (d) 16 minterms (b)

9 The number of maxterms in the truth table of 5-variables will be (a) 16 (b) 20 (c) 28 (d) 32

204

DIGITAL PRINCIPLES AND CIRCUITS

10 "A minterm can be converted into a maxterm by exchanging (+) and (.) signs". The statement is (a) True (b) False 11 The number of squares in a 4-variable K-map is (a) 8 (b) 16 (c) 32 (d) 64 12 K-map can be applied upto (a) 3 variables (c) 5 variables

4 variables (d) 6 variables (b)

13 A quad of Is in a K-map eliminates (b) 3 literals (a) 2 litera.ls (d) 5 literals (c) 4 literals 14 NAND-NAND logic is equivalent to (b) OR-AND gate logic (c) NAND-OR logic (d) AND-NOR logic 15 A single-input NAND gate behaves as (b) NOT gate (a) OR gate (d) (c) AND gate None of them 16 Two single-input NAND gates form a (a) NAND gate (b) AND gate (c) NOR gate (d) Short-circuit

(a) AND-OR

17 Complement of the term A (.8 + C ) is

+C A+BC

(a) A+B (c)

(b) AB +BC (d) A+.8C

18 The Boolean expression A + ABC would be complemented to (a) A+ABC (b) A (A+.8C) (c) A+-F (b) Logic Symbol

(a) Truth Table

Fig. 6.1 Truth table and logic symbol of XOR gate

The Boolean equation for the XOR function is written as F = AEBB= AB+AB which we read as "F equals A XOR B", with the inputs A and B. The sign of EB in this equation indicates the XOR addition which means that the output F is high, only when A or B is high, but not when both are high. Gate form.ati~n

An XOR gate can be built in a number of ways by connecting either the basic gates, or only the NAND gates, as shown in Fig. 6.2. The circuits of Figs. 6.2 (a) and (b) are obtained by

206

DIGITAL PRINCIPLES AND CIRCUITS

connecting the basic gates, while that of Fig. 6.2 (c) is obtained from Fig. 9b) by replacing the AND and OR gates with the NAND-NAND gating. \ A ---0A. +5V

(MS B)

r~ - (1231

(r2~1 AoA1~

E

AoA1~

E

r~ - (123 AoA1~

E

I1 - (1

~

AoA1~

E

74138

74138

74138

74138

Zl

Z2

Z3

4

lilli")

1111111'

IIYYIII'

Y16 ------ --- ---- y23

1111111)

Y2:;--- -- - - - --- - - Y31

Fig. E 6.9 A 5-to-32-line decoder using four 74138s

activate, its fifth output which is 1\3' Thus the total input code of 01101 (13) would cause output Yl3 to go low, while all others woilld stay high.

6.28 MULTIPLEXER When there are several signals flowing along different lines, and only one of them has to be passed onward, we always need a digital device which is called as muliplexer (or data selector). A multiplexer (MUX) receives n data inputs through n input lines and transmits only one selected input to the single output line, and therefore, it is designated as n : 1 line multiplexer. To select a particular data input, a definite set of signals, called select-inputs is required to be applied in this device. The number of select-inputs in an n : 1 line MUX is m, such that 2 m = n. Thus, in a 16:11ine MUX having 16 data inputs, the number of selectinputs will be 4 (because 2m =16 gives m = 4).

DIGITAL PRINCIPLES AND CIRCUITS

So +--

5,

Select-inputs

Data Enable inputs E

~ __i-J-J=~~=r1 +------ ---- --- ---- -------

.

~--~J-1=$=~=r~ +------ -------- ---- -------

=___=___:i__=___= _ .=___=_ n

~ -~__-___-!: __

~--l-~==~===r: 1 ______ - - - - - - - - - - - - - - - - - - - - - -

Truth Table Select inputs S1 So 0 0 1 1

0 1 0 1

Output

y Do D1 D2 D3

Fig. 6.33 A 4:1 line multiplexer with truth table

Fig. 6.33 shows the circuit of a 4:1 line MUX using four AND gates and one OR gate which are connected as the AND-OR logic. It has two select inputs (8 1 and 8 0) and four data-inputs (Do, Dh D 2 , D 3 ). Each AND gate receives two select-inputs, one of four data-inputs and one enable signal (E) which is optional. The" output of each AND gate goes to the OR gate which yields the selected data at its output Y. The different values of select-inputs for each datainput to be selected, are given in the associated truth table. The logic equation derived from this truth table can be written as Y = fh

So Do + 81 8 0 D1 + 8 1 So D2 + 8 1 8 0 D3

This equation provides selected data-bit at the output Y when appropriate values of 8 18 0 are put into it. That is, When

8 1 8 0 =00, we get Y=D o

When

8 1 8 0 =01, we get Y=D 1

When

8 1 8 0 =10, we get Y=D 2

When

8 1 8 0 =11, we get Y=D 3

Enable Input To start or stop the passage of data from input to the output, a separate control (enable) signal E can be optionally connected to each AND gate, as shown by the dashed lines in Fig. 6.32. When E = 1, the input data-bit is passed by the respective AND gate if excited with the correct select-input. However, no data can pass when E = 0, because each gate would be disabled. Expansion

The circuit of Fig. 6.33 of 4:1 line MUX can be expanded to have more input lines by adding more AND gates and select-inputs. Thus to form an 8:1 line MUX, we would require eight AND gates of 5 inputs each, and three select-inputs. Similarly, to form a 16:1 line MUX, sixteen AND gates of 6 inputs each and four select-inputs would be required. Higher-order MUXs can also be obtained by combining several identical MUXs of lower orders.

239

COMBINATIONAL CIRCUITS Example 6.10 Design a 2:1 line MUX using AND-OR logic.

Solution A 2:1 line MUX requires two AND gates and one OR gate which can be connected as shown in Fig. E 6.10. It requires one select input (S), because 2m = 2 gives m = 1.

s

j! y

o

Do

1

01

Fig. E 6.10

The data bit Do is transmitted to the output when S as obtained from the logic equation

=0, and Dl is transmitted when S =1,

Example 6.11 Connect three MUXs of2:1line each to build a 4:1 line MUX. Solution A 2:1 line MUX has two data-inputs and one select-input. To build a 4:1 line MUX, three such MUXs can be connected as shown in Fig. E 6.11, in which the outputs from Muxland MUX2 are used as the select-inputs to MUX3. The bits Do and D1 ~re the data-inputs to MUXI and D2 and D3 for the MUX2' SO is the common select-input for these MUXs while S1 is that for MUXa. Truth Table

2:1 Do 01 y O2

03

81

80

Y1

Y2

Ya

0 0 1 1

0 1 0 1

Do D1 Do D1

D2 Da D2 Da

Do D1 D2 Da

Fig. E 6.11 A 4:1 line MUX

Since the logic equations for MUX1 and MUX2 are: Y1 = So Do +SOD1 Y 2 = SoD2 +SoD3

the logic equation for MUX3 (with Y 1 and Y 2 as data-inputs) will be Y = SlY1 + S1Y2

=Sl (So Do + SoD1) + S1 (SoD 2 + SoDa) =~~~+~So~+~So~+~So~

DIGITAL PRINCIPLES AND CiRCUITS

240

which provides the output Y for each set of select-inputs 8 1 8 0 , as given in the truth table. In this way, this circuit acts as a 4:1 line MUX with Do, Db D 2 , D3 as the four data-inputs and 8 18 0 as the select-inputs. Example 6.12 Connect two 74151 MUXs to obtain a 16:1 line MUX using OR gate and an INVERTER.

Solution The 74151 is a quad which contains four similar MUXs of 8:1 line each, for which the logic symbol is shown in fig. E 6.12 (a). It has eight data-inputs (10 ... 17 ), three selectinputs (8 28 18 0 ), one active low enable E, and two normal and inverted outputs Y and Y. MUX2

h Select inputs

t

··

74151:

Data inputs

10 11 •

•

•

•

•

h 53- - - - d 5 2 +--+1 5 1 -+-1-.--.t 50 -+-I-h--.t

E Outputs_

y

y

(b) A 16:1 Mux using two 74151s

(a) Logic symbol

Fig. E 6.12

Formation of a 16:1 line MUX, using two 74151s is shown in Fig. E 6.12 (b) in which the first eight data-bits (10 ...17) are applied to MUX1 and the remaining eight bits (18 ...115 ) are applied to MUX2' The three select-inputs 8 2 8 1 8 0 are common to both units, while the fourth selectinput 8 3 acts as the en~ble E, which determines which of these MUXs is enable enabled. The outputs Y 1 and Y 2 arE; ORed to provide the final output Y. When 8 3 = 0, Mux1is enabled, and the inputs 8 28 18 0 determine which of the data-bits (10 ...17) goes to the output Y 1 and then to Y. When 8 3 = 1, MUX2 is enabled, and the inputs 8 2 8 1 8 0 determine which of the data-bits (18 ...115 ) goes to the output Y 2 , and then to Y. In this way, this circuit acts as a 16:1 line MUX with 16 data-inputs (10 ...1 15 ) and four select-inputs 8 3 8 2 8 18 0 , 6.29 MULTIPLEXER TREE

Higher-order multipliers with input-lines normally beyond 16 can be organised by combining two or more multiplexers of lower order. This can be done in a number of different ways. For example, in the formation of a 32:1 MUX, its 32 input lines can be achieved in any of the following ways:

(0 Connecting two 16:1 MUXs in a single level would give rise to 16 x 2 = 32 input lines.

COMBINATIONAL CIRCUITS

241

(ii) Connecting four 8:1 MUXs in one level and one 4:1 MUX in another level, would give

rise to 8 x 4 =32 input lines. (iii) Connecting eight 4:1 MUXs in one level and one 8:1 MUX in another level, would also give rise to 4 x 8 =32 input lines.

Single-level organisation of case (i) is illustrated in Example 6.13, while the two-level organisations of cases (U) and (iii) are illustrated in Example 16.14. To achieve still more input lines, a third level of MUXS can be organised. All these structures of MUXs, in general, are often referred to as MUX "trees". Example 6.13 Organise a 32:1 MUX connecting two 16:1 MUXs in a single level and one gate.

OR

Solution The given 16:1 chips (MUXI and MUX2) are connected as shown in Fig. E 6.13 in which Sa S2 Sl So are the common select-inputs to each chip, and the enable signal E is used to enable one chip at a time. MUXI receives 16 bits (DO ... D 15 ) as the data inputs, of which one bit is transmitted to the output Y1 and then to Y through the OR gate. MUX2 receives the other 16 bits (DIS'" D a1 ) with one bit transmitted to Y 2 and then to Y. ~ 52 51 So +- Select inputs D. Data: 0 inputs:

D15

E----+ D Data :16 inputs ; D31

53 52 5 1 50

Fig. E 6.13 A 32:1

MUX

using two 16:1

MUXs

When the enable signal is E = 1, MUXI selects one of the bits D o...D 15 according to the applied select inputs Sa S2 Sl So, and transmits it to the output Y1and then to Y. When E = 0 , MUX2 is enabled and one of the bits Dls ... Dal is transmitted to Y 2 and then to Y according to the select-inputs. In this way, this 32:1 MUX selects one bit from the Do ... Dal data bits and transmits it to the output. Example 6.14 Organise a 32:1 MUX using the 8:1 and 4:1 MUXs in two levels.

Solution The required 32:1 MUX can be organised in two ways, as illustrated in Figs. E 6.14 (a) and (b), and explained iIi the following.

DIGITAL PRINCIPLES AND CIRCUITS

242 Fig. E 6.14 (0)

In this organisation, four 8:1 MUXs (designated N 2 ) are arranged in one level with their outputs connected to the 4:1 MUX (designated N 1 ) in the second level. The select inputs eBA belong to each MUX N 2, and ED belong to the MUX N l' The total number of input lines in this organisation thus becomes N2lV1= 8 x 4 = 32 receiving the data-inputs Do through D 31 . The top MUX N 2 ,0 places the inputs Do through D7 in- sequence on to the line Lo as the select-inputs eBA change from 000 through 111. Similarly, the next MUX N 2 , 1 passes the inputs Ds through D 15 to the line L1 as the select-inputs eBA change from 000 through 111. In the same manner, the other MUXs N2,2 and N 2,3 also pass their respective inputs to the Data

B A

C B A

~o~

D3~

~4 D7 -'----'

N2 =4:1 (a) N2Nl

=8 x 4 =32 input lines

(b) N2Nl = 4 x 8 = 32 input lines

Fig. E 6.14 Two 32:1 MUXs as 2-level trees

lines, L2 and L3 each. Now, MuxN1 selects one of the lines L o... L 3 and transfers its data to the output Y using ED as the select-inputs. For example, to transmit a data input D 20 through L2 to the output Y, we would apply the select inputs eBA =100 and ED = 10, i.e. EDCBA = 10100 to the 32:1 MUX of Fig. E 6.13 (a). Fig. E 6.14 (b)

In this organisation, eight 4:1 MUXs (designated N 2 ) are arranged in one level with their outputs connected to the 8:1 MUX (designated as N 1) in the second level. This arrangement also provides the total number of input lines as N2 N1 = 4 x 8 = 32. The select-inputs in this

243

COMBINATIONAL CIRCUITS

case are BA for each MUX N2 and EDC for Nt. i.e. EDCBA for the complete organisation. The operation of this MUX can be described as in the case of Fig. E 6.14 (a). 6.30 WORD MULTIPLEXER

A word multiplexer selects one of several words, instead of bits at the input and transmits it to the output. Fig. 6.34 shows a 1-of-2-word (nibble) selector/multiplexer which selects one of the two data-words A =A3A2AIAo and B =B3 B2 BIBo by using a control signal S. There are eight AND gates in two groups, and four OR gates of 2 inputs each. When the control signal is S = 0, the first group of four AND gates on the left is enabled so that the word A is passed on to the output through the OR gates. When S = 1, the other group of AND gates on the right is enabled and the word B is passed on to the output through the OR gates. In this way, either of the two words at the input can be allowed to appear at the output by controlling the signal S.

. a

WORD A

WORD

S--~------;----r--~----r---~+-~-r~-r~~-

Control signal

Output word (A or a)

Fig. 6.34 A 1-of-2 nibble selector/multiplexer

Expansion

The circuit of Fig. 6.34 can be expanded to allow more number of words at the data-inputs, and select one of them, by increasing the number of gates and the number of inputs to each gate. To allow n data-words of m bits each the circuit would have the following requirements: Number of groups of AND gates =n Number of AND gates in each group =m Number of OR gates = m Number of inputs to each OR gate Number of inputs to each AND gate

=n =2

DIGITAL PRINCIPLES AND CIRCUITS

244 6.31 DEMULTIPLEXER

A demultiplexer (DMUX) acts in a reverse way to a multiplexer. That is, it receives a single data-input and transmits it to one of the output lines by means of an appropriate input address. In a l:n line DMUX, to select one of the n output lines we would require an address of m bits, such that 2 m =n. The 1:8 line DMUX, shown in Fig. 6.35, uses eight AND (or NAND) gates and a 3-bit address CBA (because 2m = 8 gives m = 3) which is required to select one of the 8 output lines, to which the data D has to be transmitted. The operation of this circuit is explained below using the truth table given in Table 6.10 for the transfer of data D = a . To transfer the data D = 1, another truthtable would be required.

c

B

A

+ - Address input

Data input

Output lines

D

t

r-1I~~==$=~~~~o~

0

• • Fig. 6.35 A 1:8 line demultiplexer Table 6.10 Truth table for 1:8 demultiplexer for D

Data input

Address inputs

Output lines

D

C

0

0

B 0

A

0 0

0

0

0

0

0

0

0 1 1 1 1

1 1 0 0 1 1

1 0 1 0 1

0 1 1 1 1 1 1 1

0 0 0 0

0

1

=0

1 1 0 1 1 1 1 1 1

2

1 1 0 1 1 1 1 1

3 1 1 1 0

1 1 1 1

4

1 1 1 1 0 1

1 1

5 1 1 1 1 1 0

1 1

6 1 1 1 1 1 1

7

0

1 1 1 1 1 1 1

1

0

Operation From the first row of truth table, when the address in CBA = 000, the top AND gate a is disabled, and the data D = a is transmitted to the output line O. Similarly, the address CBA = 001 disables the AND gate 1, and the data D = 0 appears at the output line 1, and so on. However, to transmit a data D = 1 , another truth table has to be prepared by interchanging all the as and Is of the output lines of Table 6.10. NOTE Using

NAND

gates in place of AND gates to form a

DMUX

would provide active-low outputs.

245

COMBINATIONAL CIRCUITS Example 6.15 Draw the circuit for a 1:2 line working.

DMUX

using D

NAND

gates and explain its

A

Solution A 1:2 DMUX transmits a single input data to one of the two output lines by using a one-bit address. It requires two NAND gates, as connected in fig. E 6. 15. When the address is A = 0, the complement jj of data D appears on the output line 0, and whenA = 1, jj appears on the line 1. Fig. E 6.15

6.32 DEMULTIPLEXER TREE

Higher-order demultiplexers for more than 16 output lines can be organised by arranging 2, 4, 8, or 16 line packages in a "tree" form to yield the desired number of lines. Two such organisations of 32 lines each are illustrated in Figs. 6.36 (a) and (b). Fig. 6.36 (a) shows a DMUX tree for N = 32 output lines using N t = 4-line DMUX as 'trunk' and four N2 = 8-line DMUXs as 'branches', so that the total number of lines becomes N = N 1N 2 = 4 x 8 = 32. The first eight lines (0 through 7) are decoded by MUX N 2 , 0, next eight lines by N 2 , 1, and so on. When the address ED =00 is applied to Nt, the lines 0 through 7 B A

C B A ED=OO

o ,---:-_..-_ 7

8 11

12 15

Data

Data

16 19 20 23

11

24

24 27

31

28 31

N2 =1:4 (a) N

=N1N2 =4 x 8 =32 output lines Fig. 6.36 Two 1:32 lines

(b) N =N1N2 = 8 x 4 = 32 output lines DMUX

trees

DIGITAL PRINCIPLES AND CIRCUITS

are decoded in sequence as the address CBA changes from 000 through 111. Similarly, the lines 8 through 15 are decoded by N 2, 1 in sequence with the addresses ED = 01 and CBA = 000 through 111. In this way the address for decoding the lines 16 through 23 would beED = 10, and for the lines 24 through 31, it would be ED = 11, with CBA = 000 through 111 in each case. Thus, if we have to decode a particular line 5, then we would have to apply the address EDCBA = 00101. The DMUX of Fig. 6.36 (b) is organised to provide the N = Nl N2 =8 x 4 = 32 output lines by arranging N 1= 8-line DMUX as 'trunk' and eight N2 = 4-line DMUXs as 'branches'. Each N2 DMUX (from N 2, 0 through N 2, 7) decodes the corresponding group of four lines using the address BA, while the DMUX, Nl uses the address EDC, thus forming the complete address asEDCBA. The designs of a 1:32 line DMUX shown in Figs. (a) and (b) are called 'single-level branching'. This DMUX can also be designed with 'two-level branching' by adding one more level of DMUXS (Ns) so that N = Nl N2 Ns = 4 x 4 x 2, or N = NIN~s= 8 x 2 x 2. However, the choice of a particular design depends on the cost and certain other factors involved. 6.33 DECODER/DEMULTIPLEXER

Some of the decoders which have enable inputs, can also be used to function as a demultiplexer. Such ICs are marked as decoder / demultiplexer, and can be used for either function. For example, the 74138 (3-to-8-1ine decoder) as shown in Fig. 6.32 can be used as a 1:8 line demultiplexer if we use the enable input E 1 as the data-input (D) of the demultiplexer and keep the other inputs E 2 and Es in the active states, i.e. E2 =E3= 1. Using the inputsA2AIAofor the address-inputs (CBA) of the demultiplexer, this Ie would transmit the data D to one of the eight output lines corresponding to the address. Thus, as the address A2AIAo successively changes from 000 through 111, the data D (0 or 1) would appear at the output Yo ...1'7. That is, when E 1 =D =0 and E2 = E3= ~, the input AND gate of 74138 is enabled, and the output line corresponding to the addressA2AIAowould-go low (0). This indicates that the data D = 0 is transmitted to this output line. When E 1 = D = 1, and E 2 = E 3= 1, the input AND gate is disabled, so that the output line corresponding to the address A2Al Ao goes high (1) which indicates the transmission of data D = 1 to this output line. 6.34

DEMULTIPLEXER APPLICATIONS

Demultiplexers are used in a variety of applications in which we want to transmit a given data to one of many channels. They are widely used as binary-to-decimal decoders. The 74138 is a 1:8 line demultiplexer package which can be used as a clock-demultiplexer that transmits a clock signal to one of 8 destinations under the control of a select signal. Security-monitoring systems, such as used in industrial plants to open/close many access doors, also use demultiplexers. They are also used in synchronous data-transmission systems where we want 0 serially transmit several data words from a transmitter to a remote receiver. 6.35 DIGITAL COMPARATORS

A digital comparator (or magnitude comparator) is a logic circuit that compares the magnitudes of two bits (or words). to determine whether they are equal, unequal, or which

247

COMBINATIONAL CIRCUITS

one is greater or less than the other. Although an XNOR gate determines the equality or inequality of the two bits applied to its input, however, it cannot tell which bit is greater or less than the other. To meet this end, comparator circuits have been designed using XNOR gates along with the other gates.

1· bit Comparator A I-bit comparator compares one bit with another. Fig. 6.37 shows a 1-bit comparator using one XNOR gate, two AND gates and two INVERTERs. It compares the bits A and B applied at the input and determines whether A =B ,A> B, or A < B, as explained below. (a) A > B is determined by the upper AND gate which receives the inputs A and Ii, and produces the output as ' Y1=AB Y1 =AB = 1 (A> B)

=0 (A < B, A =B) /

-

A--+-+------\:~-......

B--t-t-----H

'------D--

Y2 =AB+AB = 1 (A= B) =0 (A < B, A > B)

Y3 =AB

=1 (A< B) =0 (A> B, A =B)

Fig. 6.37 A i-bit comparator (i) When we get Y1

= 1 ,it determines that A > B.

When Y1 = 0, it determines that either A < B , or A =B. (b) A =B is determined by the XOR gate with the inputs of A and B and producing the output as (ii)

Y 2 =(A B +AB) (i) When we get Y2 = 1 ,it determines that A =B. (ii) When Y 2 (c) A < B

=0, it determines that A *B.,

is determined by the lower produces the output as

AND

gate which receives the inputs A and B , and

Y 3 =AB When we get Y3 = 1 , it determines that A < B. (ii) When we get Y3 = 0, it determines that A > B, or A = B. The above analysis can be summarised as follows: (a) When Y1 = 1 (with Y2 =Y3 =0), the result would be: A> B (b) When Y2 = 1 (with Y1 =Y3 =0), the result would be : A =B (c) When Y3 = 1 (with Y1 =Y2 = 0), the result would be : A < B (i)

.

248

DIGITAL PRINCIPLES AND CIRCUITS

That is, whichever of the three outputs (Yb Y 2 , Y 3 ) goes high, with the others low, the result would be the corresponding comparison. 2 - bit Comparator

A 2-bit comparator compares two words of two bits each. Fig. 6.38 shows the circuit and truth table for a 2-bit comparator which receives the two words A2 Al (= A) and B2B 1 (=B) at the input, and produces three outputs marked as YA>B, YA=B and YAB

::AJj2 +Al.8l(A~2) +A~2) ::A~2 +Al.8t"A~2·A~2 ::A~2 + Al.8 l B and h < B are grounded and I A =B is connected to +5V supply. The siIIljllarly or dissimilarity of the words is indicated by whichever output goes high. Example 6.17 Connect two 7485s to form an 8-bit comparator.

Solution To form an 8-bit comparator, two 7485s can be cascaded, as shown in Fig. E 6.17, which would compare two 8-bit words, such as A = A7AsA.5A4AaA2AIAo and B = B7B6BrJJ4BsB2BIBo. The outputs of the lower chip receiving the lower-order bits A3A2AIAo and B3 B~lBo are connected to the respective inputs of the higher chip receiving the higherorder bits A~s A5A4 and B7 Bs B5 B 4. The cascading inputs IA > Band IA < B of the lower chip are connected to ground, while IA =B is connected to +5V supply.

250

DIGITAL PRINCIPLES AND CIRCUITS Lower-order bits Aa~A1Ao

+5V

8 3 8 2 8 1 80

Higher-order bits A7

Ae

As A4

a.,

86 8s 84

7485

7485

High output for 8-bit comparison Fig. E 6.17 An 8-bit Comparator using two 7485s

The result of comparison whether A higher-order chip, which goes high

6.36

=B, or A i:.B would be indicated by that output of the

COMPARATOR APPLICATIONS

Digital comparators are used in address decoding parts of computers to compare an address-code generated by the CPU. They are also used in control applications where a binary number representing some physical quantity such as speed, etc. is compared with a reference value, and the resulting output is used to drive the quantity toward the reference value.

6.37 SERIAL ADDER A serial adder adds column by column and a carry is raised each time to the next higher column. Each. number augend and addend is presented as a train of pulses and they are added pulse by pulse starting from the LSB pulse. In this process, the carry-pulse has to be delayed by one clock-period before it is presented for addition to the next higher pulses, A separate unit meant for this purpose is termed as time-delay unit. Fig. 6.40 (a) shows the block diagram of a serial adder that uses a full adder (FA) and a time-delay (TD) unit. The TD unit receives the carry output (Co) from FA, and returns it (as C i ) after a delay of one clock-period, i.e. at the occurrence of next clock-pulse (CP). Let us explain the following addition pulse-by-pulse 0110~

Carry Ci Augend B = 0011 Addend S =01001 Sum

A = 0110

The pulse waveforms for each sjgnal (A, B, Co, Ci and S)are drawn in Fig. 6.40 (b) in which a low pulse indicates a 0 and a high pulse indicates a 1.

251

COMBINATIONAL CIRCUITS

A~

TO unit

I

FLIP-FLOP

I

-

c

K

Jn

J

A~

-J

-- 750) Example 8.15 How many flip-flops are used in a 3-stage BCD counter? Indicate the states of each flip-flop just after the occurance of: (a) 265 pulses and (b) 897 pulses

326

DIGITAL PRINCIPLES AND CIRCUITS

Solution A 3-stage BCD counter uses 3 x 4 = 12 flip-flops. (a) At the 265th pulse, the states of these flip-flops are : Hundreds counter Tens counter Units counter DCBA 0011

DCBA 0110

At the 266th pulse, these states would be as : o0 1 1 0 1 1 0

DCBA 0101

o

1 1 0

(b) At the 897th pulse, the flip-flop 8tates are : DCBA 1 000

DCBA 100 1

At the 898th pulse, these states would be as: 1 0 0 0 100 1

DCBA o1 1 1

o

0 0 0

8.26 DESIGNING A COUNTER A synchronous counter of any modulus and any counting sequence, can be designed by using Karnaugh maps. In this method, the basic data we need, is the counting sequence through which the counter has to go. Let us take to design a mod-5 counter that follows the natural binary counting sequence. The procedure to design such a counter is given below :

Procedure 1. Determine the number of flip-flops and select their type. In the present case, we need 3 flip-flops, say of T type. 2. Make a Table for counting sequence, such as Table 8.3(a), which lists the counting sequence from CBA =000 upto 100. 3. Make excitation Table, such as Table 8.3(b), for the type of flip-flop used. This table lists all the T inputs required for each pair of the present (Q) and next (Ql) states of the T flip-flop. For this flip-flop, the input is T = 1 when the flip-flop changes state (Q changes from 0 to 1, or from 1 to 0), otherwise it is T = O. ' 4. Using the excitation table, determine the required input to each flip-flop and tabulate them as illustrated in Table 8.3(c). Here, the input Tl for the flip-flop A is Tl = 1 when A changes from 0 to 1, or from 1 to 0, otherwise Tl = O. In the same manner, T2 and T3 are obtained for Band C. Table 8.3(a) Counting

,

Table 8.3(b) Excitalia Table for T flip-flop

Count 0 1 2 3

C 0

B 0

0 0 0

0

1 1

0

4

1 0

0

0

Reset

0

A

0 1 1 0

Present State Next State Q Ql

Input T

0

0

0

0

1

1

1 1

0

1

1

0

327

• DIGITAL COUNTERS Table 8.3 (c) Determining Tl> T 2 • T3 inputs C 0

0 0 0

1 0

B

Ta

· ... · ... · ... · ... · ...

A

T2

0

Tl

0

· ., . 1

· ... 0

0 0

· ... · ... · ... ....

0

1 0

1 1 0

1

1

· ... · ... · ...

1 0 0

1 1 0

1 1 1

· ... 0

0

0

0

5. Making the K-maps. Make K-maps as given in Fig. 8.20 for each of the inputs, i.e. Tb T2 and Ta. Each map has 8 squares (for the three \i-ariables A, B, C) whose abscissa is labelled with CB and ordinate with A. In the first map (for T 1 ), enter 1 and 0 values of Tl from Table 8·3(c). The four Is that appear in the first four rows of this Table are entered in the map squares corresponding to the states CBA = 000, 001, 010 and 011, while the single 0 from the fifth row is ~ntered in the square for CBA = 100. The remaining 3 empty squares are filled with the don't care ~s for the states CBA = 101, 110 and 111 because they are not included in the mod-5 counter. K-maps for T2 and Ta are also obtained in the same manner. CB 00

A 0

1

01

11

10

1

1

cjl

0

1

1

cjl

cjl

CB 00

01

11

10

0

0

cjl

0

1 [1

1

cjl

cjl).l

A 0

CB 00

A

-

A

01

11

10

cjl

11"1r- c

cjlJ

cjl

0

0

0

1

0

(1

AB

Tz

Fig. 8·20 K-maps to design mod-5 counter

6. Solving these K-maps, we get the following expressions for the three inputs, i.e. T 1 =C,

T 2 =A,

Ta=AB+C

7. Using these inputs and a proper gating network, the desired mod-5 counter can be realised as shown in Fig. 8.21. A

B

C (MSB)

CP------~----_r----~----+_----__.

Fig. 8.21 Mod-5 synchronous counter designed using K-map

DIGITAL PRINCIPLES AND CIRCUITS

328

8.27 IC COUNTERS IC counters are commercially available in several versions, both in asynchronous and synchronous categories. Some of the popular types available in MSI are listed in Table 8.4 where each box contains ICs of similar features. Table 8.4 Asynchronous and Synchronous IC counters Asynchronous Counters

Synchronous Counters

leNa.

Function

Ie No.

Function

7490, 74290

BCD Counter

74160, 74162

Decade

Up-Counter

7492

Mod-12 Counter

74161, 74163

Mod-16

Up-Counter

7493, 74293

Mod-16 Counter

74168

Decade Up/Dn Counter

74176, 74196

Presettable BCD Counter

74169

Mod-16 Up/Dn Counter

74177,74197

Presettable Mod-16 Counter

74190 74191

Decade UplDn Counter Mod-16 UplDn Counter

74390 74393 74490

Dual Decade Counter Dual Mod-16 Counter Dual BCD Counter

74192 74193

Decade UplDn Counter Mod-16 Up/Dn Counter

.

I

8.28 ASYNCHRONOUS IC COUNTERS The asynchronous counter 7490 is a BCD decade counter whose basic structure is shown in Fig. 8.22. It consists of two separate sections: mod-2 counter (flip-flop A) and mod-5 counter (flip-flops B, C and D), which can be used independently or in combination. Both the reset inputs (R 1 and R 2 ) are kept high for clearing all the flip-flops. Both the set inputs (8 1 and 8 2 ) are also kept high, when the counter is to be set at 1001 count. Outputs

0 4 (MSB)

I

I Ar-

Clock input A

Mode-2

r:>

B

C

I

I

D

Mode-5

7490

Clock input B

I

I

I

I

Fig. 8.22 Basic structure of 74900 IC counter

7490 as Divide-by-l0 Counter When the output Qb in Fig. 8.22, is connected to input B, and clock pulses are applied at input A, mod-2 counter is followed by mod-5 counter, thus forming a normal BCD decade

DIGITAL COUNTERS

329

(devide-by-lO) counter that progresses in the natural binary sequence. On the other hand, if the output Q 4 is connected to input A, and clock pulses are applied at input B, the mod-2 counter follows the mod-5 counter, and the two again form a decade counter, but not BCD, because the counting sequence this time, is not the natural binary. Table 8.5 gives the counting sequence for both the cases. Table 8.5 Counting sequence

Count

I

(Mod-5)

(Mod-5)

(Mod-2)

Ql

Q4

Q3

Q2

Ql

0 0 0 0

0 0

0

1 1

0

0 0 0

0 0

0 0 0 0 0

1 1

0

0

0

Q4

Q3

Q2

0 0 0 0

0 0

0

1 1

0

1 1 1 1

0 0

0

1

1

1 1

0

7

0 0 0 0 0 0 0 0

8 9

1 1

0 0

0 0

0

0 0 0 0

1

1

0

II

(Mod-2)

1 2 3 4 5 6

1 1

1

1 1

1 1

I

1 1 1 1 1

7490 as Divide-by-6 Counter The 7490 can be used as a divide -by-6 counter when it is connected as shown in Fig. 8.23. Connecting Ql to input B, turns it into a normal divide-by-IO counter, as described earlier. Now, if the outputs Q2 and Q3 are connected to the reset inputs Rl and R 2, the counting goes only upto Q4Q3Q2Ql = 0101, after which the counter resets to 0000. This is so because at the count N = 6 (Q4Q3Q2Ql = 0110), only Q2 and Q3 go high. Thus the unit acts as a divide-by-6 counter. 0,

7490 Input A

5, ~~----~~--~------~~

Fig. 8.23 Divide-by-6 counter using IC 7490 7492/7493/7~

IC Counters

These asynchronous IC counters, as shown in Fig. 8.24, slightly differ from the 7490 counter in that they have no set inputs.

330

DIGITAL PRINCIPLES AND CIRCUITS Outputs

0,

Clock input A

-c ">

Al-

Mode-2

0 4 (MSS)

B

rC P.

D

C

Mode-6

Mode-8

7492

7493n4293

I

I

R,

Clock input B

R2 Reset inputs

Fig. 8.24 Basic structure of 749217493174293 Ie counters

The 7492 is a mod-12 unit that has two separate sections of mod-2 and mod-6 counters, whereas the 7493 and 74293 each is a mod-16 unit with mod-2 and mod-8 sections. Each section can be used independently or in combination with the other. When the output Q 1 in 7492 is connected to the clock input B, and clock pulses are applied at input A, the counter counts upto 12 pulses in the natural sequence. The output waveforms at Q2, Q3 and Q4 are the divisions by 2, 6 and 12, respectively, i.e. their frequencies are one-half, one-sixth and one-twelfth of the clock frequency. In the case of 7493 and 74293 earh, the frequency divisions are by 2,8 and 16.

Example S.16 Show how the 74293 can be wired as a mod-lO counter. Solution The 74293 is an asynchronous counter unit that has two sections: mod-2 and mod-So The clock input A, output Ql and the reset input Rl refer to mod-2 section, while the clock input B, outputs Q2, Q3, Q4 and reset input R2 refer to mod-S section. To convert it into mod-16 counter, we must connect Ql output ofmod-2 to the clock input B of mod-8. Now to convert this mod-16 into mod-10, it must be reset at the count N ::: 10 (Q4Q3Q2Ql ::: 1010). Therefore the outputs Q2 and Q4 must be connected to the reset inputs Rl and R2 (Fig. E 8.16) because they go high at the count N = 10.

Input A

74293

L-

Input B

R,

R2

I

L

Fig. E 8.16 Mod-lO counter

331

DIGITAL COUNTERS

Example 8.17 Show how the 74293 can be wired to obtain an output frequency 2kpps (killo pulses per second) for an input clock frequency of 30 kpps. Solution For the given problem, we require a mod-15 (divide-by-15) counter, because 30 kpps/2 kpps = 15. The wiring is shown in Fig. E 8.17.

;}--

-

Input A (30 kHz)

74293

-c ~

Input B

R,

R2

I

I

Fig. E 8.17 Mod-15 counter

Connecting Ql to input B converts 74293 into mod-16 counter. To convert it into mod-15, the 16th state must be skipped off by resetting the counter at N = 15 state. Because Q4Q3Q2Ql = 1111 at this state, each output must be directly connected to the reset inputRl or R2 (the other grounded). Alternatively, Q4 can be connected to R2 and the other three to Rl through an AND gate, as shown in Fig. E 8.16. In this way, the frequency at Q4 will be 2 kHz 74176/74177/74196/74197 IC Counters The 74176 and 74196 each is a BCD counter with mod-2 and mod-5 independent sections, while the 74177 and 74197 each is a mod-16 unit having the mod-2 and mod-8 sections. These counters have Clear, Load and Preset inputs, as shown in Fig. 8.25. The clear and load inputs are active-low (shown by small circles). Keeping the clear input low, clears the Outputs

Q,

Clock Input A

Q4 (MSB)

B

A-

C

D

-c~

Mod-2 Clear --< Input

'( Clear Clock Input Input B

P- Load Mod-5

Mod-8

74176174196

74177174197

I

P,

I

I

I

P4 (MSB)

Preset inputs

Fig. 8.25 Basic structure of 74176174196174177174197

Ie counters

332

DIGITAL PRINCIPLES AND CIRCUITS

counter. To start normal counting, both the clear and load inputs should be kept high. When the load input is kept low (and clear high), the counting stops, and any binary number present at the preset inputs (P4P3P 2P l) is loaded into the counter. Variable-mod counter Any of the above mod-16 counters (74177 and 74197) can be used as a variable mod-N counter, such that N= 15-P

or

P= 15-N

where P is the decimal equivalent of the preset count P~3P2Pl applied at the preset inputs. For example, to make a mod-ll counter using 74177174197, we should have

P = 15 - N

= 15 -

11 = 4 (0100)

i.e. the preset count This means that when we apply this preset count 0100 at the preset inputs P 4, P 3, P 2 , P b the counter will return to this count as soon as the load signal is driven low at the highest count of Q4Q3Q2Ql = 1111. Example 8.18 Obtain a divide-by-7 counter using the Ie 74177, and indicate the seven states of the counter. Solution Fig. E 8.18 gives the required counter circuit in which we first obtain the mod-16 counter by connecting Ql to inputB and applying clock pulses to inputA. To obtain mod-7 counter, we have P= 15 -N =15-7 =8 (1000)

z.e Preset count

P4PaP2Pl

=1000

Thus, we apply this count to the preset inputs. To load it into the counter the load signal must go low at the highest count 1111, for which we use a NAND gate, as shown in the Figure. The seven counter-states are :

Input B

74177 Clock---GI> Input A Clear Clear

Load

Preset States 100 1001 1010 Recycles 1011 back 1100 1101 1110 1111

+ Vee

Fig. E 8.18 Divide-by-7 counter using the IC 74177

333

DIGITAL COUNTERS 74390/74393/74490 ICCounters

The 74390,74393 and 74490 are the dual units which have two mod-10. two mod-16 and two BCD counters, respectively. Each unit in itself, or in association with the other, can be connected to obtain higher moduli.

8.29 SYNCHRONOUS IC COUNTERS All the synchronous IC counters listed in Table 7.4 are positive-edge-triggered and each of them has two enable inputs (ENP and ENT), as given in Fig. 8.26 representing one group of ICs. Keeping either of these inputs low, stops the counting asynchronously. Ripple carry (RC) output is normally low, and goes high whenever the counter reaches the highest count (1001 for decade counters, and 1111 for mod-16 counters). Keeping ENT low, also inhabits RC going from low to high. O2

01

RC

0 4 (MSB)

03

CP ENT

7416on4162

(Decade)

74161n4163

(Mod-16)

ENP

Load

Clear

P1

P2

P3

P4

(MSB)

Fig. 8.26 Block diagram of synchronous Ie counters

The 71160 and 74162 each is a decade counter, and can be used to obtain a counter of any modulus Jess than 10. The 74161 and 74163 each is a mod-16 counter, and can be used to make any modulus less than 16. An example follows.

Example 8.19 Obtain a natural binary mod-12 counter using IC 74161. Solution The IC 74161 is a mod-16 counter, using which, Fig. E 8.19 gives the required mod-12 counter that counts from 0000 through 1011 (decimal 11). The 2-input NAND gate, 01

CP--I>

ENT

74161 (Mod-16)

ENP

Fig. E 8.19 Mod

counter using 74161

334

DIGITAL PRINCIPLES AND CIRCUITS

connected between Q3 and Q4 and the clear input, clears the counter, as soon as it reaches the N = 12 (1100) count. The input ENT and ENP each is kept at high. Example 8.20 Obtain a divide-by-9 counter using 74163. Solution The Ie 74163 is a mod-16 synchronous counter which can be converted into a divide-by-9 counter by presetting it at P = 16 - 9 = 7 (0111) count. Fig. E 8.20 gives the arrangement. As soon as the RC output goes high, at the highest count 1111, the preset count P (0111) present at the preset inputs, is loaded into the counter. RC

CP ENT

74163 (Mod-16) Load

Clear

+ Vee

Fig. E 8.20 Mod-9 counter using IC 74163

The general rule to obtain any modulus N with this IC, is given by the preset inputs for mod-16 counter for decade counter

P = 16-N = 10-N

Thus, to obtain a divide-by-ll counter using 74163, we have P(P4PaP2Pl) = 16 - 11 = 5(0101), and for a divide-by-6 counter using 74162, we have P (P 4P 3P 2P 1 ) = 10 - 6 = 4 (0100), and so on. 74168/74169

Ie counters

The 74168 and 74169 each, as given by the block diagram in Fig. 8.27, is a synchronous up/down counter in which the enable 'inputs ENT and ENP are active-low. The RC (ripple 0,

O2

CP ENT ENP

o.

03

(MSB)

RC

(Decade) (Mod-16)

74168 74169

UP/ON P,

P2

P3

p.

(MSB)

Load

Fig. 8.27 Block diagram of 74168174169 IC counters

335

DIGITAL COUNTERS

carry) output, which is normally held high, goes low when the count reaches maximum during up-counting, and minimum during down-counting. Since there is no clear input terminal in these lCs, a NAND gate (connected between the counter outputs and load) can be used to terminate the count (if required), before it reaches the maximum. A desired starting state (other than 0000) of the counter can also be set by presetting the inputs correspondingly. 74190 174191 IC Counters

The 74190 and 74191 lCs are also the upldown counters, which have only one active-low enable input (EN), as given in the block diagram of Fig. 8.28. The MaxIMin output terminal, which is used to detect the maximum or minimum count, is held low, but it goes high, when the count is maximum during up-counting and minimum during downcounting. It also detects overflow (or underflow) in the up (or down) counting. The ripple carry (RC ), which is held high, goes low, when the counter reaches the maximum (or minimum) count, provided the CP input is low. RC Max/Min

Cp----~~--~--~~------~--~I

74190

(Decade)

74191

(Mod-16)

EN -----0 ON/UP - - - - - ;

Load

Fig. 8.28 Block diagram of '74190/74191 Ie counters

Frequency divider To use these counters (74190/74191) as frequency-dividers, the RC output is connected to the load input, and the required frequency-divided output-wavefrom is obtained at the MaxI Min terminal. When the preset inputs are set at a binary

74192

(Decade)

74193

(Mod-16)

CP-Dn - - - - I >

Clear---I

Load

Fig. 8.29 Block diagram of 74192n4193 IC counters

To use these counters as frequency-dividers, the Carry (or Borrow) output is connected to the load terminal for up (or down) counting. Rest of the procedure is similar to that described for the 74190n4191 ICs. 8.30 IC SHIFT-REGISTER COUNTERS

The ICs 74164, 74165, 74174, 74178 and 4731B are the shift-register packages, as described in Chapter 7, which can be used for constructing digital counters. A few examples are given in the following. Example 8.22 Show how the 74178 can be wired as a ring counter, and as a Johnson counter. Explain their working also. Solution The 74178 is a 4-bit PIPO/SIPO shift register with a parallel enable PE, a shift enable SE, and a serial-data input Ds along with four preset inputs PIP2P 3P 4 and four outputs QIQ2Q3Q4. It can be wired into a ring counter, as shown in Fig. E 8.22, in which the Q3 output is connected to the serial data input D s , and the initial count (say, 1000) is applied at the parallel-input terminals P 4P 3P 2P 1 •

337

DIGITAL COUNTERS

o

0

0

74178

cp

Sc

Fig. E 8.22 Ring counter using 74178

When PE = 1, and SE = 0, the preset count is loaded into the counter, giving Q ..QaQ2QI = 1000. Next, when PE =1, and SE =1, the single 1 at Q .. shifts back to QI at the first negative clock-edge, and goes on shifting ahead at the subsequent edges. To form a Johnson counter, an INVERTER must be connected between Q .. and Ds. The preset count is also changed to 0000.

Example 8.23 Show how two 741785 can be connected as an 8-bit ring counter. Solution The two 74178s will form an 8-bit ring counter, if we connect the Q .. output to theDs input of each other, as shown in Fig. E 8.23. The PE inputs of both are kept permanently high and their .clock-inputs are connected together. The essentially r SC,

74178

74178 S~

Fig. E 8.23 Two 741783 as 8-bit ring counter

When SE I = SE 2 = 0, the count (00010000), applied at the preset inputs, is loaded into the counter, giving

When SE I = SE2 =1, the single 1 shifts right to the next Q output at each clock pulse until it reaches the last output Q'1> after which it goes back to the output Q ... Thus, it circulates around the counter once per 8 clock pulses, going through the following states :

338

DIGITAL PRINCIPLES AND CIRCUITS

Initially 00 0 1 0 000 Preset State 00001000 at CP1 00000100 at CP2 00000010 at CP3 00000001 at CP4 10000000 at CP5 01000000 at CP6 at CP7 00100000 ' - - - - - - - - - - - - - at CP8 8.31 APPLICATIONS OF COUNTERS Counters are used in digital computers, data processing systems and industrial control systems for a variety of applications, some of which are : 1. 2. 3. 4. 5.

Direct counting. Dividing the frequency of a wave. Measuring a frequency and time. Measuring the distance or speed of an object. Counting the sequence of operations in a Computrr.

8.32 DIGITAL CLOCK One of the most important applications of digital counters is a digital clock that displays the daily time in terms of hours, minutes and seconds. The essential requirement in the construction of a digital clock is an accurately controlled basic clock-frequency, which can be obtained from a quartz-crystal oscillator, or from the ac-power line. Fig. 8.30 shows the black diagram for a digital clock operated with a clock frequency of 50 Hz. This arrangement has three sections : "seconds" section, "minutes" section and "hours" section. In the "seconds" and "minutes" sections each, the frequency is divided by 60 using a BCD counter and a mod-6 counter. How this clock arrangement operates is explained below.

50Hz Standard sine wave

Square wave generator

JlSL

' -_ _ _--.J

"Hours" section

50 pps

Mod-50 counter

1pps

"Minutes" section

Fig. 8.30 Block diagram of a digital clock

"Seconds" section

339

DIGITAL COUNTERS

First of all, the 50 Hz sine-wave signal obtained from a standard source is converted into square pulses at the rate of 50 pulses per second (pps) by a square wave generator. This 50 pps waveform goes through a mod-50 counter which divides the 50 pps to 1 pps. Now, the 1 pps signal is sent into the "seconds" section, which counts and displays seconds from 0 through 59. The BCD counter advances one count per second and recycles to o. This triggers mod-6 counter and causes it to advance by one count. This continues for 59 seconds, at which the mod-6 counter is at 101 (5) count, and the BCD counter is at 1001 (9), which in turn recycles the mod-6 counter to o. The output of mod-6 counter of "seconds" section which has a frequency of 1 ppm, is fed into the "minutes" section, which counts and displays minutes from 0 through 59. This section operates similar to the "seconds" section. The output of mod-6 counter of the "minutes" section which has a frequency of 1 pph, is fed to the "hours" section which counts and displays hours from 1 to 12. This section never goes to the zero-state like the "minutes" or "seconds" sections.

8.33 SUMMARY •

Counter circuits are formed by connecting flip-flops and gating network.

'. •

They can also function as the dividers of clock-frequency. Modulus of a counter is equal to the number of states through which the counter passes.

•

In a synchronous counter, all flip-flops are activated simultaneously by the same clock. In asynchronous counters, the flip-flops are not clocked synchronously. Ripple or asynchronous counters suffer from the problem of propagation-delay, which is considerably reduced in the synchronous counters. Ripple counters also suffer from the problem of short spikes that appear at the decoder outputs. Spikes can be removed by the strobing technique. Asynchronous mod-N (~ 2n) counter can be obtained from a basic mod-2n counter by skipping off the unwanted extra states. In a ring counter, the bits are circulated through the circuit, by shifting them serially from one flip-flop to the next. Up-counter counts pulses in the ascending order, a down-counter counts them in the descending order, and the up/down counter is able to count either ways. To convert the BCD output of a counter into decimal, AND or NAND gates can be used as decoders. A large number of IC counters, which are commonly used in the modern digital applications, have been discussed in Sec. 8.27 through 8.30.

• • • • • • • • •

PROBLEMS 8.1 How many flip-flops are required in a divide-by-25 ripple counter? 8.2 Draw the logic diagram of a 5-bit up/down synchronous counter with serial carry.

DIGITAL PRINCIPLES AND CIRCUITS

8.3 Design a mod-6 eynchronous counter using T flip-flops to count in a binary· sequence. 8.4 Draw the logic circuit for a mod-12 synchronous counter to count in natural1>inary sequence using RS flip-flops.

8.5 In a 6-bit ring counter we use a clock frequency of 5 MHz. How long does it take to produce all the ring-words ? How long is each timing-bit high ? 8.6 Design a mod-6 up/down synchronous counter using JK flip-flops. 8.7 Show the AND gates required to decode a decade counter that uses 2421 code. 8.8 Design a mod-5 synchronous counter using T flip-flops which can count in the gray-code sequence. 8.9 How many flip-flops are required to construct a shift-register counters of moduli 5, 9 and 21 each. 8.10 Determine the decoding AND gates for a mod-8 counter that follows the 8421 code. Also draw the output waveforms. 8.11 Design a divide-by-9 counter using the IC 74177. 8.12 Design a divide-by-7 counter using the IC 74192. OBJECTIVE QUESTIONS

1 An n-stage register results in a delay of (a)

nT

(b) (n-l)T

(c)

(n - 2)T

(d) 2T

2 Parallel operation is preferred to serial operation in a shift register, because (a) It is faster (b) It is easier to design (c) Its circuitry is simpler (d) All the above 3 The ripple counter functions as a (a) 2: 1 counter (b) n: 1 counter n (c) .2n: 1 counter (d) 2 : 1 counter 4 The number of flip-flops required in a decade counter is (a) 2 (b) 3 (c) 4 (d) 10 5 To convert the clock frequency of 50 Hz into 1 Hz, we require a (a) ring counter (b) 4-stage ripple counter (c) divide-by-50 counter (d) divide:.by-l0 counter 6 Least delay is provided by the (a) ring counter (c) synchronous counter

(b)

(d)

ripple counter Johnson counter

7 An 8-bit synchronous counter with serial carry has (a) 2 flip-flops and one gate (b) 4 flip-flops and 2 gates (c) 8 flip-flops and 6 gates (d) 16 flip-flops and 12 gates

'341

DIGITAL COUNTERS

8 In a synchronous counter with serial carry, each AND gate has (a) 2 inputs (b) 3 inputs (c) 4 inputs (d) 6 inputs 9 A mod-l0 counter can divide the clock frequency by a factor of (a) 5 (b) 10 (d) 20 (c) 15 10 If the overall propagation delay in a counter using 4 flip-flops is Tp then the delay for each flip-flop is (a)

n Tp

(b) Tp In

(c)

n - Tp

(d) Tp - n

11 A 3 flip-flop counter would divide the clock frequency by (a) 3 (b) 6 (c) 8 (d) 10 12 Counters can be used for (a) Frequency division (b) Frequency measurement (c) Time measurement (d) All the above 13 A single clock-pulse drives all the flip-flops in a (a) Ripple counter (b) Ring counter (c) Synchronous counter (d) Asynchronous counter 14 To design a binary counter, one should prefer to use a (a) Latch (b) RS flop-flop (c) JK flip-flop (d) D flop-flop 15 In a twisted-ring counter using JK flip-flops, the last output (a) Q is connected to the first input J, and Q is connected to the first input K (b) Q is connected to the first input K, and Q is connected to the first input J 16 The highest count in a 6-bit ripple counter is (a)

62

(b) 63

(c)

64

(d) 65

17 The highest count in an n-bit ripple counter is (a) 2" (b) 2n (c)

2,,-1

(d) 2n-1

18 The number of flip-flops required to build a Inod-6 counter is (a)

3

(b) 4

(c)

5

(d) 6

19 Ring and Johnson counters are synchronous counters. (a) True (b) False 20 An output frequency equal to twice the clock frequency, can be obtained from a (a) Decade counter (b) Up counter (c) Down counter (d) Johnson counter.

342

DIGITAL PRINCIPLES AND CIRCUITS 21 The IC counter belonging to the asynchronous category is (4) 74190 (b) 74198 (c)

(d) 74191

74196

22 The IC counter belonging t.o the synchronous category is (4) 74163 (b) 74190 (d) 74390 (c) 74290 23 The IC counter that can count upto 16 pulses, is (4) 7490 (b) 7492 (c) 7493 (d) 74176 24 Preset inputs are included in the IC counter (a) 74176 (b) 74393 (d) 74190 (c) 74169 25 The IC counter that can count in both the up and down directions, is (4)

74490

(b) 74293

(c)

74197

(d) 74190

26 A single IC counter chip that can be used as a 2-decade BCD counter, is (a) 74390 (b) 74290 (d) 74176 (c) 7490 27 A multistage BCD counter requires more flip flops than a normal binary counter of the same modulus. (4) True (b) False 28 The number of flip-flops required in a 3-decade BCD counter is (4) 9 (b) 12 (c) 16 (d) ID

ANSWERS

1 (b) 9 (b)

2

(a)

10 (b)

3 (d)

4

(c)

5

(c)

11 (c) 12 (d) 13 (d)

17 (a)

18 (c) 19 (a) 20 (d)

25 (d)

26 (a) 27 (a)

28 (b)

6

(c)

14 (b)

21 (c) 22 (a)

7

(c)

15 (b)

8

(a)

16 (c)

23 (c) 24 (a)

CHAPTER

9

MEMORY SYSTEMS 9.1 INTRODUCTION In digital computers, it is always required to store digital data and program coded in the binary form, so that it can be used at any further instant whenever required. A separate section, therefore, called memory (or storage unit) is set up in the computers to provide this facility. There are two separate memories in every computer: internal memory (or main memory) and auxiliary memory (or mass-storage memory). Internal memory stores digital data and the program of instructions that are used for internal operation of the computer where digital information is continuously being moved from one location to another. This memory constantly remains in contact with the CPU. Because the internal processing of data takes place at a fast rate, high-speed flip-flops are commonly used in this memory. A large number of bipolar and MOS flip-flops integrated on a single chip has made it possible to make high-speed semiconductor memories at lower costs. The principle of storing data as charges on capacitors, has allowed formation of semiconductor memories with high-density storage and low-power requirements. Auxiliary memory is different from the internal memory. It stores massive amount of data which are not currently being used by the CPU, but they are transferred to the internal memory, whenever required. The auxiliary memory operates at much slower speed than the internal memory. The magnetic cores, disks, tapes or magnetic bubble memories are the nonvolatile devices which have been mostly used to form the auxiliary memories. However, the semiconductor flash-memory is preferred in modern computers because of its high-speed, small-size and low-power requirements. On the basis of the storage devices used, memories can be divided into two categories: magnetic memories-that use magnetic devices, and the semiconductor memories-that use semiconductor devices (bipolar or MOS transistors). Magnetic memories have large storing capacities, but they suffer from being large in size, having higher costs and operating with lower speeds, and therefore they are seldom used. Semiconductor memories, . on the other hand, have smaller size, lower cost, faster speed and more reliability. In this Chapter, we give a brief account of magnetic memories but discuss the semiconductor memories in detail. However, in the beginning we define certain common terms which are frequently used in relation to a memory. 9.2 MEMORY TERMINOLOGY Various terms which are commonly used in relation to a computer memory are defined in the following:

344

DIGITAL PRINCIPLES AND CIRCUITS

Memory Cell

An electrical device or circuit that stores a single hit, is called memory cell. A flip-flop, charged capacitor, a core, or a single spot on a magnetic tape or disk, are a few examples of memory cells.

Word

A word in the memory is a meaningful group of hits that represents instructions or data. It moves in, or out of the memory as a single unit. Word-sizes typically range from 4 to 64 hits.

Memory Location

The register that stores a word in the memory is called memory location.

Address

A group of bits that identifies a memory location in the memory is called address of that location. Addresses are always expressed in binary format, however, octal, hex and decimal formats are often used for convenience.

MDR

The register in which the data words to he written or read are first entered, is called memory data-register (MDR).

MAR

The register that contains the addresses of memory locations is called memory address-register (MAR).

Write operation

The operation through which a new word is entered (stored) into the memory location, with previous word replaced, is called write operation.

Read operation

The operation through which a word stored in a memory location is sensed and retrieved, is called read operation.

Write signal (W)

This is the control signal that commands the movement of a word into the memory location.

Read signal (R)

This is the control signal that commands the movement of a word out of the memory location.

ReadlWrite signal (RW)

This is the control signal which commands hoth the read and write operations. This is also expressed as WE.

Access time

This is the time from application of address input until the required word enters into MDR. Access time determines the speed of a memory.

Write time

This is the time from the start of write signal until the word is stored at the desired location.

Read time

This is the time from the start ofread signal until the valid data appears at the data output.

Capacity

The total number of hits which can be stored in a memory determines the capacity of a memory.

Volatile memory

This is the memory in which the stored information is lost when power is shut off.

MEMORY SYSTEMS

345

Nonvolatile memory

This is the memory which retains the stored information even after the power is shut off.

Tristate memory

This memory uses tristate buffers in data lines. When the buffers are enabled they allow the data to pass through, and when they are disabled, the data lines remain floating (in the hi-Z state).

Chip select (CS)

This is the control signal that selects (enables) the desired chip out of several chips. This is also termed as chip enable (CE).

9.3 THE BASIC MEMORY Basically, a computer memory consists of storage cells each of which stores a single bit (0 'or 1). The group of cells storing a word is called register, which is also called as location in the memory. The number of words and the number of bits in each word ~etermine the size (storage capacity) of the memory. If M be the number of words or locatIons and N be the number of bits per word, then the size of the memory is given by the number M x N bits. Normally, memories are available in various sizes, such as 64, 256, 512, 1024m 2048 or 4096 words, with a word-size of N = 1, 4 or 8 bits. However, increased capacities can be achieved by combining several memory chips. . Basic memory operations To enter (store) data into the memory is called writing, and to sense, or retrieve the stored data from it, is called reading. For the proper functioning of a memory, the following basic operations are essentially required to be performed, as illustrated in the block diagram of Fig. 9.1. 1. To select the address of a memory location for the read or write operation. 2. To select, either the read operation, or write operation to be performed. 3. To supply the input data to be stored during a write operation. 4. To hold the output data coming from memory during a read operation. 5. To enable (or disable) the memory so that it may (or may not) respond to the address and the read/write control inputs.

Address -=p7."lin-e...ls inputs MEMORY MATRIX Data --,---' inputs ----'-'-1

Data outputs

(MXN)

Control inputs

Fig. 9.1 Block diagram of basic memory

346

DIGITAL PRINCIPLES AND CIRCUITS

Address inputs Addressing a memory means activating the appropriate read, or write lines by applying a specified binary code, called address. Each location is identified by a different address. A memory with M locations requires a P-bit address, such that

=M For example, in a memory of M = 16 locations, we require a 4-bit address (because 2P = 2P

16 .,,'ives P = 4) to select one of the 16 locations. Likewise, a 5-bit address would be required to access a 32-word memory, and a 6-bit address for a 64-word memory, and so on. All the addresses are placed in a separate register, called memory address-register (MAR). Decoder

Every memory has a built-in P-to-M -line decoder (not shown in Fig. 9.1) which is required to reduce the number of address lines. The P-bit address is applied to the P inputlines of the decoder which activates one of the M read/write lines. In this way the number of address input lines is reduced froni M to P by using a decoder. The decoder circuit (Chap. 6) is simply a group of AND (or NAND) gates whose number equals the number oflocations in the memory. Data-input and Data-output lines To write data into the memory, there are N input lines (equal to the number of bits in a word) which are called data-input lines. The data to be written are applied to these lines. Another set of N lines, called data-output lines, is also provided to read (retrieve) the data already stored in the memory. In some memories, only a single set of input/output (lIO) lines is used to function both as data-input lines and data-output lines. Control inputs To give command to the memory, so that it can perform the desired functions, a few control inputs are applied to the memory through the control lines. These inputs include "write" (W) and "read" (R) signals separately to command the write and read operations. However, a single command (R/W) is often used for either operation. That is, when RIW = 1, it allows read operation, and when R / W=O, it allows write operation. A chip select signal (CS or CS) is another control signal which is required to select one of many chips in the memory. It is also designated as WE (write enable).

Bus system Each of the three sets of lines mentioned above, is called a bus. That is, the address lines are called address bus, the data lIO lines as data bus, and the control lines as the control bus. These buses run between the central processing unit (CPU) and the internal memory of the computer for communicating the addresses, data, and the control signals between them. Example 9.1 For a 32K-byte memory determine the following : (aJ Number of data-input and data-output lines

347

MEMORY SYSTEMS (b) Number of address lines

(c) Actual capacity in bits

Solution (a) Because the word-size is a byte (8 bits), the number of each of the data-input and dataoutput lines is 8. (b)

The number (P) of address lines required to access M words, is given by

2P Since the memory stores M

=M = 32 K = 32 x 1024 = 32768 words = 2P

Therefore, the number of address lines is P = 15 (c)

Actual capacity of memory = 32768 x 8 bits

9.4 MEMORY ORGANISATION A common memory cosists of the following main parts : 1. Memory address register (MAR)

2. Decoder 3 Memory data register (MDR) 4. Memory matrix These constituents are interconnected as shown in Fig. 9.2 for a small memory of 4 x 3 bits.

R'.dlln,:\

Address inputs

t

MAR

1

~ wri~I~;s1 + Register 0 AB --- --- -----, --- --- ----~ 01 AB ---------------------. Register 1 10

-At- .S Br- ~£ AS Q)

Data inputs

Register

2

---------------------. Register DECODER Data ~t t

3

N

AB

---------------------~

Memory matrix

k".

+--Rffl Read/write

11

outputs

r : :t IMDR

1+

Fig. 9.2 Block diagram of 4 x 3 memory organisation

In this arrangement, the memory address-register (MAR) provides a 2-bit address (AB) to the 2-to-4-line decoder which selects one of the four read or write lines connected to the memory matrix. The memory matrix is an array of cells which are arranged in four registers (0, 1, 2, 3). Each register storing a 3-bit word is selected with a separate read or write line. The matrix is also connected with data-input and data-output lines through the

DIGITAL PRINCIPLES AND CIRCUITS

348

memory data-register (MDR), as also to a control-signal R / W. The detailed structure of memory matrix is given in Fig. 9.3. Bit 1

Bit 2

Bit 3

+- Data-input lines Write

Iinesr--t-~---t-....,...---t----,

AB=OO Read IinesL...-_+-_ _+---+_.......--+_-+---'

.... Register 0

AB=01

.... Register 1

AB=10

.... Register

2

AB= 11

.... Register

3

+- Data-output lines

Fig. 9.3 A 4 x 3 memory matrix (Me = memory cell)

Memory matrix In the memory matrix of Fig. 9.3, each register is connected to a separate pair of read and write lines that corresponds to one of the addresses AB = 00, 01, 10, 11. Also, in the three columns, one each for Bit 1, Bit 2 and Bit 3, one separate pair of data-input and data-output lines is connected to all the memory cells (Me) in that column. In this way, each cell in a register, gets connected to one pair of read and write lines of that register, and one pair of data-input and data-output lines. Write operation In the write operation, the word to be written into a register goes from MDR to the data inputs when the read / write signal is driven low (RIW = 0). As the decoder receiving the address of the register from MAR activates the corresponding write line, the word is stored in the desired register. Read operation In the read operation, the address of the desired register goes from MAR to the decoder, as the read I write signal is driven high (R I W= 1). This activates the corresponding read line, and the contents ofthat register appear at the data outputs, and get stored in the MDR. NOTE 1 In memory of Fig. 9.2, only linear selection (using a single decoder) has been used. However, in large-size memories, X - Y selection (described later on) is often used, which would require two decoders, one for selecting a row and the other for selecting a column. 2 The memory cell in a semiconductor memory can be a bipolar or MOS device whereas in magnetic memory, it is a magnetic device.

MEMORY SYSTEMS

349

9.5 MAGNETIC MEMORIES Magnetic memories use magnetic cores, or the magentised surface of a drum, disk or tape as the storing element. Although these memories have mostly become obsolete these days, a brief account of each one is given below. Magnetic core A magnetic core, usually toroidal in shape, is a ferrite core that can be made with a finely powdered mixture of magnetite and several bivalent metals with a binding material, which is pressed in the desired shape and fired, so as to fuse into a homogeneous polycrystalline solid. The binary behaviour of a core is shown in Fig. 9.4 by its two-way magnetisation, depending on whether the current through the threading wire flows in one direction, or in the opposite direction. The magnetic flux set up in the core in the first case has one polarity and remains there as remanent flux after the current is switched off, thus keeping the core in one stable state (labelled as 1). The other stable state (labelled 0) is assumed by the core when the current is reversed and then switched off, because then the remanent flux will be of opposite polarity. I

State 0

Fig. 9.4 Binary states of a magnetic core

Since, a core can store only a single bit, a memory requires as many cores as the number of bits to be stored, which may be arranged in a two-dimensional square array, referred to as 2D-core memory. In such arrangement of planar array, only one-bit words can be stored. Thus, to store N-bit words, N such planar arrays would have to be arranged, which will form a three-dimensional system, called 3D-core memory. A 3D-core memory, therefore consists of several two-dimensional square-matrix planes stacked in parallel. Each such plane has M cores (arranged in {M rows and {M columns) equal to the number of words to be stored. These planes called bit planes, are equal to the number of bits in each word. Thus, to store M words of N bits each, we would require M x N cores in the memory. Example 9.2 A 3D-core memory has four bit-planes of 64 x 64 array each, stacked in parallel. What is its bit-capacity, word-capacity, number of address-bits and the number of bits in each word? Solution Total number of bits stored = 64 x 64 x 4 = 16,384 = 214 Number of words = 64 x 64 =4096 =212 Number of address bits P = 12 (because 2P =212) Number of bits per word (Number of bit planes) = 4

DIGITAL PRINCIPLES AND CIRCUITS

350

Magnetic drum The magnetic surface of a drum can easily be used as a storage device. A magnetic drum is a rotating cylinder (Fig. 9.5 a) whose surface is thinly coated with a magnetic material similar to that used in magnetic cores. Several recording heads, such as that shown in Fig. 9.5 (b), are mounted across the rotating drum surface for writing or reading the digital data on it.

Read/write head

....n •n

.n

.n

.n ......... '"

n •

Drum

Magnetic surface

Tracks (a)

(b)

Fig. 9.5 (a) Rotating drum with recording head (b) Recording head system

The small area of the rotating drum passing under each head, is called track. The entire drum surface is divided into many such tracks; each track, specified with a number, is subdivided into sectors, and each sector into cells. Each cell can store one bit and each sector, a word. Thus, for a 30-bit word and track capacity of 600 bit, each track would be divided into 20 sectors. A drum with 100 tracks will have a capacity of storing 100 x 20 = 2000 words or 600 x 100 =60000 bits. As shown in Fig. 8.5 (b), the recording head is a circular core of high-permeability material with a small gap, and a magnetising coil wound around it. To write on the drum, we pass a current pulse through the coil to produce a flux through the head. Since the gap in the core presents a high-reluctance path for the generated flux, most of it passes through the material on the surface passing near the gap. The small area so magnetized remains magnetized even after it has passed from under the head, or the coil current is switched-off thus keeping the data stored. To read from the drum, some flux is coupled into the reading head when the magentized area passes under it. Any changes in the flux induce signals in the head winding, whose polarity determines a 0 or 1.

Example 9.3 Calculate the storage capacity of a magnetic drum of 5 inch radius and divided into 100 tracks with a recording density of 200 bits per inch per track. If the speed of rotation of the drum is 2400 rpm, what is the average access-time for the drum? Solution Capacity of each track = Circumference x density of track = (21t x 5) x 200

= 6280 bits

MEMORY SYSTEMS

351

Therefore, total capacity of drum = 6280 x 100 = 628000 bits Time for one rotation =

~ min = 25 ms

Average access-time =

~ x time of one rotation

= 12.5 ms Magnetic hard disk A magnetic disk storage system uses a set of rotating magnetic disks as the storage device, that has a capacity of storing hundreds of megabytes. The magnetic disk, called Hard disk, is a smooth circular metal plate which is coated on both sides with a magnetic material. Several such disks, stacked one above the other with a proper spacing, are mounted on a central disk drive which has several radial arms, each holding one disk. Magnetic heads are positioned on each arm to write or read digital information on the disk surfaces. Usually, ten surfaces of six disks are used for recording, while the top surface of the highest disk and the lower surface of the lowest disk, are left unused. Each usable surface is divided into tracks, and each track into sectors. A sector stores a group of words. Thus, a system with 10 surfaces, each having 400 tracks, and each track with 50 sectors of 256 bytes, will have a capacity of 10 x 400 x 50 x 256 = 51.2 M-bytes. Typical rotation speeds of the disks are - 1000 rpm.

Magnetic tape Memory systems using a magnetic tape (such as in audio tape-recorders), are still required to store a bulk of information at a very low cost per bit. Information in these memories can be retained for quite a long time without fading, and can be erased and rewritten several times. The magnetic tape is a flexible plastic tape which is thinly coated with a ferromagnetic material. This tape, wound on a spool, is transported across a set of magnetic heads, and is rewound on another spool. The technique of writing/reading with the heads is the same as that in the drum recording. In the modern tapes, the standard 112 inch width of the tape is divided into nine tracks, each associated with one magnetic head (8 for storing a byte and one for parity bit). Thus, a tape with a recording density of 800 bits per inch (bpi) per track, has a storage capacity of 800 x 9 = 7200 bpi. The tape speeds are normally -100 inches per second. It can be noted that, because of longer access times, the magnetic tapes are disallowed to be used in high-speed computers.

Bubble memory A bubble memory is a non-volatile magnetic memory which can store huge data and retain them even after the power supply is turned off. The access to this memory is partly serial and partly randonJ-. Structurally, as shown in Fig. 9.6 these memories have a thin film of magnetic material grown on a non-magnetised substrate. Microscopic magnetised zones (called "bubbles") are created at discrete grid points on the film such that their polarity is opposite to the rest of the magnetic film. A 1 (or 0) at the grid point is represented by the presence (or absence) of a bubble at that point.

DIGITAL PRINCIPLES AND CIRCUITS

352

Bubble,

-...,.,.

1

0

1 -------------- 0

,........ ~

Window

0 i 1i

( L 0 C P of B u b b I E S :".):.-.- Rotation --~~0--~~---+0~-----------------------~1--~~~~0~--

+=1 +=0 Fig. 9.6 Organisation of bubble memory

The bubbles located at the grid points are configured into loops as shown in Fig. 9.6 with each loop having a bit-viewing "window". The bit (bubble, or no bubble) appearing in this window can be read, or modified into a desired bit. To access a specific bit location, the loop has to be rotated (as indicated with arrow) till that location appears in the window. The bits stored in consecutive grid-locations can therefore be accessed only serially. However, in a typical bubble memory that has several loops, anyone loop can be accessed randomly. The bubble memories were in usage till 1970s after which they have been totally discarded with the invent of Hard disks. 9.6 SEMICONDUCTOR MEMORIES Semiconductor memories have been developed to have lower cost, smaller size, faster dataaccess and greater reliability as compared to magnetic memories. A semiconductor memory is composed of a large number of semiconductor storage-cells which are fabricated, either or bipolar, or on MOS technology. Since each storage cell can store only a single bit, the memory must have as many cells as the number of bits to be stored in it. Commercially available chips of these memories have word-capacities of 256, 512, 1024 or more with the word-sizes of 1, 4 or 8 bits. Thus, a 256 x 8 bit memory can store 256 words of 8 bits each, providing a capacity of storing 256 x 8 bits. The number of words stored in a memory is often a multiple of 1024 = 210. Using the letter "K" for each 1024 words, the larger memories are designated as "lK" for 1024 words, "2K" for 2048 words, "4K" for 4096 words, and so on. Still higher capacities are designated with the letters "M" (mega), "G" (giga) and "B" (byte). That is, 1 MB (1 mega byte) = 1M x 8 = 1024 K x 8 = 220 bytes 1 GB (1 giga byte) = 1 G x 8 = 1024 M x 8 = 230 bytes In terms of bits, the capacities can also be expressed as 1K b, 3M b, 4G b, etc. with "b" standing for bits. 9.7 CLASSIFICATION OF SEMICONDUCTOR MEMORIES Semiconductor memories can be classified into different names, groups or categories on the basis of various aspects, such as the principle of operation, type of storage device used,

MEMORY SYSTEMS

353

physical characteristics, and the technology of their fabrication. According to the principle of operation, these memories can be classified into: 1. Read-Only Memory (ROM) 2. Random-Access Memory (RAM) 3. Content-Addressable Memory (CAM) 4. Sequential-Access Memory (SAM) 5. Charge-Coupled-Device (CCD) Memory 6. Programmable Array Logic (PAL) 7. Programmable Logic Array (PLA) On the basis of technology, semiconductor memories are divided into bipolar and MOS memories. Other names, such as volatile or non-volatile, static, or dynamic, are also associated with these memories. A volatile memory is one in which the stored information is lost when the power is shut-off. However, in non-volatile memori~s, the stored information is retained even after the power is shut-off. A static memory is one in which the stored data do not change with time, so long as the power to the device remains ON. These memories are fabricated on a bipolar or MOS technology. In a dynamic memory, on the other hand, the stored data change with time, even if the power remains ON. This is so because the data, which are stored as charges on a capacitor, leak-off with time. Periodic refreshing of data is, therefore, needed in them for keeping the stored data intact with the help of a clock.

9.8 READ-ONLY MEMORY (ROM) Read-only memory (ROM) is a semiconductor memory which is meant only for reading the information already stored in it. The process of writing into the ROM, referred to as programming, is mostly done at the time of its manufacturing. The data, once written into a ROM, cannot be changed. Consequently, these memories are best suited for storing some fixed types of data, such as mathematical tables, charts, or some permanent set of instructions which are never required to be changed. A ROM basically consists of two sections: the ROM matrix and the address decoder. The matrix section is the usual M x N array of storage cells (diodes, transistors or MOSFETs) which are arranged in M rows (word lines) and N columns (bit lines). The address decoder is meant for reading the contents of ROM, when a specified binary address is applied to it for selecting one of the rows in the matrix. Apart from binary addresses, hex and octal addresses are also used in some specific applications. Depending on the programming technique used, ROMs can be divided into the following types. 1. 2. 3. 4.

Mask-programmed ROM (MROM) Programmable ROM (PROM) Erasable programmable ROM (EPROM) Electrically erasable and programmable ROM (EEPROM)

DIGITAL PRINCIPLES AND CIRCUITS

354

9.9 MASK-PROGRAMMED ROM (MPROM) A mask-programmed ROM (MPROM), or simply named as "ROM" is programmed during its fabrication using the technique of photomasking. In this technique, a photographic negative, called mask, is prepared by depositing a thin layer of aluminium on the entire surface of silicon wafer. The pattern of electrical interconnections is obtained by selectively etching away the portions of aluminium layer according to the desired program. The row-to-column contacts are retained or etched away depending on whether a logic 1, or a 0, has to be stored, Once programmed, the data pattern in a ROM can never be changed. Because of the photomasking technique being expensive, these memories are useful only when they are produced in large quantities. Diode-ROM Organisation A diode ROM/MPROM is a matrix of horizontal and vertical lines, in which diodes are connected at each junction where a logic 1 has to be stored. Fig. 9.7 shows a diode-ROM organisation with the array of four rows and three columns. Each of the rows or registers (R o ... R3) stores one word, and the three columns indicate the 3 bits of each word. The presence of a diode at a junction indicates the storage of logic 1 and its absence indicates the storage of a logic O. Thus in the arrangement of Fig. 9.7, the row Ro stores the word 101, R l stores 010, R2 stores 111, and R3 stores the word 100. To read the contents in each row, a 2to-4-1ine decoder with a 2-bit address (AlAO ), selects a row, and the readout appears as D2 Dl Do at the data-outputs, as is explained below.

Row Word

Bits

.

t--J'--!~_--+----+--.,.---+-t:-

Ro (101)

)---,.....-----+-.t:---+---+--- R1

(010)

r-;--T-'4o,---t---+---+-T- R3

(100)

_______________ 2 ~ Matrix

2-to-4- line decoder

Oulpul_

O2

Fig. 9.7 A 4 x 3 diode-ROM organisation

When we apply the binary address A lAo == 00, the top AND gate is enabled, activating the row Ro. The high state of Ro then passes on to the first and third columns through the top two

MEMORY SYSTEMS

355

diodes. This provides the output bits as D2 = 1 and Do= 1. The middle-column output remains low (Dl = 0) because of being grounded. Thus the readout appears as D2 Dl Do= 101. Similarly, the address Al Ao = 01 activates the row Rl to provide the readout as D2D1Do = 010. To activate the row R2 we would need the address A1Ao = 10, and for the row R3 we would use Al Ao = 11. It may be noted that actual decoders are fabricated using NAND gates rather than AND gates.

Example 9.4 What are the input-output relationships which are stored in the diode ROM of Fig. 9.7. Solution The truth table for the outputs D2 Dl Do in the diode ROM of Fig. 9.7 are given in the following Table.

Address inputs Ao Al 0 0 1 0 1 0 1 1

Read Outputs D2 Dl Do 1 0 1 0 1 0 1 1 1 1 0 0

From this table, we can write the input-output relationships as

and

D2 =A1Ao, or D2 = A1Ao, or D2 =A1Ao Dl =A1Ao or Dl =A1Ao, Do =A1Ao, or Do =A1Ao,

which can be written in the form of Boolean equations as D2 = Al Ao + A1Ao + A1Ao Dl = A1Ao + A lAo

Do =A1Ao + A1Ao On simplification, the relationships become as

D2 =A1Ao+Ao Dl = A1Ao + A1Ao Do =Ao which can be implemented using the logic gates.

Example 9.5 Design a diode matrix for an 8 x 4 bit ROM that can provide the logic function of each of the OR, AND, NOR and NAND gates. Solution The 8 x 4 bit ROM stores 8 words of 4 bits each in 8 rows, and it requires a 3-bit address to activate one of the rows (because 2P = 8 gives P = 3). The following Table is the combined truth table for the four gates in question, giving the outputs for each set of inputs. The logic functions for these gates are also written on the side of this table.

356

DIGITAL PRINCIPLES AND CIRCUITS

Address inputs A2 0 0 0 0 1 1 1 1

Al

Read Outputs

Ao

0 0 1 1 0 0 1 1

Y3

Y2

YI

Yo

(OR)

(AND)

(NOR)

(NAND)

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

1 1 1 1 1 1 1 0

0 1 0 1 0 1 0 1

Logic functions Y3 (OR)

=

A2 +Al +Ao A2 A lAo

Y 2 (AND) Y1(NOR)

=

A2 +Al+Ao

Yo (NAND)

=

A2AtAo

To obtain the above functions in the output of a ROM, its matrix is shown in Fig. E 9.5. This matrix is formed in accordance with the 8 rows and 4 columns of the Output section of the truth table, and connecting a diode at each junction where a 1 appears in the Output section. In this way, the ROM outputs Y 3 , Y 2 , Y 1 and Yo provide the functions of OR, AND, NOR and NAND gates, respectively. . . Columns Rows

Address inputs

A:!

.S:

(J)

"(J)

•

U

;;; -g I---.....J ~ ~

1-----,

t")

L-~~--+---+-urll------

Y3

Y2

Y1

Yo "- Outputs

Fig. E 9.5

9.10 LINEAR AND X-Y SELECTION Addressing of memory locations can be done in two ways: one-dimensionally, called linear selection, and two-dimensionally, called X-Y selection. In linear selection, all storage cells that contain one word, are arranged in a horizontal row which is excited by one address-line. There can be several such rows, each storing a word, which are excited with different address lines. Thus, addressing in linear selection as used in Fig. 9.6, is provided by exciting one of the rows at a time. This requires only one decoder with as many gates as the number of rows i.e. one gate for each row.

357

MEMORY SYSTEMS

In X-Y selection, on the other hand, each memory cell is identified by exciting two (X and Y) address lines along the horizontal and vertical dimensions. We therefore require two decoders, one for the X, and the other for the Y address line. This scheme of selecting a cell greatly reduces the number of gates needed in the decoders as compared with the case of linear selection. Fig. 9.8 shows an arrangement for X-Y selection in a 16 x 1 memory containing 16 words of 1 bit each, in which 16 storage cells are arranged in a 4 x 4 square matrix. The horizontal lines or rows are excited by the X decoder and the vertical lines by Y decoder. Each location is identiijed by the (X, Y) number, such as (0,0) or (0,1), etc. This

~ Y-address

lines

a: UJ o

o o UJ o

>
. However, the transistor would store a 0, if its fusible-link is removed, because then the floating (disconnected) column would go into low state (ground). Column-

2

0

3

------------------------------_.-------. -----------. o Row 0 :

Row select

Aa

o

A2

00 01 10 11

CD ... CD

c

'7"8 ..r 0

CD

.9'0

~>D---...

Fig. 9.21 A 32 x 1 ROM obtained from two 16 x 1 ROMs

A4= 1, ROMois selected, which produces its 16 stored words at the data output D. Likewise, when~= 0, ROM 1 is selected, which produces the other 16 words at the data output D. In this way, this 32 x 1 ROM module produces each of the 32 words of one bit each at the data output D.

Example 9.15 Obtain a 128 x 4 RAM using four 32 x 4 RAM chips. Solution Each given 32 x 4 chip requires a 5-bit address and the desired 128 x 4 RAM requires a 7-bit address. The given four chips (RAMo ... RAM a ) can be connected as shown in Fig. E 9.15, such that the 5 address-bits (Ao· ..A 4 ) out of the 7 address-bits are supplied to each chip to select one of 32 locations at a time. The remaining 2 bits (A 5 , As) are used as chip-select signal to select one of the four chips at a time through a 2-to-4 line decoder. A ~

Data I/O lines

Do

RIW

R!W RIW I/O

Ao A1 ~

Aa

R!W I/O

RIW I/O

RIW liD

32x4 RAM1

32x4

32x4

RA~

RAM3

A..

{As

Chip select Ae--~ ~----------~

Fig. E 9.15 128 x 4 RAM using four 32 x 4 RAM chips

MEMORY SYSTEMS

381

separate R IW = 1 signal is connected to all the chips to read or write the 4-bit word Da D2 Dl Do from, or into the selected chip through the data 110 lines. Each chip locates 32 words in a sequential order, i.e., 0 to 31 in RAMo, 32 to 63 in RAMI> 64 to 95 in RAM2 and 96 to 127 in RAM a· E1[ample 9.16 How many RAM chips of 256 x 8 each should be connected to build a 4096 x 8 RAM? What size of decoder has to be used in this arrangement? Solution Each given 256 x 8 RAM requires an 8-bit address (because 256=28 ) and a 4096 x 8 RAM needs a 12-bit address. Since 4096/256 = 16, we need 16 RAM chips of 256 x 8 each, which must be connected in the manner similar to Fig. E 9.15 to make a 4096 x 8 RAM. Out of 12 address-bits, 8 should be used for each chip to access one of the 256 words, and the remaining 4 bits must be used as chip-select signals to select one of the 16 chips using a decoder. Since 16 chips are to be activated using 4 bits, a 4-to-16-line decoder would be used in this arrangement. Example 9.17 Show how the 2 K x 8 PROM chips can be connected to produce a total capacity of 8 K x 8. How many address-bus lines would be needed in this expansion?, Solution To increase the word capacity from 2 K to 8K, we require four PROM chips of 2 K x 8 each. Since 8K = 8 x 1024 = 8192 = 2 13 , thirteen address lines would be needed. The complete diagram for the 8 K x 8 module is shown in Fig. E 9.17 in which a 3-to-8-line decoder (74LSI38) has been used to generate the CS input signals. Out of the 13 address bus lines, the 2 highest-order linesAB 12 andABllare used to select one of the four PROMs, and the other 11 lines go to each PROM to select the desired location :', Address bus (13 lines)

AB'2 AB11

I

I

I

A~,o

I I I I

~Bo

I- e '--

'----

f~ -::-

0-

3-to-8-line decoder

~

I

I

11

.... -

. ..

J

11

.... -

•• n

V

"-.7

V

V

Ao-AlO

Ao-AlO

Ao-AlO

Ao-A,o

PROM,

PROMo

Lc

.. I

11

....... .....

es

-C

es

PROM3

PROM 2

Lc

es

-0

es

2Kx8

2Kx8

2Kx8

2Kx8

~-Do

~-Do

~-Do

~-Do

8

~Br DBo

I

.... -

~

. .. I

11

B A

1 - E3

.

. I

I

',I

74LS138

0

I I I I I

I I I I

11 lines

"-

~j Data bus (8 lines)

8

"-

~8

Fig. E 9.17 Four 2K x 8 PROMs providing total capacity of 8K x 8

..

~

DIGITAL PRINCIPLES AND CIRCUITS

382

within the selected PROM. The four possible combinations of AB 11 and AB 12 are decoded by the decoder to generate active-low signals that are applied to the CS inputs. For example, whenAB 11= 0 =AB12' the decoder's 0 output goes low (with all others high) and enables PROMo. This causes the PROMo outputs to generate the data word internally stored at the address determined by ABo through AB lO • All other PROMs remain disabled, thus preventing any bus contention. PROMo thus responds to the following range of 13-bit addresses: AB12 to ABo

Or

= 0000000000000 0000

=

Similarly, when AB12 = 0, ABu following range of addresses:

= 1, the

tn tn

0011111111111 07FF

decoder selects PROM!> which responds to the

tn 0111111111111 to OFFF or The address range for PROM2 (when AB12 = 1) and ABu = 0) is 0100000000000 0800

or

1000000000000 1000

and for PROM 3 (when AB12 = 1 or

(binary) (hex)

to 1011111111111 tn 17FF

(binary) (hex)

(binary) (hex)

=ABu) the address range is:

1100000000000 1800

to

tn

1111111111111 1FFF

(binary) (hex)

9.27 ULTIMATE DRAMs A large variety of modified DRAMs are available these days according to the specialised applications they are used in.

SDRAM is the synchronous DRAM appeared in 1996, which is designed to synchronize itself with the timing of the CPU. This enables the memory controller to know the exact clock cycle when the requested data will be ready, so the CPU no longer has to wait between memory accesses. SDRAM modules come in several different speeds so as to synchronize to the clock speeds of the system they will be used in. For example, PC 66, PC 100 and PC 133 SDRAMs run at 66 MHz, 100 MHz and 133 MHz speeds respectively. DDR-SDRAM is the double data-rate SDRAM that allows the memory chip to perform transactions on both the rising and falling edges of the clockcycle. Thus a 100 MHz memory bus clock-rate yields an effective data-rate of 200 MHz. RDRAM is the direct Rambus DRAM which is extra ordinarily fast compared to earlier memories. It transfers data at speeds upto 800 MHz over a narrow 16-bit bus. Such a highspeed clock rate is possible due to its "double-clocked" feature which allows operations to occur on both the edges of the clock cycle. Apart from the above, the following special memories have also been designed for video applications.

MEMORY SYSTEMS

383

VRAM

Video RAM

WHAM

Window RAM

SGRAM

Synchornised Graphics RAM

NRAM Most recently, a US based company Nantero has claimed to have developed the so called nanotube memory chips on a new technology. In this technology, rolled-up tubes of carbon are used to make the transistors and on-off switches that carry digital information within a computer. The strings of the nano-tubes move up and down to represent the Is and Os of binary code. These nanotubes stay in place even when a computer is turned off, and so they are nonvolatile. Although the size of the circular wafer (13 cm in dia) holding 10 G-bits of data, is much bigger than the equivalent memory cards, it operates some ten times faster than the presently used 'flash' cards. The new technology is called NRAM which is abbreviated for nano-tube-based-nonvolatile RAM. 9.28 CONTENT-ADDRESSABLE MEMORY (CAM)

The content addressable memory (CAM) is a kind of RAM that performs the operation of association in addition to the usual read and write operations. In the associate operation, we search for certain pre specified locations by using their contents itself, instead of their addresses (as in a usual memory). For example, to read the words that end with 00, irrespective of their locations, the CAM should be addressed by using the content "00" as the basic information. This information, referred to as "key", is associated simultaneously with all the stored words. The output lines then indicate the words that match the key, thus identifying the prespecified locations. Read or write operation is performed on these locations after their identification. Note that a CAM provides a non-destructive readout, and that it uses only the linear-selection of addressing.

Data inputs

N lines Address inputs! Match outputs

Data outputs

N lines

Fig. 9.22 Block diagram of a CAM

Fig. 9.22 shows the block diagram of a M x N bit CAM that can be operated to read, write, or associate M words of N bits each. It has four sets of operating lines. The N data-input lines, one for each bit, are used for the write operation as well as to apply the key word in the associate operation. The other set of N (data-output) lines is used for the read operation. The third set of M (address input/match output) lines is used in two ways: (i) as input lines

DIGITAL PRINCIPLES AND CIRCUITS

384

to apply the address bits during the read/write operation, and (ii) as output lines to indicate matching between the key and the stored data during the associate operation. Each line of this set corresponds to one memory location. The high (1) state of the output line indicates matching. The fourth set of operating lines is that of mode-control lines through which the control signals AI> Ao and Ware applied to select the desired operation of the CAM.

=

=

In the read or write operation, we set AI= Ao o. The write into the CAM, we apply W 0, and to read from it, we apply W = 1. In the associate operation, we set A 1= Ao= 1, and leave W unconnected. To expand word-capacity or word-size, we can connect several CAM chips in a manner similar to that used for RAMs and ROMs. Example 9.18 Obtain a 16 x 4 CAM using two 8 x 2 CAM chips. Solution An 8 x 2 CAM chip has two data-input lines (10, It), two data-output lines (Do, D 1), eight address input/match-output lines and three control inputs (A o, Al and W). The two chips are connected as shown in Fig. E 9.18 to form a 16 x 2 CAM. The data inputs, data outputs and the control inputs of one chip are correspondingly connected to those ofthe other in parallel. 16 address inputs/match outputs

Me· • • • • • Data inputs

'0 '1

MIS

8x2

CAM,

::a

Control inputs ~

t----+lAo 1----+JA1

1----.lW ~-~~~~

~-~-r-~

Dl Do -+- Data outputs

Fig. E 9.18 A 16 x 2 CAM using two 8 x 2 CAMs

SEQUENTIAL MEMORIES A sequential-access memory (SAM) is one in which the memory locations are accessed one after the other in a sequence. The access time is therefore not the same for all locations as it happens in a RAM. Some of these memories are discussed in the following sections.

9.29 SHIFT-REGISTER SEQUENTIAL MEMORY Shift registers fabricated using MOS devices are the examples of sequential memories. Static shift-registers can be fabricated using either the bipolar, or the MOS technology. However, these registers cannot be fabricated in large capacities becau~e of the requirement of increasing power and chip-area, and hence, they are seldom us~.

MEMORY SYSTEMS

385

Dynamic shift-registers, on the other hand, use only the MOS technology, and therefore, they can be fabricated in LSI with high packaging density. These registers consume less power than the static shift-registers, although it increases with the increasing clock-frequency. A dynamic shift-register stores data as charges on MOS capacitors, which can be shifted from capacitor to capacitor in a sequential manner. Any loss of charge during shifting can be compensated for by regular refreshing, thus keeping the stored data intact. 9.30 DYNAMIC SHin-REGISTER MEMORY CELL

Dynamic shift-register storage cells can be formed by cascading MOS INVERTERs (discussed in Chapter 4) Fig. 9.23 (a) shows a single stage of a 2-phase ratioless dynamic shift-register memory cell which is obtained by cascading two ratioless MOS INVERTERs. The first INVERTER is powdered by the clock signal eIl1 and the second bYell2, both clocks being of the same frequency but different phases, as shown by the waveforms in Fig. 9.21 (b). The logic levels are, V DD (1) and 0 V (0) . ~

• 1

1

.1 ~ '1 ~;. .:ts ts '

...- - Single .1 Stage ---.-a

.IWL, 2

f:J

,.

~

(8)

(b)

Fig. 9.23 (a) A 2-phase ratioless dynamic shift-register cell, (b) 2-phase clock-waveforms eIll and eIl2

Operation

Let the input signal be Vi =1. At t =tIt when eIl1 goes to 1, MOSFETs QI and Qa tum ON, and C 1 andC 2 charge to V DD (CI through Q1and C 2 through Qa). During charging of C 2 , Q2 remains OFF (because its gate voltage does not exceed the source voltage by the threshold amount). At t = t 2• when eIl1 goes to O. QI and Qa tum OFF and Q2 turns ON. C2 then discharges to 0 through Qa. which indicates that C2stores a O. If the input Vi were 0, C2 would hold a 1 at the end of ell) (t = t2 ). During the period t2 to t5 for which eIlI= 0, Q1 remains OFF, and C 1 retains Vi until t = t5. At t = ta (later than t2) the clock eIl2 goes to 1 (VDD ), so that Q4 becomes ON, and C 2 and C 3 become in parallel. If V 2 and Va are the voltages on C2 and C3 at the time just before t a• then at the time just after ta. the voltage on Ca will be

, DIGITAL PRINCIPLES AND CIRCUITS

386

C3

C 2V 2 + C 3V 3 V 2 + C; V3 V = = C 2+ C 3 1+ C3

C2

IfC 2»C3 , then V =V2 • This means that the voltage (across C2 ) of the first INVERTER appears as input (across C 3) of the second INVERTER consisting of Q5 and Q6 at the end of clock 2. The output of second INVERTER acorss C 4 is, therefore the complement of that across C 3 (or C 2 ), which in turn is the complement of that across C I . Thus, in one clock period (T) the bit at the input VI has shifted through the stage to the output Vo. Obviously, a memory with n stages, would need a time of n clock-periods to shift the input data to the output. The Intel 2401 is a duaI1024-bit dynamic NMOS shift-register chip that contains 2 x 1024 x 6 = 12288 N-MOSFETs. Disadvantages The 2-phase dynamic MOS shift-register suffers from the following disadvantages. 1. The condition C 2 »C 3 requires more chip area to fabricate a larger C 2 • 2. Increasing of C 2 increaser- the time constant of the charging circuit, which limits the speed of operation of the shift register. 3. The clocks are required to supply heavy capacitive currents. 9.31 CHARGE-COUPLED DEVICE (CCD) MEMORY A charge-coupled-device (CCD) memory is another example of sequential memory which is not only capable of storing digital information, but it can also shift the latter like a shiftregister. If consists of any array of MOS capacitors that can store or shift the data as charges on them. A CCD is basically a MOSFET of very long channel, that has a large number of gates fabricated closely (-1 pM) between source and drain. Each gate-electrode and the substrate form a MOS capacitor that can store charge when a suitable voltage is applied at the gate. By shifting this voltage from one gate to the next, the stored charge, representing a binary bit, can be shifted (or coupled) to the next capacitor toward left or right in a serial (sequential) manner. The CCD is a unipolar device, because only one kind of charge (positive or negative) can be shifted from capacitor to capacitor. A p-channel CCD is one in which the holes (minority carriers) are shifted in the n-type silicon substrate. It is excited by the negative voltages. On the other hand, in the n-channel CCD, the negative charges shift in the p-type substrate. and the exciting voltages are positive. Any loss of charge that may occur during transfer, is compensated for by regular refreshing. A CCD does not require any dc power, but it needs a clock signal for its operation. However, the defect of dark current in this memory sets a lower limit (50 kHz to 1 MHz) of the clock frequency. The upper limit from 1 MHz to 10 MHz of the clock frequency is determined by the maximum allowable power dissipation. The CCD memory is cheaper, but slower than a RAM, because of serial operation of the former. Besides their use in very high-density memories, CCDs are also used as analog signal processors and as image sensors.

387

MEMORY SYSTEMS 9.32 CAHCE MEMORY

A problem of speed-mismatch between the CPU and the main memory is commonly encountered in most computers. This is because the CPU has a high speed, whereas the main memory operates at a slower speed. The limitation on speed of the main memory is imposed by the increasing cost of its large capacity that has to accommodate huge amounts of data and program. Cache memory is a small bulk of a high-speed memory which is used as an intermediate buffer between the CPU and the main memory, so as to alleviate the speed mismatch between the two. As shown in Fig. 9.24, the program and data are transferred from the slower and cheaper main memory to the cache memory whenever they are required in the CPU.

Address

Data

Fig. 9.24 Block diagram using a cache memory

The effective cycle-time of the cache memory is about one-tenth while its cost per byte is about ten times that of the main memory. The size of cache is kept small because its cost goes excessively high with the size. 9.33 PROGRAMMABLE LOGIC DEVICES (PLDs)

The programmable logic devices (PLDs) are the recently developed general-purpose chips of different kinds each of which can be programmed to implement a large variety of logic functions for a given set of inputs. Each device comprises a set of AND gates, called AND array that feeds another set of OR gates, called OR array. The AND array produces product terms of the input variables while the OR array provides their sum. The output function is thus generated as the sum-of-products (SOP) of the inputs. These devices are made programmable at the time of manufacturing by using the fuse-wire technique. At the time of programming, the unwanted fuses are blown off by the user according to the function to be generated. Here we would discuss the followinci kinds of PLDs. 1. PROM as PLD 2. PAL (Programmable array logic) 3. PLA (Programmable logic array) 9.34 PROM as PLD

It was shown in Example 9.5 how a single ROM can be used to implement the functions of several logic gates. The same concept is used here in the formation of a PROM as PLD. To explain it, let us consider a very small 4 x 2 PROM whose PLD architecture is shown in Fig. 9.25 (a). For the two inputs A and B, this PLD requires four AND gates in the AND

DIGITAL PRINCIPLES AND CIRCUITS

388 A

S

+-Inputs Product

terms

~ AS

OR array

OR array

AS ---1P----.----

As - ; _ - - - l i - t - - AS

AS -t-t-t.......--iI-H-r

AND array

/

Programmable fuses

Outputs (a) Programmable array

(b) Programmed array

Fig. 9.25 Architecture of PROM as PLD

array, whereas in the OR array, only two OR gates are shown, although they can be more. The input lines to the AND gates are permanently wired while those to the OR gates are connected through programmable fuse wires. Programming

The PROM-PLD of Fig. 9.23 (a) can bee programmed to implement any 2-variable function simply by selectively blowing the fuses. For example, to implement the function fl = A Jj + AB, we must blow off the middle two fuses of OR gate 1. Similarly to implement another function f2 =AB + AB + AB the first fuse of OR gate 2 must be blown off. NOTE 1 More gates and more inputs in each gate can be added in the PROM PLD of Fig. 9.23 so as to increase the number of inputs and output functions. However, a practical device can use only a limited number. NOTE 2 Each product-term available in a PROM PLD is canonical (that contains each variable or its complement). This restricts the number of functions to be generated.

(a)

9.35 PROGRAMMABLE ARRAY LOGIC (PAL)

Aprogrammable array logic (PAL) is another PLD, which is capable of implementing a large number of logic functions. This device uses the AND and OR arrays similar to those of PROM-PLD. However, it differs in two aspects:

389

MEMORY SYSTEMS

1. The AND array is programmable whereas the OR array is fixed (permanently wired). 2. The product-terms available at the AND-gate outputs can be of both the typescanonical and noncanonical (containing any variable/variables or their complements). These features allow a PAL device to implement more number of complex functions. To explain the working of a PAL, let us consider the functional structure of a simple 3-input-4-output PAL of Fig. 9.26 which uses four AND gates and two OR gates in the respective arrays. A

B

c Programmable fuses

/

r--FA~

P,

OR array

AND array

I,

12

Fig. 9.26 Functional structure of a PAL

Initially at the time of formation, the AND array is made programmable by connecting a fuse wire in each input-line. In the OR f!I1'ay, each OR gate is permanently connected to receive two different product terms, i.e. OR gate 1 receives the product-term PI and P 2 , while the OR gate 2 receives the terms P a apd P4 • At the time of programming, the unwanted fuses are selectively burnt off, as shown with brocken lines in Fig. 9.24 pertaining to the functions fl and f2' Note that the circuitry is so designed that any unconnected AND-gate inputs do not affect the output of AND gate. The AND gate, producing PI is shown connected to the inputs A and B. Hence, P l =AB. Similarly, P 2 =AC, P a =~C andP4 =AC. Thus, the output functionfl generated by the OR gate 1 is obtained as

390

DIGITAL PRINCIPLES AND CIRCUITS

Similarly, the output function f2 generated by OR gate 2 is obtained as fl

= P3+ P4 = ABC+AC

NOTE 1 The PAL of Fig. 9.26 can implement only a few functions because of the small size of its array. Commercially available PALs come in much larger sizes with more number of inputs, product-terms and outputs. The PAL 18L8A has ten inputs and eight output functions. It uses seven AND gates producing equal number of product terms.

AND

NOTE 2 Although Fig. 9.26 clearly illustrates the functional structure of a PAL, the style of drawing is not suitable for larger chips that are available commercially.

Schematic of commercial PAL The drawing of architecture for a commercially available PAL, as adopted in the manufacturer's data, is illustrated in Fig. 9.27. In this drawing, each AND gate is fed with a single horizontal line which symbolizes to contain all the applied inputs. The possible inputs to AND gate come through the vertical lines crossing the horizontal lines. At each crossing of these lines, a programmable connection is marked with "x". Likewise, the inputs to each OR gate are also symbolized with a single vertical line which is permanently connected to three different AND outputs, as shown with "dots". This structure using 9 AND gates and 3 OR gates can generate 3 output functions, flo f2 and f3 which are given as : fl f2 f3 A

B

= AC+AC = AC+BC = BC + ABC

- C . - - Inputs

A

B

C

Permanently wired AC -4-4--11--+-.....-+-1

AC -+~E-I---+--+__-4 o .....--iIIHl-.-*__-i

Be -+~~E-+-~~~ AC -+-W:---+---'l--ill--+-I

o .....--iIIHf--,.-.........-I

Be -r-+-+~~+-~ ABC __-+-+-ill-......t-I

o ....~E-II-...........~~ AND array (programmable)

'2

f, 13 Out puts

(a) Programmable array

(a) Programmable array

Fuses blown off

f, ~ 13 Outputs

(b) Programmed array

(b) Programmed array

Fig. 9.27 Architecture of a commercial PAL

MEMORY SYSTEMS

391

9.36 PROGRAMMABLE LOGIC ARRAY (PLA)

A programmable logic array (PLA) is the unique and versatile logic device in which both the AND and OR arrays are made programmable by using two sets of fuses. It is therefore capable of receiving. a large number of inputs and also producing a large number of outputs, because any or both of the arrays can be programmed for a given function. Thus the capacity of a PLA becomes very large, as it is determined by the number of inputs, number of product-terms and the number of outputs. Fig. 9.28 shows the architecture of a general PLA with M inputs, n product-terms and N outputs, in which all the fuses in both the arrays are kept intact. Using the block diagram of Fig. 9.29, the function of each block is explained below.

~-----------------'Im-l~ ~inputs Po

• • • • •

• • • • •

OR array

• •

•

•

• •

• •

• • • • AND array S~1 SH-2

N outputs

~

Fig. 9.28 Architecture of PLA (Input buffers not shown) ~ ~

·• •

• • •

T M inputs

10 To

~

1,

• • • • • •

• Input buffers

• • • •

•

• • AND • array • •

'1"-1 ,,_1

1"-1

f--+-

Po P,

• • • • • •

~

•

·• • •

OR

array

• Pn- 1

2~

n

inputs

product terms

Fig. 9.29 Block diagram of PLA

• • • • • •

,

~ SN_l

N outputs

392

DIGITAL PRINCIPLES AND CIRCUITS

Input buffer The input buffers are used prior to the AND array so as to limit the loading of the sources which drive the PLA inputs. There is one buffer required for each input, which is converted into inverted and non-inverted forms. Thus the M inputs of PLA become 2M inputs to the AND array.

AND array The AND array of n gates has 2M inputs 10 .. . IM _ b and 10 ... 1M _ 1 and provides n productterms Po ... P n _ 1. Each AND gate generates one product-term which is obtained by blowing the unwanted fuses according to the program. Initially when all the fuses are intact in the array, the lowest order product-term is given by

If we retain the fuses, say for the inputs II> 14 , 15 and la, and blow up all others, then the generated product-term would be

Similarly, the other product-terms (PI, P 2 ••• ) can be generated by blowing the unwanted fuses in the AND array.

OR array The OR array consists of N OR gates that receive n product-terms (PO···P n -1) from the AND array, and produce their logical sums SO···SN _las the N outputs. When all the fuses are intact, the lowest sum-term output is given by So

= P O +P1 +P2 + ...+Pn - 1

The required sum-terms can be obtained by blowing the unwanted fuses in the OR array. For example, if we blow off all the fuses except those corresponding to the product-terms Po, P 2 and P 5 for the sum-output So, then this sum would be given by So = PO +P2 +P5

Other sums can bee similarly generated by blowing the unwanted fuses in the OR array.

Programming the PLA A PLA is programmed to provide a desired input-output relationship. Programming of PLA can be done either at the time of manufacturing, or during its use. In the first case, called mask programming, the manufacturers design suitable masks to build up datapatterns as per specifications of the customer. In the other case called field programming, and the array called as field programmable logic array (FPLA), it is programmed

MEMORY SYSTEMS

393

manually by the user on a PROM programmer, for which the manufacturers supply the programming-format sheets. In the FPLA all the fuses are kept intact during manufacturing. The unwanted fuses are blown electrically, by applying suitable voltages at the inputs and outputs of the device. Once programmed, an FPLA cannot be reprogrammed. An actual FPLA is the FPLA 840, which has a capacity of 14 x 32 x 6. It has 14 inputs, 32 AND gates and 6 OR gates.

Erasable PLA Normally, a PLA can be programmed only once. It cannot be reprogrammed, because once a fuse is blown off, it cannot be reconnected. However, :recently some erasable PLAs have been developed which can be erased and reprogrammed again and again, just like the EEPRMs. In place of fuse-wires, these devices use electronic switches which can be opened and closed electrically.

Capacity expansion The capacity of a PLA can be increased either by increasing the number, of inputs, or the number of product-terms, or the number of outputs. This can be done by suitably connecting several identical PLAs with each other in the following manners. 1. To increase the number of outputs, the inputs of two or more PLAs are connected in parallel. 2. To increase the number of product-terms, the inputs, as well as outputs of two or more PLAs are connected in parallel. 3. To increase the number of inputs, two or more PLAs can be connected along with a decoder. If the number of inputs has to be increased by Q, we require 2Qidentical PLAs and a Q-to-2Q-line decoder. All the inputs of each PLA, as well as all their outputs, are connected in parallel. Each of the 2Q outputs of the decoder is also connected to the chip enable (CE input of each PLA, successively. In this way, M inputs of each PLA plus Q inputs of the decoder, make M + Q inputs of the new PLA device. The number of product terms is also increased to n x 2Q in this method. See Example 9.19.

Example 9.19 How many 3-input PLAs are required, and how are they connected, to increase the number of inputs to 5. Also connect the decoder required. Solution To increase the number of inputs by 2, we require 22 =4 identical PLAs of 3 inputs each. The decoder required in this case would be a 2-to-22-line decoder. The connections are shown in Fig. E 9.19 with the 3 inputs (10, It. 12 ) and N outputs of each PLA connected in parallel. Each of the four outp,uts from the decoder acts as chip enable (CE) to one chip. In this manner, this combination has 5 inputs (10 through 14 ).

394

DIGITAL PRINCIPLES AND CIRCUITS

PLAo CE

l 5 inputs

--

r=: 2-to-4line

decoder

~1

CE

r- ,--

l

~2

3

I--

PLA1

!

t:::

CE

r-

PLAz t-- f-

y ~

......

1 CE p~

r--

r--

Fig. E 9.19

Integrated circuit PLAs Several PLAs in Ie version are available for commercial purposes. The series-20 contains each PLA with 20 pins, and is specified with a particular number, such as 12H6, 10H8. 16e1, etc. The first number in these numbers indicates the number of inputs, and the last number is the number of outputs. The middle letter, anyone of the four (H,L,e,R), indicates the type of output, whether active-high (H), active-low (L), complementary (e), or registered (R). Pinouts of a few PLA devices: 10H8, 14L4, 16e1 and 16R4 are given in Appendix A (Fig. 31).

9.37 FPGA An FPGA (field-programmable gate array) is a different type of programmable device that supports implementation of relatively larger logic circuits. This device is totally different from PLDs because it does not contain any AND or OR arrays in it. Instead, it provides logic blocks for implementation of the required function. A general structure of an FPGA is illustrated in Fig. 9.30, which comprises three main types of resources; logic blocks (shown with hollow boxes), interconnection-wires and switches (shown with shaded boxes), and the I 10 blocks.

The logic blocks are arranged in a two-dimensional array, and the inter-connectionwires and switches are organised as horizontal and vertical routing channels between rows and columns of logic blocks. The routing channels contain wires and programmable switches that allow the logic blocks to be interconnected in many ways. There are two locations for the programmable switches-shaded boxes adjacent to the logic blocks and those existing diagonally between them. The adjacent boxes hold switches that connect the logic-block's input and output terminals to the interconnection-wires. The diagonal boxes

MEMORY SYSTEMS

395 Diagonal boxes

.A--t--

Adjacent boxes Logic blocks

Fig. 9.30 General structure of an FPGA

connect one interconnection-wire to another (such as a vertical line to a horizontal line). Programmable connections also exist between the 110 blocks and the interconnection wires. The actual number of programmable switches and wires in an FPGA depends on the particular chip. Using the above kind of architecture, an FPGA has much more flexibility to implement a large variety of logic functions, as much as that requiring several hundreds of thousand logic gates.

9.38 MASS-STORAGE DEVICES The mass storage technology has come a long way since 1970s when first floppy and hard disks appeared. The present day manufacturers of the mass storage devices are day-byday reaching new horizons to achieve increasing capacities and better performance. The latest versions of these devices, which are available these days are : 1. Floppy disk 2. Floptical 3. Magneto-optical (MO) disk 4. Mini disk (MD) 5. CD-ROM 6. DVD-ROM 7. Hard Disk (HD) 8. Flash Memory cards 9. Plastic memory

Although the simple and inexpensive floppy diskettes are being commonly used as a storage medium for most data and programmes at least in microcomputers, they are

396

DIGITAL PRINCIPLES AND CIRCUITS

treated at the bottom of the capacity and performance scale. Despite all the advances in technology, the capacity could not be improved beyond 1.44 MB. However, 2.88 MB floppies are quite expensive and also less available.

Flopiticals, on the other hand, have several times better performance and a storage capacity about 15 times higher than 1. 44MB floppies as well as full backward read/write compatibility with the latter. 42 MB flopticals are coming the next generation, offering read/write compatibility with 2.88 MB floppies. Such a high amount of data-packing on these specially coated diskettes has been possible because of their using the technique of optical storage. Its operation is based on the reflection, or scattering of an extremely narrow laser beam off a disk that has microscopic pits or bubbles representing logic Is "burned" on to its surface. Magneto-optical (MO) disks combine the density of optical data-storage with the performance and read/write capabilities of magnetic media. The new capacity standard of the MO disk with the 3.5-inch drive format has reached 230 MB from the initial capacity of 128 MB. One can still get over 400 MB from it by using Stacker. Three types of MO disks, i.e. full read / write, partial read / write and read-only are available. The average access times are between 30 and 40 ms with a sustained transfer rates of upto 2MB/s. However, with the 5.25-inch formats, much higher capacities of 650 MB (single density) and 1.3 GB (double density) can be obtained. The 2 GB (triple density) 2.25-inch MO disk is such that it can contain three full CD-ROMs. Sony-made mini disk (MD) can pack upto 140 MB on a single 2.25-inch disk. The speed of these disks is similar to that of CD-ROMs, but about four times slower than MO disks. However, MD disks have the advantage of being relatively cheaper.

Compact disk (CD)-ROM drives are a common component of every multimedia personal computer these days. The double-speed (300 HB/s) drive with an access time of about 350 ms, and the quad-speed (600 KB/s) with an access time between 160 and 220 ms, are currently available, while the 6 x and 8 x drives are expected to come in near future. The 3.5-inch CD-ROM format with 180 MB capacity, however, has not been successful. Information on a CD-ROM is written by creating pits on the disk surface by shining a laser beam. As the disk rotates, the laser beam traces out a continuous spiral. The sharply focussed beam creates a circular pit around 0.8 pm diameter wherever a 1 has to be written, and no pit (also called land) if a 0 is to be written. Reading the pre-recorded data on a CDROM is accomplished by a CD-ROM reader that uses a laser beam. The disk is rotated and the laser head moves in and out to the specified position. It senses pits and lands and we get Is and Os as the readout. A DVD-ROM (digital-versatile-disk ROM) is a better storage device which has been designed on the same principle as in CD-ROM. However, it differs in using a sharper laser beam of smaller wavelength which is focussed on two different layers of the disk, thus doubling the recording capacity (- 8.5 GB). This capacity is further doubled to - 17 GB by sticking two such disks back to back.

Hard disks (HD) have also been continuing as an effective storage medium in the computers. The current capacities of HD in various formats are: 420 MB in 1.8-inch, 810 MB in 2.5-inch, 2 GB in 3.5-inch and 9 GB in 5.5-inch formats. A new Diamond Max D 540

MEMORY SYSTEMS

397

X is the most recent entry which has a capacity of 160 GB. This hard drive runs at a speed of 5400 rpm and consists offour platters of 40 GB each.

Flash-memory cards are available in the market in various formats whose size and capacity depend on the device into which they could be fitted or removed. The choice for a particular format mainly depends on the type of slot available in the device. Smart Media Card and Compact Flash Card are the most popular formats which are used as electronic film in digital cameras. Smart Media Card has a size of 45 mm length x 37 mm width x Imm thickness and a storage capacity between 2MB to 128 MB. Compact Flash Card is a bit thicker than the Smart Card and allows greater storage between 8MB to 192 MB. It has the size of 36 mm length x 43 mm width x 5.5 mm thickness. Other popular formats are named as Flash Stick, Secure Digital Card and Multimedia Card. A total different kind of memory called plasti:c memory has recently appeared with an immense storage feature compared to the conventional silicon chip. It is a hybrid plastic memory which has been made using a plastic film, flexible foil substrate and silicon. The non-crystalline strength of plastic allows storage of huge amount of information. However, writing can be done only once, although efforts for rewriting are in progress.

9.39

SUMMAR~

•

The memory of a computer is the place where the program and data are stored.

•

The ROM is a read-only memory which is meant only for reading the data stoted in it.

•

The MROM is mask-programmed by the manufacturer.

•

A PROM is the programmable ROM that can be programmed only once by the user by means of a PROM programmer unit.

•

An EPROM is the uv-erasable and electrically programmable ROM that can be erased with uv light and reprogrammed by the user any number of times he requires.

•

All ROMs, PROMs, EPROMs and EEPROMs are nonvolatile memories in which the data remain stored even when the power is shut off.

•

A semiconductor RAM is the random-access memory that can be written into or read from by the user. In this memory any location is as accessible a's any other in a fixed amount of time.

•

Static RAMs use bipolar or MOS storage cells in which the data are stored permanently as long as power remains applied.

•

Dynamic RAMs use MOSFETs and store data as charges on capacitors. They require periodic refreshing of data.

•

Both the static and dynamic RAMs are volatile because they lose the stored data when power is even momentarily shut off.

•

The memory cell of a dynamic RAM is simpler and smaller than that of a static RAM. This allows a larger number of cells in a dynamic RAM compar'ed to the static RAM of the same chip-area.

•

A CAM is he content-addressable memory that can also perform the associate operation to access certain specified locations in it, by matching them with the 'key'.

398

DIGITAL PRINCIPLES AND CIRCUITS

•

A dynamic MaS shift-register is a sequential memory which is fabricated by using MaS technology. It can store or shift data in a sequential manner. It is also called as serially accessed memory (SAM).

•

A 2-phase dynamic MaS shift-register cell uses two MaS INVERTERs in cascade, each being powered with a separate clock, shifted in phase from the other. The first INVERTER inverts the input bit and shifts it to the input of second INVERTER when cl>l goes high. The second INVERTER then inverts its input-bit and shifts it to its output capacitor, when cl>2 goes high. Thus, I-bit shifting occurs in one clock period.

•

A CCD-memory uses charge-coupled devices in which the data are stored as charge on a small MaS capacitor that can be shifted from one capacitor to the next in a serial manner.

•

PLDs are the logic devices which are made user-programmable to generate several logic functions.

•

A PROM can be used as a programmable logic device in which AND array is permanently wired, while the OR array is programmable.

•

The PAL is the programmable-array logic device in which the AND array is programmable while the OR array is permanently wired.

•

The PLA or FPLA is the programmable logic array in which both the AND and OR arrays are programmable. PROBLEMS

9. 1 How many bit-planes and how many cores in each plane are required in a coincident memory of 32 x 32 array of 6-bit words? 9· 2 What is the word capacity of a core memory formed in square matrices and using a 12-bit address? 9.3 What is the packing density per inch of each of the 30 tracks on a magnetic drum of 4 inch radius storing 5000 words of30 bits each? 9.4 What is the rate of data movement on a drum of 20 inch diameter and rotating at 30,000 rpm? 9. 5 How many words of 4 bits each can be stored in a 2048-bit memory? 9.6 How many address bits are needed to access a 1024 x 8 bit memory? 9.7 How many NAND gates and how many inputs to each gate, are required in the decoder for a 256 x 4 bit ROM? 9.8 A 4-kb ROM matrix has 128 rows and 4 output bits. How many words does it contain, and how many address bits are needed for each of X-and Y-decoders? 9.9 The matrix of a 4-Kb ROM with 4 output bits, has 64 rows. How many bits are required for the X address and the Y address! 9.10 9.11 9. 12 9. 13

Draw a 256 x 6 bit RAM matrix using basic I-bit storage cells with linear selection. Construct a 512 x 4 bit memory using 512 x 1 RAM chips. Draw a block diagram of ao 1024 x 4 RAM system using 256 x 1 RAMs. Indicate how to convert two 32 x 8 ROM chips into a 128 x 8 ROM.

MEMORY SYSTEMS

399

9. 14 Obtain a 64 x 8 ROM from two 32 x 8 ROM chips 9. 15 What is the highest address in a lK memory? Express the answer in hex and decimal forms. 9. 16 Obtain a 32 x 4 CAM using two 16 x 4 CAM chips. 9. 17 A byte is stored in hex location 6F, 9E. What is the decimal address? OBJECTIVE QUESTIONS 1 The number of cores required in a 3-D coincident current memory to store N words

of B bits each, is (a) NB (b) NIB (c) N2B (d) NB2 2 The number of inhibit wires required in the above memory would be (a)

{B

(c) N2B

(b) B

(d) B2

3 Core memories are (b) Non-volatile (a) Volatile (c) Cheaper and fast (d) Readily available in the market 4 Disk and drums in a computer are the (a) Hardware part (b) Software part (c) Firmware part (d) None of the above 5 A 4 M x 4 memory has the number of locations (a) 4096K (b) 4096Kx4 (c) 4096x4K (d) 4096 6 A 4-Kb memory can store (a) 4xl0000bits (c) 4 x 1024 bits

4xl024xl0bits (d) 4 x 1000 x 10 bits 7 The number of bits required to address 512 memory locations is (a) 8 (b)

10

(b)

(b) 9 (d)

12

8 Binary information can be stored in (a) A latch (b) A register (b) A RAM (d) All the above 9 Access in a drum memory is (a) Totally random (b) Sequential and cyclic (c) Partly random and partly (d) Cyclic sequential cyclic sequential 10 Semiconductor memories are (a) Volatile (b) Non-volatile (c) Volatile and small-size (d) Non- volatile small-size

400

DIGITAL PRINCIPLES AND CIRCUITS

11 A semiconductor ROM is basically (a) A combinational circuit (b) A group of flip-flops (c) A sequential circuit with

flip-flops and gates

(d)

None of the above

12 The number of words which can be accessed by 6-bit address, is ~)

~

~)~

(c) 64

(d) 72

13 The number of NAND gates required in the decoder for a 1024 x 2 hits ROM. is (a) 1024 (b) ~ (c)

4096

(d) None of the above

14 Find the oddman out in the following (a) ROM (b) RAM (c)

PROM

(d) EPROM

15 Access times in the static MOS memories, are of the order of (a) 20 - 400 ns (b) 200 - 400 JlS (c) 20 - 400 ros (d) 20-400s 16 In dynamic memories in the following (a) Power dissipation is relatively lower (b) Refreshing operation of data is required to store data permanently (c) A clock is required (d)

All of the above

17 Dynamic MOS memories make use of parasitic capacitance to store data permanently. (a) True (b) False 18 When memory chips are combined to form a module with a larger word capacity the chip-select inputs of each chip are always connected together. (a) True (b) False 19 The speed of operation of a static MOS RAM is larger than the bipolar version. (a) True (b) False ID A static RAM is more expensive than a dynamic RAM. (a) True (b) False 21 A dynamic RAM has grater power consumption than the static RAM. (a) True (b) False 22 An MROM is user-programmable (a) True

(b)

False

(b)

False'

ZJ All ROMs are non-volatile (a)

True

401

MEMORY SYSTEMS 2i A DRAM holds its data as long as the electrical power is applied (a) True 2)

(b)

False

In most DRAMs it is only necessary to read from one cell in each row in order to refresh all cells in that row. (a) True (b) False

a; Only AND gate array is programmable in (a)

PAL

(b)

(c)

PLA

(d) ROM

23 Both the AND and (a) PAL ~)

OR

PLD

arrays are programmable in (b) PLD

PLA

W) ROM ANSWER

1 (a)

2 (b)

3 (b)

4 (a)

5 (a)

6 (c)

7 (b)

8 (d)

9 (c)

10 (c)

11 (a)

12 (c)

13 (a)

14 (b)

15(a)

16 (d)

17 (b)

18 (b)

19 (b)

20 (a)

21 (b)

22(b)

23 (a)

24 (b)

25 (a)

26 (d)

27 (c)

CHAPTER

10

DIA AND AID CONVERTERS 10.1 INTRODUCTION Most physical quantities, such as temperature, pressure, weight, strain , intensity of light or sound, and many others occuring in nature, are analog. That is, their value can be assigned at any level in a continuous range. In the case of digital computers, an analog quantity cannot be used as input signal until we convert it into a digital format. The task of this format-conversion is performed by the circuits which are named as analog-todigital (AI D) converters. Also, the digital quantity produced at the output of a digital computer requires conversion into the analog format, before we use it to control some external system. This kind of reverse conversion requires circuits which are named as digital-to-analog (D I A) converters.

10.2 DIGITAL-TO-ANALOG (D/A) CONVERTER D I A converter (DAC) converts digital data-input into analog output (voltage or current)

which is proportional to the applied digital input. The digital input is mostly applied either in a pure binary, or a BCD format, while the analog output is obtained in terms of usual voltage or current. To design a DAC-circuit the common procedure is to first divide the digital input in binary progression and then to sum-up all the corresponding analog outputs using a summing amplifier. The most commonly used DAC circuits are of two types: 1. Weighted-resistor D/A converter 2. R-2R Ladder D/A converter

10.3 WEIGHTED-RESISTOR

DIA

CONVERTER (Voltage output)

Fig. 10.1 shows a simple circuit of a 3-bit DIA converter which produces an analog voltage output proportional to the applied digital input. This circuit consists of a group of input resistors (R, 2R, 4R) which are valued (weighted) in binary progression (2°,2 1, 22). Each input resistor divides the respective digital input according to its weight. The associated OP-AMP acts as a summing amplifier which produces the weighted sum of all the inputs. In this circuit, since the digital input Vc is divided by 1, VB is divided by 2, and VA by 4, their summed-up value gives the analog output as Va

=-

(Vc +

~ VB + ~ VA )

... (10.1)

01A AND AID CONVERTERS

403 Ratio RflR

Digital Input (MSB)

R

R,

Vc o--.JVI.N'---,

2R VB o---'\I\~--+------I (lSB)

>-----oVo

4R

VA Digital inputs

-

OP-AMP as

AnaJog

summing

output voltage

amplifier

=1 Analog Output

Vc

VB

VA

Vo(Volts)

0 0 0 0

0 0

0

1

0

1

1

1

0 0

0

1

1

0

1

1

1

0 - 1.25 LSB - 2.50 - 3.'75 -5.00 -6.25 -7.50 - 8.75 Full Scale

1

1

1

Fig. 10.1 A 3-bit weighted-resistor D I A converter (voltage output) and the conversion table

in which the negative sign appears because of inversion by the OP-AMP. Also Eq. (10.1) is valid for the ratio RflR = 1. For any other ratio, we must express this equation as ... (10.2) The Table given in Fig. 10.1 lists all the possible eight digital-inputs and the resulting output voltages using the logic levels as 0 = OV and 1 = 5V. For example, if the digital input is Vc VB VA = 101, that is Vc = VA = 5V ad VB = OV, then Eq. (10.1) gives the output as

Vo =-

(5V+OV+~ X5V)

=-6.25V It can be noted in this Table that each input bit contributes a different amount to the analog output. The LSB contributes 1.25 V which is also termed as "resolution" of the nAC, because the analog output increases by 1.25 V for each increment of the digital input. The second LSB (VB) contributes 2.5V and the MSB (Vel contributes 5.00 V to the output. The full-scale (FS) analog output is thus the maximum output voltage that corresponds to the full-scale digital input ofVCVBVA = 111, and is given by

V FS =-

(5V+~X5V+~X5V)

=-S.75V

... (10.3)

Eq. 10.2 can also be expressed in terms of the input-output relationship of the nAC, i.e. Analog output = K x Digi.taI input

... (10.4)

in which the proportionality factor K =RfIR, is a constant value in volts for a given nACo In fact, this factor K also equals the LSB contribution (or resolution) of the nACo Eq. (10.4) is more convenient to directly calculate the analog output for any digital input (in decimal). .

404

DIGITAL PRINCIPLES AND CIRCUITS

Example 10.1 Determine the LSB contribution and the full-scale output voltage in a 4-bit DAC using the ratio RrI R = 3, and logic levels as OVand 5V. Also find the analog output voltage for the digital input of 1010. Solution In a 4-bit DAC, the analog output is given by

Vo

=- ~ (Vn

+

~ Vc + ~ VB + ~ VA)

To obtain LSB contribution, we must use the digital input as 0001, i.e. VD = Vc = VB = OVand VA = 5V. Thus, LSB contribution

= - 3 ( OV + OV + OV + ~ x 5V) =-1.875V

To obtain the full scale analog output, we must have the digital input as 1111, i.e. V D = Vc = VB = VA = 5V, so that the full-scale output is V FS =-3 (5V +

~X5V + ~X5V + ~X5V)

=-28.125 V Analog output voltage for the given digital input of 1010, is Va = - 3 (5V + OV + ~ x 5V + OV)

=-18.75 V Example 10.2 What is the largest value of output voltage in an 8-bit DAC that produces 2.0 V for a digital input of 001 010002 ?

Solution Digital input: 001010002 = 40 10 Using Eq. (10.4), Therefore

2.0 V

= Kx40

K = 50mV

The largest (full-scale) output will occur for the full-scale input of 111111112 = 255 10 Therefore (using Eq. 10.4), it becomes as

VFS = 50mVx255 = 12.75V 10.4 WEIGHTED-RESISTOR D/A CONVERTER (CURRENT OUTPUT)

Another circuit for a 3-bit D/A converter using binary-weighted resistors, is shown in Fig. 10.2. This circuit produces an analog current output proportional to the applied digital

405

DIA AND AID CONVERTERS

input. This analog current-output is converted into analog voltage by the associated opAMP that acts as the current-to-voltage converter. -VR

0--,-----...,...------, 2R

D1 LSB Weighted-resistor network Switch open '" Input bit 0 Switch closed", Input bit 1 OP-AMPas current-to-voltage converter

. Fig. 10.2 A 3-bit weighted-resister D I A converter (current output)

In this circuit, each of the resistors (R, 2R, 4R) which are weighted in binary progression (as before), is connected to a common reference voltage -VR through a switch (D 2 , D 1, or Do). Each resistor divides the current through it according to the resistor's weight. The switches are operated digitally, which means that binary 1 passes as input to the DAC when a switch is closed, and a binary 0 passes when the switch is open. For example, when D2 and Do are closed, and Dl is open, the digital input of D2DIDo = 101 passes to the DAC. The total output current 10 is the sum of all the individual currents, i.e. 1 1 10 =1 + '2 I + 4 I ... (10.5) When all the switches are closed, the full-scale digital input D2DIDo full-scale (maximum) output cu~rent as I Fs

I

because

1 1)

V R ( 1 + '2 + 4 =-If

= 111 produces the

... (10.6)

=_ VRR

Eq. (10.5) can be generalised in terms of input-bits, as 10

=- ~R (D2

+

~ DI + ~ Do)

The analog output voltage of the DAC would then be VR !!:t Vo =-loxRr= 4 x R (DO+ 2DI +4D2 ) Assuming the proportionality factor RrlR Vo

YR'

= 22

... (10.7)

... (10.8)

= 1, we have

(Do + 2DI + 4D2)

... (10.9)

DIGITAL PRINCIPLES AND CIRCUITS

406

From Eq. (10.9); for the LSB (Do = I), the input of D2DIDO = 001 produces the output of Vo =V R I4, which. is the LSB contribution. For the second LSB, Dl =1 (input D2DIDO =010), the output is Vo =2V114. For the MSB, D2 =1 (input D~IDo =100), the output is Vo =4VR I4 This indicates that the bit-contributions increase in binary progression. Table 10.1 gives binary weights for each bit and the respective bit-contributions to Vo in an n-bit DAC with the factor RrlR = 1. Also this table provides the analog outputs for each digital input in a 3-bit DAC with RrlR = 1. It may however be noted that if the factor RflR has a value other than unity, the bit-contribution as well as the output Vo, will have to be multiplied by the same value. Table 10.1 (R,IR

= 1)

Bit

Weight

Bit contribution

LSB 2nd LSB 3rd LSB

1 l/za2/2"-1

V 1 2,,-1 2VR I2,,-1

4/2"-1

4VR 12n-l

•

•

•

R

•

•

•

MSB

1

VR

Table 10.2 (R,IR = 1) Digital input

Analog output

D2 0

Dl 0

Do 0

0

0

1

VR I4

0

2VR I4

1 0 1 0

3VR I4

0 0

1 1 1 1

1 1 0 0 1 1

1

Vo 0

4VR I4 5VR I4 6VR I4 7VR I4

Eq. (10.8) can be generalized to apply to an n-bit DAC having n resistors with lowest value as R (for MSB) and the highest value as 2ra-l R (for LSB). This gives

VR . ~ Vo = 2"-1 R (Do + 21 D1 + 22 ~ + ...... + 2-1Dra-1)

... (10.10)

Eq. (10.10) can also be written (as before) in the form of input-output relationship, i.e. Aualog output • K x Digital input

where

K -J!JL.~ -~ R

is the proportionality factor in volts, and equals the LSB contribution.

... (10.11) ... (10.12)

DIA AND AID CONVERTERS

407

Example 10.3 Find the bit-contributions to the output voltage and the full-scale output voltage in a 5-bit DAC. Also determine the analog output voltage for a digital input of D4 D3 D2 Dl Do = 10101. Consider the reference voltage VR = 10 volts and the factor Rfl R = 1. Solution Because, the number of input bits is n =5, therefore Contribution of LSB (Do) = VR 12n- 1 = 10/16 volts Tt 1 » =2 VR /2 - = 20/16 volts 2nd LSB (D 1 ) 1 n » =4 VR /2 - =40/16 volts 3rd LSB (D 2 ) » =8 VR /22-1 = 80/16 volts 4th LSB (D3) n 1 » =16 VR /2 - = 160V~16 volts MSB (D4) 10 ID 40 00 160 Full-scale output = 16 + 16 + 16 + 16 + 16

310

=16 volts

Analog output for the given input of 10101, is 10

Vo

40

160

210

= 16 + 0 + 16 + 0 + 16 = 16

volts

This can also be obtained using Eq. (10.11).

Example 10.4 In a 6-bit DAC using binary-weighted resistors, if the MSB resistor is 20 k-ohms, what is the LSB resistor ? Solution R = 120 k-ohms MSB resistor, =2n- 1 R Therefore, the LSB resistor

=26-1 X 20 k-homs =640 k-ohms Example 10.5 What is the largest value of analog output from an 8-bit DAC that produces 1.0 V for a digital input of 0011 0010 ? Solution The given input is Using Eq. (10.11)

001l001~

1.0V

:. K

= 5010 = Kx 50 = 20

mV

The largest output that would occur for the full-scale input of

is given by

111111112 Vo (max)

= 25510 = 20mV x

255

= 5.10V Example 10.6 Find the analog output for the input of 11010 in a 5-bit DAC in which the feedback resistor has twice the value of MSB resistor. Assume the reference-v.oltage level of5 volts.

408

DIGITAL PRINCIPLES AND CIRCUITS

Solution Digital input,

D4 D3 D2 Dl Do RflR

Proportionality factor,

= 11010 =2

VR = 5 V

Reference voltage

Using Eq. (10.10), the required analog output for the digital input of 11010 is 5x2 Vo = 25-1 (0 + 2 x 1 + 22 X 0 + 23 X 1 + 24 x 1) 260

= 16

V

= 16.25 V

Disadvantages of weighted.resistor DAC The weighted-resistor DAC has the following disadvantages. 1. The range of resistor-values, increases with the increasing number of input bits, which becomes quite impractical to manage. 2. The accuracy and stability of the DAC depends on the accuracy (tolerance) of the resistors, which is very difficult and expensive to achieve due to the resistor-values vastly differing from each other. 3. The resistor at MSB is required to handle a much greater current than the LSB resistor. This loading effect on the switches increases with the increasing number of bits. To overcome these problems, the other version, called Ladder DAC, is more commonly used.

10.5 R-2R LADDER D/A CONVERTER The problem of range and accuracy of the weighted resistors can be removed, if we use a ladder-type network of resistors that have only two values -R and 2R. Fig. 10.3 shows a 3-bit DAC using R-2R ladder network, in which the digital input (D 2D 1D o) is obtained by connecting the ladder to a common reference voltage (VR ) through the digital switches. A closed switch (connecting VR) represents a 1 bit, while an open switch (not connecting V R ) represents a 0 bit at the input. The analog voltage Vo obtained at the output of OP-AMP is the R,

B

A

C

R 2R

-=-

2R

2R

Do

R

fLSB) ~

2R

--

D,

-=-

R-2R Ladder network

Fig. 10.3 R-2R ladder D/A converter

DIA AND AID CONVERTERS

409

sum of the binary-weighted voltages that are contributed by the input bits, and therefore it is proportional to the applied digital input. Note that the number of resistors required in this DAC is just double of that used in the weighted-resistor DAC. Circuit analysis The ladder network of Fig. 10.3 would assume the form as shown in Fig. 10.4 (a) for Do = 1 (when switch Do is closed and others are open); in Fig. 10.4 (b) for Dl = 1 (when switch Dl is closeq. and others are open); and in Fig. 10·4 (c) for D2 = 1 (when switch D2 is closed and others are open). Applying the Thevenin's theorem to each section toward the left of the Nodes A, Band C in these figures, we get the reduced forms successively in each case. A

B

R 2R

2R

r- VR

-

A

C

2R

R

I~

-

-

C

R 2R

2R

=:)

-

B

=:)

=:)

~

-

-

-

r

Reduced forms (a) For Do = 1

A

R 2R

2R

2R

B

IVR

-

-

2R

R 2R

C

B

C

R

2R

==>

C

C

2R

=:)

IVR -

IV; -

-

-=-

-::-

~

L

Reduced forms (b) For Dl

A

R 2R

2R

2R

B

=1

C

R 2R

2R

-

-

C

R

==>

-

-

t::::::}

2R

IVR -

C

r- VR

1: ~

Reduced forms (c) For

D2 = 1 Fig. 10.4

Using the last three reduced forms of the ladder network, the simplified circuit of the DAC is shown in Fig. 10.5, from which the analog output voltage is given below by the Equation:

DIGITAL PRINCIPLES AND CIRCUITS

410

vR 2

R,

R

LSB

3

R

VR

22

>--+--OVo

R

V MSB R

2" Fig. 10.5 Simplified circuit of ladder DAC of Fig. 10.3

_ !!:t (VR VR VR) 23 Do + 22 D1 + 21 D2

Vo - - R =-

VR !!:t( 2 23 . R 2 D2 + 2 1Dl + 20 Do)

Generalizing it for an n-bit DAC, we have Vo

Also where

=- ~~

.;r (~-l

Dn- 1 + ~-2 Dn- 2 + '" + 20 Do)

Analog output = K x Digital input K

... (10.13) ... (10·14)

= _ VnR . Rr 2

R

is the LSB contribution or resolution of the DAC. Example 10.7 Find the full-scale output in a 4-bit ladder DAC, assuming V R

=-lOVand

Rr=R.

Solution Given that The full-scale output for the full-scale input of 11112 = 15 10 , using Eq. (10,14) is 10 150 Vo = 16 x 15 = 16 volts Example 10.8 What are the output voltages caused by each bit, and the full-scale output voltage, in a 5-bit ladder. Assume the logic levels as 0 = OV and 1 = - 10 V, and the gain RrIR=1.

Solution The required bit contributions for VR =-10 V are given below. For LSB, Vo = - V R 12n = 10/25 = 0.312 n For 2nd LSB, Vo = - 2VR 12 =20132 = 0.625 For 3rdLSB, Vo=-4VR/2n =40132 =1.25 n For 4th LSB, Vo =- 8VR 12 =80132 =2.50 For MSB, Vo = -16VR 12" = 160/32 = 5.00 Full-scale output VFS = 5 + 2.5 + 1.25 + 0.625 + 0.312 = 9.687 volts.

volts " "

" " "

DIA AND AID CONVERTERS

411

10.6 INVERTED LADDER DAC

If we connect each switch (in Fig. 10.3) directly to the OP-AMP input, and the reference voltage V R to the Node opposite to MSB, the circuit becomes an inverted-ladder DAC, as shown in Fig. 10.6. Using this technique, the total input current I drawn from V R remains constant (equal to VRIR) and independent of the digital input. However, the output current 10 still remains proportional to the digital input as required. The propagation delay transients are also eliminated in this circuit. B

A

2R R,=2R

rl

10

L-----i-----~----~------~-~~=~X2R Fig. 10.6 Inverted-ladder D/A converter

10.7 BIPOLAR DAC

A normal DAC, as discussed so far, is also called as cenipolar DAC, because it produces an output of single polarity (either positive or negative). Such a DAC has logic 0 level at OV and produces zero output for a zero digital input. A bipolar DAC, on the other hand, is one that can produce output of both the positive and negative polarities. Such a DAC can be obtained for a unipolar DAC if its logic 0 level is shifted for ov to some other value, so that it may produce a zero output for a non-zero input. Shifting of zero level is termed as offsetting of the DAC, and cab be achieved by connecting a separate offset circuit to the normal DAC. Offset circuit: This circuit is simply a resistor (R or) connected to a suitable voltage source (Vor) that allows a current through the feedback resistor (Rr) of a normal DAC so as to balance out the latter's output (Vo) and effectively produce a zero output for a non-zero input. Fig. 10.7 shows a bipolar DAC obtained in this way with the offset circuit connected across the normal DAC output VO' R,

_.. _-_ .... _............ ..

··

Normal DAC network

Vo

~

>--'--- V' 0 = Vo - V,

Offset Circuit

Fig. 10.7 Offset circuit in bipolar DAC

412

DIGITAL PRINCIPLES AND CIRCUITS

The voltage across R f produced by the offset circuit is given by ~ . Rf Vf= - R

... (10.15)

of

which is in opposition to the analog output Vo (Eg. 10.10) of the normal DAC (without offset). The net output voltage of the bipolar DAC would therefore, be

=V o -

V o'

... (10.15)

Vf

According to this equation, a zero output (V' 0 = 0) for a non-zero digital input can be achieved by making V f =Vo for which V of and R f can be adjusted accordingly. See Example 10.9.

Example 10.9 In a 4-bit bipolar DAC, assuming Rf'R = 8 and V R = IV;

(a) Determine the offset voltage to produce a zero output for the digital input of 10()0. (b) Calculate the analog outputs for all the sixteen 4-bit digital inputs of 0000 through 1111. Solution (a)

Using Eq. (10.12),

For the digital input of 10002 = 810, the output Vo (without offset) = 1 x 810 = 8V

(Eq.1O.14)

Net analog output (with offset) is given by V o' ;:VO-Vf

V o'

To make

=0,

we must have V{ =Vo =8V Vof

Le.

V

(Eq. 10.15)

RXRf =8 of

. =R, then R!!:LBt = R = 8, as gIven of

If we assume

ROf

which gives

V of =8=1 V

8V

Thus, the digital input of 1000 produces output of 8 V in the normal DAC , and 0 V in the bipolar DAC when 1 V is supplied at the Vo{ terminal of the resistor Rof (= R), the ladder resistor). (b) The analog outputs (Vo') for the sixteen 4-bit inputs of 0000 through 1111 each are given in Table 10.3, which have been calculated below: (1)

=Vo -

For digital input 00002 = 010

Since

V o'

VO=KX01O= 1xO =OV

therefore

Vo'=0-8=8V

therefore

V o' = 1 - 8 = -7 V

V off

(2) For digital input 00012 = 110 Vo = K

X

110 = 1 x 1 = 1 V

DIA AND AID CONVERTERS

413

(3) For digital input 0010 =210 Vo =Kx 210= 1x2 =2V,

therefore

Vo' =2 - B =- 6 V

therefore

V o' = B - B = 0 V

(9) For digital input 1000 =BlO Vo=KxB

=1 xB =BV,

(16) For digital input 1111 = 1510 therefore Vo' = 15 - B = +7 V Vo =K x 15 =1 x 15 =15 V, Table 10.3 Bipolar outputs in Ex. 10.9(b) Digital inputs Da

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Dl 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Analog output Do

(Vo')

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

-8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7

10.8 DAC CHARACTERISTICS The quality of performance of a D/A converter is mainly judged by the following important characteristics which are also specified by the manufacture in the data sheets. 1. Monotonicity

2. Resolution 3. Accuracy 4. Settling time 5. Temperature sensitivity 10.9 MONOTONICITY

Monotonicity of a DAC means linearity of analog output with the digital input. A DAC is monotonic when its output increases linearly (step-by-step) for every successive increament of the digital input. This is shown by the staircase waveform in Fig. 10.B with each step being of the same size. Any missing steps, unequal steps, upward or downward steps, indicate malfunctioning (non-linearity) of the DAC.

414

DIGITAL PRINCIPLES AND CIRCuns Full scale

I

Digital inputs

------

LSB increment or Step-size

o~~~--------------------------. Analog output

Fig. 10.8 Staircase output in a DAC

Because a perfect monotonicity is difficult to achieve in practice, an approximate definition. "Output increases with the increasing input" is often assumed sufficient for the monotonicity. 10.10 RESOLUTION Resolution of a DAC is the smallest possible change in the analog output for any change in the digital input. This change in the output caused by the LSB itself, is expressed as a fraction, or percentage of the full-scale output. In a 4-bit DAC , since there are 16 values of analog output, the smallest change is 1/15 of the full-scale output which means that the DAC can resolve one part in 15. For an n-bit DAC, therefore, we can express the resolution as Resolution % Resolution

output = Full-scale 2n -1

=

... (10.17)

Resolution x 100% Full-scale out put

= _l_x 100% 2n_1

... (10.18)

Thus, smaller the percentage of resolution, better is the resolution. A DAC having more number of input-bits (n) has better resolution than that having smaller number of bits, as is obvious from Table lOA. For this reason, most manufacturers specify the resolution directly by the number of input-bits of the DAC. Thus, a 6-bit DAC has resolution of6 bits. Table 10.4

Input bits 4 6 8 10 12

Resolution 115 1163 11255 111023 114095

F.S. F.S. F.S. F.S. F.S.

% Resolution

6.67 1.59 0.392 0.0978 0.0244

DIA AND AID CONVERTERS

415

10.11 ACCURACY

The actual analog output of a DAC slightly differs from the expected ideal value, mainly because of the inaccurate values of the ladder resistors. Accuracy of a DAC refers to the maximum deviation of the DAC output from its expected ideal value. It is defined by the maximum error expressed as the percentage of the full-scale output, i.e. Accuracy

(maximum) error 100 = Full-scale x -10 Full-scale output 0l

'" (10.19)

For example, if a DAC produces a full-scale output of 9.9 V in place of the expected value of 10 V, then

Therefore

Maximum error

= 10 -

Accuracy

=

0.1

9.9

= 0.1 V

10 x 100 =

± 1%

Quantization error Quantization error is another term that interprets accuracy in terms of LSB increments. + 1 LSB error +1/2 LSB

-1/2 LSB

-1 LSB

error

Fig. 10.9 (a) Error of ± 1 LSB

(b) Maximum error of ± 112 LSB

Referring to Fig. 10.9 (a), when the actual output (solid line) deviates from the ideal output (dashed line) by one step upward (or downward), it indicates an error of +1 LSB (or -1 LSB) which is termed as quantization error. Note that a DAC is considered to be monotonic till the maximum error at each output-level remains less than ± 1/2 LSB. In the worst case, as shown in Fig. 10.8(b), when a +1/2 LSB error is followed by a -1/2 LSB error, an indistinguishable critical level is produced and the monotonicity is lost.

Offset error Offset error in a DAC arises when the latter does not produce a zero output for the zero input. A very small amount of voltage that often appears at the output for a zero digital input, is referred to as offset error. This voltage can be positive or negative, and gets added to each ideal output for all the digital inputs. To correct this error, an offset-adjustment potentiometer. (Fig. 10.7) is externally provided with the DAC, which can be adjusted until a zero output is obtained for the zero digital-input.

416

DIGITAL PRINCIPLES AND CIRCUITS

10.12 SEnLiNG TIME The analog output in a DAC has small variations due to transients that appear due to the presence of switches etc. in the circuit. As a result, the output takes some small time to settle (stabilize) to a final value. Settling time is the time that the DAC output takes to settle at its full-scale value to within ± 1/2 LSB when the input is changed from all Os to all Is. This time is important because it imposes a limit on how fast one can change the digital input. For a DAC with a resolution of 10 mV, the time taken by the output to settle to within ± 5 mV. being ± 1/2 LSB, is the settling time. 'rypical settling times range from lOlls to 50 ns. Increasing number of bits increases the settling time. Example 10.10 A DAC with an accuracy of ± 0.2% has a full-scale output of 5 V. By how much amount can the actual output go off? Solution The amount by which the actual output may deviate from the ideal output of 5 V is the maximum error of the DAC. Using Eq. (10.19),

Maximum error = Accuracy x full-scale output 0.2 = 100 x 5 V = 10 mV Thus, the actual output = 5V ± 10 mV Example 10.11 How many bits are required at the input of a ladder DAC to achieve a resolution of 5m V, if the full-scale output is of 10 V ?

Solution Using Eq. (10.17), we have Resolution =

Full-scale output 2n_1 10V

i.e.

5mV

or

10V ~-1 =5mV=2000

Therefore

~

So that, the Number of bits,

n=l1

= 2001 = 2048 = 211

, Example 10.12 An 8-bit D/A converter has a full-scale output of 2 mA and an accuracy of 0.5%. What is the range of possible outputs for an input of 10000000 ?

Solution Resolution (Step-size) =

Full-scale output 2n -1

2mA = 255 = 7.84 !..LA Since

1000 00002 = 12810 The expected (ideal) output = 7.84 x 128 = 1004 !..LA

DIA AND AID CONVERTERS

417

0.5 F ul I-scale error = 2 rnA x 100 = ± 10 ~ Thus, the actual output can be anywhere within the range 1004 ± 10

~

10.13 COMPATIBILITY OF RESOLUTION AND ACCURACY

Resolution and accuracy in a DAC system should be compatible. For example, in a 4-bit DAC with a resolution of 1 V, it is not advisable to achieve an accuracy of 0.1 %. Because then, the DAC would be accurate to within ± 16 mV while it is capable of distinguishing only to the nearest 1 V. Similarly, it is wasteful to construct a 12-bit DAC with a resolution of 5 mV if it has an accuracy of only 1%. Because then, the output voltage would be accurate only to ± 200 m V, whereas the DAC is capable of distinguishing as fine as 5 m V. Thus, to keep accuracy compatible with resolution, one must observe that : Maximum (full-scale) error == Resolution Example 10.13 What must be the accuracy compatible with the resolution of (a) 1 V in a 4bit DAC, and (b) 5 m V in a 12-bit DAC ? Solution (a)

Full-scale output

Resolution

=

Full-scale output

= Resolution x (2n = 1 Vx15

Compatible accuracy

n

2 -1 -

1)

= 15V Full-scale error - Full-scale output Resolution = Full-scale output

IV

= 15V = 0.066 = 6.6% (b)

Full-scale output

= Resolution x (2n _1)

= 5 m V x (212 Compatible accuracy

1)

= 5 x 4095 mV=20V Full-scale error = Full-scale output 5mV = 20 m V = 0.00025 = 0.025 %

Example 10.14 An 8-bit DAC produces an output of2V for the input of 0110 0100. Determine the following.

DIGITAL PRINCIPLES AND CIRCUITS

418

(a) Output voltage for the input of 1011 0011. (b) Weight of each input bit. (c) Resolution in volts and percentage.

Solution

K

= K x digital input = Kx 0110 01002 = Kx 10010 = 20 mV

1011 0011 2

= 17910, we have the

(a) Since, Analog output

2V which gives For the input of

= K x digital input = 20mVx179 = 3.58V

Analog output

Since the weight of LSB is 20 mY, the weights of successive higher-bits would be in binary progression i.e. 40 m V, 80 m V, 160 m V, 320 m V, 640 m V, 1280 m V and 2560 m V.

(b)

(c) From (a),

Resolution = K =20 mV . 100 IIX' % ResolutIon = 2n_ 1 = 255 % = 0.392 %

10.14 ANALOG OUTPUT OF DAC In fact, the output of a DAC is not exactly an analog quantity, because it varies only in steps of specific values, and not in a continuous manner. The number of different output-values can, however, be increased, (i.e., the difference between successive values decreased) by increasing the number of bits. This allows us to produce outputs that can be considered as an approximation to a pure analog quantity.

10.15 BCD INPUTS In the DACs discussed so far, we used binary format for the digital inputs. However, many DACs use inputs in the BCD format in which a 4-bit code group is used for each decimal digit. The weights of different bits in a 4-bit group are in the usual binary progression (8, 4, 2, 1), but the relative weights of each group are different by a factor of 10. That is, each bit in a 4-bit group has a relative weight that is ten times greater than the corresponding bit of the preceding lower group. For example, in the 2-digit BCD input-code, MSD LSD = (XYho

Ir

the weight of bit Dl is ten times greater than that of Do. Similarly, the weight of C 1 is then times greater than that of Co, and so on. Table 10.5 lists these weights for each bit of two the groups.

0/A AND A/D CONVERTERS

419

Table 10.5 Weights in a 2-digit BCD input XY

Ao

Do 0.8

0.1

Resolution: The resolution (step-size) is the weight of LSB of the LSD, i.e. 0.1 V for the 2-digit BCD. It can also be found using the previous methods as follows: Since the highest allowed 4-bit code in BCD is 1001, therefore Full-scale input = 10011001 Therefore, Full-scale output = (8 + 0 + 0 + 1) + (0.8 + 0 + 0 + 0.1) = 9.9 V (using the weights in volts) 9.9 V = K x digital input Thus, = K x 99 9.9V Resolution K =9"9 = O.lV Resolution can also be found using the number of decimal digits (n') 'on Full-scale output __ 9.9V __ 01 V Resolutl l.e. = lon'-l 102-1. Also,

1

100

% Resolution = lOn _ 1 x 100 = 99 = 1.01 %

Example 10.15 A 12-bit (3-digit) DAC uses BCD input, and produces a full-scale output of 9.99V. Determine the following (a) Resolution in volts (b) Percent resolution (c) Analog output for the BCD input of 0110 1001 1000. Solution (a)

Resolution

=

Full-scale output IOn'_1

= 9.99V = 9.99 V = 10 V 103-1 999 m

(b) (c)

100

% Resolution = lOn' _ 1

Analog output

100 999 = 0.1 %

=K x digital input =10 mVx 0110 10011000 BCD =10mV x 69810 = 6.98 V

Example 10.16 Compare the step-size and percent resolution of a DAC using 8-bit binary input and another DAC using 8-bit BCD input. Assume 990 m V full-scale in each case. Solution (i) For DAC using binary input:

420

DIGITAL PRINCIPLES AND CIRCUlTS Step-size

FS

990mV 255 = 3.88 mV

100 100 % Resolution =2n--1 - =255 - = 0392% . (ii) For the DAC using BCD input:

FS

'Step-size

= lOn' _ 1

% Resolution

= 102 _ 1

100

990 102 -1 mV

= 10 mV

100 99 = 1.01 %

10.16 CURRENT DAC VS VOLTAGE DAC A current-DAC produces current output and a voltage-DAC produces voltage output. A current DAC provides better resolution and grater accuracy than in a voltage DAC. It is also faster than the voltage DAC because the former has much smaller settling times than the latter. The main reason for this difference is the response time of the OP-AMP which is used as the current-to-voltage converter. A current DAC uses a smaller load-resistance compared to that in a voltage DAC, which becomes impracticably large with the increasing number of bits.

10.17 IC D/A CONVERTERS MosrDACs are commercially available in IC packages. The least expensive chips have resolutions of 8 to 12 bits, while the most expensive ones have resolutions of 16 to 18 bits. These are mostly monotonic with less than +1/2 LSB error. The 0808 is a widely used 8-bit high-speed ladder DAC available in 16-bit DIP package. As shown in the pin-configuration of Fig. 32 in Appendix A, it has eight digital-input pins, Dl (LSB) through DB (MSB), two pins for complementary outputs, and two pins each for power supply, Vee (+ 15 V) and VEE (- 15 V). It requires a full-scale current of 2 mA, and has a settling time of about 85 ns to settle within ± 1/2 LSB of 8-bit accuracy. It settles to a 6bit accuracy in about 65-70 ns. The output capacitance of this DAC is 15 pF. The 1408 is another 8-bit DAC that is compatible with TTL and CMOS logic. It has a settling time around 300 ns. The pin diagram, as shown in Fig. 32 (Appendix A) is similar to that of DAC 0808, except that it has the input data-lines in a reverse order from Dl (MSB) through DB (LSB). The AD558 is an 8-bit DAC that can be easily interfaced with the 8085/8080A microprocessor. It includes a built-in latch and an output OP-AMP. It can be operated with one power supply voltage between + 4.5 V to + 16.5 V. The AD7522 is a 10-bit CMOS D/A converter with an input buffer and a holding register. It can be easily interfaced with a microprocessor. The DAC80 is a 12-bit D/A converter in 24-pin DIP using a precision ladder network. It can be operated either in bipolar or the unipolar mode With options of both the current and voltage outputs. It has resolution of 12 bits, accuracy of ± 0.12% and settling time of ± 0.01% of the full-scale. Its block diagram is shown in Fig. 10.10.

01 A AND AID CONVERTERS

• 1

421

-en

2

I

3

24

~I -

I

REF Control

23

-

22

21

-b 6 7

8

20

12-Bit Ladder Network & Current Switches

5K

10

-

12

I

19

v ryv

-

11

5K .A

9

,

GainAdj

r--

4 5

6.3 VR Out

18 6.3K .AA,yv

rV -

17 16

Common Summing junction 20V Range 10V Range Bipolar Offset Ref input

15 14

t-13

f - - Logic supply

Fig. 10.10 Block diagram of DAC 80 D/A converter

10.18 ANALOG-TO-DIGITAL (A/D) CONVERTER The analog-to-digital converter (ADC) converts analog inputs into digital outputs. This converter is an indispensable part of any digital communication-system in which the analog signals are digitized at the sending end. The process of analog-to-digital conversion is just reverse of the process of digital-to-analog conversion, which has been discussed in the foregoing Sections.

Classification AID Converter (ADC) circuits can be classified into two groups depending on the technique of conversion used in them. The first group uses the technique in which the given analog signal is compared with an internally-generated equivalent signal. This group includes the following circuits : 1. Counter-controlled AID Converter 2. Successive-approximation AID Converter 3. Flash AID Converter The second group of ADCs uses an indirect technique that involves changing the analog signal into a proportional time or frequency, and measuring the latter in terms of a number of pulses counted by a counter. Because of an integrator circuit being used in these ADCs, they are also referred to as integrating ADCs. These converters have higher accuracy of conversion, but they are slower in speed than the first-group ADCs. The second group includes the following circuits :

422

DIGITAL PRINCIPLES AND CIRCUITS 1. Dual-slope AID converter 2. Voltage-to-frequency AID converter 3. Voltage-to-time AID converter

10.19

COUNTER-CONTROLLED AID CONVERTER

A Converter-controlled AID converter essentially uses a binary counter, an analog comparator and a D/A converter whose output is compared with the given analog input. The input to the D/A converter is generated by the binary counter that continues to count as long as the comparator output remains positive. The circuit for this ADC is shown in Fig. 10.11. Analog input

Va

Comparator

---+I ,--___of---

Clock

Va DAC output

D/A Converter

Binary Couner

:

Clear

Fig. 10.11 Counter-controlled AID Converter

Operation First of all, the binary counter is reset to zero count by exciting the clear signal. Now, as the clock is turned ON, the counter starts counting the clock pulses whose number goes on increasing with time. The output of the counter applied as input to the AID converter also increases correspondingly. The output (Vo ) of the D/A converter, which has the waveform like a staircase, as shown in Fig. 10.12, is presented to the comparator OP-AMP for comparison with Va'

1'\ Counter stops counting Conversion Completed

i

Number of clock-pulses

Fig. 10.12 Staircase output (Vo) of D/A converter

DIA AND AID CONVERTERS

423

As long as the analog input Va is greater than V o, the output of the comparator remains high which enables the AND gate to freely transmit the clock-pulses to the counter. As and when the input Va becomes less than V o, the comparator output goes low and the AND gate is disabled. At this point the counter stops counting and the conversion becomes complete. The counter output Dn ... Do then represents the required digital equivalent for the analog input Va' Conversion time (tc ) The Conversion time of DAC is the time-interval between the start and end of counting. Note that the value of this time depends on Va' That is, larger the value of Va, greater would be the conversion time. Also, for a given value of Va, the conversion time in creases with the increasing number of bits (n). For an n-bit DAC, the maximum conversion time is : tc (max) = 2n - 1 Clock pulses Also, the average conversion, times : tc (avg) = (1/2) tc (max) Clock pulses Quantization error As explained earlier, quantization error in a DAC has a fixed value of ± 1 LSB which is thought of as being the built-in error of the DAC. This error is in addition to the specified error that appears in the output due to the inaccuracies of the circuit components. For the staircase output, the output Vo can go off by as much as the size of one step. Example 10.17 The ADC of Fig. 10.11 uses 8 bits and the DAC in it produces 5.1 V fullscale. Find the resolutions of ADC and the digital output for the analog input of 3.5 V. Also calculate the conversion times when a clock-frequency of I MHz is used. Solution Resolution of an ADC is the same as that of the DAC, i.e. Full-scale ouput Resolution = n 2 -1

=

5.1 V 255

= 20

mV

Thus, the DAC output (Vo) will advance in steps' of 20 m V for each count or pulse. For the input of Va = 3.5 V, 3.5 V The number of steps or pulses = 20mV

= 175 Thus the required digital output is Conversion time, Maximum conversion- time, Average conversion time,

17510 tc

= 101011112 = 175

clock-cycles = 175 x 1 J.1S = 175 J.1S tc (max) = (28 - 1) x 1 JlS =255 J.1S tc (avg) = (112) x 255 J.1S =127.5 J.1S

424

DIGITAL PRINCIPLES AND CIRCUITS

Example 10.18. An ADC has a 12-bit resolution and a full-scale output of +5 V with a fullsf-ole error of 0.03%. Find the quantization error and the total possible error in volts. Solution Quantization error = Resolution Full- Scale output

=

Full-scale error

2n -1

5V

=

4095

= 1.22

=

0.03 V 100 x 5

mV

= 1.5 mV

Total possible error

= 1.22 = 2.72

mV + 1.5 mV mV

10.20 SUCCESSIVE-APPROXIMATION AID CONVERTER Successive approximation (SA) is the method that is used to achieve higher speed and better accuracy in the conversion of analog signals into digital format. Like the counter method, this method also uses a DAC, and a comparator, but in the place of a counter, it uses a storage register which is named as successive-approximation register (SAR). The method of successive approximation is similar to weighing an unknown mass on a balance by successively increasing the number of weights. The weighing procedure begins with the heaviest weight, to which the subsequent weights (in decreasing order) are added until the balance is obtained. Fig. 10.13 shows a 4-bit SA-ADC, whose operation is explained below. Analog input

Comparator

r;==--p..........- Start Conversion 4--M-- Clock (CP) L..:::::.:;::::.:..Pttr- End Conversion

Va - - - - - ,..

DAC output

Vo

4-Bit DAC

D3 D2 Dl Do (Digital output)

Fig. 10.13 A 4-bit successive-approximation AID converter

Operation' In the SA-ADC of Fig. 10.13, a 1 for each bit (starting from (MSB) of the DAC input is successively entered into the SAR and tested by comparing the D/A output Vo with the

D/A AND A/D CONVERTERS

425

analog input Va' If Vo > Va, this bit is reset to 0, and if Vo < Va, it .is retained as 1, as explained below. When the Start-conversion signal is driven low, a 1 representing the MSB (V3) is entered into SAR by the control circuit during the first clock-pulse (CP). This gives the SAR output as

D3D2DIDo = 1000 If Va > Va, the comparator output goes negative which causes the control circuit to reset the MSB to D3 = O. Buit, if Vo < Va, the positive output of comparator causes the control circuit to retain the MSB at D3 = l. ~ During the second CP, the next bit (V2) is set and tested in the above manner. That is, if Vo > Va, the bit is D2 = 0, but if Va < Va> it is D2 = 1, so that the SAR output becomes as D3D2DIDo = 1100 In this way, during the third and fourth CPs, the remaining bits Dl and Do are also set and tested successively. At the end of fourth CP, the conversion ends, and a low endconversion signal applied to the control circuit transfers the digital equivalent D3D2DIDo into the output register. Conversion time ( tc ) Since the process of conversion for each bit takes one clock-cycle, the total conversion time for an n-bit SA-AID converter would be n clock-cycles. That is, tc = n Clock-cycles Note that this conversion time does not depend on the value of analog input Va, as it happens in the case of counter-ADC.

Example 10.19 Compare the maximum conversion times of a lO-bit counter ADC and a 10bit SA-ADC when both use a clock frequency of 500 kHz. Solution For the counter ADC, tc(max) = 2n - 1 Clock cycles = 1023x2 f..1S = 2046 f..1S For the SA - ADC, tc(max) = tc = n Clock-cycles = 10x2 f..1S = 20 f..1S Thus, the SA-ADC is about 100 times faster than the counter-ADC. ICPackages The ADC 80 is a 12-bit SA-AID converter available in a 32-pin DIP, which can provide both the unipolar and bipolar outputs. It has a linearity error of ± 0.012% and maximum conversion time of 25 J.Ls. ADC 0801 is an 8-bit ADC package that uses successive-approximation technique to convert a 0-to-5V analog input into the 8-bit digital output. It has an on-chip clock generator and needs a supply of only + 5V. The optimum conversion-time is of 100 J.LS. The 20-pin diagram of this ADC is shown in Appendix A (Fig. 33).

426

DIGITAL PRINCIPLES AND CIRCUITS

10.21 FLASH AID CONVERTER . A flash AID converter is the f~stest converter that generates digital output within short period .like a flash. However, this ADC requires much more circuitry than any other converter. For example, a 6-bit trash ADC requires 63 analog comparators whereas an 8-bit flash ADC requires 255. Thus, 2n - 1 comparators are required for an n-bit flash ADC. Fig. 10.14 shows a 3-bit flash AID converter that uses 7 analog comparators. It provides a 3-t,;t resolution with a step-size of IV. The reference voltage (VR = 10V) is successively divided by the voltage-divider into seven reference-levels: IV (LSB), 2V, 3V, ... 7V (fullscale) , with.one level applied to each comparator's (+) input. The analog input Va is applied to the (-) input of each comparator. All the comparator-outputs (C b ... C7 ) are fed to an active-low priority encoder that generates a digital output (CRA) corresponding to the highest-numbered-comparator output that goes low. Operation: When Va < 1 V, all the comparator outputs (C b ..• C7 ) go high. But when Va > IV, one or more of these outputs go low. For example, if Va is between 3 and 4 V, the outputs C l , C 2 and C 3 go low and all others go high. The priority encoder then responds only to the low at C 3 and produces a digital output ofCRA = OIl. If Va > 7 V, all the seven outputs go low and the encoder produces CRA = 111. The associated Table in Fig. 10.14 furnishes all these data. . VR (+10'\1)

Va (Analog input) 3K

Truth Table

1K

1K

Voltage 1K Divider 1K

Priority

C

B A Digital Output

1K

Analog input Va 0-1V 1-2V 2-3V 3-4V 4-5V 5-6V 6-7V >7V

Comparator outputs

C1 C2 C3 C4 C5 C6 C7 1 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 1 1 1 .1 0 1 0 0 0 0 0 0

1K

1K

Fig. 10.14 A 3-bit flash AID converter and truth table

1 1 1 1 1 1 0 0

1 1 1 1 1 1 1 0

Digital output C B 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1

A 0 1 0 1 0 1 0 1

D/A AND A/D CONVERTERS

427

Conversion time Note that the flash ADC does not use any clock-signals and the conversion takes place almost instantaneously. The conversion time in this converter is extremely small - a few nanoseconds because it depends only on the propagation delays of the comparators and the encoder logic. 10.22 DUAL-SLOPE AID CONVERTER

The dual-slope AID converter is relatively slow, but less expensive and more accurate. Its basic circuit, as shown in Fig. 10.15 (a) mainly includes an integrator, a comparator, a counter and a reference voltage (VR)' The operation of this ADC involves the linear charging and discharging or the capacitor (C) using constant currents. Fig. 10.15 (b) shows the integrated voltage (Vo) during charging as well as discharging.

Charging: Initially, at time t =0, the switch S connects the analog input Va to the integrator for a fixed period Te during which Va is integrated by the integrator and C charges linearly with a constant current Ie. The integrated-output Vo appears as a linear ramp, as shown in Fig. 10.15(b). At the end of charging, at t =Te, the counter i.s reset to zero. Discharging: As the charging ends (at t = T e ), the switch S is turned to connect VR to the integrator The capacitor C then discharges linearly with a constant current I d , and the counter again starts counting from zero. The discharge ramp of opposite slope is also shown in Fig. 10.15 (b) during the discharge period T d , after which Vo drops to zero and counting is stopped. The reading of counter at this time is proportional to the analog input Va, as explained below : C

Vo

Integrator

Va

Comparator

VR--c:t

,,

0

Analog switch

-

-

Clear Clock

D':',' 'Do

(a)

(b)

Fig. 10.15 (a) Dual-slope ND converter, (b) Integrator output (Yo)

Since the total capacitor-charge during charging must be equal to that during discharging, we must have

..

428

DIGITAL PRINCIPLES AND CIRCUITS

Now, since Ie is proportional to Va and Id is proportional to V R, therefore ~

Disch arge period

T d == V R . Tc

If T is the clock-period, then the reading of counter, i.e.

_ Va. Tc N -- Td T - VR T

Number of clock pulses

Since V R , Tc and T each has a constant value, the counter reading (digital output of ADC), D n - 1 ..•Do is proportional to the analog input Va, as required. Note that for large values of Va, the conversion process takes a longer time because the period of discharging increases although the charging period remains unchanged. 10.23 VOLTAGE-TO-FREQUENCY AID CONVERTER A voltage-to-frequency A I D converter is simpler because it does not use any DAC. In this converter, the ~ven analog voltage is first converted into a proportionate frequency of pulses, and then the pulses are counted for a fixed period of time. The final count gives the digital equivalent ofthe given analog voltage. Fig. 10.16 shows the circuit of a voltage-tofrequency D/A converter, in which the integrator and comparator convert the analog input (Va) into pulses of frequency that varies in accordance with Va. The number of purses counted by the counter in a fixed period gives the required result. Initially, the capacitor C charges with Va for a fixed period T, and the integrator output Vo decreases linearly with time (t), as given by

Va Vo ==-RC t

c Integrator

R

Va

•

Analog input

EN

D~l Do Digital output (N)

Fig. 10.16 Voltage-to-frequency AID converter

As Vo reaches the value of -VR at time t == T, the comparator-output Ve goes high. This causes C to discharge until Vo diminishes to zero. Putting Vo == - V R , and t == T in the above equation, we have·

D/A AND A/D CONVERTERS

429

This gives the frequency cf pulses of Vo or V c as 1 1 Va f= T = RC ·VR These pulses are applied to the clock-input of the binary counter through an AND gate that allows the counter to count the pulses when the enable input (EN) is raised high. The number of pulses counted within a fixed time-interval Tl is given by N=fTl

Va

Tl

= RC· V R

which gives the digital output proportional to Va.

10.24 VOLTAGE-TO-TIME AID CONVERTER In the voltage-to-time AID converter, instead of varying the frequency, we vary the timeinterval in accordance with the analog voltage and count the number of cycles in every time-interval. This count gives the digital-output equivalent to the analog input voltage.

c Integrator R

~----------------~ Analog input

Fig. 10.17 Voltage-to-time ND converter

Using this principle, Fig. 10.17 shows a voltage-to-time AID converter, in which the analog voltage Va is applied to the (+) input of the comparator instead of{-) input of the integrator. Also, the reference voltage -VR is connected to the (-) input of integrator in place of (+) input of comparator. In this way, the comparator compares the integrated voltage Vo with the analog voltage Va, producing a high output Vc = 1 so long as V o< Va. During this period, say T, the enable signal EN allows the AND gate to pass on the clock pulses to be counted by the binary counter. When Voexceeds Va, after time T, Vc goes low (O), and the AND gate is disabled to pass any clock pulses. The reading of the counter at time T gives the digital equivalent Dn - 1 .•. Do of the analog input.

10.25 SAMPLE-AND-HOLD CIRCUIT To obtain accurate results at the output of an ADC, it is essentially required that the analog voltage presented at the input remains at a stable level throughout the process of conversion. The circuit used for obtaining a stable analog-input to the ADC, is referred to as sample-and-hold circuit in stable analog input to the ADC is referred to as sample-and -hold circuit, in which the given analog voltage is first sampled and then held at the sampled level.

DIGITAL PRINCIPLES AND CIRCUITS

430

Stable Output (to ADC input)

Analog 0 - - - 1 input

Fig.

10.18 Sample-and-hold

circuit

One such circuit, shown in Fig. 10.18, contains two unity-gain buffer amplifiers (AI and A 2 ) with a very high input-impedance, a capacitor (C H ) called hold-capacitor, and a digital switch that operates in two modes. That is, when this switch is closed (1), the low output impedance of Al allows the capacitor to charge rapidly to the analog input voltage with a very low time-constant. This operation is called as "sample mode". When the switch is open (0), the capacitor holds (maintains) its voltage-level because of the high inputimpedance of A2 that prevents the capacitor to discharge. Thus, during this "hold mode" of operation, a constant level of analog voltage is passed on to the input of ADC for the entire period of conversion. Acquisition time: The tine for which the digital switch has to remain closed and the hold capacitor charges, is termed as acquisition time. This mainly depends on the capacity of hold capacitor. Aperture time: The time for which the digital switch remains completely open after the 'hold' signal is excited, is termed as aperture time. Both the acquisition and aperture times are the parameters of a sample-and-hold circuit which must be kept as low as zero (ideally). The maximum sampling frequency of the circuit is determined by these times as well as the conversion time. The LF 198 is an integrated sample-and-hold circuit that has a typical acquisition time of 4 microsecond for CH = 1000 pF, and 20 microsecond for CH = 0.01 microfarad.

10. 26 SUMMARY •

DAC converts digital data into equivalent analog voltage or current.

•

Weighted-resistors DAC uses binary-weighted resistors with a large range of values. The number of resistors increases with increasing number of input-bits.

•

Ladder-resistor DAC uses only two values of resistors.

•

Monotonicity, resolution and accuracy are the important characteristics of a DAC .

•

A DAC is monotonic if its output increases in uniform equal steps for every increment ofthe input.

•

Resolution is the smallest change in the output and is expressed as the fraction of the full-scale output.

DIA AND AID CONVERTERS

431

•

Accuracy tells how far the actual output differs from the ideal value:

•

ADC converts analog signals into equivalent digital data.

•

The analog comparator is the key element in an ADC.

•

Counter-controlled ADC has a counter and a DAC, whose output is compared by a comparator with the applied analog input.

•

Simultaneous conversion by a flash ADC is the most rapid method of conversion because it requires a time of only one clock-pulse to provide the output. However, it needs a large number of comparators.

•

Dual-slope ADC is slower but less expensive.

•

In a voltage-to-frequency ADC, frequency is varied according to the analog voltage and the number of pulses are counted in a fixed time interval.

•

In a voltage-to-time ADC, the time-interval is varied in accordance with the analog voltage, and the number of pulses are counted in every time-interval.

•

A sample-and-hold circuit is used to stabilize the analog input to an ADC during the process of conversion. PROBLEMS

10. 1 An 8-bit DAC has an output of 3.6 rnA for an input of 01100010 2 • What are the resolution and full-scale output? 10. 2 What is the percent resolution of a lO-bit DAC? 10.3 Consider a 12-bit DAC with BCD inputs and a resolution of 10 mV. What will be the output for the BCD input of 0110 01011O00? 10. 4 Compare the step-size and percent resolution of a DAC using 8-bit binary inputs to a DAC using an 8-bit BCD input. Assume 990 mV full-scale output for each DAC. 10.5 A 12-bit DAC using BCD input, has a full-scale output of 9.99 V. Determine the stepsize, percent resolution and analog output for the BCD input code of 0110 1001 0101. 10. 6 A 6-bit DAC produces can output of 2V for the input of 011001. What will be the output for an input of 101100? 10.7 What is the resolution in volts of a 10-bit DAC whose full-scale output is 5V. 10. 8 How many bits are required for a DAC so that its full-scale output is 10mV, and resolution is less than 400 J.1V? 10.9 Determine the required value of Rrl R in Fig. 10.1 for the LSB contribution of 0.5 V. What is the change in percent resolution with this new value of Rrl R. 10. 10 Calculate the analog voltage corresponding to the LSB and MSB for a 12-bit ADC calibrated for a 0 to 5 V range. 10. 11 If an ADC has a resolution of 100 mV percount, what analog voltage is represented by a logic 1 at the third LSB of the output? 10.12 A counter-controlled ADC, using a 5-bit counter, has the reference voltage of 16V. What is the resolution of the ADC? What analog voltage does the MSB represent?

DIGITAL PRINCIPLES AND CIRCUITS

432

OBJECTIVE QUESTIONS

1 A lO-bit DAC has a better resolution than a 12-bit DAC for the same full-scale output. (a)

True

(b)

False

2 A lO-bit DAC with a full-scale output of 10 V has a smaller % resolution than a 10-bit DAC with 12 V full-scale. (a)

True

(b)

False

3 For a 5-bit weighted-resistor DAC, the LSB weight is (b) 1132

(a) 32 (c)

1/31

(d) 15

4 In a 5-bit ladder DAC, with logic levels of 0 = 0 V and 1= 10V, the analog output for the digital input of 11010, is (a)

7.125 V

(b)

8.125 V

(d) 13 V

(c) 26 V

5 The percent resolution for a 9-bit ladder DAC is (a)

0.195

(b)

0.175

(c)

O. 150

(d)

O. 125

6 In a DAC with a resolution of 5 m V, the 1/2 LSB error is equal to (a)

5 mV

(b)

10 mV

(c)

2.5 mV

(d)

1.25 mV

7 A voltage DAC is faster than a current DAC. (a)

True

(b)

False

8 In a counter-type AID Converter with an n-bit output, the number of required clock pulses is (b) n

(d) 2n

9 In a successive-approximation AID converter, the output of DAC relative to analog voltage should be (a)

Less

(b) More

(c)

Equal

(d)

Any thing

10 The fastest of the ADCs is the (a)

Dual-slope ADC

(b)

Successive -approximation ADC

(c)

Flash ADC

(d)

Counter-controlled ADC

11 The number of analog comparators required in a flash AID converter of n bits, is (a) 2n - 1 (c) 2n -

(b) 2n - 1

1

(d) 22n- 1

DIA AND AID CONVERTERS

433

12 Conversion time of the SA-ADC increases with the analog input signal. (a)

True

(b)

False

13 Conversion time in a counter-ADC increases with the analog input signal. (a)

True

(b)

False

(b)

False

14 A flash ADC uses no clock-signals. (a)

True

ANSWERS 1 (b)

2 (b)

3 (c)

4 (b)

5 (a)

6 (c)

9 (b)

10 (c)

11 (c)

12 (b)

13 (a)

14 (a)

7 (b)

8 (a)

APPENDIX A PINOUTS 7400

7404

7402 14

Vee

14

14

2

13

2

13

2

13

3

12

3

12

3

12

4

11

4

11

4

11

5

10

5

10

5

10

6

9

6

9

6

9

7 GND

8

7

8

7

GND

GND

Quad NAND

Quad NOR

Hex Inverter

Fig. 1

Fig. 2

Fig. 3

7408

7410

7410

14

8

14

14

2

2

13

2

13

3

3

12

3

12

4

4

11

11

5

5

10

10

6

6

9

9

7

GND

8

Quad AND

8

TTL NAND

Triple AND

Fig. 6

Fig. 5

Fig. 4 7432

Vee

7486 14

Vee

14

2

13

2

3

12

3

4

11

4

11

5

10

5

10

9

6

6

7 GND

7

GND

13

Quad OR

QuadXOR

Fig. 7

Fig.S

8

435

APPENDIX A 4025

4002

4001 14

14

2

13

13

2

13

3

12

12

3

12

4

11

4

11

4

11

5

10

5

10

5

10

6

9

6

Ne

9

6

9

8

7

Vss

8

7 Vss

8

Vee

7

GND

Dual NOR (CMOS)

Quad NOR (CMOS)

Fig. 9

Triple NOR (CMOS)

Fig. 11

Fig. 10

MC724

CD 4049

Vee

15

3

14

4

13

5

12

6

11

7 GND

MC846 14

14

16

2

8

Ne

14

2

13

2

13

3

12

3

12

Vee 11

4

11

5

10

5

10

10

6

9

6

9

9

7

8

7 GND

8

4 GND

Quad NOR

Hex INVERTER

Quad NOR

Fig. 14

Fig. 13

Fig. 12

74180 8

9

10 11 12 13 11

2

J-,

15

13 12

4

PE Po

14 13

11

5

2 4

GND

Po

7

74180 3

PE

Vee 6

5

Vee 14

Is

14

3

LOE

12

10

6

LOa

I,

9

7

GND

10 8

Logic symbol

Fig. 16 Parity generator (8-bits)

Pinout

436

DIGITAL PRINCIPLES AND CIRcurrs 7476

74175

CP,

CLR

K,

+Vcc

Qo 2

15

~

00

3

14

0;

13 GND

Do

4

13

03

12 K2

0,

5

12

~

6

11

Q2

Q,

6

11

~

PRE2

7

10

0;

Q,

7

10

Q2

CLR2

8

9 J2

GND

8

9

CP

PRE,

2

15 Q

CLR,

3

14

J,

4

+ Vee

5

CP2

Q,

Dual JK flip-flop

Quad D flip-flop

Fig. 17 5

4

Fig. IS 13

12

0,

03

9

GND

9

8

8 74175 40175 74LS174

74175 .40175 74LS175 1

16

16

Logic symbol for Hex 0 flip-flop

Logic symbol for quad D flip-flop

Fig. 20

Fig. 19

9300 9

4

5

6

7 MR

2 10 3

J PE

P,

Vee

Qo 15

P3 GND

Q3

9300

CP

KMR

P2

Q3 14

13

8 11 16

Vee

16 15

P,

Qo Q, Q2 Q3

P2

0;

11

7

P3

CP

10

8

GND

PE

9

2

J

3

K

4

Po

5 6

12

Logic symbol

Fig. 21 Universal Shift-register (4-bits>

Pin-diagram

14 13 12

437

APPENDIX A CMOS 4404A 9

4

3

5

6

CEP

10

CET

2

TC

74LS169

Os

13(27)

(26 )3

0,

01

12

(2 5)4

06

O2

11 (2)

(24)5

05

NC

10

(23 )6

04

03

9(22)

15

Vee

CP

7 14

13

12

11

Fig. 22 Up/down counter symbol

NC

-Vss

24

A4 A3

Vee As Ag A12 CSICS

~

A10

19 18

8

A1 Ao

All Os

17

9 10 11

01 O2 03

Or

16 15 14

12

GND

06 05 04

A7

2 3

As

4 5 6 7

As

23 22 21 20

13

Fig. 24 Pinout for 8K x 8 ROM

93406

As Logic symbol

Os

A1 93406 256x4 ROM

~

A3 ~

As As Ar

00

8

Fig. 23 Pinout for 8-bit synchronous counter

2364 1

14

Reset

2

PE Po P1 P2 Po GNO VIO 7

+Voo

CP

Vee A7

18

C~

14

CS1 Do

13

15

2

As

3 4

A4 A3

5

Ao

6

A1

01

11

7

~2

10

8

GND

O2 03 Pinout

Fig. 25 Logic-symbol and pinout for 93406 ROM

12

9

438

DIGITAL PRINCIPLES AND CIRCUITS 2764

2708

2732

A7 2 3 4 5 6 7

8 9 10 11 12

As

Ag

A4 A3 A2 A,

VBB Cs/WE VDD PROG

24 23 22 21 20 19 18

Ao

07

17

00 0,

Oe

16 15 14 13

As

As

05 04 03

O:! GND

7

8 9 10 11 12

Vpp

Vpp

28

2 4

As

PGM NC As

27

3

A12 A7

5

24

8

~

All OE A10

23

7

A5 A4 A3

Ag

CEICS Y7

20

Ye

18

Y5 Y4 Y3

16

As

Vee As

As

Ag

A4 A3 A2 Al

All DE A10 CE

24 23 22 21 20 19 18

Ao

~

17

00 0,

Oe

16 15 12 14 13 13 14

A7 2 3 4 5 6

1

05 04 03

O2 GND

6

9

Al

10

Ao

11

Yo Y, Y2 GND

4KxB

1Kx8

26 25

22 21 19 17

15

BKx8

Fig. 26 Pinouts for EPROMs

5101 1 2 3 4 5 6 7

8 9 10 11

A3 ~

A,

Ao

As As A7 GND

01, 00, 012

Aee A4 WE CE, OE CE2 004 014 003 013 002

CMOS RAM

22 21 20 19 18 17 16 15 14 13 12

2114

As 2 3 4 5 6 7

8 9

A5 A4 A3

Vee A7 As

18

Ag

15 14 13

Ao

00,

A, A2 CE

002

GND

17 16

4116 2 3 4

004

12 11

5 6 7

WE

10

8

003

NMOS static RAM

Fig. 27 Pinouts for

RAM~

VBB D,n WE RAS

Ao ~

A, VDD

Vss CAS

16 15

°OUI

As

14 13 12 11 10

Vee

9

As A3 A4

NMOS dynamic RAM

APPENDIX A

439 51C67 16 2

A,

A'3

15

3

~

A'2

14

4

A3

A"

13

5

A4

A,o

12

Ag

As

6 7

As

Aa

8

D out

A7

9

WE

Dm

10

GND

CS

51C64L NC

11 10

16

2

DIN

CAS

15

3

WE

DOUT

14

4

RAS

As

13

A3 A4 As

12

~

9

5

Ao A2 9 7 A, 10 8 VDD 9

6

SRAM

11 10

DRAM

Fig. 28 Static and dyanmic RAMs

20

22

2

19

18

4

3

17

5

16

15

7

6

9 13

12

00

D,

10

11

14

9

8

Fig. 29 256 x 4 High-speed bipolar RAM

24

23

22

21

20

19

18

17

16

15

14

6161 CMOS RAM

2

3

4

5

Ao _ A,o : Address /10, _ /IOa : Data in/out

CS WE

: Chip select : Write enable

6

A,

Ao

7

8

9

10

11

12

OE : Output enable Vee: Power GND: Ground

Fig. 30 2K x 8 CMOS RAM

13

440

DIGITAL PRINCIPLES AND CIRCUITS PLA 10J8

AND

PLA 14L4

~--&._

GATE

ARRAY ~--&.-

PLA 16R4

r-----,

r------,

PLA 16C1

4 5

AND OR GATE

6

ARRAY

7 8

Fig. 31 Pinouts of active-high lORS, active-low l4L4, complementary, and registered l6R4 PLAs

APPENDIX A

441 DAC0808

DAC 1408

NC Compensation

2

GND

3

VEE

4

lOUT

NC

16

Compensation

16

VR(_)

15

15

2

VR(+)

14

3

VEE

oc

VR(+)

14

Vee

13

4

VOUT

8 Vee

13

De

Ve

12 11

VR(_)

GND

5

V7

Do

12

5

D,

6

D6

D,

11

6

~

~

V7

7

Ds

O2

10

7

D3

Os

Vs

10

8

04

03

9

8

04

Os

Vs

9

Fig. 32 Pinouts of8-bit high-speed D/A converters

0801 CS

Vee

20

2

RO

CLKR

19

3

WR

00

18

4

CLKIN

0,

17

5

INTR

O2

16

6

lliN (+)

03

15

7

lliNH

04

14

8

GNOA

Os

13

VR/2

Os

12

GNOD

07

11

9 10

Fig.33 Pinout of 8-bit 0801 AID converter

APPENDIX B 7400 Series ICs Number 7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 I

7410 7411 7412 7413 7414 7416 7417 7420 7421 7422 7423 7425 7226

Function

Number

Quad 2-input NAND gates 7430 Quad 2-input NAND gates (open 7432 collector) 7437 Quad 2-input NOR gates 7438 Quad 2-input NOR gates (open collector) 7439 Hex inverters 7440 Hex inverters (open collector) 7441 Hex inverter buffer-driver Hex buffer-drivers 7442 Quad 2-input AND gates 7443 Quad 2-input AND gates (open 7444 collector) 7445 Triple 3-input NAND gates 7446 Triple 3-input AND gates Triple 3-input NAND gates (open 7447 collector) Dual Schmitt trigger 7448 Hex Schmitt triggers Hex inverter buffer-drivers 7450 Hex buffer-drivers Dual 4-input NAND gates 7451 Dual4-input AND gates 7452 Dual 4-input NAND gates (open collector) 7453 Expandable dual 4-input NOR gates 7454 Dual 4-input NOR gates Quad 2-input TTL-MOS interface 7455 NAND gates

7427

Tripple 3-input NOR gates

7428

Quad 2-input NOR buffer

7459

Function 8-input NAND gate Quad 2-input OR gates Quad 2-input NAND buffers Quad 2-input NAND buffers (open collector) Quad 2-input NAND buffers (open collector) Dual 4-input NAND buffers BCD-to-decimal decoder-Nixie driver BCD-to-decimal decoder Excess 3-to-decimal decoder Excess Gray-to-decimal BCD-to-decimal decoder-driver BCD-to-seven segment decoderdrivers (30-V output) BCD-to-seven segment decoderdrivers (15-V output) BCD-to-seven segment decoderdrivers Expandable dual 2-input 2-wide AND-OR-INVERT gates Dual 2-input 2-wide AND-ORINVERT gates Expandable 2-input 4-wide ANDOR gates Expandable 2-input 4-wide ANDOR-INVERT gates 2-input 4-wide AND-OR-INVERT gates Expandable 4-input 2-wide ANDOR-INVERT gates Dual 2-3 input 2-wide AND-ORINVERT GATES

APPENDIX 8 7460 7461 7465 7470 7472 7473 7474 7475 7476 7480 7482 7483 7485 7486 7489 7490 7191 7492 7493 7494 7495 7496 74100 74104 74105 74107 74109 74116 74121 74122 74123 74125 74126 74132 74136

443

Dual4-input expanders Triple 3-input expanders 4-wide AND-OR-INVERT gates (open collector) Edge-triggered JK flip-flop JK master-slave flip-flop Dual JK master-slave flip-flop Dual D flip-flop Quad latch Dual JK master-slave flip-flop Gates full adder 2-bit binary full adder 4-bit binary full adder 4-bit magnitude comparator Quad EXCLUSIVE-OR gate 64-bit random-access read-write memory Decade counter 8-bit shift register Divide-by-12 counter 4-bit binary counter 4-bit shift register 4-bit right-shift-Ieft-shift register 5-bit parallel-in-parallel-out shift register 4-bit bistable latch JK master-slave flip-flop JK master-slave flip-flop Dual JK master-slave flip-flop Dual JK positive-edge-triggered flip-flop Dual 4-bit latches with clear Monostable multivibrator Monostable multivibrator with clear Monostable multivibrator Tri-state quad bus buffer Tri-state quad bus bl.lffer Quad Schmitt trigger Quad 2-input EXCLUS1VE-OR gate

74141 74142 74145 74147 74148 74150 74151 74152 74153 74154 74155 74156 74157 74160 74161 74162 74163 74164 74165 74166 74LS169 74173 74174 74175 74176 74177 74179 74180 74181 74182 74184 74185 74189

BCD-to-decimal decoder-drive BCD counter-latch-driver BCD-to-decimal decoder-driver 10/4 priority encoder Priority encoder 16-line-to-1-line multiplexer 8-channel digital multiplexer 8-channel data selectormultiplexer Dual 4/1 multiplexer 4-line-to-16-line decoderdemultiplexer Dual 2/4 demultiplexer Dual 2/4 demultiplixer Quad 2/1 data selector Decade counter with asynchronous clear Synch onous 4-bit counter Synchronous 4-bit counter Synchronous 4-bit counter 8-bit serial shift register Parallel-load 8-bit serial shift register 8-bit shift register Up/down counter 4-bit tri-state register Hex flip-flop with clear Quad D flip-flop with clear 35-MHz perceptible decade counter 35-MHz presettable binary counter 4-bit parallel-access shift register 8-bit odd-even parity generatorchecker Arithmetic-logic unit Look-ahead carry generator BCD-to-binary converter Binary-to-BCD converter Tri-state 64-bit random-access memory

444

74190 74191 74192 74193 74194 74195 74196 74197 74198 74199 74221 74251

DIGITAL PRINCIPLES AND CIRCUITS

Up-down decade counter Synchronous binary up-down counter Binary up-down counter Binary up-down counter 4-bit directional shift register 4-bit parallel-access shift register Presettable decade counter Presettable binary counter 8-bit shift register 8-bit shift register Dual one-shot Schmitt trigger Tri-state 8-channel multiplexer

74259 74276 74279 74283 74284 74285 74365 74366 74367 74368 74390 74393

8-bit addressable latch Quad JK flip-flop Quad debouncer 4-bit binary full adder with fast carry Tri-state 4-bit multiplexer Tri-state 4-bit multiplexer Tri-state hex buffers Tri-state hex buffers Tri-state hex buffers Tri-state hex buffers Individual clocks with flip-flops Dual 4-bit binary counter

OTHER ICs 1408 2114 2364 2708 2732 2764 4001 4002 4025 4116 4404A 5101 6161

8-bit DIA converter NMOS static RAM 8Kx 32 ROM 1Kx 8 EPROM 4Kx8EPROM 8Kx8EPROM Quad 2-input CMOS NOR Dual 4-input CMOS NOR Triple 3-input CMOS NOR NMOS dynamic RAM CMOS synchronous counter CMOS RAM CMOS RAM

9300 93408 0801 0808 16C1 10H8 14L4 16R4 CD 4049 MC724 MC846 51C67 51C 64L 93L 422

4-bit universal shift register 256 x 4 ROM 8-bit NO converter 8-bit DIA converter PLA PLA PLA PLA Hex inverter Quad 2-input XOR gates Quad 2-input NAND gates Static RAM Dynamic RAM 256 x 4 bipolar RAM

APPENDIX C SOLUTIONS TO ODD-NUMBERED PROBLEMS Chapter 2 2.1

(a) 101 2 = 1 X 22 + 0 X 21 + 1 x 2° = 510 (b) 11011 2 = 2710 (c) 0.1001 2 = 0.5610

2.3

(f) 101.0012 = 5.125 10 (a) 110 (b) 010 110

J, 2.5

(a)

(b)

(d) (e)

2.7

(a)

J,

(c) 0·1011

J, (a) (b) (d)

(f) 2.11

(a)

J,

J,

J,

J,

B 0100

J,

J,

J,

J,

J,

J,

2 2 = 228 (b) 8.A16 = 1000 . 10102 = 001 000· 101

J,

J,

1 O· 5 = 10.5 8 (d) A7.2 16 = 1010111 . 102 = 001 010111·100

J,

J,

1 2 (a) 1110 2 + 1011 2 = 11001 2 = 25 10

J,

J,

7· 4=127.48

J,

3 ' 7 = 3.78

J,

E E = EE 16 O·B 4 = 0·B416 1 20 16 = 2 X 16 + 0 x 16° = 3210 AB2 16 =A X 162 + B X 161 + 2 x 16° = 2738 10 7,C 16 = 7 x 16° + C x 16-1 = 7.75 10 9.3A16 = 9 x 16° + 3 x 16-1 + A X 16-2 = 9.2410 1816 = 100102 = 010 010

J,

011· 111

7 5 C = 5.7C 16 (d) 1110· 1110

7 = B7 16

J,

213.

(d)

J,

6 7· 5 = 67.5 8 2 6 = 268 1 128 = 1 X 8 + 2 x 8° = 10 10 1248=lx82+2x81+4x8o=8410 16.28 = 1 X 8 1 + 6 x 80 + 2 X 8-1 = 14.25 10 2642.5 8 = 1442.6210 (b) 0101·0111 1100 101101112 = 1011 0111

J,

2.9.

(c) 110 111 . 101

J,

446

DIGITAL PRINCIPLES AND CIRCUITS (b) 1011.102 + 1111· 01 2 = 101001.11 2 = 41.75 10 (e) 10101 2 + 0.110 2 = 10101.1102 = 21.75 10 (e) 111.1 2 + 111.1 2 = 1111· O2 = 15 10

2.15 2.17 2.19 2.21 2.23. 2.25 2.27 2.29

x 9 10 = 1111 X 10012 = 100001112 :: 135 10 (b) 23 x 2.5 10 = 10111 X 10.1 2 = 111001.1 2 = 57.5 10 (a) (7+4)8=13 8 (b)(26 +6.2)8 =34.2 8 (e) (512·3 + 22·7)8 = 535.2 8 (d) (3·04 + 6·1)8 = 11.148 (a) (74 - 36)8 = 36 8 (b) (24.2 - 15.6)8 = 06.48 (a) (5 x 6)8 = {l01 x 110h = 011110 2 = 36 8 (e) (3.2 x 7)8 = (011 . 010 x 111h = 010 110 . 110 2 = 26.68 (a) 01000 (+8), (b) 0010111 (+41), (e) 001100 (+12), (d) 011100 (+28) N =10 bits (a) 01011, (b) 0110, (d) 00100 (e) 1110q, Product 11110002 (a) 15

Chapter 3 3.1

(a) 1000,

(b) 0010 0000 0110 0111, (e) 0101 1001 0110 1000,

(d) 1000 0010 0101 0011. 3.3

(a) 1001 1011, (b) 0110 01000101, (e) 0100 1010, (d) 0111 0011 1011

3.5

(a) 01000110,

3.7

(a) 11011,

3.9

(a) 10010101000,

3.11

8310

~

(b) 1010, (e) 1011, (d) 0100 0100

(b) 1111011100,

(e) 011000.

(b) 10110010 10111, (e) 01101110010

1001 0011 using Table 3·3.

3.13

(a) 25 10 ~ 0000000100, (b) 4310~ 0000100000 using Table 3·7.

3.15 3.17

'63 10 using Table 3.3. (a) 101111, (b) 0100 0111, 0111.

(e) 0111 1010;

(d) 2F,

(e) 57,

(f) 011 0101 011

3.19 HELP

Chapter 4 4.1 4.3 4.5

4.7

2 1°,00000000002 ,1111111111 2

INVERTER (a) Negative, (b) Positive, (e) Negative, (d) Positive AB+AB= AB(A +B)

A

B

A

B

AB

AB

AB

AB

A+B

0

0

1

1

0

0

0

1

0

0

0

0

1

1

0

1

0

0

1

1

1

1

1

0

0

1

0

1

0

1

1

1

1

1

0

0

0

0

1

0

1 1 .

0

0

APPENDIXC

447

--

4.9

A

B

0 0 1 1

0 1 0 1

-

AB AB A-I;B A+B Neg. Al"lD :::: NOR Neg. OR:::: NAND Neg. NAND:::: OR Neg. NOR:::: AND

1 0 0 0

1 1 1 0

0

0 1 1 1

0 0 1

4.11 A

INPUT Waveforms

,,

B

AB

,,

Jl ,

,, - - - - ! - - ! - - - !-,

AND OUTPUT waveforms

A+B

AB

-U;-'

A+B

"

1 - - - - - OR

--~--+-----

,,

,,

,

j - '- - . . . ;

NAND

i - - - - - NOR

AND

4.13

j--------------------A

B I ..............................................,

5.1

5.3

A

B

AB

(A +AB)::::A

A

B

AB

A

0

0

0

0

0

0

0

1

1

0

0

1

0

0

0

1

0

1

1

0

1

0

0

1

1

0

0

0

o

0

1

1

1

1

1

1

1

0

1

1

=A . B· (B + C) =AB + An C =An

(a)

A +B +C+D

(b)

A(B+C)(C +D) =A+BC +CD

(c)

A (jj + C ) = A + BC

(d) ABC + An

:: lA ... B ;- C )(A + B) :: AC + B C + Ali + An =1\(8 + C) + B