Digital Design: Basic Concepts and Principles (Solutions, Instructor Solution Manual) [1 ed.] 9781420061314, 9781439852040, 1420061313

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SOLUTIONS MANUAL FOR Digital Design: Basic Concepts and Principles

by Mohammad A. Karim Xinghao Chen

SOLUTIONS MANUAL FOR Digital Design: Basic Concepts and Principles

by Mohammad A. Karim Xinghao Chen

Boca Raton London New York

CRC Press is an imprint of the Taylor & Francis Group, an informa business

CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2011 by Taylor and Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number: 978-1-4398-5204-0 (Paperback) This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com

FOREWARD Too many digital design problems do not have unique solutions. A problem may have many different solutions – each one of them often valid. One solution may be preferred over another based on parameters such as cost of the overall solution, speed of the resulting device, or ease with which one arrives at the solution. While one can go about finding a valid solution using steps that have been highlighted and worked out in the text book, there are too many digital problems for which solutions can be found simply by observations of patterns and other such visual cues that would often be missed by most inexperienced designers. While writing Digital Design: Basic Concepts and Principles, the authors were particularly cognizant that the students do not come away thinking that they have to always arrive at the same design conclusion. As such, the authors have worked out a whole variety of many problems in each of the chapters with two objectives in mind: (a) provide examples for students to study and be able to work out most problems; and (b) emphasize what assumptions were often made in a worked-out problem to arrive at that particular solution. A different set of assumptions for some of the problems could easily lead to a completely different but valid solution. In working out mostly the odd-numbered problems in this Solution Manual, we have chosen to either direct the instructors to appropriate worked out example in the main textbook if one so exists or provide enough hints and steps to complete the problem. However, even for those problems that have been worked out in full, we want to insist yet again that for many of these problems there may be other equally valid solutions. While grading home works of students, therefore, instructors will need to be particularly careful to not use this Solution Manual as their final arbiter but focus on what assumptions were made by a student in coming up with his or her respective solutions. MAK XC

1.1.

See worked out Examples 1.1 and 1.2 (page 6) for these problems.

Multiply each one of the given digits by their respective values of Rn where R is the given radix and n represents the position (positive for integer part and negative for fraction part). Add the products together to find base-10 equivalent.

1.2.

See worked out Examples 1.3 (page 7) and 1.8 (page 11) for these problems.

(i) As shown in Example 1.3, take the integer part of the given base-10 number and divide successively by 2 to determine remainders until the result is 0. The first-found remainder is LSDi and the last one is MSDi. The equivalent integer in base-2 is then MSDi…LSDi. Then as shown in Example 1.8, take the given fractional part and multiply it successively by 2 to determine integers that get generated to the left of decimal point. The first-found integer is MSDf and the last one is LSDf. The equivalent integer in base-2 is then MSDf…LSDf. The equivalent base-2 number is MSDi…LSDi.MSDf….LSDf (ii) Repeat 1.2(i) using 8 to divide with as well as to multiply with. Alternatively, once we have had the base-2 number in 1.2(i), we can extract the equivalent base-8 number by grouping the base-2 numbers in three’s and substituting their equivalent octal number using Table 1.3 (page 9). (iii) Repeat 1.2(i) using 16 to divide with as well as to multiply with. Alternatively, once we have had the base-2 number in 1.2(i), we can extract the equivalent base-16 number by grouping the base-2 numbers in four’s and substituting their equivalent hexadecimal number using Table 1.3 (page 9).

1.3. Line up the two given numbers column-wise based on their respective positional weights. Next, add the digits column-wise starting at the least significant position. (a) Each time sum of a column is 2 or more, convert the sum to its equivalent base-2 number. Place the lower significant number as sum under the column in question. Then move to the column on the left with a carry-out of 1 and find the sum for this new column. (b) Repeat 1.3(a) above but use 8 instead of 2. (c) Repeat 1.3(a) above but use 16 instead of 2. (d) Repeat 1.3(a) above.

1.5. (a) See worked out Example 1.18 (page 28). 423 – 526 can be determined as follows: 1024 423 = 1 -526= 0 0

-512 1 1

256 0 0

-128 1 0

64 1 0

-32 1 1

16 1 1

-8 1 0

4 0 1

-2 1 1

1 1 0

0

0

1

1

1

0

1

0

0

1

Therefore, 423 – 526 = -128 + 64 - 32 - 8 + 1 = -103 (b) See worked out Example 1.19 (page 29). 423 = 1 -526= 0

1’ 1’

0 0

1’ 0

1 0

1’ 1’

1 1

1’ 0

0 1

1’ 1’

1 0

Sig = 1 Chi = 01’ S= 00

0 0 0

0 0 0

1’ 0 1’

1 1’ 0

0 1 1

0 0 0

1’ 0 1’

1 1’ 0

0 1 1

1’ 1’

The resulting sum = 1’0101’011’ = -128 + 32 – 8 + 2 – 1 = -103 In signed 2’s complement form: 423 = 0 0110100111 526 = 0 1000001110 -526= 1 0111110010 Thus, 423-526

= 1 1110011001 = -(0 0001100111) = -(64+32+4+2+1) = -103

1.7. The range of acceptable numbers in the 1’s complement system is symmetric, and equals -(2n-1 – 1) and (2n-1 – 1). As a result, there are two representations of zero, for +0 and -0. The given equation is correct and can be validated by checking, for example, 1010 which represents the value –(23 – 1) + 2 = - 5.

1.9. (a) 1000 0111 0110 0100 0101 (b) 0011 0100 0010 0001 0100 0101.0011 0010 (c) 0001 0100 0101 0010 0011.0010 0101

1.11.

See worked out Example 1.20 (page 37) for each of these problems. We work out 1.11(a) for emphasizing the steps.

(a) m = 8. Therefore, p = 4 and thus the result will be a 12-bit word. 1100 1011 1010 1001 1 1 0 1 The Hamming coded word =

1000 0111 0110 0101 0100 0011 0010 0001 0 1 1 1 1 1 1 0 110110111110.

1.13. See worked out Example 1.20 (page 37). m=4, p=3 and thus the result is a 7-bit word. Parity 1 will take care of positions 3, 5 and 7 Parity 2 will take care of positions 3, 6 and 7 Parity 3 will take care of positions 5, 6 and 7 Accordingly, 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

0001011 0001100 0010011 0010100 0100000 0100111 0111000 0111111 1000000 1000111

2.1 (a) A.(B.C) = (A.B).C A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

B.C 0 0 0 1 0 0 0 1

A.B 0 0 0 0 0 0 1 1

A.(B.C) 0 0 0 0 0 0 0 1

(A.B).C 0 0 0 0 0 0 0 1

Therefore, A.(B.C) = (A.B).C (b) A.(A’+B) = A.B A.(A’+B) = A.A’ + A.B = 0 + A.B = A.B (c) (A.B)’ = A’ + B’ A 0 0 1 1

B 0 1 0 1

A’ 1 1 0 0

B’ 1 0 1 0

(AB)’ 1 1 1 0

A’+B’ 1 1 1 0

Therefore, (A.B)’ = A’ + B’ (d) (A+B).(A’+C) = AC +A’B (A+B).(A’+C) = A.A’ + A.C + B.A’ + B.C = A.C + B.A’ + B.C = A.C + A’.B

2.3. (a) (Sum(0,1,3,4,6)’ = (A’B’C’ + A’B’C + A’BC + AB’C’ + ABC’)’ = (A+B+C)(A+B+C’)(A+B’+C’)(A’+B+C)(A’+B’+C) =(A+B+AC+BC)(A+B’+C’)(A’+A’B’+A’C+A’B+BC+A’C+B’C+C) =(A+B)(A+B’+C’)(A’+BC+B’C+C)=(A+B)(A+B’+C’)(A’+C) =(A+AB+BC’)(A’+C) = A’BC’+AC+ABC= A’BC’+ABC+AB’C = Sum(2,5,7)

2.5. (a) (AB+AC’+A’C)’ = (A’+B’)(A’+C)(A+C’) = (A’+A’C+A’B’+B’C)(A+C’) =(A’+B’C)(A+C’) = AB’C+A’C’ (b) (A(A+C’))’ = (A+AC’)’ = A’(A’+C) = A’ + A’C = A’ (c) (BC’+B’C)’ = (B’+C)(B+C’) = BC + B’C’ (d) (AB + A’B’)’ = (A’+B’)(A+B) = AB’ + A’B

2.7 A’ XOR B’ = (A’)’B’ + A’(B’)’ = AB’ + A’B = A XOR B A XOR B XOR AB = (A’B + AB’) XOR AB = (A’B + AB’)’AB + (A’B + AB’) (AB)’ = (A+B’)(A’+B)AB + (A’B + AB’)(A’ + B’) = (A’B + AB)AB + (A’B + AB’) = AB + A’B + AB’ = A + A’B = A + B (A XOR B)’ = A XOR B XOR 1 RHS = (AB’ + A’B) XOR 1 = (AB’ + A’B)’.1 = (A XOR B)’ = LHS 2.9. B3B2B1B0 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000

G3G2G1G0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

We can determine the answer both by observation and Boolean algebra. G3 = B3 G2 = B3 XOR B2 G1 = B3 XOR B2 XOR B1 G0 = B3 XOR B2 XOR B1 XOR B0

2.11. ABC 000 001 010 011 100 101 110 111

f 0 0 0 1 0 1 1 1

Thus, f = A’BC + AB’C + ABC’ + ABC = (A’B + AB’)C + AB = (A XOR B)C + AB

2.13. ABCD EFGH 0000 0000 0001 1111 0010 1110 0011 1101 0100 1100 0101 1011 0110 1010 0111 1001 1000 1000 1001 0111 1010 0110 1011 0101 1100 0100 1101 0011 1110 0010 1111 0001

E = A’B’C’D + A’B’CD’ + A’B’CD’ + A’B’CD + A’BC’D’ + A’BC’D + A’BCD’ + A’BCD + AB’C’D’ F = A’B’C’D + A’B’CD’ + A’B’CD + A’BC’D’ + AB’C’D + AB’CD’ + AB’CD + ABC’D’ G = A’B’C’D + A’B’CD’ + A’BC’D + A’BCD’ + AB’C’D + AB’CD’ + ABC’D + ABCD’ H = D (by observation)

2.15. (AB XOR AC)’((A+B) XOR (A+C))’ = [(AB)’AC + AB(AC)’]’[(A+B)’(A+C) + (A+B)(A+C)’]’ = [(A’+B’)AC + AB(A’+C’)]’[A’B’(A+C) + (A+B)A’C’]’ = [AB’C + ABC’]’[A’B’C + A’BC’]’ = (A’+B+C’)(A’+B’+C)(A+B+C’)(A+B’+C) = (A’+B’C’+BC)(A+B’C’+BC) = AB’C’ + ABC + A’B’C’ + B’C’+A’BC+BC = AB’C’ + BC + B’C’ = BC + B’C’ = (B XOR C)’

2.17. Put a second TG below the one in Figure 2.P1. Let (a) NOT output (C‘) be connected to the top input of this second TG, (b) C be connected directly to the bottom input of this second TG, and (c) X‘ be connected to the input of second TG. Tie the two outputs together to generate the overall output. When both C and X are low, the top TG is ON and bottom TG is OFF which makes the output same as A. When both C and X are high, the top TG is OFF and bottom TG is ON which makes the output same as A‘.

2.19. A XOR (B XOR C) = A XOR (B’C + BC’) = A’(B’C + BC’) + A(BC + B’C’) = A’B’C + A’BC’ + ABC + AB’C’ = (A’B’ + AB)C + (A’B + AB’)C’ = (A XNOR B)C + (A XOR B)C’ = (A XOR B) XOR C

2.21. (A XOR B)’ = (A’B + AB’)’ = (A+B’)(A’+B) = (AB + A’B’) = (A XNOR B)

3.1. Follow Examples 3.1 (page 77) and 3.2 (page 80). The answers may not be unique. 3.3. Follow Example 3.6 (page 88) and as reflected in Figure 3.17. The answers may not be unique based on the groupings chosen. 3.5. Following Figure 3.18 (page 89), as an example, let’s work out 5(a) for f = f(a,b,c,d,e). mabcdef 0000001 0000010 1000101 1000110 2001000 2001010 3001100 3001110 4010001 4010010 5010101 5010110 6011000 6011010 7011100 7011110 8100001 8100010 9100101 9100110 A101000 A101010 B101100 B101110 C110001 C110010 D110101 D110110 E111000 E111010 F111100 F111110

d’ d’ d’ d’ 0 0 0 0 d’ d’ d’ d’ 0 0 0 0 d’ d’ d’ d’ 0 0 0 0 d’ d’ d’ d’ 0 0 0 0

By plotting these all in a 4x4 K-map, we can conclude that f = c’d’.

3.7. (a) f = A’B’(DE) + AC’(F) (b) f = A’(C’ + D) + AC’(E) + ACD(F) (c) f = C’D’+ BC’ + A’C(E) + CD’(F) + A’B’C’D(E) (d) (e)

3.9a. f(A,B,C,D)

= (A’C + CD’ +A’D)(B’ + D’) = A’B’C + BCD’ + A’B’D + A’CD’ + CD’ = A’B’CD + A’B’CD’ + ABCD’ + A’BCD’ + A’B’C’D + A’B’CD + A’B’CD’ + A’BCD’ + A’B’CD’ + A’BCD’ + AB’CD’ + ABCD’ = Sum m(2,3,6,9,10,14)

3.9c. f(A,B,C,D,E) = AB--- + --C’D- + --- DE = (24, 25, 26, 27, 28, 29, 30, 31)+ (00C’D- + 01C’D- + 10C’D- + 11C’D-) +(000DE + 001DE + 010DE + 011DE + 100DE + 101DE + 110DE + 111DE) = (24,25,26,27,28,29,30,31) + (2,3,10,11,18,19,26,27) +(3,7, 11, 15, 19, 23, 27, 31) = Sum m(2,3,7,10,11,15,18,19,23,24,25,26,27,28,29,30,31) 3.9e. f(A,B,C,D)

= (A’ + C’)(A + B’)(B + D’) = (AC’ + A’B’ + B’C’)(B + D’) = ABC’ + AC’D’ + A’B’D’ + B’C’D’ = ABC’- + A-C’D’ + A’B’-D’ + -B’C’D’ = (12,13) + (8,12) + (0,2) + (0,8) = Sum m(0,2,8,12,13)

3.11. Follow and repeat Example 3.10 (page 109) for these three problems.

3.13 ABCDf 00001 00010 00100 00111 01000 01011 01101 01110 10000 10011 10101 10110 11001 11010 11100 11111 f(A,B,C,D) = A’ XOR B XOR C XOR D

3.15. abcd 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100

efgh 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 h = d’ (by observation)

For the other three functions, we can group 0’s: e’ = a’ + c’d + cd’ + bd + b’d’ e = a(c + d’)(c’ + d)(b’ + d’)(b + d) Likewise, f = (a’ + b’)(a + b)(a + c)(a + c’ + d)(a’ + c’ + d’) g = (a + b)(a’ + b’)(c’ + d’)(c + d)

3.17. By plotting f in a 4-variable K-map, we find that the groups of 0’s have two nonoverlapping edges that would cause glitch (when b changes value and when c changes value). These two glitches can be removed by including (A’ + D’), that covers these two non-overlapping edges, as an additional POS term.

3.19.

ab x cd = efgh abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

efgh 0000 0000 0000 0000 0000 0001 0010 0011 0000 0010 0100 0110 0000 0011 0110 1001

e = abcd f = ab’cd’ + ab’cd + abcd’ + abcd = ab’c + abc = ac g = a’bcd’ + a’bcd + ab’c’d + ab’cd + abc’d + abcd’ = a’bc + ab’d + abc’d + abcd’ h = a’bc’d + a’bcd + abc’d + abcd = a’bd + abd = bd

4.1. Follow the steps used in Example 4.3 (page 124) for each of these problems.

4.3. C4

= G3 + P3G2 + P3P2G1 + P3P2P1 (G0 + P0C0) = (G3’ (P3G2)’ (P3P2G1)’ ((P3P2P1)’ + (G0 + P0C0)’)’

4.5a. A XOR B XOR AB = (A’B + AB’) XOR AB = (AB + A’B’)AB + (A’B + AB’)(A’ + B’) = AB + A’B + AB’ = A + B A XOR A’B = A’(A’B) + A(A + B’) = A’B + A + AB’ = A’B + A = A + B

4.5b. A (B XOR C) = A(B’C + BC’) = AB’C + ABC’ AB XOR AC = (A’ + B’)AC + AB(A’ + C’) = AB’C + ABC’ Therefore, A(B XOR C) = AB XOR AC.

4.5c. (A XOR B XOR C)’ = A XOR (B XOR C)’ = A XOR B XNOR C

4.5d. A XNOR B = AB + A’B’ A XOR B’ = AB + A’B’ Thus, A XNOR B = A XOR B’ and likewise = A’ XOR B.

4.7. For each of 4.6 problems, find the closest matched XOR K-maps from Figure 4.15 (page 128). Then carry out the problem using the steps same as in Example 4.7 (page 131).

4.9. For each of 4.8 problems, carry out the problem using the steps same as in Example 4.4 (page 125).

4.13a. f = AB’C + BD + AD’ = AB’C(D + D’) + (A+A’)B(C+C’)D + A(B+B’)(C+C’)D’ =A’B’C’(0) + A’B’C(0) + A’BC’(D) + A’BC(D) + AB’C’(D’) + AB’C(1) + ABC’(1) + ABC(1) The 1-of-8 MUX data inputs should then be 0, 0, D, D, D’, 1, 1, and 1.

4.13b. f = AB’C + BD + AD’ = AB’C(D + D’) + (A+A’)B(C+C’)D + A(B+B’)(C+C’)D’ =B’C’D’(A) + B’C’D(0) + B’CD’(A) + B’CD(A) + BC’D’(A) + BC’D(1) + BCD’(A) + BCD(1) The 1-of-8 MUX data inputs should be A, 0, A, A, A, 1, A, and 1.

4.13c. f = AB’C + BD + AD’ = AB’C(D + D’) + (A+A’)B(C+C’)D + A(B+B’)(C+C’)D’ =A’C’D’(1) + A’C’D(B) + A’CD’(0) + A’CD(B) + AC’D’(1) + AC’D(B) + ACD’(1) + ACD(1) The 1-of-8 MUX data inputs should be 1, B, 0, B, 1, B, 1 and 1.

4.17. Follow worked-out Example 4.11 (page 142).

4.19. Each of these functions will need to be set up differently, for example, with (i) A and B as control; (ii) A and C as controls; (iii) A and D as controls, and so on.. For 4.19(a),

Sum m(1,3,4,6,9,11,13,15) = A’B’C’D + A’B’CD + A’BC’D’ + A’BCD’ + AB’C’D + AB’CD + ABC’D + ABCD = A’B’(D) + A’B(D’) + AB’(D) + AB(D) ……………………………….(1) = A’C’(B XOR D) + A’C(B XOR D) + AC’(D) + AC(D) …………………(2) = A’D’(B) + A’D(B’) + AD’(0) + AD(1) …………………………………(3) Other than a 1-of-4 MUX, Option 1 and 3 will require 1 NOT gate each. Option 2 on the other hand will require an XOR gate. We could also seek to explore other control combinations: B and C, B and D, and C and D. It seems that we have already identified Options 1 and 3 as reasonably optimum since they require a NOT gate rather an XOR.

4.21. Follow worked-out Example 4.15 (page 156).

4.23. We can design a 5-to-32 line decoder using 3-to-8 line decoders as follows. A 3-to-8 line decoder is followed up by four 3-to-8 line decoders nearly in the same format as that done in Figure 4.41 (page 153) except that (a) one of three inputs and (b) four of eight outputs of the first 3-to-8 line decoders are unused.

4.25. We can design a 6-to-64 line decoder using 3-to-8 line decoders as follows. A 3-to-8 line decoder is followed up by eight 3-to-8 line decoders. Unlike Problem 4.23 above, all three inputs as well as all eight outputs of the first 3-to-8 line decoders are used.

4.27. Follow Example 4.17 (page 161) with 6 inputs (a2a1a0b2b1b0) and six outputs for product (p5p4p3p2p1p0).

4.29., 4.31., 4.33, 4.35. Follow Example 4.18 (page 171) for these four problems. Start with a Truth Table for each of the problems.

4.37. Follow Example 4.7 (page 131). The solution is Ci+1 = (Ai XOR Bi)Ci + AiBi. 4.39. Follow Example 4.20 (page 179).

4.41 Follow Example 4.19 (page 178) for (a), (b), and (c). Plot the resulting truth table and then confirm your observations.

5.1., 5.3., 5.5. The solutions are very similar to the examples shown in Chapter 5.

6.1. Follow Example 4.15 (page 156) - feed D0, D1, D3 and D4 as inputs to a 4-input NAND logic gate.

6.3. From the 16-input 4-output truth table of a priority encoder (similar to the one shown in Example 6.2, page 230), the following equations are obtained. f3 = D8 + D9 + …... + D15 f2 = (D4 + D5 + D6 + D7)(D8 + D9 + D10 + D11)’ + D12 + D13 + D14 + D15 f1 = (D2 + D3)(D4 + D5 + …+ D13)’ + (D6 + D7)(D8 + D9 + ...+ D13)’ + (D0 + D11)(D12 + D13)’ + D14 + D15 f0 = (...((((D1D2’ + D3)D4’ + D5)D6’ + D7)D8’ + D9)…)D14’ + D15 The logic circuit is then obtained from above equations.

6.5. (a) Extend Figure 6.23 (page 246) by adding 2 more bits to the left. (b) Extend Figure 6.23 (page 246) by adding 6 more bits to the left. (c) Extend Figure 6.23 (page 246) by adding 10 more bits to the left.

6.11. (a) Add 1010 using a 4-bit binary adder if D3D2D1D0 > 0100, i.e., when f = D3(D2 + D1D0). Feed 2-4-2-1 as one 4-bit input and f-0-f-0 as the other 4-bit input. (b) Feed XS3 as one 4-bit input and 1100 as the other 4-bit input. (c) Feed 8-4-2-1 as one 4-bit input and 0011 as the other 4-bit input. (d) Feed 1100 as one 4-bit input and XS6 as the other 4-bit input. (e) Feed 0011 as one 4-bit input and BCD number as the other 4-bit input.

6.13. Use combinational logic design principles to come up with SOP equations from the truth table.

6.17. P1 P2 M1 P3 M2 M3 M4 P4 M5 M6 M7 M8 M9 1 0 0 1 1 1 1 0 0 1 0 1 1 Test bits are: T1 T2 T3 T2

= (P1 XOR M1 XOR M2 XOR M4 XOR M5 XOR M7 XOR M9)’ = (1 XOR 0 XOR 1 XOR 1 XOR 0 XOR 0 XOR 1)’ = 1 = (P2 XOR M1 XOR M3 XOR M4 XOR M6 XOR M7)’ = (0 XOR 0 XOR 1 XOR 1 XOR 1 XOR 0)’ = 0 = (P3 XOR M2 XOR M3 XOR M4 XOR M5 XOR M9)’ = (1 XOR 1 XOR 1 XOR 1 XOR 0 XOR 1)’ = 0 = (P4 XOR M5 XOR M6 XOR M7 XOR M8 XOR M9)’ = (0 XOR 0 XOR 1 XOR 0 XOR 1 XOR 1 XOR 1)’ = 1

T4 T3 T2 T1 = 1001  Error is in the 9th bit. Correction circuit: D1 = M1 XOR (T4’ T3’ T2 T1) D2 = M2 XOR (T4’ T3 T2’ T1’) D3 = M3 XOR (T4’ T3 T2 T1’) D4 = M4 XOR (T4’ T3 T2 T1) D5 = M5 XOR (T4 T3’ T2’ T1) D6 = M6 XOR (T4 T3’ T2 T1’) D7 = M7 XOR (T4 T3’ T2 T1) D8 = M8 XOR (T4 T3 T2’ T1’) D9 = M9 XOR (T4 T3 T2’ T1’)

6.19 F = AB’C’D’ + A’BC’D’ + A’B’CD’ + A’B’C’D

6.21a-b. Ci = Sum m(3,5,6,7) Si = Sum m(1,2,4,7) Feed D3, D5, D6 and D7 into a 4-input NAND and D1, D2, D4, and D7 to another 4input NAND to generate respectively Ci and Si. Di = Sum m(1,2,4,7) Bi = Sum m(1,2,3,7)

Feed D1, D2, D4 and D7 into a 4-input NAND and D1, D2, D3, and D7 to another 4input NAND to generate respectively Di and Bi.

6.23. The result of a1a0 plus b1b0 can be determined by adding (i) a0 and b0 and (ii) adding a1, b1 and carry-out of (i). This will require a half adder for (i) and a full adder for (ii).

6.26. 4-bit FA using ROM would require a size of (2 EXP 9) x 5 = 2560 bits. Accordingly, truth table corresponding to it would have 9 inputs and 5 outputs.

6.29. Xi 0 0 0 0 1 1 1 1

Yi 0 0 1 1 0 0 1 1

Bi-1 0 1 0 1 0 1 0 1

Bi 0 1 1 1 0 0 0 1

Di 0 1 1 0 1 0 0 1

Di = Xi XOR Yi XOR Bi-1 Bi = Sum m(1,2,3,7) = Xi’Yi + Bi(Xi XOR Yi)’ using bridging.

6.31a D0 D1 D2  C01 S01 D3 D4 D5  C02 S02 D6 D7 D8  C03 S03 D9 D10 D11  C04 S04 S01 S02 S03  C05 S05 C01 C02 C03  C06 S06 S04 S05 0  C07 S0 C04 S06 C05  C08 S08

0 S08 C07  C09 S1 C06 C08 C09  S3 S2 6.31b Follow same steps as in 6.31a above.

6.33. Di = Sum m(1,2,4,7) Bi = Sum m(1,2,3,7)

Di’ = Sum m(0,3,5,6) Bi’ = Sum m(0,4,5,6)

Therefore, Di

= (Sum m(0,3,5,6))’ = (A’B’C’ + A’BC + AB’C + ABC’)’ = ((A+B+C)’ + (A+B’+C’)’ + (A’+B+C’)’ + (A’+B’+C)’)’

Bi

= ((A+B+C)’ + (A’ + B + C)’ + (A’ + B + C’)’ + (A’+B’+C)’)’

Connect the 4 1-bit FS in ripple fashipn so that borrow-out of one is entered as borro-in of the next FS.

6.35. Feed minuend and complement of subtrahend to a CLA(n).

6.37 ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

EFGH 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100

IJKL 0000 0101 0000 0101 0000 0101 0000 0101 0000 0101

By inspection: E=0 F=A G=B H=C I=0 J=D K=0 L=D

6.41 Use a 1-of-4 MUX and appropriate logic gates to realize (a) and (c). For (b), a 1-of-2 MUX is enough.

6.43 HC A0 0 0 1 1

FC B0 0 1 0 1

G0 0 0 1 0

L0 0 1 0 0

Ai 0 0 1 1

Bi 0 1 0 1

Gi Gi-1 0 1 Gi-1

Li Li-1 1 0 Li-1

We can use combinational circuit to design these 2-input 2-output circuits and they can be cascaded to generate n-bit comparator. For comparison of multi-bit numbers, this circuit is slow in operation since the L’s and G’s would have to ripple down through several stages. An improved circuit for 4-bit inputs, for example, would be as follows. A > B can be determined from: A3B3’ + A2B2’(A3 XOR B3)’ + A1’B1(A3 XOR B3)’(A2 XOR B2)’ + A0’B0’(A3 XOR B3)’(A2 XOR B2)’(A1 XOR B1)’ A = B can be determined from: (A3 XOR B3)’(A2 XOR B2)’(A1 XOR B1)’(A0 XOR B0)’ A < B can be determined from: A3’B3 + A2’B2(A3 XOR B3)’ + A1’B1(A3 XOR B3)’(A2 XOR B2)’ + A0’B0(A3 XOR B3)’(A2 XOR B2)’(A1 XOR B1)’

6.45. Follow Example 6.20 (page 282).

6.47. Follow example shown in Figure 4.36 to design 8-bit barrel left rotator.

7.1. J1 = Q2 XOR x K1 = 1 J2 = Q1 K2 = Q1’ X=0 J1K1 01 11 01 11

Q1Q2 00 01 10 11

X=1 J2K2 J1K1 01 11 01 01 10 11 10 01

X=0 Q1Q2 00 10 01 01

J2K2 01 01 10 10

X=1 Q1Q2 10 00 01 01

Timing diagram follows.

7.3. J = (XQ’)’ = X’ + Q K = (X’Q)’ = X + Q’ Z = ((XQ’)’(X’Q)’(X’Q)’)’ = XQ’ + X’Q = X XOR Q

Q(0) 0 1

JK X=0 11 10

X=1 01 11

Q(t) X=0 1 1

(a) X Q Z

Z(t) X=0 0 1

X=1 0 0

(b) = 10011011000 = 01100100111 = 11111111111

X Q Z

= 10110111001 = 01001000110 = 11111111111

S2R2 A=0 10 -0 10 -0

A=1 001 10 -0

7.5a

Q1Q2 00 01 10 11

X=1 1 0

Q1(t)Q2(t) A=0 A=1 01 00 11 10 01 11 11 11

S1R1 A=0 010 01 -0

A=1 010 -0 -0

S1 = Q1’Q2 R1 = Q1Q2’A’ S2 = Q1 + A R2 = Q1’A

7.5c D1(t) = AQ1(t) + Q2(t) D2(t) = A’Q2(t) + Q1(t)

7.7. As long as T is 0, Q remains unchanged; but the moment T=1, Q changes its state.

7.9. (This problem refers to Figure 7.P4) (a) I1 0 0 1 1

I2 0 1 0 1

SR 00 00 10 01

No change No change Set Reset

When I1 = 0, no change. With I1=1, it sets when I2 = 0 and resets when I2 = 1. (b) T = (A + Q)B. Unclocked T-FF gets changed to a D-FF. (c) D = A’Q + BQ’. It sets when (i) AB=01 (ii) AB=00 and Q=1; and (iii) AB=11 and Q=0. (e) D = AQ’ + B’Q (g) T = AQ’ + BQ It toggles when (i) AB=11; (ii) AB=10 and Q=0; and (iii) AB=01 and Q=1.

8.1. PS NS,Z A B,0 C,1 B D,1 A,1 C A,0 D,0 D C,1 B,1 _______________ A0 B,0 C,1 A1 B,0 C,1 B D,1 A1,1 C A0,0 D,0 D C,1 B,1 _______________ A0 B0,0 C,1 A1 B0,0 C,1 B0 D1,1 A1,1 B1 D1,1 A1,1 C A0,0 D0,0 D0 C,1 B1,1 D1 C,1 B1,1 PS A0 A1 B0 B1 C D0 D1

NS B0 B0 D1 D1 A0 C C

C C A1 A1 D0 B1 B1

Z 0 1 0 1 1 0 1

8.3. (ABEF)(CD) (AB)(EF)(CD) (A)(B)(EF)(CD) (A)(B)(E)(F)(C)(D) Number of states can not be reduced any further. When we repeat with implication method of Figure 8.22, we’ll come to the same conclusion.

8.5. (A,D,E)(B,C) and 3 inputs (I1, I2, and I3) PS A B

I1 A,1 A,0

I2 B,0 A,0

000 001 010 011 100 101 110 111

-11 101 011 110 -11 010 111 001

I3 A,1 B,1

8.9. | | | | | | | |

D1 = Q1Q3’ + Q3Q1’ = Q1 XOR Q3 D2 = Q3’ + Q1 XOR Q2 D3 = Q3’ + (Q1 XOR Q2)’ 000  011  110 100  111  001 Unused states cycle out in one clock.

8.11. PS A B C D

00 01 11 10

D1D2 11,0 11,0 00,0 01,1

01,0 10,0 10,0 00,1

D1 = Q1’X’ + Q2X D2 = Q1’X’ + Q2’X’ + Q1’Q2’ Z = Q1Q2’

8.13. PS A B C D

00 01 11 10

NS,Z 11,0 11,0 00,0 01,1

01,0 10,0 10,0 00,1

U’ 111 000 001 010 011 100 101 110

U 001 010 011 100 101 110 111 000

J1K1 11-1 -1

01-0 -1

J2K2 1-0 -1 1-

1-1 -1 0-

J1 = X’ + Q2 K1 = X’ + Q2’ J2 = X’ + Q1’ K2 = X + Q1

8.19. |Q1Q2Q3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 D1 D2 D3

= Q3’ = Q2Q3U’ + Q3’Q2U + Q1’Q2’Q3’U’ + Q1’Q2’Q3U + Q1Q2’Q3’U’ +Q1Q2’Q3U = Q3’

8.21. PS A B C D E F

NS X=0 A C D A F,1 A

NS X=1 B B B E B B

Follow using 3 D-FFs since there are more than 4 states.

8.23. Repeat 8.21 but using 3 JK FFs.

9.1 Q1Q2Q3 000 001 010 011 100 101 110 111

D1 0 0 0 0 0 1 1 1

D2 0 1 0 0 1 1 0 0

D3 1 0 1 0 1 0 1 0

Q1(t)Q2(t)Q3(t) 001 010 001 000 011 110 101 100

State diagram follows.

9.3. When modulo-4 completes one cycle (00, 01, 10, 11), modulo-3 will go up by one count, and so on.

9.5. (a) Use circuit of Figure 9.16(a), page 399. (b) Use circuit of Figure 9.16(b), page 399. Feed SRO from LSB to SRI at MSB.

9.7. Circuit of Figure 9.17 can be modified, where each of D-FFs can be changed to JK FF with a NOT gate placed between J and K inputs of the LSB. K3 = Q2’, K2 = Q1’ and K1 = Q0’.

9.9. A 4-bit counter can be used to sequence 16 different operations by feeding its input to a 4-16 line decoder.

9.11. i-th bit feeds into a 1-of-4 MUX whose inputs are: D0 = Ai D1 = Qi’ D2 = (Q0 + …+Qi-1) XOR Qi D3 = (Q0….Qi-1) XOR Qi

9.13. Take a 4-bit counter whose four outputs are used to generate X9 = QAQB’QC’QD. X9 is used to CLR the counter.

9.15. Feed X2-X1-X0-0 and 0-0-X2-X1 as inputs to the 4-bit FA and X0 as its carry in, then the product is obtained as 5-bit sum C0-S3-S2-S1-S0.

9.17. J1 = K1 = C + Q2 J2 = K2 = C’

9.18. Feed the input to two 4-bit counters designated as divide-by-3 and divide-by-13 counters. Take the two outputs of these two counters to the input of a 2-input AND. The AND output is the divide-by-39 output.

9.19.

PS S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15

NS 0 S0 S2 S4 S6 S8 S10 S12 S14 S0 S2 S4 S6 S8 S10 S12 S14

1 S1 S3 S5 S7 S9 S11 S13 S15 S1 S3 S5 S7 S9 S11 S13 S15

10.1. Circuit of Figure 10.1 (page 424) can be used for this purpose. E is set for subtracting magnitude of B from that of A.

10.3. To terminate the operation at S=2, the first test in the RTL algorithm is modified as follows: IF ((N = n -1) AND (X0(Y0 XOR E)CBFF0 + X0’(Y0 XOR E)’CBFF0 = 1)) THEN S  3;

10.6. (a) Five 1-of-2 MUX each feeding into D input of separate D-FF. A total of 5 D-FFs are needed as shown below.

(b) A simple up-counter can be used. The output T should be made high as soon as the count exceeds n-2. (c) The CCC equations are used to generate the combinational circuit.

10.7. The unused counter states could be decoded to produce an output U. Then K = T + U may be used to turn off the event FF.

10.8. When a binary counter is used in place of a ring counter, additional combinational circuit would be necessary to generate equivalent sequencer outputs. A 2-bit up-counter would be enough to provide for four sequences, T’ is loaded asynchronously to return the counter to state S=2.

11.1a.

A B C D E F G

X1 B C D E,1 B D E,1

X2 A F D E,1 A G B

Put A = 001, B = 001, C = 011, D = 010, E = 110, F = 111 and G = 101 and use 3 SR FFs. S1 = X1(Q1’Q2Q3’) + X2[Q1’(Q2 XOR Q3) + Q1Q3] R1 = X1Q1Q2 + X2[Q1(Q2 XNR Q3) + Q1(Q2 XOR Q3)] Z = Q1’Q2Q3’(X1 + X2) + X1(Q1Q2’) In the same manner, extract equations for S2, R2, S3 and R3.

11.1c. PS A B C D E F G H

X1 B C A E A B F,1 D

X2 H D E G F,1 A A H

Now repeat steps as in 11.1a above.

11.3 PS A B C D E

X1 B B D,1 B B

X2 A C A A C

which reduces to: PS A B C E

X1 B B A,1 B

X2 A C A C

PS 00 01 11 10

X1 01 01 00,1 01

X2 00 11 00 11

Q1Q2 T1 X1 00 0 01 0 11 1 10 1

T1 X2 0 1 1 0

T2 X1 1 0 1 1

T2 X2 0 0 1 1

Z X1 0 0 1 0

Z X2 0 0 0 0

T1 = X1Q1 + X2Q1Q2 T2 = X1(Q1’Q2’ + Q1) + X2(Q1) = X1(Q2’ + Q1) + X2Q1 Z = X1Q1Q2

11.5. PS P Q R S

A Q P P S,z

B P R P P

A X2 X3 X4 X4 X2 X2

B X1 X1 X1 X5 X6,z X1

11.7a. PS X1 X2 X3 X4 X5 X6

C P P S,z S,z

11.9. Q1Q2 11 00 01 10

x=0 “11” “00” 01-

x=1 -1 -0 “01” “10”

z 1 1 0 1

S1R1 Q1Q2 x=0 00 001 011 -0 10 -0

S1R1 x=1 -0--0

S2R2 x=0 0--0 --

S1 = Q1

R1=Q1’

S2= Q2

R2=Q2’

AB 01 “00” “11” 0-0

AB 11 01“01” “10”

AB 10 01“01” “10”

Q1Q2 00 11 01 10

AB 00 1 0 0

AB 01 0 1 0

AB 11 1 0 1 0

AB 10 1 1 1 1

AB 01 00 011 -0

AB 11 001 110

AB 10 001 110

AB Q1Q2 00 00 1 01 11 0 10 0

AB 01 0 1 0

AB 11 1 1 0 0

AB 10 1 1 1 1

S2R2 x=1 0-0 -0 0-

Q1Q2 00 01 11 10

x=0 00 011 1-

z x=0 1 0 0 1

z x=1 1 0 0 1

x=1 -0 01 -1 10

z 1 0 0 1

z = Q2’

11.11.

Q1Q2 00 01 11 10

AB 00 “00” “11” -1 1-

AB Q1Q2 00 00 00 01 -1 11 11 10 1-

11.13. X1X2 00 “1” 8 6 1 1 “8”

01 3 5 “3” “5” 3 3

11 “2” 7 7 2 2 “7” -

10 6 4 “4” “6” 4 4

z 0 0 1 1 0 0 1 1

“a” c “c”

b “b” “c”

c “b” “c”

“a” “b” a

a=00

b=01 c=11 and introduce a cycle state d=10

11.15a.

“a” c “c” -

b “b” “c” -

d “b” “c” c

“a” “b” d a

Q1Q2 00 01 11 10

X1X2 00 00 11 11 --

X1X2 01 01 01 11 --

X1X2 11 10 01 11 11

X1X2 10 00 01 10 00

11.15c. _____________________ “a” b c d a “b” “b” “b” a “c” “c” “c” a “d” “d” “d”

A possible assignment would then be a = 000, b=001, c=010 and d=100. Follow Example 11.7 (page 466) thereafter.

11.17a. Assuming “8” is actually “3”, 1,4  a 5b 2,3  c 6,7  d We can introduce a cycle state (i) c’ between a and d’ and (ii) d’ between b and c. Q3 0 1

Q1Q2 Q1Q2 Q1Q2 00 01 11 a d’ c’ b

Q1Q2 10 c d

Rest follows as in Example 11.7 (page 466).

11.17b. Q3 0 1

Q1Q2 00 a a

Q1Q2 01 b c

Q1Q2 11 b c

Q1Q2 10 d d

Rest follows as in Example 11.7 (page 466).

12. Begin with a Note: As with most engineering problems in practice, a solution to a problem often relies on what assumptions and trade-offs are considered and taken. Hence the solutions suggested below are far from to be the only answers to the exercises. By design, the exercises are not specified to every bit of details in order to encourage discussions among students and instructors. Due to the page limitations only the very essential basic information (even this is debatable) are discussed in this chapter. Hence, students and instructors will need to find relevant information in the reference books to complete some of the exercises. Further more, students and instructors are encouraged to explore different solutions so long as the assumptions make sense and are justified. The suggested solutions described below are merely serving as examples. Corrections Table 12.1. Observability Back Propagation Rules LOGIC FUNCTION XOR/XNOR

Backward Propagation/Calculation of Observability at An Input Sum of the output observability and the minimum of 1controllability and 0-controllability of the other input

Table 12.2. Random Controllability Propagation Rules LOGIC FUNCTION XNOR

Propagation/Calculation of Controllability at Output 1-Controllability 0-Controllability 1 minus 0-controllability C1(a ) × C 0(b) + C 0(a ) × C1(b)

12.1 Let F = a ⊕ b ⊕ c , then: a b

1/1/3 1/1/3

c 1/1/3

2/2/2 3/3/1 F

12.2

a b c

0.5/0.5/1

0.25/0.75/1 0.25/0.75/1 F

0.5/0.5/1 0.5/0.5/1

12.3 The order of the input test sequence is x11xxx. The failure data can be observed at the output after the fifth and sixth pulses, respectively.

12.4 The objective is to use the least number of input patterns to test the most of the stuck-at faults in the circuit. The optimal number can be different based the gate-level circuit implementations. An economically-optimal test set often means that it uses the least number of input patterns. Use the same approach as demonstrated in the solution (below) for P12.5 to derive a test set.

12.5 First, develop the AND-OR implementation of XOR and label each distinct wire branch as follows: F = a ⊕ b = a ⋅b + a ⋅b c

a

e

i

f F g b d

h

j

Then, develop the following table with all individual stuck-at faults and check-mark the detection of faults by respective inputs:

Inputs

Stuck-at faults f g a b 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 √ √ √ √ 0 1 √ √ √ √ √ 1 0 √ √ √ √ 1 1 √ √ √ √ √ A √ symbol marks the fault being detected by the associated input. a

b

c

d

e

h 0 √

i 1

0 √

√

j 1 √ √

0 √

F 1 √ √

0 √ √

1 √ √

Finally, examine the rows and columns in the table carefully. An input can be removed from a test set if all of its check-marked columns have multiple checks. An input cannot be removed if at least one of its check-marked columns has only one check. In this case, all four test inputs are required in order to detect all single stuck-at faults. In terms of equivalency, faults are equivalent if they can be detected by the same set of inputs. For example, stuck-at faults F_1, j_1 and i_1 are equivalent since they can be detected by the same test inputs. Similarly, stuck-at faults a_1 and g_1 are equivalent, so are c_1, e_0, f_0 and i_0. Note that the same process can be used for other gate-level implementations of XOR

12.6 The analysis can be derived based on the solution for P12.4 with the same method as demonstrated in the solution to P12.5.

12.7 For XOR, a pseudo-code section for calculating the output’s controllability is as follows:

int net_1[n-1], net_0[n-1]; net_1[0] = ctl_1(input_1), net_0[0] = ctl_0(input_1); for(int input_i=2; input_ictl0 = 1; break; case PO: case BUF: gate[g]->ctl1 = gate[gate[g]->inputs[1]]->ctl1; gate[g]->ctl0 = gate[gate[g]->inputs[1]]->ctl0; break; case AND: gate[g]->ctl1 = gate[gate[g]->inputs[g]]->ctl1; gate[g]->ctl0 = gate[gate[g]->inputs[g]]->ctl0; for(int j=2; jnum_ins; j++) { gate[g]->ctl1 += gate[gate[g]->inputs[j]]->ctl1; gate[g]->ctl0 = min(gate[g]->ctl0, gate[gate[g]->inputs[j]]->ctl0); } break;

case NAND: gate[g]->ctl1 = gate[gate[g]->inputs[1]]->ctl0; gate[g]->ctl0 = gate[gate[g]->inputs[1]]->ctl1; for(int j=2; jnum_ins; j++) { gate[g]->ctl0 += gate[gate[g]->inputs[j]]->ctl1; gate[g]->ctl1 = min(gate[g]->ctl1, gate[gate[g]->inputs[j]]->ctl0); } break; case OR: gate[g]->ctl1 = gate[gate[g]->inputs[1]]->ctl1; gate[g]->ctl0 = gate[gate[g]->inputs[1]]->ctl0; for(int j=2; jnum_ins; j++) { gate[g]->ctl0 += gate[gate[g]->inputs[j]]->ctl0; gate[g]->ctl1 = min(gate[g]->ctl1, gate[gate[g]->inputs[j]]->ctl1); } break; case NOR: gate[g]->ctl1 = gate[gate[g]->inputs[1]]->ctl0; gate[g]->ctl0 = gate[gate[g]->inputs[1]]->ctl1; for(int j=2; jnum_ins; j++) { gate[g]->ctl1 += gate[gate[g]->inputs[j]]->ctl0; gate[g]->ctl0 = min(gate[g]->ctl0, gate[gate[g]->inputs[j]]->ctl1); } break; case INV: gate[g].ctl1 = gate[gate[g].inputs[1]]->ctl0; gate[g].ctl0 = gate[gate[g].inputs[1]]->ctl1; break; case XOR: /** plug in a section similar to the solution for P12.7 **/ break; case XNOR: /** plug in a section similar to the solution for P12.7 **/ break; other: /** exit the procedure with error as an undefined gate type is encounted **/ exit(ERROR_UNDEFINED_GATE_TYPE); } } /** calculating observability mesures **/ for(int i=1; iobs = 1; break; all else: gate[g]->obs = INFINITY; int in_ctl, out_obs, in_g; for(int j=1; j num_outs; j++) { int og = gate[j]->outputs[j]; switch(function_type(og)) { case AND: case NAND: out_obs = gate[og]->obs; for(int k=1; k num_ins; k++) { in_g = gate[og]->inputs[k]; if(in_g != g) out_obs += gate[in_g]->ctl1; } break; case OR: case NOR: out_obs = gate[og]->obs; for(int k=1; k num_ins; k++) { in_g = gate[og]->inputs[k]; if(in_g != g) out_obs += gate[in_g]->ctl0; } break; case BUF: case INV: out_obs = gate[og]->obs; break; all else: /** exit with error of undefined function type **/ exit(ERROR_UNDEFINED_GATE_TYPE); } gate[g]->obs = min(gate[g]->obs, out_obs); } } }

12.14 The procedures are similar to the ones in the solution to P12.13.

12.15 In the following figure 1/0 marks where a stuck-at-0 fault may be present based on the described failure data. A B

1/0

0/-

Sum

1/1

1/0 1/0

0/-

1/0

0/0

1/0

1/0

1/-

Cout

Cin

12.16 In the following figure 1/0 marks where a stuck-at-0 fault may be present based on the described failure data. A B

1/-

1/0-1

0/0/-

1/1-0

1/-

1/0-1 0/1

1/0-1 1/0

0/0 1/1-0

Cin

1/1-0

Sum

1/0 Cout

Based on the two failure data, the following faults are potentially present in the circuit implementation: stuck-at-1 on signal Sum, stuck-at-0 on signal Cout, stuck-at-0 on either of the inputs of the OR gate, stuck-at faults on either of the inputs of the XOR gate of Sum, … Instructors and students are encouraged to conduct discussions on other stuck-at faults that are potentially present.

12.17 This is a general problem to deal with design-for-test issues in reconvergent circuit structures. Instructors are encouraged to give circuit examples of limited scope and illustrate the general principles of DFT.

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