Computational Electronic Circuits: Simulation and Analysis with MATLAB® [1st ed. 2022] 3030755673, 9783030755676

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Sotoudeh Hamedi-Hagh

Computational Electronic Circuits Simulation and Analysis with MATLAB®

Computational Electronic Circuits

Sotoudeh Hamedi-Hagh

Computational Electronic Circuits Simulation and Analysis with MATLAB®

Sotoudeh Hamedi-Hagh San Jose State University San Jose, CA, USA

ISBN 978-3-030-75567-6 ISBN 978-3-030-75568-3 https://doi.org/10.1007/978-3-030-75568-3

(eBook)

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

To my dearest family For their love and support

Preface

Writing a full-scale circuit simulator is a very intriguing and satisfying task, especially for students. In the process of writing a circuit simulator, students will better understand and learn the circuit theory and analysis. These are the motivations that prompt me to write this book. A circuit simulator has two main parts. The first part is the generation of a graphical user interface for drawing circuits and interconnects. This is called the schematic editor. The second part is translating the circuit into codes that can be mathematically computed. This is called the circuit analyzer. Both the graphical user interface and the computational engine are integrated into a compiler called the circuit simulator. The compiler is written using a computer programming language like C and includes an extensive library of different functions that users can execute, such as moving a circuit component to a new location and rotating it or creating netlist from the circuit and performing a specific simulation followed by calculating some characteristics, such as the time-domain average of a signal or the frequency-domain group delay of a voltage-gain transfer function. Writing a compiler using a programming language is not in the scope of this book. Instead, a versatile compiler such as MATLAB is used in this book in order to show the generation of a circuit graphical user interface, translating the circuit into codes that can be computationally calculated as well as creating a library of circuit analysis functions. The generation of the graphical user interface and translating circuits into netlists are demonstrated at the end of Chap. 1 after circuit components and their characteristics are studied. Although the generation of a graphical user interface is very fun and helpful for creating a circuit simulator, it is not essential in learning circuit theories and analyses. As a result, this first part of the circuit simulator is only studied in Chap. 1. The main emphasize in the remaining chapters is to show how to create computational codes required by the second part of the circuit simulator in order to analyze circuits and extract their characteristics. The universal adaptability of computational codes is considered throughout his book. As an example, instead of asking students to hand calculate the voltage-gain transfer functions of different filters before plotting them using MATLAB, the voltage-gain transfer functions for circuits with different number of nodes and vii

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configurations are automatically calculated using Cramer’s rules and Laplace expansions applied to admittance matrices. As a result, the codes and the methods adopted in this book can be used in a universal circuit simulator rather than a specific-task simulation. Utilizing custom simulation functions such as calculating fast Fourier transform and numerical analysis of systems of equations are also used throughout this book instead of relying on pre-existing MATLAB functions, such as FFT or solve commands. Most of the computational books in engineering topics use extensive amounts of math that can easily force a reader to lose the comprehension and the interest in the topic. While an extensive amount of simulation methods is covered in this book, the amount of math is kept at a minimum level. Circuit analysis can be done using nodal currents, mesh voltages, or both. Each method if applied properly can analyze any kind of circuits. The nodal analysis based on Kirchhoff’s current law is used throughout this book to analyze circuits. The signal notations used in this book include presenting the instantaneous voltage and current signals by “VTR” and “ITR” (capital letter followed by capital subscript), the DC components of the signals by “vDC” and “iDC” (lowercase letter followed by capital subscript), and presenting the AC components of the signals by “vac” and “iac” (lowercase italic letter followed by lowercase subscript). In the absence of AC signals in DC analysis, the DC and instantaneous signals become equal and the DC voltages and currents might optionally be shown with the instantaneous signal notation. Circuit analysis is done using two distinct numerical and symbolic approaches. Both methods are covered in this book. The numerical approach generates a component-obscure result after each simulation but is very computer-memory efficient because when multiple numbers are added, subtracted, multiplied, or divided together, the result will be just a number. The symbolic approach generates a component-visible result that shows how the circuit characteristic changes by varying each component but is very computer-memory inefficient because as different symbolic variables are added, subtracted, multiplied, or divided together, the mathematical expressions expand in size. For small circuits or simple building blocks that are studied in electronic courses, the symbolic analysis is advantageous in teaching students how the circuits work. For large circuits, full symbolic analysis becomes impractical and the numerical analysis becomes the only practical choice in creating circuit simulators. The modeling and characteristics of circuit components and creating circuits and netlists are studied in Chap. 1. The DC analysis of linear and nonlinear circuits is studied in Chap. 2. The calculation of inverse matrix, Laplace expansion, LU decomposition, Gaussian elimination, and iterative methods such as conjugate gradient, Gauss-Seidel, and Newton-Raphson are demonstrated in this chapter. The transient analysis of linear and nonlinear circuits is studied in Chap. 3. The calculation of finite difference and finite integrals, Laplace transforms, partial fraction decomposition, and fast Fourier transform are demonstrated in this chapter. The AC analysis of linearized circuits is studied in Chap. 4. The Cramer’s rules and Laplace expansion, Taylor series expansion, node elimination, extraction of admittance matrix and transfer functions, power gains, Y-, Z-, and S-parameters and their

Preface

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conversions, poles and zeros, impulse and step responses, Bode, Nyquist and Nichols plots, root locus and Smith charts are demonstrated in this chapter. The noise analysis of linearized circuits is studied in Chap. 5. The transient and spectral noise characteristics, noise matrices, noise transformation, input and output referred noise calculations, noise factors, and noise and power tradeoff are demonstrated in this chapter. Finally, the behavioral analysis of circuits where specific-task modeling and algorithms are applied to different circuits in order to study their functionality is studied in Chap. 6. An overview of chapter topics is listed in the following table. Schematic Composing

Signals Ch. 1 Framework Components

Ch. 2

Ch. 3

DC Analysis

Transient Analysis

Netlisting

DC, Transient, AC and Noise modeling

Linear Equations

Direct Methods

Nonlinear Equations

Iterative Methods

DC Circuit Model

Linear Circuits

Aperiodic and Periodic Signals

Laplace Transform

Nonlinear Circuits

Switching Circuits

Differential Equations

Ch. 4

AC Analysis

Linearized s-domain Model

Matrix Calculations

Ch. 5

Noise Analysis

Linearized s-domain Model

Noise Matrix Calculations

Ch. 6

Behavioral Analysis

Block-Level Modeling

Transfer Function Characteristics

Noise Transformation

Accuracy and Speed Tradeoff

In contrary to the current computational methods for some engineering fields such as electromagnetics and antenna where different methods and approaches are required for simulating different open boundary or closed boundary systems, the circuit analysis is very well structured and developed. For example, a single transient analysis can solve any type of linear or nonlinear circuits with any type of components with any number of nodes and meshes with any number and types of signal sources. A simulation algorithm works for all types of circuits. All fundamental knowledge and skills required for students in order to develop their own circuit simulator are included in this book with the hope to make circuit and electronic courses very enjoyable and memorable for all. San Jose, CA, USA

Sotoudeh Hamedi-Hagh

Contents

1

Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Numeric and Symbolic Analyses . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Finite Integral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Finite Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Laplace Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Basic Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Multiplication and Convolution . . . . . . . . . . . . . . . . . . . 1.4.3 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 Differentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.6 Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.7 Multiplication by Time . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.8 Conjugate Property . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.9 Initial and Final Values . . . . . . . . . . . . . . . . . . . . . . . . 1.4.10 Periodicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3 Open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.4 Ideal Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.5 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.6 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.7 Nonideal Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.8 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.9 Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.10 Nonideal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.11 Dependent Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.12 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 2 2 5 6 7 8 8 9 9 9 10 10 10 10 11 17 17 17 17 17 18 21 24 24 28 29 30 31

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1.6.13 Bipolar Junction Transistors . . . . . . . . . . . . . . . . . . . . 1.6.14 Metal Oxide Semiconductor Field Effect Transistors . . 1.7 LTI/LTV/NTI/NTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Schematic Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1 Netlisting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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37 44 53 54 55 60 60 60 62 62 63 64 64 65 66 67 68

2

DC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Analysis Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Inverse Matrix Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Determinant Ratios Obtained by Laplace Expansion . . . . . . . . . 2.4 Determinant Ratios Obtained by LU Decomposition . . . . . . . . . 2.5 Gaussian Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Conjugate Gradient Iterations . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Gauss-Seidel Iterative Method . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Newton-Raphson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.2.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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71 72 75 81 86 91 96 102 105 109 109 109 111 112 113 114 115 116 118

3

Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Partial Fraction Decomposition . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Aperiodic Capacitive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Aperiodic Inductive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Periodic Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Periodic Capacitive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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119 121 122 126 130 131 131

Contents

3.5.2 Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Periodic Inductive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Circuits with Both Capacitors and Inductors . . . . . . . . . . . . . . . 3.7.1 Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 Circuit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Causality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 Circuit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Spectral Decomposition Using Fourier Series . . . . . . . . . . . . . . 3.9.1 Fast Fourier Transformation . . . . . . . . . . . . . . . . . . . . 3.10 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

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135 138 140 140 145 147 150 150 154 157 160 163 164 168 171 176 182 183 186 187 187 188 189 190 191 192

AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Admittance Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Cramer’s Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Laplace Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Applying Voltage or Current Sources to a Circuit . . . . . . . . . . . . 4.5 Circuits with Multiple Input Sources . . . . . . . . . . . . . . . . . . . . . 4.6 Shorting a Circuit Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Fundamental Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.3 Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.4 Example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Taylor Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Transistor Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Node Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.1 Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Y-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Signal Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

195 196 198 199 200 202 203 204 207 211 215 221 226 229 232 233 236 237

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Contents

4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23

Primary Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circular-Shaped Power Dividers . . . . . . . . . . . . . . . . . . . . . . . Star-Shaped Power Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . Power Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Admittance Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impedance S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.1 Poles and Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.2 Impulse Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.3 Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.4 Bode Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.5 Root Locus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.6 Nyquist Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.7 Nichols Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23.8 Smith Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 Piezoelectric Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 Shunt Harmonic Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 Sequential Harmonic Passes . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 Shunt Harmonic Passes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 Single-Stage Poly Phase Filters . . . . . . . . . . . . . . . . . . . . . . . . 4.29 Low Pass Couplers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 Substrate Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 Substrate Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 Model Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.33 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.4.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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239 241 242 246 250 254 256 259 261 264 268 269 271 271 272 273 273 274 275 276 281 285 288 292 299 307 314 322 326 327 327 327 328 329 330 331 332 333 334

Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Signal Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Transient Noise Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Spectral Noise Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Simple Noise Transformations . . . . . . . . . . . . . . . . . . . . . . . . .

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337 338 338 342 343

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5.4.1 Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Noise Analysis Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Noise Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Two-Node Resistive Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 External Noise Transformations . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 From Output Voltage to Input Voltage . . . . . . . . . . . . . 5.8.2 From Output Voltage to Input Current . . . . . . . . . . . . . . 5.8.3 From Output Current to Input Voltage . . . . . . . . . . . . . . 5.8.4 From Output Current to Input Current . . . . . . . . . . . . . . 5.8.5 Between Input Current and Input Voltage . . . . . . . . . . . 5.8.6 From Input Voltage to Output Voltage . . . . . . . . . . . . . 5.8.7 From Input Voltage to Output Current . . . . . . . . . . . . . . 5.8.8 From Input Current to Output Voltage . . . . . . . . . . . . . . 5.8.9 From Input Current to Output Current . . . . . . . . . . . . . . 5.8.10 Between Output Current and Output Voltage . . . . . . . . . 5.9 Total Referred Noises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Input Referred Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Variations of the Noise Factors . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Noise Factor and Maximum Power Trade-Offs . . . . . . . . . . . . . . 5.12.1 Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.2 Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.3 Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.5.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.5.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q.5.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

344 344 345 346 348 350 350 351 352 353 354 356 357 358 359 360 361 362 364 366 366 368 372 381 382 382 383 384 385 386 387 388

Behavioral Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Block-Level Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Opamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Inverting Hysteresis Circuit . . . . . . . . . . . . . . . . . . . . . 6.2.2 Noninverting Hysteresis Circuit . . . . . . . . . . . . . . . . . . 6.2.3 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Diode Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Full-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

391 392 397 397 400 403 405 406 408 411 414 414

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Q.6.1 . Q.6.2 . Q.6.3 . Q.6.4 . Q.6.5 . Q.6.6 . Q.6.7 . Q.6.8 .

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414 415 415 417 417 419 419 421

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

List of Figures

Fig. 1.1 Fig. 1.2

Fig. 1.3 Fig. 1.4 Fig. 1.5 Fig. 1.6 Fig. 1.7 Fig. 1.8 Fig. 1.9 Fig. 1.10 Fig. 1.11 Fig. 1.12 Fig. 1.13 Fig. 1.14 Fig. 1.15 Fig. 1.16 Fig. 1.17 Fig. 1.18 Fig. 1.19 Fig. 1.20 Fig. 1.21 Fig. 1.22 Fig. 1.23 Fig. 1.24 Fig. 1.25

Comparison of symbolic and numeric integral calculations, (a) 11 discrete points and (b) 51 discrete points . . . . . . . . . . . . . . Comparison of symbolic and numeric derivative calculations, (a) 11 discrete points and (b) 51 discrete points . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . The s-plane used in Laplace transformation . . . . . . . . . . . . . . . . . . . A Heaviside step waveform . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . A sinusoidal waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The absolute of the sinusoidal waveform . . . . . . . . . . . . . . . . . . . . . . A square waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A triangle waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Sawtooth waveform . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . .. . . . . . .. . . A backward Sawtooth waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A pulse waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground symbol . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . . .. . Voltage drop and current flow of a short . . . . . . . . . . . . . . . . . . . . . . Voltage drop and current flow of an open . . . . . . . . . . . . . . . . . . . . . Operating states of a switch, (a) Short and (b) Open . . . . . . . . . Transfer characteristics of an ideal switch . . . . . . . . . . . . . . . . . . . . . Physical resistor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics of resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistor symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Laplace transformation of a resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal noise of a resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical capacitor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electric fields of a capacitor, (a) Positive charges on top plate and (b) Negative charges on top plate . . . . . . . . . . . . . . . . . . . Capacitor symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Time-domain and (b and c) Laplace transformations of a capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

6 7 12 12 13 14 14 15 15 16 18 18 18 18 19 19 19 19 20 20 21 22 22 23

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Fig. 1.26

Fig. 1.27 Fig. 1.28 Fig. 1.29 Fig. 1.30 Fig. 1.31 Fig. 1.32 Fig. 1.33 Fig. 1.34

Fig. 1.35 Fig. 1.36 Fig. 1.37 Fig. 1.38 Fig. 1.39 Fig. 1.40 Fig. 1.41 Fig. 1.42 Fig. 1.43 Fig. 1.44 Fig. 1.45 Fig. 1.46 Fig. 1.47 Fig. 1.48 Fig. 1.49 Fig. 1.50 Fig. 1.51 Fig. 1.52 Fig. 1.53 Fig. 1.54 Fig. 1.55 Fig. 1.56 Fig. 1.57 Fig. 1.58 Fig. 1.59 Fig. 1.60 Fig. 1.61 Fig. 1.62

List of Figures

(a) Shorting high frequency signals by shunt capacitors and (b) Blocking low frequency signals by sequential capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model of a capacitor with leakage current . . . . . . . . . . . . . . . . . . . . . Modeling of nonideal switches, (a) Close position and (b) Open position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coil inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Solenoid inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Toroid inductor .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . Inductor symbol . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . .. . . . . (a) Time-domain and (b and c) Laplace transformations of an inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Shorting low frequency signals by shunt inductors and (b) Blocking high frequency signals by sequential inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model of an inductor with wire resistance . . . . . . . . . . . . . . . . . . . . . Spiral transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transformer symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transformer model . .. . .. . .. . .. . .. . .. . .. .. . .. . .. . .. . .. . .. . .. .. . .. . Modeling of the voltage source resistance . . . . . . . . . . . . . . . . . . . . . Modeling of the current source resistance . . . . . . . . . . . . . . . . . . . . . Voltage-controlled voltage source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current controlled current source . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . Current controlled voltage source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage-controlled current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A pn diode . .. . . . .. . . . .. . . . .. . . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . Depletion region of the diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode in reverse bias operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode in forward bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parasitic diode . . . . .. . . . . . .. . . . . . .. . . . . . . .. . . . . . .. . . . . . . .. . . . . . .. . . Diode layout view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristic of a diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode model in reverse bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode model in forward bias . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . Noise model of the diode in forward bias . . . . . . . . . . . . . . . . . . . . . Bipolar junction transistor cross section . . . . . . . . . . . . . . . . . . . . . . . The NPN BJT operation in forward active region . . . . . . . . . . . . NPN transistor symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics of NPN transistor . . . . . . . . . . . . . . . . . . . . . Small-signal model of NPN transistors in forward cutoff region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal model of NPN transistors in forward saturation region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23 23 24 25 25 26 26 27

27 27 28 28 29 30 30 31 31 31 31 32 32 32 33 33 34 34 35 35 35 36 37 37 38 39 39 40 41

List of Figures

Fig. 1.63 Fig. 1.64 Fig. 1.65 Fig. 1.66 Fig. 1.67 Fig. 1.68 Fig. 1.69 Fig. 1.70 Fig. 1.71 Fig. 1.72 Fig. 1.73 Fig. 1.74 Fig. 1.75 Fig. 1.76 Fig. 1.77 Fig. 1.78 Fig. 1.79 Fig. 1.80 Fig. 1.81 Fig. 1.82 Fig. 1.83 Fig. 1.84 Fig. 1.85 Fig. 1.86 Fig. 2.1 Fig. 2.2 Fig. 2.3 Fig. 2.4 Fig. 2.5 Fig. 2.6 Fig. 2.7 Fig. 2.8 Fig. 2.9 Fig. 2.10

xix

Small-signal model of NPN transistors in forward active region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NPN transistor layout view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise model of the NPN transistors in saturation region . . . . . Noise model of the NPN transistors in active region . . . . . . . . . The DC voltage polarity and the DC current flow of (a) NPN and (b) PNP transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal oxide semiconductor field effect transistor cross section . . .. .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. .. . .. .. . .. .. . Operation of NMOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NMOS transistor symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristic of the NMOS transistor .. . .. . .. .. . .. . .. NMOS transistor model in cutoff region . . .. . . . .. . . .. . . . .. . . .. . NMOS transistor model in triode region . . . . . . . . . . . . . . . . . . . . . . . NMOS transistor model in saturation region . . . . . . . . . . . . . . . . . . Capacitors of NMOS transistor in (a) Cutoff, (b) Triode, and (c) Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal oxide semiconductor field effect transistor layout view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise model of the NMOS transistor in triode region . . . . . . . . Noise model of the NMOS transistors in saturation region . . The DC voltage polarity and the DC current flow of (a) NMOS and (b) PMOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . IV curves for I DS ¼ 12 μn C ox WL ðV GS  V th Þ2 ð1 þ λn V DS Þ . . . . . IV curves for I DS ¼ 2 1 W 2 μn C ox L ðV GS  V th Þ ð1 þ λn ðV DS  ðV GS  V th ÞÞÞ . . . . . . . . . Design functions and symbol instances of a schematic editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of nodes and loops in the same circuit . . . . . . . . . . Transient analysis of an RLC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient analysis of a transistor amplifier . . . . . . . . . . . . . . . . . . . . An overview of this chapter topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit used for inverse matrix calculation . . . . . . . . . . . . . . . . . . . . DC model .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit analyzed by Cramer’s rules and Laplace expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Π-arrayed rearrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Replacement with Norton models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC model .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . .

41 42 43 43 44 44 45 46 46 48 48 48 49 49 50 51 51 52 52 55 56 57 58 61 75 76 76 76 77 77 82 82 82 82

xx

Fig. 2.11 Fig. 2.12 Fig. 2.13 Fig. 2.14 Fig. 2.15 Fig. 2.16 Fig. 2.17 Fig. 2.18 Fig. 2.19 Fig. 2.20 Fig. 2.21 Fig. 2.22 Fig. 2.23 Fig. 2.24 Fig. 2.25 Fig. 2.26 Fig. 2.27 Fig. 2.28 Fig. 2.29 Fig. 2.30 Fig. 2.31 Fig. 2.32 Fig. 2.33 Fig. 2.34 Fig. 2.35 Fig. 2.36 Fig. 2.37 Fig. 2.38 Fig. 2.39 Fig. 2.40 Fig. 2.41 Fig. 2.42 Fig. 2.43 Fig. 2.44 Fig. 2.45 Fig. 2.46 Fig. 2.47 Fig. 2.48 Fig. 2.49 Fig. 2.50 Fig. 2.51 Fig. 2.52 Fig. 2.53 Fig. 2.54

List of Figures

KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit analyzed by Cramer’s rules and LU decomposition . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . Π-arrayed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Final DC model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit analyzed by the Gaussian elimination . . . . . . . . . . . . . . . . . Π-arrayed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding zero series resistors to voltage sources . . .. . .. . .. . .. . .. Final DC model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Independent current sources connected to circuit nodes . . . . . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit analyzed by the conjugate gradient method . . . . . . . . . . . Π-arrayed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC model .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Practice circuit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Π-arrayed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC model .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . A common source amplifier .. . .. . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . DC model of the common source amplifier . . . . . . . . . . . . . . . . . . . An overview of this chapter topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 1 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . Circuit of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 2 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . Circuit of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 3 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . Circuit of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 4 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . Circuit of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 5 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . Circuit of Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 6 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . Circuit of Question 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 7 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . Circuit of Question 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Annotated Circuit of Question 8 . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . .

83 83 83 88 88 88 88 89 92 92 92 93 93 93 94 94 97 97 97 98 98 98 102 102 103 106 106 110 110 111 111 112 112 113 113 114 114 115 115 116 116 117 117 117

List of Figures

Fig. 3.1 Fig. 3.2 Fig. 3.3 Fig. 3.4 Fig. 3.5 Fig. 3.6 Fig. 3.7 Fig. 3.8 Fig. 3.9 Fig. 3.10 Fig. 3.11 Fig. 3.12 Fig. 3.13 Fig. 3.14 Fig. 3.15 Fig. 3.16 Fig. 3.17 Fig. 3.18 Fig. 3.19 Fig. 3.20 Fig. 3.21 Fig. 3.22 Fig. 3.23 Fig. 3.24 Fig. 3.25 Fig. 3.26 Fig. 3.27 Fig. 3.28 Fig. 3.29 Fig. 3.30 Fig. 3.31 Fig. 3.32 Fig. 3.33 Fig. 3.34 Fig. 3.35 Fig. 3.36 Fig. 3.37 Fig. 3.38 Fig. 3.39 Fig. 3.40 Fig. 3.41 Fig. 3.42 Fig. 3.43 Fig. 3.44 Fig. 3.45

xxi

RC circuit . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC circuit . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC circuit . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC circuit . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RLC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RLC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit before switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit after switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 3 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching RL circuit . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . Circuit before switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit after switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 3 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching RLC circuit . . . . . . . . . .. . . . . . . . .. . . . . . . . . .. . . . . . . . .. . . . . Circuit before switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit after switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 3 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching RLC circuit . . . . . . . . . .. . . . . . . . .. . . . . . . . . .. . . . . . . . .. . . . . Circuit before switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit after switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 3 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node 4 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

123 125 126 129 131 134 136 137 138 140 141 144 145 147 148 149 150 152 154 155 157 159 160 162 164 164 165 166 166 168 168 169 170 170 172 172 173 175 175 177 177 179 180 180 181

xxii

Fig. 3.46 Fig. 3.47 Fig. 3.48 Fig. 3.49 Fig. 3.50 Fig. 3.51 Fig. 3.52 Fig. 3.53 Fig. 3.54 Fig. 3.55 Fig. 3.56 Fig. 4.1 Fig. 4.2 Fig. 4.3 Fig. 4.4 Fig. 4.5 Fig. 4.6 Fig. 4.7 Fig. 4.8 Fig. 4.9 Fig. 4.10 Fig. 4.11 Fig. 4.12 Fig. 4.13 Fig. 4.14 Fig. 4.15 Fig. 4.16 Fig. 4.17 Fig. 4.18 Fig. 4.19 Fig. 4.20 Fig. 4.21 Fig. 4.22 Fig. 4.23 Fig. 4.24 Fig. 4.25 Fig. 4.26 Fig. 4.27 Fig. 4.28 Fig. 4.29

List of Figures

Decomposition of the periodic square waveform into frequency harmonics . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . .. . . .. . . .. . . .. . The sinusoidal components of the waveform . . . . . . . . . . . . . . . . . . The composite waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency components of the composite waveform . . . . . . . . . . Spectral characteristics of signal with noise, spurs, harmonic, and intermodulation distortions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . An overview of this chapter topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External connections of a general three-node circuit . . . . . . . . . A general three-node passive circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . Ohm’s law at node 1 of the three-node circuit . . . . . . . . . . . . . . . . Ohm’s law at node 2 of the three-node circuit . . . . . . . . . . . . . . . . Ohm’s law at node 3 of the three-node circuit . . . . . . . . . . . . . . . . Driving a circuit with (a) Voltage and (b) Current sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driving a circuit with (a) Voltage and (b) Current sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testbench for calculating TF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testbench for calculating TF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A three-node circuit .. . .. . . .. . . .. . .. . . .. . .. . . .. . . .. . .. . . .. . . .. . .. . Practice circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Π-arrayed circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Π-arrayed circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Elimination of redundant node . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . AC model .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Π-arrayed circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Elimination of redundant node . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . Final AC model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Π-arrayed circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

183 184 185 185 187 188 188 190 191 192 193 196 196 197 197 197 201 202 203 203 203 207 208 208 208 211 211 212 212 212 213 215 216 216 216 217 217 218 221 221

List of Figures

Fig. 4.30 Fig. 4.31 Fig. 4.33 Fig. 4.32 Fig. 4.34 Fig. 4.35 Fig. 4.36 Fig. 4.37 Fig. 4.38 Fig. 4.39 Fig. 4.40 Fig. 4.41 Fig. 4.42 Fig. 4.43 Fig. 4.44 Fig. 4.45 Fig. 4.46 Fig. 4.47 Fig. 4.48 Fig. 4.49 Fig. 4.50 Fig. 4.51 Fig. 4.52 Fig. 4.53 Fig. 4.54 Fig. 4.55 Fig. 4.56 Fig. 4.58 Fig. 4.57 Fig. 4.59 Fig. 4.60 Fig. 4.61

xxiii

AC model .. . . .. . . . .. . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . KCL at node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KCL at node 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A common source amplifier .. . .. . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . The small-signal AC model of the common source amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Π-arrayed small-signal AC model of the common source amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The small-signal voltages of the common source amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node elimination, (a) Original n-node circuit, and (b) Reduced circuit with n-1 nodes . . .. . .. .. . .. . .. .. . .. . .. . .. .. . (a) 4-node Y-shaped circuit and (b) 3-node delta-shaped circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-port model of a circuit using Y-parameters . . . . . . . . . . . . . . Testbench for calculating differential admittance . . . . . . . . . . . . . Loaded two-port circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Source transformation, (a) Input current source, and (b) Input voltage source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A general two-port loaded circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input and output admittances of the two-port circuit with respect to source and load admittances . . . . . . . . . . . . . . . . . . . . . . . . A 3-gon power divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impedance matching conditions for the 3-gon power divider . . .. .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. .. . .. .. . .. .. . A 3-pole power divider . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . Impedance matching conditions for the 3-pole power divider . . .. .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. . .. .. .. . .. .. . .. .. . Powers of a loaded two-port circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input model to calculate maximum available power from source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output model to calculate maximum available power from circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mismatch between source and load admittances . . . . . . . . . . . . . . Impact of admittance variation on power . . . . . . . . . . . . . . . . . . . . . . Testbench to calculate S-parameters of a two-port circuit . . . . Excitation of the two-port circuit at input port . . . . . . . . . . . . . . . . Testbench to calculate differential impedance of a two-port circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modeling a two-port circuit with Z-parameters . . . . . . . . . . . . . . . Mismatch between source and load impedances . . . . . . . . . . . . . . Testbench to calculate impedance S-parameters of a two-port circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loaded two-port circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

222 222 223 223 229 230 230 230 233 234 236 236 237 238 239 241 242 244 246 248 250 251 251 255 256 257 258 260 260 264 266 269

xxiv

Fig. 4.62 Fig. 4.63 Fig. 4.64 Fig. 4.65 Fig. 4.66 Fig. 4.67 Fig. 4.68 Fig. 4.69 Fig. 4.70 Fig. 4.71 Fig. 4.72 Fig. 4.73 Fig. 4.74 Fig. 4.75 Fig. 4.76 Fig. 4.77 Fig. 4.78 Fig. 4.79 Fig. 4.80 Fig. 4.81 Fig. 4.82 Fig. 4.83 Fig. 4.84 Fig. 4.85 Fig. 4.86 Fig. 4.87 Fig. 4.88 Fig. 4.89 Fig. 4.90 Fig. 4.91 Fig. 4.92 Fig. 4.93 Fig. 4.94 Fig. 4.95 Fig. 4.96 Fig. 4.97 Fig. 4.98 Fig. 4.99 Fig. 4.100 Fig. 4.101 Fig. 4.102

List of Figures

A piezoelectric crystal filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Input admittance and (b) Voltage-gain of the filter . . . . . . . S-parameters of the filter, (a) S11 and (b) S21 . . . . . . . . . . . . . . . . . (a) Impulse and (b) Step responses of the filter . . . . . . . . . . . . . . . Root locus of the filter . .. . . . . . .. . . . . . . .. . . . . . . .. . . . . . .. . . . . . . .. . . (a) Nyquist and (b) Nichols plots of the filter . . . . . . . . . . . . . . . . . (a) Transient response and (b) Spectrum of the sinusoidal waveforms in filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transient response and (b) Spectrum of the square waveforms in filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transient response and (b) Spectrum of the sawtooth waveforms in filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pole-zero map of the filter . . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. Gain, phase, and delay responses of the filter . . . . . . . . . . . . . . . . . Filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pole-zero map of the filter . . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. Gain, phase, and delay responses of the filter . . . . . . . . . . . . . . . . . Filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pole-zero map of the Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain, phase, and delay responses of the Filter . . . . . . . . . . . . . . . . Single-stage poly phase filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient responses of the single-stage poly phase filter . . . . . Gain, phase, and delay of the single-stage poly phase filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input impedance of the single-stage poly phase filter . . . . . . . . . Output impedance of the single-stage poly phase filter . . . . . . . Low pass directional coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S22 of the coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage-gain from node 3 to node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . S33 of the coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage-gain from node 4 to node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . S44 of the coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage-gain from node 5 to node 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . S55 of the coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cross section of substrate capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model of the substrate capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y-parameters of the substrate capacitor . . . . . . . . . . . . . . . . . . . . . . . . S-parameters of the substrate capacitor . . . . . . . . . . . . . . . . . . . . . . . . Conductance between terminals 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . Capacitance between terminals 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . Quality factor of the substrate capacitor . . . . . . . . . . . . . . . . . . . . . . . Cross section of substrate inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model of the substrate inductor .. . . . . .. . . . . .. . . . .. . . . . .. . . . . .. . . Z-parameters of the substrate inductor . . . . . . . . . . . . . . . . . . . . . . . . .

277 277 278 278 279 279 279 280 280 282 283 283 285 286 287 289 290 291 292 294 295 295 296 299 301 301 302 303 304 304 305 308 308 309 310 311 311 311 314 315 317

List of Figures

Fig. 4.103 Fig. 4.104 Fig. 4.105 Fig. 4.106 Fig. 4.107 Fig. 4.108 Fig. 4.109 Fig. 4.110 Fig. 4.111 Fig. 4.112 Fig. 4.113 Fig. 4.114 Fig. 4.115 Fig. 4.116 Fig. 4.117 Fig. 4.118 Fig. 4.119 Fig. 4.120 Fig. 4.122 Fig. 4.121 Fig. 4.123 Fig. 4.124 Fig. 4.125 Fig. 5.1 Fig. 5.2 Fig. 5.3 Fig. 5.4 Fig. 5.5 Fig. 5.6 Fig. 5.7 Fig. 5.8 Fig. 5.9 Fig. 5.10 Fig. 5.11 Fig. 5.12 Fig. 5.13 Fig. 5.14 Fig. 5.15 Fig. 5.16

xxv

S-parameters of the substrate inductor . . . . . . . . . . . . . . . . . . . . . . . . . Resistance between terminals 1 and 5 .. . . .. . .. . .. . .. . . .. . .. . .. . Inductance between terminals 1 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . Quality factor of the substrate inductor . . . . . . . . . . . . . . . . . . . . . . . . The S-parameters of the measured and the modeled substrate inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . An overview of this chapter topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-Signal AC Model of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 7 . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC Model of Question 8 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 9 . . . . . . . . . . . . . . . . . . . . . . . . . Voltage noise signals with (a) Uniform and (b) Normal distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Uniform and (b) Normal probability distribution functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Power spectral density and (b) Signal spectral density of a noise voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Thevenin and (b) Norton models of the resistor thermal noise .. .. . .. . .. .. . .. . .. .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. .. . .. . .. .. . Noise of capacitor using Thevenin model . . . . . . . . . . . . . . . . . . . . . Noise of capacitor using Norton model . . . . . . . . . . . . . . . . . . . . . . . . A general n-node circuit with internal noise sources . . . . . . . . . A general two-node resistive circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . vno to vni transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vno to ini transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ino to vni transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ino to ini transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vni and ini transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vni to vno transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vni to ino transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ini to vno transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

318 319 319 319 322 326 327 327 328 328 328 329 329 330 330 331 331 332 333 333 334 335 335 339 339 342 344 344 345 346 349 351 352 353 354 355 356 357 358

xxvi

Fig. 5.17 Fig. 5.18 Fig. 5.19 Fig. 5.20 Fig. 5.21 Fig. 5.22 Fig. 5.23 Fig. 5.24 Fig. 5.25 Fig. 5.26 Fig. 5.27 Fig. 5.28 Fig. 5.29 Fig. 5.30 Fig. 5.31 Fig. 5.32 Fig. 5.33 Fig. 5.34 Fig. 5.35 Fig. 5.36 Fig. 5.37 Fig. 5.38 Fig. 5.39 Fig. 5.40 Fig. 5.41 Fig. 5.42 Fig. 5.43 Fig. 5.44 Fig. 5.45 Fig. 5.46 Fig. 5.47 Fig. 5.48 Fig. 5.49 Fig. 5.50 Fig. 5.51 Fig. 5.52 Fig. 5.53 Fig. 5.54 Fig. 5.55 Fig. 5.56 Fig. 5.57

List of Figures

ini to ino transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vno and ino transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Network current noises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total referred noises of a circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Incorrect and (b) Correct noise transformations . . . . . . . . . . . (a) Input/output current and (b) Input voltage/current noise models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Input/output current and (b) Input voltage/current noise models with shorted inputs . .. . . . .. . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . (a) Input/output current and (b) Input voltage/current noise models with shorted outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testbench to measure the voltage noise factor of a circuit . . . Testbench to measure the voltage noise factor of a circuit . . . Testbench to measure the power noise factor of a circuit . . . . Delivered power and noise factor characteristics of two-port circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of the current noise factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of voltage noise factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and noise factor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Example of a passive two-port circuit . . . .. . . . . . .. . . . . .. . . . . . .. . The passive two-port circuit used in Example 2 . . . . . . . . . . . . . . Input referred noise current spectral density . . . . . . . . . . . . . . . . . . . Transient noise current at input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input referred noise voltage spectral density . . . . . . . . . . . . . . . . . . Transient noise voltage at input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise factor characteristics versus frequency . . .. . . .. . .. . .. . . .. Example of an active two-port circuit . . . . . . . . . . . . . . . . . . . . . . . . . . The active two-port circuit used in Example 2 . . . . . . . . . . . . . . . . Input referred noise current spectral density . . . . . . . . . . . . . . . . . . . Transient noise current at input of the two-port circuit . . . . . . . Input referred noise voltage spectral density . . . . . . . . . . . . . . . . . . Transient noise voltage at input of the two-port circuit . . . . . . . Power and noise factor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Noise factor characteristics versus load variations . . . . . . . . . . . . An overview of this chapter topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

359 360 361 361 362 363 363 363 364 365 365 366 367 367 368 368 369 370 371 371 372 372 373 373 373 376 376 377 377 378 378 381 382 382 383 383 384 384 385 385 386

List of Figures

xxvii

Fig. 5.58 Fig. 5.59 Fig. 5.60 Fig. 5.61 Fig. 5.62

Small-signal AC model of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal AC model of Question 7 . . . . . . . . . . . . . . . . . . . . . . . . .

387 387 388 389 389

Fig. 6.1 Fig. 6.2 Fig. 6.3 Fig. 6.4 Fig. 6.5 Fig. 6.6 Fig. 6.7 Fig. 6.8 Fig. 6.9 Fig. 6.10 Fig. 6.11 Fig. 6.12 Fig. 6.13 Fig. 6.14 Fig. 6.15 Fig. 6.16 Fig. 6.17 Fig. 6.18 Fig. 6.19 Fig. 6.20 Fig. 6.21 Fig. 6.22 Fig. 6.23 Fig. 6.24

A full-wave rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Different levels of circuit modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals of the rectifier circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The inverting hysteresis circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The noninverting hysteresis circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The diode rectifier circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ESD protection circuit . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The full-wave rectifier circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . An overview of this chapter topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transfer characteristics and (b) Transient response of Question 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transfer characteristics and (b) Transient response of Question 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transfer characteristics and (b) Transient response of Question 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transfer characteristics and (b) Transient response of Question 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transfer characteristics and (b) Transient response of Question 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

393 393 394 398 398 399 400 401 401 403 404 404 406 406 407 409 409 409 411 412 412 414 415

Fig. 6.25 Fig. 6.26 Fig. 6.27 Fig. 6.28 Fig. 6.29 Fig. 6.30 Fig. 6.31 Fig. 6.32 Fig. 6.33

415 416 416 416 417 417 418 418 418 419

xxviii

Fig. 6.34 Fig. 6.35 Fig. 6.36 Fig. 6.37 Fig. 6.38

List of Figures

(a) Transfer characteristics and (b) Transient response of Question 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transfer characteristics and (b) Transient response of Question 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit of Question 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Transfer characteristics and (b) Transient response of Question 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

419 420 420 420 421

List of Tables

Table 1.1 Table 1.2 Table 1.3 Table 1.4 Table 1.5 Table 1.6

Table 1.11

Signal values at different time stamps . . . . . . . . . . . . . . . . . . . . . . . . . Integral values at different time stamps . . . . . . . . . . . . . . . . . . . . . . . . Numerical integral calculation using 11 discrete points . . . . . . Numerical derivation calculation using discrete points . . . . . . . Different biasings of NPN transistors . . . . . . . . . . . . . . . . . . . . . . . . . . Small-signal parameters of the NPN transistor in different operating regions . . . .. . . . . .. . . . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . . .. . Capacitors of NPN transistor in different operating regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current equations of long channel NMOS transistors . . . . . . . . Small-signal parameters of the NMOS transistor in different operating regions . . . .. . . . . .. . . . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . . .. . Capacitors of NMOS transistor in different operating regions for a one-finger layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General characteristics of basic electronic components .. . . .. .

Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14

Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC values .. . .. .. . .. . .. .. . .. .. . .. . .. .. . .. .. . .. . .. .. . .. .. . .. . .. .. . .. Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 1.7 Table 1.8 Table 1.9 Table 1.10

3 3 3 5 38 41 42 47 49 50 54 78 80 83 87 89 91 94 96 99 101 103 105 107 109

xxix

xxx

List of Tables

Table 3.1 Table 3.2 Table 3.3 Table 3.4 Table 3.5 Table 3.6 Table 3.7 Table 3.8 Table 3.9 Table 3.10 Table 3.11 Table 3.12 Table 3.13 Table 3.14 Table 3.15 Table 3.16 Table 3.17 Table 3.18 Table 3.19 Table 3.20 Table 3.21 Table 3.22 Table 3.23 Table 3.24 Table 3.25 Table 3.26 Table 3.27

Basic Laplace transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter valuess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numerical values to calculate circuit response . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numerical values to calculate circuit response . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numerical values to calculate circuit response . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numerical values to calculate circuit response . . . . . . . . . . . . . . . . Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial conditions in Laplace transformations . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter values of Question 1 . .. . . . . . . . . .. . . . . . . . .. . . . . . . . .. . . Parameter values of Question 2 . .. . . . . . . . . .. . . . . . . . .. . . . . . . . .. . . Parameter values of Question 3 . .. . . . . . . . . .. . . . . . . . .. . . . . . . . .. . . Parameter values of Question 4 . .. . . . . . . . . .. . . . . . . . .. . . . . . . . .. . . Parameter values of Question 5 . .. . . . . . . . . .. . . . . . . . .. . . . . . . . .. . .

122 123 123 127 127 131 132 136 138 141 141 145 148 150 154 158 161 163 166 170 175 180 189 190 191 192 193

Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Table 4.6 Table 4.7 Table 4.8 Table 4.9

Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculating circuit transfer functions in terms of Av and Yin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit parameters .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . Circuit parameters .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . Circuit parameters .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . Circuit parameters .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . .. .. . Component values of the low pass coupler . . . . . . . . . . . . . . . . . . . . Component values of the substrate inductor . . . . . . . . . . . . . . . . . . .

208 210 211 214 215 219 221 225

Table 4.10 Table 4.11 Table 4.12 Table 4.13 Table 4.14 Table 4.15

240 283 286 290 294 300 323

List of Tables

Table 4.16 Table 4.17 Table 5.1 Table 5.2 Table 5.3

xxxi

Initial guesses for the component values of the substrate inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modeled Component Values of the Substrate Inductor . . . . . . . Samples of uniformly distributed x1(t) and normally distributed x2(t) noise signals . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . Circuit parameters in Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit parameters in Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

323 323 340 370 375

Chapter 1

Framework

The framework of a circuit simulator is studied in this chapter. It includes modeling of electronic components, generation of electric signals, and programming of some schematic editor functions. An electronic component can have different models for different types of simulations. For each simulation, the netlisting must use appropriate models for generating the system of equations. Modeling of resistors, capacitors, inductors, transformers, and semiconductor devices such as diodes, bipolar and field-effect transistors for DC, transient, AC, and noise analyses are explained in this chapter. Signal waveforms are defined in time and s-domains for transient and AC analyses. The editor functions such as placement, moving and rotating components as well as creating a netlist are also presented. An Overview of this chapter topics is listed in the following table. Schematic Composing

Signals Ch. 1 Framework Components

Ch. 2

Ch. 3

DC Analysis

Transient Analysis

DC, Transient, AC and Noise modeling

Netlisting

Linear Equations

Direct Methods

Nonlinear Equations

Iterative Methods

DC Circuit Model

Linear Circuits

Aperiodic and Periodic Signals

Laplace Transform

Nonlinear Circuits

Switching Circuits

Differential Equations

Ch. 4

AC Analysis

Linearized s-domain Model

Matrix Calculations

Ch. 5

Noise Analysis

Linearized s-domain Model

Noise Matrix Calculations

Ch. 6

Behavioral Analysis

Block-Level Modeling

Transfer Function Characteristics

Noise Transformation

Accuracy and Speed Tradeoff

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 S. Hamedi-Hagh, Computational Electronic Circuits, https://doi.org/10.1007/978-3-030-75568-3_1

1

2

1.1

1 Framework

Numeric and Symbolic Analyses

Circuit analysis is performed using two general methods of numeric and symbolic approaches. The symbolic circuit analysis provides an in-depth knowledge for understanding the circuit characteristic and behavior. While results generated by the symbolic analysis yield full accuracy, the computational disk and memory requirement to store and process the symbolic expressions increase exponentially as the number of nodes increases in a circuit. When many symbolic parameters are added, subtracted, multiplied, and divided together, the result will be a huge expression that includes all constituting parameters. This is the main and only disadvantage of symbolic analysis in designing large-scale circuits. On the other hand, the length and size of numeric data do not change when many numeric results are added, subtracted, multiplied, and divided together. This makes the numerical analysis very suitable for efficient use of disk and memory resources. For a trade-off between the symbolic and the numeric analyses, a hybrid approach of keeping limited number of critical symbolic circuit parameters while the rest of the components use numeric values can be adopted. The numerical approach is the focus of this textbook while the symbolic approach is also addressed as a reference for the verification of simulation results. As an example, the Laplace transformation is used as a reference for measuring the accuracy of the results generated by discretized transient analysis. The four major circuit simulations include DC, transient, AC, and noise analyses. In DC simulation, the objective is to find the offset level of signals and the biasing points of semiconductor devices that indicate their behavior. Inductors become short and capacitors remain open during DC analysis. Transient analysis is used for timedomain analysis of circuits that could include large signal and nonlinear behaviors. In AC analysis, circuits are linearized and their small-signal characteristics are extracted by transforming circuits and signals to s-domain. Two different approaches of transient and AC analyses can be used to obtain the noise characteristic of circuits. All four major types of simulations are explained in detail in the next chapters.

1.2

Finite Integral

Converting time-domain signals to discrete numbers is essential in numeric analysis. Assume a time-domain voltage signal v(t) is given by the following expression. vðt Þ ¼ 2ð0:1tÞ6 þ 5ð0:1tÞ3  0:4t þ 2

ð1:1Þ

The signal values at different time steps are given in Table 1.1. The integral of the voltage signal v(t) can be analytically calculated by the following expression.

1.2 Finite Integral

3

Table 1.1 Signal values at different time stamps t [s]

0

v(t) [V]

2.0000 1.6050 1.2399 0.9335 0.7118 0.5938 0.5867 0.6797 0.8357 0.9821 1.0000

1

2

3

4

5

6

7

8

9

10

Table 1.2 Integral values at different time stamps t [s] 0 1 2 3 4 5 6 7 8 9 10 f(t) 0 1.8012 3.2200 4.3006 5.1153 5.7589 6.3400 6.9660 7.7208 8.6347 9.6429

Table 1.3 Numerical integral calculation using 11 discrete points

tk [s] 0 1 2 3 4 5 6 7 8 9 10 11

k 1 2 3 4 5 6 7 8 9 10 11 12

vk [V] 2.0000 1.6050 1.2399 0.9335 0.7118 0.5938 0.5867 0.6797 0.8357 0.9821 1.0000 –

fk f1 ¼ initial condition f2 ¼ f1 + v1(t2  t1) f3 ¼ f2 + v2(t3  t2) f4 ¼ f3 + v3(t4  t3) f5 ¼ f4 + v4(t5  t4) f6 ¼ f5 + v5(t6  t5) f7 ¼ f6 + v6(t7  t6) f8 ¼ f7 + v7(t8  t7) f9 ¼ f8 + v8(t9  t8) f10 ¼ f9 + v9(t10  t9) f11 ¼ f10 + v10(t11  t10) f12 ¼ f11 + v11(t12  t11)

ð 2 5 4 ð0:1tÞ7 þ ð0:1tÞ4  ð0:1tÞ2 þ 2t f ðt Þ ¼ vðt Þdt ¼ 0:7 0:4 0:2

value 0 2.0000 3.6050 4.8449 5.7784 6.4902 7.0840 7.6707 8.3504 9.1861 10.1682 11.1682

ð1:2Þ

The integral values at different time steps are given in Table 1.2. The advantages of symbolic analysis are obtaining the closed form expressions of signals and their precise values that accurately represent the signals at any time. The integral value of a signal for numerical analysis suitable for computer simulations is calculated by discretizing the integral using the following expression. f k ¼ initial condition þ

N X

vk1 ðt k  t k1 Þ

ð1:3Þ

k¼2

where N is the number of discrete points used in the simulation. The value of initial condition depends on the signal and the circuit configuration. It is very important to obtain the correct initial condition from circuit information in order to maintain calculation accuracy. For N ¼ 11 and an initial condition of 0, the numerical integral is calculated as listed in Table 1.3. Results obtained by the numeric integral calculation is shown in Fig. 1.1. For N ¼ 11 discrete points, results are erroneous, as shown in Fig. 1.1a. To reduce the calculation errors, the time steps must be reduced and the number of discrete points

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Fig. 1.1 Comparison of symbolic and numeric integral calculations, (a) 11 discrete points and (b) 51 discrete points

must be increased. For N ¼ 51 discrete points, results become more accurate, as shown in Fig. 1.1b. The drawbacks of increasing data points to achieve higher accuracy are slower simulation speeds and higher memory requirement. To improve the performance of numerical simulations, it is possible to vary simulation time steps based on signal characteristics. When signal variations are small, larger time steps can be selected and when signal variations are high, smaller time steps can be selected. The following MATLAB code compares the accuracy of the discretized integral of an arbitrary function with respect to the integration time steps.

t=(0:1:10); f=-2*(0.1*t).^6+5*(0.1*t).^3-4*(0.1*t)+2; Sf=(-2/0.7)*(0.1*t).^7+(5/0.4)*(0.1*t).^4-(4/0.2)*(0.1*t).^2+2*t; %symbolic integral dSf=zeros(1,length(t)); dSf(1)=Sf(1); % integral initial condition for k=2:length(t) dSf(k)=f(k-1)*(t(k)-t(k-1))+dSf(k-1); %numeric integral end disp(['number of points = ',num2str(length(t))]) disp(['time = ',num2str(t(1:1:end),'%.3f ')]) disp(['signal = ',num2str(f(1:1:end),'%.3f ')]) disp(['symbolic integral = ',num2str(Sf(1:1:end),'%.3f ')]) disp(['numeric integral = ',num2str(dSf(1:1:end),'%.3f ')])

1.3 Finite Difference

1.3

5

Finite Difference

The derivation of a signal is symbolically calculated by the following expression. vð t Þ ¼

∂f ðt Þ ∂t

ð1:4Þ

To calculate a signal derivation using numerical analysis, the following expression can be used. vk ¼

f  fk Δf ¼ kþ1 Δt t kþ1  t k

ð1:5Þ

The discretized derivation values vk are calculated using fk values listed in Table 1.2. The results are listed in Table 1.4. From the table, the derivation of the integral of a signal is close to the signal itself as expected. To increase the accuracy of the discrete derivation, time steps must be reduced or the number of discrete points must be increased in a trade-off with slower simulation speeds and higher memory requirement (Fig. 1.2). The following MATLAB code compares the accuracy of the discretized derivation of an arbitrary function with respect to the derivation time steps.

Table 1.4 Numerical derivation calculation using discrete points tk [s] 0 1 2 3 4 5 6 7 8 9 10 11

k 1 2 3 4 5 6 7 8 9 10 11 12

fk f1 ¼ initial condition ¼ 0 f2 ¼ f1 + v1(t2  t1) ¼ 1.801 f3 ¼ f2 + v2(t3  t2) ¼ 3.220 f4 ¼ f3 + v3(t4  t3) ¼ 4.301 f5 ¼ f4 + v4(t5  t4) ¼ 5.115 f6 ¼ f5 + v5(t6  t5) ¼ 5.759 f7 ¼ f6 + v6(t7  t6) ¼ 6.340 f8 ¼ f7 + v7(t8  t7) ¼ 6.966 f9 ¼ f8 + v8(t9  t8) ¼ 7.721 f10 ¼ f9 + v9(t10  t9) ¼ 8.635 f11 ¼ f10 + v10(t11  t10) ¼ 9.643 f12 ¼ f11 + v11(t12  t11) ¼ 10.533

vk [V] v1 ¼ ( f2  f1)/(t2  t1) v2 ¼ ( f3  f2)/(t3  t2) v3 ¼ ( f4  f3)/(t4  t3) v4 ¼ ( f5  f4)/(t5  t4) v5 ¼ ( f6  f5)/(t6  t5) v6 ¼ ( f7  f6)/(t7  t6) v7 ¼ ( f8  f7)/(t8  t7) v8 ¼ ( f9  f8)/(t9  t8) v9 ¼ ( f10  f9)/(t10  t9) v10 ¼ ( f11  f10)/(t11  t10) v11 ¼ ( f12  f11)/(t2  t1) –

value 1.801 1.419 1.081 0.815 0.644 0.581 0.626 0.755 0.914 1.008 0.891 –

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Fig. 1.2 Comparison of symbolic and numeric derivative calculations, (a) 11 discrete points and (b) 51 discrete points

t=(0:1:10); f=(-2/0.7)*(0.1*t).^7+(5/0.4)*(0.1*t).^4-(4/0.2)*(0.1*t).^2+2*t; % signal df=-2*(0.1*t).^6+5*(0.1*t).^3-4*(0.1*t)+2; %symbolic derivative ddf=zeros(1,length(t)); for k=2:length(t) ddf(k-1)=(f(k)-f(k-1))/(t(k)-t(k-1)); %numeric derivative end disp(['number of points = ',num2str(length(t))]) disp(['time = ',num2str(t(1:1:end),'%.3f ')]) disp(['signal = ',num2str(f(1:1:end),'%.3f ')]) disp(['symbolic derivative = ',num2str(df(1:1:end),'%.3f ')]) disp(['numeric derivative = ',num2str(ddf(1:1:end),'%.3f ')])

1.4

Laplace Transformation

To achieve full analysis accuracy, symbolic analysis such as Laplace transformation can be used. The Laplace transformation converts a signal from time-domain to complex-domain by the following integral. 1 ð

F ðsÞ ¼ 0

f ðtÞest dt

ð1:6Þ

1.4 Laplace Transformation

7

jω imaginary axis

Fig. 1.3 The s-plane used in Laplace transformation

0

real axis σ

The complex-domain is also called the s-domain where s ¼ σ + jω. To prevent the integral from diverging to infinity, the condition of σ  0 must be satisfied, as shown in Fig. 1.3. The signals in s-domain are converted back to time-domain by applying the inverse Laplace transformation given by 1 f ðt Þ ¼ lim j2π T!1

jT ð

F ðsÞest ds

ð1:7Þ

jT

The Laplace transformation helps to convert integrals and derivations into linear s-domain functions that can be easily solved using simple algebraic methods. The results are easily converted back to time-domain without the requirement to solve nonlinear integrals and differential equations. Some popular conversions between the time-domain and the s-domains signals that are widely used in circuits are presented here.

1.4.1

Basic Signals

The Laplace transformation of the unit impulse is given by. L

δ ðt Þ $ 1

ð1:8Þ

The Laplace transformation of the unit step is given by. L

uð t Þ $

1 s

ð1:9Þ

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The Laplace transformation of a sinusoidal signal is given by. L

sin ðωt Þuðt Þ $

ω s 2 þ ω2

ð1:10Þ

The Laplace transformation of the cosine signal is given by. L

cos ðωt Þuðt Þ $

1.4.2

s s 2 þ ω2

ð1:11Þ

Multiplication and Convolution

The multiplication of two signals in time-domain is equivalent to their convolution in s-domain, as given by L

1 lim f ðt Þgðt Þ $ j2π T!1

σþjT ð

F ðσ ÞGðs  σ Þdσ ¼ F ðsÞ  GðsÞ

ð1:12Þ

σjT

The convolution of two signals in time-domain is equivalent to their multiplication in s-domain, as given by ðt

L

f ðt Þ  gðt Þ ¼ f ðτÞgðt  τÞdτ $ F ðsÞGðsÞ

ð1:13Þ

0

1.4.3

Scaling

The scaling property of Laplace transformation is given by. L

f ðat Þuðt Þ $

  1 s F a a

ð1:14Þ

The scaling property shows the fact that if a signal variation becomes faster in time-domain, it will expand in the s-domain and vice versa.

1.4 Laplace Transformation

1.4.4

9

Shifting

The frequency shift property of the Laplace transformation is given by. L

eat f ðt Þuðt Þ $ F ðs þ aÞ

ð1:15Þ

The time shift property of the Laplace transformation is given by. L

f ðt  aÞuðt  aÞ $ eas F ðsÞ

1.4.5

ð1:16Þ

Differentiation

The time-domain derivative property of the Laplace transformation is given by.   n k1 n X ∂ f ðt Þ L n ∂ f ð t Þ  nk $ s F ð s Þ  s k1  ∂t n ∂t k¼1

ð1:17Þ t¼0

The s-domain derivative property of the Laplace transformation is given by. L

tn f ðtÞ $ ð1Þn

1.4.6

n

∂ F ðsÞ ∂sn

ð1:18Þ

Integration

The time-domain integral property of the Laplace transformation is given by. ðt

L

f ðt Þdt $

1 F ðsÞ s

ð1:19Þ

0

The s-domain integral property of the Laplace transformation is given by. L 1 f ðt Þ $ t

1 ð

F ðsÞds s

ð1:20Þ

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1.4.7

Multiplication by Time

The multiplication by the time property of the Laplace transformation is given by. L

tn uðtÞ $

n! sn

ð1:21Þ

The multiplication and the shifting properties can be combined such as L

tn eat uðtÞ $

1.4.8

n! ð s þ aÞ n

ð1:22Þ

Conjugate Property

The conjugate property of Laplace transformation is given by. L

f  ðt Þ $ F  ðs Þ

1.4.9

ð1:23Þ

Initial and Final Values

The initial value of a signal is obtained by L

f ð0Þ $ lim sF ðsÞ s!1

ð1:24Þ

The final value of a signal is obtained by L

f ð1Þ $ lim sF ðsÞ s!0

ð1:25Þ

1.4.10 Periodicity The periodicity property of the Laplace transformation is given by L

f ðt þ T Þ ¼ f ðt Þ $

F ðsÞ 1  esT

ð1:26Þ

1.5 Waveforms

11

Since majority of signals applied to electronic circuits are periodic such as Sawtooth, Triangle, Pulse, and Square waveforms, the periodicity property of the Laplace transformation helps to accurately calculate the circuit responses for a variety of periodic signals. These responses can be used as references to measure the accuracy of the transient simulations calculated by discretizing the differential and integral equations, as will be explained in Chap. 3.

1.5

Waveforms

Signals applied to circuits are categorized into aperiodic and periodic waveforms. It is possible to express aperiodic signals as combinations of constant values or periodic signals multiplied by a series of Heaviside functions. Examples of aperiodic signals are narrowband pulses or repeating patters with random shapes. Examples of periodic signals are sinusoidal, square, triangular, Sawtooth, and pulse waveforms. Square waveforms are used in switching applications and clock generation. Triangular waveforms are used in characterization of the hysteresis and comparator circuits and transfer characteristics. Sawtooth waveforms are used in characterization of the data converters and transistor transfer characteristics. Pulse waveforms with small duty cycles (when pulses have high peaks during short time intervals) are used in radars and characterization of high frequency circuit behaviors. A Heaviside step function in time-domain is given by f ðt  0Þ ¼ 1 and f ðt < 0Þ ¼ 0

ð1:27Þ

and in s-domain is given by F ðsÞ ¼

1 s

ð1:28Þ

The time t ¼ 0 is when the signal is applied to the circuit. The Heaviside step waveform is shown in Fig. 1.4. A sinusoidal waveform in time-domain is given by f ðt  0Þ ¼ sin ðωt Þ

ð1:29Þ

and in s-domain is given by F ðsÞ ¼

ω ω 2 þ s2

The sinusoidal waveform is shown in Fig. 1.5. The absolute value of a sinusoidal waveform in time-domain is given by

ð1:30Þ

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Fig. 1.4 A Heaviside step waveform

Fig. 1.5 A sinusoidal waveform

f ðt  0Þ ¼ j sin ðωt Þj

ð1:31Þ

and in s-domain is given by F ðsÞ ¼

 πs 2 1þeω ω  2πs s 2 þ ω2 1e ω

The absolute of the sinusoidal waveform is shown in Fig. 1.6. A square waveform in time-domain is given by

ð1:32Þ

1.5 Waveforms

13

Fig. 1.6 The absolute of the sinusoidal waveform

f ðt  0Þ ¼ ð1Þb π c ωt

ð1:33Þ

where b c is the floor function. The square waveform in s-domain is given by  πs 2 1eω   F ðsÞ ¼ 2πs s 1e ω

ð1:34Þ

The square waveform is shown in Fig. 1.7. A triangle waveform in time-domain is given by  j k ωt  ωt  þ 0:5   1 f ð t  0Þ ¼ 2  2π 2π

ð1:35Þ

where b c is the floor function. The triangle waveform in s-domain is given by

F ðsÞ ¼

2ω π



  πs 2 2πs 1eω s 1e ω   2πs s2 1  e ω

ð1:36Þ

The triangle waveform is shown in Fig. 1.8. A Sawtooth waveform in time-domain is given by f ð t  0Þ ¼ 2



j k ωt ωt  þ 0:5  1 2π 2π

ð1:37Þ

where b c is the floor function. The sawtooth waveform in s-domain is given by

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Fig. 1.7 A square waveform

Fig. 1.8 A triangle waveform

ω F ðsÞ ¼

π s



 2πs 2πs 1  e ω  2se ω   2πs s2 1  e ω

ð1:38Þ

The Sawtooth waveform is shown in Fig. 1.9. A backward Sawtooth waveform in time-domain is given by f ð t  0Þ ¼ 1  2



j k ωt ωt  þ 0:5 2π 2π

ð1:39Þ

where b c is the floor function. The backward sawtooth waveform in s-domain is given by

1.5 Waveforms

15

Fig. 1.9 A Sawtooth waveform

Fig. 1.10 A backward Sawtooth waveform

F ðsÞ ¼

2se

2πs ω

   2πs þ s  ωπ 1  e ω   2πs s2 1  e ω

ð1:40Þ

The backward Sawtooth waveform is shown in Fig. 1.10. A pulse waveform in time-domain is given by $  % duty k ω t  2π 100ω ωt  f ð t  0Þ ¼ 2π 2π j

where b c is the floor function. The pulse waveform in s-domain is given by

ð1:41Þ

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Fig. 1.11 A pulse waveform

    2πs 2πs  1  e ω þ 2 1  eð ω dutyÞ   F ðsÞ ¼ 2πs s 1  e ω

ð1:42Þ

The pulse waveform is shown in Fig. 1.11. The following MATLAB code generates pulse waveforms using two different methods of the direct time-domain and the inverse Laplace transformation of the s-domain.

syms s f0=1e+07; np=4; nt=101; dt=(np/f0)/(np*nt); time=0:dt:(np/f0)-dt; duty=10; PULSE=exp(-0*s/(100*f0))*(1-exp(-s*duty/(100*f0)))/(s*(1-exp(-s/ (1*f0)))); pulse1=double(subs(ilaplace(PULSE),sym('t'),time)); pulse2=floor(f0*time)-floor(f0*(time-duty/(100*f0))); figure plot(time,pulse1) figure plot(time,pulse2)

1.6 Components

1.6

17

Components

Electronic circuits are built with components and characteristics of these components are required in order to create accurate models and analyze circuits and extract their transfer functions.

1.6.1

Ground

Due to its massive mass, the earth has a constant potential that hardly changes and can be used as a reference level to measure the potential of other charges. Similarly, in circuits there is a common return path for currents from other components that is used as a reference level to measure other voltages. This reference level is called ground and is assumed to have a zero-potential voltage. The ground in circuits has a symbol shown in Fig. 1.12. Because ground currents are the replica from other nodes, they are not used in KCL equations to prevent redundancy.

1.6.2

Short

In circuits, wires are used to connect different electronic components together. An ideal wire is a “short” meaning the electric potential between the two ends of the wire are exactly equal. Therefore, the wire voltage drop that is defined as the voltage difference between the two ends of the wire will be zero. Also, any amount of current can pass through ideal wires, as shown in Fig. 1.13.

1.6.3

Open

When a wire is cut or removed, it is an “open” meaning its current flow stops and their voltage drops becomes equal to the existing voltage difference between the ends of the disconnected wire. In another word, an open can hold any amount of voltage while the current flow through it is zero, as shown in Fig. 1.14.

1.6.4

Ideal Switch

Switches are electronic components that have two states of operation. When a switch is in ON position, it acts like a short and passes any current while the voltage

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Fig. 1.12 Ground symbol

Fig. 1.13 Voltage drop and current flow of a short

ΔV=0 I: finite

Fig. 1.14 Voltage drop and current flow of an open

ΔV: finite I=0

Fig. 1.15 Operating states of a switch, (a) Short and (b) Open

ΔV=0

ΔV: finite

I: finite

I=0

(a)

(b)

difference between the two ends of the switch will remain zero. When the switch is in OFF position, it acts like an open and holds the voltage difference between its two ends while the current flow between the two ends of the switch will remain zero. The symbol of a switch and its two modes of operations are shown in Fig. 1.15a, b. The labeled voltages and currents of the switches are measured after the switching action takes place (t  0). Ideal switches have transfer characteristics, as shown in Fig. 1.16.

1.6.5

Resistors

Resistors are built using conductive materials, as shown in Fig. 1.17. The value of a resistor, called its resistance, is given by R¼ρ

ℓ A

ð1:43Þ

Where ρ is the material resistivity measured in [Ω.m], ℓ is the length of material measured in [m], and A is the cross-sectional area measured in [m2]. To increase the resistance, highly resistive materials with a long length and small cross-sectional area can be used. However, a small cross-sectional area reduces the current handling capability of a resistor.

1.6 Components

19

Fig. 1.16 Transfer characteristics of an ideal switch

short

I open ΔV

Fig. 1.17 Physical resistor structure

area: A

Fig. 1.18 Transfer characteristics of resistors

IR Slope=1/R VR

Fig. 1.19 Resistor symbol

VR(t) R IR(t)

Resistors have linear transfer characteristics between their voltage drop and current flow, as illustrated in Fig. 1.18. When a voltage is applied to a resistor, it creates a current flow. The relationship between the voltage drop VR and the current flow IR of a resistor is given by VR ¼ R  IR

ð1:44Þ

In a linear and time invariant (LTI) model, the resistance R is voltage independent and does not change over time. Resistors in circuits are represented by the symbol shown in Fig. 1.19. Conductors are another representation of resistors given by IG ¼ G  V G

ð1:45Þ

20

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vR(t) R

Fig. 1.20 Laplace transformation of a resistor

i R(t)

VR(s) R IR(s)

(a) Fig. 1.21 Thermal noise of a resistor

(b)

R

vn

Conductors are inverse of resistors and using them can simplify expressions written in forms of Kirchhoff’s current laws. Resistors can handle certain amounts of voltages and currents depending on their material type and physical structure. Above these certain levels, the product of resistor voltage and current creates a considerable amount of power dissipation that appears as heat. If the heat generation is not controlled by using an external coolant such as heat sinks, the resistor will experience a huge amount of thermal stress and will go into the breakdown. Different materials have different temperature coefficients, and their properties vary differently with the change in temperature. In resistors with positive temperature coefficients, ions move faster when temperature is increased and collide more randomly with the moving charges. Therefore, for these types of resistors the increase in temperature appears as the reduction of the current flow through the resistor. For linear time invariant resistors, the s-domain model after applying Laplace transformation is the same as time-domain model as shown in Fig. 1.20. The voltage and current of a resistor in s-domain are related by V ðsÞ ¼ R  IðsÞ

ð1:46Þ

The random movement of electric charges in a resistor creates a noise voltage drop across the resistor even when no external voltage is applied to the resistor. The noise model of a resistor is shown in Fig. 1.21. The thermal voltage noise of a resistor caused by the random movement of electrons with four degrees of freedom is given by vnR ¼

pffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi 4KTR V= Hz

ð1:47Þ

  Where K ¼ 1:38  1023 KJ is the Boltzmann’s coefficient and T ¼ 300 K is the absolute temperature in Kelvin. Over a given frequency range of Δf ¼ f2  f1 called the noise bandwidth, the variance of the noise voltage σ vnR is calculated by

1.6 Components

21

Fig. 1.22 Physical capacitor structure

distance: d area: A

ðf 2 jvnR j2 df ¼ 4KTR  Δf

σ vnR ¼

ð1:48Þ

f1

1.6.6

Capacitors

When a voltage is applied to a capacitor, it stores electric charges Q(t). Qðt Þ ¼ CV ðt Þ

ð1:49Þ

where C is the capacitor value called capacitance. Capacitors are realized using two parallel metal plates that are closely separated from each other, as shown in Fig. 1.22. The capacitance is given by C ¼ ε0 εr

A d

ð1:50Þ

 Where ε0 ¼ 8:854  1023 mF is the air permittivity, εr is the relative permittivity of the dielectric material between the two capacitor parallel plates with respect to air, A is the plate area measured in [m2], and d is the distance between the two plates measured in [m]. To increase the capacitance, dielectric materials with a large permittivity can be placed between the two capacitor plates, the plate area can be increased and the distance between the two plates can be decreased. In DC, a capacitor is like an open structure because there is no physical connection between its two terminals. When an external DC voltage is applied to the capacitor, as shown in Fig. 1.23, different positive and negative electric charges are stored at each capacitor plate and electric fields are created between the two plates. At each plate, similar charges push each other away increasing the charge density at each corner. Electric fields pass through the insulator that is placed between the capacitor plates ionizing the material. Above a certain limit, the insulator becomes short and conductive. If a large external voltage is applied to a capacitor, there will be an electric arc between the two plates of the capacitor causing breakdown.

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(a)

(b)

Fig. 1.23 Electric fields of a capacitor, (a) Positive charges on top plate and (b) Negative charges on top plate

vC

Fig. 1.24 Capacitor symbol

C iC When an AC voltage is applied to capacitor, the polarity and the number of charges stored on each capacitor plate vary and alternatingly change the direction of electric fields between the two plates. The changing electric fields between the two capacitor plates create varying magnetic flux and an AC current will flow through the capacitor. The capacitor symbol is shown in Fig. 1.24. The linear time invariant (LTI) relationship between the alternating voltage and the current of a capacitor is given by iC ðt Þ ¼

∂Qðt Þ ∂v ðt Þ ¼C C ∂t ∂t

ð1:51Þ

It is assumed that capacitance C is voltage independent and does not change over time. The capacitor voltage is calculated by 1 v C ð t Þ ¼ v C ð 0Þ þ C

ðt iC ðt Þdt

ð1:52Þ

0

The initial condition vC(0) is required to properly calculate the integral. For linear time invariant capacitors, the voltage and the current of a capacitor in s-domain are related by VC ðsÞ ¼

v ð 0Þ 1 1  ðIC ðsÞ þ CvC ð0ÞÞ ¼ IC ðsÞ þ C s sC sC

ð1:53Þ

1.6 Components

23

vC(t) C i C(t)

VC(s) 1/sC

1/sC

IC(s)

VC(s)

vC(0)/s

IC(s) CvC(0)

(a )

(b)

(c)

Fig. 1.25 (a) Time-domain and (b and c) Laplace transformations of a capacitor Fig. 1.26 (a) Shorting high frequency signals by shunt capacitors and (b) Blocking low frequency signals by sequential capacitors

node x

node x

1/sC node y

node x

1/sC

(a)

(b)

Fig. 1.27 Model of a capacitor with leakage current

V(s) 1/sC I(s)

G

Using the Laplace transformation, the capacitor differential equation is converted to a linear algebraic equation. The s-domain model after applying Laplace transformation is shown in Fig. 1.25. 1 The impedance of a capacitor is sC and is frequency dependent. When high and low frequency signals are applied to a circuit, capacitors might short the signal to ground or block it if they are placed in shunts or sequentially, as shown in Fig. 1.26. At high frequencies, the capacitor impedance will be very small and comparable to wires. If a high frequency signal appears at node x of a circuit as shown in Fig. 1.26a, the signal is shorted to ground and remains at the zero voltage. At low frequencies, capacitor impedance becomes very large and acts as an open. If a low frequency signal travels from node x to node y of a circuit, as shown in Fig. 1.26b, the signal will be blocked by the capacitor. When the dielectric material used between capacitor plates start to age due to constant ionization, it passes a low frequency current. This leakage is modeled by a resistor in parallel to the capacitor, as shown in Fig. 1.27. The quality factor Q of a capacitor is defined as the ratio of its reactance to its parallel conductance as given by Q¼

sC G

ð1:54Þ

24

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When the leakage current of the capacitor is zero, its parallel resistance becomes infinite and acts as an open. The quality factor of such an ideal capacitor becomes infinity. When the leakage current of the capacitor increases, its parallel resistance decreases and the capacitor quality factor drops.

1.6.7

Nonideal Switch

Modeling electronic components more accurately helps to better characterize the behavior of circuits. When a practical switch is in close “ON” position, it can be modeled by a resistor that represents the resistive loss of the switch contacts, as shown in Fig. 1.28a. When the switch is in open “OFF” position, it can be modeled by a capacitor that represents the electric field formed between the open terminals of the switch, as shown in Fig. 1.28b.

1.6.8

Inductors

When a current pass through an inductor, it stores magnetic flux ϕ(t). ϕðt Þ ¼ Liðt Þ

ð1:55Þ

where L is the inductor value called inductance. Straight wires have negligible inductances. To get large inductors, they are formed by wire windings. A coil inductor is shown in Fig. 1.29. The inductance L of the coil is approximately given by L¼N

ϕ I

ð1:56Þ

where N is number of turns, ϕ is magnetic flux, and I is the current. A solenoid inductor is shown in Fig. 1.30. Fig. 1.28 Modeling of nonideal switches, (a) Close position and (b) Open position

close

open

R

C

(a)

(b)

1.6 Components

25

Fig. 1.29 Coil inductor

iL

Fig. 1.30 Solenoid inductor

iL

The inductance L of the solenoid is approximately given by L ¼ μ0

N 2A l

ð1:57Þ

where N is number of turns, A is the winding area, l is the solenoid length, and μ0 is permeability of air and equal to 4π  107 [H/m]. A toroid inductor is shown in Fig. 1.31. The inductance L of the toroid is approximately given by L ¼ μ0 μr

N2A 2πr

ð1:58Þ

where N is number of turns, A is the winding area, r is the toroid average radius, μ0 is permeability of air and equal to 4π  107 [H/m], and μr is the relative permeability of the ferrite disc used to form the toroid inductor. Ferrites are materials with low reluctivity meaning that magnetic flux can easily pass through them and create a high-density flux environment.

26

1 Framework

Fig. 1.31 Toroid inductor

iL

vL

Fig. 1.32 Inductor symbol

L

iL In DC, an inductor is like a short structure because of the wire used to create the inductor. When an external DC current is applied to the inductor, magnetic flux appears inside inductor loops. When an AC current is applied to the inductor, the intensity and direction of magnetic flux varies. The changing magnetic flux creates varying electric fields and an AC voltage will appear across the inductor. The inductor symbol is shown in Fig. 1.32. The linear time invariant (LTI) relationship between the alternating voltage and the current of an inductor is given by vL ð t Þ ¼

∂ϕðt Þ ∂i ðt Þ ¼L L ∂t ∂t

ð1:59Þ

It is assumed that inductance L is current independent and does not change over time. The inductor current is calculated by 1 iL ðt Þ ¼ iL ð0Þ þ L

ðt vL ðt Þdt

ð1:60Þ

0

The initial condition iL(0) is required to properly calculate the integral. For linear time invariant inductors, the voltage and current of an inductor in s-domain are related by

 i ð0Þ VL ðsÞ ¼ sL  IL ðsÞ  LiL ð0Þ ¼ sL IL ðsÞ  L s

ð1:61Þ

1.6 Components

27

vL L

VL(s) sL

VL(s)

sL

iL

LiL(0)

L(s)

L(s)

iL(0)/s (a)

(b)

(c)

Fig. 1.33 (a) Time-domain and (b and c) Laplace transformations of an inductor Fig. 1.34 (a) Shorting low frequency signals by shunt inductors and (b) Blocking high frequency signals by sequential inductors

node x

node x

node x

sL

node y

sL

(a)

(b)

Fig. 1.35 Model of an inductor with wire resistance

sL

V(s) R

I(s) Using the Laplace transformation, the inductor differential equation is converted to linear algebraic equation. The s-domain model after applying Laplace transformation is shown in Fig. 1.33. The impedance of an inductor is sL and is frequency dependent. When low and high frequency signals are applied to a circuit, inductors might short the signal to ground or block it if they are placed in shunt or sequentially, as shown in Fig. 1.34. At low frequencies, the inductor impedance will be very small and comparable to wires. If a low frequency signal appears at node x of a circuit as shown in Fig. 1.34a, the signal is shorted to ground and remains at zero voltage. At high frequencies, capacitor impedance will be very large and acts as an open. If a high frequency signal travels from node x to node y of a circuit, as shown in Fig. 1.34b, the signal is blocked by the inductor. The resistance of the wire used to build inductors is modeled by a resistor in series with the inductor, as shown in Fig. 1.35. The quality factor of an inductor is defined as the ratio of its reactance to its series resistance as given by Q¼

sL R

ð1:62Þ

28

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When perfect conductors are used to build inductors, the series resistance of the inductor becomes zero and the quality factor of the inductor becomes infinite. When the inductor wire resistance increases due to skin effects at high frequencies or high wire resistivity or small cross-sectional area, the series resistance of the inductor increases and the inductor quality factor drops.

1.6.9

Transformers

When magnetic fluxes of an inductor (primary) pass through another inductor (secondary), they induce current in the secondary inductor. The percentage of fluxes that pass through the secondary inductor is called coupling factor (k) and change between 0 (no coupling) and 1 (full coupling). To achieve full coupling, the size of two inductors must be preferably equal and they must be placed as close as possible to each other, as shown in Fig. 1.36. The symbol of a transformer is shown in Fig. 1.37. Based on the winding directions, the two currents at primary and secondary can have the same direction such as flowing into the transformer. These two terminals are identified by two dots in transformer symbol. In order to analyze transformers, the coupling factor is converter to mutual inductance (M) by pffiffiffiffiffiffiffiffiffiffi M ¼ k L1 L2

ð1:63Þ

Fig. 1.36 Spiral transformer

iL1

Fig. 1.37 Transformer symbol

i L2

k

iL1

i L2

v L1

v L2

L1

L2

1.6 Components

29

Fig. 1.38 Transformer model

L1-M

i L1 vL1

L2-M

M

iL2 vL2

The equivalent transformer model is shown in Fig. 1.38. The transformer equation at its primary is given by vL1 ðt Þ ¼ L1

∂iL1 ðt Þ ∂i ðt Þ þ M L2 ∂t ∂t

ð1:64Þ

and the transformer equation at its secondary is given by vL2 ðt Þ ¼ M

∂iL1 ðt Þ ∂i ðt Þ þ L2 L2 ∂t ∂t

ð1:65Þ

The transformer current at primary is given by 0 iL1 ðt Þ ¼ iL1 ð0Þ þ

ðt

ðt

1

1 @L2 vL1 ðt Þdt þ M vL2 ðt Þdt A L1 L2  M 2 0

ð1:66Þ

0

and the transformer current at secondary is given by 0 t 1 ðt ð 1 @M vL1 ðt Þdt þ L1 vL2 ðt Þdt A iL2 ðt Þ ¼ iL2 ð0Þ þ L1 L2  M 2 0

ð1:67Þ

0

Initial conditions of iL1(0) and iL2(0) are required to calculate transformer currents properly.

1.6.10 Nonideal Sources Voltage and current sources have internal resistances. An ideal voltage source should be able to provide its expected voltage to its load regardless of the load resistance. This requires the voltage source to have an internal resistance much smaller than its load resistance. When the voltage of the source divides between the source and the load resistors, the voltage should mainly appear across the load. Therefore, a good voltage source should have a very small internal resistance. This

30

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Fig. 1.39 Modeling of the voltage source resistance

RS

RL

VS

source Fig. 1.40 Modeling of the current source resistance

load

RL IS

RS

source

load

small resistance cannot be modeled in parallel to the voltage source; otherwise, all current provided by the voltage source will pass through its own internal resistance rather than the load. The proper modeling of a voltage source will be adding a small resistance in series with the source, as shown in Fig. 1.39. On the other hand, an ideal current source should be able to provide its expected current to its load regardless of the load resistance. This requires the current source to have an internal resistance much larger than its load resistance. When the current divides between the source and the load resistors, all source current should flow through the load. Therefore, a good current source should have a very large internal resistance. This large resistance cannot be modeled in series to the current source; otherwise, all voltage provided by the current source will drop across its own internal resistance rather than the load. The proper modeling of a current source will be adding a large resistance in parallel with the source, as shown in Fig. 1.40.

1.6.11 Dependent Sources Dependent sources are controlled by the voltage drop across other circuit components or the current flow through them. A voltage-controlled voltage source is shown in Fig. 1.41. AV is the voltage-gain. A current controlled current source is shown in Fig. 1.42. AI is the current gain. A current controlled voltage source is shown in Fig. 1.43. Zm is the transimpedance gain. Other variations include transresistance gain Rm and transinductance gain sLm. A voltage-controlled current source is shown in Fig. 1.44. Ym is the transadmittance gain. Other variations include transconductance gain Gm and transcapacitance gain sCm.

1.6 Components

31

Fig. 1.41 Voltagecontrolled voltage source

IL VL

RS

RL

Fig. 1.42 Current controlled current source

AVVL

IL VL

RL

Fig. 1.43 Current controlled voltage source

IL VL

Fig. 1.44 Voltagecontrolled current source

RS

AIIL

RS

RL

ZmIL

IL VL

RS

RL YmVL

1.6.12 Diodes A PN diode is the simplest form of semiconductor devices and is made by depositing n-type and p-type materials into each other, as shown in Fig. 1.45. The boundary between n-type and p-type materials is called junction. Diode has two terminals. The terminal from the n-type material is called cathode and the terminal from the p-type material is called anode. The diffusion current flows the free electrons from the n-type material into the p-type material at the junction. The loss of electrons by the n-type material at the junction change the atoms to positively charged ions and the gain of electrons by the p-type material at the junction change the atoms to negatively charged ions. The ions at the junction create an area with immobile charges. This area is called depletion region, as shown in Fig. 1.46. Depletion region extends more into lower doped material. At equilibrium, the electron-flow is stopped and a built-in potential is formed in the depletion region. By applying an external voltage, characteristics of the diode can change. When the positive terminal of an external voltage source is connected to the cathode terminal of the diode, as shown in Fig. 1.47, diode becomes reverse bias. The external electric field generated by the voltage source increases the depth of the depletion region and opposes the electron movement making the current flow zero. If

32

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Fig. 1.45 A pn diode

n-type (cathode)

Fig. 1.46 Depletion region of the diode

n-type depletion region (cathode)

n-type depletion region (cathode)

junction

p-type (anode)

p-type (anode)

p-type (anode)

Ir≈0 Vr

Fig. 1.47 Diode in reverse bias operation

reverse bias voltage is increased more than a certain limit called breakdown voltage (VBR), a large area of n-type and p-type materials become depleted and a large number of charges accumulate around the depletion region. When these excessive number of charges suddenly pass through the depletion region, a large amount of current (called the avalanche current) is created that permanently damages the diode.

1.6 Components

33 n-type depletion region (cathode)

p-type (anode)

If Vf

Fig. 1.48 Diode in forward bias

vD

Fig. 1.49 Diode symbol

a

c

iD When the positive terminal of an external voltage source is connected to the anode terminal of the diode, as shown in Fig. 1.48, diode becomes forward bias. When the voltage of the external source reaches to the built-in junction voltage (VON) of the diode, the area of depletion region becomes negligible and the external electric field move charges through the junction. Increasing the voltage of the external source beyond the built-in junction voltage will exponentially increase the amount of current flow through the diode. If a very large voltage above a certain limit is applied to the diode in forward bias, the huge current passing through the diode will cause thermal runaway damaging the diode. To prevent this, a series resistance can be added to the diode in order to control the amount of the forward bias current that flows into the diode. The diode symbol is shown in Fig. 1.49. The device cross section of a PN diode built inside an n-well over a P-type silicon substrate is shown in Fig. 1.50. The substrate of the silicon wafer is p-type and low doped. The low doping concentration of the substrate makes it easier to deposit n-type materials on the surface. There are two diodes in the device cross section, as shown in Fig. 1.51. D1 is the main diode and D2 is the parasitic diode that exists because of fabrication steps to create D1. Because other semiconductor devices and components are usually built on the same substrate to lower the fabrication cost, the terminal voltages of the D1 diode must be isolated from other circuit devices and components built on the same substrate. Assuming all circuits are operating from a positive supply voltage (battery), then terminal voltages of all components built on the same substrate are limited

34

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Fig. 1.50 Diode cross section

bulk cathode anode cathode bulk

p+

n+

p+

n+

p+

cathode anode cathode

bulk

n-well

P--sub Fig. 1.51 Parasitic diode

bulk

p+

n+ n-well

p+

n+

p+

D1 D2: OFF

P--sub

between zero (ground) and the positive supply voltage. To isolate D1, D2 must be reverse bias. The n-well forms the cathode terminals of D1 and D2 and might have a varying voltage that changes from zero to the positive supply voltage because D1 is a circuit component that can have any voltage applied to its terminals. Therefore, the anode of D2 must be selected properly in order to reverse bias D2 and to isolate D1 terminal voltages from the rest of the circuit. To reverse bias D2, the bulk terminal connected to the P-type substrate that forms the D2 anode must be connected to the lowest voltage in the circuit, which is ground, as shown in Fig. 1.51. The main area that creates D1 (P+ anode and the n-well cathode) is called the intrinsic part of the diode and the rest of terminals and parasitic components that exist due to fabrication and isolation requirements are called the extrinsic parts of the diode. The top layout view of the diode is shown in Fig. 1.52. This view helps to calculate the junction area of the diode and to decide the connectivity (metal routing) between diode and other circuit components. To reduce the diode resistance, the anode is surrounded by cathode. The transfer characteristic of the diode is shown in Fig. 1.53.

1.6 Components

35

Fig. 1.52 Diode layout view

p n p+ anode cathode substrate

iD

Fig. 1.53 Transfer characteristic of a diode

VBR

vD

VON

Fig. 1.54 Diode model in reverse bias

Cj a

c

In reverse bias operation, VBR < vD < VON, iD  0 and diode is modeled by a capacitor, shown in Fig. 1.54. The diode junction capacitance Cj is given by Cj ¼ 

C

j0

D 1 þ VVON

0:5

ð1:68Þ

where Cj0 is the junction capacitance when no external voltage is applied to the diode and depends on the junction area, type, and doping concentration of materials used to build the diode. In forward bias operation, vD  VON and diode current is given by  VD  I D ¼ I S enV T  1

ð1:69Þ

36

1 Framework

where IS is the scaling current that change by temperature, junction area and doping concentration of the n-type and p-type materials, n is an empirical factor, and VT is the thermal voltage given by VT ¼

KT q

ð1:70Þ

  where K ¼ 1:38  1023 KJ is the Boltzmann’s coefficient, T is temperature measured in Kelvin, and q ¼ 1.602  1019 (C) is the electron charge in columb. The small-signal model of the diode is obtained by applying Taylor expansion series to the large-signal equation of the diode as 2

i D ¼ vD

3

∂I D vD 2 ∂ I D vD 3 ∂ I D þ þ þ ... 2! ∂V D 2 3! ∂V D 3 ∂V D

ð1:71Þ

and considering the small-signal operation, only the first term will be dominant. The approximate diode current equation is given by i D  vD

∂I D ¼ gd v D ∂V D

ð1:72Þ

where the diode conductance gd is calculated by gd ¼

∂I D I  D ∂V D nV T

ð1:73Þ

The diode model in forward bias is shown in Fig. 1.55. The diode conductance does not depend on the diode voltage. This is because diode characteristics in forward bias is nonlinear and the diode conductance does not follow the linear ohmic equations such as those in regular resistors. The large-signal equation of the diode does not include the signal delay as it passes through the diode. This delay is modeled by a capacitor that is obtained from diode device cross section and operation. The diffusion capacitance Cd presents the rate of change of charges accumulated at both sides of the depletion region with respect to change of diode voltage. When the diode voltage increases, the width of depletion region reduces and the diode current flow increases. As a result, charges accumulated at both sides of the depletion

Fig. 1.55 Diode model in forward bias

Cd a

gd

c

1.6 Components

37

region increase and the effect is seen as the existence of a capacitor at diode junction given by Cd ¼

∂ðI D :t Þ ¼ gd τ ∂V D

ð1:74Þ

where τ is the time constant of the diode and depends in its device cross section and doping profile. The shot noise of the diode generated at the PN junction is given by pffiffiffiffiffiffiffiffiffiffiffiffiffiffi ind ¼ 4KTgd ¼

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi I 4 qI D A= Hz 4KT D ¼ n nV T

ð1:75Þ

where ID is the DC biasing current of the diode, q is the electron charge, and n is an empirical factor that is usually equal to 2 in noise equation. The noise model of the diode in forward bias is shown in Fig. 1.56.

1.6.13 Bipolar Junction Transistors The device cross sections of n-type and p-type bipolar junction transistors (BJTs) are shown in Fig. 1.57.

Fig. 1.56 Noise model of the diode in forward bias

Cd a

c

gd

ind npn BJT bulk

p+

p+

n+ p+ p-well base

n+

Vsup

col lector base emitter base collector

collector base emitter base collector

n+

pnp BJT

Vsup

p+

n+

p+

n+

n-well collector

p+ n+ n-well base

p-well collector

D1: OFF

D2: OFF

P--sub

Fig. 1.57 Bipolar junction transistor cross section

D3: OFF

n_well

p+

bulk

n+

bulk

p+

38

1 Framework

Table 1.5 Different biasings of NPN transistors Region Conditions

Forward active VBE  VON VBC < VON

Saturation VBE  VON VBC  VON

n-type (emitter)

Cutoff VBE < VON VBC < VON

p-type (base)

IE

n-type (collector)

IC

IB

VBE

Reverse active VBE < VON VBC  VON

VBC

Fig. 1.58 The NPN BJT operation in forward active region

The intrinsic n-type BJT is formed by three regions made by n+ emitter junction, p-well base area, and the n-well collector area and is called NPN in abbreviation. The intrinsic p-type BJT is formed by three regions made by p+ emitter junction, n-well base area, and the p-well collector area and is called PNP in abbreviation. The p+ bulk terminals must connect the p-type substrate to the lowest voltage (ground) and the n+ bulk terminals must connect the n-well substrate to the highest voltage (supply voltage Vsup) in order to keep D1, D2, and D3 parasitic diodes OFF and isolate the terminal voltages of NPN and PNP transistors from the rest of the circuit components built on the same substrate. The NPN transistor is explained here. The PNP transistors are characterized very similarly by exchanging the n-type and the p-type materials and changing the direction of DC current flows and the polarity of DC voltages at transistor terminals. The intrinsic NPN transistor has two diodes (base-emitter and base-collector) and it can operate at four biasing regions, as listed in Table 1.5. In active operating region, shown in Fig. 1.58, the base-emitter diode is forward biased and conducts current. The base-collector diode is reverse bias and creates a strong electric field between collector and base terminals. The distance between the n-type emitter and the n-type collector is called the base width. If the base width is very narrow, electrons that move into base from emitter are easily moved into collector by the strong reverse bias electric field that exists between collector and base terminals. As a result, increasing the base-emitter voltage will increase the collector current of the transistor. The emitter current is equal to sum of the base and collector currents (IE ¼ IB + IC).

1.6 Components

39

Fig. 1.59 NPN transistor symbol

c IB

IC

VBE

IE

b

VCE

e Fig. 1.60 Transfer characteristics of NPN transistor

IC VBE5 VBE4 VBE3 VBE2 VBE1 cutoff

VCE

The ratio between collector current and the base current is the current gain (β f ¼ I C=I B ) of the transistor and directly depends on the narrow base width. In saturation region, both diodes are ON and there is no current gain amplification. In cutoff region, both diodes are OFF and all currents become zero. The operation of the transistor in reverse active region is similar to that in forward active but with a much lower current gain (βr) because the doping concentration of electrons in lowly doped collector is much less that those in emitter and this will directly impact the amount of current flow between emitter and collector terminals caused by the base-collector voltage. The NPN transistor symbol is shown in Fig. 1.59. The transfer characteristics of the NPN transistor is shown in Fig. 1.60. The current equations of the transistor are given by

   

V BC  V BE I S VVBCT V CE VT VT IC ¼ IS e  e e 1  1þ  βr VA

ð1:76Þ

and

IB ¼

    V BC 

I S VVBET I V e  1  S e VT  1  1 þ CE βf βr VA

ð1:77Þ

and

   

V BC  V BE I S VVBET V CE VT VT e 1  1þ IE ¼  IS e  e þ βf VA

ð1:78Þ

The dominant term in the collector current equation is given by

 V BE V I C ¼ I S e V T  1 þ CE VA

ð1:79Þ

40

1 Framework

The small-signal model of the transistor is obtained by applying Taylor expansion series to the large-signal equation of the transistor as ∂I C ∂I C 1 þ vCE þ ∂V BE ∂V CE 2!

 2 2 2 ∂ IC 1 2 ∂ IC 2 ∂ IC  vBE þ 2vBE vCE þ vCE þ 2 2 3! ∂V V ∂V BE ∂V CE BE CE

 3 3 3 3 ∂ IC ∂ IC 3 ∂ IC 2 2 3 ∂ IC  vBE þ 3vBE vCE þ 3vBE vCE þ vCE ∂V BE 3 ∂V BE 2 V CE ∂V BE V CE 2 ∂V CE 3

iC ¼ vBE

þ ... ð1:80Þ and considering the small-signal operation, only the first two terms will be dominant. The approximate collector current equation is given by iC  vBE

∂I C ∂I C þ vCE ¼ gm vBE þ go vCE ∂V BE ∂V CE

ð1:81Þ

where the transconductance gm is calculated by gm ¼

∂I C I  C V ∂V BE T

ð1:82Þ

And the output conductance go is calculated by go ¼

∂I C I  C V ∂V CE A

ð1:83Þ

The large signal equation of the transistor does not include the signal delay as it passes through the transistor. This delay is modeled by capacitors that are obtained from transistor device cross section and operation. The small-signal model of NPN transistors in cutoff active region is shown in Fig. 1.61. The small-signal model of NPN transistors in saturation region is shown in Fig. 1.62. Fig. 1.61 Small-signal model of NPN transistors in forward cutoff region

Cμ

b Cπ e

c Ccs

1.6 Components

41

Fig. 1.62 Small-signal model of NPN transistors in forward saturation region

gμ Cμ

b gπ

c

Cπ

Ccs

e Fig. 1.63 Small-signal model of NPN transistors in forward active region

Cμ

b gπ

Cπ

vπ

c

gmvπ

go

Ccs

e Table 1.6 Small-signal parameters of the NPN transistor in different operating regions

Cutoff

gπ ¼ 0 gμ ¼ 0 gm ¼ 0 go ¼ 0

Saturation

∂I B gπ ¼ ∂V ¼ VI BT BE ∂I B ∂V BC

gμ ¼ gm ¼ 0 go ¼ 0 Forward active

VEB < VON VCB < VON

¼

IB VT

∂I B gπ ¼ ∂V ¼ VI BT BE gμ ¼ 0 ∂I C B gm ¼ ∂V ¼ VI CT ¼ βI VT BE

VEB  VON VCB  VON

VEB  VON VCB < VON

∂I C go ¼ ∂V ¼ VI CA CE

The small-signal model of NPN transistors in forward active region is shown in Fig. 1.63. The small-signal parameters of the PNP transistor in different operating regions are listed in Table 1.6. where β  1 is the current gain, gm is the transconductance, VT is the thermal voltage, gπ is the base-emitter conductance, gμ is the base-emitter conductance, go is the output conductance, and VA is the early voltage of transistor. The top layout view of the NPN transistor is shown in Fig. 1.64. This view helps to calculate the junction areas of the transistor and to decide the connectivity (metal routing) between transistor and other circuit components. To reduce the base resistance, it is surrounded by emitter and collector from both sides. The capacitors of the PNP transistor in different operating regions are listed in Table 1.7.

42

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Fig. 1.64 NPN transistor layout view

p (n) n (p) p (n) n+ (p+) emitter base collector substrate

Table 1.7 Capacitors of NPN transistor in different operating regions

Cπ ¼ 

Cutoff

Cμ ¼ 

C

j0

0:5

V 1þV BE ON

C

j0

VEB < VON VCB < VON

0:5

V 1þV BC ON

C cs ¼ 

C

j0

0:5

V

1þV C

ON

C π ¼ gπ τ π Cμ ¼ gμτμ C j0 0:5 C cs ¼ 

Saturation

VEB  VON VCB  VON

V

1þV C

ON

Forward active

C π ¼ gπ τ π C j0 0:5 Cμ ¼ 

VEB  VON VCB < VON

V

1þV BC

ON

C cs ¼ 

C

j0

0:5

V

1þV C

ON

Where τπ is the time constant of the base-emitter diode and τμ is the time constant of the base-emitter diode. The noise of the NPN transistor in saturation region is modeled at base terminal, as shown in Fig. 1.65. At transistor base, noise is generated by shot noise and is given by inπ ¼

pffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi 2qI B A= Hz

ð1:84Þ

inμ ¼

pffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi 2qI B A= Hz

ð1:85Þ

and

where IB is the DC biasing current of the base and q is the electron charge.

1.6 Components

43

inμ

Fig. 1.65 Noise model of the NPN transistors in saturation region

gμ Cμ

b in π

gπ

Cπ

c Ccs

e Fig. 1.66 Noise model of the NPN transistors in active region

Cμ

b

in π

gπ

Cπ

vπ

gmvπ

c go ino

Ccs

e

The noise of NPN transistor in active region is modeled at base and collector terminals, as shown in Fig. 1.66. At transistor base, noise is generated by shot noise and flicker noise and is given by sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi K f I BA f inπ ¼ 2qI B þ A= Hz f

ð1:86Þ

where IB is the DC diasing current of the base, q is the electron charge, 1013 < Kf < 1016 and 0.5 < Af < 1.5. At transistor collector, noise is generated by shot noise and is given by ino ¼

pffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi 2qI C A= Hz

ð1:87Þ

where IC is the DC diasing current of the collector. The emitter terminal of the NPN transistor has lower DC voltage than the base and the collector terminals and the DC current flows out of the emitter terminal. The PNP transistor has similar operating concept and small-signal and noise models as those of the NPN transistor. However, the emitter terminal of the PNP transistor has higher DC voltage than the base and the collector terminals and the DC current flows into the emitter terminal, as shown in Fig. 1.67.

44

1 Framework

Fig. 1.67 The DC voltage polarity and the DC current flow of (a) NPN and (b) PNP transistors

c IB

b

e IC

VEB

b

VCE VBE

e

VCE IC

IB

IE

c

(a) n-type MOSFET bulk

p+

source gate drain

gate source

n+

n+ D1: OFF

n+ D2: OFF

(b) p-type MOSFET

Vsup

source gate drain

p+

n+

D3: OFF

IE

p+

gate source

p+

p+ D5: OFF

Vsup

D6: OFF

bulk

n+

bulk

p+

D7: OFF

n_well D4: OFF

P--sub

Fig. 1.68 Metal oxide semiconductor field effect transistor cross section

1.6.14 Metal Oxide Semiconductor Field Effect Transistors The cross section of n-type and p-type metal oxide semiconductor field effect transistors (MOSFETs) are shown in Fig. 1.68. The intrinsic n-type MOSFET is surrounded by gate-oxide, the n+ drain and the + n source junctions, and the p-type substrate and is called NMOS in abbreviation. The intrinsic p-type MOSFET is surrounded by gate-oxide, the p+ drain and the p+ source junctions, and the n-well substrate and is called PMOS in abbreviation. The p+ bulk terminals must connect the p-type substrate to the lowest voltage (ground) and the n+ bulk terminals must connect the n-well substrate to the highest voltage (supply voltage Vsup) in order to keep D1, D2, D3, D4, D5, D6, and D7 parasitic diodes OFF and isolate the terminal voltages of NMOS and PMOS transistors from the rest of the circuit components built on the same substrate. The NMOS transistor is explained here. The PMOS transistors are characterized very similarly by exchanging the n-type and the p-type materials and changing the direction of DC current flows and the polarity of DC voltages at transistor terminals. The operation of NMOS transistor is shown in Fig. 1.69. The NMOS transistor channel (area under gate oxide and between source and drain junctions) is p-type material and has free holes. As shown in Fig. 1.69a, the drain and source terminals are isolated by reverse biased diodes at these terminals. When the positive terminal of an external DC voltage source (VG) is applied to the gate, as shown in Fig. 1.69b, vertical electric fields are created at channel and

1.6 Components

45

bulk

source gate

drain

bulk

source

gate

VG

drain

electric field

(a)

(b )

VG

VG

bulk

source

gate

VDS

drain drain

electric field

(c)

bulk source

gate electric field

(d)

Fig. 1.69 Operation of NMOS transistor

electrons from the negative terminal of the external voltage source are attracted towards the channel surface. These electrons combine with existing holes of the p-type channel. At a certain gate voltage called the threshold voltage, the channel surface becomes depleted, as shown in Fig. 1.69b. By increasing the gate voltage above threshold voltage, more electrons appear at the channel surface and channel inverts, as shown in Fig. 1.69c. The inverted channel connects the n+ source and drain junctions together and a current can start to flow between these two junctions if they are connected to an external source, as shown in Fig. 1.69d. Although the source and the drain terminals are symmetrical, the terminal that has a voltage closer to the bulk is called the source of the transistor and the source terminal is physically located closer to the bulk terminal. The NMOS transistor symbol is shown in Fig. 1.70. If the bulk terminal is not physically available and NMOS transistors have only three terminals, the bulk and the source are internally connected inside the transistor package. The proper external DC voltages that must be applied to an NMOS transistor for proper operation and the direction of the current flow in transistor channel are shown in Fig. 1.70. The transfer characteristic of the NMOS transistor is shown in Fig. 1.71. From transfer characteristic, the NMOS transistor has three distinct operating regions. In cutoff, the NMOS transistor does not conduct current and is modeled by

46

1 Framework

Fig. 1.70 NMOS transistor symbol

d g

b VDS

VGS s Fig. 1.71 Transfer characteristic of the NMOS transistor

IDS

IDS VGS5 VGS4 VGS3 VGS2 VGS1 cutoff

VDS

capacitors among its terminals. In triode, the NMOS transistor acts like a conductance in addition to its capacitors. In saturation, the NMOS transistor acts like a nonideal current source in addition to its capacitors. The general large-signal equations that present the behavior of an NMOS transistor in all operating regions are given by V GS V th

ln 1 þ e V GSTeff

2KT ¼ q

1 þ 2e



!

2KT=q

V GS V th

ð1:88Þ

2KT=q

and V DSsat ¼ V GSTeff þ

2KT q

ð1:89Þ

and V DSeff ¼ V DSsat

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  0:5 V DSsat  V DS  Dn þ ðV DSsat  V DS  Dn Þ2 þ 4Dn V DSsat ð1:90Þ and

1.6 Components

47

Table 1.8 Current equations of long channel NMOS transistors Cutoff Triode

IDS ¼ 0 I DS ¼ μn C ox WL ðV GS  V th ÞV DS

Saturation

I DS ¼ 12 μn C ox WL ðV GS  V th Þ2 ð1 þ λn ðV DS  ðV GS  V th ÞÞÞ

VGS < Vth VGS > Vth VDS < VGS  Vth VGS > Vth VDS > VGS  Vth

! I DS

V DSeff W ¼ μn Cox V GSTeff V DSeff 1  0:5 L V GSTeff þ 2KT q

ð1:91Þ

For NMOS transistors with long channel lengths above 1μm, simpler forms of large-signal current can be used, as listed in Table 1.8. The small-signal model of the long channel transistor is obtained by applying Taylor expansion series to the large-signal long channel equation of the transistor as ∂I DS ∂I 1 þ vDS DS þ ∂V GS ∂V DS 2!

 2 2 2 ∂ I DS 1 2 ∂ I DS 2 ∂ I DS  vGS þ 2vGS vDS þ vDS þ 3! ∂V GS V DS ∂V GS 2 ∂V DS 2

 3 3 3 3 ∂ I DS ∂ I DS ∂ I DS 2 2 3 ∂ I DS  vGS 3 þ 3v v þ 3v v þ v GS DS GS DS DS ∂V GS 3 ∂V GS 2 V DS ∂V GS V DS 2 ∂V DS 3

iDS ¼ vGS

þ ... ð1:92Þ and considering the small-signal operation, only the first two terms will be dominant. The approximate collector current equation is given by iDS  vGS

∂I DS ∂I þ vDS DS ¼ gm vGS þ go vDS ∂V GS ∂V DS

ð1:93Þ

where the transconductance gm is calculated by gm ¼

∂I DS W  μn Cox ðV GS  V th Þ L ∂V GS

ð1:94Þ

And the output conductance gds is calculated by gds ¼

∂I DS  λn I DS ∂V DS

ð1:95Þ

48

1 Framework

Fig. 1.72 NMOS transistor model in cutoff region

g Cgs

Cgd

g

b

Cgd

Cgs

d gds

g

s

b

Cgd Vgs

Cgs

Cdb

Csb

s Fig. 1.74 NMOS transistor model in saturation region

Cdb

Csb s

Fig. 1.73 NMOS transistor model in triode region

d

d gmVgs

gbVbs

gds

Cdb

Csb b

The large signal equation of the transistor does not include the signal delay as it passes through the transistor. This delay is modeled by capacitors that are obtained from transistor device cross section and operation. The small-signal model of the NMOS transistor in cutoff region is shown in Fig. 1.72. The small-signal model of the NMOS transistor in triode region is shown in Fig. 1.73. The small-signal model of the NMOS transistor in saturation region is shown in Fig. 1.74. The gb current source is added to compensate the connection of the external DC voltage needed to invert the channel between gate and source terminals (schematic symbol shown in Fig. 1.70) instead of the gate and bulk terminals (layout cross section shown in Fig. 1.69). The small-signal parameters of the NMOS transistor in different operating regions are listed in Table 1.9. In triode, the drain and source biasing voltages are relatively small and equal and both drain and source junctions have a narrow depletion region making the physical appearance of the channel symmetrical. In saturation, the drain biasing voltage increases compared with the source voltage and the depletion region around drain junction gets wider and extends more into the lower doped substrate and pushes the channel away making the physical appearance of the channel asymmetrical, as shown in Fig. 1.75. Capacitors in NMOS transistors are created by the overlap length Lov (the extension of the source and drain junctions under the gate oxide), the gate oxide, and the depletion regions of the source and drain junctions, as shown Fig. 1.75.

1.6 Components

49

Table 1.9 Small-signal parameters of the NMOS transistor in different operating regions gm ¼ 0 gds ¼ 0 gm ¼ 0 ∂I DS gds ¼ ∂V ¼ μn C ox WL ðV GS  V th Þ DS

Cutoff Triode Saturation

∂I DS gm ¼ ∂V ¼ μn C ox WL ðV GS  V th Þ ¼ GS

VGS < Vth VGS > Vth VDS < VGS  Vth

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi DS 2μn C ox WL I DS ¼ V GS2IV th

VGS > Vth VDS > VGS  Vth

∂I DS gds ¼ ∂V ¼ λn I DS DS

bulk

p+

source gate drain

+ Xj n

bulk

n+

P--sub

p+

source gate drain

+ Xj n

bulk

n+

P--sub

source gate drain

+ Xj n

p+

n+

P--sub

(a)

(b )

( c)

Fig. 1.75 Capacitors of NMOS transistor in (a) Cutoff, (b) Triode, and (c) Saturation

gate

L+2Lov

Δk

bulk

Δk

source

gate

source

bulk

Wk

Δk

drain

Fig. 1.76 Metal oxide semiconductor field effect transistor layout view

L+2Lov

The top layout view of an NMOS transistor is shown in Fig. 1.76. This view helps to calculate the junction areas of the transistor and to decide the connectivity (metal routing) between the transistor and other circuit components. To reduce the size of transistor capacitors, multi-finger layout can be used in which a transistor is breaking down into smaller parallel transistors. By choosing even number of fingers, drain capacitors are reduced and by choosing odd number of fingers, source capacitors are reduced compared to a single-finger transistor. Multiple gates, sources, and drains of the multi-finger transistor are connected using metal routings.

50

1 Framework

Table 1.10 Capacitors of NMOS transistor in different operating regions for a one-finger layout Cutoff

Triode

Saturation

Cgb ¼ WLCox Cgs ¼ WLovCox Cgd ¼ WLovCox Cdb ¼ (ΔW + 2(Δ + W )Xj)Cjd Csb ¼ (ΔW + 2(Δ + W )Xj)Cjs Cgb ¼ 0 C gs ¼ WLov C ox þ 12 WLCox C gd ¼ WLov C ox þ 12 WLCox C db ¼ ðΔ þ L=2ÞW þ 2ðΔ þ W ÞX j ÞC jd C sb ¼ ðΔ þ L=2ÞW þ 2ðΔ þ W ÞX j ÞC js Cgb ¼ 0 C gs ¼ WLov C ox þ 23 WLCox C gd ¼ WLov C ox þ 13 WLCox C db ¼ ðΔ þ L=3ÞW þ 2ðΔ þ W ÞX j ÞC jd C sb ¼ ðΔ þ 2L=3ÞW þ 2ðΔ þ W ÞX j ÞC js

Fig. 1.77 Noise model of the NMOS transistor in triode region

g

VGS < Vth

VGS > Vth VDS < VGS  Vth

VGS > Vth VDS > VGS  Vth

Cgd

Cgs

gds s

d in d

Cdb

Csb b

Wk is the channel width of each finger and Δk is the junction length of each finger. Depending on design requirements, different junctions can have different length in the layout. From the layout, the total channel width W of the transistor and the total junction length Δ of source and drain terminals can be calculated in order to find the capacitors of the transistor. The capacitors of the NMOS transistor in different operating regions for a one-finger layout are listed in Table 1.10. The noise of NMOS transistor in triode region is modeled at drain terminal, as shown in Fig. 1.77. At transistor drain, noise is generated by the thermal noise of the channel and is given by ind ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi 4KTgds A= Hz

ð1:96Þ

 where K ¼ 1:38  1023 KJ and T ¼ 300 K is the temperature in Kelvin. The noise of NMOS transistor in saturation region is modeled at drain terminal, as shown in Fig. 1.78. At transistor drain, noise is generated by the thermal noise and the flicker noise of the channel and is given by

1.6 Components

g Cgs

51

Cgd Vgs

d gmVgs

gbVbs

gds

ind

Cdb

Csb

s

b

Fig. 1.78 Noise model of the NMOS transistors in saturation region Fig. 1.79 The DC voltage polarity and the DC current flow of (a) NMOS and (b) PMOS Transistors

VSG s

d g

b VDS

VGS s

IDS

(a) sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi K f gm 2 2 A= Hz ind ¼ 4KTgm þ 2 3 WLC ox f

g

b VSD d ISD (b)

ð1:97Þ

 where K ¼ 1:38  1023 KJ and T ¼ 300 K is the temperature in Kelvin and 1022 < Kf < 1027. The source terminal of the NMOS transistor has lower DC voltage than the gate and the drain terminals and the DC current flows out of the source terminal. The PMOS transistor has similar operating concept and small-signal and noise models as those of the NMOS transistor. However, the source terminal of the PMOS transistor has higher DC voltage than the gate and the drain terminals and the DC current flows into the source terminal, as shown in Fig. 1.79. Choosing a long channel current equation given by the following expression rather than the expression presented in Table 1.8 results in discontinuity at VDS ¼ VGS  Vth in the transfer characteristics and must be avoided (Figs. 1.80 and 1.81). 1 W I DS ¼ μn C ox ðV GS  V th Þ2 ð1 þ λn V DS Þ 2 L

ð1:98Þ

The following code shows the discontinuity at VDS ¼ VGS  Vth caused by the (1.98) expression given above.

52

1 Framework

Fig. 1.80 IV curves for I DS ¼ 12 μn C ox WL ðV GS  V th Þ2 ð1 þ λn V DS Þ

Fig. 1.81 IV curves for I DS ¼ 12 μn C ox WL ðV GS  V th Þ2 ð1 þ λn ðV DS  ðV GS  V th ÞÞÞ

1.7 LTI/LTV/NTI/NTV

53

L=45e-09; %channel length nf=10; %number of fingers W=1e-06; %finger width size un=0.135; %electron mobility Vth=0.4; %threshold voltage Ln=0.1; %n-channel length modulation e0=8.854e-12; %air permittivity er=3.9; %3.9 for low-k and 12 for high-k materials tox=1.6e-09; %gate oxide thickness Cox=e0*er/tox; %oxide capacitance per unit area Vdd=1.5; %power supply %generate I-V curves Vgs=linspace(0,Vdd,151); Vds=linspace(0,Vdd,151); Ids=zeros(length(Vgs),length(Vds)); for k=1:length(Vgs) %use the following for Ids=0.5*un*Cox*(W*nf/L)*((Vgs(k)-Vth).^2)* (1+Ln*(Vds-(Vgs(k)-Vth))) Ids(k,:)=((Vgs(k)>Vth & Vds>0 & VdsVth & Vds>Vgs(k)-Vth & VdsVth & Vds>0 & VdsVth & Vds>Vgs(k)-Vth & Vds 0Þ ¼ 2



j k ωt ωt  þ 0:5  1 2π 2π

ð3:33Þ

where b c is the floor function. The circuit parameters are listed in Table 3.8. The voltage-gain of the circuit is given by v2 G1 þ sC 1 ¼ v1 G1 þ G2 þ sC 1

ð3:34Þ

The voltage at node 1 is given by   2πs 2πs ω  s 1  e  2se ω π   v1 ¼ 2πs s2 1  e ω ω

ð3:35Þ

136

3 Transient Analysis

Fig. 3.7 RC circuit

G1 1

C1

v1

Table 3.8 Parameter values

G1 1 mA/V

C1 1 nF

G2 1 mA/V

2 G2

ω 2π  1.6  105 rad/s

and the output voltage at node 2 is given by ω v2 ¼

π s



 2πs 2πs 1  e ω  2se ω G1 þ sC 1    2πs G þ G2 þ sC 1 2 1 s 1e ω

ð3:36Þ

The periodic voltage at node 2 with a period of 2π ω is given by   2πs v2p ¼ v2  1  e ω     2πs 2πs ω G1 þ sC 1 ¼  s 1  e ω  2se ω  2 π s ðG1 þ G2 þ sC 1 Þ

ð3:37Þ

That is fractionally expanded as v2p ¼

  2πs ω 1e ω π G1 1 C 1 G2 1 C 1 G2 1   þ    G1 þ G2 s2 ðG1 þ G2 Þ2 s ðG1 þ G2 Þ2 s þ G1 þG2 C1 !   2πs G1 1 G2 1  1þe ω  þ  G1 þ G2 s G1 þ G2 s þ G1 þG2 C1

!

ð3:38Þ

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as

3.5 Periodic Capacitive Circuits

137

Fig. 3.8 Node voltages

0 1 ðG1 þG2 Þ t ω @ G1 t C 1 G2 C1 G2 e C1 A v2p ðt Þ ¼ þ  π G1 þ G2 ðG1 þ G2 Þ2 ðG1 þ G2 Þ2 0 1 ðG1 þG2 Þ   t C1 2π G1 G e A  δðt Þ  δ t  @ þ 2 ω G1 þ G2 G1 þ G2 

   2π  δðt Þ þ δ t  ω

ð3:39Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

ð3:40Þ

The node voltages of the circuit are plotted in Fig. 3.8. Using the following template and the MATLAB codes provided in the previous sections, write a code to simulate the circuit shown in this section by solving the time-domain finite difference equations obtained from the Kirchhoff’s current law.

G1=1e-03; G2=1e-03; C1=1e-09; gz=1e03; T0=1/f0; XS=(4-(2+s*T0)*(1+exp(-s*T0)))/(T0*s^2*(1-exp(-s*T0))); xs=sawtooth(2*pi*t0(k)/T0);

138

3 Transient Analysis

%s-domain equations KCL(1)=s*C1*(v1-v2)+G1*(v1-v2)+gz*(v1-XS); KCL(2)=s*C1*(v2-v1)+G2*v2+G1*(v2-v1)]; %time-domain equations KCL(1)=C1*diff([v0(k-1,1)-v0(k-1,2) v(1)-v(2)])/diff(t0(k-1:k)) +G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=C1*diff([v0(k-1,2)-v0(k-1,1) v(2)-v(1)])/diff(t0(k-1:k)) +G2*v(2)+G1*(v(2)-v(1));

3.5.3

Circuit 3

A two-node circuit, shown in Fig. 3.9, will be analyzed in this example. Capacitors are initially discharged (vC1(0) ¼ 0 and vC2(0) ¼ 0). The input node 1 is connected to a staircase waveform given by v 1 ð t > 0Þ ¼ 2

j

ωt 2π

k

ð3:41Þ

where b c is the floor function. The circuit parameters are listed in Table 3.9. The voltage-gain of the circuit is given by v2 G1 þ sC 1 ¼ v1 G 1 þ s ð C 1 þ C 2 Þ

ð3:42Þ

The voltage at node 1 is given by

Fig. 3.9 RC circuit

G1 1

v1

Table 3.9 Parameter values

G1 1 mA/V

C1 1 nF

C2 1 nF

C1

2 C2

ω 2π  105 rad/s

3.5 Periodic Capacitive Circuits

139 2πs

1:5e ω  1  v1 ¼  2πs s 1e ω

ð3:43Þ

and the output voltage at node 2 is given by 2πs

1:5e ω  1 G1 þ sC 1  v2 ¼  2πs G þ sðC 1 þ C 2 Þ 1 s 1e ω

ð3:44Þ

The periodic voltage at node 2 with a period of 2π ω is given by     2πs 2πs v2p ¼ v2  1  e ω ¼ 1:5e ω  1 

G1 þ sC 1 sðG1 þ sðC 1 þ C2 ÞÞ

ð3:45Þ

That is fractionally expanded as 

v2p ¼ 1:5e

2πs ω

!



1 

1 C2 1   s C 1 þ C 2 s þ G1

ð3:46Þ

C1 þC 2

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as  v2p ðt Þ ¼ 1 

G1 t C2 eC1 þC2 C1 þ C2

     2π  δ ðt Þ  1:5δ t  ω

ð3:47Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

ð3:48Þ

The node voltages of the circuit are plotted in Fig. 3.10. Using the following template and the MATLAB codes provided in the previous sections, write a code to simulate the circuit shown in this section by solving the time-domain finite difference equations obtained from the Kirchhoff’s current law.

G1=1e-03; C1=1e-09; C2=1e-09; gz=1e03; XS=(1/np)*2*(exp(-s*T0)/(s*(1-exp(-s*T0)))); xs=(1/np)*2*floor(t0(k)/T0);

140

3 Transient Analysis

Fig. 3.10 Node voltages

%s-domain equations KCL(1)=G1*(v1-v2)+s*C1*(v1-v2)+gz*(v1-XS); KCL(2)=G1*(v2-v1)+s*C1*(v2-v1)+s*C2*(v2-0)]; %time-domain equations KCL(1)=G1*(v(1)-v(2))+C1*diff([v0(k-1,1)-v0(k-1,2) v(1)-v(2)])/ diff(t0(k-1:k))+gz*(v(1)-xs); KCL(2)=G1*(v(2)-v(1))+C1*diff([v0(k-1,2)-v0(k-1,1) v(2)-v(1)])/ diff(t0(k-1:k))+C2*diff([v0(k-1,2) v(2)])/diff(t0(k-1:k));

3.6

Periodic Inductive Circuits

Circuits that include inductors are solved by nodal equations that include differential equations. A few examples and their accurate and approximate solutions are provided here in the presence of periodic input signals.

3.6.1

Circuit 1

A two-node circuit, shown in Fig. 3.11, will be analyzed in this example. The inductor is initially disfluxed (iL1(0) ¼ 0) and acts as a short circuit (v2(0) ¼ v1(0)). The input node 1 is connected to the absolute of a sinusoidal waveform given by v1 ðt > 0Þ ¼ j sin ðωt Þj The circuit parameters are listed in Table 3.10.

ð3:49Þ

3.6 Periodic Inductive Circuits

141

Fig. 3.11 RL circuit

1

v1

Table 3.10 Parameter Values

G1 1 mA/V

Table 3.11 Numerical values to calculate circuit response

tk 0 1.25 μs 2.5 μs 3.75 μs 5 μs 6.25 μs 7.5 μs 8.75 μs 10 μs ⋮

v1(tk) 0V 0.70711 V 1V 0.70711 V 0V 0.70711 V 1V 0.70711 V 0V ⋮

2 G1

ω 2π  105 rad/s

L1 1 mH

k 1 2 3 4 5 6 7 8 9 ⋮

L1

v2(tk) 0 V (initial condition) 0.39284 V 0.73015 V 0.71735 V 0.31882 V 0.53454 V 0.79313 V 0.74534 V 0.33126 V ⋮

The inductor voltage is obtained by vL1 ðt Þ ¼ L1

diL1 ðt Þ dðG1 v2 ðt ÞÞ ¼ L1 ¼ v1 ðt Þ  v2 ðt Þ dt dt

ð3:50Þ

The circuit equation has derivatives and the voltage-gain vv21 ððttÞÞ cannot be directly calculated using linear algebra. To find voltage at output node 2, the Eq. (3.50) can be solved numerically as L1 G1

ðv2 ðt k Þ  v2 ðt k1 ÞÞ ¼ v1 ð t k Þ  v2 ð t k Þ t k  t k1

ð3:51Þ

v1 ðt k Þðt k  t k1 Þ þ L1 G1 v2 ðt k1 Þ L1 G1 þ ðt k  t k1 Þ

ð3:52Þ

that simplifies to v2 ð t k Þ ¼

and the voltage at output node 2 is numerically obtained, as shown in Table 3.11. To increase accuracy, time steps must be reduced that results in a slower simulation. The following MATLAB code solves the time-domain finite difference equations of this example obtained from the Kirchhoff’s current law.

142

3 Transient Analysis

global k v0 t0 T0 G1 L1 gz f0=1e05; np=5; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; N=np*nt; n=2; G1=1e-03; L1=1e-03; gz=1e03; T0=1/f0; t0=time; v0=zeros(N,n); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'Display','off'); c=char(''); tstart=tic; for k=3:N v0(k,1:n)=real(fsolve(@TRsim,v0(k-1,:),opts)); pause(0.01) fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*k/N)),' percent done! ']); fprintf(c) end fprintf('\n') fprintf(['elapsed time: ',num2str(toc(tstart))]); fprintf('\n') plot(time,v0) function KCL=TRsim(v) global k v0 t0 T0 G1 L1 gz xs=abs(sin(2*pi*t0(k)/T0)); KCL(1)=(1/L1)*((v(1)-v(2))*diff(t0(k-1:k))+sum((v0(2:k-1,1)-v0(2: k-1,2)).*diff(t0(1:k-1)).',1))+gz*(v(1)-xs); KCL(2)=G1*v(2)+(1/L1)*((v(2)-v(1))*diff(t0(k-1:k))+sum((v0(2:k1,2)-v0(2:k-1,1)).*diff(t0(1:k-1)).',1)); End

And the voltage at node 2 follows the absolute of a sinusoidal waveform. Obtaining node voltages in terms of expressions rather than numbers can provide more accuracy and insight on how the circuit functions. To find the voltage expression at node 2, Laplace transformation is applied to differential equation (3.50).

3.6 Periodic Inductive Circuits

143

L1 G1 sv2 ¼ v1  v2 )

v2 1 ¼ v1 1 þ sL1 G1

ð3:53Þ

For the absolute of the sinusoidal input, the voltage at node 1 is given by  πs 2 1þeω ω v1 ¼ 2  2πs s þ ω2 1e ω

ð3:54Þ

and the output voltage at node 2 is given by  πs 2 1þeω ω 1 v2 ¼ 2   2πs 2 1 þ sL s þω 1 G1 1e ω

ð3:55Þ

The periodic voltage at node 2 with a period of 2π ω is given by v2p

  2πs ¼ v2  1  e ω ¼

 πs 2 1þeω ω  s2 þ ω2 1 þ sL1 G1

ð3:56Þ

That is fractionally expanded as πs

v2p ¼

2πs

1 þ 2e ω þ e ω 1 þ ðωL1 G1 Þ2 

ωL1 G1 0:5ð j  ωL1 G1 Þ 0:5ð j þ ωL1 G1 Þ  þ s þ jω s  jω s þ L11G1

! ð3:57Þ

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as

v2p ðt Þ ¼

  t sin ðωt Þ  ωL1 G1 cos ðωt Þ  eL1 G1 1 þ ðωL1 G1 Þ2      π 2π  δðt Þ þ 2δ t  þδ t ω ω

ð3:58Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

ð3:59Þ

The node voltages of the circuit are plotted in Fig. 3.12. The following MATLAB code applies the inverse Laplace transformation to the partial fraction decomposition of the s-domain nodal voltage signals in this example.

144

3 Transient Analysis

Fig. 3.12 Node voltages

syms v1 v2 syms i1 i2 syms s t syms G1 L1 gz XS Vvec=[v1 v2]; Ivec=[i1 i2]; equ=[i1==(1/(s*L1))*(v1-v2)+gz*(v1-XS);... i2==G1*v2+(1/(s*L1))*(v2-v1)]; [A,B]=equationsToMatrix(-subs(equ,Ivec,zeros(1,length(Ivec))), Vvec); f0=1e05; np=5; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; N=np*nt; n=2; G1=1e-03; L1=1e-03; gz=1e03; T0=1/f0; XS=(2*pi/T0/(s^2+(2*pi/T0)^2))*(1+exp(-s*T0/2))^2; X=sym.empty(0,1); x=cell.empty(0,1); for k=1:n C=A; C(:,k)=B;

3.6 Periodic Inductive Circuits

145

X(k)=vpa(partfrac(simplifyFraction(det(eval(C))/det(eval (A)))),4); x{k}=double(subs(vpa(ilaplace(X(k),s,t),4),t,time.')).*ones (length(time),1); end y=x; for k1=1:n for k2=1:(np/(T0*f0))-1 z=circshift(x{k1},k2*nt); z(1:k2*nt)=0; y{k1}=y{k1}+z; end end plot(time,cell2mat(y))

3.6.2

Circuit 2

A two-node circuit, shown in Fig. 3.13, will be analyzed in this example. The inductor is initially disfluxed (iL1(0) ¼ 0). The input node 1 is connected to a backward sawtooth waveform given by v 1 ð t > 0Þ ¼ 1  2



j k ωt ωt  þ 0:5 2π 2π

ð3:60Þ

where b c is the floor function. The circuit parameters are listed in Table 3.12. The voltage-gain of the circuit is given by v2 1 þ sG1 L1 ¼ v1 1 þ sL1 ðG1 þ G2 Þ

ð3:61Þ

Fig. 3.13 RL circuit

G1 1

v1

Table 3.12 Parameter Values

G1 1 mA/V

L1 1 mH

G2 1 mA/V

L1

2 G2

ω 2π  1.6  105 rad/s

146

3 Transient Analysis

The voltage at node 1 is given by

v1 ¼

2se

2πs ω

   2πs þ s  ωπ 1  e ω   2πs s2 1  e ω

ð3:62Þ

and the output voltage at node 2 is given by

v2 ¼

2se

2πs ω

   2πs þ s  ωπ 1  e ω 1 þ sG1 L1    2πs 1 þ sL1 ðG1 þ G2 Þ 2 s 1e ω

ð3:63Þ

The periodic voltage at node 2 with a period of 2π ω is given by   2πs v2p ¼ v2  1  e ω   2πs   2πs ω 1 þ sG1 L1 ¼ 2se ω þ s  1e ω  2 π s ð1 þ sL1 ðG1 þ G2 ÞÞ

ð3:64Þ

That is fractionally expanded as v2p

  2πs ω 1 G2 L1 G2 L1 1e ω ¼  þ π s s2 s þ L1 ðG11þG2 Þ ! 1 G2 1    s G1 þ G2 s þ L ðG 1þG Þ 1 1 2

!

  2πs þ 1þe ω ð3:65Þ

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as v2p ðt Þ ¼

      t ω 2π t  G2 L1 1  eL1 ðG1 þG2 Þ  δðt Þ  δ t  π ω      t G2 2π þ 1 eL1 ðG1 þG2 Þ  δðt Þ þ δ t  ω G1 þ G2

ð3:66Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

The node voltages of the circuit are plotted in Fig. 3.14.

ð3:67Þ

3.6 Periodic Inductive Circuits

147

Fig. 3.14 Node voltages

Using the following template and the MATLAB codes provided in the previous sections, write a code to simulate the circuit shown in this section by solving the time-domain finite difference equations obtained from the Kirchhoff’s current law.

G1=1e-03; G2=1e-03; L1=1e-03; gz=1e03; XS=((2+s*T0)*(1+exp(-s*T0))-4)/(T0*s^2*(1-exp(-s*T0))); xs=-sawtooth(2*pi*t0(k)/T0); %s-domain equations KCL(1)= (1/(s*L1))*(v1-v2)+G1*(v1-v2)+gz*(v1-XS); KCL(2)= (1/(s*L1))*(v2-v1)+G1*(v2-v1)+G2*v2]; %time-domain equations KCL(1)=(1/L1)*((v(1)-v(2))*diff(t0(k-1:k))+sum((v0(2:k-1,1)-v0(2: k-1,2)).*diff(t0(1:k-1)).',1))+G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=(1/L1)*((v(2)-v(1))*diff(t0(k-1:k))+sum((v0(2:k-1,2)-v0(2: k-1,1)).*diff(t0(1:k-1)).',1))+G1*(v(2)-v(1))+G2*v(2); end

3.6.3

Circuit 3

A two-node circuit, shown in Fig. 3.15, will be analyzed in this example. Inductors are initially disfluxed (iL1(0) ¼ 0 and iL2(0) ¼ 0). The input node 1 is connected to a backward staircase waveform given by

148

3 Transient Analysis

Fig. 3.15 RL circuit

G1 L1

1

v1

Table 3.13 Parameter values

G1 10 mA/V

L1 1 mH

v 1 ð t > 0Þ ¼ 1  2

j

L2

ω 2π  105 rad/s

L2 1 mH

ωt 2π

2

k

ð3:68Þ

where b c is the floor function. The circuit parameters are listed in Table 3.13. The voltage-gain of the circuit is given by L2 ð1 þ sG1 L1 Þ v2 ¼ v1 L1 þ L2 þ sG1 L1 L2

ð3:69Þ

The voltage at node 1 is given by 2πs

1  1:5e ω  v1 ¼  2πs s 1e ω

ð3:70Þ

and the output voltage at node 2 is given by 2πs

L2 ð1 þ sG1 L1 Þ 1  1:5e ω  v2 ¼  2πs L 1 þ L2 þ sG1 L1 L2 s 1e ω

ð3:71Þ

The periodic voltage at node 2 with a period of 2π ω is given by     2πs 2πs v2p ¼ v2  1  e ω ¼ 1  1:5e ω 

L2 ð1 þ sG1 L1 Þ sðL1 þ L2 þ sG1 L1 L2 Þ

ð3:72Þ

That is fractionally expanded as v2p

  2πs ¼ 1  1:5e ω 

! L2 1 L1 1  þ  L1 þ L2 s L1 þ L2 s þ GL1 LþLL2

1 1 2

ð3:73Þ

3.6 Periodic Inductive Circuits

149

Fig. 3.16 Node voltages

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as  v2p ðt Þ ¼

ðL1 þL2 Þt L2 L1 þ e G1 L1 L2 L1 þ L2 L1 þ L2

    2π  δðt Þ  1:5δ t  ω

ð3:74Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

ð3:75Þ

The node voltages of the circuit are plotted in Fig. 3.16. Using the following template and the MATLAB codes provided in the previous sections, write a code to simulate the circuit shown in this section by solving the time-domain finite difference equations obtained from the Kirchhoff’s current law.

G1=1e-02; L1=1e-03; L2=1e-03; gz=1e03; XS=-(1/np)*2*(exp(-s*T0)/(s*(1-exp(-s*T0)))); xs=-(1/np)*2*floor(t0(k)/T0); %s-domain equations KCL(1)=(1/(s*L1))*(v1-v2)+gz*(v1-XS)+G1*(v1-v2); KCL(2)=(1/(s*L1))*(v2-v1)+(1/(s*L2))*v2+G1*(v2-v1)];

150

3 Transient Analysis

%time-domain equations KCL(1)=(1/L1)*((v(1)-v(2))*diff(t0(k-1:k))+sum((v0(2:k-1,1)-v0(2: k-1,2)).*diff(t0(1:k-1)).',1))+gz*(v(1)-xs)+G1*(v(1)-v(2)); KCL(2)=(1/L1)*((v(2)-v(1))*diff(t0(k-1:k))+sum((v0(2:k-1,2)-v0(2: k-1,1)).*diff(t0(1:k-1)).',1))+(1/L2)*(v(2)*diff(t0(k-1:k))+sum (v0(2:k-1,2).*diff(t0(1:k-1)).',1))+G1*(v(2)-v(1));

3.7

Circuits with Both Capacitors and Inductors

Circuits that include both capacitors and inductors are solved by nodal equations that might include both differential and integral equations. A few examples and their accurate and approximate solutions are provided here.

3.7.1

Circuit 1

A two-node circuit, shown in Fig. 3.17, will be analyzed in this example. The inductor is initially disfluxed (iL1(0) ¼ 0) and the capacitor is initially discharged (vC1(0) ¼ 0). The input node 1 is connected to a square waveform given by v1 ðt > 0Þ ¼ ð1Þb π c ωt

ð3:76Þ

where b c is the floor function. The circuit parameters are listed in Table 3.14. The voltage-gain of the circuit is given by v2 1 ¼ v1 1 þ s2 L1 C1

ð3:77Þ

The voltage at node 1 is given by

Fig. 3.17 LC circuit

1

v1

Table 3.14 Parameter values

L1 1 mH

C1 1 nF

L1

2 C1

ω 2π  105 rad/s

3.7 Circuits with Both Capacitors and Inductors

151

 πs 2 1eω   v1 ¼ 2πs s 1e ω

ð3:78Þ

and the output voltage at node 2 is given by  πs 2 1eω 1   v2 ¼ 2L C 2πs 1 þ s 1 1 s 1e ω

ð3:79Þ

The periodic voltage at node 2 with a period of 2π ω is given by v2p

 πs 2   1eω 2πs ω ¼ v2  1  e ¼ sð1 þ s2 L1 C1 Þ

ð3:80Þ

That is fractionally expanded as v2p

  πs 2πs ¼ 1  2e ω þ e ω 

! 1 0:5 0:5  j ffi j ffi s s þ pffiffiffiffiffiffiffi s  pffiffiffiffiffiffiffi L1 C 1

ð3:81Þ

L1 C 1

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as      π 2π v2p ðt Þ ¼ ð1  cos ðωt ÞÞ  δðt Þ þ 2δ t  þδ t ω ω

ð3:82Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

ð3:83Þ

The node voltages of the circuit are plotted in Fig. 3.18. The following MATLAB code applies the inverse Laplace transformation to the partial fraction decomposition of the s-domain nodal voltage signals in this example. It also solves the time-domain finite difference equations of this example obtained from the Kirchhoff’s current law.

global k v0 t0 T0 C1 L1 gz syms v1 v2 syms i1 i2

152

3 Transient Analysis

Fig. 3.18 Node voltages

syms s t syms C1 L1 gz XS Vvec=[v1 v2]; Ivec=[i1 i2]; equ=[i1==(1/(s*L1))*(v1-v2)+gz*(v1-XS);... i2==(1/(s*L1))*(v2-v1)+s*C1*v2]; [A,B]=equationsToMatrix(-subs(equ,Ivec,zeros(1,length(Ivec))), Vvec); f0=1e05; np=5; nt=1001; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; N=np*nt; n=2; C1=1e-09; L1=1e-03; gz=1e03; T0=1/f0; XS=(1-exp(-s*T0/2))^2/s; X=sym.empty(0,1); x=cell.empty(0,1); for k=1:n C=A; C(:,k)=B; X(k)=vpa(partfrac(simplifyFraction(det(eval(C))/det(eval (A)))),4); x{k}=double(subs(vpa(ilaplace(X(k),s,t),4),t,time.')).*ones

3.7 Circuits with Both Capacitors and Inductors

153

(length(time),1); end y=x; for k1=1:n for k2=1:(np/(T0*f0))-1 z=circshift(x{k1},k2*nt); z(1:k2*nt)=0; y{k1}=y{k1}+z; end end t0=time; v0=zeros(N,n); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'Display','off'); c=char(''); tstart=tic; for k=3:N v0(k,1:n)=real(fsolve(@TRsim,v0(k-1,:),opts)); pause(0.01) fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*k/N)),' percent done! ']); fprintf(c) end fprintf('\n') fprintf(['elapsed time: ',num2str(toc(tstart))]); fprintf('\n') plot(time,cell2mat(y)) hold on plot(time,v0) legend([sprintfc('$v_{%d}(t) : Laplace$',1:n),sprintfc('$v_{%d} (t) : transient$',1:n)],... 'fontsize',12,'box','off','Location', 'best','interpreter','latex') function KCL=TRsim(v) global k v0 t0 T0 C1 L1 gz xs=sign(sin(2*pi*t0(k)/T0)); KCL(1)=(1/L1)*((v(1)-v(2))*diff(t0(k-1:k))+sum((v0(2:k-1,1)-v0(2: k-1,2)).*diff(t0(1:k-1)).',1))+gz*(v(1)-xs); KCL(2)=(1/L1)*((v(2)-v(1))*diff(t0(k-1:k))+sum((v0(2:k-1,2)-v0(2: k-1,1)).*diff(t0(1:k-1)).',1))+C1*diff([v0(k-1,2) v(2)])/diff(t0 (k-1:k)); End

154

3 Transient Analysis

Fig. 3.19 LC circuit

1 v1

Table 3.15 Parameter values

3.7.2

L1 1 mH

C1 1 nF

C1

2 L1

ω 2π  5  104 rad/s

Circuit 2

A two-node circuit, shown in Fig. 3.19, will be analyzed in this example. The inductor is initially disfluxed (iL1(0) ¼ 0) and the capacitor is initially discharged (vC1(0) ¼ 0). The input node 1 is connected to a triangle waveform given by j k ωt ωt v1 ðt > 0Þ ¼ 2  þ 0:5  1 2π 2π

ð3:84Þ

where b c is the floor function. The circuit parameters are listed in Table 3.15. The voltage-gain of the circuit is given by v2 s2 L1 C1 ¼ v1 1 þ s2 L1 C1

ð3:85Þ

The voltage at node 1 is given by

v1 ¼

2ω π



  πs 2 2πs 1eω s 1e ω   2πs s2 1  e ω

ð3:86Þ

and the output voltage at node 2 is given by

v2 ¼

2ω π



  πs 2 2πs 1eω s 1e ω s2 L1 C 1    2πs 1 þ s2 L1 C 1 s2 1  e ω

ð3:87Þ

The periodic voltage at node 2 with a period of 2π ω is given by       2πs πs 2 2πs 2ω L1 C 1 v2p ¼ v2  1  e ω ¼ ð3:88Þ 1eω s 1e ω  π 1 þ s2 L1 C 1

3.7 Circuits with Both Capacitors and Inductors

155

That is fractionally expanded as v2p ¼

1 ffi   pffiffiffiffiffiffiffi πs 2 2πs 2ω pffiffiffiffiffiffiffiffiffiffi s L1 C 1 ω L1 C 1 1  e ω  1  e 1 1 2 2 π þ s L1 C 1 L1 C 1 þ s

ð3:89Þ

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as v2p ðt Þ ¼

       2ω pffiffiffiffiffiffiffiffiffiffi t π 2π L1 C1 sin pffiffiffiffiffiffiffiffiffiffi  δðt Þ  2δ t  þδ t π ω ω L1 C1      t 2π  cos pffiffiffiffiffiffiffiffiffiffi  δðt Þ  δ t  ω L1 C1

ð3:90Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

ð3:91Þ

The node voltages of the circuit are plotted in Fig. 3.20. The following MATLAB code applies the inverse Laplace transformation to the partial fraction decomposition of the s-domain nodal voltage signals in this example. It also solves the time-domain finite difference equations of this example obtained from the Kirchhoff’s current law. Fig. 3.20 Node voltages

156

3 Transient Analysis

global k v0 t0 T0 C1 L1 gz syms v1 v2 syms i1 i2 syms s t syms C1 L1 gz XS Vvec=[v1 v2]; Ivec=[i1 i2]; equ=[i1==s*C1*(v1-v2)+gz*(v1-XS);... i2==(1/(s*L1))*v2+s*C1*(v2-v1)]; [A,B]=equationsToMatrix(-subs(equ,Ivec,zeros(1,length(Ivec))), Vvec); f0=5e04; np=5; nt=1001; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; N=np*nt; n=2; C1=1e-09; L1=1e-03; gz=1e03; T0=1/f0; XS=((4/T0)*(1-exp(-s*T0/2))^2-s*(1-exp(-s*T0)))/s^2; X=sym.empty(0,1); x=cell.empty(0,1); for k=1:n C=A; C(:,k)=B; X(k)=vpa(partfrac(simplifyFraction(det(eval(C))/det(eval (A)))),4); x{k}=double(subs(vpa(ilaplace(X(k),s,t),4),t,time.')).*ones (length(time),1); end y=x; for k1=1:n for k2=1:(np/(T0*f0))-1 z=circshift(x{k1},k2*nt); z(1:k2*nt+1)=0; y{k1}=y{k1}+z; end end t0=time; v0=zeros(N,n);

3.7 Circuits with Both Capacitors and Inductors

157

opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'Display','off'); c=char(''); tstart=tic; for k=3:N v0(k,1:n)=real(fsolve(@TRsim,v0(k-1,:),opts)); pause(0.01) fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*k/N)),' percent done! ']); fprintf(c) end fprintf('\n') fprintf(['elapsed time: ',num2str(toc(tstart))]); fprintf('\n') plot(time,cell2mat(y)) hold on plot(time,v0) legend([sprintfc('$v_{%d}(t) : Laplace$',1:n),sprintfc('$v_{%d} (t) : transient$',1:n)],... 'fontsize',12,'box','off','Location', 'best','interpreter','latex') function KCL=TRsim(v) global k v0 t0 T0 C1 L1 gz xs=4*(abs(rem(t0(k)/T0+0.5,1)-0.5))-1; KCL(1)=C1*diff([v0(k-1,1)-v0(k-1,2) v(1)-v(2)])/diff(t0(k-1:k)) +gz*(v(1)-xs); KCL(2)=(1/L1)*(v(2)*diff(t0(k-1:k))+sum(v0(2:k-1,2).*diff(t0(1:k1)).',1))+C1*diff([v0(k-1,2)-v0(k-1,1) v(2)-v(1)])/diff(t0(k-1: k)); End

3.7.3

Circuit 3

A two-node circuit, shown in Fig. 3.21, will be analyzed in this example.

Fig. 3.21 RLC circuit

G1 1

v1

L1

2 C1

158

3 Transient Analysis

Table 3.16 Parameter values

G1 1 mA/V

L1 100 nH

C1 1 nF

duty 10%

ω 2π  5  106 rad/s

The inductor is initially disfluxed (iL1(0) ¼ 0) and the capacitor is initially discharged (vC1(0) ¼ 0). The input node 1 is connected to a pulse waveform given by $  % duty k ω t  2π 100ω ωt  v1 ðt > 0Þ ¼ 2π 2π j

ð3:92Þ

where b c is the floor function. The circuit parameters are listed in Table 3.16. The voltage-gain of the circuit is given by v2 1 þ sG1 L1 ¼ v1 1 þ sG1 L1 þ s2 L1 C1

ð3:93Þ

The voltage at node 1 is given by     2πs 2πs  1  e ω þ 2 1  eð ω dutyÞ   v1 ¼ 2πs s 1  e ω

ð3:94Þ

and the output voltage at node 2 is given by     2πs 2πs  1  e ω þ 2 1  eð ω dutyÞ 1 þ sG1 L1    v2 ¼ 2 1 þ sG 2πs 1 L1 þ s L1 C 1 ω s 1e

ð3:95Þ

The periodic voltage at node 2 with a period of 2π ω is given by   2πs v2p ¼ v2  1  e ω      2πs 2πs ¼ 2 1  eð ω dutyÞ  1  e ω 

1 þ sG1 L1 sð1 þ sG1 L1 þ s2 L1 C 1 Þ

ð3:96Þ

That is fractionally expanded as 

v2p ¼ 1 þ e

2πs ω

 2e

2πs ω duty



4C 1 þG1 A1



4C1 þG1 A2

1 2A3 2A3   A2 s s  A1 s  2L1 C 1 2L1 C 1

! ð3:97Þ

where A1 ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L1 2 G1 2  4L1 C1  G1 L1

ð3:98Þ

3.7 Circuits with Both Capacitors and Inductors

159

and A2 ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L1 2 G1 2  4L1 C1 þ G1 L1

ð3:99Þ

and A3 ¼ L1 G1 2 þ 4C1

ð3:100Þ

and the periodic voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as 

4C þ G1 A1 2LA1 C1 t1 4C1 þ G1 A2 2LA1 C2 t1 v2p ðt Þ ¼ 1  1 e  e 2A3 2A3      2π 2π  δ ðt Þ þ δ t   2δ t   duty ω ω



ð3:101Þ

and the voltage at node 2 is calculated by v2 ð t Þ ¼

  2π v2p t  k ω k¼0

1 X

ð3:102Þ

The node voltages of the circuit are plotted in Fig. 3.22. Using the following template and the MATLAB codes provided in the previous sections, write a code to simulate the circuit shown in this section by solving the inverse Laplace transformation of the nodal voltage signals in s-domain as well as solving the time-domain finite difference equations obtained from the Kirchhoff’s current law.

Fig. 3.22 Node voltages

160

3 Transient Analysis

G1=1e-03; C1=1e-09; L1=1e-07; gz=1e03; duty=10; XS=(1+exp(-s*T0)-2*exp(-s*T0*duty/100))/(s*(1-exp(-s*T0))); xs=square(2*pi*t0(k)/T0,duty); %s-domain equations KCL(1)=(1/(s*L1))*(v1-v2)+G1*(v1-v2)+gz*(v1-XS);... KCL(2)=s*C1*v2+(1/(s*L1))*(v2-v1)+G1*(v2-v1)]; %time-domain equations KCL(1)=(1/L1)*((v(1)-v(2))*diff(t0(k-1:k))+sum((v0(2:k-1,1)-v0(2: k-1,2)).*diff(t0(1:k-1)).',1))+G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=C1*diff([v0(k-1,2)-0 v(2)-0])/diff(t0(k-1:k))+(1/L1)*((v (2)-v(1))*diff(t0(k-1:k))+sum((v0(2:k-1,2)-v0(2:k-1,1)).*diff(t0 (1:k-1)).',1))+G1*(v(2)-v(1));

3.7.4

Circuit 4

A two-node circuit, shown in Fig. 3.23, will be analyzed in this example. The inductor is initially disfluxed (iL1(0) ¼ 0) and the capacitor is initially discharged (vC1(0) ¼ 0). The input node 1 is connected to an arbitrary waveform given by v 1 ð t > 0Þ ¼

 2    ωt π U ðt Þ  U t  π ω  2      ωt π 2π þ 2 U t U t π ω ω

ð3:103Þ

where U is the Heaviside step function. The circuit parameters are listed in Table 3.17. The voltage-gain of the circuit is given by Fig. 3.23 RLC circuit

G1 1

v1

C1

2 L1

3.7 Circuits with Both Capacitors and Inductors Table 3.17 Parameter values

G1 1 mA/V

161

L1 1 μH

ω 2π  5  106 rad/s

C1 1 nF

sL1 ðG1 þ sC 1 Þ v2 ¼ v1 1 þ sL1 ðG1 þ sC 1 Þ

ð3:104Þ

The voltage at node 1 is given by

v1 ¼

8ω2 ð2π Þ2



1  e ω

2πs



πs

ω  8sω 2π e

ð3:105Þ

s3

and the output voltage at node 2 is given by v2 ¼

  8ω2 sL1 G1 þ s2 L1 C1 8ω πsω 2πs ω 1  e e   2 3 ð1 þ sL G þ s2 L C Þ 2π s 1 1 1 1 ð2π Þ 

sL1 G1 þ s2 L1 C1 þ sL1 G1 þ s2 L1 C1 Þ

ð3:106Þ

s2 ð1

That is fractionally expanded as v2 ¼

  8ω2 2πs ω 1  e ð2π Þ2 G1 L1 G1 2 L1 2  L1 C 1 A2  8L1 C1 2 2C1 G1 2 L1 2 A2 þ 8L1 C1 2 2C1 G1 2 L1 2    s s2 s þ 2LA4C s  2LA3C A1 A3



1

 

A1 A4

1

1

8ω πsω e 2π G1 L1 A6 þ 8L1 C1 2 2C1 G1 2 L1 2 A6  8L1 C1 2 2C1 G1 2 L1 2 þ þ s s þ A4 s  A3 A5 A4

A5 A3

2L1 C 1

2L1 C1

!

1

!

ð3:107Þ where   A1 ¼ L1 C 1 G1 3L1 C1  G1 2 L1 2

ð3:108Þ

and A2 ¼ and

  L1 2C1 2  4L1 C1 G1 2 þ G1 4 L1 2 4C 1  L1 G1 2

ð3:109Þ

162

3 Transient Analysis

A3 ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L1 2 G1 2  4L1 C1  G1 L1

ð3:110Þ

A4 ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L1 2 G1 2  4L1 C1 þ G1 L1

ð3:111Þ

and

and   A5 ¼ L1 C1 2C 1  L1 G1 2

ð3:112Þ

  L1 G1 L1 2 G1 2  3C 1 A6 ¼ 4C 1  L1 G1 2

ð3:113Þ

and

The voltage at node 2 in time-domain by applying the inverse Laplace transform is obtained as    A3 t  2 2  8ω2 A1 A3  A G L t  G L  L C  e2L1 C1 1 1 1 1 1 1 2 2 2 2 2 8L1 C1  2C1 G1 L1 ð2π Þ       A4 t A1 A4 2π e2L1 C1  δðt Þ  δ t   A2 þ 2 2 2 ω 8L C  2C 1 G1 L1  1 1    At  A4 t 3 8ω A5 A4 A5 A3 2L1 C1 G1 L 1 þ A6 þ  þ A  e e2L1 C1 6 2 2 2 2 2 2 2π 8L1 C1  2C1 G1 L1 8L1 C 1  2C1 G1 L1    π  δ t ω v 2 ðt Þ ¼

ð3:114Þ The node voltages of the circuit are plotted in Fig. 3.24. Fig. 3.24 Node voltages

3.8 Causality

163

Using the following template and the MATLAB codes provided in the previous sections, write a code to simulate the circuit shown in this section by solving the inverse Laplace transformation of the nodal voltage signals in s-domain as well as solving the time-domain finite difference equations obtained from the Kirchhoff’s current law

G1=1e-03; C1=1e-09; L1=1e-06; gz=1e03; XS=8*(1-exp(-s*T)-s*T*exp(-s*T/2))/(T^2*s^3); xs=(((2*f0*t0(k))^2)*(heaviside(t0(k))-heaviside(t0(k)-1/(2*f0))) +((2*f0*(t0(k)-1/f0))^2)*(heaviside(t0(k)-1/(2*f0))-heaviside(t0 (k)-2/(2*f0)))); %s-domain equations KCL(1)=s*C1*(v1-v2)+G1*(v1-v2)+gz*(v1-XS); KCL(2)=(1/(s*L1))*v2+s*C1*(v2-v1)+G1*(v2-v1)]; %time-domain equations KCL(1)=C1*diff([v0(k-1,1)-v0(k-1,2) v(1)-v(2)])/diff(t0(k-1:k)) +G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=(1/L1)*(v(2)*diff(t0(k-1:k))+sum(v0(2:k-1,2).*diff(t0(1:k1)).',1))+C1*diff([v0(k-1,2)-v0(k-1,1) v(2)-v(1)])/diff(t0(k-1:k)) +G1*(v(2)-v(1));

3.8

Causality

The transfer functions of the circuits that include capacitors and inductors depend on the initial conditions of these components. Capacitors store electric fields (voltages) and inductors store magnetic fluxes (currents). In circuits that involve switches and storage devices such as capacitors and inductors, the behavior of the circuit depends on the circuit operation before switching. The impacts of voltages and currents stored in capacitors and inductors acting as initial conditions for the next switching state are shown by the following Laplace transformation properties, as listed in Table 3.18. Table 3.18 Initial conditions in Laplace transformations f(t) df ðt Þ dt d f 2 ðt Þ dt 2 d f n ðt Þ dt n Ð1 0 f ðt Þdt

F(s) sF(s)  f(0) s2 F ðsÞ  sf ð0Þ  dfdtð0Þ sn F ðsÞ  sn1 f ð0Þ  sn2 dfdtð0Þ  . . .  s d fdtn2ð0Þ  d fdtn1ð0Þ n2

F ðsÞ s

n1

164

3 Transient Analysis

Because of this causality or dependency on initial conditions, the analysis of circuits that involve storage devices and switches using Laplace transformation must be broken down into consecutive switching intervals. The calculated final voltages and currents in each state must be used as initial conditions for the next switching states. A major advantage of the transient analysis using discretized differential and integral equations is the inherit transformation of the calculated voltages and currents to the next switching states without the requirements of breaking the simulation into different switching intervals. Therefore, a trade-off for transient analysis using Laplace transformation and discretized differential and integral equations is the simulation accuracy versus versatility. The Laplace transformation provides accurate results and the discretized approach can be applied to all circuits including the nonlinear and the time-variant components.

3.8.1

Circuit 1

A three-node circuit, shown in Fig. 3.25, will be analyzed in this example. A step waveform (v1(t  0) ¼ 1) is applied to the circuit input at node 1. The switch is initially closed and capacitor is discharged (vC1(t ¼ 0) ¼ 0). The circuit model is shown in Fig. 3.26. The circuit equation is given by ðG2 þ sC 1 Þv2 ¼ G1 ðv1  v2 Þ and v2 ¼ v3

ð3:115Þ

That is simplified to

Fig. 3.25 Switching RC circuit

1

G1 2

sw1 3

v1

C1

Fig. 3.26 Circuit before switching

1 v1

G1

G2

2,3 C1

G2

3.8 Causality

165

Fig. 3.27 Circuit after switching

3 C1

C1vC1(0)

v2 G1 ¼ v1 G1 þ G2 þ sC 1

G2

ð3:116Þ

The voltages at nodes 2 and 3 are given by G1

v2 ¼ v3 ¼

G1

G1 2 ¼ G1 þG2  G1 GþG s sðG1 þ G2 þ sC 1 Þ s þ 1CþG2

ð3:117Þ

1

The voltages at nodes 2 and 3 in time-domain are given by   ðG1 þG2 Þ G1 t C1 v2 ð t Þ ¼ v3 ð t Þ ¼ 1e  U ðt Þ G1 þ G2

ð3:118Þ

Where U is the heaviside function. The capacitor voltage will exponentially increase until switch is opened at t ¼ toff. vC1 ðtoff Þ ¼

  ðG1 þG2 Þ G1 t 1  e C1 off G1 þ G2

ð3:119Þ

When the switch is opened, the circuit model is shown in Fig. 3.27. In the remaining circuit, the current flow of G1 becomes zero and the voltage at node 2 becomes equal to that at node 1. The circuit equation is given by ðG2 þ sC 1 Þv3 ¼ C 1 vC1 ð0Þ

ð3:120Þ

  vC1 ð0Þ ¼ vC1 t off

ð3:121Þ

where

The circuit equation is simplified to     C 1 vC1 t off 1 ¼ vC1 t off  v3 ¼ G2 þ sC 1 s þ G2 C1

The voltage at node 2 in time-domain is given by

ð3:122Þ

166

3 Transient Analysis

Table 3.19 Parameter values

G1 1 mA/V

G2 1 mA/V

C1 1 nF

toff 2 μs

Fig. 3.28 Node 2 voltage Fig. 3.29 Node 3 voltage

    G2 tt   v2 t  t off ¼ vC1 t off e C1 ð off Þ  U t  t off

ð3:123Þ

Where U is the heaviside function. The circuit parameters are listed in Table 3.19. The voltage at node 2 is shown in Fig. 3.28. The voltage at node 3 is shown in Fig. 3.29. The following MATLAB code solves the time-domain finite difference equations of this example obtained from the Kirchhoff’s current law.

3.8 Causality

167

global k t0 v0 f0=125e03; np=1; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; N=np*nt; n=3; t0=time; v0=zeros(N,n); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'Display','off'); c=char(''); tstart=tic; for k=3:N v0(k,1:n)=real(fsolve(@TRsim,v0(k-1,:),opts)); pause(0.01) fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*k/N)),' percent done! ']); fprintf(c) end fprintf('\n') fprintf(['elapsed time: ',num2str(toc(tstart))]); fprintf('\n') for k=1:n subplot(n,1,k) plot(time,v0(:,k)) end function KCL=TRsim(v) global k t0 v0 G1=1e-03; G2=1e-03; C1=1e-09; gz=1e03; ton=1e-08; gH=1e03; gL=1e-06; toff=2e-06; xs=0.5*(1+sign(t0(k)-ton)); switchoff=gL+(gH-gL)*0.5*(1-sign(t0(k)-toff)); KCL(1)=G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=G1*(v(2)-v(1))+switchoff*(v(2)-v(3)); KCL(3)=C1*diff([v0(k-1,3) v(3)])/diff(t0(k-1:k))+switchoff*(v(3)-v (2))+G2*v(3); End

168

3.8.2

3 Transient Analysis

Circuit 2

A three-node circuit, shown in Fig. 3.30, will be analyzed in this example. A step waveform (v1(t  0) ¼ 1) is applied to the circuit input at node 1. The switch is initially closed and inductor is disfluxed (iL1(t ¼ 0) ¼ 0). The circuit model is shown in Fig. 3.31. The circuit equation is given by   1 G2 þ v ¼ G1 ðv1  v2 Þ and v2 ¼ v3 sL1 2

ð3:124Þ

That is simplified to v2 sL1 G1 ¼ v1 1 þ sL1 ðG1 þ G2 Þ

ð3:125Þ

The voltages at nodes 2 and 3 are given by G1

L1 G1 G1 þG2 v2 ¼ v3 ¼ ¼ 1 þ sL1 ðG1 þ G2 Þ s þ L ðG 1þG Þ 1

1

ð3:126Þ

2

The voltages at nodes 2 and 3 in time-domain are given by v2 ð t Þ ¼ v3 ð t Þ ¼

1 t G1 eL1 ðG1 þG2 Þ  U ðt Þ G1 þ G2

ð3:127Þ

Where U is the heaviside function. The inductor voltage will exponentially decrease and the inductor current at t ¼ toff is obtained by

Fig. 3.30 Switching RL circuit

1 v1

Fig. 3.31 Circuit before switching

2 L1

1 v1

sw1

G1

G1

3 G2

2,3 L1

G2

3.8 Causality

169

Fig. 3.32 Circuit after switching

1

G1

v1



iL1 t off



1 ¼ L1

tð off

2 L1

  1 t off v2 ðt Þdt ¼ G1 1  eL1 ðG1 þG2 Þ

iL1(0)/s

ð3:128Þ

0

When the switch is opened, the circuit model is shown in Fig. 3.32. In the remaining circuit, the current flow and the voltage drop of conductor G2 drop to zero. The circuit equation is given by i ð 0Þ v2 ¼ G1 ðv1  v2 Þ  L1 s sL1

ð3:129Þ

  iL1 ð0Þ ¼ iL1 t off

ð3:130Þ

where

and v1 ¼

1 s

ð3:131Þ

The circuit equation is simplified to v2 ¼

G1  iL1 ð0Þ G1  iL1 ð0Þ 1 ¼  1 þ sG1 L1 G1 L1 s þ G 1L

ð3:132Þ

1 1

The voltage at node 2 in time-domain is given by   G  iL1 ð0Þ 1 ðttoff Þ   eG 1 L 1  U t  t off v2 t  t off ¼ 1 G1 L1

ð3:133Þ

Where U is the heaviside function. The circuit parameters are listed in Table 3.20. The voltage at node 2 is shown in Fig. 3.33. The voltage at node 3 is shown in Fig. 3.34. The following MATLAB code solves the time-domain finite difference equations of this example obtained from the Kirchhoff’s current law.

170 Table 3.20 Parameter values

Fig. 3.33 Node 2 voltage

Fig. 3.34 Node 3 voltage

global k t0 v0 f0=125e03; np=1; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt;

3 Transient Analysis

R1 1 kΩ

R2 1 kΩ

L1 1 mH

toff 2 μs

3.8 Causality

171

N=np*nt; n=3; t0=time; v0=zeros(N,n); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'Display','off'); c=char(''); tstart=tic; for k=3:N v0(k,1:n)=real(fsolve(@TRsim,v0(k-1,:),opts)); pause(0.01) fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*k/N)),' percent done! ']); fprintf(c) end fprintf('\n') fprintf(['elapsed time: ',num2str(toc(tstart))]); fprintf('\n') for k=1:n subplot(n,1,k) plot(time,v0(:,k)) end function KCL=TRsim(v) global k t0 v0 G1=1e-03; G2=1e-03; L1=1e-03; gz=1e03; ton=1e-09; gH=1e03; gL=1e-06; toff=2e-06; xs=0.5*(1+sign(t0(k)-ton)); switchoff=gL+(gH-gL)*0.5*(1-sign(t0(k)-toff)); KCL(1)=G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=G1*(v(2)-v(1))+switchoff*(v(2)-v(3))+(1/L1)*((v(2)-0)*diff (t0(k-1:k))+sum((v0(2:k-1,2)-0).*diff(t0(1:k-1)).',1)); KCL(3)=switchoff*(v(3)-v(2))+G2*v(3); End

3.8.3

Circuit 3

A three-node circuit, shown in Fig. 3.35, will be analyzed in this example. A step waveform (v1(t  0) ¼ 1) is applied to the circuit input at node 1. The switch is initially closed and capacitor is discharged (vC1(t ¼ 0) ¼ 0) and inductor is disfluxed (iL1(t ¼ 0) ¼ 0). The circuit model before switching is shown in Fig. 3.36.

172

3 Transient Analysis

Fig. 3.35 Switching RLC circuit

1

sw1

G1 2

3

v1

L1

C1

Fig. 3.36 Circuit before switching

1

G1

v1

G2

2,3 C1

L1 G2

The circuit equation is given by   1 G2 þ sC 1 þ v ¼ G1 ðv1  v2 Þ and v2 ¼ v3 sL1 2

ð3:134Þ

That is simplified to v2 sL1 G1 ¼ v1 1 þ sL1 ðG1 þ G2 Þ þ sL1 C 1

ð3:135Þ

The voltages at nodes 2 and 3 are given by v2 ¼ v3 ¼

L1 G1 þ 1 þ sL1 ðG1 þ G2 Þ þ sL1 C 1

G1 ðL1 ðG1 þG2 ÞA1 Þ A3 s þ 2LA11C1

þ

G1 ðL1 ðG1 þG2 ÞA2 Þ A3 s þ 2LA12C1

ð3:136Þ

where A1 ¼ L1 ðG1 þ G2 Þ 

pffiffiffiffiffiffiffiffiffiffi L1 A3

ð3:137Þ

A2 ¼ L1 ðG1 þ G2 Þ þ

pffiffiffiffiffiffiffiffiffiffi L1 A3

ð3:138Þ

and

and A3 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi   L1 G1 2 þ G2 2 þ 2L1 G1 G2  4C 1

ð3:139Þ

3.8 Causality

173

The voltages at nodes 2 and 3 in time-domain are given by v2 ð t Þ ¼ v3 ð t Þ   G1 ðL1 ðG1 þ G2 Þ  A1 Þ 2LAC1 t G1 ðL1 ðG1 þ G2 Þ  A2 Þ 2LAC2 t ¼ e 11 þ e 11 A3 A3  U ðt Þ

ð3:140Þ

Where U is the heaviside function. The inductor and capacitor voltages will exponentially decrease until switch is open. The capacitor voltage at t ¼ toff is obtained by     vC1 t off ¼ v2 t off

ð3:141Þ

and the inductor current at t ¼ toff is obtained by 

iL1 t off



1 ¼ L1

tð off

v2 ðt Þdt 0

 A1 2L C G ðL ðG þ G2 Þ  A1 Þ  t ¼ 1 1 1 1 1 1  e2L1 C1 off A3 A1  A2 2L C G ðL ðG þ G2 Þ  A2 Þ  t þ 1 1 1 1 1 1  e2L1 C1 off A3 A2

ð3:142Þ

When the switch is opened, the circuit model is shown in Fig. 3.37. In the remaining circuit, the current flow of G1 becomes zero and the voltage at node 2 becomes equal to that at node 1. The circuit equation is given by   i ð 0Þ 1 G2 þ sC 1 þ v ¼ C 1 vC1 ð0Þ  L1 s sL1 3

ð3:143Þ

where

Fig. 3.37 Circuit after switching

3 C1

C1vC1(0)

L1

iL1(0)/s

G2

174

3 Transient Analysis

  vC1 ð0Þ ¼ vC1 t off

ð3:144Þ

  iL1 ð0Þ ¼ iL1 t off

ð3:145Þ

and

The circuit equation is simplified to     sL1 C1 vC1 t off L1 iL1 t off v3 ¼  1 þ sL1 G1 þ s2 L1 C 1 1 þ sL1 G1 þ s2 L1 C 1 pffiffiffiffi 0 pffiffiffiffi 1 G1 ð A1 L1 G1 Þ G1 ð A1 þL1 G1 Þ 2 2  þ   A A 2L C A 2L C A 1 1 1 1 1 1 1 1A pffiffiffiffi pffiffiffiffi  L1 C1 vC1 t off ¼@  A1 L1 G1 A1 þL1 G1 s  2L1 C1 s þ 2L1 C1 0 1 pffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi G1 L1  2A1 C1 G1 L1 þ 2A1 C1 G1 G1  þ 2 2 2C 1 A1 2C 1 A1 4C1 L1 G1 4C1 L1 G1 A pffiffiffiffi pffiffiffiffi þ@  A1 þL1 G1 1 G1 s  A2L1 L s þ 2L1 C 1 1 C1    L1 iL1 t off

ð3:146Þ

where   A1 ¼ L1 L1 G2 2  4C1

ð3:147Þ

The voltage at node 3 in time-domain is given by   v3 t  toff ¼    pffiffiffi  pffiffiffiffiffi  pffiffiffi G  pffiffiffiffiffi  A1 L1 G1 1 1 G1 A1  L1 G1 G1 A1 þ L1 G1 2 2  2LA11L tt off Þ ð 2L1 C 1 ðtt off Þ C1   þ e e 2L1 C 1 A1 2L1 C 1 A1 A1 A1  pffiffiffi  pffiffiffiffiffiffiffiffiffiffiffiffiffi A1 L1 G1     G1 L1  2A1 C 1 G1 tt e 2L1 C1 ð off Þ   L1 C 1 vC1 toff U t  t off þ 2 2C 1 A1 4C 1  L1 G1   pffiffiffi  pffiffiffiffiffiffiffiffiffiffiffiffiffi A1 L1 G1     G1 L1 þ 2A1 C 1 G1 tt off Þ ð 2L1 C 1 e  L1 iL1 toff U t  t off þ  2C 1 A1 4C 1  L1 G1 2

ð3:148Þ Where U is the Heaviside function. The circuit parameters are listed in Table 3.21. The voltage at node 2 is shown in Fig. 3.38. The voltage at node 3 is shown in Fig. 3.39. The following MATLAB code solves the time-domain finite difference equations of this example obtained from the Kirchhoff’s current law.

3.8 Causality Table 3.21 Parameter values

Fig. 3.38 Node 2 voltage

Fig. 3.39 Node 3 voltage

global k t0 v0 f0=125e03; np=1; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt;

175

G1 1 mA/V

G2 1 mA/V

C1 1 nF

L1 1 mH

toff 2 μs

176

3 Transient Analysis

N=np*nt; n=3; t0=time; v0=zeros(N,n); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'Display','off');c=char(''); tstart=tic; for k=3:N v0(k,1:n)=real(fsolve(@TRsim,v0(k-1,:),opts)); pause(0.01) fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*k/N)),' percent done! ']); fprintf(c) end fprintf('\n') fprintf(['elapsed time: ',num2str(toc(tstart))]); fprintf('\n') for k=1:n subplot(n,1,k) plot(time,v0(:,k)) end function KCL=TRsim(v) global k t0 v0 G1=1e-03; G2=1e-03; C1=1e-09; L1=1e-03; gz=1e03; ton=1e-09; gH=1e03; gL=1e-06; toff=2e-06; xs=0.5*(1+sign(t0(k)-ton)); switchoff=gL+(gH-gL)*0.5*(1-sign(t0(k)-toff)); KCL(1)=G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=G1*(v(2)-v(1))+switchoff*(v(2)-v(3)); KCL(3)=switchoff*(v(3)-v(2))+G2*v(3)+(1/L1)*(v(3)*diff(t0(k-1:k)) +sum(v0(2:k-1,3).*diff(t0(1:k-1)).',1))+C1*diff([v0(k-1,3) v(3)])/ diff(t0(k-1:k)); end

3.8.4

Circuit 4

A four-node circuit, shown in Fig. 3.40, will be analyzed in this example.

3.8 Causality

177

Fig. 3.40 Switching RLC circuit

sw1

G1 2

1

3

v1

L1 C1

G2

Fig. 3.41 Circuit before switching

G1

1

v1

2,3 G2

4

L1

4 C1

A step waveform (v1(t  0) ¼ 1) is applied to the circuit input at node 1. The switch is initially closed and capacitor is discharged (vC1(t ¼ 0) ¼ 0) and inductor is disfluxed (iL1(t ¼ 0) ¼ 0). The circuit model before switching is shown in Fig. 3.41. The circuit equations are given by G1 ðv2  v1 Þ þ G2 v2 þ

1 ðv  v4 Þ ¼ 0 and v2 ¼ v3 sL1 2

ð3:149Þ

and 1 ðv  v2 Þ þ sC 1 v4 ¼ 0 and v2 ¼ v3 sL1 4

ð3:150Þ

That is simplified to v2 G1 þ s2 L1 C1 G1 ¼ v1 G1 þ G2 þ sC 1 þ s2 L1 C 1 ðG1 þ G2 Þ

ð3:151Þ

v4 G1 ¼ v1 G1 þ G2 þ sC 1 þ s2 L1 C 1 ðG1 þ G2 Þ

ð3:152Þ

and

The voltages at nodes 2 and 3 are given by

v2 ¼ v3 ¼ and

L1 C1 G1 þ A1

2G1 A2

 s

pffiffiffiffiffiffiffiffi C 1 G1 ðC 1  C 1 A2 Þ 2A1 A2 ðG1 þG2 Þ pffiffiffiffiffiffiffiffi þ C1 2AC1 1 A2

þ

2G1 A2

 s

pffiffiffiffiffiffiffiffi C 1 G1 ðC 1 þ C 1 A2 Þ 2A1 A2 ðG1 þG2 Þ pffiffiffiffiffiffiffiffi þ C1 þ2AC1 1 A2

ð3:153Þ

178

3 Transient Analysis

v4 ¼

G1 A2

pffiffiffiffiffiffiffiffi G 1 ðC 1  C 1 A 2 Þ C 1 A2 pffiffiffiffiffiffiffiffi C 1  C 1 A2 þ 2A1

 s

þ

G1 A2

pffiffiffiffiffiffiffiffi G1 ðC 1 þ C 1 A2 Þ C 1 A2 pffiffiffiffiffiffiffiffi C 1 þ C 1 A2 þ 2A1

 s

ð3:154Þ

where A1 ¼ L1 C1 ðG1 þ G2 Þ

ð3:155Þ

A2 ¼ C1  4ðG1 þ G2 Þ2

ð3:156Þ

and

The voltages at nodes 2 and 3 in time-domain are given by  pffiffiffiffiffiffiffiffiffiffiffi  pffiffiffiffiffiffiffi  C1 þ C 1 A2 L1 C1 G1 2G1 C 1 G1 C 1  C 1 A2 t 2A1 v2 ðt Þ ¼ v3 ðt Þ ¼ δ ðt Þ þ  e A1 A2 2A1 A2 ðG1 þ G2 Þ  pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffi   C 1  C1 A2 2G1 C1 G1 C1 þ C 1 A2 t 2A1 þ   U ðt Þ e A2 2A1 A2 ðG1 þ G2 Þ ð3:157Þ The voltage at node 4 in time-domain is given by v 4 ðt Þ ¼

  pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi  pffiffiffiffiffiffiffi  pffiffiffiffiffiffiffi  C 1 þ C 1 A2 C 1  C 1 A2 G 1 G 1 C 1  C 1 A2 G1 G1 C 1 þ C 1 A2 t t  þ  e 2A1 e 2A1 C 1 A2 C 1 A2 A2 A2  U ðt Þ

ð3:158Þ Where U is the heaviside function. The inductor and capacitor voltages will exponentially increase until switch is open. The capacitor voltage at t ¼ toff is obtained by     vC1 t off ¼ v4 t off

ð3:159Þ

and the inductor current at t ¼ toff is obtained by 

iL1 t off



1 ¼ L1

tð off

ðv3 ðt Þ  v4 ðt ÞÞdt

ð3:160Þ

0

When the switch is opened, the circuit model is shown in Fig. 3.42. In the remaining circuit, the current flow of G1 becomes zero and the voltage at node 2 becomes equal to that at node 1.

3.8 Causality

179

iL1(0)/s

Fig. 3.42 Circuit after switching

3 G2

L1

4 C1

C1vC1(0)

The circuit equations are given by i ð0Þ 1 ðv  v4 Þ ¼ L1 s sL1 3

ð3:161Þ

i ð 0Þ 1 ðv  v3 Þ ¼ C 1 vC1 ð0Þ þ L1 s sL1 4

ð3:162Þ

G2 v3 þ and sC 1 v4 þ

The voltage at node 3 is given by v3 ¼

s2 L1 C 1 iL1 ð0Þ þ sC 1 vC1 ð0Þ  2iL1 ð0Þ sðG2 þ sC 1 þ s2 G2 L1 C 1 Þ

ð3:163Þ

The voltage at node 4 is given by v4 ¼

C 1 vC1 ð0Þ þ G2 L1 iL1 ð0Þ þ sG2 L1 C1 vC1 ð0Þ sðG2 þ sC 1 þ s2 G2 L1 C 1 Þ

ð3:164Þ

where   vC1 ð0Þ ¼ vC1 t off

ð3:165Þ

  iL1 ð0Þ ¼ iL1 t off

ð3:166Þ

and

Circuit equations in time-domain are obtained by applying inverse Laplace transformation to voltages at nodes 3 and 4. The circuit parameters are listed in Table 3.22. The voltage at node 2 is shown in Fig. 3.43. The voltage at node 3 is shown in Fig. 3.44. The voltage at node 4 is shown in Fig. 3.45.

180 Table 3.22 Parameter values

3 Transient Analysis

G1 1 mA/V

G2 1 mA/V

C1 1 nF

L1 1 μH

toff 2 μs

Fig. 3.43 Node 2 voltage

Fig. 3.44 Node 3 voltage

The following MATLAB code solves the time-domain finite difference equations of this example obtained from the Kirchhoff’s current law.

global k t0 v0 f0=125e03; np=1;

3.8 Causality

181

Fig. 3.45 Node 4 voltage

nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; N=np*nt; n=4; t0=time; v0=zeros(N,n); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'Display','off'); c=char(''); tstart=tic; for k=3:N v0(k,1:n)=real(fsolve(@TRsim,v0(k-1,:),opts)); pause(0.01) fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*k/N)),' percent done! ']); fprintf(c) end fprintf('\n') fprintf(['elapsed time: ',num2str(toc(tstart))]); fprintf('\n') for k=1:n subplot(n,1,k) plot(time,v0(:,k)) end function KCL=TRsim(v) global k t0 v0 G1=1e-03; G2=1e-03; C1=1e-09;

182

3 Transient Analysis

L1=1e-06; gz=1e03; ton=1e-09; gH=1e03; gL=1e-06; toff=2e-06; xs=0.5*(1+sign(t0(k)-ton)); switchoff=gL+(gH-gL)*0.5*(1-sign(t0(k)-toff)); KCL(1)=G1*(v(1)-v(2))+gz*(v(1)-xs); KCL(2)=G1*(v(2)-v(1))+switchoff*(v(2)-v(3)); KCL(3)=switchoff*(v(3)-v(2))+G2*v(3)+(1/L1)*((v(3)-v(4))*diff(t0 (k-1:k))+sum((v0(2:k-1,3)-v0(2:k-1,4)).*diff(t0(1:k-1)).',1)); KCL(4)=(1/L1)*((v(4)-v(3))*diff(t0(k-1:k))+sum((v0(2:k-1,4)-v0(2: k-1,3)).*diff(t0(1:k-1)).',1))+C1*diff([v0(k-1,4) v(4)])/diff(t0 (k-1:k)); End

3.9

Spectral Decomposition Using Fourier Series

When signals are plotted in the time-domain, their amplitudes, periods, delays, slopes, waveforms, swings, and many other characteristics are easily observed and characterized. There is many other hidden embedded information in the signals that need special treatment in order to better characterize electronic circuits. This information can be observed in the signal spectrum. A signal spectrum is obtained by decomposing the time-domain signal into frequency harmonics that form the signal, as shown in Fig. 3.46. A variety of algorithms perform the decomposing task such as discrete Fourier transformation (DFT) or fast Fourier transformation (FFT) and the electronic instrument that plots and measures the signal spectrum is called spectrum analyzer. The two sin(ωt) and cos(ωt) are fundamental signals because they only contain a single frequency. A periodic signal f(t) contains a combination of frequencies and therefore, can be decomposed into series of sine and cosine functions such as X X 1 f ðtÞ ¼ a0 þ an cos ðnωtÞ þ bn sin ðnωtÞ 2 n¼1 n¼1 1

1

ð3:167Þ

where n ¼ 1, 2, 3, . . . representing different frequency tones. The DC term is calculated by ð2 T

a0 ¼

2 T

f ðtÞdt T 2

and the cosine coefficients are calculated by

ð3:168Þ

183

magnitude (dB)

amplitude (V)

3.9 Spectral Decomposition Using Fourier Series

Fig. 3.46 Decomposition of the periodic square waveform into frequency harmonics T

2 an ¼ T

ð2 f ðtÞ cos ðnωtÞdt

ð3:169Þ

T 2

and the sine coefficients are calculated by ð2 T

2 bn ¼ T

3.9.1

f ðtÞ sin ðnωtÞdt

ð3:170Þ

T 2

Fast Fourier Transformation

The spectrum X(1 : N ) of a discretized signal x(1 : N ) is obtained by transforming its time-domain signal into the frequency domain using the following expression.

184

3 Transient Analysis

Fig. 3.47 The sinusoidal components of the waveform

X ð1 : N Þ ¼

N X k 1 ¼1

X k1 δðk1Þ ¼

N X k 1 ¼1

0 @

N X

xk 2 e

j2π

 1 ðk2 1N2 Þðk2 1N2 Þ N Aδðk1Þ ð3:171Þ

k 2 ¼1

where xð 1 : N Þ ¼

N X

xk2 δðk2Þ

ð3:172Þ

k2 ¼1

As an example, a composite time-domain signal x(t) is created by     xðt Þ ¼ 7 sin 2π  106 t þ 5 sin 2π  2  106 t   þ 3 sin 2π  3  106 t

ð3:173Þ

The components of the signal x(t) are shown in Fig. 3.47. The composite signal x(t) is shown in Fig. 3.48. The time-domain signal x(t) is discretized and its corresponding spectrum is calculated using the fast Fourier transformation algorithm, as shown in Fig. 3.49. From the spectrum, the components of the composite signal can be distinctly observed. The composite signal consists of three sinusoidal with amplitudes of 7V, 5V, and 3V and frequencies of 1MHz, 2MHz, and 3MHz, respectively. The following MATLAB code calculates the Fast Fourier Transform of a composite signal and plots its transient waveform and spectrum.

3.9 Spectral Decomposition Using Fourier Series Fig. 3.48 The composite waveform

Fig. 3.49 Frequency components of the composite waveform

f0=1e06; np=10; nt=101; dt=1/(nt*f0); df=f0/np; time=0:dt:(np/f0)-dt; freq=0:df:(nt*f0)-df; N=np*nt;

185

186

3 Transient Analysis

sig1=7*sin(2*pi*1e06*time); sig2=5*sin(2*pi*2e06*time); sig3=3*sin(2*pi*3e06*time); sig=sig1+sig2+sig3; SIG1=[]; out=double.empty(0,1); for k1=1:N for k2=1:N out(k2)=sig(k2).*exp(-1i*2*pi*((-N/2)+k2-1)*((-N/2)+k1-1)/N); end tmp=[SIG1 sum(out)]; SIG1=tmp; end SIG2=fft(sig); figure plot(time,sig1) hold on plot(time,sig2) plot(time,sig3) figure plot(time,sig) figure semilogx(freq(1:round(end/2)),2*abs(SIG1(end-round(end/2)+1: end))/N) hold on semilogx(freq(1:round(end/2)),2*abs(SIG2(1:round(end/2)))/N,'--')

3.10

Spectral Characteristics

The quality of signals in communication systems is impacted by noise, harmonic distortions (HDs), intermodulation distortions (IMDs) and spurs that are undesired tones above the noise floor which are generated by the spectral interference of all distortion sources. The spectrum of a signal in the presence of major distortion sources is shown in Fig. 3.50. The signal quality can be characterized by the distance from the peak of the signal magnitude to the largest peak of the noise floor, spurs, harmonic, and intermodulation distortion tones. Among all distortive sources, the noise floor is the most critical for the weak signals and the third-order intermodulation distortion is the most critical for the strong signals.

2 HD

5 IMD

3rd HD

th

nd

3rd IMD

signal to spur

signal to noise

signal

signal to HD

187

signal to IMD

magnitude (dB)

Questions

spurs

noise floor f0

2f0

3f0

f

Fig. 3.50 Spectral characteristics of signal with noise, spurs, harmonic, and intermodulation distortions

3.11

Conclusions

Transient signal waveforms reveal important information such as linearity, delay, and swing. The time-domain transient analysis can utilize large signal and differential equations for characterizing linear and nonlinear circuits with aperiodic and periodic signals and switches. Transient analyses become accurate when simulation time steps are very small increasing simulation time. If a circuit is linear and timeinvariant and does not include switches during the simulation timeframe, an accurate analysis that does not depend on the time step can be performed using Laplace transformation. For analysis of linear and time-invariant circuits that include periodic signals using Laplace transformation, the circuit response in one period is first calculated and then added together for finding the circuit response over longer periods. Variants of transient analyses studied in this chapter are illustrated in Fig. 3.51.

Questions Answer the following questions using materials and codes you have learned in this chapter.

188

3 Transient Analysis

Fig. 3.51 An overview of this chapter topics

Linear and Nonlinear Circuits

Aperiodic and Periodic Signals

Switching Circuits

Laplace Transform

Differential Equations

Results Fig. 3.52 Circuit of Question 1

C1 1

L1

v1

Q.3.1 Write a code to plot the node voltages for the following circuit (Fig. 3.52). The input node 1 is connected to an arbitrary waveform given by

2 G1

Questions

189

Table 3.23 Parameter values of Question 1

v 1 ð t > 0Þ ¼

G1 1 mA/V

L1 10 μH

C1 1 nF

ω 2π  5  106 rad/s

     ωt π ωt U ðt Þ  U t  þ 2 π ω π        π 3π ωt  U t U t þ 1 ω 2ω π        3π 2π ωt U t þ 3  U t 2ω ω π      2π 3π  U t U t ω ω

ð3:174Þ

where U is the Heaviside step function. The circuit parameters are given by (Table 3.23) Answers:

Q.3.2 Write a code to plot the node voltages for the following circuit (Fig. 3.53). The circuit parameters are given by (Table 3.24) Answers:

190

3 Transient Analysis

Fig. 3.53 Circuit of Question 2

1

v1

Table 3.24 Parameter values of Question 2

G1 1 mA/V

G2 1 mA/V

sw1

G1

2 C1

C1 1 nF

Q.3.3 Write a code to plot the node voltages for the following circuit (Fig. 3.54). The circuit parameters are given by (Table 3.25)

3 G2

ton 2 μs

Questions

191

Fig. 3.54 Circuit of Question 3

1

G1 2

v1

Table 3.25 Parameter values of Question 3

G1 1 mA/V

sw1 3 C1

G2 1 mA/V

C1 1 nF

Answers:

Q.3.4 Write a code to plot the node voltages for the following circuit (Fig. 3.55). The circuit parameters are given by (Table 3.26)

G2

toff 2 μs

192

3 Transient Analysis

Fig. 3.55 Circuit of Question 4

1

v1

Table 3.26 Parameter values of Question 4

G1 1 mA/V

G2 1 mA/V

sw1

G1

3

2 L1

L1 1 mH

Answers:

Q.3.5 Write a code to plot the node voltages for the following circuit (Fig. 3.56). The circuit parameters are given by (Table 3.27)

G2

ton 2 μs

Questions

193

Fig. 3.56 Circuit of Question 5

1

G1 2

v1

Table 3.27 Parameter values of Question 5

Answers:

G1 1 mA/V

sw1 3 L1

G2 1 mA/V

L1 1 mH

G2

ton 2 μs

Chapter 4

AC Analysis

The AC analysis deals with the small-signal, linear and time invariant circuits. The analysis is done in s-domain and studies the frequency properties of the circuit transfer functions. The AC analysis is very straightforward and by applying the Laplace expansions to signals obtained by Cramer’s rules, a wide variety of transfer functions can be extracted from a single nodal analysis. This strong analysis tool will be used to analyze a wide variety of circuits as demonstrated in this chapter. An overview of this chapter topics is listed in the following table. Schematic Composing

Signals Ch. 1 Framework Components

Ch. 2

Ch. 3

DC Analysis

Transient Analysis

DC, Transient, AC and Noise modeling

Netlisting

Linear Equations

Direct Methods

Nonlinear Equations

Iterative Methods

DC Circuit Model

Linear Circuits

Aperiodic and Periodic Signals

Laplace Transform

Nonlinear Circuits

Switching Circuits

Differential Equations

Ch. 4

AC Analysis

Linearized s‐domain Model

Matrix Calculations

Ch. 5

Noise Analysis

Linearized s‐domain Model

Noise Matrix Calculations

Ch. 6

Behavioral Analysis

Block‐Level Modeling

Transfer Function Characteristics

Noise Transformation

Accuracy and Speed Tradeoff

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 S. Hamedi-Hagh, Computational Electronic Circuits, https://doi.org/10.1007/978-3-030-75568-3_4

195

196

4.1

4 AC Analysis

Admittance Matrix

All circuits in this book will be analyzed by applying Kirchhoff’s current laws to circuit nodes and generating admittance matrix obtained from systems of equations. The external connections of a general three-node circuit are shown in Fig. 4.1. External sources connected to the three-node circuit apply currents to these nodes and writing equations at these three nodes generates the system of equations required to analyze and characterize the circuit. To create systems of equations, the internal connectivity of the circuit is needed. The system of equations will be created for the general circuit shown in Fig. 4.2. The external current i1 applied to node 1 as shown in Fig. 4.1 passes through Y1, Y2, and Y6 components in Fig. 4.2. Current passing through Y1, Y2, and Y6 components enters from node 1 and exits from other nodes. Therefore, the positive polarity of the voltage drop across Y1, Y2, and Y6 components will be at node 1 and the negative polarity of the voltage drop will be at other nodes, as shown in Fig. 4.3. Applying Kirchhoff’s current law to node 1 of the circuit considering the polarities of the voltage drops and directions of the current flows results in Y 1 v1 þ Y 2 ðv1  v2 Þ þ Y 6 ðv1  v3 Þ ¼ i1

ð4:1Þ

The external current i2 applied to node 2 as shown in Fig. 4.1 passes through Y2, Y3, and Y4 components in Fig. 4.2. Current passing through Y2, Y3, and Y4 Fig. 4.1 External connections of a general three-node circuit

i1

3

1

i3

circuit

v3

v1 i2

2

v2

Fig. 4.2 A general threenode passive circuit

Y6 1

Y1

Y2

2

Y3

Y4

3

Y5

4.1 Admittance Matrix

197

Fig. 4.3 Ohm’s law at node 1 of the three-node circuit

Y6 2

1

Y1

Y2

Fig. 4.4 Ohm’s law at node 2 of the three-node circuit

Y4

Y3

3

Y5

Y6 2

1

Y1

Y2

3

Y3

Y4

Y5

Fig. 4.5 Ohm’s law at node 3 of the three-node circuit

1

Y6

Y2

Y1

2

Y3

3

Y4

Y5

components enters from node 2 and exits from other nodes. Therefore, the positive polarity of the voltage drop across Y2, Y3, and Y4 components will be at node 2 and the negative polarity of the voltage drop will be at other nodes, as shown in Fig. 4.4. Applying Kirchhoff’s current law to node 2 of the circuit considering the polarities of the voltage drops and directions of the current flows results in Y 2 ðv2  v1 Þ þ Y 3 v2 þ Y 4 ðv2  v3 Þ ¼ i2

ð4:2Þ

The external current i3 applied to node 3 as shown in Fig. 4.1 passes through Y4, Y5, and Y6 components in Fig. 4.2. Current passing through Y4, Y5, and Y6 components enters from node 3 and exits from other nodes. Therefore, the positive polarity of the voltage drop across Y4, Y5, and Y6 components will be at node 3 and the negative polarity of the voltage drop will be at other nodes, as shown in Fig. 4.5. Applying Kirchhoff’s current law to node 3 of the circuit considering the polarities of the voltage drops and directions of the current flows results in Y 6 ðv3  v1 Þ þ Y 4 ðv3  v2 Þ þ Y 5 v3 ¼ i3

ð4:3Þ

198

4 AC Analysis

From three (4.1), (4.2), and (4.3) equations, the following system of equations in matrix format is extracted. 2 6 4

Y1 þ Y2 þ Y6

Y 2

Y 6

Y 2

Y2 þ Y3 þ Y4

Y 6

Y 4

32

v1

3

2

i1

3

76 7 6 7 54 v2 5 ¼ 4 i2 5 Y4 þ Y5 þ Y6 v3 i3 Y 4

ð4:4Þ

The 3  3 matrix is called admittance matrix and is given by 2

Y1 þ Y2 þ Y6 6 Y ¼4 Y 2

Y 2 Y2 þ Y3 þ Y4

Y 6 Y 4

Y 4

Y4 þ Y5 þ Y6

Y 6

2

Y 1,1 6 ¼ 4 Y 2,1 Y 3,1

Y 1,2

Y 1,3

3

3 7 5

7 Y 2,3 5 Y 3,3

Y 2,2 Y 3,2

ð4:5Þ

All circuit information exists in the admittance matrix and all circuit transfer functions can be directly extracted from the admittance matrix.

4.2

Cramer’s Rules

The system of equations for a three-node circuit in general format is given by 2

Y 1,1

6 4 Y 2,1 Y 3,1

Y 1,2 Y 2,2 Y 3,2

Y 1,3

32

v1

3

2

i1

3

76 7 6 7 Y 2,3 54 v2 5 ¼ 4 i2 5 Y 3,3 v3 i3

ð4:6Þ

Node voltages form dependent parameters and can be obtained by 2

v1

3

2

Y 1,1

6 7 6 4 v2 5 ¼ 4 Y 2,1 v3 Y 3,1

Y 1,2 Y 2,2 Y 3,2

Y 1,3

31 2

i1

3

7 6 7 Y 2,3 5 4 i2 5 Y 3,3 i3

ð4:7Þ

Calculating and reorganizing this matrix results into Cramer’s rules presented by the following expressions. The node voltages are obtained by

4.3 Laplace Expansion

199

ð4:8Þ

and

ð4:9Þ

and

ð4:10Þ

Transfer functions of the general three-node circuit are obtained by expanding the numerators of the node voltages.

4.3

Laplace Expansion

Laplace expansion is used to calculate a determinant. For any determinant of order n, n cofactors can be defined. These cofactors are selected from elements in a row or a column of the determinant. Any row or column can be selected for generating cofactors. For any cofactor, a unique determinant minor can be extracted. The minor is formed when the row and column of the cofactor in the admittance matrix are truncated. The sign of each cofactor is determined by the summation of the row and column of the cofactor. For even numbers, sign is positive and for odd numbers, sign is negative. As an example, the determinant of the numerator in v1 expression (Eq. (4.8)) is calculated by choosing cofactors from the first column. These cofactors are i1, i2, and i3. To extract determinant minor corresponding to i1, the  first row and the first  Y 2,2 Y 2,3   . The sign of column of the main determinant are truncated resulting  Y Y  3,2

3,3

the i1 cofactor is calculated by (1)1 + 1. To extract determinant minor correspong to i2, the second row and   the first column of the main determinant are truncated  Y 1,2 Y 1,3   . The sign of the i2 cofactor is calculated by (1)2 + 1. To resulting  Y Y  3,2

3,3

200

4 AC Analysis

extract determinant minor correspong to i3, the third row  and the first column of the  Y 1,2 Y 1,3  . The sign of the i3 cofactor is main determinant are truncated resulting  Y Y  2,2

calculated by (1)3 calculated by

+ 1

2,3

. Therefore, the determinant using Laplace expansion is

ð4:11Þ Calculating node voltages using Laplace expansion applied to the expressions from Cramer’s rules results in the following equations. The node voltages are given by

ð4:12Þ

and

ð4:13Þ

and

ð4:14Þ

Each node voltage is calculated by the linear summation of responses made by all external sources connected to the circuit.

4.4

Applying Voltage or Current Sources to a Circuit

A signal can be applied to a circuit using either a voltage source or a current source, as shown in Fig. 4.6.

4.4 Applying Voltage or Current Sources to a Circuit

node i

ii

circuit

vi

201

node io o

vo

vi

node i

circuit

io

ii

Yo

node o

vo Yo

Yin

Yin (a)

(b)

Fig. 4.6 Driving a circuit with (a) Voltage and (b) Current sources

In both circuits, the following relationships are valid. ii ¼ Y in vi

ð4:15Þ

io ¼ Y o vo

ð4:16Þ

and

where Yin is the total admittance seen at the input node i and Yo is the shunt admittance connected to the output node o of the circuit. If the voltage-gain vvoi , the total input admittance Yin and the output shunt admittance Yo are known, all input and output voltages and currents (vi, vo, ii, and io) can be obtained and all circuit transfer functions can be calculated. The transadmittance gain of the circuit is calculated by i o Y o vo v ¼ ¼ Yo  o vi vi vi

ð4:17Þ

The transimpedance gain of the circuit is calculated by vo v 1 v ¼ o ¼  o ii Y in vi Y in vi

ð4:18Þ

The current gain of the circuit is calculated by i o Y o vo Y o vo ¼ ¼  ii Y in vi Y in vi

ð4:19Þ

The voltage-gain (vvoi ) and the input admittance (viii ) provide fundamental information in analysis of any circuit. After calculating these two transfer functions, all other circuit transfer functions can be extracted with no further analysis. The difference between driving a circuit using either a voltage source or a current source lies in the internal resistance of these two types of sources. The internal resistances of voltage sources are very small making these sources behave as short connections. The internal resistances of current sources are very large making these

202

4 AC Analysis

sources behave as open connections. These two important properties are very useful when analyzing circuits with multiple input sources using superposition. This will be explained in the next section.

4.5

Circuits with Multiple Input Sources

An example of a circuit with two input sources is shown in Fig. 4.7. A current-type source iS1 is connected to node i1 is and a voltage-type source vS2 is connected to node i2. The voltage at the output node of the circuit is generally given by vo ¼ iS1  TF1 þ vS2  TF2

ð4:20Þ

The first transfer function TF1 is given by TF1 ¼

1 v  o Y in1 vi1

ð4:21Þ

and the second transfer function TF2 is given by TF2 ¼

vo vi2

ð4:22Þ

To calculate the first transfer function TF1, the source vS2 connected to node i2 must be disabled by setting vS2 ¼ 0. It is important to remember that a disabled voltage source has a zero internal resistance while calculating the TF1 using the testbench shown in Fig. 4.8. To calculate the second transfer function TF2, the source iS1 connected to node i1 must be disabled by setting iS1 ¼ 0. It is important to remember that a disabled current source has an infinite internal resistance while calculating the TF2 using the testbench shown in Fig. 4.9. Fig. 4.7 Driving a circuit with (a) Voltage and (b) Current sources

vi1

ii1 node i1

iS1

Yin1 vi2

ii2 node i2

vS2

Yin2

circuit

node io o

vo

Yo

4.6 Shorting a Circuit Node Fig. 4.8 Testbench for calculating TF1

203

vi1

ii1 node i1

iS1

Yin1

circuit

vi2

vo

node i2

vS2=0

Fig. 4.9 Testbench for calculating TF2

node io o

Yo

vi1 node i1

iS1=0

vi2

circuit

ii2

node io o

vo

node i2

vS2

Yo

Yin2

Fig. 4.10 A three-node circuit

Y6 1

Y1

Y2

2

Y3

Y4

3

Y5

Disabling a voltage source is analogous to replacing it with a wire because a wire has zero resistance and zero voltage drop across it and disabling a current source is analogous to replacing it with an open circuit because an open circuit has infinite resistance with zero current flow through it.

4.6

Shorting a Circuit Node

Shorting the circuit node x to the ground is equivalent to truncating the xth row and the xth column from the original admittance matrix. As an example, the admittance matrices of a three-node circuit shown in Fig. 4.10 will be regenerated from the original admittance matrix when nodes of the circuit are shorted to the ground.

204

4 AC Analysis

The new admittance matrix of the circuit when its node 1 is shorted to the ground is given by ð4:23Þ The new admittance matrix of the circuit when its node 2 is shorted to the ground is given by ð4:24Þ The new admittance matrix of the circuit when its node 3 is shorted to the ground is given by ð4:25Þ The new admittance matrix of the circuit when its nodes 1 and 2 are shorted to the ground is given by ð4:26Þ The new admittance matrix of the circuit when its nodes 1 and 3 are shorted to the ground is given by ð4:27Þ The new admittance matrix of the circuit when its nodes 2 and 3 are shorted to the ground is given by ð4:28Þ This algorithm can be easily programmed for the AC analysis of any circuit.

4.7

Fundamental Transfer Functions

From the Laplace expansion of circuit signals obtained from Cramer’s rules (such as 4.12, 4.13, and 4.14 equations), fundamental transfer functions of a circuit can be extracted by the ratio of admittance matrix determinants while some rows and columns are truncated in the transfer functions.

4.7 Fundamental Transfer Functions

205

The voltage-gain transfer function of a circuit from the input node i to the output node o with only one input voltage source connected to node i is calculated by

ð4:29Þ

The bars that pass horizontally and vertically represent the rows and columns that must be truncated in the admittance matrix. The voltage-gain transfer function of a circuit from the input node i to the output node o with the input voltage source connected to node i and other voltage sources connected to nodes x is calculated by

ð4:30Þ

The input node admittance (or conductance if there is no imaginary part) transfer function of a circuit at node i without voltage sources connected to other nodes is calculated by

ð4:31Þ

The input node admittance (or conductance if there is no imaginary part) transfer function of a circuit at node i with voltage sources connected to nodes x is calculated by

206

4 AC Analysis

ð4:32Þ

The output node admittance (or conductance if there is no imaginary part) transfer function of a circuit at node o when there is no voltage source connected to the circuit is calculated by

ð4:33Þ

The output node admittance (or conductance if there is no imaginary part) transfer function of a circuit at node o with voltage sources connected to nodes x is calculated by

ð4:34Þ

After the admittance matrix of a circuit is obtained using Ohm’s and Kirchhoff’s laws, all transfer functions of the circuit are easily extracted using the presented general transfer functions. The following MATLAB code calculates the voltage-gain, the input and the output admittances of a 3-node circuit from the admittance matrix using Cramer’s rules.

4.7 Fundamental Transfer Functions

207

syms s G1 G2 G3 G4 G5 syms v1 v2 v3 syms i1 [Y]=equationsToMatrix([... G1*v1+G2*(v1-v2)==i1,... G3*v2+G2*(v2-v1)+G4*(v2-v3)==0,... G5*v3+G4*(v3-v2)==0,... ],[v1,v2,v3]); in=1; out=3; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp('voltage-gain vo/vi :') pretty(vgain) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp('input admittance ii/vi :') pretty(Yin) Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp('output admittance io/vo :') pretty(Yout)

4.7.1

Example 1

The first practice circuit is shown in Fig. 4.11. There are an independent source v1 (AC) and a dependent source Ym1v1 that depends on AC voltage signal. Circuit parameters are listed in Table 4.1.

i1

Fig. 4.11 Practice circuit 1

v1

1 R1 R2

Ym1v1

R3 2

208 Table 4.1 Component values

4 AC Analysis

R1 1 kΩ

R2 1 2 kΩ

Fig. 4.12 Π-arrayed circuit

i1 v1

Fig. 4.13 KCL at node 1

R3 1 3 kΩ

G2

1

G1

i1

v1

v1

2

Ym1v1

G3

v2

G2

G1

Fig. 4.14 KCL at node 2

Ym1 4 mA/V

Ym1v1

G3

G1

i2

v2

G2

G3

Ym1v1

First, the circuit is reorganized in Π-arrayed structure, as shown in Fig. 4.12. Resistors are also represented by their conductance values to simplify the terms in the admittance matrix. Objectives of AC analysis would be finding voltage-gains, current gains, transimpedance, transadmittance, node impedance (resistance), node admittance (conductance), and power gain transfer functions of the circuit as well as component powers. The circuit shown in Fig. 4.13 is used to extract the KCL at node 1. The KCL at node 1 of the circuit is given by G1 v1 þ G2 ðv1  v2 Þ ¼ i1 The circuit shown in Fig. 4.14 is used to extract the KCL at node 2. The KCL at node 2 of the circuit is given by

ð4:35Þ

4.7 Fundamental Transfer Functions

209

Ym1 v1 þ G2 ðv2  v1 Þ þ G3 v2 ¼ i2

ð4:36Þ

The system of equations in matrix format is given by 

G1 þ G2

G2

G2  Ym1

G2 þ G3



v1



v2

 ¼

i1

 ð4:37Þ

i2

The admittance matrix of the circuit is given by  Y¼

Y1,1

Y1,2

Y2,1

Y2,2



 ¼

G1 þ G2

G2

G2  Ym1

G2 þ G3

 ð4:38Þ

The first node is the input node (i ¼ 1) and the second node is the output node (o ¼ 2). The voltage-gain of the circuit is given by

ð4:39Þ

The input conductance of the circuit is given by

ð4:40Þ

The output conductance of the circuit is given by

ð4:41Þ

AC transfer functions of circuit 1 are listed in Table 4.2.

210

4 AC Analysis

Table 4.2 AC transfer functions Transfer functions

i ¼ node 1 o ¼ node 2

1.2 V/V

0.6m A/V

5m A/V

The following MATLAB code calculates the voltage-gain, the input and the output admittances of the circuit in this example from the admittance matrix using Cramer’s rules.

syms v1 v2 syms i1 syms xs gz=1e06; G1=1e-03; G2=2e-03; G3=3e-03; Ym1=4e-03; [Y]=equationsToMatrix([... gz*(xs-v1)==i1;... gz*(v1-xs)+G1*v1+G2*(v1-v2)==0;... G2*(v2-v1)+G3*v2-Ym1*v1==0,... ],[xs,v1,v2]); %AC equations in=1; out=3; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')])

4.7 Fundamental Transfer Functions

211

i1

Fig. 4.15 Circuit 2

1 R4

R1

v1

R2 Ym1v1

R3

Va 2

Table 4.3 Component values

R1 1 kΩ

R2 1 2 kΩ

R3 1 3 kΩ

R4 1 4 kΩ

Fig. 4.16 Π-arrayed circuit

1

G1

Va 2V

Va

G4

i1

4.7.2

Ym1 - 5 mA/V

G2

2

G3

Ym1v1

Example 2

The circuit shown in Fig. 4.15 is analyzed in this example. There are two independent sources i1 (AC) and Va (DC) in the circuit. There is a dependent source Ym1v1 that only depends on AC signals. As a result, circuit will be different with respect to DC and AC signals and superposition must be used to analyze the circuit. Circuit parameters are listed in Table 4.3. First, the circuit is reorganized in Π-arrayed structure, as shown in Fig. 4.16. Resistors are represented by their conductance values to simplify the terms in the admittance matrix. The node shown with the red dot is redundant because no information is required to be calculated for this node. If any information needed to be extracted for this node, the circuit 2 would be considered to have 3 nodes. Here, the redundant node (red dot) is eliminated by source transformation and the two parallel conductors G2 and G4 are added together, as shown in Fig. 4.17.

212

4 AC Analysis

Fig. 4.17 Elimination of redundant node

G4Va

i1

G2+G4

1

G1

i1

Fig. 4.18 AC model

i1

v1

Ym1v1

G3

v1

v2

G2+G4

G1

Fig. 4.19 KCL at node 1

2

Ym1v1

G3

G2+G4

G1

v2

G3

Ym1v1

Objectives of AC analysis would be finding voltage-gains, current gains, transimpedance, transadmittance, node impedance (resistance), node admittance (conductance), and power gain transfer functions of the circuit as well as component powers. To create AC model of the circuit, DC sources will be discarded (the DC voltage sources will be replaced by a short model and the DC current sources will be replaced by open models). The AC model of the circuit is shown in Fig. 4.18. The circuit shown in Fig. 4.19 is used to extract the KCL at node 1. The KCL at node 1 of the circuit is given by G1 v1 þ ðG2 þ G4 Þðv1  v2 Þ ¼ i1 The circuit shown in Fig. 4.20 is used to extract the KCL at node 2. The KCL at node 2 of the circuit is given by

ð4:42Þ

4.7 Fundamental Transfer Functions

213

Fig. 4.20 KCL at node 2

v1 G1

i2

v2

G2+G4

Ym1v1

G3

Ym1 v1 þ ðG2 þ G4 Þðv2  v1 Þ þ G3 v2 ¼ i2

ð4:43Þ

The system of equations in matrix format is given by 

G1 þ G2 þ G4 G2  G4  Ym1

G2  G4 G2 þ G3 þ G4



v1 v2





i1 ¼ i2

 ð4:44Þ

The admittance matrix of the circuit is given by  Y¼

Y1,1

Y1,2

Y2,1

Y2,2



 ¼

G1 þ G2 þ G4

G2  G4

G2  G4  Ym1

G2 þ G3 þ G4

 ð4:45Þ

The first node is the input node (i ¼ 1) and the second node is the output node (o ¼ 2). The voltage-gain of the circuit is given by

ð4:46Þ

The input conductance of the circuit is given by

ð4:47Þ

The output conductance of the circuit is given by

214

4 AC Analysis

Table 4.4 AC transfer functions Transfer functions

i ¼ node 1 o ¼ node 2

0.111 V/V

6.33m A/V

8.143m A/V

ð4:48Þ

AC transfer functions of circuit 2 are listed in Table 4.4. The following MATLAB code calculates the voltage-gain, the input and the output admittances of the circuit in this example from the admittance matrix using Cramer’s rules.

syms v1 v2 syms i1 syms xs gz=1e06; G1=1e-03; G2=2e-03; G3=3e-03; G4=4e-03; Ym1=-5e-03; [Y]=equationsToMatrix([... G1*v1+(G2+G4)*(v1-v2)==i1;... (G2+G4)*(v2-v1)+G3*v2-Ym1*v1==0,... ],[v1,v2]); %AC equations in=1; out=2; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')])

4.7 Fundamental Transfer Functions

215

Fig. 4.21 Circuit 3

v1

1 R1

ia R3

R2 2

R5

Ym1v1

R6 Zm1ia

R4

R3

AV1v1

Ib

3

Table 4.5 Component values R1 1 kΩ

R2 1 2 kΩ

R3 1 3 kΩ

R4 1 4 kΩ

R5 1 5 kΩ

R6 1 6 kΩ

Av1 5 V/V

Ym1 5 mA/V

Zm1 5 V/A

Ib 10 mA

Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y)/det(Y((1:end)~=out,(1:end)~=out)); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')])

4.7.3

Example 3

The circuit shown in Fig. 4.21 is analyzed in this example. There are two independent sources v1 (AC) and Ib (DC) in the circuit. There are three dependent sources Ym1v1, Av1v1, and Zm1ia that only depends on AC signals. As a result, circuit will be different with respect to DC and AC signals and superposition must be used to analyze the circuit. There are two redundant nodes in the circuit shown with red dots that can be eliminated for simplification. Circuit parameters are listed in Table 4.5. First, the circuit is reorganized in Π-arrayed structure, as shown in Fig. 4.22. Resistors are represented by their conductance values to simplify the terms in the admittance matrix. The circuit after the two redundant nodes are eliminated using source transformation is shown in Fig. 4.23. Objectives of AC analysis would be finding voltage-gains, current gains, transimpedance, transadmittance, node impedance (resistance), node admittance (conductance), and power gain transfer functions of the circuit as well as component powers. To create AC model of the circuit, DC sources will be discarded (DC voltage sources will be shorted and DC current sources will be opened). There are no DC sources in the circuit and the AC model is similar to the circuit shown in Fig. 4.23.

216

4 AC Analysis

Fig. 4.22 Π-arrayed circuit

Zm1ia

G6 G2

1

v1

G1

ia

AV1v1

G4

2

Ym1v1

G3

Fig. 4.23 Elimination of redundant node

3

G5

Ib

G6 G6Zm1ia G4 G2

1

v1

G1

2

G3

ia

Fig. 4.24 Final AC model

G4AV1v1

Ym1v1

3

G5

G6 G1G6Zm1v1 G4 1

v1

G1

G2

2

G3

G4AV1v1

Ym1v1

3

G5

The dependent source G6Zm1ia can be modified to replace current ia with node voltage v1, as shown in Fig. 4.24. The circuit shown in Fig. 4.25 is used to extract the KCL at node 1. The KCL at node 1 of the circuit is given by

4.7 Fundamental Transfer Functions

217

Fig. 4.25 KCL at node 1

G6 G1G6Zm1v1 G4 G2

1

2

G3

G1

G4AV1v1

Ym1v1

3

G5

i1 Fig. 4.26 KCL at node 2

G6 G1G6Zm1v1 G4 G2

1

2

G3

G1

G4AV1v1

Ym1v1

3

G5

i2 G1 v1 þ G2 ðv1  v2 Þ þ G6 ðv1  v3 Þ þ G1 G6 Zm1 v1 ¼ i1

ð4:49Þ

The circuit shown in Fig. 4.26 is used to extract the KCL at node 2. The KCL at node 2 of the circuit is given by G4 Av1 v1  Ym1 v1 þ G2 ðv2  v1 Þ þ G3 v2 þ G4 ðv2  v3 Þ ¼ i2 The circuit shown in Fig. 4.27 is used to extract the KCL at node 3. The KCL at node 3 of the circuit is given by

ð4:50Þ

218

4 AC Analysis

Fig. 4.27 KCL at node 3

G6 G1G6Zm1v1 G4 G2

1

G4AV1v1

2

G3

G1

Ym1v1

3

G5

i3 G1 G6 Zm1 v1  G4 Av1 v1 þ G6 ðv3  v1 Þ þ G4 ðv3  v2 Þ þ G5 v3 ¼ i3

ð4:51Þ

The system of equations in matrix format is given by 2 6 4

G1 þ G2 þ G6 þ G1 G6 Zm1

G2

G6

AV1 G4  Ym1  G2

G2 þ G3 þ G4

AV1 G4  G1 G6 Zm1  G6 2 3 i1 6 7 ¼ 4 i2 5

G4

32

v1

3

76 7 5 4 v2 5 G4 þ G5 þ G6 v3 G4

ð4:52Þ

i3 The admittance matrix of the circuit is given by 2

Y1,1

Y1,2

Y1,3

3

6 7 Y ¼ 4 Y2,1 Y2,2 Y2,3 5 Y3,1 Y3,2 Y3,3 2 G1 þ G2 þ G6 þ G1 G6 Zm1 6 AV1 G4  Ym1  G2 ¼4 AV1 G4  G1 G6 Zm1  G6

G2 G2 þ G3 þ G4 G4

G6

3

7 G4 5 G4 þ G5 þ G6

ð4:53Þ

The first node is the input node (i ¼ 1) and the second node is the output node (o ¼ 3). The voltage-gain of the circuit is given by

4.7 Fundamental Transfer Functions

219

ð4:54Þ The input conductance of the circuit is given by

ð4:55Þ

The output conductance of the circuit is given by

ð4:56Þ

AC transfer functions of circuit 2 are listed in Table 4.6. The following MATLAB code calculates the voltage-gain, the input and the output admittances of the circuit in this example from the admittance matrix using Cramer’s rules.

Table 4.6 AC transfer functions Transfer functions

i ¼ node 1 o ¼ node 2

1.53 V/V

1.367m A/V

13.22m A/V

220

4 AC Analysis

syms v1 v2 v3 syms i1 syms xs gz=1e06; G1=1e-03; G2=2e-03; G3=3e-03; G4=4e-03; G5=5e-03; G6=6e-03; Av1=5; Ym1=5e-03; Zm1=5; [Y]=equationsToMatrix([... gz*(xs-v1)==i1;... gz*(v1-xs)+G1*v1+G2*(v1-v2)+G6*(v1-v3)+G1*G6*Zm1*v1==0;... G2*(v2-v1)+G3*v2+G4*(v2-v3)-Ym1*v1+G4*Av1*v1==0;... G6*(v3-v1)+G4*(v3-v2)+G5*v3-G1*G6*Zm1*v1-G4*Av1*v1==0,... ],[xs,v1,v2,v3]); %AC equations in=1; out=4; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) tgain=((-1)^(in+out))*det(Y)/det(Y((1:end)~=out,(1:end)~=in)); disp(['transadmittance gain io/vi = ',num2str(double (tgain),'%.4e')]) igain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=out,(1:end)~=out)); disp(['current gain io/ii = ',num2str(double(igain),'%.4e')]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')])

4.7 Fundamental Transfer Functions

221

Fig. 4.28 Circuit 4

C1

1

C2

2

G1

G3 L1

Ia

i1

3

G2

Vb

Ic

Table 4.7 Component values R1 1 kΩ

R2 1 2 kΩ

R3 1 3 kΩ

R4 1 4 kΩ

C1 100 pF

C2 100 pF

L1 10 nH

Ia 5 mA

Fig. 4.29 Π-arrayed circuit

Ic 10 mA

G4

1

i1

4.7.4

Vb 2V

C1

C2

2

3

L1 Ia

G2

G1

G3

Ic

Vb

Example 4

The circuit shown in Fig. 4.28 is analyzed in this example. There are two independent sources v1 (AC) and Ib (DC) in the circuit. There are three dependent sources Ym1v1, Av1v1, and Zm1ia that only depends on AC signals. As a result, circuit will be different with respect to DC and AC signals and superposition must be used to analyze the circuit. There is one redundant node in the circuit shown with a red dot that can be eliminated for simplification. Circuit parameters are listed in Table 4.7. First, the circuit is reorganized in Π-arrayed structure, as shown in Fig. 4.29. Resistors are represented by their conductance values to simplify the terms in the admittance matrix. Objectives of AC analysis would be finding voltage-gains, current gains, transimpedance, transadmittance, node impedance (resistance), node admittance (conductance), and power gain transfer functions of the circuit as well as component powers. To create AC model of the circuit, DC sources will be discarded

222

4 AC Analysis

Fig. 4.30 AC model

G4 C1vC1(0) sC1

1

i1

C2vC2(0)

G1

sC2

2

1/sL1

iL1(0)/s

Fig. 4.31 KCL at node 1

G2

3

G3

G4 1

G1

sC1

sC2

2

1/sL1

G2

3

G3

i1+C1vC1(0) (DC voltage sources will be shorted and DC current sources will be opened). The AC model of the circuit 2 is shown in Fig. 4.30. The circuit shown in Fig. 4.31 is used to extract the KCL at node 1. The KCL at node 1 of the circuit is given by G1 v1 þ sC1 ðv1  v2 Þ þ G4 ðv1  v3 Þ ¼ i1 þ C1 vC1 ð0Þ

ð4:57Þ

The circuit shown in Fig. 4.32 is used to extract the KCL at node 2. The KCL at node 2 of the circuit is given by   sC1 ðv2  v1 Þ þ G2 þ 1=sL1 v2 þ sC2 ðv2  v3 Þ ¼ iL1 ð0Þ  C1 vC1 ð0Þ þ C2 vC2 ð0Þ The circuit shown in Fig. 4.33 is used to extract the KCL at node 3. The KCL at node 3 of the circuit is given by

ð4:58Þ

4.7 Fundamental Transfer Functions

223

Fig. 4.32 KCL at node 2

G4 1

sC1

G1

sC2

2

1/sL1

3

G3

G2

iL1(0)/s-C1vC1(0)+C2vC2(0) Fig. 4.33 KCL at node 3

G4 1

sC1

G1

sC2

2

1/sL1

G2

3

G3

-C1vC1(0) G4 ðv3  v1 Þ þ sC2 ðv3  v2 Þ þ G3 v3 ¼ C2 vC2 ð0Þ

ð4:59Þ

The systems of equations in matrix format is given by 2 6 4

G1 þ G4 þ sC1 sC1 G4

sC1

G2 þ sðC1 þ C2 Þ þ 1=sL1 sC2 2 3 i1 þ C1 vC1 ð0Þ 6 7 ¼ 4 iL1 ð0Þ  C1 vC1 ð0Þ þ C2 vC2 ð0Þ 5 C2 vC2 ð0Þ

G4

32

v1

3

76 7 sC2 54 v 2 5 G3 þ G4 þ sC2 v3

The admittance matrix of the circuit is given by

ð4:60Þ

224

4 AC Analysis

2

Y1,1 6 Y ¼ 4 Y2,1

Y1,2 Y2,2

3 Y1,3 7 Y2,3 5

Y3,1

Y3,2

Y3,3

2

G1 þ G4 þ sC1 6 ¼4 sC1 G4

sC1 G2 þ sðC1 þ C2 Þ þ 1=sL1

G4 sC2

sC2

G3 þ G4 þ sC2

3 7 5

ð4:61Þ

The first node is the input node (i ¼ 1) and the second node is the output node (o ¼ 3). The voltage-gain of the circuit is given by

ð4:62Þ The input conductance of the circuit is given by

ð4:63Þ

The output conductance of the circuit is given by

ð4:64Þ

AC transfer functions of circuit 2 are listed in Table 4.8. The following MATLAB code calculates the voltage-gain, the input and the output admittances of the circuit in this example from the admittance matrix using Cramer’s rules.

4.7 Fundamental Transfer Functions

225

Table 4.8 AC transfer functions Transfer functions

i ¼ node 1 o ¼ node 2

0.57 V/V

2.71m A/V

3.8m A/V

syms v1 v2 v3 syms i1 syms xs s gz=1e06; G1=1e-03; G2=2e-03; G3=3e-03; G4=4e-03; C1=100e-12; C2=100e-12; L1=10e-09; vC10=0; vC20=0; iL10=0; [Y]=equationsToMatrix([... G1*v1+s*C1*(v1-v2)+G4*(v1-v3)==i1+C1*vC10;... s*C1*(v2-v1)+(G2+1/(s*L1+1/gz))*v2+s*C2*(v2-v3)==iL10/s+C2*vC20C1*vC10;... G4*(v3-v1)+s*C2*(v3-v2)+G3*v3==-C2*vC20,... ],[v1,v2,v3]); Y=subs(Y,s,1i*2*pi*0); %AC equations in=1; out=3; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y)/det(Y((1:end)~=out,(1:end)~=out)); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')])

226

4.8

4 AC Analysis

Taylor Expansion

The AC analysis for the linear time invariant (LTI) circuits provides important information such as poles, zeros, stability, phase margin, voltage, and gain transfer functions that are not easily obtained using transient analysis. However, transient analysis can solve any nonlinear circuit using discretized differential and integral equations. Circuits with nonlinear components such as diodes and transistors must be linearized before AC analysis. As a result, important information such as harmonics and intermodulation distortions will be lost. To linearize nonlinear circuits for AC analysis, the Taylor expansion series is used to approximate the transfer characteristics of diodes and transistors. In devices like diodes, the current depends mainly on the biasing voltage. A diode can be considered as a single variable nonlinear device and its current can be linearized using the following Taylor expansion series.  1 X Δxk d k f ðxÞ f ðx0 þ ΔxÞ ¼ f ðx0 Þ þ k! dxk x¼x0 k¼1

ð4:65Þ

The function f(x) represents the instantaneous diode current Id, the variable x represents the instantaneous diode voltage Vd, the fixed variable x0 represents the DC biasing voltage vd applied across the diode and the variation Δx represents the AC voltage swing vd applied to the diode. The Taylor expansion series is expanded as f ðx0 þ ΔxÞ ¼ f ðx0 Þ þ Δx

   df ðxÞ ðΔxÞ2 d 2 f ðxÞ ðΔxÞ3 d3 f ðxÞ þ þ þ ... dx x¼x0 2! 3! dx2 x¼x0 dx3 x¼x0 ð4:66Þ

Under certain conditions, the nonlinear terms that include higher exponents such as (Δx)2, (Δx)3 become negligible if the linear term that includes Δx becomes dominant. This is called the small-signal operation. The Taylor expansion series in this case is simplified to  df ðxÞ f ðx0 þ ΔxÞ  f ðx0 Þ  Δx dx x¼x0 |fflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}

ð4:67Þ

AC variation

where f(x0 + Δx)  f(x0) can represent the AC current swing id of the diode. The large-signal transfer characteristics of the diode relates its instantaneous current and voltage together and is given by  VD I D ¼ I S enV T  1

ð4:68Þ

4.8 Taylor Expansion

227

Linearizing the large-signal diode transfer characteristics using the Taylor expansion series yields an equation that creates the small-signal AC model of the diode and relates the AC current and the AC voltage of the diode together as i D  vD

∂I D I ¼ D v D ¼ gd v D ∂V D nV T

ð4:69Þ

To create the linearized AC model of the diode, first the DC analysis must be performed in order to find the DC biasing voltage and current of the diode. From the DC analysis, the diode conductance gd is calculated and the simplified AC model is used in the linearized AC analysis. For semiconductor devices like transistors, the current transfer characteristics might depend on more than two voltages. For example, in MOSFETs the drain current ID(VGS, VDS) mainly depends on two gate-source and drain-source voltages and in BJTs the collector current IC(VBE, VCE) mainly depends on two base-emitter and collector-emitter voltages. In these cases, the two-variable Taylor expansion series is used in order to linearize MOSFETs and BJTs. 0 f ðx0 þ Δx, y0 þ ΔyÞ ¼ f ðx0 , y0 Þ þ

1

 1 k B C X d k f ðx, yÞ  1 XB k! C ðΔxÞkn ðΔxÞn kn n  x ¼ x C B 0A k! n¼0 @n!ðk  nÞ! dx dy k¼1 y ¼ y0

ð4:70Þ The two-variable Taylor expansion series is expanded as   df ðx, yÞ df ðx, yÞ f ðx0 þ Δx, y0 þ ΔyÞ ¼ f ðx0 , y0 Þ þ Δx þ Δy dx  x ¼ x0 dy  x ¼ x0 y ¼ y0

0

y ¼ y0

1

   B C 2 2   d2 f ðx, yÞ 1B C 2 d f ðx, yÞ 2 d f ðx, yÞ þ BðΔxÞ þ 2ΔxΔy þ ð Δy Þ    x ¼ x0 x ¼ x0 C dxdy x ¼ x0 2! @ dx2 dy2 A 0

y ¼ y0

y ¼ y0

y ¼ y0

  B 3  d3 f ðx, yÞ 1B 3 d f ðx, yÞ 2 þ BðΔxÞ þ 3ðΔxÞ Δy 3! @ dx3  x ¼ x0 dx2 dy  x ¼ x0 y ¼ y0 þ3ΔxðΔyÞ2

y ¼ y0 1

  C 3  d 3 f ðx, yÞ C 3 d f ðx, yÞ þ ð Δy Þ C þ ...   2 3 x ¼ x x ¼ x 0 0A dxdy dy y ¼ y0

y ¼ y0 ð4:71Þ

228

4 AC Analysis

To linearize transistors, the small-signal condition must be satisfied to ensure the linear terms that include Δx and Δy become dominant and nonlinear terms that include higher exponents such as (Δx)2 and (Δy)2 become negligible. The two-variable Taylor expansion series can be simplified to f ðx0 þ Δx, y0 þ ΔyÞ  f ðx0 , y0 Þ  Δx |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}

  df ðx, yÞ df ðx, yÞ þ Δy dx  x ¼ x0 dy  x ¼ x0

AC variation

y ¼ y0

y ¼ y0 ð4:72Þ

The results can be used to create linearized AC model for transistors from their instantaneous current transfer characteristics. The exact model of the transistors and diode were presented in detail in Chap. 1. When different transfer characteristics or functions are linearized and approximated by the Taylor expansion series, they will introduce errors in simulations. To reduce these errors, a greater number of terms must be included in the expanded Taylor series and the variable swings must be kept at minimum to satisfy the smallsignal operation. The following MATLAB code calculates the errors introduced by linearizing a nonlinear function.

syms x Dx N=6; equ=2.0*cos(0.5*x)+0.5*sin(2.0*x); f0=matlabFunction(equ); x0=0; xf=1; xk=linspace(x0,xf,11); dx=gradient(xk); disp(['time steps : ',num2str(xk(2:end),'%0.3e ')]) fprintf('\n') disp(['original signal : ',num2str(f0(xk(2:end)),'%0.3e ')]) fprintf('\n') figure plot(NaN,NaN) hold on for k2=N:-1:2 eqs=sym(0); for k1=0:k2 eqs=sum(eqs+Dx^k1*diff(equ,k1)/factorial(k1)); end

4.9 Transistor Amplifier

229

f1=matlabFunction(eqs); error=sqrt(sum((f0(xk(2:end))-f1(dx(1:end-1),xk(1:end-1))).^2)); disp([' number of terms in Taylor series = ',num2str(k2),' error = ',num2str(error,'%0.3e ')]) disp(['simulated signal : ',num2str(f1(dx(1:end-1),xk(1:end-1)),'% 0.3e ')]) fprintf('\n') plot(f0(xk(2:end))-f1(dx(1:end-1),xk(1:end-1)),'LineWidth',1.5) end

4.9

Transistor Amplifier

A transistor amplifier, shown in Fig. 4.34, will be linearized for AC analysis. The two DC voltage sources Vdd and Vgg are used in order to bias the transistor and obtain the small-signal parameters such as gm and gds. The DC analysis of the circuit was studied in Chap. 2. For AC analysis, superposition is used and the DC voltage sources are disabled. The very large external capacitors C1 are considered as short connections because of the very small impedance of these capacitors in AC analysis. But this is just an optional assumption that further simplifies the AC model of the amplifier and can be avoided by including the admittance of the C1 capacitors. The transistor is replaced with its small-signal model in the AC analysis, as shown in Fig. 4.35. The equivalent AC model of the amplifier in ∏  arrayed configuration is shown in Fig. 4.36. The KCL equations can be written at circuit nodes in order to create the system of equations and the admittance matrix of the amplifier. Using voltage-gain transfer functions calculated from the minor determinants of the admittance matrix, the node voltages of the amplifier can be calculated as shown in Fig. 4.37.

Fig. 4.34 A common source amplifier

Vdd

R1

RD Vout

C Q1

r Vin R2 Vgg

230

4 AC Analysis

Fig. 4.35 The small-signal AC model of the common source amplifier

Vdd

R1

RD

Vout

Vgs1

Cdb1

gb1Vbs1

r

Cgd1

gm1Vgs1

C∞

Csb1

Cgs1

Vin

rds1

R2 Vgg

Cgd1 r

Cgs1

Vgs1 gm1Vgs1

Vout rds1

Cdb1

RD

Vin RB1||RB2 Fig. 4.36 The Π-arrayed small-signal AC model of the common source amplifier

Fig. 4.37 The small-signal voltages of the common source amplifier

The following MATLAB code shows the complete DC and AC analyses of a common source NMOS amplifier. The AC model used excludes the capacitor admittances and only accounts for the low frequency operation of the amplifier.

4.9 Transistor Amplifier

231

syms R2 RD RL VG VS VD IDS gm rds gain vip unCox=200e-06; L=100e-09; W=10e-06; Ln=0.1; Vth=0.5; f0=1e06; r=50; np=4; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0); Vdd=3; Vgg=0; R1=10e03; equ1=[... VG==Vdd*R2/(R1+R2);... VS==0; VD==Vdd-RD*IDS;... VD==0.5*(Vdd+(VG-VS-Vth));... VG-VS-Vth==0.3; IDS==0.5*unCox*W/L*(VG-VS-Vth)^2*(1+Ln*(VD-VS-(VG-VS-Vth)));... ]; Sol=solve(equ1,IDS,VD,VG,VS,R2,RD,'MaxDegree',5); VG=double(Sol.VG); VS=double(Sol.VS); VD=double(Sol.VD); VGS=VG-VS; disp(['VGS = ',num2str(VGS)]) VDS=VD-VS; disp(['VDS = ',num2str(VDS)]) IDS=double(Sol.IDS); disp(['IDS = ',num2str(IDS)]) R2=double(Sol.R2); disp(['R2 = ',num2str(R2)]) RD=double(Sol.RD); disp(['RD = ',num2str(RD)]) gm=unCox*W/L*(VGS-Vth); disp(['gm = ',num2str(gm)]) rds=1/(Ln*IDS); disp(['rds = ',num2str(rds)]) RL=2*RD; disp(['RL = ',num2str(RL)]) vop=Vdd-VDS;

232

4 AC Analysis

Y=[1/r -1/r 0; -1/r 1/r+1/R1+1/R2 0; 0 gm 1/rds+1/RD+1/RL]; in=1; out=3; gain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['gain = ',num2str(gain)]) vip=vop/abs(gain); disp(['vip = ',num2str(vip)]) in=1; out=2; Rin=det(Y((1:end)~=in & (1:end)~=out,(1:end)~=in & (1:end)~=out))/ det(Y((1:end)~=in,(1:end)~=in)); disp(['Rin = ',num2str(Rin)]) in=1; out=3; Rout=det(Y((1:end)~=in & (1:end)~=out,(1:end)~=in & (1:end)~=out))/ det(Y((1:end)~=in,(1:end)~=in)); disp(['Rout = ',num2str(Rout)]) figure plot(time,Vgg+vip*sin(2*pi*f0*time),'b') hold on plot(time,VG+vip*sin(2*pi*f0*time),'g') plot(time,VD+gain*vip*sin(2*pi*f0*time),'r') plot(time,gain*vip*sin(2*pi*f0*time),'m')

As an optional practice, the capacitors in the AC model of the common source NMOS amplifier can be added to this code in order to analyze the high frequency small-signal operation of the amplifier.

4.10

Node Elimination

System of equations in admittance format for a circuit with n nodes includes n equations. Node voltages form dependent variables and node currents form independent variables. Using algebraic methods such as Gaussian elimination, independent variables can be removed from systems of equations and the order of an n-by-n admittance matrix can be reduced to less than n, as shown in Fig. 4.38. To ensure the functionality and characteristics of a circuit is not impacted by node elimination, the new admittance matrix of the circuit with reduced order must be precisely calculated to include all original information. If the admittance matrix of the original circuit is given by the following system of equations

4.10

Node Elimination

v1

233

in

i1 n×n

i2

v1

vn

n 1×n 1

i2

in 1

v2

i1 in 1

v2

vn 1

vn 1

Fig. 4.38 Node elimination, (a) Original n-node circuit, and (b) Reduced circuit with n-1 nodes

2

Y 1,1 6Y 6 2,1 6 4 ⋮ Y n,1

32 3 2 3 v1 i1 Y 1,n 7 6 7 6 Y 2,n 76 v2 7 6 i2 7 7 76 7 ¼ 6 7 ⋮ 54 ⋮ 5 4 ⋮ 5

Y 1,2 Y 2,2

⋯ ⋯

⋮ Y n,2

⋱ . . . Y n,n

vn

ð4:73Þ

in

and node n is being eliminated, the resulting admittance matrix will be 2

Y 1,1 6 Y 6 2,1 6 4 ⋮ Y n1,1

32 v1 Y 1,n1 6 v Y 2,n1 7 76 2 76 ⋮ 54 ⋮

Y 1,2 Y 2,2

⋯ ⋯

⋮

⋱ . . . Y n1,n1

Y n1,2

3

2

i1

7 6 i 7 6 2 7¼6 5 4 ⋮

vn1

3 7 7 7 5

ð4:74Þ

in1

The new elements of the admittance matrix with reduced order are calculated by Yij ¼ Yij 

Ynj Yin , 1  ði, jÞ < n Ynn

ð4:75Þ

The node elimination algorithm given by 4.75 is directly extracted from algebraic methods such as variable substitution and elimination.

4.10.1 Example 1 Using the node elimination algorithm, a 4-node Y-shaped circuit, shown in Fig. 4.39a, can be converted to a 3-node Delta-shaped circuit, shown in Fig. 4.39b.

234

4 AC Analysis

Fig. 4.39 (a) 4-node Y-shaped circuit and (b) 3-node delta-shaped circuit

1 4

G1

Gb

1

3

3

G3 Ga

G2

Gc 2

2 (a)

(b)

The admittance matrix of the Y-shaped circuit is given by 2

0

0

G1

G2 0

0 G3

G2 G3

G2

G3

G1 þ G2 þ G3

G1

6 0 6 6 4 0

G1

3 7 7 7 5

ð4:76Þ

After applying the node elimination algorithm to node 4, the admittance matrix converts to 2

G1 2 G  1 6 G1 þ G2 þ G3 6 6 G1 G2 6  6 G1 þ G2 þ G3 6 4 G1 G3  G1 þ G2 þ G3

G1 G2 G1 þ G2 þ G3 G2 2 G2  G1 þ G2 þ G3 G2 G3  G1 þ G2 þ G3 

3 G1 G3 G1 þ G2 þ G3 7 7 7 G2 G3 7  G1 þ G2 þ G3 7 7 5 G3 2 G3  G1 þ G2 þ G3 

ð4:77Þ

The admittance matrix of the Delta-shaped circuit is given by 2

Ga þ Gb 6 4 Ga Gb

Ga Ga þ Gc Gc

3 Gb 7 Gc 5 Gb þ Gc

ð4:78Þ

Comparing (4.77) and (4.78) results into the following relationships. Ga ¼

G1 G2 G1 þ G2 þ G3

ð4:79Þ

Gb ¼

G1 G3 G1 þ G2 þ G3

ð4:80Þ

and

4.10

Node Elimination

235

and Gc ¼

G1 G3 G1 þ G2 þ G3

ð4:81Þ

For passive circuits, the node elimination follows the following expression. Y Y Y mn ¼ Pm n Yk

ð4:82Þ

where k is the node to be eliminated, ∑Yk is the sum of all admittances connected to node k, m, and n represent nodes that are connected to node k through admittances Ym and Yn. For circuits that include dependent sources, the node elimination must be applied through the general expression given by (4.75). The following MATLAB code converts a fully populated 3-node passive circuit to an equivalent 2-node circuit.

syms s G1 G2 G3 G4 G5 G6 syms v1 v2 v3 syms i1 i2 [Ym]=equationsToMatrix([... G1*v1+G2*(v1-v2)+G6*(v1-v3)==i1,... G3*v2+G2*(v2-v1)+G4*(v2-v3)==i2,... G5*v3+G4*(v3-v2)+G6*(v3-v1)==0,... ],[v1,v2,v3]); Y=Ym; [m,n]=size(Y); %number of nodes remaining after node elimination nodes=2; for k=1:m-nodes for km=1:m-1 for kn=1:n-1 Y(km,kn)=Y(km,kn)-(Y(m,kn)*Y(km,n))/Y(m,n); end end m=m-1; n=n-1; end Y(setdiff(1:size(Ym,1),1:nodes),:)=[]; Y(:,setdiff(1:size(Ym,2),1:nodes))=[]; disp(Y)

236

4.11

4 AC Analysis

Y-Parameters

A circuit is called a two-port circuit when all internal nodes of an n-node circuit are continuously eliminated until only two input and output nodes remain in the circuit. The admittance matrix of a two-port circuit is given by the following system of equations 

Y 1,1 Y 2,1

Y 1,2 Y 2,2



v1 v2





i1 ¼ i2

 ð4:83Þ

where node 1 represents the input node and node 2 represents the output node. The two-port model of the circuit using Y-parameter is shown in Fig. 4.40. Eliminating node 2 will give the total circuit admittance at input node 1 given by Y1 ¼

i1 Y Y ¼ Y11  12 21 v1 Y22

ð4:84Þ

and eliminating node 1 will give the total circuit admittance at output node 2 given by Y2 ¼

i2 Y Y ¼ Y22  12 21 v2 Y11

ð4:85Þ

The differential admittance between nodes 1 and 2 of the two-port circuit is calculated using testbench shown in Fig. 4.41. From the testbench, the following equations are extracted.

Fig. 4.40 Two-port model of a circuit using Y-parameters

i1

v1

Fig. 4.41 Testbench for calculating differential admittance

i2 Y11

Y21v1 Y22

v

i1

v1

Y12v2

Y11

i

Y12v2 Y21v1 Y22

v2

i2

v2

4.12

Signal Gains

237

v ¼ v2  v1

ð4:86Þ

i ¼ i2 ¼ i1

ð4:87Þ

i1 ¼ Y11 v1 þ Y12 v2

ð4:88Þ

i2 ¼ Y21 v1 þ Y22 v2

ð4:89Þ

and

and

and

And the differential admittance is given by i Y11 Y22  Y12 Y21 Yd ¼ ¼ v Y11 þ Y12 þ Y21 þ Y22

4.12

ð4:90Þ

Signal Gains

The model of a two-port circuit connected to the input source and the output load is shown in Fig. 4.42. From the model, the following equations can be extracted. iS ¼ YS v1 þ i1

ð4:91Þ

i2 ¼ YL v2

ð4:92Þ

and

Using source transformation shown in Fig. 4.43, the input current source can be converted to input voltage source.

i1

Fig. 4.42 Loaded two-port circuit

iS

YS

v1

source

i2 Y11

Y12v2 Y21v1 Y22

two port circuit

v2

YL

load

238

4 AC Analysis

i1 iS

YS

YS two port circuit

v1

vS

(a)

i1 two port circuit

v1 (b)

Fig. 4.43 Source transformation, (a) Input current source, and (b) Input voltage source

The relationship between the input current source and the input voltage source is given by iS ¼ YS vS

ð4:93Þ

From (4.88), (4.89), (4.91), (4.92), and (4.93), a few signal gains can be defined for the two-port circuit. The input admittance is given by Yin ¼

i1 Y Y ¼ Y11  12 21 v1 Y22 þ YL

ð4:94Þ

The output admittance is given by Yout ¼

i2 Y Y ¼ Y22  12 21 v2 Y11 þ YS

ð4:95Þ

The two-port voltage-gain is given by v2 Y21 ¼ v1 YL þ Y22

ð4:96Þ

The overall voltage-gain is given by v2 YS Y21 YS v ¼  2 ¼ vS Y12 Y21  ðYS þ Y11 ÞðYL þ Y22 Þ Yin þ YS v1

ð4:97Þ

The overall impedance gain is given by v2 Y21 1 v ¼  2 ¼ iS Y12 Y21  ðYS þ Y11 ÞðYL þ Y22 Þ Yin þ YS v1 The two-port impedance gain is given by

ð4:98Þ

4.13

Primary Transfer Functions

239

v2 Y21 1 v ¼  2 ¼ i1 Y12 Y21  Y11 ðYL þ Y22 Þ Yin v1

ð4:99Þ

The overall admittance gain is given by i2 YS YL Y21 YS YL v ¼  2 ¼ vS Y12 Y21  ðYS þ Y11 ÞðYL þ Y22 Þ Yin þ YS v1

ð4:100Þ

The two-port admittance gain is given by i2 YL Y21 v ¼ ¼ YL  2 v1 YL þ Y22 v1

ð4:101Þ

The overall current gain is given by i2 YL Y21 YL v ¼  2 ¼ iS Y12 Y21  ðYS þ Y11 ÞðYL þ Y22 Þ Yin þ YS v1

ð4:102Þ

The two-port current gain is given by i2 YL Y21 YL v2 ¼  ¼ i1 Y12 Y21  Y11 ðYL þ Y22 Þ Yin v1

4.13

ð4:103Þ

Primary Transfer Functions

The general model of a two-port circuit connected to the input source and the output load is shown in Fig. 4.44. Transfer functions of the two-port circuit that were extracted earlier are summarized in Table 4.9. As listed in the table, all circuit transfer functions can be extracted if the two voltage-gain and the input admittance transfer functions are known. The two voltage-gain and the input admittance transfer functions are called the primary or the fundamental transfer functions of the circuit that can be obtained using the ratios of the truncated determinants of the admittance matrix studied earlier.

ii

Fig. 4.44 A general two-port loaded circuit

iS

io

vi

YS Yin

Circuit

vo

YL

240

4 AC Analysis Table 4.9 Calculating circuit transfer functions in terms of Av and Yin

The voltage-gain transfer function is generally given by

ð4:104Þ

For the two-port circuit, i ¼ 1 and o ¼ 2, the voltage-gain transfer function is given by Av ¼ 

Y 2,1 Y 2,2 þ Y L

ð4:105Þ

The input admittance transfer function is given by

ð4:106Þ

For the two-port circuit, i ¼ 1 and o ¼ 2, the input admittance transfer function is given by    Y 1,1 Y 1,2   Y Y 2,2 þ Y L  Y in ¼ 2,1 Y 2,2 þ Y L

ð4:107Þ

4.14

Maximum Power

Fig. 4.45 Input and output admittances of the two-port circuit with respect to source and load admittances

241

i2

i1 iS

YS

two port circuit

v1 Yin

4.14

v2

YL

Yout

Maximum Power

Signals travel through wires or air. These transmission mediums have finite permittivity and permeability and affect the magnitude of voltage (electric field) or current (magnetic flux). Changing one of these signal components will impact the other component. High levels of signal powers are required to ensure signals can travel longer distance while keeping their strength more than noise. The signal powers are kept at high levels if the input and the output admittances of the two-port circuit are selected properly compared with the source and the load admittances, as shown in Fig. 4.45. At the input of the two-port circuit, the following equation exists. iS ¼ ðYS þ Yin Þv1

ð4:108Þ

The power delivered to the two-port circuit is calculated by Pin ¼ Yin v1 2

ð4:109Þ

From 4.108 and 4.109, the following expression is extracted. Pin ¼ iS 2

Yin ðYS þ Yin Þ2

ð4:110Þ

Objective is to find conditions by varying Yin with respect to YS that maximized the power. Taking power derivative with respect to Yin and setting it to zero will give the maximum point given by ðY þ Yin Þ2  2Yin ðYS þ Yin Þ dPin ¼ iS 2 S ¼ 0 ) Yin ¼ YS dYin ðYS þ Yin Þ4

ð4:111Þ

Signal power is stored and released in capacitors and inductors during positive and negative cycles but is dissipated by resistors and conductors at any time. Therefore, the real part of the admittances uses the power to perform a task such as heat generation. For a general case when admittances are complex and have real (conductance) and imaginary (susceptance) parts, only real parts of Yin and YS must

242

4 AC Analysis

be equal and the imaginary parts must either be zero or be the conjugate of each other in order to become zero while adding them for parallel Yin and YS. Therefore, the following general condition satisfies the maximum power transformation from input source to the two-port circuit. Yin ¼ YS 

ð4:112Þ

Similarly, the relationship between the output admittance of the two-port circuit and the load to maximize the power delivery to load is given by Yout ¼ YL 

4.15

ð4:113Þ

Circular-Shaped Power Dividers

Resistive circuits are used for dividing voltage and current signals without adding a phase. They also divide power from a source to multiple loads or recombine powers from multiple sources and deliver them to a load. The advantage of using resistive circuits for signal transformation is their infinite bandwidth. The disadvantage of using resistive circuits for signal transformation is their high voltage and current losses. A 3-gon power divider is shown in Fig. 4.46. The power divider drives two equal loads and when the impedance matching conditions are applied to the source and loads, the maximum power from source is delivered to the divider and the maximum power from divider is delivered to the loads. This idea can be expanded to multiple loads by using a multigon circuit. The KCL at input source is given by GS ðvS  v2 Þ ¼ iS

ð4:114Þ

Fig. 4.46 A 3-gon power divider

3-gon G2

2 GS vS

G1

4 G3

3

GL

GL load

source load

4.15

Circular-Shaped Power Dividers

243

where iS is the current applied to the circuit by the external voltage source vS. The KCL at node 2 of the circuit is given by GS ðv2  vS Þ þ G1 ðv2  v3 Þ þ G2 ðv2  v4 Þ ¼ 0

ð4:115Þ

The KCL at node 3 of the circuit is given by G1 ðv3  v2 Þ þ GL v3 þ G3 ðv3  v4 Þ ¼ 0

ð4:116Þ

The KCL at node 4 of the circuit is given by G2 ðv4  v2 Þ þ G3 ðv4  v3 Þ þ GL v4 ¼ 0

ð4:117Þ

The system of equations for the power divider in matrix format is given by 2

6 6 GS 6 6 6 0 4

32

GS

0

0

GS þ G1 þ G2

G1

G2

G1

GL þ G1 þ G3

G3

G2

G3

GL þ G2 þ G3

GS

0

vS

3

2

iS

3

76 7 6 7 7 6 v2 7 6 0 7 76 7 6 7 76 7 ¼ 6 7 7 6 v3 7 6 0 7 54 5 4 5 0

v4

ð4:118Þ The admittance matrix of the power divider is given by 2

GS

6 G S 6 Y¼6 4 0 0

GS

0

0

GS þ G1 þ G2 G1

G1 GL þ G1 þ G3

G2 G3

G2

G3

GL þ G2 þ G3

3 7 7 7 5

ð4:119Þ

In the 4  4 admittance matrix, the x ¼ 1 represents the internal node of the nonideal source where vS is connected, the i ¼ 2 represents the input node of the power divider and the o ¼ 4 represents the output node of the power divider. The voltage-gain of the power divider is given by

ð4:120Þ

244

4 AC Analysis

The conductance at the input node of the power divider after shorting the input source is given by

ð4:121Þ

The conductance at the output of the power divider after shorting the input source is given by

ð4:122Þ

The power divider with impedance matching conditions is shown in Fig. 4.47. For impedance matching and transformation using the power divider, the following relationship must be satisfied ii ¼ 2GS vi

ð4:123Þ

and

Fig. 4.47 Impedance matching conditions for the 3-gon power divider

3-gon G2

2 GS

4 G3

G1 3

vS GS

GL GL

GL GL

load

source load

4.15

Circular-Shaped Power Dividers

245

io ¼ 2GL vo

ð4:124Þ

and the component values in the power divider by setting the voltage-gain to a number less than unity (here it is assumed vvoi ¼ 0:5) are given by G1 ¼ GL GS

3GL  4GS 4GS 2  7GL GS þ 2GL 2

ð4:125Þ

G2 ¼ GL GS

4GS  5GL 4GS 2  7GL GS þ 2GL 2

ð4:126Þ

GL 3  7GL GS þ 2GL 2

ð4:127Þ

and

and G3 ¼

4GS

2

In order to obtain real and positive values for divider components, the following relationship must be satisfied 4GS 4GS < GL < ð4:128Þ 5 3 A A 1 1 As an example, GS ¼ 50 of the power V , GL ¼ 50 V , and the components  A 1 A 1 A 1 , G , and G . The voltage-gain divider are given by G1 ¼ 50 ¼ ¼ 2 3 V 50 V 50 V vo of the power divider is vi ¼ 0:5 ¼ 6dB and the current gain of the power divider is io ii ¼ 0:8 ¼ 1:9dB. The following MATLAB code calculates the voltage-gain, the input and the output admittances of the circuit in this example using Cramer’s rules.

syms v1 v2 v3 syms i1 syms vs GS=1/50; G1=1/50; G2=1/50; G3=1/50; GL=1/50; [Y]=equationsToMatrix([... GS*(vs-v1)==i1;...

246

4 AC Analysis

GS*(v1-vs)+G1*(v1-v2)+G2*(v1-v3)==0;... G1*(v2-v1)+GL*v2+G3*(v2-v3)==0;... G2*(v3-v1)+G3*(v3-v2)+GL*v3==0,... ],[vs,v1,v2,v3]); %AC equations x=1; in=2; out=4; vgain=((-1)^(in+out))*det(Y(setdiff(1:n,[x in]),setdiff(1:n, [x out])))/det(Y(setdiff(1:n,[x in]),setdiff(1:n,[x in]))); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) Yin=det(Y(setdiff(1:n,x),setdiff(1:n,x)))/det(Y(setdiff(1:n, [x in]),setdiff(1:n,[x in]))); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y(setdiff(1:n,x),setdiff(1:n,x)))/det(Y(setdiff(1:n, [x out]),setdiff(1:n,[x out]))); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')])

4.16

Star-Shaped Power Dividers

A 3-pole power divider is shown in Fig. 4.48. The power divider drives two equal loads and when the impedance matching conditions are applied to the source and loads, the maximum power from source is delivered to the divider and the maximum power from divider is delivered to the loads. This functionality can be expanded to multiple loads by using a multipole circuit. The KCL at the input source is given by GS ðvS  v2 Þ ¼ iS

Fig. 4.48 A 3-pole power divider

ð4:129Þ

3-pole 2 GS

G1 5

4

G3 G2

3

GL

vS GL load

source load

4.16

Star-Shaped Power Dividers

247

where iS is the current applied to the circuit by the external voltage source vS. The KCL at node 2 of the circuit is given by G S ð v2  vS Þ þ G 1 ð v2  v5 Þ ¼ 0

ð4:130Þ

The KCL at node 3 of the circuit is given by G2 ðv3  v5 Þ þ GL v3 ¼ 0

ð4:131Þ

The KCL at node 4 of the circuit is given by G3 ðv4  v5 Þ þ GL v4 ¼ 0

ð4:132Þ

The KCL at node 5 of the circuit is given by G1 ðv5  v2 Þ þ G2 ðv5  v3 Þ þ G3 ðv5  v4 Þ ¼ 0

ð4:133Þ

The system of equations for the power divider in matrix format is given by 2

GS

6 6 GS 6 6 6 0 6 6 6 0 4 0

GS

0

0

GS þ G1

0

0

0

GL þ G2

0

0

0

GL þ G3

G1

G2

G3

0

32

vS

3

2

iS

3

76 7 6 7 76 v 2 7 6 0 7 76 7 6 7 76 7 6 7 76 v 3 7 ¼ 6 0 7 G2 76 7 6 7 76 7 6 7 76 v 4 7 6 0 7 G3 54 5 4 5 0 G1 þ G2 þ G3 v5 G1

ð4:134Þ The admittance matrix of the power divider is given by 2

GS 6 6 GS 6 Y¼6 6 0 6 4 0 0

GS GS þ G1

0 0

0 0

0 G1

0

GL þ G2

0

G2

0 G1

0 G2

GL þ G3 G3

G3 G1 þ G2 þ G3

3 7 7 7 7 7 7 5

ð4:135Þ

In the 4  4 admittance matrix, the x ¼ 1 represents the internal node of the nonideal source where vS is connected, the i ¼ 2 represents the input node of the power divider, and the o ¼ 4 represents the output node of the power divider. The voltage-gain of the power divider is given by

248

4 AC Analysis

ð4:136Þ

The conductance at the input node of the power divider after shorting the input source is given by

ð4:137Þ

The conductance at the output of the power divider after shorting the input source is given by

ð4:138Þ

The power divider with impedance matching conditions is shown in Fig. 4.49. For impedance matching and transformation using the power divider, the following relationship must be satisfied Fig. 4.49 Impedance matching conditions for the 3-pole power divider

3-pole 2

G1 5

GS

4

G3 G2

3

vS GS

GL

GL GL

GL

source load

load

4.16

Star-Shaped Power Dividers

249

ii ¼ 2GS vi

ð4:139Þ

io ¼ 2GL vo

ð4:140Þ

and

and the component values in the power divider by setting the voltage-gain to a number less than unity (here it is assumed vvoi ¼ 0:5) are given by GS ð4GS  GL Þ GL

ð4:141Þ

G2 ¼ GL

4GS  GL 5GL  4GS

ð4:142Þ

G3 ¼ GL

4GS  GL 4GS  3GL

ð4:143Þ

G1 ¼ and

and

In order to obtain real and positive values for divider components, the following relationship must be satisfied GL 5GL < GS < ð4:144Þ 4 4 A A 1 1 of the power As an example, GS ¼ 50 V , GL ¼ 50 V , and the components  A 3 A 3 A 3 divider are given by G1 ¼ 50 , G , and G . The voltage-gain ¼ ¼ 2 3 V 50 V 50 V of the power divider is vvoi ¼ 0:5 ¼ 6dB and the current gain of the power divider is io ii ¼ 0:8 ¼ 1:9dB. The following MATLAB code calculates the voltage-gain, the input and the output admittances of the circuit in this example using Cramer’s rules.

syms v1 v2 v3 v4 syms i1 syms vs GS=1/50; G1=3/50; G2=3/50;

250

4 AC Analysis

G3=3/50; GL=1/50; [Y]=equationsToMatrix([... GS*(vs-v1)==i1;... GS*(v1-vs)+G1*(v1-v4)==0;... G2*(v2-v4)+GL*v2==0;... G3*(v3-v4)+GL*v3==0;... G1*(v4-v1)+G2*(v4-v2)+G3*(v4-v3)==0, ],[vs,v1,v2,v3,v4]); %AC equations x=1; in=2; out=4; vgain=((-1)^(in+out))*det(Y(setdiff(1:n,[x in]),setdiff(1:n, [x out])))/det(Y(setdiff(1:n,[x in]),setdiff(1:n,[x in]))); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) Yin=det(Y(setdiff(1:n,x),setdiff(1:n,x)))/det(Y(setdiff(1:n, [x in]),setdiff(1:n,[x in]))); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y(setdiff(1:n,x),setdiff(1:n,x)))/det(Y(setdiff(1:n, [x out]),setdiff(1:n,[x out]))); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')])

4.17

Power Gains

Four different powers can be defined for a two-port circuit that is connected to the source and load admittances, as shown in Fig. 4.50. The input power of the two-port circuit is given by jv 2j 1 Pin ¼ realfv1 i1  g ¼ 1 realfY in g 2 2

ð4:145Þ

i2

i1 iS

YS

two port circuit

v1 PAS Pin

Fig. 4.50 Powers of a loaded two-port circuit

v2 PAO PL

YL

4.17

Power Gains

251

i1

Fig. 4.51 Input model to calculate maximum available power from source

iS

YS

v1

Yin

i2

Fig. 4.52 Output model to calculate maximum available power from circuit

iout

Yout

v2

YL

The load power is given by jv 2j 1 PL ¼ realfv2 i2  g ¼ 2 realfY L g 2 2

ð4:146Þ

The available power from source can be calculated from the testbench shown in Fig. 4.51. The maximum power from source is delivered when the input admittance of the two-port circuit is equal to conjugate of the source admittance. When Yin ¼ YS, Yin + YS ¼ 2real{YS}, and the maximum power at source is obtained by PS ¼

1 iS 2 1 iS 2 ¼ 2 Y in þ Y S 4 realfY S g

ð4:147Þ

The source power is delivered equally between YS and Yin. The maximum available power from source delivered to the two-port circuit is given by 1 1 iS 2 PAS ¼  PS ¼ 2 8 realfY S g

ð4:148Þ

The available power from two-port circuit can be calculated from the testbench shown in Fig. 4.52. From (4.88), (4.89), (4.91), (4.92), and (4.95), the output current iout is calculated by iout ¼

Y21 i YS þ Y11 S

ð4:149Þ

The maximum power from two-port circuit is delivered when the output admittance of the two-port circuit is equal to conjugate of the load admittance. When

252

4 AC Analysis

Yout ¼ YL, Yout + YL ¼ 2real{Yout}, and the maximum power from two-port circuit is obtained by Pout ¼

1 iout 2 1 iout 2 ¼ 2 Y out þ Y L 4 realfY out g

ð4:150Þ

The power from two-port circuit is delivered equally between Yout and YL. The maximum available power from two-port circuit delivered to the load is given by

1 PAO ¼  Pout 2

   Y21 2 2  Y þY 1 iout 1 S 11  iS ¼ ¼ 8 realfY out g 8 realfY out g 2

ð4:151Þ

The power gain of the two-port circuit is given by   jv2 2 j realfY L g  Y21 2 realfY L g PL n o ¼ jv 22 j ¼  1 Pin Y þ Y Y21 L 22 real Y f g real Y11  YY12þY in 2 22

ð4:152Þ

L

The maximum available power gain is given by    Y21 2 2 YS þY11  iS

  1  Y21 2 realfY S g PAO 8 realfY out g   n o ¼ ¼ iS 2 1 PAS YS þ Y11  real Y  Y12 Y21 8 realfY S g

22

ð4:153Þ

Y11 þYS

The overall power gain is given by PL ¼ PAS

jv2 2 j 2 realfY L g iS 2 1 8 realfY S g

 2   Y21   realfY L grealfY S g ¼ 4 Y12 Y21  ðYS þ Y11 ÞðYL þ Y22 Þ

ð4:154Þ

The following MATLAB code calculates the voltage-gain, the input and the output admittances of the 4-node circuit in this example using Cramer’s rules. Next, it eliminates the two internal nodes and reduces the circuit to two input and output nodes. Finally, the Y-parameters and the power gain transfer functions of the circuit are calculated.

4.17

Power Gains

253

syms v1 v2 v3 v4 syms i1 syms vs GS=1/50; G1=3/50; G2=3/50; G3=3/50; GL=1/50; [Y]=equationsToMatrix([... GS*(vs-v1)==i1;... GS*(v1-vs)+G1*(v1-v4)==0;... G2*(v2-v4)+GL*v2==0;... G3*(v3-v4)+GL*v3==0;... G1*(v4-v1)+G2*(v4-v2)+G3*(v4-v3)==0, ],[vs,v1,v2,v3,v4]); %AC equations in=2; out=4; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')]) in=1; out=4; Y([2,out],:)=Y([out,2],:); Y(:,[2,out])=Y(:,[out,2]); Y([1,in],:)=Y([in,1],:); Y(:,[1,in])=Y(:,[in,1]); [m,n]=size(Y); %number of nodes remaining after node elimination nodes=2; for k=1:m-nodes for km=1:m-1 for kn=1:n-1 Y(km,kn)=Y(km,kn)-(Y(m,kn)*Y(km,n))/Y(m,n); end end m=m-1; n=n-1;

254

4 AC Analysis

end Y(setdiff(1:size(Y,1),1:nodes),:)=[]; Y(:,setdiff(1:size(Y,2),1:nodes))=[]; disp(Y) Y11=Y(1,1); Y12=Y(1,2); Y21=Y(2,1); Y22=Y(2,2); YS=GS; YL=GL; Yin=Y11-Y12*Y21/(Y22+YL); Yout=Y22-Y12*Y21/(Y11+YS); v2v1=-Y21/(Y22+YL); v2iS=Y21/(Y12*Y21-(Y11+YS)*(Y22+YL)); Ydif=(Y11*Y22-Y12*Y21)/(Y11+Y12+Y21+Y22); disp([' pLp1 = ',num2str(double(((abs(v2v1))^2)*real(conj(YL))/real (conj(Yin))))]); disp([' p2pS = ',num2str(double(((abs(Y21/(Y11+YS)))^2)*real(YS)/ real(Yout)))]); disp([' pLpS = ',num2str(double(4*((abs(v2iS))^2)*real(conj(YL)) *real(YS)))]); disp([' pU = ',num2str(double(((abs(Y21))^2)/(4*real(Y11)*real (Y22))))]); Kfact=(2*real(Y11)*real(Y22)-real(Y12)*real(Y21))/abs(Y12*Y21); disp([' Kfact = ',num2str(double((2*real(Y11)*real(Y22)-real(Y12) *real(Y21))/abs(Y12*Y21)))]); disp([' MSG = ',num2str(double(abs(Y21/Y12)))]); disp([' MAG = ',num2str(double(abs(Y21/Y12)*(Kfact-sqrt(Kfact^21))))]); disp([' H21 = ',num2str(double(Y21/Y11))]); disp([' U = ',num2str(double(abs(Y21-Y12)^2/(4*real(Y11)*real(Y22)4*real(Y12)*real(Y21))))]);

4.18

Admittance Mismatch

Using the simple model shown in Fig. 4.53, the maximum power from the source is delivered to the load when the source and load admittances are conjugate of each other and have equal real parts. When the load admittance is varied from this optimum value the power delivered to load reduces from the maximum value.

4.18

Admittance Mismatch

255

Fig. 4.53 Mismatch between source and load admittances

L

iS

YS

vL

source

YL=YS± Y

load

The load current and voltage is given by iL ¼ YL vL ¼ YL

iS YS þ YL

ð4:155Þ

When there is a mismatch between load and (YL 6¼ YS or YL ¼ YS  ΔY ), the load voltage is given by 1 i ¼ S  vL ¼ i S YS þ YL 2YS

 ΔY 2 1 YS  ΔY 2

source

admittances

! ¼ vi  vr

ð4:156Þ

The load voltage can be written as difference between incident voltage (vi) and reflected voltage (vr). The load current is given by YL i ¼ S iL ¼ iS YS þ YL 2

 ΔY 2 1þ YS  ΔY 2

! ¼ ii þ ir ¼ YS ðvi þ vr Þ

ð4:157Þ

The load current can be written as summation of incident current (ii) and reflected current (ir). When load and source admittances are matched (YL ¼ YS) with zero imaginary parts, the load voltage is given by vL ¼ iS

1 i ¼ S  ð 1  0Þ ¼ v i  0 YS þ YL 2YS

ð4:158Þ

and there will be no reflected voltage. The load voltage becomes equal to the incident voltage (vi) with zero reflected voltage (vr). The load current is given by iL ¼ iS

YL i ¼ S  ð1 þ 0Þ ¼ ii þ 0 ¼ YS ðvi þ 0Þ YS þ YL 2

ð4:159Þ

Under admittance matching condition, the load current is equal to the incident current (ii) with zero reflected current (ir). The variation of the load power with respect to the load admittance is shown in Fig. 4.54.

256

4 AC Analysis

Fig. 4.54 Impact of admittance variation on power

PL Pmax Pmax P

YS Y

YS YS+ Y YL

When load admittance is equal to source admittance with no imaginary parts, the reflected voltage and the reflected current become zero and maximum power is delivered to load. YL ¼ YS ) vr ¼ 0 and ir ¼ 0 and PL ¼ Pmax

ð4:160Þ

When there is a mismatch between the load and source admittances, the reflected voltage and the reflected current become nonzero and there will be finite power loss. YL 6¼ YS ) vr 6¼ 0 and ir 6¼ 0 and PL ¼ Pmax  ΔP

ð4:161Þ

Therefore, although models in circuits are lumped and there are no travelling electromagnetic waves as opposed to the distributed components, it is possible to assume that the incident voltage is being sent from the source to the load and the reflected voltage is returned from the load to the source under admittance mismatch conditions. The load shown in Fig. 4.53 can be considered as a one-port circuit. The ratio of reflected voltage to incident voltage given by 4.156 is called scattering parameter or S-parameter and is equal to

S¼

4.19

vr ¼ vi

iS 2YS

 ΔY   Y 2ΔY S

iS 2YS

 ð 1Þ

2

¼

ΔY Y  YL ¼ S 2YS  ΔY YS þ YL

ð4:162Þ

S-Parameters

S-parameters define relationship between the incident and the reflected voltages in circuits. It is possible to generalize the definition of the S-parameters to multi-port circuits but they are defined here for two-port circuits only using the testbench shown in Fig. 4.55.

4.19

S-Parameters

257

i2

i1 iS1

two port circuit

v1

YS

v2

iS2

YL

Yout

Yin

Fig. 4.55 Testbench to calculate S-parameters of a two-port circuit

The S-parameters of a two-port circuit are defined as 

S1,1

S1,2

S2,1

S2,2



vi1



 ¼

vi2

vr1

 ð4:163Þ

vr2

The voltages at the input and the output nodes of the two-port circuit are given by 

v1



v2

 ¼

vi1



 

vi2

vr1



 ¼

vr2



1  S1,1

S1,2

S2,1

1  S2,2

vi1



vi2

ð4:164Þ

The currents at the input and the output nodes of the two-port circuit are given by 

i1 i2



 ¼  ¼

ii1



 þ

ii2 YS

0

0

YL

ir1

ir2 



 ¼

YS

0

0

YL

 

vi1



 þ

1 þ S1,1

S1,2

vi2   vi1

S2,1

1 þ S2,2

vi2

vr1



vr2 ð4:165Þ

In a special case when the source and the load admittances are equal (YS ¼ YL ¼ Y0), the currents of the two-port circuit are given by 

i1 i2



 ¼ Y0

1 þ S1,1

S1,2

S2,1

1 þ S2,2



vi1 vi2

 ð4:166Þ

1 ½A=V  because the characteristic admittance of cables used Traditionally, Y 0 ¼ 50 in wireline communications or the characteristic admittance of antennas used in 1 wireless communications were close to 50 ½A=V . From 4.164 and 4.165, the relationship between the input and the output voltages and currents of the two-port circuit in terms of S-parameters is given by

258

4 AC Analysis

i2

i1

Fig. 4.56 Excitation of the two-port circuit at input port

iS

YS

two port circuit

v1

v2

YL

Yin 

i1 i2



 ¼

YS

0

0

YL



1 þ S1,1

S1,2

S2,1

1 þ S2,2



1  S1,1

S1,2

S2,1

1  S2,2

1 

v1 v2

 ð4:167Þ

Generally, S-parameters are complex numbers unless the circuit is purely resistive. For stable circuits, magnitude of S-parameters is between zero and unity because for these circuits, the reflected voltages cannot be more than the incident voltages. If the two-port circuit is only excited at the input port, as shown in Fig. 4.56, the incident voltage vi2 at the output port becomes zero because of the absence of a source at output. From 4.164 and 4.165, the following equations are derived. v1 ¼ ð1  S1,1 Þvi1

ð4:168Þ

v2 ¼ S2,1 vi1

ð4:169Þ

i1 ¼ Y S ð1 þ S1,1 Þvi1

ð4:170Þ

i2 ¼ Y L S2,1 vi1

ð4:171Þ

and

and

and

From 4.168 and 4.170, the input admittance of the two-port circuit is given by Yin ¼

1 þ S1,1 i1 ¼ YS v1 1  S1,1

ð4:172Þ

From 4.168 and 4.169, the voltage-gain of the two-port circuit is given by

4.20

Z-Parameters

259

S2,1 v2 ¼ v1 1  S1,1

ð4:173Þ

From 4.170 and 4.171, the current gain of the two-port circuit is given by i2 Y L S2,1 ¼ i1 YS 1 þ S1,1

ð4:174Þ

Yin  YS Yin þ YS

ð4:175Þ

From 4.172, S1, 1 is given by S1,1 ¼

When S1, 1 is zero, Yin ¼ YS, admittances match at the input, the reflected voltage at the input becomes zero and the maximum power is delivered from source to the input of the two-port circuit. From 4.177, S2, 1 is given by S2,1 ¼

v2 ð S  1Þ v1 1,1

If the input of the two-port circuit is matched to the source, then S2, measure of the voltage-gain. Similarly, Yout ¼

ð4:176Þ 1

will be a

1 þ S2,2 i2 ¼ YL v2 1  S2,2

ð4:177Þ

Yout  YL Yout þ YL

ð4:178Þ

and S2, 2 is given by S2,2 ¼

When S2, 2 is zero, Yout ¼ YL, admittances matching at the output, the reflected voltage at the output becomes zero and the maximum power is delivered from the output of the two-port circuit to the load.

4.20

Z-Parameters

Modeling some circuits and components with Z-parameters (impedance parameters), as shown in Fig. 4.57, makes it easier to extract their characteristics.

260

4 AC Analysis

i1

Fig. 4.57 Modeling a two-port circuit with Z-parameters

i2 Z11 Z12i2

v1

Fig. 4.58 Testbench to calculate differential impedance of a two-port circuit

Z22 Z21i1

v

i1 Z11 Z12i2

v1

v2

i

i2

Z22 Z21i1

v2

The Z-parameters are given by 

Z 1,1 Z 2,1

Z 1,2 Z 2,2



i1 i2





v1 ¼ v2

 ð4:179Þ

The differential admittance between nodes 1 and 2 of the two-port circuit is calculated using the testbench shown in Fig. 4.58. From the testbench, the following equations are extracted. v ¼ v2  v1

ð4:180Þ

i ¼ i2 ¼ i1

ð4:181Þ

v1 ¼ Z11 i1 þ Z12 i2

ð4:182Þ

v2 ¼ Z21 i1 þ Z22 i2

ð4:183Þ

and

and

and

And the differential impedance is given by v Zd ¼ ¼ Z11 þ Z22  ðZ12 þ Z21 Þ i

ð4:184Þ

4.21

Parameter Conversion

4.21

261

Parameter Conversion

The conversion of S-parameters to Y-parameters and Z-parameters are obtained from 4.83, 4.167, and 4.179 using the following equation. 

Y 1,2 Y 2,2

Y 1,1 Y 2,1



 ¼  ¼

Z 1,2 Z 2,2  0

Z 1,1 Z 2,1 YS 0 



1

YL 1 þ S1,1 S2,1

S1,2 1 þ S2,2



1  S1,1 S2,1

S1,2 1  S2,2

1 ð4:185Þ

The conversion of Y-parameters to S-parameters is achieved by the following steps. 

Y 1,1 Y 2,1

Y 1,2 Y 2,2



v1 v2



 ¼



i1 i2

ð4:186Þ

and 

Y 1,1 Y 2,1

Y 1,2 Y 2,2

 

       vi1 vr1 ii1 ir1  ¼ þ vi2 vr2 ii2 ir2       vi1 YS 0 vr1 ¼ þ 0 YL vi2 vr2

ð4:187Þ

and 

Y 1,1

Y 1,2



vi1



 

YS

0

0 YL Y 2,1 Y 2,2 vi2     Y 1,1 Y 1,2 vr1 YS ¼ þ 0 Y 2,1 Y 2,2 vr2



vi1



vi2   0 vr1 YL

ð4:188Þ

vr2

and 

and

Y 1,1  Y S

Y 1,2

Y 2,1

Y 2,2  Y L



vi1 vi2



 ¼

Y 1,1 þ Y S

Y 1,2

Y 2,1

Y 2,2 þ Y L



vr1 vr2

 ð4:189Þ

262

4 AC Analysis



1 

Y 1,1 þ Y S

Y 1,2

Y 2,1

Y 2,2 þ Y L



Y 1,1  Y S

Y 1,2

Y 2,1

Y 2,2  Y L

vi1



 ¼

vi2

vr1

 ð4:190Þ

vr2

and 

S1,1 S2,1

S1,2 S2,2





Y 1,1 þ Y S ¼ Y 2,1

1 

Y 1,2 Y 2,2 þ Y L

Y 1,1  Y S Y 2,1

Y 1,2 Y 2,2  Y L

 ð4:191Þ

Similarly, the conversion of Z-parameters to S-parameters is achieved by the following steps. 

Z 1,2 Z 2,2

Z 1,1 Z 2,1



i1 i2



 ¼

v1 v2

 ð4:192Þ

and 

Z 1,1

Z 1,2

Z 2,1

Z 2,2

 

ii1



 þ

ii2

ir1



 ¼

Z 1,1

Z 1,2



YS



0

0 YL Z 2,1 Z 2,2

    vi1 vr1  þ vi2 vr2

    vi1 vr1 ¼  vi2 vr2

ir2

ð4:193Þ

and 

1 0 ¼

0 1 



  Z 1,1 vi1  vi2 Z 2,1  Z 1,1 Z 1,2 Y S Z 2,1

   Z 1,2 Y S 0 vi1 0 Y L vi2 Z 2,2      vr1 1 0 vr1 0 þ 0 1 vr2 YL vr2

0

Z 2,2

ð4:194Þ

and 



1  Z 1,1 Y S

Z 1,2 Y L

Z 2,1 Y S

1  Z 2,2 Y L

vi1 vi2



 ¼



1 þ Z 1,1 Y S

Z 1,2 Y L

Z 2,1 Y S

1 þ Z 2,2 Y L

vr1

 ð4:195Þ

vr2

and 

1 þ Z 1,1 Y S

Z 1,2 Y L

Z 2,1 Y S

1 þ Z 2,2 Y L

and

1 

1  Z 1,1 Y S

Z 1,2 Y L

Z 2,1 Y S

1  Z 2,2 Y L



vi1 vi2



 ¼

vr1 vr2

 ð4:196Þ

4.21

Parameter Conversion



S1,1

S1,2

S2,1

S2,2



 ¼

263

1 þ Z 1,1 Y S

Z 1,2 Y L

Z 2,1 Y S

1 þ Z 2,2 Y L

1 

1  Z 1,1 Y S Z 2,1 Y S

Z 1,2 Y L



1  Z 2,2 Y L ð4:197Þ

The following MATLAB code calculates the voltage-gain, the input and the output admittances of the 4-node circuit in this example using Cramer’s rules. Next, it eliminates the two internal nodes and reduces the circuit to two input and output nodes. Finally, the Y- and Z-parameters of the circuit are calculated.

syms v1 v2 v3 v4 syms i1 syms vs GS=1/50; G1=3/50; G2=3/50; G3=3/50; GL=1/50; [Y]=equationsToMatrix([... GS*(vs-v1)==i1;... GS*(v1-vs)+G1*(v1-v4)==0;... G2*(v2-v4)+GL*v2==0;... G3*(v3-v4)+GL*v3==0;... G1*(v4-v1)+G2*(v4-v2)+G3*(v4-v3)==0, ],[vs,v1,v2,v3,v4]); %AC equations in=2; out=4; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')]) Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')]) in=1; out=4; Y([2,out],:)=Y([out,2],:); Y(:,[2,out])=Y(:,[out,2]); Y([1,in],:)=Y([in,1],:); Y(:,[1,in])=Y(:,[in,1]);

264

4 AC Analysis

[m,n]=size(Y); %number of nodes remaining after node elimination nodes=2; for k=1:m-nodes for km=1:m-1 for kn=1:n-1 Y(km,kn)=Y(km,kn)-(Y(m,kn)*Y(km,n))/Y(m,n); end end m=m-1; n=n-1; end Y(setdiff(1:size(Y,1),1:nodes),:)=[]; Y(:,setdiff(1:size(Y,2),1:nodes))=[]; disp(Y) Y11=Y(1,1); Y12=Y(1,2); Y21=Y(2,1); Y22=Y(2,2); deltaZ=Y11.*Y22-Y12.*Y21; Z11=Y22./deltaZ; Z12=-Y12./deltaZ; Z21=-Y21./deltaZ; Z22=Y11./deltaZ;

4.22

Impedance S-Parameters

S-parameters are usually plotted based on circuit impedances. The maximum power from the source is delivered to the load when the source and the load impedances are conjugate of each other and have equal real parts. When the load impedance is varied from this optimum value, as shown in Fig. 4.59, the power delivered to the load reduces from the maximum value. When there is a mismatch between the load and the source admittances (ZL 6¼ ZS or ZL ¼ ZS  ΔZ ), the load voltage is given by

Fig. 4.59 Mismatch between source and load impedances

ZS

vS

iL

vL source

load

ZL=ZS± Z

4.22

Impedance S-Parameters

265

ZL v vL ¼ v S ¼ S ZS þ ZL 2

 ΔZ 2 1þ ZS  ΔZ 2

! ¼ vi þ vr

ð4:198Þ

The load voltage can be written as the summation of the incident voltage (vi) and the reflected voltage (vr). The load current is given by 1 v ¼ S  i L ¼ vS ZS þ ZL 2ZS

 ΔZ 2 1 ZS  ΔZ 2

! ¼ ii  ir ¼

1 ð v þ vr Þ ZS i

ð4:199Þ

The load current can be written as the difference between the incident current (ii) and the reflected current (ir). When the load and the source admittances are matched (ZL ¼ ZS) with zero imaginary parts, the load voltage is given by vL ¼ vS

ZL v ¼ S  ð 1 þ 0Þ ¼ v i þ 0 ZS þ ZL 2

ð4:200Þ

The load voltage is equal to the incident voltage (vi) with zero reflected voltage (vr). The load current is given by iL ¼ vS

1 v 1 ¼ S  ð 1  0Þ ¼ i i  0 ¼ ð v i þ 0Þ ZS þ ZL 2ZS ZS

ð4:201Þ

The load current is equal to the incident current (ii) with zero reflected current (ir). When the load admittance is equal to the source admittance with no imaginary parts, the reflected voltage and the reflected current become zero and the maximum power is delivered to the load. When there is a mismatch between the load and the source admittances, the reflected voltage and the reflected current become nonzero and there will be finite power loss. The load shown in Fig. 4.59 can be considered as a one-port circuit. The ratio of reflected voltage to incident voltage given by 4.198 is called scattering parameter or S-parameter and is equal to

S¼

vr ¼ vi

vS 2

 vS 2



ΔZ 2 ZS ΔZ 2

 ð 1Þ

¼

 ΔZ Z  ZS 2 ¼ L ZL þ ZS ZS  ΔZ 2

ð4:202Þ

The definition of the S-parameters for the two-port circuits is obtained using the testbench shown in Fig. 4.60. The S-parameters of a two-port circuit are defined as

266

4 AC Analysis

i1

ZS

vS1

i2 two port circuit

v1

ZL

vS2

v2

Fig. 4.60 Testbench to calculate impedance S-parameters of a two-port circuit



S1,1

S1,2

S2,1

S2,2



vi1 vi2



 ¼

vr1

 ð4:203Þ

vr2

The voltages at the input and the output nodes of the two-port circuit are given by 

v1 v2



 ¼

vi1



 þ

vi2

vr1 vr2



 ¼



1 þ S1,1

S1,2

S2,1

1 þ S2,2

vi1



vi2

ð4:204Þ

The currents at the input and the output nodes of the two-port circuit are given by 

i1 i2



 ¼





ii1 ir1  ii2 ir2

2 1 6Z ¼4 S 0



2 1 6Z ¼4 S 0

3  7 1  S1,1 5 1 S2,1 ZL 0

3

    vr1 7 vi1 þ 5 1 vi2 vr2 ZL 0

S1,2



1  S2,2

vi1

 ð4:205Þ

vi2

In a special case when the source and the load admittances are equal (ZS ¼ ZL ¼ Z0), the currents of the two-port circuit are given by 

i1 i2



 1 1  S1,1 ¼ Z 0 S2,1

S1,2 1  S2,2



vi1 vi2

 ð4:206Þ

Traditionally, Z0 ¼ 50 Ω because the characteristic impedance of cables used in wireline communications or the characteristic impedance of antennas used in wireless communications were close to 50 Ω. From 4.204 and 4.205, the relationship between the input and the output voltages and currents of the two-port circuit in terms of S-parameters are given by

4.22



Impedance S-Parameters

i1



i2

2 1 6Z ¼4 S 0

267

3

 7 1  S1,1 5 1 S2,1 ZL 0

S1,2



1 þ S1,1

S1,2

S2,1

1 þ S2,2

1  S2,2

1 

v1 v2

 ð4:207Þ

or 

v1 v2



 ¼

1 þ S1,1

S1,2

S2,1

1 þ S2,2



1  S1,1

S1,2

S2,1

1  S2,2

1

2 1 6 ZL 4 0

3

  7 i1 ð4:208Þ 5 1 i2 ZS 0

From above equations, S-parameters defined using impedance models can be converted to Z- and Y-parameters. The following MATLAB code calculates the voltage-gain, the input and the output admittances of the 4-node circuit in this example using Cramer’s rules. Next, it eliminates the two internal nodes and reduces the circuit to two input and output nodes. Finally, the Y- and S-parameters of the circuit are calculated.

syms v1 v2 v3 v4 syms i1 syms vs GS=1/50; G1=3/50; G2=3/50; G3=3/50; GL=1/50; [Y]=equationsToMatrix([... GS*(vs-v1)==i1;... GS*(v1-vs)+G1*(v1-v4)==0;... G2*(v2-v4)+GL*v2==0;... G3*(v3-v4)+GL*v3==0;... G1*(v4-v1)+G2*(v4-v2)+G3*(v4-v3)==0, ],[vs,v1,v2,v3,v4]); %AC equations in=2; out=4; vgain=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1: end)~=in,(1:end)~=in)); disp(['voltage-gain vo/vi = ',num2str(double(vgain),'%.4e')]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['input admittance ii/vi = ',num2str(double(Yin),'%.4e')])

268

4 AC Analysis

Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp(['output admittance io/vo = ',num2str(double(Yout),'%.4e')]) in=1; out=4; Y([2,out],:)=Y([out,2],:); Y(:,[2,out])=Y(:,[out,2]); Y([1,in],:)=Y([in,1],:); Y(:,[1,in])=Y(:,[in,1]); [m,n]=size(Y); %number of nodes remaining after node elimination nodes=2; for k=1:m-nodes for km=1:m-1 for kn=1:n-1 Y(km,kn)=Y(km,kn)-(Y(m,kn)*Y(km,n))/Y(m,n); end end m=m-1; n=n-1; end Y(setdiff(1:size(Y,1),1:nodes),:)=[]; Y(:,setdiff(1:size(Y,2),1:nodes))=[]; disp(Y) Y11=Y(1,1); Y12=Y(1,2); Y21=Y(2,1); Y22=Y(2,2); Z0=50; deltaS=(1+Z0*Y11).*(1+Z0*Y22)-Z0^2*Y12.*Y21; S11=((1-Z0*Y11).*(1+Z0*Y22)+Z0^2*Y12.*Y21)./deltaS; S12=-2*Z0*Y12./deltaS; S21=-2*Z0*Y21./deltaS; S22=((1+Z0*Y11).*(1-Z0*Y22)+Z0^2*Y12.*Y21)./deltaS;

4.23

Characterization

Besides the transient and the spectral plots studied earlier, many other informative plots can be generated in order to help with a thorough circuit analysis. A variety of charts that are generated from circuit transfer functions help with the measurement of the open-loop and the closed-loop gain, phase and impedance variations with respect to frequency, the variations of zeros and poles with changes of the gain, the impedance mismatches, and the stability.

4.23

Characterization

269

ii iS

io

vi

YS

Circuit

vo

YL

Yin Fig. 4.61 Loaded two-port circuit

4.23.1 Poles and Zeros Calculating primary transfer functions (Av( jω) and Yin( jω)) of a two-port circuit in frequency domain, shown in Fig. 4.61, include zeros and poles when the circuit has inductors and capacitors. The general voltage-gain transfer function is given by k P

v ð jωÞ i¼0 Av ð jωÞ ¼ o ¼ k vi ð jωÞ P

ðjωÞi N i ðjωÞi Di

i¼0

¼

N 0 þ ð jωÞN 1 þ ð jωÞ2 N 2 þ ⋯ þ ð jωÞk N k D0 þ ð jωÞD1 þ ð jωÞ2 D2 þ ⋯ þ ð jωÞk Dk

ð4:209Þ

The general input admittance transfer function is given by k P

i ð jωÞ i¼0 Y in ð jωÞ ¼ i ¼ k vi ð jωÞ P

ðjωÞi Oi ðjωÞi Di

i¼0

¼

O0 þ ð jωÞO1 þ ð jωÞ2 O2 þ ⋯ þ ð jωÞk Ok D0 þ ð jωÞD1 þ ð jωÞ2 D2 þ ⋯ þ ð jωÞk Dk

ð4:210Þ

Denominator of both transfer functions is equal. The number of capacitors in electronic circuits is usually higher than the number of inductors because parasitic capacitors exist between all components and interconnects while inductors only exist in long metal interconnects and wires and coils. The voltage-gain transfer function can be rewritten as

270

4 AC Analysis

   N 0 1 þ j ωωz1 1 þ j ωωz2 ⋯ 1 þ j ωωzk   Av ð jωÞ ¼  D0 1 þ j ωωp1 1 þ j ωωp2 ⋯ 1 þ j ωωpk

ð4:211Þ

and   ð jωÞk 2 1 1 1 1 þ ð jω Þ 1 þ jω þ ⋯ þ þ ⋯ þ ωz1 ωzk ωz1 ωz2 ωzk1 ωzk þ ⋯ þ ωz1 ωz2 ⋯ωzk N0   Av ð jωÞ ¼ ð jωÞk D0 1 þ jω 1 þ ⋯ þ 1 þ ð jωÞ2 1 þ ⋯ þ 1 ωp1 ωpk ωp1 ωp2 ωpk1 ωpk þ ⋯ þ ωp1 ωp2 ⋯ωpk

ð4:212Þ and P

1 þ jω

Av ð jωÞ ¼

1 ωzk

þ ð jωÞ2

P

1 ωzk ωzl

m

Þ þ ⋯ þ ωz1ðωz2jω⋯ω zm

k¼1...m ðk6¼lÞ¼1...m N0 ð4:213Þ P P ð jωÞm 2 1 1 D0 1 þ jω ωpk þ ð jωÞ ωpk ωpl þ ⋯ þ ωp1 ωp2 ⋯ωpm ðk6¼lÞ¼1...m

k¼1...m

and P

P

Nkl Ck Cl þ ⋯ þ ð jωÞm N12⋯m C1 C2 ⋯Cm k¼1...m ðk6¼lÞ¼1...m N0 Av ð jωÞ ¼ P P D0 1 þ jω Dk Ck þ ð jωÞ2 Dkl Ck Cl þ ⋯ þ ð jωÞm D12⋯m C1 C2 ⋯Cm 1 þ jω

Nk Ck þ ð jωÞ2

k¼1...m

ðk6¼lÞ¼1...m

ð4:214Þ Similarly, the input admittance transfer function can be written as P

k¼1...m

Ok Ck þ ð jωÞ2

P

Okl Ck Cl þ ⋯ þ ð jωÞm O12⋯m C1 C2 ⋯Cm k¼1...m ðk6¼lÞ¼1...m O0 Y in ð jωÞ ¼ P P D0 1 þ jω Dk Ck þ ð jωÞ2 Dkl Ck Cl þ ⋯ þ ð jωÞm D12⋯m C1 C2 ⋯Cm 1 þ jω

ðk6¼lÞ¼1...m

ð4:215Þ It is possible to obtain each term in numerator and denominator of the voltagegain and input admittance transfer function directly without solving the whole circuit by switching (shorting and opening) capacitors and inductors.

4.23

Characterization

271

4.23.2 Impulse Response When the input signal applied to a circuit is an impulse function δ(t), the signal obtained at the output is called the impulse response h(t) and is equal to the inverse Laplace of the circuit transfer function given by V out ðsÞ ¼ H ðsÞ and V in ðsÞ ¼ 1 ) V out ðsÞ ¼ H ðsÞ V in ðsÞ

ð4:216Þ

Or in time-domain, the output response is given by vout ðt Þ ¼ hðt Þ  vin ðt Þ and vin ðt Þ ¼ δðtÞ ) vout ðt Þ ¼ hðt Þ

ð4:217Þ

Therefore, by applying an impulse function to a circuit with an unknown transfer function, the transfer function can be obtained by measuring the response at the output.

4.23.3 Step Response The step response of a circuit provides important information such as stability and the steady-state behavior at the output of the circuit. When the input signal applied to a circuit is a step function U(t), the signal obtained at the output is called the step response and is obtained by V out ðsÞ H ðsÞ 1 ¼ H ðsÞ and V in ðsÞ ¼ ) V out ðsÞ ¼ s s V in ðsÞ

ð4:218Þ

Or in time-domain, the output response is given by vout ðt Þ ¼ hðt Þ  vin ðt Þ and vin ðt Þ ¼ UðtÞ ¼ ¼

ð1

ð1

δðtÞdt ) vout ðt Þ

0

hðtÞdt

ð4:219Þ

t

Because a step function is the integral of the impulse function, the step response can be considered as the integral of the circuit transfer function. If this integral is finite, the circuit can be stable.

272

4 AC Analysis

4.23.4 Bode Plots The bode plot measures the change of gain magnitude and phase of a circuit transfer function (mostly voltage-gain) with respect to the frequency in Cartesian coordinates. From 4.211, the magnitude of voltage-gain transfer function is obtained by      N 1 þ j ω 1 þ j ω ⋯ 1 þ j ω   0 ωz1 ωz2 ωzk     jAv ð jωÞj ¼   D0 1 þ j ωω 1 þ j ωω ⋯ 1 þ j ωω  p1 p2 pk

ð4:220Þ

and the phase of voltage-gain transfer function is obtained by    N 0 1 þ j ωωz1 1 þ j ωωz2 ⋯ 1 þ j ωωzk   ∠Av ð jωÞ ¼ ∠  D0 1 þ j ωωp1 1 þ j ωωp2 ⋯ 1 þ j ωωpk

ð4:221Þ

Which simplifies to ∠Av ð jωÞ ¼

X

tan 1

X ω ω  tan 1 ωzk ωpk

ð4:222Þ

And the group delay is calculated by delay ¼ 

X ω d∠Av ð jωÞ X ωpk zk ¼  2 2 dω ω þ ωpk ω2 þ ωzk 2

ð4:223Þ

The gain magnitude of the bode plot is scaled as 20log10|Av( jω)| and frequency axis takes a logarithmic scale in order to show details of the gain, the phase, and the group delay variations. From the bode plot, low frequency and high frequency poles and zeros can be extracted. It also shows the gain flatness and parameters such as gain and phase margins to help determine the stability of a circuit. The gain margin is defined as the gain difference between the unity-gain and the gain where it has a phase shift of 180 . The phase margin is defined as the phase difference between the phase of the operating gain and 180 . In circuits with feedback, a 180 phase shift in the gain transfer function can cause instability and positive feedback. To prevent instability, the operating frequency must be chosen in an interval where the phase margin is relatively large in order to ensure the phase of the circuit transfer function never gets close to 180 .

4.23

Characterization

273

4.23.5 Root Locus The root locus plot measures the variations of the poles and zeros of a transfer function in a polar plot (imaginary versus real) with respect to the change of a constant gain k > 0 defined from (4.211), by Av ð jωÞ k ðs þ ωz1 Þðs þ ωz2 Þ⋯ðs þ ωzk Þ      ¼ 1 þ Av ð jωÞ k ððs þ ωz1 Þðs þ ωz2 Þ⋯ðs þ ωzk ÞÞ þ s þ ωp1 s þ ωp2 ⋯ s þ ωpk ð4:224Þ In a circuit with certain poles and zeros, solving the following equation and finding s in terms of k generates in Root Locus.      k ððs þ ωz1 Þðs þ ωz2 Þ⋯ðs þ ωzk ÞÞ þ s þ ωp1 s þ ωp2 ⋯ s þ ωpk ¼ 0 ð4:225Þ

4.23.6 Nyquist Plot The Nyquist plot measures the variations of the real and imaginary parts of the openloop voltage-gain transfer function by sweeping the frequency in polar coordinates. From 4.211, the gain can be written as Av ð jωÞ ¼ Gð jωÞejθð

jωÞ

ð4:226Þ

When placed in a direct negative feedback, the closed-loop gain of the circuit is given by Av ð jωÞ Gð jωÞejθð jωÞ ¼ M ð jωÞejφð ¼ 1 þ Av ð jωÞ 1 þ Gð jωÞejθð jωÞ

jωÞ

ð4:227Þ

The magnitude contours of the Nyquist plot are obtained by    Gð jωÞejθð jωÞ  Gð jωÞ   ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi M ð jωÞ ¼  ð4:228Þ  jθ ð jω Þ 1 þ Gð jωÞe 1 þ Gð jωÞ2 þ 2Gð jωÞ cos ðθð jωÞÞ And the phase contours of the Nyquist plot are obtained by

 Gð jωÞejθð jωÞ sin ðθð jωÞÞ 1 ¼ tan φð jωÞ ¼ ∠ Gð jωÞ þ cos ðθð jωÞÞ 1 þ Gð jωÞejθð jωÞ

ð4:229Þ

274

4 AC Analysis

The phase contours are mapped to a numerical axis by N ð jωÞ ¼ tan ðφð jωÞÞ ¼

sin ðθð jωÞÞ Gð jωÞ þ cos ðθð jωÞÞ

ð4:230Þ

The stability of a transfer function can be determined by the difference between the clockwise and the counter clock-wise encirclement of the Nyquist plot over point 1 + j0. A higher number of clockwise encirclement suggest the system can be unstable. The Nyquist plot is first generated for positive frequencies and then mirrored horizontally to create the rest of the plot for negative frequencies. This mirroring will create a continuous plot. At low frequencies, capacitors and inductors are open or short and the transfer function will be real. Therefore, the start of the Nyquist plot from low frequencies begins from the horizontal line where imaginary axis is zero. Tracing the Nyquist plot from low frequencies towards high frequencies helps determine the clockwise or the counter clock-wise encirclement of the point 1 + j0.

4.23.7 Nichols Plot The Nichols plot measures the variations of the gain and phase of the open-loop voltage-gain transfer function by sweeping the frequency in Cartesian coordinates. From 4.211, the gain can be written as Av ð jωÞ ¼ xð jωÞ þ jyð jωÞ

ð4:231Þ

When placed in a direct negative feedback, the closed-loop gain of the circuit is given by Av ð jωÞ xð jωÞ þ jyð jωÞ ¼ ¼ M ð jωÞejφð 1 þ Av ð jωÞ 1 þ xð jωÞ þ jyð jωÞ

jωÞ

ð4:232Þ

The magnitude contours of the Nichols plot are obtained by qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   xð jωÞ2 þ yð jωÞ2  xð jωÞ þ jyð jωÞ   ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi M ð jωÞ ¼  1 þ xð jωÞ þ jyð jωÞ ð1 þ xð jωÞÞ2 þ yð jωÞ2 And the phase contours of the Nichols plot are obtained by

ð4:233Þ

4.23

Characterization

275

xð jωÞ þ jyð jωÞ 1 þ xð jωÞ þ jyð jωÞ



 yð jωÞ 1 yð jωÞ 1 ¼ tan  tan xð jωÞ 1 þ xð jωÞ

φð jωÞ ¼ ∠

ð4:234Þ

The phase contours are mapped to a numerical axis by N ð jωÞ ¼ tan ðφð jωÞÞ ¼

yð jωÞ xð jωÞ2 þ xð jωÞ þ yð jωÞ2

ð4:235Þ

and M and N contours are obtained by rewriting 4.233 and 4.235 as M ð jωÞ2 xð jωÞ  1  M ð jωÞ2

!2 2

þ yð jωÞ ¼

M ð jωÞ 1  M ð jωÞ2

!2 ð4:236Þ

and 0rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2ffi12 1

2  B 1 þ N ð jωÞ C 1 2 1 C xð jωÞ þ þ yð jωÞ  ¼B @ A 2 2 2N ð jωÞ

ð4:237Þ

4.23.8 Smith Chart The Smith Chart is the polar plot (imaginary versus real) of S-parameters and Γ contours obtained from 4.172 by Yin ð jωÞ 1 þ S1,1 ð jωÞ 1 þ Γ r ð jωÞ þ jΓ i ð jωÞ ¼ ¼ ¼ rð jωÞ þ jxð jωÞ ð4:238Þ YS 1  S1,1 ð jωÞ 1  Γ r ð jωÞ  jΓ i ð jωÞ where Γ r is the real part and Γ i is the imaginary part of the S-parameter and 0  r < 1 is the normalized resistance and 1 < x < 1 is the normalized reactance. The normalized resistance and reactance are obtained by

rð jωÞ ¼ real and

1 þ Γ r ð jωÞ þ jΓ i ð jωÞ 1  Γ r ð jωÞ  jΓ i ð jωÞ

 ¼

1  Γ r ð jωÞ2  Γ i ð jωÞ2 ð1  Γ r ð jωÞÞ2 þ Γ i ð jωÞ2

ð4:239Þ

276

4 AC Analysis

 1 þ Γ r ð jωÞ þ jΓ i ð jωÞ 2Γ i ð jωÞ xð jωÞ ¼ imag ð4:240Þ ¼ 1  Γ r ð jωÞ  jΓ i ð jωÞ ð1  Γ r ð jωÞÞ2 þ Γ i ð jωÞ2 and Γ contours are obtained by rewriting 4.239 and 4.240 as

Γ r ð jωÞ 

gð jωÞ gð jωÞ þ 1

2

2

þ Γ i ð jωÞ ¼

1 gð jωÞ þ 1

2 ð4:241Þ

and

1 ðΓ r ð jωÞ  1Þ þ Γ i ð jωÞ  bð jωÞ 2

2

¼

1 bð jωÞ

2 ð4:242Þ

In the Smith chart, the upper half-circle represents where the circuit behaves as inductors and the lower half-circle represents where the circuit behaves as capacitors. The center of the Smith chart represents where the impedance of the circuit is matched to the impedance of the load or the external source. The horizontal line passing through the center of the Smith chart presents where the circuit becomes purely resistive with no imaginary part. The left point on the horizontal line presents an open circuit and the right point on the horizontal line presents a short circuit. If a transfer function has a plot outside of the Smith chart circle, the magnitude of the S-parameters becomes more than unity meaning the reflection voltage or current signals are larger than the incident voltage or current signals indicating the instability of the circuit.

4.24

Piezoelectric Crystal

A piezoelectric material accumulates electric charges based on the pressure applied to it. Under varying pressure or vibration, a piezoelectric material generates a varying current that can be used to process the pressure. By applying a varying voltage to the piezoelectric material, it oscillates at harmonics of its natural frequency. This can be used for stabilization of a waveform that has a frequency close to the oscillation frequency of the piezoelectric material. A piezoelectric crystal filter is characterized, as shown in Fig. 4.62. The inductance between input and the inner terminal of the crystal filter is measured to be L ¼ 1 μH. The capacitance between the inner terminal of the crystal filter and the output is measured to be C ¼ 100 pF. The conductance between the inner terminal of the crystal filter and the ground is G ¼ 103 Ω1. At output, the filter is connected to YL ¼ 0.02 Ω1 load admittance. The input admittance of the filter is given by

4.24

Piezoelectric Crystal

277

Fig. 4.62 A piezoelectric crystal filter

1

2

L G

C

YL

Fig. 4.63 (a) Input admittance and (b) Voltage-gain of the filter

Y in ðsÞ ¼

s2

106 s þ 9:524  1012 þ 5:714  107 s þ 9:524  1015

ð4:243Þ

The voltage-gain of the filter is given by v2 ð s Þ 4:762  107 s ¼ 2 v1 ðsÞ s þ 5:714  107 s þ 9:524  1015

ð4:244Þ

The input admittance and voltage-gain bode plots of the filter are shown in Fig. 4.63. The magnitude and phase change at the resonance frequency of 15 MHz. The crystal represents a bandpass behavior. The S-parameters of the filter are shown in Fig. 4.64. At low frequencies, the crystal behaves as a capacitor and after the resonance frequency of 15 MHz, the crystal behaves as an inductor. The impulse and step responses of the filter are shown in Fig. 4.65. The graphs show that the crystal has an underdamped response and is stable. The root locus of the filter is shown in Fig. 4.66. The graph shows the variation of the zero and the two poles of the crystal as the loop-gain of the filter changes.

278

4 AC Analysis

Fig. 4.64 S-parameters of the filter, (a) S11 and (b) S21

Fig. 4.65 (a) Impulse and (b) Step responses of the filter

The Nyquist and Nichols plots of the filter are shown in Fig. 4.67. The graphs show the variations of the real and imaginary parts and the gain and phase of the open-loop voltage-gain of the crystal with respect to the frequency change. The transient response and the spectrum of the sinusoidal waveforms passing through filter are shown in Fig. 4.68. The crystal attenuates sinusoidal frequencies that are not close to the harmonics of its natural frequencies. The bandpass characteristic of the crystal filters the waveforms and extracts sinusoidal, as shown by the following two figures. The transient response and the spectrum of the square waveforms passing through filter are shown in Fig. 4.69. The transient response and the spectrum of the Sawtooth waveforms passing through filter are shown in Fig. 4.70.

4.24

Piezoelectric Crystal

Fig. 4.66 Root locus of the filter

Fig. 4.67 (a) Nyquist and (b) Nichols plots of the filter

Fig. 4.68 (a) Transient response and (b) Spectrum of the sinusoidal waveforms in filter

279

280

4 AC Analysis

Fig. 4.69 (a) Transient response and (b) Spectrum of the square waveforms in filter

Fig. 4.70 (a) Transient response and (b) Spectrum of the sawtooth waveforms in filter

The following MATLAB code calculates the voltage-gain and the input admittance of a Piezoelectric from the admittance matrix and then calculates the S-parameters and generates a variety of plots in order to characterize the Piezoelectric.

f0=1e+07; C=100e-12; L=1e-06; G=1e-03; YL=1/50; YS=YL; f=logspace(5,9,1001); syms s t Y=[1/(s*L) 0 -1/(s*L);...

4.25

Shunt Harmonic Traps

281

0 s*C+YL -s*C;... -1/(s*L) -s*C G+s*C+1/(s*L)]; v2v1=-det(Y((1:end)~=1,(1:end)~=2))/det(Y((1:end)~=1,(1:end) ~=1)); Yin=det(Y)/det(Y((1:end)~=1,(1:end)~=1)); S11=subs((Yin-YS)/(Yin+YS),s,1i*2*pi*f); S21=subs(-v2v1*2*YS/(Yin+YS),s,1i*2*pi*f); disp(['Analyzed Transfer Function: ',char('v2v1')]) mysys=tf2sys(v2v1,'show'); figure subplot(2,1,1) semilogx(f,abs(double(subs(Yin,s,1i*2*pi*f)))) subplot(2,1,2) semilogx(f,angle(double(subs(Yin,s,1i*2*pi*f)))) figure smithplot(double(S11)) figure smithplot(double(S21)) figure bode(mysys) figure rlocus(mysys) figure nyquist(mysys) figure nichols(mysys) figure step(mysys) figure impulse(mysys) function mysys=tf2sys(mytf,show) mysys=mytf; if isequal(show,'show') disp(vpa(partfrac(mysys,sym('s')),2)) end eval('s=tf(''s'');') eval(['mysys=',char(mysys),';']) end

4.25

Shunt Harmonic Traps

A harmonic trap consists of the series combination of an inductor and a capacitor placed in shunt. At the resonance frequency, the impedance of the series LC becomes zero. When the series LC is placed in shunt, it connects the node voltage

282

4 AC Analysis

Fig. 4.71 Filter circuit

1

G1

v1

5 L1

L2

L3

2

3

4

C1

C2

C3

to the ground at the resonance frequency and acts as a trap while passing all other frequencies. The filter circuit is shown in Fig. 4.71. The admittance matrix of the filter is given by 2

G1 6 6 0 6 Y¼6 6 0 6 4 0 G1

0 sC1 þ 1=ðsL1 Þ

0 0

0 0

0 0

sC2 þ 1=ðsL2 Þ 0

0 sC3 þ 1=ðsL3 Þ

1=ðsL1 Þ

1=ðsL2 Þ

1=ðsL3 Þ

3 G1 7 1=ðsL1 Þ 7 7 1=ðsL2 Þ 7 7 7 1=ðsL3 Þ 5 Y5,5 ð4:245Þ

where Y5,5 ¼ G1 þ 1=ðsL1 Þ þ 1=ðsL2 Þ þ 1=ðsL3 Þ

ð4:246Þ

The voltage-gain transfer function of the filter (the input node i ¼ 1 and the output node o ¼ 5) is given by

ð4:247Þ The circuit parameters are listed in Table 4.10. The pole-zero map of the filter is shown in Fig. 4.72. The filter consists of three inductors and three capacitors creating three complex zeros and poles. The gain, phase, and delay responses of the filter are shown in Fig. 4.73. As expected, the filter traps three frequencies where the three series LC circuits resonate.

4.25

Shunt Harmonic Traps

Table 4.10 Circuit parameters

Fig. 4.72 Pole-zero map of the filter

Fig. 4.73 Gain, phase, and delay responses of the filter

283 G1 ¼ 0.01 [A/V]

L1 ¼ 16 μH L2 ¼ 8 μH L3 ¼ 5.3 μH

C1 ¼ 1.6 nF C2 ¼ 800 pF C3 ¼ 530 pF

284

4 AC Analysis

The following MATLAB code uses Cramer’s rules to calculate the voltage-gain and input and output admittances of the circuit in this example. It also plots the polezero map and the phase and the group delay characteristics of the voltage-gain.

syms G1 C1 L1 G2 C2 L2 G3 C3 L3 syms s Y=[G1 0 0 0 -G1;... 0 1/(s*L1)+s*C1 0 0 -1/(s*L1) ;... 0 0 1/(s*L2)+s*C2 0 -1/(s*L2);... 0 0 0 1/(s*L3)+s*C3 -1/(s*L3);... -G1 -1/(s*L1) -1/(s*L2) -1/(s*L3) 1/(s*L1)+1/(s*L2)+1/(s*L3) +G1+G2]; in=1; out=5; H=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1:end) ~=in,(1:end)~=in)); Yi=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); Yo=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); f0=1e06; G1=0.01; C1=G1/(2*pi*f0*1); L1=1/(C1*(2*pi*(f0*1))^2); G2=0.01; C2=G2/(2*pi*f0*2); L2=1/(C2*(2*pi*(f0*2))^2); G3=0.01; C3=G3/(2*pi*f0*3); L3=1/(C3*(2*pi*(f0*3))^2); disp(H) disp(['C1 = ',num2str(C1)]) disp(['L1 = ',num2str(L1)]) disp(['C2 = ',num2str(C2)]) disp(['L2 = ',num2str(L2)]) disp(['C3 = ',num2str(C3)]) disp(['L3 = ',num2str(L3)]) [num,den]=numden(eval(H)); cnum=sym2poly(num); cden=sym2poly(den); [p,z]=pzmap(tf(cnum,cden)); f=logspace(log10(f0)-1,log10(f0)+1,1000); figure xline(0,'--r','LineWidth',1.0); yline(0,'--r','LineWidth',1.0); hold on

4.26

Sequential Harmonic Passes

285

plot(real(z),imag(z),'o','MarkerSize',6); plot(real(p),imag(p),'p','MarkerSize',10); figure subplot(3,1,1) semilogx(f,20*log10(abs(double(subs(eval(H),s,1i*2*pi*f).')))) subplot(3,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(H), s,1i*2*pi*f).')))) subplot(3,1,3) loglog(f(1:end-1),-diff(unwrap(angle(double(subs(eval(H), s,1i*2*pi*f).'))))./diff(2*pi*f.'))

4.26

Sequential Harmonic Passes

A harmonic pass consists of the series combination of an inductor and a capacitor placed sequentially. At the resonance frequency, the impedance of the series LC becomes zero. When the series LC is placed sequentially between two nodes, it connects them together at the resonance frequency and acts as a pass while blocking all other frequencies. The filter circuit is shown in Fig. 4.74. The admittance matrix of the filter is given by 2

Y1,1

6 6 1=ðsL1 Þ 6 Y¼6 6 1=ðsL2 Þ 6 4 1=ðsL3 Þ 0

1=ðsL1 Þ

1=ðsL2 Þ

1=ðsL3 Þ

sC1 þ 1=ðsL1 Þ

0

0

0 0

sC2 þ 1=ðsL2 Þ 0

0 sC3 þ 1=ðsL3 Þ

sC1

sC2

sC3

0

3

7 sC1 7 7 sC2 7 7 7 sC3 5 Y5,5 ð4:248Þ

where

Fig. 4.74 Filter circuit

1 v1

L1

2

L2

3

L3

4

C1 C2 C3

5 G1

286

4 AC Analysis

Y1,1 ¼ 1=ðsL1 Þ þ 1=ðsL2 Þ þ 1=ðsL3 Þ

ð4:249Þ

Y5,5 ¼ G1 þ sC1 þ sC2 þ sC3

ð4:250Þ

and

The voltage-gain transfer function of the filter (the input node i ¼ 1 and the output node o ¼ 5) is given by

ð4:251Þ The circuit parameters are listed in Table 4.11. The pole-zero map of the filter is shown in Fig. 4.75. The filter consists of three inductors and three capacitors creating three complex zeros and poles.

Table 4.11 Circuit parameters

Fig. 4.75 Pole-zero map of the filter

G1 ¼ 0.01 [A/V]

L1 ¼ 16 μH L2 ¼ 8 μH L3 ¼ 5.3 μH

C1 ¼ 1.6 nF C2 ¼ 800 pF C3 ¼ 530 pF

4.26

Sequential Harmonic Passes

287

Fig. 4.76 Gain, phase, and delay responses of the filter

The gain, phase, and delay responses of the filter are shown in Fig. 4.76. As expected, the filter passes three frequencies where the three series LC circuits resonate. The following MATLAB code uses Cramer’s rules to calculate the voltage-gain and input and output admittances of the circuit in this example. It also plots the polezero map and the phase and the group delay characteristics of the voltage-gain.

syms G1 C1 L1 G2 C2 L2 G3 C3 L3 GL syms s Y=[1/(s*L1)+1/(s*L2)+1/(s*L3) -1/(s*L1) -1/(s*L2) -1/(s*L3) 0;... -1/(s*L1) 1/(s*L1)+s*C1 0 0 -s*C1;... -1/(s*L2) 0 1/(s*L2)+s*C2 0 -s*C2;... -1/(s*L3) 0 0 1/(s*L3)+s*C3 -s*C3;... 0 -s*C1 -s*C2 -s*C3 s*C1+s*C2+s*C3+GL]; in=1; out=5; H=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1:end) ~=in,(1:end)~=in)); Yi=det(Y)/det(Y((1:end)~=in,(1:end)~=in));

288

4 AC Analysis

Yo=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); f0=1e06; GL=0.01; G1=0.001; C1=G1/(2*pi*f0*1); L1=1/(C1*(2*pi*(f0*1))^2); G2=0.001; C2=G2/(2*pi*f0*2); L2=1/(C2*(2*pi*(f0*2))^2); G3=0.001; C3=G3/(2*pi*f0*3); L3=1/(C3*(2*pi*(f0*3))^2); disp(H) disp(['C1 = ',num2str(C1)]) disp(['L1 = ',num2str(L1)]) disp(['C2 = ',num2str(C2)]) disp(['L2 = ',num2str(L2)]) disp(['C3 = ',num2str(C3)]) disp(['L3 = ',num2str(L3)]) [num,den]=numden(eval(H)); cnum=sym2poly(num); cden=sym2poly(den); [p,z]=pzmap(tf(cnum,cden)); f=logspace(log10(f0)-1,log10(f0)+1,1000); figure xline(0,'--r','LineWidth',1.0); yline(0,'--r','LineWidth',1.0); hold on plot(real(z),imag(z),'o','MarkerSize',6); plot(real(p),imag(p),'p','MarkerSize',10); figure subplot(3,1,1) semilogx(f,20*log10(abs(double(subs(eval(H),s,1i*2*pi*f).')))) subplot(3,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(H), s,1i*2*pi*f).')))) subplot(3,1,3) loglog(f(1:end-1),-diff(unwrap(angle(double(subs(eval(H), s,1i*2*pi*f).'))))./diff(2*pi*f.'))

4.27

Shunt Harmonic Passes

A harmonic pass consists of the parallel combination of an inductor and a capacitor placed in shunt. At the resonance frequency, the admittance of the parallel LC becomes zero (infinite impedance). When the parallel LC is placed in shunt, it

4.27

Shunt Harmonic Passes

289

Fig. 4.77 Filter circuit

G1

1 v1

4 L1

C1 3

L2

C2 2

L3

C3

disconnects the node voltage from ground at the resonance frequency and acts as a pass while trapping all other frequencies. The filter circuit is shown in Fig. 4.77. The admittance matrix of the filter is given by 2

G1

6 0 6 Y¼6 4 0

G1

0

0

G1

Yb þ Yc Yb

Yb Ya þ Yb

0 Ya

0

Ya

G1 þ Ya

3 7 7 7 5

ð4:252Þ

where Ya ¼ sC1 þ 1=ðsL1 Þ

ð4:253Þ

Yb ¼ sC2 þ 1=ðsL2 Þ

ð4:254Þ

Yc ¼ sC3 þ 1=ðsL3 Þ

ð4:255Þ

and

and

The voltage-gain transfer function of the filter (the input node i ¼ 1 and the output node o ¼ 4) is given by

ð4:256Þ

The circuit parameters are listed in Table 4.12.

290 Table 4.12 Circuit parameters

4 AC Analysis G1 ¼ 0.01 [A/V]

L1 ¼ 16 μH L2 ¼ 8 μH L3 ¼ 5.3 μH

C1 ¼ 1.6 nF C2 ¼ 800 pF C3 ¼ 530 pF

Fig. 4.78 Pole-zero map of the Filter

The pole-zero map of the filter is shown in Fig. 4.78. The filter consists of three inductors and three capacitors creating three complex zeros and poles. The gain, phase and delay responses of the filter are shown in Fig. 4.79. As expected, the filter passes three frequencies where the three series LC circuits resonate. The following MATLAB code uses Cramer’s rules to calculate the voltage-gain and input and output admittances of the circuit in this example. It also plots the polezero map and the phase and the group delay characteristics of the voltage-gain.

syms G1 C1 L1 G2 C2 L2 G3 C3 L3 GS syms s Y=[GS 0 0 -GS;... 0 1/(s*L2)+s*C2+1/(s*L3)+s*C3 -1/(s*L2)-s*C2 0;... 0 -1/(s*L2)-s*C2 1/(s*L1)+s*C1+1/(s*L2)+s*C2 -1/(s*L1)-s*C1;... -GS 0 -1/(s*L1)-s*C1 GS+1/(s*L1)+s*C1]; in=1; out=4; H=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1:end) ~=in,(1:end)~=in)); Yi=det(Y)/det(Y((1:end)~=in,(1:end)~=in));

4.27

Shunt Harmonic Passes

Fig. 4.79 Gain, phase, and delay responses of the Filter

Yo=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); f0=1e06; GS=0.001; G1=0.01; C1=G1/(2*pi*f0*1); L1=1/(C1*(2*pi*(f0*1))^2); G2=0.01; C2=G2/(2*pi*f0*2); L2=1/(C2*(2*pi*(f0*2))^2); G3=0.01; C3=G3/(2*pi*f0*3); L3=1/(C3*(2*pi*(f0*3))^2); disp(H) disp(['C1 = ',num2str(C1)]) disp(['L1 = ',num2str(L1)]) disp(['C2 = ',num2str(C2)]) disp(['L2 = ',num2str(L2)]) disp(['C3 = ',num2str(C3)]) disp(['L3 = ',num2str(L3)]) [num,den]=numden(eval(H)); cnum=sym2poly(num); cden=sym2poly(den);

291

292

4 AC Analysis

[p,z]=pzmap(tf(cnum,cden)); f=logspace(log10(f0)-1,log10(f0)+1,1000); figure xline(0,'--r','LineWidth',1.0); yline(0,'--r','LineWidth',1.0); hold on plot(real(z),imag(z),'o','MarkerSize',6); plot(real(p),imag(p),'p','MarkerSize',10); figure subplot(3,1,1) semilogx(f,20*log10(abs(double(subs(eval(H),s,1i*2*pi*f).')))) subplot(3,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(H), s,1i*2*pi*f).')))) subplot(3,1,3) loglog(f(1:end-1),-diff(unwrap(angle(double(subs(eval(H), s,1i*2*pi*f).'))))./diff(2*pi*f.'))

4.28

Single-Stage Poly Phase Filters

Poly phase filters are used to generate equal phase shifts among their outputs. A single-stage poly phase filter is shown in Fig. 4.80. The input source of the poly phase filter is differential (vin+ ¼  vin) and connected between nodes 1 and 2. The outputs are taken from nodes 3, 4, 5, and 6 as listed by

Fig. 4.80 Single-stage poly phase filter

G1

3

GL

4

GL

5

GL

6

GL

C1 1

G1 C1

vin

G1 2

C1 G1 C1

4.28

Single-Stage Poly Phase Filters

293

3 2 3 i1 v1 6 v 7 6 i 7 6 27 6 17 7 6 7 6 6 v3 7 6 0 7 7¼6 7 Y6 6v 7 6 0 7 7 6 47 6 7 6 7 6 4 v5 5 4 0 5 2

v6

ð4:257Þ

0

The admittance matrix of the poly phase filter is given by 2

2G1 þ 2sC1 6 0 6 6 6 G1 Y¼6 6 G  sC 1 1 6 6 4 sC1 0

0

G1

G1  sC1

sC1

0

2G1 þ 2sC1

sC1

0

G1

G1  sC1

sC1 0

G1 þ GL þ sC1 0

0 G1 þ GL þ sC1

0 0

0 0

G1 G1  sC1

0 0

0 0

G1 þ GL þ sC1 0

0 G1 þ GL þ sC1

3 7 7 7 7 7 7 7 7 5

ð4:258Þ The voltage-gain transfer function at node 3 of the polyphaser filter is obtained by superposition with respect to vin+ when vin is shorted to ground and with respect to vin when vin+ is shorted to ground. The voltage at node 3 is given by v3 ¼

jYðdelete rows 1 and 2, delete columns 2 and 3Þj þ v jYðdelete rows 1 and 2, delete columns 1 and 2Þj in 

jYðdelete rows 1 and 2, delete columns 1 and 3Þj  v jYðdelete rows 1 and 2, delete columns 1 and 2Þj in

ð4:259Þ

which is simplified to v3 G1 þ sC1 ¼ vin G1 þ GL þ sC1

ð4:260Þ

The voltage-gain transfer function at node 4 of the polyphaser filter is obtained by v4 G1  sC1 ¼ vin G1 þ GL þ sC1

ð4:261Þ

The voltage-gain transfer function at node 5 of the polyphaser filter is obtained by v5 G1  sC1 ¼ vin G1 þ GL þ sC1

ð4:262Þ

The voltage-gain transfer function at node 6 of the polyphaser filter is obtained by

294

4 AC Analysis

Table 4.13 Circuit parameters G1 ¼ 0.01 [A/V]

C1 ¼ 16 pF

f0 ¼ 108 Hz

GL ¼ 0.0001 [A/V]

Fig. 4.81 Transient responses of the single-stage poly phase filter

v6 G1 þ sC1 ¼ vin G1 þ GL þ sC1

ð4:263Þ

The component values of the filter for f0 ¼ 108 Hz are listed in Table 4.13. The transient response of the single-stage poly phase filter is shown in Fig. 4.81. Equal phase shifts among the four outputs appear as uniform delays in the transient response. The gain, phase, and delay variations of the single-stage poly phase filter with respect to frequency are shown in Fig. 4.82. At f0, the phase differences between consecutive outputs become 90 . The input impedance of the poly phase filter is obtained by jYðdelete row 2, delete column 2Þj i1 ¼ v1 jYðdelete rows 1 and 2, delete columns 1 and 2Þj

ð4:264Þ

which is simplified to G G þ sC1 ðG1 þ GL Þ i1 ¼2 1 L G1 þ GL þ sC1 v1

ð4:265Þ

The variation of the input impedance of the poly phase filter with respect to the frequency is shown in Fig. 4.83. This graph is very useful while the impedance matching and the maximum power transformation must be satisfied at the input of a poly phase filter used in a receiver. The output impedance of the poly phase filter is obtained by

4.28

Single-Stage Poly Phase Filters

Fig. 4.82 Gain, phase, and delay of the single-stage poly phase filter

Fig. 4.83 Input impedance of the single-stage poly phase filter

295

296

4 AC Analysis

Fig. 4.84 Output impedance of the singlestage poly phase filter

jYðdelete rows 1 and 2, delete columns 1 and 2Þj i3 ¼ v3 jYðdelete rows 1, 2, and 3, delete columns 1, 2, and 3Þj

ð4:266Þ

which is simplified to i3 ¼ G1 þ GL þ sC1 v3

ð4:267Þ

The variation of the output impedance of the poly phase filter with respect to the frequency is shown in Fig. 4.84. This graph is very useful while the impedance matching and the maximum power transformation must be satisfied at the output of a poly phase filter used in a transmitter. The following MATLAB code uses Cramer’s rules to calculate the voltage signals and the impedances at different nodes of the poly phase filter studied in this example.

syms s G C GL %in+,in-,out1,out2,out3,out4 Y=[2*(G+s*C) 0 -G -G-s*C -s*C 0;... 0 2*(G+s*C) -s*C 0 -G -G-s*C;... -G -s*C GL+G+s*C 0 0 0;... -G-s*C 0 0 GL+G+s*C 0 0;...

4.28

Single-Stage Poly Phase Filters

297

-s*C -G 0 0 GL+G+s*C 0;... 0 -G-s*C 0 0 0 GL+G+s*C]; in1=1; in2=2; out=3; v3vin=((-1)^(in1+in2+out))*det(Y((1:end)~=in2 & (1:end)~=in1,(1: end)~=in2 & (1:end)~=out))/det(Y((1:end)~=in2 & (1:end)~=in1,(1:end) ~=in2 & (1:end)~=in1))-... ((-1)^(in1+in2+out))*det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=out))/det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=in2)); simplify(v3vin) in1=1; in2=2; out=4; v4vin=((-1)^(in1+in2+out))*det(Y((1:end)~=in2 & (1:end)~=in1,(1: end)~=in2 & (1:end)~=out))/det(Y((1:end)~=in2 & (1:end)~=in1,(1:end) ~=in2 & (1:end)~=in1))-... ((-1)^(in1+in2+out))*det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=out))/det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=in2)); simplify(v4vin) in1=1; in2=2; out=5; v5vin=((-1)^(in1+in2+out))*det(Y((1:end)~=in2 & (1:end)~=in1,(1: end)~=in2 & (1:end)~=out))/det(Y((1:end)~=in2 & (1:end)~=in1,(1:end) ~=in2 & (1:end)~=in1))-... ((-1)^(in1+in2+out))*det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=out))/det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=in2)); simplify(v5vin) in1=1; in2=2; out=6; v6vin=((-1)^(in1+in2+out))*det(Y((1:end)~=in2 & (1:end)~=in1,(1: end)~=in2 & (1:end)~=out))/det(Y((1:end)~=in2 & (1:end)~=in1,(1:end) ~=in2 & (1:end)~=in1))-... ((-1)^(in1+in2+out))*det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=out))/det(Y((1:end)~=in1 & (1:end)~=in2,(1:end) ~=in1 & (1:end)~=in2)); simplify(v6vin) in1=1; in2=2; i1v1=det(Y((1:end)~=in2,(1:end)~=in2))/det(Y((1:end)~=in2 & (1:end) ~=in1,(1:end)~=in2 & (1:end)~=in1)); simplify(i1v1)

298

4 AC Analysis

in1=1; in2=2; out=3; i3v3=det(Y((1:end)~=in2 & (1:end)~=in1,(1:end)~=in2 & (1:end) ~=in1))/det(Y((1:end)~=in2 & (1:end)~=in1 & (1:end)~=out,(1:end) ~=in2 & (1:end)~=in1 & (1:end)~=out)); simplify(i3v3) in1=1; in2=2; out=4; i4v4=det(Y((1:end)~=in2 & (1:end)~=in1,(1:end)~=in2 & (1:end) ~=in1))/det(Y((1:end)~=in2 & (1:end)~=in1 & (1:end)~=out,(1:end) ~=in2 & (1:end)~=in1 & (1:end)~=out)); simplify(i4v4) in1=1; in2=2; out=5; i5v5=det(Y((1:end)~=in2 & (1:end)~=in1,(1:end)~=in2 & (1:end) ~=in1))/det(Y((1:end)~=in2 & (1:end)~=in1 & (1:end)~=out,(1:end) ~=in2 & (1:end)~=in1 & (1:end)~=out)); simplify(i5v5) in1=1; in2=2; out=6; i6v6=det(Y((1:end)~=in2 & (1:end)~=in1,(1:end)~=in2 & (1:end) ~=in1))/det(Y((1:end)~=in2 & (1:end)~=in1 & (1:end)~=out,(1:end) ~=in2 & (1:end)~=in1 & (1:end)~=out)); simplify(i6v6) f=logspace(7,9,101); f0=1e8; G=1e-02; GL=1e-04; C=G/(2*pi*f0); figure semilogx(f,20*log10(abs(double(subs(eval(v3vin), s,1i*2*pi*f.'))))) hold on semilogx(f,20*log10(abs(double(subs(eval(v4vin), s,1i*2*pi*f.'))))) semilogx(f,20*log10(abs(double(subs(eval(v5vin), s,1i*2*pi*f.'))))) semilogx(f,20*log10(abs(double(subs(eval(v6vin), s,1i*2*pi*f.'))))) figure subplot(2,1,1) semilogx(f,abs(double(subs(eval(1/i1v1),s,1i*2*pi*f.'))))

4.29

Low Pass Couplers

299

subplot(2,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(1/i1v1), s,1i*2*pi*f.'))))) figure subplot(2,1,1) semilogx(f,abs(double(subs(eval(1/i3v3),s,1i*2*pi*f.')))) subplot(2,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(1/i3v3), s,1i*2*pi*f.')))))

4.29

Low Pass Couplers

Couplers are used for measurement of high frequency signal powers or for connecting transceivers to antenna. The measured power of the coupled signal is multiplied by the coupling ratio in order to calculate the power of the main signal. This indirect measurement has benefits of isolating the main signal from the measurement unit. For continuous time transceivers that use FDMA (frequency division multiplexing access) or CDMA (code division multiplexing access), the outgoing signal from transmitter must appear at the antenna and should not interfere with the incoming signal from the antenna that must appear at the receiver. Realization of a coupler designed by two 1-segment lumped low-pass LC λ/4 transmission lines coupled together with two capacitors is shown in Fig. 4.85. The admittance matrix of the coupler is given by

Fig. 4.85 Low pass directional coupler

/4 transmission line 1

GS 2

L C 2

vS

3

C 2

Cc

GL Cc

L GL

5

C 2

C 2

/4 transmission line

4

GL

300

4 AC Analysis

Table 4.14 Component values of the low pass coupler Z0 1 50 A=V 2

GS 6 6 GS 6 6 6 6 Y¼6 0 6 6 6 0 6 4 0

GS A=V

GL A=V

1 50

1 50

GS 1 GS þ sðCc þ C Þ þ sL 1  sL

L Z0 4f 0

C ¼ 1:25 μH

1 4Z0 f 0

0 1  sL GL þ sðCc þ C Þ þ

0

sCc

sCc

0

1 sL

¼ 0:5 nH

Cc 0.1C ¼ 50 pH

f0 10MHz

3

0

0

0

sCc

sCc

0

1 1  GL þ sðCc þ C Þ þ sL sL 1 1  GL þ sðCc þ C Þ þ sL sL

7 7 7 7 7 7 7 7 7 7 7 5

ð4:268Þ The component values are listed in Table 4.14. The admittance at node 2 of the coupler after shorting the input (i ¼ 1 and o ¼ 2) is given by

ð4:269Þ

The S22 parameter of the coupler is shown in Fig. 4.86. The result shows that node 2 of the coupler is impedance matched to the input source at node 1 for signals operating at 10 MHz. The voltage-gain of the coupler at node 3 (i ¼ 1 and o ¼ 3) is obtained by

ð4:270Þ

The voltage-gain of the coupler from node 1 to node 3 is shown in Fig. 4.87. The result shows that at 10 MHz, the signal from node 1 reaches to node 3 with some minor attenuation. The admittance at node 3 of the coupler after shorting the input (i ¼ 1 and o ¼ 3) is given by

4.29

Low Pass Couplers

Fig. 4.86 S22 of the coupler

Fig. 4.87 Voltage-gain from node 3 to node 1

301

302

4 AC Analysis

Fig. 4.88 S33 of the coupler

xth column xth row

xth row

ð4:271Þ

th

o row xth column

oth column

The S33 parameter of the coupler is shown in Fig. 4.88. The result shows that load GL is impedance matched to the node 3 of the coupler. The voltage-gain of the coupler at node 4 (i ¼ 1 and o ¼ 4) is obtained by

ð4:272Þ

The voltage-gain of the coupler from node 1 to node 4 is shown in Fig. 4.89. The result shows that at 10 MHz, the signal from node 1 reaches to node 4 with some minor attenuation while lower frequency signals experience higher attenuation. The admittance at node 4 of the coupler after shorting the input (i ¼ 1 and o ¼ 4) is given by

4.29

Low Pass Couplers

303

Fig. 4.89 Voltage-gain from node 4 to node 1

ð4:273Þ

The S44 parameter of the coupler is shown in Fig. 4.90. The result shows that load GL is impedance matched to the node 4 of the coupler. The voltage-gain of the coupler at node 5 (i ¼ 1 and o ¼ 5) is obtained by

ð4:274Þ

The voltage-gain of the coupler from node 1 to node 5 is shown in Fig. 4.91. The result shows that at 10 MHz, the signal from node 1 reaches to node 5 with a

304 Fig. 4.90 S44 of the coupler

Fig. 4.91 Voltage-gain from node 5 to node 1

4 AC Analysis

4.29

Low Pass Couplers

305

Fig. 4.92 S55 of the coupler

considerable attenuation while lower frequency signals experience significantly higher attenuation. The admittance at node 5 of the coupler after shorting the input (i ¼ 1 and o ¼ 5) is given by

ð4:275Þ

The S55 parameter of the coupler is shown in Fig. 4.92. The result shows that load GL is impedance matched to the node 5 of the coupler. The following MATLAB code uses Cramer’s rules to calculate the voltage-gain and the S-parameters of the circuit in this example.

syms s Z0 L C Cc Y=[1/Z0 -1/Z0 0 0 0;... -1/Z0 1/Z0+s*(C/2+Cc)+1/(s*L) -1/(s*L) 0 -s*Cc;... 0 -1/(s*L) 1/Z0+s*(C/2+Cc)+1/(s*L) -s*Cc 0;...

306

4 AC Analysis

0 0 -s*Cc 1/Z0+s*(C/2+Cc)+1/(s*L) -1/(s*L);... 0 -s*Cc 0 -1/(s*L) 1/Z0+s*(C/2+Cc)+1/(s*L)]; i2v2=det(Y((1:end)~=1,(1:end)~=1))/det(Y((1:end)~=1 & (1:end)~=2, (1:end)~=1 & (1:end)~=2)); i3v3=det(Y((1:end)~=1,(1:end)~=1))/det(Y((1:end)~=1 & (1:end)~=3, (1:end)~=1 & (1:end)~=3)); i4v4=det(Y((1:end)~=1,(1:end)~=1))/det(Y((1:end)~=1 & (1:end)~=4, (1:end)~=1 & (1:end)~=4)); i5v5=det(Y((1:end)~=1,(1:end)~=1))/det(Y((1:end)~=1 & (1:end)~=5, (1:end)~=1 & (1:end)~=5)); v3v1=det(Y((1:end)~=1,(1:end)~=3))/det(Y((1:end)~=1,(1:end)~=1)); v4v1=det(Y((1:end)~=1,(1:end)~=4))/det(Y((1:end)~=1,(1:end)~=1)); v5v1=det(Y((1:end)~=1,(1:end)~=5))/det(Y((1:end)~=1,(1:end)~=1)); f=logspace(6,8,101); f0=1e7; Z0=50; kc=0.1; L=Z0/(4*f0); C=1/(Z0*4*f0); Cc=kc*C; figure subplot(3,1,1) semilogx(f,20*log10(abs(double(subs(eval(v3v1),s,1i*2*pi*f))).')) subplot(3,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(v3v1), s,1i*2*pi*f))).')) subplot(3,1,3) semilogx(f(2:end),-diff(unwrap(angle(double(subs(eval(v3v1), s,1i*2*pi*f))).'))./diff(2*pi*f.')) figure subplot(3,1,1) semilogx(f,20*log10(abs(double(subs(eval(v4v1),s,1i*2*pi*f))).')) subplot(3,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(v4v1), s,1i*2*pi*f))).')) subplot(3,1,3) semilogx(f(2:end),-diff(unwrap(angle(double(subs(eval(v4v1), s,1i*2*pi*f))).'))./diff(2*pi*f.')) figure subplot(3,1,1) semilogx(f,20*log10(abs(double(subs(eval(v5v1),s,1i*2*pi*f))).')) subplot(3,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(eval(v5v1), s,1i*2*pi*f))).')) subplot(3,1,3)

4.30

Substrate Capacitors

307

semilogx(f(2:end),-diff(unwrap(angle(double(subs(eval(v5v1), s,1i*2*pi*f))).'))./diff(2*pi*f.')) figure subplot(2,1,1) semilogx(f,20*log10(abs(double(subs(((eval(1/i2v2)-Z0)./(eval (1/i2v2)+Z0)),s,1i*2*pi*f))).')) subplot(2,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(((eval(1/i2v2)-Z0)./ (eval(1/i2v2)+Z0)),s,1i*2*pi*f))).')) figure subplot(2,1,1) semilogx(f,20*log10(abs(double(subs(((eval(1/i3v3)-Z0)./(eval (1/i3v3)+Z0)),s,1i*2*pi*f))).')) subplot(2,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(((eval(1/i3v3)-Z0)./ (eval(1/i3v3)+Z0)),s,1i*2*pi*f))).')) figure subplot(2,1,1) semilogx(f,20*log10(abs(double(subs(((eval(1/i4v4)-Z0)./(eval (1/i4v4)+Z0)),s,1i*2*pi*f))).')) subplot(2,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(((eval(1/i4v4)-Z0)./ (eval(1/i4v4)+Z0)),s,1i*2*pi*f))).')) figure subplot(2,1,1) semilogx(f,20*log10(abs(double(subs(((eval(1/i5v5)-Z0)./(eval (1/i5v5)+Z0)),s,1i*2*pi*f))).')) subplot(2,1,2) semilogx(f,(180/pi)*unwrap(angle(double(subs(((eval(1/i5v5)-Z0)./ (eval(1/i5v5)+Z0)),s,1i*2*pi*f))).'))

4.30

Substrate Capacitors

The structure of a capacitor realized over a Silicon substrate is shown in Fig. 4.93. The model of the capacitor is shown in Fig. 4.94. Capacitor plates have square shapes with the side lengths of l ¼ 100 μm. The capacitance is calculated by C ¼ ε0 εox

l2 ¼ 74:37 fF d

ð4:276Þ

where d ¼ 5μm is the distance between the capacitor plates, ε0 ¼ 8.854  1012 F/m is the permittivity of the air and εox ¼ 4.2 is the relative permittivity of the Silicon

308 Fig. 4.93 Cross section of substrate capacitor

4 AC Analysis

top plate bottom plate

insulator silicon dioxide

silicon

ground plane Fig. 4.94 Model of the substrate capacitor

C

1

3

Cox 2 Gsi

Csi

dioxide between the capacitor plates. The oxide under the capacitor has a height of tox ¼ 50μm. The oxide capacitance under the capacitor is calculated by C ox ¼ ε0 εox

l2 ¼ 7:437 fF t ox

ð4:277Þ

The Silicon has a height of tsi ¼ 300μm and a relative permittivity of εsi ¼ 11.7 and a resistivity of ρsi ¼ 0.1 (Ω. m). The Silicon capacitance under the capacitor is calculated by C si ¼ ε0 εsi

l2 ¼ 3:45 fF t si

and the Silicon conductance Gsi under the capacitor is calculated by

ð4:278Þ

4.30

Substrate Capacitors

309

Gsi ¼

l2

ρcopper  t si

¼ 333:3μ A=V

ð4:279Þ

The admittance matrix of the capacitor realized over a Silicon substrate is given by 2

sC 6 Y¼4 0 sC

0 Gsi þ sðCox þ Csi Þ

sC sCox

sCox

sðCox þ CÞ

3 7 5

ð4:280Þ

Using node elimination, the capacitor model is converted to a two-port admittance network. From the two-port admittance network, the Y-parameters of the network are plotted, as shown in Fig. 4.95.

Fig. 4.95 Y-parameters of the substrate capacitor

310

4 AC Analysis

Fig. 4.96 S-parameters of the substrate capacitor

The two-port S-parameters are obtained from Y-parameters, as shown in Fig. 4.96. The differential admittance between terminals 1 and 3 are calculated from Y-parameters. The real part of the differential admittance is equal to the conductance, as shown in Fig. 4.97. The imaginary part of the differential admittance is equal to the capacitance, as shown in Fig. 4.98. The quality factor of the capacitor is the ratio between the imaginary and the real parts of the differential admittance between nodes 1 and 3 and is shown in Fig. 4.99. The quality factor of the capacitors realized over a Silicon substrate is very high and close to ideal. The following MATLAB code eliminates the internal nodes of the integrated capacitor model studied in this example and then calculates the Y-, Z-, and S-

4.30

Substrate Capacitors

Fig. 4.97 Conductance between terminals 1 and 3

Fig. 4.98 Capacitance between terminals 1 and 3

Fig. 4.99 Quality factor of the substrate capacitor

311

312

4 AC Analysis

parameters. It finally extracts the capacitance and the quality factor from the Y-parameters.

syms C Cox Gsi Csi syms s syms Z0 Y=[s*C 0 -s*C;... 0 Gsi+s*(Csi+Cox) -s*Cox;... -s*C -s*Cox s*(C+Cox)]; in=1; out=3; A=Y; A([2,out],:)=A([out,2],:); A(:,[2,out])=A(:,[out,2]); A([1,in],:)=A([in,1],:); A(:,[1,in])=A(:,[in,1]); [ma,na]=size(A); for kk=1:ma-2 for km=1:ma-1 for kn=1:na-1 A(km,kn)=A(km,kn)-(A(ma,kn)*A(km,na))/A(ma,na); end end ma=ma-1; na=na-1; end Y11=A(1,1); Y12=A(1,2); Y21=A(2,1); Y22=A(2,2); Ydif=(Y11*Y22-Y12*Y21)/(Y11+Y12+Y21+Y22); deltaZ=Y11.*Y22-Y12.*Y21; Z11=Y22./deltaZ; Z12=-Y12./deltaZ; Z21=-Y21./deltaZ; Z22=Y11./deltaZ; Zdif=Z11+Z22-Z12-Z21; deltaS=(1+Z0*Y11).*(1+Z0*Y22)-Z0^2*Y12.*Y21; S11=((1-Z0*Y11).*(1+Z0*Y22)+Z0^2*Y12.*Y21)./deltaS; S12=-2*Z0*Y12./deltaS; S21=-2*Z0*Y21./deltaS; S22=((1+Z0*Y11).*(1-Z0*Y22)+Z0^2*Y12.*Y21)./deltaS;

4.30

Substrate Capacitors

313

H=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1:end) ~=in,(1:end)~=in)); disp(['vo/vi = ',char(H)]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['Yin = ',char(Yin)]) Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp(['Yout = ',char(Yout)]) f0=1e06; e0=8.854e-12; esi=11.7; eox=4.2; rosi=1e-01; tsi=300e-06; tox=50e-06; d=5e-06; l=100e-06; Z0=50; C=eox*e0*l*l/d; Cox=eox*e0*l*l/tox; Gsi=l*l/(rosi*tsi); Csi=esi*e0*l*l/tsi; disp(['Ydif = ',char(Ydif)]) disp(['C = ',num2str(C)]) disp(['Cox = ',num2str(Cox)]) disp(['Gsi = ',num2str(Gsi)]) disp(['Csi = ',num2str(Csi)]) [num,den]=numden(eval(H)); cnum=sym2poly(num); cden=sym2poly(den); [p,z]=pzmap(tf(cnum,cden)); disp(['poles = ',num2str(p.','%5.3e ')]) disp(['zeros = ',num2str(z.','%5.3e ')]) f=logspace(8,12,100); Y11=double(subs(eval(Y11),s,1i*2*pi*f)); Y12=double(subs(eval(Y12),s,1i*2*pi*f)); Y21=double(subs(eval(Y21),s,1i*2*pi*f)); Y22=double(subs(eval(Y22),s,1i*2*pi*f)); Z11=double(subs(eval(Z11),s,1i*2*pi*f)); Z12=double(subs(eval(Z12),s,1i*2*pi*f)); Z21=double(subs(eval(Z21),s,1i*2*pi*f)); Z22=double(subs(eval(Z22),s,1i*2*pi*f)); S11=double(subs(eval(S11),s,1i*2*pi*f)); S12=double(subs(eval(S12),s,1i*2*pi*f)); S21=double(subs(eval(S21),s,1i*2*pi*f)); S22=double(subs(eval(S22),s,1i*2*pi*f));

314

4 AC Analysis

Yd=double(subs(eval(Ydif),s,1i*2*pi*f)); Yr=real(Yd); Yi=imag(Yd); Q=Yi./Yr; figure loglog(f,Yr); figure loglog(f,Yi./(2*pi*f)); figure loglog(f,Yi./Yr);

4.31

Substrate Inductors

The structure of an inductor realized over a Silicon substrate is shown in Fig. 4.100. The model of the inductor is shown in Fig. 4.101. Inductor is realized with a copper metal with a resistivity of ρcopper ¼ 1.68e  08 (Ω. m). The metal has a width of W ¼ 1 μm and a thickness of t ¼ 1 μm. Inductor has a shape of square with the side lengths of l ¼ 100 μm. The inductance L is approximately calculated by

Fig. 4.100 Cross section of substrate inductor

silicon dioxide

silicon

ground plane

4.31

Substrate Inductors

315

Fig. 4.101 Model of the substrate inductor

C G

1 Cox 2 Gsi 2

L ¼ μ0 μr

4

Cox 2

2 Csi 2

Nl2 ¼ 25:13 nH W

L

Gsi 2

5

3 Csi 2

ð4:281Þ

where is N ¼ 2 the number of turns, μ0 ¼ 4π  107H/m is the permeability of the air, and μr ¼ 1 is the relative permeability of the Silicon dioxide. The conductance G is calculated by G¼

Wt ¼ 74:4m A=V ρcopper  4Nl

ð4:282Þ

and the capacitance between inductor turns are calculated by C ¼ ε0 εox

4Nlt ¼ 29:75 fF d

ð4:283Þ

where d ¼ 1μm is the distance between the inductor windings, ε0 ¼ 8.854  1012 F/m is the permittivity of the air, and εox ¼ 4.2 is the relative permittivity of the Silicon dioxide. The oxide under the inductor has a height of tox ¼ 50μm. The oxide capacitance under the inductor is calculated by C ox ¼ ε0 εox

l2 ¼ 7:437 fF t ox

ð4:284Þ

The Silicon has a height of tsi ¼ 300μm and a relative permittivity of εsi ¼ 11.7 and a resistivity of ρsi ¼ 0.1 (Ω. m). The Silicon capacitance under the inductor is calculated by C si ¼ ε0 εsi

l2 ¼ 3:45 fF t si

ð4:285Þ

316

4 AC Analysis

and the Silicon conductance Gsi under the inductor is calculated by Gsi ¼

l2

ρcopper  t si

¼ 333:3μ A=V

ð4:286Þ

The oxide capacitance, the Silicon conductance, and the Silicon capacitance under the inductor are divided equally between the input and output terminals of the inductor. The admittance matrix of the inductor realized over a Silicon substrate is given by 2

 Cox 6G þ s 2 þ C 6 6 sC 6  ox 6 2 6 6 Y¼6 0 6 6 6 G 6 6 4 sC

sC  ox 2  Gsi Cox Csi þs þ 2 2 2 0

3 0

G

0  Gsi C C þ s ox þ si 2 2 2

0

0 0

0 

sCox 2

0 1 sL 1  sL

Gþ

sC

7 7 7 7 0 7 7 7 sCox 7  7 2 7 1 7  7 sL 7  Cox 1 5 þC þ s 2 sL

ð4:287Þ Using node elimination, the inductor model is converted to a two-port admittance network. From the two-port admittance network, the Z-parameters of the network are plotted, as shown in Fig. 4.102. The two-port S-parameters are obtained from Z-parameters, as shown in Fig. 4.103. The inductor characteristics are calculated by the differential impedance between nodes 1 and 5. The resistance of the inductor is shown in Fig. 4.104. At resonance frequency, the inductor behavior changes to a capacitor and the resistance of the inductor reaches its maximum peak. The inductance variation is shown in Fig. 4.105. After the resonance frequency, inductor value becomes negative representing capacitive behavior. The quality factor of the inductor is the ratio between the imaginary and the real parts of the differential impedance between terminals 1 and 5 and is shown in Fig. 4.106. The quality factor of the components used to build electronic circuits is finite impacting the performance of the circuits such as filters. The following MATLAB code eliminates the internal nodes of the integrated inductor model studied in this example and then calculates the Y-, Z-, and S-parameters. It finally extracts the inductance and the quality factor from the Z-parameters.

4.31

Substrate Inductors

Fig. 4.102 Z-parameters of the substrate inductor

syms G L C Cox Gsi Csi syms s syms Z0 Y=[G+s*(C+0.5*Cox) -0.5*s*Cox 0 -G -s*C;... -0.5*s*Cox 0.5*Gsi+0.5*s*(Csi+Cox) 0 0 0;... 0 0 0.5*Gsi+0.5*s*(Csi+Cox) 0 -0.5*s*Cox;... -G 0 0 G+1/(s*L) -1/(s*L);... -s*C 0 -0.5*s*Cox -1/(s*L) 1/(s*L)+s*(C+0.5*Cox)]; in=1; out=5;

317

318

Fig. 4.103 S-parameters of the substrate inductor A=Y; A([2,out],:)=A([out,2],:); A(:,[2,out])=A(:,[out,2]); A([1,in],:)=A([in,1],:); A(:,[1,in])=A(:,[in,1]); [ma,na]=size(A); for kk=1:ma-2 for km=1:ma-1 for kn=1:na-1 A(km,kn)=A(km,kn)-(A(ma,kn)*A(km,na))/A(ma,na); end end ma=ma-1; na=na-1; end

4 AC Analysis

4.31

Substrate Inductors

Fig. 4.104 Resistance between terminals 1 and 5

Fig. 4.105 Inductance between terminals 1 and 5

Fig. 4.106 Quality factor of the substrate inductor

319

320

4 AC Analysis

Y11=A(1,1); Y12=A(1,2); Y21=A(2,1); Y22=A(2,2); Ydif=(Y11*Y22-Y12*Y21)/(Y11+Y12+Y21+Y22); deltaZ=Y11.*Y22-Y12.*Y21; Z11=Y22./deltaZ; Z12=-Y12./deltaZ; Z21=-Y21./deltaZ; Z22=Y11./deltaZ; Zdif=Z11+Z22-Z12-Z21; deltaS=(1+Z0*Y11).*(1+Z0*Y22)-Z0^2*Y12.*Y21; S11=((1-Z0*Y11).*(1+Z0*Y22)+Z0^2*Y12.*Y21)./deltaS; S12=-2*Z0*Y12./deltaS; S21=-2*Z0*Y21./deltaS; S22=((1+Z0*Y11).*(1-Z0*Y22)+Z0^2*Y12.*Y21)./deltaS; H=((-1)^(in+out))*det(Y((1:end)~=in,(1:end)~=out))/det(Y((1:end) ~=in,(1:end)~=in)); disp(['vo/vi = ',char(H)]) Yin=det(Y)/det(Y((1:end)~=in,(1:end)~=in)); disp(['Yin = ',char(Yin)]) Yout=det(Y((1:end)~=in,(1:end)~=in))/det(Y((1:end)~=in & (1:end) ~=out,(1:end)~=in & (1:end)~=out)); disp(['Yout = ',char(Yout)]) f0=1e06; u0=1; ur=4*pi*1e-07; e0=8.854e-12; esi=11.7; eox=4.2; rosi=1e-01; rocu=1.68e-08; tsi=300e-06; tox=50e-06; w=1e-06; t=1e-06; d=1e-06; l=100e-06; N=2; Z0=50; G=w*t/(rocu*N*4*l); L=N*u0*ur*l*l/w; C=N*eox*e0*4*l*t/d; Cox=eox*e0*l*l/tox; Gsi=l*l/(rosi*tsi); Csi=esi*e0*l*l/tsi;

4.31

Substrate Inductors

disp(['Zdif = ',char(Zdif)]) disp(['G = ',num2str(G)]) disp(['C = ',num2str(C)]) disp(['L = ',num2str(L)]) disp(['Cox = ',num2str(Cox)]) disp(['Gsi = ',num2str(Gsi)]) disp(['Csi = ',num2str(Csi)]) [num,den]=numden(eval(H)); cnum=sym2poly(num); cden=sym2poly(den); [p,z]=pzmap(tf(cnum,cden)); disp(['poles = ',num2str(p.','%5.3e ')]) disp(['zeros = ',num2str(z.','%5.3e ')]) f=logspace(8,11,1000); Y11=double(subs(eval(Y11),s,1i*2*pi*f)); Y12=double(subs(eval(Y12),s,1i*2*pi*f)); Y21=double(subs(eval(Y21),s,1i*2*pi*f)); Y22=double(subs(eval(Y22),s,1i*2*pi*f)); Z11=double(subs(eval(Z11),s,1i*2*pi*f)); Z12=double(subs(eval(Z12),s,1i*2*pi*f)); Z21=double(subs(eval(Z21),s,1i*2*pi*f)); Z22=double(subs(eval(Z22),s,1i*2*pi*f)); S11=double(subs(eval(S11),s,1i*2*pi*f)); S12=double(subs(eval(S12),s,1i*2*pi*f)); S21=double(subs(eval(S21),s,1i*2*pi*f)); S22=double(subs(eval(S22),s,1i*2*pi*f)); Zd=double(subs(eval(Zdif),s,1i*2*pi*f)); Zr=real(Zd); Zi=imag(Zd); L=Zi./(2*pi*f); Q=Zi./Zr; L(L : G þ v þ Gþ þ jωC v2  ing þ inL ¼ i2 jωL 1 jωL 8 > > >
< > :



YL

i1

G

i2

v1

LC gmv1

v2

 1 v  ðG þ jωC Þv2  ing ¼ i1 G þ jωC þ jωL 1

ð5:128Þ

ðgm þ G þ jωC Þv1 þ ðG þ jωCÞv2  ing þ inL ¼ i2

These systems of equations are converted to general admittance and noise matrices given by

374

5

2

3   1 1 v G  jωC G þ jωC þ 4 5 1 þ jωL 1 v2 gm  G  jωC G þ jωC   i1 in1 ¼ þ i2 in2

0 1



ing

Noise Analysis



inL ð5:129Þ

The noise current at the input of the two-port circuit is given by  2 jin1 j2 ¼ ing 

ð5:130Þ

The noise current at the output of the two-port circuit for uncorrelated noises is given by  2 jin2 j2 ¼ ing  þ jinL j2

ð5:131Þ

 2   ing  ¼ 4KTG A2=Hz

ð5:132Þ

where

and jinL j2 ¼ 4KT  realfY L g



A2=Hz



ð5:133Þ

Circuit parameters are listed in Table 5.3. The input referred noise current spectral density |in1| is shown in Fig. 5.42. The transient noise current at input of the two-port circuit is calculated by vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uZ1 u u iniðt Þ ¼ randn t jin1 j2 df

ð5:134Þ

0

The transient noise current at input of the two-port circuit has a variance of 1.6394  1013 (A) and is plotted in Fig. 5.43. The input referred noise voltage spectral density |vn1|2 is shown in Fig. 5.44. The transient noise voltage at input of the two-port circuit is calculated by

YS ¼ 2e  02 [A/V]

G ¼ 1e  03 [A/V]

Table 5.3 Circuit parameters in Example 3 L ¼ 1 nH

C ¼ 10 pF

ω ¼ 2π  5e9 [ras/s]

gm ¼ 1e  03 [A/V]

5.12 Noise Factor and Maximum Power Trade-Offs 375

376

5

Noise Analysis

Fig. 5.42 Input referred noise current spectral density

Fig. 5.43 Transient noise current at input of the two-port circuit

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uZ1 u u vniðt Þ ¼ randn t jvn1 j2 df

ð5:135Þ

0

The transient noise voltage at input of the two-port circuit has a variance varying from 2.2902  1010 (V ) to 1.6271  1009 (V ) and is plotted in Fig. 5.45. The admittance at the input of the two-port circuit is obtained by 4.94. The maximum power is delivered from source to circuit when Yin ¼ YS , real{Yin} ¼ YS and imag{Yin} is either canceled by adding a shunt capacitor or inductor or is zero

5.12

Noise Factor and Maximum Power Trade-Offs

377

Fig. 5.44 Input referred noise voltage spectral density

Fig. 5.45 Transient noise voltage at input of the two-port circuit

and negligible. When Yin ¼ YS, maximum power is delivered to the load, as shown in Fig. 5.46. The noise factor variation with respect to load variations is shown in Fig. 5.47. The optimum conditions that maximize the input power while minimizing the noise factor occur under different load admittances. At conditions when noise factor becomes minimum, the delivered power is not maximum and a circuit design must consider this trade-off. This is the general case for Electronic circuits with more than

378

5

Noise Analysis

Fig. 5.46 Power and noise factor characteristics

Fig. 5.47 Noise factor characteristics versus load variations

one port and the best design approach is to select a load admittance which is the geometric mean of the two load admittances that yield the maximum power and the minimum noise factor. The following MATLAB code converts the 3-node circuit studied in this example to two nodes and obtains the two input and output current noise sources of the circuit. Next, it calculates the Y-parameters of the circuit and obtains the maximum normalized delivered power and the total input referred noise and the noise factor of the circuit.

5.12

Noise Factor and Maximum Power Trade-Offs

syms s syms G C L gm syms YL YS syms v1 v2 v3 syms i1 i2 i3 syms ins inG inl Vvec=[v1 v2 v3]; Nvec=inG; equ=[i1==YS*(v1-v2)+ins; i2==YS*(v2-v1)-ins+(1/(s*L))*v2+(G+s*C)*(v2-v3)+inG;... i3==(G+s*C)*(v3-v2)-inG+gm*v1+YL*v3+inl]; [Nmat,b]=equationsToMatrix(equ,Nvec); [Ymat,a]=equationsToMatrix(b,Vvec); YP=subs(Ymat((1:end)~=1,(1:end)~=1),[YS,YL],[0,0]); NP=-Nmat((1:end)~=1,:); A=YP; in=1; out=2; A([2,out],:)=A([out,2],:); A(:,[2,out])=A(:,[out,2]); A([1,in],:)=A([in,1],:); A(:,[1,in])=A(:,[in,1]); B=NP; B([2,out],:)=B([out,2],:); B([1,in],:)=B([in,1],:); [ma,na]=size(A); [mb,nb]=size(B); for kk=1:ma-2 for km=1:ma-1 for kn=1:nb B(km,kn)=B(km,kn)-(B(ma,kn)*A(km,na))/A(ma,na); end for kn=1:na-1 A(km,kn)=A(km,kn)-(A(ma,kn)*A(km,na))/A(ma,na); end end ma=ma-1; na=na-1; end IN1=sum(abs(B(1,:)).^2.*Nvec); IN2=sum(abs(B(2,:)).^2.*Nvec)+inl; Y11=A(1,1); Y12=A(1,2); Y21=A(2,1); Y22=A(2,2);

379

380

5

Noise Analysis

disp('KCL equations :') disp(equ) disp('two-port Y-parameters :') disp(A(1:2,1:2)) disp('two-port noise matrix :') disp(B(1:2,:)) disp('noise equations :') disp([['ini = ';'ino = '],char(string([IN1;IN2]))]) fprintf('\n') f1=1e08; f2=1e10; f0=1.6e09; np=4; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; f=logspace(log10(f1),log10(f2),100*(log10(f2)-log10(f1))+1); G=1e-03; L=1e-09; C=10e-12; gm=1e-03; s=1i*2*pi*f; K=1.38e-23; T=300; Z0=1; YL=logspace(log10(0.1/Z0),log10(10/Z0),11).'; YS=(1/50).*ones(size(YL)); inG=4*K*T*G; ins=4*K*T*real(YS); inl=4*K*T*real(YL); vns=4*K*T./real(YS); vnl=4*K*T./real(YL); Yin=Y11-Y12.*Y21./(Y22+YL); NPower=2*YS.*real(Yin)./(abs(YS+Yin)).^2; inti=abs(eval(IN1)-eval(IN2).*abs(eval(Y12./(Y22+YL))).^2); vnti=inti./abs(eval(Yin)).^2; ini=eval(IN1); vni=eval(IN2).*abs(eval(Y12./(Y11.*(Y22+YL)-Y12.*Y21))).^2; vnivar=sum(vni.*repmat([0,diff(f)],size(YL)),2); inivar=sum(ini.*repmat([0,diff(f)],size(YL)),2); vnsvar=sum(vns.*repmat([0,diff(f)],size(YL)),2); insvar=sum(ins.*repmat([0,diff(f)],size(YL)),2); NF=1+(vnivar+inivar./real(YS).^2)./vnsvar;

5.13

Conclusions

381

vnit=sqrt(vnivar).*randn(1,length(time)); init=sqrt(inivar).*randn(1,length(time)); loglog(f,sqrt(vni)) loglog(f,sqrt(ini)) plot(time,vnit) plot(time,init) semilogy(1./YL,NF) mesh(f,1./YL,eval(NPower)*100)

5.13

Conclusions

Signals with small amplitudes and power levels get buried into noise and are lost. The noise analysis determines the maximum noise signals in form of currents and voltages that are generated by circuits. The noise of components is modeled spectrally in s-domain and small-signal circuit models are used because of the very small noise signal levels. The noise matrix of the circuits is obtained using matrix calculations and the input and output noise currents are calculated. The total input referred voltage and current noise signals are calculated using transformations that were studied in this Chapter. Finally, the noise factor of the circuits is calculated in order to characterize the minimum signal levels required to keep circuits functional. The overview of the topics studied in this chapter is illustrated in Fig. 5.48.

Fig. 5.48 An overview of this chapter topics

Linearized s‐domain Model

Noise Matrix Calculations

Noise Transformation

Results

382

5

Noise Analysis

Questions Answer the following questions using materials and codes you have learned in this chapter.

Q.5.1 Create the small-signal AC model of the following circuit and write a code to calculate the noise at the input of the amplifier (Fig. 5.49). Answers: See Fig. 5.50. Y a ¼ G1 þ G2 þ jωCgs1 Y b ¼ jωC gd1

Fig. 5.49 Circuit of Question 1

Vdd

R1

RD Vout

C∞ Q1

r Vin R2 Vgg

(1)

vin

g

Yb

(2)

Ya

vgs1

Fig. 5.50 Small-signal AC model of Question 1

(3)

gm1vgs1

Yc

vout

Questions

383

Y c ¼ gds1 þ GD þ jωCdb1 Assuming every resistor has a parallel noise source: in1 ¼ inG1 + inG2 + ing + (inGD*(Yb - gm))/(Ya + Yb + g) + (inds*(Yb - gm))/ (Ya + Yb + g)

Q.5.2 Create the small-signal AC model of the following circuit and write a code to calculate the noise at the input of the amplifier (Fig. 5.51). Answers: See Fig. 5.52. Y a ¼ G2 þ jωC gs1 Y b ¼ G1 þ jωCgd1

Fig. 5.51 Circuit of Question 2

Vdd

R1

RD

Vout

C∞ Q1

r Vin R2 Vgg

(1)

vin

g

Yb

(2)

Ya

vgs1

Fig. 5.52 Small-signal AC model of Question 2

(3)

gm1vgs1

Yc

vout

384

5

Noise Analysis

Y c ¼ gds1 þ GD þ jωCdb1 Assuming every resistor has a parallel noise source: in1 ¼ inG2 + ing + inG1*((Yb - gm)/(Ya + Yb + g) + 1) + (inGD*(Yb - gm))/ (Ya + Yb + g) + (inds*(Yb - gm))/(Ya + Yb + g)

Q.5.3 Create the small-signal AC model of the following circuit and write a code to calculate the noise at the input of the amplifier (Fig. 5.53). Answers: See Fig. 5.54. Y a ¼ G1 þ G2 þ jωC gd1 Y b ¼ jωC gs1 Y c ¼ gds1 þ GS þ jωC sb1 Assuming every resistor has a parallel noise source: Fig. 5.53 Circuit of Question 3

Vdd

R1 C∞ Q1 Vout

r Vin R2

RS

Vgg

(1)

vin

g

(2)

Ya

Yb

vgs1 g v m1 gs1

Fig. 5.54 Small-signal AC model of Question 3

(3)

gb1vbs1

Yc

vout

Questions

385

in1 ¼ inG1 + inG2 + ing + (inGS*(Yb + gm))/(Ya + Yb + g) + (inds*(Yb + gm))/ (Ya + Yb + g)

Q.5.4 Create the small-signal AC model of the following circuit and write a code to calculate the noise at the input of the amplifier (Fig. 5.55). Answers: See Fig. 5.56.   Y a ¼ GS þ jω C gs1 þ C sb1

Fig. 5.55 Circuit of Question 4

Vdd

RD

R1

Vout C∞ Q1 C∞

R2

r RS Vin Vgg

gb1vbs1

Fig. 5.56 Small-signal AC model of Question 4

gm1vgs1 (1)

vin

g

Yb

(2)

Ya

vgs1

(3)

Yc

vout

386

5

Noise Analysis

Y b ¼ gds1   Y c ¼ GD þ jω C gd1 þ C db1 Assuming every resistor has a parallel noise source: in1 ¼ inGS + ing + inds*((Yb + gb + gm)/(Ya + Yb + gb + gm + g) + 1) + (inGD* (Yb + gb + gm))/(Ya + Yb + gb + gm + g)

Q.5.5 Create the small-signal AC model of the following circuit and write a code to calculate the noise at the input of the amplifier (Fig. 5.57). Answers: See Fig. 5.58.   Y a ¼ GS þ jω C gs1 þ C sb1 Y b ¼ gds1   Y c ¼ GD þ G1 þ jω Cgd1 þ C db1 Assuming every resistor has a parallel noise source:

Fig. 5.57 Circuit of Question 5

Vdd

RD R1

Vout

C∞ Q1 C∞

R2

r RS Vin Vgg

Questions

387

gb1vbs1

Fig. 5.58 Small-signal AC model of Question 5

gm1vgs1 (1)

vin

g

Yb

(2)

Ya

Fig. 5.59 Circuit of Question 6

vgs1

Vdd

(3)

Yc

R1

vout

RD Vout

C∞

Q1

r Vin R2

RS

Vgg

in1 ¼ inGS + ing + inds*((Yb + gb + gm)/(Ya + Yb + gb + gm + g) + 1) + (inG1* (Yb + gb + gm))/(Ya + Yb + gb + gm + g) + (inGD*(Yb + gb + gm))/(Ya + Yb + gb + gm + g)

Q.5.6 Create the small-signal AC model of the following circuit and write a code to calculate the noise at the input of the amplifier (Fig. 5.59). Answers: See Fig. 5.60. Y a ¼ G1 þ G2

388

5

Noise Analysis

Yf gb1vbs1 gm1vgs1 (1)

vin

g

(2)

Ya

Yb

(3)

vgs1

Yc

Yd

(4)

Ye

vout

Fig. 5.60 Small-signal AC model of Question 6

Y b ¼ jωC gs1 Y c ¼ GS þ jωCsb1 Y d ¼ gds1 Y e ¼ GD þ jωC db1

Y f ¼ jωCgd1 Assuming every resistor has a parallel noise source: in1 ¼ inG1 + inG2 + ing + inds*((Yf - gm)/(Ya + Yb + Yf + g) + (((Yb + gm)/ (Ya + Yb + Yf + g) + 1)*(Yd + gb + gm + (Yb*(Yf - gm))/(Ya + Yb + Yf + g)))/ (Yb + Yc + Yd + gb + gm - (Yb*(Yb + gm))/(Ya + Yb + Yf + g))) + inGD*((Yf gm)/(Ya + Yb + Yf + g) + ((Yb + gm)*(Yd + gb + gm + (Yb*(Yf - gm))/(Ya + Yb + Yf + g)))/((Ya + Yb + Yf + g)*(Yb + Yc + Yd + gb + gm - (Yb*(Yb + gm))/(Ya + Yb + Yf + g)))) + (inGS*(Yd + gb + gm + (Yb*(Yf - gm))/(Ya + Yb + Yf + g)))/(Yb + Yc + Yd + gb + gm - (Yb*(Yb + gm))/(Ya + Yb + Yf + g))

Questions

389

Fig. 5.61 Circuit of Question 7

Vdd

R1

RD Vout

C∞

Q1

r Vin R2

RS

Vgg

Yf gb1vbs1 gm1vgs1 (1)

vin

g

(2)

Ya

Yb

(3)

vgs1

Yc

Yd

(4)

Ye

vout

Fig. 5.62 Small-signal AC model of Question 7

Q.5.7 Create the small-signal AC model of the following circuit and write a code to calculate the noise at the input of the amplifier (Fig. 5.61). Answers: See Fig. 5.62. Y a ¼ G2 Y b ¼ jωC gs1

390

5

Noise Analysis

Y c ¼ GS þ jωCsb1 Y d ¼ gds1 Y e ¼ GD þ jωC db1 Y f ¼ G1 þ jωC gd1 Assuming every resistor has a parallel noise source: in1 ¼ inG2 + ing + inds*((Yf - gm)/(Ya + Yb + Yf + g) + (((Yb + gm)/(Ya + Yb + Yf + g) + 1)*(Yd + gb + gm + (Yb*(Yf - gm))/(Ya + Yb + Yf + g)))/(Yb + Yc + Yd + gb + gm - (Yb*(Yb + gm))/(Ya + Yb + Yf + g))) + inG1*((Yf - gm)/(Ya + Yb + Yf + g) + ((Yb + gm)*(Yd + gb + gm + (Yb*(Yf - gm))/(Ya + Yb + Yf + g)))/((Ya + Yb + Yf + g)*(Yb + Yc + Yd + gb + gm - (Yb*(Yb + gm))/(Ya + Yb + Yf + g))) + 1) + inGD*((Yf - gm)/(Ya + Yb + Yf + g) + ((Yb + gm)*(Yd + gb + gm + (Yb*(Yf gm))/(Ya + Yb + Yf + g)))/((Ya + Yb + Yf + g)*(Yb + Yc + Yd + gb + gm - (Yb* (Yb + gm))/(Ya + Yb + Yf + g)))) + (inGS*(Yd + gb + gm + (Yb*(Yf - gm))/(Ya + Yb + Yf + g)))/(Yb + Yc + Yd + gb + gm - (Yb*(Yb + gm))/(Ya + Yb + Yf + g))

Chapter 6

Behavioral Analysis

For time-domain transient analysis, circuits can be analyzed using three different methods. In the first method, circuits are solved using Laplace transformation that provides full accuracy. Circuits must be linear and time-invariant in order to be analyzed using Laplace transformation. In the second method, circuits are solved using discretized differential equations. All circuits including the nonlinear and the time-varying circuits can be solved using discretized differential equations. The analysis accuracy increases by using smaller time steps and using higher order Taylor expansion series in models and equations. As the number of nodes increases, computers require more memory and processing speeds in order to generate accurate transient simulation results. To overcome these limitations, the third method of the transient simulation, called the behavioral analysis, is developed. In the behavioral analysis, a circuit operation must be known and is modeled using high-level mathematical expressions rather than solving the low-level systems of equations formed by the Ohm’s and Kirchhoff’s laws. An Overview of this chapter topics is listed in the following Table.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 S. Hamedi-Hagh, Computational Electronic Circuits, https://doi.org/10.1007/978-3-030-75568-3_6

391

392

6 Behavioral Analysis

Schematic Composing

Signals Ch. 1 Framework Components

Ch. 2

Ch. 3

DC Analysis

Transient Analysis

DC, Transient, AC and Noise modeling

DC Circuit Model

Linear Equations

Direct Methods

Nonlinear Equations

Iterative Methods

Linear Circuits

Aperiodic and Periodic Signals

Laplace Transform

Nonlinear Circuits

Switching Circuits

Differential Equations

Ch. 4

AC Analysis

Linearized s‐domain Model

Matrix Calculations

Ch. 5

Noise Analysis

Linearized s‐domain Model

Noise Matrix Calculations

Ch. 6

Behavioral Analysis

6.1

Netlisting

Block‐Level Modeling

Transfer Function Characteristics

Noise Transformation

Accuracy and Speed Tradeoff

Block-Level Modeling

As an example, a variety of behavioral models can be created for the full-wave rectifier circuit, shown in Fig. 6.1. The full-wave rectifier circuit can be analyzed when the system of equations formed by four KCL equations at diode terminals is solved at different time step. This method represents the low-level modeling and the time required to analyze the circuit for 4 periods of a 1KHz sinusoidal with a peak voltage of 5 V and 101 time steps in each period is in the range of hundreds of milliseconds. Studying the full-wave rectifier circuit shows that only two diodes are ON in each period of the input signal. Converting the differential input and output signals to single-ended signals and keeping one of these two ON diodes for simulations will reduce the number of equations to one. This method represents the mid-level modeling and the time required to analyze the circuit for the same input explained earlier using the same computer is in the range of tens of milliseconds. The full-wave rectifier circuit generates an output that is mathematically equivalent to the absolute function of the input signal. Using this simple equation to represent the low-level modeling of the circuit reduces the simulation time to fractions of prior methods.

6.1 Block-Level Modeling

393

Fig. 6.1 A full-wave rectifier

Iin

1 D4 4

Vin

D1 2

D3 3

D2 R1

Vout Iout

low-level

mid-level

high-level

Fig. 6.2 Different levels of circuit modeling Vout(x)=

0 ;abs(x)=2*VON KCL=v-(abs(vi(k))-2*VON); else KCL=v; end end

The following MATLAB code analyzes the full-wave rectifier using the highlevel modeling.

f0=1e03; np=4; nt=101; dt=1/(nt*f0); time=0:dt:(np/f0)-dt; N=np*nt; K=1.38e-23; T=300; q=1.602e-19; VT=K*T/q;

6.2 Opamps

397

IS=1e-03; VON=1; vip=5; vi=vip*sin(2*pi*f0*time); syms x I=@(x) ((x=VON).*IS.*(exp((x-VON)/VT)-1)); vo=@(x) ((abs(x)=2*VON).*(abs(x)-2*VON)); tic vd1=0.50*(vi-vo(vi)); toc plot(time,vi) hold on plot(time,vo(vi)) plot(time,vd1)

6.2

Opamps

Opamps are used in many electronic circuits that require amplification, filtering, and signal processing. To reduce the simulation time, opamp circuits can be simplified using the behavioral models derived from opamp characteristics. A simple behavioral model of the opamp includes a voltage-controlled voltage source with complex input and output impedances. The voltage-gain of the dependent source changes with frequency and saturates as the signal amplitude increases. More characteristics such as offset voltage, signal delay, and input common range can also be added to the opamp model for better accuracies.

6.2.1

Inverting Hysteresis Circuit

An inverting hysteresis circuit is used when the zero-crossing perturbation of a signal needs to be removed and the signal needs to be inverted. The circuit of an inverting hysteresis circuit is shown in Fig. 6.4. The voltage at the noninverting terminal of the opamp is obtained through the R1 and R2 voltage divider connected to the output. When the amplitude of the input signal is smaller than the voltage at the noninverting terminal, the high gain of the opamp drives the output towards +Vcc positive voltages. When the amplitude of the input signal is larger than the voltage at the noninverting terminal, the high gain of the opamp drives the output towards Vcc negative voltages. By adjusting the ratios of the R1 and R2, the two high and low threshold levels that create a window in the circuit transfer function are adjusted, as shown in Fig. 6.5.

398

6 Behavioral Analysis

Fig. 6.4 The inverting hysteresis circuit

Vcc Vin Vout

-Vcc R2 R1

Fig. 6.5 Transfer characteristics

The transient response is shown in Fig. 6.6. The application of the inverting hysteresis circuit is the signal inversion and the removal of the zero-crossing noise from the transient waveforms. The following MATLAB code simulates the transient analysis of the inverting hysteresis circuit using the mid-level modeling.

global Vo k global G1 G2 f0=1.35e+08; np=4;

6.2 Opamps

399

Fig. 6.6 Transient response

nt=101; dt=1/(nt*f0); df=f0/np; time=0:dt:(np/f0)-dt; freq=0:df:(nt*f0)-df; vip=10; G1=1e-03; G2=1e-03; C1=1e-11; Vcc=5; Vi=vip*sawtooth(2*pi*f0*time+pi/2,0.5); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'StepTolerance',1e12,'Display','off'); Vo(1)=-Vcc; %initial condition vp(1)=0; x0=vp(1); for k=2:length(Vi) if Vi(k) > vp(k-1) Vo(k)=-Vcc; x=fsolve(@KCL,x0,opts); vp(k)=x; x0=vp(k); else Vo(k)=+Vcc; x=fsolve(@KCL,x0,opts); vp(k)=x; x0=vp(k); end end

400

6 Behavioral Analysis

figure plot(Vi(2:end),Vo(2:end)) figure plot(time,Vi) hold on plot(time,Vo) function F=KCL(x) global Vo k global G1 G2 F=G2*x+G1*(x-Vo(k)); End

6.2.2

Noninverting Hysteresis Circuit

An inverting hysteresis circuit is used when the zero-crossing perturbation of a signal needs to be removed. The circuit of a noninverting hysteresis circuit is shown in Fig. 6.7. The resistive network R0, R1, and R2 connected between the input and the output of the circuit create a signal at the noninverting terminal of the opamp. When the amplitude of this signal is above zero, the high gain of the opamp drives the output towards +Vcc positive voltages. When the amplitude of the signal at the noninverting terminal of the opamp is less than zero, the high gain of the opamp drives the output towards Vcc negative voltages. By adjusting the ratios of the R1 and R2, the two high and low threshold levels that create a window in the circuit transfer function are adjusted, as shown in Fig. 6.8. The transient response is shown in Fig. 6.9. Fig. 6.7 The noninverting hysteresis circuit

Vcc Vout R0

‐Vcc R1

Vin R2

6.2 Opamps

401

Fig. 6.8 Transfer characteristics

Fig. 6.9 Transient response

The application of the inverting hysteresis circuit is the removal of the zerocrossing noise from the transient waveforms without inverting the signal. The following MATLAB code simulates the transient analysis of the noninverting hysteresis circuit using the mid-level modeling.

global Vi Vo k global G0 G1 G2 f0=1.35e+08; np=4; nt=101;

402

6 Behavioral Analysis

dt=1/(nt*f0); df=f0/np; time=0:dt:(np/f0)-dt; freq=0:df:(nt*f0)-df; vip=10; G0=1e-03; G1=1e-03; G2=1e-03; C1=1e-11; Vcc=5; Vi=vip*sawtooth(2*pi*f0*time+pi/2,0.5); opts=optimoptions('fsolve','Algorithm','levenberg-marquardt',... 'FunctionTolerance',1e-12,'StepTolerance',1e12,'Display','off'); Vo(1)=-Vcc; %initial condition vp(1)=0; x0=vp(1); for k=2:length(Vi) if 0 > vp(k-1) Vo(k)=-Vcc; x=fsolve(@KCL,x0,opts); vp(k)=x; x0=vp(k); else Vo(k)=+Vcc; x=fsolve(@KCL,x0,opts); vp(k)=x; x0=vp(k); end end figure plot(Vi(2:end),Vo(2:end)) figure plot(time,Vi) hold on plot(time,Vo) function F=KCL(x) global Vi Vo k global G0 G1 G2 F=G0*(x-Vi(k))+G2*x+G1*(x-Vo(k)); End

6.2 Opamps

6.2.3

403

Oscillator Circuit

An oscillator generates an alternating signal with a certain amplitude, frequency, and waveform from a circuit that is connected to a DC power supply. An oscillator circuit that works based on the concepts of hysteresis circuits, studied earlier, is shown in Fig. 6.10. When the output is +Vcc, the capacitor C1 charges towards +Vcc positive voltages. When the signal amplitude at the inverting terminal exceeds the signal amplitude at the noninverting terminal, the output becomes Vcc. The capacitor C1 discharges towards Vcc negative voltages. When the signal amplitude at the inverting terminal becomes less than the signal amplitude at the noninverting terminal, the output becomes +Vcc. These charging and discharging of the capacitor continue and an alternating square waveform is generated at the output. The frequency and the amplitude of the waveform can be adjusted by changing the values of resistors and capacitor. The transfer characteristics is shown in Fig. 6.11. The transient response is shown in Fig. 6.12. The following MATLAB code simulates the transient analysis of the oscillator circuit using the mid-level modeling.

global vp G1=1e-03; G2=1e-03; G3=1e-03;

Fig. 6.10 The oscillator circuit

R3 C1 Vcc Vout

-Vcc R2 R1

404 Fig. 6.11 Transfer characteristics

Fig. 6.12 Transient response

C1=1e-09; Vcc=5; tf=20e-06; ts=0; ys=0; time=0; cap=0; Vo=-Vcc; out=Vo; c=char('');

6 Behavioral Analysis

6.3 Diodes

405

syms t v(t) while ts < tf vp=G2*Vo/(G1+G2); EQ=C1*diff(v(t),t) == G3*(Vo-v(t)); [V]=odeToVectorField(EQ); M=matlabFunction(V,'vars', {'t','Y'}); opts=odeset('Events',@yval); [T,y,te,ye,ie]=ode45(M,[ts tf],ys,opts); ts=T(end); ys=y(end); time=vertcat(time,T(1:end)); cap=vertcat(cap,y(1:end)); out=vertcat(out,repmat(Vo,length(y),1)); Vo=-Vo; fprintf(repmat('\b',[1 length(c)])) c=char([num2str(round(100*ts/tf)),' percent done!']); fprintf(c) end fprintf('\n') Vi=cap; Vo=out; figure plot(Vi(2:end),Vo(2:end)) figure plot(time,Vi) hold on plot(time,Vo) function [value,isterminal,direction]=yval(~,y) global vp value=y(1)-vp; isterminal=1; direction=0; end

6.3

Diodes

A simple way to create the behavioral models of circuits that include diodes is to replace diodes with switches. Diodes are ON when their voltage exceeds a certain value and they are OFF when their voltage reduces from that certain value. For lower level modeling, mathematical expressions are used to explain the operation of the whole diode circuits, as explained earlier.

406

6.3.1

6 Behavioral Analysis

Diode Rectifier

A rectifier circuit passes and processes one of the positive or negative cycles of an AC waveform while blocking the other cycle. A positive cycle diode rectifier circuit is shown in Fig. 6.13. The diode becomes ON during the positive input cycles and when the input amplitude exceeds the ON voltage of the diode. Otherwise, the diode will be OFF and a constant output voltage is obtained by the R1 and R2 voltage divider connected to +Vcc. The transfer characteristics is shown in Fig. 6.14. The transient response is shown in Fig. 6.15. The following MATLAB code simulates the transient analysis of the half-wave diode rectifier circuit using the mid-level modeling.

global vi k I global G1 G2 Vcc

Fig. 6.13 The diode rectifier circuit

+Vcc

D1 R2 Vout Vin

Fig. 6.14 Transfer characteristics

R1

6.3 Diodes

407

Fig. 6.15 Transient response

f0=1.35e+08; np=4; nt=101; dt=1/(nt*f0); df=f0/np; time=0:dt:(np/f0)-dt; freq=0:df:(nt*f0)-df; vip=10; K=1.38e-23; T=300; q=1.602e-19; VT=K*T/q; IS=1e-015; VON=1; VBR=-50; GBR=10; G1=1e-03; G2=1e-03; Vcc=5; vi=vip*sin(2*pi*f0*time); syms x I=@(x) ((x