Biomedical Engineering and Science [1 ed.] 9781601323491

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PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON BIOMEDICAL ENGINEERING AND SCIENCE

Editors Hamid R. Arabnia Leonidas Deligiannidis Associate Editors George Jandieri Ashu M. G. Solo, Fernando G. Tinetti

WORLDCOMP’15 July 27-30, 2015 Las Vegas Nevada, USA www.world-academy-of-science.org ©

CSREA Press

This volume contains papers presented at The 2015 International Conference on Biomedical Engineering and Science (BIOENG'15). Their inclusion in this publication does not necessarily constitute endorsements by editors or by the publisher.

Copyright and Reprint Permission Copying without a fee is permitted provided that the copies are not made or distributed for direct commercial advantage, and credit to source is given. Abstracting is permitted with credit to the source. Please contact the publisher for other copying, reprint, or republication permission. © Copyright 2015 CSREA Press ISBN: 1-60132-417-0 Printed in the United States of America

CSREA Press U. S. A.

Foreword It gives us great pleasure to introduce this collection of papers to be presented at the 2015 International Conference on Biomedical Engineering and Science (BIOENG’15), July 27-30, 2015, at Monte Carlo Resort, Las Vegas, USA. An important mission of the World Congress in Computer Science, Computer Engineering, and Applied Computing (a federated congress to which this conference is affiliated with) includes "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." By any definition of diversity, this congress is among the most diverse scientific meeting in USA. We are proud to report that this federated congress has authors and participants from 76 different nations representing variety of personal and scientific experiences that arise from differences in culture and values. As can be seen (see below), the program committee of this conference as well as the program committee of all other tracks of the federated congress are as diverse as its authors and participants. The program committee would like to thank all those who submitted papers for consideration. About 50% of the submissions were from outside the United States. Each submitted paper was peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee was charged to make the final decision; often, this involved seeking help from additional referees. In addition, papers whose authors included a member of the conference program committee were evaluated using the double-blinded review process. One exception to the above evaluation process was for papers that were submitted directly to chairs/organizers of pre-approved sessions/workshops; in these cases, the chairs/organizers were responsible for the evaluation of such submissions. The overall paper acceptance rate for regular papers was 22%; 12% of the remaining papers were accepted as poster papers (at the time of this writing, we had not yet received the acceptance rate for a few individual tracks.) We are very grateful to the many colleagues who offered their services in organizing the conference. In particular, we would like to thank the members of the Program Committee of BIOENG’15, members of the congress Steering Committee, and members of the committees of federated congress tracks that have topics within the scope of BIOENG. Many individuals listed below, will be requested after the conference to provide their expertise and services for selecting papers for publication (extended versions) in journal special issues as well as for publication in a set of research books (to be prepared for publishers including: Springer, Elsevier, BMC journals, and others). x x x

x x x x

Prof. Abbas M. Al-Bakry (Congress Steering Committee); University President, University of IT and Communications, Baghdad, Iraq Prof. Christine Amaldas; Ritsumeikan Asia Pacific University, Kyoto, Japan Prof. Hamid R. Arabnia (Congress Steering Committee & Coordinator); Professor of Computer Science; The University of Georgia, USA; Editor-in-Chief, Journal of Supercomputing (Springer); Editor-in-Chief, Transactions of Computational Science & Computational Intelligence (Springer); Elected Fellow, Int'l Society of Intelligent Biological Medicine (ISIBM); USA Prof. Juan Jose Martinez Castillo; Director, The Acantelys Alan Turing Nikola Tesla Research Group and GIPEB, Universidad Nacional Abierta, Venezuela Dr. En Cheng; Department of Computer Science, The University of Akron, Akron, Ohio, USA Dr. Ravi Chityala; Elekta Inc, Sunnyvale, California, USA; and University of California Santa Cruz Extension, San Jose, California, USA Prof. Kevin Daimi (Congress Steering Committee); Director, Computer Science and Software Engineering Programs, Department of Mathematics, Computer Science and Software Engineering, University of Detroit Mercy, Detroit, Michigan, USA

x x x x x x x x x x x x x x x x x

Prof. Leonidas Deligiannidis; Department of Computer Information Systems, Wentworth Institute of Technology, Boston, Massachusetts, USA Prof. Mary Mehrnoosh Eshaghian-Wilner (Congress Steering Committee); Professor of Engineering Practice, University of Southern California, California, USA; Adjunct Professor, Electrical Engineering, University of California Los Angeles, Los Angeles (UCLA), California, USA Prof. Houcine Hassan; Universitat Politecnica de Valencia, Spain Prof. George Jandieri (Congress Steering Committee); Georgian Technical University, Tbilisi, Georgia; Chief Scientist, The Institute of Cybernetics, Georgian Academy of Science, Georgia; Editorial Board Member: International Journal of Microwaves and Optical Technology Prof. Tai-hoon Kim; School of Information and Computing Science, University of Tasmania, Australia Dr. Andrew Marsh (Congress Steering Committee); CEO, HoIP Telecom Ltd (Healthcare over Internet Protocol), UK; Secretary General of World Academy of BioMedical Sciences and Technologies (WABT) a UNESCO NGO, The United Nations Prof. G. N. Pandey (Congress Steering Committee); Vice-Chancellor, Arunachal University of Studies, Arunachal Pradesh, India; Adjunct Professor, Indian Institute of Information Technology, Allahabad, India Prof. James J. (Jong Hyuk) Park (Congress Steering Committee); Department of Computer Science and Engineering (DCSE), SeoulTech, Korea; President, FTRA, EiC, HCIS Springer, JoC, IJITCC; Head of DCSE, SeoulTech, Korea Prof. Khemaissia Seddik; University of Tebessa, Algerie, Algeria Dr. Akash Singh (Congress Steering Committee); IBM Corporation, Sacramento, California, USA; Chartered Scientist, Science Council, UK; Fellow, British Computer Society; Member, Senior IEEE, AACR, AAAS, and AAAI; IBM Corporation, USA Ashu M. G. Solo, (Publicity Chair), Fellow of British Computer Society, Principal/R&D Engineer, Maverick Technologies America Inc. Prof. Fernando G. Tinetti (Congress Steering Committee); School of Computer Science, Universidad Nacional de La Plata, La Plata, Argentina; Co-editor, Journal of Computer Science & Technology (JCS&T) Prof. Shiuh-Jeng Wang (Congress Steering Committee); Department of Information Management, Central Police University, Taiwan; Program Chair, Security & Forensics, Taiwan; Director, Information Crypto and Construction Lab (ICCL) & ICCL-FROG Prof. Mary Q. Yang (Congress Steering Committee); Director, Mid-South Bioinformatics Center and Joint Bioinformatics Ph.D. Program, Medical Sciences and George W. Donaghey College of Engineering and Information Technology, University of Arkansas, USA Prof. Jane You (Congress Steering Committee); Associate Head, Department of Computing, The Hong Kong Polytechnic University, Kowloon, Hong Kong Peng Zhang; Biomedical Engineering Department, Stony Brook University, Stony Brook, New York, USA Prof. Wenbing Zhao; Department of Electrical and Computer Engineering, Cleveland State University, Cleveland, Ohio, USA

We would like to extend our appreciation to the members of the program committees of individual sessions, tracks, and workshops; their names do not appear in this document; they are listed on the web sites of individual tracks. As Sponsors-at-large, partners, and/or organizers each of the followings (separated by semicolons) provided help for at least one track of the World Congress: Computer Science Research, Education, and Applications Press (CSREA); US Chapter of World Academy of Science (http://www.world-academy-ofscience.org/) ; American Council on Science & Education & Federated Research Council (http://www.americancse.org/); HoIP, Health Without Boundaries, Healthcare over Internet Protocol, UK (http://www.hoip.eu); HoIP Telecom, UK (http://www.hoip-telecom.co.uk); and WABT, Human Health Medicine, UNESCO NGOs, Paris, France (http://www.thewabt.com/ ). In addition, a number of university faculty members and their staff (names appear on the cover of the set of proceedings), several publishers of computer science and computer engineering books and journals, chapters and/or task forces of computer science associations/organizations from 4 countries, and developers of high-performance machines and systems provided significant help in organizing the conference as well as providing some resources. We are grateful to them all. We express our gratitude to keynote, invited, and individual conference/tracks and tutorial speakers - the list of speakers appears on the conference web site. We would also like to thank the followings: UCMSS (Universal Conference Management Systems & Support, California, USA) for managing all aspects of the conference; Dr. Tim Field of APC for coordinating and managing the printing of the proceedings; and the

staff of Monte Carlo Resort (Convention department) in Las Vegas for the professional service they provided. Last but not least, we would like to thank the Co-Editors and Associate Co-Editors of BIOENG’15: Prof. Hamid R. Arabnia, Prof. Leonidas Deligiannidis, Prof. George Jandieri, Ashu M. G. Solo, and Prof. Fernando G. Tinetti. We present the proceedings of BIOENG’15.

Steering Committee, 2015 http://www.world-academy-of-science.org/

Contents SESSION: MEDICAL DEVICES AND SUPPORTING SYSTEMS Evaluation of Embedded ISAs for Smart Cardiac Pacemaker Workloads Safwat Mostafa Noor, Eugene John

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A Recording System to Eavesdrop on Marmosets Christopher Casebeer, Emery Newlon, Kyler Callahan, Cory Miller, Ross Snider

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Real Heart Valve Model for Different Severity Level of Mitral Regurgitation Carolina Rosas-Huerta, Jorge Fco. Martinez-Carballido

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State of the Art Mock Circulation Loop and a Proposed Novel Design T. Batuhan Baturalp, Atila Ertas

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SESSION: COMPUTATIONAL BIOLOGY: NOVEL ALGORITHMS AND APPLICATIONS A System for Estimating Spatio-Temporal Gait Parameters and Pelvis Kinematics Maria Vittoria Avolio, Stefano Mammolito, Giuseppe Spingola

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Algorithm Detecting Point Microcalcifications Using Matlab for Breast Cancer Shafiul Islam

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ERP Analysis of Emotional Stimuli from Brain EEG Signal Raja Majin Mehmood, Hyo Jong Lee

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Cardiovascular Authentication: Fusion of Electrocardiogram and Ejection Fraction Rabita Alamgir, Obaidul Malek, Laila Alamgir, Mohammad Matin

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SESSION: BIOMEDICAL ENGINEERING AND IMAGING SCIENCE Spatial Fuzzy C-Means Algorithm for Bias Correction and Segmentation of Brain MRI Data Wedad S. Salem, Hesham F. Ali , Ahmed F. Seddik

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V.I.S System Revolutionary Technic of Medical Diagnosis Taieb Boucherit, Abdelkader Yaghoubi

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SESSION: POSTER PAPERS Posture Tracking Study with Custom Wireless 3-D Gait Analysis Sensor (WGAS) and Commercial Posture Sensor Paul Lie, B.T. Nukala, Donald Lie, Jerry Lopez, Tam Nguyen

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Classification of Alzheimer's Disease Using Combination of each Recognition Method in MR Scans Saruar Alam, Moonsoo Kang, Seokjoo Shin, Jae-Young Pyun, Goo-Rak Kwon

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SESSION: LATE BREAKING PAPER: CANCER RESEARCH Developing Meta-Analysis Method for Identifying Biomarker of Gastric Cancer 81 Xiaoya Chen, Jinjun Li, William Yang, Lili Lu, Hongyan Jin, Zexiong Wei, Wei Gu, Hamid R. Arabnia, Mary Yang, Youping Deng

Int'l Conf. Biomedical Engineering and Science | BIOENG'15 |

SESSION MEDICAL DEVICES AND SUPPORTING SYSTEMS Chair(s) TBA

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Evaluation of Embedded ISAs for Smart Cardiac Pacemaker Workloads Safwat Mostafa Noor and Eugene John Department of Electrical and Computer Engineering, University of Texas at San Antonio San Antonio, Texas Abstract - Embedding microprocessors in implantable cardiac pacemakers for analyzing data and executing preprogrammed behavior has always been a challenging task where achieving a suitable balance between power and performance is the main focus. The upcoming generation of pacemakers is expected to both diversify the processor workload and demand significantly increased computational capabilities. This paper investigates potential workloads for future cardiac pacemakers and evaluates the key challenges in the path of development. Relevant benchmark programs including heart signal processing, physical activity detection, security via encryption and cyclic redundancy check are simulated on commercial embedded processors for performance-power analysis. An insight into the appropriateness of current processors is achieved and key Instruction Set Architecture features that achieve benefit in the realm of pacemaker applications are identified. Correlations between instruction-mix and power consumption are visualized for different workloads. The simulation results are analyzed to understand requirements of implantable processors for future smart pacemakers. Keywords: Pacemaker, Smart Pacemaker, Implantable Processor, ImplantBench, ARM

1

Introduction

In the past few years commercial and consumer electronics has gone through vast changes due to the advent of embedded processors and ubiquitous mobile wireless connectivity [1]. It has become a trend to integrate smart computing capabilities into electronic devices, wherever it is deemed feasible. Not only has this revolutionized the way people connect with each other but it has also created a path for people to interact with the devices they own. This new realm of connectivity has immense potential for integration into biomedical or implantable electronics [2]. Examples of such approaches can already be seen on recent wearable monitoring devices such heart rate sensors or pedometers. However, to integrate the concept of smart computing and connectivity into critical application such as pacemakers requires higher degrees of security, combined with extreme power efficiency and reliability. This paper is intended to provide an insight into possible application workloads expected in next generation of secured smart pacemakers and evaluate the computational performance of current commercial embedded processor for such applications, including their power consumption analysis. The experiments conducted in this research helps to

bring forward the desirable features in processor architectures that can benefit the development of future smart pacemakers. The use of pacemakers has increased 55.6% between the years 1993 to 2009 with approximately 2.9 million patients receiving a pacemaker implant [3]. They are proven to be an effective and highly reliable treatment to complex heart conditions such as arrhythmia. Not many years ago, the functionality of a pacemaker was mostly limited to monitoring signals from the heart and assisting its operation via artificial pacing when any predefined abnormality was detected. In the recent years manufacturers started incorporating advance features to make the pacemaker smarter and more user-friendly [4]. These improvements not only include the refinement of the fundamental sensing and pacing procedure, but also adds convenient features such as data logging and configuration via wireless telemetry. Future smart pacemakers are expected to communicate seamlessly with the patient's smart-phone or integrate easily into a hospitals wireless network infrastructure. This is still not efficiently feasible using current pacemaker technology and can introduces serious security risks [5], [6]. In the mentioned future use cases, the pacemaker can be configured to automatically transmit alerts via the connected smart-phone or wireless network when life critical situations occur. Operational data can logged and viewed on the SDWLHQW¶V smart-phone for easy monitoring. The possibilities depend on the innovativeness of the developer, given that a suitable and efficient programmable computing platform is provided to implement the required software stacks and security features. The major obstacle for realizing this goal is the limited computational ability available on processors used in pacemakers. The manufacturers are also often inclined towards ASIC based design for carrying out the demanding computation workloads. While choosing the ASIC approach provides the lowest power and highest performance for the application at hand, it does not provide freedom to the firmware developer for expanding its feature set. The solution to this situation lies in the development of application specific instruction-set processors (ASIP) or System on Chips (SoCs) that are able to provide adequate computational capability while adhering to the low power requirements; ensuring the flexibility needed for next generation pacemakers.

2

Background Study

The human heart consists of special conduction fibers and two primary nodes that make up its native pace-making system. The Sinoatrial Node (SA Node) acts to distribute electric impulses through the Bachmann’s Bundle fibers and

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the Atrioventricular Node (A-V Node) introduces an important synchronizing delay before distributing the impulses to the Bundle branch and Purkinje fibers [Figure.1]. The SA node and AV nodes are connected via Internodal tracks and the delay of the signal travelling from the SA node to the A-V node ensures the synchronization between the contraction/depolarization of the Atria and Ventricle chambers [7]. The movement of the chambers are driven by myocardium muscles and require a certain period of the impulse to fully activate. The impulses are often called action potentials. Described simply, the periodic pacing procedure of the heart is a synchronized flow of electric impulses through the conduction fibers followed by the contraction of the muscles. The whole process depends largely on the correct behavior of SA and AV nodes.

The challenges in enabling wireless connectivity in critical implantable devices originate mainly in the form of security and power consumption. Security in Cardiac pacemakers with wireless connectivity is particularly important as the outcome of any security breach can be used to trigger lethal life threating attacks. Examples of such security compromises and risks have come up both in research [5] and in real life scenarios [6]. Better security requires stronger data encryption schemes which in turns translate to higher computational load and higher power consumption. In the current embedded industry, security protocols and standards such as WEP (IEEE Standard 802.11), Advanced Encryption Standard (AES), Internet Protocol Security (IPSec) and Secure Sockets Layer (SSL) are regularly used to secure the data services and transmission. While security protocols and cryptographic algorithms address securiW\FRQVLGHUDWLRQVIURPD³IXQFWLRQDO´SHUVSHFWLYH implantable systems are constrained by the environments they operate in, and by the resources they possess. The computational load for implementing industry standard security protocols such as AES or SSL includes both cryptographic and non-cryptographic components [9]. Computational load is also contributed from the integrity checks such as Cyclic Redundancy Check (CRC), Message-Digest 5 (MD5) hash calculation that are involved in data transmission. Figure.2 shows a breakdown of SSL in percentage for a process of encryption and integrity check for varying size of data transaction.

Figure.1. The Conduction System of the Heart [8] Common cardiac diseases such as Arrhythmias are mainly caused by cardiac conduction problems resulting in abnormal heart rhythms. The hearts natural pacemaker may develop damaged conduction paths, blocked A-V node or failure to generate impulse. The artificial demand pacemaker monitors the impulses of the heart via Intracardiac electrogram (IECG) and determines the requirement of artificial pacing. Many modern rate responsive pacemakers take into account multiple other factors such as the activity level of the patient, body temperature, pH level of the blood etc. when sensing the heart signals to better regulate the artificial pacing in accordance ZLWK WKH SDWLHQW¶V physical situation. The signal processing required in these operations involves FFT calculation of the ECG data and algorithms for pattern matching [10]. ASIC designs [11] are often the preferred implementations for processing these workloads as they run continuously during the SDFHPDNHU¶V RSHUDWLRQ OLIHWLPH $OWKRXJK WKHUH KDYH EHHQ attempts to use simpler 8-bit or 16-bit low power microcontrollers in the place of ASIC solutions [12] [13], these processors are expected to be overwhelmed by complex encryption workloads. Three workloads representing ECG signal processing, Activity detection and Heart pacing monitoring are included in the hardware performance analysis performed in this paper. The results serve as a feasibility study for using a 32-bit embedded processor for performing monitoring tasks.

Figure.2. Breakup of SSL workload into cryptographic and non-cryptographic components [9] It can be observed that the workload variation depends mostly on the data rate requirement of a certain encryption process. This indicates a need for a combined hardware and software based approach to deal with security in cardiac pacemakers. Further along in this paper we explore the hardware performance of encryption algorithms and data integrity calculations on embedded platforms. The two Instruction Set Architecture (ISA) used for comparison are ARMv4 and the MIPS like PISA (Portable ISA) provided with SimpleScalar architectural simulator [14]. Since the PISA essentially implements a modern MIPS architecture; the simulation results will effectively compare the ARM and MIPS ISA. The ARM architecture is currently one of the most

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popular embedded architectures and has ubiquitous use in many different fields. It is typically a 32 bit RISC machine with a Von Neumann architecture and was first developed in 1980 by Acron Computers. The ISA currently has multiple micro-architectures ranging from real time high performance implementations to low power microcontroller solutions [15]. The MIPS ISA was developed in 1981 by MIPS Computer Systems. The version used in this research is largely similar to the MIPS1 ISA which is the 32 bit version with a Floating Point (FP) unit [14]. The benchmarks were selected from Implantbench [16] which was released in 2008 by A. Cheng in the hope of enabling implantable nano-scale computing ImplantBench is the only major benchmark suite that provides the required set of programs to simulate and study future implantable devices. Although ImplantBench has been used for multiple different research [17], [18] focusing on benchmark analysis, actual analysis of the programs running on real world hardware models are not abundant.

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Research Description

We utilize architectural simulations to generate statistics on performance for executing workloads of a smart pacemaker. Table I shows the simulation configurations that were used. TABLE I Configuration for simulation ARM Processor

MIPS Processor

ARMv4 Architecture

MIPS-I Architecture

ARM ISA

MIPS32 ISA

Dual-issue, out-of-order, 7 stage pipeline 16KB i-cache and d-cache 4 way associative

dual-issue, out-of-order, 5 stage pipeline 16KB i-cache and d-cache 4 way associative

Single Hardware Thread

Single Hardware Thread

100MhZ at 1.1V

100MhZ at 1.1V

Supporting components such as cache, NoCs and memory systems were included in the simulation. However, the study tries to focus mostly on the performance of the pipeline and the components that are closely related to it. Therefore performance of NoCs and memory systems are taken out of the discussion and statistics originating only from the Out Of Order (O3) pipeline and cache are discussed in most detail. We explore three major types of workloads using five different benchmarks from ImplantBench. The Five benchmark programs represents Heartbeat monitoring, Physical activity monitoring, Security (Encryption), and Redundancy (CRC). The selected programs and adopted method for simulation are discussed in the next section.

3.1

Benchmark and Methodology

ImplantBench includes dedicated programs for heart activity and physiological monitoring as well as CRC and encryption.

A.

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Heart Activity and Physiology

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